bsp.c 3.2 KB

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  1. #include "bsp/shark_bsp.h"
  2. #include "bsp/gpio.h"
  3. #include "bsp/uart.h"
  4. #include "bsp/AT24CXX.h"
  5. #include "bsp/shark_rtc.h"
  6. #include "bsp/clock.h"
  7. #include "bsp/fmc_flash.h"
  8. #include "bsp/cht8305.h"
  9. #include "libs/logger.h"
  10. #include "libs/shark_task.h"
  11. #include "version.h"
  12. #include <string.h>
  13. #if defined CONFIG_BOARD_SP700
  14. #ifdef SP710_V2
  15. const char iap_board_name[] __attribute__((at(0x08002800))) = "SP710";
  16. #else
  17. const char iap_board_name[] __attribute__((at(0x08002800))) = "SP700";
  18. #endif
  19. #elif defined CONFIG_BOARD_SP600
  20. const char iap_board_name[] __attribute__((at(0x08002800))) = "SP600";
  21. #endif
  22. const char iap_fw_version[] __attribute__((at(0x08002A00))) = CONFIG_VERSION;
  23. const char iap_fw_name[] __attribute__((at(0x08002C00))) = "App";
  24. extern void system_clock_config(void);
  25. extern void SystemCoreClockUpdate(void);
  26. extern void gpio_key_init(void);
  27. static void dianostic_timer_handler(shark_timer_t *timer);
  28. static shark_timer_t _dianostic_stop_timer = {.handler = dianostic_timer_handler};
  29. #ifndef CONFIG_DEBUG
  30. #define CONFIG_DEBUG 0
  31. #endif
  32. static uint32_t reset_source = 0;
  33. static uint32_t backup_reg = 0;
  34. //all board's low level init is here
  35. void bsp_init(void){
  36. reset_source = RCU_RSTSCK;
  37. backup_reg = RTC_BKP0;
  38. wdog_start(4);
  39. shark_rtc_init();
  40. enable_mcu_power();
  41. system_clock_config(); //after dcdc open, MCU can run on full speed
  42. SystemCoreClockUpdate();
  43. rcu_all_reset_flag_clear();
  44. task_ticks_enable();
  45. gpio_init();
  46. set_log_level(MOD_SYSTEM, L_debug);
  47. shark_uart_init(SHARK_UART0);
  48. #if UART_NUM==2
  49. shark_uart_init(SHARK_UART1);
  50. #endif
  51. AT24CXX_Init();
  52. #if (CONFIG_BOARD_TYPE==SHARK_BOARD_SP700)
  53. cht8305_init();
  54. #endif
  55. AUX_VOL_OPEN(0);
  56. gpio_key_init();
  57. DIANOCTIC_LED(1);
  58. shark_timer_post(&_dianostic_stop_timer, 5000);
  59. RTC_BKP0 = 0;
  60. }
  61. static void dianostic_timer_handler(shark_timer_t *timer) {
  62. DIANOCTIC_LED(0);
  63. }
  64. uint32_t bsp_get_rst_reson(void){
  65. return reset_source;
  66. }
  67. uint32_t bsp_get_backup(void){
  68. return backup_reg;
  69. }
  70. void systick_close(void)
  71. {
  72. SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
  73. }
  74. void systick_open(void)
  75. {
  76. SysTick_Config(SystemCoreClock / 1000);
  77. }
  78. char* bsp_get_fversion(void){
  79. return (char *)iap_fw_version;
  80. }
  81. void system_reboot(void){
  82. NVIC_SystemReset();
  83. }
  84. /* timeout:1-25 */
  85. void wdog_start(int timeout){
  86. #if CONFIG_DEBUG == 0
  87. /* enable IRC40K */
  88. rcu_osci_on(RCU_IRC40K);
  89. /* wait till IRC40K is ready */
  90. while(SUCCESS != rcu_osci_stab_wait(RCU_IRC40K)){
  91. }
  92. /* confiure FWDGT counter clock: 40KHz(IRC40K) / 256 = 0.15625 KHz */
  93. fwdgt_config(timeout*40000UL/256, FWDGT_PSC_DIV256);
  94. /* after 4 seconds to generate a reset */
  95. fwdgt_enable();
  96. #endif
  97. }
  98. void wdog_reload(void){
  99. #if CONFIG_DEBUG == 0
  100. fwdgt_counter_reload();
  101. #endif
  102. }
  103. int wdog_set_timeout(int wdog_time)
  104. {
  105. #if CONFIG_DEBUG == 0
  106. uint32_t flag_status = RESET;
  107. uint32_t timeout = FWDGT_RLD_TIMEOUT;
  108. /* enable write access to FWDGT_PSC,and FWDGT_RLD */
  109. FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
  110. /* wait until the RUD flag to be reset */
  111. do{
  112. flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
  113. }while((--timeout > 0U) && (RESET != flag_status));
  114. if (RESET != flag_status){
  115. return -1;
  116. }
  117. FWDGT_RLD = RLD_RLD(wdog_time*40000UL/256);
  118. /* reload the counter */
  119. FWDGT_CTL = FWDGT_KEY_RELOAD;
  120. #endif
  121. return 0;
  122. }