bsp.c 2.3 KB

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  1. #include "bsp/shark_bsp.h"
  2. #include "bsp/gpio.h"
  3. #include "bsp/uart.h"
  4. #include "bsp/AT24CXX.h"
  5. #include "bsp/shark_rtc.h"
  6. #include "bsp/clock.h"
  7. #include "bsp/fmc_flash.h"
  8. #include "libs/logger.h"
  9. #include "version.h"
  10. #include <string.h>
  11. #if defined CONFIG_BOARD_SP700
  12. const char iap_board_name[] __attribute__((at(0x08002800))) = "SP700";
  13. #elif defined CONFIG_BOARD_SP600
  14. const char iap_board_name[] __attribute__((at(0x08002800))) = "SP600";
  15. #endif
  16. const char iap_fw_version[] __attribute__((at(0x08002A00))) = CONFIG_VERSION;
  17. const char iap_fw_name[] __attribute__((at(0x08002C00))) = "App";
  18. extern void system_clock_config(void);
  19. extern void SystemCoreClockUpdate(void);
  20. #define ALARM_TEST 1
  21. #ifndef CONFIG_DEBUG
  22. #define CONFIG_DEBUG 0
  23. #endif
  24. #if 0
  25. void test_fmc_flash(void){
  26. uint8_t data[128];
  27. fmc_erase_image(50 * 1024);
  28. fmc_start_read_image();
  29. for(int i = 0; i < sizeof(data); i++){
  30. data[i] = i;
  31. }
  32. int count = 50;
  33. while(count-- >= 0) {
  34. for(int i = 0; i < sizeof(data); i++){
  35. data[i] = i;
  36. }
  37. fmc_write_image(data, sizeof(data));
  38. memset(data, 0, sizeof(data));
  39. fmc_read_image(data, sizeof(data));
  40. for(int i = 0; i < sizeof(data); i++){
  41. if (data[i] != (uint8_t)i){
  42. sys_debug("");
  43. }
  44. }
  45. }
  46. }
  47. #endif
  48. //all board's low level init is here
  49. void bsp_init(void){
  50. wdog_start(4);
  51. shark_rtc_init();
  52. enable_mcu_power();
  53. delay_us(100);
  54. system_clock_config(); //after dcdc open, MCU can run on full speed
  55. SystemCoreClockUpdate();
  56. gpio_init();
  57. shark_uart_init(SHARK_UART0);
  58. shark_uart_init(SHARK_UART1);
  59. AT24CXX_Init();
  60. }
  61. char* bsp_get_fversion(void){
  62. return (char *)iap_fw_version;
  63. }
  64. /* timeout:1-25 */
  65. void wdog_start(int timeout){
  66. #if CONFIG_DEBUG == 0
  67. /* enable IRC40K */
  68. rcu_osci_on(RCU_IRC40K);
  69. /* wait till IRC40K is ready */
  70. while(SUCCESS != rcu_osci_stab_wait(RCU_IRC40K)){
  71. }
  72. /* confiure FWDGT counter clock: 40KHz(IRC40K) / 256 = 0.15625 KHz */
  73. fwdgt_config(timeout*40000UL/256, FWDGT_PSC_DIV256);
  74. /* after 4 seconds to generate a reset */
  75. fwdgt_enable();
  76. #endif
  77. }
  78. void wdog_reload(void){
  79. #if CONFIG_DEBUG == 0
  80. fwdgt_counter_reload();
  81. #endif
  82. }
  83. void wdog_set_timeout(int timeout)
  84. {
  85. #if CONFIG_DEBUG == 0
  86. /* enable write access to FWDGT_PSC,and FWDGT_RLD */
  87. FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
  88. FWDGT_RLD = RLD_RLD(timeout*40000UL/256);
  89. /* reload the counter */
  90. FWDGT_CTL = FWDGT_KEY_RELOAD;
  91. #endif
  92. }