uart.c 14 KB

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  1. #include "uart.h"
  2. #include "bsp/shark_bsp.h"
  3. #include "bsp/gpio.h"
  4. #include "libs/shark_libs.h"
  5. #define SHARK_UART_BAUDRATE 38400
  6. #define SHARK_UART0_com USART0
  7. #define SHARK_UART0_tx_port GPIOB
  8. #define SHARK_UART0_tx_pin GPIO_PIN_6
  9. #define SHARK_UART0_rx_port GPIOB
  10. #define SHARK_UART0_rx_pin GPIO_PIN_7
  11. #define SHARK_UART0_irq USART0_IRQn
  12. #define SHARK_UART0_clk RCU_USART0
  13. #define SHARK_UART0_tx_gpio_clk RCU_GPIOB
  14. #define SHARK_UART0_rx_gpio_clk RCU_GPIOB
  15. #define SHARK_UART0_tx_dma DMA
  16. #define SHARK_UART0_tx_dma_ch DMA_CH1
  17. #define SHARK_UART0_tx_dma_clk RCU_DMA
  18. #define SHARK_UART0_rx_dma DMA
  19. #define SHARK_UART0_rx_dma_ch DMA_CH2
  20. #define SHARK_UART0_rx_dma_clk RCU_DMA
  21. #define SHARK_UART1_com USART1
  22. #define SHARK_UART1_tx_port GPIOA
  23. #define SHARK_UART1_tx_pin GPIO_PIN_2
  24. #define SHARK_UART1_rx_port GPIOA
  25. #define SHARK_UART1_rx_pin GPIO_PIN_3
  26. #define SHARK_UART1_irq USART1_IRQn
  27. #define SHARK_UART1_clk RCU_USART1
  28. #define SHARK_UART1_tx_gpio_clk RCU_GPIOA
  29. #define SHARK_UART1_rx_gpio_clk RCU_GPIOA
  30. #define SHARK_UART1_tx_dma DMA
  31. #define SHARK_UART1_tx_dma_ch DMA_CH3
  32. #define SHARK_UART1_tx_dma_clk RCU_DMA
  33. #define SHARK_UART1_rx_dma DMA
  34. #define SHARK_UART1_rx_dma_ch DMA_CH4
  35. #define SHARK_UART1_rx_dma_clk RCU_DMA
  36. // ================================================================================
  37. static u8 shark_uart0_tx_cache[SHARK_UART_TX_MEM_SIZE];
  38. static u8 shark_uart1_tx_cache[SHARK_UART_TX_MEM_SIZE];
  39. static u8 shark_uart_rx_cache[SHARK_UART_RX_MEM_SIZE];
  40. static shark_uart_t _shark_uart[SHARK_UART_COUNT];
  41. static shark_task_t _uart_task;
  42. static bool new_prococol = false;
  43. static u64 _rx_time;
  44. #define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(uart->rx_dma_ch))
  45. extern void protocol_recv_frame(uart_enum_t uart_no, char *data, int len);
  46. extern void protocol_notify_old_frame(uart_enum_t uart_no);
  47. // ================================================================================
  48. static uart_enum_t _uart_index(uint32_t com){
  49. return com == SHARK_UART0_com?SHARK_UART0:SHARK_UART1;
  50. }
  51. static bool shark_uart_on_rx_frame(shark_uart_t *uart)
  52. {
  53. u16 crc0 = shark_decode_u16(uart->rx_frame + uart->rx_length);
  54. u16 crc1 = shark_crc16_check(uart->rx_frame, uart->rx_length);
  55. if (crc0 != crc1) {
  56. return false;
  57. }
  58. new_prococol = true;
  59. protocol_recv_frame(_uart_index(uart->uart_com), (char *)uart->rx_frame, uart->rx_length);
  60. return true;
  61. }
  62. static void shark_uart_rx(shark_uart_t *uart){
  63. while(1) {
  64. u8 data;
  65. update_dma_w_pos(uart);
  66. if (circle_get_one_data(&uart->rx_queue, &data) != 1) {
  67. if (!new_prococol){//通过老协议发送过来的,需要回复一个信息,告知使用新协议,霍尔移除,通信超时需要reset new_protocol
  68. if (shark_get_mseconds() >= (30 + _rx_time)) {
  69. _rx_time = 0xFFFFFFFFFFFFL;
  70. protocol_notify_old_frame(_uart_index(uart->uart_com));
  71. }
  72. }
  73. break;
  74. }
  75. _rx_time = shark_get_mseconds();
  76. switch(data){
  77. case CH_START:
  78. uart->rx_length = 0;
  79. uart->escape = false;
  80. break;
  81. case CH_END:
  82. if (uart->rx_length > 2 && uart->rx_length != 0xFF){
  83. shark_uart_on_rx_frame(uart);
  84. }
  85. uart->rx_length = 0xFF;
  86. break;
  87. case CH_ESC:
  88. uart->escape = true;
  89. break;
  90. default:
  91. if (uart->escape) {
  92. uart->escape = false;
  93. switch (data) {
  94. case CH_ESC_START:
  95. data = CH_START;
  96. break;
  97. case CH_ESC_END:
  98. data = CH_END;
  99. break;
  100. case CH_ESC_ESC:
  101. data = CH_ESC;
  102. break;
  103. default:
  104. data = 0xFF;
  105. }
  106. }
  107. if (uart->rx_length < sizeof(uart->rx_frame)) {
  108. uart->rx_frame[uart->rx_length] = data;
  109. uart->rx_length++;
  110. } else {
  111. uart->rx_length = 0xFF;
  112. }
  113. }
  114. }
  115. }
  116. static void shark_uart_dma_tx(shark_uart_t *uart)
  117. {
  118. u32 value = DMA_CHCTL(uart->tx_dma_ch);
  119. if (value & DMA_CHXCTL_CHEN) {
  120. if (SET != dma_flag_get(uart->tx_dma_ch, DMA_FLAG_FTF)) {
  121. return;
  122. }
  123. byte_queue_skip(&uart->tx_queue, uart->tx_length);
  124. DMA_CHCTL(uart->tx_dma_ch) = value & (~DMA_CHXCTL_CHEN);
  125. }
  126. uart->tx_length = byte_queue_peek(&uart->tx_queue);
  127. if (uart->tx_length > 0) {
  128. DMA_CHCNT(uart->tx_dma_ch) = uart->tx_length;
  129. DMA_CHMADDR(uart->tx_dma_ch) = (u32) byte_queue_head(&uart->tx_queue);
  130. dma_flag_clear(uart->tx_dma_ch, DMA_FLAG_FTF);
  131. DMA_CHCTL(uart->tx_dma_ch) = value | DMA_CHXCTL_CHEN;
  132. }
  133. }
  134. static void shark_uart_write(shark_uart_t *uart, const u8 *buff, u16 size)
  135. {
  136. while (size > 0) {
  137. u16 length = byte_queue_write(&uart->tx_queue, buff, size);
  138. if (length == size) {
  139. shark_uart_dma_tx(uart);
  140. break;
  141. }
  142. shark_uart_dma_tx(uart);
  143. buff += length;
  144. size -= length;
  145. }
  146. }
  147. static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
  148. {
  149. shark_uart_write(uart, &value, 1);
  150. }
  151. static void shark_uart_tx_dma_init(shark_uart_t *uart){
  152. dma_parameter_struct dma_init_struct;
  153. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  154. dma_deinit(uart->tx_dma_ch);
  155. dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
  156. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  157. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  158. dma_init_struct.periph_addr = (u32) &USART_TDATA(uart->uart_com);
  159. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  160. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  161. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  162. dma_init(uart->tx_dma_ch, &dma_init_struct);
  163. dma_circulation_disable(uart->tx_dma_ch);
  164. dma_memory_to_memory_disable(uart->tx_dma_ch);
  165. usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
  166. #if 0
  167. if (uart->tx_dma_ch == DMA_CH1) {
  168. nvic_irq_enable(DMA_Channel1_2_IRQn ,4, 0);
  169. }else {
  170. nvic_irq_enable(DMA_Channel3_4_IRQn ,4, 0);
  171. }
  172. dma_interrupt_enable(uart->tx_dma_ch, DMA_INT_FTF);
  173. #endif
  174. }
  175. static void shark_uart_rx_dma_init(shark_uart_t *uart){
  176. dma_parameter_struct dma_init_struct;
  177. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  178. dma_deinit(uart->rx_dma_ch);
  179. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  180. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  181. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  182. dma_init_struct.memory_addr = (u32)uart->rx_queue.buffer;
  183. dma_init_struct.number = uart->rx_queue.buffer_len;
  184. dma_init_struct.periph_addr = (u32) &USART_RDATA(uart->uart_com);
  185. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  186. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  187. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  188. dma_init(uart->rx_dma_ch, &dma_init_struct);
  189. dma_circulation_enable(uart->rx_dma_ch);
  190. dma_memory_to_memory_disable(uart->rx_dma_ch);
  191. dma_channel_enable(uart->rx_dma_ch);
  192. usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
  193. }
  194. static void shark_uart_pin_init(shark_uart_t *uart){
  195. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  196. rcu_periph_clock_enable(SHARK_UART0_clk);
  197. rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
  198. rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
  199. gpio_af_set(SHARK_UART0_tx_port, GPIO_AF_0,SHARK_UART0_tx_pin);
  200. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_tx_pin);
  201. gpio_output_options_set(SHARK_UART0_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART0_tx_pin);
  202. gpio_af_set(SHARK_UART0_rx_port, GPIO_AF_0,SHARK_UART0_rx_pin);
  203. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_rx_pin);
  204. gpio_output_options_set(SHARK_UART0_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
  205. }else {
  206. rcu_periph_clock_enable(SHARK_UART1_clk);
  207. rcu_periph_clock_enable(SHARK_UART1_rx_gpio_clk);
  208. rcu_periph_clock_enable(SHARK_UART1_tx_gpio_clk);
  209. gpio_af_set(SHARK_UART1_tx_port, GPIO_AF_1,SHARK_UART1_tx_pin);
  210. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_tx_pin);
  211. gpio_output_options_set(SHARK_UART1_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART1_tx_pin);
  212. gpio_af_set(SHARK_UART1_rx_port, GPIO_AF_1,SHARK_UART1_rx_pin);
  213. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_rx_pin);
  214. gpio_output_options_set(SHARK_UART1_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART1_rx_pin);
  215. }
  216. }
  217. static void shark_uart_device_init(shark_uart_t *uart){
  218. usart_deinit(uart->uart_com);
  219. usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
  220. usart_word_length_set(uart->uart_com, USART_WL_8BIT);
  221. usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
  222. usart_parity_config(uart->uart_com, USART_PM_NONE);
  223. usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
  224. usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
  225. usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
  226. usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
  227. }
  228. static u32 shark_uart_handler(void)
  229. {
  230. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  231. if (uart->uart_com != 0) {
  232. shark_uart_rx(uart);
  233. shark_uart_dma_tx(uart);
  234. }
  235. uart = _shark_uart + SHARK_UART1;
  236. if (uart->uart_com != 0) {
  237. shark_uart_rx(uart);
  238. shark_uart_dma_tx(uart);
  239. }
  240. return 0;
  241. }
  242. void shark_uart_flush(void){
  243. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  244. if (uart->uart_com != 0) {
  245. shark_uart_dma_tx(uart);
  246. }
  247. uart = _shark_uart + SHARK_UART1;
  248. if (uart->uart_com != 0) {
  249. shark_uart_dma_tx(uart);
  250. }
  251. }
  252. #if 0
  253. void DMA_Channel1_2_IRQHandler(void){
  254. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  255. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  256. shark_uart_dma_tx(uart);
  257. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  258. }
  259. }
  260. void DMA_Channel3_4_IRQHandler(void){
  261. shark_uart_t *uart = _shark_uart + SHARK_UART1;
  262. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  263. shark_uart_dma_tx(uart);
  264. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  265. }
  266. }
  267. #endif
  268. static u8 *tx_cache_addr(uart_enum_t uart_no){
  269. return (uart_no == SHARK_UART0)?shark_uart0_tx_cache:shark_uart1_tx_cache;
  270. }
  271. void shark_uart_deinit(uart_enum_t uart_no){
  272. shark_uart_t *uart = _shark_uart + uart_no;
  273. if (uart->uart_com != 0) {
  274. usart_disable(uart->uart_com);
  275. usart_deinit(uart->uart_com);
  276. rcu_periph_clock_enable(uart_no == SHARK_UART0?SHARK_UART0_clk:SHARK_UART1_clk);
  277. dma_channel_disable(uart->rx_dma_ch);
  278. dma_channel_disable(uart->tx_dma_ch);
  279. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  280. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  281. }
  282. if (uart_no == SHARK_UART0) {
  283. UART0_IR_EN(0);
  284. }else {
  285. UART1_IR_EN(0);
  286. }
  287. new_prococol = false;
  288. }
  289. void shark_uart_init(uart_enum_t uart_no)
  290. {
  291. shark_uart_t *uart = _shark_uart + uart_no;
  292. uart->escape = false;
  293. uart->rx_length = 0;
  294. uart->tx_length = 0;
  295. uart->uart_com = (uart_no == SHARK_UART0)?SHARK_UART0_com:SHARK_UART1_com;
  296. circle_buffer_init(&uart->rx_queue, shark_uart_rx_cache, SHARK_UART_TX_MEM_SIZE);
  297. byte_queue_init(&uart->tx_queue,tx_cache_addr(uart_no), SHARK_UART_TX_MEM_SIZE);
  298. uart->rx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_rx_dma_ch:SHARK_UART1_rx_dma_ch;
  299. uart->tx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_tx_dma_ch:SHARK_UART1_tx_dma_ch;
  300. shark_uart_pin_init(uart);
  301. shark_uart_device_init(uart);
  302. shark_uart_rx_dma_init(uart);
  303. shark_uart_tx_dma_init(uart);
  304. usart_enable(uart->uart_com);
  305. if (_uart_task.handler == NULL) {
  306. _uart_task.handler = shark_uart_handler;
  307. shark_task_add(&_uart_task);
  308. }
  309. if (uart_no == SHARK_UART0) {
  310. UART0_IR_EN(1);
  311. }else {
  312. UART1_IR_EN(1);
  313. }
  314. _rx_time = 0xFFFFFFFFFFFFL;
  315. }
  316. static void shark_uart_write_byte_esc(shark_uart_t *uart, u8 value)
  317. {
  318. switch (value) {
  319. case CH_START:
  320. shark_uart_write_byte(uart, CH_ESC);
  321. value = CH_ESC_START;
  322. break;
  323. case CH_END:
  324. shark_uart_write_byte(uart, CH_ESC);
  325. value = CH_ESC_END;
  326. break;
  327. case CH_ESC:
  328. shark_uart_write_byte(uart, CH_ESC);
  329. value = CH_ESC_ESC;
  330. break;
  331. }
  332. shark_uart_write_byte(uart, value);
  333. }
  334. static void shark_uart_write_esc(shark_uart_t *uart, const u8 *buff, u16 length)
  335. {
  336. const u8 *buff_end;
  337. for (buff_end = buff + length; buff < buff_end; buff++) {
  338. shark_uart_write_byte_esc(uart, *buff);
  339. }
  340. }
  341. static void shark_uart_tx_start(shark_uart_t *uart)
  342. {
  343. shark_uart_write_byte(uart, CH_START);
  344. uart->tx_crc16 = 0;
  345. }
  346. static void shark_uart_tx_continue(shark_uart_t *uart, const void *buff, u16 length)
  347. {
  348. shark_uart_write_esc(uart, (const u8 *) buff, length);
  349. uart->tx_crc16 = shark_crc16_update(uart->tx_crc16, (const u8 *) buff, length);
  350. }
  351. static void shark_uart_tx_end(shark_uart_t *uart)
  352. {
  353. shark_uart_write_esc(uart, (u8 *)&uart->tx_crc16, sizeof(uart->tx_crc16));
  354. shark_uart_write_byte(uart, CH_END);
  355. }
  356. void shark_uart_write_frame(uart_enum_t uart_no, uint8_t *bytes, int len){
  357. shark_uart_t *uart = _shark_uart + uart_no;
  358. shark_uart_tx_start(uart);
  359. shark_uart_tx_continue(uart, bytes, len);
  360. shark_uart_tx_end(uart);
  361. }
  362. void shark_uart_frame_start(uart_enum_t uart_no, uint8_t *bytes, int len){
  363. shark_uart_t *uart = _shark_uart + uart_no;
  364. shark_uart_tx_start(uart);
  365. shark_uart_tx_continue(uart, bytes, len);
  366. }
  367. void shark_uart_frame_continue(uart_enum_t uart_no, uint8_t *bytes, int len){
  368. shark_uart_t *uart = _shark_uart + uart_no;
  369. shark_uart_tx_continue(uart, bytes, len);
  370. }
  371. void shark_uart_frame_end(uart_enum_t uart_no){
  372. shark_uart_tx_end(_shark_uart + uart_no);
  373. }
  374. void shark_uart_write_bytes(uart_enum_t uart_no, u8 *buff, u16 size){
  375. shark_uart_write(_shark_uart + uart_no, buff, size);
  376. }