bms/Application/bsp/bsp.c

#include "bsp/shark_bsp.h"
#include "bsp/gpio.h"
#include "bsp/uart.h"
#include "bsp/AT24CXX.h"
#include "bsp/shark_rtc.h"
#include "bsp/clock.h"
#if defined CONFIG_BOARD_SP700
const char iap_board_name[] __attribute__((at(0x08002800))) = "SP700";
#elif defined CONFIG_BOARD_SP600
const char iap_board_name[] __attribute__((at(0x08002800))) = "SP600";
#endif
const char iap_fw_version[] __attribute__((at(0x08002A00))) = "1.0";
const char iap_fw_name[] __attribute__((at(0x08002C00))) = "App";

#define CONFIG_DEBUG 0

extern void system_clock_config(void);
extern void SystemCoreClockUpdate(void);
#define ALARM_TEST 1
//all board's low level init is here
void bsp_init(void){
	wdog_start(4);
	shark_rtc_init();
	gpio_init();
	DCDC_VOL_OPEN(1);
	delay_us(100);
	system_clock_config(); //after dcdc open, MCU can run on full speed
	SystemCoreClockUpdate();
	shark_uart_init(SHARK_UART0);
	shark_uart_init(SHARK_UART1);
	AT24CXX_Init();
}

/* timeout:1-25 */
void wdog_start(int timeout){
#if CONFIG_DEBUG == 0
	/* enable IRC40K */
	rcu_osci_on(RCU_IRC40K);
	/* wait till IRC40K is ready */
	while(SUCCESS != rcu_osci_stab_wait(RCU_IRC40K)){
	}  
	
	/* confiure FWDGT counter clock: 40KHz(IRC40K) / 256 = 0.15625 KHz */
	fwdgt_config(timeout*40000UL/256, FWDGT_PSC_DIV256);  
	/* after 4 seconds to generate a reset */
	fwdgt_enable();
#endif   

}

void wdog_reload(void){
#if CONFIG_DEBUG == 0
	fwdgt_counter_reload();
#endif 
}

void  wdog_set_timeout(int timeout)
{  
#if CONFIG_DEBUG == 0
    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    FWDGT_RLD = RLD_RLD(timeout*40000UL/256);

    /* reload the counter */
    FWDGT_CTL = FWDGT_KEY_RELOAD;
#endif	
}