uart.c 14 KB

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  1. #include "uart.h"
  2. #include "bsp/shark_bsp.h"
  3. #include "bsp/gpio.h"
  4. #include "libs/shark_libs.h"
  5. #define SHARK_UART_BAUDRATE 38400
  6. #define SHARK_UART0_com USART0
  7. #define SHARK_UART0_tx_port GPIOB
  8. #define SHARK_UART0_tx_pin GPIO_PIN_6
  9. #define SHARK_UART0_rx_port GPIOB
  10. #define SHARK_UART0_rx_pin GPIO_PIN_7
  11. #define SHARK_UART0_irq USART0_IRQn
  12. #define SHARK_UART0_clk RCU_USART0
  13. #define SHARK_UART0_tx_gpio_clk RCU_GPIOB
  14. #define SHARK_UART0_rx_gpio_clk RCU_GPIOB
  15. #define SHARK_UART0_tx_dma DMA
  16. #define SHARK_UART0_tx_dma_ch DMA_CH1
  17. #define SHARK_UART0_tx_dma_clk RCU_DMA
  18. #define SHARK_UART0_rx_dma DMA
  19. #define SHARK_UART0_rx_dma_ch DMA_CH2
  20. #define SHARK_UART0_rx_dma_clk RCU_DMA
  21. #define SHARK_UART1_com USART1
  22. #define SHARK_UART1_tx_port GPIOA
  23. #define SHARK_UART1_tx_pin GPIO_PIN_2
  24. #define SHARK_UART1_rx_port GPIOA
  25. #define SHARK_UART1_rx_pin GPIO_PIN_3
  26. #define SHARK_UART1_irq USART1_IRQn
  27. #define SHARK_UART1_clk RCU_USART1
  28. #define SHARK_UART1_tx_gpio_clk RCU_GPIOA
  29. #define SHARK_UART1_rx_gpio_clk RCU_GPIOA
  30. #define SHARK_UART1_tx_dma DMA
  31. #define SHARK_UART1_tx_dma_ch DMA_CH3
  32. #define SHARK_UART1_tx_dma_clk RCU_DMA
  33. #define SHARK_UART1_rx_dma DMA
  34. #define SHARK_UART1_rx_dma_ch DMA_CH4
  35. #define SHARK_UART1_rx_dma_clk RCU_DMA
  36. // ================================================================================
  37. static u8 shark_uart0_tx_cache[SHARK_UART_TX_MEM_SIZE];
  38. static u8 shark_uart1_tx_cache[SHARK_UART_TX_MEM_SIZE];
  39. static u8 shark_uart_rx_cache[SHARK_UART_RX_MEM_SIZE];
  40. static shark_uart_t _shark_uart[SHARK_UART_COUNT];
  41. static shark_task_t _uart_task;
  42. static bool new_prococol = false;
  43. static u64 _rx_time;
  44. static bool uart_no_data = false;
  45. #define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(uart->rx_dma_ch))
  46. extern void protocol_recv_frame(uart_enum_t uart_no, char *data, int len);
  47. extern void protocol_notify_old_frame(uart_enum_t uart_no);
  48. // ================================================================================
  49. static uart_enum_t _uart_index(uint32_t com){
  50. return com == SHARK_UART0_com?SHARK_UART0:SHARK_UART1;
  51. }
  52. static bool shark_uart_on_rx_frame(shark_uart_t *uart)
  53. {
  54. u16 crc0 = shark_decode_u16(uart->rx_frame + uart->rx_length);
  55. u16 crc1 = shark_crc16_check(uart->rx_frame, uart->rx_length);
  56. if (crc0 != crc1) {
  57. return false;
  58. }
  59. new_prococol = true;
  60. protocol_recv_frame(_uart_index(uart->uart_com), (char *)uart->rx_frame, uart->rx_length);
  61. return true;
  62. }
  63. static void shark_uart_rx(shark_uart_t *uart){
  64. while(1) {
  65. u8 data;
  66. update_dma_w_pos(uart);
  67. if (circle_get_one_data(&uart->rx_queue, &data) != 1) {
  68. if (!new_prococol){//通过老协议发送过来的,需要回复一个信息,告知使用新协议,霍尔移除,通信超时需要reset new_protocol
  69. if (shark_get_mseconds() >= (30 + _rx_time)) {
  70. _rx_time = 0xFFFFFFFFFFFFL;
  71. protocol_notify_old_frame(_uart_index(uart->uart_com));
  72. }
  73. }else if (shark_get_mseconds() >= (2000 + _rx_time)){
  74. uart_no_data = true;
  75. }else {
  76. uart_no_data = false;
  77. }
  78. break;
  79. }
  80. _rx_time = shark_get_mseconds();
  81. switch(data){
  82. case CH_START:
  83. uart->rx_length = 0;
  84. uart->escape = false;
  85. break;
  86. case CH_END:
  87. if (uart->rx_length > 2 && uart->rx_length != 0xFF){
  88. uart->rx_length -= 2; //skip crc
  89. shark_uart_on_rx_frame(uart);
  90. }
  91. uart->rx_length = 0xFF;
  92. break;
  93. case CH_ESC:
  94. uart->escape = true;
  95. break;
  96. default:
  97. if (uart->escape) {
  98. uart->escape = false;
  99. switch (data) {
  100. case CH_ESC_START:
  101. data = CH_START;
  102. break;
  103. case CH_ESC_END:
  104. data = CH_END;
  105. break;
  106. case CH_ESC_ESC:
  107. data = CH_ESC;
  108. break;
  109. default:
  110. data = 0xFF;
  111. }
  112. }
  113. if (uart->rx_length < sizeof(uart->rx_frame)) {
  114. uart->rx_frame[uart->rx_length] = data;
  115. uart->rx_length++;
  116. } else {
  117. uart->rx_length = 0xFF;
  118. }
  119. }
  120. }
  121. }
  122. static void shark_uart_dma_tx(shark_uart_t *uart)
  123. {
  124. u32 value = DMA_CHCTL(uart->tx_dma_ch);
  125. if (value & DMA_CHXCTL_CHEN) {
  126. if (SET != dma_flag_get(uart->tx_dma_ch, DMA_FLAG_FTF)) {
  127. return;
  128. }
  129. byte_queue_skip(&uart->tx_queue, uart->tx_length);
  130. DMA_CHCTL(uart->tx_dma_ch) = value & (~DMA_CHXCTL_CHEN);
  131. }
  132. uart->tx_length = byte_queue_peek(&uart->tx_queue);
  133. if (uart->tx_length > 0) {
  134. DMA_CHCNT(uart->tx_dma_ch) = uart->tx_length;
  135. DMA_CHMADDR(uart->tx_dma_ch) = (u32) byte_queue_head(&uart->tx_queue);
  136. dma_flag_clear(uart->tx_dma_ch, DMA_FLAG_FTF);
  137. DMA_CHCTL(uart->tx_dma_ch) = value | DMA_CHXCTL_CHEN;
  138. }
  139. }
  140. static void shark_uart_write(shark_uart_t *uart, const u8 *buff, u16 size)
  141. {
  142. while (size > 0) {
  143. u16 length = byte_queue_write(&uart->tx_queue, buff, size);
  144. if (length == size) {
  145. shark_uart_dma_tx(uart);
  146. break;
  147. }
  148. shark_uart_dma_tx(uart);
  149. buff += length;
  150. size -= length;
  151. }
  152. }
  153. static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
  154. {
  155. shark_uart_write(uart, &value, 1);
  156. }
  157. static void shark_uart_tx_dma_init(shark_uart_t *uart){
  158. dma_parameter_struct dma_init_struct;
  159. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  160. dma_deinit(uart->tx_dma_ch);
  161. dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
  162. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  163. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  164. dma_init_struct.periph_addr = (u32) &USART_TDATA(uart->uart_com);
  165. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  166. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  167. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  168. dma_init(uart->tx_dma_ch, &dma_init_struct);
  169. dma_circulation_disable(uart->tx_dma_ch);
  170. dma_memory_to_memory_disable(uart->tx_dma_ch);
  171. usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
  172. #if 0
  173. if (uart->tx_dma_ch == DMA_CH1) {
  174. nvic_irq_enable(DMA_Channel1_2_IRQn ,4, 0);
  175. }else {
  176. nvic_irq_enable(DMA_Channel3_4_IRQn ,4, 0);
  177. }
  178. dma_interrupt_enable(uart->tx_dma_ch, DMA_INT_FTF);
  179. #endif
  180. }
  181. static void shark_uart_rx_dma_init(shark_uart_t *uart){
  182. dma_parameter_struct dma_init_struct;
  183. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  184. dma_deinit(uart->rx_dma_ch);
  185. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  186. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  187. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  188. dma_init_struct.memory_addr = (u32)uart->rx_queue.buffer;
  189. dma_init_struct.number = uart->rx_queue.buffer_len;
  190. dma_init_struct.periph_addr = (u32) &USART_RDATA(uart->uart_com);
  191. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  192. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  193. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  194. dma_init(uart->rx_dma_ch, &dma_init_struct);
  195. dma_circulation_enable(uart->rx_dma_ch);
  196. dma_memory_to_memory_disable(uart->rx_dma_ch);
  197. dma_channel_enable(uart->rx_dma_ch);
  198. usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
  199. }
  200. static void shark_uart_pin_init(shark_uart_t *uart){
  201. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  202. rcu_periph_clock_enable(SHARK_UART0_clk);
  203. rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
  204. rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
  205. gpio_af_set(SHARK_UART0_tx_port, GPIO_AF_0,SHARK_UART0_tx_pin);
  206. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_tx_pin);
  207. gpio_output_options_set(SHARK_UART0_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART0_tx_pin);
  208. gpio_af_set(SHARK_UART0_rx_port, GPIO_AF_0,SHARK_UART0_rx_pin);
  209. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_rx_pin);
  210. gpio_output_options_set(SHARK_UART0_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
  211. }else {
  212. rcu_periph_clock_enable(SHARK_UART1_clk);
  213. rcu_periph_clock_enable(SHARK_UART1_rx_gpio_clk);
  214. rcu_periph_clock_enable(SHARK_UART1_tx_gpio_clk);
  215. gpio_af_set(SHARK_UART1_tx_port, GPIO_AF_1,SHARK_UART1_tx_pin);
  216. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_tx_pin);
  217. gpio_output_options_set(SHARK_UART1_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART1_tx_pin);
  218. gpio_af_set(SHARK_UART1_rx_port, GPIO_AF_1,SHARK_UART1_rx_pin);
  219. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_rx_pin);
  220. gpio_output_options_set(SHARK_UART1_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART1_rx_pin);
  221. }
  222. }
  223. static void shark_uart_device_init(shark_uart_t *uart){
  224. usart_deinit(uart->uart_com);
  225. usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
  226. usart_word_length_set(uart->uart_com, USART_WL_8BIT);
  227. usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
  228. usart_parity_config(uart->uart_com, USART_PM_NONE);
  229. usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
  230. usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
  231. usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
  232. usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
  233. }
  234. static u32 shark_uart_handler(void)
  235. {
  236. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  237. if (uart->uart_com != 0) {
  238. shark_uart_rx(uart);
  239. shark_uart_dma_tx(uart);
  240. }
  241. uart = _shark_uart + SHARK_UART1;
  242. if (uart->uart_com != 0) {
  243. shark_uart_rx(uart);
  244. shark_uart_dma_tx(uart);
  245. }
  246. return 0;
  247. }
  248. void shark_uart_flush(void){
  249. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  250. if (uart->uart_com != 0) {
  251. shark_uart_dma_tx(uart);
  252. }
  253. uart = _shark_uart + SHARK_UART1;
  254. if (uart->uart_com != 0) {
  255. shark_uart_dma_tx(uart);
  256. }
  257. }
  258. #if 0
  259. void DMA_Channel1_2_IRQHandler(void){
  260. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  261. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  262. shark_uart_dma_tx(uart);
  263. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  264. }
  265. }
  266. void DMA_Channel3_4_IRQHandler(void){
  267. shark_uart_t *uart = _shark_uart + SHARK_UART1;
  268. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  269. shark_uart_dma_tx(uart);
  270. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  271. }
  272. }
  273. #endif
  274. static u8 *tx_cache_addr(uart_enum_t uart_no){
  275. return (uart_no == SHARK_UART0)?shark_uart0_tx_cache:shark_uart1_tx_cache;
  276. }
  277. void shark_uart_deinit(uart_enum_t uart_no){
  278. shark_uart_t *uart = _shark_uart + uart_no;
  279. if (uart->uart_com != 0) {
  280. usart_disable(uart->uart_com);
  281. usart_deinit(uart->uart_com);
  282. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_clk:SHARK_UART1_clk);
  283. dma_channel_disable(uart->rx_dma_ch);
  284. dma_channel_disable(uart->tx_dma_ch);
  285. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  286. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  287. }
  288. if (uart_no == SHARK_UART0) {
  289. UART0_IR_EN(0);
  290. }else {
  291. UART1_IR_EN(0);
  292. }
  293. new_prococol = false;
  294. uart_no_data = true;
  295. }
  296. bool shark_uart_timeout(void){
  297. return uart_no_data;
  298. }
  299. void shark_uart_init(uart_enum_t uart_no)
  300. {
  301. shark_uart_t *uart = _shark_uart + uart_no;
  302. uart->escape = false;
  303. uart->rx_length = 0;
  304. uart->tx_length = 0;
  305. uart->uart_com = (uart_no == SHARK_UART0)?SHARK_UART0_com:SHARK_UART1_com;
  306. circle_buffer_init(&uart->rx_queue, shark_uart_rx_cache, SHARK_UART_TX_MEM_SIZE);
  307. byte_queue_init(&uart->tx_queue,tx_cache_addr(uart_no), SHARK_UART_TX_MEM_SIZE);
  308. uart->rx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_rx_dma_ch:SHARK_UART1_rx_dma_ch;
  309. uart->tx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_tx_dma_ch:SHARK_UART1_tx_dma_ch;
  310. shark_uart_pin_init(uart);
  311. shark_uart_device_init(uart);
  312. shark_uart_rx_dma_init(uart);
  313. shark_uart_tx_dma_init(uart);
  314. usart_enable(uart->uart_com);
  315. if (_uart_task.handler == NULL) {
  316. _uart_task.handler = shark_uart_handler;
  317. shark_task_add(&_uart_task);
  318. }
  319. if (uart_no == SHARK_UART0) {
  320. UART0_IR_EN(1);
  321. }else {
  322. UART1_IR_EN(1);
  323. }
  324. _rx_time = 0xFFFFFFFFFFFFL;
  325. }
  326. static void shark_uart_write_byte_esc(shark_uart_t *uart, u8 value)
  327. {
  328. switch (value) {
  329. case CH_START:
  330. shark_uart_write_byte(uart, CH_ESC);
  331. value = CH_ESC_START;
  332. break;
  333. case CH_END:
  334. shark_uart_write_byte(uart, CH_ESC);
  335. value = CH_ESC_END;
  336. break;
  337. case CH_ESC:
  338. shark_uart_write_byte(uart, CH_ESC);
  339. value = CH_ESC_ESC;
  340. break;
  341. }
  342. shark_uart_write_byte(uart, value);
  343. }
  344. static void shark_uart_write_esc(shark_uart_t *uart, const u8 *buff, u16 length)
  345. {
  346. const u8 *buff_end;
  347. for (buff_end = buff + length; buff < buff_end; buff++) {
  348. shark_uart_write_byte_esc(uart, *buff);
  349. }
  350. }
  351. static void shark_uart_tx_start(shark_uart_t *uart)
  352. {
  353. shark_uart_write_byte(uart, CH_START);
  354. uart->tx_crc16 = 0;
  355. }
  356. static void shark_uart_tx_continue(shark_uart_t *uart, const void *buff, u16 length)
  357. {
  358. shark_uart_write_esc(uart, (const u8 *) buff, length);
  359. uart->tx_crc16 = shark_crc16_update(uart->tx_crc16, (const u8 *) buff, length);
  360. }
  361. static void shark_uart_tx_end(shark_uart_t *uart)
  362. {
  363. shark_uart_write_esc(uart, (u8 *)&uart->tx_crc16, sizeof(uart->tx_crc16));
  364. shark_uart_write_byte(uart, CH_END);
  365. }
  366. void shark_uart_write_frame(uart_enum_t uart_no, uint8_t *bytes, int len){
  367. shark_uart_t *uart = _shark_uart + uart_no;
  368. shark_uart_tx_start(uart);
  369. shark_uart_tx_continue(uart, bytes, len);
  370. shark_uart_tx_end(uart);
  371. }
  372. void shark_uart_frame_start(uart_enum_t uart_no, uint8_t *bytes, int len){
  373. shark_uart_t *uart = _shark_uart + uart_no;
  374. shark_uart_tx_start(uart);
  375. shark_uart_tx_continue(uart, bytes, len);
  376. }
  377. void shark_uart_frame_continue(uart_enum_t uart_no, uint8_t *bytes, int len){
  378. shark_uart_t *uart = _shark_uart + uart_no;
  379. shark_uart_tx_continue(uart, bytes, len);
  380. }
  381. void shark_uart_frame_end(uart_enum_t uart_no){
  382. shark_uart_tx_end(_shark_uart + uart_no);
  383. }
  384. void shark_uart_write_bytes(uart_enum_t uart_no, u8 *buff, u16 size){
  385. shark_uart_write(_shark_uart + uart_no, buff, size);
  386. }