uart.c 15 KB

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  1. #include "uart.h"
  2. #include "bsp/shark_bsp.h"
  3. #include "bsp/gpio.h"
  4. #include "libs/shark_libs.h"
  5. #define SHARK_UART_BAUDRATE 38400
  6. #define SHARK_UART0_com USART0
  7. #define SHARK_UART0_tx_port GPIOB
  8. #define SHARK_UART0_tx_pin GPIO_PIN_6
  9. #define SHARK_UART0_rx_port GPIOB
  10. #define SHARK_UART0_rx_pin GPIO_PIN_7
  11. #define SHARK_UART0_irq USART0_IRQn
  12. #define SHARK_UART0_clk RCU_USART0
  13. #define SHARK_UART0_tx_gpio_clk RCU_GPIOB
  14. #define SHARK_UART0_rx_gpio_clk RCU_GPIOB
  15. #define SHARK_UART0_tx_dma DMA
  16. #define SHARK_UART0_tx_dma_ch DMA_CH1
  17. #define SHARK_UART0_tx_dma_clk RCU_DMA
  18. #define SHARK_UART0_rx_dma DMA
  19. #define SHARK_UART0_rx_dma_ch DMA_CH2
  20. #define SHARK_UART0_rx_dma_clk RCU_DMA
  21. #define SHARK_UART1_com USART1
  22. #define SHARK_UART1_tx_port GPIOA
  23. #define SHARK_UART1_tx_pin GPIO_PIN_2
  24. #define SHARK_UART1_rx_port GPIOA
  25. #define SHARK_UART1_rx_pin GPIO_PIN_3
  26. #define SHARK_UART1_irq USART1_IRQn
  27. #define SHARK_UART1_clk RCU_USART1
  28. #define SHARK_UART1_tx_gpio_clk RCU_GPIOA
  29. #define SHARK_UART1_rx_gpio_clk RCU_GPIOA
  30. #define SHARK_UART1_tx_dma DMA
  31. #define SHARK_UART1_tx_dma_ch DMA_CH3
  32. #define SHARK_UART1_tx_dma_clk RCU_DMA
  33. #define SHARK_UART1_rx_dma DMA
  34. #define SHARK_UART1_rx_dma_ch DMA_CH4
  35. #define SHARK_UART1_rx_dma_clk RCU_DMA
  36. // ================================================================================
  37. static u8 shark_uart0_tx_cache[SHARK_UART_TX_MEM_SIZE];
  38. static u8 shark_uart1_tx_cache[SHARK_UART_TX_MEM_SIZE];
  39. static u8 shark_uart_rx_cache[SHARK_UART_RX_MEM_SIZE];
  40. static shark_uart_t _shark_uart[2];
  41. static shark_task_t _uart_task;
  42. static u64 _rx_time;
  43. ///static bool uart_no_data = false;
  44. #define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(uart->rx_dma_ch))
  45. extern void protocol_recv_frame(uart_enum_t uart_no, char *data, int len);
  46. extern void protocol_old_recv_frame(uart_enum_t uart_no, uint8_t *data, int len);
  47. // ================================================================================
  48. static uart_enum_t _uart_index(uint32_t com){
  49. return com == SHARK_UART0_com?SHARK_UART0:SHARK_UART1;
  50. }
  51. static bool shark_uart_on_rx_frame(shark_uart_t *uart)
  52. {
  53. u16 crc0 = shark_decode_u16(uart->rx_frame + uart->rx_length);
  54. u16 crc1 = shark_crc16_check(uart->rx_frame, uart->rx_length);
  55. if (crc0 != crc1) {
  56. return false;
  57. }
  58. protocol_recv_frame(_uart_index(uart->uart_com), (char *)uart->rx_frame, uart->rx_length);
  59. return true;
  60. }
  61. static void shark_uart_rx(shark_uart_t *uart){
  62. while(1) {
  63. u8 data;
  64. update_dma_w_pos(uart);
  65. if (circle_get_one_data(&uart->rx_queue, &data) != 1) {
  66. if (shark_get_mseconds() >= (30 + _rx_time)) {
  67. //_rx_time = 0xFFFFFFFFFFFFL;
  68. if (uart->rx_length_old_prot > 0){
  69. protocol_old_recv_frame(_uart_index(uart->uart_com), uart->rx_frame_old_prot, uart->rx_length_old_prot);
  70. uart->rx_length_old_prot = 0;
  71. }
  72. }
  73. if (shark_get_mseconds() >= (UART_TIMEOUT + _rx_time)){
  74. uart->uart_no_data = true;
  75. }else {
  76. uart->uart_no_data = false;
  77. }
  78. break;
  79. }
  80. _rx_time = shark_get_mseconds();
  81. uart->rx_frame_old_prot[uart->rx_length_old_prot ++] = data;
  82. if (uart->rx_length_old_prot == sizeof(uart->rx_frame_old_prot)){
  83. uart->rx_length_old_prot = 0;
  84. }
  85. switch(data){
  86. case CH_START:
  87. uart->rx_length = 0;
  88. uart->escape = false;
  89. break;
  90. case CH_END:
  91. if (uart->rx_length > 2 && uart->rx_length != 0xFFFF){
  92. uart->rx_length -= 2; //skip crc
  93. shark_uart_on_rx_frame(uart);
  94. }
  95. uart->rx_length = 0xFFFF;
  96. break;
  97. case CH_ESC:
  98. uart->escape = true;
  99. break;
  100. default:
  101. if (uart->escape) {
  102. uart->escape = false;
  103. switch (data) {
  104. case CH_ESC_START:
  105. data = CH_START;
  106. break;
  107. case CH_ESC_END:
  108. data = CH_END;
  109. break;
  110. case CH_ESC_ESC:
  111. data = CH_ESC;
  112. break;
  113. default:
  114. data = 0xFF;
  115. }
  116. }
  117. if (uart->rx_length < sizeof(uart->rx_frame)) {
  118. uart->rx_frame[uart->rx_length] = data;
  119. uart->rx_length++;
  120. } else {
  121. uart->rx_length = 0xFFFF;
  122. }
  123. }
  124. }
  125. }
  126. static void shark_uart_dma_tx(shark_uart_t *uart)
  127. {
  128. u32 value = DMA_CHCTL(uart->tx_dma_ch);
  129. if (value & DMA_CHXCTL_CHEN) {
  130. if (SET != dma_flag_get(uart->tx_dma_ch, DMA_FLAG_FTF)) {
  131. return;
  132. }
  133. byte_queue_skip(&uart->tx_queue, uart->tx_length);
  134. DMA_CHCTL(uart->tx_dma_ch) = value & (~DMA_CHXCTL_CHEN);
  135. }
  136. uart->tx_length = byte_queue_peek(&uart->tx_queue);
  137. if (uart->tx_length > 0) {
  138. DMA_CHCNT(uart->tx_dma_ch) = uart->tx_length;
  139. DMA_CHMADDR(uart->tx_dma_ch) = (u32) byte_queue_head(&uart->tx_queue);
  140. dma_flag_clear(uart->tx_dma_ch, DMA_FLAG_FTF);
  141. DMA_CHCTL(uart->tx_dma_ch) = value | DMA_CHXCTL_CHEN;
  142. }
  143. }
  144. static void shark_uart_write(shark_uart_t *uart, const u8 *buff, u16 size)
  145. {
  146. while (size > 0) {
  147. u16 length = byte_queue_write(&uart->tx_queue, buff, size);
  148. if (length == size) {
  149. shark_uart_dma_tx(uart);
  150. break;
  151. }
  152. shark_uart_dma_tx(uart);
  153. buff += length;
  154. size -= length;
  155. }
  156. }
  157. static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
  158. {
  159. shark_uart_write(uart, &value, 1);
  160. }
  161. static void shark_uart_tx_dma_init(shark_uart_t *uart){
  162. dma_parameter_struct dma_init_struct;
  163. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  164. dma_deinit(uart->tx_dma_ch);
  165. dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
  166. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  167. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  168. dma_init_struct.periph_addr = (u32) &USART_TDATA(uart->uart_com);
  169. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  170. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  171. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  172. dma_init(uart->tx_dma_ch, &dma_init_struct);
  173. dma_circulation_disable(uart->tx_dma_ch);
  174. dma_memory_to_memory_disable(uart->tx_dma_ch);
  175. usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
  176. #if 0
  177. if (uart->tx_dma_ch == DMA_CH1) {
  178. nvic_irq_enable(DMA_Channel1_2_IRQn ,4, 0);
  179. }else {
  180. nvic_irq_enable(DMA_Channel3_4_IRQn ,4, 0);
  181. }
  182. dma_interrupt_enable(uart->tx_dma_ch, DMA_INT_FTF);
  183. #endif
  184. }
  185. static void shark_uart_rx_dma_init(shark_uart_t *uart){
  186. dma_parameter_struct dma_init_struct;
  187. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  188. dma_deinit(uart->rx_dma_ch);
  189. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  190. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  191. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  192. dma_init_struct.memory_addr = (u32)uart->rx_queue.buffer;
  193. dma_init_struct.number = uart->rx_queue.buffer_len;
  194. dma_init_struct.periph_addr = (u32) &USART_RDATA(uart->uart_com);
  195. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  196. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  197. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  198. dma_init(uart->rx_dma_ch, &dma_init_struct);
  199. dma_circulation_enable(uart->rx_dma_ch);
  200. dma_memory_to_memory_disable(uart->rx_dma_ch);
  201. dma_channel_enable(uart->rx_dma_ch);
  202. usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
  203. }
  204. static void shark_uart_pin_init(shark_uart_t *uart){
  205. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  206. rcu_periph_clock_enable(SHARK_UART0_clk);
  207. rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
  208. rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
  209. gpio_af_set(SHARK_UART0_tx_port, GPIO_AF_0,SHARK_UART0_tx_pin);
  210. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_tx_pin);
  211. gpio_output_options_set(SHARK_UART0_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART0_tx_pin);
  212. gpio_af_set(SHARK_UART0_rx_port, GPIO_AF_0,SHARK_UART0_rx_pin);
  213. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_rx_pin);
  214. gpio_output_options_set(SHARK_UART0_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
  215. }else {
  216. rcu_periph_clock_enable(SHARK_UART1_clk);
  217. rcu_periph_clock_enable(SHARK_UART1_rx_gpio_clk);
  218. rcu_periph_clock_enable(SHARK_UART1_tx_gpio_clk);
  219. gpio_af_set(SHARK_UART1_tx_port, GPIO_AF_1,SHARK_UART1_tx_pin);
  220. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_tx_pin);
  221. gpio_output_options_set(SHARK_UART1_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART1_tx_pin);
  222. gpio_af_set(SHARK_UART1_rx_port, GPIO_AF_1,SHARK_UART1_rx_pin);
  223. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_rx_pin);
  224. gpio_output_options_set(SHARK_UART1_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART1_rx_pin);
  225. }
  226. }
  227. static void shark_uart_pin_deinit(shark_uart_t *uart){
  228. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  229. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, SHARK_UART0_tx_pin);
  230. gpio_bit_set(SHARK_UART0_tx_port, SHARK_UART0_tx_pin);
  231. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SHARK_UART0_rx_pin);
  232. }else {
  233. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, SHARK_UART1_tx_pin);
  234. gpio_bit_set(SHARK_UART1_tx_port, SHARK_UART1_tx_pin);
  235. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SHARK_UART1_rx_pin);
  236. }
  237. }
  238. static void shark_uart_device_init(shark_uart_t *uart){
  239. usart_deinit(uart->uart_com);
  240. usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
  241. usart_word_length_set(uart->uart_com, USART_WL_8BIT);
  242. usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
  243. usart_parity_config(uart->uart_com, USART_PM_NONE);
  244. usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
  245. usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
  246. usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
  247. usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
  248. }
  249. static u32 shark_uart_handler(void)
  250. {
  251. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  252. if (uart->uart_com != 0) {
  253. shark_uart_rx(uart);
  254. shark_uart_dma_tx(uart);
  255. }
  256. uart = _shark_uart + SHARK_UART1;
  257. if (uart->uart_com != 0) {
  258. shark_uart_rx(uart);
  259. shark_uart_dma_tx(uart);
  260. }
  261. return 0;
  262. }
  263. void shark_uart_flush(void){
  264. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  265. if (uart->uart_com != 0) {
  266. shark_uart_dma_tx(uart);
  267. }
  268. uart = _shark_uart + SHARK_UART1;
  269. if (uart->uart_com != 0) {
  270. shark_uart_dma_tx(uart);
  271. }
  272. }
  273. #if 0
  274. void DMA_Channel1_2_IRQHandler(void){
  275. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  276. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  277. shark_uart_dma_tx(uart);
  278. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  279. }
  280. }
  281. void DMA_Channel3_4_IRQHandler(void){
  282. shark_uart_t *uart = _shark_uart + SHARK_UART1;
  283. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  284. shark_uart_dma_tx(uart);
  285. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  286. }
  287. }
  288. #endif
  289. static u8 *tx_cache_addr(uart_enum_t uart_no){
  290. return (uart_no == SHARK_UART0)?shark_uart0_tx_cache:shark_uart1_tx_cache;
  291. }
  292. void shark_uart_deinit(uart_enum_t uart_no){
  293. shark_uart_t *uart = _shark_uart + uart_no;
  294. if (uart->uart_com != 0) {
  295. usart_disable(uart->uart_com);
  296. usart_deinit(uart->uart_com);
  297. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_clk:SHARK_UART1_clk);
  298. dma_channel_disable(uart->rx_dma_ch);
  299. dma_channel_disable(uart->tx_dma_ch);
  300. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  301. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  302. shark_uart_pin_deinit(uart);
  303. }
  304. if (uart_no == SHARK_UART0) {
  305. UART0_IR_EN(0);
  306. }else {
  307. UART1_IR_EN(0);
  308. }
  309. }
  310. bool shark_uart_timeout(void){
  311. return (_shark_uart[0].uart_no_data && _shark_uart[1].uart_no_data)?TRUE:FALSE;
  312. }
  313. void shark_uart_init(uart_enum_t uart_no)
  314. {
  315. shark_uart_t *uart = _shark_uart + uart_no;
  316. uart->escape = false;
  317. uart->rx_length = 0;
  318. uart->tx_length = 0;
  319. uart->uart_com = (uart_no == SHARK_UART0)?SHARK_UART0_com:SHARK_UART1_com;
  320. circle_buffer_init(&uart->rx_queue, shark_uart_rx_cache, SHARK_UART_TX_MEM_SIZE);
  321. byte_queue_init(&uart->tx_queue,tx_cache_addr(uart_no), SHARK_UART_TX_MEM_SIZE);
  322. uart->rx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_rx_dma_ch:SHARK_UART1_rx_dma_ch;
  323. uart->tx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_tx_dma_ch:SHARK_UART1_tx_dma_ch;
  324. shark_uart_pin_init(uart);
  325. shark_uart_device_init(uart);
  326. shark_uart_rx_dma_init(uart);
  327. shark_uart_tx_dma_init(uart);
  328. usart_enable(uart->uart_com);
  329. if (_uart_task.handler == NULL) {
  330. _uart_task.handler = shark_uart_handler;
  331. shark_task_add(&_uart_task);
  332. }
  333. if (uart_no == SHARK_UART0) {
  334. UART0_IR_EN(1);
  335. }else {
  336. UART1_IR_EN(1);
  337. }
  338. _rx_time = shark_get_mseconds();
  339. uart->uart_no_data = false;
  340. }
  341. static void shark_uart_write_byte_esc(shark_uart_t *uart, u8 value)
  342. {
  343. switch (value) {
  344. case CH_START:
  345. shark_uart_write_byte(uart, CH_ESC);
  346. value = CH_ESC_START;
  347. break;
  348. case CH_END:
  349. shark_uart_write_byte(uart, CH_ESC);
  350. value = CH_ESC_END;
  351. break;
  352. case CH_ESC:
  353. shark_uart_write_byte(uart, CH_ESC);
  354. value = CH_ESC_ESC;
  355. break;
  356. }
  357. shark_uart_write_byte(uart, value);
  358. }
  359. static void shark_uart_write_esc(shark_uart_t *uart, const u8 *buff, u16 length)
  360. {
  361. const u8 *buff_end;
  362. for (buff_end = buff + length; buff < buff_end; buff++) {
  363. shark_uart_write_byte_esc(uart, *buff);
  364. }
  365. }
  366. static void shark_uart_tx_start(shark_uart_t *uart)
  367. {
  368. shark_uart_write_byte(uart, CH_START);
  369. uart->tx_crc16 = 0;
  370. }
  371. static void shark_uart_tx_continue(shark_uart_t *uart, const void *buff, u16 length)
  372. {
  373. shark_uart_write_esc(uart, (const u8 *) buff, length);
  374. uart->tx_crc16 = shark_crc16_update(uart->tx_crc16, (const u8 *) buff, length);
  375. }
  376. static void shark_uart_tx_end(shark_uart_t *uart)
  377. {
  378. shark_uart_write_esc(uart, (u8 *)&uart->tx_crc16, sizeof(uart->tx_crc16));
  379. shark_uart_write_byte(uart, CH_END);
  380. }
  381. void shark_uart_write_frame(uart_enum_t uart_no, uint8_t *bytes, int len){
  382. shark_uart_t *uart = _shark_uart + uart_no;
  383. shark_uart_tx_start(uart);
  384. shark_uart_tx_continue(uart, bytes, len);
  385. shark_uart_tx_end(uart);
  386. }
  387. void shark_uart_frame_start(uart_enum_t uart_no, uint8_t *bytes, int len){
  388. shark_uart_t *uart = _shark_uart + uart_no;
  389. shark_uart_tx_start(uart);
  390. shark_uart_tx_continue(uart, bytes, len);
  391. }
  392. void shark_uart_frame_continue(uart_enum_t uart_no, uint8_t *bytes, int len){
  393. shark_uart_t *uart = _shark_uart + uart_no;
  394. shark_uart_tx_continue(uart, bytes, len);
  395. }
  396. void shark_uart_frame_end(uart_enum_t uart_no){
  397. shark_uart_tx_end(_shark_uart + uart_no);
  398. }
  399. void shark_uart_write_bytes(uart_enum_t uart_no, u8 *buff, u16 size){
  400. shark_uart_write(_shark_uart + uart_no, buff, size);
  401. }