bsp.c 2.3 KB

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  1. #include "bsp/shark_bsp.h"
  2. #include "bsp/gpio.h"
  3. #include "bsp/uart.h"
  4. #include "bsp/AT24CXX.h"
  5. #include "bsp/shark_rtc.h"
  6. #include "bsp/clock.h"
  7. #include "bsp/fmc_flash.h"
  8. #include "libs/logger.h"
  9. #include "version.h"
  10. #include <string.h>
  11. #if defined CONFIG_BOARD_SP700
  12. const char iap_board_name[] __attribute__((at(0x08002800))) = "SP700";
  13. #elif defined CONFIG_BOARD_SP600
  14. const char iap_board_name[] __attribute__((at(0x08002800))) = "SP600";
  15. #endif
  16. const char iap_fw_version[] __attribute__((at(0x08002A00))) = CONFIG_VERSION;
  17. const char iap_fw_name[] __attribute__((at(0x08002C00))) = "App";
  18. #define CONFIG_DEBUG 1
  19. extern void system_clock_config(void);
  20. extern void SystemCoreClockUpdate(void);
  21. #define ALARM_TEST 1
  22. #if 0
  23. void test_fmc_flash(void){
  24. uint8_t data[128];
  25. fmc_erase_image(50 * 1024);
  26. fmc_start_read_image();
  27. for(int i = 0; i < sizeof(data); i++){
  28. data[i] = i;
  29. }
  30. int count = 50;
  31. while(count-- >= 0) {
  32. for(int i = 0; i < sizeof(data); i++){
  33. data[i] = i;
  34. }
  35. fmc_write_image(data, sizeof(data));
  36. memset(data, 0, sizeof(data));
  37. fmc_read_image(data, sizeof(data));
  38. for(int i = 0; i < sizeof(data); i++){
  39. if (data[i] != (uint8_t)i){
  40. sys_debug("");
  41. }
  42. }
  43. }
  44. }
  45. #endif
  46. //all board's low level init is here
  47. void bsp_init(void){
  48. wdog_start(4);
  49. shark_rtc_init();
  50. enable_mcu_power();
  51. delay_us(100);
  52. system_clock_config(); //after dcdc open, MCU can run on full speed
  53. SystemCoreClockUpdate();
  54. gpio_init();
  55. shark_uart_init(SHARK_UART0);
  56. shark_uart_init(SHARK_UART1);
  57. AT24CXX_Init();
  58. }
  59. char* bsp_get_fversion(void){
  60. return (char *)iap_fw_version;
  61. }
  62. /* timeout:1-25 */
  63. void wdog_start(int timeout){
  64. #if CONFIG_DEBUG == 0
  65. /* enable IRC40K */
  66. rcu_osci_on(RCU_IRC40K);
  67. /* wait till IRC40K is ready */
  68. while(SUCCESS != rcu_osci_stab_wait(RCU_IRC40K)){
  69. }
  70. /* confiure FWDGT counter clock: 40KHz(IRC40K) / 256 = 0.15625 KHz */
  71. fwdgt_config(timeout*40000UL/256, FWDGT_PSC_DIV256);
  72. /* after 4 seconds to generate a reset */
  73. fwdgt_enable();
  74. #endif
  75. }
  76. void wdog_reload(void){
  77. #if CONFIG_DEBUG == 0
  78. fwdgt_counter_reload();
  79. #endif
  80. }
  81. void wdog_set_timeout(int timeout)
  82. {
  83. #if CONFIG_DEBUG == 0
  84. /* enable write access to FWDGT_PSC,and FWDGT_RLD */
  85. FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
  86. FWDGT_RLD = RLD_RLD(timeout*40000UL/256);
  87. /* reload the counter */
  88. FWDGT_CTL = FWDGT_KEY_RELOAD;
  89. #endif
  90. }