uart.c 15 KB

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  1. #include "uart.h"
  2. #include "bsp/shark_bsp.h"
  3. #include "bsp/gpio.h"
  4. #include "libs/shark_libs.h"
  5. #define SHARK_UART_BAUDRATE 38400
  6. #define SHARK_UART0_com USART0
  7. #define SHARK_UART0_tx_port GPIOB
  8. #define SHARK_UART0_tx_pin GPIO_PIN_6
  9. #define SHARK_UART0_rx_port GPIOB
  10. #define SHARK_UART0_rx_pin GPIO_PIN_7
  11. #define SHARK_UART0_irq USART0_IRQn
  12. #define SHARK_UART0_clk RCU_USART0
  13. #define SHARK_UART0_tx_gpio_clk RCU_GPIOB
  14. #define SHARK_UART0_rx_gpio_clk RCU_GPIOB
  15. #define SHARK_UART0_tx_dma DMA
  16. #define SHARK_UART0_tx_dma_ch DMA_CH1
  17. #define SHARK_UART0_tx_dma_clk RCU_DMA
  18. #define SHARK_UART0_rx_dma DMA
  19. #define SHARK_UART0_rx_dma_ch DMA_CH2
  20. #define SHARK_UART0_rx_dma_clk RCU_DMA
  21. #define SHARK_UART1_com USART1
  22. #define SHARK_UART1_tx_port GPIOA
  23. #define SHARK_UART1_tx_pin GPIO_PIN_2
  24. #define SHARK_UART1_rx_port GPIOA
  25. #define SHARK_UART1_rx_pin GPIO_PIN_3
  26. #define SHARK_UART1_irq USART1_IRQn
  27. #define SHARK_UART1_clk RCU_USART1
  28. #define SHARK_UART1_tx_gpio_clk RCU_GPIOA
  29. #define SHARK_UART1_rx_gpio_clk RCU_GPIOA
  30. #define SHARK_UART1_tx_dma DMA
  31. #define SHARK_UART1_tx_dma_ch DMA_CH3
  32. #define SHARK_UART1_tx_dma_clk RCU_DMA
  33. #define SHARK_UART1_rx_dma DMA
  34. #define SHARK_UART1_rx_dma_ch DMA_CH4
  35. #define SHARK_UART1_rx_dma_clk RCU_DMA
  36. // ================================================================================
  37. static u8 shark_uart0_tx_cache[SHARK_UART_TX_MEM_SIZE];
  38. #if UART_NUM==2
  39. static u8 shark_uart1_tx_cache[SHARK_UART_TX_MEM_SIZE];
  40. #endif
  41. static u8 shark_uart_rx_cache[SHARK_UART_RX_MEM_SIZE];
  42. static shark_uart_t _shark_uart[UART_NUM];
  43. static shark_task_t _uart_task;
  44. static u64 _rx_time;
  45. ///static bool uart_no_data = false;
  46. #define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(uart->rx_dma_ch))
  47. extern void protocol_recv_frame(uart_enum_t uart_no, char *data, int len);
  48. extern void protocol_old_recv_frame(uart_enum_t uart_no, uint8_t *data, int len);
  49. // ================================================================================
  50. static uart_enum_t _uart_index(uint32_t com){
  51. return com == SHARK_UART0_com?SHARK_UART0:SHARK_UART1;
  52. }
  53. static bool shark_uart_on_rx_frame(shark_uart_t *uart)
  54. {
  55. u16 crc0 = shark_decode_u16(uart->rx_frame + uart->rx_length);
  56. u16 crc1 = shark_crc16_check(uart->rx_frame, uart->rx_length);
  57. if (crc0 != crc1) {
  58. return false;
  59. }
  60. protocol_recv_frame(_uart_index(uart->uart_com), (char *)uart->rx_frame, uart->rx_length);
  61. return true;
  62. }
  63. static void shark_uart_rx(shark_uart_t *uart){
  64. while(1) {
  65. u8 data;
  66. update_dma_w_pos(uart);
  67. if (circle_get_one_data(&uart->rx_queue, &data) != 1) {
  68. if (shark_get_mseconds() >= (30 + _rx_time)) {
  69. //_rx_time = 0xFFFFFFFFFFFFL;
  70. if (uart->rx_length_old_prot > 0){
  71. protocol_old_recv_frame(_uart_index(uart->uart_com), uart->rx_frame_old_prot, uart->rx_length_old_prot);
  72. uart->rx_length_old_prot = 0;
  73. }
  74. }
  75. if (shark_get_mseconds() >= (UART_TIMEOUT + _rx_time)){
  76. uart->uart_no_data = true;
  77. }else {
  78. uart->uart_no_data = false;
  79. }
  80. break;
  81. }
  82. _rx_time = shark_get_mseconds();
  83. uart->rx_frame_old_prot[uart->rx_length_old_prot ++] = data;
  84. if (uart->rx_length_old_prot == sizeof(uart->rx_frame_old_prot)){
  85. uart->rx_length_old_prot = 0;
  86. }
  87. switch(data){
  88. case CH_START:
  89. uart->rx_length = 0;
  90. uart->escape = false;
  91. break;
  92. case CH_END:
  93. if (uart->rx_length > 2 && uart->rx_length != 0xFFFF){
  94. uart->rx_length -= 2; //skip crc
  95. shark_uart_on_rx_frame(uart);
  96. }
  97. uart->rx_length = 0xFFFF;
  98. break;
  99. case CH_ESC:
  100. uart->escape = true;
  101. break;
  102. default:
  103. if (uart->escape) {
  104. uart->escape = false;
  105. switch (data) {
  106. case CH_ESC_START:
  107. data = CH_START;
  108. break;
  109. case CH_ESC_END:
  110. data = CH_END;
  111. break;
  112. case CH_ESC_ESC:
  113. data = CH_ESC;
  114. break;
  115. default:
  116. data = 0xFF;
  117. }
  118. }
  119. if (uart->rx_length < sizeof(uart->rx_frame)) {
  120. uart->rx_frame[uart->rx_length] = data;
  121. uart->rx_length++;
  122. } else {
  123. uart->rx_length = 0xFFFF;
  124. }
  125. }
  126. }
  127. }
  128. static void shark_uart_dma_tx(shark_uart_t *uart)
  129. {
  130. u32 value = DMA_CHCTL(uart->tx_dma_ch);
  131. if (value & DMA_CHXCTL_CHEN) {
  132. if (SET != dma_flag_get(uart->tx_dma_ch, DMA_FLAG_FTF)) {
  133. return;
  134. }
  135. byte_queue_skip(&uart->tx_queue, uart->tx_length);
  136. DMA_CHCTL(uart->tx_dma_ch) = value & (~DMA_CHXCTL_CHEN);
  137. }
  138. uart->tx_length = byte_queue_peek(&uart->tx_queue);
  139. if (uart->tx_length > 0) {
  140. DMA_CHCNT(uart->tx_dma_ch) = uart->tx_length;
  141. DMA_CHMADDR(uart->tx_dma_ch) = (u32) byte_queue_head(&uart->tx_queue);
  142. dma_flag_clear(uart->tx_dma_ch, DMA_FLAG_FTF);
  143. DMA_CHCTL(uart->tx_dma_ch) = value | DMA_CHXCTL_CHEN;
  144. }
  145. }
  146. static void shark_uart_write(shark_uart_t *uart, const u8 *buff, u16 size)
  147. {
  148. while (size > 0) {
  149. u16 length = byte_queue_write(&uart->tx_queue, buff, size);
  150. if (length == size) {
  151. shark_uart_dma_tx(uart);
  152. break;
  153. }
  154. shark_uart_dma_tx(uart);
  155. buff += length;
  156. size -= length;
  157. }
  158. }
  159. static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
  160. {
  161. shark_uart_write(uart, &value, 1);
  162. }
  163. static void shark_uart_tx_dma_init(shark_uart_t *uart){
  164. dma_parameter_struct dma_init_struct;
  165. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  166. dma_deinit(uart->tx_dma_ch);
  167. dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
  168. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  169. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  170. dma_init_struct.periph_addr = (u32) &USART_TDATA(uart->uart_com);
  171. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  172. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  173. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  174. dma_init(uart->tx_dma_ch, &dma_init_struct);
  175. dma_circulation_disable(uart->tx_dma_ch);
  176. dma_memory_to_memory_disable(uart->tx_dma_ch);
  177. usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
  178. #if 0
  179. if (uart->tx_dma_ch == DMA_CH1) {
  180. nvic_irq_enable(DMA_Channel1_2_IRQn ,4, 0);
  181. }else {
  182. nvic_irq_enable(DMA_Channel3_4_IRQn ,4, 0);
  183. }
  184. dma_interrupt_enable(uart->tx_dma_ch, DMA_INT_FTF);
  185. #endif
  186. }
  187. static void shark_uart_rx_dma_init(shark_uart_t *uart){
  188. dma_parameter_struct dma_init_struct;
  189. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  190. dma_deinit(uart->rx_dma_ch);
  191. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  192. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  193. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  194. dma_init_struct.memory_addr = (u32)uart->rx_queue.buffer;
  195. dma_init_struct.number = uart->rx_queue.buffer_len;
  196. dma_init_struct.periph_addr = (u32) &USART_RDATA(uart->uart_com);
  197. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  198. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  199. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  200. dma_init(uart->rx_dma_ch, &dma_init_struct);
  201. dma_circulation_enable(uart->rx_dma_ch);
  202. dma_memory_to_memory_disable(uart->rx_dma_ch);
  203. dma_channel_enable(uart->rx_dma_ch);
  204. usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
  205. }
  206. static void shark_uart_pin_init(shark_uart_t *uart){
  207. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  208. rcu_periph_clock_enable(SHARK_UART0_clk);
  209. rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
  210. rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
  211. gpio_af_set(SHARK_UART0_tx_port, GPIO_AF_0,SHARK_UART0_tx_pin);
  212. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_tx_pin);
  213. gpio_output_options_set(SHARK_UART0_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART0_tx_pin);
  214. gpio_af_set(SHARK_UART0_rx_port, GPIO_AF_0,SHARK_UART0_rx_pin);
  215. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_rx_pin);
  216. gpio_output_options_set(SHARK_UART0_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
  217. }else {
  218. rcu_periph_clock_enable(SHARK_UART1_clk);
  219. rcu_periph_clock_enable(SHARK_UART1_rx_gpio_clk);
  220. rcu_periph_clock_enable(SHARK_UART1_tx_gpio_clk);
  221. gpio_af_set(SHARK_UART1_tx_port, GPIO_AF_1,SHARK_UART1_tx_pin);
  222. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_tx_pin);
  223. gpio_output_options_set(SHARK_UART1_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART1_tx_pin);
  224. gpio_af_set(SHARK_UART1_rx_port, GPIO_AF_1,SHARK_UART1_rx_pin);
  225. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_rx_pin);
  226. gpio_output_options_set(SHARK_UART1_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART1_rx_pin);
  227. }
  228. }
  229. static void shark_uart_pin_deinit(shark_uart_t *uart){
  230. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  231. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, SHARK_UART0_tx_pin);
  232. gpio_bit_set(SHARK_UART0_tx_port, SHARK_UART0_tx_pin);
  233. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SHARK_UART0_rx_pin);
  234. }else {
  235. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, SHARK_UART1_tx_pin);
  236. gpio_bit_set(SHARK_UART1_tx_port, SHARK_UART1_tx_pin);
  237. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SHARK_UART1_rx_pin);
  238. }
  239. }
  240. static void shark_uart_device_init(shark_uart_t *uart){
  241. usart_deinit(uart->uart_com);
  242. usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
  243. usart_word_length_set(uart->uart_com, USART_WL_8BIT);
  244. usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
  245. usart_parity_config(uart->uart_com, USART_PM_NONE);
  246. usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
  247. usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
  248. usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
  249. usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
  250. }
  251. static u32 shark_uart_handler(void)
  252. {
  253. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  254. if (uart->uart_com != 0) {
  255. shark_uart_rx(uart);
  256. shark_uart_dma_tx(uart);
  257. }
  258. #if UART_NUM==2
  259. uart = _shark_uart + SHARK_UART1;
  260. if (uart->uart_com != 0) {
  261. shark_uart_rx(uart);
  262. shark_uart_dma_tx(uart);
  263. }
  264. #endif
  265. return 0;
  266. }
  267. void shark_uart_flush(void){
  268. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  269. if (uart->uart_com != 0) {
  270. shark_uart_dma_tx(uart);
  271. }
  272. #if UART_NUM==2
  273. uart = _shark_uart + SHARK_UART1;
  274. if (uart->uart_com != 0) {
  275. shark_uart_dma_tx(uart);
  276. }
  277. #endif
  278. }
  279. #if 0
  280. void DMA_Channel1_2_IRQHandler(void){
  281. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  282. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  283. shark_uart_dma_tx(uart);
  284. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  285. }
  286. }
  287. void DMA_Channel3_4_IRQHandler(void){
  288. shark_uart_t *uart = _shark_uart + SHARK_UART1;
  289. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  290. shark_uart_dma_tx(uart);
  291. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  292. }
  293. }
  294. #endif
  295. static u8 *tx_cache_addr(uart_enum_t uart_no){
  296. #if UART_NUM==2
  297. return (uart_no == SHARK_UART0)?shark_uart0_tx_cache:shark_uart1_tx_cache;
  298. #else
  299. return shark_uart0_tx_cache;
  300. #endif
  301. }
  302. void shark_uart_deinit(uart_enum_t uart_no){
  303. shark_uart_t *uart = _shark_uart + uart_no;
  304. if (uart->uart_com != 0) {
  305. usart_disable(uart->uart_com);
  306. usart_deinit(uart->uart_com);
  307. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_clk:SHARK_UART1_clk);
  308. dma_channel_disable(uart->rx_dma_ch);
  309. dma_channel_disable(uart->tx_dma_ch);
  310. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  311. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  312. shark_uart_pin_deinit(uart);
  313. }
  314. if (uart_no == SHARK_UART0) {
  315. UART0_IR_EN(0);
  316. }else {
  317. UART1_IR_EN(0);
  318. }
  319. }
  320. bool shark_uart_timeout(void){
  321. #if UART_NUM==2
  322. return (_shark_uart[0].uart_no_data && _shark_uart[1].uart_no_data)?TRUE:FALSE;
  323. #else
  324. return (_shark_uart[0].uart_no_data)?TRUE:FALSE;
  325. #endif
  326. }
  327. void shark_uart_init(uart_enum_t uart_no)
  328. {
  329. shark_uart_t *uart = _shark_uart + uart_no;
  330. uart->escape = false;
  331. uart->rx_length = 0;
  332. uart->tx_length = 0;
  333. uart->uart_com = (uart_no == SHARK_UART0)?SHARK_UART0_com:SHARK_UART1_com;
  334. circle_buffer_init(&uart->rx_queue, shark_uart_rx_cache, SHARK_UART_TX_MEM_SIZE);
  335. byte_queue_init(&uart->tx_queue,tx_cache_addr(uart_no), SHARK_UART_TX_MEM_SIZE);
  336. uart->rx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_rx_dma_ch:SHARK_UART1_rx_dma_ch;
  337. uart->tx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_tx_dma_ch:SHARK_UART1_tx_dma_ch;
  338. shark_uart_pin_init(uart);
  339. shark_uart_device_init(uart);
  340. shark_uart_rx_dma_init(uart);
  341. shark_uart_tx_dma_init(uart);
  342. usart_enable(uart->uart_com);
  343. if (_uart_task.handler == NULL) {
  344. _uart_task.handler = shark_uart_handler;
  345. shark_task_add(&_uart_task);
  346. }
  347. if (uart_no == SHARK_UART0) {
  348. UART0_IR_EN(1);
  349. }else {
  350. UART1_IR_EN(1);
  351. }
  352. _rx_time = shark_get_mseconds();
  353. uart->uart_no_data = false;
  354. }
  355. static void shark_uart_write_byte_esc(shark_uart_t *uart, u8 value)
  356. {
  357. switch (value) {
  358. case CH_START:
  359. shark_uart_write_byte(uart, CH_ESC);
  360. value = CH_ESC_START;
  361. break;
  362. case CH_END:
  363. shark_uart_write_byte(uart, CH_ESC);
  364. value = CH_ESC_END;
  365. break;
  366. case CH_ESC:
  367. shark_uart_write_byte(uart, CH_ESC);
  368. value = CH_ESC_ESC;
  369. break;
  370. }
  371. shark_uart_write_byte(uart, value);
  372. }
  373. static void shark_uart_write_esc(shark_uart_t *uart, const u8 *buff, u16 length)
  374. {
  375. const u8 *buff_end;
  376. for (buff_end = buff + length; buff < buff_end; buff++) {
  377. shark_uart_write_byte_esc(uart, *buff);
  378. }
  379. }
  380. static void shark_uart_tx_start(shark_uart_t *uart)
  381. {
  382. shark_uart_write_byte(uart, CH_START);
  383. uart->tx_crc16 = 0;
  384. }
  385. static void shark_uart_tx_continue(shark_uart_t *uart, const void *buff, u16 length)
  386. {
  387. shark_uart_write_esc(uart, (const u8 *) buff, length);
  388. uart->tx_crc16 = shark_crc16_update(uart->tx_crc16, (const u8 *) buff, length);
  389. }
  390. static void shark_uart_tx_end(shark_uart_t *uart)
  391. {
  392. shark_uart_write_esc(uart, (u8 *)&uart->tx_crc16, sizeof(uart->tx_crc16));
  393. shark_uart_write_byte(uart, CH_END);
  394. }
  395. void shark_uart_write_frame(uart_enum_t uart_no, uint8_t *bytes, int len){
  396. shark_uart_t *uart = _shark_uart + uart_no;
  397. shark_uart_tx_start(uart);
  398. shark_uart_tx_continue(uart, bytes, len);
  399. shark_uart_tx_end(uart);
  400. }
  401. void shark_uart_frame_start(uart_enum_t uart_no, uint8_t *bytes, int len){
  402. shark_uart_t *uart = _shark_uart + uart_no;
  403. shark_uart_tx_start(uart);
  404. shark_uart_tx_continue(uart, bytes, len);
  405. }
  406. void shark_uart_frame_continue(uart_enum_t uart_no, uint8_t *bytes, int len){
  407. shark_uart_t *uart = _shark_uart + uart_no;
  408. shark_uart_tx_continue(uart, bytes, len);
  409. }
  410. void shark_uart_frame_end(uart_enum_t uart_no){
  411. shark_uart_tx_end(_shark_uart + uart_no);
  412. }
  413. void shark_uart_write_bytes(uart_enum_t uart_no, u8 *buff, u16 size){
  414. shark_uart_write(_shark_uart + uart_no, buff, size);
  415. }