uart.c 11 KB

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  1. #include "uart.h"
  2. #include "bsp/shark_bsp.h"
  3. #include "bsp/gpio.h"
  4. #include "libs/shark_libs.h"
  5. #define SHARK_UART_BAUDRATE 38400
  6. #define SHARK_UART0_com USART0
  7. #define SHARK_UART0_tx_port GPIOA
  8. #define SHARK_UART0_tx_pin GPIO_PIN_9
  9. #define SHARK_UART0_rx_port GPIOA
  10. #define SHARK_UART0_rx_pin GPIO_PIN_10
  11. #define SHARK_UART0_irq USART0_IRQn
  12. #define SHARK_UART0_clk RCU_USART0
  13. #define SHARK_UART0_tx_gpio_clk RCU_GPIOA
  14. #define SHARK_UART0_rx_gpio_clk RCU_GPIOA
  15. #define SHARK_UART0_tx_dma DMA
  16. #define SHARK_UART0_tx_dma_ch DMA_CH1
  17. #define SHARK_UART0_tx_dma_clk RCU_DMA
  18. #define SHARK_UART0_rx_dma DMA
  19. #define SHARK_UART0_rx_dma_ch DMA_CH2
  20. #define SHARK_UART0_rx_dma_clk RCU_DMA
  21. #define SHARK_UART1_com USART1
  22. #define SHARK_UART1_tx_port GPIOA
  23. #define SHARK_UART1_tx_pin GPIO_PIN_2
  24. #define SHARK_UART1_rx_port GPIOA
  25. #define SHARK_UART1_rx_pin GPIO_PIN_3
  26. #define SHARK_UART1_irq USART1_IRQn
  27. #define SHARK_UART1_clk RCU_USART1
  28. #define SHARK_UART1_tx_gpio_clk RCU_GPIOA
  29. #define SHARK_UART1_rx_gpio_clk RCU_GPIOA
  30. #define SHARK_UART1_tx_dma DMA
  31. #define SHARK_UART1_tx_dma_ch DMA_CH3
  32. #define SHARK_UART1_tx_dma_clk RCU_DMA
  33. #define SHARK_UART1_rx_dma DMA
  34. #define SHARK_UART1_rx_dma_ch DMA_CH4
  35. #define SHARK_UART1_rx_dma_clk RCU_DMA
  36. // ================================================================================
  37. static u8 shark_uart0_tx_cache[SHARK_UART_TX_MEM_SIZE];
  38. static u8 shark_uart1_tx_cache[SHARK_UART_TX_MEM_SIZE];
  39. static u8 shark_uart_rx_cache[SHARK_UART_RX_MEM_SIZE];
  40. static shark_uart_t _shark_uart[SHARK_UART_COUNT];
  41. static shark_task_t _uart_task;
  42. static bool new_prococol = false;
  43. static u64 _rx_time;
  44. #define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(uart->rx_dma_ch))
  45. extern void protocol_recv_frame(uart_enum_t uart_no, char *data, int len);
  46. // ================================================================================
  47. static uart_enum_t _uart_index(uint32_t com){
  48. return com == SHARK_UART0_com?SHARK_UART0:SHARK_UART1;
  49. }
  50. static bool shark_uart_on_rx_frame(shark_uart_t *uart)
  51. {
  52. u16 crc0 = shark_decode_u16(uart->rx_frame + uart->rx_length);
  53. u16 crc1 = shark_crc16_check(uart->rx_frame, uart->rx_length);
  54. if (crc0 != crc1) {
  55. return false;
  56. }
  57. new_prococol = true;
  58. protocol_recv_frame(_uart_index(uart->uart_com), (char *)uart->rx_frame, uart->rx_length);
  59. return true;
  60. }
  61. static void shark_uart_rx(shark_uart_t *uart){
  62. while(1) {
  63. u8 data;
  64. update_dma_w_pos(uart);
  65. if (circle_get_one_data(&uart->rx_queue, (char *)&data) != 1) {
  66. if (!new_prococol){//通过老协议发送过来的,需要回复一个信息,告知使用新协议,霍尔移除,通信超时需要reset new_protocol
  67. if (shark_get_mseconds() - _rx_time >= 30) {
  68. _rx_time = 0xFFFFFFFFFFFFL;
  69. protocol_recv_frame(_uart_index(uart->uart_com), NULL, 0);
  70. }
  71. }
  72. break;
  73. }
  74. _rx_time = shark_get_mseconds();
  75. switch(data){
  76. case CH_START:
  77. uart->rx_length = 0;
  78. uart->escape = false;
  79. break;
  80. case CH_END:
  81. if (uart->rx_length > 2 && uart->rx_length != 0xFF){
  82. shark_uart_on_rx_frame(uart);
  83. }
  84. uart->rx_length = 0xFF;
  85. break;
  86. case CH_ESC:
  87. uart->escape = true;
  88. break;
  89. default:
  90. if (uart->escape) {
  91. uart->escape = false;
  92. switch (data) {
  93. case CH_ESC_START:
  94. data = CH_START;
  95. break;
  96. case CH_ESC_END:
  97. data = CH_END;
  98. break;
  99. case CH_ESC_ESC:
  100. data = CH_ESC;
  101. break;
  102. default:
  103. data = 0xFF;
  104. }
  105. }
  106. if (uart->rx_length < sizeof(uart->rx_frame)) {
  107. uart->rx_frame[uart->rx_length] = data;
  108. uart->rx_length++;
  109. } else {
  110. uart->rx_length = 0xFF;
  111. }
  112. }
  113. }
  114. }
  115. static void shark_uart_dma_tx(shark_uart_t *uart)
  116. {
  117. u32 value = DMA_CHCTL(uart->tx_dma_ch);
  118. if (value & DMA_CHXCTL_CHEN) {
  119. if (SET != dma_flag_get(uart->tx_dma_ch, DMA_FLAG_FTF)) {
  120. return;
  121. }
  122. byte_queue_skip(&uart->tx_queue, uart->tx_length);
  123. DMA_CHCTL(uart->tx_dma_ch) = value & (~DMA_CHXCTL_CHEN);
  124. }
  125. uart->tx_length = byte_queue_peek(&uart->tx_queue);
  126. if (uart->tx_length > 0) {
  127. DMA_CHCNT(uart->tx_dma_ch) = uart->tx_length;
  128. DMA_CHMADDR(uart->tx_dma_ch) = (u32) byte_queue_head(&uart->tx_queue);
  129. dma_flag_clear(uart->tx_dma_ch, DMA_FLAG_FTF);
  130. DMA_CHCTL(uart->tx_dma_ch) = value | DMA_CHXCTL_CHEN;
  131. }
  132. }
  133. static void shark_uart_write(shark_uart_t *uart, const u8 *buff, u16 size)
  134. {
  135. while (size > 0) {
  136. u16 length = byte_queue_write(&uart->tx_queue, buff, size);
  137. if (length == size) {
  138. break;
  139. }
  140. shark_uart_dma_tx(uart);
  141. buff += length;
  142. size -= length;
  143. }
  144. }
  145. static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
  146. {
  147. shark_uart_write(uart, &value, 1);
  148. }
  149. void shark_uart_dma_init(dma_channel_enum channelx, u8 direction, u32 periph_addr, void *memory_addr, u16 length)
  150. {
  151. u32 ctl;
  152. DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
  153. /* configure peripheral base address */
  154. DMA_CHPADDR(channelx) = periph_addr;
  155. /* configure memory base address */
  156. DMA_CHMADDR(channelx) = (u32) memory_addr;
  157. /* configure the number of remaining data to be transferred */
  158. DMA_CHCNT(channelx) = length;
  159. /* configure peripheral transfer width,memory transfer width and priority */
  160. ctl = DMA_CHCTL(channelx);
  161. ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
  162. ctl |= (DMA_PERIPHERAL_WIDTH_8BIT | DMA_MEMORY_WIDTH_8BIT | DMA_PRIORITY_ULTRA_HIGH);
  163. DMA_CHCTL(channelx) = ctl;
  164. /* configure peripheral increasing mode */
  165. DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
  166. /* configure memory increasing mode */
  167. DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
  168. /* configure the direction of data transfer */
  169. if (DMA_PERIPHERAL_TO_MEMORY == direction) {
  170. DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
  171. } else {
  172. DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
  173. }
  174. }
  175. static u32 shark_uart_handler(void)
  176. {
  177. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  178. if (uart->uart_com != 0) {
  179. shark_uart_rx(uart);
  180. shark_uart_dma_tx(uart);
  181. }
  182. uart = _shark_uart + SHARK_UART1;
  183. if (uart->uart_com != 0) {
  184. shark_uart_rx(uart);
  185. shark_uart_dma_tx(uart);
  186. }
  187. return 0;
  188. }
  189. static u8 *tx_cache_addr(uart_enum_t uart_no){
  190. return (uart_no == SHARK_UART0)?shark_uart0_tx_cache:shark_uart1_tx_cache;
  191. }
  192. void shark_uart_deinit(uart_enum_t uart_no){
  193. shark_uart_t *uart = _shark_uart + uart_no;
  194. if (uart->uart_com != 0) {
  195. usart_deinit(uart->uart_com);
  196. rcu_periph_clock_enable(uart_no == SHARK_UART0?SHARK_UART0_clk:SHARK_UART1_clk);
  197. dma_channel_disable(uart->rx_dma_ch);
  198. dma_channel_disable(uart->tx_dma_ch);
  199. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  200. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  201. }
  202. if (uart_no == SHARK_UART0) {
  203. UART0_IR_EN(0);
  204. }else {
  205. UART1_IR_EN(0);
  206. }
  207. }
  208. void shark_uart_init(uart_enum_t uart_no)
  209. {
  210. shark_uart_t *uart = _shark_uart + uart_no;
  211. uart->escape = false;
  212. uart->rx_length = 0;
  213. uart->tx_length = 0;
  214. uart->uart_com = (uart_no == SHARK_UART0)?SHARK_UART0_com:SHARK_UART1_com;
  215. circle_buffer_init(&uart->rx_queue, (char *)shark_uart_rx_cache, SHARK_UART_TX_MEM_SIZE);
  216. byte_queue_init(&uart->tx_queue,tx_cache_addr(uart_no), SHARK_UART_TX_MEM_SIZE);
  217. uart->rx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_rx_dma_ch:SHARK_UART1_rx_dma_ch;
  218. uart->tx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_tx_dma_ch:SHARK_UART1_tx_dma_ch;
  219. if (uart_no == SHARK_UART0) {
  220. rcu_periph_clock_enable(SHARK_UART0_clk);
  221. rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
  222. rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
  223. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, SHARK_UART0_tx_pin);
  224. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, SHARK_UART0_rx_pin);
  225. }else {
  226. rcu_periph_clock_enable(SHARK_UART1_clk);
  227. rcu_periph_clock_enable(SHARK_UART1_rx_gpio_clk);
  228. rcu_periph_clock_enable(SHARK_UART1_tx_gpio_clk);
  229. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, SHARK_UART1_tx_pin);
  230. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, SHARK_UART1_rx_pin);
  231. }
  232. usart_deinit(uart->uart_com);
  233. usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
  234. usart_word_length_set(uart->uart_com, USART_WL_8BIT);
  235. usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
  236. usart_parity_config(uart->uart_com, USART_PM_NONE);
  237. usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
  238. usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
  239. usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
  240. usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
  241. rcu_periph_clock_enable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  242. shark_uart_dma_init(uart->tx_dma_ch, DMA_MEMORY_TO_PERIPHERAL, uart->uart_com + 0x04, tx_cache_addr(uart_no), 0);
  243. dma_circulation_disable(uart->tx_dma_ch);
  244. usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
  245. rcu_periph_clock_enable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  246. shark_uart_dma_init(uart->rx_dma_ch, DMA_PERIPHERAL_TO_MEMORY, uart->uart_com + 0x04, shark_uart_rx_cache, SHARK_UART_TX_MEM_SIZE);
  247. dma_circulation_enable(uart->rx_dma_ch);
  248. dma_channel_enable(uart->rx_dma_ch);
  249. usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
  250. usart_enable(uart->uart_com);
  251. if (_uart_task.handler == NULL) {
  252. _uart_task.handler = shark_uart_handler;
  253. shark_task_add(&_uart_task);
  254. }
  255. if (uart_no == SHARK_UART0) {
  256. UART0_IR_EN(1);
  257. }else {
  258. UART1_IR_EN(1);
  259. }
  260. _rx_time = 0xFFFFFFFFFFFFL;
  261. }
  262. static void shark_uart_write_byte_esc(shark_uart_t *uart, u8 value)
  263. {
  264. switch (value) {
  265. case CH_START:
  266. shark_uart_write_byte(uart, CH_ESC);
  267. value = CH_ESC_START;
  268. break;
  269. case CH_END:
  270. shark_uart_write_byte(uart, CH_ESC);
  271. value = CH_ESC_END;
  272. break;
  273. case CH_ESC:
  274. shark_uart_write_byte(uart, CH_ESC);
  275. value = CH_ESC_ESC;
  276. break;
  277. }
  278. shark_uart_write_byte(uart, value);
  279. }
  280. static void shark_uart_write_esc(shark_uart_t *uart, const u8 *buff, u16 length)
  281. {
  282. const u8 *buff_end;
  283. for (buff_end = buff + length; buff < buff_end; buff++) {
  284. shark_uart_write_byte_esc(uart, *buff);
  285. }
  286. }
  287. static void shark_uart_tx_start(shark_uart_t *uart)
  288. {
  289. shark_uart_write_byte(uart, CH_START);
  290. uart->tx_crc16 = 0;
  291. }
  292. static void shark_uart_tx_continue(shark_uart_t *uart, const void *buff, u16 length)
  293. {
  294. shark_uart_write_esc(uart, (const u8 *) buff, length);
  295. uart->tx_crc16 = shark_crc16_update(uart->tx_crc16, (const u8 *) buff, length);
  296. }
  297. static void shark_uart_tx_end(shark_uart_t *uart)
  298. {
  299. shark_uart_write_esc(uart, (u8 *)&uart->tx_crc16, sizeof(uart->tx_crc16));
  300. shark_uart_write_byte(uart, CH_END);
  301. }
  302. void shark_uart_write_frame(uart_enum_t uart_no, char *bytes, int len){
  303. shark_uart_t *uart = _shark_uart + uart_no;
  304. shark_uart_tx_start(uart);
  305. shark_uart_tx_continue(uart, bytes, len);
  306. shark_uart_tx_end(uart);
  307. }