shark_uart.c 24 KB

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  1. #include "s600_turn_key.h"
  2. #include "ws2818_spi.h"
  3. #include "s600_uart.h"
  4. #include "s600_can.h"
  5. #include "s600_pwm.h"
  6. #include "s600_adc.h"
  7. #include "s600_dac.h"
  8. #include "string.h"
  9. #include "stdlib.h"
  10. #define S600_UART0_com USART0
  11. #if CONFIG_UART_MAIN == 0
  12. #define S600_UART0_baudrate 500000
  13. #else
  14. #define S600_UART0_baudrate 115200
  15. #endif
  16. #define S600_UART0_tx_port GPIOA
  17. #define S600_UART0_tx_pin GPIO_PIN_9
  18. #define S600_UART0_rx_port GPIOA
  19. #define S600_UART0_rx_pin GPIO_PIN_10
  20. #define S600_UART0_irq USART0_IRQn
  21. #define S600_UART0_clk RCU_USART0
  22. #define S600_UART0_tx_gpio_clk RCU_GPIOA
  23. #define S600_UART0_rx_gpio_clk RCU_GPIOA
  24. #define S600_UART0_tx_dma DMA0
  25. #define S600_UART0_tx_dma_ch DMA_CH3
  26. #define S600_UART0_tx_dma_clk RCU_DMA0
  27. #define S600_UART0_rx_dma DMA0
  28. #define S600_UART0_rx_dma_ch DMA_CH4
  29. #define S600_UART0_rx_dma_clk RCU_DMA0
  30. #define S600_UART0_on_data_received s600_uart0_received
  31. #define S600_UART1_com USART1
  32. #if CONFIG_UART_MAIN == 1
  33. #define S600_UART1_baudrate 500000
  34. #else
  35. #define S600_UART1_baudrate 115200
  36. #endif
  37. #define S600_UART1_tx_port GPIOA
  38. #define S600_UART1_tx_pin GPIO_PIN_2
  39. #define S600_UART1_rx_port GPIOA
  40. #define S600_UART1_rx_pin GPIO_PIN_3
  41. #define S600_UART1_irq USART1_IRQn
  42. #define S600_UART1_clk RCU_USART1
  43. #define S600_UART1_tx_gpio_clk RCU_GPIOA
  44. #define S600_UART1_rx_gpio_clk RCU_GPIOA
  45. #define S600_UART1_tx_dma DMA0
  46. #define S600_UART1_tx_dma_ch DMA_CH6
  47. #define S600_UART1_tx_dma_clk RCU_DMA0
  48. #define S600_UART1_rx_dma DMA0
  49. #define S600_UART1_rx_dma_ch DMA_CH5
  50. #define S600_UART1_rx_dma_clk RCU_DMA0
  51. #define S600_UART1_on_data_received s600_uart1_received
  52. #define S600_UART2_com USART2
  53. #define S600_UART2_baudrate 115200
  54. #define S600_UART2_tx_port GPIOB
  55. #define S600_UART2_tx_pin GPIO_PIN_10
  56. #define S600_UART2_rx_port GPIOB
  57. #define S600_UART2_rx_pin GPIO_PIN_11
  58. #define S600_UART2_irq USART2_IRQn
  59. #define S600_UART2_clk RCU_USART2
  60. #define S600_UART2_tx_gpio_clk RCU_GPIOB
  61. #define S600_UART2_rx_gpio_clk RCU_GPIOB
  62. #define S600_UART2_tx_dma DMA0
  63. #define S600_UART2_tx_dma_ch DMA_CH1
  64. #define S600_UART2_tx_dma_clk RCU_DMA0
  65. #define S600_UART2_rx_dma DMA0
  66. #define S600_UART2_rx_dma_ch DMA_CH2
  67. #define S600_UART2_rx_dma_clk RCU_DMA0
  68. #define S600_UART2_on_data_received s600_uart2_received
  69. #define S600_UART3_com UART3
  70. #define S600_UART3_baudrate 115200
  71. #define S600_UART3_tx_port GPIOC
  72. #define S600_UART3_tx_pin GPIO_PIN_10
  73. #define S600_UART3_rx_port GPIOC
  74. #define S600_UART3_rx_pin GPIO_PIN_11
  75. #define S600_UART3_irq UART3_IRQn
  76. #define S600_UART3_clk RCU_UART3
  77. #define S600_UART3_tx_gpio_clk RCU_GPIOC
  78. #define S600_UART3_rx_gpio_clk RCU_GPIOC
  79. #define S600_UART3_tx_dma DMA1
  80. #define S600_UART3_tx_dma_ch DMA_CH4
  81. #define S600_UART3_tx_dma_clk RCU_DMA1
  82. #define S600_UART3_rx_dma DMA1
  83. #define S600_UART3_rx_dma_ch DMA_CH2
  84. #define S600_UART3_rx_dma_clk RCU_DMA1
  85. #define S600_UART3_on_data_received s600_uart3_received
  86. #define S600_UART4_com UART4
  87. #define S600_UART4_baudrate 38400
  88. #define S600_UART4_tx_port GPIOC
  89. #define S600_UART4_tx_pin GPIO_PIN_12
  90. #define S600_UART4_rx_port GPIOD
  91. #define S600_UART4_rx_pin GPIO_PIN_2
  92. #define S600_UART4_irq UART4_IRQn
  93. #define S600_UART4_clk RCU_UART4
  94. #define S600_UART4_tx_gpio_clk RCU_GPIOC
  95. #define S600_UART4_rx_gpio_clk RCU_GPIOD
  96. #define S600_UART4_on_data_received s600_uart4_received
  97. // ================================================================================
  98. #define S600_UART_CACHE_SIZE \
  99. ((S600_UART_TX_MEM_SIZE + S600_UART_RX_MEM_SIZE) * (S600_UART_COUNT - 1) + S600_UART_MAIN_TX_MEM_SIZE + S600_UART_MAIN_RX_MEM_SIZE)
  100. #define S600_UART_DMA_ADDR(index) \
  101. (S600_UART##index##_com + 0x04)
  102. #define S600_UART_DMA_CHCTL_TX(uart) \
  103. DMA_CHCTL(uart->tx_dma, uart->tx_dma_ch)
  104. #define S600_UART_DMA_CHCNT_TX(uart) \
  105. DMA_CHCNT(uart->tx_dma, uart->tx_dma_ch)
  106. #define S600_UART_DMA_CHMADDR_TX(uart) \
  107. DMA_CHMADDR(uart->tx_dma, uart->tx_dma_ch)
  108. #define S600_UART_DMA_CHCTL_RX(uart) \
  109. DMA_CHCTL(uart->rx_dma, uart->rx_dma_ch)
  110. #define S600_UART_DMA_CHCNT_RX(uart) \
  111. DMA_CHCNT(uart->rx_dma, uart->rx_dma_ch)
  112. #define S600_UART_DMA_CHMADDR_RX(uart) \
  113. DMA_CHMADDR(uart->rx_dma, uart->rx_dma_ch)
  114. #define S600_UART_DEVICE_INIT(index) \
  115. do { \
  116. s600_uarts[index].com = S600_UART##index##_com; \
  117. s600_uarts[index].on_data_received = S600_UART##index##_on_data_received; \
  118. byte_queue_init(&s600_uarts[index].tx_queue, s600_uarts[index].tx_cache, s600_uarts[index].tx_cache_size); \
  119. byte_queue_init(&s600_uarts[index].rx_queue, s600_uarts[index].rx_cache, s600_uarts[index].rx_cache_size); \
  120. rcu_periph_clock_enable(S600_UART##index##_clk); \
  121. rcu_periph_clock_enable(S600_UART##index##_rx_gpio_clk); \
  122. rcu_periph_clock_enable(S600_UART##index##_tx_gpio_clk); \
  123. gpio_init(S600_UART##index##_tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, S600_UART##index##_tx_pin); \
  124. gpio_init(S600_UART##index##_rx_port, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, S600_UART##index##_rx_pin); \
  125. usart_deinit(S600_UART##index##_com); \
  126. usart_baudrate_set(S600_UART##index##_com, S600_UART##index##_baudrate); \
  127. usart_word_length_set(S600_UART##index##_com, USART_WL_8BIT); \
  128. usart_stop_bit_set(S600_UART##index##_com, USART_STB_1BIT); \
  129. usart_parity_config(S600_UART##index##_com, USART_PM_NONE); \
  130. usart_hardware_flow_rts_config(S600_UART##index##_com, USART_RTS_DISABLE); \
  131. usart_hardware_flow_cts_config(S600_UART##index##_com, USART_CTS_DISABLE); \
  132. usart_receive_config(S600_UART##index##_com, USART_RECEIVE_ENABLE); \
  133. usart_transmit_config(S600_UART##index##_com, USART_TRANSMIT_ENABLE); \
  134. } while (0)
  135. #define S600_UART_TX_IRQ_INIT(index) \
  136. do { \
  137. s600_uarts[index].tx_poll = s600_uart_irq_tx; \
  138. nvic_irq_enable(S600_UART##index##_irq, 0, 0); \
  139. } while (0)
  140. #define S600_UART_RX_IRQ_INIT(index) \
  141. do { \
  142. s600_uarts[index].rx_poll = s600_uart_irq_rx; \
  143. usart_interrupt_enable(S600_UART##index##_com, USART_INT_RBNE); \
  144. nvic_irq_enable(S600_UART##index##_irq, 0, 0); \
  145. } while (0)
  146. #if S600_UART_USE_DMA
  147. #define S600_UART_TX_DMA_INIT(index) \
  148. do { \
  149. dma_parameter_struct dma_init_struct; \
  150. s600_uarts[index].tx_poll = s600_uart_dma_tx; \
  151. s600_uarts[index].tx_dma = S600_UART##index##_tx_dma; \
  152. s600_uarts[index].tx_dma_ch = S600_UART##index##_tx_dma_ch; \
  153. rcu_periph_clock_enable(S600_UART##index##_tx_dma_clk); \
  154. dma_deinit(S600_UART##index##_tx_dma, S600_UART##index##_tx_dma_ch); \
  155. dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; \
  156. dma_init_struct.memory_addr = (u32) s600_uarts[index].tx_cache; \
  157. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; \
  158. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; \
  159. dma_init_struct.number = 0; \
  160. dma_init_struct.periph_addr = S600_UART_DMA_ADDR(index); \
  161. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; \
  162. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; \
  163. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; \
  164. dma_init(S600_UART##index##_tx_dma, S600_UART##index##_tx_dma_ch, &dma_init_struct); \
  165. dma_circulation_disable(S600_UART##index##_tx_dma, S600_UART##index##_tx_dma_ch); \
  166. usart_dma_transmit_config(S600_UART##index##_com, USART_DENT_ENABLE); \
  167. } while (0)
  168. #define S600_UART_RX_DMA_INIT(index) \
  169. do { \
  170. dma_parameter_struct dma_init_struct; \
  171. s600_uarts[index].rx_poll = s600_uart_dma_rx; \
  172. s600_uarts[index].rx_dma = S600_UART##index##_rx_dma; \
  173. s600_uarts[index].rx_dma_ch = S600_UART##index##_rx_dma_ch; \
  174. rcu_periph_clock_enable(S600_UART##index##_rx_dma_clk); \
  175. dma_deinit(S600_UART##index##_rx_dma, S600_UART##index##_rx_dma_ch); \
  176. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; \
  177. dma_init_struct.memory_addr = (u32) s600_uarts[index].rx_cache; \
  178. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; \
  179. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; \
  180. dma_init_struct.number = s600_uarts[index].rx_cache_size; \
  181. dma_init_struct.periph_addr = S600_UART_DMA_ADDR(index); \
  182. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; \
  183. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; \
  184. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; \
  185. dma_init(S600_UART##index##_rx_dma, S600_UART##index##_rx_dma_ch, &dma_init_struct); \
  186. dma_circulation_enable(S600_UART##index##_rx_dma, S600_UART##index##_rx_dma_ch); \
  187. dma_channel_enable(S600_UART##index##_rx_dma, S600_UART##index##_rx_dma_ch); \
  188. usart_dma_receive_config(S600_UART##index##_com, USART_DENR_ENABLE); \
  189. } while (0)
  190. #else
  191. #define S600_UART_TX_DMA_INIT(index) \
  192. S600_UART_TX_IRQ_INIT(index)
  193. #define S600_UART_RX_DMA_INIT(index) \
  194. S600_UART_RX_IRQ_INIT(index)
  195. #endif
  196. #define S600_UART_INIT_DMA(index) \
  197. do { \
  198. S600_UART_DEVICE_INIT(index); \
  199. S600_UART_TX_DMA_INIT(index); \
  200. S600_UART_RX_DMA_INIT(index); \
  201. } while (0)
  202. #define S600_UART_INIT_IRQ(index) \
  203. do { \
  204. S600_UART_DEVICE_INIT(index); \
  205. S600_UART_TX_IRQ_INIT(index); \
  206. S600_UART_RX_IRQ_INIT(index); \
  207. } while (0)
  208. // ================================================================================
  209. static u16 s600_print_pos;
  210. static u8 s600_print_buff[S600_UART_FRAME_SIZE];
  211. static u16 s600_uart_index;
  212. static bool s600_uart_valid;
  213. static bool s600_uart_escape;
  214. static u8 s600_uart_frame[S600_UART_FRAME_SIZE];
  215. static u8 s600_uart_cache[S600_UART_CACHE_SIZE];
  216. s600_uart_device_t s600_uarts[S600_UART_COUNT];
  217. s600_uart_device_t *s600_uart_passthrough;
  218. // ================================================================================
  219. void s600_uart_dma_tx(s600_uart_device_t *uart)
  220. {
  221. u32 value = S600_UART_DMA_CHCTL_TX(uart);
  222. if (value & DMA_CHXCTL_CHEN) {
  223. if (SET != dma_flag_get(uart->tx_dma, uart->tx_dma_ch, DMA_FLAG_FTF)) {
  224. return;
  225. }
  226. byte_queue_skip(&uart->tx_queue, uart->tx_length);
  227. S600_UART_DMA_CHCTL_TX(uart) = value & (~DMA_CHXCTL_CHEN);
  228. }
  229. uart->tx_length = byte_queue_peek(&uart->tx_queue);
  230. if (uart->tx_length > 0) {
  231. S600_UART_DMA_CHCNT_TX(uart) = uart->tx_length;
  232. S600_UART_DMA_CHMADDR_TX(uart) = (u32) byte_queue_head(&uart->tx_queue);
  233. dma_flag_clear(uart->tx_dma, uart->tx_dma_ch, DMA_FLAG_FTF);
  234. S600_UART_DMA_CHCTL_TX(uart) = value | DMA_CHXCTL_CHEN;
  235. }
  236. }
  237. void s600_uart_cache_data(s600_uart_device_t *uart, u8 *buff, u16 length)
  238. {
  239. #if S600_UART_USE_CACHE
  240. while (length > 0) {
  241. u8 remain = sizeof(uart->cache) - uart->cache_len;
  242. uart->cache_times = S600_UART_CACHE_TIMES;
  243. if (length < remain) {
  244. memcpy(uart->cache + uart->cache_len, buff, length);
  245. uart->cache_len += length;
  246. break;
  247. }
  248. memcpy(uart->cache + uart->cache_len, buff, remain);
  249. uart->on_data_received(uart->cache, sizeof(uart->cache));
  250. uart->cache_len = 0;
  251. length -= remain;
  252. buff += remain;
  253. }
  254. #else
  255. if (length > 0) {
  256. uart->on_data_received(buff, length);
  257. }
  258. #endif
  259. }
  260. void s600_uart_dma_rx(s600_uart_device_t *uart)
  261. {
  262. u16 index = uart->rx_index;
  263. uart->rx_index = uart->rx_cache_size - S600_UART_DMA_CHCNT_RX(uart);
  264. if (uart->rx_index < index) {
  265. uart->do_cache_data(uart, uart->rx_cache + index, uart->rx_cache_size - index);
  266. uart->do_cache_data(uart, uart->rx_cache, uart->rx_index);
  267. } else {
  268. uart->do_cache_data(uart, uart->rx_cache + index, uart->rx_index - index);
  269. }
  270. }
  271. void s600_uart_irq_tx(s600_uart_device_t *uart)
  272. {
  273. }
  274. void s600_uart_irq_rx(s600_uart_device_t *uart)
  275. {
  276. u8 buff[128];
  277. u8 length;
  278. length = s600_uart_read(uart, buff, sizeof(buff));
  279. uart->do_cache_data(uart, buff, length);
  280. }
  281. void s600_uart_rx(s600_uart_device_t *uart)
  282. {
  283. u32 com = uart->com;
  284. while (usart_flag_get(com, USART_FLAG_RBNE) == SET) {
  285. u8 value = usart_data_receive(com);
  286. byte_queue_write(&uart->rx_queue, &value, 1);
  287. }
  288. }
  289. void s600_uart_device_tx(s600_uart_device_t *uart)
  290. {
  291. u32 com = uart->com;
  292. if (usart_flag_get(com, USART_FLAG_TBE) == SET) {
  293. u8 value;
  294. if (byte_queue_read(&uart->tx_queue, &value, 1) > 0) {
  295. usart_data_transmit(com, value);
  296. } else {
  297. usart_interrupt_disable(com, USART_INT_TBE);
  298. }
  299. }
  300. }
  301. void s600_uart_write(s600_uart_device_t *uart, const u8 *buff, u16 size)
  302. {
  303. while (size > 0) {
  304. u16 length = byte_queue_write(&uart->tx_queue, buff, size);
  305. if (uart->tx_dma == 0) {
  306. usart_interrupt_enable(uart->com, USART_INT_TBE);
  307. }
  308. if (length == size) {
  309. break;
  310. }
  311. if (uart->tx_dma != 0) {
  312. s600_uart_dma_tx(uart);
  313. }
  314. buff += length;
  315. size -= length;
  316. }
  317. }
  318. u16 s600_uart_read(s600_uart_device_t *uart, u8 *buff, u16 size)
  319. {
  320. return byte_queue_read(&uart->rx_queue, buff, size);
  321. }
  322. void s600_uart_write_byte(s600_uart_device_t *uart, u8 value)
  323. {
  324. s600_uart_write(uart, &value, 1);
  325. }
  326. u16 s600_uart_write_available(s600_uart_device_t *uart)
  327. {
  328. return byte_queue_get_free(&uart->tx_queue);
  329. }
  330. bool s600_uart_write_full(s600_uart_device_t *uart, const u8 *buff, u16 size)
  331. {
  332. if (s600_uart_write_available(uart) < size) {
  333. return false;
  334. }
  335. s600_uart_write(uart, buff, size);
  336. return true;
  337. }
  338. void s600_uart_write_byte_esc(s600_uart_device_t *uart, u8 value)
  339. {
  340. switch (value) {
  341. case CH_START:
  342. s600_uart_write_byte(uart, CH_ESC);
  343. value = CH_ESC_START;
  344. break;
  345. case CH_END:
  346. s600_uart_write_byte(uart, CH_ESC);
  347. value = CH_ESC_END;
  348. break;
  349. case CH_ESC:
  350. s600_uart_write_byte(uart, CH_ESC);
  351. value = CH_ESC_ESC;
  352. break;
  353. }
  354. s600_uart_write_byte(uart, value);
  355. }
  356. void s600_uart_message_init(s600_uart_message_t *msg, const void *buff, u16 size)
  357. {
  358. msg->buff = (u8 *) buff;
  359. msg->size = size;
  360. }
  361. void s600_uart_write_messages(s600_uart_device_t *uart, const s600_uart_message_t *msgs, u8 count)
  362. {
  363. const s600_uart_message_t *msg_end;
  364. u16 crc = 0;
  365. #ifdef CONFIG_BOARD_M6_JIG
  366. s600_uart_write_byte(uart, 0xAA);
  367. #endif
  368. s600_uart_write_byte(uart, CH_START);
  369. for (msg_end = msgs + count; msgs < msg_end; msgs++) {
  370. const u8 *buff = msgs->buff;
  371. const u8 *buff_end = buff + msgs->size;
  372. while (buff < buff_end) {
  373. u8 value = *buff++;
  374. s600_uart_write_byte_esc(uart, value);
  375. crc = s600_crc_put_byte(crc, value);
  376. }
  377. }
  378. s600_uart_write_byte_esc(uart, crc);
  379. s600_uart_write_byte_esc(uart, crc >> 8);
  380. s600_uart_write_byte(uart, CH_END);
  381. }
  382. // ================================================================================
  383. static void s600_uart_process_cmd_can(u8 *buff, u16 length)
  384. {
  385. s600_can_efid_t efid;
  386. if (length < 5) {
  387. return;
  388. }
  389. efid.value = s600_decode_u32(buff);
  390. if (efid.dest == 0x00 && efid.src == 0x45) {
  391. s600_can_process_frame(efid, buff + 4, length - 4);
  392. } else {
  393. u8 mailbox = s600_can_wait_mailbox();
  394. if (mailbox != CAN_NOMAILBOX) {
  395. s600_can_send_frame(mailbox, efid.value, buff + 4, length - 4);
  396. }
  397. }
  398. }
  399. static int s600_uart_process_cmd_version(u8 *buff, u16 length)
  400. {
  401. length = sizeof(CONFIG_BOARD_NAME) - 1;
  402. memcpy(buff, CONFIG_BOARD_NAME, length);
  403. return length;
  404. }
  405. static int s600_uart_process_command(u16 command, u8 *buff, u16 length)
  406. {
  407. return -1;
  408. }
  409. static s600_uart_device_t *s600_uart_get_device(int uart)
  410. {
  411. if (uart < NELEM(s600_uarts)) {
  412. return s600_uarts + uart;
  413. }
  414. return NULL;
  415. }
  416. static void s600_uart_passthrough_master(u8 *buff, u16 size)
  417. {
  418. s600_uart_write(s600_uart_passthrough, buff, size);
  419. }
  420. static void s600_uart_passthrough_slave(u8 *buff, u16 size)
  421. {
  422. s600_uart_write(s600_uart_get_main(), buff, size);
  423. }
  424. static int s600_uart_process_uart_config(u8 *buff, u16 length)
  425. {
  426. s600_uart_device_t *uart;
  427. if (length < 2) {
  428. return -1;
  429. }
  430. uart = s600_uart_get_device(buff[0]);
  431. if (uart == NULL) {
  432. return -1;
  433. }
  434. if (length > 5) {
  435. u32 baudrate = s600_decode_u32(buff + 2);
  436. usart_baudrate_set(uart->com, baudrate);
  437. }
  438. if (buff[1]) {
  439. usart_enable(uart->com);
  440. if ((buff[1] & 0x02) != 0) {
  441. s600_uart_passthrough = uart;
  442. uart->on_data_received = s600_uart_passthrough_slave;
  443. s600_uart_get_main()->on_data_received = s600_uart_passthrough_master;
  444. }
  445. } else {
  446. usart_disable(uart->com);
  447. }
  448. return 0;
  449. }
  450. static u32 s600_uart_gpio_decode_port(u8 value)
  451. {
  452. u8 index = value >> 5;
  453. rcu_periph_clock_enable(s600_gpio_rcu_map[index]);
  454. return s600_gpio_map[index];
  455. }
  456. static u32 s600_uart_gpio_decode_pin(u8 value)
  457. {
  458. return 1 << (value & 0x1F);
  459. }
  460. static u32 s600_uart_exti_decode_port(u8 value)
  461. {
  462. return value >> 5;
  463. }
  464. static u32 s600_uart_exti_decode_pin(u8 value)
  465. {
  466. return value & 0x1F;
  467. }
  468. static int s600_uart_process_gpio_init(u8 *buff, u16 length)
  469. {
  470. if (length < 6) {
  471. u32 port = s600_uart_gpio_decode_port(buff[0]);
  472. u32 pin = s600_uart_gpio_decode_pin(buff[0]);
  473. gpio_init(port, buff[1], buff[2], pin);
  474. } else {
  475. gpio_pin_remap_config(s600_decode_u32(buff + 1), (ControlStatus) buff[5]);
  476. }
  477. return 1;
  478. }
  479. static int s600_uart_process_gpio_input_bit_get(u8 *buff, u16 length)
  480. {
  481. u32 port = s600_uart_gpio_decode_port(buff[0]);
  482. u32 pin = s600_uart_gpio_decode_pin(buff[0]);
  483. if (length > 1) {
  484. gpio_init(port, buff[1], GPIO_OSPEED_50MHZ, pin);
  485. }
  486. buff[1] = gpio_input_bit_get(port, pin);
  487. return 2;
  488. }
  489. static int s600_uart_process_gpio_output_bit_set(u8 *buff, u16 length)
  490. {
  491. u32 port = s600_uart_gpio_decode_port(buff[0]);
  492. u32 pin = s600_uart_gpio_decode_pin(buff[0]);
  493. if (length > 2) {
  494. gpio_init(port, buff[2], GPIO_OSPEED_50MHZ, pin);
  495. }
  496. if (buff[1] == 0) {
  497. gpio_bit_reset(port, pin);
  498. } else {
  499. gpio_bit_set(port, pin);
  500. }
  501. return 1;
  502. }
  503. static int s600_uart_process_gpio_output_bit_get(u8 *buff, u16 length)
  504. {
  505. u32 port = s600_uart_gpio_decode_port(buff[0]);
  506. u32 pin = s600_uart_gpio_decode_pin(buff[0]);
  507. buff[1] = gpio_output_bit_get(port, pin);
  508. return 2;
  509. }
  510. static int s600_uart_process_gpio_input_port_get(u8 *buff, u16 length)
  511. {
  512. u32 port = s600_uart_gpio_decode_port(buff[0]);
  513. s600_encode_u16(buff + 1, gpio_input_port_get(port));
  514. return 3;
  515. }
  516. static int s600_uart_process_gpio_output_port_set(u8 *buff, u16 length)
  517. {
  518. u32 port = s600_uart_gpio_decode_port(buff[0]);
  519. gpio_port_write(port, s600_decode_u16(buff + 1));
  520. return 1;
  521. }
  522. static int s600_uart_process_gpio_output_port_get(u8 *buff, u16 length)
  523. {
  524. u32 port = s600_uart_gpio_decode_port(buff[0]);
  525. s600_encode_u16(buff + 1, gpio_output_port_get(port));
  526. return 3;
  527. }
  528. static int s600_uart_process_adc(u8 *buff, u16 length)
  529. {
  530. return s600_adc_get_values(buff[0], buff + 1) - buff + 1;
  531. }
  532. static int s600_uart_process_write_dac(int index, u8 *buff, u16 length)
  533. {
  534. length = s600_dac_write(index, buff, length);
  535. s600_encode_u16(buff, length);
  536. return 2;
  537. }
  538. static int s600_uart_process_dac_set_enable(u8 *buff, u16 length)
  539. {
  540. u8 dac = buff[0];
  541. if (buff[1] == 0) {
  542. s600_dac_disable(dac);
  543. } else {
  544. s600_dac_enable(dac);
  545. }
  546. return 1;
  547. }
  548. static int s600_uart_process_dac_set_volume(u8 *buff, u16 length)
  549. {
  550. s600_dac_set_volume(buff[0], buff[1]);
  551. return 1;
  552. }
  553. static int s600_uart_process_dac_set_rate(u8 *buff, u16 length)
  554. {
  555. s600_dac_set_rate(buff[0], s600_decode_u16(buff + 1));
  556. return 1;
  557. }
  558. static int s600_uart_process_single_comm_config(u8 *buff, u16 length)
  559. {
  560. if (length < 2) {
  561. return -1;
  562. }
  563. if (buff[1]) {
  564. u32 port, pin;
  565. if (length < 3) {
  566. return -1;
  567. }
  568. port = s600_uart_exti_decode_port(buff[2]);
  569. pin = s600_uart_exti_decode_pin(buff[2]);
  570. s600_turn_key_init(buff[0], port, pin);
  571. } else {
  572. s600_turn_key_deinit(buff[0]);
  573. }
  574. return 0;
  575. }
  576. static int s600_uart_process_spi_led_init(void)
  577. {
  578. ws2818_spi_init();
  579. return 0;
  580. }
  581. static int s600_uart_process_spi_led_commit(void)
  582. {
  583. ws2818_commit();
  584. return 0;
  585. }
  586. static int s600_uart_process_spi_led_clear(u8 *buff, u16 length)
  587. {
  588. u32 color;
  589. u8 index;
  590. u8 count;
  591. if (length > 0) {
  592. index = buff[0];
  593. } else {
  594. index = 0;
  595. }
  596. if (length > 1) {
  597. count = buff[1];
  598. } else {
  599. count = WS2818_LED_COUNT - index;
  600. }
  601. if (length < 5) {
  602. color = 0x00000000;
  603. } else {
  604. color = s600_decode_u24(buff + 2);
  605. }
  606. ws2818_set_color_burst(index, index + count, color);
  607. return 0;
  608. }
  609. static int s600_uart_process_spi_led_set_color(u8 *buff, u16 length)
  610. {
  611. u8 index;
  612. if (length < 1) {
  613. return -1;
  614. }
  615. for (index = buff[0], buff++, length--; length >= 3; index++) {
  616. ws2818_set_color(index, s600_decode_u24(buff));
  617. length -= 3;
  618. buff += 3;
  619. }
  620. return 0;
  621. }
  622. static int s600_uart_process_reg_rw(u8 *buff, u16 length)
  623. {
  624. return 0;
  625. }
  626. static int s600_uart_process_mem_rw(u8 *buff, u16 length)
  627. {
  628. return 0;
  629. }
  630. static void s600_uart_exti_notify(u8 index)
  631. {
  632. exti_interrupt_flag_clear((exti_line_enum) BIT(index));
  633. s600_uart_send_command(CMD_EXTI_NOTIFY, &index, 1);
  634. }
  635. static void s600_uart_put(struct s600_uart_device *uart, u8 *buff, u16 length)
  636. {
  637. const u8 *buff_end;
  638. for (buff_end = buff + length; buff < buff_end; buff++) {
  639. u8 value = *buff;
  640. switch (value) {
  641. case CH_START:
  642. s600_uart_index = 0;
  643. s600_uart_valid = true;
  644. s600_uart_escape = false;
  645. break;
  646. case CH_END:
  647. if (s600_uart_valid && s600_uart_index > 0) {
  648. s600_uart_process_frame(s600_uart_frame, s600_uart_index);
  649. s600_uart_index = 0;
  650. }
  651. s600_uart_valid = false;
  652. s600_uart_escape = false;
  653. break;
  654. case CH_ESC:
  655. s600_uart_escape = true;
  656. break;
  657. default:
  658. if (s600_uart_escape) {
  659. s600_uart_escape = false;
  660. switch (value) {
  661. case CH_ESC_START:
  662. value = CH_START;
  663. break;
  664. case CH_ESC_END:
  665. value = CH_END;
  666. break;
  667. case CH_ESC_ESC:
  668. value = CH_ESC;
  669. break;
  670. default:
  671. s600_uart_valid = false;
  672. break;
  673. }
  674. }
  675. if (s600_uart_index < sizeof(s600_uart_frame)) {
  676. s600_uart_frame[s600_uart_index++] = value;
  677. } else {
  678. s600_uart_valid = false;
  679. }
  680. }
  681. }
  682. }
  683. void s600_uart_poll(void)
  684. {
  685. int i;
  686. for (i = 0; i < NELEM(s600_uarts); i++) {
  687. s600_uart_device_t *uart = s600_uarts + i;
  688. uart->tx_poll(uart);
  689. uart->rx_poll(uart);
  690. #if S600_UART_USE_CACHE
  691. if (uart->cache_times > 0) {
  692. if (uart->cache_times == 1 && uart->cache_len > 0) {
  693. uart->on_data_received(uart->cache, uart->cache_len);
  694. uart->cache_len = 0;
  695. }
  696. uart->cache_times--;
  697. }
  698. #endif
  699. }
  700. }
  701. void s600_uart_print_flush(short_command_t cmd)
  702. {
  703. s600_uart_send_command(cmd, s600_print_buff, s600_print_pos);
  704. s600_print_pos = 0;
  705. }
  706. void s600_uart0_received(u8 *buff, u16 length)
  707. {
  708. s600_uart_send_command(CMD_UART0, buff, length);
  709. }
  710. void s600_uart1_received(u8 *buff, u16 length)
  711. {
  712. s600_uart_send_command(CMD_UART1, buff, length);
  713. }
  714. void s600_uart2_received(u8 *buff, u16 length)
  715. {
  716. s600_uart_send_command(CMD_UART2, buff, length);
  717. }
  718. void s600_uart3_received(u8 *buff, u16 length)
  719. {
  720. s600_uart_send_command(CMD_UART3, buff, length);
  721. }
  722. void s600_uart4_received(u8 *buff, u16 length)
  723. {
  724. s600_uart_send_command(CMD_UART4, buff, length);
  725. }
  726. void s600_uart_rcu_config(void)
  727. {
  728. u16 position = 0;
  729. int i;
  730. for (i = 0; i < NELEM(s600_uarts); i++) {
  731. s600_uart_device_t *uart = s600_uarts + i;
  732. if (i == CONFIG_UART_MAIN) {
  733. uart->tx_cache_size = S600_UART_MAIN_TX_MEM_SIZE;
  734. uart->rx_cache_size = S600_UART_MAIN_RX_MEM_SIZE;
  735. uart->do_cache_data = s600_uart_put;
  736. } else {
  737. uart->tx_cache_size = S600_UART_TX_MEM_SIZE;
  738. uart->rx_cache_size = S600_UART_RX_MEM_SIZE;
  739. uart->do_cache_data = s600_uart_cache_data;
  740. }
  741. uart->tx_cache = s600_uart_cache + position;
  742. uart->rx_cache = uart->tx_cache + uart->tx_cache_size;
  743. }
  744. S600_UART_INIT_DMA(0);
  745. S600_UART_INIT_DMA(1);
  746. #ifdef CONFIG_BOARD_M6_CDL
  747. S600_UART_INIT_IRQ(2);
  748. #else
  749. S600_UART_INIT_DMA(2);
  750. #endif
  751. S600_UART_INIT_DMA(3);
  752. S600_UART_INIT_IRQ(4);
  753. usart_enable(s600_uart_get_main()->com);
  754. }
  755. int fputc(int ch, FILE *f)
  756. {
  757. if (ch == '\n') {
  758. if (s600_print_pos > 0) {
  759. s600_uart_print_flush(CMD_PRINT_END);
  760. }
  761. } else {
  762. while (1) {
  763. if (s600_print_pos < sizeof(s600_print_buff)) {
  764. s600_print_buff[s600_print_pos] = ch;
  765. s600_print_pos++;
  766. break;
  767. }
  768. s600_uart_print_flush(CMD_PRINT_ADD);
  769. }
  770. }
  771. return ch;
  772. }
  773. void USART0_IRQHandler(void)
  774. {
  775. s600_uart_rx(s600_uarts);
  776. s600_uart_device_tx(s600_uarts);
  777. }
  778. void USART1_IRQHandler(void)
  779. {
  780. s600_uart_rx(s600_uarts + 1);
  781. s600_uart_device_tx(s600_uarts + 1);
  782. }
  783. void USART2_IRQHandler(void)
  784. {
  785. s600_uart_rx(s600_uarts + 2);
  786. s600_uart_device_tx(s600_uarts + 2);
  787. }
  788. void UART3_IRQHandler(void)
  789. {
  790. s600_uart_rx(s600_uarts + 3);
  791. s600_uart_device_tx(s600_uarts + 3);
  792. }
  793. void UART4_IRQHandler(void)
  794. {
  795. s600_uart_rx(s600_uarts + 4);
  796. s600_uart_device_tx(s600_uarts + 4);
  797. }