uart.c 14 KB

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  1. #include "uart.h"
  2. #include "bsp/shark_bsp.h"
  3. #include "bsp/gpio.h"
  4. #include "libs/shark_libs.h"
  5. #define SHARK_UART_BAUDRATE 38400
  6. #define SHARK_UART0_com USART0
  7. #define SHARK_UART0_tx_port GPIOB
  8. #define SHARK_UART0_tx_pin GPIO_PIN_6
  9. #define SHARK_UART0_rx_port GPIOB
  10. #define SHARK_UART0_rx_pin GPIO_PIN_7
  11. #define SHARK_UART0_irq USART0_IRQn
  12. #define SHARK_UART0_clk RCU_USART0
  13. #define SHARK_UART0_tx_gpio_clk RCU_GPIOB
  14. #define SHARK_UART0_rx_gpio_clk RCU_GPIOB
  15. #define SHARK_UART0_tx_dma DMA
  16. #define SHARK_UART0_tx_dma_ch DMA_CH1
  17. #define SHARK_UART0_tx_dma_clk RCU_DMA
  18. #define SHARK_UART0_rx_dma DMA
  19. #define SHARK_UART0_rx_dma_ch DMA_CH2
  20. #define SHARK_UART0_rx_dma_clk RCU_DMA
  21. #define SHARK_UART1_com USART1
  22. #define SHARK_UART1_tx_port GPIOA
  23. #define SHARK_UART1_tx_pin GPIO_PIN_2
  24. #define SHARK_UART1_rx_port GPIOA
  25. #define SHARK_UART1_rx_pin GPIO_PIN_3
  26. #define SHARK_UART1_irq USART1_IRQn
  27. #define SHARK_UART1_clk RCU_USART1
  28. #define SHARK_UART1_tx_gpio_clk RCU_GPIOA
  29. #define SHARK_UART1_rx_gpio_clk RCU_GPIOA
  30. #define SHARK_UART1_tx_dma DMA
  31. #define SHARK_UART1_tx_dma_ch DMA_CH3
  32. #define SHARK_UART1_tx_dma_clk RCU_DMA
  33. #define SHARK_UART1_rx_dma DMA
  34. #define SHARK_UART1_rx_dma_ch DMA_CH4
  35. #define SHARK_UART1_rx_dma_clk RCU_DMA
  36. // ================================================================================
  37. static u8 shark_uart0_tx_cache[SHARK_UART_TX_MEM_SIZE];
  38. static u8 shark_uart1_tx_cache[SHARK_UART_TX_MEM_SIZE];
  39. static u8 shark_uart_rx_cache[SHARK_UART_RX_MEM_SIZE];
  40. static shark_uart_t _shark_uart[SHARK_UART_COUNT];
  41. static shark_task_t _uart_task;
  42. static bool new_prococol = false;
  43. static u64 _rx_time;
  44. static bool uart_no_data = false;
  45. #define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(uart->rx_dma_ch))
  46. extern void protocol_recv_frame(uart_enum_t uart_no, char *data, int len);
  47. extern void protocol_notify_old_frame(uart_enum_t uart_no);
  48. // ================================================================================
  49. static uart_enum_t _uart_index(uint32_t com){
  50. return com == SHARK_UART0_com?SHARK_UART0:SHARK_UART1;
  51. }
  52. static bool shark_uart_on_rx_frame(shark_uart_t *uart)
  53. {
  54. u16 crc0 = shark_decode_u16(uart->rx_frame + uart->rx_length);
  55. u16 crc1 = shark_crc16_check(uart->rx_frame, uart->rx_length);
  56. if (crc0 != crc1) {
  57. return false;
  58. }
  59. new_prococol = true;
  60. protocol_recv_frame(_uart_index(uart->uart_com), (char *)uart->rx_frame, uart->rx_length);
  61. return true;
  62. }
  63. static void shark_uart_rx(shark_uart_t *uart){
  64. while(1) {
  65. u8 data;
  66. update_dma_w_pos(uart);
  67. if (circle_get_one_data(&uart->rx_queue, &data) != 1) {
  68. if (!new_prococol){//通过老协议发送过来的,需要回复一个信息,告知使用新协议,霍尔移除,通信超时需要reset new_protocol
  69. if (shark_get_mseconds() >= (30 + _rx_time)) {
  70. _rx_time = 0xFFFFFFFFFFFFL;
  71. protocol_notify_old_frame(_uart_index(uart->uart_com));
  72. }
  73. }else if (shark_get_mseconds() >= (2000 + _rx_time)){
  74. uart_no_data = true;
  75. }else {
  76. uart_no_data = false;
  77. }
  78. break;
  79. }
  80. _rx_time = shark_get_mseconds();
  81. switch(data){
  82. case CH_START:
  83. uart->rx_length = 0;
  84. uart->escape = false;
  85. break;
  86. case CH_END:
  87. if (uart->rx_length > 2 && uart->rx_length != 0xFF){
  88. shark_uart_on_rx_frame(uart);
  89. }
  90. uart->rx_length = 0xFF;
  91. break;
  92. case CH_ESC:
  93. uart->escape = true;
  94. break;
  95. default:
  96. if (uart->escape) {
  97. uart->escape = false;
  98. switch (data) {
  99. case CH_ESC_START:
  100. data = CH_START;
  101. break;
  102. case CH_ESC_END:
  103. data = CH_END;
  104. break;
  105. case CH_ESC_ESC:
  106. data = CH_ESC;
  107. break;
  108. default:
  109. data = 0xFF;
  110. }
  111. }
  112. if (uart->rx_length < sizeof(uart->rx_frame)) {
  113. uart->rx_frame[uart->rx_length] = data;
  114. uart->rx_length++;
  115. } else {
  116. uart->rx_length = 0xFF;
  117. }
  118. }
  119. }
  120. }
  121. static void shark_uart_dma_tx(shark_uart_t *uart)
  122. {
  123. u32 value = DMA_CHCTL(uart->tx_dma_ch);
  124. if (value & DMA_CHXCTL_CHEN) {
  125. if (SET != dma_flag_get(uart->tx_dma_ch, DMA_FLAG_FTF)) {
  126. return;
  127. }
  128. byte_queue_skip(&uart->tx_queue, uart->tx_length);
  129. DMA_CHCTL(uart->tx_dma_ch) = value & (~DMA_CHXCTL_CHEN);
  130. }
  131. uart->tx_length = byte_queue_peek(&uart->tx_queue);
  132. if (uart->tx_length > 0) {
  133. DMA_CHCNT(uart->tx_dma_ch) = uart->tx_length;
  134. DMA_CHMADDR(uart->tx_dma_ch) = (u32) byte_queue_head(&uart->tx_queue);
  135. dma_flag_clear(uart->tx_dma_ch, DMA_FLAG_FTF);
  136. DMA_CHCTL(uart->tx_dma_ch) = value | DMA_CHXCTL_CHEN;
  137. }
  138. }
  139. static void shark_uart_write(shark_uart_t *uart, const u8 *buff, u16 size)
  140. {
  141. while (size > 0) {
  142. u16 length = byte_queue_write(&uart->tx_queue, buff, size);
  143. if (length == size) {
  144. shark_uart_dma_tx(uart);
  145. break;
  146. }
  147. shark_uart_dma_tx(uart);
  148. buff += length;
  149. size -= length;
  150. }
  151. }
  152. static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
  153. {
  154. shark_uart_write(uart, &value, 1);
  155. }
  156. static void shark_uart_tx_dma_init(shark_uart_t *uart){
  157. dma_parameter_struct dma_init_struct;
  158. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  159. dma_deinit(uart->tx_dma_ch);
  160. dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
  161. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  162. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  163. dma_init_struct.periph_addr = (u32) &USART_TDATA(uart->uart_com);
  164. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  165. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  166. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  167. dma_init(uart->tx_dma_ch, &dma_init_struct);
  168. dma_circulation_disable(uart->tx_dma_ch);
  169. dma_memory_to_memory_disable(uart->tx_dma_ch);
  170. usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
  171. #if 0
  172. if (uart->tx_dma_ch == DMA_CH1) {
  173. nvic_irq_enable(DMA_Channel1_2_IRQn ,4, 0);
  174. }else {
  175. nvic_irq_enable(DMA_Channel3_4_IRQn ,4, 0);
  176. }
  177. dma_interrupt_enable(uart->tx_dma_ch, DMA_INT_FTF);
  178. #endif
  179. }
  180. static void shark_uart_rx_dma_init(shark_uart_t *uart){
  181. dma_parameter_struct dma_init_struct;
  182. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  183. dma_deinit(uart->rx_dma_ch);
  184. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  185. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  186. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  187. dma_init_struct.memory_addr = (u32)uart->rx_queue.buffer;
  188. dma_init_struct.number = uart->rx_queue.buffer_len;
  189. dma_init_struct.periph_addr = (u32) &USART_RDATA(uart->uart_com);
  190. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  191. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  192. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  193. dma_init(uart->rx_dma_ch, &dma_init_struct);
  194. dma_circulation_enable(uart->rx_dma_ch);
  195. dma_memory_to_memory_disable(uart->rx_dma_ch);
  196. dma_channel_enable(uart->rx_dma_ch);
  197. usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
  198. }
  199. static void shark_uart_pin_init(shark_uart_t *uart){
  200. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  201. rcu_periph_clock_enable(SHARK_UART0_clk);
  202. rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
  203. rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
  204. gpio_af_set(SHARK_UART0_tx_port, GPIO_AF_0,SHARK_UART0_tx_pin);
  205. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_tx_pin);
  206. gpio_output_options_set(SHARK_UART0_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART0_tx_pin);
  207. gpio_af_set(SHARK_UART0_rx_port, GPIO_AF_0,SHARK_UART0_rx_pin);
  208. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_rx_pin);
  209. gpio_output_options_set(SHARK_UART0_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
  210. }else {
  211. rcu_periph_clock_enable(SHARK_UART1_clk);
  212. rcu_periph_clock_enable(SHARK_UART1_rx_gpio_clk);
  213. rcu_periph_clock_enable(SHARK_UART1_tx_gpio_clk);
  214. gpio_af_set(SHARK_UART1_tx_port, GPIO_AF_1,SHARK_UART1_tx_pin);
  215. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_tx_pin);
  216. gpio_output_options_set(SHARK_UART1_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART1_tx_pin);
  217. gpio_af_set(SHARK_UART1_rx_port, GPIO_AF_1,SHARK_UART1_rx_pin);
  218. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_rx_pin);
  219. gpio_output_options_set(SHARK_UART1_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART1_rx_pin);
  220. }
  221. }
  222. static void shark_uart_device_init(shark_uart_t *uart){
  223. usart_deinit(uart->uart_com);
  224. usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
  225. usart_word_length_set(uart->uart_com, USART_WL_8BIT);
  226. usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
  227. usart_parity_config(uart->uart_com, USART_PM_NONE);
  228. usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
  229. usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
  230. usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
  231. usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
  232. }
  233. static u32 shark_uart_handler(void)
  234. {
  235. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  236. if (uart->uart_com != 0) {
  237. shark_uart_rx(uart);
  238. shark_uart_dma_tx(uart);
  239. }
  240. uart = _shark_uart + SHARK_UART1;
  241. if (uart->uart_com != 0) {
  242. shark_uart_rx(uart);
  243. shark_uart_dma_tx(uart);
  244. }
  245. return 0;
  246. }
  247. void shark_uart_flush(void){
  248. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  249. if (uart->uart_com != 0) {
  250. shark_uart_dma_tx(uart);
  251. }
  252. uart = _shark_uart + SHARK_UART1;
  253. if (uart->uart_com != 0) {
  254. shark_uart_dma_tx(uart);
  255. }
  256. }
  257. #if 0
  258. void DMA_Channel1_2_IRQHandler(void){
  259. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  260. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  261. shark_uart_dma_tx(uart);
  262. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  263. }
  264. }
  265. void DMA_Channel3_4_IRQHandler(void){
  266. shark_uart_t *uart = _shark_uart + SHARK_UART1;
  267. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  268. shark_uart_dma_tx(uart);
  269. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  270. }
  271. }
  272. #endif
  273. static u8 *tx_cache_addr(uart_enum_t uart_no){
  274. return (uart_no == SHARK_UART0)?shark_uart0_tx_cache:shark_uart1_tx_cache;
  275. }
  276. void shark_uart_deinit(uart_enum_t uart_no){
  277. shark_uart_t *uart = _shark_uart + uart_no;
  278. if (uart->uart_com != 0) {
  279. usart_disable(uart->uart_com);
  280. usart_deinit(uart->uart_com);
  281. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_clk:SHARK_UART1_clk);
  282. dma_channel_disable(uart->rx_dma_ch);
  283. dma_channel_disable(uart->tx_dma_ch);
  284. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  285. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  286. }
  287. if (uart_no == SHARK_UART0) {
  288. UART0_IR_EN(0);
  289. }else {
  290. UART1_IR_EN(0);
  291. }
  292. new_prococol = false;
  293. uart_no_data = true;
  294. }
  295. bool shark_uart_timeout(void){
  296. return uart_no_data;
  297. }
  298. void shark_uart_init(uart_enum_t uart_no)
  299. {
  300. shark_uart_t *uart = _shark_uart + uart_no;
  301. uart->escape = false;
  302. uart->rx_length = 0;
  303. uart->tx_length = 0;
  304. uart->uart_com = (uart_no == SHARK_UART0)?SHARK_UART0_com:SHARK_UART1_com;
  305. circle_buffer_init(&uart->rx_queue, shark_uart_rx_cache, SHARK_UART_TX_MEM_SIZE);
  306. byte_queue_init(&uart->tx_queue,tx_cache_addr(uart_no), SHARK_UART_TX_MEM_SIZE);
  307. uart->rx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_rx_dma_ch:SHARK_UART1_rx_dma_ch;
  308. uart->tx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_tx_dma_ch:SHARK_UART1_tx_dma_ch;
  309. shark_uart_pin_init(uart);
  310. shark_uart_device_init(uart);
  311. shark_uart_rx_dma_init(uart);
  312. shark_uart_tx_dma_init(uart);
  313. usart_enable(uart->uart_com);
  314. if (_uart_task.handler == NULL) {
  315. _uart_task.handler = shark_uart_handler;
  316. shark_task_add(&_uart_task);
  317. }
  318. if (uart_no == SHARK_UART0) {
  319. UART0_IR_EN(1);
  320. }else {
  321. UART1_IR_EN(1);
  322. }
  323. _rx_time = 0xFFFFFFFFFFFFL;
  324. }
  325. static void shark_uart_write_byte_esc(shark_uart_t *uart, u8 value)
  326. {
  327. switch (value) {
  328. case CH_START:
  329. shark_uart_write_byte(uart, CH_ESC);
  330. value = CH_ESC_START;
  331. break;
  332. case CH_END:
  333. shark_uart_write_byte(uart, CH_ESC);
  334. value = CH_ESC_END;
  335. break;
  336. case CH_ESC:
  337. shark_uart_write_byte(uart, CH_ESC);
  338. value = CH_ESC_ESC;
  339. break;
  340. }
  341. shark_uart_write_byte(uart, value);
  342. }
  343. static void shark_uart_write_esc(shark_uart_t *uart, const u8 *buff, u16 length)
  344. {
  345. const u8 *buff_end;
  346. for (buff_end = buff + length; buff < buff_end; buff++) {
  347. shark_uart_write_byte_esc(uart, *buff);
  348. }
  349. }
  350. static void shark_uart_tx_start(shark_uart_t *uart)
  351. {
  352. shark_uart_write_byte(uart, CH_START);
  353. uart->tx_crc16 = 0;
  354. }
  355. static void shark_uart_tx_continue(shark_uart_t *uart, const void *buff, u16 length)
  356. {
  357. shark_uart_write_esc(uart, (const u8 *) buff, length);
  358. uart->tx_crc16 = shark_crc16_update(uart->tx_crc16, (const u8 *) buff, length);
  359. }
  360. static void shark_uart_tx_end(shark_uart_t *uart)
  361. {
  362. shark_uart_write_esc(uart, (u8 *)&uart->tx_crc16, sizeof(uart->tx_crc16));
  363. shark_uart_write_byte(uart, CH_END);
  364. }
  365. void shark_uart_write_frame(uart_enum_t uart_no, uint8_t *bytes, int len){
  366. shark_uart_t *uart = _shark_uart + uart_no;
  367. shark_uart_tx_start(uart);
  368. shark_uart_tx_continue(uart, bytes, len);
  369. shark_uart_tx_end(uart);
  370. }
  371. void shark_uart_frame_start(uart_enum_t uart_no, uint8_t *bytes, int len){
  372. shark_uart_t *uart = _shark_uart + uart_no;
  373. shark_uart_tx_start(uart);
  374. shark_uart_tx_continue(uart, bytes, len);
  375. }
  376. void shark_uart_frame_continue(uart_enum_t uart_no, uint8_t *bytes, int len){
  377. shark_uart_t *uart = _shark_uart + uart_no;
  378. shark_uart_tx_continue(uart, bytes, len);
  379. }
  380. void shark_uart_frame_end(uart_enum_t uart_no){
  381. shark_uart_tx_end(_shark_uart + uart_no);
  382. }
  383. void shark_uart_write_bytes(uart_enum_t uart_no, u8 *buff, u16 size){
  384. shark_uart_write(_shark_uart + uart_no, buff, size);
  385. }