uart.c 15 KB

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  1. #include "uart.h"
  2. #include "bsp/shark_bsp.h"
  3. #include "bsp/gpio.h"
  4. #include "libs/shark_libs.h"
  5. #define SHARK_UART_BAUDRATE 38400
  6. #define SHARK_UART0_com USART0
  7. #define SHARK_UART0_tx_port GPIOB
  8. #define SHARK_UART0_tx_pin GPIO_PIN_6
  9. #define SHARK_UART0_rx_port GPIOB
  10. #define SHARK_UART0_rx_pin GPIO_PIN_7
  11. #define SHARK_UART0_irq USART0_IRQn
  12. #define SHARK_UART0_clk RCU_USART0
  13. #define SHARK_UART0_tx_gpio_clk RCU_GPIOB
  14. #define SHARK_UART0_rx_gpio_clk RCU_GPIOB
  15. #define SHARK_UART0_tx_dma DMA
  16. #define SHARK_UART0_tx_dma_ch DMA_CH1
  17. #define SHARK_UART0_tx_dma_clk RCU_DMA
  18. #define SHARK_UART0_rx_dma DMA
  19. #define SHARK_UART0_rx_dma_ch DMA_CH2
  20. #define SHARK_UART0_rx_dma_clk RCU_DMA
  21. #define SHARK_UART1_com USART1
  22. #define SHARK_UART1_tx_port GPIOA
  23. #define SHARK_UART1_tx_pin GPIO_PIN_2
  24. #define SHARK_UART1_rx_port GPIOA
  25. #define SHARK_UART1_rx_pin GPIO_PIN_3
  26. #define SHARK_UART1_irq USART1_IRQn
  27. #define SHARK_UART1_clk RCU_USART1
  28. #define SHARK_UART1_tx_gpio_clk RCU_GPIOA
  29. #define SHARK_UART1_rx_gpio_clk RCU_GPIOA
  30. #define SHARK_UART1_tx_dma DMA
  31. #define SHARK_UART1_tx_dma_ch DMA_CH3
  32. #define SHARK_UART1_tx_dma_clk RCU_DMA
  33. #define SHARK_UART1_rx_dma DMA
  34. #define SHARK_UART1_rx_dma_ch DMA_CH4
  35. #define SHARK_UART1_rx_dma_clk RCU_DMA
  36. // ================================================================================
  37. static u8 shark_uart0_tx_cache[SHARK_UART_TX_MEM_SIZE];
  38. #if UART_NUM==2
  39. static u8 shark_uart1_tx_cache[SHARK_UART_TX_MEM_SIZE];
  40. #endif
  41. static u8 shark_uart_rx_cache[SHARK_UART_RX_MEM_SIZE];
  42. static shark_uart_t _shark_uart[UART_NUM];
  43. static shark_task_t _uart_task;
  44. static u64 _rx_time;
  45. ///static bool uart_no_data = false;
  46. #define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(uart->rx_dma_ch))
  47. extern void protocol_recv_frame(uart_enum_t uart_no, char *data, int len);
  48. extern void protocol_old_recv_frame(uart_enum_t uart_no, uint8_t *data, int len);
  49. extern void health_add_uart_error(uint32_t c, uint32_t l, uint32_t d);
  50. // ================================================================================
  51. static uart_enum_t _uart_index(uint32_t com){
  52. return com == SHARK_UART0_com?SHARK_UART0:SHARK_UART1;
  53. }
  54. static bool shark_uart_on_rx_frame(shark_uart_t *uart)
  55. {
  56. u16 crc0 = shark_decode_u16(uart->rx_frame + uart->rx_length);
  57. u16 crc1 = shark_crc16_check(uart->rx_frame, uart->rx_length);
  58. if (crc0 != crc1) {
  59. health_add_uart_error(1, 0, 0);
  60. return false;
  61. }
  62. protocol_recv_frame(_uart_index(uart->uart_com), (char *)uart->rx_frame, uart->rx_length);
  63. return true;
  64. }
  65. static void shark_uart_rx(shark_uart_t *uart){
  66. while(1) {
  67. u8 data;
  68. update_dma_w_pos(uart);
  69. if (circle_get_one_data(&uart->rx_queue, &data) != 1) {
  70. if (shark_get_mseconds() >= (5 + _rx_time)) {
  71. //_rx_time = 0xFFFFFFFFFFFFL;
  72. if (uart->rx_length_old_prot > 0){
  73. protocol_old_recv_frame(_uart_index(uart->uart_com), uart->rx_frame_old_prot, uart->rx_length_old_prot);
  74. uart->rx_length_old_prot = 0;
  75. }
  76. }
  77. if (shark_get_mseconds() >= (UART_TIMEOUT + _rx_time)){
  78. uart->uart_no_data = true;
  79. }else {
  80. uart->uart_no_data = false;
  81. }
  82. break;
  83. }
  84. _rx_time = shark_get_mseconds();
  85. uart->rx_frame_old_prot[uart->rx_length_old_prot ++] = data;
  86. if (uart->rx_length_old_prot == sizeof(uart->rx_frame_old_prot)){
  87. uart->rx_length_old_prot = 0;
  88. }
  89. switch(data){
  90. case CH_START:
  91. uart->rx_length = 0;
  92. uart->escape = false;
  93. uart->start = true;
  94. break;
  95. case CH_END:
  96. if (uart->rx_length > 2 && uart->rx_length != 0xFFFF){
  97. uart->rx_length -= 2; //skip crc
  98. shark_uart_on_rx_frame(uart);
  99. }else if (uart->start == true){
  100. health_add_uart_error(0, 1, 0);
  101. }
  102. uart->rx_length = 0xFFFF;
  103. uart->start = false;
  104. break;
  105. case CH_ESC:
  106. uart->escape = true;
  107. break;
  108. default:
  109. if (uart->escape) {
  110. uart->escape = false;
  111. switch (data) {
  112. case CH_ESC_START:
  113. data = CH_START;
  114. break;
  115. case CH_ESC_END:
  116. data = CH_END;
  117. break;
  118. case CH_ESC_ESC:
  119. data = CH_ESC;
  120. break;
  121. default:
  122. data = 0xFF;
  123. }
  124. }
  125. if (uart->rx_length < sizeof(uart->rx_frame)) {
  126. uart->rx_frame[uart->rx_length] = data;
  127. uart->rx_length++;
  128. } else {
  129. uart->rx_length = 0xFFFF;
  130. if (uart->start == true) {
  131. health_add_uart_error(0, 1, 0);
  132. }
  133. }
  134. }
  135. }
  136. }
  137. static void shark_uart_dma_tx(shark_uart_t *uart)
  138. {
  139. u32 value = DMA_CHCTL(uart->tx_dma_ch);
  140. if (value & DMA_CHXCTL_CHEN) {
  141. if (SET != dma_flag_get(uart->tx_dma_ch, DMA_FLAG_FTF)) {
  142. return;
  143. }
  144. byte_queue_skip(&uart->tx_queue, uart->tx_length);
  145. DMA_CHCTL(uart->tx_dma_ch) = value & (~DMA_CHXCTL_CHEN);
  146. }
  147. uart->tx_length = byte_queue_peek(&uart->tx_queue);
  148. if (uart->tx_length > 0) {
  149. DMA_CHCNT(uart->tx_dma_ch) = uart->tx_length;
  150. DMA_CHMADDR(uart->tx_dma_ch) = (u32) byte_queue_head(&uart->tx_queue);
  151. dma_flag_clear(uart->tx_dma_ch, DMA_FLAG_FTF);
  152. DMA_CHCTL(uart->tx_dma_ch) = value | DMA_CHXCTL_CHEN;
  153. }
  154. }
  155. static void shark_uart_write(shark_uart_t *uart, const u8 *buff, u16 size)
  156. {
  157. while (size > 0) {
  158. u16 length = byte_queue_write(&uart->tx_queue, buff, size);
  159. if (length == size) {
  160. shark_uart_dma_tx(uart);
  161. break;
  162. }
  163. shark_uart_dma_tx(uart);
  164. buff += length;
  165. size -= length;
  166. }
  167. }
  168. static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
  169. {
  170. shark_uart_write(uart, &value, 1);
  171. }
  172. static void shark_uart_tx_dma_init(shark_uart_t *uart){
  173. dma_parameter_struct dma_init_struct;
  174. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  175. dma_deinit(uart->tx_dma_ch);
  176. dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
  177. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  178. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  179. dma_init_struct.periph_addr = (u32) &USART_TDATA(uart->uart_com);
  180. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  181. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  182. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  183. dma_init(uart->tx_dma_ch, &dma_init_struct);
  184. dma_circulation_disable(uart->tx_dma_ch);
  185. dma_memory_to_memory_disable(uart->tx_dma_ch);
  186. usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
  187. #if 0
  188. if (uart->tx_dma_ch == DMA_CH1) {
  189. nvic_irq_enable(DMA_Channel1_2_IRQn ,4, 0);
  190. }else {
  191. nvic_irq_enable(DMA_Channel3_4_IRQn ,4, 0);
  192. }
  193. dma_interrupt_enable(uart->tx_dma_ch, DMA_INT_FTF);
  194. #endif
  195. }
  196. static void shark_uart_rx_dma_init(shark_uart_t *uart){
  197. dma_parameter_struct dma_init_struct;
  198. rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  199. dma_deinit(uart->rx_dma_ch);
  200. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  201. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  202. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  203. dma_init_struct.memory_addr = (u32)uart->rx_queue.buffer;
  204. dma_init_struct.number = uart->rx_queue.buffer_len;
  205. dma_init_struct.periph_addr = (u32) &USART_RDATA(uart->uart_com);
  206. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  207. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  208. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  209. dma_init(uart->rx_dma_ch, &dma_init_struct);
  210. dma_circulation_enable(uart->rx_dma_ch);
  211. dma_memory_to_memory_disable(uart->rx_dma_ch);
  212. dma_channel_enable(uart->rx_dma_ch);
  213. usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
  214. }
  215. static void shark_uart_pin_init(shark_uart_t *uart){
  216. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  217. rcu_periph_clock_enable(SHARK_UART0_clk);
  218. rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
  219. rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
  220. gpio_af_set(SHARK_UART0_tx_port, GPIO_AF_0,SHARK_UART0_tx_pin);
  221. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_tx_pin);
  222. gpio_output_options_set(SHARK_UART0_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART0_tx_pin);
  223. gpio_af_set(SHARK_UART0_rx_port, GPIO_AF_0,SHARK_UART0_rx_pin);
  224. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_rx_pin);
  225. gpio_output_options_set(SHARK_UART0_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
  226. }else {
  227. rcu_periph_clock_enable(SHARK_UART1_clk);
  228. rcu_periph_clock_enable(SHARK_UART1_rx_gpio_clk);
  229. rcu_periph_clock_enable(SHARK_UART1_tx_gpio_clk);
  230. gpio_af_set(SHARK_UART1_tx_port, GPIO_AF_1,SHARK_UART1_tx_pin);
  231. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_tx_pin);
  232. gpio_output_options_set(SHARK_UART1_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART1_tx_pin);
  233. gpio_af_set(SHARK_UART1_rx_port, GPIO_AF_1,SHARK_UART1_rx_pin);
  234. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_rx_pin);
  235. gpio_output_options_set(SHARK_UART1_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART1_rx_pin);
  236. }
  237. }
  238. static void shark_uart_pin_deinit(shark_uart_t *uart){
  239. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  240. gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SHARK_UART0_tx_pin);
  241. gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SHARK_UART0_rx_pin);
  242. }else {
  243. gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SHARK_UART1_tx_pin);
  244. gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SHARK_UART1_rx_pin);
  245. }
  246. }
  247. static void shark_uart_device_init(shark_uart_t *uart){
  248. usart_deinit(uart->uart_com);
  249. usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
  250. usart_word_length_set(uart->uart_com, USART_WL_8BIT);
  251. usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
  252. usart_parity_config(uart->uart_com, USART_PM_NONE);
  253. usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
  254. usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
  255. usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
  256. usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
  257. }
  258. static u32 shark_uart_handler(void)
  259. {
  260. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  261. if (uart->uart_com != 0) {
  262. shark_uart_rx(uart);
  263. shark_uart_dma_tx(uart);
  264. }
  265. #if UART_NUM==2
  266. uart = _shark_uart + SHARK_UART1;
  267. if (uart->uart_com != 0) {
  268. shark_uart_rx(uart);
  269. shark_uart_dma_tx(uart);
  270. }
  271. #endif
  272. return 0;
  273. }
  274. void shark_uart_flush(void){
  275. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  276. if (uart->uart_com != 0) {
  277. shark_uart_dma_tx(uart);
  278. }
  279. #if UART_NUM==2
  280. uart = _shark_uart + SHARK_UART1;
  281. if (uart->uart_com != 0) {
  282. shark_uart_dma_tx(uart);
  283. }
  284. #endif
  285. }
  286. #if 0
  287. void DMA_Channel1_2_IRQHandler(void){
  288. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  289. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  290. shark_uart_dma_tx(uart);
  291. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  292. }
  293. }
  294. void DMA_Channel3_4_IRQHandler(void){
  295. shark_uart_t *uart = _shark_uart + SHARK_UART1;
  296. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  297. shark_uart_dma_tx(uart);
  298. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  299. }
  300. }
  301. #endif
  302. static u8 *tx_cache_addr(uart_enum_t uart_no){
  303. #if UART_NUM==2
  304. return (uart_no == SHARK_UART0)?shark_uart0_tx_cache:shark_uart1_tx_cache;
  305. #else
  306. return shark_uart0_tx_cache;
  307. #endif
  308. }
  309. void shark_uart_deinit(uart_enum_t uart_no){
  310. shark_uart_t *uart = _shark_uart + uart_no;
  311. if (uart->uart_com != 0) {
  312. usart_disable(uart->uart_com);
  313. usart_deinit(uart->uart_com);
  314. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_clk:SHARK_UART1_clk);
  315. dma_channel_disable(uart->rx_dma_ch);
  316. dma_channel_disable(uart->tx_dma_ch);
  317. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
  318. rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
  319. shark_uart_pin_deinit(uart);
  320. }
  321. if (uart_no == SHARK_UART0) {
  322. UART0_IR_EN(0);
  323. }else {
  324. UART1_IR_EN(0);
  325. }
  326. }
  327. bool shark_uart_timeout(void){
  328. #if UART_NUM==2
  329. return (_shark_uart[0].uart_no_data && _shark_uart[1].uart_no_data)?TRUE:FALSE;
  330. #else
  331. return (_shark_uart[0].uart_no_data)?TRUE:FALSE;
  332. #endif
  333. }
  334. void shark_uart_init(uart_enum_t uart_no)
  335. {
  336. shark_uart_t *uart = _shark_uart + uart_no;
  337. uart->escape = false;
  338. uart->rx_length = 0;
  339. uart->tx_length = 0;
  340. uart->uart_com = (uart_no == SHARK_UART0)?SHARK_UART0_com:SHARK_UART1_com;
  341. circle_buffer_init(&uart->rx_queue, shark_uart_rx_cache, SHARK_UART_TX_MEM_SIZE);
  342. byte_queue_init(&uart->tx_queue,tx_cache_addr(uart_no), SHARK_UART_TX_MEM_SIZE);
  343. uart->rx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_rx_dma_ch:SHARK_UART1_rx_dma_ch;
  344. uart->tx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_tx_dma_ch:SHARK_UART1_tx_dma_ch;
  345. shark_uart_pin_init(uart);
  346. shark_uart_device_init(uart);
  347. shark_uart_rx_dma_init(uart);
  348. shark_uart_tx_dma_init(uart);
  349. usart_enable(uart->uart_com);
  350. if (_uart_task.handler == NULL) {
  351. _uart_task.handler = shark_uart_handler;
  352. shark_task_add(&_uart_task);
  353. }
  354. if (uart_no == SHARK_UART0) {
  355. UART0_IR_EN(1);
  356. }else {
  357. UART1_IR_EN(1);
  358. }
  359. _rx_time = shark_get_mseconds();
  360. uart->uart_no_data = false;
  361. }
  362. static void shark_uart_write_byte_esc(shark_uart_t *uart, u8 value)
  363. {
  364. switch (value) {
  365. case CH_START:
  366. shark_uart_write_byte(uart, CH_ESC);
  367. value = CH_ESC_START;
  368. break;
  369. case CH_END:
  370. shark_uart_write_byte(uart, CH_ESC);
  371. value = CH_ESC_END;
  372. break;
  373. case CH_ESC:
  374. shark_uart_write_byte(uart, CH_ESC);
  375. value = CH_ESC_ESC;
  376. break;
  377. }
  378. shark_uart_write_byte(uart, value);
  379. }
  380. static void shark_uart_write_esc(shark_uart_t *uart, const u8 *buff, u16 length)
  381. {
  382. const u8 *buff_end;
  383. for (buff_end = buff + length; buff < buff_end; buff++) {
  384. shark_uart_write_byte_esc(uart, *buff);
  385. }
  386. }
  387. static void shark_uart_tx_start(shark_uart_t *uart)
  388. {
  389. shark_uart_write_byte(uart, CH_START);
  390. uart->tx_crc16 = 0;
  391. }
  392. static void shark_uart_tx_continue(shark_uart_t *uart, const void *buff, u16 length)
  393. {
  394. shark_uart_write_esc(uart, (const u8 *) buff, length);
  395. uart->tx_crc16 = shark_crc16_update(uart->tx_crc16, (const u8 *) buff, length);
  396. }
  397. static void shark_uart_tx_end(shark_uart_t *uart)
  398. {
  399. shark_uart_write_esc(uart, (u8 *)&uart->tx_crc16, sizeof(uart->tx_crc16));
  400. shark_uart_write_byte(uart, CH_END);
  401. }
  402. void shark_uart_write_frame(uart_enum_t uart_no, uint8_t *bytes, int len){
  403. shark_uart_t *uart = _shark_uart + uart_no;
  404. shark_uart_tx_start(uart);
  405. shark_uart_tx_continue(uart, bytes, len);
  406. shark_uart_tx_end(uart);
  407. }
  408. void shark_uart_frame_start(uart_enum_t uart_no, uint8_t *bytes, int len){
  409. shark_uart_t *uart = _shark_uart + uart_no;
  410. shark_uart_tx_start(uart);
  411. shark_uart_tx_continue(uart, bytes, len);
  412. }
  413. void shark_uart_frame_continue(uart_enum_t uart_no, uint8_t *bytes, int len){
  414. shark_uart_t *uart = _shark_uart + uart_no;
  415. shark_uart_tx_continue(uart, bytes, len);
  416. }
  417. void shark_uart_frame_end(uart_enum_t uart_no){
  418. shark_uart_tx_end(_shark_uart + uart_no);
  419. }
  420. void shark_uart_write_bytes(uart_enum_t uart_no, u8 *buff, u16 size){
  421. shark_uart_write(_shark_uart + uart_no, buff, size);
  422. }