bms/Application/bsp/bsp.c

#include "bsp/shark_bsp.h"
#include "bsp/gpio.h"
#include "bsp/uart.h"
#include "bsp/AT24CXX.h"
#include "bsp/shark_rtc.h"
#include "bsp/clock.h"
#include "bsp/fmc_flash.h"
#include "bsp/cht8305.h"
#include "libs/logger.h"
#include "libs/shark_task.h"
#include "version.h"
#include <string.h>

#if defined CONFIG_BOARD_SP700
const char iap_board_name[] __attribute__((at(0x08002800))) = "SP700";
#elif defined CONFIG_BOARD_SP600
const char iap_board_name[] __attribute__((at(0x08002800))) = "SP600";
#endif
const char iap_fw_version[] __attribute__((at(0x08002A00))) = CONFIG_VERSION;
const char iap_fw_name[] __attribute__((at(0x08002C00))) = "App";

extern void system_clock_config(void);
extern void SystemCoreClockUpdate(void);
extern void gpio_key_init(void);

#ifndef CONFIG_DEBUG
#define CONFIG_DEBUG 0
#endif
static uint32_t reset_source = 0;
static uint32_t backup_reg = 0;
//all board's low level init is here
void bsp_init(void){
	reset_source = RCU_RSTSCK;
	backup_reg = RTC_BKP0;
	wdog_start(4);
	shark_rtc_init();
	enable_mcu_power();
	system_clock_config(); //after dcdc open, MCU can run on full speed
	SystemCoreClockUpdate();
	rcu_all_reset_flag_clear();
	task_ticks_enable();
	gpio_init();
	set_log_level(MOD_SYSTEM, L_debug);
	shark_uart_init(SHARK_UART0);
#if UART_NUM==2
	shark_uart_init(SHARK_UART1);
#endif
	AT24CXX_Init();
	cht8305_init();
	AUX_VOL_OPEN(0);
	gpio_key_init();
	RTC_BKP0 = 0;
}

uint32_t bsp_get_rst_reson(void){
	return reset_source;
}

uint32_t bsp_get_backup(void){
	return backup_reg;
}

void systick_close(void)
{
	SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;
}

void systick_open(void)
{
	SysTick_Config(SystemCoreClock / 1000);
}


char* bsp_get_fversion(void){
	return (char *)iap_fw_version;
}

void system_reboot(void){
	NVIC_SystemReset();
}


/* timeout:1-25 */
void wdog_start(int timeout){
#if CONFIG_DEBUG == 0
	/* enable IRC40K */
	rcu_osci_on(RCU_IRC40K);
	/* wait till IRC40K is ready */
	while(SUCCESS != rcu_osci_stab_wait(RCU_IRC40K)){
	}  
	
	/* confiure FWDGT counter clock: 40KHz(IRC40K) / 256 = 0.15625 KHz */
	fwdgt_config(timeout*40000UL/256, FWDGT_PSC_DIV256);  
	/* after 4 seconds to generate a reset */
	fwdgt_enable();
#endif   

}

void wdog_reload(void){
#if CONFIG_DEBUG == 0
	fwdgt_counter_reload();
#endif 
}

int  wdog_set_timeout(int wdog_time)
{  
#if CONFIG_DEBUG == 0
	uint32_t flag_status = RESET;
	uint32_t timeout = FWDGT_RLD_TIMEOUT;
    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
  
    /* wait until the RUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    }while((--timeout > 0U) && (RESET != flag_status));
   
    if (RESET != flag_status){
        return -1;
    }
    
    FWDGT_RLD = RLD_RLD(wdog_time*40000UL/256);

    /* reload the counter */
    FWDGT_CTL = FWDGT_KEY_RELOAD;
#endif
	return 0;
}