set clk of apb1 to sysclk/4(21M), this can use 100K I2C clk

Signed-off-by: huhui <huhui@sharkgulf.com>

Librarys/CMSIS/GD32F3x0/Source/system_gd32f3x0.c

@@ -476,7 +476,7 @@ static void system_clock_84m_irc8m(void)
     /* APB2 = AHB/2 */
     RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
     /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
     /* PLL = (IRC8M/2) * 21 = 84 MHz */
     RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
     RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL21);