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@@ -0,0 +1,140 @@
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+/*****************************************************************************
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+ ml5238_reg.h
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+
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+ Copyright (C) 2012 LAPIS Semiconductor Co., Ltd.
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+ All rights reserved.
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+
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+ LAPIS Semiconductor shall not be liable for any direct, indirect,
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+ consequential or incidental damages arising from using or modifying this
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+ program.
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+
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+ History
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+ 2012.11.20 ver.2.00
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+ 2012.09.13 ver.1.00
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+******************************************************************************/
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+#ifndef _ML5238_REG_H_
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+#define _ML5238_REG_H_
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+
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+#define ML5238_NOOP (0x00u)
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+#define ML5238_VMON (0x01u)
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+#define ML5238_IMON (0x02u)
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+#define ML5238_FET (0x03u)
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+#define ML5238_PSENSE (0x04u)
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+#define ML5238_RSENSE (0x05u)
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+#define ML5238_POWER (0x06u)
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+#define ML5238_STATUS (0x07u)
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+#define ML5238_CBALH (0x08u)
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+#define ML5238_CBALL (0x09u)
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+#define ML5238_SETSC (0x0Au)
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+
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+/**********************************
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+ NOOP(0x00)
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+**********************************/
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+#define NOOP_NO0 (0x01u)
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+#define NOOP_NO1 (0x02u)
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+#define NOOP_NO2 (0x04u)
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+#define NOOP_NO3 (0x08u)
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+#define NOOP_NO4 (0x10u)
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+#define NOOP_NO5 (0x20u)
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+#define NOOP_NO6 (0x40u)
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+#define NOOP_NO7 (0x80u)
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+
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+/**********************************
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+ VMON(0x01)
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+**********************************/
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+#define VMON_CN0 (0x01u)
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+#define VMON_CN1 (0x02u)
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+#define VMON_CN2 (0x04u)
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+#define VMON_CN3 (0x08u)
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+#define VMON_OUT (0x10u)
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+
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+/**********************************
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+ IMON(0x02)
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+**********************************/
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+#define IMON_GIM (0x01u)
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+#define IMON_ZERO (0x02u)
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+#define IMON_GCAL0 (0x04u)
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+#define IMON_GCAL1 (0x08u)
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+#define IMON_OUT (0x10u)
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+
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+/**********************************
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+ FET(0x03)
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+**********************************/
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+#define FET_DF (0x01u)
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+#define FET_CF (0x02u)
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+#define FET_DRV (0x10u)
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+
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+/**********************************
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+ PSENSE(0x04)
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+**********************************/
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+#define PSENSE_PSL (0x01u)
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+#define PSENSE_RPSL (0x02u)
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+#define PSENSE_IPSL (0x04u)
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+#define PSENSE_EPSL (0x08u)
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+#define PSENSE_PSH (0x10u)
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+#define PSENSE_RPSH (0x20u)
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+#define PSENSE_IPSH (0x40u)
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+#define PSENSE_EPSH (0x80u)
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+
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+/**********************************
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+ RSENSE(0x05)
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+**********************************/
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+#define RSENSE_RS (0x01u)
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+#define RSENSE_RRS (0x02u)
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+#define RSENSE_IRS (0x04u)
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+#define RSENSE_ERS (0x08u)
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+#define RSENSE_SC (0x10u)
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+#define RSENSE_RSC (0x20u)
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+#define RSENSE_ISC (0x40u)
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+#define RSENSE_ESC (0x80u)
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+
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+/**********************************
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+ POWER(0x06)
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+**********************************/
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+#define POWER_PSV (0x01u)
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+#define POWER_PDWN (0x10u)
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+#define POWER_PUPIN (0x80u)
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+
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+/**********************************
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+ STATUS(0x07)
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+**********************************/
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+#define STATUS_DF (0x01u)
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+#define STATUS_CF (0x02u)
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+#define STATUS_PSV (0x04u)
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+#define STATUS_INT (0x08u)
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+#define STATUS_RPSL (0x10u)
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+#define STATUS_RPSH (0x20u)
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+#define STATUS_RRS (0x40u)
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+#define STATUS_RSC (0x80u)
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+
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+/**********************************
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+ CBALH(0x08)
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+**********************************/
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+#define CBALH_SW9 (0x01u)
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+#define CBALH_SW10 (0x02u)
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+#define CBALH_SW11 (0x04u)
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+#define CBALH_SW12 (0x08u)
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+#define CBALH_SW13 (0x10u)
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+#define CBALH_SW14 (0x20u)
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+#define CBALH_SW15 (0x40u)
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+#define CBALH_SW16 (0x80u)
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+
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+/**********************************
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+ CBALL(0x09)
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+**********************************/
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+#define CBALL_SW1 (0x01u)
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+#define CBALL_SW2 (0x02u)
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+#define CBALL_SW3 (0x04u)
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+#define CBALL_SW4 (0x08u)
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+#define CBALL_SW5 (0x10u)
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+#define CBALL_SW6 (0x20u)
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+#define CBALL_SW7 (0x40u)
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+#define CBALL_SW8 (0x80u)
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+
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+/**********************************
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+ SETSC(0x0A)
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+**********************************/
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+#define SETSC_SC0 (0x01u)
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+#define SETSC_SC1 (0x02u)
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+
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+#endif /*_ML5238_REG_H_*/
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