修改工程芯片位GD32F330C8

Signed-off-by: huhui <huhui@sharkgulf.com>

Application/bsp/cs1180.c

@@ -59,14 +59,18 @@ static void spi_read_reg(uint8_t reg, uint8_t *data, uint8_t len){
 static void cs1180_osalsys(void)
 {
 	cs1180_cs(0);
+	delay();
 	cs1180_write_one_data(CS1180_OCALSYS);
+	delay_50us();
 	cs1180_cs(1);
 }
 
 static void cs1180_calibSelf(void)
 {
 	cs1180_cs(0);
+	delay();
 	cs1180_write_one_data(CS1180_CALSELF);
+	delay_50us();
 	cs1180_cs(1);
 }
 

Application/bsp/gpio.h

@@ -1,7 +1,7 @@
 #ifndef _GPIO_H__
 #define _GPIO_H__
-#include "gd32f1x0.h"
-#include "gd32f1x0_libopt.h"
+#include "gd32f3x0.h"
+#include "gd32f3x0_libopt.h"
 
 /*switch for temperature sensers */
 #define TEMP_OPEN(x) gpio_bit_write(GPIOF,GPIO_PIN_1,(bit_status)(x))

Application/bsp/i2c.c

@@ -1,5 +1,5 @@
-#include "gd32f1x0.h"
-#include "gd32f1x0_i2c.h"
+#include "gd32f3x0.h"
+#include "gd32f3x0_i2c.h"
 #include "gpio.h"
 #include "i2c.h"
 

Application/bsp/irqs.c

@@ -1,4 +1,4 @@
-#include "gd32f1x0.h"
+#include "gd32f3x0.h"
 /*!
     \brief      this function handles NMI exception
     \param[in]  none

Librarys/CMSIS/GD32F1x0/Include/gd32f1x0.h

@@ -1,260 +0,0 @@
-/*!
-    \file  gd32f1x0.h
-    \brief general definitions for gd32f1x0
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F1X0_H
-#define GD32F1X0_H
-
-#ifdef cplusplus
- extern "C" {
-#endif 
-
-/* define GD32F1x0 */
-#if !defined (GD32F1x0)
-  #define GD32F1x0
-#endif /* define GD32F1x0 */
-#if !defined (GD32F1x0)
- #error "Please select the target GD32F1x0 device used in your application (in gd32f1x0.h file)"
-#endif /* undefine GD32F1x0 tip */
-
-/* define GD32F1x0 device category */
-#if (!defined (GD32F170_190))&&(!defined (GD32F130_150))
- #error "Please select GD32F1x0 device category( GD32F130_150 or GD32F170_190 )"
-#endif /* undefine GD32F170_190 or GD32F130_150 tip */
-#if (defined (GD32F170_190))&&(defined (GD32F130_150))
- #error "Please select one GD32F1x0 device category( GD32F130_150 or GD32F170_190 )"
-#endif /* define GD32F170_190 and GD32F130_150 tip */
-
-/* define value of high speed crystal oscillator (HXTAL) in Hz */
-#if !defined  (HXTAL_VALUE)
-#define HXTAL_VALUE    ((uint32_t)8000000)
-#endif /* high speed crystal oscillator value */
-
-/* define startup timeout value of high speed crystal oscillator (HXTAL) */
-#if !defined  (HXTAL_STARTUP_TIMEOUT)
-#define HXTAL_STARTUP_TIMEOUT   ((uint16_t)0x0800)
-#endif /* high speed crystal oscillator startup timeout */
-
-/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
-#if !defined  (IRC8M_VALUE) 
-#define IRC8M_VALUE  ((uint32_t)8000000)
-#endif /* internal 8MHz RC oscillator value */
-
-/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
-#if !defined  (IRC8M_STARTUP_TIMEOUT)
-#define IRC8M_STARTUP_TIMEOUT   ((uint16_t)0x0500)
-#endif /* internal 8MHz RC oscillator startup timeout */
-
-/* define value of internal RC oscillator for ADC in Hz */
-#ifdef GD32F170_190
-#if !defined  (IRC28M_VALUE)
-#define IRC28M_VALUE ((uint32_t)28000000)
-#endif /* IRC28M for GD32F170_190 */
-#else 
-#if !defined  (IRC14M_VALUE) 
-#define IRC14M_VALUE ((uint32_t)14000000)
-#endif /* IRC14M for GD32F130_150 */
-#endif /* GD32F170_190 */
-
-/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
-#if !defined  (IRC40K_VALUE) 
-#define IRC40K_VALUE  ((uint32_t)40000)
-#endif /* internal 40KHz RC oscillator value */
-
-/* define value of low speed crystal oscillator (LXTAL)in Hz */
-#if !defined  (LXTAL_VALUE) 
-#define LXTAL_VALUE  ((uint32_t)32768)
-#endif /* low speed crystal oscillator value */
-
-/* GD32F1x0 firmware library version number V3.0 */
-#define __GD32F1x0_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:24] main version     */
-#define __GD32F1x0_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version     */
-#define __GD32F1x0_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version     */
-#define __GD32F1x0_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __GD32F1x0_STDPERIPH_VERSION        ((__GD32F1x0_STDPERIPH_VERSION_MAIN << 24)\
-                                            |(__GD32F1x0_STDPERIPH_VERSION_SUB1 << 16)\
-                                            |(__GD32F1x0_STDPERIPH_VERSION_SUB2 << 8)\
-                                            |(__GD32F1x0_STDPERIPH_VERSION_RC))
-
-/* configuration of the Cortex-M3 processor and core peripherals */
-#define __MPU_PRESENT             1        /*!< GD32F1x0 do not provide MPU                              */
-#define __NVIC_PRIO_BITS          4        /*!< GD32F1x0 uses 4 bits for the priority levels             */
-#define __Vendor_SysTickConfig    0        /*!< set to 1 if different sysTick config is used             */
-
-/* define interrupt number */
-typedef enum IRQn
-{
-    /* Cortex-M3 processor exceptions numbers */
-    NonMaskableInt_IRQn          = -14,    /*!< 2 non maskable interrupt                                 */
-    MemoryManagement_IRQn        = -12,    /*!< 4 Cortex-M3 memory management interrupt                  */
-    BusFault_IRQn                = -11,    /*!< 5 Cortex-M3 bus fault interrupt                          */
-    UsageFault_IRQn              = -10,    /*!< 6 Cortex-M3 usage fault interrupt                        */
-    SVCall_IRQn                  = -5,     /*!< 11 Cortex-M3 SV call interrupt                           */
-    DebugMonitor_IRQn            = -4,     /*!< 12 Cortex-M3 debug monitor interrupt                     */
-    PendSV_IRQn                  = -2,     /*!< 14 Cortex-M3 pend SV interrupt                           */
-    SysTick_IRQn                 = -1,     /*!< 15 Cortex-M3 system tick interrupt                       */
-    /* interruput numbers */
-    WWDGT_IRQn                   = 0,      /*!< window watchdog timer interrupt                          */
-    LVD_IRQn                     = 1,      /*!< LVD through EXTI line detect interrupt                   */
-    RTC_IRQn                     = 2,      /*!< RTC through EXTI line interrupt                          */
-    FMC_IRQn                     = 3,      /*!< FMC interrupt                                            */
-    RCU_IRQn                     = 4,      /*!< RCU interrupt                                            */
-    EXTI0_1_IRQn                 = 5,      /*!< EXTI line 0 and 1 interrupts                             */
-    EXTI2_3_IRQn                 = 6,      /*!< EXTI line 2 and 3 interrupts                             */
-    EXTI4_15_IRQn                = 7,      /*!< EXTI line 4 to 15 interrupts                             */
-    TSI_IRQn                     = 8,      /*!< TSI Interrupt                                            */
-    DMA_Channel0_IRQn            = 9,      /*!< DMA channel 0 interrupt                                  */
-    DMA_Channel1_2_IRQn          = 10,     /*!< DMA channel 1 and channel 2 interrupts                   */
-    DMA_Channel3_4_IRQn          = 11,     /*!< DMA channel 3 and channel 4 interrupts                   */
-    ADC_CMP_IRQn                 = 12,     /*!< ADC, CMP0 and CMP1 interrupts                            */
-    TIMER0_BRK_UP_TRG_COM_IRQn   = 13,     /*!< TIMER0 break, update, trigger and commutation interrupts */
-    TIMER0_Channel_IRQn          = 14,     /*!< TIMER0 channel interrupt                                 */
-    TIMER1_IRQn                  = 15,     /*!< TIMER1 interrupt                                         */
-    TIMER2_IRQn                  = 16,     /*!< TIMER2 interrupt                                         */
-    TIMER5_DAC_IRQn              = 17,     /*!< TIMER5 and DAC interrupts                                */
-    TIMER13_IRQn                 = 19,     /*!< TIMER13 interrupt                                        */
-    TIMER14_IRQn                 = 20,     /*!< TIMER14 interrupt                                        */
-    TIMER15_IRQn                 = 21,     /*!< TIMER15 interrupt                                        */
-    TIMER16_IRQn                 = 22,     /*!< TIMER16 interrupt                                        */
-    I2C0_EV_IRQn                 = 23,     /*!< I2C0 event interrupt                                     */
-    I2C1_EV_IRQn                 = 24,     /*!< I2C1 event interrupt                                     */
-    SPI0_IRQn                    = 25,     /*!< SPI0 interrupt                                           */
-    SPI1_IRQn                    = 26,     /*!< SPI1 interrupt                                           */
-    USART0_IRQn                  = 27,     /*!< USART0 interrupt                                         */
-    USART1_IRQn                  = 28,     /*!< USART1 interrupt                                         */
-    CEC_IRQn                     = 30,     /*!< CEC interrupt                                            */
-    I2C0_ER_IRQn                 = 32,     /*!< I2C0 error interrupt                                     */
-    I2C1_ER_IRQn                 = 34,     /*!< I2C1 error interrupt                                     */
-    I2C2_EV_IRQn                 = 35,     /*!< I2C2 event interrupt                                     */
-    I2C2_ER_IRQn                 = 36,     /*!< I2C2 error interrupt                                     */
-    USBD_LP_IRQn                 = 37,     /*!< USBD_LP interrupt                                        */
-    USBD_HP_IRQn                 = 38,     /*!< USBD_HP interrupt                                        */
-    USBDWakeUp_IRQChannel        = 42,     /*!< USBD_WKUP interrupt                                      */
-    CAN0_TX_IRQn                 = 43,     /*!< CAN0 TX interrupt                                        */
-    CAN0_RX0_IRQn                = 44,     /*!< CAN0 RX0 interrupt                                       */
-    CAN0_RX1_IRQn                = 45,     /*!< CAN0 RX1 interrupt                                       */
-    CAN0_SCE_IRQn                = 46,     /*!< CAN0 SCE interrupt                                       */
-    SLCD_IRQn                    = 47,     /*!< SLCD interrupt                                           */
-    DMA_Channel5_6_IRQn          = 48,     /*!< DMA1 channel 5 and channel 6 interrupts                  */
-    SPI2_IRQn                    = 51,     /*!< SPI2 global interrupt                                    */ 
-    CAN1_TX_IRQn                 = 70,     /*!< CAN1 TX interrupt                                        */
-    CAN1_RX0_IRQn                = 71,     /*!< CAN1 RX0 interrupt                                       */
-    CAN1_RX1_IRQn                = 72,     /*!< CAN1 RX1 interrupt                                       */
-    CAN1_SCE_IRQn                = 73,     /*!< CAN1 SCE interrupt                                       */ 
-} IRQn_Type;
-
-/* includes */
-#include "core_cm3.h"
-#include "system_gd32f1x0.h"
-#include <stdint.h>
-
-/* enum definitions */
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
-typedef enum {FALSE = 0, TRUE = !FALSE} bool;
-typedef enum {RESET = 0, SET = !RESET} FlagStatus;
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
-
-/* bit operations */
-#define REG32(addr)                  (*(volatile uint32_t *)(uint32_t)(addr))
-#define REG16(addr)                  (*(volatile uint16_t *)(uint32_t)(addr))
-#define REG8(addr)                   (*(volatile uint8_t *)(uint32_t)(addr))
-#define BIT(x)                       ((uint32_t)((uint32_t)0x01U<<(x)))
-#define BITS(start, end)             ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 
-#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
-
-/* main flash and SRAM memory map */
-#define FLASH_BASE            ((uint32_t)0x08000000U)        /*!< main FLASH base address          */
-#define SRAM_BASE             ((uint32_t)0x20000000U)        /*!< SRAM base address                */
-/* SRAM and peripheral base bit-band region */
-#define SRAM_BB_BASE          ((uint32_t)0x22000000U)        /*!< SRAM bit-band base address       */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U)        /*!< peripheral bit-band base address */
-/* peripheral memory map */
-#define APB1_BUS_BASE         ((uint32_t)0x40000000U)        /*!< apb1 base address                */
-#define APB2_BUS_BASE         ((uint32_t)0x40010000U)        /*!< apb2 base address                */
-#define AHB1_BUS_BASE         ((uint32_t)0x40020000U)        /*!< ahb1 base address                */
-#define AHB2_BUS_BASE         ((uint32_t)0x48000000U)        /*!< ahb2 base address                */
-/* advanced peripheral bus 1 memory map */
-#define TIMER_BASE            (APB1_BUS_BASE + 0x00000000U)  /*!< TIMER base address               */
-#define SLCD_BASE             (APB1_BUS_BASE + 0x00002400U)  /*!< SLCD base address                */
-#define RTC_BASE              (APB1_BUS_BASE + 0x00002800U)  /*!< RTC base address                 */
-#define WWDGT_BASE            (APB1_BUS_BASE + 0x00002C00U)  /*!< WWDGT base address               */
-#define FWDGT_BASE            (APB1_BUS_BASE + 0x00003000U)  /*!< FWDGT base address               */
-#define USART_BASE            (APB1_BUS_BASE + 0x00004400U)  /*!< USART base address               */
-#define SPI_BASE              (APB1_BUS_BASE + 0x00003800U)  /*!< SPI base address                 */
-#define I2C_BASE              (APB1_BUS_BASE + 0x00005400U)  /*!< I2C base address                 */
-#define USBD_BASE             (APB1_BUS_BASE + 0x00005C00U)  /*!< USBD base address                */
-#define USBD_RAM_BASE         (APB1_BUS_BASE + 0x00006000U)  /*!< USBD RAM base address            */
-#define CAN_BASE              (APB1_BUS_BASE + 0x00006400U)  /*!< CAN base address                 */
-#define PMU_BASE              (APB1_BUS_BASE + 0x00007000U)  /*!< PMU base address                 */
-#define DAC_BASE              (APB1_BUS_BASE + 0x00007400U)  /*!< DAC base address                 */
-#define CEC_BASE              (APB1_BUS_BASE + 0x00007800U)  /*!< CEC base address                 */
-#define OPA_BASE              (APB1_BUS_BASE + 0x00007C5CU)  /*!< OPA base address                 */
-#define IVREF_BASE            (APB1_BUS_BASE + 0x00007C00U)  /*!< IVREF base address               */
-/* advanced peripheral bus 2 memory map */
-#define SYSCFG_BASE           (APB2_BUS_BASE + 0x00000000U)  /*!< SYSCFG base address              */
-#define CMP_BASE              (APB2_BUS_BASE + 0x0000001CU)  /*!< CMP base address                 */
-#define EXTI_BASE             (APB2_BUS_BASE + 0x00000400U)  /*!< EXTI base address                */
-#define ADC_BASE              (APB2_BUS_BASE + 0x00002400U)  /*!< ADC base address                 */
-/* advanced high performance bus 1 memory map */
-#define DMA_BASE              (AHB1_BUS_BASE + 0x00000000U)  /*!< DMA base address                 */
-#define DMA_CHANNEL_BASE      (DMA_BASE + 0x00000008U)       /*!< DMA channel base address         */
-#define RCU_BASE              (AHB1_BUS_BASE + 0x00001000U)  /*!< RCU base address                 */
-#define FMC_BASE              (AHB1_BUS_BASE + 0x00002000U)  /*!< FMC base address                 */
-#define CRC_BASE              (AHB1_BUS_BASE + 0x00003000U)  /*!< CRC base address                 */
-#define TSI_BASE              (AHB1_BUS_BASE + 0x00004000U)  /*!< TSI base address                 */
-/* advanced high performance bus 2 memory map */
-#define GPIO_BASE             (AHB2_BUS_BASE + 0x00000000U)  /*!< GPIO base address                 */
-/* option byte and debug memory map */
-#define OB_BASE               ((uint32_t)0x1FFFF800U)        /*!< OB base address                  */
-#define DBG_BASE              ((uint32_t)0xE0042000U)        /*!< DBG base address                 */
-
-/* define marco USE_STDPERIPH_DRIVER */
-#if !defined  USE_STDPERIPH_DRIVER
-#define USE_STDPERIPH_DRIVER
-#endif 
-#ifdef USE_STDPERIPH_DRIVER
-#include "gd32f1x0_libopt.h"
-#endif /* USE_STDPERIPH_DRIVER */
-
-#ifdef cplusplus
-}
-#endif
-#endif 
-
-
-
-

Librarys/CMSIS/GD32F1x0/Include/gd32f1x0_libopt.h

@@ -1,51 +0,0 @@
-/*!
-    \file  gd32f1x0_libopt.h
-    \brief library optional for gd32f1x0
-*/
-
-/*
-    Copyright (C) 2017 GigaDevice
-
-    2014-12-26, V1.0.0, firmware for GD32F1x0(x=3,5)
-    2016-01-15, V2.0.0, firmware for GD32F1x0(x=3,5,7,9)
-    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#ifndef GD32F1X0_LIBOPT_H
-#define GD32F1X0_LIBOPT_H
-
-/* Includes */
-/* Comment the line below to disable peripheral header file inclusion */
-
-
-#include "gd32f1x0_adc.h"
-#include "gd32f1x0_can.h"
-#include "gd32f1x0_cec.h"
-#include "gd32f1x0_crc.h"
-#include "gd32f1x0_cmp.h"
-#include "gd32f1x0_dac.h"
-#include "gd32f1x0_dbg.h"
-#include "gd32f1x0_dma.h"
-#include "gd32f1x0_exti.h"
-#include "gd32f1x0_fmc.h"
-#include "gd32f1x0_gpio.h"
-#include "gd32f1x0_syscfg.h"
-#include "gd32f1x0_i2c.h"
-#include "gd32f1x0_fwdgt.h"
-#include "gd32f1x0_pmu.h"
-#include "gd32f1x0_rcu.h"
-#include "gd32f1x0_rtc.h"
-#include "gd32f1x0_spi.h"
-#include "gd32f1x0_timer.h"
-#include "gd32f1x0_usart.h"
-#include "gd32f1x0_wwdgt.h"
-#include "gd32f1x0_misc.h"
-#include "gd32f1x0_tsi.h"
-#include "gd32f1x0_slcd.h"
-#include "gd32f1x0_opa.h"
-#include "gd32f1x0_ivref.h"
-
-#endif /* __GD32F1X0_LIBOPT_H */
-
-/******************* (C) COPYRIGHT 2019 GIGADEVICE *****END OF FILE****/

Librarys/CMSIS/GD32F1x0/Source/system_gd32f1x0.c

@@ -1,333 +0,0 @@
-/*!
-    \file  system_gd32f1x0.c
-    \brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for
-           GD32F1x0 Device Series
-*/
-
-/* Copyright (c) 2012 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
-
-#include "gd32f1x0.h"
-
-/* system frequency define */
-#define __IRC8M           (IRC8M_VALUE)            /* internal 8 MHz RC oscillator frequency */
-#define __HXTAL           (HXTAL_VALUE)            /* high speed crystal oscillator frequency */
-#define __SYS_OSC_CLK     (__IRC8M)                /* main oscillator frequency */
-
-/* select a system clock by uncommenting the following line */
-//#define __SYSTEM_CLOCK_8M_HXTAL              (__HXTAL)
-//#define __SYSTEM_CLOCK_8M_IRC8M              (__IRC8M)
-#define __SYSTEM_CLOCK_72M_PLL_HXTAL         (uint32_t)(72000000)
-//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2    (uint32_t)(72000000)
-
-#define SEL_IRC8M       0x00
-#define SEL_HXTAL       0x01
-#define SEL_PLL         0x02
-
-/* set the system clock frequency and declare the system clock configuration function */
-#ifdef __SYSTEM_CLOCK_8M_HXTAL
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
-static void system_clock_8m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
-static void system_clock_72m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
-static void system_clock_72m_irc8m(void);
-#else
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
-static void system_clock_8m_irc8m(void);
-#endif /* __SYSTEM_CLOCK_8M_HXTAL */
-
-/* configure the system clock */
-static void system_clock_config(void);
-
-/*!
-    \brief      setup the microcontroller system, initialize the system
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void SystemInit (void)
-{
-    /* enable IRC8M */
-    RCU_CTL0 |= RCU_CTL0_IRC8MEN;
-    while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
-    }
-    /* reset RCU */
-#ifdef GD32F130_150
-    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
-                  RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
-#elif defined (GD32F170_190)
-    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
-                  RCU_CFG0_ADCPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
-#endif /* GD32F130_150 */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLPREDV);
-#ifdef GD32F130_150
-    RCU_CFG0 &= ~(RCU_CFG0_USBDPSC);
-#endif /* GD32F130_150 */
-    RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
-    RCU_CFG1 &= ~RCU_CFG1_HXTALPREDV;
-    RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_CECSEL | RCU_CFG2_ADCSEL);
-#ifdef GD32F130_150
-    RCU_CTL1 &= ~RCU_CTL1_IRC14MEN;
-#elif defined (GD32F170_190)
-    RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
-    RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
-    RCU_CFG3 &= ~RCU_CFG3_CKOUT1SEL;
-    RCU_CFG3 &= ~RCU_CFG3_CKOUT1DIV;
-#endif /* GD32F130_150 */
-    RCU_INT = 0x00000000U;
-    
-    /* configure system clock */
-    system_clock_config();
-}
-
-/*!
-    \brief      configure the system clock
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_config(void)
-{
-#ifdef __SYSTEM_CLOCK_8M_HXTAL
-    system_clock_8m_hxtal();
-#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
-    system_clock_72m_hxtal();
-#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
-    system_clock_72m_irc8m();
-#else
-    system_clock_8m_irc8m();
-#endif /* __SYSTEM_CLOCK_8M_HXTAL */
-}
-
-#ifdef __SYSTEM_CLOCK_8M_HXTAL
-/*!
-    \brief      configure the system clock to 8M by HXTAL
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_8m_hxtal(void)
-{
-    uint32_t timeout = 0;
-    
-    /* enable HXTAL */
-    RCU_CTL0 |= RCU_CTL0_HXTALEN;
-    
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    while((0 == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++));
-    
-    /* if fail */
-    if(0 == (RCU_CTL0 & RCU_CTL0_HXTALSTB))
-        return;
-    
-    /* HXTAL is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
-    
-    /* select HXTAL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
-    
-    /* wait until HXTAL is selected as system clock */
-    while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL));
-}
-
-#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
-/*!
-    \brief      configure the system clock to 72M by PLL which selects HXTAL as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_72m_hxtal(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-    
-    /* enable HXTAL */
-    RCU_CTL0 |= RCU_CTL0_HXTALEN;
-
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
-    }
-    while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
-        return;
-    }
-    
-    /* HXTAL is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
-
-    /* PLL = HXTAL * 9 = 72 MHz */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
-    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
-
-    /* enable PLL */
-    RCU_CTL0 |= RCU_CTL0_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
-#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
-/*!
-    \brief      configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_72m_irc8m(void)
-{
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
-    /* PLL = (IRC8M/2) * 18 = 72 MHz */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
-    RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
-    
-    /* enable PLL */
-    RCU_CTL0 |= RCU_CTL0_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0 == (RCU_CTL0 & RCU_CTL0_PLLSTB));
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0 == (RCU_CFG0 & RCU_SCSS_PLL));
-}
-
-#else
-/*!
-    \brief      configure the system clock to 8M by IRC8M
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_8m_irc8m(void)
-{
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
-    
-    /* select IRC8M as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
-    
-    /* wait until IRC8M is selected as system clock */
-    while(0 != (RCU_CFG0 & RCU_SCSS_IRC8M));
-}
-#endif /* __SYSTEM_CLOCK_8M_HXTAL */
-
-/*!
-    \brief      update the SystemCoreClock with current core clock retrieved from cpu registers
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void SystemCoreClockUpdate (void)
-{
-    uint32_t sws = 0U;
-    uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
-    /* exponent of AHB clock divider */
-    const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-    
-    sws = GET_BITS(RCU_CFG0, 2, 3);
-    switch(sws){
-    /* IRC8M is selected as CK_SYS */
-    case SEL_IRC8M:
-        SystemCoreClock = IRC8M_VALUE;
-        break;
-    /* HXTAL is selected as CK_SYS */
-    case SEL_HXTAL:
-        SystemCoreClock = HXTAL_VALUE;
-        break;
-    /* PLL is selected as CK_SYS */
-    case SEL_PLL:
-        /* get the value of PLLMF[3:0] */
-        pllmf = GET_BITS(RCU_CFG0, 18, 21);
-        pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
-        /* high 16 bits */
-        if(1U == pllmf4){
-            pllmf += 17U;
-        }else{
-            pllmf += 2U;
-        }
-        /* PLL clock source selection, HXTAL or IRC8M/2 */
-        pllsel = GET_BITS(RCU_CFG0, 16, 16);
-        if(0U != pllsel){
-            prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
-            SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
-        }else{
-            SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
-        }
-        break;
-    /* IRC8M is selected as CK_SYS */
-    default:
-        SystemCoreClock = IRC8M_VALUE;
-        break;
-    }
-    /* calculate AHB clock frequency */
-    idx = GET_BITS(RCU_CFG0, 4, 7);
-    clk_exp = ahb_exp[idx];
-    SystemCoreClock >>= clk_exp;
-}

Librarys/CMSIS/GD32F3x0/Include/gd32f3x0.h

@@ -0,0 +1,242 @@
+/*!
+    \file  gd32f3x0.h
+    \brief general definitions for gd32f3x0
+    
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_H
+#define GD32F3X0_H
+
+#ifdef cplusplus
+ extern "C" {
+#endif 
+
+/* define GD32F3x0 */
+#if !defined (GD32F3x0)
+  #define GD32F3x0
+#endif /* define GD32F3x0 */
+#if !defined (GD32F3x0)
+ #error "Please select the target GD32F3x0 device used in your application (in gd32f3x0.h file)"
+#endif /* undefine GD32F3x0 tip */
+
+/* define GD32F3x0 device category */
+#if (!defined (GD32F330))&&(!defined (GD32F350))
+ #error "Please select GD32F3x0 device category( GD32F330 or GD32F350 )"
+#endif /* undefine GD32F330 or GD32F350 tip */
+#if (defined (GD32F330))&&(defined (GD32F350))
+ #error "Please select one GD32F3x0 device category( GD32F330 or GD32F350 )"
+#endif /* define GD32F330 and GD32F350 tip */
+
+/* define value of high speed crystal oscillator (HXTAL) in Hz */
+#if !defined  (HXTAL_VALUE)
+#define HXTAL_VALUE    ((uint32_t)8000000)
+#endif /* high speed crystal oscillator value */
+
+/* define startup timeout value of high speed crystal oscillator (HXTAL) */
+#if !defined  (HXTAL_STARTUP_TIMEOUT)
+#define HXTAL_STARTUP_TIMEOUT   ((uint16_t)0x0800)
+#endif /* high speed crystal oscillator startup timeout */
+
+/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
+#if !defined  (IRC8M_VALUE) 
+#define IRC8M_VALUE  ((uint32_t)8000000)
+#endif /* internal 8MHz RC oscillator value */
+
+/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
+#if !defined  (IRC8M_STARTUP_TIMEOUT)
+#define IRC8M_STARTUP_TIMEOUT   ((uint16_t)0x0500)
+#endif /* internal 8MHz RC oscillator startup timeout */
+
+/* define value of internal RC oscillator for ADC in Hz */
+#if !defined  (IRC28M_VALUE) 
+#define IRC28M_VALUE ((uint32_t)28000000)
+#endif /* IRC28M_VALUE */
+
+#if !defined  (IRC48M_VALUE) 
+#define IRC48M_VALUE ((uint32_t)48000000)
+#endif /* IRC48M_VALUE */
+
+/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
+#if !defined  (IRC40K_VALUE) 
+#define IRC40K_VALUE  ((uint32_t)40000)
+#endif /* internal 40KHz RC oscillator value */
+
+/* define value of low speed crystal oscillator (LXTAL)in Hz */
+#if !defined  (LXTAL_VALUE) 
+#define LXTAL_VALUE  ((uint32_t)32768)
+#endif /* low speed crystal oscillator value */
+
+/* GD32F3x0 firmware library version number V1.0 */
+#define __GD32F3x0_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version     */
+#define __GD32F3x0_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version     */
+#define __GD32F3x0_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version     */
+#define __GD32F3x0_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __GD32F3x0_STDPERIPH_VERSION        ((__GD32F3x0_STDPERIPH_VERSION_MAIN << 24)\
+                                            |(__GD32F3x0_STDPERIPH_VERSION_SUB1 << 16)\
+                                            |(__GD32F3x0_STDPERIPH_VERSION_SUB2 << 8)\
+                                            |(__GD32F3x0_STDPERIPH_VERSION_RC))
+
+/* configuration of the Cortex-M4 processor and core peripherals */
+#define __CM4_REV                 0x0001   /*!< Core revision r0p1                                       */
+#define __MPU_PRESENT             0U       /*!< GD32F3x0 do not provide MPU                              */
+#define __NVIC_PRIO_BITS          4U       /*!< GD32F3x0 uses 4 bits for the priority levels             */
+#define __Vendor_SysTickConfig    0U       /*!< set to 1 if different sysTick config is used             */
+#define __FPU_PRESENT             1U       /*!< FPU present                                              */
+
+/* define interrupt number */
+typedef enum IRQn
+{
+    /* Cortex-M4 processor exceptions numbers */
+    NonMaskableInt_IRQn          = -14,    /*!< 2 non maskable interrupt                                 */
+    MemoryManagement_IRQn        = -12,    /*!< 4 Cortex-M4 memory management interrupt                  */
+    BusFault_IRQn                = -11,    /*!< 5 Cortex-M4 bus fault interrupt                          */
+    UsageFault_IRQn              = -10,    /*!< 6 Cortex-M4 usage fault interrupt                        */
+    SVCall_IRQn                  = -5,     /*!< 11 Cortex-M4 SV call interrupt                           */
+    DebugMonitor_IRQn            = -4,     /*!< 12 Cortex-M4 debug monitor interrupt                     */
+    PendSV_IRQn                  = -2,     /*!< 14 Cortex-M4 pend SV interrupt                           */
+    SysTick_IRQn                 = -1,     /*!< 15 Cortex-M4 system tick interrupt                       */
+    /* interruput numbers */
+    WWDGT_IRQn                   = 0,      /*!< window watchdog timer interrupt                          */
+    LVD_IRQn                     = 1,      /*!< LVD through EXTI line detect interrupt                   */
+    RTC_IRQn                     = 2,      /*!< RTC interrupt                                            */
+    FMC_IRQn                     = 3,      /*!< FMC interrupt                                            */
+    RCU_CTC_IRQn                 = 4,      /*!< RCU and CTC interrupt                                    */
+    EXTI0_1_IRQn                 = 5,      /*!< EXTI line 0 and 1 interrupts                             */
+    EXTI2_3_IRQn                 = 6,      /*!< EXTI line 2 and 3 interrupts                             */
+    EXTI4_15_IRQn                = 7,      /*!< EXTI line 4 to 15 interrupts                             */
+    TSI_IRQn                     = 8,      /*!< TSI Interrupt                                            */
+    DMA_Channel0_IRQn            = 9,      /*!< DMA channel 0 interrupt                                  */
+    DMA_Channel1_2_IRQn          = 10,     /*!< DMA channel 1 and channel 2 interrupts                   */
+    DMA_Channel3_4_IRQn          = 11,     /*!< DMA channel 3 and channel 4 interrupts                   */
+    ADC_CMP_IRQn                 = 12,     /*!< ADC, CMP0 and CMP1 interrupts                            */
+    TIMER0_BRK_UP_TRG_COM_IRQn   = 13,     /*!< TIMER0 break, update, trigger and commutation interrupts */
+    TIMER0_Channel_IRQn          = 14,     /*!< TIMER0 channel capture compare interrupts                */
+    TIMER1_IRQn                  = 15,     /*!< TIMER1 interrupt                                         */
+    TIMER2_IRQn                  = 16,     /*!< TIMER2 interrupt                                         */
+#ifdef GD32F350
+    TIMER5_DAC_IRQn              = 17,     /*!< TIMER5 and DAC interrupts                                */
+#endif /* GD32F350 */
+    TIMER13_IRQn                 = 19,     /*!< TIMER13 interrupt                                        */
+    TIMER14_IRQn                 = 20,     /*!< TIMER14 interrupt                                        */
+    TIMER15_IRQn                 = 21,     /*!< TIMER15 interrupt                                        */
+    TIMER16_IRQn                 = 22,     /*!< TIMER16 interrupt                                        */
+    I2C0_EV_IRQn                 = 23,     /*!< I2C0 event interrupt                                     */
+    I2C1_EV_IRQn                 = 24,     /*!< I2C1 event interrupt                                     */
+    SPI0_IRQn                    = 25,     /*!< SPI0 interrupt                                           */
+    SPI1_IRQn                    = 26,     /*!< SPI1 interrupt                                           */
+    USART0_IRQn                  = 27,     /*!< USART0 interrupt                                         */
+    USART1_IRQn                  = 28,     /*!< USART1 interrupt                                         */
+#ifdef GD32F350
+    CEC_IRQn                     = 30,     /*!< CEC interrupt                                            */
+#endif /* GD32F350 */
+    I2C0_ER_IRQn                 = 32,     /*!< I2C0 error interrupt                                     */
+    I2C1_ER_IRQn                 = 34,     /*!< I2C1 error interrupt                                     */
+    DMA_Channel5_6_IRQn          = 48,     /*!< DMA channel 5 and channel 6 interrupts                   */
+#ifdef GD32F350
+    USBFS_WKUP_IRQn              = 42,     /*!< USBFS wakeup interrupt                                   */
+    USBFS_IRQn                   = 67,     /*!< USBFS global interrupt                                   */
+#endif /* GD32F350 */
+} IRQn_Type;
+
+/* includes */
+#include "core_cm4.h"
+#include "system_gd32f3x0.h"
+#include <stdint.h>
+
+/* enum definitions */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+typedef enum {RESET = 0, SET = !RESET} FlagStatus;
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
+
+/* bit operations */
+#define REG32(addr)                  (*(volatile uint32_t *)(uint32_t)(addr))
+#define REG16(addr)                  (*(volatile uint16_t *)(uint32_t)(addr))
+#define REG8(addr)                   (*(volatile uint8_t *)(uint32_t)(addr))
+#define BIT(x)                       ((uint32_t)((uint32_t)0x01U<<(x)))
+#define BITS(start, end)             ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 
+#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
+
+/* main flash and SRAM memory map */
+#define FLASH_BASE            ((uint32_t)0x08000000U)       /*!< main FLASH base address          */
+#define SRAM_BASE             ((uint32_t)0x20000000U)       /*!< SRAM base address                */
+/* SRAM and peripheral base bit-band region */
+#define SRAM_BB_BASE          ((uint32_t)0x22000000U)       /*!< SRAM bit-band base address       */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U)       /*!< peripheral bit-band base address */
+/* peripheral memory map */
+#define APB1_BUS_BASE         ((uint32_t)0x40000000U)       /*!< apb1 base address                */
+#define APB2_BUS_BASE         ((uint32_t)0x40010000U)       /*!< apb2 base address                */
+#define AHB1_BUS_BASE         ((uint32_t)0x40020000U)       /*!< ahb1 base address                */
+#define AHB2_BUS_BASE         ((uint32_t)0x48000000U)       /*!< ahb2 base address                */
+/* advanced peripheral bus 1 memory map */
+#define TIMER_BASE            (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address               */
+#define RTC_BASE              (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address                 */
+#define WWDGT_BASE            (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address               */
+#define FWDGT_BASE            (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address               */
+#define SPI_BASE              (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address                 */
+#define USART_BASE            (APB1_BUS_BASE + 0x00004400U) /*!< USART base address               */
+#define I2C_BASE              (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address                 */
+#define PMU_BASE              (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address                 */
+#define DAC_BASE              (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address                 */
+#define CEC_BASE              (APB1_BUS_BASE + 0x00007800U) /*!< CEC base address                 */
+#define CTC_BASE              (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address                 */
+/* advanced peripheral bus 2 memory map */
+#define SYSCFG_BASE           (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address              */
+#define CMP_BASE              (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address                 */
+#define EXTI_BASE             (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address                */
+#define ADC_BASE              (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address                 */
+/* advanced high performance bus 1 memory map */
+#define DMA_BASE              (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address                 */
+#define DMA_CHANNEL_BASE      (DMA_BASE + 0x00000008U)      /*!< DMA channel base address         */
+#define RCU_BASE              (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address                 */
+#define FMC_BASE              (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address                 */
+#define CRC_BASE              (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address                 */
+#define TSI_BASE              (AHB1_BUS_BASE + 0x00004000U) /*!< TSI base address                 */
+#define USBFS_BASE            (AHB1_BUS_BASE + 0x0FFE0000U) /*!< USBFS base address               */
+/* advanced high performance bus 2 memory map */
+#define GPIO_BASE             (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address                 */
+/* option byte and debug memory map */
+#define OB_BASE               ((uint32_t)0x1FFFF800U)       /*!< OB base address                  */
+#define DBG_BASE              ((uint32_t)0xE0042000U)       /*!< DBG base address                 */
+
+/* define marco USE_STDPERIPH_DRIVER */
+#if !defined  USE_STDPERIPH_DRIVER
+#define USE_STDPERIPH_DRIVER
+#endif 
+#ifdef USE_STDPERIPH_DRIVER
+#include "gd32f3x0_libopt.h"
+#endif /* USE_STDPERIPH_DRIVER */
+
+#ifdef cplusplus
+}
+#endif
+#endif

Librarys/CMSIS/GD32F1x0/Include/system_gd32f1x0.h → Librarys/CMSIS/GD32F3x0/Include/system_gd32f3x0.h

@@ -1,7 +1,7 @@
 /*!
-    \file  system_gd32f1x0.h
-    \brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for
-           GD32F1x0 Device Series
+    \file  system_gd32f3x0.h
+    \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
+           GD32F3x0 Device Series
 */
 
 /* Copyright (c) 2012 ARM LIMITED
@@ -33,8 +33,8 @@
 
 /* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
 
-#ifndef SYSTEM_GD32F1X0_H
-#define SYSTEM_GD32F1X0_H
+#ifndef SYSTEM_GD32F3X0_H
+#define SYSTEM_GD32F3X0_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -55,4 +55,4 @@ extern void SystemCoreClockUpdate (void);
 }
 #endif
 
-#endif /* SYSTEM_GD32F1X0_H */
+#endif /* SYSTEM_GD32F3X0_H */

Librarys/CMSIS/GD32F1x0/Source/startup_gd32f1x0.s → Librarys/CMSIS/GD32F3x0/Source/startup_gd32f3x0.s

@@ -1,14 +1,11 @@
 ;/*!
-;    \file  startup_gd32f1x0.s
+;    \file  startup_gd32f3x0.s
 ;    \brief start up file
-
-;    2014-12-26, V1.0.0, firmware for GD32F1x0(x=3,5)
-;    2016-01-15, V2.0.0, firmware for GD32F1x0(x=3,5,7,9)
-;    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-;    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-;    2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+;
+;    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+;    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 ;*/
-
+;
 ;/*
 ;    Copyright (c) 2019, GigaDevice Semiconductor Inc.
 ;
@@ -89,7 +86,7 @@ __Vectors       DCD     __initial_sp                      ; Top of Stack
                 DCD     LVD_IRQHandler                    ; 17:LVD through EXTI Line detect
                 DCD     RTC_IRQHandler                    ; 18:RTC through EXTI Line
                 DCD     FMC_IRQHandler                    ; 19:FMC
-                DCD     RCU_IRQHandler                    ; 20:RCU
+                DCD     RCU_CTC_IRQHandler                ; 20:RCU and CTC
                 DCD     EXTI0_1_IRQHandler                ; 21:EXTI Line 0 and EXTI Line 1
                 DCD     EXTI2_3_IRQHandler                ; 22:EXTI Line 2 and EXTI Line 3
                 DCD     EXTI4_15_IRQHandler               ; 23:EXTI Line 4 to EXTI Line 15
@@ -99,7 +96,7 @@ __Vectors       DCD     __initial_sp                      ; Top of Stack
                 DCD     DMA_Channel3_4_IRQHandler         ; 27:DMA Channel 3 and DMA Channel 4
                 DCD     ADC_CMP_IRQHandler                ; 28:ADC and Comparator 0-1
                 DCD     TIMER0_BRK_UP_TRG_COM_IRQHandler  ; 29:TIMER0 Break,Update,Trigger and Commutation
-                DCD     TIMER0_Channel_IRQHandler         ; 30:TIMER0 Channel
+                DCD     TIMER0_Channel_IRQHandler         ; 30:TIMER0 Channel Capture Compare
                 DCD     TIMER1_IRQHandler                 ; 31:TIMER1
                 DCD     TIMER2_IRQHandler                 ; 32:TIMER2
                 DCD     TIMER5_DAC_IRQHandler             ; 33:TIMER5 and DAC
@@ -120,28 +117,23 @@ __Vectors       DCD     __initial_sp                      ; Top of Stack
                 DCD     I2C0_ER_IRQHandler                ; 48:I2C0 Error
                 DCD     0                                 ; Reserved
                 DCD     I2C1_ER_IRQHandler                ; 50:I2C1 Error
-                DCD     I2C2_EV_IRQHandler                ; 51:I2C2 Event
-                DCD     I2C2_ER_IRQHandler                ; 52:I2C2 Error
-                DCD     USBD_LP_IRQHandler                ; 53:USBD LP
-                DCD     USBD_HP_IRQHandler                ; 54:USBD HP
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
-                DCD     USBDWakeUp_IRQHandler             ; 58:USBD Wakeup
-                DCD     CAN0_TX_IRQHandler                ; 59:CAN0 TX
-                DCD     CAN0_RX0_IRQHandler               ; 60:CAN0 RX0
-                DCD     CAN0_RX1_IRQHandler               ; 61:CAN0 RX1
-                DCD     CAN0_SCE_IRQHandler               ; 62:CAN0 SCE
-                DCD     SLCD_IRQHandler                   ; 63:SLCD
-                DCD     DMA_Channel5_6_IRQHandler         ; 64:DMA Channel5 and Channel6 
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
-                DCD     SPI2_IRQHandler                   ; 67:SPI2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     USBFS_WKUP_IRQHandler             ; 58:USBFS Wakeup
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
+                DCD     DMA_Channel5_6_IRQHandler         ; 64:DMA Channel5 and Channel6 
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
@@ -155,10 +147,9 @@ __Vectors       DCD     __initial_sp                      ; Top of Stack
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
                 DCD     0                                 ; Reserved
-                DCD     CAN1_TX_IRQHandler                ; 86:CAN1 TX
-                DCD     CAN1_RX0_IRQHandler               ; 87:CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler               ; 88:CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler               ; 89:CAN1 SCE
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     USBFS_IRQHandler                  ; 83:USBFS
 __Vectors_End
 
 __Vectors_Size  EQU     __Vectors_End - __Vectors
@@ -227,7 +218,7 @@ Default_Handler PROC
                 EXPORT  LVD_IRQHandler                    [WEAK]
                 EXPORT  RTC_IRQHandler                    [WEAK]
                 EXPORT  FMC_IRQHandler                    [WEAK]
-                EXPORT  RCU_IRQHandler                    [WEAK]
+                EXPORT  RCU_CTC_IRQHandler                [WEAK]
                 EXPORT  EXTI0_1_IRQHandler                [WEAK]
                 EXPORT  EXTI2_3_IRQHandler                [WEAK]
                 EXPORT  EXTI4_15_IRQHandler               [WEAK]
@@ -254,29 +245,16 @@ Default_Handler PROC
                 EXPORT  CEC_IRQHandler                    [WEAK]
                 EXPORT  I2C0_ER_IRQHandler                [WEAK]
                 EXPORT  I2C1_ER_IRQHandler                [WEAK]
-                EXPORT  I2C2_EV_IRQHandler                [WEAK]
-                EXPORT  I2C2_ER_IRQHandler                [WEAK]
-                EXPORT  USBD_LP_IRQHandler                [WEAK]
-                EXPORT  USBD_HP_IRQHandler                [WEAK]
-                EXPORT  USBDWakeUp_IRQHandler             [WEAK]
-                EXPORT  CAN0_TX_IRQHandler                [WEAK]
-                EXPORT  CAN0_RX0_IRQHandler               [WEAK]
-                EXPORT  CAN0_RX1_IRQHandler               [WEAK]
-                EXPORT  CAN0_SCE_IRQHandler               [WEAK]
-                EXPORT  SLCD_IRQHandler                   [WEAK]
+                EXPORT  USBFS_WKUP_IRQHandler             [WEAK]
                 EXPORT  DMA_Channel5_6_IRQHandler         [WEAK]
-                EXPORT  SPI2_IRQHandler                   [WEAK]
-                EXPORT  CAN1_TX_IRQHandler                [WEAK]
-                EXPORT  CAN1_RX0_IRQHandler               [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler               [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler               [WEAK]
+                EXPORT  USBFS_IRQHandler                  [WEAK]
 
 ;/* external interrupts handler */
 WWDGT_IRQHandler
 LVD_IRQHandler
 RTC_IRQHandler
 FMC_IRQHandler
-RCU_IRQHandler
+RCU_CTC_IRQHandler
 EXTI0_1_IRQHandler
 EXTI2_3_IRQHandler
 EXTI4_15_IRQHandler
@@ -303,22 +281,10 @@ USART1_IRQHandler
 CEC_IRQHandler
 I2C0_ER_IRQHandler
 I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-USBD_LP_IRQHandler
-USBD_HP_IRQHandler
-USBDWakeUp_IRQHandler
-CAN0_TX_IRQHandler
-CAN0_RX0_IRQHandler
-CAN0_RX1_IRQHandler
-CAN0_SCE_IRQHandler
-SLCD_IRQHandler
+USBFS_WKUP_IRQHandler
 DMA_Channel5_6_IRQHandler
-SPI2_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
+USBFS_IRQHandler
+
                 B       .
                 ENDP
 

Librarys/CMSIS/GD32F3x0/Source/system_gd32f3x0.c

@@ -0,0 +1,808 @@
+/*!
+    \file  system_gd32f3x0.c
+    \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
+           GD32F3x0 Device Series
+*/
+
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#include "gd32f3x0.h"
+
+/* system frequency define */
+#define __IRC8M           (IRC8M_VALUE)            /* internal 8 MHz RC oscillator frequency */
+#define __HXTAL           (HXTAL_VALUE)            /* high speed crystal oscillator frequency */
+#define __SYS_OSC_CLK     (__IRC8M)                /* main oscillator frequency */
+
+#define VECT_TAB_OFFSET  (uint32_t)0x00            /* vector table base offset */
+
+/* select a system clock by uncommenting the following line */
+#if defined (GD32F330)
+//#define __SYSTEM_CLOCK_8M_HXTAL              (__HXTAL)
+//#define __SYSTEM_CLOCK_8M_IRC8M              (__IRC8M)
+//#define __SYSTEM_CLOCK_72M_PLL_HXTAL         (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2    (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2     (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_84M_PLL_HXTAL           (uint32_t)(84000000)
+#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2    (uint32_t)(84000000)
+#endif /* GD32F330 */
+
+#if defined (GD32F350)
+//#define __SYSTEM_CLOCK_8M_HXTAL              (__HXTAL)
+//#define __SYSTEM_CLOCK_8M_IRC8M              (__IRC8M)
+//#define __SYSTEM_CLOCK_72M_PLL_HXTAL         (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2    (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_84M_PLL_HXTAL         (uint32_t)(84000000)
+//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2    (uint32_t)(84000000)
+//#define __SYSTEM_CLOCK_96M_PLL_HXTAL         (uint32_t)(96000000)
+//#define __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2      (uint32_t)(96000000)
+//#define __SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2     (uint32_t)(96000000)
+#define __SYSTEM_CLOCK_108M_PLL_HXTAL        (uint32_t)(108000000)
+//#define __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2   (uint32_t)(108000000)
+#endif /* GD32F350 */
+
+#define SEL_IRC8M       0x00
+#define SEL_HXTAL       0x01
+#define SEL_PLL         0x02
+
+/* set the system clock frequency and declare the system clock configuration function */
+#ifdef __SYSTEM_CLOCK_8M_HXTAL
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
+static void system_clock_8m_hxtal(void);
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
+static void system_clock_72m_hxtal(void);
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
+static void system_clock_72m_irc8m(void);
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2;
+static void system_clock_72m_irc48m(void);
+
+#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_HXTAL;
+static void system_clock_84m_hxtal(void);
+
+#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2;
+static void system_clock_84m_irc8m(void);
+
+#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL;
+static void system_clock_96m_hxtal(void);
+
+#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2;
+static void system_clock_96m_irc8m(void);
+
+#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2;
+static void system_clock_96m_irc48m(void);
+
+#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
+static void system_clock_108m_hxtal(void);
+
+#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2;
+static void system_clock_108m_irc8m(void);
+
+#else
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
+static void system_clock_8m_irc8m(void);
+#endif /* __SYSTEM_CLOCK_8M_HXTAL */
+
+/* configure the system clock */
+static void system_clock_config(void);
+
+/*!
+    \brief      setup the microcontroller system, initialize the system
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SystemInit (void)
+{
+#if (defined(GD32F350))
+    RCU_APB2EN = BIT(0);
+    CMP_CS |= (CMP_CS_CMP1MSEL | CMP_CS_CMP0MSEL);
+#endif /* GD32F350 */
+    if(((FMC_OBSTAT & OB_OBSTAT_PLEVEL_HIGH) != OB_OBSTAT_PLEVEL_HIGH) &&
+        (((FMC_OBSTAT >> 13)& 0x1) == SET)){
+    FMC_KEY = UNLOCK_KEY0;
+    FMC_KEY = UNLOCK_KEY1 ;
+    FMC_OBKEY = UNLOCK_KEY0;
+    FMC_OBKEY = UNLOCK_KEY1 ;
+    FMC_CTL |= FMC_CTL_OBER;
+    FMC_CTL |= FMC_CTL_START;
+    while((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY));
+    FMC_CTL &= ~FMC_CTL_OBER;
+    FMC_CTL |= FMC_CTL_OBPG; 
+    if((FMC_OBSTAT & OB_OBSTAT_PLEVEL_HIGH) == OB_OBSTAT_PLEVEL_NO){
+         OB_SPC = FMC_NSPC;
+    }else if ((FMC_OBSTAT & OB_OBSTAT_PLEVEL_HIGH) == OB_OBSTAT_PLEVEL_LOW){
+         OB_SPC = FMC_LSPC;
+    }
+    OB_USER = OB_USER_DEFAULT & ((uint8_t)(FMC_OBSTAT >> 8));
+    OB_DATA0 = ((uint8_t)(FMC_OBSTAT >> 16));
+    OB_DATA1 = ((uint8_t)(FMC_OBSTAT >> 24));
+    OB_WP0 = ((uint8_t)(FMC_WP));
+    OB_WP1 = ((uint8_t)(FMC_WP >> 8));
+    while((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY));
+    FMC_CTL &= ~FMC_CTL_OBPG;
+    FMC_CTL &= ~FMC_CTL_OBWEN;
+    FMC_CTL |= FMC_CTL_LK;
+    }
+    /* FPU settings */
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* enable IRC8M */
+    RCU_CTL0 |= RCU_CTL0_IRC8MEN;
+    while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
+    }
+    /* reset RCU */
+    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
+                  RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
+#if (defined(GD32F350))
+    RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC);
+    RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2);
+#endif /* GD32F350 */
+    RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
+    RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL);
+    RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
+    RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
+    RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
+    RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
+    RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN;
+    RCU_INT = 0x00000000U;
+    RCU_ADDINT = 0x00000000U;
+    
+    /* configure system clock */
+    system_clock_config();
+    
+#ifdef VECT_TAB_SRAM
+    nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
+#else
+    nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
+#endif
+}
+
+/*!
+    \brief      configure the system clock
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_config(void)
+{
+#ifdef __SYSTEM_CLOCK_8M_HXTAL
+    system_clock_8m_hxtal();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+    system_clock_72m_hxtal();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
+    system_clock_72m_irc8m();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
+    system_clock_72m_irc48m();
+#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL)
+    system_clock_84m_hxtal();
+#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2)
+    system_clock_84m_irc8m();
+#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
+    system_clock_96m_hxtal();
+#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2)
+    system_clock_96m_irc8m();
+#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2)
+    system_clock_96m_irc48m();
+#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
+    system_clock_108m_hxtal();
+#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2)
+    system_clock_108m_irc8m();
+#else
+    system_clock_8m_irc8m();
+#endif /* __SYSTEM_CLOCK_8M_HXTAL */
+}
+
+#ifdef __SYSTEM_CLOCK_8M_HXTAL
+/*!
+    \brief      configure the system clock to 8M by HXTAL
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_8m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL0 |= RCU_CTL0_HXTALEN;
+    
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
+    }
+    while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));    
+    /* if fail */
+    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
+        return;
+    }
+    
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+    
+    /* select HXTAL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
+    
+    /* wait until HXTAL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 72M by PLL which selects HXTAL as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_72m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL0 |= RCU_CTL0_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
+    }
+    while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+    /* if fail */
+    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
+        return;
+    }
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* PLL = HXTAL * 9 = 72 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL9);
+
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
+/*!
+    \brief      configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_72m_irc8m(void)
+{
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+    /* PLL = (IRC8M/2) * 18 = 72 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
+    RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
+    
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
+/*!
+    \brief      configure the system clock to 72M by PLL which selects IRC48M/2 as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_72m_irc48m(void)
+{    
+    /* enable IRC48M */
+    RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN;
+
+    /* wait until IRC48M is stable*/
+    while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)){
+    }
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+    /* PLL = (IRC48M/2) * 3 = 96 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
+    RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
+    RCU_CFG1 |= (RCU_PLL_PREDV2 |RCU_PLLPRESEL_IRC48M);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL3);
+           
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 84M by PLL which selects HXTAL as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_84m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    /* enable HXTAL */
+    RCU_CTL0 |= RCU_CTL0_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
+    }
+    while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+    /* if fail */
+    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
+        return;
+    }
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* PLL = HXTAL /2 * 21 = 84 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
+    RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
+    RCU_CFG1 |= RCU_PLL_PREDV2;
+    RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL21);
+
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2)
+/*!
+    \brief      configure the system clock to 84M by PLL which selects IRC8M/2 as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_84m_irc8m(void)
+{
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+    /* PLL = (IRC8M/2) * 21 = 84 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
+    RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL21);
+    
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 96M by PLL which selects HXTAL as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_96m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    /* enable HXTAL */
+    RCU_CTL0 |= RCU_CTL0_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
+    }
+    while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+    /* if fail */
+    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
+        return;
+    }
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* PLL = HXTAL /2 * 24 = 96 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
+    RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
+    RCU_CFG1 |= RCU_PLL_PREDV2;
+    RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL24);
+
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2)
+/*!
+    \brief      configure the system clock to 96M by PLL which selects IRC8M/2 as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_96m_irc8m(void)
+{
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+    /* PLL = (IRC8M/2) * 24 = 96 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
+    RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL24);
+    
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2)
+/*!
+    \brief      configure the system clock to 96M by PLL which selects IRC48M/2 as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_96m_irc48m(void)
+{    
+    /* enable IRC48M */
+    RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN;
+
+    /* wait until IRC48M is stable*/
+    while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)){
+    }
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+    /* PLL = (IRC48M/2) * 4 = 96 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
+    RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
+    RCU_CFG1 |= (RCU_PLL_PREDV2 |RCU_PLLPRESEL_IRC48M);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL4);
+           
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 84M by PLL which selects HXTAL as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_108m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL0 |= RCU_CTL0_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
+    }
+    while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+    /* if fail */
+    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
+        return;
+    }
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* PLL = HXTAL /2 * 27 = 108 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
+    RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
+    RCU_CFG1 |= RCU_PLL_PREDV2;
+    RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL27);
+
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2)
+/*!
+    \brief      configure the system clock to 108M by PLL which selects IRC8M/2 as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_108m_irc8m(void)
+{
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+    /* PLL = (IRC8M/2) * 27 = 108 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
+    RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL27);
+    
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#else
+/*!
+    \brief      configure the system clock to 8M by IRC8M
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_8m_irc8m(void)
+{
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+    
+    /* select IRC8M as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
+    
+    /* wait until IRC8M is selected as system clock */
+    while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
+    }
+}
+#endif /* __SYSTEM_CLOCK_8M_HXTAL */
+
+/*!
+    \brief      update the SystemCoreClock with current core clock retrieved from cpu registers
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SystemCoreClockUpdate (void)
+{
+    uint32_t sws = 0U;
+    uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
+    /* exponent of AHB clock divider */
+    const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+    
+    sws = GET_BITS(RCU_CFG0, 2, 3);
+    switch(sws){
+    /* IRC8M is selected as CK_SYS */
+    case SEL_IRC8M:
+        SystemCoreClock = IRC8M_VALUE;
+        break;
+    /* HXTAL is selected as CK_SYS */
+    case SEL_HXTAL:
+        SystemCoreClock = HXTAL_VALUE;
+        break;
+    /* PLL is selected as CK_SYS */
+    case SEL_PLL:
+        /* get the value of PLLMF[3:0] */
+        pllmf = GET_BITS(RCU_CFG0, 18, 21);
+        pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
+        pllmf5 = GET_BITS(RCU_CFG1, 31, 31);
+        /* high 16 bits */
+        if(1U == pllmf4){
+            pllmf += 17U;
+        }else{
+            pllmf += 2U;
+        }
+        if(1U == pllmf5){
+            pllmf += 31U;
+        }
+        /* PLL clock source selection, HXTAL or IRC8M/2 */
+        pllsel = GET_BITS(RCU_CFG0, 16, 16);
+        if(0U != pllsel){
+            prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
+            if(0U == pllpresel){
+                SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
+            }else{
+                SystemCoreClock = (IRC48M_VALUE / prediv) * pllmf;
+            }
+        }else{
+            SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
+        }
+        break;
+    /* IRC8M is selected as CK_SYS */
+    default:
+        SystemCoreClock = IRC8M_VALUE;
+        break;
+    }
+    /* calculate AHB clock frequency */
+    idx = GET_BITS(RCU_CFG0, 4, 7);
+    clk_exp = ahb_exp[idx];
+    SystemCoreClock >>= clk_exp;
+}

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_adc.h

@@ -1,379 +0,0 @@
-/*!
-    \file  gd32f1x0_adc.h
-    \brief definitions for the ADC
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F1X0_ADC_H
-#define GD32F1X0_ADC_H
-
-#include "gd32f1x0.h"
-
-/* ADC definitions */
-#define ADC                             ADC_BASE
-
-/* registers definitions */
-#define ADC_STAT                        REG32(ADC + 0x00000000U)            /*!< ADC status register */
-#define ADC_CTL0                        REG32(ADC + 0x00000004U)            /*!< ADC control register 0 */
-#define ADC_CTL1                        REG32(ADC + 0x00000008U)            /*!< ADC control register 1 */
-#define ADC_SAMPT0                      REG32(ADC + 0x0000000CU)            /*!< ADC sampling time register 0 */
-#define ADC_SAMPT1                      REG32(ADC + 0x00000010U)            /*!< ADC sampling time register 1 */
-#define ADC_IOFF0                       REG32(ADC + 0x00000014U)            /*!< ADC inserted channel data offset register 0 */
-#define ADC_IOFF1                       REG32(ADC + 0x00000018U)            /*!< ADC inserted channel data offset register 1 */
-#define ADC_IOFF2                       REG32(ADC + 0x0000001CU)            /*!< ADC inserted channel data offset register 2 */
-#define ADC_IOFF3                       REG32(ADC + 0x00000020U)            /*!< ADC inserted channel data offset register 3 */
-#define ADC_WDHT                        REG32(ADC + 0x00000024U)            /*!< ADC watchdog high threshold register */
-#define ADC_WDLT                        REG32(ADC + 0x00000028U)            /*!< ADC watchdog low threshold register */
-#define ADC_RSQ0                        REG32(ADC + 0x0000002CU)            /*!< ADC regular sequence register 0 */
-#define ADC_RSQ1                        REG32(ADC + 0x00000030U)            /*!< ADC regular sequence register 1 */
-#define ADC_RSQ2                        REG32(ADC + 0x00000034U)            /*!< ADC regular sequence register 2 */
-#define ADC_ISQ                         REG32(ADC + 0x00000038U)            /*!< ADC inserted sequence register */
-#define ADC_IDATA0                      REG32(ADC + 0x0000003CU)            /*!< ADC inserted data register 0 */
-#define ADC_IDATA1                      REG32(ADC + 0x00000040U)            /*!< ADC inserted data register 1 */
-#define ADC_IDATA2                      REG32(ADC + 0x00000044U)            /*!< ADC inserted data register 2 */
-#define ADC_IDATA3                      REG32(ADC + 0x00000048U)            /*!< ADC inserted data register 3 */
-#define ADC_RDATA                       REG32(ADC + 0x0000004CU)            /*!< ADC regular data register */
-
-#ifdef GD32F170_190
-#define ADC_OVSAMPCTL                   REG32(ADC + 0x00000080U)            /*!< ADC oversampling control register */
-#endif /* GD32F170_190 */
-
-/* bits definitions */
-/* ADC_STAT */
-#define ADC_STAT_WDE                    BIT(0)                              /*!< analog watchdog event flag */
-#define ADC_STAT_EOC                    BIT(1)                              /*!< end of conversion flag */
-#define ADC_STAT_EOIC                   BIT(2)                              /*!< inserted channel end of conversion flag */
-#define ADC_STAT_STIC                   BIT(3)                              /*!< inserted channel start flag */
-#define ADC_STAT_STRC                   BIT(4)                              /*!< regular channel start flag */
-
-/* ADC_CTL0 */
-#define ADC_CTL0_WDCHSEL                BITS(0,4)                           /*!< analog watchdog channel select bits */
-#define ADC_CTL0_EOCIE                  BIT(5)                              /*!< interrupt enable for EOC */
-#define ADC_CTL0_WDEIE                  BIT(6)                              /*!< analog watchdog interrupt enable */
-#define ADC_CTL0_EOICIE                 BIT(7)                              /*!< interrupt enable for inserted channels */
-#define ADC_CTL0_SM                     BIT(8)                              /*!< scan mode */
-#define ADC_CTL0_WDSC                   BIT(9)                              /*!< when in scan mode, analog watchdog is effective on a single channel */
-#define ADC_CTL0_ICA                    BIT(10)                             /*!< automatic inserted group conversion */
-#define ADC_CTL0_DISRC                  BIT(11)                             /*!< discontinuous mode on regular channels */
-#define ADC_CTL0_DISIC                  BIT(12)                             /*!< discontinuous mode on inserted channels */
-#define ADC_CTL0_DISNUM                 BITS(13,15)                         /*!< discontinuous mode channel count */
-#define ADC_CTL0_IWDEN                  BIT(22)                             /*!< analog watchdog enable on inserted channels */
-#define ADC_CTL0_RWDEN                  BIT(23)                             /*!< analog watchdog enable on regular channels */
-
-#ifdef GD32F170_190
-#define ADC_CTL0_DRES                   BITS(24,25)                         /*!< ADC data resolution */
-#endif /* GD32F170_190 */
-
-/* ADC_CTL1 */
-#define ADC_CTL1_ADCON                  BIT(0)                              /*!< ADC converter on */
-#define ADC_CTL1_CTN                    BIT(1)                              /*!< continuous conversion */
-#define ADC_CTL1_CLB                    BIT(2)                              /*!< ADC calibration */
-#define ADC_CTL1_RSTCLB                 BIT(3)                              /*!< reset calibration */
-#define ADC_CTL1_DMA                    BIT(8)                              /*!< direct memory access mode */
-#define ADC_CTL1_DAL                    BIT(11)                             /*!< data alignment */
-#define ADC_CTL1_ETSIC                  BITS(12,14)                         /*!< external trigger select for inserted channel */
-#define ADC_CTL1_ETEIC                  BIT(15)                             /*!< external trigger enable for inserted channel */
-#define ADC_CTL1_ETSRC                  BITS(17,19)                         /*!< external trigger select for regular channel */
-#define ADC_CTL1_ETERC                  BIT(20)                             /*!< external trigger enable for regular channel */
-#define ADC_CTL1_SWICST                 BIT(21)                             /*!< start on inserted channel */
-#define ADC_CTL1_SWRCST                 BIT(22)                             /*!< start on regular channel */
-#define ADC_CTL1_TSVREN                 BIT(23)                             /*!< enable channel 16 and 17 */
-#define ADC_CTL1_VBETEN                 BIT(24)                             /*!< VBAT enable */
-
-/* ADC_SAMPTx x=0..1 */
-#define ADC_SAMPTX_SPTN                 BITS(0,2)                           /*!< channel n(n=0..18) sample time selection */
-
-/* ADC_IOFFx x=0..3 */
-#define ADC_IOFFX_IOFF                  BITS(0,11)                          /*!< data offset for inserted channel x */
-
-/* ADC_WDHT */
-#define ADC_WDHT_WDHT                   BITS(0,11)                          /*!< analog watchdog high threshold */
-
-/* ADC_WDLT */
-#define ADC_WDLT_WDLT                   BITS(0,11)                          /*!< analog watchdog low threshold */
-
-/* ADC_RSQx x=0..2 */
-#define ADC_RSQX_RSQN                   BITS(0,4)                           /*!< n conversion in regular sequence */
-#define ADC_RSQ0_RL                     BITS(20,23)                         /*!< regular channel sequence length */
-
-/* ADC_ISQ */
-#define ADC_ISQ_ISQN                    BITS(0,4)                           /*!< n conversion in regular sequence */
-#define ADC_ISQ_IL                      BITS(20,21)                         /*!< inserted sequence length */
-
-/* ADC_IDATAx x=0..3*/
-#define ADC_IDATAX_IDATAN               BITS(0,15)                          /*!< inserted channel x conversion data */
-
-/* ADC_RDT */
-#define ADC_RDATA_RDATA                 BITS(0,15)                          /*!< regular channel data */
-
-#ifdef GD32F170_190
-/* ADC_OVCTL */
-#define ADC_OVSAMPCTL_OVSEN             BIT(0)                              /*!< oversampling enable */
-#define ADC_OVSAMPCTL_OVSR              BITS(2,4)                           /*!< oversampling ratio */
-#define ADC_OVSAMPCTL_OVSS              BITS(5,8)                           /*!< oversampling shift */
-#define ADC_OVSAMPCTL_TOVS              BIT(9)                              /*!< triggered oversampling */
-#endif /* GD32F170_190 */
-
-/* constants definitions */
-/* ADC flag definitions */
-#define ADC_FLAG_WDE                    ADC_STAT_WDE                        /*!< analog watchdog event flag */
-#define ADC_FLAG_EOC                    ADC_STAT_EOC                        /*!< end of group conversion flag */
-#define ADC_FLAG_EOIC                   ADC_STAT_EOIC                       /*!< end of inserted channel group conversion flag */
-#define ADC_FLAG_STIC                   ADC_STAT_STIC                       /*!< start flag of inserted channel group */
-#define ADC_FLAG_STRC                   ADC_STAT_STRC                       /*!< start flag of regular channel group */
-
-/* adc_ctl0 register value */
-#define CTL0_DISNUM(regval)             (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */
-
-/* ADC special function */
-#define ADC_SCAN_MODE                   ADC_CTL0_SM                         /*!< scan mode */
-#define ADC_INSERTED_CHANNEL_AUTO       ADC_CTL0_ICA                        /*!< inserted channel group convert automatically */
-#define ADC_CONTINUOUS_MODE             ADC_CTL1_CTN                        /*!< continuous mode */
-
-/* ADC data alignment */
-#define ADC_DATAALIGN_RIGHT             ((uint32_t)0x00000000U)             /*!< right alignment */
-#define ADC_DATAALIGN_LEFT              ADC_CTL1_DAL                        /*!< left alignment */
-
-/* external trigger select for regular  channel */
-#define CTL1_ETSRC(regval)              (BITS(17,19) & ((uint32_t)(regval) << 17))
-#define ADC_EXTTRIG_REGULAR_T0_CH0      CTL1_ETSRC(0)                       /*!< TIMER0 CH0 event select */
-#define ADC_EXTTRIG_REGULAR_T0_CH1      CTL1_ETSRC(1)                       /*!< TIMER0 CH1 event select */
-#define ADC_EXTTRIG_REGULAR_T0_CH2      CTL1_ETSRC(2)                       /*!< TIMER0 CH2 event select */
-#define ADC_EXTTRIG_REGULAR_T1_CH1      CTL1_ETSRC(3)                       /*!< TIMER1 CH1 event select */
-#define ADC_EXTTRIG_REGULAR_T2_TRGO     CTL1_ETSRC(4)                       /*!< TIMER2 TRGO event select */
-#define ADC_EXTTRIG_REGULAR_T14_CH0     CTL1_ETSRC(5)                       /*!< TIMER14 CH0 event select */
-#define ADC_EXTTRIG_REGULAR_EXTI_11     CTL1_ETSRC(6)                       /*!< external interrupt line 11 */
-#define ADC_EXTTRIG_REGULAR_NONE        CTL1_ETSRC(7)                       /*!< software trigger */
-
-/* external trigger select for inserted channel */
-#define CTL1_ETSIC(regval)              (BITS(12,14) & ((uint32_t)(regval) << 12))
-#define ADC_EXTTRIG_INSERTED_T0_TRGO    CTL1_ETSIC(0)                       /*!< TIMER0 TRGO event select */
-#define ADC_EXTTRIG_INSERTED_T0_CH3     CTL1_ETSIC(1)                       /*!< TIMER0 CH3 event select */
-#define ADC_EXTTRIG_INSERTED_T1_TRGO    CTL1_ETSIC(2)                       /*!< TIMER1 TRGO event select */
-#define ADC_EXTTRIG_INSERTED_T1_CH0     CTL1_ETSIC(3)                       /*!< TIMER1 CH0 event select */
-#define ADC_EXTTRIG_INSERTED_T2_CH3     CTL1_ETSIC(4)                       /*!< TIMER2 CH3 event select */
-#define ADC_EXTTRIG_INSERTED_T14_TRGO   CTL1_ETSIC(5)                       /*!< TIMER14 TRGO event select */
-#define ADC_EXTTRIG_INSERTED_EXTI_15    CTL1_ETSIC(6)                       /*!< external interrupt line 15 */
-#define ADC_EXTTRIG_INSERTED_NONE       CTL1_ETSIC(7)                       /*!< software trigger */
-
-/* adc_samptx register value */
-#define SAMPTX_SPT(regval)              (BITS(0,2) & ((uint32_t)(regval) << 0))
-#define ADC_SAMPLETIME_1POINT5          SAMPTX_SPT(0)                       /*!< 1.5 sampling cycles */
-#define ADC_SAMPLETIME_7POINT5          SAMPTX_SPT(1)                       /*!< 7.5 sampling cycles */
-#define ADC_SAMPLETIME_13POINT5         SAMPTX_SPT(2)                       /*!< 13.5 sampling cycles */
-#define ADC_SAMPLETIME_28POINT5         SAMPTX_SPT(3)                       /*!< 28.5 sampling cycles */
-#define ADC_SAMPLETIME_41POINT5         SAMPTX_SPT(4)                       /*!< 41.5 sampling cycles */
-#define ADC_SAMPLETIME_55POINT5         SAMPTX_SPT(5)                       /*!< 55.5 sampling cycles */
-#define ADC_SAMPLETIME_71POINT5         SAMPTX_SPT(6)                       /*!< 71.5 sampling cycles */
-#define ADC_SAMPLETIME_239POINT5        SAMPTX_SPT(7)                       /*!< 239.5 sampling cycles */
-
-/* ADC data offset for inserted channel x */
-#define IOFFX_IOFF(regval)              (BITS(0,11) & ((uint32_t)(regval) << 0))
-
-/* ADC analog watchdog high threshold  */
-#define WDHT_WDHT(regval)               (BITS(0,11) & ((uint32_t)(regval) << 0))
-
-/* ADC analog watchdog low  threshold */
-#define WDLT_WDLT(regval)               (BITS(0,11) & ((uint32_t)(regval) << 0))
-
-/* ADC regular channel group length */
-#define RSQ0_RL(regval)                 (BITS(20,23) & ((uint32_t)(regval) << 20))
-
-/* ADC inserted channel group length */
-#define ISQ_IL(regval)                  (BITS(20,21) & ((uint32_t)(regval) << 20))
-
-/* ADC resolution definitions */
-#define CTL0_DRES(regval)               (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< ADC resolution */
-#define ADC_RESOLUTION_12B              CTL0_DRES(0)                        /*!< 12-bit ADC resolution */
-#define ADC_RESOLUTION_10B              CTL0_DRES(1)                        /*!< 10-bit ADC resolution */
-#define ADC_RESOLUTION_8B               CTL0_DRES(2)                        /*!< 8-bit ADC resolution */
-#define ADC_RESOLUTION_6B               CTL0_DRES(3)                        /*!< 6-bit ADC resolution */
-
-#ifdef GD32F170_190
-/* ADC oversampling shift */
-#define OVSAMPCTL_OVSS(regval)          (BITS(5,8) & ((uint32_t)(regval) << 5))
-#define ADC_OVERSAMPLING_SHIFT_NONE     OVSAMPCTL_OVSS(0)                   /*!< no oversampling shift */
-#define ADC_OVERSAMPLING_SHIFT_1B       OVSAMPCTL_OVSS(1)                   /*!< 1-bit oversampling shift */
-#define ADC_OVERSAMPLING_SHIFT_2B       OVSAMPCTL_OVSS(2)                   /*!< 2-bit oversampling shift */
-#define ADC_OVERSAMPLING_SHIFT_3B       OVSAMPCTL_OVSS(3)                   /*!< 3-bit oversampling shift */
-#define ADC_OVERSAMPLING_SHIFT_4B       OVSAMPCTL_OVSS(4)                   /*!< 4-bit oversampling shift */
-#define ADC_OVERSAMPLING_SHIFT_5B       OVSAMPCTL_OVSS(5)                   /*!< 5-bit oversampling shift */
-#define ADC_OVERSAMPLING_SHIFT_6B       OVSAMPCTL_OVSS(6)                   /*!< 6-bit oversampling shift */
-#define ADC_OVERSAMPLING_SHIFT_7B       OVSAMPCTL_OVSS(7)                   /*!< 7-bit oversampling shift */
-#define ADC_OVERSAMPLING_SHIFT_8B       OVSAMPCTL_OVSS(8)                   /*!< 8-bit oversampling shift */
-
-/* ADC oversampling ratio */
-#define OVSAMPCTL_OVSR(regval)          (BITS(2,4) & ((uint32_t)(regval) << 2))
-#define ADC_OVERSAMPLING_RATIO_MUL2     OVSAMPCTL_OVSR(0)                   /*!< oversampling ratio multiple 2 */
-#define ADC_OVERSAMPLING_RATIO_MUL4     OVSAMPCTL_OVSR(1)                   /*!< oversampling ratio multiple 4 */
-#define ADC_OVERSAMPLING_RATIO_MUL8     OVSAMPCTL_OVSR(2)                   /*!< oversampling ratio multiple 8 */
-#define ADC_OVERSAMPLING_RATIO_MUL16    OVSAMPCTL_OVSR(3)                   /*!< oversampling ratio multiple 16 */
-#define ADC_OVERSAMPLING_RATIO_MUL32    OVSAMPCTL_OVSR(4)                   /*!< oversampling ratio multiple 32 */
-#define ADC_OVERSAMPLING_RATIO_MUL64    OVSAMPCTL_OVSR(5)                   /*!< oversampling ratio multiple 64 */
-#define ADC_OVERSAMPLING_RATIO_MUL128   OVSAMPCTL_OVSR(6)                   /*!< oversampling ratio multiple 128 */
-#define ADC_OVERSAMPLING_RATIO_MUL256   OVSAMPCTL_OVSR(7)                   /*!< oversampling ratio multiple 256 */
-
-/* ADC triggered oversampling */
-#define ADC_OVERSAMPLING_ALL_CONVERT    (0U)                                /*!< all oversampled conversions for a channel are done consecutively after a trigger */
-#define ADC_OVERSAMPLING_ONE_CONVERT    (1U)                                /*!< each oversampled conversion for a channel needs a trigger */
-#endif /* GD32F170_190 */
-
-/* ADC channel group definitions */
-#define ADC_REGULAR_CHANNEL             ((uint8_t)0x01U)                    /*!< ADC regular channel group */
-#define ADC_INSERTED_CHANNEL            ((uint8_t)0x02U)                    /*!< ADC inserted channel group */
-#define ADC_REGULAR_INSERTED_CHANNEL    ((uint8_t)0x03U)                    /*!< both regular and inserted channel group */
-#define ADC_CHANNEL_DISCON_DISABLE      ((uint8_t)0x04U)                    /*!< disable discontinuous mode of regular & inserted channel */
-/* ADC inserted channel definitions */
-#define ADC_INSERTED_CHANNEL_0          ((uint8_t)0x00U)                    /*!< ADC inserted channel 0 */
-#define ADC_INSERTED_CHANNEL_1          ((uint8_t)0x01U)                    /*!< ADC inserted channel 1 */
-#define ADC_INSERTED_CHANNEL_2          ((uint8_t)0x02U)                    /*!< ADC inserted channel 2 */
-#define ADC_INSERTED_CHANNEL_3          ((uint8_t)0x03U)                    /*!< ADC inserted channel 3 */
-
-/* ADC channel definitions */
-#define ADC_CHANNEL_0                   ((uint8_t)0x00U)                    /*!< ADC channel 0 */
-#define ADC_CHANNEL_1                   ((uint8_t)0x01U)                    /*!< ADC channel 1 */
-#define ADC_CHANNEL_2                   ((uint8_t)0x02U)                    /*!< ADC channel 2 */
-#define ADC_CHANNEL_3                   ((uint8_t)0x03U)                    /*!< ADC channel 3 */
-#define ADC_CHANNEL_4                   ((uint8_t)0x04U)                    /*!< ADC channel 4 */
-#define ADC_CHANNEL_5                   ((uint8_t)0x05U)                    /*!< ADC channel 5 */
-#define ADC_CHANNEL_6                   ((uint8_t)0x06U)                    /*!< ADC channel 6 */
-#define ADC_CHANNEL_7                   ((uint8_t)0x07U)                    /*!< ADC channel 7 */
-#define ADC_CHANNEL_8                   ((uint8_t)0x08U)                    /*!< ADC channel 8 */
-#define ADC_CHANNEL_9                   ((uint8_t)0x09U)                    /*!< ADC channel 9 */
-#define ADC_CHANNEL_10                  ((uint8_t)0x0AU)                    /*!< ADC channel 10 */
-#define ADC_CHANNEL_11                  ((uint8_t)0x0BU)                    /*!< ADC channel 11 */
-#define ADC_CHANNEL_12                  ((uint8_t)0x0CU)                    /*!< ADC channel 12 */
-#define ADC_CHANNEL_13                  ((uint8_t)0x0DU)                    /*!< ADC channel 13 */
-#define ADC_CHANNEL_14                  ((uint8_t)0x0EU)                    /*!< ADC channel 14 */
-#define ADC_CHANNEL_15                  ((uint8_t)0x0FU)                    /*!< ADC channel 15 */
-#define ADC_CHANNEL_16                  ((uint8_t)0x10U)                    /*!< ADC channel 16 */
-#define ADC_CHANNEL_17                  ((uint8_t)0x11U)                    /*!< ADC channel 17 */
-#define ADC_CHANNEL_18                  ((uint8_t)0x12U)                    /*!< ADC channel 18 */
-
-/* ADC interrupt definitions */
-#define ADC_INT_WDE                     ADC_STAT_WDE                        /*!< analog watchdog event interrupt */
-#define ADC_INT_EOC                     ADC_STAT_EOC                        /*!< end of group conversion interrupt */
-#define ADC_INT_EOIC                    ADC_STAT_EOIC                       /*!< end of inserted group conversion interrupt */
-
-/* ADC interrupt flag */
-#define ADC_INT_FLAG_WDE                ADC_STAT_WDE                        /*!< analog watchdog event interrupt flag */
-#define ADC_INT_FLAG_EOC                ADC_STAT_EOC                        /*!< end of group conversion interrupt flag */
-#define ADC_INT_FLAG_EOIC               ADC_STAT_EOIC                       /*!< end of inserted group conversion interrupt flag */
-
-/* function declarations */
-/* reset ADC */
-void adc_deinit(void);
-/* enable ADC interface */
-void adc_enable(void);
-/* disable ADC interface */
-void adc_disable(void);
-
-/* ADC calibration and reset calibration */
-void adc_calibration_enable(void);
-/* enable DMA request */
-void adc_dma_mode_enable(void);
-/* disable DMA request */
-void adc_dma_mode_disable(void);
-
-/* enable the temperature sensor and Vrefint channel */
-void adc_tempsensor_vrefint_enable(void);
-/* disable the temperature sensor and Vrefint channel */
-void adc_tempsensor_vrefint_disable(void);
-/* enable the vbat channel */
-void adc_vbat_enable(void);
-/* disable the vbat channel */
-void adc_vbat_disable(void);
-
-/* configure ADC discontinuous mode */
-void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length);
-/* configure ADC special function */
-void adc_special_function_config(uint32_t function, ControlStatus newvalue);
-
-/* configure ADC data alignment */
-void adc_data_alignment_config(uint32_t data_alignment);
-/* configure the length of regular channel group or inserted channel group */
-void adc_channel_length_config(uint8_t channel_group, uint32_t length);
-/* configure ADC regular channel */
-void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
-/* configure ADC inserted channel */
-void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
-/* configure ADC inserted channel offset */
-void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset);
-/* enable ADC external trigger */
-void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue);
-/* configure ADC external trigger source */
-void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source);
-/* enable ADC software trigger */
-void adc_software_trigger_enable(uint8_t channel_group);
-
-/* read ADC regular group data register */
-uint16_t adc_regular_data_read(void);
-/* read ADC inserted group data register */
-uint16_t adc_inserted_data_read(uint8_t inserted_channel);
-
-/* get the ADC flag bits */
-FlagStatus adc_flag_get(uint32_t flag);
-/* clear the ADC flag bits */
-void adc_flag_clear(uint32_t flag);
-/* get the ADC interrupt bits */
-FlagStatus adc_interrupt_flag_get(uint32_t flag);
-/* clear the ADC flag */
-void adc_interrupt_flag_clear(uint32_t flag);
-/* enable ADC interrupt */
-void adc_interrupt_enable(uint32_t interrupt);
-/* disable ADC interrupt */
-void adc_interrupt_disable(uint32_t interrupt);
-
-/* configure ADC analog watchdog single channel */
-void adc_watchdog_single_channel_enable(uint8_t channel);
-/* configure ADC analog watchdog group channel */
-void adc_watchdog_group_channel_enable(uint8_t channel_group);
-/* disable ADC analog watchdog */
-void adc_watchdog_disable(void);
-/* configure ADC analog watchdog threshold */
-void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
-
-#ifdef GD32F170_190
-/* configure ADC resolution */
-void adc_resolution_config(uint32_t resolution);
-/* configure ADC oversample mode */
-void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
-/* enable ADC oversample mode */
-void adc_oversample_mode_enable(void);
-/* disable ADC oversample mode */
-void adc_oversample_mode_disable(void);
-#endif /* GD32F170_190 */
-
-#endif /* GD32F1X0_ADC_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_can.h

@@ -1,749 +0,0 @@
-/*!
-    \file  gd32f1x0_can.h
-    \brief definitions for the CAN
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifdef GD32F170_190
-#ifndef GD32F1X0_CAN_H
-#define GD32F1X0_CAN_H
-
-#include "gd32f1x0.h"
-
-/* CAN definitions */
-#define CAN0                               CAN_BASE                     /*!< CAN0 base address */
-#define CAN1                               (CAN0 + 0x00000400U)         /*!< CAN1 base address */
-
-/* registers definitions */
-#define CAN_CTL(canx)                      REG32((canx) + 0x00U)         /*!< CAN control register */
-#define CAN_STAT(canx)                     REG32((canx) + 0x04U)         /*!< CAN status register */
-#define CAN_TSTAT(canx)                    REG32((canx) + 0x08U)         /*!< CAN transmit status register*/
-#define CAN_RFIFO0(canx)                   REG32((canx) + 0x0CU)         /*!< CAN receive FIFO0 register */
-#define CAN_RFIFO1(canx)                   REG32((canx) + 0x10U)         /*!< CAN receive FIFO1 register */
-#define CAN_INTEN(canx)                    REG32((canx) + 0x14U)         /*!< CAN interrupt enable register */
-#define CAN_ERR(canx)                      REG32((canx) + 0x18U)         /*!< CAN error register */
-#define CAN_BT(canx)                       REG32((canx) + 0x1CU)         /*!< CAN bit timing register */
-#define CAN_TMI0(canx)                     REG32((canx) + 0x180U)        /*!< CAN transmit mailbox0 identifier register */
-#define CAN_TMP0(canx)                     REG32((canx) + 0x184U)        /*!< CAN transmit mailbox0 property register */
-#define CAN_TMDATA00(canx)                 REG32((canx) + 0x188U)        /*!< CAN transmit mailbox0 data0 register */
-#define CAN_TMDATA10(canx)                 REG32((canx) + 0x18CU)        /*!< CAN transmit mailbox0 data1 register */
-#define CAN_TMI1(canx)                     REG32((canx) + 0x190U)        /*!< CAN transmit mailbox1 identifier register */
-#define CAN_TMP1(canx)                     REG32((canx) + 0x194U)        /*!< CAN transmit mailbox1 property register */
-#define CAN_TMDATA01(canx)                 REG32((canx) + 0x198U)        /*!< CAN transmit mailbox1 data0 register */
-#define CAN_TMDATA11(canx)                 REG32((canx) + 0x19CU)        /*!< CAN transmit mailbox1 data1 register */
-#define CAN_TMI2(canx)                     REG32((canx) + 0x1A0U)        /*!< CAN transmit mailbox2 identifier register */
-#define CAN_TMP2(canx)                     REG32((canx) + 0x1A4U)        /*!< CAN transmit mailbox2 property register */
-#define CAN_TMDATA02(canx)                 REG32((canx) + 0x1A8U)        /*!< CAN transmit mailbox2 data0 register */
-#define CAN_TMDATA12(canx)                 REG32((canx) + 0x1ACU)        /*!< CAN transmit mailbox2 data1 register */
-#define CAN_RFIFOMI0(canx)                 REG32((canx) + 0x1B0U)        /*!< CAN receive FIFO0 mailbox identifier register */
-#define CAN_RFIFOMP0(canx)                 REG32((canx) + 0x1B4U)        /*!< CAN receive FIFO0 mailbox property register */
-#define CAN_RFIFOMDATA00(canx)             REG32((canx) + 0x1B8U)        /*!< CAN receive FIFO0 mailbox data0 register */
-#define CAN_RFIFOMDATA10(canx)             REG32((canx) + 0x1BCU)        /*!< CAN receive FIFO0 mailbox data1 register */
-#define CAN_RFIFOMI1(canx)                 REG32((canx) + 0x1C0U)        /*!< CAN receive FIFO1 mailbox identifier register */
-#define CAN_RFIFOMP1(canx)                 REG32((canx) + 0x1C4U)        /*!< CAN receive FIFO1 mailbox property register */
-#define CAN_RFIFOMDATA01(canx)             REG32((canx) + 0x1C8U)        /*!< CAN receive FIFO1 mailbox data0 register */
-#define CAN_RFIFOMDATA11(canx)             REG32((canx) + 0x1CCU)        /*!< CAN receive FIFO1 mailbox data1 register */
-#define CAN_FCTL(canx)                     REG32((canx) + 0x200U)        /*!< CAN filter control register */
-#define CAN_FMCFG(canx)                    REG32((canx) + 0x204U)        /*!< CAN filter mode register */
-#define CAN_FSCFG(canx)                    REG32((canx) + 0x20CU)        /*!< CAN filter scale register */
-#define CAN_FAFIFO(canx)                   REG32((canx) + 0x214U)        /*!< CAN filter associated FIFO register */
-#define CAN_FW(canx)                       REG32((canx) + 0x21CU)        /*!< CAN filter working register */
-#define CAN_F0DATA0(canx)                  REG32((canx) + 0x240U)        /*!< CAN filter 0 data 0 register */
-#define CAN_F1DATA0(canx)                  REG32((canx) + 0x248U)        /*!< CAN filter 1 data 0 register */
-#define CAN_F2DATA0(canx)                  REG32((canx) + 0x250U)        /*!< CAN filter 2 data 0 register */
-#define CAN_F3DATA0(canx)                  REG32((canx) + 0x258U)        /*!< CAN filter 3 data 0 register */
-#define CAN_F4DATA0(canx)                  REG32((canx) + 0x260U)        /*!< CAN filter 4 data 0 register */
-#define CAN_F5DATA0(canx)                  REG32((canx) + 0x268U)        /*!< CAN filter 5 data 0 register */
-#define CAN_F6DATA0(canx)                  REG32((canx) + 0x270U)        /*!< CAN filter 6 data 0 register */
-#define CAN_F7DATA0(canx)                  REG32((canx) + 0x278U)        /*!< CAN filter 7 data 0 register */
-#define CAN_F8DATA0(canx)                  REG32((canx) + 0x280U)        /*!< CAN filter 8 data 0 register */
-#define CAN_F9DATA0(canx)                  REG32((canx) + 0x288U)        /*!< CAN filter 9 data 0 register */
-#define CAN_F10DATA0(canx)                 REG32((canx) + 0x290U)        /*!< CAN filter 10 data 0 register */
-#define CAN_F11DATA0(canx)                 REG32((canx) + 0x298U)        /*!< CAN filter 11 data 0 register */
-#define CAN_F12DATA0(canx)                 REG32((canx) + 0x2A0U)        /*!< CAN filter 12 data 0 register */
-#define CAN_F13DATA0(canx)                 REG32((canx) + 0x2A8U)        /*!< CAN filter 13 data 0 register */
-#define CAN_F14DATA0(canx)                 REG32((canx) + 0x2B0U)        /*!< CAN filter 14 data 0 register */
-#define CAN_F15DATA0(canx)                 REG32((canx) + 0x2B8U)        /*!< CAN filter 15 data 0 register */
-#define CAN_F16DATA0(canx)                 REG32((canx) + 0x2C0U)        /*!< CAN filter 16 data 0 register */
-#define CAN_F17DATA0(canx)                 REG32((canx) + 0x2C8U)        /*!< CAN filter 17 data 0 register */
-#define CAN_F18DATA0(canx)                 REG32((canx) + 0x2D0U)        /*!< CAN filter 18 data 0 register */
-#define CAN_F19DATA0(canx)                 REG32((canx) + 0x2D8U)        /*!< CAN filter 19 data 0 register */
-#define CAN_F20DATA0(canx)                 REG32((canx) + 0x2E0U)        /*!< CAN filter 20 data 0 register */
-#define CAN_F21DATA0(canx)                 REG32((canx) + 0x2E8U)        /*!< CAN filter 21 data 0 register */
-#define CAN_F22DATA0(canx)                 REG32((canx) + 0x2F0U)        /*!< CAN filter 22 data 0 register */
-#define CAN_F23DATA0(canx)                 REG32((canx) + 0x3F8U)        /*!< CAN filter 23 data 0 register */
-#define CAN_F24DATA0(canx)                 REG32((canx) + 0x300U)        /*!< CAN filter 24 data 0 register */
-#define CAN_F25DATA0(canx)                 REG32((canx) + 0x308U)        /*!< CAN filter 25 data 0 register */
-#define CAN_F26DATA0(canx)                 REG32((canx) + 0x310U)        /*!< CAN filter 26 data 0 register */
-#define CAN_F27DATA0(canx)                 REG32((canx) + 0x318U)        /*!< CAN filter 27 data 0 register */
-#define CAN_F0DATA1(canx)                  REG32((canx) + 0x244U)        /*!< CAN filter 0 data 1 register */
-#define CAN_F1DATA1(canx)                  REG32((canx) + 0x24CU)        /*!< CAN filter 1 data 1 register */
-#define CAN_F2DATA1(canx)                  REG32((canx) + 0x254U)        /*!< CAN filter 2 data 1 register */
-#define CAN_F3DATA1(canx)                  REG32((canx) + 0x25CU)        /*!< CAN filter 3 data 1 register */
-#define CAN_F4DATA1(canx)                  REG32((canx) + 0x264U)        /*!< CAN filter 4 data 1 register */
-#define CAN_F5DATA1(canx)                  REG32((canx) + 0x26CU)        /*!< CAN filter 5 data 1 register */
-#define CAN_F6DATA1(canx)                  REG32((canx) + 0x274U)        /*!< CAN filter 6 data 1 register */
-#define CAN_F7DATA1(canx)                  REG32((canx) + 0x27CU)        /*!< CAN filter 7 data 1 register */
-#define CAN_F8DATA1(canx)                  REG32((canx) + 0x284U)        /*!< CAN filter 8 data 1 register */
-#define CAN_F9DATA1(canx)                  REG32((canx) + 0x28CU)        /*!< CAN filter 9 data 1 register */
-#define CAN_F10DATA1(canx)                 REG32((canx) + 0x294U)        /*!< CAN filter 10 data 1 register */
-#define CAN_F11DATA1(canx)                 REG32((canx) + 0x29CU)        /*!< CAN filter 11 data 1 register */
-#define CAN_F12DATA1(canx)                 REG32((canx) + 0x2A4U)        /*!< CAN filter 12 data 1 register */
-#define CAN_F13DATA1(canx)                 REG32((canx) + 0x2ACU)        /*!< CAN filter 13 data 1 register */
-#define CAN_F14DATA1(canx)                 REG32((canx) + 0x2B4U)        /*!< CAN filter 14 data 1 register */
-#define CAN_F15DATA1(canx)                 REG32((canx) + 0x2BCU)        /*!< CAN filter 15 data 1 register */
-#define CAN_F16DATA1(canx)                 REG32((canx) + 0x2C4U)        /*!< CAN filter 16 data 1 register */
-#define CAN_F17DATA1(canx)                 REG32((canx) + 0x24CU)        /*!< CAN filter 17 data 1 register */
-#define CAN_F18DATA1(canx)                 REG32((canx) + 0x2D4U)        /*!< CAN filter 18 data 1 register */
-#define CAN_F19DATA1(canx)                 REG32((canx) + 0x2DCU)        /*!< CAN filter 19 data 1 register */
-#define CAN_F20DATA1(canx)                 REG32((canx) + 0x2E4U)        /*!< CAN filter 20 data 1 register */
-#define CAN_F21DATA1(canx)                 REG32((canx) + 0x2ECU)        /*!< CAN filter 21 data 1 register */
-#define CAN_F22DATA1(canx)                 REG32((canx) + 0x2F4U)        /*!< CAN filter 22 data 1 register */
-#define CAN_F23DATA1(canx)                 REG32((canx) + 0x2FCU)        /*!< CAN filter 23 data 1 register */
-#define CAN_F24DATA1(canx)                 REG32((canx) + 0x304U)        /*!< CAN filter 24 data 1 register */
-#define CAN_F25DATA1(canx)                 REG32((canx) + 0x30CU)        /*!< CAN filter 25 data 1 register */
-#define CAN_F26DATA1(canx)                 REG32((canx) + 0x314U)        /*!< CAN filter 26 data 1 register */
-#define CAN_F27DATA1(canx)                 REG32((canx) + 0x31CU)        /*!< CAN filter 27 data 1 register */
-#define CAN_PHYCTL(canx)                   REG32((canx) + 0x3FCU)        /*!< CAN PHY control register */
-
-/* CAN transmit mailbox bank */
-#define CAN_TMI(canx, bank)                REG32((canx) + 0x180U + ((bank) * 0x10U))      /*!< CAN transmit mailbox identifier register */
-#define CAN_TMP(canx, bank)                REG32((canx) + 0x184U + ((bank) * 0x10U))      /*!< CAN transmit mailbox property register */
-#define CAN_TMDATA0(canx, bank)            REG32((canx) + 0x188U + ((bank) * 0x10U))      /*!< CAN transmit mailbox data0 register */
-#define CAN_TMDATA1(canx, bank)            REG32((canx) + 0x18CU + ((bank) * 0x10U))      /*!< CAN transmit mailbox data1 register */
-
-/* CAN filter bank */
-#define CAN_FDATA0(canx, bank)             REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
-#define CAN_FDATA1(canx, bank)             REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
-
-/* CAN receive fifo mailbox bank */
-#define CAN_RFIFOMI(canx, bank)            REG32((canx) + 0x1B0U + ((bank) * 0x10U))      /*!< CAN receive FIFO mailbox identifier register */
-#define CAN_RFIFOMP(canx, bank)            REG32((canx) + 0x1B4U + ((bank) * 0x10U))      /*!< CAN receive FIFO mailbox property register */
-#define CAN_RFIFOMDATA0(canx, bank)        REG32((canx) + 0x1B8U + ((bank) * 0x10U))      /*!< CAN receive FIFO mailbox data0 register */
-#define CAN_RFIFOMDATA1(canx, bank)        REG32((canx) + 0x1BCU + ((bank) * 0x10U))      /*!< CAN receive FIFO mailbox data1 register */
-
-/* bits definitions */
-/* CAN_CTL */
-#define CAN_CTL_IWMOD                      BIT(0)                       /*!< initial working mode */
-#define CAN_CTL_SLPWMOD                    BIT(1)                       /*!< sleep working mode */
-#define CAN_CTL_TFO                        BIT(2)                       /*!< transmit FIFO order */
-#define CAN_CTL_RFOD                       BIT(3)                       /*!< receive FIFO overwrite disable */
-#define CAN_CTL_ARD                        BIT(4)                       /*!< automatic retransmission disable */
-#define CAN_CTL_AWU                        BIT(5)                       /*!< automatic wakeup */
-#define CAN_CTL_ABOR                       BIT(6)                       /*!< automatic bus-off recovery */
-#define CAN_CTL_TTC                        BIT(7)                       /*!< time triggered communication */
-#define CAN_CTL_SWRST                      BIT(15)                      /*!< CAN software reset */
-#define CAN_CTL_DFZ                        BIT(16)                      /*!< CAN debug freeze */
-
-/* CAN_STAT */
-#define CAN_STAT_IWS                       BIT(0)                       /*!< initial working state */
-#define CAN_STAT_SLPWS                     BIT(1)                       /*!< sleep working state */
-#define CAN_STAT_ERRIF                     BIT(2)                       /*!< error interrupt flag*/
-#define CAN_STAT_WUIF                      BIT(3)                       /*!< status change interrupt flag of wakeup from sleep working mode */
-#define CAN_STAT_SLPIF                     BIT(4)                       /*!< status change interrupt flag of sleep working mode entering */
-#define CAN_STAT_TS                        BIT(8)                       /*!< transmitting state */
-#define CAN_STAT_RS                        BIT(9)                       /*!< receiving state */
-#define CAN_STAT_LASTRX                    BIT(10)                      /*!< last sample value of rx pin */
-#define CAN_STAT_RXL                       BIT(11)                      /*!< CAN rx signal */
-
-/* CAN_TSTAT */
-#define CAN_TSTAT_MTF0                     BIT(0)                       /*!< mailbox0 transmit finished */
-#define CAN_TSTAT_MTFNERR0                 BIT(1)                       /*!< mailbox0 transmit finished and no error */
-#define CAN_TSTAT_MAL0                     BIT(2)                       /*!< mailbox0 arbitration lost */
-#define CAN_TSTAT_MTE0                     BIT(3)                       /*!< mailbox0 transmit error */
-#define CAN_TSTAT_MST0                     BIT(7)                       /*!< mailbox0 stop transmitting */
-#define CAN_TSTAT_MTF1                     BIT(8)                       /*!< mailbox1 transmit finished */
-#define CAN_TSTAT_MTFNERR1                 BIT(9)                       /*!< mailbox1 transmit finished and no error */
-#define CAN_TSTAT_MAL1                     BIT(10)                      /*!< mailbox1 arbitration lost */
-#define CAN_TSTAT_MTE1                     BIT(11)                      /*!< mailbox1 transmit error */
-#define CAN_TSTAT_MST1                     BIT(15)                      /*!< mailbox1 stop transmitting */
-#define CAN_TSTAT_MTF2                     BIT(16)                      /*!< mailbox2 transmit finished */
-#define CAN_TSTAT_MTFNERR2                 BIT(17)                      /*!< mailbox2 transmit finished and no error */
-#define CAN_TSTAT_MAL2                     BIT(18)                      /*!< mailbox2 arbitration lost */
-#define CAN_TSTAT_MTE2                     BIT(19)                      /*!< mailbox2 transmit error */
-#define CAN_TSTAT_MST2                     BIT(23)                      /*!< mailbox2 stop transmitting */
-#define CAN_TSTAT_NUM                      BITS(24,25)                  /*!< mailbox number */
-#define CAN_TSTAT_TME0                     BIT(26)                      /*!< transmit mailbox0 empty */
-#define CAN_TSTAT_TME1                     BIT(27)                      /*!< transmit mailbox1 empty */
-#define CAN_TSTAT_TME2                     BIT(28)                      /*!< transmit mailbox2 empty */
-#define CAN_TSTAT_TMLS0                    BIT(29)                      /*!< last sending priority flag for mailbox0 */
-#define CAN_TSTAT_TMLS1                    BIT(30)                      /*!< last sending priority flag for mailbox1 */
-#define CAN_TSTAT_TMLS2                    BIT(31)                      /*!< last sending priority flag for mailbox2 */
-
-/* CAN_RFIFO0 */
-#define CAN_RFIFO0_RFL0                    BITS(0,1)                    /*!< receive FIFO0 length */
-#define CAN_RFIFO0_RFF0                    BIT(3)                       /*!< receive FIFO0 full */
-#define CAN_RFIFO0_RFO0                    BIT(4)                       /*!< receive FIFO0 overfull */
-#define CAN_RFIFO0_RFD0                    BIT(5)                       /*!< receive FIFO0 dequeue */
-
-/* CAN_RFIFO1 */
-#define CAN_RFIFO1_RFL1                    BITS(0,1)                    /*!< receive FIFO1 length */
-#define CAN_RFIFO1_RFF1                    BIT(3)                       /*!< receive FIFO1 full */
-#define CAN_RFIFO1_RFO1                    BIT(4)                       /*!< receive FIFO1 overfull */
-#define CAN_RFIFO1_RFD1                    BIT(5)                       /*!< receive FIFO1 dequeue */
-
-/* CAN_INTEN */
-#define CAN_INTEN_TMEIE                    BIT(0)                       /*!< transmit mailbox empty interrupt enable */
-#define CAN_INTEN_RFNEIE0                  BIT(1)                       /*!< receive FIFO0 not empty interrupt enable */
-#define CAN_INTEN_RFFIE0                   BIT(2)                       /*!< receive FIFO0 full interrupt enable */
-#define CAN_INTEN_RFOIE0                   BIT(3)                       /*!< receive FIFO0 overfull interrupt enable */
-#define CAN_INTEN_RFNEIE1                  BIT(4)                       /*!< receive FIFO1 not empty interrupt enable */
-#define CAN_INTEN_RFFIE1                   BIT(5)                       /*!< receive FIFO1 full interrupt enable */
-#define CAN_INTEN_RFOIE1                   BIT(6)                       /*!< receive FIFO1 overfull interrupt enable */
-#define CAN_INTEN_WERRIE                   BIT(8)                       /*!< warning error interrupt enable */
-#define CAN_INTEN_PERRIE                   BIT(9)                       /*!< passive error interrupt enable */
-#define CAN_INTEN_BOIE                     BIT(10)                      /*!< bus-off interrupt enable */
-#define CAN_INTEN_ERRNIE                   BIT(11)                      /*!< error number interrupt enable */
-#define CAN_INTEN_ERRIE                    BIT(15)                      /*!< error interrupt enable */
-#define CAN_INTEN_WIE                      BIT(16)                      /*!< wakeup interrupt enable */
-#define CAN_INTEN_SLPWIE                   BIT(17)                      /*!< sleep working interrupt enable */
-
-/* CAN_ERR */
-#define CAN_ERR_WERR                       BIT(0)                       /*!< warning error */
-#define CAN_ERR_PERR                       BIT(1)                       /*!< passive error */
-#define CAN_ERR_BOERR                      BIT(2)                       /*!< bus-off error */
-#define CAN_ERR_ERRN                       BITS(4,6)                    /*!< error number */
-#define CAN_ERR_TECNT                      BITS(16,23)                  /*!< transmit error count */
-#define CAN_ERR_RECNT                      BITS(24,31)                  /*!< receive error count */
-
-/* CAN_BT */
-#define CAN_BT_BAUDPSC                     BITS(0,9)                    /*!< baudrate prescaler */
-#define CAN_BT_BS1                         BITS(16,19)                  /*!< bit segment 1 */
-#define CAN_BT_BS2                         BITS(20,22)                  /*!< bit segment 2 */
-#define CAN_BT_SJW                         BITS(24,25)                  /*!< resynchronization jump width */
-#define CAN_BT_LCMOD                       BIT(30)                      /*!< loopback communication mode */
-#define CAN_BT_SCMOD                       BIT(31)                      /*!< silent communication mode */
-
-/* CAN_TMIx */
-#define CAN_TMI_TEN                        BIT(0)                       /*!< transmit enable */
-#define CAN_TMI_FT                         BIT(1)                       /*!< frame type */
-#define CAN_TMI_FF                         BIT(2)                       /*!< frame format */
-#define CAN_TMI_EFID                       BITS(3,31)                   /*!< the frame identifier */
-#define CAN_TMI_SFID                       BITS(21,31)                  /*!< the frame identifier */
-
-/* CAN_TMPx */
-#define CAN_TMP_DLENC                      BITS(0,3)                    /*!< data length code */
-#define CAN_TMP_TSEN                       BIT(8)                       /*!< time stamp enable */
-#define CAN_TMP_TS                         BITS(16,31)                  /*!< time stamp */
-
-/* CAN_TMDATA0x */
-#define CAN_TMDATA0_DB0                    BITS(0,7)                    /*!< transmit data byte 0 */
-#define CAN_TMDATA0_DB1                    BITS(8,15)                   /*!< transmit data byte 1 */
-#define CAN_TMDATA0_DB2                    BITS(16,23)                  /*!< transmit data byte 2 */
-#define CAN_TMDATA0_DB3                    BITS(24,31)                  /*!< transmit data byte 3 */
-
-/* CAN_TMDATA1x */
-#define CAN_TMDATA1_DB4                    BITS(0,7)                    /*!< transmit data byte 4 */
-#define CAN_TMDATA1_DB5                    BITS(8,15)                   /*!< transmit data byte 5 */
-#define CAN_TMDATA1_DB6                    BITS(16,23)                  /*!< transmit data byte 6 */
-#define CAN_TMDATA1_DB7                    BITS(24,31)                  /*!< transmit data byte 7 */
-
-/* CAN_RFIFOMIx */
-#define CAN_RFIFOMI_FT                     BIT(1)                       /*!< frame type */
-#define CAN_RFIFOMI_FF                     BIT(2)                       /*!< frame format */
-#define CAN_RFIFOMI_EFID                   BITS(3,31)                   /*!< the frame identifier */
-#define CAN_RFIFOMI_SFID                   BITS(21,31)                  /*!< the frame identifier */
-
-/* CAN_RFIFOMPx */
-#define CAN_RFIFOMP_DLENC                  BITS(0,3)                    /*!< receive data length code */
-#define CAN_RFIFOMP_FI                     BITS(8,15)                   /*!< filter index */
-#define CAN_RFIFOMP_TS                     BITS(16,31)                  /*!< time stamp */
-
-/* CAN_RFIFOMDATA0x */
-#define CAN_RFIFOMDATA0_DB0                BITS(0,7)                    /*!< receive data byte 0 */
-#define CAN_RFIFOMDATA0_DB1                BITS(8,15)                   /*!< receive data byte 1 */
-#define CAN_RFIFOMDATA0_DB2                BITS(16,23)                  /*!< receive data byte 2 */
-#define CAN_RFIFOMDATA0_DB3                BITS(24,31)                  /*!< receive data byte 3 */
-
-/* CAN_RFIFOMDATA1x */
-#define CAN_RFIFOMDATA1_DB4                BITS(0,7)                    /*!< receive data byte 4 */
-#define CAN_RFIFOMDATA1_DB5                BITS(8,15)                   /*!< receive data byte 5 */
-#define CAN_RFIFOMDATA1_DB6                BITS(16,23)                  /*!< receive data byte 6 */
-#define CAN_RFIFOMDATA1_DB7                BITS(24,31)                  /*!< receive data byte 7 */
-
-/* CAN_FCTL */
-#define CAN_FCTL_FLD                       BIT(0)                       /*!< filter lock disable */
-#define CAN_FCTL_HBC1F                     BITS(8,13)                   /*!< header bank of CAN1 filter */
-
-/* CAN_FMCFG */
-#define CAN_FMCFG_FMOD(regval)             BIT(regval)                  /*!< filter mode, list or mask*/
-
-/* CAN_FSCFG */
-#define CAN_FSCFG_FS(regval)               BIT(regval)                  /*!< filter scale, 32 bits or 16 bits*/
-
-/* CAN_FAFIFO */
-#define CAN_FAFIFOR_FAF(regval)            BIT(regval)                  /*!< filter associated with FIFO */
-
-/* CAN_FW */
-#define CAN_FW_FW(regval)                  BIT(regval)                  /*!< filter working */
-
-/* CAN_FxDATAy */
-#define CAN_FDATA_FD(regval)               BIT(regval)                  /*!< filter data */
-
-/* CAN_PHYCTL */
-#define CAN_PHYCTL_PHYEN                   BIT(0)                       /*!< PHY enable */
-#define CAN_PHYCTL_POMOD                   BITS(8,9)                    /*!< PHY mode */
-
-/* consts definitions */
-/* define the CAN bit position and its register index offset */
-#define CAN_REGIDX_BIT(regidx, bitpos)              (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
-#define CAN_REG_VAL(canx, offset)                   (REG32((canx) + ((uint32_t)(offset) >> 6)))
-#define CAN_BIT_POS(val)                            ((uint32_t)(val) & 0x1FU)
-
-#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1)   (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
-#define CAN_REG_VALS(canx, offset)                  (REG32((canx) + ((uint32_t)(offset) >> 12)))
-#define CAN_BIT_POS0(val)                           (((uint32_t)(val) >> 6) & 0x1FU)
-#define CAN_BIT_POS1(val)                           ((uint32_t)(val) & 0x1FU)
-
-/* register offset */
-#define STAT_REG_OFFSET                    ((uint8_t)0x04U)             /*!< STAT register offset */
-#define TSTAT_REG_OFFSET                   ((uint8_t)0x08U)             /*!< TSTAT register offset */
-#define RFIFO0_REG_OFFSET                  ((uint8_t)0x0CU)             /*!< RFIFO0 register offset */
-#define RFIFO1_REG_OFFSET                  ((uint8_t)0x10U)             /*!< RFIFO1 register offset */
-#define ERR_REG_OFFSET                     ((uint8_t)0x18U)             /*!< ERR register offset */
-
-/* CAN flags */
-typedef enum
-{
-    /* flags in TSTAT register */
-    CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U),              /*!< mailbox 2 transmit error */
-    CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U),              /*!< mailbox 1 transmit error */
-    CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U),               /*!< mailbox 0 transmit error */
-    CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U),              /*!< mailbox 2 transmit finished */
-    CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U),               /*!< mailbox 1 transmit finished */
-    CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U),               /*!< mailbox 0 transmit finished */
-    /* flags in RFIFO0 register */
-    CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U),              /*!< receive FIFO0 overfull */
-    CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U),              /*!< receive FIFO0 full */
-    /* flags in RFIFO1 register */
-    CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U),              /*!< receive FIFO1 overfull */
-    CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U),              /*!< receive FIFO1 full */
-    /* flags in ERR register */
-    CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U),                /*!< bus-off error */
-    CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U),                 /*!< passive error */
-    CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U),                 /*!< warning error */
-} can_flag_enum;
-
-/* CAN interrupt flags */
-typedef enum
-{
-    /* interrupt flags in STAT register */
-    CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U),      /*!< status change interrupt flag of sleep working mode entering */
-    CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16),        /*!< status change interrupt flag of wakeup from sleep working mode */
-    CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15),       /*!< error interrupt flag */
-    /* interrupt flags in TSTAT register */
-    CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U),      /*!< mailbox 2 transmit finished interrupt flag */
-    CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U),       /*!< mailbox 1 transmit finished interrupt flag */
-    CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U),       /*!< mailbox 0 transmit finished interrupt flag */
-    /* interrupt flags in RFIFO0 register */
-    CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U),      /*!< receive FIFO0 overfull interrupt flag */
-    CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U),      /*!< receive FIFO0 full interrupt flag */
-    /* interrupt flags in RFIFO0 register */
-    CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U),      /*!< receive FIFO1 overfull interrupt flag */
-    CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U),      /*!< receive FIFO1 full interrupt flag */
-} can_interrupt_flag_enum;
-
-/* CAN initiliaze parameters struct */
-typedef struct
-{
-    uint8_t working_mode;                                                 /*!< CAN working mode */
-    uint8_t resync_jump_width;                                            /*!< CAN resynchronization jump width */
-    uint8_t time_segment_1;                                               /*!< time segment 1 */
-    uint8_t time_segment_2;                                               /*!< time segment 2 */
-    ControlStatus time_triggered;                                         /*!< time triggered communication mode */
-    ControlStatus auto_bus_off_recovery;                                  /*!< automatic bus-off recovery */
-    ControlStatus auto_wake_up;                                           /*!< automatic wake-up mode */
-    ControlStatus no_auto_retrans;                                        /*!< automatic retransmission mode disable */
-    ControlStatus rec_fifo_overwrite;                                     /*!< receive FIFO overwrite mode */
-    ControlStatus trans_fifo_order;                                       /*!< transmit FIFO order */
-    uint16_t prescaler;                                                   /*!< baudrate prescaler */
-} can_parameter_struct;
-
-/* CAN transmit message struct */
-typedef struct
-{
-    uint32_t tx_sfid;                                                     /*!< standard format frame identifier */
-    uint32_t tx_efid;                                                     /*!< extended format frame identifier */
-    uint8_t tx_ff;                                                        /*!< format of frame, standard or extended format */
-    uint8_t tx_ft;                                                        /*!< type of frame, data or remote */
-    uint8_t tx_dlen;                                                      /*!< data length */
-    uint8_t tx_data[8];                                                   /*!< transmit data */
-} can_trasnmit_message_struct;
-
-/* CAN receive message struct */
-typedef struct
-{
-    uint32_t rx_sfid;                                                     /*!< standard format frame identifier */
-    uint32_t rx_efid;                                                     /*!< extended format frame identifier */
-    uint8_t rx_ff;                                                        /*!< format of frame, standard or extended format */
-    uint8_t rx_ft;                                                        /*!< type of frame, data or remote */
-    uint8_t rx_dlen;                                                      /*!< data length */
-    uint8_t rx_data[8];                                                   /*!< receive data */
-    uint8_t rx_fi;                                                        /*!< filtering index */
-} can_receive_message_struct;
-
-/* CAN filter parameters struct */
-typedef struct
-{
-    uint16_t filter_list_high;                                            /*!< filter list number high bits*/
-    uint16_t filter_list_low;                                             /*!< filter list number low bits */
-    uint16_t filter_mask_high;                                            /*!< filter mask number high bits */
-    uint16_t filter_mask_low;                                             /*!< filter mask number low bits */
-    uint16_t filter_fifo_number;                                          /*!< receive FIFO associated with the filter */
-    uint16_t filter_number;                                               /*!< filter number */
-    uint16_t filter_mode;                                                 /*!< filter mode, list or mask */
-    uint16_t filter_bits;                                                 /*!< filter scale */
-    ControlStatus filter_enable;                                          /*!< filter work or not */
-} can_filter_parameter_struct;
-
-/* CAN errors */
-typedef enum
-{
-    CAN_ERROR_NONE = 0,                                                   /*!< no error */
-    CAN_ERROR_FILL,                                                       /*!< fill error */
-    CAN_ERROR_FORMATE,                                                    /*!< format error */
-    CAN_ERROR_ACK,                                                        /*!< ACK error */
-    CAN_ERROR_BITRECESSIVE,                                               /*!< bit recessive error */
-    CAN_ERROR_BITDOMINANTER,                                              /*!< bit dominant error */
-    CAN_ERROR_CRC,                                                        /*!< CRC error */
-    CAN_ERROR_SOFTWARECFG,                                                /*!< software configure */
-}can_error_enum;
-
-/* transmit states */
-typedef enum
-{
-    CAN_TRANSMIT_FAILED = 0,                                             /*!< CAN transmitted failure */
-    CAN_TRANSMIT_OK = 1,                                                 /*!< CAN transmitted success */
-    CAN_TRANSMIT_PENDING = 2,                                            /*!< CAN transmitted pending */
-    CAN_TRANSMIT_NOMAILBOX = 4,                                          /*!< no empty mailbox to be used for CAN */
-} can_transmit_state_enum;
-
-typedef enum
-{
-    CAN_INIT_STRUCT = 0,                                                 /*!< CAN initiliaze parameters struct */
-    CAN_FILTER_STRUCT,                                                   /*!< CAN filter parameters struct */
-    CAN_TX_MESSAGE_STRUCT,                                               /*!< CAN transmit message struct */
-    CAN_RX_MESSAGE_STRUCT,                                               /*!< CAN receive message struct */
-} can_struct_type_enum;
-
-/* CAN baudrate prescaler*/
-#define BT_BAUDPSC(regval)                 (BITS(0,9) & ((uint32_t)(regval) << 0))
-
-/* CAN bit segment 1*/
-#define BT_BS1(regval)                     (BITS(16,19) & ((uint32_t)(regval) << 16))
-
-/* CAN bit segment 2*/
-#define BT_BS2(regval)                     (BITS(20,22) & ((uint32_t)(regval) << 20))
-
-/* CAN resynchronization jump width*/
-#define BT_SJW(regval)                     (BITS(24,25) & ((uint32_t)(regval) << 24))
-
-/* CAN communication mode*/
-#define BT_MODE(regval)                    (BITS(30,31) & ((uint32_t)(regval) << 30))
-
-/* CAN FDATA high 16 bits */
-#define FDATA_MASK_HIGH(regval)            (BITS(16,31) & ((uint32_t)(regval) << 16))
-
-/* CAN FDATA low 16 bits */
-#define FDATA_MASK_LOW(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0))
-
-/* CAN1 filter start bank_number*/
-#define FCTL_HBC1F(regval)                 (BITS(8,13) & ((uint32_t)(regval) << 8))
-
-/* CAN transmit mailbox extended identifier*/
-#define TMI_EFID(regval)                   (BITS(3,31) & ((uint32_t)(regval) << 3))
-
-/* CAN transmit mailbox standard identifier*/
-#define TMI_SFID(regval)                   (BITS(21,31) & ((uint32_t)(regval) << 21))
-
-/* transmit data byte 0 */
-#define TMDATA0_DB0(regval)                (BITS(0,7) & ((uint32_t)(regval) << 0))
-
-/* transmit data byte 1 */
-#define TMDATA0_DB1(regval)                (BITS(8,15) & ((uint32_t)(regval) << 8))
-
-/* transmit data byte 2 */
-#define TMDATA0_DB2(regval)                (BITS(16,23) & ((uint32_t)(regval) << 16))
-
-/* transmit data byte 3 */                 
-#define TMDATA0_DB3(regval)                (BITS(24,31) & ((uint32_t)(regval) << 24))
-
-/* transmit data byte 4 */                 
-#define TMDATA1_DB4(regval)                (BITS(0,7) & ((uint32_t)(regval) << 0))
-
-/* transmit data byte 5 */                 
-#define TMDATA1_DB5(regval)                (BITS(8,15) & ((uint32_t)(regval) << 8))
-
-/* transmit data byte 6 */                 
-#define TMDATA1_DB6(regval)                (BITS(16,23) & ((uint32_t)(regval) << 16))
-
-/* transmit data byte 7 */                 
-#define TMDATA1_DB7(regval)                (BITS(24,31) & ((uint32_t)(regval) << 24))
-
-/* receive mailbox extended identifier*/
-#define GET_RFIFOMI_EFID(regval)           GET_BITS((uint32_t)(regval), 3, 31)
-
-/* receive mailbox standrad identifier*/
-#define GET_RFIFOMI_SFID(regval)           GET_BITS((uint32_t)(regval), 21, 31)
-
-/* receive data length */
-#define GET_RFIFOMP_DLENC(regval)          GET_BITS((uint32_t)(regval), 0, 3)
-
-/* the index of the filter by which the frame is passed */
-#define GET_RFIFOMP_FI(regval)             GET_BITS((uint32_t)(regval), 8, 15)
-
-/* receive data byte 0 */
-#define GET_RFIFOMDATA0_DB0(regval)        GET_BITS((uint32_t)(regval), 0, 7)
-
-/* receive data byte 1 */
-#define GET_RFIFOMDATA0_DB1(regval)        GET_BITS((uint32_t)(regval), 8, 15)
-
-/* receive data byte 2 */
-#define GET_RFIFOMDATA0_DB2(regval)        GET_BITS((uint32_t)(regval), 16, 23)
-
-/* receive data byte 3 */
-#define GET_RFIFOMDATA0_DB3(regval)        GET_BITS((uint32_t)(regval), 24, 31)
-
-/* receive data byte 4 */
-#define GET_RFIFOMDATA1_DB4(regval)        GET_BITS((uint32_t)(regval), 0, 7)
-
-/* receive data byte 5 */
-#define GET_RFIFOMDATA1_DB5(regval)        GET_BITS((uint32_t)(regval), 8, 15)
-
-/* receive data byte 6 */
-#define GET_RFIFOMDATA1_DB6(regval)        GET_BITS((uint32_t)(regval), 16, 23)
-
-/* receive data byte 7 */
-#define GET_RFIFOMDATA1_DB7(regval)        GET_BITS((uint32_t)(regval), 24, 31)
-
-/* error number */
-#define GET_ERR_ERRN(regval)               GET_BITS((uint32_t)(regval), 4, 6)
-
-/* transmit error count */
-#define GET_ERR_TECNT(regval)              GET_BITS((uint32_t)(regval), 16, 23)
-
-/* receive  error count */
-#define GET_ERR_RECNT(regval)              GET_BITS((uint32_t)(regval), 24, 31)
-
-/* CAN errors */
-#define ERR_ERRN(regval)                   (BITS(4,6) & ((uint32_t)(regval) << 4))
-#define CAN_ERRN_0                         ERR_ERRN(0)                  /*!<  no error */
-#define CAN_ERRN_1                         ERR_ERRN(1)                  /*!< fill error */
-#define CAN_ERRN_2                         ERR_ERRN(2)                  /*!< format error */
-#define CAN_ERRN_3                         ERR_ERRN(3)                  /*!< ACK error */
-#define CAN_ERRN_4                         ERR_ERRN(4)                  /*!< bit recessive error */
-#define CAN_ERRN_5                         ERR_ERRN(5)                  /*!< bit dominant error */
-#define CAN_ERRN_6                         ERR_ERRN(6)                  /*!< CRC error */
-#define CAN_ERRN_7                         ERR_ERRN(7)                  /*!< software error */
-
-/* CAN phy mode bits */
-#define PHYCTL_POMOD(regval)               (BITS(8,9) & ((uint32_t)(regval) << 8))
-
-#define CAN_PHYCTL_POMODE_0                PHYCTL_POMOD(0)              /*!< low slope mode */
-#define CAN_PHYCTL_POMODE_1                PHYCTL_POMOD(1)              /*!< middle slope mode */
-#define CAN_PHYCTL_POMODE_2                PHYCTL_POMOD(2)              /*!< high slope mode */
-#define CAN_PHYCTL_POMODE_3                PHYCTL_POMOD(3)              /*!< high speed mode */
-#define CAN_PHYCTL_POMODE_MASK             PHYCTL_POMOD(3)              /*!< mask of phy mode */
-
-#define CAN_STATE_PENDING                  ((uint32_t)0x00000000U)      /*!< CAN pending */
-
-/* CAN communication mode */
-#define CAN_NORMAL_MODE                    ((uint8_t)0x00U)             /*!< normal communication mode */
-#define CAN_LOOPBACK_MODE                  ((uint8_t)0x01U)             /*!< loopback communication mode */
-#define CAN_SILENT_MODE                    ((uint8_t)0x02U)             /*!< silent communication mode */
-#define CAN_SILENT_LOOPBACK_MODE           ((uint8_t)0x03U)             /*!< loopback and silent communication mode */
-
-/* CAN resynchronisation jump width */
-#define CAN_BT_SJW_1TQ                     ((uint8_t)0x00U)             /*!< 1 time quanta */
-#define CAN_BT_SJW_2TQ                     ((uint8_t)0x01U)             /*!< 2 time quanta */
-#define CAN_BT_SJW_3TQ                     ((uint8_t)0x02U)             /*!< 3 time quanta */
-#define CAN_BT_SJW_4TQ                     ((uint8_t)0x03U)             /*!< 4 time quanta */
-
-/* CAN time segment 1 */
-#define CAN_BT_BS1_1TQ                     ((uint8_t)0x00U)             /*!< 1 time quanta */
-#define CAN_BT_BS1_2TQ                     ((uint8_t)0x01U)             /*!< 2 time quanta */
-#define CAN_BT_BS1_3TQ                     ((uint8_t)0x02U)             /*!< 3 time quanta */
-#define CAN_BT_BS1_4TQ                     ((uint8_t)0x03U)             /*!< 4 time quanta */
-#define CAN_BT_BS1_5TQ                     ((uint8_t)0x04U)             /*!< 5 time quanta */
-#define CAN_BT_BS1_6TQ                     ((uint8_t)0x05U)             /*!< 6 time quanta */
-#define CAN_BT_BS1_7TQ                     ((uint8_t)0x06U)             /*!< 7 time quanta */
-#define CAN_BT_BS1_8TQ                     ((uint8_t)0x07U)             /*!< 8 time quanta */
-#define CAN_BT_BS1_9TQ                     ((uint8_t)0x08U)             /*!< 9 time quanta */
-#define CAN_BT_BS1_10TQ                    ((uint8_t)0x09U)             /*!< 10 time quanta */
-#define CAN_BT_BS1_11TQ                    ((uint8_t)0x0AU)             /*!< 11 time quanta */
-#define CAN_BT_BS1_12TQ                    ((uint8_t)0x0BU)             /*!< 12 time quanta */
-#define CAN_BT_BS1_13TQ                    ((uint8_t)0x0CU)             /*!< 13 time quanta */
-#define CAN_BT_BS1_14TQ                    ((uint8_t)0x0DU)             /*!< 14 time quanta */
-#define CAN_BT_BS1_15TQ                    ((uint8_t)0x0EU)             /*!< 15 time quanta */
-#define CAN_BT_BS1_16TQ                    ((uint8_t)0x0FU)             /*!< 16 time quanta */
-
-/* CAN time segment 2 */
-#define CAN_BT_BS2_1TQ                     ((uint8_t)0x00U)             /*!< 1 time quanta */
-#define CAN_BT_BS2_2TQ                     ((uint8_t)0x01U)             /*!< 2 time quanta */
-#define CAN_BT_BS2_3TQ                     ((uint8_t)0x02U)             /*!< 3 time quanta */
-#define CAN_BT_BS2_4TQ                     ((uint8_t)0x03U)             /*!< 4 time quanta */
-#define CAN_BT_BS2_5TQ                     ((uint8_t)0x04U)             /*!< 5 time quanta */
-#define CAN_BT_BS2_6TQ                     ((uint8_t)0x05U)             /*!< 6 time quanta */
-#define CAN_BT_BS2_7TQ                     ((uint8_t)0x06U)             /*!< 7 time quanta */
-#define CAN_BT_BS2_8TQ                     ((uint8_t)0x07U)             /*!< 8 time quanta */
-
-/* CAN mailbox number */
-#define CAN_MAILBOX0                       ((uint8_t)0x00U)             /*!< mailbox0 */
-#define CAN_MAILBOX1                       ((uint8_t)0x01U)             /*!< mailbox1 */
-#define CAN_MAILBOX2                       ((uint8_t)0x02U)             /*!< mailbox2 */
-#define CAN_NOMAILBOX                      ((uint8_t)0x03U)             /*!< no mailbox empty */
-
-/* CAN frame format */
-#define CAN_FF_STANDARD                    ((uint32_t)0x00000000U)      /*!< standard frame */
-#define CAN_FF_EXTENDED                    ((uint32_t)0x00000004U)      /*!< extended frame */
-
-/* CAN receive fifo */
-#define CAN_FIFO0                          ((uint8_t)0x00U)             /*!< receive FIFO0 */
-#define CAN_FIFO1                          ((uint8_t)0x01U)             /*!< receive FIFO1 */
-
-/* frame number of receive fifo */
-#define CAN_RFIF_RFL_MASK                  ((uint32_t)0x00000003U)      /*!< mask for frame number in receive FIFOx */
-
-#define CAN_SFID_MASK                      ((uint32_t)0x000007FFU)      /*!< mask of standard identifier */
-#define CAN_EFID_MASK                      ((uint32_t)0x1FFFFFFFU)      /*!< mask of extended identifier */
-
-/* CAN working mode */
-#define CAN_MODE_INITIALIZE                ((uint8_t)0x01U)             /*!< CAN initialize mode */
-#define CAN_MODE_NORMAL                    ((uint8_t)0x02U)             /*!< CAN normal mode */
-#define CAN_MODE_SLEEP                     ((uint8_t)0x04U)             /*!< CAN sleep mode */
-
-/* filter bits */
-#define CAN_FILTERBITS_16BIT               ((uint8_t)0x00U)             /*!< CAN filter 16 bits */
-#define CAN_FILTERBITS_32BIT               ((uint8_t)0x01U)             /*!< CAN filter 32 bits */
-
-/* filter mode */
-#define CAN_FILTERMODE_MASK                ((uint8_t)0x00U)             /*!< mask mode */
-#define CAN_FILTERMODE_LIST                ((uint8_t)0x01U)             /*!< list mode */
-
-/* filter 16 bits mask */
-#define CAN_FILTER_MASK_16BITS             ((uint32_t)0x0000FFFFU)      /*!< can filter 16 bits mask */
-
-/* frame type */
-#define CAN_FT_DATA                        ((uint32_t)0x00000000U)      /*!< data frame */
-#define CAN_FT_REMOTE                      ((uint32_t)0x00000002U)      /*!< remote frame */
-
-/* CAN timeout */
-#define CAN_TIMEOUT                        ((uint32_t)0x0000FFFFU)      /*!< timeout value */
-
-/* interrupt enable bits */
-#define CAN_INT_TME                        CAN_INTEN_TMEIE              /*!< transmit mailbox empty interrupt enable */
-#define CAN_INT_RFNE0                      CAN_INTEN_RFNEIE0            /*!< receive FIFO0 not empty interrupt enable */
-#define CAN_INT_RFF0                       CAN_INTEN_RFFIE0             /*!< receive FIFO0 full interrupt enable */
-#define CAN_INT_RFO0                       CAN_INTEN_RFOIE0             /*!< receive FIFO0 overfull interrupt enable */
-#define CAN_INT_RFNE1                      CAN_INTEN_RFNEIE1            /*!< receive FIFO1 not empty interrupt enable */
-#define CAN_INT_RFF1                       CAN_INTEN_RFFIE1             /*!< receive FIFO1 full interrupt enable */
-#define CAN_INT_RFO1                       CAN_INTEN_RFOIE1             /*!< receive FIFO1 overfull interrupt enable */
-#define CAN_INT_WERR                       CAN_INTEN_WERRIE             /*!< warning error interrupt enable */
-#define CAN_INT_PERR                       CAN_INTEN_PERRIE             /*!< passive error interrupt enable */
-#define CAN_INT_BO                         CAN_INTEN_BOIE               /*!< bus-off interrupt enable */
-#define CAN_INT_ERRN                       CAN_INTEN_ERRNIE             /*!< error number interrupt enable */
-#define CAN_INT_ERR                        CAN_INTEN_ERRIE              /*!< error interrupt enable */
-#define CAN_INT_WAKEUP                     CAN_INTEN_WIE                /*!< wakeup interrupt enable */
-#define CAN_INT_SLPW                       CAN_INTEN_SLPWIE             /*!< sleep working interrupt enable */
-
-/* function declarations */
-/* deinitialize CAN */
-void can_deinit(uint32_t can_periph);
-/* initialize CAN struct */
-void can_struct_para_init(can_struct_type_enum type, void* p_struct);
-/* initialize CAN */
-ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init);
-/* CAN filter init */
-void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init);
-/* set can1 fliter start bank number */
-void can1_filter_start_bank(uint8_t start_bank);
-/* enable functions */
-/* CAN debug freeze enable */
-void can_debug_freeze_enable(uint32_t can_periph);
-/* CAN debug freeze disable */
-void can_debug_freeze_disable(uint32_t can_periph);
-/* CAN time triggle mode enable */
-void can_time_trigger_mode_enable(uint32_t can_periph);
-/* CAN time triggle mode disable */
-void can_time_trigger_mode_disable(uint32_t can_periph);
-
-/* transmit functions */
-/* transmit CAN message */
-uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message);
-/* get CAN transmit state */
-can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
-/* stop CAN transmission */
-void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
-/* CAN receive message */
-void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message);
-/* CAN release fifo */
-void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
-/* CAN receive message length */
-uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
-/* CAN working mode */
-ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
-/* CAN wakeup from sleep mode */
-ErrStatus can_wakeup(uint32_t can_periph);
-
-/* CAN get error */
-can_error_enum can_error_get(uint32_t can_periph);
-/* get CAN receive error number */
-uint8_t can_receive_error_number_get(uint32_t can_periph);
-/* get CAN transmit error number */
-uint8_t can_transmit_error_number_get(uint32_t can_periph);
-
-/* CAN interrupt enable */
-void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
-/* CAN interrupt disable */
-void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
-/* CAN get flag state */
-FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
-/* CAN clear flag state */
-void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
-/* CAN get interrupt flag state */
-FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
-/* CAN clear interrupt flag state */
-void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
-
-/* enable CAN phy */
-void can_phy_enable(uint32_t can_periph);
-/* disable CAN phy */
-void can_phy_disable(uint32_t can_periph);
-/* set CAN PHY mode */
-void can_phy_mode(uint32_t can_periph, uint32_t phy_mode);
-
-#endif /* GD32F1X0_CAN_H */
-
-#endif /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_dac.h

@@ -1,266 +0,0 @@
-/*!
-    \file  gd32f1x0_dac.h
-    \brief definitions for the DAC
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F1X0_DAC_H
-#define GD32F1X0_DAC_H
-
-#include "gd32f1x0.h"
-
-/* DACx(x=0,1) definitions */
-#define DAC                     DAC_BASE
-#define DAC0                    0U
-#ifdef GD32F170_190
-#define DAC1                    1U
-#endif  /* GD32F170_190 */
-
-/* registers definitions */
-#define DAC_CTL                 REG32(DAC + 0x00U) /*!< DAC control register */
-#define DAC_SWT                 REG32(DAC + 0x04U) /*!< DAC software trigger register */
-#define DAC0_R12DH              REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */
-#define DAC0_L12DH              REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */
-#define DAC0_R8DH               REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */
-#ifdef GD32F170_190
-#define DAC1_R12DH              REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */
-#define DAC1_L12DH              REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */
-#define DAC1_R8DH               REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */
-#define DACC_R12DH              REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
-#define DACC_L12DH              REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
-#define DACC_R8DH               REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
-#endif  /* GD32F170_190 */
-#define DAC0_DO                 REG32(DAC + 0x2CU) /*!< DAC0 output data register */
-#ifdef GD32F170_190
-#define DAC1_DO                 REG32(DAC + 0x30U) /*!< DAC1 output data register */
-#endif  /* GD32F170_190 */
-#define DAC_STAT                REG32(DAC + 0x34U) /*!< DAC status register */
-
-/* bits definitions */
-/* DAC_CTL */
-#define DAC_CTL_DEN0            BIT(0)             /*!< DAC0 enable/disable bit */
-#define DAC_CTL_DBOFF0          BIT(1)             /*!< DAC0 output buffer turn on/turn off bit */
-#define DAC_CTL_DTEN0           BIT(2)             /*!< DAC0 trigger enable/disable bit */
-#define DAC_CTL_DTSEL0          BITS(3,5)          /*!< DAC0 trigger source selection enable/disable bits */
-#define DAC_CTL_DDMAEN0         BIT(12)            /*!< DAC0 DMA enable/disanle bit */
-#define DAC_CTL_DDUDRIE0        BIT(13)            /*!< DAC0 DMA underrun Interrupt enable/disable bit */
-#ifdef GD32F170_190
-#define DAC_CTL_DEN1            BIT(16)            /*!< DAC1 enable/disable bit */ 
-#define DAC_CTL_DBOFF1          BIT(17)            /*!< DAC1 output buffer turn on/turn off bit */
-#define DAC_CTL_DTEN1           BIT(18)            /*!< DAC1 trigger enable/disable bit */
-#define DAC_CTL_DTSEL1          BITS(19,21)        /*!< DAC1 trigger source selection enable/disable bits */
-#define DAC_CTL_DDMAEN1         BIT(28)            /*!< DAC1 DMA enable/disable bit */
-#define DAC_CTL_DDUDRIE1        BIT(29)            /*!< DAC1 DMA underrun interrupt enable/disable bit */
-#endif  /* GD32F170_190 */
-
-/* DAC_SWT */
-#define DAC_SWT_SWTR0           BIT(0)             /*!< DAC0 software trigger bit,cleared by hardware */
-#ifdef GD32F170_190
-#define DAC_SWT_SWTR1           BIT(1)             /*!< DAC1 software trigger bit,cleared by hardware */
-#endif  /* GD32F170_190 */
-
-/* DAC0_R12DH */
-#define DAC0_R12DH_DAC0_DH      BITS(0,11)         /*!< DAC0 12-bit right-aligned data bits */
-
-/* DAC0_L12DH */
-#define DAC0_L12DH_DAC0_DH      BITS(4,15)         /*!< DAC0 12-bit left-aligned data bits */
-
-/* DAC0_R8DH */
-#define DAC0_R8DH_DAC0_DH       BITS(0,7)          /*!< DAC0 8-bit right-aligned data bits */
-
-#ifdef GD32F170_190
-/* DAC1_R12DH */
-#define DAC1_R12DH_DAC1_DH      BITS(0,11)         /*!< DAC1 12-bit right-aligned data bits */
-
-/* DAC1_L12DH */
-#define DAC1_L12DH_DAC1_DH      BITS(4,15)         /*!< DAC1 12-bit left-aligned data bits */
-
-/* DAC1_R8DH */
-#define DAC1_R8DH_DAC1_DH       BITS(0,7)          /*!< DAC1 8-bit right-aligned data bits */
-
-/* DACC_R12DH */
-#define DACC_R12DH_DAC0_DH      BITS(0,11)         /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
-#define DACC_R12DH_DAC1_DH      BITS(16,27)        /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
-
-/* DACC_L12DH */
-#define DACC_L12DH_DAC0_DH      BITS(4,15)         /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
-#define DACC_L12DH_DAC1_DH      BITS(20,31)        /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
-
-/* DACC_R8DH */
-#define DACC_R8DH_DAC0_DH       BITS(0,7)          /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
-#define DACC_R8DH_DAC1_DH       BITS(8,15)         /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
-#endif  /* GD32F170_190 */
-
-/* DAC0_DO */
-#define DAC0_DO_DAC0_DO         BITS(0,11)         /*!< DAC0 12-bit output data bits */
-
-#ifdef GD32F170_190
-/* DAC1_DO */
-#define DAC1_DO_DAC1_DO         BITS(0,11)         /*!< DAC1 12-bit output data bits */
-#endif  /* GD32F170_190 */
-
-/* DAC_STAT */
-#define DAC_STAT_DDUDR0         BIT(13)            /*!< DAC0 DMA underrun flag */
-#ifdef GD32F170_190
-#define DAC_STAT_DDUDR1         BIT(29)            /*!< DAC1 DMA underrun flag */
-#endif  /* GD32F170_190 */
-
-/* constants definitions */
-/* DAC trigger source */
-#define CTL_DTSEL(regval)       (BITS(3,5) & ((uint32_t)(regval) << 3))
-#define DAC_TRIGGER_T5_TRGO     CTL_DTSEL(0)       /*!< TIMER5 TRGO */
-#define DAC_TRIGGER_T2_TRGO     CTL_DTSEL(1)       /*!< TIMER2 TRGO */
-#define DAC_TRIGGER_T14_TRGO    CTL_DTSEL(3)       /*!< TIMER14 TRGO */
-#define DAC_TRIGGER_T1_TRGO     CTL_DTSEL(4)       /*!< TIMER1 TRGO */
-#define DAC_TRIGGER_EXTI_9    CTL_DTSEL(6)         /*!< EXTI interrupt line9 event */
-#define DAC_TRIGGER_SOFTWARE    CTL_DTSEL(7)       /*!< software trigger */
-
-/* dac data alignment */
-#define DATA_ALIGN(regval)      (BITS(0,1) & ((uint32_t)(regval) << 0))
-#define DAC_ALIGN_12B_R         DATA_ALIGN(0)      /*!< data right 12b alignment */
-#define DAC_ALIGN_12B_L         DATA_ALIGN(1)      /*!< data left 12b alignment */
-#define DAC_ALIGN_8B_R          DATA_ALIGN(2)      /*!< data right 8b alignment */
-
-/* function declarations */
-/* deinit DAC */
-void dac_deinit(void);
-
-/* enable DAC0 function */
-void dac0_enable(void);
-/* disable DAC0 function */
-void dac0_disable(void);
-/* enable DAC0 DMA function */
-void dac0_dma_enable(void);
-/* disable DAC0 DMA function */
-void dac0_dma_disable(void);
-/* enable DAC0 output buffer function */
-void dac0_output_buffer_enable(void);
-/* disable DAC0 output buffer function */
-void dac0_output_buffer_disable(void);
-/* enable DAC0 trigger function */
-void dac0_trigger_enable(void);
-/* disable DAC0 trigger function */
-void dac0_trigger_disable(void);
-/* enable DAC0 software trigger function */
-void dac0_software_trigger_enable(void);
-/* disable DAC0 software trigger function */
-void dac0_software_trigger_disable(void);
-/* enable DAC0 interrupt(DAC0 DMA underrun interrupt) */
-void dac0_interrupt_enable(void);
-/* disable DAC0 interrupt(DAC0 DMA underrun interrupt) */
-void dac0_interrupt_disable(void);
-
-/* set DAC0 tgigger source function */
-void dac0_trigger_source_config(uint32_t triggersource);
-/* get the last data output value */
-uint16_t dac0_output_value_get(void);
-
-/* get the specified DAC0 flag(DAC0 DMA underrun flag) */
-FlagStatus dac0_flag_get(void);
-/* clear the specified DAC0 flag(DAC0 DMA underrun flag) */
-void dac0_flag_clear(void);
-/* get the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag) */
-FlagStatus dac0_interrupt_flag_get(void);
-/* clear the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag) */
-void dac0_interrupt_flag_clear(void); 
-
-/* set DAC0 data holding register value */
-void dac0_data_set(uint32_t dac_align, uint16_t data);
-
-#ifdef GD32F170_190
-/* enable DAC */
-void dac_enable(uint32_t dac_periph);
-/* disable DAC */
-void dac_disable(uint32_t dac_periph);
-/* enable DAC DMA */
-void dac_dma_enable(uint32_t dac_periph);
-/* disable DAC DMA */
-void dac_dma_disable(uint32_t dac_periph); 
-/* enable DAC output buffer */
-void dac_output_buffer_enable(uint32_t dac_periph);
-/* disable DAC output buffer */
-void dac_output_buffer_disable(uint32_t dac_periph);
-/* enable DAC trigger */
-void dac_trigger_enable(uint32_t dac_periph);
-/* disable DAC trigger */
-void dac_trigger_disable(uint32_t dac_periph);
-/* enable DAC software trigger */
-void dac_software_trigger_enable(uint32_t dac_periph);
-/* disable DAC software trigger */
-void dac_software_trigger_disable(uint32_t dac_periph);
-/* enable DAC interrupt(DAC0 DMA underrun interrupt) */
-void dac_interrupt_enable(uint32_t dac_periph);
-/* disable DAC interrupt(DAC0 DMA underrun interrupt) */
-void dac_interrupt_disable(uint32_t dac_periph);
-
-/* set DAC tgigger source */
-void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource);
-/* get the last data output value */
-uint16_t dac_output_value_get(uint32_t dac_periph);
-
-/* get the specified DAC flag(DAC DMA underrun flag) */
-FlagStatus dac_flag_get(uint32_t dac_periph);
-/* clear the specified DAC flag(DAC DMA underrun flag) */
-void dac_flag_clear(uint32_t dac_periph);
-/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
-FlagStatus dac_interrupt_flag_get(uint32_t dac_periph);
-/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
-void dac_interrupt_flag_clear(uint32_t dac_periph);
-
-/* enable DAC concurrent mode */
-void dac_concurrent_enable(void);
-/* disable DAC concurrent mode */
-void dac_concurrent_disable(void);
-/* enable DAC concurrent software trigger */
-void dac_concurrent_software_trigger_enable(void);
-/* disable DAC concurrent software trigger */
-void dac_concurrent_software_trigger_disable(void);
-/* enable DAC concurrent buffer */
-void dac_concurrent_output_buffer_enable(void);
-/* disable DAC concurrent buffer */
-void dac_concurrent_output_buffer_disable(void);
-/* enable DAC concurrent interrupt */
-void dac_concurrent_interrupt_enable(void);
-/* disable DAC concurrent interrupt */
-void dac_concurrent_interrupt_disable(void);
-
-/* set DAC data holding register value */
-void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
-/* set DAC concurrent mode data holding register value */
-void dac_concurrent_data_set(uint32_t dac_align, uint16_t data1, uint16_t data2);
-
-#endif /* GD32F170_190 */
-
-#endif /* GD32F1X0_DAC_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_dbg.h

@@ -1,140 +0,0 @@
-/*!
-    \file  gd32f1x0_dbg.h
-    \brief definitions for the DBG
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F1X0_DBG_H
-#define GD32F1X0_DBG_H
-
-#include "gd32f1x0.h"
-
-/* DBG definitions */
-#define DBG                     DBG_BASE
-
-/* registers definitions */
-#define DBG_ID                  REG32(DBG + 0x00000000U)    /*!< DBG_ID code register */
-#define DBG_CTL0                REG32(DBG + 0x00000004U)    /*!< DBG control register 0 */
-#define DBG_CTL1                REG32(DBG + 0x00000008U)    /*!< DBG control register 1 */
-
-/* bits definitions */
-/* DBG_ID */
-#define DBG_ID_ID_CODE          BITS(0,31)                  /*!< DBG ID code values */
-
-/* DBG_CTL0 */
-#define DBG_CTL0_SLP_HOLD       BIT(0)                      /*!< keep debugger connection during sleep mode */
-#define DBG_CTL0_DSLP_HOLD      BIT(1)                      /*!< keep debugger connection during deepsleep mode */
-#define DBG_CTL0_STB_HOLD       BIT(2)                      /*!< keep debugger connection during standby mode */
-#define DBG_CTL0_FWDGT_HOLD     BIT(8)                      /*!< debug FWDGT kept when core is halted */
-#define DBG_CTL0_WWDGT_HOLD     BIT(9)                      /*!< debug WWDGT kept when core is halted */
-#define DBG_CTL0_TIMER0_HOLD    BIT(10)                     /*!< TIMER0 counter kept when core is halted */
-#define DBG_CTL0_TIMER1_HOLD    BIT(11)                     /*!< TIMER1 counter kept when core is halted */
-#define DBG_CTL0_TIMER2_HOLD    BIT(12)                     /*!< TIMER2 counter kept when core is halted */
-#define DBG_CTL0_I2C0_HOLD      BIT(15)                     /*!< hold I2C0 smbus when core is halted */
-#define DBG_CTL0_I2C1_HOLD      BIT(16)                     /*!< hold I2C1 smbus when core is halted */
-#define DBG_CTL0_I2C2_HOLD      BIT(17)                     /*!< hold I2C2 smbus when core is halted */
-#ifdef GD32F170_190
-#define DBG_CTL0_CAN0_HOLD      BIT(18)                     /*!< CAN0 counter kept when core is halted */
-#endif /* GD32F170_190 */
-#define DBG_CTL0_TIMER5_HOLD    BIT(19)                     /*!< hold TIMER5 counter when core is halted */
-#ifdef GD32F170_190
-#define DBG_CTL0_CAN1_HOLD      BIT(21)                     /*!< hold CAN1 counter when core is halted */
-#endif /* GD32F170_190 */
-#define DBG_CTL0_TIMER13_HOLD   BIT(27)                     /*!< hold TIMER13 counter when core is halted */
-
-/* DBG_CTL1 */
-#define DBG_CTL1_RTC_HOLD       BIT(10)                     /*!< hold RTC calendar and wakeup counter when core is halted */
-#define DBG_CTL1_TIMER14_HOLD   BIT(16)                     /*!< hold TIMER14 counter when core is halted */
-#define DBG_CTL1_TIMER15_HOLD   BIT(17)                     /*!< hold TIMER15 counter when core is halted */
-#define DBG_CTL1_TIMER16_HOLD   BIT(18)                     /*!< hold TIMER16 counter when core is halted */
-
-/* constants definitions */
-#define DBG_LOW_POWER_SLEEP     DBG_CTL0_SLP_HOLD           /*!< keep debugger connection during sleep mode */
-#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD          /*!< keep debugger connection during deepsleep mode */
-#define DBG_LOW_POWER_STANDBY   DBG_CTL0_STB_HOLD           /*!< keep debugger connection during standby mode */
-
-/* define the peripheral debug hold bit position and its register index offset */
-#define DBG_REGIDX_BIT(regidx, bitpos)      (((regidx) << 6) | (bitpos))
-#define DBG_REG_VAL(periph)                 (REG32(DBG + ((uint32_t)(periph) >> 6)))
-#define DBG_BIT_POS(val)                    ((uint32_t)(val) & 0x0000001FU)
-
-/* register index */
-typedef enum 
-{
-    DBG_IDX_CTL0            = 0x04U,                                         /*!< DBG control register 0 offset */
-    DBG_IDX_CTL1            = 0x08U,                                         /*!< DBG control register 1 offset */
-}dbg_reg_idx;
-
-/* peripherals hold bit */
-typedef enum
-{
-    DBG_FWDGT_HOLD          = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U),              /*!< FWDGT hold bit */
-    DBG_WWDGT_HOLD          = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U),              /*!< WWDGT hold bit */
-    DBG_TIMER0_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U),             /*!< TIMER0 hold bit */
-    DBG_TIMER1_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U),             /*!< TIMER1 hold bit */
-    DBG_TIMER2_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U),             /*!< TIMER2 hold bit */
-#ifdef GD32F170_190
-    DBG_CAN0_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL0, 14U),             /*!< CAN0 hold bit */
-#endif /* GD32F170_190 */
-    DBG_I2C0_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U),             /*!< I2C0 hold bit */
-    DBG_I2C1_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U),             /*!< I2C1 hold bit */
-    DBG_I2C2_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL0, 17U),             /*!< I2C2 hold bit */
-    DBG_TIMER5_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U),             /*!< TIMER5 hold bit */
-#ifdef GD32F170_190
-    DBG_CAN1_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL0, 21U),             /*!< CAN1 hold bit */
-#endif /* GD32F170_190 */
-    DBG_TIMER13_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U),             /*!< TIMER13 hold bit */
-    DBG_RTC_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U),             /*!< RTC hold bit */
-    DBG_TIMER14_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U),             /*!< TIMER14 hold bit */
-    DBG_TIMER15_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U),             /*!< TIMER15 hold bit */
-    DBG_TIMER16_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U),             /*!< TIMER16 hold bit */
-}dbg_periph_enum;
-
-/* function declarations */
-/* deinitialize the DBG */
-void dbg_deinit(void);
-/* read DBG_ID code register */
-uint32_t dbg_id_get(void);
-
-/* enable low power behavior when the MCU is in debug mode */
-void dbg_low_power_enable(uint32_t dbg_low_power);
-/* disable low power behavior when the MCU is in debug mode */
-void dbg_low_power_disable(uint32_t dbg_low_power);
-
-/* enable peripheral behavior when the MCU is in debug mode */
-void dbg_periph_enable(dbg_periph_enum dbg_periph);
-/* disable peripheral behavior when the MCU is in debug mode */
-void dbg_periph_disable(dbg_periph_enum dbg_periph);
-#endif /* GD32F1X0_DBG_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_dma.h

@@ -1,278 +0,0 @@
-/*!
-    \file  gd32f1x0_dma.h
-    \brief definitions for the DMA
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F1X0_DMA_H
-#define GD32F1X0_DMA_H
-
-#include "gd32f1x0.h"
-
-/* DMA definitions */
-#define DMA                               DMA_BASE               /*!< DMA base address */
-
-/* registers definitions */
-#define DMA_INTF                          REG32(DMA + 0x00U)     /*!< DMA interrupt flag register */
-#define DMA_INTC                          REG32(DMA + 0x04U)     /*!< DMA interrupt flag clear register */
-
-#define DMA_CH0CTL                        REG32(DMA + 0x08U)     /*!< DMA channel 0 control register */
-#define DMA_CH0CNT                        REG32(DMA + 0x0CU)     /*!< DMA channel 0 counter register */
-#define DMA_CH0PADDR                      REG32(DMA + 0x10U)     /*!< DMA channel 0 peripheral base address register */
-#define DMA_CH0MADDR                      REG32(DMA + 0x14U)     /*!< DMA channel 0 memory base address register */
-
-#define DMA_CH1CTL                        REG32(DMA + 0x1CU)     /*!< DMA channel 1 control register */
-#define DMA_CH1CNT                        REG32(DMA + 0x20U)     /*!< DMA channel 1 counter register */
-#define DMA_CH1PADDR                      REG32(DMA + 0x24U)     /*!< DMA channel 1 peripheral base address register */
-#define DMA_CH1MADDR                      REG32(DMA + 0x28U)     /*!< DMA channel 1 memory base address register */
-
-#define DMA_CH2CTL                        REG32(DMA + 0x30U)     /*!< DMA channel 2 control register */
-#define DMA_CH2CNT                        REG32(DMA + 0x34U)     /*!< DMA channel 2 counter register */
-#define DMA_CH2PADDR                      REG32(DMA + 0x38U)     /*!< DMA channel 2 peripheral base address register */
-#define DMA_CH2MADDR                      REG32(DMA + 0x3CU)     /*!< DMA channel 2 memory base address register */
-
-#define DMA_CH3CTL                        REG32(DMA + 0x44U)     /*!< DMA channel 3 control register */
-#define DMA_CH3CNT                        REG32(DMA + 0x48U)     /*!< DMA channel 3 counter register */
-#define DMA_CH3PADDR                      REG32(DMA + 0x4CU)     /*!< DMA channel 3 peripheral base address register */
-#define DMA_CH3MADDR                      REG32(DMA + 0x50U)     /*!< DMA channel 3 memory base address register */
-
-#define DMA_CH4CTL                        REG32(DMA + 0x58U)     /*!< DMA channel 4 control register */
-#define DMA_CH4CNT                        REG32(DMA + 0x5CU)     /*!< DMA channel 4 counter register */
-#define DMA_CH4PADDR                      REG32(DMA + 0x60U)     /*!< DMA channel 4 peripheral base address register */
-#define DMA_CH4MADDR                      REG32(DMA + 0x64U)     /*!< DMA channel 4 memory base address register */
-
-#define DMA_CH5CTL                        REG32(DMA + 0x6CU)     /*!< DMA channel 5 control register */
-#define DMA_CH5CNT                        REG32(DMA + 0x70U)     /*!< DMA channel 5 counter register */
-#define DMA_CH5PADDR                      REG32(DMA + 0x74U)     /*!< DMA channel 5 peripheral base address register */
-#define DMA_CH5MADDR                      REG32(DMA + 0x78U)     /*!< DMA channel 5 memory base address register */
-
-#define DMA_CH6CTL                        REG32(DMA + 0x80U)     /*!< DMA channel 6 control register */
-#define DMA_CH6CNT                        REG32(DMA + 0x84U)     /*!< DMA channel 6 counter register */
-#define DMA_CH6PADDR                      REG32(DMA + 0x88U)     /*!< DMA channel 6 peripheral base address register */
-#define DMA_CH6MADDR                      REG32(DMA + 0x8CU)     /*!< DMA channel 6 memory base address register */
-
-/* bits definitions */
-/* DMA_INTF */
-#define DMA_INTF_GIF                      BIT(0)                 /*!< global interrupt flag of channel */
-#define DMA_INTF_FTFIF                    BIT(1)                 /*!< transfer complete flag of channel */
-#define DMA_INTF_HTFIF                    BIT(2)                 /*!< half transfer complete flag of channel */
-#define DMA_INTF_ERRIF                    BIT(3)                 /*!< error flag of channel */
-
-/* DMA_INTC */
-#define DMA_INTFC_GIFC                    BIT(0)                 /*!< clear global interrupt flag of channel */
-#define DMA_INTFC_FTFIFC                  BIT(1)                 /*!< clear transfer complete flag of channel */
-#define DMA_INTFC_HTFIFC                  BIT(2)                 /*!< clear half transfer complete flag of channel */
-#define DMA_INTFC_ERRIFC                  BIT(3)                 /*!< clear error flag of channel */
-
-/* DMA_CHxCTL,x=0..6 */
-#define DMA_CHXCTL_CHEN                   BIT(0)                 /*!< channel x enable */
-#define DMA_CHXCTL_FTFIE                  BIT(1)                 /*!< enable bit for channel x transfer complete interrupt */
-#define DMA_CHXCTL_HTFIE                  BIT(2)                 /*!< enable bit for channel x transfer half complete interrupt */
-#define DMA_CHXCTL_ERRIE                  BIT(3)                 /*!< enable bit for channel x error interrupt */
-#define DMA_CHXCTL_DIR                    BIT(4)                 /*!< transfer direction */
-#define DMA_CHXCTL_CMEN                   BIT(5)                 /*!< circulation mode */
-#define DMA_CHXCTL_PNAGA                  BIT(6)                 /*!< next address generation algorithm of peripheral */
-#define DMA_CHXCTL_MNAGA                  BIT(7)                 /*!< next address generation algorithm of memory */
-#define DMA_CHXCTL_PWIDTH                 BITS(8,9)              /*!< transfer data size of peripheral */
-#define DMA_CHXCTL_MWIDTH                 BITS(10,11)            /*!< transfer data size of memory */
-#define DMA_CHXCTL_PRIO                   BITS(12,13)            /*!< priority level of channelx */
-#define DMA_CHXCTL_M2M                    BIT(14)                /*!< memory to memory mode */
-
-/* DMA_CHxCNT, x=0..6 */
-#define DMA_CHXCNT_CNT                    BITS(0,15)             /*!< transfer counter */
-
-/* DMA_CHxPADDR, x=0..6 */
-#define DMA_CHXPADDR_PADDR                BITS(0,31)             /*!< peripheral base address */
-
-/* DMA_CHxMADDR, x=0..6 */
-#define DMA_CHXMADDR_MADDR                BITS(0,31)             /*!< memory base address */
-
-/* constants definitions */
-/* DMA channel select */
-typedef enum 
-{
-    DMA_CH0 = 0,            /*!< DMA Channel0 */
-    DMA_CH1,                /*!< DMA Channel1 */ 
-    DMA_CH2,                /*!< DMA Channel2 */ 
-    DMA_CH3,                /*!< DMA Channel3 */ 
-    DMA_CH4,                /*!< DMA Channel4 */ 
-    DMA_CH5,                /*!< DMA Channel5 */ 
-    DMA_CH6                 /*!< DMA Channel6 */
-} dma_channel_enum;
-
-/* DMA initialize struct */
-typedef struct
-{
-    uint32_t periph_addr;   /*!< peripheral base address */
-    uint32_t periph_width;  /*!< transfer data size of peripheral */
-    uint32_t periph_inc;    /*!< peripheral increasing mode */
-    uint32_t memory_addr;   /*!< memory base address */
-    uint32_t memory_width;  /*!< transfer data size of memory */
-    uint32_t memory_inc;    /*!< memory increasing mode */
-    uint32_t direction;     /*!< channel data transfer direction */
-    uint32_t number;        /*!< channel transfer number */
-    uint32_t priority;      /*!< channel priority level */
-} dma_parameter_struct;
-
-/* flag bits */
-#define DMA_FLAG_G                        DMA_INTF_GIF           /*!< global interrupt flag of channel */
-#define DMA_FLAG_FTF                      DMA_INTF_FTFIF         /*!< full transfer finish flag of channel */
-#define DMA_FLAG_HTF                      DMA_INTF_HTFIF         /*!< half transfer finish flag of channel */
-#define DMA_FLAG_ERR                      DMA_INTF_ERRIF         /*!< error flag of channel */
-
-/* interrupt flag bits */
-#define DMA_INT_FLAG_G                    DMA_INTF_GIF           /*!< global interrupt flag of channel */
-#define DMA_INT_FLAG_FTF                  DMA_INTF_FTFIF         /*!< full transfer finish interrupt flag of channel */
-#define DMA_INT_FLAG_HTF                  DMA_INTF_HTFIF         /*!< half transfer finish interrupt flag of channel */
-#define DMA_INT_FLAG_ERR                  DMA_INTF_ERRIF         /*!< error interrupt flag of channel */
-
-/* interrupt enable bits */
-#define DMA_INT_FTF                       DMA_CHXCTL_FTFIE       /*!< enable bit for channel full transfer finish interrupt */
-#define DMA_INT_HTF                       DMA_CHXCTL_HTFIE       /*!< enable bit for channel half transfer finish interrupt */
-#define DMA_INT_ERR                       DMA_CHXCTL_ERRIE       /*!< enable bit for channel error interrupt */
-
-/* DMA_CHCTL base address */
-#define DMA_CHXCTL_BASE                   (DMA + 0x08U)          /*!< the base address of DMA channel CHXCTL register */
-#define DMA_CHXCNT_BASE                   (DMA + 0x0CU)          /*!< the base address of DMA channel CHXCNT register */
-#define DMA_CHXPADDR_BASE                 (DMA + 0x10U)          /*!< the base address of DMA channel CHXPADDR register */
-#define DMA_CHXMADDR_BASE                 (DMA + 0x14U)          /*!< the base address of DMA channel CHXMADDR register */
-#define DMA_FLAG_ADD(flag,shift)          ((uint32_t)(flag)<<((uint32_t)(shift)*4U))   /*!< DMA channel flag shift */
-
-/* DMA channel shift bit */
-#define DMA_CHCTL(channel)                REG32(DMA_CHXCTL_BASE + 0x14U*(channel))     /*!< the address of DMA channel CHXCTL register  */
-#define DMA_CHCNT(channel)                REG32(DMA_CHXCNT_BASE + 0x14U*(channel))     /*!< the address of DMA channel CHXCNT register */
-#define DMA_CHPADDR(channel)              REG32(DMA_CHXPADDR_BASE + 0x14U*(channel))   /*!< the address of DMA channel CHXPADDR register */
-#define DMA_CHMADDR(channel)              REG32(DMA_CHXMADDR_BASE + 0x14U*(channel))   /*!< the address of DMA channel CHXMADDR register */
-
-/* channel priority level */
-#define CHCTL_PRIO(regval)                (BITS(12,13) & ((regval) << 12U))            /*!< DMA channel priority level */
-#define DMA_PRIORITY_LOW                  CHCTL_PRIO(0U)                               /*!< low priority */
-#define DMA_PRIORITY_MEDIUM               CHCTL_PRIO(1U)                               /*!< medium priority */
-#define DMA_PRIORITY_HIGH                 CHCTL_PRIO(2U)                               /*!< high priority */
-#define DMA_PRIORITY_ULTRA_HIGH           CHCTL_PRIO(3U)                               /*!< ultra high priority */
-
-/* transfer data size of memory */
-#define CHCTL_MSIZE(regval)               (BITS(10,11) & ((regval) << 10U))            /*!< transfer data size of memory */
-#define DMA_MEMORY_WIDTH_8BIT             CHCTL_MSIZE(0U)                              /*!< transfer data size of memory is 8-bit */
-#define DMA_MEMORY_WIDTH_16BIT            CHCTL_MSIZE(1U)                              /*!< transfer data size of memory is 16-bit */
-#define DMA_MEMORY_WIDTH_32BIT            CHCTL_MSIZE(2U)                              /*!< transfer data size of memory is 32-bit */
-
-/* transfer data size of peripheral */
-#define CHCTL_PSIZE(regval)               (BITS(8,9) & ((regval) << 8U))               /*!< transfer data size of peripheral */
-#define DMA_PERIPHERAL_WIDTH_8BIT         CHCTL_PSIZE(0U)                              /*!< transfer data size of peripheral is 8-bit */
-#define DMA_PERIPHERAL_WIDTH_16BIT        CHCTL_PSIZE(1U)                              /*!< transfer data size of peripheral is 16-bit */
-#define DMA_PERIPHERAL_WIDTH_32BIT        CHCTL_PSIZE(2U)                              /*!< transfer data size of peripheral is 32-bit */
-
-/* channel data transfer direction */
-#define DMA_PERIPHERAL_TO_MEMORY          ((uint32_t)0x00000000U)                      /*!< read from peripheral and write to memory */
-#define DMA_MEMORY_TO_PERIPHERAL          ((uint32_t)0x00000001U)                      /*!< read from memory and write to peripheral */
-
-/* peripheral increasing mode */
-#define DMA_PERIPH_INCREASE_ENABLE        ((uint32_t)0x00000000U)                      /*!< next address of peripheral is increasing address mode */
-#define DMA_PERIPH_INCREASE_DISABLE       ((uint32_t)0x00000001U)                      /*!< next address of peripheral is fixed address mode */
-
-/* memory increasing mode */
-#define DMA_MEMORY_INCREASE_ENABLE        ((uint32_t)0x00000000U)                      /*!< next address of memory is increasing address mode */
-#define DMA_MEMORY_INCREASE_DISABLE       ((uint32_t)0x00000001U)                      /*!< next address of memory is fixed address mode */
-
-/* DMA reset value */
-#define DMA_CHCTL_RESET_VALUE             ((uint32_t)0x00000000U)                      /*!< the reset value of DMA channel CHXCTL register  */
-#define DMA_CHCNT_RESET_VALUE             ((uint32_t)0x00000000U)                      /*!< the reset value of DMA channel CHXCNT register  */
-#define DMA_CHPADDR_RESET_VALUE           ((uint32_t)0x00000000U)                      /*!< the reset value of DMA channel CHXPADDR register  */
-#define DMA_CHMADDR_RESET_VALUE           ((uint32_t)0x00000000U)                      /*!< the reset value of DMA channel CHXMADDR register  */
-#define DMA_CHINTF_RESET_VALUE            ((uint32_t)0x0000000FU)                      /*!< clear DMA channel CHXINTFS register  */
-
-/* function declarations */
-/* DMA initialization functions */
-/* deinitialize DMA a channel registers */
-void dma_deinit(dma_channel_enum channelx);
-/* initialize the parameters of DMA struct with the default values */
-void dma_struct_para_init(dma_parameter_struct* init_struct);
-/* initialize DMA channel */
-void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct);
-/* enable DMA circulation mode */
-void dma_circulation_enable(dma_channel_enum channelx);
-/* disable DMA circulation mode */
-void dma_circulation_disable(dma_channel_enum channelx);
-/* enable memory to memory mode */
-void dma_memory_to_memory_enable(dma_channel_enum channelx);
-/* disable memory to memory mode */
-void dma_memory_to_memory_disable(dma_channel_enum channelx);
-/* enable DMA channel */
-void dma_channel_enable(dma_channel_enum channelx);
-/* disable DMA channel */
-void dma_channel_disable(dma_channel_enum channelx);
-
-/* DMA configuration functions */
-/* set DMA peripheral base address */
-void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
-/* set DMA Memory base address */
-void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
-/* set the number of remaining data to be transferred by the DMA */
-void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
-/* get the number of remaining data to be transferred by the DMA */
-uint32_t dma_transfer_number_get(dma_channel_enum channelx);
-/* configure priority level of DMA channel */
-void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
-/* configure transfer data size of memory */
-void dma_memory_width_config (dma_channel_enum channelx, uint32_t msize);
-/* configure transfer data size of peripheral */
-void dma_periph_width_config (dma_channel_enum channelx, uint32_t psize);
-/* enable next address increasement algorithm of memory */
-void dma_memory_increase_enable(dma_channel_enum channelx);
-/* disable next address increasement algorithm of memory */
-void dma_memory_increase_disable(dma_channel_enum channelx);
-/* enable next address increasement algorithm of peripheral */
-void dma_periph_increase_enable(dma_channel_enum channelx);
-/* disable next address increasement algorithm of peripheral */
-void dma_periph_increase_disable(dma_channel_enum channelx);
-/* configure the direction of data transfer on the channel */
-void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction);
-
-/* DMA interrupt and flag functions */
-/* check DMA flag is set or not */
-FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
-/* clear DMA a channel flag */
-void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
-/* enable DMA interrupt */
-void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
-/* disable DMA interrupt */
-void dma_interrupt_disable(dma_channel_enum channelx,uint32_t source);
-/* check DMA flag is set or not */
-FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
-/* clear DMA a channel flag */
-void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
-
-#endif /* GD32F1X0_DMA_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_exti.h

@@ -1,290 +0,0 @@
-/*!
-    \file  gd32f1x0_exti.h
-    \brief definitions for the EXTI
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F1X0_EXTI_H
-#define GD32F1X0_EXTI_H
-
-#include "gd32f1x0.h"
-
-/* EXTI definitions */
-#define EXTI                        EXTI_BASE
-
-/* registers definitions */
-#define EXTI_INTEN                  REG32(EXTI + 0x00000000U)       /*!< interrupt enable register */
-#define EXTI_EVEN                   REG32(EXTI + 0x00000004U)       /*!< event enable register */
-#define EXTI_RTEN                   REG32(EXTI + 0x00000008U)       /*!< rising edge trigger enable register */
-#define EXTI_FTEN                   REG32(EXTI + 0x0000000CU)       /*!< falling trigger enable register */
-#define EXTI_SWIEV                  REG32(EXTI + 0x00000010U)       /*!< software interrupt event register */
-#define EXTI_PD                     REG32(EXTI + 0x00000014U)       /*!< pending register */
-
-/* bits definitions */
-/* EXTI_INTEN */
-#define EXTI_INTEN_INTEN0           BIT(0)                   /*!< interrupt from line 0 */
-#define EXTI_INTEN_INTEN1           BIT(1)                   /*!< interrupt from line 1 */
-#define EXTI_INTEN_INTEN2           BIT(2)                   /*!< interrupt from line 2 */
-#define EXTI_INTEN_INTEN3           BIT(3)                   /*!< interrupt from line 3 */
-#define EXTI_INTEN_INTEN4           BIT(4)                   /*!< interrupt from line 4 */
-#define EXTI_INTEN_INTEN5           BIT(5)                   /*!< interrupt from line 5 */
-#define EXTI_INTEN_INTEN6           BIT(6)                   /*!< interrupt from line 6 */
-#define EXTI_INTEN_INTEN7           BIT(7)                   /*!< interrupt from line 7 */
-#define EXTI_INTEN_INTEN8           BIT(8)                   /*!< interrupt from line 8 */
-#define EXTI_INTEN_INTEN9           BIT(9)                   /*!< interrupt from line 9 */
-#define EXTI_INTEN_INTEN10          BIT(10)                  /*!< interrupt from line 10 */
-#define EXTI_INTEN_INTEN11          BIT(11)                  /*!< interrupt from line 11 */
-#define EXTI_INTEN_INTEN12          BIT(12)                  /*!< interrupt from line 12 */
-#define EXTI_INTEN_INTEN13          BIT(13)                  /*!< interrupt from line 13 */
-#define EXTI_INTEN_INTEN14          BIT(14)                  /*!< interrupt from line 14 */
-#define EXTI_INTEN_INTEN15          BIT(15)                  /*!< interrupt from line 15 */
-#define EXTI_INTEN_INTEN16          BIT(16)                  /*!< interrupt from line 16 */
-#define EXTI_INTEN_INTEN17          BIT(17)                  /*!< interrupt from line 17 */
-#define EXTI_INTEN_INTEN18          BIT(18)                  /*!< interrupt from line 18 */
-#define EXTI_INTEN_INTEN19          BIT(19)                  /*!< interrupt from line 19 */
-#define EXTI_INTEN_INTEN20          BIT(20)                  /*!< interrupt from line 20 */
-#define EXTI_INTEN_INTEN21          BIT(21)                  /*!< interrupt from line 21 */
-#define EXTI_INTEN_INTEN22          BIT(22)                  /*!< interrupt from line 22 */
-#define EXTI_INTEN_INTEN23          BIT(23)                  /*!< interrupt from line 23 */
-#define EXTI_INTEN_INTEN24          BIT(24)                  /*!< interrupt from line 24 */
-#define EXTI_INTEN_INTEN25          BIT(25)                  /*!< interrupt from line 25 */
-#define EXTI_INTEN_INTEN26          BIT(26)                  /*!< interrupt from line 26 */
-#define EXTI_INTEN_INTEN27          BIT(27)                  /*!< interrupt from line 27 */
-
-/* EXTI_EVEN */
-#define EXTI_EVEN_EVEN0             BIT(0)                   /*!< event from line 0 */
-#define EXTI_EVEN_EVEN1             BIT(1)                   /*!< event from line 1 */
-#define EXTI_EVEN_EVEN2             BIT(2)                   /*!< event from line 2 */
-#define EXTI_EVEN_EVEN3             BIT(3)                   /*!< event from line 3 */
-#define EXTI_EVEN_EVEN4             BIT(4)                   /*!< event from line 4 */
-#define EXTI_EVEN_EVEN5             BIT(5)                   /*!< event from line 5 */
-#define EXTI_EVEN_EVEN6             BIT(6)                   /*!< event from line 6 */
-#define EXTI_EVEN_EVEN7             BIT(7)                   /*!< event from line 7 */
-#define EXTI_EVEN_EVEN8             BIT(8)                   /*!< event from line 8 */
-#define EXTI_EVEN_EVEN9             BIT(9)                   /*!< event from line 9 */
-#define EXTI_EVEN_EVEN10            BIT(10)                  /*!< event from line 10 */
-#define EXTI_EVEN_EVEN11            BIT(11)                  /*!< event from line 11 */
-#define EXTI_EVEN_EVEN12            BIT(12)                  /*!< event from line 12 */
-#define EXTI_EVEN_EVEN13            BIT(13)                  /*!< event from line 13 */
-#define EXTI_EVEN_EVEN14            BIT(14)                  /*!< event from line 14 */
-#define EXTI_EVEN_EVEN15            BIT(15)                  /*!< event from line 15 */
-#define EXTI_EVEN_EVEN16            BIT(16)                  /*!< event from line 16 */
-#define EXTI_EVEN_EVEN17            BIT(17)                  /*!< event from line 17 */
-#define EXTI_EVEN_EVEN18            BIT(18)                  /*!< event from line 18 */
-#define EXTI_EVEN_EVEN19            BIT(19)                  /*!< event from line 19 */
-#define EXTI_EVEN_EVEN20            BIT(20)                  /*!< event from line 20 */
-#define EXTI_EVEN_EVEN21            BIT(21)                  /*!< event from line 21 */
-#define EXTI_EVEN_EVEN22            BIT(22)                  /*!< event from line 22 */
-#define EXTI_EVEN_EVEN23            BIT(23)                  /*!< event from line 23 */
-#define EXTI_EVEN_EVEN24            BIT(24)                  /*!< event from line 24 */
-#define EXTI_EVEN_EVEN25            BIT(25)                  /*!< event from line 25 */
-#define EXTI_EVEN_EVEN26            BIT(26)                  /*!< event from line 26 */
-#define EXTI_EVEN_EVEN27            BIT(27)                  /*!< event from line 27 */
-
-/* EXTI_RTEN */
-#define EXTI_RTEN_RTEN0             BIT(0)                   /*!< rising edge from line 0 */
-#define EXTI_RTEN_RTEN1             BIT(1)                   /*!< rising edge from line 1 */
-#define EXTI_RTEN_RTEN2             BIT(2)                   /*!< rising edge from line 2 */
-#define EXTI_RTEN_RTEN3             BIT(3)                   /*!< rising edge from line 3 */
-#define EXTI_RTEN_RTEN4             BIT(4)                   /*!< rising edge from line 4 */
-#define EXTI_RTEN_RTEN5             BIT(5)                   /*!< rising edge from line 5 */
-#define EXTI_RTEN_RTEN6             BIT(6)                   /*!< rising edge from line 6 */
-#define EXTI_RTEN_RTEN7             BIT(7)                   /*!< rising edge from line 7 */
-#define EXTI_RTEN_RTEN8             BIT(8)                   /*!< rising edge from line 8 */
-#define EXTI_RTEN_RTEN9             BIT(9)                   /*!< rising edge from line 9 */
-#define EXTI_RTEN_RTEN10            BIT(10)                  /*!< rising edge from line 10 */
-#define EXTI_RTEN_RTEN11            BIT(11)                  /*!< rising edge from line 11 */
-#define EXTI_RTEN_RTEN12            BIT(12)                  /*!< rising edge from line 12 */
-#define EXTI_RTEN_RTEN13            BIT(13)                  /*!< rising edge from line 13 */
-#define EXTI_RTEN_RTEN14            BIT(14)                  /*!< rising edge from line 14 */
-#define EXTI_RTEN_RTEN15            BIT(15)                  /*!< rising edge from line 15 */
-#define EXTI_RTEN_RTEN16            BIT(16)                  /*!< rising edge from line 16 */
-#define EXTI_RTEN_RTEN17            BIT(17)                  /*!< rising edge from line 17 */
-#define EXTI_RTEN_RTEN18            BIT(18)                  /*!< rising edge from line 18 */
-#define EXTI_RTEN_RTEN19            BIT(19)                  /*!< rising edge from line 19 */
-#define EXTI_RTEN_RTEN21            BIT(21)                  /*!< rising edge from line 21 */
-#define EXTI_RTEN_RTEN22            BIT(22)                  /*!< rising edge from line 22 */
-
-/* EXTI_FTEN */
-#define EXTI_FTEN_FTEN0             BIT(0)                   /*!< falling edge from line 0 */
-#define EXTI_FTEN_FTEN1             BIT(1)                   /*!< falling edge from line 1 */
-#define EXTI_FTEN_FTEN2             BIT(2)                   /*!< falling edge from line 2 */
-#define EXTI_FTEN_FTEN3             BIT(3)                   /*!< falling edge from line 3 */
-#define EXTI_FTEN_FTEN4             BIT(4)                   /*!< falling edge from line 4 */
-#define EXTI_FTEN_FTEN5             BIT(5)                   /*!< falling edge from line 5 */
-#define EXTI_FTEN_FTEN6             BIT(6)                   /*!< falling edge from line 6 */
-#define EXTI_FTEN_FTEN7             BIT(7)                   /*!< falling edge from line 7 */
-#define EXTI_FTEN_FTEN8             BIT(8)                   /*!< falling edge from line 8 */
-#define EXTI_FTEN_FTEN9             BIT(9)                   /*!< falling edge from line 9 */
-#define EXTI_FTEN_FTEN10            BIT(10)                  /*!< falling edge from line 10 */
-#define EXTI_FTEN_FTEN11            BIT(11)                  /*!< falling edge from line 11 */
-#define EXTI_FTEN_FTEN12            BIT(12)                  /*!< falling edge from line 12 */
-#define EXTI_FTEN_FTEN13            BIT(13)                  /*!< falling edge from line 13 */
-#define EXTI_FTEN_FTEN14            BIT(14)                  /*!< falling edge from line 14 */
-#define EXTI_FTEN_FTEN15            BIT(15)                  /*!< falling edge from line 15 */
-#define EXTI_FTEN_FTEN16            BIT(16)                  /*!< falling edge from line 16 */
-#define EXTI_FTEN_FTEN17            BIT(17)                  /*!< falling edge from line 17 */
-#define EXTI_FTEN_FTEN18            BIT(18)                  /*!< falling edge from line 18 */
-#define EXTI_FTEN_FTEN19            BIT(19)                  /*!< falling edge from line 19 */
-#define EXTI_FTEN_FTEN21            BIT(21)                  /*!< falling edge from line 21 */
-#define EXTI_FTEN_FTEN22            BIT(22)                  /*!< falling edge from line 22 */
-
-/* EXTI_SWIEV */
-#define EXTI_SWIEV_SWIEV0           BIT(0)                   /*!< software interrupt/event request from line 0 */
-#define EXTI_SWIEV_SWIEV1           BIT(1)                   /*!< software interrupt/event request from line 1 */
-#define EXTI_SWIEV_SWIEV2           BIT(2)                   /*!< software interrupt/event request from line 2 */
-#define EXTI_SWIEV_SWIEV3           BIT(3)                   /*!< software interrupt/event request from line 3 */
-#define EXTI_SWIEV_SWIEV4           BIT(4)                   /*!< software interrupt/event request from line 4 */
-#define EXTI_SWIEV_SWIEV5           BIT(5)                   /*!< software interrupt/event request from line 5 */
-#define EXTI_SWIEV_SWIEV6           BIT(6)                   /*!< software interrupt/event request from line 6 */
-#define EXTI_SWIEV_SWIEV7           BIT(7)                   /*!< software interrupt/event request from line 7 */
-#define EXTI_SWIEV_SWIEV8           BIT(8)                   /*!< software interrupt/event request from line 8 */
-#define EXTI_SWIEV_SWIEV9           BIT(9)                   /*!< software interrupt/event request from line 9 */
-#define EXTI_SWIEV_SWIEV10          BIT(10)                  /*!< software interrupt/event request from line 10 */
-#define EXTI_SWIEV_SWIEV11          BIT(11)                  /*!< software interrupt/event request from line 11 */
-#define EXTI_SWIEV_SWIEV12          BIT(12)                  /*!< software interrupt/event request from line 12 */
-#define EXTI_SWIEV_SWIEV13          BIT(13)                  /*!< software interrupt/event request from line 13 */
-#define EXTI_SWIEV_SWIEV14          BIT(14)                  /*!< software interrupt/event request from line 14 */
-#define EXTI_SWIEV_SWIEV15          BIT(15)                  /*!< software interrupt/event request from line 15 */
-#define EXTI_SWIEV_SWIEV16          BIT(16)                  /*!< software interrupt/event request from line 16 */
-#define EXTI_SWIEV_SWIEV17          BIT(17)                  /*!< software interrupt/event request from line 17 */
-#define EXTI_SWIEV_SWIEV18          BIT(18)                  /*!< software interrupt/event request from line 18 */
-#define EXTI_SWIEV_SWIEV19          BIT(19)                  /*!< software interrupt/event request from line 19 */
-#define EXTI_SWIEV_SWIEV21          BIT(21)                  /*!< software interrupt/event request from line 21 */
-#define EXTI_SWIEV_SWIEV22          BIT(22)                  /*!< software interrupt/event request from line 22 */
-
-/* EXTI_PD */
-#define EXTI_PD_PD0                 BIT(0)                   /*!< interrupt/event pending status from line 0 */
-#define EXTI_PD_PD1                 BIT(1)                   /*!< interrupt/event pending status from line 1 */
-#define EXTI_PD_PD2                 BIT(2)                   /*!< interrupt/event pending status from line 2 */
-#define EXTI_PD_PD3                 BIT(3)                   /*!< interrupt/event pending status from line 3 */
-#define EXTI_PD_PD4                 BIT(4)                   /*!< interrupt/event pending status from line 4 */
-#define EXTI_PD_PD5                 BIT(5)                   /*!< interrupt/event pending status from line 5 */
-#define EXTI_PD_PD6                 BIT(6)                   /*!< interrupt/event pending status from line 6 */
-#define EXTI_PD_PD7                 BIT(7)                   /*!< interrupt/event pending status from line 7 */
-#define EXTI_PD_PD8                 BIT(8)                   /*!< interrupt/event pending status from line 8 */
-#define EXTI_PD_PD9                 BIT(9)                   /*!< interrupt/event pending status from line 9 */
-#define EXTI_PD_PD10                BIT(10)                  /*!< interrupt/event pending status from line 10 */
-#define EXTI_PD_PD11                BIT(11)                  /*!< interrupt/event pending status from line 11 */
-#define EXTI_PD_PD12                BIT(12)                  /*!< interrupt/event pending status from line 12 */
-#define EXTI_PD_PD13                BIT(13)                  /*!< interrupt/event pending status from line 13 */
-#define EXTI_PD_PD14                BIT(14)                  /*!< interrupt/event pending status from line 14 */
-#define EXTI_PD_PD15                BIT(15)                  /*!< interrupt/event pending status from line 15 */
-#define EXTI_PD_PD16                BIT(16)                  /*!< interrupt/event pending status from line 16 */
-#define EXTI_PD_PD17                BIT(17)                  /*!< interrupt/event pending status from line 17 */
-#define EXTI_PD_PD18                BIT(18)                  /*!< interrupt/event pending status from line 18 */
-#define EXTI_PD_PD19                BIT(19)                  /*!< interrupt/event pending status from line 19 */
-#define EXTI_PD_PD21                BIT(21)                  /*!< interrupt/event pending status from line 21 */
-#define EXTI_PD_PD22                BIT(22)                  /*!< interrupt/event pending status from line 22 */
-
-/* constants definitions */
-/* EXTI line number */
-typedef enum
-{
-    EXTI_0      = BIT(0),                                    /*!< EXTI line 0 */
-    EXTI_1      = BIT(1),                                    /*!< EXTI line 1 */
-    EXTI_2      = BIT(2),                                    /*!< EXTI line 2 */
-    EXTI_3      = BIT(3),                                    /*!< EXTI line 3 */
-    EXTI_4      = BIT(4),                                    /*!< EXTI line 4 */
-    EXTI_5      = BIT(5),                                    /*!< EXTI line 5 */
-    EXTI_6      = BIT(6),                                    /*!< EXTI line 6 */
-    EXTI_7      = BIT(7),                                    /*!< EXTI line 7 */
-    EXTI_8      = BIT(8),                                    /*!< EXTI line 8 */
-    EXTI_9      = BIT(9),                                    /*!< EXTI line 9 */
-    EXTI_10     = BIT(10),                                   /*!< EXTI line 10 */
-    EXTI_11     = BIT(11),                                   /*!< EXTI line 11 */
-    EXTI_12     = BIT(12),                                   /*!< EXTI line 12 */
-    EXTI_13     = BIT(13),                                   /*!< EXTI line 13 */
-    EXTI_14     = BIT(14),                                   /*!< EXTI line 14 */
-    EXTI_15     = BIT(15),                                   /*!< EXTI line 15 */
-    EXTI_16     = BIT(16),                                   /*!< EXTI line 16 */
-    EXTI_17     = BIT(17),                                   /*!< EXTI line 17 */
-#ifdef GD32F130_150
-    EXTI_18     = BIT(18),                                   /*!< EXTI line 18 */
-#endif /* GD32F130_150 */
-    EXTI_19     = BIT(19),                                   /*!< EXTI line 19 */
-    EXTI_21     = BIT(21),                                   /*!< EXTI line 21 */
-    EXTI_22     = BIT(22),                                   /*!< EXTI line 22 */
-    EXTI_25     = BIT(25),                                   /*!< EXTI line 25 */
-    EXTI_27     = BIT(27)                                    /*!< EXTI line 27 */
-}exti_line_enum;
-
-/* external interrupt and event  */
-typedef enum
-{
-    EXTI_INTERRUPT   = 0,                                    /*!< EXTI interrupt mode */
-    EXTI_EVENT                                               /*!< EXTI event mode */
-}exti_mode_enum;
-
-/* interrupt trigger mode */
-typedef enum
-{
-    EXTI_TRIG_RISING = 0,                                    /*!< EXTI rising edge trigger */
-    EXTI_TRIG_FALLING,                                       /*!< EXTI falling edge trigger */
-    EXTI_TRIG_BOTH                                           /*!< EXTI rising and falling edge trigger */
-}exti_trig_type_enum;
-
-/* function declarations */
-/* initialization functions */
-/* deinitialize the EXTI */
-void exti_deinit(void);
-/* initialize the EXTI */
-void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
-
-/* enable functions */
-/* enable the interrupts from EXTI line x */
-void exti_interrupt_enable(exti_line_enum linex);
-/* enable the events from EXTI line x */
-void exti_event_enable(exti_line_enum linex);
-/* disable the interrupts from EXTI line x */
-void exti_interrupt_disable(exti_line_enum linex);
-/* disable the events from EXTI line x */
-void exti_event_disable(exti_line_enum linex);
-
-/* interrupt & flag functions */
-/* get EXTI lines pending flag */
-FlagStatus exti_flag_get(exti_line_enum linex);
-/* clear EXTI lines pending flag */
-void exti_flag_clear(exti_line_enum linex);
-/* get EXTI lines flag when the interrupt flag is set */
-FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
-/* clear EXTI lines pending flag */
-void exti_interrupt_flag_clear(exti_line_enum linex);
-/* enable EXTI software interrupt event */
-void exti_software_interrupt_enable(exti_line_enum linex);
-/* disable EXTI software interrupt event */
-void exti_software_interrupt_disable(exti_line_enum linex);
-
-#endif /* GD32F1X0_EXTI_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_ivref.h

@@ -1,242 +0,0 @@
-/*!
-    \file  gd32f1x0_ivref.h
-    \brief definitions for the IVREF
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifdef GD32F170_190
-
-#ifndef GD32F1X0_IVREF_H
-#define GD32F1X0_IVREF_H
-
-#include "gd32f1x0.h"
-
-/* IVREF definitions */
-#define IVREF                           IVREF_BASE
-
-/* registers definitions */
-#define IVREF_CTL                       REG32(IVREF + 0x00000300U)  /*!< IVREF control register */
-
-/* bits definitions */
-/* IVREF_CTL */
-#define IVREF_CTL_CSDT                  BITS(0,5)              /*!< current step data */
-#define IVREF_CTL_SCMOD                 BIT(7)                 /*!< sink current mode */
-#define IVREF_CTL_CPT                   BITS(8,12)             /*!< current precision trim */
-#define IVREF_CTL_SSEL                  BIT(14)                /*!< step selection */ 
-#define IVREF_CTL_CREN                  BIT(15)                /*!< current reference enable */
-#define IVREF_CTL_VPT                   BITS(24,28)            /*!< voltage precision trim */
-#define IVREF_CTL_DECAP                 BIT(30)                /*!< connect/disconnect external capacitor */
-#define IVREF_CTL_VREN                  BIT(31)                /*!< voltage reference enable */
-
-/* constants definitions */
-/* vref mode selection */
-#define VREF_DISCONNECT_EXTERNAL_CAP    BIT(30)                /*!< VREF disconnect external capacitor */
-#define VREF_CONNECT_EXTERNAL_CAP       ((uint32_t)0x00000000) /*!< VREF connect external capacitor */
-
-/* vref voltage precision trim */
-#define CTL_VPT(regval)                 (BITS(24,28) & ((regval) << 24))
-#define VREF_VOLT_PRECISION_TRIM_0      CTL_VPT(0)             /*!< VREF voltage precision trim 0 */
-#define VREF_VOLT_PRECISION_TRIM_1      CTL_VPT(1)             /*!< VREF voltage precision trim 1 */
-#define VREF_VOLT_PRECISION_TRIM_2      CTL_VPT(2)             /*!< VREF voltage precision trim 2 */
-#define VREF_VOLT_PRECISION_TRIM_3      CTL_VPT(3)             /*!< VREF voltage precision trim 3 */
-#define VREF_VOLT_PRECISION_TRIM_4      CTL_VPT(4)             /*!< VREF voltage precision trim 4 */
-#define VREF_VOLT_PRECISION_TRIM_5      CTL_VPT(5)             /*!< VREF voltage precision trim 5 */
-#define VREF_VOLT_PRECISION_TRIM_6      CTL_VPT(6)             /*!< VREF voltage precision trim 6 */
-#define VREF_VOLT_PRECISION_TRIM_7      CTL_VPT(7)             /*!< VREF voltage precision trim 7 */
-#define VREF_VOLT_PRECISION_TRIM_8      CTL_VPT(8)             /*!< VREF voltage precision trim 8 */
-#define VREF_VOLT_PRECISION_TRIM_9      CTL_VPT(9)             /*!< VREF voltage precision trim 9 */
-#define VREF_VOLT_PRECISION_TRIM_10     CTL_VPT(10)            /*!< VREF voltage precision trim 10 */
-#define VREF_VOLT_PRECISION_TRIM_11     CTL_VPT(11)            /*!< VREF voltage precision trim 11 */
-#define VREF_VOLT_PRECISION_TRIM_12     CTL_VPT(12)            /*!< VREF voltage precision trim 12 */
-#define VREF_VOLT_PRECISION_TRIM_13     CTL_VPT(13)            /*!< VREF voltage precision trim 13 */
-#define VREF_VOLT_PRECISION_TRIM_14     CTL_VPT(14)            /*!< VREF voltage precision trim 14 */
-#define VREF_VOLT_PRECISION_TRIM_15     CTL_VPT(15)            /*!< VREF voltage precision trim 15 */
-#define VREF_VOLT_PRECISION_TRIM_16     CTL_VPT(16)            /*!< VREF voltage precision trim 16 */
-#define VREF_VOLT_PRECISION_TRIM_17     CTL_VPT(17)            /*!< VREF voltage precision trim 17 */
-#define VREF_VOLT_PRECISION_TRIM_18     CTL_VPT(18)            /*!< VREF voltage precision trim 18 */
-#define VREF_VOLT_PRECISION_TRIM_19     CTL_VPT(19)            /*!< VREF voltage precision trim 19 */
-#define VREF_VOLT_PRECISION_TRIM_20     CTL_VPT(20)            /*!< VREF voltage precision trim 20 */
-#define VREF_VOLT_PRECISION_TRIM_21     CTL_VPT(21)            /*!< VREF voltage precision trim 21 */
-#define VREF_VOLT_PRECISION_TRIM_22     CTL_VPT(22)            /*!< VREF voltage precision trim 22 */
-#define VREF_VOLT_PRECISION_TRIM_23     CTL_VPT(23)            /*!< VREF voltage precision trim 23 */
-#define VREF_VOLT_PRECISION_TRIM_24     CTL_VPT(24)            /*!< VREF voltage precision trim 24 */
-#define VREF_VOLT_PRECISION_TRIM_25     CTL_VPT(25)            /*!< VREF voltage precision trim 25 */
-#define VREF_VOLT_PRECISION_TRIM_26     CTL_VPT(26)            /*!< VREF voltage precision trim 26 */
-#define VREF_VOLT_PRECISION_TRIM_27     CTL_VPT(27)            /*!< VREF voltage precision trim 27 */
-#define VREF_VOLT_PRECISION_TRIM_28     CTL_VPT(28)            /*!< VREF voltage precision trim 28 */
-#define VREF_VOLT_PRECISION_TRIM_29     CTL_VPT(29)            /*!< VREF voltage precision trim 29 */
-#define VREF_VOLT_PRECISION_TRIM_30     CTL_VPT(30)            /*!< VREF voltage precision trim 30 */
-#define VREF_VOLT_PRECISION_TRIM_31     CTL_VPT(31)            /*!< VREF voltage precision trim 31 */
-
-/* iref current precision trim */
-#define CTL_CPT(regval)                 (BITS(8,12) & ((regval) << 8))
-#define IREF_CUR_PRECISION_TRIM_0       CTL_CPT(0)             /*!< IREF current precision trim 0 */
-#define IREF_CUR_PRECISION_TRIM_1       CTL_CPT(1)             /*!< IREF current precision trim 1 */
-#define IREF_CUR_PRECISION_TRIM_2       CTL_CPT(2)             /*!< IREF current precision trim 2 */
-#define IREF_CUR_PRECISION_TRIM_3       CTL_CPT(3)             /*!< IREF current precision trim 3 */
-#define IREF_CUR_PRECISION_TRIM_4       CTL_CPT(4)             /*!< IREF current precision trim 4 */
-#define IREF_CUR_PRECISION_TRIM_5       CTL_CPT(5)             /*!< IREF current precision trim 5 */
-#define IREF_CUR_PRECISION_TRIM_6       CTL_CPT(6)             /*!< IREF current precision trim 6 */
-#define IREF_CUR_PRECISION_TRIM_7       CTL_CPT(7)             /*!< IREF current precision trim 7 */
-#define IREF_CUR_PRECISION_TRIM_8       CTL_CPT(8)             /*!< IREF current precision trim 8 */
-#define IREF_CUR_PRECISION_TRIM_9       CTL_CPT(9)             /*!< IREF current precision trim 9 */
-#define IREF_CUR_PRECISION_TRIM_10      CTL_CPT(10)            /*!< IREF current precision trim 10 */
-#define IREF_CUR_PRECISION_TRIM_11      CTL_CPT(11)            /*!< IREF current precision trim 11 */
-#define IREF_CUR_PRECISION_TRIM_12      CTL_CPT(12)            /*!< IREF current precision trim 12 */
-#define IREF_CUR_PRECISION_TRIM_13      CTL_CPT(13)            /*!< IREF current precision trim 13 */
-#define IREF_CUR_PRECISION_TRIM_14      CTL_CPT(14)            /*!< IREF current precision trim 14 */
-#define IREF_CUR_PRECISION_TRIM_15      CTL_CPT(15)            /*!< IREF current precision trim 15 */
-#define IREF_CUR_PRECISION_TRIM_16      CTL_CPT(16)            /*!< IREF current precision trim 16 */
-#define IREF_CUR_PRECISION_TRIM_17      CTL_CPT(17)            /*!< IREF current precision trim 17 */
-#define IREF_CUR_PRECISION_TRIM_18      CTL_CPT(18)            /*!< IREF current precision trim 18 */
-#define IREF_CUR_PRECISION_TRIM_19      CTL_CPT(19)            /*!< IREF current precision trim 19 */
-#define IREF_CUR_PRECISION_TRIM_20      CTL_CPT(20)            /*!< IREF current precision trim 20 */
-#define IREF_CUR_PRECISION_TRIM_21      CTL_CPT(21)            /*!< IREF current precision trim 21 */
-#define IREF_CUR_PRECISION_TRIM_22      CTL_CPT(22)            /*!< IREF current precision trim 22 */
-#define IREF_CUR_PRECISION_TRIM_23      CTL_CPT(23)            /*!< IREF current precision trim 23 */
-#define IREF_CUR_PRECISION_TRIM_24      CTL_CPT(24)            /*!< IREF current precision trim 24 */
-#define IREF_CUR_PRECISION_TRIM_25      CTL_CPT(25)            /*!< IREF current precision trim 25 */
-#define IREF_CUR_PRECISION_TRIM_26      CTL_CPT(26)            /*!< IREF current precision trim 26 */
-#define IREF_CUR_PRECISION_TRIM_27      CTL_CPT(27)            /*!< IREF current precision trim 27 */
-#define IREF_CUR_PRECISION_TRIM_28      CTL_CPT(28)            /*!< IREF current precision trim 28 */
-#define IREF_CUR_PRECISION_TRIM_29      CTL_CPT(29)            /*!< IREF current precision trim 29 */
-#define IREF_CUR_PRECISION_TRIM_30      CTL_CPT(30)            /*!< IREF current precision trim 30 */
-#define IREF_CUR_PRECISION_TRIM_31      CTL_CPT(31)            /*!< IREF current precision trim 31 */
- 
-/* iref mode selection */
-#define IREF_MODE_LOW_POWER             ((uint32_t)0x00000000)
-#define IREF_MODE_HIGH_CURRENT          BIT(14)
- 
-/* iref current step */
-#define CTL_CSDA(regval)                (BITS(0,5) & ((regval) << 0))
-#define IREF_CUR_STEP_DATA_0            CTL_CSDA(0)            /*!< IREF current step data 0 */
-#define IREF_CUR_STEP_DATA_1            CTL_CSDA(1)            /*!< IREF current step data 1 */
-#define IREF_CUR_STEP_DATA_2            CTL_CSDA(2)            /*!< IREF current step data 2 */
-#define IREF_CUR_STEP_DATA_3            CTL_CSDA(3)            /*!< IREF current step data 3 */
-#define IREF_CUR_STEP_DATA_4            CTL_CSDA(4)            /*!< IREF current step data 4 */
-#define IREF_CUR_STEP_DATA_5            CTL_CSDA(5)            /*!< IREF current step data 5 */
-#define IREF_CUR_STEP_DATA_6            CTL_CSDA(6)            /*!< IREF current step data 6 */
-#define IREF_CUR_STEP_DATA_7            CTL_CSDA(7)            /*!< IREF current step data 7 */
-#define IREF_CUR_STEP_DATA_8            CTL_CSDA(8)            /*!< IREF current step data 8 */
-#define IREF_CUR_STEP_DATA_9            CTL_CSDA(9)            /*!< IREF current step data 9 */
-#define IREF_CUR_STEP_DATA_10           CTL_CSDA(10)           /*!< IREF current step data 10 */
-#define IREF_CUR_STEP_DATA_11           CTL_CSDA(11)           /*!< IREF current step data 11 */
-#define IREF_CUR_STEP_DATA_12           CTL_CSDA(12)           /*!< IREF current step data 12 */
-#define IREF_CUR_STEP_DATA_13           CTL_CSDA(13)           /*!< IREF current step data 13 */
-#define IREF_CUR_STEP_DATA_14           CTL_CSDA(14)           /*!< IREF current step data 14 */
-#define IREF_CUR_STEP_DATA_15           CTL_CSDA(15)           /*!< IREF current step data 15 */
-#define IREF_CUR_STEP_DATA_16           CTL_CSDA(16)           /*!< IREF current step data 16 */
-#define IREF_CUR_STEP_DATA_17           CTL_CSDA(17)           /*!< IREF current step data 17 */
-#define IREF_CUR_STEP_DATA_18           CTL_CSDA(18)           /*!< IREF current step data 18 */
-#define IREF_CUR_STEP_DATA_19           CTL_CSDA(19)           /*!< IREF current step data 19 */
-#define IREF_CUR_STEP_DATA_20           CTL_CSDA(20)           /*!< IREF current step data 20 */
-#define IREF_CUR_STEP_DATA_21           CTL_CSDA(21)           /*!< IREF current step data 21 */
-#define IREF_CUR_STEP_DATA_22           CTL_CSDA(22)           /*!< IREF current step data 22 */
-#define IREF_CUR_STEP_DATA_23           CTL_CSDA(23)           /*!< IREF current step data 23 */
-#define IREF_CUR_STEP_DATA_24           CTL_CSDA(24)           /*!< IREF current step data 24 */
-#define IREF_CUR_STEP_DATA_25           CTL_CSDA(25)           /*!< IREF current step data 25 */
-#define IREF_CUR_STEP_DATA_26           CTL_CSDA(26)           /*!< IREF current step data 26 */
-#define IREF_CUR_STEP_DATA_27           CTL_CSDA(27)           /*!< IREF current step data 27 */
-#define IREF_CUR_STEP_DATA_28           CTL_CSDA(28)           /*!< IREF current step data 28 */
-#define IREF_CUR_STEP_DATA_29           CTL_CSDA(29)           /*!< IREF current step data 29 */
-#define IREF_CUR_STEP_DATA_30           CTL_CSDA(30)           /*!< IREF current step data 30 */
-#define IREF_CUR_STEP_DATA_31           CTL_CSDA(31)           /*!< IREF current step data 31 */
-#define IREF_CUR_STEP_DATA_32           CTL_CSDA(32)           /*!< IREF current step data 32 */
-#define IREF_CUR_STEP_DATA_33           CTL_CSDA(33)           /*!< IREF current step data 33 */
-#define IREF_CUR_STEP_DATA_34           CTL_CSDA(34)           /*!< IREF current step data 34 */
-#define IREF_CUR_STEP_DATA_35           CTL_CSDA(35)           /*!< IREF current step data 35 */
-#define IREF_CUR_STEP_DATA_36           CTL_CSDA(36)           /*!< IREF current step data 36 */
-#define IREF_CUR_STEP_DATA_37           CTL_CSDA(37)           /*!< IREF current step data 37 */
-#define IREF_CUR_STEP_DATA_38           CTL_CSDA(38)           /*!< IREF current step data 38 */
-#define IREF_CUR_STEP_DATA_39           CTL_CSDA(39)           /*!< IREF current step data 39 */
-#define IREF_CUR_STEP_DATA_40           CTL_CSDA(40)           /*!< IREF current step data 40 */
-#define IREF_CUR_STEP_DATA_41           CTL_CSDA(41)           /*!< IREF current step data 41 */
-#define IREF_CUR_STEP_DATA_42           CTL_CSDA(42)           /*!< IREF current step data 42 */
-#define IREF_CUR_STEP_DATA_43           CTL_CSDA(43)           /*!< IREF current step data 43 */
-#define IREF_CUR_STEP_DATA_44           CTL_CSDA(44)           /*!< IREF current step data 44 */
-#define IREF_CUR_STEP_DATA_45           CTL_CSDA(45)           /*!< IREF current step data 45 */
-#define IREF_CUR_STEP_DATA_46           CTL_CSDA(46)           /*!< IREF current step data 46 */
-#define IREF_CUR_STEP_DATA_47           CTL_CSDA(47)           /*!< IREF current step data 47 */
-#define IREF_CUR_STEP_DATA_48           CTL_CSDA(48)           /*!< IREF current step data 48 */
-#define IREF_CUR_STEP_DATA_49           CTL_CSDA(49)           /*!< IREF current step data 49 */
-#define IREF_CUR_STEP_DATA_50           CTL_CSDA(50)           /*!< IREF current step data 50 */
-#define IREF_CUR_STEP_DATA_51           CTL_CSDA(51)           /*!< IREF current step data 51 */
-#define IREF_CUR_STEP_DATA_52           CTL_CSDA(52)           /*!< IREF current step data 52 */
-#define IREF_CUR_STEP_DATA_53           CTL_CSDA(53)           /*!< IREF current step data 53 */
-#define IREF_CUR_STEP_DATA_54           CTL_CSDA(54)           /*!< IREF current step data 54 */
-#define IREF_CUR_STEP_DATA_55           CTL_CSDA(55)           /*!< IREF current step data 54 */
-#define IREF_CUR_STEP_DATA_56           CTL_CSDA(56)           /*!< IREF current step data 54 */
-#define IREF_CUR_STEP_DATA_57           CTL_CSDA(57)           /*!< IREF current step data 57 */
-#define IREF_CUR_STEP_DATA_58           CTL_CSDA(58)           /*!< IREF current step data 58 */
-#define IREF_CUR_STEP_DATA_59           CTL_CSDA(59)           /*!< IREF current step data 59 */
-#define IREF_CUR_STEP_DATA_60           CTL_CSDA(60)           /*!< IREF current step data 60 */
-#define IREF_CUR_STEP_DATA_61           CTL_CSDA(61)           /*!< IREF current step data 61 */
-#define IREF_CUR_STEP_DATA_62           CTL_CSDA(62)           /*!< IREF current step data 62 */
-#define IREF_CUR_STEP_DATA_63           CTL_CSDA(63)           /*!< IREF current step data 63 */
-
-/* iref sink current mode*/ 
-#define IREF_SOURCE_CURRENT             ((uint32_t)0x00000000) /*!< IREF source current */
-#define IREF_SINK_CURRENT               BIT(7)                 /*!< IREF sink current */
-
-/* function declarations */
-/* initialization functions */
-/* deinit vref */
-void ivref_deinit(void);
-/* enable vref */
-void vref_enable(void);
-/* disable vref */
-void vref_disable(void);
-/* enable vref */
-void iref_enable(void);
-/* disable iref */
-void iref_disable(void);
-
-/* function configuration */
-/* set verf mode */
-void vref_mode_set(uint32_t vrefmode);
-/* set vrer voltage precision trim value */
-void vref_precision_trim_value_set(uint32_t precisiontrim);
-/* set iref mode*/
-void iref_mode_set(uint32_t irefmode);
-/* set iref sink current mode*/
-void iref_sink_set(uint32_t irefsinkmode);
-/* set iref current precision trim value */
-void iref_precision_trim_value_set(uint32_t precisiontrim);
-/* set iref step data*/
-void iref_step_data_config(uint32_t irefstepdata);
-
-#endif /* GD32F1X0_IVREF_H */
-
-#endif /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_misc.h

@@ -1,71 +0,0 @@
-/*!
-    \file  gd32f1x0_misc.h
-    \brief definitions for the MISC
-*/
-
-/*
-    Copyright (C) 2017 GigaDevice
-
-    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#ifndef GD32F1X0_MISC_H
-#define GD32F1X0_MISC_H
-
-#include "gd32f1x0.h"
-
-/* constants definitions */
-/* set the RAM and FLASH base address */
-#define NVIC_VECTTAB_RAM            ((uint32_t)0x20000000U) /*!< RAM base address */
-#define NVIC_VECTTAB_FLASH          ((uint32_t)0x08000000U) /*!< Flash base address */
-
-/* set the NVIC vector table offset mask */
-#define NVIC_VECTTAB_OFFSET_MASK    ((uint32_t)0x1FFFFF80U)
-
-/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
-#define NVIC_AIRCR_VECTKEY_MASK     ((uint32_t)0x05FA0000U)
-
-/* priority group - define the pre-emption priority and the subpriority */
-#define NVIC_PRIGROUP_PRE0_SUB4     ((uint32_t)0x700U) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
-#define NVIC_PRIGROUP_PRE1_SUB3     ((uint32_t)0x600U) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
-#define NVIC_PRIGROUP_PRE2_SUB2     ((uint32_t)0x500U) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
-#define NVIC_PRIGROUP_PRE3_SUB1     ((uint32_t)0x400U) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
-#define NVIC_PRIGROUP_PRE4_SUB0     ((uint32_t)0x300U) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
-
-/* choose the method to enter or exit the lowpower mode */
-#define SCB_SCR_SLEEPONEXIT         ((uint8_t)0x02U) /*!< choose the the system whether enter low power mode by exiting from ISR */
-#define SCB_SCR_SLEEPDEEP           ((uint8_t)0x04U) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
-#define SCB_SCR_SEVONPEND           ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the lowpower mode */
-
-#define SCB_LPM_SLEEP_EXIT_ISR      SCB_SCR_SLEEPONEXIT
-#define SCB_LPM_DEEPSLEEP           SCB_SCR_SLEEPDEEP
-#define SCB_LPM_WAKE_BY_ALL_INT     SCB_SCR_SEVONPEND
-
-/* choose the systick clock source */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
-#define SYSTICK_CLKSOURCE_HCLK      ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
-
-/* function declarations */
-/* set the priority group */
-void nvic_priority_group_set(uint32_t nvic_prigroup);
-
-/* enable NVIC request */
-void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
-/* disable NVIC request */
-void nvic_irq_disable(uint8_t nvic_irq);
-
-/* set the NVIC vector table base address */
-void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
-
-/* set the state of the low power mode */
-void system_lowpower_set(uint8_t lowpower_mode);
-/* reset the state of the low power mode */
-void system_lowpower_reset(uint8_t lowpower_mode);
-
-/* set the systick clock source */
-void systick_clksource_set(uint32_t systick_clksource);
-
-#endif /* GD32F1X0_MISC_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_opa.h

@@ -1,167 +0,0 @@
-/*!
-    \file  gd32f1x0_opa.h
-    \brief definitions for the OPA
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifdef GD32F170_190
-
-#ifndef GD32F1X0_OPA_H
-#define GD32F1X0_OPA_H
-
-#include "gd32f1x0.h"
-
-/* OPAx(x=0,1,2) definitions */
-#define OPA                     OPA_BASE
-#define OPA0                    ((uint32_t)0)
-#define OPA1                    ((uint32_t)1)
-#define OPA2                    ((uint32_t)2)
-
-/* registers definitions */
-#define OPA_CTL                 REG32(OPA + 0x00000000U)     /*!< OPA control register */
-#define OPA_BT                  REG32(OPA + 0x00000004U)     /*!< OPA bias trimming register for normal mode */
-#define OPA_LPBT                REG32(OPA + 0x00000008U)     /*!< OPA bias trimming register for low power mode */
-
-/* bits definitions */
-/* OPA_CLT */
-#define OPA_CTL_OPA0PD          BIT(0)                 /*!< OPA0 power down */
-#define OPA_CTL_T3OPA0          BIT(1)                 /*!< T3 switch enable for OPA0 */
-#define OPA_CTL_S1OPA0          BIT(2)                 /*!< S1 switch enable for OPA0 */
-#define OPA_CTL_S2OPA0          BIT(3)                 /*!< S2 switch enable for OPA0 */
-#define OPA_CTL_S3OPA0          BIT(4)                 /*!< S3 switch enable for OPA0 */
-#define OPA_CTL_OPA0CAL_L       BIT(5)                 /*!< OPA1 offset calibration for P diff */
-#define OPA_CTL_OPA0CAL_H       BIT(6)                 /*!< OPA1 offset calibration for N diff */
-#define OPA_CTL_OPA0LPM         BIT(7)                 /*!< OPA0 low power mode */
-#define OPA_CTL_OPA1PD          BIT(8)                 /*!< OPA1 power down */
-#define OPA_CTL_T3OPA1          BIT(9)                 /*!< T3 switch enable for OPA1 */
-#define OPA_CTL_S1OPA1          BIT(10)                /*!< S1 switch enable for OPA1 */
-#define OPA_CTL_S2OPA1          BIT(11)                /*!< S2 switch enable for OPA1 */
-#define OPA_CTL_S3OPA1          BIT(12)                /*!< S3 switch enable for OPA1 */
-#define OPA_CTL_OPA1CAL_L       BIT(13)                /*!< OPA1 offset calibration for P diff */
-#define OPA_CTL_OPA1CAL_H       BIT(14)                /*!< OPA1 offset calibration for N diff */
-#define OPA_CTL_OPA1LPM         BIT(15)                /*!< OPA1 low power mode */
-#define OPA_CTL_OPA2PD          BIT(16)                /*!< OPA2 power down */
-#define OPA_CTL_T3OPA2          BIT(17)                /*!< T3 switch enable for OPA2 */
-#define OPA_CTL_S1OPA2          BIT(18)                /*!< S1 switch enable for OPA2 */
-#define OPA_CTL_S2OPA2          BIT(19)                /*!< S2 switch enable for OPA2 */
-#define OPA_CTL_S3OPA2          BIT(20)                /*!< S3 switch enable for OPA2 */
-#define OPA_CTL_OPA2CAL_L       BIT(21)                /*!< OPA2 offset calibration for P diff */
-#define OPA_CTL_OPA2CAL_H       BIT(22)                /*!< OPA2 offset calibration for N diff */
-#define OPA_CTL_OPA2LPM         BIT(23)                /*!< OPA2 low power mode */
-#define OPA_CTL_S4OPA1          BIT(27)                /*!< S4 switch enable for OPA2 */
-#define OPA_CTL_OPA_RANGE       BIT(28)                /*!< Power supply range */
-#define OPA_CTL_OPA0CALOUT      BIT(29)                /*!< OPA0 calibration output */
-#define OPA_CTL_OPA1CALOUT      BIT(30)                /*!< OPA1 calibration output */
-#define OPA_CTL_OPA2CALOUT      BIT(31)                /*!< OPA2 calibration output */
-
-/* OPA_BT */ 
-#define OPA_BT_OA0_TRIM_LOW     BITS(0,4)              /*!< OPA0, normal mode 5-bit bias trim value for PMOS pairs */
-#define OPA_BT_OA0_TRIM_HIGH    BITS(5,9)              /*!< OPA0, normal mode 5-bit bias trim value for NMOS pairs */
-#define OPA_BT_OA1_TRIM_LOW     BITS(10,14)            /*!< OPA1, normal mode 5-bit bias trim value for PMOS pairs */
-#define OPA_BT_OA1_TRIM_HIGH    BITS(15,19)            /*!< OPA1, normal mode 5-bit bias trim value for NMOS pairs */
-#define OPA_BT_OA2_TRIM_LOW     BITS(20,24)            /*!< OPA2, normal mode 5-bit bias trim value for PMOS pairs*/
-#define OPA_BT_OA2_TRIM_HIGH    BITS(25,29)            /*!< OPA2, normal mode 5-bit bias trim value for NMOS pairs */
-#define OPA_BT_OT_USER          BIT(31)                /*!< OPA trimming mode */
-
-/* OPA_LPBT */
-#define OPA_LPBT_OA0_TRIM_LOW   BITS(0,4)              /*!< OPA0, low-power mode 5-bit bias trim value for PMOS pairs */
-#define OPA_LPBT_OA0_TRIM_HIGH  BITS(5,9)              /*!< OPA0, low-power mode 5-bit bias trim value for NMOS pairs */
-#define OPA_LPBT_OA1_TRIM_LOW   BITS(10,14)            /*!< OPA1, low-power mode 5-bit bias trim value for PMOS pairs */
-#define OPA_LPBT_OA1_TRIM_HIGH  BITS(15,19)            /*!< OPA1, low-power mode 5-bit bias trim value for NMOS pairs */
-#define OPA_LPBT_OA2_TRIM_LOW   BITS(20,24)            /*!< OPA2, low-power mode 5-bit bias trim value for PMOS pairs */
-#define OPA_LPBT_OA2_TRIM_HIGH  BITS(25,29)            /*!< OPA2, low-power mode 5-bit bias trim value for NMOS pairs */
-
-/* constants definitions */
-/* opa switch definitions */
-#define OPA_T3OPA0              OPA_CTL_T3OPA0         /*!< T3 switch enable for OPA0 */
-#define OPA_S1OPA0              OPA_CTL_S1OPA0         /*!< S1 switch enable for OPA0 */
-#define OPA_S2OPA0              OPA_CTL_S2OPA0         /*!< S2 switch enable for OPA0 */
-#define OPA_S3OPA0              OPA_CTL_S3OPA0         /*!< S3 switch enable for OPA0 */
-#define OPA_T3OPA1              OPA_CTL_S3OPA1         /*!< T3 switch enable for OPA1 */
-#define OPA_S1OPA1              OPA_CTL_S1OPA1         /*!< S1 switch enable for OPA1 */
-#define OPA_S2OPA1              OPA_CTL_S2OPA1         /*!< S2 switch enable for OPA1 */
-#define OPA_S3OPA1              OPA_CTL_S3OPA1         /*!< S3 switch enable for OPA1 */
-#define OPA_S4OPA1              OPA_CTL_S4OPA1         /*!< S4 switch enable for OPA1 */
-#define OPA_T3OPA2              OPA_CTL_T3OPA2         /*!< T3 switch enable for OPA2 */
-#define OPA_S1OPA2              OPA_CTL_S1OPA2         /*!< S1 switch enable for OPA2 */
-#define OPA_S2OPA2              OPA_CTL_S2OPA2         /*!< S2 switch enable for OPA2 */
-#define OPA_S3OPA2              OPA_CTL_S3OPA2         /*!< S3 switch enable for OPA2 */
-
-/* opa trimming mode */
-#define OPA_BT_TRIM_FACTORY     ((uint32_t)0x00000000) /*!< factory trimming */
-#define OPA_BT_TRIM_USER        OPA_BT_OT_USER         /*!< user trimming */
-
-/* opa input */
-#define OPA_INPUT_N             ((uint32_t)0x00000040) /*!< NMOS input */
-#define OPA_INPUT_P             ((uint32_t)0x00000020) /*!< PMOS input */
-
-/* opa power range */
-#define OPA_POWRANGE_LOW        ((uint32_t)0x00000000) /*!< low power range is selected (VDDA is lower than 3.3V) */
-#define OPA_POWRANGE_HIGH       OPA_CTL_OPA_RANGE      /*!< high power range is selected (VDDA is higher than 3.3V) */
-
-/* function declarations */
-/* initialization functions */
-/* deinit opa */
-void opa_deinit(void);
-/* enable opa */
-void opa_enable(uint32_t opa_periph);
-/* disable opa */
-void opa_disable(uint32_t opa_periph);
-/* enable opa switch */
-void opa_switch_enable(uint32_t opax_swy);
-/* disable opa switch */
-void opa_switch_disable(uint32_t opax_swy);
-
-/* function configuration */
-/* enable opa low_power mode */
-void opa_low_power_enable(uint32_t opa_periph);
-/* dis opa low_power mode */
-void opa_low_power_disable(uint32_t opa_periph);
-/* set opa power range */
-void opa_power_range_config(uint32_t powerrange); 
-/* set opa bias trimming mode */
-void opa_trim_mode_set(uint32_t opa_trimmode);
-/* set opa bias trimming value normal mode */
-void opa_trim_value_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue);
-/* set opa bias trimming value low power mode */
-void opa_trim_value_lp_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue);
-
-/* flag & interrupt functions */
-/* get opa calibration flag */
-FlagStatus opa_cal_out_get(uint32_t opa_periph);
-
-#endif /* GD32F1X0_OPA_H */
-
-#endif /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_pmu.h

@@ -1,133 +0,0 @@
-/*!
-    \file  gd32f1x0_pmu.h
-    \brief definitions for the PMU
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F1X0_PMU_H
-#define GD32F1X0_PMU_H
-
-#include "gd32f1x0.h"
-
-/* PMU definitions */
-#define PMU                           PMU_BASE
-
-/* registers definitions */
-#define PMU_CTL                       REG32(PMU + 0x00000000U) /*!< PMU control register */
-#define PMU_CS                        REG32(PMU + 0x00000004U) /*!< PMU control and status register */
-
-/* bits definitions */
-/* PMU_CTL */
-#define PMU_CTL_LDOLP                 BIT(0)                   /*!< LDO low power mode */
-#define PMU_CTL_STBMOD                BIT(1)                   /*!< standby mode */
-#define PMU_CTL_WURST                 BIT(2)                   /*!< wakeup flag reset */
-#define PMU_CTL_STBRST                BIT(3)                   /*!< standby flag reset */
-#define PMU_CTL_LVDEN                 BIT(4)                   /*!< low voltage detector enable */
-#define PMU_CTL_LVDT                  BITS(5,7)                /*!< low voltage detector threshold */
-#define PMU_CTL_BKPWEN                BIT(8)                   /*!< backup domain write enable */
-
-/* PMU_CS */
-#define PMU_CS_WUF                    BIT(0)                   /*!< wakeup flag */
-#define PMU_CS_STBF                   BIT(1)                   /*!< standby flag */
-#define PMU_CS_LVDF                   BIT(2)                   /*!< low voltage detector status flag */
-#define PMU_CS_WUPEN0                 BIT(8)                   /*!< wakeup pin 0 enable */
-#define PMU_CS_WUPEN1                 BIT(9)                   /*!< wakeup pin 1 enable */
-
-/* constants definitions */
-/* PMU low voltage detector threshold definitions */
-#define CTL_LVDT(regval)              (BITS(5,7)&((uint32_t)(regval) << 5))
-#define PMU_LVDT_0                    CTL_LVDT(0)              /*!< voltage threshold is 2.2V */
-#define PMU_LVDT_1                    CTL_LVDT(1)              /*!< voltage threshold is 2.3V */
-#define PMU_LVDT_2                    CTL_LVDT(2)              /*!< voltage threshold is 2.4V */
-#define PMU_LVDT_3                    CTL_LVDT(3)              /*!< voltage threshold is 2.5V */
-#define PMU_LVDT_4                    CTL_LVDT(4)              /*!< voltage threshold is 2.6V */
-#define PMU_LVDT_5                    CTL_LVDT(5)              /*!< voltage threshold is 2.7V */
-#define PMU_LVDT_6                    CTL_LVDT(6)              /*!< voltage threshold is 2.8V */
-#define PMU_LVDT_7                    CTL_LVDT(7)              /*!< voltage threshold is 2.9V */
-
-/* PMU flag definitions */
-#define PMU_FLAG_WAKEUP               PMU_CS_WUF               /*!< wakeup flag status */
-#define PMU_FLAG_STANDBY              PMU_CS_STBF              /*!< standby flag status */
-#define PMU_FLAG_LVD                  PMU_CS_LVDF              /*!< lvd flag status */
-
-/* PMU ldo definitions */
-#define PMU_LDO_NORMAL                ((uint32_t)0x00000000U)  /*!< LDO normal work when pmu enter deepsleep mode */
-#define PMU_LDO_LOWPOWER              PMU_CTL_LDOLP            /*!< LDO work at low power status when pmu enter deepsleep mode */
-
-/* PMU flag reset definitions */
-#define PMU_FLAG_RESET_WAKEUP         ((uint8_t)0x00)          /*!< wakeup flag reset */
-#define PMU_FLAG_RESET_STANDBY        ((uint8_t)0x01)          /*!< standby flag reset */
-
-/* PMU command constants definitions */
-#define WFI_CMD                       ((uint8_t)0x00)          /*!< use WFI command */
-#define WFE_CMD                       ((uint8_t)0x01)          /*!< use WFE command */
-
-/* PMU wakeup pin definitions */
-#define PMU_WAKEUP_PIN0               PMU_CS_WUPEN0            /*!< wakeup pin 0 */
-#define PMU_WAKEUP_PIN1               PMU_CS_WUPEN1            /*!< wakeup pin 1 */
-
-/* function declarations */
-/* reset PMU registers */
-void pmu_deinit(void);
-/* select low voltage detector threshold */
-void pmu_lvd_select(uint32_t lvdt_n);
-/* disable PMU lvd */
-void pmu_lvd_disable(void);
-
-/* set PMU mode */
-/* PMU work in sleep mode */
-void pmu_to_sleepmode(uint8_t sleepmodecmd);
-/* PMU work in deepsleep mode */
-void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd);
-/* PMU work in standby mode */
-void pmu_to_standbymode(uint8_t standbymodecmd);
-/* enable PMU wakeup pin*/
-void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
-/* disable PMU wakeup pin */
-void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
-
-/* backup related functions */
-/* enable backup domain write */
-void pmu_backup_write_enable(void);
-/* disable backup domain write */
-void pmu_backup_write_disable(void);
-
-/* flag functions */
-/* clear flag bit */
-void pmu_flag_clear(uint32_t flag_clear);
-/* get flag state */
-FlagStatus pmu_flag_get(uint32_t flag);
-
-#endif /* GD32F1X0_PMU_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_rcu.h

@@ -1,1001 +0,0 @@
-/*!
-    \file  gd32f1x0_rcu.h
-    \brief definitions for the RCU
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F1X0_RCU_H
-#define GD32F1X0_RCU_H
-
-#include "gd32f1x0.h"
-
-/* RCU definitions */
-#define RCU                         RCU_BASE
-
-/* registers definitions */
-#define RCU_CTL0                    REG32(RCU + 0x00000000U)        /*!< control register 0 */
-#define RCU_CFG0                    REG32(RCU + 0x00000004U)        /*!< configuration register 0 */
-#define RCU_INT                     REG32(RCU + 0x00000008U)        /*!< interrupt register */
-#define RCU_APB2RST                 REG32(RCU + 0x0000000CU)        /*!< APB2 reset register */
-#define RCU_APB1RST                 REG32(RCU + 0x00000010U)        /*!< APB1 reset register */
-#define RCU_AHBEN                   REG32(RCU + 0x00000014U)        /*!< AHB enable register */
-#define RCU_APB2EN                  REG32(RCU + 0x00000018U)        /*!< APB2 enable register */
-#define RCU_APB1EN                  REG32(RCU + 0x0000001CU)        /*!< APB1 enable register  */
-#define RCU_BDCTL                   REG32(RCU + 0x00000020U)        /*!< backup domain control register */
-#define RCU_RSTSCK                  REG32(RCU + 0x00000024U)        /*!< reset source /clock register */
-#define RCU_AHBRST                  REG32(RCU + 0x00000028U)        /*!< AHB reset register */
-#define RCU_CFG1                    REG32(RCU + 0x0000002CU)        /*!< configuration register 1 */
-#define RCU_CFG2                    REG32(RCU + 0x00000030U)        /*!< configuration register 2 */
-#define RCU_CTL1                    REG32(RCU + 0x00000034U)        /*!< control register 1 */
-#ifdef GD32F170_190
-#define RCU_CFG3                    REG32(RCU + 0x00000080U)        /*!< configuration register 3 */
-#endif /* GD32F170_190 */
-#define RCU_ADDAPB1EN               REG32(RCU + 0x000000F8U)        /*!< APB1 additional enable register */
-#define RCU_ADDAPB1RST              REG32(RCU + 0x000000FCU)        /*!< APB1 additional reset register */
-#define RCU_VKEY                    REG32(RCU + 0x00000100U)        /*!< voltage key register */
-#define RCU_DSV                     REG32(RCU + 0x00000134U)        /*!< deep-sleep mode voltage register */
-#ifdef GD32F130_150
-#define RCU_PDVSEL                  REG32(RCU + 0x00000138U)        /*!< power down voltage select register */
-#endif /* GD32F130_150 */
-
-/* bits definitions */
-/* RCU_CTL0 */
-#define RCU_CTL0_IRC8MEN            BIT(0)                    /*!< internal high speed oscillator enable */
-#define RCU_CTL0_IRC8MSTB           BIT(1)                    /*!< IRC8M high speed internal oscillator stabilization flag */
-#define RCU_CTL0_IRC8MADJ           BITS(3,7)                 /*!< high speed internal oscillator clock trim adjust value */
-#define RCU_CTL0_IRC8MCALIB         BITS(8,15)                /*!< high speed internal oscillator calibration value register */
-#define RCU_CTL0_HXTALEN            BIT(16)                   /*!< external high speed oscillator enable */
-#define RCU_CTL0_HXTALSTB           BIT(17)                   /*!< external crystal oscillator clock stabilization flag */
-#define RCU_CTL0_HXTALBPS           BIT(18)                   /*!< external crystal oscillator clock bypass mode enable */
-#define RCU_CTL0_CKMEN              BIT(19)                   /*!< HXTAL clock monitor enable */
-#define RCU_CTL0_PLLEN              BIT(24)                   /*!< PLL enable */
-#define RCU_CTL0_PLLSTB             BIT(25)                   /*!< PLL clock stabilization flag */
-
-/* RCU_CFG0 */
-#define RCU_CFG0_SCS                BITS(0,1)                 /*!< system clock switch */
-#define RCU_CFG0_SCSS               BITS(2,3)                 /*!< system clock switch status */
-#define RCU_CFG0_AHBPSC             BITS(4,7)                 /*!< AHB prescaler selection */
-#define RCU_CFG0_APB1PSC            BITS(8,10)                /*!< APB1 prescaler selection */
-#define RCU_CFG0_APB2PSC            BITS(11,13)               /*!< APB2 prescaler selection */
-#define RCU_CFG0_ADCPSC             BITS(14,15)               /*!< ADC clock prescaler selection */
-#define RCU_CFG0_PLLSEL             BIT(16)                   /*!< PLL clock source selection */
-#define RCU_CFG0_PLLPREDV           BIT(17)                   /*!< HXTAL divider for PLL source clock selection */
-#define RCU_CFG0_PLLMF              (BIT(27) | BITS(18,21))   /*!< PLL multiply factor */
-#ifdef GD32F130_150
-#define RCU_CFG0_USBDPSC            BITS(22,23)               /*!< USBD clock prescaler selection */
-#define RCU_CFG0_CKOUTSEL           BITS(24,26)               /*!< CK_OUT clock source selection */
-#elif defined (GD32F170_190)
-#define RCU_CFG0_CKOUT0SEL          BITS(24,26)               /*!< CK_OUT0 clock source selection */
-#endif /* GD32F130_150 */
-#define RCU_CFG0_PLLMF4             BIT(27)                   /*!< bit 4 of PLLMF */
-#ifdef GD32F130_150
-#define RCU_CFG0_CKOUTDIV           BITS(28,30)               /*!< CK_OUT divider which the CK_OUT frequency can be reduced */
-#elif defined (GD32F170_190)
-#define RCU_CFG0_CKOUT0DIV          BITS(28,30)               /*!< CK_OUT0 divider which the CK_OUT0 frequency can be reduced */
-#endif /* GD32F130_150 */
-#define RCU_CFG0_PLLDV              BIT(31)                   /*!< CK_PLL divide by 1 or 2 for CK_OUT(GD32F130_150) or CK_OUT0(GD32F170_190) */
-
-/* RCU_INT */
-#define RCU_INT_IRC40KSTBIF         BIT(0)                    /*!< IRC40K stabilization interrupt flag */
-#define RCU_INT_LXTALSTBIF          BIT(1)                    /*!< LXTAL stabilization interrupt flag */
-#define RCU_INT_IRC8MSTBIF          BIT(2)                    /*!< IRC8M stabilization interrupt flag */
-#define RCU_INT_HXTALSTBIF          BIT(3)                    /*!< HXTAL stabilization interrupt flag */
-#define RCU_INT_PLLSTBIF            BIT(4)                    /*!< PLL stabilization interrupt flag */
-#ifdef GD32F130_150
-#define RCU_INT_IRC14MSTBIF         BIT(5)                    /*!< IRC14M stabilization interrupt flag */
-#elif defined (GD32F170_190)
-#define RCU_INT_IRC28MSTBIF         BIT(5)                    /*!< IRC28M stabilization interrupt flag */
-#endif /* GD32F130_150 */
-#define RCU_INT_CKMIF               BIT(7)                    /*!< HXTAL clock stuck interrupt flag */
-#define RCU_INT_IRC40KSTBIE         BIT(8)                    /*!< IRC40K stabilization interrupt enable */
-#define RCU_INT_LXTALSTBIE          BIT(9)                    /*!< LXTAL stabilization interrupt enable */
-#define RCU_INT_IRC8MSTBIE          BIT(10)                   /*!< IRC8M stabilization interrupt enable */
-#define RCU_INT_HXTALSTBIE          BIT(11)                   /*!< HXTAL stabilization interrupt enable */
-#define RCU_INT_PLLSTBIE            BIT(12)                   /*!< PLL stabilization interrupt enable */
-#ifdef GD32F130_150
-#define RCU_INT_IRC14MSTBIE         BIT(13)                   /*!< IRC14M stabilization interrupt enable */
-#elif defined (GD32F170_190)
-#define RCU_INT_IRC28MSTBIE         BIT(13)                   /*!< IRC28M stabilization interrupt enable */
-#endif /* GD32F130_150 */
-#define RCU_INT_IRC40KSTBIC         BIT(16)                   /*!< IRC40K stabilization interrupt clear */
-#define RCU_INT_LXTALSTBIC          BIT(17)                   /*!< LXTAL stabilization interrupt clear */
-#define RCU_INT_IRC8MSTBIC          BIT(18)                   /*!< IRC8M stabilization interrupt clear */
-#define RCU_INT_HXTALSTBIC          BIT(19)                   /*!< HXTAL stabilization interrupt clear */
-#define RCU_INT_PLLSTBIC            BIT(20)                   /*!< PLL stabilization interrupt clear */
-#ifdef GD32F130_150
-#define RCU_INT_IRC14MSTBIC         BIT(21)                   /*!< IRC14M stabilization interrupt clear */
-#elif defined (GD32F170_190)
-#define RCU_INT_IRC28MSTBIC         BIT(21)                   /*!< IRC28M stabilization interrupt clear */
-#endif /* GD32F130_150 */
-#define RCU_INT_CKMIC               BIT(23)                   /*!< HXTAL clock stuck interrupt clear */
-
-/* RCU_APB2RST */
-#define RCU_APB2RST_CFGCMPRST       BIT(0)                    /*!< system configuration and comparator reset */
-#define RCU_APB2RST_ADCRST          BIT(9)                    /*!< ADC reset */
-#define RCU_APB2RST_TIMER0RST       BIT(11)                   /*!< TIMER0 reset */
-#define RCU_APB2RST_SPI0RST         BIT(12)                   /*!< SPI0 reset */
-#define RCU_APB2RST_USART0RST       BIT(14)                   /*!< USART0 reset */
-#define RCU_APB2RST_TIMER14RST      BIT(16)                   /*!< TIMER14 reset */
-#define RCU_APB2RST_TIMER15RST      BIT(17)                   /*!< TIMER15 reset */
-#define RCU_APB2RST_TIMER16RST      BIT(18)                   /*!< TIMER16 reset */
-
-/* RCU_APB1RST */
-#define RCU_APB1RST_TIMER1RST       BIT(0)                    /*!< TIMER1 timer reset */
-#define RCU_APB1RST_TIMER2RST       BIT(1)                    /*!< TIMER2 timer reset */
-#define RCU_APB1RST_TIMER5RST       BIT(4)                    /*!< TIMER5 timer reset */
-#define RCU_APB1RST_TIMER13RST      BIT(8)                    /*!< TIMER13 timer reset */
-#ifdef GD32F170_190
-#define RCU_APB1RST_SLCDRST         BIT(9)                    /*!< SLCD reset */
-#endif /* GD32F170_190 */
-#define RCU_APB1RST_WWDGTRST        BIT(11)                   /*!< window watchdog timer reset */
-#define RCU_APB1RST_SPI1RST         BIT(14)                   /*!< SPI1 reset */
-#define RCU_APB1RST_SPI2RST         BIT(15)                   /*!< SPI2 reset */
-#define RCU_APB1RST_USART1RST       BIT(17)                   /*!< USART1 reset */
-#define RCU_APB1RST_I2C0RST         BIT(21)                   /*!< I2C0 reset */
-#define RCU_APB1RST_I2C1RST         BIT(22)                   /*!< I2C1 reset */
-#ifdef GD32F130_150
-#define RCU_APB1RST_USBDRST         BIT(23)                   /*!< USBD reset */
-#endif /* GD32F130_150 */
-#ifdef GD32F170_190
-#define RCU_APB1RST_CAN0RST         BIT(25)                   /*!< CAN0 reset */
-#define RCU_APB1RST_CAN1RST         BIT(26)                   /*!< CAN1 reset */
-#endif /* GD32F170_190 */
-#define RCU_APB1RST_PMURST          BIT(28)                   /*!< power control reset */
-#define RCU_APB1RST_DACRST          BIT(29)                   /*!< DAC reset */
-#define RCU_APB1RST_CECRST          BIT(30)                   /*!< HDMI CEC reset */
-#ifdef GD32F170_190
-#define RCU_APB1RST_OPAIVREFRST     BIT(31)                   /*!< OPA and IVREF reset */
-#endif /* GD32F170_190 */
-
-/* RCU_AHBEN */
-#define RCU_AHBEN_DMAEN             BIT(0)                    /*!< DMA clock enable */
-#define RCU_AHBEN_SRAMSPEN          BIT(2)                    /*!< SRAM interface clock enable when sleep mode */
-#define RCU_AHBEN_FMCSPEN           BIT(4)                    /*!< FMC clock enable when sleep mode */
-#define RCU_AHBEN_CRCEN             BIT(6)                    /*!< CRC clock enable */
-#define RCU_AHBEN_PAEN              BIT(17)                   /*!< GPIO port A clock enable */
-#define RCU_AHBEN_PBEN              BIT(18)                   /*!< GPIO port B clock enable */
-#define RCU_AHBEN_PCEN              BIT(19)                   /*!< GPIO port C clock enable */
-#define RCU_AHBEN_PDEN              BIT(20)                   /*!< GPIO port D clock enable */
-#define RCU_AHBEN_PFEN              BIT(22)                   /*!< GPIO port F clock enable */
-#define RCU_AHBEN_TSIEN             BIT(24)                   /*!< TSI clock enable */
-
-/* RCU_APB2EN */
-#define RCU_APB2EN_CFGCMPEN         BIT(0)                    /*!< system configuration and comparator clock enable */
-#define RCU_APB2EN_ADCEN            BIT(9)                    /*!< ADC interface clock enable */
-#define RCU_APB2EN_TIMER0EN         BIT(11)                   /*!< TIMER0 timer clock enable */
-#define RCU_APB2EN_SPI0EN           BIT(12)                   /*!< SPI0 clock enable */
-#define RCU_APB2EN_USART0EN         BIT(14)                   /*!< USART0 clock enable */
-#define RCU_APB2EN_TIMER14EN        BIT(16)                   /*!< TIMER14 timer clock enable */
-#define RCU_APB2EN_TIMER15EN        BIT(17)                   /*!< TIMER15 timer clock enable */
-#define RCU_APB2EN_TIMER16EN        BIT(18)                   /*!< TIMER16 timer clock enable */
-
-/* RCU_APB1EN */
-#define RCU_APB1EN_TIMER1EN         BIT(0)                    /*!< TIMER1 timer clock enable */
-#define RCU_APB1EN_TIMER2EN         BIT(1)                    /*!< TIMER2 timer clock enable */
-#define RCU_APB1EN_TIMER5EN         BIT(4)                    /*!< TIMER5 timer clock enable */
-#define RCU_APB1EN_TIMER13EN        BIT(8)                    /*!< TIMER13 timer clock enable */
-#ifdef GD32F170_190
-#define RCU_APB1EN_SLCDEN           BIT(9)                    /*!< SLCD clock enable */
-#endif /* GD32F170_190 */
-#define RCU_APB1EN_WWDGTEN          BIT(11)                   /*!< window watchdog timer clock enable */
-#define RCU_APB1EN_SPI1EN           BIT(14)                   /*!< SPI1 clock enable */
-#define RCU_APB1EN_SPI2EN           BIT(15)                   /*!< SPI2 clock enable */
-#define RCU_APB1EN_USART1EN         BIT(17)                   /*!< USART1 clock enable */
-#define RCU_APB1EN_I2C0EN           BIT(21)                   /*!< I2C0 clock enable */
-#define RCU_APB1EN_I2C1EN           BIT(22)                   /*!< I2C1 clock enable */
-#ifdef GD32F130_150
-#define RCU_APB1EN_USBDEN           BIT(23)                   /*!< USBD clock enable */
-#endif /* GD32F130_150 */
-#ifdef GD32F170_190
-#define RCU_APB1EN_CAN0EN           BIT(25)                   /*!< CAN0 clock enable */
-#define RCU_APB1EN_CAN1EN           BIT(26)                   /*!< CAN1 clock enable */
-#endif /* GD32F170_190 */
-#define RCU_APB1EN_PMUEN            BIT(28)                   /*!< power interface clock enable */
-#define RCU_APB1EN_DACEN            BIT(29)                   /*!< DAC interface clock enable */
-#define RCU_APB1EN_CECEN            BIT(30)                   /*!< HDMI CEC interface clock enable */
-#ifdef GD32F170_190
-#define RCU_APB1EN_OPAIVREFEN       BIT(31)                   /*!< OPA and IVREF clock enable */
-#endif /* GD32F170_190 */
-
-/* RCU_BDCTL */
-#define RCU_BDCTL_LXTALEN           BIT(0)                    /*!< LXTAL enable */
-#define RCU_BDCTL_LXTALSTB          BIT(1)                    /*!< external low-speed oscillator stabilization */
-#define RCU_BDCTL_LXTALBPS          BIT(2)                    /*!< LXTAL bypass mode enable */
-#define RCU_BDCTL_LXTALDRI          BITS(3,4)                 /*!< LXTAL drive capability */
-#define RCU_BDCTL_RTCSRC            BITS(8,9)                 /*!< RTC clock entry selection */
-#define RCU_BDCTL_RTCEN             BIT(15)                   /*!< RTC clock enable */
-#define RCU_BDCTL_BKPRST            BIT(16)                   /*!< Backup domain reset */
-
-/* RCU_RSTSCK */
-#define RCU_RSTSCK_IRC40KEN         BIT(0)                    /*!< IRC40K enable */
-#define RCU_RSTSCK_IRC40KSTB        BIT(1)                    /*!< IRC40K stabilization */
-#define RCU_RSTSCK_V12RSTF          BIT(23)                   /*!< V12 domain Power reset flag */
-#define RCU_RSTSCK_RSTFC            BIT(24)                   /*!< reset flag clear */
-#define RCU_RSTSCK_OBLRSTF          BIT(25)                   /*!< option byte loader reset flag */
-#define RCU_RSTSCK_EPRSTF           BIT(26)                   /*!< external pin reset flag */
-#define RCU_RSTSCK_PORRSTF          BIT(27)                   /*!< power reset flag */
-#define RCU_RSTSCK_SWRSTF           BIT(28)                   /*!< software reset flag */
-#define RCU_RSTSCK_FWDGTRSTF        BIT(29)                   /*!< free watchdog timer reset flag */
-#define RCU_RSTSCK_WWDGTRSTF        BIT(30)                   /*!< window watchdog timer reset flag */
-#define RCU_RSTSCK_LPRSTF           BIT(31)                   /*!< low-power reset flag */
-
-/* RCU_AHBRST */
-#define RCU_AHBRST_PARST            BIT(17)                   /*!< GPIO port A reset */
-#define RCU_AHBRST_PBRST            BIT(18)                   /*!< GPIO port B reset */
-#define RCU_AHBRST_PCRST            BIT(19)                   /*!< GPIO port C reset */
-#define RCU_AHBRST_PDRST            BIT(20)                   /*!< GPIO port D reset */
-#define RCU_AHBRST_PFRST            BIT(22)                   /*!< GPIO port F reset */
-#define RCU_AHBRST_TSIRST           BIT(24)                   /*!< TSI unit reset */
-
-/* RCU_CFG1 */
-#define RCU_CFG1_HXTALPREDV         BITS(0,3)                 /*!< CK_HXTAL divider previous PLL */
-
-/* RCU_CFG2 */
-#define RCU_CFG2_USART0SEL          BITS(0,1)                 /*!< CK_USART0 clock source selection */
-#define RCU_CFG2_CECSEL             BIT(6)                    /*!< CK_CEC clock source selection */
-#define RCU_CFG2_ADCSEL             BIT(8)                    /*!< CK_ADC clock source selection */
-#ifdef GD32F170_190
-#define RCU_CFG2_IRC28MDIV          BIT(16)                   /*!< CK_IRC28M divider 2 or not */
-#endif /* GD32F170_190 */
-
-/* RCU_CTL1 */
-#ifdef GD32F130_150
-#define RCU_CTL1_IRC14MEN           BIT(0)                    /*!< IRC14M internal 14M RC oscillator enable */
-#define RCU_CTL1_IRC14MSTB          BIT(1)                    /*!< IRC14M internal 14M RC oscillator stabilization flag */
-#define RCU_CTL1_IRC14MADJ          BITS(3,7)                 /*!< internal 14M RC oscillator clock trim adjust value */
-#define RCU_CTL1_IRC14MCALIB        BITS(8,15)                /*!< internal 14M RC oscillator calibration value register */
-#elif defined (GD32F170_190)
-#define RCU_CTL1_IRC28MEN           BIT(0)                    /*!< IRC28M internal 28M RC oscillator enable */
-#define RCU_CTL1_IRC28MSTB          BIT(1)                    /*!< IRC28M internal 28M RC oscillator stabilization flag */
-#define RCU_CTL1_IRC28MADJ          BITS(3,7)                 /*!< internal 28M RC oscillator clock trim adjust value */
-#define RCU_CTL1_IRC28MCALIB        BITS(8,15)                /*!< internal 28M RC oscillator calibration value register */
-#endif /* GD32F130_150 */
-
-#ifdef GD32F170_190
-/* RCU_CFG3 */
-#define RCU_CFG3_CKOUT1SEL          BITS(0,2)                 /*!< CKOUT1 clock source selection */
-#define RCU_CFG3_CKOUT1DIV          BITS(8,13)                /*!< CK_OUT1 divider which the CK_OUT1 frequency can be reduced */
-#endif /* GD32F170_190 */
-
-/* RCU_ADDAPB1EN */
-#define RCU_ADDAPB1EN_I2C2EN        BIT(0)                    /*!< I2C2 unit clock enable */
-
-/* RCU_ADDAPB1RST */
-#define RCU_ADDAPB1RST_I2C2RST      BIT(0)                    /*!< I2C2 unit reset */
-
-/* RCU_VKEY */
-#define RCU_VKEY_KEY                BITS(0,31)                /*!< key of RCU_PDVSEL and RCU_DSV register */
-
-/* RCU_DSV */
-#define RCU_DSV_DSLPVS              BITS(0,2)                 /*!< deep-sleep mode voltage select */
-
-#ifdef GD32F130_150
-/* RCU_PDVSEL */
-#define RCU_PDVSEL_PDRVS            BIT(0)                    /*!< power down voltage select */
-#endif /* GD32F130_150 */
-
-/* constants definitions */
-/* define the peripheral clock enable bit position and its register index offset */
-#define RCU_REGIDX_BIT(regidx, bitpos)      (((uint32_t)(regidx) << 6) | (bitpos))
-#define RCU_REG_VAL(periph)                 (REG32(RCU + ((uint32_t)(periph) >> 6)))
-#define RCU_BIT_POS(val)                    ((uint32_t)(val) & 0x1FU)
-/* define the voltage key unlock value */
-#define RCU_VKEY_UNLOCK                 ((uint32_t)0x1A2B3C4DU)
-
-/* register index */
-enum reg_idx
-{
-    /* peripherals enable */
-    IDX_AHBEN   = 0x14U, 
-    IDX_APB2EN  = 0x18U, 
-    IDX_APB1EN  = 0x1CU, 
-    IDX_ADDAPB1EN = 0xF8U,
-    /* peripherals reset */
-    IDX_AHBRST  = 0x28U, 
-    IDX_APB2RST = 0x0CU, 
-    IDX_APB1RST = 0x10U, 
-    IDX_ADDAPB1RST = 0xFCU,
-    /* clock stabilization */
-    IDX_CTL0    = 0x00U,
-    IDX_BDCTL   = 0x20U,
-    IDX_STB     = 0x24U,
-    IDX_CTL1    = 0x34U,
-    /* peripheral reset */
-    IDX_RSTSCK  = 0x24U,
-    /* clock stabilization and stuck interrupt */
-    IDX_INT     = 0x08U,
-    /* configuration register */
-    IDX_CFG0    = 0x04U,
-    IDX_CFG2    = 0x30U
-};
-
-/* peripheral clock enable */
-typedef enum
-{
-    /* AHB peripherals */
-    RCU_DMA     = RCU_REGIDX_BIT(IDX_AHBEN, 0U),              /*!< DMA clock */
-    RCU_CRC     = RCU_REGIDX_BIT(IDX_AHBEN, 6U),              /*!< CRC clock */
-    RCU_GPIOA   = RCU_REGIDX_BIT(IDX_AHBEN, 17U),             /*!< GPIOA clock */
-    RCU_GPIOB   = RCU_REGIDX_BIT(IDX_AHBEN, 18U),             /*!< GPIOB clock */
-    RCU_GPIOC   = RCU_REGIDX_BIT(IDX_AHBEN, 19U),             /*!< GPIOC clock */
-    RCU_GPIOD   = RCU_REGIDX_BIT(IDX_AHBEN, 20U),             /*!< GPIOD clock */
-    RCU_GPIOF   = RCU_REGIDX_BIT(IDX_AHBEN, 22U),             /*!< GPIOF clock */
-    RCU_TSI     = RCU_REGIDX_BIT(IDX_AHBEN, 24U),             /*!< TSI clock */
-    
-    /* APB2 peripherals */
-    RCU_CFGCMP  = RCU_REGIDX_BIT(IDX_APB2EN, 0U),             /*!< CFGCMP clock */
-    RCU_ADC     = RCU_REGIDX_BIT(IDX_APB2EN, 9U),             /*!< ADC clock */
-    RCU_TIMER0  = RCU_REGIDX_BIT(IDX_APB2EN, 11U),            /*!< TIMER0 clock */
-    RCU_SPI0    = RCU_REGIDX_BIT(IDX_APB2EN, 12U),            /*!< SPI0 clock */
-    RCU_USART0  = RCU_REGIDX_BIT(IDX_APB2EN, 14U),            /*!< USART0 clock */
-    RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U),            /*!< TIMER14 clock */
-    RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U),            /*!< TIMER15 clock */
-    RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U),            /*!< TIMER16 clock */
-    
-    /* APB1 peripherals */
-    RCU_TIMER1  = RCU_REGIDX_BIT(IDX_APB1EN, 0U),             /*!< TIMER1 clock */
-    RCU_TIMER2  = RCU_REGIDX_BIT(IDX_APB1EN, 1U),             /*!< TIMER2 clock */
-    RCU_TIMER5  = RCU_REGIDX_BIT(IDX_APB1EN, 4U),             /*!< TIMER5 clock */
-    RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U),             /*!< TIMER13 clock */
-#ifdef GD32F170_190
-    RCU_SLCD    = RCU_REGIDX_BIT(IDX_APB1EN, 9U),             /*!< SLCD clock */
-#endif /* GD32F170_190 */
-    RCU_WWDGT   = RCU_REGIDX_BIT(IDX_APB1EN, 11U),            /*!< WWDGT clock */
-    RCU_SPI1    = RCU_REGIDX_BIT(IDX_APB1EN, 14U),            /*!< SPI1 clock */
-    RCU_SPI2    = RCU_REGIDX_BIT(IDX_APB1EN, 15U),            /*!< SPI2 clock */
-    RCU_USART1  = RCU_REGIDX_BIT(IDX_APB1EN, 17U),            /*!< USART1 clock */
-    RCU_I2C0    = RCU_REGIDX_BIT(IDX_APB1EN, 21U),            /*!< I2C0 clock */
-    RCU_I2C1    = RCU_REGIDX_BIT(IDX_APB1EN, 22U),            /*!< I2C1 clock */
-#ifdef GD32F130_150
-    RCU_USBD    = RCU_REGIDX_BIT(IDX_APB1EN, 23U),            /*!< USBD clock */
-#endif /* GD32F130_150 */
-#ifdef GD32F170_190
-    RCU_CAN0    = RCU_REGIDX_BIT(IDX_APB1EN, 25U),            /*!< CAN0 clock */
-    RCU_CAN1    = RCU_REGIDX_BIT(IDX_APB1EN, 26U),            /*!< CAN1 clock */
-#endif /* GD32F170_190 */
-    RCU_PMU     = RCU_REGIDX_BIT(IDX_APB1EN, 28U),            /*!< PMU clock */
-    RCU_DAC     = RCU_REGIDX_BIT(IDX_APB1EN, 29U),            /*!< DAC clock */
-    RCU_CEC     = RCU_REGIDX_BIT(IDX_APB1EN, 30U),            /*!< CEC clock */
-#ifdef GD32F170_190
-    RCU_OPAIVREF = RCU_REGIDX_BIT(IDX_APB1EN, 31U),           /*!< OPAIVREF clock */
-#endif /* GD32F170_190 */
-    RCU_RTC     = RCU_REGIDX_BIT(IDX_BDCTL, 15U),             /*!< RTC clock */
-    
-    /* RCU_ADDAPB1EN */
-    RCU_I2C2    = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 0U)           /*!< I2C2 clock */
-}rcu_periph_enum;
-
-/* peripheral clock enable when sleep mode*/
-typedef enum
-{
-    /* AHB peripherals */
-    RCU_SRAM_SLP   = RCU_REGIDX_BIT(IDX_AHBEN, 2U),           /*!< SRAM clock when sleep mode */
-    RCU_FMC_SLP    = RCU_REGIDX_BIT(IDX_AHBEN, 4U)            /*!< FMC clock when sleep mode */
-}rcu_periph_sleep_enum;
-
-/* peripherals reset */
-typedef enum
-{
-    /* AHB peripherals reset */
-    RCU_GPIOARST   = RCU_REGIDX_BIT(IDX_AHBRST, 17U),         /*!< GPIOA reset */
-    RCU_GPIOBRST   = RCU_REGIDX_BIT(IDX_AHBRST, 18U),         /*!< GPIOB reset */
-    RCU_GPIOCRST   = RCU_REGIDX_BIT(IDX_AHBRST, 19U),         /*!< GPIOC reset */
-    RCU_GPIODRST   = RCU_REGIDX_BIT(IDX_AHBRST, 20U),         /*!< GPIOD reset */
-    RCU_GPIOFRST   = RCU_REGIDX_BIT(IDX_AHBRST, 22U),         /*!< GPIOF reset */
-    RCU_TSIRST     = RCU_REGIDX_BIT(IDX_AHBRST, 24U),         /*!< TSI reset */
-    
-    /* APB2 peripherals reset */
-    RCU_CFGCMPRST  = RCU_REGIDX_BIT(IDX_APB2RST, 0U),         /*!< CFGCMP reset */
-    RCU_ADCRST     = RCU_REGIDX_BIT(IDX_APB2RST, 9U),         /*!< ADC reset */
-    RCU_TIMER0RST  = RCU_REGIDX_BIT(IDX_APB2RST, 11U),        /*!< TIMER0 reset */
-    RCU_SPI0RST    = RCU_REGIDX_BIT(IDX_APB2RST, 12U),        /*!< SPI0 reset */
-    RCU_USART0RST  = RCU_REGIDX_BIT(IDX_APB2RST, 14U),        /*!< USART0 reset */
-    RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U),        /*!< TIMER14 reset */
-    RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U),        /*!< TIMER15 reset */
-    RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U),        /*!< TIMER16 reset */
-    
-    /* APB1 peripherals reset */
-    RCU_TIMER1RST  = RCU_REGIDX_BIT(IDX_APB1RST, 0U),         /*!< TIMER1 reset */
-    RCU_TIMER2RST  = RCU_REGIDX_BIT(IDX_APB1RST, 1U),         /*!< TIMER2 reset */
-    RCU_TIMER5RST  = RCU_REGIDX_BIT(IDX_APB1RST, 4U),         /*!< TIMER5 reset */
-    RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U),         /*!< TIMER13 reset */
-#ifdef GD32F170_190
-    RCU_SLCDRST    = RCU_REGIDX_BIT(IDX_APB1RST, 9U),         /*!< SLCD reset */
-#endif /* GD32F170_190 */
-    RCU_WWDGTRST   = RCU_REGIDX_BIT(IDX_APB1RST, 11U),        /*!< WWDGT reset */
-    RCU_SPI1RST    = RCU_REGIDX_BIT(IDX_APB1RST, 14U),        /*!< SPI1 reset */
-    RCU_SPI2RST    = RCU_REGIDX_BIT(IDX_APB1RST, 15U),        /*!< SPI2 reset */
-    RCU_USART1RST  = RCU_REGIDX_BIT(IDX_APB1RST, 17U),        /*!< USART1 reset */
-    RCU_I2C0RST    = RCU_REGIDX_BIT(IDX_APB1RST, 21U),        /*!< I2C0 reset */
-    RCU_I2C1RST    = RCU_REGIDX_BIT(IDX_APB1RST, 22U),        /*!< I2C1 reset */
-#ifdef GD32F130_150
-    RCU_USBDRST    = RCU_REGIDX_BIT(IDX_APB1RST, 23U),        /*!< USBD reset */
-#endif /* GD32F130_150 */
-#ifdef GD32F170_190
-    RCU_CAN0RST    = RCU_REGIDX_BIT(IDX_APB1RST, 25U),        /*!< CAN0 reset */
-    RCU_CAN1RST    = RCU_REGIDX_BIT(IDX_APB1RST, 26U),        /*!< CAN1 reset */
-#endif /* GD32F170_190 */
-    RCU_PMURST     = RCU_REGIDX_BIT(IDX_APB1RST, 28U),        /*!< PMU reset */
-    RCU_DACRST     = RCU_REGIDX_BIT(IDX_APB1RST, 29U),        /*!< DAC reset */
-    RCU_CECRST     = RCU_REGIDX_BIT(IDX_APB1RST, 30U),        /*!< CEC reset */
-#ifdef GD32F170_190
-    RCU_OPAIVREFRST = RCU_REGIDX_BIT(IDX_APB1RST, 31U),       /*!< OPAIVREF reset */
-#endif /* GD32F170_190 */
-
-    /* RCU_ADDAPB1RST */
-    RCU_I2C2RST    = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 0U),      /*!< I2C2 reset */
-}rcu_periph_reset_enum;
-
-/* clock stabilization and peripheral reset flags */
-typedef enum
-{
-    RCU_FLAG_IRC40KSTB    = RCU_REGIDX_BIT(IDX_STB, 1U),      /*!< IRC40K stabilization flag */
-    RCU_FLAG_LXTALSTB     = RCU_REGIDX_BIT(IDX_BDCTL, 1U),    /*!< LXTAL stabilization flag */
-    RCU_FLAG_IRC8MSTB     = RCU_REGIDX_BIT(IDX_CTL0, 1U),     /*!< IRC8M stabilization flag */
-    RCU_FLAG_HXTALSTB     = RCU_REGIDX_BIT(IDX_CTL0, 17U),    /*!< HXTAL stabilization flag */
-    RCU_FLAG_PLLSTB       = RCU_REGIDX_BIT(IDX_CTL0, 25U),    /*!< PLL stabilization flag */
-#ifdef GD32F130_150
-    RCU_FLAG_IRC14MSTB    = RCU_REGIDX_BIT(IDX_CTL1, 1U),     /*!< IRC14M stabilization flag */
-#elif defined (GD32F170_190)
-    RCU_FLAG_IRC28MSTB    = RCU_REGIDX_BIT(IDX_CTL1, 1U),     /*!< IRC28M stabilization flag */
-#endif /* GD32F130_150 */
-    RCU_FLAG_V12RST       = RCU_REGIDX_BIT(IDX_RSTSCK, 23U),  /*!< 1.2V reset flags */
-    RCU_FLAG_OBLRST       = RCU_REGIDX_BIT(IDX_RSTSCK, 25U),  /*!< option byte loader reset flag */
-    RCU_FLAG_EPRST        = RCU_REGIDX_BIT(IDX_RSTSCK, 26U),  /*!< external pin reset reset flag */
-    RCU_FLAG_PORRST       = RCU_REGIDX_BIT(IDX_RSTSCK, 27U),  /*!< power reset flag */
-    RCU_FLAG_SWRST        = RCU_REGIDX_BIT(IDX_RSTSCK, 28U),  /*!< software reset reset flag */
-    RCU_FLAG_FWDGTRST     = RCU_REGIDX_BIT(IDX_RSTSCK, 29U),  /*!< free watchdog timer reset flag */
-    RCU_FLAG_WWDGTRST     = RCU_REGIDX_BIT(IDX_RSTSCK, 30U),  /*!< window watchdog timer reset flag */
-    RCU_FLAG_LPRST        = RCU_REGIDX_BIT(IDX_RSTSCK, 31U)   /*!< low-power reset flag */
-}rcu_flag_enum;
-
-/* clock stabilization and ckm interrupt flags */
-typedef enum
-{
-    RCU_INT_FLAG_IRC40KSTB = RCU_INT_IRC40KSTBIF,             /*!< IRC40K stabilization interrupt flag */
-    RCU_INT_FLAG_LXTALSTB  = RCU_INT_LXTALSTBIF,              /*!< LXTAL stabilization interrupt flag */
-    RCU_INT_FLAG_IRC8MSTB  = RCU_INT_IRC8MSTBIF,              /*!< IRC8M stabilization interrupt flag */
-    RCU_INT_FLAG_HXTALSTB  = RCU_INT_HXTALSTBIF,              /*!< HXTAL stabilization interrupt flag */
-    RCU_INT_FLAG_PLLSTB    = RCU_INT_PLLSTBIF,                /*!< PLL stabilization interrupt flag */
-#ifdef GD32F130_150
-    RCU_INT_FLAG_IRC14MSTB = RCU_INT_IRC14MSTBIF,             /*!< IRC14M stabilization interrupt flag */
-#elif defined (GD32F170_190)
-    RCU_INT_FLAG_IRC28MSTB = RCU_INT_IRC28MSTBIF,             /*!< IRC28M stabilization interrupt flag */
-#endif /* GD32F130_150 */
-    RCU_INT_FLAG_CKM       = RCU_INT_CKMIF                    /*!< HXTAL clock stuck interrupt flag */
-}rcu_int_flag_enum;
-
-/* clock stabilization and stuck interrupt flags clear */
-typedef enum
-{
-    RCU_INT_FLAG_IRC40KSTB_CLR = RCU_INT_IRC40KSTBIC,        /*!< IRC40K stabilization interrupt flags clear */
-    RCU_INT_FLAG_LXTALSTB_CLR  = RCU_INT_LXTALSTBIC,         /*!< LXTAL stabilization interrupt flags clear */
-    RCU_INT_FLAG_IRC8MSTB_CLR  = RCU_INT_IRC8MSTBIC,         /*!< IRC8M stabilization interrupt flags clear */
-    RCU_INT_FLAG_HXTALSTB_CLR  = RCU_INT_HXTALSTBIC,         /*!< HXTAL stabilization interrupt flags clear */
-    RCU_INT_FLAG_PLLSTB_CLR    = RCU_INT_PLLSTBIC,           /*!< PLL stabilization interrupt flags clear */
-#ifdef GD32F130_150
-    RCU_INT_FLAG_IRC14MSTB_CLR = RCU_INT_IRC14MSTBIC,        /*!< IRC14M stabilization interrupt flags clear */
-#elif defined (GD32F170_190)
-    RCU_INT_FLAG_IRC28MSTB_CLR = RCU_INT_IRC28MSTBIC,        /*!< IRC28M stabilization interrupt flags clear */
-#endif /* GD32F130_150 */
-    RCU_INT_FLAG_CKM_CLR       = RCU_INT_CKMIC               /*!< HXTAL clock stuck interrupt flags clear */
-}rcu_int_flag_clear_enum;
-
-/* clock stabilization interrupt enable or disable */
-typedef enum
-{
-    RCU_INT_IRC40KSTB       = RCU_INT_IRC40KSTBIE,           /*!< IRC40K stabilization interrupt */
-    RCU_INT_LXTALSTB        = RCU_INT_LXTALSTBIE,            /*!< LXTAL stabilization interrupt */
-    RCU_INT_IRC8MSTB        = RCU_INT_IRC8MSTBIE,            /*!< IRC8M stabilization interrupt */
-    RCU_INT_HXTALSTB        = RCU_INT_HXTALSTBIE,            /*!< HXTAL stabilization interrupt */
-    RCU_INT_PLLSTB          = RCU_INT_PLLSTBIE,              /*!< PLL stabilization interrupt */
-#ifdef GD32F130_150
-    RCU_INT_IRC14MSTB       = RCU_INT_IRC14MSTBIE            /*!< IRC14M stabilization interrupt */
-#elif defined (GD32F170_190)
-    RCU_INT_IRC28MSTB       = RCU_INT_IRC28MSTBIE            /*!< IRC28M stabilization interrupt */
-#endif /* GD32F130_150 */
-}rcu_int_enum;
-
-/* ADC clock source */
-typedef enum
-{
-#ifdef GD32F130_150
-    RCU_ADCCK_IRC14M        = 0,                             /*!< ADC clock source select IRC14M */
-#elif defined (GD32F170_190)
-    RCU_ADCCK_IRC28M_DIV2   = 0,                             /*!< ADC clock source select IRC28M/2 */
-    RCU_ADCCK_IRC28M,                                        /*!< ADC clock source select IRC28M */
-#endif /* GD32F130_150 */
-    RCU_ADCCK_APB2_DIV2,                                     /*!< ADC clock source select APB2/2 */
-    RCU_ADCCK_APB2_DIV4,                                     /*!< ADC clock source select APB2/4 */
-    RCU_ADCCK_APB2_DIV6,                                     /*!< ADC clock source select APB2/6 */
-    RCU_ADCCK_APB2_DIV8                                      /*!< ADC clock source select APB2/8 */
-}rcu_adc_clock_enum;
-
-/* oscillator types */
-typedef enum
-{
-    RCU_HXTAL   = RCU_REGIDX_BIT(IDX_CTL0, 16U),             /*!< HXTAL */
-    RCU_LXTAL   = RCU_REGIDX_BIT(IDX_BDCTL, 0U),             /*!< LXTAL */
-    RCU_IRC8M   = RCU_REGIDX_BIT(IDX_CTL0, 0U),              /*!< IRC8M */
-#ifdef GD32F130_150
-    RCU_IRC14M  = RCU_REGIDX_BIT(IDX_CTL1, 0U),              /*!< IRC14M */
-#elif defined (GD32F170_190)
-    RCU_IRC28M  = RCU_REGIDX_BIT(IDX_CTL1, 0U),              /*!< IRC28M */
-#endif /* GD32F130_150 */
-    RCU_IRC40K  = RCU_REGIDX_BIT(IDX_RSTSCK, 0U),            /*!< IRC40K */
-    RCU_PLL_CK  = RCU_REGIDX_BIT(IDX_CTL0, 24U)              /*!< PLL */
-}rcu_osci_type_enum;
-
-/* rcu clock frequency */
-typedef enum
-{
-    CK_SYS      = 0,                                         /*!< system clock */
-    CK_AHB,                                                  /*!< AHB clock */
-    CK_APB1,                                                 /*!< APB1 clock */
-    CK_APB2,                                                 /*!< APB2 clock */
-    CK_ADC,                                                  /*!< ADC clock */
-    CK_CEC,                                                  /*!< CEC clock */
-    CK_USART                                                 /*!< USART clock */
-}rcu_clock_freq_enum;
-
-/* system clock source select */
-#define CFG0_SCS(regval)            (BITS(0,1) & ((uint32_t)(regval) << 0))
-#define RCU_CKSYSSRC_IRC8M          CFG0_SCS(0)              /*!< system clock source select IRC8M */
-#define RCU_CKSYSSRC_HXTAL          CFG0_SCS(1)              /*!< system clock source select HXTAL */
-#define RCU_CKSYSSRC_PLL            CFG0_SCS(2)              /*!< system clock source select PLL */
-
-/* system clock source select status */
-#define CFG0_SCSS(regval)           (BITS(2,3) & ((uint32_t)(regval) << 2))
-#define RCU_SCSS_IRC8M              CFG0_SCSS(0)             /*!< system clock source select IRC8M */
-#define RCU_SCSS_HXTAL              CFG0_SCSS(1)             /*!< system clock source select HXTAL */
-#define RCU_SCSS_PLL                CFG0_SCSS(2)             /*!< system clock source select PLL */
-
-/* AHB prescaler selection */
-#define CFG0_AHBPSC(regval)         (BITS(4,7) & ((uint32_t)(regval) << 4))
-#define RCU_AHB_CKSYS_DIV1          CFG0_AHBPSC(0)           /*!< AHB prescaler select CK_SYS */
-#define RCU_AHB_CKSYS_DIV2          CFG0_AHBPSC(8)           /*!< AHB prescaler select CK_SYS/2 */
-#define RCU_AHB_CKSYS_DIV4          CFG0_AHBPSC(9)           /*!< AHB prescaler select CK_SYS/4 */
-#define RCU_AHB_CKSYS_DIV8          CFG0_AHBPSC(10)          /*!< AHB prescaler select CK_SYS/8 */
-#define RCU_AHB_CKSYS_DIV16         CFG0_AHBPSC(11)          /*!< AHB prescaler select CK_SYS/16 */
-#define RCU_AHB_CKSYS_DIV64         CFG0_AHBPSC(12)          /*!< AHB prescaler select CK_SYS/64 */
-#define RCU_AHB_CKSYS_DIV128        CFG0_AHBPSC(13)          /*!< AHB prescaler select CK_SYS/128 */
-#define RCU_AHB_CKSYS_DIV256        CFG0_AHBPSC(14)          /*!< AHB prescaler select CK_SYS/256 */
-#define RCU_AHB_CKSYS_DIV512        CFG0_AHBPSC(15)          /*!< AHB prescaler select CK_SYS/512 */
-
-/* APB1 prescaler selection */
-#define CFG0_APB1PSC(regval)        (BITS(8,10) & ((uint32_t)(regval) << 8))
-#define RCU_APB1_CKAHB_DIV1         CFG0_APB1PSC(0)          /*!< APB1 prescaler select CK_AHB */
-#define RCU_APB1_CKAHB_DIV2         CFG0_APB1PSC(4)          /*!< APB1 prescaler select CK_AHB/2 */
-#define RCU_APB1_CKAHB_DIV4         CFG0_APB1PSC(5)          /*!< APB1 prescaler select CK_AHB/4 */
-#define RCU_APB1_CKAHB_DIV8         CFG0_APB1PSC(6)          /*!< APB1 prescaler select CK_AHB/8 */
-#define RCU_APB1_CKAHB_DIV16        CFG0_APB1PSC(7)          /*!< APB1 prescaler select CK_AHB/16 */
-
-/* APB2 prescaler selection */
-#define CFG0_APB2PSC(regval)        (BITS(11,13) & ((uint32_t)(regval) << 11))
-#define RCU_APB2_CKAHB_DIV1         CFG0_APB2PSC(0)          /*!< APB2 prescaler select CK_AHB */
-#define RCU_APB2_CKAHB_DIV2         CFG0_APB2PSC(4)          /*!< APB2 prescaler select CK_AHB/2 */
-#define RCU_APB2_CKAHB_DIV4         CFG0_APB2PSC(5)          /*!< APB2 prescaler select CK_AHB/4 */
-#define RCU_APB2_CKAHB_DIV8         CFG0_APB2PSC(6)          /*!< APB2 prescaler select CK_AHB/8 */
-#define RCU_APB2_CKAHB_DIV16        CFG0_APB2PSC(7)          /*!< APB2 prescaler select CK_AHB/16 */
-
-/* ADC clock prescaler selection */
-#define CFG0_ADCPSC(regval)         (BITS(14,15) & ((uint32_t)(regval) << 14))
-#define RCU_ADC_CKAPB2_DIV2         CFG0_ADCPSC(0)           /*!< ADC clock prescaler select CK_APB2/2 */
-#define RCU_ADC_CKAPB2_DIV4         CFG0_ADCPSC(1)           /*!< ADC clock prescaler select CK_APB2/4 */
-#define RCU_ADC_CKAPB2_DIV6         CFG0_ADCPSC(2)           /*!< ADC clock prescaler select CK_APB2/6 */
-#define RCU_ADC_CKAPB2_DIV8         CFG0_ADCPSC(3)           /*!< ADC clock prescaler select CK_APB2/8 */
-
-/* PLL clock source selection */
-#define RCU_PLLSRC_IRC8M_DIV2       (uint32_t)0x00000000     /*!< PLL clock source select IRC8M/2 */
-#define RCU_PLLSRC_HXTAL            RCU_CFG0_PLLSEL          /*!< PLL clock source select HXTAL */
-
-/* HXTAL divider for PLL source clock selection */
-#define RCU_PLLPREDV_HXTAL          (uint32_t)0x00000000     /*!< HXTAL clock selected */
-#define RCU_PLLPREDV_HXTAL_DIV2     RCU_CFG0_PLLPREDV        /*!< HXTAL/2 clock selected */
-
-/* PLL multiply factor */
-#define CFG0_PLLMF(regval)          (BITS(18,21) & ((uint32_t)(regval) << 18))
-#define RCU_PLL_MUL2                CFG0_PLLMF(0)                       /*!< PLL source clock multiply by 2 */
-#define RCU_PLL_MUL3                CFG0_PLLMF(1)                       /*!< PLL source clock multiply by 3 */
-#define RCU_PLL_MUL4                CFG0_PLLMF(2)                       /*!< PLL source clock multiply by 4 */
-#define RCU_PLL_MUL5                CFG0_PLLMF(3)                       /*!< PLL source clock multiply by 5 */
-#define RCU_PLL_MUL6                CFG0_PLLMF(4)                       /*!< PLL source clock multiply by 6 */
-#define RCU_PLL_MUL7                CFG0_PLLMF(5)                       /*!< PLL source clock multiply by 7 */
-#define RCU_PLL_MUL8                CFG0_PLLMF(6)                       /*!< PLL source clock multiply by 8 */
-#define RCU_PLL_MUL9                CFG0_PLLMF(7)                       /*!< PLL source clock multiply by 9 */
-#define RCU_PLL_MUL10               CFG0_PLLMF(8)                       /*!< PLL source clock multiply by 10 */
-#define RCU_PLL_MUL11               CFG0_PLLMF(9)                       /*!< PLL source clock multiply by 11 */
-#define RCU_PLL_MUL12               CFG0_PLLMF(10)                      /*!< PLL source clock multiply by 12 */
-#define RCU_PLL_MUL13               CFG0_PLLMF(11)                      /*!< PLL source clock multiply by 13 */
-#define RCU_PLL_MUL14               CFG0_PLLMF(12)                      /*!< PLL source clock multiply by 14 */
-#define RCU_PLL_MUL15               CFG0_PLLMF(13)                      /*!< PLL source clock multiply by 15 */
-#define RCU_PLL_MUL16               CFG0_PLLMF(14)                      /*!< PLL source clock multiply by 16 */
-#define RCU_PLL_MUL17               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0))   /*!< PLL source clock multiply by 17 */
-#define RCU_PLL_MUL18               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1))   /*!< PLL source clock multiply by 18 */
-#define RCU_PLL_MUL19               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2))   /*!< PLL source clock multiply by 19 */
-#define RCU_PLL_MUL20               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3))   /*!< PLL source clock multiply by 20 */
-#define RCU_PLL_MUL21               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4))   /*!< PLL source clock multiply by 21 */
-#define RCU_PLL_MUL22               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5))   /*!< PLL source clock multiply by 22 */
-#define RCU_PLL_MUL23               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6))   /*!< PLL source clock multiply by 23 */
-#define RCU_PLL_MUL24               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7))   /*!< PLL source clock multiply by 24 */
-#define RCU_PLL_MUL25               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8))   /*!< PLL source clock multiply by 25 */
-#define RCU_PLL_MUL26               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9))   /*!< PLL source clock multiply by 26 */
-#define RCU_PLL_MUL27               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10))  /*!< PLL source clock multiply by 27 */
-#define RCU_PLL_MUL28               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11))  /*!< PLL source clock multiply by 28 */
-#define RCU_PLL_MUL29               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12))  /*!< PLL source clock multiply by 29 */
-#define RCU_PLL_MUL30               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13))  /*!< PLL source clock multiply by 30 */
-#define RCU_PLL_MUL31               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14))  /*!< PLL source clock multiply by 31 */
-#define RCU_PLL_MUL32               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15))  /*!< PLL source clock multiply by 32 */
-
-#ifdef GD32F130_150
-/* USBD clock prescaler selection */
-#define CFG0_USBDPSC(regval)        (BITS(22,23) & ((uint32_t)(regval) << 22))
-#define RCU_USBD_CKPLL_DIV1_5       CFG0_USBDPSC(0)                     /*!< USBD clock prescaler select CK_PLL/1.5 */
-#define RCU_USBD_CKPLL_DIV1         CFG0_USBDPSC(1)                     /*!< USBD clock prescaler select CK_PLL */
-#define RCU_USBD_CKPLL_DIV2_5       CFG0_USBDPSC(2)                     /*!< USBD clock prescaler select CK_PLL/2.5 */
-#define RCU_USBD_CKPLL_DIV2         CFG0_USBDPSC(3)                     /*!< USBD clock prescaler select CK_PLL/2 */
-
-/* CK_OUT clock source selection */
-#define CFG0_CKOUTSEL(regval)       (BITS(24,26) & ((uint32_t)(regval) << 24))
-#define RCU_CKOUTSRC_NONE           CFG0_CKOUTSEL(0)                    /*!< no clock selected */
-#define RCU_CKOUTSRC_IRC14M         CFG0_CKOUTSEL(1)                    /*!< CK_OUT clock source select IRC14M */
-#define RCU_CKOUTSRC_IRC40K         CFG0_CKOUTSEL(2)                    /*!< CK_OUT clock source select IRC40K */
-#define RCU_CKOUTSRC_LXTAL          CFG0_CKOUTSEL(3)                    /*!< CK_OUT clock source select LXTAL */
-#define RCU_CKOUTSRC_CKSYS          CFG0_CKOUTSEL(4)                    /*!< CK_OUT clock source select CKSYS */
-#define RCU_CKOUTSRC_IRC8M          CFG0_CKOUTSEL(5)                    /*!< CK_OUT clock source select IRC8M */
-#define RCU_CKOUTSRC_HXTAL          CFG0_CKOUTSEL(6)                    /*!< CK_OUT clock source select HXTAL */
-#define RCU_CKOUTSRC_CKPLL_DIV1     (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */
-#define RCU_CKOUTSRC_CKPLL_DIV2     CFG0_CKOUTSEL(7)                    /*!< CK_OUT clock source select CK_PLL/2 */
-
-/* CK_OUT divider */
-#define CFG0_CKOUTDIV(regval)       (BITS(28,30) & ((uint32_t)(regval) << 28))
-#define RCU_CKOUT_DIV1              CFG0_CKOUTDIV(0)                    /*!< CK_OUT is divided by 1 */
-#define RCU_CKOUT_DIV2              CFG0_CKOUTDIV(1)                    /*!< CK_OUT is divided by 2 */
-#define RCU_CKOUT_DIV4              CFG0_CKOUTDIV(2)                    /*!< CK_OUT is divided by 4 */
-#define RCU_CKOUT_DIV8              CFG0_CKOUTDIV(3)                    /*!< CK_OUT is divided by 8 */
-#define RCU_CKOUT_DIV16             CFG0_CKOUTDIV(4)                    /*!< CK_OUT is divided by 16 */
-#define RCU_CKOUT_DIV32             CFG0_CKOUTDIV(5)                    /*!< CK_OUT is divided by 32 */
-#define RCU_CKOUT_DIV64             CFG0_CKOUTDIV(6)                    /*!< CK_OUT is divided by 64 */
-#define RCU_CKOUT_DIV128            CFG0_CKOUTDIV(7)                    /*!< CK_OUT is divided by 128 */
-
-#elif defined (GD32F170_190)
-/* CK_OUT0 clock source selection */
-#define CFG0_CKOUT0SEL(regval)      (BITS(24,26) & ((uint32_t)(regval) << 24))
-#define RCU_CKOUT0SRC_NONE          CFG0_CKOUT0SEL(0)                    /*!< no clock selected */
-#define RCU_CKOUT0SRC_IRC28M        CFG0_CKOUT0SEL(1)                    /*!< CK_OUT0 clock source select IRC28M */
-#define RCU_CKOUT0SRC_IRC40K        CFG0_CKOUT0SEL(2)                    /*!< CK_OUT0 clock source select IRC40K */
-#define RCU_CKOUT0SRC_LXTAL         CFG0_CKOUT0SEL(3)                    /*!< CK_OUT0 clock source select LXTAL */
-#define RCU_CKOUT0SRC_CKSYS         CFG0_CKOUT0SEL(4)                    /*!< CK_OUT0 clock source select CKSYS */
-#define RCU_CKOUT0SRC_IRC8M         CFG0_CKOUT0SEL(5)                    /*!< CK_OUT0 clock source select IRC8M */
-#define RCU_CKOUT0SRC_HXTAL         CFG0_CKOUT0SEL(6)                    /*!< CK_OUT0 clock source select HXTAL */
-#define RCU_CKOUT0SRC_CKPLL_DIV1    (RCU_CFG0_PLLDV | CFG0_CKOUT0SEL(7)) /*!< CK_OUT0 clock source select CK_PLL */
-#define RCU_CKOUT0SRC_CKPLL_DIV2    CFG0_CKOUT0SEL(7)                    /*!< CK_OUT0 clock source select CK_PLL/2 */
-
-/* CK_OUT0 divider */
-#define CFG0_CKOUT0DIV(regval)      (BITS(28,30) & ((uint32_t)(regval) << 28))
-#define RCU_CKOUT0_DIV1             CFG0_CKOUT0DIV(0)                   /*!< CK_OUT0 is divided by 1 */
-#define RCU_CKOUT0_DIV2             CFG0_CKOUT0DIV(1)                   /*!< CK_OUT0 is divided by 2 */
-#define RCU_CKOUT0_DIV4             CFG0_CKOUT0DIV(2)                   /*!< CK_OUT0 is divided by 4 */
-#define RCU_CKOUT0_DIV8             CFG0_CKOUT0DIV(3)                   /*!< CK_OUT0 is divided by 8 */
-#define RCU_CKOUT0_DIV16            CFG0_CKOUT0DIV(4)                   /*!< CK_OUT0 is divided by 16 */
-#define RCU_CKOUT0_DIV32            CFG0_CKOUT0DIV(5)                   /*!< CK_OUT0 is divided by 32 */
-#define RCU_CKOUT0_DIV64            CFG0_CKOUT0DIV(6)                   /*!< CK_OUT0 is divided by 64 */
-#define RCU_CKOUT0_DIV128           CFG0_CKOUT0DIV(7)                   /*!< CK_OUT0 is divided by 128 */
-#endif /* GD32F130_150 */
-
-/* CK_PLL divide by 1 or 2 for CK_OUT */
-#define RCU_PLLDV_CKPLL_DIV2        (uint32_t)0x00000000U               /*!< CK_PLL divide by 2 for CK_OUT */
-#define RCU_PLLDV_CKPLL             RCU_CFG0_PLLDV                      /*!< CK_PLL divide by 1 for CK_OUT */
-
-/* LXTAL drive capability */
-#define BDCTL_LXTALDRI(regval)      (BITS(3,4) & ((uint32_t)(regval) << 3))
-#define RCU_LXTAL_LOWDRI            BDCTL_LXTALDRI(0)                   /*!< lower driving capability */
-#define RCU_LXTAL_MED_LOWDRI        BDCTL_LXTALDRI(1)                   /*!< medium low driving capability */
-#define RCU_LXTAL_MED_HIGHDRI       BDCTL_LXTALDRI(2)                   /*!< medium high driving capability */
-#define RCU_LXTAL_HIGHDRI           BDCTL_LXTALDRI(3)                   /*!< higher driving capability */
-
-/* RTC clock entry selection */
-#define BDCTL_RTCSRC(regval)        (BITS(8,9) & ((uint32_t)(regval) << 8))
-#define RCU_RTCSRC_NONE             BDCTL_RTCSRC(0)                     /*!< no clock selected */
-#define RCU_RTCSRC_LXTAL            BDCTL_RTCSRC(1)                     /*!< LXTAL selected as RTC source clock */
-#define RCU_RTCSRC_IRC40K           BDCTL_RTCSRC(2)                     /*!< IRC40K selected as RTC source clock */
-#define RCU_RTCSRC_HXTAL_DIV32      BDCTL_RTCSRC(3)                     /*!< HXTAL/32 selected as RTC source clock */
-
-#ifdef GD32F170_190
-/* SLCD clock entry selection */
-#define BDCTL_RTCSRC(regval)        (BITS(8,9) & ((uint32_t)(regval) << 8))
-#define RCU_SLCDSRC_NONE            BDCTL_RTCSRC(0)                     /*!< no clock selected */
-#define RCU_SLCDSRC_LXTAL           BDCTL_RTCSRC(1)                     /*!< LXTAL selected as SLCD source clock */
-#define RCU_SLCDSRC_IRC40K          BDCTL_RTCSRC(2)                     /*!< IRC40K selected as SLCD source clock */
-#define RCU_SLCDSRC_HXTAL_DIV32     BDCTL_RTCSRC(3)                     /*!< HXTAL/32 selected as SLCD source clock */
-#endif /* GD32F170_190 */
-
-/* CK_HXTAL divider previous PLL */
-#define CFG1_HXTALPREDV(regval)     (BITS(0,3) & ((uint32_t)(regval) << 0))
-#define RCU_PLL_HXTAL_DIV1          CFG1_HXTALPREDV(0)                  /*!< HXTAL input to PLL not divided */
-#define RCU_PLL_HXTAL_DIV2          CFG1_HXTALPREDV(1)                  /*!< HXTAL input to PLL divided by 2 */
-#define RCU_PLL_HXTAL_DIV3          CFG1_HXTALPREDV(2)                  /*!< HXTAL input to PLL divided by 3 */
-#define RCU_PLL_HXTAL_DIV4          CFG1_HXTALPREDV(3)                  /*!< HXTAL input to PLL divided by 4 */
-#define RCU_PLL_HXTAL_DIV5          CFG1_HXTALPREDV(4)                  /*!< HXTAL input to PLL divided by 5 */
-#define RCU_PLL_HXTAL_DIV6          CFG1_HXTALPREDV(5)                  /*!< HXTAL input to PLL divided by 6 */
-#define RCU_PLL_HXTAL_DIV7          CFG1_HXTALPREDV(6)                  /*!< HXTAL input to PLL divided by 7 */
-#define RCU_PLL_HXTAL_DIV8          CFG1_HXTALPREDV(7)                  /*!< HXTAL input to PLL divided by 8 */
-#define RCU_PLL_HXTAL_DIV9          CFG1_HXTALPREDV(8)                  /*!< HXTAL input to PLL divided by 9 */
-#define RCU_PLL_HXTAL_DIV10         CFG1_HXTALPREDV(9)                  /*!< HXTAL input to PLL divided by 10 */
-#define RCU_PLL_HXTAL_DIV11         CFG1_HXTALPREDV(10)                 /*!< HXTAL input to PLL divided by 11 */
-#define RCU_PLL_HXTAL_DIV12         CFG1_HXTALPREDV(11)                 /*!< HXTAL input to PLL divided by 12 */
-#define RCU_PLL_HXTAL_DIV13         CFG1_HXTALPREDV(12)                 /*!< HXTAL input to PLL divided by 13 */
-#define RCU_PLL_HXTAL_DIV14         CFG1_HXTALPREDV(13)                 /*!< HXTAL input to PLL divided by 14 */
-#define RCU_PLL_HXTAL_DIV15         CFG1_HXTALPREDV(14)                 /*!< HXTAL input to PLL divided by 15 */
-#define RCU_PLL_HXTAL_DIV16         CFG1_HXTALPREDV(15)                 /*!< HXTAL input to PLL divided by 16 */
-
-/* USART0 clock source selection */
-#define CFG2_USART0SEL(regval)      (BITS(0,1) & ((uint32_t)(regval) << 0))
-#define RCU_USART0SRC_CKAPB2        CFG2_USART0SEL(0)                   /*!< CK_USART0 select CK_APB2 */
-#define RCU_USART0SRC_CKSYS         CFG2_USART0SEL(1)                   /*!< CK_USART0 select CK_SYS */
-#define RCU_USART0SRC_LXTAL         CFG2_USART0SEL(2)                   /*!< CK_USART0 select LXTAL */
-#define RCU_USART0SRC_IRC8M         CFG2_USART0SEL(3)                   /*!< CK_USART0 select IRC8M */
-
-/* CEC clock source selection */
-#define RCU_CECSRC_IRC8M_DIV244     (uint32_t)0x00000000U               /*!< CK_CEC clock source select IRC8M/244 */
-#define RCU_CECSRC_LXTAL            RCU_CFG2_CECSEL                     /*!< CK_CEC clock source select LXTAL */
-
-#ifdef GD32F130_150
-/* ADC clock source selection */
-#define RCU_ADCSRC_IRC14M           (uint32_t)0x00000000U               /*!< ADC clock source select */
-#define RCU_ADCSRC_APB2DIV          RCU_CFG2_ADCSEL                     /*!< ADC clock source select */
-#elif defined (GD32F170_190)
-/* ADC clock source selection */
-#define RCU_ADCSRC_IRC28M           (uint32_t)0x00000000U               /*!< ADC clock source select */
-#define RCU_ADCSRC_APB2DIV          RCU_CFG2_ADCSEL                     /*!< ADC clock source select */
-
-/* IRC28M clock divider for ADC */
-#define RCU_ADC_IRC28M_DIV2         (uint32_t)0x00000000U               /*!< IRC28M/2 select to ADC clock */
-#define RCU_ADC_IRC28M_DIV1         RCU_CFG2_IRC28MDIV                  /*!< IRC28M select to ADC clock */
-
-/* CK_OUT1 clock source selection */
-#define CFG3_CKOUT1SEL(regval)      (BITS(0,2) & ((uint32_t)(regval) << 0))
-#define RCU_CKOUT1SRC_NONE          CFG3_CKOUT1SEL(0)                   /*!< no clock selected */
-#define RCU_CKOUT1SRC_IRC28M        CFG3_CKOUT1SEL(1)                   /*!< CK_OUT1 clock source select IRC28M */
-#define RCU_CKOUT1SRC_IRC40K        CFG3_CKOUT1SEL(2)                   /*!< CK_OUT1 clock source select IRC40K */
-#define RCU_CKOUT1SRC_LXTAL         CFG3_CKOUT1SEL(3)                   /*!< CK_OUT1 clock source select LXTAL */
-#define RCU_CKOUT1SRC_CKSYS         CFG3_CKOUT1SEL(4)                   /*!< CK_OUT1 clock source select CKSYS */
-#define RCU_CKOUT1SRC_IRC8M         CFG3_CKOUT1SEL(5)                   /*!< CK_OUT1 clock source select IRC8M */
-#define RCU_CKOUT1SRC_HXTAL         CFG3_CKOUT1SEL(6)                   /*!< CK_OUT1 clock source select HXTAL */
-#define RCU_CKOUT1SRC_CKPLL_DIV1    0x00000007U                         /*!< CK_OUT1 clock source select CK_PLL */
-#define RCU_CKOUT1SRC_CKPLL_DIV2    0x00000008U                         /*!< CK_OUT1 clock source select CK_PLL/2 */
-
-/* CK_OUT1 divider */
-#define CFG3_CKOUT1DIV(regval)      (BITS(8,13) & ((uint32_t)(regval) << 8))
-#define RCU_CKOUT1_DIV1             CFG3_CKOUT1DIV(0)                   /*!< CK_OUT1 is divided by 1 */
-#define RCU_CKOUT1_DIV2             CFG3_CKOUT1DIV(1)                   /*!< CK_OUT1 is divided by 2 */
-#define RCU_CKOUT1_DIV3             CFG3_CKOUT1DIV(2)                   /*!< CK_OUT1 is divided by 3 */
-#define RCU_CKOUT1_DIV4             CFG3_CKOUT1DIV(3)                   /*!< CK_OUT1 is divided by 4 */
-#define RCU_CKOUT1_DIV5             CFG3_CKOUT1DIV(4)                   /*!< CK_OUT1 is divided by 5 */
-#define RCU_CKOUT1_DIV6             CFG3_CKOUT1DIV(5)                   /*!< CK_OUT1 is divided by 6 */
-#define RCU_CKOUT1_DIV7             CFG3_CKOUT1DIV(6)                   /*!< CK_OUT1 is divided by 7 */
-#define RCU_CKOUT1_DIV8             CFG3_CKOUT1DIV(7)                   /*!< CK_OUT1 is divided by 8 */
-#define RCU_CKOUT1_DIV9             CFG3_CKOUT1DIV(8)                   /*!< CK_OUT1 is divided by 9 */
-#define RCU_CKOUT1_DIV10            CFG3_CKOUT1DIV(9)                   /*!< CK_OUT1 is divided by 10 */
-#define RCU_CKOUT1_DIV11            CFG3_CKOUT1DIV(10)                  /*!< CK_OUT1 is divided by 11 */
-#define RCU_CKOUT1_DIV12            CFG3_CKOUT1DIV(11)                  /*!< CK_OUT1 is divided by 12 */
-#define RCU_CKOUT1_DIV13            CFG3_CKOUT1DIV(12)                  /*!< CK_OUT1 is divided by 13 */
-#define RCU_CKOUT1_DIV14            CFG3_CKOUT1DIV(13)                  /*!< CK_OUT1 is divided by 14 */
-#define RCU_CKOUT1_DIV15            CFG3_CKOUT1DIV(14)                  /*!< CK_OUT1 is divided by 15 */
-#define RCU_CKOUT1_DIV16            CFG3_CKOUT1DIV(15)                  /*!< CK_OUT1 is divided by 16 */
-#define RCU_CKOUT1_DIV17            CFG3_CKOUT1DIV(16)                  /*!< CK_OUT1 is divided by 17 */
-#define RCU_CKOUT1_DIV18            CFG3_CKOUT1DIV(17)                  /*!< CK_OUT1 is divided by 18 */
-#define RCU_CKOUT1_DIV19            CFG3_CKOUT1DIV(18)                  /*!< CK_OUT1 is divided by 19 */
-#define RCU_CKOUT1_DIV20            CFG3_CKOUT1DIV(19)                  /*!< CK_OUT1 is divided by 20 */
-#define RCU_CKOUT1_DIV21            CFG3_CKOUT1DIV(20)                  /*!< CK_OUT1 is divided by 21 */
-#define RCU_CKOUT1_DIV22            CFG3_CKOUT1DIV(21)                  /*!< CK_OUT1 is divided by 22 */
-#define RCU_CKOUT1_DIV23            CFG3_CKOUT1DIV(22)                  /*!< CK_OUT1 is divided by 23 */
-#define RCU_CKOUT1_DIV24            CFG3_CKOUT1DIV(23)                  /*!< CK_OUT1 is divided by 24 */
-#define RCU_CKOUT1_DIV25            CFG3_CKOUT1DIV(24)                  /*!< CK_OUT1 is divided by 25 */
-#define RCU_CKOUT1_DIV26            CFG3_CKOUT1DIV(25)                  /*!< CK_OUT1 is divided by 26 */
-#define RCU_CKOUT1_DIV27            CFG3_CKOUT1DIV(26)                  /*!< CK_OUT1 is divided by 27 */
-#define RCU_CKOUT1_DIV28            CFG3_CKOUT1DIV(27)                  /*!< CK_OUT1 is divided by 28 */
-#define RCU_CKOUT1_DIV29            CFG3_CKOUT1DIV(28)                  /*!< CK_OUT1 is divided by 29 */
-#define RCU_CKOUT1_DIV30            CFG3_CKOUT1DIV(29)                  /*!< CK_OUT1 is divided by 30 */
-#define RCU_CKOUT1_DIV31            CFG3_CKOUT1DIV(30)                  /*!< CK_OUT1 is divided by 31 */
-#define RCU_CKOUT1_DIV32            CFG3_CKOUT1DIV(31)                  /*!< CK_OUT1 is divided by 32 */
-#define RCU_CKOUT1_DIV33            CFG3_CKOUT1DIV(32)                  /*!< CK_OUT1 is divided by 33 */
-#define RCU_CKOUT1_DIV34            CFG3_CKOUT1DIV(33)                  /*!< CK_OUT1 is divided by 34 */
-#define RCU_CKOUT1_DIV35            CFG3_CKOUT1DIV(34)                  /*!< CK_OUT1 is divided by 35 */
-#define RCU_CKOUT1_DIV36            CFG3_CKOUT1DIV(35)                  /*!< CK_OUT1 is divided by 36 */
-#define RCU_CKOUT1_DIV37            CFG3_CKOUT1DIV(36)                  /*!< CK_OUT1 is divided by 37 */
-#define RCU_CKOUT1_DIV38            CFG3_CKOUT1DIV(37)                  /*!< CK_OUT1 is divided by 38 */
-#define RCU_CKOUT1_DIV39            CFG3_CKOUT1DIV(38)                  /*!< CK_OUT1 is divided by 39 */
-#define RCU_CKOUT1_DIV40            CFG3_CKOUT1DIV(39)                  /*!< CK_OUT1 is divided by 40 */
-#define RCU_CKOUT1_DIV41            CFG3_CKOUT1DIV(40)                  /*!< CK_OUT1 is divided by 41 */
-#define RCU_CKOUT1_DIV42            CFG3_CKOUT1DIV(41)                  /*!< CK_OUT1 is divided by 42 */
-#define RCU_CKOUT1_DIV43            CFG3_CKOUT1DIV(42)                  /*!< CK_OUT1 is divided by 43 */
-#define RCU_CKOUT1_DIV44            CFG3_CKOUT1DIV(43)                  /*!< CK_OUT1 is divided by 44 */
-#define RCU_CKOUT1_DIV45            CFG3_CKOUT1DIV(44)                  /*!< CK_OUT1 is divided by 45 */
-#define RCU_CKOUT1_DIV46            CFG3_CKOUT1DIV(45)                  /*!< CK_OUT1 is divided by 46 */
-#define RCU_CKOUT1_DIV47            CFG3_CKOUT1DIV(46)                  /*!< CK_OUT1 is divided by 47 */
-#define RCU_CKOUT1_DIV48            CFG3_CKOUT1DIV(47)                  /*!< CK_OUT1 is divided by 48 */
-#define RCU_CKOUT1_DIV49            CFG3_CKOUT1DIV(48)                  /*!< CK_OUT1 is divided by 49 */
-#define RCU_CKOUT1_DIV50            CFG3_CKOUT1DIV(49)                  /*!< CK_OUT1 is divided by 50 */
-#define RCU_CKOUT1_DIV51            CFG3_CKOUT1DIV(50)                  /*!< CK_OUT1 is divided by 51 */
-#define RCU_CKOUT1_DIV52            CFG3_CKOUT1DIV(51)                  /*!< CK_OUT1 is divided by 52 */
-#define RCU_CKOUT1_DIV53            CFG3_CKOUT1DIV(52)                  /*!< CK_OUT1 is divided by 53 */
-#define RCU_CKOUT1_DIV54            CFG3_CKOUT1DIV(53)                  /*!< CK_OUT1 is divided by 54 */
-#define RCU_CKOUT1_DIV55            CFG3_CKOUT1DIV(54)                  /*!< CK_OUT1 is divided by 55 */
-#define RCU_CKOUT1_DIV56            CFG3_CKOUT1DIV(55)                  /*!< CK_OUT1 is divided by 56 */
-#define RCU_CKOUT1_DIV57            CFG3_CKOUT1DIV(56)                  /*!< CK_OUT1 is divided by 57 */
-#define RCU_CKOUT1_DIV58            CFG3_CKOUT1DIV(57)                  /*!< CK_OUT1 is divided by 58 */
-#define RCU_CKOUT1_DIV59            CFG3_CKOUT1DIV(58)                  /*!< CK_OUT1 is divided by 59 */
-#define RCU_CKOUT1_DIV60            CFG3_CKOUT1DIV(59)                  /*!< CK_OUT1 is divided by 60 */
-#define RCU_CKOUT1_DIV61            CFG3_CKOUT1DIV(60)                  /*!< CK_OUT1 is divided by 61 */
-#define RCU_CKOUT1_DIV62            CFG3_CKOUT1DIV(61)                  /*!< CK_OUT1 is divided by 62 */
-#define RCU_CKOUT1_DIV63            CFG3_CKOUT1DIV(62)                  /*!< CK_OUT1 is divided by 63 */
-#define RCU_CKOUT1_DIV64            CFG3_CKOUT1DIV(63)                  /*!< CK_OUT1 is divided by 64 */
-#endif /* GD32F130_150 */
-
-#ifdef GD32F130_150
-/* Deep-sleep mode voltage */
-#define DSV_DSLPVS(regval)          (BITS(0,2) & ((uint32_t)(regval) << 0))
-#define RCU_DEEPSLEEP_V_1_2         DSV_DSLPVS(0)                       /*!< core voltage is 1.2V in deep-sleep mode */
-#define RCU_DEEPSLEEP_V_1_1         DSV_DSLPVS(1)                       /*!< core voltage is 1.1V in deep-sleep mode */
-#define RCU_DEEPSLEEP_V_1_0         DSV_DSLPVS(2)                       /*!< core voltage is 1.0V in deep-sleep mode */
-#define RCU_DEEPSLEEP_V_0_9         DSV_DSLPVS(3)                       /*!< core voltage is 0.9V in deep-sleep mode */
-
-/*Power down voltage select*/
-#define RCU_PDR_V_2_6               (uint32_t)0x00000000U               /*!< power down voltage is 2.6V */
-#define RCU_PDR_V_1_8               RCU_PDVSEL_PDRVS                    /*!< power down voltage is 1.8V */
-
-#elif defined (GD32F170_190)
-/* Deep-sleep mode voltage */
-#define DSV_DSLPVS(regval)          (BITS(0,2) & ((uint32_t)(regval) << 0))
-#define RCU_DEEPSLEEP_V_1_8         DSV_DSLPVS(0)                       /*!< core voltage is 1.8V in deep-sleep mode */
-#define RCU_DEEPSLEEP_V_1_6         DSV_DSLPVS(1)                       /*!< core voltage is 1.6V in deep-sleep mode */
-#define RCU_DEEPSLEEP_V_1_4         DSV_DSLPVS(2)                       /*!< core voltage is 1.4V in deep-sleep mode */
-#define RCU_DEEPSLEEP_V_1_2         DSV_DSLPVS(3)                       /*!< core voltage is 1.2V in deep-sleep mode */
-#endif /* GD32F130_150 */
-
-/* function declarations */
-/* initialization, peripheral clock and reset configuration functions */
-/* deinitialize the RCU */
-void rcu_deinit(void);
-/* enable the peripherals clock */
-void rcu_periph_clock_enable(rcu_periph_enum periph);
-/* disable the peripherals clock */
-void rcu_periph_clock_disable(rcu_periph_enum periph);
-/* enable the peripherals clock when sleep mode */
-void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
-/* disable the peripherals clock when sleep mode */
-void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
-/* reset the peripherals */
-void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
-/* disable reset the peripheral */
-void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
-/* reset the BKP domain */
-void rcu_bkp_reset_enable(void);
-/* disable the BKP domain reset */
-void rcu_bkp_reset_disable(void);
-
-/* system clock, AHB, APB1, APB2, clock out, USART, ADC and other periphral configuration functions */
-/* configure the system clock source */
-void rcu_system_clock_source_config(uint32_t ck_sys);
-/* get the system clock source */
-uint32_t rcu_system_clock_source_get(void);
-/* configure the AHB prescaler selection */
-void rcu_ahb_clock_config(uint32_t ck_ahb);
-/* configure the APB1 prescaler selection */
-void rcu_apb1_clock_config(uint32_t ck_apb1);
-/* configure the APB2 prescaler selection */
-void rcu_apb2_clock_config(uint32_t ck_apb2);
-/* configure the ADC clock source and prescaler selection */
-void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc);
-#ifdef GD32F130_150
-/* configure the USBD prescaler selection */
-void rcu_usbd_clock_config(uint32_t ck_usbd);
-/* configure the CK_OUT clock source and divider */
-void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div);
-#elif defined (GD32F170_190)
-/* configure the CK_OUT0 clock source and divider */
-void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div);
-/* configure the CK_OUT1 clock source and divider */
-void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div);
-#endif /* GD32F130_150 */
-/* configure the PLL clock source selection and PLL multiply factor */
-void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
-/* configure the USART clock source selection */
-void rcu_usart_clock_config(uint32_t ck_usart);
-/* configure the CEC clock source selection */
-void rcu_cec_clock_config(uint32_t ck_cec);
-/* configure the RTC clock source selection */
-void rcu_rtc_clock_config(uint32_t rtc_clock_source);
-#ifdef GD32F170_190
-void rcu_slcd_clock_config(uint32_t slcd_clock_source);
-#endif /* GD32F170_190 */
-/* configure the HXTAL divider used as input of PLL */
-void rcu_hxtal_prediv_config(uint32_t hxtal_prediv);
-/* configure the LXTAL drive capability */
-void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap);
-
-/* flag and interrupt functions */
-/* get the clock stabilization and periphral reset flags */
-FlagStatus rcu_flag_get(rcu_flag_enum flag);
-/* clear the reset flag */
-void rcu_all_reset_flag_clear(void);
-/* get the clock stabilization interrupt and ckm flags */
-FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
-/* clear the interrupt flags */
-void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
-/* enable the stabilization interrupt */
-void rcu_interrupt_enable(rcu_int_enum stab_int);
-/* disable the stabilization interrupt */
-void rcu_interrupt_disable(rcu_int_enum stab_int);
-
-/* oscillator configuration functions */
-/* wait until oscillator stabilization flags is SET or oscillator startup is timeout */
-ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
-/* turn on the oscillator */
-void rcu_osci_on(rcu_osci_type_enum osci);
-/* turn off the oscillator */
-void rcu_osci_off(rcu_osci_type_enum osci);
-/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it  */
-void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
-/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
-void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
-/* enable the HXTAL clock monitor */
-void rcu_hxtal_clock_monitor_enable(void);
-/* disable the HXTAL clock monitor */
-void rcu_hxtal_clock_monitor_disable(void);
-
-/* set the IRC8M adjust value */
-void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval);
-#ifdef GD32F130_150
-/* set the IRC14M adjust value */
-void rcu_irc14m_adjust_value_set(uint8_t irc14m_adjval);
-#elif defined (GD32F170_190)
-/* set the IRC28M adjust value */
-void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval);
-#endif /* GD32F130_150 */
-/* unlock the voltage key */
-void rcu_voltage_key_unlock(void);
-/* set the deep sleep mode voltage */
-void rcu_deepsleep_voltage_set(uint32_t dsvol);
-#ifdef GD32F130_150
-/* set the power down voltage */
-void rcu_power_down_voltage_set(uint32_t pdvol);
-#endif /* GD32F130_150 */
-
-/* get the system clock, bus and peripheral clock frequency */
-uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
-
-#endif /* GD32F1X0_RCU_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_slcd.h

@@ -1,285 +0,0 @@
-/*!
-    \file  gd32f1x0_slcd.h
-    \brief definitions for the SLCD
-    
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifdef GD32F170_190
-#ifndef GD32F1X0_SLCD_H
-#define GD32F1X0_SLCD_H
-
-#include "gd32f1x0.h"
-
-/* SLCD definitions */
-#define SLCD                            SLCD_BASE
-
-/* registers definitions */
-#define SLCD_CTL                        REG32(SLCD + 0x00000000U)           /*!< SLCD controller register */
-#define SLCD_CFG                        REG32(SLCD + 0x00000004U)           /*!< SLCD configuration register */
-#define SLCD_STAT                       REG32(SLCD + 0x00000008U)           /*!< SLCD status flag register */
-#define SLCD_STATC                      REG32(SLCD + 0x0000000CU)           /*!< SLCD status flag clear register */
-#define SLCD_DATA0                      REG32(SLCD + 0x00000014U)           /*!< SLCD display data register 0 */
-#define SLCD_DATA1                      REG32(SLCD + 0x0000001CU)           /*!< SLCD display data register 1 */
-#define SLCD_DATA2                      REG32(SLCD + 0x00000024U)           /*!< SLCD display data register 2 */
-#define SLCD_DATA3                      REG32(SLCD + 0x0000002CU)           /*!< SLCD display data register 3 */
-#define SLCD_DATA4                      REG32(SLCD + 0x00000034U)           /*!< SLCD display data register 4 */
-#define SLCD_DATA5                      REG32(SLCD + 0x0000003CU)           /*!< SLCD display data register 5 */
-#define SLCD_DATA6                      REG32(SLCD + 0x00000044U)           /*!< SLCD display data register 6 */
-#define SLCD_DATA7                      REG32(SLCD + 0x0000004CU)           /*!< SLCD display data register 7 */
-
-/* bits definitions */
-/* SLCD_CTL */
-#define SLCD_CTL_SLCDON                 BIT(0)                              /*!< SLCD controller start */
-#define SLCD_CTL_VSRC                   BIT(1)                              /*!< SLCD Voltage source */
-#define SLCD_CTL_DUTY                   BITS(2,4)                           /*!< duty select */
-#define SLCD_CTL_BIAS                   BITS(5,6)                           /*!< SLCD bias voltage select */
-#define SLCD_CTL_COMS                   BIT(7)                              /*!< regular channel start flag */
-
-/* SLCD_CFG */
-#define SLCD_CFG_HDEN                   BIT(0)                              /*!< high drive enable */
-#define SLCD_CFG_SOFIE                  BIT(1)                              /*!< start of frame interrupt enable */
-#define SLCD_CFG_UPDIE                  BIT(3)                              /*!< SLCD update done interrupt enable */
-#define SLCD_CFG_PULSE                  BITS(4,6)                           /*!< pulse on duration */
-#define SLCD_CFG_DTD                    BITS(7,9)                           /*!< dead time duration */
-#define SLCD_CFG_CONR                   BITS(10,12)                         /*!< contrast ratio */
-#define SLCD_CFG_BLKDIV                 BITS(13,15)                         /*!< blink frequency divider */
-#define SLCD_CFG_BLKMOD                 BITS(16,17)                         /*!< blink mode */
-#define SLCD_CFG_DIV                    BITS(18,21)                         /*!< SLCD clock divider */
-#define SLCD_CFG_PSC                    BITS(22,25)                         /*!< SLCD clock prescaler */
-
-/* SLCD_STAT */
-#define SLCD_STAT_ONF                   BIT(0)                              /*!< SLCD controller on flag */
-#define SLCD_STAT_SOF                   BIT(1)                              /*!< start of frame flag */
-#define SLCD_STAT_UPRF                  BIT(2)                              /*!< SLCD data update request flag */
-#define SLCD_STAT_UPDF                  BIT(3)                              /*!< update data done flag */
-#define SLCD_STAT_VRDYF                 BIT(4)                              /*!< SLCD voltage ready flag */
-#define SLCD_STAT_SYNF                  BIT(5)                              /*!< SLCD register synchronization flag */
-
-/* SLCD_STATC */
-#define SLCD_STATC_SOFC                 BIT(1)                              /*!< start of frame flag clear */
-#define SLCD_STATC_UPDC                 BIT(3)                              /*!< SLCD data update done clear bit */
-
-/* SLCD_DATAx */
-#define SLCD_DATAx_DATA                 BITS(0,31)                          /*!< each bit corresponds to one segment to display */
-
-/* constants definitions */
-/* status flag */
-#define SLCD_FLAG_ON                    SLCD_STAT_ONF                       /*!< SLCD controller on flag */
-#define SLCD_FLAG_SOF                   SLCD_STAT_SOF                       /*!< start of frame flag */
-#define SLCD_FLAG_UPR                   SLCD_STAT_UPRF                      /*!< SLCD data update request flag */
-#define SLCD_FLAG_UPD                   SLCD_STAT_UPDF                      /*!< update data done flag */
-#define SLCD_FLAG_VRDY                  SLCD_STAT_VRDYF                     /*!< SLCD voltage ready flag */
-#define SLCD_FLAG_SYN                   SLCD_STAT_SYNF                      /*!< SLCD register synchronization flag */
-
-/* interrupt flag */
-#define SLCD_INT_FLAG_SOF               ((uint8_t)0x00U)                    /*!< start of frame interrupt */
-#define SLCD_INT_FLAG_UPD               ((uint8_t)0x01U)                    /*!< update data done interrupt */
-
-/* interrupt source */
-#define SLCD_INT_SOF                    ((uint8_t)0x00U)                    /*!< start of frame interrupt */
-#define SLCD_INT_UPD                    ((uint8_t)0x01U)                    /*!< update data done interrupt */
-
-/* voltage source definitions */
-#define SLCD_VOLTAGE_INTERNAL           ((uint8_t)0x00U)                    /*!< SLCD internal voltage source */
-#define SLCD_VOLTAGE_EXTERNAL           ((uint8_t)0x01U)                    /*!< SLCD external voltage source */
-
-/*data register number */
-typedef enum 
-{
-    SLCD_DATA_REG0,                                              /*!< SLCD display data register 0 */
-    SLCD_DATA_REG1,                                                  /*!< SLCD display data register 1 */
-    SLCD_DATA_REG2,                                                  /*!< SLCD display data register 2 */
-    SLCD_DATA_REG3,                                                  /*!< SLCD display data register 3 */
-    SLCD_DATA_REG4,                                                  /*!< SLCD display data register 4 */
-    SLCD_DATA_REG5,                                                  /*!< SLCD display data register 5 */
-    SLCD_DATA_REG6,                                                  /*!< SLCD display data register 6 */
-    SLCD_DATA_REG7,                                                  /*!< SLCD display data register 7 */
-}slcd_data_register_enum;
-
-/* SLCD data register */
-#define SLCD_DATA0_7(number)             REG32((SLCD) + 0x14U + (number) * 0x08U)
-
-/* bias voltage definitions */
-#define CTL_BIAS(regval)                (BITS(5,6) & ((uint32_t)(regval) << 5U))
-#define SLCD_BIAS_1_4                   CTL_BIAS(0)                         /*!< 1/4 voltage bias */
-#define SLCD_BIAS_1_2                   CTL_BIAS(1)                         /*!< 1/2 voltage bias */
-#define SLCD_BIAS_1_3                   CTL_BIAS(2)                         /*!< 1/3 voltage bias */
-
-/* duty select definitions */
-#define CTL_DUTY(regval)                (BITS(2,4) & ((uint32_t)(regval) << 2U))
-#define SLCD_DUTY_STATIC                CTL_DUTY(0)                         /*!< static dutycycle */
-#define SLCD_DUTY_1_2                   CTL_DUTY(1)                         /*!< 1/2 dutycycle */
-#define SLCD_DUTY_1_3                   CTL_DUTY(2)                         /*!< 1/3 dutycycle */
-#define SLCD_DUTY_1_4                   CTL_DUTY(3)                         /*!< 1/4 dutycycle */
-#define SLCD_DUTY_1_6                   CTL_DUTY(5)                         /*!< 1/6 dutycycle */
-#define SLCD_DUTY_1_8                   CTL_DUTY(4)                         /*!< 1/8 dutycycle */
-
-/* SLCD clock prescaler */
-#define CFG_PRE(regval)                 (BITS(22,25) & ((uint32_t)(regval) << 22U))
-#define SLCD_PRESCALER_1                CFG_PRE(0)                          /*!< PRE = 0 */
-#define SLCD_PRESCALER_2                CFG_PRE(1)                          /*!< PRE = 1 */
-#define SLCD_PRESCALER_4                CFG_PRE(2)                          /*!< PRE = 2 */
-#define SLCD_PRESCALER_8                CFG_PRE(3)                          /*!< PRE = 3 */
-#define SLCD_PRESCALER_16               CFG_PRE(4)                          /*!< PRE = 4 */
-#define SLCD_PRESCALER_32               CFG_PRE(5)                          /*!< PRE = 5 */
-#define SLCD_PRESCALER_64               CFG_PRE(6)                          /*!< PRE = 6 */
-#define SLCD_PRESCALER_128              CFG_PRE(7)                          /*!< PRE = 7 */
-#define SLCD_PRESCALER_256              CFG_PRE(8)                          /*!< PRE = 8 */
-#define SLCD_PRESCALER_512              CFG_PRE(9)                          /*!< PRE = 9 */
-#define SLCD_PRESCALER_1024             CFG_PRE(10)                         /*!< PRE = 10 */
-#define SLCD_PRESCALER_2048             CFG_PRE(11)                         /*!< PRE = 11 */
-#define SLCD_PRESCALER_4096             CFG_PRE(12)                         /*!< PRE = 12 */
-#define SLCD_PRESCALER_8192             CFG_PRE(13)                         /*!< PRE = 13 */
-#define SLCD_PRESCALER_16384            CFG_PRE(14)                         /*!< PRE = 14 */
-#define SLCD_PRESCALER_32768            CFG_PRE(15)                         /*!< PRE = 15 */
-
-/* SLCD clock divider */
-#define CFG_DIV(regval)                 (BITS(18,21) & ((uint32_t)(regval) << 18U))
-#define SLCD_DIVIDER_16                 CFG_DIV(0)                          /*!< DIV = 16 */
-#define SLCD_DIVIDER_17                 CFG_DIV(1)                          /*!< DIV = 17 */
-#define SLCD_DIVIDER_18                 CFG_DIV(2)                          /*!< DIV = 18 */
-#define SLCD_DIVIDER_19                 CFG_DIV(3)                          /*!< DIV = 19 */
-#define SLCD_DIVIDER_20                 CFG_DIV(4)                          /*!< DIV = 20 */
-#define SLCD_DIVIDER_21                 CFG_DIV(5)                          /*!< DIV = 21 */
-#define SLCD_DIVIDER_22                 CFG_DIV(6)                          /*!< DIV = 22 */
-#define SLCD_DIVIDER_23                 CFG_DIV(7)                          /*!< DIV = 23 */
-#define SLCD_DIVIDER_24                 CFG_DIV(8)                          /*!< DIV = 24 */
-#define SLCD_DIVIDER_25                 CFG_DIV(9)                          /*!< DIV = 25 */
-#define SLCD_DIVIDER_26                 CFG_DIV(10)                         /*!< DIV = 26 */
-#define SLCD_DIVIDER_27                 CFG_DIV(11)                         /*!< DIV = 27 */
-#define SLCD_DIVIDER_28                 CFG_DIV(12)                         /*!< DIV = 28 */
-#define SLCD_DIVIDER_29                 CFG_DIV(13)                         /*!< DIV = 29 */
-#define SLCD_DIVIDER_30                 CFG_DIV(14)                         /*!< DIV = 30 */
-#define SLCD_DIVIDER_31                 CFG_DIV(15)                         /*!< DIV = 31 */
-
-/* SLCD blink mode */
-#define CFG_BLKM(regval)                (BITS(16,17) & ((uint32_t)(regval) << 16U))
-#define SLCD_BLINKMODE_OFF              CFG_BLKM(0)                         /*!< blink disabled */
-#define SLCD_BLINKMODE_SEG0_COM0        CFG_BLKM(1)                         /*!< blink enabled on SEG[0], COM[0] */
-#define SLCD_BLINKMODE_SEG0_ALLCOM      CFG_BLKM(2)                         /*!< blink enabled on SEG[0], all COM */
-#define SLCD_BLINKMODE_ALLSEG_ALLCOM    CFG_BLKM(3)                         /*!< blink enabled on all SEG and all COM */
-
-/* SLCD blink frequency divider */
-#define CFG_BLKDIV(regval)              (BITS(13,15) & ((uint32_t)(regval) << 13U))
-#define SLCD_BLINK_FREQUENCY_DIV8       CFG_BLKDIV(0)                       /*!< blink frequency = fSLCD/8 */
-#define SLCD_BLINK_FREQUENCY_DIV16      CFG_BLKDIV(1)                       /*!< blink frequency = fSLCD/16 */
-#define SLCD_BLINK_FREQUENCY_DIV32      CFG_BLKDIV(2)                       /*!< blink frequency = fSLCD/32 */
-#define SLCD_BLINK_FREQUENCY_DIV64      CFG_BLKDIV(3)                       /*!< blink frequency = fSLCD/64 */
-#define SLCD_BLINK_FREQUENCY_DIV128     CFG_BLKDIV(4)                       /*!< blink frequency = fSLCD/128 */
-#define SLCD_BLINK_FREQUENCY_DIV256     CFG_BLKDIV(5)                       /*!< blink frequency = fSLCD/256 */
-#define SLCD_BLINK_FREQUENCY_DIV512     CFG_BLKDIV(6)                       /*!< blink frequency = fSLCD/512 */
-#define SLCD_BLINK_FREQUENCY_DIV1024    CFG_BLKDIV(7)                       /*!< blink frequency = fSLCD/1024 */
-
-/* SLCD Contrast ratio */
-#define CFG_CONR(regval)                (BITS(10,12) & ((uint32_t)(regval) << 10U))
-#define SLCD_CONTRAST_LEVEL_0           CFG_CONR(0)                         /*!< maximum SLCD Voltage = 2.60V */
-#define SLCD_CONTRAST_LEVEL_1           CFG_CONR(1)                         /*!< maximum SLCD Voltage = 2.73V */
-#define SLCD_CONTRAST_LEVEL_2           CFG_CONR(2)                         /*!< maximum SLCD Voltage = 2.86V */
-#define SLCD_CONTRAST_LEVEL_3           CFG_CONR(3)                         /*!< maximum SLCD Voltage = 2.99V */
-#define SLCD_CONTRAST_LEVEL_4           CFG_CONR(4)                         /*!< maximum SLCD Voltage = 3.12V */
-#define SLCD_CONTRAST_LEVEL_5           CFG_CONR(5)                         /*!< maximum SLCD Voltage = 3.25V */
-#define SLCD_CONTRAST_LEVEL_6           CFG_CONR(6)                         /*!< maximum SLCD Voltage = 3.38V */
-#define SLCD_CONTRAST_LEVEL_7           CFG_CONR(7)                         /*!< maximum SLCD Voltage = 3.51V */
-
-/* dead time duration */
-#define CFG_DD(regval)                  (BITS(7,9) & ((uint32_t)(regval) << 7U))
-#define SLCD_DEADTIME_PERIOD_0          CFG_DD(0)                           /*!< no dead time */
-#define SLCD_DEADTIME_PERIOD_1          CFG_DD(1)                           /*!< 1 phase inserted between couple of frame */
-#define SLCD_DEADTIME_PERIOD_2          CFG_DD(2)                           /*!< 2 phase inserted between couple of frame */
-#define SLCD_DEADTIME_PERIOD_3          CFG_DD(3)                           /*!< 3 phase inserted between couple of frame */
-#define SLCD_DEADTIME_PERIOD_4          CFG_DD(4)                           /*!< 4 phase inserted between couple of frame */
-#define SLCD_DEADTIME_PERIOD_5          CFG_DD(5)                           /*!< 5 phase inserted between couple of frame */
-#define SLCD_DEADTIME_PERIOD_6          CFG_DD(6)                           /*!< 6 phase inserted between couple of frame */
-#define SLCD_DEADTIME_PERIOD_7          CFG_DD(7)                           /*!< 7 phase inserted between couple of frame */
-
-/* pulse on duration */
-#define CFG_PULSE(regval)               (BITS(4,6) & ((uint32_t)(regval) << 4U))
-#define SLCD_PULSEON_DURATION_0         CFG_PULSE(0)                        /*!< pulse on duration = 0 */
-#define SLCD_PULSEON_DURATION_1         CFG_PULSE(1)                        /*!< pulse on duration = 1*1/fPRE */
-#define SLCD_PULSEON_DURATION_2         CFG_PULSE(2)                        /*!< pulse on duration = 2*1/fPRE */
-#define SLCD_PULSEON_DURATION_3         CFG_PULSE(3)                        /*!< pulse on duration = 3*1/fPRE */
-#define SLCD_PULSEON_DURATION_4         CFG_PULSE(4)                        /*!< pulse on duration = 4*1/fPRE */
-#define SLCD_PULSEON_DURATION_5         CFG_PULSE(5)                        /*!< pulse on duration = 5*1/fPRE */
-#define SLCD_PULSEON_DURATION_6         CFG_PULSE(6)                        /*!< pulse on duration = 6*1/fPRE */
-#define SLCD_PULSEON_DURATION_7         CFG_PULSE(7)                        /*!< pulse on duration = 7*1/fPRE */
-
-/* function declarations */
-/* check the SLCD status flag */
-FlagStatus slcd_flag_get(uint8_t slcd_flag);
-/* check the SLCD interrupt flag */
-FlagStatus slcd_interrupt_flag_get(uint8_t slcd_interrupt);
-/* clear the SLCD flag */
-void slcd_flag_clear(uint8_t slcd_flag);
-/* clear the SLCD interrupt flag */
-void slcd_interrupt_flag_clear(uint8_t slcd_interrupt);
-/* the SLCD interrupt config */
-void slcd_interrupt_config(uint8_t slcd_interrupt,ControlStatus newvalue);
-
-/* SLCD bias voltage select */
-void slcd_bias_voltage_select(uint32_t bias_voltage);
-/* SLCD duty select */
-void slcd_duty_select(uint32_t duty);
-/* SLCD input clock config */
-void slcd_clock_config(uint32_t prescaler,uint32_t divider);
-/* SLCD blink mode config */
-void slcd_blink_mode_config(uint32_t mode,uint32_t blink_divider);
-/* SLCD contrast ratio config */
-void slcd_contrast_ratio_config(uint32_t contrast_ratio);
-/* SLCD dead time duration config */
-void slcd_dead_time_config(uint32_t dead_time);
-/* SLCD pulse on duration config */
-void slcd_pulse_on_duration_config(uint32_t duration);
-/* SLCD common/segment pad select */
-void slcd_com_seg_remap(ControlStatus newvalue);
-/* SLCD voltage source select */
-void slcd_voltage_source_select(uint8_t voltage_source);
-/* SLCD high drive enable */
-void slcd_high_drive_config(ControlStatus newvalue);
-
-/* SLCD data register write */
-void slcd_data_register_write(slcd_data_register_enum register_number, uint32_t data);
-/* SLCD data update request */
-void slcd_data_update_request(void);
-
-/* SLCD reset */
-void slcd_deinit(void);
-/* enable SLCD interface */
-void slcd_enable(void);
-/* disable SLCD interface */
-void slcd_disable(void);
-
-#endif /* GD32F1X0_SLCD_H */
-
-#endif /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_tsi.h

@@ -1,366 +0,0 @@
-/*!
-    \file  gd32f1x0_tsi.h
-    \brief definitions for the TSI
-    
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F1X0_TSI_H
-#define GD32F1X0_TSI_H
-
-#include "gd32f1x0.h"
-
-/* TSI definitions */
-#define TSI                     TSI_BASE                  /*!< TSI base address */
-
-/* registers definitions */
-#define TSI_CTL                 REG32(TSI + 0x00000000U)  /*!< TSI control register */
-#define TSI_INTEN               REG32(TSI + 0x00000004U)  /*!< TSI interrupt enable register */
-#define TSI_INTC                REG32(TSI + 0x00000008U)  /*!< TSI interrupt flag clear register */
-#define TSI_INTF                REG32(TSI + 0x0000000CU)  /*!< TSI interrupt flag register */
-#define TSI_PHM                 REG32(TSI + 0x00000010U)  /*!< TSI pin hysteresis mode register */
-#define TSI_ASW                 REG32(TSI + 0x00000018U)  /*!< TSI analog switch register */
-#define TSI_SAMPCFG             REG32(TSI + 0x00000020U)  /*!< TSI sample configuration register */
-#define TSI_CHCFG               REG32(TSI + 0x00000028U)  /*!< TSI channel configuration register */
-#define TSI_GCTL                REG32(TSI + 0x00000030U)  /*!< TSI group control register */
-#define TSI_G0CYCN              REG32(TSI + 0x00000034U)  /*!< TSI group 0 cycle number register */
-#define TSI_G1CYCN              REG32(TSI + 0x00000038U)  /*!< TSI group 1 cycle number register */
-#define TSI_G2CYCN              REG32(TSI + 0x0000003CU)  /*!< TSI group 2 cycle number register */
-#define TSI_G3CYCN              REG32(TSI + 0x00000040U)  /*!< TSI group 3 cycle number register */
-#define TSI_G4CYCN              REG32(TSI + 0x00000044U)  /*!< TSI group 4 cycle number register */
-#define TSI_G5CYCN              REG32(TSI + 0x00000048U)  /*!< TSI group 5 cycle number register */
-
-/* bits definitions */
-/* TSI_CTL */
-#define TSI_CTL_TSIEN           BIT(0)              /*!< TSI enable */
-#define TSI_CTL_TSIS            BIT(1)              /*!< TSI start */
-#define TSI_CTL_TRGMOD          BIT(2)              /*!< trigger mode selection */
-#define TSI_CTL_EGSEL           BIT(3)              /*!< edge selection */
-#define TSI_CTL_PINMOD          BIT(4)              /*!< pin mode */
-#define TSI_CTL_MCN             BITS(5,7)           /*!< max cycle number of a sequence */
-#define TSI_CTL_CTCDIV          BITS(12,14)         /*!< CTCLK clock division factor */
-#define TSI_CTL_ECDIV           BIT(15)             /*!< ECCLK clock division factor */
-#define TSI_CTL_ECEN            BIT(16)             /*!< extend charge state enable */
-#define TSI_CTL_ECDT            BITS(17,23)         /*!< extend charge State maximum duration time */
-#define TSI_CTL_CTDT            BITS(24,27)         /*!< charge transfer state duration time */
-#define TSI_CTL_CDT             BITS(28,31)         /*!< charge state duration time */
-
-/* TSI_INTEN */
-#define TSI_INTEN_CTCFIE        BIT(0)              /*!< charge transfer complete flag interrupt enable */
-#define TSI_INTEN_MNERRIE       BIT(1)              /*!< max cycle number error interrupt enable */
-
-/* TSI_INTC */
-#define TSI_INTC_CCTCF          BIT(0)              /*!< clear charge transfer complete flag */
-#define TSI_INTC_CMNERR         BIT(1)              /*!< clear max cycle number error */
-
-/* TSI_INTF */
-#define TSI_INTF_CTCF           BIT(0)              /*!< charge transfer complete flag */
-#define TSI_INTF_MNERR          BIT(1)              /*!< max cycle number error */
-
-/* TSI_PHM */
-#define TSI_PHM_G0P0            BIT(0)              /*!< pin G0P0 Schmitt trigger hysteresis state */
-#define TSI_PHM_G0P1            BIT(1)              /*!< pin G0P1 Schmitt trigger hysteresis state */
-#define TSI_PHM_G0P2            BIT(2)              /*!< pin G0P2 Schmitt trigger hysteresis state */
-#define TSI_PHM_G0P3            BIT(3)              /*!< pin G0P3 Schmitt trigger hysteresis state */
-#define TSI_PHM_G1P0            BIT(4)              /*!< pin G1P0 Schmitt trigger hysteresis state */
-#define TSI_PHM_G1P1            BIT(5)              /*!< pin G1P1 Schmitt trigger hysteresis state */
-#define TSI_PHM_G1P2            BIT(6)              /*!< pin G1P2 Schmitt trigger hysteresis state */
-#define TSI_PHM_G1P3            BIT(7)              /*!< pin G1P3 Schmitt trigger hysteresis state */
-#define TSI_PHM_G2P0            BIT(8)              /*!< pin G2P0 Schmitt trigger hysteresis state */
-#define TSI_PHM_G2P1            BIT(9)              /*!< pin G2P1 Schmitt trigger hysteresis state */
-#define TSI_PHM_G2P2            BIT(10)             /*!< pin G2P2 Schmitt trigger hysteresis state */
-#define TSI_PHM_G2P3            BIT(11)             /*!< pin G2P3 Schmitt trigger hysteresis state */
-#define TSI_PHM_G3P0            BIT(12)             /*!< pin G3P0 Schmitt trigger hysteresis state */
-#define TSI_PHM_G3P1            BIT(13)             /*!< pin G3P1 Schmitt trigger hysteresis state */
-#define TSI_PHM_G3P2            BIT(14)             /*!< pin G3P2 Schmitt trigger hysteresis state */
-#define TSI_PHM_G3P3            BIT(15)             /*!< pin G3P3 Schmitt trigger hysteresis state */
-#define TSI_PHM_G4P0            BIT(16)             /*!< pin G4P0 Schmitt trigger hysteresis state */
-#define TSI_PHM_G4P1            BIT(17)             /*!< pin G4P1 Schmitt trigger hysteresis state */
-#define TSI_PHM_G4P2            BIT(18)             /*!< pin G4P2 Schmitt trigger hysteresis state */
-#define TSI_PHM_G4P3            BIT(19)             /*!< pin G4P3 Schmitt trigger hysteresis state */
-#define TSI_PHM_G5P0            BIT(20)             /*!< pin G5P0 Schmitt trigger hysteresis state */
-#define TSI_PHM_G5P1            BIT(21)             /*!< pin G5P1 Schmitt trigger hysteresis state */
-#define TSI_PHM_G5P2            BIT(22)             /*!< pin G5P2 Schmitt trigger hysteresis state */
-#define TSI_PHM_G5P3            BIT(23)             /*!< pin G5P3 Schmitt trigger hysteresis state */
-
-/* TSI_ASW */
-#define TSI_ASW_G0P0            BIT(0)              /*!< pin G0P0 analog switch state */
-#define TSI_ASW_G0P1            BIT(1)              /*!< pin G0P2 analog switch state */
-#define TSI_ASW_G0P2            BIT(2)              /*!< pin G0P3 analog switch state */
-#define TSI_ASW_G0P3            BIT(3)              /*!< pin G0P4 analog switch state */
-#define TSI_ASW_G1P0            BIT(4)              /*!< pin G1P0 analog switch state */
-#define TSI_ASW_G1P1            BIT(5)              /*!< pin G1P1 analog switch state */
-#define TSI_ASW_G1P2            BIT(6)              /*!< pin G1P2 analog switch state */
-#define TSI_ASW_G1P3            BIT(7)              /*!< pin G1P3 analog switch state */
-#define TSI_ASW_G2P0            BIT(8)              /*!< pin G2P0 analog switch state */
-#define TSI_ASW_G2P1            BIT(9)              /*!< pin G2P1 analog switch state */
-#define TSI_ASW_G2P2            BIT(10)             /*!< pin G2P2 analog switch state */
-#define TSI_ASW_G2P3            BIT(11)             /*!< pin G2P3 analog switch state */
-#define TSI_ASW_G3P0            BIT(12)             /*!< pin G3P0 analog switch state */
-#define TSI_ASW_G3P1            BIT(13)             /*!< pin G3P1 analog switch state */
-#define TSI_ASW_G3P2            BIT(14)             /*!< pin G3P2 analog switch state */
-#define TSI_ASW_G3P3            BIT(15)             /*!< pin G3P3 analog switch state */
-#define TSI_ASW_G4P0            BIT(16)             /*!< pin G4P0 analog switch state */
-#define TSI_ASW_G4P1            BIT(17)             /*!< pin G4P1 analog switch state */
-#define TSI_ASW_G4P2            BIT(18)             /*!< pin G4P2 analog switch state */
-#define TSI_ASW_G4P3            BIT(19)             /*!< pin G4P3 analog switch state */
-#define TSI_ASW_G5P0            BIT(20)             /*!< pin G5P0 analog switch state */
-#define TSI_ASW_G5P1            BIT(21)             /*!< pin G5P1 analog switch state */
-#define TSI_ASW_G5P2            BIT(22)             /*!< pin G5P2 analog switch state */
-#define TSI_ASW_G5P3            BIT(23)             /*!< pin G5P3 analog switch state */
-
-/* TSI_SAMPCFG */
-#define TSI_SAMPCFG_G0P0        BIT(0)              /*!< pin G0P0 sample pin mode */
-#define TSI_SAMPCFG_G0P1        BIT(1)              /*!< pin G0P1 sample pin mode */
-#define TSI_SAMPCFG_G0P2        BIT(2)              /*!< pin G0P2 sample pin mode */
-#define TSI_SAMPCFG_G0P3        BIT(3)              /*!< pin G0P3 sample pin mode */
-#define TSI_SAMPCFG_G1P0        BIT(4)              /*!< pin G1P0 sample pin mode */
-#define TSI_SAMPCFG_G1P1        BIT(5)              /*!< pin G1P1 sample pin mode */
-#define TSI_SAMPCFG_G1P2        BIT(6)              /*!< pin G1P2 sample pin mode */
-#define TSI_SAMPCFG_G1P3        BIT(7)              /*!< pin G1P3 sample pin mode */
-#define TSI_SAMPCFG_G2P0        BIT(8)              /*!< pin G2P0 sample pin mode */
-#define TSI_SAMPCFG_G2P1        BIT(9)              /*!< pin G2P1 sample pin mode */
-#define TSI_SAMPCFG_G2P2        BIT(10)             /*!< pin G2P2 sample pin mode */
-#define TSI_SAMPCFG_G2P3        BIT(11)             /*!< pin G2P3 sample pin mode */
-#define TSI_SAMPCFG_G3P0        BIT(12)             /*!< pin G3P0 sample pin mode */
-#define TSI_SAMPCFG_G3P1        BIT(13)             /*!< pin G3P1 sample pin mode */
-#define TSI_SAMPCFG_G3P2        BIT(14)             /*!< pin G3P2 sample pin mode */
-#define TSI_SAMPCFG_G3P3        BIT(15)             /*!< pin G3P3 sample pin mode */
-#define TSI_SAMPCFG_G4P0        BIT(16)             /*!< pin G4P0 sample pin mode */
-#define TSI_SAMPCFG_G4P1        BIT(17)             /*!< pin G4P1 sample pin mode */
-#define TSI_SAMPCFG_G4P2        BIT(18)             /*!< pin G4P2 sample pin mode */
-#define TSI_SAMPCFG_G4P3        BIT(19)             /*!< pin G4P3 sample pin mode */
-#define TSI_SAMPCFG_G5P0        BIT(20)             /*!< pin G5P0 sample pin mode */
-#define TSI_SAMPCFG_G5P1        BIT(21)             /*!< pin G5P1 sample pin mode */
-#define TSI_SAMPCFG_G5P2        BIT(22)             /*!< pin G5P2 sample pin mode */
-#define TSI_SAMPCFG_G5P3        BIT(23)             /*!< pin G5P3 sample pin mode */
-
-/* TSI_CHCFG */
-#define TSI_CHCFG_G0P0          BIT(0)              /*!< pin G0P0 channel pin mode */
-#define TSI_CHCFG_G0P1          BIT(1)              /*!< pin G0P1 channel pin mode */
-#define TSI_CHCFG_G0P2          BIT(2)              /*!< pin G0P2 channel pin mode */
-#define TSI_CHCFG_G0P3          BIT(3)              /*!< pin G0P3 channel pin mode */
-#define TSI_CHCFG_G1P0          BIT(4)              /*!< pin G1P0 channel pin mode */
-#define TSI_CHCFG_G1P1          BIT(5)              /*!< pin G1P1 channel pin mode */
-#define TSI_CHCFG_G1P2          BIT(6)              /*!< pin G1P2 channel pin mode */
-#define TSI_CHCFG_G1P3          BIT(7)              /*!< pin G1P3 channel pin mode */
-#define TSI_CHCFG_G2P0          BIT(8)              /*!< pin G2P0 channel pin mode */
-#define TSI_CHCFG_G2P1          BIT(9)              /*!< pin G2P1 channel pin mode */
-#define TSI_CHCFG_G2P2          BIT(10)             /*!< pin G2P2 channel pin mode */
-#define TSI_CHCFG_G2P3          BIT(11)             /*!< pin G2P3 channel pin mode */
-#define TSI_CHCFG_G3P0          BIT(12)             /*!< pin G3P0 channel pin mode */
-#define TSI_CHCFG_G3P1          BIT(13)             /*!< pin G3P1 channel pin mode */
-#define TSI_CHCFG_G3P2          BIT(14)             /*!< pin G3P2 channel pin mode */
-#define TSI_CHCFG_G3P3          BIT(15)             /*!< pin G3P3 channel pin mode */
-#define TSI_CHCFG_G4P0          BIT(16)             /*!< pin G4P0 channel pin mode */
-#define TSI_CHCFG_G4P1          BIT(17)             /*!< pin G4P1 channel pin mode */
-#define TSI_CHCFG_G4P2          BIT(18)             /*!< pin G4P2 channel pin mode */
-#define TSI_CHCFG_G4P3          BIT(19)             /*!< pin G4P3 channel pin mode */
-#define TSI_CHCFG_G5P0          BIT(20)             /*!< pin G5P0 channel pin mode */
-#define TSI_CHCFG_G5P1          BIT(21)             /*!< pin G5P1 channel pin mode */
-#define TSI_CHCFG_G5P2          BIT(22)             /*!< pin G5P2 channel pin mode */
-#define TSI_CHCFG_G5P3          BIT(23)             /*!< pin G5P3 channel pin mode */
-
-/* TSI_GCTL */
-#define TSI_GCTL_GE0            BIT(0)              /*!< group0 enable */
-#define TSI_GCTL_GE1            BIT(1)              /*!< group1 enable */
-#define TSI_GCTL_GE2            BIT(2)              /*!< group2 enable */
-#define TSI_GCTL_GE3            BIT(3)              /*!< group3 enable */
-#define TSI_GCTL_GE4            BIT(4)              /*!< group4 enable */
-#define TSI_GCTL_GE5            BIT(5)              /*!< group5 enable */
-#define TSI_GCTL_GC0            BIT(16)             /*!< group0 complete */
-#define TSI_GCTL_GC1            BIT(17)             /*!< group1 complete */
-#define TSI_GCTL_GC2            BIT(18)             /*!< group2 complete */
-#define TSI_GCTL_GC3            BIT(19)             /*!< group3 complete */
-#define TSI_GCTL_GC4            BIT(20)             /*!< group4 complete */
-#define TSI_GCTL_GC5            BIT(21)             /*!< group5 complete */
-
-/* constants definitions */
-/* CTCLK clock division factor */
-#define CTL_CTCDIV(regval)      (BITS(12,14) & ((regval) << 12U))   /*!< CTCLK clock division factor */
-#define TSI_CTCDIV_DIV1         CTL_CTCDIV(0)                       /*!< fCTCLK = fHCLK */
-#define TSI_CTCDIV_DIV2         CTL_CTCDIV(1)                       /*!< fCTCLK = fHCLK/2 */
-#define TSI_CTCDIV_DIV4         CTL_CTCDIV(2)                       /*!< fCTCLK = fHCLK/4 */
-#define TSI_CTCDIV_DIV8         CTL_CTCDIV(3)                       /*!< fCTCLK = fHCLK/8 */
-#define TSI_CTCDIV_DIV16        CTL_CTCDIV(4)                       /*!< fCTCLK = fHCLK/16 */
-#define TSI_CTCDIV_DIV32        CTL_CTCDIV(5)                       /*!< fCTCLK = fHCLK/32 */
-#define TSI_CTCDIV_DIV64        CTL_CTCDIV(6)                       /*!< fCTCLK = fHCLK/64 */
-#define TSI_CTCDIV_DIV128       CTL_CTCDIV(7)                       /*!< fCTCLK = fHCLK/128 */
-
-/* charge transfer state duration Time */
-#define CTL_CTDT(regval)        (BITS(24,27) & ((regval) << 24U))   /*!< charge transfer state duration time */
-#define TSI_TRANSFER_1CTCLK     CTL_CTDT(0)                         /*!< the duration time of transfer state is 1 CTCLK */
-#define TSI_TRANSFER_2CTCLK     CTL_CTDT(1)                         /*!< the duration time of transfer state is 2 CTCLK */
-#define TSI_TRANSFER_3CTCLK     CTL_CTDT(2)                         /*!< the duration time of transfer state is 3 CTCLK */
-#define TSI_TRANSFER_4CTCLK     CTL_CTDT(3)                         /*!< the duration time of transfer state is 4 CTCLK */
-#define TSI_TRANSFER_5CTCLK     CTL_CTDT(4)                         /*!< the duration time of transfer state is 5 CTCLK */
-#define TSI_TRANSFER_6CTCLK     CTL_CTDT(5)                         /*!< the duration time of transfer state is 6 CTCLK */
-#define TSI_TRANSFER_7CTCLK     CTL_CTDT(6)                         /*!< the duration time of transfer state is 7 CTCLK */
-#define TSI_TRANSFER_8CTCLK     CTL_CTDT(7)                         /*!< the duration time of transfer state is 8 CTCLK */
-#define TSI_TRANSFER_9CTCLK     CTL_CTDT(8)                         /*!< the duration time of transfer state is 9 CTCLK */
-#define TSI_TRANSFER_10CTCLK    CTL_CTDT(9)                         /*!< the duration time of transfer state is 10 CTCLK */
-#define TSI_TRANSFER_11CTCLK    CTL_CTDT(10)                        /*!< the duration time of transfer state is 11 CTCLK */
-#define TSI_TRANSFER_12CTCLK    CTL_CTDT(11)                        /*!< the duration time of transfer state is 12 CTCLK */
-#define TSI_TRANSFER_13CTCLK    CTL_CTDT(12)                        /*!< the duration time of transfer state is 13 CTCLK */
-#define TSI_TRANSFER_14CTCLK    CTL_CTDT(13)                        /*!< the duration time of transfer state is 14 CTCLK */
-#define TSI_TRANSFER_15CTCLK    CTL_CTDT(14)                        /*!< the duration time of transfer state is 15 CTCLK */
-#define TSI_TRANSFER_16CTCLK    CTL_CTDT(15)                        /*!< the duration time of transfer state is 16 CTCLK */
-
-/* charge state duration time */
-#define CTL_CDT(regval)         (BITS(28,31) & ((regval) << 28U))   /*!< charge state duration time */
-#define TSI_CHARGE_1CTCLK       CTL_CDT(0)                          /*!< the duration time of charge state is 1 CTCLK */
-#define TSI_CHARGE_2CTCLK       CTL_CDT(1)                          /*!< the duration time of charge state is 2 CTCLK */
-#define TSI_CHARGE_3CTCLK       CTL_CDT(2)                          /*!< the duration time of charge state is 3 CTCLK */
-#define TSI_CHARGE_4CTCLK       CTL_CDT(3)                          /*!< the duration time of charge state is 4 CTCLK */
-#define TSI_CHARGE_5CTCLK       CTL_CDT(4)                          /*!< the duration time of charge state is 5 CTCLK */
-#define TSI_CHARGE_6CTCLK       CTL_CDT(5)                          /*!< the duration time of charge state is 6 CTCLK */
-#define TSI_CHARGE_7CTCLK       CTL_CDT(6)                          /*!< the duration time of charge state is 7 CTCLK */
-#define TSI_CHARGE_8CTCLK       CTL_CDT(7)                          /*!< the duration time of charge state is 8 CTCLK */
-#define TSI_CHARGE_9CTCLK       CTL_CDT(8)                          /*!< the duration time of charge state is 9 CTCLK */
-#define TSI_CHARGE_10CTCLK      CTL_CDT(9)                          /*!< the duration time of charge state is 10 CTCLK */
-#define TSI_CHARGE_11CTCLK      CTL_CDT(10)                         /*!< the duration time of charge state is 11 CTCLK */
-#define TSI_CHARGE_12CTCLK      CTL_CDT(11)                         /*!< the duration time of charge state is 12 CTCLK */
-#define TSI_CHARGE_13CTCLK      CTL_CDT(12)                         /*!< the duration time of charge state is 13 CTCLK */
-#define TSI_CHARGE_14CTCLK      CTL_CDT(13)                         /*!< the duration time of charge state is 14 CTCLK */
-#define TSI_CHARGE_15CTCLK      CTL_CDT(14)                         /*!< the duration time of charge state is 15 CTCLK */
-#define TSI_CHARGE_16CTCLK      CTL_CDT(15)                         /*!< the duration time of charge state is 16 CTCLK */
-
-/* max cycle number of a sequence */
-#define CTL_MCN(regval)         (BITS(5,7) & ((regval) << 5U))      /*!< max cycle number of a sequence */
-#define TSI_MAXNUM255           CTL_MCN(0)                          /*!< the max cycle number of a sequence is 255 */
-#define TSI_MAXNUM511           CTL_MCN(1)                          /*!< the max cycle number of a sequence is 511 */
-#define TSI_MAXNUM1023          CTL_MCN(2)                          /*!< the max cycle number of a sequence is 1023 */
-#define TSI_MAXNUM2047          CTL_MCN(3)                          /*!< the max cycle number of a sequence is 2047 */
-#define TSI_MAXNUM4095          CTL_MCN(4)                          /*!< the max cycle number of a sequence is 4095 */
-#define TSI_MAXNUM8191          CTL_MCN(5)                          /*!< the max cycle number of a sequence is 8191 */
-#define TSI_MAXNUM16383         CTL_MCN(6)                          /*!< the max cycle number of a sequence is 16383 */
-
-/* ECCLK clock division factor */
-#define TSI_EXTEND_DIV1         ((uint32_t)0x00000000U)             /*!< fECCLK = fHCLK */
-#define TSI_EXTEND_DIV2         ((uint32_t)0x00000001U)             /*!< fECCLK = fHCLK/2 */
-
-/* Extend Charge State Maximum Duration Time */
-#define TSI_EXTENDMAX(regval)   (BITS(17,23) & ((regval) << 17U))   /* value range 1...128,extend charge state maximum duration time */
-
-/* hardware trigger mode */
-#define TSI_FALLING_TRIGGER     ((uint32_t)0x00000000U)             /*!< falling edge trigger TSI charge transfer sequence */
-#define TSI_RISING_TRIGGER      ((uint32_t)0x00000001U)             /*!< rising edge trigger TSI charge transfer sequence */
-
-/* pin mode */
-#define TSI_OUTPUT_LOW          ((uint32_t)0x00000000U)             /*!< TSI pin will output low when IDLE */
-#define TSI_INPUT_FLOATING      ((uint32_t)0x00000001U)             /*!< TSI pin will keep input_floating when IDLE */
-
-/* interrupt enable bits */
-#define TSI_INT_CTCF            TSI_INTEN_CTCFIE                    /*!< charge transfer complete flag interrupt enable */
-#define TSI_INTEN_MNERR         TSI_INTEN_MNERRIE                   /*!< max cycle number error interrupt enable */
-
-/* interrupt flag bits */
-#define TSI_INT_FLAG_CTC        TSI_INTF_CTCF                       /*!< charge transfer complete flag */
-#define TSI_INT_FLAG_MNERR      TSI_INTF_MNERR                      /*!< max cycle number error */
-
-/* function declarations */
-/*  initialization functions */
-/* reset TSI peripheral */
-void tsi_deinit(void);
-/* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */
-void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number);
-/* enable TSI module */
-void tsi_enable(void);
-/* disable TSI module */
-void tsi_disable(void);
-/* enable sample pin */
-void tsi_sample_pin_enable(uint32_t sample);
-/* disable sample pin */
-void tsi_sample_pin_disable(uint32_t sample);
-/* enable channel pin */
-void tsi_channel_pin_enable(uint32_t channel);
-/* disable channel pin */
-void tsi_channel_pin_disable(uint32_t channel);
-
-/* function configuration */
-/* configure TSI triggering by software */
-void tsi_sofeware_mode_config(void);
-/* start a charge-transfer sequence when TSI is in software trigger mode */
-void tsi_software_start(void);
-/* stop a charge-transfer sequence when TSI is in software trigger mode */
-void tsi_software_stop(void);
-/* configure TSI triggering by hardware */
-void tsi_hardware_mode_config(uint8_t trigger_edge);
-/* configure TSI pin mode when charge-transfer sequence is IDLE */
-void tsi_pin_mode_config(uint8_t pin_mode);
-/* configure extend charge state */
-void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration);
-/* configure charge plus and transfer plus */
-void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration);
-/* configure the max cycle number of a charge-transfer sequence */
-void tsi_max_number_config(uint32_t max_number);
-/* switch on hysteresis pin */
-void tsi_hysteresis_on(uint32_t group_pin);
-/* switch off hysteresis pin */
-void tsi_hysteresis_off(uint32_t group_pin);
-/* switch on analog pin */
-void tsi_analog_on(uint32_t group_pin);
-/* switch off analog pin */
-void tsi_analog_off(uint32_t group_pin);
-
-/* interrupt & flag functions */
-/* enable TSI interrupt */
-void tsi_interrupt_enable(uint32_t source);
-/* disable TSI interrupt */
-void tsi_interrupt_disable(uint32_t source);
-/* clear TSI interrupt flag */
-void tsi_interrupt_flag_clear(uint32_t flag);
-/* get TSI interrupt flag */
-FlagStatus tsi_interrupt_flag_get(uint32_t status);
-
-/* enbale group */
-void tsi_group_enable(uint32_t group);
-/* disbale group */
-void tsi_group_disable(uint32_t group);
-/* get group complete status */
-FlagStatus tsi_group_status_get(uint32_t group);
-/* get the cycle number for group0 as soon as a charge-transfer sequence completes */
-uint16_t tsi_group0_cycle_get(void);
-/* get the cycle number for group1 as soon as a charge-transfer sequence completes */
-uint16_t tsi_group1_cycle_get(void);
-/* get the cycle number for group2 as soon as a charge-transfer sequence completes */
-uint16_t tsi_group2_cycle_get(void);
-/* get the cycle number for group3 as soon as a charge-transfer sequence completes */
-uint16_t tsi_group3_cycle_get(void);
-/* get the cycle number for group4 as soon as a charge-transfer sequence completes */
-uint16_t tsi_group4_cycle_get(void);
-/* get the cycle number for group5 as soon as a charge-transfer sequence completes */
-uint16_t tsi_group5_cycle_get(void);
-
-#endif /* GD32F1X0_TSI_H */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_can.c

@@ -1,1036 +0,0 @@
-/*!
-    \file  gd32f1x0_can.c
-    \brief CAN driver
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifdef GD32F170_190
-
-#include "gd32f1x0_can.h"
-
-#define CAN_ERROR_HANDLE(s)     do{}while(1)
-
-/*!
-    \brief      deinitialize CAN 
-    \param[in]  can_periph
-    \arg        CANx(x=0,1) 
-    \param[out] none
-    \retval     none
-*/
-void can_deinit(uint32_t can_periph)
-{
-    if(CAN0 == can_periph){
-        rcu_periph_reset_enable(RCU_CAN0RST);
-        rcu_periph_reset_disable(RCU_CAN0RST);
-    }else{
-        rcu_periph_reset_enable(RCU_CAN1RST);
-        rcu_periph_reset_disable(RCU_CAN1RST);
-    }
-}
-
-/*!
-    \brief      initialize CAN parameter struct with a default value
-    \param[in]  type: the type of CAN parameter struct  
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_INIT_STRUCT: the CAN initial struct
-      \arg        CAN_FILTER_STRUCT: the CAN filter struct
-      \arg        CAN_TX_MESSAGE_STRUCT: the CAN TX message struct
-      \arg        CAN_RX_MESSAGE_STRUCT: the CAN RX message struct
-    \param[in]  p_struct: the pointer of the specific struct 
-    \param[out] none
-    \retval     none
-*/
-void can_struct_para_init(can_struct_type_enum type, void* p_struct)
-{
-    uint8_t i;
-    
-    /* get type of the struct */
-    switch(type){
-        /* used for can_init() */
-        case CAN_INIT_STRUCT:
-            ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE;
-            ((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE;
-            ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE;
-            ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; 
-            ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; 
-            ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ;
-            ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ;
-            ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ;
-            ((can_parameter_struct*)p_struct)->time_triggered = DISABLE;
-            ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE;
-            ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE;
-            
-            break;
-        /* used for can_filter_init() */
-        case CAN_FILTER_STRUCT:
-            ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT;
-            ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE;
-            ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0;
-            ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U;
-            ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U;
-            ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U;
-            ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U;
-            ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK;
-            ((can_filter_parameter_struct*)p_struct)->filter_number = 0U;
-
-            break;
-        /* used for can_message_transmit() */
-        case CAN_TX_MESSAGE_STRUCT:
-            for(i = 0U; i < 8U; i++){
-                ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U;
-            }
-            
-            ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u;
-            ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U;
-            ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD;
-            ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA;
-            ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U;
-            
-            break;
-        /* used for can_message_receive() */
-        case CAN_RX_MESSAGE_STRUCT:
-            for(i = 0U; i < 8U; i++){
-                ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U;
-            }
-            
-            ((can_receive_message_struct*)p_struct)->rx_dlen = 0U;
-            ((can_receive_message_struct*)p_struct)->rx_efid = 0U;
-            ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD;
-            ((can_receive_message_struct*)p_struct)->rx_fi = 0U;
-            ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA;
-            ((can_receive_message_struct*)p_struct)->rx_sfid = 0U;
-            
-            break;
-
-        default:
-            CAN_ERROR_HANDLE("parameter is invalid \r\n");
-    }
-}
-
-/*!
-    \brief      initialize CAN
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[in]  can_parameter_init: parameters for CAN initializtion
-      \arg        working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE
-      \arg        resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4)
-      \arg        time_segment_1: CAN_BT_BS1_xTQ(1..16)
-      \arg        time_segment_2: CAN_BT_BS2_xTQ(1..8)
-      \arg        time_triggered: ENABLE or DISABLE
-      \arg        auto_bus_off_recovery: ENABLE or DISABLE
-      \arg        auto_wake_up: ENABLE or DISABLE
-      \arg        no_auto_retrans: ENABLE or DISABLE
-      \arg        rec_fifo_overwrite: ENABLE or DISABLE
-      \arg        trans_fifo_order: ENABLE or DISABLE
-      \arg        prescaler: 0x0001 - 0x0400
-    \param[out] none
-    \retval     ErrStatus: SUCCESS or ERROR
-*/
-ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init)
-{
-    uint32_t timeout = CAN_TIMEOUT;
-    ErrStatus flag = ERROR;
-    
-    /* disable sleep mode */
-    CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
-    /* enable initialize mode */
-    CAN_CTL(can_periph) |= CAN_CTL_IWMOD;
-    /* wait ACK */
-    while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
-        timeout--;
-    }
-    /* check initialize working success */
-    if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
-        flag = ERROR;
-    }else{
-        /* set the bit timing register */
-        CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \
-                              BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \
-                              BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
-                              BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
-                              BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
-        /* time trigger communication mode */
-        if(ENABLE == can_parameter_init->time_triggered){
-            CAN_CTL(can_periph) |= CAN_CTL_TTC;
-        }else{
-            CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
-        }
-        /* automatic bus-off managment */
-        if(ENABLE == can_parameter_init->auto_bus_off_recovery){
-            CAN_CTL(can_periph) |= CAN_CTL_ABOR;
-        }else{
-            CAN_CTL(can_periph) &= ~CAN_CTL_ABOR;
-        }
-        /* automatic wakeup mode */
-        if(ENABLE == can_parameter_init->auto_wake_up){
-            CAN_CTL(can_periph) |= CAN_CTL_AWU;
-        }else{
-            CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
-        }
-        /* automatic retransmission mode disable*/
-        if(ENABLE == can_parameter_init->no_auto_retrans){
-            CAN_CTL(can_periph) |= CAN_CTL_ARD;
-        }else{
-            CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
-        }
-        /* receive fifo overwrite mode */        
-        if(ENABLE == can_parameter_init->rec_fifo_overwrite){
-            CAN_CTL(can_periph) |= CAN_CTL_RFOD;
-        }else{
-            CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
-        } 
-        /* transmit fifo order */
-        if(ENABLE == can_parameter_init->trans_fifo_order){
-            CAN_CTL(can_periph) |= CAN_CTL_TFO;
-        }else{
-            CAN_CTL(can_periph) &= ~CAN_CTL_TFO;
-        }  
-        /* disable initialize mode */
-        CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD;
-        timeout = CAN_TIMEOUT;
-        /* wait the ACK */
-        while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
-            timeout--;
-        }
-        /* check exit initialize mode */
-        if(0U != timeout){
-            flag = SUCCESS;
-        }
-    }
-    return flag;
-}
-
-/*!
-    \brief      initialize CAN filter 
-    \param[in]  can_filter_parameter_init: struct for CAN filter initialization
-      \arg        filter_list_high: 0x0000 - 0xFFFF
-      \arg        filter_list_low: 0x0000 - 0xFFFF
-      \arg        filter_mask_high: 0x0000 - 0xFFFF
-      \arg        filter_mask_low: 0x0000 - 0xFFFF
-      \arg        filter_fifo_number: CAN_FIFO0, CAN_FIFO1 
-      \arg        filter_number: 0 - 27
-      \arg        filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST
-      \arg        filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT 
-      \arg        filter_enable: ENABLE or DISABLE
-    \param[out] none
-    \retval     none
-*/
-void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
-{
-    uint32_t val = 0U;
-    
-    val = ((uint32_t)1) << (can_filter_parameter_init->filter_number);
-    /* filter lock disable */
-    CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
-    /* disable filter */
-    CAN_FW(CAN0) &= ~(uint32_t)val;
-    /* filter 16 bits */
-    if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){
-        /* set filter 16 bits */
-        CAN_FSCFG(CAN0) &= ~(uint32_t)val;
-        /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */
-        CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
-                                FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \
-                                FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
-        /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */
-        CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
-                                FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \
-                                FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS);
-    }
-    /* filter 32 bits */
-    if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){
-        /* set filter 32 bits */
-        CAN_FSCFG(CAN0) |= (uint32_t)val;
-        /* 32 bits list or first 32 bits list */
-        CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
-                                FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) |
-                                FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
-        /* 32 bits mask or second 32 bits list */
-        CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
-                                FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) |
-                                FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS);
-    }
-    /* filter mode */
-    if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){
-        /* mask mode */
-        CAN_FMCFG(CAN0) &= ~(uint32_t)val;
-    }else{
-        /* list mode */
-        CAN_FMCFG(CAN0) |= (uint32_t)val;
-    }
-    /* filter FIFO */
-    if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){
-        /* FIFO0 */
-        CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
-    }else{
-        /* FIFO1 */
-        CAN_FAFIFO(CAN0) |= (uint32_t)val;
-    }
-    /* filter working */
-    if(ENABLE == can_filter_parameter_init->filter_enable){
-        
-        CAN_FW(CAN0) |= (uint32_t)val;
-    }
-    /* filter lock enable */
-    CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
-}
-
-/*!
-    \brief      set CAN1 fliter start bank number
-    \param[in]  start_bank: CAN1 start bank number
-                only one parameter can be selected which is shown as below:
-      \arg        (1..27)
-    \param[out] none
-    \retval     none
-*/
-void can1_filter_start_bank(uint8_t start_bank)
-{
-    /* filter lock disable */
-    CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
-    /* set CAN1 filter start number */
-    CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F;
-    CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank);
-    /* filter lock enaable */
-    CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
-}
-
-/*!
-    \brief      enable CAN debug freeze
-    \param[in]  can_periph
-      \arg        CANx(x=0,1) 
-    \param[out] none
-    \retval     none
-*/
-void can_debug_freeze_enable(uint32_t can_periph)
-{
-    /* set DFZ bit */
-    CAN_CTL(can_periph) |= CAN_CTL_DFZ;
-
-    if(CAN0 == can_periph){
-        dbg_periph_enable(DBG_CAN0_HOLD);
-    }else{
-        dbg_periph_enable(DBG_CAN1_HOLD);
-    }
-}
-
-/*!
-    \brief      disable CAN debug freeze
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void can_debug_freeze_disable(uint32_t can_periph)
-{
-    CAN_CTL(can_periph) &= ~CAN_CTL_DFZ;
-
-    if(CAN0 == can_periph){
-        dbg_periph_disable(DBG_CAN0_HOLD);
-    }else{
-        dbg_periph_disable(DBG_CAN1_HOLD);
-    }
-}
-
-/*!
-    \brief      enable CAN time trigger mode
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void can_time_trigger_mode_enable(uint32_t can_periph)
-{
-    uint8_t mailbox_number;
-    
-    /* enable the tcc mode */
-    CAN_CTL(can_periph) |= CAN_CTL_TTC;
-    /* enable time stamp */
-    for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){
-        CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN;
-    }
-}
-
-/*!
-    \brief      disable CAN time trigger mode
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void can_time_trigger_mode_disable(uint32_t can_periph)
-{
-    uint8_t mailbox_number; 
-    
-    /* disable the TCC mode */
-    CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
-    /* reset TSEN bits */
-    for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){
-        CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN;
-    }
-}
-
-/*!
-    \brief       transmit CAN message
-    \param[in]  can_periph
-      \arg        CANx(x=0,1) 
-    \param[in]  transmit_message: struct for CAN transmit message
-      \arg        tx_sfid: 0x00000000 - 0x000007FF
-      \arg        tx_efid: 0x00000000 - 0x1FFFFFFF
-      \arg        tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
-      \arg        tx_ft: CAN_FT_DATA, CAN_FT_REMOTE
-      \arg        tx_dlenc: 0 - 8
-      \arg        tx_data[]: 0x00 - 0xFF
-    \param[out] none
-    \retval     mailbox_number
-*/
-uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message)
-{
-    uint8_t mailbox_number = CAN_MAILBOX0;
-
-    /* select one empty mailbox */
-    if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){
-        mailbox_number = CAN_MAILBOX0;
-    }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){
-        mailbox_number = CAN_MAILBOX1;
-    }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){
-        mailbox_number = CAN_MAILBOX2;
-    }else{
-        mailbox_number = CAN_NOMAILBOX;
-    }
-    if(CAN_NOMAILBOX == mailbox_number){
-        return CAN_NOMAILBOX;
-    }
-    
-    CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN;
-    if(CAN_FF_STANDARD == transmit_message->tx_ff){
-        /* set transmit mailbox standard identifier */
-        CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \
-                                                transmit_message->tx_ft);
-    }else{
-        /* set transmit mailbox extended identifier */
-        CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \
-                                                transmit_message->tx_ff | \
-                                                transmit_message->tx_ft);
-    }
-    /* set the data length */
-    CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC);
-    CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
-    /* set the data */
-    CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \
-                                              TMDATA0_DB2(transmit_message->tx_data[2]) | \
-                                              TMDATA0_DB1(transmit_message->tx_data[1]) | \
-                                              TMDATA0_DB0(transmit_message->tx_data[0]);
-    CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \
-                                              TMDATA1_DB6(transmit_message->tx_data[6]) | \
-                                              TMDATA1_DB5(transmit_message->tx_data[5]) | \
-                                              TMDATA1_DB4(transmit_message->tx_data[4]);
-    /* enable transmission */
-    CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN;
-
-    return mailbox_number;
-}
-
-/*!
-    \brief      get CAN transmit state 
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[in]  mailbox_number
-      \arg        CAN_MAILBOX(x=0,1,2)
-    \param[out] none
-    \retval     can_transmit_state_enum
-*/
-can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number)
-{
-    can_transmit_state_enum state = CAN_TRANSMIT_FAILED;
-    uint32_t val = 0U;
-    
-    /* check selected mailbox state */    
-    switch(mailbox_number){
-    /* mailbox0 */
-    case CAN_MAILBOX0:
-        val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0);
-        break;
-    /* mailbox1 */
-    case CAN_MAILBOX1:
-        val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1);
-        break;
-    /* mailbox2 */
-    case CAN_MAILBOX2:
-        val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2);
-        break;
-    default:
-        val = CAN_TRANSMIT_FAILED;
-        break;
-    }
-    
-    switch(val){
-        /* transmit pending */
-    case (CAN_STATE_PENDING): 
-        state = CAN_TRANSMIT_PENDING;
-        break;
-        /* mailbox0 transmit succeeded */
-    case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0):
-        state = CAN_TRANSMIT_OK;
-        break;
-        /* mailbox1 transmit succeeded */
-    case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1):
-        state = CAN_TRANSMIT_OK;
-        break;
-        /* mailbox2 transmit succeeded */
-    case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2):
-        state = CAN_TRANSMIT_OK;
-        break;
-        /* transmit failed */
-    default: 
-        state = CAN_TRANSMIT_FAILED;
-        break;
-    }
-    return state;
-}
-
-/*!
-    \brief      stop CAN transmission
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[in]  mailbox_number
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_MAILBOXx(x=0,1,2)
-    \param[out] none
-    \retval     none
-*/
-void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
-{
-    if(CAN_MAILBOX0 == mailbox_number){
-        CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
-        while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){
-        }
-    }else if(CAN_MAILBOX1 == mailbox_number){
-        CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
-        while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){
-        }
-    }else if(CAN_MAILBOX2 == mailbox_number){
-        CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
-        while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){
-        }
-    }else{
-        /* illegal parameters */
-    }
-}
-
-/*!
-    \brief      CAN receive message
-    \param[in]  can_periph
-      \arg        CANx(x=0,1) 
-    \param[in]  fifo_number
-      \arg        CAN_FIFOx(x=0,1)
-    \param[out] receive_message: struct for CAN receive message
-      \arg        rx_sfid: 0x00000000 - 0x000007FF
-      \arg        rx_efid: 0x00000000 - 0x1FFFFFFF
-      \arg        rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
-      \arg        rx_ft: CAN_FT_DATA, CAN_FT_REMOTE
-      \arg        rx_dlenc: 0 - 8
-      \arg        rx_data[]: 0x00 - 0xFF
-      \arg        rx_fi: 0 - 27
-    \retval     none
-*/
-void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message)
-{
-    /* get the frame format */
-    receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number));
-    if(CAN_FF_STANDARD == receive_message->rx_ff){
-        /* get standard identifier */
-        receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number)));
-    }else{
-        /* get extended identifier */
-        receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number)));
-    }
-    
-    /* get frame type */
-    receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number));        
-    /* filtering index */
-    receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number)));
-    /* get recevie data length */
-    receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number)));
-    /* filtering index */
-    receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number)));     
-    
-    /* receive data */
-    receive_message->rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number)));
-    receive_message->rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number)));
-    receive_message->rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number)));
-    receive_message->rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number)));
-    receive_message->rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number)));
-    receive_message->rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number)));
-    receive_message->rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number)));
-    receive_message->rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number)));
-    
-    /* release FIFO */
-    if(CAN_FIFO0 == fifo_number){
-        CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
-    }else{
-        CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
-    }
-}
-
-/*!
-    \brief      release FIFO0
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[in]  fifo_number
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_FIFOx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void can_fifo_release(uint32_t can_periph, uint8_t fifo_number)
-{
-    if(CAN_FIFO0 == fifo_number){
-        CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
-    }else if(CAN_FIFO1 == fifo_number){
-        CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
-    }else{
-        /* illegal parameters */
-    }
-}
-
-/*!
-    \brief      CAN receive message length
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[in]  fifo_number
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_FIFOx(x=0,1) 
-    \param[out] none
-    \retval     message length
-*/
-uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
-{
-    uint8_t val = 0U;
-    
-    if(CAN_FIFO0 == fifo_number){
-        val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK);
-    }else if(CAN_FIFO1 == fifo_number){
-        val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK);
-    }else{
-        /* illegal parameters */
-    }
-    return val;
-}
-
-/*!
-    \brief      set CAN working mode
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[in]  can_working_mode
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_MODE_INITIALIZE
-      \arg        CAN_MODE_NORMAL
-      \arg        CAN_MODE_SLEEP
-    \param[out] none
-    \retval     ErrStatus: SUCCESS or ERROR
-*/
-ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
-{
-    ErrStatus flag = ERROR;
-    /* timeout for IWS or also for SLPWS bits */
-    uint32_t timeout = CAN_TIMEOUT; 
-    
-    if(CAN_MODE_INITIALIZE == working_mode){
-        /* disable sleep mode */
-        CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD);
-        /* set initialize mode */
-        CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD;
-        /* wait the acknowledge */
-        while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
-            timeout--;
-        }
-        if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
-            flag = ERROR;
-        }else{
-            flag = SUCCESS;
-        }
-    }else if(CAN_MODE_NORMAL == working_mode){
-        /* enter normal mode */
-        CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD);
-        /* wait the acknowledge */
-        while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){
-            timeout--;
-        }
-        if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){
-            flag = ERROR;
-        }else{
-            flag = SUCCESS;
-        }
-    }else if(CAN_MODE_SLEEP == working_mode){
-        /* disable initialize mode */
-        CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD);
-        /* set sleep mode */
-        CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD;
-        /* wait the acknowledge */
-        while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){
-            timeout--;
-        }
-        if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
-            flag = ERROR;
-        }else{
-            flag = SUCCESS;
-        }
-    }else{
-        flag = ERROR;
-    }
-    return flag;
-}
-
-/*!
-    \brief      wake up CAN
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[out] none
-    \retval     ErrStatus: SUCCESS or ERROR
-*/
-ErrStatus can_wakeup(uint32_t can_periph)
-{
-    ErrStatus flag = ERROR;
-    uint32_t timeout = CAN_TIMEOUT;
-    
-    /* wakeup */
-    CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
-    
-    while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){
-        timeout--;
-    }
-    /* check state */
-    if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
-        flag = ERROR;
-    }else{
-        flag = SUCCESS;
-    }
-    return flag;
-}
-
-/*!
-    \brief      get CAN error type
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[out] none
-    \retval     can_error_enum
-      \arg        CAN_ERROR_NONE: no error
-      \arg        CAN_ERROR_FILL: fill error
-      \arg        CAN_ERROR_FORMATE: format error
-      \arg        CAN_ERROR_ACK: ACK error
-      \arg        CAN_ERROR_BITRECESSIVE: bit recessive
-      \arg        CAN_ERROR_BITDOMINANTER: bit dominant error
-      \arg        CAN_ERROR_CRC: CRC error
-      \arg        CAN_ERROR_SOFTWARECFG: software configure
-*/
-can_error_enum can_error_get(uint32_t can_periph)
-{
-    can_error_enum error;
-    error = CAN_ERROR_NONE;
-    
-    /* get error type */
-    error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph)));
-    return error;
-}
-
-/*!
-    \brief      get CAN receive error number
-    \param[in]  can_periph
-      \arg        CANx(x=0,1) 
-    \param[out] none
-    \retval     error number
-*/
-uint8_t can_receive_error_number_get(uint32_t can_periph)
-{
-    uint8_t val;
-    
-    /* get error count */
-    val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph)));
-    return val;
-}
-
-/*!
-    \brief      get CAN transmit error number
-    \param[in]  can_periph
-      \arg        CANx(x=0,1) 
-    \param[out] none
-    \retval     error number
-*/
-uint8_t can_transmit_error_number_get(uint32_t can_periph)
-{
-    uint8_t val;
-    
-    val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph)));
-    return val;
-}
-
-/*!
-    \brief      enable CAN interrupt 
-    \param[in]  can_periph
-      \arg        CANx(x=0,1) 
-    \param[in]  interrupt 
-                one or more parameters can be selected which are shown as below:
-      \arg        CAN_INT_TME: transmit mailbox empty interrupt enable
-      \arg        CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
-      \arg        CAN_INT_RFF0: receive FIFO0 full interrupt enable
-      \arg        CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
-      \arg        CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
-      \arg        CAN_INT_RFF1: receive FIFO1 full interrupt enable
-      \arg        CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
-      \arg        CAN_INT_WERR: warning error interrupt enable
-      \arg        CAN_INT_PERR: passive error interrupt enable
-      \arg        CAN_INT_BO: bus-off interrupt enable
-      \arg        CAN_INT_ERRN: error number interrupt enable
-      \arg        CAN_INT_ERR: error interrupt enable
-      \arg        CAN_INT_WU: wakeup interrupt enable
-      \arg        CAN_INT_SLPW: sleep working interrupt enable
-    \param[out] none
-    \retval     none
-*/
-void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
-{
-    CAN_INTEN(can_periph) |= interrupt;
-}
-
-/*!
-    \brief      disable CAN interrupt 
-    \param[in]  can_periph
-      \arg        CANx(x=0,1) 
-    \param[in]  interrupt
-                one or more parameters can be selected which are shown as below:
-      \arg        CAN_INT_TME: transmit mailbox empty interrupt enable
-      \arg        CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
-      \arg        CAN_INT_RFF0: receive FIFO0 full interrupt enable
-      \arg        CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
-      \arg        CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
-      \arg        CAN_INT_RFF1: receive FIFO1 full interrupt enable
-      \arg        CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
-      \arg        CAN_INT_WERR: warning error interrupt enable
-      \arg        CAN_INT_PERR: passive error interrupt enable
-      \arg        CAN_INT_BO: bus-off interrupt enable
-      \arg        CAN_INT_ERRN: error number interrupt enable
-      \arg        CAN_INT_ERR: error interrupt enable
-      \arg        CAN_INT_WU: wakeup interrupt enable
-      \arg        CAN_INT_SLPW: sleep working interrupt enable
-    \param[out] none
-    \retval     none
-*/
-void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
-{
-    CAN_INTEN(can_periph) &= ~interrupt;
-}
-
-/*!
-    \brief      get CAN flag state
-    \param[in]  can_periph
-      \arg        CANx(x=0,1) 
-    \param[in]  flag: CAN flags, refer to can_flag_enum
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_FLAG_MTE2: mailbox 2 transmit error
-      \arg        CAN_FLAG_MTE1: mailbox 1 transmit error
-      \arg        CAN_FLAG_MTE0: mailbox 0 transmit error
-      \arg        CAN_FLAG_MTF2: mailbox 2 transmit finished
-      \arg        CAN_FLAG_MTF1: mailbox 1 transmit finished
-      \arg        CAN_FLAG_MTF0: mailbox 0 transmit finished
-      \arg        CAN_FLAG_RFO0: receive FIFO0 overfull
-      \arg        CAN_FLAG_RFF0: receive FIFO0 full
-      \arg        CAN_FLAG_RFO1: receive FIFO1 overfull
-      \arg        CAN_FLAG_RFF1: receive FIFO1 full
-      \arg        CAN_FLAG_BOERR: bus-off error
-      \arg        CAN_FLAG_PERR: passive error
-      \arg        CAN_FLAG_WERR: warning error
-    \param[out] none
-    \retval     FlagStatus: SET or RESET
-*/
-FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
-{  
-    /* get flag and interrupt enable state */
-    if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){
-        return SET;
-    }else{
-        return RESET;
-    }
-}
-
-/*!
-    \brief      clear CAN flag state
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[in]  flag: CAN flags, refer to can_flag_enum
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_FLAG_MTE2: mailbox 2 transmit error
-      \arg        CAN_FLAG_MTE1: mailbox 1 transmit error
-      \arg        CAN_FLAG_MTE0: mailbox 0 transmit error
-      \arg        CAN_FLAG_MTF2: mailbox 2 transmit finished
-      \arg        CAN_FLAG_MTF1: mailbox 1 transmit finished
-      \arg        CAN_FLAG_MTF0: mailbox 0 transmit finished
-      \arg        CAN_FLAG_RFO0: receive FIFO0 overfull
-      \arg        CAN_FLAG_RFF0: receive FIFO0 full
-      \arg        CAN_FLAG_RFO1: receive FIFO1 overfull
-      \arg        CAN_FLAG_RFF1: receive FIFO1 full
-    \param[out] none
-    \retval     none
-*/
-void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
-{
-    CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag));
-}
-
-/*!
-    \brief      get CAN interrupt flag state
-    \param[in]  can_periph
-      \arg        CANx(x=0,1) 
-    \param[in]  flag: CAN interrupt flags, refer to can_interrupt_flag_enum
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
-      \arg        CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
-      \arg        CAN_INT_FLAG_ERRIF: error interrupt flag
-      \arg        CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
-      \arg        CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
-      \arg        CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
-      \arg        CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
-      \arg        CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
-      \arg        CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
-      \arg        CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
-    \param[out] none
-    \retval     FlagStatus: SET or RESET
-*/
-FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag)
-{  
-    uint32_t ret1 = RESET;
-    uint32_t ret2 = RESET;
-    
-    /* get the staus of interrupt flag */
-    ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag));
-    /* get the staus of interrupt enale bit */
-    ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag));
-    if(ret1 && ret2){
-        return SET;
-    }else{
-        return RESET;
-    }
-}
-
-/*!
-    \brief      clear CAN interrupt flag state
-    \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[in]  flag: CAN interrupt flags, refer to can_interrupt_flag_enum
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
-      \arg        CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
-      \arg        CAN_INT_FLAG_ERRIF: error interrupt flag
-      \arg        CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
-      \arg        CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
-      \arg        CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
-      \arg        CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
-      \arg        CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
-      \arg        CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
-      \arg        CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
-    \param[out] none
-    \retval     none
-*/
-void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag)
-{
-    if (flag == CAN_INT_FLAG_RFO1){
-        CAN_REG_VALS(can_periph, flag) &= ~BIT(CAN_BIT_POS0(flag));
-    } else {
-        CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag));
-    }
-}
-
-/*!
-    \brief      enable CAN phy 
-     \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void can_phy_enable(uint32_t can_periph)
-{
-    CAN_PHYCTL(can_periph) |= CAN_PHYCTL_PHYEN;
-}
-
-/*!
-    \brief      disable CAN phy 
-     \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void can_phy_disable(uint32_t can_periph)
-{
-    CAN_PHYCTL(can_periph) &= ~CAN_PHYCTL_PHYEN;
-}
-
-/*!
-    \brief      set CAN phy mode
-     \param[in]  can_periph
-      \arg        CANx(x=0,1)
-    \param[in]  can_phy_mode
-                only one parameter can be selected which is shown as below:
-      \arg        CAN_PHYMODE_LOW_SLOPE
-      \arg        CAN_PHYMODE_MIDDLE_SLOPE
-      \arg        CAN_PHYMODE_HIGH_SLOPE
-      \arg        CAN_PHYMODE_HIGH_SPEED
-    \param[out] none
-    \retval     none
-*/
-void can_phy_mode(uint32_t can_periph, uint32_t phy_mode)
-{
-    CAN_PHYCTL(can_periph) &= (~CAN_PHYCTL_POMODE_MASK);
-    switch(phy_mode){
-    case CAN_PHYCTL_POMODE_0:
-        /*!< CAN PHY low slope mode */
-        CAN_PHYCTL(can_periph) |= CAN_PHYCTL_POMODE_0;
-        break;
-    case CAN_PHYCTL_POMODE_1:
-        /*!< CAN PHY middle slope mode */
-        CAN_PHYCTL(can_periph) |= CAN_PHYCTL_POMODE_1;
-        break;
-    case CAN_PHYCTL_POMODE_2:
-        /*!< CAN PHY high slope mode */
-        CAN_PHYCTL(can_periph) |= CAN_PHYCTL_POMODE_2;
-        break;
-    case CAN_PHYCTL_POMODE_3:
-        /*!< CAN PHY high speed mode */
-        CAN_PHYCTL(can_periph) |= CAN_PHYCTL_POMODE_3;
-        break;
-    default:
-        break;
-    }
-}
-
-#endif /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_dac.c

@@ -1,816 +0,0 @@
-/*!
-    \file  gd32f1x0_dac.c
-    \brief DAC driver
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-
-#include "gd32f1x0_dac.h"
-
-/*!
-    \brief      deinit DAC
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac_deinit(void)
-{
-    rcu_periph_reset_enable(RCU_DACRST);
-    rcu_periph_reset_disable(RCU_DACRST);
-}
-
-/*!
-    \brief      enable DAC0
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_enable(void)
-{
-    DAC_CTL |= DAC_CTL_DEN0;
-}
-
-/*!
-    \brief      disable DAC0
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_disable(void)
-{
-    DAC_CTL &= ~DAC_CTL_DEN0;
-}
-
-/*!
-    \brief      enable DAC0 DMA
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_dma_enable(void)
-{
-    DAC_CTL |= DAC_CTL_DDMAEN0;
-}
-
-/*!
-    \brief      disable DAC0 DMA
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_dma_disable(void)
-{
-    DAC_CTL &= ~DAC_CTL_DDMAEN0;
-}
-
-/*!
-    \brief      enable DAC0 output buffer
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_output_buffer_enable(void)
-{
-    DAC_CTL &= ~DAC_CTL_DBOFF0;
-}
-
-/*!
-    \brief      disable DAC0 output buffer
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_output_buffer_disable(void)
-{
-    DAC_CTL |= DAC_CTL_DBOFF0;
-}
-
-/*!
-    \brief      enable DAC0 trigger
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_trigger_enable(void)
-{
-    DAC_CTL |= DAC_CTL_DTEN0;
-}
-
-/*!
-    \brief      disable DAC0 trigger
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_trigger_disable(void)
-{
-    DAC_CTL &= ~DAC_CTL_DTEN0;
-}
-
-/*!
-    \brief      enable DAC0 software trigger
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_software_trigger_enable(void)
-{
-    DAC_SWT |= DAC_SWT_SWTR0;
-}
-
-/*!
-    \brief      disable DAC0 software trigger
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_software_trigger_disable(void)
-{
-    DAC_SWT &= ~DAC_SWT_SWTR0;
-}
-
-/*!
-    \brief      enable DAC0 interrupt(DAC0 DMA underrun interrupt)
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_interrupt_enable(void)
-{
-    DAC_CTL |= DAC_CTL_DDUDRIE0;
-}
-
-/*!
-    \brief      disable DAC0 interrupt(DAC0 DMA underrun interrupt)
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_interrupt_disable(void)
-{
-    DAC_CTL &= ~DAC_CTL_DDUDRIE0;
-}
-
-/*!
-    \brief      set DAC0 tgigger source
-    \param[in]  triggersource: external triggers of DAC
-      \arg        DAC_TRIGGER_T1_TRGO: trigger source is timer1 trgo
-      \arg        DAC_TRIGGER_T2_TRGO: trigger source is timer2 trgo
-      \arg        DAC_TRIGGER_T5_TRGO: trigger source is timer5 trgo
-      \arg        DAC_TRIGGER_T14_TRGO: trigger source is timer14 trgo
-      \arg        DAC_TRIGGER_EXTI_IT9: trigger source is exti interrupt line 9
-      \arg        DAC_TRIGGER_SOFTWARE: trigger source is software
-    \param[out] none
-    \retval     none
-*/
-void dac0_trigger_source_config(uint32_t triggersource)
-{
-    DAC_CTL &= ~DAC_CTL_DTSEL0;
-    DAC_CTL |= triggersource;
-}
-
-/*!
-    \brief      get the last data output value of DAC0
-    \param[in]  none
-    \param[out] none
-    \retval     DAC output data
-*/
-uint16_t dac0_output_value_get(void)
-{
-    uint16_t data = 0U;
-    data = (uint16_t)DAC0_DO;
-    return data;
-}
-
-/*!
-    \brief      get the specified DAC0 flag(DAC0 DMA underrun flag)
-    \param[in]  none
-    \param[out] none
-    \retval     the state of dac bit(SET or RESET)
-*/
-FlagStatus dac0_flag_get(void)
-{
-    /* check the DMA underrun flag */
-    if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR0)){
-        return SET;
-    }else{
-        return RESET;
-    }
-}
-
-/*!
-    \brief      clear the specified DAC0 flag(DAC0 DMA underrun flag)
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_flag_clear(void)
-{
-    DAC_STAT &= ~DAC_STAT_DDUDR0;
-}
-
-/*!
-    \brief      get the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag)
-    \param[in]  none
-    \param[out] none
-    \retval     the state of DAC interrupt flag(SET or RESET)
-*/
-FlagStatus dac0_interrupt_flag_get(void)
-{
-    uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
-    ddudr_flag = (DAC_STAT & DAC_STAT_DDUDR0);
-    ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0;
-    /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
-    if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
-         return SET;
-    }else{
-        return RESET;
-    }
-}
-
-/*!
-    \brief      clear the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag)
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac0_interrupt_flag_clear(void)
-{
-    DAC_CTL &= ~DAC_CTL_DDUDRIE0;
-}
-
-/*!
-    \brief      set DAC0 data holding register value
-    \param[in]  dac_align
-      \arg        DAC_ALIGN_8B_R: data right 8b alignment
-      \arg        DAC_ALIGN_12B_R: data right 12b alignment
-      \arg        DAC_ALIGN_12B_L: data left 12b alignment
-    \param[in]  data: data to be loaded
-    \param[out] none
-    \retval     none
-*/
-void dac0_data_set(uint32_t dac_align, uint16_t data)
-{
-    switch(dac_align){
-        /* data right 12b alignment */
-        case DAC_ALIGN_12B_R:
-            DAC0_R12DH = data;
-            break;
-        /* data left 12b alignment */
-        case DAC_ALIGN_12B_L:
-            DAC0_L12DH = data;
-            break;
-        /* data right 8b alignment */
-        case DAC_ALIGN_8B_R:
-            DAC0_R8DH = data;
-            break;
-        default:
-            break;
-    }
-}
-
-#ifdef GD32F170_190
-/*!
-    \brief      enable DAC
-    \param[in]  dac_periph
-      \arg        DACx(x =0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_enable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL |= DAC_CTL_DEN0;
-    }else{
-        DAC_CTL |= DAC_CTL_DEN1;
-    }
-} 
-
-/*!
-    \brief      disable DAC
-    \param[in]  dac_periph
-      \arg        DACx(x =0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_disable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL &= ~DAC_CTL_DEN0;
-    }else{
-        DAC_CTL &= ~DAC_CTL_DEN1;
-    }
-}
-
-/*!
-    \brief      enable DAC DMA function
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_dma_enable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL |= DAC_CTL_DDMAEN0;
-    }else{
-        DAC_CTL |= DAC_CTL_DDMAEN1;
-    }
-}
-
-/*!
-    \brief      disable DAC DMA function
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_dma_disable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL &= ~DAC_CTL_DDMAEN0;
-    }else{
-        DAC_CTL &= ~DAC_CTL_DDMAEN1;
-    }
-}
-
-/*!
-    \brief      enable DAC output buffer
-    \param[in]  dac_periph
-      \arg        DACx(x =0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_output_buffer_enable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL &= ~DAC_CTL_DBOFF0;
-    }else{
-        DAC_CTL &= ~DAC_CTL_DBOFF1;
-    }
-}
-
-/*!
-    \brief      disable DAC output buffer
-    \param[in]  dac_periph
-      \arg        DACx(x =0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_output_buffer_disable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL |= DAC_CTL_DBOFF0;
-    }else{
-        DAC_CTL |= DAC_CTL_DBOFF1;
-    }
-}
-
-/*!
-    \brief      enable DAC trigger
-    \param[in]  dac_periph
-      \arg        DACx(x =0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_trigger_enable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL |= DAC_CTL_DTEN0;
-    }else{
-        DAC_CTL |= DAC_CTL_DTEN1;
-    }
-}
-
-/*!
-    \brief      disable DAC trigger
-    \param[in]  dac_periph
-      \arg        DACx(x =0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_trigger_disable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL &= ~DAC_CTL_DTEN0;
-    }else{
-        DAC_CTL &= ~DAC_CTL_DTEN1;
-    }
-}
-
-/*!
-    \brief      enable DAC software trigger
-    \param[in]  dac_periph
-      \arg        DACx(x =0,1)
-    \retval     none
-*/
-void dac_software_trigger_enable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_SWT |= DAC_SWT_SWTR0;
-    }else{
-        DAC_SWT |= DAC_SWT_SWTR1;
-    }
-}
-
-/*!
-    \brief      disable DAC software trigger
-    \param[in]  dac_periph
-      \arg        DACx(x =0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_software_trigger_disable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_SWT &= ~DAC_SWT_SWTR0;
-    }else{
-        DAC_SWT &= ~DAC_SWT_SWTR1;
-    }
-}
-
-/*!
-    \brief      get DAC output value
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[out] none
-    \retval     DAC output data
-*/
-uint16_t dac_output_value_get(uint32_t dac_periph)
-{
-    uint16_t data = 0U;
-    if(DAC0 == dac_periph){
-        data = (uint16_t)DAC0_DO;
-    }else{
-        data = (uint16_t)DAC1_DO;
-    }
-    return data;
-}
-
-/*!
-    \brief      enable DAC interrupt(DAC0 DMA underrun interrupt)
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_interrupt_enable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL |= DAC_CTL_DDUDRIE0;
-    }else{
-        DAC_CTL |= DAC_CTL_DDUDRIE1;
-    }
-}
-
-/*!
-    \brief      disable DAC interrupt(DAC0 DMA underrun interrupt)
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_interrupt_disable(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL &= ~DAC_CTL_DDUDRIE0;
-    }else{
-        DAC_CTL &= ~DAC_CTL_DDUDRIE1;
-    }
-}
-
-/*!
-    \brief      set DAC trigger source
-    \param[in]  dac_periph
-      \arg        DACx(x =0,1)
-    \param[in]  triggersource: external triggers of DAC
-      \arg        DAC_TRIGGER_T1_TRGO: trigger source is timer1 trgo
-      \arg        DAC_TRIGGER_T2_TRGO: trigger source is timer2 trgo
-      \arg        DAC_TRIGGER_T5_TRGO: trigger source is timer5 trgo
-      \arg        DAC_TRIGGER_T14_TRGO: trigger source is timer14 trgo
-      \arg        DAC_TRIGGER_EXTI_IT9: trigger source is exti interrupt line 9
-      \arg        DAC_TRIGGER_SOFTWARE: trigger source is software
-    \param[out] none
-    \retval     none
-*/
-void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource)
-{
-    if(DAC0 == dac_periph){
-        DAC_CTL &= ~DAC_CTL_DTSEL0;
-        DAC_CTL |= triggersource;
-    }else{
-        DAC_CTL &= ~DAC_CTL_DTSEL1;
-        DAC_CTL |= (triggersource <<16);
-    }
-}
-
-/*!
-    \brief      get the specified DAC flag(DAC DMA underrun flag)
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[out] none
-    \retval     the state of dac bit(SET or RESET)
-*/
-FlagStatus dac_flag_get(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        /* check the DMA underrun flag */
-        if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)){
-            return SET;
-        }else{
-            return RESET;
-        }
-    }else{
-        /* check the DMA underrun flag */
-        if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)){
-            return SET;
-        }else{
-            return RESET;
-        }
-    }
-}
-
-/*!
-    \brief      clear the specified DAC flag(DAC DMA underrun flag)
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_flag_clear(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_STAT |= DAC_STAT_DDUDR0;
-    }else{
-        DAC_STAT |= DAC_STAT_DDUDR1;
-    }
-}
-
-/*!
-    \brief      get the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[out] none
-    \retval     the state of DAC interrupt flag(SET or RESET)
-*/
-FlagStatus dac_interrupt_flag_get(uint32_t dac_periph)
-{
-    uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
-    if(DAC0 == dac_periph){
-        ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0;
-        ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0;
-        /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
-        if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
-             return SET;
-        }else{
-            return RESET;
-        }
-    }else{
-        ddudr_flag = DAC_STAT & DAC_STAT_DDUDR1;
-        ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE1;
-        /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
-        if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
-             return SET;
-        }else{
-            return RESET;
-        }
-    }
-}
-
-/*!
-    \brief      clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[out] none
-    \retval     none
-*/
-void dac_interrupt_flag_clear(uint32_t dac_periph)
-{
-    if(DAC0 == dac_periph){
-        DAC_STAT |= DAC_STAT_DDUDR0;
-    }else{
-        DAC_STAT |= DAC_STAT_DDUDR1;
-    }
-}
-
-/*!
-    \brief      enable DAC concurrent mode
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac_concurrent_enable(void)
-{
-    uint32_t ctl = 0U;
-    ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
-    DAC_CTL |= (ctl);
-}
-
-/*!
-    \brief      disable DAC concurrent mode
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac_concurrent_disable(void)
-{
-    uint32_t ctl = 0U;
-    ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
-    DAC_CTL &= (~ctl);
-}
-
-/*!
-    \brief      enable DAC concurrent software trigger function
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac_concurrent_software_trigger_enable(void)
-{
-    uint32_t swt = 0U;
-    swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
-    DAC_SWT |= (swt); 
-}
-
-/*!
-    \brief      disable DAC concurrent software trigger function
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac_concurrent_software_trigger_disable(void)
-{
-    uint32_t swt = 0U;
-    swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
-    DAC_SWT &= (~swt);
-}
-
-/*!
-    \brief      enable DAC concurrent buffer funcution
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac_concurrent_output_buffer_enable(void)
-{
-    uint32_t ctl = 0U;
-    ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
-    DAC_CTL &= (~ctl);
-}
-
-/*!
-    \brief      disable DAC concurrent buffer funcution
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac_concurrent_output_buffer_disable(void)
-{
-    uint32_t ctl = 0U;
-    ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
-    DAC_CTL |= (ctl);
-}
-
-/*!
-    \brief      enable DAC concurrent interrupt funcution
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac_concurrent_interrupt_enable(void)
-{
-    DAC_CTL |= DAC_CTL_DDUDRIE0;
-    DAC_CTL |= DAC_CTL_DDUDRIE1;
-}
-
-/*!
-    \brief      disable DAC concurrent interrupt funcution
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void dac_concurrent_interrupt_disable(void)
-{
-    DAC_CTL &= ~DAC_CTL_DDUDRIE0;
-    DAC_CTL &= ~DAC_CTL_DDUDRIE1;
-}
-
-/*!
-    \brief      set the DAC specified data holding register value
-    \param[in]  dac_periph
-      \arg        DACx(x=0,1)
-    \param[in]  dac_align
-      \arg        DAC_ALIGN_8B_R: data right 8b alignment
-      \arg        DAC_ALIGN_12B_R: data right 12b alignment
-      \arg        DAC_ALIGN_12B_L: data left 12b alignment
-    \param[in]  data: data to be loaded
-    \param[out] none
-    \retval     none
-*/
-void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
-{
-    if(DAC0 == dac_periph){
-        switch(dac_align){
-        /* data right 12b alignment */
-        case DAC_ALIGN_12B_R:
-            DAC0_R12DH = data;
-            break;
-        /* data left 12b alignment */
-        case DAC_ALIGN_12B_L:
-            DAC0_L12DH = data;
-            break;
-        /* data right 8b alignment */
-        case DAC_ALIGN_8B_R:
-            DAC0_R8DH = data;
-            break;
-        default:
-            break;
-        }
-    }else{
-        switch(dac_align){
-        /* data right 12b alignment */
-        case DAC_ALIGN_12B_R:
-            DAC1_R12DH = data;
-            break;
-        /* data left 12b alignment */
-        case DAC_ALIGN_12B_L:
-            DAC1_L12DH = data;
-            break;
-        /* data right 8b alignment */
-        case DAC_ALIGN_8B_R:
-            DAC1_R8DH = data;
-            break;
-        default:
-            break;
-        }
-    }
-}
-
-/*!
-    \brief      set DAC concurrent mode data holding register value
-    \param[in]  dac_align
-      \arg        DAC_ALIGN_8B_R: data right 8b alignment
-      \arg        DAC_ALIGN_12B_R: data right 12b alignment
-      \arg        DAC_ALIGN_12B_L: data left 12b alignment
-    \param[in]  data1: data to be loaded
-    \param[in]  data2: data to be loaded
-    \param[out] none
-    \retval     none
-*/
-void dac_concurrent_data_set(uint32_t dac_align, uint16_t data1, uint16_t data2)
-{
-    uint32_t data = 0U;
-    switch(dac_align){
-    /* data right 12b alignment */
-    case DAC_ALIGN_12B_R:
-        data = ((uint32_t)data2 << 16U) | data1;
-        DACC_R12DH = data;
-        break;
-    /* data left 12b alignment */
-    case DAC_ALIGN_12B_L:
-        data = ((uint32_t)data2 << 16U) | data1;
-        DACC_L12DH = data;
-        break;
-    /* data right 8b alignment */
-    case DAC_ALIGN_8B_R:
-        data = ((uint32_t)data2 << 8U) | data1;
-        DACC_R8DH = data;
-        break;
-    default:
-        break;
-    }
-}
-
-#endif /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_ivref.c

@@ -1,206 +0,0 @@
-/*!
-    \file  gd32f1x0_ivref.c
-    \brief IVREF driver
-	
-    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifdef GD32F170_190
-
-#include "gd32f1x0_ivref.h"
-
-/*!
-    \brief      deinit IVREF
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void ivref_deinit(void)
-{
-    rcu_periph_reset_enable(RCU_OPAIVREFRST);
-    rcu_periph_reset_disable(RCU_OPAIVREFRST);
-}
-
-/*!
-    \brief      enable VREF
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void vref_enable(void)
-{
-    IVREF_CTL |= IVREF_CTL_VREN;
-}
-
-/*!
-    \brief      disable VREF
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void vref_disable(void)
-{
-    IVREF_CTL &= ~IVREF_CTL_VREN;
-}
-
-/*!
-    \brief      set VREF mode
-    \param[in]  vrefmode
-      \arg        VREF_CONNECT_EXTERNAL_CAP: vref connect external capacitor
-      \arg        VREF_DISCONNECT_EXTERNAL_CAP: vref disconnect external capacitor
-    \param[out] none
-    \retval     none
-*/
-void vref_mode_set(uint32_t vrefmode)
-{
-    uint32_t ctl = 0U;
-    ctl = IVREF_CTL;
-    /* clear voltage reference enable bits */
-    ctl &= ~IVREF_CTL_DECAP;
-    ctl |= vrefmode;
-    IVREF_CTL = ctl;
-}
-
-/*!
-    \brief      set VREF voltage precision trim.
-    \param[in]  precisiontrim
-      \arg        VREF_VOLT_PRECISION_TRIM_X(x=0..31): (-6.4+ 0.4*x)%
-    \param[out] none
-    \retval     none
-*/
-void vref_precision_trim_value_set(uint32_t precisiontrim)
-{
-    uint32_t ctl = 0U;
-    ctl = IVREF_CTL;
-    ctl &= ~IVREF_CTL_VPT;
-    ctl |= precisiontrim;
-    IVREF_CTL = ctl;
-}
-
-/*!
-    \brief      enable IREF
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void iref_enable(void)
-{
-    IVREF_CTL |= IVREF_CTL_CREN;
-}
-
-/*!
-    \brief      disable IREF
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void iref_disable(void)
-{
-    IVREF_CTL &= ~IVREF_CTL_CREN;
-}
-
-/*!
-    \brief      set IREF mode
-    \param[in]  irefmode
-      \arg        IREF_MODE_LOW_POWER: 1uA step
-      \arg        IREF_MODE_HIGH_CURRENT: 8uA step
-    \param[out] none
-    \retval     none
-*/
-void iref_mode_set(uint32_t irefmode)
-{
-    uint32_t ctl = 0U;
-    ctl = IVREF_CTL;
-    ctl &= ~IVREF_CTL_SSEL;
-    ctl |= irefmode;
-    IVREF_CTL = ctl;
-}
-
-/*!
-    \brief      set IREF precision_trim_value
-    \param[in]  precisiontrim
-      \arg        IREF_CUR_PRECISION_TRIM_X(x=0..31): (-15+ x)%
-    \param[out] none
-    \retval     none
-*/
-void iref_precision_trim_value_set(uint32_t precisiontrim)
-{
-    uint32_t ctl = 0U;
-    ctl = IVREF_CTL;
-    ctl &= ~IVREF_CTL_CPT;
-    ctl |= precisiontrim;
-    IVREF_CTL = ctl;
-}
-
-/*!
-    \brief      set IREF sink mode
-    \param[in]  irefsinkmode
-      \arg        IREF_SOURCE_CURRENT : source current.
-      \arg        IREF_SINK_CURRENT: sink current
-    \param[out] none
-    \retval     none
-*/
-void iref_sink_set(uint32_t irefsinkmode)
-{
-    uint32_t ctl = 0U;
-    ctl = IVREF_CTL;
-    /* clear sink current mode bits */
-    ctl &= ~IVREF_CTL_SCMOD;
-    /* set sink current mode bits */
-    ctl |= irefsinkmode;
-    IVREF_CTL = ctl;
-}
-
-/*!
-    \brief      set IREF step data 
-    \param[in]  irefstepdata
-      \arg        IREF_CUR_STEP_DATA_X:(x=0..63): step*x
-    \param[out] none
-    \retval     none
-*/
-void iref_step_data_config(uint32_t irefstepdata)
-{
-    uint32_t ctl = 0U;
-    /* get ctl value */
-    ctl = IVREF_CTL;
-    /* clear current step data bits */
-    ctl &= ~IVREF_CTL_CSDT;
-    /* set current step data bits */
-    ctl |= irefstepdata;
-    IVREF_CTL = ctl;
-}
-
-#endif  /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_opa.c

@@ -1,367 +0,0 @@
-/*!
-    \file  gd32f1x0_opa.c
-    \brief OPA driver
-
-    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifdef GD32F170_190
-
-#include "gd32f1x0_opa.h" 
-
-/*!
-    \brief      deinit the OPA register to its default reset value
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void opa_deinit(void)
-{
-    rcu_periph_reset_enable(RCU_OPAIVREFRST);
-    rcu_periph_reset_disable(RCU_OPAIVREFRST);
-}
-
-/*!
-    \brief      enable OPA switch
-    \param[in]  opax_swy
-      \arg        OPA_T3OPA0: T3 switch enable for OPA0
-      \arg        OPA_S1OPA0: S1 switch enable for OPA0
-      \arg        OPA_S2OPA0: S2 switch enable for OPA0
-      \arg        OPA_S3OPA0: S3 switch enable for OPA0
-      \arg        OPA_T3OPA1: T3 switch enable for OPA1
-      \arg        OPA_S1OPA1: S1 switch enable for OPA1
-      \arg        OPA_S2OPA1: S2 switch enable for OPA1
-      \arg        OPA_S3OPA1: S3 switch enable for OPA1
-      \arg        OPA_S4OPA1: S4 switch enable for OPA1
-      \arg        OPA_T3OPA2: T3 switch enable for OPA2
-      \arg        OPA_S1OPA2: S3 switch enable for OPA2
-      \arg        OPA_S2OPA2: S3 switch enable for OPA2
-      \arg        OPA_S3OPA2: S3 switch enable for OPA2
-    \param[out] none
-    \retval     none
-*/
-void opa_switch_enable(uint32_t opax_swy)
-{
-    OPA_CTL |= (uint32_t)(opax_swy);
-}
-
-/*!
-    \brief      enable OPA
-    \param[in]  opa_periph
-      \arg        OPAx(x =0,1,2)
-    \param[out] none
-    \retval     none
-*/
-void opa_enable(uint32_t opa_periph)
-{
-    if(OPA0 == opa_periph){
-        OPA_CTL &= ~OPA_CTL_OPA0PD;
-    }else if(OPA1 == opa_periph){
-        OPA_CTL &= ~OPA_CTL_OPA1PD;
-    }else{
-        OPA_CTL &= ~OPA_CTL_OPA2PD;
-    }
-}
-
-/*!
-    \brief      disable OPA
-    \param[in]  opa_periph
-      \arg        OPAx(x =0,1,2)
-    \param[out] none
-    \retval     none
-*/
-void opa_disable(uint32_t opa_periph)
-{
-    if(OPA0 == opa_periph){
-        OPA_CTL |= OPA_CTL_OPA0PD;
-    }else if(OPA1 == opa_periph){
-        OPA_CTL |= OPA_CTL_OPA1PD;
-    }else{
-        OPA_CTL |= OPA_CTL_OPA2PD;
-    }
-}
-
-/*!
-    \brief      disable OPA switch
-    \param[in]  opax_swy
-      \arg        OPA_T3OPA0: T3 switch enable for OPA0
-      \arg        OPA_S1OPA0: S1 switch enable for OPA0
-      \arg        OPA_S2OPA0: S2 switch enable for OPA0
-      \arg        OPA_S3OPA0: S3 switch enable for OPA0
-      \arg        OPA_T3OPA1: T3 switch enable for OPA1
-      \arg        OPA_S1OPA1: S1 switch enable for OPA1
-      \arg        OPA_S2OPA1: S2 switch enable for OPA1
-      \arg        OPA_S3OPA1: S3 switch enable for OPA1
-      \arg        OPA_S4OPA1: S4 switch enable for OPA1
-      \arg        OPA_T3OPA2: T3 switch enable for OPA2
-      \arg        OPA_S1OPA2: S3 switch enable for OPA2
-      \arg        OPA_S2OPA2: S3 switch enable for OPA2
-      \arg        OPA_S3OPA2: S3 switch enable for OPA2
-    \param[out] none
-    \retval     none
-*/
-void opa_switch_disable(uint32_t opax_swy)
-{
-    OPA_CTL &= ~opax_swy;
-}
-
-/*!
-    \brief      enable OPA in low power mode
-    \param[in]  opa_periph
-      \arg        OPAx(x =0,1,2)
-    \param[out] none
-    \retval     none
-*/
-void opa_low_power_enable(uint32_t opa_periph)
-{
-    if(OPA0 == opa_periph){
-        OPA_CTL &= ~OPA_CTL_OPA0LPM;
-    }else if(OPA1 == opa_periph){
-        OPA_CTL &= ~OPA_CTL_OPA1LPM;
-    }else{
-        OPA_CTL &= ~OPA_CTL_OPA2LPM;
-    }
-}
-
-/*!
-    \brief      disable OPA in low power mode
-    \param[in]  opa_periph
-      \arg        OPAx(x =0,1,2)
-    \param[out] none
-    \retval     none
-*/
-void opa_low_power_disable(uint32_t opa_periph)
-{
-    if(OPA0 == opa_periph){
-        OPA_CTL |= OPA_CTL_OPA0LPM;
-    }else if(OPA1 == opa_periph){
-        OPA_CTL |= OPA_CTL_OPA1LPM;
-    }else{
-        OPA_CTL |= OPA_CTL_OPA2LPM;
-    }
-}
-
-/*!
-    \brief      set OPA power range
-    \param[in]  powerrange
-      \arg        OPA_POWRANGE_LOW: Low power range is selected (VDDA is lower than 3.3V)
-      \arg        OPA_POWRANGE_HIGH: High power range is selected (VDDA is higher than 3.3V)
-    \param[out] none
-    \retval     none
-*/
-void opa_power_range_config(uint32_t powerrange)
-{
-    OPA_CTL &= ~OPA_CTL_OPA_RANGE;
-    OPA_CTL |= powerrange;
-}
-
-/*!
-    \brief      set OPA bias trimming mode
-    \param[in]  opa_trimmode
-      \arg        OPA_BT_TRIM_FACTORY: factory trimming values are used for offset calibration
-      \arg        OPA_BT_TRIM_USER: user trimming values are used for offset calibration
-    \param[out] none
-    \retval     none
-*/
-void opa_trim_mode_set(uint32_t opa_trimmode)
-{
-    OPA_BT &= ~OPA_BT_OT_USER;
-    OPA_BT |= opa_trimmode;
-}
-
-/*!
-    \brief      set OPA bias trimming value
-    \param[in]  opa_periph
-      \arg        OPAx(x =0,1,2)
-    \param[in]  opa_input
-      \arg        OPA_INPUT_P: PMOS input is selected to configure the trimming value
-      \arg        OPA_INPUT_N: NMOS input is selected to configure the trimming value
-    \param[in]  opa_trimmode
-      \arg        this parameter can be any value lower or equal to 0x0000001F.
-    \param[out] none
-    \retval     none
-*/
-void opa_trim_value_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue)
-{
-    uint32_t bt = 0U, ctl = 0U;
-    ctl = OPA_CTL;
-    bt  = OPA_BT;
-
-    if(OPA0 == opa_periph){
-        /* clear the specified opa calibration for N diff and P diff */
-        ctl &= (uint32_t)~(OPA_CTL_OPA0CAL_L | OPA_CTL_OPA0CAL_H);
-        /* set the specified opa calibration for N diff or P diff */
-        ctl |= opa_input;
-        if(OPA_INPUT_P == opa_input){
-            /* clear the specified PMOS pairs normal mode 5-bit offset trim value */
-            bt &= (~OPA_BT_OA0_TRIM_LOW);
-            bt |= (opa_trimvalue);
-        }else{
-            /* clear the specified NMOS pairs normal mode 5-bit offset trim value */
-            bt &= (~OPA_BT_OA0_TRIM_HIGH);
-            bt |= (opa_trimvalue << 5U);
-        }
-
-    }else if(OPA1 == opa_periph){
-        ctl &= (uint32_t)~(OPA_CTL_OPA1CAL_L | OPA_CTL_OPA1CAL_H);
-        ctl |= (uint32_t)(opa_input << 8U);
-        if(OPA_INPUT_P == opa_input){
-            /* clear the specified PMOS pairs normal mode 5-bit offset trim value */
-            bt &= (~OPA_BT_OA1_TRIM_LOW);
-            bt |= (opa_trimvalue << 10U);
-        }else{
-            /* clear the specified NMOS pairs normal mode 5-bit offset trim value */
-            bt &= (~OPA_BT_OA1_TRIM_HIGH);
-            bt |= (opa_trimvalue << 15U);
-        }
-    }else{
-        ctl &= (uint32_t)~(OPA_CTL_OPA2CAL_L | OPA_CTL_OPA2CAL_H);
-        ctl |= (uint32_t)(opa_input << 16U);
-        if(OPA_INPUT_P == opa_input){
-            /* clear the specified PMOS pairs normal mode 5-bit offset trim value */
-            bt &= (~OPA_BT_OA2_TRIM_LOW);
-            bt |= (opa_trimvalue << 20U);
-        }else{
-            /* clear the specified NMOS pairs normal mode 5-bit offset trim value */
-            bt &= (~OPA_BT_OA2_TRIM_HIGH);
-            bt |= (opa_trimvalue << 25U);
-        }
-    }
-
-    OPA_CTL = ctl;
-    OPA_BT  = bt;
-}
-
-/*!
-    \brief      set OPA bias trimming value low power
-    \param[in]  opa_periph
-      \arg        OPAx(x =0,1,2)
-    \param[in]  opa_input
-      \arg        OPA_INPUT_P: PMOS input is selected to configure the trimming value
-      \arg        OPA_INPUT_N: NMOS input is selected to configure the trimming value
-    \param[in]  opa_trimmode
-      \arg        this parameter can be any value lower or equal to 0x0000001F.
-    \param[out] none
-    \retval     none
-*/
-void opa_trim_value_lp_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue)
-{
-    uint32_t lpbt = 0U, ctl  = 0U;
-    ctl  = OPA_CTL;
-    lpbt = OPA_LPBT;
-
-    if(OPA0 == opa_periph){
-        ctl &= (uint32_t)~(OPA_CTL_OPA0CAL_L | OPA_CTL_OPA0CAL_H);
-        ctl |= opa_input;
-        if(OPA_INPUT_P == opa_input){
-            /* clear the specified PMOS pairs low power mode 5-bit offset trim value */
-            lpbt &= (~OPA_LPBT_OA0_TRIM_LOW);
-            lpbt |= (opa_trimvalue);
-        }else{
-            /* clear the specified NMOS pairs low power mode 5-bit offset trim value */
-            lpbt &= (~OPA_LPBT_OA0_TRIM_HIGH);
-            lpbt |= (opa_trimvalue << 5U);
-        }
-    }else if (OPA1 == opa_periph){
-        ctl &= (uint32_t)~(OPA_CTL_OPA0CAL_L | OPA_CTL_OPA0CAL_H);
-        ctl |= (uint32_t)(opa_input << 8U);
-        if(OPA_INPUT_P == opa_input){
-            /* clear the specified PMOS pairs low power mode 5-bit offset trim value */
-            lpbt &= (~OPA_LPBT_OA1_TRIM_LOW);
-            lpbt |= (opa_trimvalue << 10U);
-        }else{
-            /* clear the specified NMOS pairs low power mode 5-bit offset trim value */
-            lpbt &= (~OPA_LPBT_OA1_TRIM_HIGH);
-            lpbt |= (opa_trimvalue << 15U);
-        }
-
-    }else{
-        ctl &= (uint32_t)~(OPA_CTL_OPA2CAL_L | OPA_CTL_OPA2CAL_H);
-        ctl |= (uint32_t)(opa_input << 16U);
-        if(OPA_INPUT_P == opa_input){
-            /* clear the specified PMOS pairs low power mode 5-bit offset trim value */
-            lpbt &= (~OPA_LPBT_OA2_TRIM_LOW);
-            lpbt |= (opa_trimvalue << 20U);
-        }else{
-            /* clear the specified NMOS pairs low power mode 5-bit offset trim value */
-            lpbt &= (~OPA_LPBT_OA2_TRIM_HIGH);
-            lpbt |= (opa_trimvalue << 25U);
-        }
-    }
-
-    OPA_CTL  = ctl;
-    OPA_LPBT = lpbt;
-}
-
-/*!
-    \brief      get OPA calibration flag
-    \param[in]  opa_periph
-      \arg        OPAx(x =0,1,2)
-    \param[out] none
-    \retval     The state of the OPA calibration flag (SET or RESET)
-*/
-FlagStatus opa_cal_out_get(uint32_t opa_periph)
-{
-    uint32_t data = 0U;
-    FlagStatus bitstatus = RESET;
-    data = OPA_CTL;
-
-    if(OPA0 == opa_periph){
-        /* get opa0 calibration output bit status */
-        if ((uint32_t)RESET != (data & OPA_CTL_OPA1CALOUT)){
-            bitstatus = SET;
-        }else{
-            bitstatus = RESET;
-        }
-    }else if(OPA1 == opa_periph){
-        /* get opa1 calibration output bit status */
-        if ((uint32_t)RESET != (data & OPA_CTL_OPA1CALOUT)){
-            bitstatus = SET;
-        }else{
-            bitstatus = RESET;
-        }
-    }else{
-        /* get opa2 calibration output bit status */
-        if((uint32_t)RESET != (data & OPA_CTL_OPA1CALOUT)){
-            bitstatus = SET;
-        }else{
-            bitstatus = RESET;
-        }
-    }
-    return bitstatus;
-}
-
-#endif  /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_slcd.c

@@ -1,464 +0,0 @@
-/*!
-    \file  gd32f1x0_slcd.c
-    \brief SLCD driver
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-/*
-    Copyright (c) 2019, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification, 
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this 
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
-OF SUCH DAMAGE.
-*/
-
-#ifdef GD32F170_190
-#include "gd32f1x0_slcd.h"
-
-/*!
-    \brief      SLCD reset 
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void slcd_deinit(void)
-{
-    rcu_periph_reset_enable(RCU_SLCDRST);
-    rcu_periph_reset_disable(RCU_SLCDRST);
-}
-
-/*!
-    \brief      get the SLCD status flag
-    \param[in]  slcd_flag: the adc status flag bits
-      \arg        SLCD_FLAG_ON: SLCD controller on flag
-      \arg        SLCD_FLAG_SOF: start of frame flag
-      \arg        SLCD_FLAG_UPR: SLCD data update request flag
-      \arg        SLCD_FLAG_UPD: update LCDS data done flag
-      \arg        SLCD_FLAG_VRDY: SLCD voltage ready flag
-      \arg        SLCD_FLAG_SYN: SLCD CFG register synchronization flag
-    \param[out] none
-    \retval     FlagStatus: SET or RESET
-*/
-FlagStatus slcd_flag_get(uint8_t slcd_flag)
-{
-    if(SLCD_STAT & slcd_flag){
-        return SET;
-    }else{
-        return RESET;
-    }
-}
-
-/*!
-    \brief      get the SLCD interrupt flag
-    \param[in]  slcd_interrupt: the adc interrupt flag bits
-      \arg        SLCD_INT_FLAG_SOF: start of frame interrupt
-      \arg        SLCD_INT_FLAG_UPD: SLCD update done interrupt
-    \param[out] none
-    \retval     FlagStatus: SET or RESET
-*/
-FlagStatus slcd_interrupt_flag_get(uint8_t slcd_interrupt)
-{
-    FlagStatus interrupt_flag = RESET;
-    uint32_t state;
-    /* check the interrupt bits */
-    switch(slcd_interrupt){
-    case SLCD_INT_FLAG_SOF:
-        state = SLCD_STAT & SLCD_FLAG_SOF;
-        if((SLCD_CFG & SLCD_CFG_SOFIE) && state){
-            interrupt_flag = SET;
-        }
-        break;
-    case SLCD_INT_FLAG_UPD:
-        state = SLCD_STAT & SLCD_FLAG_UPD;
-        if((SLCD_CFG & SLCD_CFG_UPDIE) && state){
-            interrupt_flag = SET;
-        }
-        break;
-    default:
-        break;
-    }
-    return interrupt_flag;
-}
-
-/*!
-    \brief      clear the SLCD flag
-    \param[in]  slcd_flag: the adc status flag bits
-      \arg        SLCD_FLAG_SOF: start of frame flag
-      \arg        SLCD_FLAG_UPD: update LCDS data done flag
-    \param[out] none
-    \retval     none
-*/
-void slcd_flag_clear(uint8_t slcd_flag)
-{
-    /* check the interrupt bits */
-    switch(slcd_flag){
-    case SLCD_FLAG_SOF:
-        SLCD_STATC |= SLCD_STATC_SOFC;
-        break;
-    case SLCD_FLAG_UPD:
-        SLCD_STATC |= SLCD_STATC_UPDC;
-        break;
-    default:
-        break;
-    }
-}
-
-/*!
-    \brief      clear the SLCD interrupt flag
-    \param[in]  slcd_interrupt: the adc interrupt bits
-      \arg        SLCD_INT_FLAG_SOF: start of frame interrupt
-      \arg        SLCD_INT_FLAG_UPD: SLCD update done interrupt
-    \param[out] none
-    \retval     none
-*/
-void slcd_interrupt_flag_clear(uint8_t slcd_interrupt)
-{
-    /* check the interrupt bits */
-    switch(slcd_interrupt){
-    case SLCD_INT_FLAG_SOF:
-        SLCD_STATC |= SLCD_STATC_SOFC;
-        break;
-    case SLCD_INT_FLAG_UPD:
-        SLCD_STATC |= SLCD_STATC_UPDC;
-        break;
-    default:
-        break;
-    }
-}
-
-/*!
-    \brief      the SLCD interrupt config
-    \param[in]  slcd_interrupt: the adc interrupt bits
-      \arg        SLCD_INT_SOF: start of frame interrupt
-      \arg        SLCD_INT_UPD: SLCD update done interrupt
-    \param[out] none
-    \retval     none
-*/
-void slcd_interrupt_config(uint8_t slcd_interrupt,ControlStatus newvalue)
-{
-    /* ENABLE or DISABLE the interrupt */
-    if(newvalue){
-        /* select the interrupt source */
-        switch(slcd_interrupt){
-        case SLCD_INT_SOF:
-            SLCD_CFG |= (uint32_t) SLCD_CFG_SOFIE;
-            break;
-        case SLCD_INT_UPD:
-            SLCD_CFG |= (uint32_t) SLCD_CFG_UPDIE;
-            break;
-        default:
-            break;
-        }
-    }else{
-        switch(slcd_interrupt){
-        /* select the interrupt source */
-        case SLCD_INT_SOF:
-            SLCD_CFG &= (uint32_t)~(SLCD_CFG_SOFIE);
-            break;
-        case SLCD_INT_UPD:
-            SLCD_CFG &= (uint32_t)~(SLCD_CFG_UPDIE);
-            break;
-        default:
-            break;
-        }
-    }
-}
-
-/*!
-    \brief      SLCD bias voltage select
-    \param[in]  bias_voltage: the SLCD voltage bias
-      \arg        SLCD_BIAS_1_4: 1/4 voltage bias
-      \arg        SLCD_BIAS_1_2: 1/2 voltage bias
-      \arg        SLCD_BIAS_1_3: 1/3 voltage bias
-    \param[out] none
-    \retval     none
-*/
-void slcd_bias_voltage_select(uint32_t bias_voltage)
-{
-    SLCD_CTL &= (uint32_t)~(SLCD_CTL_BIAS);
-    SLCD_CTL |= (uint32_t)bias_voltage;
-}
-
-/*!
-    \brief      SLCD duty cycle select
-    \param[in]  duty: the adc flag bits
-      \arg        SLCD_DUTY_STATIC: static dutycycle
-      \arg        SLCD_DUTY_1_2: 1/2 dutycycle
-      \arg        SLCD_DUTY_1_3: 1/3 dutycycle
-      \arg        SLCD_DUTY_1_4: 1/4 dutycycle
-      \arg        SLCD_DUTY_1_6: 1/6 dutycycle
-      \arg        SLCD_DUTY_1_8: 1/8 dutycycle
-    \param[out] none
-    \retval     none
-*/
-void slcd_duty_select(uint32_t duty)
-{
-    SLCD_CTL &= (uint32_t)~(SLCD_CTL_DUTY);
-    SLCD_CTL |= (uint32_t)duty;
-}
-
-/*!
-    \brief      config the prescaler and the divider of SLCD clock
-                fSLCD = finclk/( pow( 2 , PRE )* DIV )
-    \param[in]  prescaler: the prescaler factor
-      \arg        SLCD_PRESCALER_1: PRE = 0
-      \arg        SLCD_PRESCALER_2: PRE = 1
-      \arg        SLCD_PRESCALER_4: PRE = 2
-      \arg        SLCD_PRESCALER_8: PRE = 3
-      \arg        SLCD_PRESCALER_16: PRE = 4
-      \arg        SLCD_PRESCALER_32: PRE = 5
-      \arg        SLCD_PRESCALER_64: PRE = 6
-      \arg        SLCD_PRESCALER_128: PRE = 7
-      \arg        SLCD_PRESCALER_256: PRE = 8
-      \arg        SLCD_PRESCALER_512: PRE = 9
-      \arg        SLCD_PRESCALER_1024: PRE = 10
-      \arg        SLCD_PRESCALER_2048: PRE = 11
-      \arg        SLCD_PRESCALER_4096: PRE = 12
-      \arg        SLCD_PRESCALER_8192: PRE = 13
-      \arg        SLCD_PRESCALER_16384: PRE = 14
-      \arg        SLCD_PRESCALER_32768: PRE = 15
-    \param[in]  divider: the divider factor
-      \arg        SLCD_DIVIDER_x: x= 16..31 ,DIV = 16..31
-    \param[out] none
-    \retval     none
-*/
-void slcd_clock_config(uint32_t prescaler,uint32_t divider)
-{
-    uint32_t cfg;
-    
-    /* config the prescaler and the divider */
-    cfg = SLCD_CFG;
-    cfg &= (uint32_t)~(SLCD_CFG_PSC | SLCD_CFG_DIV);
-    cfg |= (uint32_t)(prescaler | divider);
-    SLCD_CFG = cfg;
-}
-
-/*!
-    \brief      SLCD blink mode config
-    \param[in]  mode: the prescaler factor
-      \arg        SLCD_BLINKMODE_OFF: blink disabled
-      \arg        SLCD_BLINKMODE_SEG0_COM0: blink enabled on SEG[0], COM[0]
-      \arg        SLCD_BLINKMODE_SEG0_ALLCOM: blink enabled on SEG[0], all COM
-      \arg        SLCD_BLINKMODE_ALLSEG_ALLCOM: blink enabled on all SEG and all COM
-    \param[in]  blink_divider: the divider factor
-      \arg        SLCD_BLINK_FREQUENCY_DIV8: blink frequency = fSLCD/8
-      \arg        SLCD_BLINK_FREQUENCY_DIV16: blink frequency = fSLCD/16
-      \arg        SLCD_BLINK_FREQUENCY_DIV32: blink frequency = fSLCD/32
-      \arg        SLCD_BLINK_FREQUENCY_DIV64: blink frequency = fSLCD/64
-      \arg        SLCD_BLINK_FREQUENCY_DIV128: blink frequency = fSLCD/128
-      \arg        SLCD_BLINK_FREQUENCY_DIV256: blink frequency = fSLCD/256
-      \arg        SLCD_BLINK_FREQUENCY_DIV512: blink frequency = fSLCD/512
-      \arg        SLCD_BLINK_FREQUENCY_DIV1024: blink frequency = fSLCD/1024
-    \param[out] none
-    \retval     none
-*/
-void slcd_blink_mode_config(uint32_t mode,uint32_t blink_divider)
-{
-    SLCD_CFG &= (uint32_t)~(SLCD_CFG_BLKMOD | SLCD_CFG_BLKDIV);
-    SLCD_CFG |= (uint32_t)(mode | blink_divider);
-}
-
-/*!
-    \brief      SLCD contrast ratio config
-    \param[in]  contrast_ratio: specify the VSLCD voltage ,when chosing the internal voltage source
-      \arg        SLCD_CONTRAST_LEVEL_0: maximum SLCD Voltage = 2.60V
-      \arg        SLCD_CONTRAST_LEVEL_1: maximum SLCD Voltage = 2.73V
-      \arg        SLCD_CONTRAST_LEVEL_2: maximum SLCD Voltage = 2.86V
-      \arg        SLCD_CONTRAST_LEVEL_3: maximum SLCD Voltage = 2.99V
-      \arg        SLCD_CONTRAST_LEVEL_4: maximum SLCD Voltage = 3.12V
-      \arg        SLCD_CONTRAST_LEVEL_5: maximum SLCD Voltage = 3.25V
-      \arg        SLCD_CONTRAST_LEVEL_6: maximum SLCD Voltage = 3.38V
-      \arg        SLCD_CONTRAST_LEVEL_7: maximum SLCD Voltage = 3.51V
-    \param[out] none
-    \retval     none
-*/
-void slcd_contrast_ratio_config(uint32_t contrast_ratio)
-{
-    uint32_t cfg;
-    
-    /* config the contrast ratio */
-    cfg = SLCD_CFG;
-    cfg &= (uint32_t)~(SLCD_CFG_CONR);
-    cfg |= (uint32_t)contrast_ratio;
-    SLCD_CFG = cfg;
-}
-
-/*!
-    \brief      SLCD dead time duration config
-    \param[in]  dead_time: configure the length of the dead time between frames
-      \arg        SLCD_DEADTIME_PERIOD_0: no dead time
-      \arg        SLCD_DEADTIME_PERIOD_1: 1 phase inserted between couple of frame
-      \arg        SLCD_DEADTIME_PERIOD_2: 2 phase inserted between couple of frame
-      \arg        SLCD_DEADTIME_PERIOD_3: 3 phase inserted between couple of frame
-      \arg        SLCD_DEADTIME_PERIOD_4: 4 phase inserted between couple of frame
-      \arg        SLCD_DEADTIME_PERIOD_5: 5 phase inserted between couple of frame
-      \arg        SLCD_DEADTIME_PERIOD_6: 6 phase inserted between couple of frame
-      \arg        SLCD_DEADTIME_PERIOD_7: 7 phase inserted between couple of frame
-    \param[out] none
-    \retval     none
-*/
-void slcd_dead_time_config(uint32_t dead_time)
-{
-    uint32_t cfg;
-    
-    /* config dead time duration */
-    cfg = SLCD_CFG;
-    cfg &= (uint32_t)~(SLCD_CFG_DTD);
-    cfg |= (uint32_t)dead_time;
-    SLCD_CFG = cfg;
-}
-
-/*!
-    \brief      SLCD pulse on duration config
-    \param[in]  duration: configure the length of the dead time between frames
-      \arg        SLCD_PULSEON_DURATION_0: pulse on duration = 0
-      \arg        SLCD_PULSEON_DURATION_1: pulse on duration = 1*1/fPRE
-      \arg        SLCD_PULSEON_DURATION_2: pulse on duration = 2*1/fPRE
-      \arg        SLCD_PULSEON_DURATION_3: pulse on duration = 3*1/fPRE
-      \arg        SLCD_PULSEON_DURATION_4: pulse on duration = 4*1/fPRE
-      \arg        SLCD_PULSEON_DURATION_5: pulse on duration = 5*1/fPRE
-      \arg        SLCD_PULSEON_DURATION_6: pulse on duration = 6*1/fPRE
-      \arg        SLCD_PULSEON_DURATION_7: pulse on duration = 7*1/fPRE
-    \param[out] none
-    \retval     none
-*/
-void slcd_pulse_on_duration_config(uint32_t duration)
-{
-    uint32_t cfg;
-    
-    /* config pulse on duration */
-    cfg = SLCD_CFG;
-    cfg &= (uint32_t)~(SLCD_CFG_PULSE);
-    cfg |= (uint32_t)duration;
-    SLCD_CFG = cfg; 
-}
-
-/*!
-    \brief      SLCD common/segment pad select
-    \param[in]  NewValue: ENABLE or DISABLE
-      \arg        ENABLE: LCD_COM[7:4] pad select LCD_SEG[31:28]
-      \arg        DISABLE: LCD_COM[7:4] pad select LCD_COM[7:4]
-    \param[out] none
-    \retval     none
-*/
-void slcd_com_seg_remap(ControlStatus newvalue)
-{
-    if( ENABLE == newvalue ){
-        SLCD_CTL |= SLCD_CTL_COMS;
-    }else{
-        SLCD_CTL &= ~(SLCD_CTL_COMS);
-    }
-}
-
-/*!
-    \brief      SLCD voltage source select
-    \param[in]  voltage_source: the SLCD voltage source
-      \arg        SLCD_VOLTAGE_INTERNAL: internal source
-      \arg        SLCD_VOLTAGE_EXTERNAL: external source (VSLCD pin)
-    \param[out] none
-    \retval     none
-*/
-void slcd_voltage_source_select(uint8_t voltage_source)
-{
-    if( SLCD_VOLTAGE_EXTERNAL == voltage_source ){
-        SLCD_CTL |= SLCD_CTL_VSRC;
-    }else{
-        SLCD_CTL &= ~(SLCD_CTL_VSRC);
-    }
-}
-
-/*!
-    \brief      enable or disable permanent high drive
-    \param[in]  NewValue: ENABLE or DISABLE
-    \param[out] none
-    \retval     none
-*/
-void slcd_high_drive_config(ControlStatus newvalue)
-{
-    if( ENABLE == newvalue ){
-        SLCD_CFG |= SLCD_CFG_HDEN;
-    }else{
-        SLCD_CFG &= ~(SLCD_CFG_HDEN);
-    }
-}
-
-/*!
-    \brief      SLCD voltage source select
-    \param[in]  register_number: refer to slcd_data_register_enum
-                only one parameter can be selected which is shown as below:
-      \arg        SLCD_DATA_REG0: SLCD_DATA register 0
-      \arg        SLCD_DATA_REG1: SLCD_DATA Register 1
-      \arg        SLCD_DATA_REG2: SLCD_DATA register 2
-      \arg        SLCD_DATA_REG3: SLCD_DATA Register 3
-      \arg        SLCD_DATA_REG4: SLCD_DATA register 4
-      \arg        SLCD_DATA_REG5: SLCD_DATA Register 5
-      \arg        SLCD_DATA_REG6: SLCD_DATA register 6
-      \arg        SLCD_DATA_REG7: SLCD_DATA Register 7
-    \param[in]  data: the data write to the register
-    \param[out] none
-    \retval     none
-*/
-void slcd_data_register_write(slcd_data_register_enum register_number, uint32_t data)
-{
-    /* wtite data word to DATA register */
-    SLCD_DATA0_7((uint32_t)register_number) = data; 
-}
-
-/*!
-    \brief      SLCD data update request
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void slcd_data_update_request(void)
-{
-    SLCD_STAT |= SLCD_STAT_UPRF;
-}
-
-/*!
-    \brief      enable SLCD interface
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void slcd_enable(void)
-{
-    SLCD_CTL |= SLCD_CTL_SLCDON;
-}
-
-/*!
-    \brief      disable SLCD interface
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void slcd_disable(void)
-{
-    SLCD_CTL &= ~(SLCD_CTL_SLCDON);
-}
-
-#endif /* GD32F170_190 */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_adc.h

@@ -0,0 +1,365 @@
+/*!
+    \file  gd32f3x0_adc.h
+    \brief definitions for the ADC
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_ADC_H
+#define GD32F3X0_ADC_H
+
+#include "gd32f3x0.h"
+
+/* ADC definitions */
+#define ADC                              ADC_BASE
+
+/* registers definitions */
+#define ADC_STAT                         REG32(ADC + 0x00000000U)            /*!< ADC status register */
+#define ADC_CTL0                         REG32(ADC + 0x00000004U)            /*!< ADC control register 0 */
+#define ADC_CTL1                         REG32(ADC + 0x00000008U)            /*!< ADC control register 1 */
+#define ADC_SAMPT0                       REG32(ADC + 0x0000000CU)            /*!< ADC sampling time register 0 */
+#define ADC_SAMPT1                       REG32(ADC + 0x00000010U)            /*!< ADC sampling time register 1 */
+#define ADC_IOFF0                        REG32(ADC + 0x00000014U)            /*!< ADC inserted channel data offset register 0 */
+#define ADC_IOFF1                        REG32(ADC + 0x00000018U)            /*!< ADC inserted channel data offset register 1 */
+#define ADC_IOFF2                        REG32(ADC + 0x0000001CU)            /*!< ADC inserted channel data offset register 2 */
+#define ADC_IOFF3                        REG32(ADC + 0x00000020U)            /*!< ADC inserted channel data offset register 3 */
+#define ADC_WDHT                         REG32(ADC + 0x00000024U)            /*!< ADC watchdog high threshold register */
+#define ADC_WDLT                         REG32(ADC + 0x00000028U)            /*!< ADC watchdog low threshold register */
+#define ADC_RSQ0                         REG32(ADC + 0x0000002CU)            /*!< ADC regular sequence register 0 */
+#define ADC_RSQ1                         REG32(ADC + 0x00000030U)            /*!< ADC regular sequence register 1 */
+#define ADC_RSQ2                         REG32(ADC + 0x00000034U)            /*!< ADC regular sequence register 2 */
+#define ADC_ISQ                          REG32(ADC + 0x00000038U)            /*!< ADC inserted sequence register */
+#define ADC_IDATA0                       REG32(ADC + 0x0000003CU)            /*!< ADC inserted data register 0 */
+#define ADC_IDATA1                       REG32(ADC + 0x00000040U)            /*!< ADC inserted data register 1 */
+#define ADC_IDATA2                       REG32(ADC + 0x00000044U)            /*!< ADC inserted data register 2 */
+#define ADC_IDATA3                       REG32(ADC + 0x00000048U)            /*!< ADC inserted data register 3 */
+#define ADC_RDATA                        REG32(ADC + 0x0000004CU)            /*!< ADC regular data register */
+#define ADC_OVSAMPCTL                    REG32(ADC + 0x00000080U)            /*!< ADC oversampling control register */
+
+/* bits definitions */
+/* ADC_STAT */
+#define ADC_STAT_WDE                     BIT(0)                              /*!< analog watchdog event flag */
+#define ADC_STAT_EOC                     BIT(1)                              /*!< end of conversion flag */
+#define ADC_STAT_EOIC                    BIT(2)                              /*!< inserted channel end of conversion flag */
+#define ADC_STAT_STIC                    BIT(3)                              /*!< inserted channel start flag */
+#define ADC_STAT_STRC                    BIT(4)                              /*!< regular channel start flag */
+
+/* ADC_CTL0 */
+#define ADC_CTL0_WDCHSEL                 BITS(0,4)                           /*!< analog watchdog channel select bits */
+#define ADC_CTL0_EOCIE                   BIT(5)                              /*!< interrupt enable for EOC */
+#define ADC_CTL0_WDEIE                   BIT(6)                              /*!< analog watchdog interrupt enable */
+#define ADC_CTL0_EOICIE                  BIT(7)                              /*!< interrupt enable for inserted channels */
+#define ADC_CTL0_SM                      BIT(8)                              /*!< scan mode */
+#define ADC_CTL0_WDSC                    BIT(9)                              /*!< when in scan mode, analog watchdog is effective on a single channel */
+#define ADC_CTL0_ICA                     BIT(10)                             /*!< automatic inserted group conversion */
+#define ADC_CTL0_DISRC                   BIT(11)                             /*!< discontinuous mode on regular channels */
+#define ADC_CTL0_DISIC                   BIT(12)                             /*!< discontinuous mode on inserted channels */
+#define ADC_CTL0_DISNUM                  BITS(13,15)                         /*!< discontinuous mode channel count */
+#define ADC_CTL0_IWDEN                   BIT(22)                             /*!< analog watchdog enable on inserted channels */
+#define ADC_CTL0_RWDEN                   BIT(23)                             /*!< analog watchdog enable on regular channels */
+#define ADC_CTL0_DRES                    BITS(24,25)                         /*!< ADC data resolution */
+
+/* ADC_CTL1 */
+#define ADC_CTL1_ADCON                   BIT(0)                              /*!< ADC converter on */
+#define ADC_CTL1_CTN                     BIT(1)                              /*!< continuous conversion */
+#define ADC_CTL1_CLB                     BIT(2)                              /*!< ADC calibration */
+#define ADC_CTL1_RSTCLB                  BIT(3)                              /*!< reset calibration */
+#define ADC_CTL1_DMA                     BIT(8)                              /*!< direct memory access mode */
+#define ADC_CTL1_DAL                     BIT(11)                             /*!< data alignment */
+#define ADC_CTL1_ETSIC                   BITS(12,14)                         /*!< external trigger select for inserted channel */
+#define ADC_CTL1_ETEIC                   BIT(15)                             /*!< external trigger enable for inserted channel */
+#define ADC_CTL1_ETSRC                   BITS(17,19)                         /*!< external trigger select for regular channel */
+#define ADC_CTL1_ETERC                   BIT(20)                             /*!< external trigger enable for regular channel */
+#define ADC_CTL1_SWICST                  BIT(21)                             /*!< start on inserted channel */
+#define ADC_CTL1_SWRCST                  BIT(22)                             /*!< start on regular channel */
+#define ADC_CTL1_TSVREN                  BIT(23)                             /*!< enable channel 16 and 17 */
+#define ADC_CTL1_VBETEN                  BIT(24)                             /*!< VBAT enable */
+
+/* ADC_SAMPTx x=0,1 */
+#define ADC_SAMPTX_SPTN                  BITS(0,2)                           /*!< channel n(n=0..18) sample time selection */
+
+/* ADC_IOFFx x=0..3 */
+#define ADC_IOFFX_IOFF                   BITS(0,11)                          /*!< data offset for inserted channel x */
+
+/* ADC_WDHT */
+#define ADC_WDHT_WDHT                    BITS(0,11)                          /*!< analog watchdog high threshold */
+
+/* ADC_WDLT */
+#define ADC_WDLT_WDLT                    BITS(0,11)                          /*!< analog watchdog low threshold */
+
+/* ADC_RSQx x=0..2 */
+#define ADC_RSQX_RSQN                    BITS(0,4)                           /*!< n conversion in regular sequence */
+#define ADC_RSQ0_RL                      BITS(20,23)                         /*!< regular channel sequence length */
+
+/* ADC_ISQ */
+#define ADC_ISQ_ISQN                     BITS(0,4)                           /*!< n conversion in regular sequence */
+#define ADC_ISQ_IL                       BITS(20,21)                         /*!< inserted sequence length */
+
+/* ADC_IDATAx x=0..3 */
+#define ADC_IDATAX_IDATAN                BITS(0,15)                          /*!< inserted channel x conversion data  */
+
+/* ADC_RDATA */
+#define ADC_RDATA_RDATA                  BITS(0,15)                          /*!< regular channel data */
+
+/* ADC_OVSAMPCTL */
+#define ADC_OVSAMPCTL_OVSEN              BIT(0)                              /*!< oversampling enable */
+#define ADC_OVSAMPCTL_OVSR               BITS(2,4)                           /*!< oversampling ratio */
+#define ADC_OVSAMPCTL_OVSS               BITS(5,8)                           /*!< oversampling shift */
+#define ADC_OVSAMPCTL_TOVS               BIT(9)                              /*!< triggered oversampling */
+
+/* constants definitions */
+/* ADC flag definitions */
+#define ADC_FLAG_WDE                     ADC_STAT_WDE                                /*!< analog watchdog event flag */
+#define ADC_FLAG_EOC                     ADC_STAT_EOC                                /*!< end of group conversion flag */
+#define ADC_FLAG_EOIC                    ADC_STAT_EOIC                               /*!< end of inserted channel group conversion flag */
+#define ADC_FLAG_STIC                    ADC_STAT_STIC                               /*!< start flag of inserted channel group */
+#define ADC_FLAG_STRC                    ADC_STAT_STRC                               /*!< start flag of regular channel group */
+
+/* adc_ctl0 register value */
+#define CTL0_DISNUM(regval)              (BITS(13,15) & ((uint32_t)(regval) << 13))  /*!< number of conversions in discontinuous mode */
+
+/* ADC special function */
+#define ADC_SCAN_MODE                    ADC_CTL0_SM                                 /*!< scan mode */
+#define ADC_INSERTED_CHANNEL_AUTO        ADC_CTL0_ICA                                /*!< inserted channel group convert automatically */
+#define ADC_CONTINUOUS_MODE              ADC_CTL1_CTN                                /*!< continuous mode */
+
+/* ADC data alignment */
+#define ADC_DATAALIGN_RIGHT              ((uint32_t)0x00000000U)                     /*!< right alignment */
+#define ADC_DATAALIGN_LEFT               ADC_CTL1_DAL                                /*!< left alignment */
+
+/* external trigger select for regular channel */
+#define CTL1_ETSRC(regval)               (BITS(17,19) & ((uint32_t)(regval) << 17))  
+#define ADC_EXTTRIG_REGULAR_T0_CH0       CTL1_ETSRC(0)                               /*!< TIMER0 CH0 event select */
+#define ADC_EXTTRIG_REGULAR_T0_CH1       CTL1_ETSRC(1)                               /*!< TIMER0 CH1 event select */
+#define ADC_EXTTRIG_REGULAR_T0_CH2       CTL1_ETSRC(2)                               /*!< TIMER0 CH2 event select */
+#define ADC_EXTTRIG_REGULAR_T1_CH1       CTL1_ETSRC(3)                               /*!< TIMER1 CH1 event select */
+#define ADC_EXTTRIG_REGULAR_T2_TRGO      CTL1_ETSRC(4)                               /*!< TIMER2 TRGO event select */
+#define ADC_EXTTRIG_REGULAR_T14_CH0      CTL1_ETSRC(5)                               /*!< TIMER14 CH0 event select */
+#define ADC_EXTTRIG_REGULAR_EXTI_11      CTL1_ETSRC(6)                               /*!< external interrupt line 11 */
+#define ADC_EXTTRIG_REGULAR_NONE         CTL1_ETSRC(7)                               /*!< software trigger */
+
+/* external trigger select for inserted channel */
+#define CTL1_ETSIC(regval)               (BITS(12,14) & ((uint32_t)(regval) << 12))  
+#define ADC_EXTTRIG_INSERTED_T0_TRGO     CTL1_ETSIC(0)                               /*!< TIMER0 TRGO event select */
+#define ADC_EXTTRIG_INSERTED_T0_CH3      CTL1_ETSIC(1)                               /*!< TIMER0 CH3 event select */
+#define ADC_EXTTRIG_INSERTED_T1_TRGO     CTL1_ETSIC(2)                               /*!< TIMER1 TRGO event select */
+#define ADC_EXTTRIG_INSERTED_T1_CH0      CTL1_ETSIC(3)                               /*!< TIMER1 CH0 event select */
+#define ADC_EXTTRIG_INSERTED_T2_CH3      CTL1_ETSIC(4)                               /*!< TIMER2 CH3 event select */
+#define ADC_EXTTRIG_INSERTED_T14_TRGO    CTL1_ETSIC(5)                               /*!< TIMER14 TRGO event select */
+#define ADC_EXTTRIG_INSERTED_EXTI_15     CTL1_ETSIC(6)                               /*!< external interrupt line 15 */
+#define ADC_EXTTRIG_INSERTED_NONE        CTL1_ETSIC(7)                               /*!< software trigger */
+
+/* adc_samptx register value */
+#define SAMPTX_SPT(regval)               (BITS(0,2) & ((uint32_t)(regval) << 0))     
+#define ADC_SAMPLETIME_1POINT5           SAMPTX_SPT(0)                               /*!< 1.5 sampling cycles */
+#define ADC_SAMPLETIME_7POINT5           SAMPTX_SPT(1)                               /*!< 7.5 sampling cycles */
+#define ADC_SAMPLETIME_13POINT5          SAMPTX_SPT(2)                               /*!< 13.5 sampling cycles */
+#define ADC_SAMPLETIME_28POINT5          SAMPTX_SPT(3)                               /*!< 28.5 sampling cycles */
+#define ADC_SAMPLETIME_41POINT5          SAMPTX_SPT(4)                               /*!< 41.5 sampling cycles */
+#define ADC_SAMPLETIME_55POINT5          SAMPTX_SPT(5)                               /*!< 55.5 sampling cycles */
+#define ADC_SAMPLETIME_71POINT5          SAMPTX_SPT(6)                               /*!< 71.5 sampling cycles */
+#define ADC_SAMPLETIME_239POINT5         SAMPTX_SPT(7)                               /*!< 239.5 sampling cycles */
+
+/* ADC data offset for inserted channel x */
+#define IOFFX_IOFF(regval)               (BITS(0,11) & ((uint32_t)(regval) << 0))
+
+/* ADC analog watchdog high threshold */
+#define WDHT_WDHT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))
+
+/* ADC analog watchdog low  threshold */
+#define WDLT_WDLT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))
+
+/* ADC regular channel group length */
+#define RSQ0_RL(regval)                  (BITS(20,23) & ((uint32_t)(regval) << 20))
+
+/* ADC inserted channel group length */
+#define ISQ_IL(regval)                   (BITS(20,21) & ((uint32_t)(regval) << 20))
+
+/* ADC resolution definitions */
+#define CTL0_DRES(regval)                (BITS(24,25) & ((uint32_t)(regval) << 24))  /*!< ADC resolution */
+#define ADC_RESOLUTION_12B               CTL0_DRES(0)                                /*!< 12-bit ADC resolution */
+#define ADC_RESOLUTION_10B               CTL0_DRES(1)                                /*!< 10-bit ADC resolution */
+#define ADC_RESOLUTION_8B                CTL0_DRES(2)                                /*!< 8-bit ADC resolution */
+#define ADC_RESOLUTION_6B                CTL0_DRES(3)                                /*!< 6-bit ADC resolution */
+
+/* ADC oversampling shift */
+#define OVSAMPCTL_OVSS(regval)           (BITS(5,8) & ((uint32_t)(regval) << 5))
+#define ADC_OVERSAMPLING_SHIFT_NONE      OVSAMPCTL_OVSS(0)                           /*!< no oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_1B        OVSAMPCTL_OVSS(1)                           /*!< 1-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_2B        OVSAMPCTL_OVSS(2)                           /*!< 2-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_3B        OVSAMPCTL_OVSS(3)                           /*!< 3-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_4B        OVSAMPCTL_OVSS(4)                           /*!< 4-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_5B        OVSAMPCTL_OVSS(5)                           /*!< 5-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_6B        OVSAMPCTL_OVSS(6)                           /*!< 6-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_7B        OVSAMPCTL_OVSS(7)                           /*!< 7-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_8B        OVSAMPCTL_OVSS(8)                           /*!< 8-bit oversampling shift */
+
+/* ADC oversampling ratio */
+#define OVSAMPCTL_OVSR(regval)           (BITS(2,4) & ((uint32_t)(regval) << 2))
+#define ADC_OVERSAMPLING_RATIO_MUL2      OVSAMPCTL_OVSR(0)                           /*!< oversampling ratio multiple 2 */
+#define ADC_OVERSAMPLING_RATIO_MUL4      OVSAMPCTL_OVSR(1)                           /*!< oversampling ratio multiple 4 */
+#define ADC_OVERSAMPLING_RATIO_MUL8      OVSAMPCTL_OVSR(2)                           /*!< oversampling ratio multiple 8 */
+#define ADC_OVERSAMPLING_RATIO_MUL16     OVSAMPCTL_OVSR(3)                           /*!< oversampling ratio multiple 16 */
+#define ADC_OVERSAMPLING_RATIO_MUL32     OVSAMPCTL_OVSR(4)                           /*!< oversampling ratio multiple 32 */
+#define ADC_OVERSAMPLING_RATIO_MUL64     OVSAMPCTL_OVSR(5)                           /*!< oversampling ratio multiple 64 */
+#define ADC_OVERSAMPLING_RATIO_MUL128    OVSAMPCTL_OVSR(6)                           /*!< oversampling ratio multiple 128 */
+#define ADC_OVERSAMPLING_RATIO_MUL256    OVSAMPCTL_OVSR(7)                           /*!< oversampling ratio multiple 256 */
+
+/* ADC triggered oversampling */
+#define ADC_OVERSAMPLING_ALL_CONVERT     0U                                          /*!< all oversampled conversions for a channel are done consecutively after a trigger */
+#define ADC_OVERSAMPLING_ONE_CONVERT     1U                                          /*!< each oversampled conversion for a channel needs a trigger */
+
+/* ADC channel group definitions */
+#define ADC_REGULAR_CHANNEL              ((uint8_t)0x01U)                            /*!< ADC regular channel group */
+#define ADC_INSERTED_CHANNEL             ((uint8_t)0x02U)                            /*!< ADC inserted channel group */
+#define ADC_REGULAR_INSERTED_CHANNEL     ((uint8_t)0x03U)                            /*!< both regular and inserted channel group */
+#define ADC_CHANNEL_DISCON_DISABLE       ((uint8_t)0x04U)                            /*!< disable discontinuous mode of regular & inserted channel */
+
+/* ADC inserted channel definitions */
+#define ADC_INSERTED_CHANNEL_0           ((uint8_t)0x00U)                            /*!< ADC inserted channel 0 */
+#define ADC_INSERTED_CHANNEL_1           ((uint8_t)0x01U)                            /*!< ADC inserted channel 1 */
+#define ADC_INSERTED_CHANNEL_2           ((uint8_t)0x02U)                            /*!< ADC inserted channel 2 */
+#define ADC_INSERTED_CHANNEL_3           ((uint8_t)0x03U)                            /*!< ADC inserted channel 3 */
+
+/* ADC channel definitions */
+#define ADC_CHANNEL_0                    ((uint8_t)0x00U)                            /*!< ADC channel 0 */
+#define ADC_CHANNEL_1                    ((uint8_t)0x01U)                            /*!< ADC channel 1 */
+#define ADC_CHANNEL_2                    ((uint8_t)0x02U)                            /*!< ADC channel 2 */
+#define ADC_CHANNEL_3                    ((uint8_t)0x03U)                            /*!< ADC channel 3 */
+#define ADC_CHANNEL_4                    ((uint8_t)0x04U)                            /*!< ADC channel 4 */
+#define ADC_CHANNEL_5                    ((uint8_t)0x05U)                            /*!< ADC channel 5 */
+#define ADC_CHANNEL_6                    ((uint8_t)0x06U)                            /*!< ADC channel 6 */
+#define ADC_CHANNEL_7                    ((uint8_t)0x07U)                            /*!< ADC channel 7 */
+#define ADC_CHANNEL_8                    ((uint8_t)0x08U)                            /*!< ADC channel 8 */
+#define ADC_CHANNEL_9                    ((uint8_t)0x09U)                            /*!< ADC channel 9 */
+#define ADC_CHANNEL_10                   ((uint8_t)0x0AU)                            /*!< ADC channel 10 */
+#define ADC_CHANNEL_11                   ((uint8_t)0x0BU)                            /*!< ADC channel 11 */
+#define ADC_CHANNEL_12                   ((uint8_t)0x0CU)                            /*!< ADC channel 12 */
+#define ADC_CHANNEL_13                   ((uint8_t)0x0DU)                            /*!< ADC channel 13 */
+#define ADC_CHANNEL_14                   ((uint8_t)0x0EU)                            /*!< ADC channel 14 */
+#define ADC_CHANNEL_15                   ((uint8_t)0x0FU)                            /*!< ADC channel 15 */
+#define ADC_CHANNEL_16                   ((uint8_t)0x10U)                            /*!< ADC channel 16 */
+#define ADC_CHANNEL_17                   ((uint8_t)0x11U)                            /*!< ADC channel 17 */
+#define ADC_CHANNEL_18                   ((uint8_t)0x12U)                            /*!< ADC channel 18 */
+
+/* ADC interrupt definitions */
+#define ADC_INT_WDE                      ADC_STAT_WDE                                /*!< analog watchdog event interrupt */
+#define ADC_INT_EOC                      ADC_STAT_EOC                                /*!< end of group conversion interrupt */
+#define ADC_INT_EOIC                     ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt */
+
+/* ADC interrupt flag */
+#define ADC_INT_FLAG_WDE                 ADC_STAT_WDE                                /*!< analog watchdog event interrupt flag */
+#define ADC_INT_FLAG_EOC                 ADC_STAT_EOC                                /*!< end of group conversion interrupt flag */
+#define ADC_INT_FLAG_EOIC                ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt flag */
+
+/* function declarations */
+/* reset ADC */
+void adc_deinit(void);
+/* enable ADC interface */
+void adc_enable(void);
+/* disable ADC interface */
+void adc_disable(void);
+
+/* ADC calibration and reset calibration */
+void adc_calibration_enable(void);
+/* enable DMA request */
+void adc_dma_mode_enable(void);
+/* disable DMA request */
+void adc_dma_mode_disable(void);
+
+/* enable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_enable(void);
+/* disable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_disable(void);
+/* enable the Vbat channel */
+void adc_vbat_enable(void);
+/* disable the Vbat channel */
+void adc_vbat_disable(void);
+
+/* configure ADC discontinuous mode */
+void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length);
+/* configure ADC special function */
+void adc_special_function_config(uint32_t function, ControlStatus newvalue);
+
+/* configure ADC data alignment */
+void adc_data_alignment_config(uint32_t data_alignment);
+/* configure the length of regular channel group or inserted channel group */
+void adc_channel_length_config(uint8_t channel_group, uint32_t length);
+/* configure ADC regular channel */
+void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
+/* configure ADC inserted channel */
+void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
+/* configure ADC inserted channel offset */
+void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset);
+/* enable ADC external trigger */
+void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue);
+/* configure ADC external trigger source */
+void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source);
+/* enable ADC software trigger */
+void adc_software_trigger_enable(uint8_t channel_group);
+
+/* read ADC regular group data register */
+uint16_t adc_regular_data_read(void);
+/* read ADC inserted group data register */
+uint16_t adc_inserted_data_read(uint8_t inserted_channel);
+
+/* get the ADC flag bits */
+FlagStatus adc_flag_get(uint32_t flag);
+/* clear the ADC flag bits */
+void adc_flag_clear(uint32_t flag);
+/* get the ADC interrupt bits */
+FlagStatus adc_interrupt_flag_get(uint32_t flag);
+/* clear the ADC flag */
+void adc_interrupt_flag_clear(uint32_t flag);
+/* enable ADC interrupt */
+void adc_interrupt_enable(uint32_t interrupt);
+/* disable ADC interrupt */
+void adc_interrupt_disable(uint32_t interrupt);
+
+/* configure ADC analog watchdog single channel */
+void adc_watchdog_single_channel_enable(uint8_t channel);
+/* configure ADC analog watchdog group channel */
+void adc_watchdog_group_channel_enable(uint8_t channel_group);
+/* disable ADC analog watchdog */
+void adc_watchdog_disable(void);
+/* configure ADC analog watchdog threshold */
+void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
+
+/* configure ADC resolution */
+void adc_resolution_config(uint32_t resolution);
+/* configure ADC oversample mode */
+void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
+/* enable ADC oversample mode */
+void adc_oversample_mode_enable(void);
+/* disable ADC oversample mode */
+void adc_oversample_mode_disable(void);
+
+#endif /* GD32F3X0_ADC_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_cec.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_cec.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_cec.h
+    \file  gd32f3x0_cec.h
     \brief definitions for the CEC
     
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,21 +33,23 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_CEC_H
-#define GD32F1X0_CEC_H
+#ifdef GD32F350
 
-#include "gd32f1x0.h"
+#ifndef GD32F3X0_CEC_H
+#define GD32F3X0_CEC_H
+
+#include "gd32f3x0.h"
 
 /* CEC definitions */
 #define CEC                                CEC_BASE                   /*!< CEC base address */
 
 /* registers definitions */
-#define CEC_CTL                            REG32(CEC + 0x00000000U)         /*!< CEC control register */
-#define CEC_CFG                            REG32(CEC + 0x00000004U)         /*!< CEC configuration register */
-#define CEC_TDATA                          REG32(CEC + 0x00000008U)         /*!< CEC transmit data register */
-#define CEC_RDATA                          REG32(CEC + 0x0000000CU)         /*!< CEC receive data register */
-#define CEC_INTF                           REG32(CEC + 0x00000010U)         /*!< CEC interrupt flag Register */
-#define CEC_INTEN                          REG32(CEC + 0x00000014U)         /*!< CEC interrupt enable register */
+#define CEC_CTL                            REG32(CEC + 0x00000000U)   /*!< CEC control register */
+#define CEC_CFG                            REG32(CEC + 0x00000004U)   /*!< CEC configuration register */
+#define CEC_TDATA                          REG32(CEC + 0x00000008U)   /*!< CEC transmit data register */
+#define CEC_RDATA                          REG32(CEC + 0x0000000CU)   /*!< CEC receive data register */
+#define CEC_INTF                           REG32(CEC + 0x00000010U)   /*!< CEC interrupt flag Register */
+#define CEC_INTEN                          REG32(CEC + 0x00000014U)   /*!< CEC interrupt enable register */
 
 /* bits definitions */
 /* CEC_CTL */
@@ -182,12 +181,12 @@ OF SUCH DAMAGE.
 #define CEC_INT_FLAG_TAERR                 CEC_INTF_TAERR             /*!< TX ACK error flag */
 
 /* interrupt enable bits */
-#define CEC_INT_BR                         CEC_INTEN_BRIE             /*!< BR interrupt enable */
+#define CEC_INT_BR                         CEC_INTEN_BRIE             /*!< RBR interrupt enable */
 #define CEC_INT_REND                       CEC_INTEN_RENDIE           /*!< REND interrupt enable */
 #define CEC_INT_RO                         CEC_INTEN_ROIE             /*!< RO interrupt enable */
-#define CEC_INT_BRE                        CEC_INTEN_BREIE            /*!< BRE interrupt enable. */
-#define CEC_INT_BPSE                       CEC_INTEN_BPSEIE           /*!< BPSE interrupt enable */
-#define CEC_INT_BPLE                       CEC_INTEN_BPLEIE           /*!< BPLE interrupt enable. */
+#define CEC_INT_BRE                        CEC_INTEN_BREIE            /*!< RBRE interrupt enable. */
+#define CEC_INT_BPSE                       CEC_INTEN_BPSEIE           /*!< RSBPE interrupt enable */
+#define CEC_INT_BPLE                       CEC_INTEN_BPLEIE           /*!< RLBPE interrupt enable. */
 #define CEC_INT_RAE                        CEC_INTEN_RAEIE            /*!< RAE interrupt enable */
 #define CEC_INT_ARBF                       CEC_INTEN_ARBFIE           /*!< ALRLST interrupt enable */
 #define CEC_INT_TBR                        CEC_INTEN_TBRIE            /*!< TBR interrupt enable */
@@ -196,12 +195,11 @@ OF SUCH DAMAGE.
 #define CEC_INT_TERR                       CEC_INTEN_TERRIE           /*!< TE interrupt enable */
 #define CEC_INT_TAERR                      CEC_INTEN_TAERRIE          /*!< TAE interrupt enable */
 
-/* function configuration */
-/*  initialization functions */
+/* function declarations */
 /* reset HDMI-CEC controller */
 void cec_deinit(void);
 /* configure signal free time,the signal free time counter start option,own address */
-void cec_init(uint32_t sftopt, uint32_t sft, uint32_t address);
+void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address);
 /* configure generate Error-bit, whether stop receive message when detected bit rising error */
 void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp);
 /* enable HDMI-CEC controller */
@@ -209,7 +207,6 @@ void cec_enable(void);
 /* disable HDMI-CEC controller */
 void cec_disable(void);
 
-/* function configuration */
 /* start CEC message transmission */
 void cec_transmission_start(void);
 /* end CEC message transmission */
@@ -221,7 +218,7 @@ void cec_listen_mode_disable(void);
 /* configure and clear own address */
 void cec_own_address_config(uint32_t address);
 /* configure signal free time and the signal free time counter start option */
-void cec_sft_config(uint32_t sftopt,uint32_t sft);
+void cec_sft_config(uint32_t sftmopt,uint32_t sft);
 /* configure generate Error-bit when detected some abnormal situation or not */
 void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre);
 /* whether stop receive message when detected bit rising error */
@@ -235,19 +232,19 @@ void cec_data_send(uint8_t data);
 /* receive a data by the CEC peripheral */
 uint8_t cec_data_receive(void);
 
-/* interrupt & flag functions */
-/* get CEC interrupt flag */
-FlagStatus cec_interrupt_flag_get(uint32_t flag);
-/* clear CEC interrupt flag */
-void cec_interrupt_flag_clear(uint32_t flag);
-/* enable CEC interrupt */
+/* enable interrupt */
 void cec_interrupt_enable(uint32_t flag);
-/* disable CEC interrupt */
+/* disable interrupt */
 void cec_interrupt_disable(uint32_t flag);
 /* get CEC status */
 FlagStatus cec_flag_get(uint32_t flag);
 /* clear CEC status */
 void cec_flag_clear(uint32_t flag);
+/* get CEC int flag and status */
+FlagStatus cec_interrupt_flag_get(uint32_t flag);
+/* clear CEC int flag and status */
+void cec_interrupt_flag_clear(uint32_t flag);
 
-#endif /* GD32F1X0_CEC_H */
+#endif /* GD32F3X0_CEC_H */
 
+#endif /* GD32F350 */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_cmp.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_cmp.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_cmp.h
+    \file  gd32f3x0_cmp.h
     \brief definitions for the CMP
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,10 +33,10 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_CMP_H
-#define GD32F1X0_CMP_H
+#ifndef GD32F3X0_CMP_H
+#define GD32F3X0_CMP_H
 
-#include "gd32f1x0.h"   
+#include "gd32f3x0.h"
 
 /* CMP definitions */
 #define CMP                                      CMP_BASE                       /*!< CMP base address */  
@@ -47,8 +44,7 @@ OF SUCH DAMAGE.
 /* registers definitions */
 #define CMP_CS                                   REG32((CMP) + 0x00000000U)     /*!< CMP control and status register */
 
-/* bits definitions */
-/* CMP_CS */
+/* CMP_CS bits definitions */
 #define CMP_CS_CMP0EN                            BIT(0)                         /*!< CMP0 enable  */
 #define CMP_CS_CMP0SW                            BIT(1)                         /*!< CMP0 switch */
 #define CMP_CS_CMP0M                             BITS(2,3)                      /*!< CMP0 mode */
@@ -85,13 +81,9 @@ typedef enum
     CMP_1_2VREFINT,                                                             /*!< VREFINT /2 input */
     CMP_3_4VREFINT,                                                             /*!< VREFINT *3/4 input */
     CMP_VREFINT,                                                                /*!< VREFINT input */
-    CMP_DAC0,                                                                   /*!< PA4 (DAC0) input */
-#ifdef GD32F170_190
-    CMP_DAC1,                                                                   /*!< DAC1 input */
-#else
+    CMP_DAC,                                                                    /*!< PA4 (DAC) input */
     CMP_PA5,                                                                    /*!< PA5 input */
-#endif
-    CMP_PA_0_2                                                                  /*!< PA0 input when CMP0 is selected, PA2 input when CMP1 is selected */
+    CMP_PA_0_2                                                                  /*!< PA0 or PA2 input */
 }inverting_input_enum;
 
 /* hysteresis */
@@ -129,7 +121,7 @@ typedef enum
 #define CS_CMP0MSEL_1_2VREFINT                   CS_CMP0MSEL(1)                 /*!< CMP0 inverting input 1/2 Vrefint */
 #define CS_CMP0MSEL_3_4VREFINT                   CS_CMP0MSEL(2)                 /*!< CMP0 inverting input 3/4 Vrefint */
 #define CS_CMP0MSEL_VREFINT                      CS_CMP0MSEL(3)                 /*!< CMP0 inverting input Vrefint */
-#define CS_CMP0MSEL_DAC0                         CS_CMP0MSEL(4)                 /*!< CMP0 inverting input DAC0*/
+#define CS_CMP0MSEL_DAC                          CS_CMP0MSEL(4)                 /*!< CMP0 inverting input DAC*/
 #define CS_CMP0MSEL_PA5                          CS_CMP0MSEL(5)                 /*!< CMP0 inverting input PA5*/
 #define CS_CMP0MSEL_PA0                          CS_CMP0MSEL(6)                 /*!< CMP0 inverting input PA0*/
 
@@ -164,15 +156,11 @@ typedef enum
 #define CS_CMP1MSEL_1_2VREFINT                   CS_CMP1MSEL(1)                 /*!< CMP1 inverting input 1/2 Vrefint */
 #define CS_CMP1MSEL_3_4VREFINT                   CS_CMP1MSEL(2)                 /*!< CMP1 inverting input 3/4 Vrefint */
 #define CS_CMP1MSEL_VREFINT                      CS_CMP1MSEL(3)                 /*!< CMP1 inverting input Vrefint */
-#define CS_CMP1MSEL_DAC0                         CS_CMP1MSEL(4)                 /*!< CMP1 inverting input DAC0*/
-#ifdef GD32F170_190
-#define CS_CMP1MSEL_PA5                          CS_CMP1MSEL(5)                 /*!< CMP1 inverting input PA5*/
-#else
-#define CS_CMP1MSEL_DAC1                         CS_CMP1MSEL(5)                 /*!< CMP1 inverting input DAC1*/
-#endif
-#define CS_CMP1MSEL_PA2                          CS_CMP1MSEL(6)                 /*!< CMP1 inverting input PA2*/
-
-/* comparator channel1 output */
+#define CS_CMP1MSEL_DAC                          CS_CMP1MSEL(4)                 /*!< CMP1 inverting input DAC */
+#define CS_CMP1MSEL_PA5                          CS_CMP1MSEL(5)                 /*!< CMP1 inverting input PA5 */
+#define CS_CMP1MSEL_PA2                          CS_CMP1MSEL(6)                 /*!< CMP1 inverting input PA2 */
+
+/* CMP1 output */
 #define CS_CMP1OSEL(regval)                      (BITS(24,26) & ((uint32_t)(regval) << 24))
 #define CS_CMP1OSEL_OUTPUT_NONE                  CS_CMP1OSEL(0)                 /*!< CMP1 output none  */
 #define CS_CMP1OSEL_OUTPUT_TIMER0BKIN            CS_CMP1OSEL(1)                 /*!< CMP1 output TIMER 0 break input */
@@ -191,30 +179,26 @@ typedef enum
 #define CS_CMP1HST_HYSTERESIS_HIGH               CS_CMP1HST(3)                  /*!< CMP1 output high hysteresis */
 
 /* comparator x definitions */
-#define CMP0                                     ((uint32_t)0x00000000U)        /*!< comparator 0 */
-#define CMP1                                     ((uint32_t)0x00000010U)        /*!< comparator 1 */
+#define CMP0                                     ((uint32_t)0x00000000U)          /*!< comparator 0 */
+#define CMP1                                     ((uint32_t)0x00000010U)          /*!< comparator 1 */
 
 /* comparator output level */
-#define CMP_OUTPUTLEVEL_HIGH                     ((uint32_t)0x00000001U)        /*!< comparator output high */
-#define CMP_OUTPUTLEVEL_LOW                      ((uint32_t)0x00000000U)        /*!< comparator output low */
+#define CMP_OUTPUTLEVEL_HIGH                     ((uint32_t)0x00000001U)          /*!< comparator output high */
+#define CMP_OUTPUTLEVEL_LOW                      ((uint32_t)0x00000000U)          /*!< comparator output low */
 
 /* output polarity of comparator */
-#define CMP_OUTPUT_POLARITY_INVERTED             ((uint32_t)0x00000001U)        /*!< output is inverted */
-#define CMP_OUTPUT_POLARITY_NOINVERTED           ((uint32_t)0x00000000U)        /*!< output is not inverted */
+#define CMP_OUTPUT_POLARITY_INVERTED             ((uint32_t)0x00000001U)          /*!< output is inverted */
+#define CMP_OUTPUT_POLARITY_NOINVERTED           ((uint32_t)0x00000000U)          /*!< output is not inverted */
 
 /* function declarations */
+
 /* initialization functions */
 /* CMP deinit */
 void cmp_deinit(void);
 /* CMP mode init */
-void cmp_mode_init(uint32_t cmp_periph, \
-                   operating_mode_enum cmp_operating_mode, \
-                   inverting_input_enum cmp_inverting_input, \
-                   cmp_hysteresis_enum output_hysteresis);
+void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis);
 /* CMP output init */
-void cmp_output_init(uint32_t cmp_periph, \
-                     cmp_output_enum cmp_output_slection, \
-                     uint32_t cmp_output_polarity);
+void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity);
 
 /* enable functions */
 /* enable CMP */
@@ -236,4 +220,4 @@ void cmp_lock_enable(uint32_t cmp_periph);
 /* get output level */
 uint32_t cmp_output_level_get(uint32_t cmp_periph);
 
-#endif /* GD32F1X0_CMP_H */
+#endif /* GD32F3X0_CMP_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_crc.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_crc.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_crc.h
+    \file  gd32f3x0_crc.h
     \brief definitions for the CRC
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,37 +33,47 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_CRC_H
-#define GD32F1X0_CRC_H
+#ifndef GD32F3X0_CRC_H
+#define GD32F3X0_CRC_H
 
-#include "gd32f1x0.h"
+#include "gd32f3x0.h"
 
 /* CRC definitions */
 #define CRC                            CRC_BASE
 
 /* registers definitions */
-#define CRC_DATA                       REG32(CRC + 0x00U)              /*!< CRC data register */
-#define CRC_FDATA                      REG32(CRC + 0x04U)              /*!< CRC free data register */
-#define CRC_CTL                        REG32(CRC + 0x08U)              /*!< CRC control register */
-#define CRC_IDATA                      REG32(CRC + 0x10U)              /*!< CRC initialization data register */
+#define CRC_DATA                       REG32(CRC + 0x00000000U)            /*!< CRC data register */
+#define CRC_FDATA                      REG32(CRC + 0x00000004U)            /*!< CRC free data register */
+#define CRC_CTL                        REG32(CRC + 0x00000008U)            /*!< CRC control register */
+#define CRC_IDATA                      REG32(CRC + 0x00000010U)            /*!< CRC initialization data register */
+#define CRC_POLY                       REG32(CRC + 0x00000014U)            /*!< CRC polynomial register */
 
 /* bits definitions */
-
 /* CRC_DATA */
-#define CRC_DATA_DATA                  BITS(0,31)                      /*!< CRC calculation result bits */
+#define CRC_DATA_DATA                  BITS(0,31)                      /*!< CRC data bits */
 
 /* CRC_FDATA */
 #define CRC_FDATA_FDATA                BITS(0,7)                       /*!< CRC free data bits */
 
 /* CRC_CTL */
 #define CRC_CTL_RST                    BIT(0)                          /*!< CRC reset bit */
+#define CRC_CTL_PS                     BITS(3,4)                       /*!< size of polynomial function bits */
 #define CRC_CTL_REV_I                  BITS(5,6)                       /*!< input data reverse function bits */
 #define CRC_CTL_REV_O                  BIT(7)                          /*!< output data reverse function bit */
 
-/* CRC_IDATA */
+/* CRC_INIT */
 #define CRC_IDATA_IDATA                BITS(0,31)                      /*!< CRC initialization data bits */
 
+/* CRC_POLY */
+#define CRC_POLY_POLY                  BITS(0,31)                      /*!< CRC polynomial value bits */
+
 /* constants definitions */
+/* size of polynomial function */
+#define CTL_PS(regval)                 (BITS(3, 4) & ((regval) << 3))
+#define CRC_CTL_PS_32                  CTL_PS(0)                       /*!< 32-bit polynomial for CRC calculation */
+#define CRC_CTL_PS_16                  CTL_PS(1)                       /*!< 16-bit polynomial for CRC calculation */
+#define CRC_CTL_PS_8                   CTL_PS(2)                       /*!< 8-bit polynomial for CRC calculation */
+#define CRC_CTL_PS_7                   CTL_PS(3)                       /*!< 7-bit polynomial for CRC calculation */
 
 /* input data reverse function */
 #define CTL_REV_I(regval)              (BITS(5, 6) & ((regval) << 5))
@@ -76,7 +83,6 @@ OF SUCH DAMAGE.
 #define CRC_INPUT_DATA_WORD            CTL_REV_I(3)                    /*!< input data reversed by word type */
 
 /* function declarations */
-
 /* deinit CRC calculation unit */
 void crc_deinit(void);
 
@@ -95,14 +101,19 @@ uint8_t crc_free_data_register_read(void);
 /* write the free data register */
 void crc_free_data_register_write(uint8_t free_data);
 
-/* write the initializaiton data register */
+/* write the initial value register */
 void crc_init_data_register_write(uint32_t init_data);
 /* configure the CRC input data function */
 void crc_input_data_reverse_config(uint32_t data_reverse);
 
+/* configure the CRC size of polynomial function */
+void crc_polynomial_size_set(uint32_t poly_size);
+/* configure the CRC polynomial value function */
+void crc_polynomial_set(uint32_t poly);
+
 /* CRC calculate a 32-bit data */
 uint32_t crc_single_data_calculate(uint32_t sdata);
 /* CRC calculate a 32-bit data array */
 uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
 
-#endif /* GD32F1X0_CRC_H */
+#endif /* GD32F3X0_CRC_H */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_ctc.h

@@ -0,0 +1,191 @@
+/*!
+    \file  gd32f3x0_ctc.h
+    \brief definitions for the CTC
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_CTC_H
+#define GD32F3X0_CTC_H
+
+#include "gd32f3x0.h"
+
+/* CTC definitions */
+#define CTC                          CTC_BASE
+
+/* registers definitions */
+#define CTC_CTL0                     REG32(CTC + 0x00000000U)  /*!< CTC control register 0 */
+#define CTC_CTL1                     REG32(CTC + 0x00000004U)  /*!< CTC control register 1 */
+#define CTC_STAT                     REG32(CTC + 0x00000008U)  /*!< CTC status register */
+#define CTC_INTC                     REG32(CTC + 0x0000000CU)  /*!< CTC interrupt clear register */
+
+/* bits definitions */
+/* CTC_CTL0 */
+#define CTC_CTL0_CKOKIE              BIT(0)                    /*!< clock trim OK(CKOKIF) interrupt enable */ 
+#define CTC_CTL0_CKWARNIE            BIT(1)                    /*!< clock trim warning(CKWARNIF) interrupt enable */
+#define CTC_CTL0_ERRIE               BIT(2)                    /*!< error(ERRIF) interrupt enable */
+#define CTC_CTL0_EREFIE              BIT(3)                    /*!< EREFIF interrupt enable */
+#define CTC_CTL0_CNTEN               BIT(5)                    /*!< CTC counter enable */
+#define CTC_CTL0_AUTOTRIM            BIT(6)                    /*!< hardware automatically trim mode */
+#define CTC_CTL0_SWREFPUL            BIT(7)                    /*!< software reference source sync pulse */
+#define CTC_CTL0_TRIMVALUE           BITS(8,13)                /*!< IRC48M trim value */
+
+/* CTC_CTL1 */
+#define CTC_CTL1_RLVALUE             BITS(0,15)                /*!< CTC counter reload value */
+#define CTC_CTL1_CKLIM               BITS(16,23)               /*!< clock trim base limit value */
+#define CTC_CTL1_REFPSC              BITS(24,26)               /*!< reference signal source prescaler */
+#define CTC_CTL1_REFSEL              BITS(28,29)               /*!< reference signal source selection */
+#define CTC_CTL1_REFPOL              BIT(31)                   /*!< reference signal source polarity */
+
+/* CTC_STAT */
+#define CTC_STAT_CKOKIF              BIT(0)                    /*!< clock trim OK interrupt flag */
+#define CTC_STAT_CKWARNIF            BIT(1)                    /*!< clock trim warning interrupt flag */
+#define CTC_STAT_ERRIF               BIT(2)                    /*!< error interrupt flag */
+#define CTC_STAT_EREFIF              BIT(3)                    /*!< expect reference interrupt flag */
+#define CTC_STAT_CKERR               BIT(8)                    /*!< clock trim error bit */
+#define CTC_STAT_REFMISS             BIT(9)                    /*!< reference sync pulse miss */
+#define CTC_STAT_TRIMERR             BIT(10)                   /*!< trim value error bit */
+#define CTC_STAT_REFDIR              BIT(15)                   /*!< CTC trim counter direction when reference sync pulse occurred */
+#define CTC_STAT_REFCAP              BITS(16,31)               /*!< CTC counter capture when reference sync pulse occurred */
+
+/* CTC_INTC */
+#define CTC_INTC_CKOKIC              BIT(0)                    /*!< CKOKIF interrupt clear bit */
+#define CTC_INTC_CKWARNIC            BIT(1)                    /*!< CKWARNIF interrupt clear bit */
+#define CTC_INTC_ERRIC               BIT(2)                    /*!< ERRIF interrupt clear bit */
+#define CTC_INTC_EREFIC              BIT(3)                    /*!< EREFIF interrupt clear bit */
+
+/* constants definitions */
+#define CTL0_TRIMVALUE(regval)                           (BITS(8,13) & ((uint32_t)(regval) << 8))
+#define CTL1_CKLIM(regval)                               (BITS(16,23) & ((uint32_t)(regval) << 16))
+#define GET_STAT_REFCAP(regval)                          GET_BITS((regval),16,31)
+#define GET_CTL0_TRIMVALUE(regval)                       GET_BITS((regval),8,13)
+
+/* hardware automatically trim mode definitions */
+#define CTC_HARDWARE_TRIM_MODE_ENABLE                    CTC_CTL0_AUTOTRIM            /*!< hardware automatically trim mode enable*/
+#define CTC_HARDWARE_TRIM_MODE_DISABLE                   ((uint32_t)0x00000000U)      /*!< hardware automatically trim mode disable*/
+
+/* reference signal source polarity definitions */
+#define CTC_REFSOURCE_POLARITY_FALLING                   CTC_CTL1_REFPOL              /*!< reference signal source polarity is falling edge*/
+#define CTC_REFSOURCE_POLARITY_RISING                    ((uint32_t)0x00000000U)      /*!< reference signal source polarity is rising edge*/
+
+/* reference signal source selection definitions */
+#define CTL1_REFSEL(regval)                              (BITS(28,29) & ((uint32_t)(regval) << 28))
+#define CTC_REFSOURCE_GPIO                               CTL1_REFSEL(0)               /*!< GPIO is selected */
+#define CTC_REFSOURCE_LXTAL                              CTL1_REFSEL(1)               /*!< LXTAL is clock selected */
+#define CTC_REFSOURCE_USBSOF                             CTL1_REFSEL(2)               /*!< USBFSSOF selected */
+
+/* reference signal source prescaler definitions */
+#define CTL1_REFPSC(regval)                              (BITS(24,26) & ((uint32_t)(regval) << 24))
+#define CTC_REFSOURCE_PSC_OFF                            CTL1_REFPSC(0)               /*!< reference signal not divided */
+#define CTC_REFSOURCE_PSC_DIV2                           CTL1_REFPSC(1)               /*!< reference signal divided by 2 */
+#define CTC_REFSOURCE_PSC_DIV4                           CTL1_REFPSC(2)               /*!< reference signal divided by 4 */
+#define CTC_REFSOURCE_PSC_DIV8                           CTL1_REFPSC(3)               /*!< reference signal divided by 8 */
+#define CTC_REFSOURCE_PSC_DIV16                          CTL1_REFPSC(4)               /*!< reference signal divided by 16 */
+#define CTC_REFSOURCE_PSC_DIV32                          CTL1_REFPSC(5)               /*!< reference signal divided by 32 */
+#define CTC_REFSOURCE_PSC_DIV64                          CTL1_REFPSC(6)               /*!< reference signal divided by 64 */
+#define CTC_REFSOURCE_PSC_DIV128                         CTL1_REFPSC(7)               /*!< reference signal divided by 128 */
+
+/* CTC interrupt enable definitions */
+#define CTC_INT_CKOK                                     CTC_CTL0_CKOKIE              /*!< clock trim OK interrupt enable */
+#define CTC_INT_CKWARN                                   CTC_CTL0_CKWARNIE            /*!< clock trim warning interrupt enable */
+#define CTC_INT_ERR                                      CTC_CTL0_ERRIE               /*!< error interrupt enable */
+#define CTC_INT_EREF                                     CTC_CTL0_EREFIE              /*!< expect reference interrupt enable */
+
+/* CTC interrupt source definitions */
+#define CTC_INT_FLAG_CKOK                                CTC_STAT_CKOKIF              /*!< clock trim OK interrupt flag */
+#define CTC_INT_FLAG_CKWARN                              CTC_STAT_CKWARNIF            /*!< clock trim warning interrupt flag */
+#define CTC_INT_FLAG_ERR                                 CTC_STAT_ERRIF               /*!< error interrupt flag */
+#define CTC_INT_FLAG_EREF                                CTC_STAT_EREFIF              /*!< expect reference interrupt flag */
+#define CTC_INT_FLAG_CKERR                               CTC_STAT_CKERR               /*!< clock trim error bit */
+#define CTC_INT_FLAG_REFMISS                             CTC_STAT_REFMISS             /*!< reference sync pulse miss */
+#define CTC_INT_FLAG_TRIMERR                             CTC_STAT_TRIMERR             /*!< trim value error */
+
+/* CTC flag definitions */
+#define CTC_FLAG_CKOK                                    CTC_STAT_CKOKIF              /*!< clock trim OK flag */
+#define CTC_FLAG_CKWARN                                  CTC_STAT_CKWARNIF            /*!< clock trim warning flag */
+#define CTC_FLAG_ERR                                     CTC_STAT_ERRIF               /*!< error flag */
+#define CTC_FLAG_EREF                                    CTC_STAT_EREFIF              /*!< expect reference flag */
+#define CTC_FLAG_CKERR                                   CTC_STAT_CKERR               /*!< clock trim error bit */
+#define CTC_FLAG_REFMISS                                 CTC_STAT_REFMISS             /*!< reference sync pulse miss */
+#define CTC_FLAG_TRIMERR                                 CTC_STAT_TRIMERR             /*!< trim value error bit */
+
+/* function declarations */
+/* initialization functions */
+/* reset ctc clock trim controller */
+void ctc_deinit(void);
+/* configure reference signal source polarity */
+void ctc_refsource_polarity_config(uint32_t polarity);
+/* select reference signal source */
+void ctc_refsource_signal_select(uint32_t refs);
+/* configure reference signal source prescaler */
+void ctc_refsource_prescaler_config(uint32_t prescaler);
+/* configure clock trim base limit value */
+void ctc_clock_limit_value_config(uint8_t limit_value);
+/* configure CTC counter reload value */
+void ctc_counter_reload_value_config(uint16_t reload_value);
+/* enable CTC trim counter */
+void ctc_counter_enable(void);
+/* disable CTC trim counter */
+void ctc_counter_disable(void);
+
+/* function configuration */
+/* configure the IRC48M trim value */
+void ctc_irc48m_trim_value_config(uint8_t trim_value);
+/* generate software reference source sync pulse */
+void ctc_software_refsource_pulse_generate(void);
+/* configure hardware automatically trim mode */
+void ctc_hardware_trim_mode_config(uint32_t hardmode);
+
+/* reading functions */
+/* read CTC counter capture value when reference sync pulse occurred */
+uint16_t ctc_counter_capture_value_read(void);
+/* read CTC trim counter direction when reference sync pulse occurred */
+FlagStatus ctc_counter_direction_read(void);
+/* read CTC counter reload value */
+uint16_t ctc_counter_reload_value_read(void);
+/* read the IRC48M trim value */
+uint8_t ctc_irc48m_trim_value_read(void);
+
+/* interrupt & flag functions */
+/* enable the CTC interrupt */
+void ctc_interrupt_enable(uint32_t interrupt);
+/* disable the CTC interrupt */
+void ctc_interrupt_disable(uint32_t interrupt);
+/* get CTC flag */
+FlagStatus ctc_flag_get(uint32_t flag);
+/* clear CTC flag */
+void ctc_flag_clear(uint32_t flag);
+/* get CTC interrupt flag */
+FlagStatus ctc_interrupt_flag_get(uint32_t interrupt); 
+/* clear CTC interrupt flag */
+void ctc_interrupt_flag_clear(uint32_t interrupt);
+
+#endif /* GD32F3X0_CTC_H */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_dac.h

@@ -0,0 +1,204 @@
+/*!
+    \file  gd32f3x0_dac.h
+    \brief definitions for the DAC
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifdef GD32F350
+#ifndef GD32F3X0_DAC_H
+#define GD32F3X0_DAC_H
+
+#include "gd32f3x0.h"
+
+/* DAC definitions */
+#define DAC                     DAC_BASE
+
+/* registers definitions */
+#define DAC_CTL                 REG32(DAC + (0x00000000U))  /*!< DAC control register */
+#define DAC_SWT                 REG32(DAC + (0x00000004U))  /*!< DAC software trigger register */
+#define DAC_R12DH               REG32(DAC + (0x00000008U))  /*!< DAC 12-bit right-aligned data holding register */
+#define DAC_L12DH               REG32(DAC + (0x0000000CU))  /*!< DAC 12-bit left-aligned data holding register */
+#define DAC_R8DH                REG32(DAC + (0x00000010U))  /*!< DAC 8-bit right-aligned data holding register */
+#define DAC_DO                  REG32(DAC + (0x0000002CU))  /*!< DAC output data register */
+#define DAC_STAT                REG32(DAC + (0x00000034U))  /*!< DAC status register */
+
+/* bits definitions */
+/* DAC_CTL */
+#define DAC_CTL_DEN             BIT(0)                      /*!< DAC enable/disable bit */
+#define DAC_CTL_DBOFF           BIT(1)                      /*!< DAC output buffer turn on/turn off bit */
+#define DAC_CTL_DTEN            BIT(2)                      /*!< DAC trigger enable/disable bit */
+#define DAC_CTL_DTSEL           BITS(3,5)                   /*!< DAC trigger source selection enable/disable bits */
+#define DAC_CTL_DWM             BITS(6,7)                   /*!< DAC noise wave mode */
+#define DAC_CTL_DWBW            BITS(8,11)                  /*!< DAC noise wave bit width */
+#define DAC_CTL_DDMAEN          BIT(12)                     /*!< DAC DMA enable/disable bit */
+#define DAC_CTL_DDUDRIE         BIT(13)                     /*!< DAC DMA underrun interrupt enable/disable bit */
+
+/* DAC_SWT */
+#define DAC_SWT_SWTR            BIT(0)                      /*!< DAC software trigger bit,cleared by hardware */
+
+/* DAC_R12DH */
+#define DAC_R12DH_DAC_DH        BITS(0,11)                  /*!< DAC 12-bit right-aligned data bits */
+
+/* DAC_L12DH */
+#define DAC_L12DH_DAC_DH        BITS(4,15)                  /*!< DAC 12-bit left-aligned data bits */
+
+/* DAC_R8DH */
+#define DAC_R8DH_DAC_DH         BITS(0,7)                   /*!< DAC 8-bit right-aligned data bits */
+
+/* DAC_DO */
+#define DAC_DO_DAC_DO           BITS(0,11)                  /*!< DAC 12-bit output data bits */
+
+/* DAC_STAT */
+#define DAC_STAT_DDUDR          BIT(13)                     /*!< DAC DMA underrun flag */
+
+/* constants definitions */
+/* DAC trigger source */
+#define CTL_DTSEL(regval)       (BITS(3,5) & ((uint32_t)(regval) << 3))
+#define DAC_TRIGGER_T5_TRGO     CTL_DTSEL(0)                /*!< TIMER5 TRGO */
+#define DAC_TRIGGER_T2_TRGO     CTL_DTSEL(1)                /*!< TIMER2 TRGO */
+#define DAC_TRIGGER_T14_TRGO    CTL_DTSEL(3)                /*!< TIMER14 TRGO */
+#define DAC_TRIGGER_T1_TRGO     CTL_DTSEL(4)                /*!< TIMER1 TRGO */
+#define DAC_TRIGGER_EXTI_9      CTL_DTSEL(6)                /*!< EXTI interrupt line9 event */
+#define DAC_TRIGGER_SOFTWARE    CTL_DTSEL(7)                /*!< software trigger */
+
+/* DAC noise wave mode */
+#define CTL_DWM(regval)         (BITS(6,7) & ((uint32_t)(regval) << 6))
+#define DAC_WAVE_DISABLE        CTL_DWM(0)                  /*!< wave disable */
+#define DAC_WAVE_MODE_LFSR      CTL_DWM(1)                  /*!< LFSR noise mode */
+#define DAC_WAVE_MODE_TRIANGLE  CTL_DWM(2)                  /*!< triangle noise mode */
+
+/* DAC noise wave bit width */
+#define DWBW(regval)            (BITS(8,11) & ((uint32_t)(regval) << 8))
+#define DAC_WAVE_BIT_WIDTH_1    DWBW(0)                     /*!< bit width of the wave signal is 1 */
+#define DAC_WAVE_BIT_WIDTH_2    DWBW(1)                     /*!< bit width of the wave signal is 2 */
+#define DAC_WAVE_BIT_WIDTH_3    DWBW(2)                     /*!< bit width of the wave signal is 3 */
+#define DAC_WAVE_BIT_WIDTH_4    DWBW(3)                     /*!< bit width of the wave signal is 4 */
+#define DAC_WAVE_BIT_WIDTH_5    DWBW(4)                     /*!< bit width of the wave signal is 5 */
+#define DAC_WAVE_BIT_WIDTH_6    DWBW(5)                     /*!< bit width of the wave signal is 6 */
+#define DAC_WAVE_BIT_WIDTH_7    DWBW(6)                     /*!< bit width of the wave signal is 7 */
+#define DAC_WAVE_BIT_WIDTH_8    DWBW(7)                     /*!< bit width of the wave signal is 8 */
+#define DAC_WAVE_BIT_WIDTH_9    DWBW(8)                     /*!< bit width of the wave signal is 9 */
+#define DAC_WAVE_BIT_WIDTH_10   DWBW(9)                     /*!< bit width of the wave signal is 10 */
+#define DAC_WAVE_BIT_WIDTH_11   DWBW(10)                    /*!< bit width of the wave signal is 11 */
+#define DAC_WAVE_BIT_WIDTH_12   DWBW(11)                    /*!< bit width of the wave signal is 12 */
+
+/* unmask LFSR bits in DAC LFSR noise mode */
+#define DAC_LFSR_BIT0           DAC_WAVE_BIT_WIDTH_1        /*!< unmask the LFSR bit0 */
+#define DAC_LFSR_BITS1_0        DAC_WAVE_BIT_WIDTH_2        /*!< unmask the LFSR bits[1:0] */
+#define DAC_LFSR_BITS2_0        DAC_WAVE_BIT_WIDTH_3        /*!< unmask the LFSR bits[2:0] */
+#define DAC_LFSR_BITS3_0        DAC_WAVE_BIT_WIDTH_4        /*!< unmask the LFSR bits[3:0] */
+#define DAC_LFSR_BITS4_0        DAC_WAVE_BIT_WIDTH_5        /*!< unmask the LFSR bits[4:0] */
+#define DAC_LFSR_BITS5_0        DAC_WAVE_BIT_WIDTH_6        /*!< unmask the LFSR bits[5:0] */
+#define DAC_LFSR_BITS6_0        DAC_WAVE_BIT_WIDTH_7        /*!< unmask the LFSR bits[6:0] */
+#define DAC_LFSR_BITS7_0        DAC_WAVE_BIT_WIDTH_8        /*!< unmask the LFSR bits[7:0] */
+#define DAC_LFSR_BITS8_0        DAC_WAVE_BIT_WIDTH_9        /*!< unmask the LFSR bits[8:0] */
+#define DAC_LFSR_BITS9_0        DAC_WAVE_BIT_WIDTH_10       /*!< unmask the LFSR bits[9:0] */
+#define DAC_LFSR_BITS10_0       DAC_WAVE_BIT_WIDTH_11       /*!< unmask the LFSR bits[10:0] */
+#define DAC_LFSR_BITS11_0       DAC_WAVE_BIT_WIDTH_12       /*!< unmask the LFSR bits[11:0] */
+
+/* triangle amplitude in DAC triangle noise mode */
+#define DAC_TRIANGLE_AMPLITUDE_1    DAC_WAVE_BIT_WIDTH_1    /*!< triangle amplitude is 1 */
+#define DAC_TRIANGLE_AMPLITUDE_3    DAC_WAVE_BIT_WIDTH_2    /*!< triangle amplitude is 3 */
+#define DAC_TRIANGLE_AMPLITUDE_7    DAC_WAVE_BIT_WIDTH_3    /*!< triangle amplitude is 7 */
+#define DAC_TRIANGLE_AMPLITUDE_15   DAC_WAVE_BIT_WIDTH_4    /*!< triangle amplitude is 15 */
+#define DAC_TRIANGLE_AMPLITUDE_31   DAC_WAVE_BIT_WIDTH_5    /*!< triangle amplitude is 31 */
+#define DAC_TRIANGLE_AMPLITUDE_63   DAC_WAVE_BIT_WIDTH_6    /*!< triangle amplitude is 63 */
+#define DAC_TRIANGLE_AMPLITUDE_127  DAC_WAVE_BIT_WIDTH_7    /*!< triangle amplitude is 127 */
+#define DAC_TRIANGLE_AMPLITUDE_255  DAC_WAVE_BIT_WIDTH_8    /*!< triangle amplitude is 255 */
+#define DAC_TRIANGLE_AMPLITUDE_511  DAC_WAVE_BIT_WIDTH_9    /*!< triangle amplitude is 511 */
+#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10   /*!< triangle amplitude is 1023 */
+#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11   /*!< triangle amplitude is 2047 */
+#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12   /*!< triangle amplitude is 4095 */
+
+/* DAC data alignment */
+#define DATA_ALIGN(regval)      (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define DAC_ALIGN_12B_R         DATA_ALIGN(0)               /*!< data right 12b alignment */
+#define DAC_ALIGN_12B_L         DATA_ALIGN(1)               /*!< data left 12b alignment */
+#define DAC_ALIGN_8B_R          DATA_ALIGN(2)               /*!< data right 8b alignment */
+
+/* function declarations */
+/* deinitialize DAC */
+void dac_deinit(void);
+
+/* enable DAC */
+void dac_enable(void);
+/* disable DAC */
+void dac_disable(void);
+/* enable DAC DMA */
+void dac_dma_enable(void);
+/* disable DAC DMA */
+void dac_dma_disable(void);
+/* enable DAC output buffer */
+void dac_output_buffer_enable(void);
+/* disable DAC output buffer */
+void dac_output_buffer_disable(void);
+/* enable DAC trigger */
+void dac_trigger_enable(void);
+/* disable DAC trigger */
+void dac_trigger_disable(void);
+/* enable DAC software trigger */
+void dac_software_trigger_enable(void);
+/* disable DAC software trigger */
+void dac_software_trigger_disable(void);
+/* enable DAC interrupt(DAC DMA underrun interrupt) */
+void dac_interrupt_enable(void);
+/* disable DAC interrupt(DAC DMA underrun interrupt) */
+void dac_interrupt_disable(void);
+
+/* configure DAC trigger source */
+void dac_trigger_source_config(uint32_t triggersource);
+/* configure DAC wave mode */
+void dac_wave_mode_config(uint32_t wave_mode);
+/* configure DAC wave bit width */
+void dac_wave_bit_width_config(uint32_t bit_width);
+/* configure DAC LFSR noise mode */
+void dac_lfsr_noise_config(uint32_t unmask_bits);
+/* configure DAC triangle noise mode */
+void dac_triangle_noise_config(uint32_t amplitude);
+/* get the last data output value */
+uint16_t dac_output_value_get(void);
+
+/* get the specified DAC flag(DAC DMA underrun flag) */
+FlagStatus dac_flag_get(void);
+/* clear the specified DAC flag(DAC DMA underrun flag) */
+void dac_flag_clear(void);
+/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
+FlagStatus dac_interrupt_flag_get(void);
+/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
+void dac_interrupt_flag_clear(void); 
+
+/* set DAC data holding register value */
+void dac_data_set(uint32_t dac_align, uint16_t data);
+
+#endif /* GD32F3X0_DAC_H */
+
+#endif /* GD32F350 */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_dbg.h

@@ -0,0 +1,128 @@
+/*!
+    \file  gd32f3x0_dbg.h
+    \brief definitions for the DBG
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_DBG_H
+#define GD32F3X0_DBG_H
+
+#include "gd32f3x0.h"
+
+/* DBG definitions */
+#define DBG                      DBG_BASE
+
+/* registers definitions */
+#define DBG_ID                   REG32(DBG + 0x00000000U)      /*!< DBG_ID code register */
+#define DBG_CTL0                 REG32(DBG + 0x00000004U)      /*!< DBG control register 0 */
+#define DBG_CTL1                 REG32(DBG + 0x00000008U)      /*!< DBG control register 1 */
+
+/* bits definitions */
+/* DBG_ID */
+#define DBG_ID_ID_CODE           BITS(0,31)                    /*!< DBG ID code values */
+
+/* DBG_CTL0 */
+#define DBG_CTL0_SLP_HOLD        BIT(0)                        /*!< keep debugger connection during sleep mode */
+#define DBG_CTL0_DSLP_HOLD       BIT(1)                        /*!< keep debugger connection during deepsleep mode */
+#define DBG_CTL0_STB_HOLD        BIT(2)                        /*!< keep debugger connection during standby mode */
+#define DBG_CTL0_FWDGT_HOLD      BIT(8)                        /*!< debug FWDGT kept when core is halted */
+#define DBG_CTL0_WWDGT_HOLD      BIT(9)                        /*!< debug WWDGT kept when core is halted */
+#define DBG_CTL0_TIMER0_HOLD     BIT(10)                       /*!< hold TIMER0 counter when core is halted */
+#define DBG_CTL0_TIMER1_HOLD     BIT(11)                       /*!< hold TIMER1 counter when core is halted */
+#define DBG_CTL0_TIMER2_HOLD     BIT(12)                       /*!< hold TIMER2 counter when core is halted */
+#define DBG_CTL0_I2C0_HOLD       BIT(15)                       /*!< hold I2C0 smbus when core is halted */
+#define DBG_CTL0_I2C1_HOLD       BIT(16)                       /*!< hold I2C1 smbus when core is halted */
+#ifdef GD32F350
+#define DBG_CTL0_TIMER5_HOLD     BIT(19)                       /*!< hold TIMER5 counter when core is halted */
+#endif /* GD32F350 */
+#define DBG_CTL0_TIMER13_HOLD    BIT(27)                       /*!< hold TIMER13 counter when core is halted */
+
+/* DBG_CTL1 */
+#define DBG_CTL1_RTC_HOLD        BIT(10)                       /*!< hold RTC calendar and wakeup counter when core is halted */
+#define DBG_CTL1_TIMER14_HOLD    BIT(16)                       /*!< hold TIMER14 counter when core is halted */
+#define DBG_CTL1_TIMER15_HOLD    BIT(17)                       /*!< hold TIMER15 counter when core is halted */
+#define DBG_CTL1_TIMER16_HOLD    BIT(18)                       /*!< hold TIMER16 counter when core is halted */
+
+/* constants definitions */
+#define DBG_LOW_POWER_SLEEP      DBG_CTL0_SLP_HOLD             /*!< keep debugger connection during sleep mode */
+#define DBG_LOW_POWER_DEEPSLEEP  DBG_CTL0_DSLP_HOLD            /*!< keep debugger connection during deepsleep mode */
+#define DBG_LOW_POWER_STANDBY    DBG_CTL0_STB_HOLD             /*!< keep debugger connection during standby mode */
+
+/* define the peripheral debug hold bit position and its register index offset */
+#define DBG_REGIDX_BIT(regidx, bitpos)      (((regidx) << 6) | (bitpos))
+#define DBG_REG_VAL(periph)                 (REG32(DBG + ((uint32_t)(periph) >> 6)))
+#define DBG_BIT_POS(val)                    ((uint32_t)(val) & 0x0000001FU)
+
+/* register index */
+typedef enum 
+{
+    DBG_IDX_CTL0            = 0x04U,                                         /*!< DBG control register 0 offset */
+    DBG_IDX_CTL1            = 0x08U,                                         /*!< DBG control register 1 offset */
+}dbg_reg_idx;
+
+/* peripherals hold bit */
+typedef enum
+{
+    DBG_FWDGT_HOLD          = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U),              /*!< debug FWDGT kept when core is halted */
+    DBG_WWDGT_HOLD          = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U),              /*!< debug WWDGT kept when core is halted */
+    DBG_TIMER0_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U),             /*!< hold TIMER0 counter when core is halted */
+    DBG_TIMER1_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U),             /*!< hold TIMER1 counter when core is halted */
+    DBG_TIMER2_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U),             /*!< hold TIMER2 counter when core is halted */
+#ifdef GD32F350
+    DBG_TIMER5_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U),             /*!< hold TIMER5 counter when core is halted */
+#endif /* GD32F350 */
+    DBG_TIMER13_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U),             /*!< hold TIMER13 counter when core is halted */
+    DBG_TIMER14_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U),             /*!< hold TIMER14 counter when core is halted */
+    DBG_TIMER15_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U),             /*!< hold TIMER15 counter when core is halted */
+    DBG_TIMER16_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U),             /*!< hold TIMER16 counter when core is halted  */
+    DBG_I2C0_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U),             /*!< hold I2C0 smbus when core is halted */
+    DBG_I2C1_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U),             /*!< hold I2C1 smbus when core is halted */
+    DBG_RTC_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U),             /*!< hold RTC calendar and wakeup counter when core is halted */
+}dbg_periph_enum;
+
+/* function declarations */
+/* deinitialize the DBG */
+void dbg_deinit(void);
+/* read DBG_ID code register */
+uint32_t dbg_id_get(void);
+
+/* enable low power behavior when the MCU is in debug mode */
+void dbg_low_power_enable(uint32_t dbg_low_power);
+/* disable low power behavior when the MCU is in debug mode */
+void dbg_low_power_disable(uint32_t dbg_low_power);
+
+/* enable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_enable(dbg_periph_enum dbg_periph);
+/* disable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_disable(dbg_periph_enum dbg_periph);
+
+#endif /* GD32F3X0_DBG_H */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_dma.h

@@ -0,0 +1,273 @@
+/*!
+    \file  gd32f3x0_dma.h
+    \brief definitions for the DMA
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_DMA_H
+#define GD32F3X0_DMA_H
+
+#include "gd32f3x0.h"
+
+/* DMA definitions */
+#define DMA                               DMA_BASE                    /*!< DMA base address */
+
+/* registers definitions */
+#define DMA_INTF                          REG32(DMA + 0x00000000U)    /*!< DMA interrupt flag register */
+#define DMA_INTC                          REG32(DMA + 0x00000004U)    /*!< DMA interrupt flag clear register */
+#define DMA_CH0CTL                        REG32(DMA + 0x00000008U)    /*!< DMA channel 0 control register */
+#define DMA_CH0CNT                        REG32(DMA + 0x0000000CU)    /*!< DMA channel 0 counter register */
+#define DMA_CH0PADDR                      REG32(DMA + 0x00000010U)    /*!< DMA channel 0 peripheral base address register */
+#define DMA_CH0MADDR                      REG32(DMA + 0x00000014U)    /*!< DMA channel 0 memory base address register */
+#define DMA_CH1CTL                        REG32(DMA + 0x0000001CU)    /*!< DMA channel 1 control register */
+#define DMA_CH1CNT                        REG32(DMA + 0x00000020U)    /*!< DMA channel 1 counter register */
+#define DMA_CH1PADDR                      REG32(DMA + 0x00000024U)    /*!< DMA channel 1 peripheral base address register */
+#define DMA_CH1MADDR                      REG32(DMA + 0x00000028U)    /*!< DMA channel 1 memory base address register */
+#define DMA_CH2CTL                        REG32(DMA + 0x00000030U)    /*!< DMA channel 2 control register */
+#define DMA_CH2CNT                        REG32(DMA + 0x00000034U)    /*!< DMA channel 2 counter register */
+#define DMA_CH2PADDR                      REG32(DMA + 0x00000038U)    /*!< DMA channel 2 peripheral base address register */
+#define DMA_CH2MADDR                      REG32(DMA + 0x0000003CU)    /*!< DMA channel 2 memory base address register */
+#define DMA_CH3CTL                        REG32(DMA + 0x00000044U)    /*!< DMA channel 3 control register */
+#define DMA_CH3CNT                        REG32(DMA + 0x00000048U)    /*!< DMA channel 3 counter register */
+#define DMA_CH3PADDR                      REG32(DMA + 0x0000004CU)    /*!< DMA channel 3 peripheral base address register */
+#define DMA_CH3MADDR                      REG32(DMA + 0x00000050U)    /*!< DMA channel 3 memory base address register */
+#define DMA_CH4CTL                        REG32(DMA + 0x00000058U)    /*!< DMA channel 4 control register */
+#define DMA_CH4CNT                        REG32(DMA + 0x0000005CU)    /*!< DMA channel 4 counter register */
+#define DMA_CH4PADDR                      REG32(DMA + 0x00000060U)    /*!< DMA channel 4 peripheral base address register */
+#define DMA_CH4MADDR                      REG32(DMA + 0x00000064U)    /*!< DMA channel 4 memory base address register */
+#define DMA_CH5CTL                        REG32(DMA + 0x0000006CU)    /*!< DMA channel 5 control register */
+#define DMA_CH5CNT                        REG32(DMA + 0x00000070U)    /*!< DMA channel 5 counter register */
+#define DMA_CH5PADDR                      REG32(DMA + 0x00000074U)    /*!< DMA channel 5 peripheral base address register */
+#define DMA_CH5MADDR                      REG32(DMA + 0x00000078U)    /*!< DMA channel 5 memory base address register */
+#define DMA_CH6CTL                        REG32(DMA + 0x00000080U)    /*!< DMA channel 6 control register */
+#define DMA_CH6CNT                        REG32(DMA + 0x00000084U)    /*!< DMA channel 6 counter register */
+#define DMA_CH6PADDR                      REG32(DMA + 0x00000088U)    /*!< DMA channel 6 peripheral base address register */
+#define DMA_CH6MADDR                      REG32(DMA + 0x0000008CU)    /*!< DMA channel 6 memory base address register */
+
+/* bits definitions */
+/* DMA_INTF */
+#define DMA_INTF_GIF                      BIT(0)                /*!< global interrupt flag of channel */
+#define DMA_INTF_FTFIF                    BIT(1)                /*!< full transfer finish flag of channel */
+#define DMA_INTF_HTFIF                    BIT(2)                /*!< half transfer finish flag of channel */
+#define DMA_INTF_ERRIF                    BIT(3)                /*!< error flag of channel */
+
+/* DMA_INTC */
+#define DMA_INTC_GIFC                     BIT(0)                /*!< clear global interrupt flag of channel */
+#define DMA_INTC_FTFIFC                   BIT(1)                /*!< clear transfer finish flag of channel */
+#define DMA_INTC_HTFIFC                   BIT(2)                /*!< clear half transfer finish flag of channel */
+#define DMA_INTC_ERRIFC                   BIT(3)                /*!< clear error flag of channel */
+
+/* DMA_CHxCTL,x=0..6 */
+#define DMA_CHXCTL_CHEN                   BIT(0)                /*!< channel x enable */
+#define DMA_CHXCTL_FTFIE                  BIT(1)                /*!< enable bit for channel x transfer complete interrupt */
+#define DMA_CHXCTL_HTFIE                  BIT(2)                /*!< enable bit for channel x transfer half complete interrupt */
+#define DMA_CHXCTL_ERRIE                  BIT(3)                /*!< enable bit for channel x error interrupt */
+#define DMA_CHXCTL_DIR                    BIT(4)                /*!< direction of the data transfer on the channel */
+#define DMA_CHXCTL_CMEN                   BIT(5)                /*!< circulation mode */
+#define DMA_CHXCTL_PNAGA                  BIT(6)                /*!< next address generation algorithm of peripheral */
+#define DMA_CHXCTL_MNAGA                  BIT(7)                /*!< next address generation algorithm of memory */
+#define DMA_CHXCTL_PWIDTH                 BITS(8,9)             /*!< transfer data size of peripheral */
+#define DMA_CHXCTL_MWIDTH                 BITS(10,11)           /*!< transfer data size of memory */
+#define DMA_CHXCTL_PRIO                   BITS(12,13)           /*!< priority level of channelx */
+#define DMA_CHXCTL_M2M                    BIT(14)               /*!< memory to memory mode */
+
+/* DMA_CHxCNT,x=0..6 */
+#define DMA_CHXCNT_CNT                    BITS(0,15)            /*!< transfer counter */
+
+/* DMA_CHxPADDR,x=0..6 */
+#define DMA_CHXPADDR_PADDR                BITS(0,31)            /*!< peripheral base address */
+
+/* DMA_CHxMADDR,x=0..6 */
+#define DMA_CHXMADDR_MADDR                BITS(0,31)            /*!< memory base address */
+
+/* constants definitions */
+/* DMA channel select */
+typedef enum 
+{
+    DMA_CH0 = 0,                          /*!< DMA Channel0 */
+    DMA_CH1,                              /*!< DMA Channel1 */
+    DMA_CH2,                              /*!< DMA Channel2 */
+    DMA_CH3,                              /*!< DMA Channel3 */
+    DMA_CH4,                              /*!< DMA Channel4 */
+    DMA_CH5,                              /*!< DMA Channel5 */
+    DMA_CH6                               /*!< DMA Channel6 */
+} dma_channel_enum;
+
+/* DMA initialize struct */
+typedef struct
+{
+    uint32_t periph_addr;                 /*!< peripheral base address */
+    uint32_t periph_width;                /*!< transfer data size of peripheral */
+    uint8_t periph_inc;                   /*!< peripheral increasing mode */
+    uint32_t memory_addr;                 /*!< memory base address */
+    uint32_t memory_width;                /*!< transfer data size of memory */
+    uint8_t memory_inc;                   /*!< memory increasing mode */
+    uint8_t direction;                    /*!< channel data transfer direction */
+    uint32_t number;                      /*!< channel transfer number */
+    uint32_t priority;                    /*!< channel priority level */
+} dma_parameter_struct;
+
+/* DMA reset value */
+#define DMA_CHCTL_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCTL register */
+#define DMA_CHCNT_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCNT register */
+#define DMA_CHPADDR_RESET_VALUE           ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXPADDR register */
+#define DMA_CHMADDR_RESET_VALUE           ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXMADDR register */
+#define DMA_CHINTF_RESET_VALUE            (DMA_INTF_GIF | DMA_INTF_FTFIF | \
+                                           DMA_INTF_HTFIF | DMA_INTF_ERRIF)
+
+#define DMA_FLAG_ADD(flag,shift)          ((flag) << ((uint32_t)(shift) * 4U))            /*!< DMA channel flag shift */
+
+/* DMA_CHCTL base address */
+#define DMA_CHXCTL_BASE                   (DMA + (uint32_t)0x00000008U)                   /*!< the base address of DMA channel CHXCTL register */
+#define DMA_CHXCNT_BASE                   (DMA + (uint32_t)0x0000000CU)                   /*!< the base address of DMA channel CHXCNT register */
+#define DMA_CHXPADDR_BASE                 (DMA + (uint32_t)0x00000010U)                   /*!< the base address of DMA channel CHXPADDR register */
+#define DMA_CHXMADDR_BASE                 (DMA + (uint32_t)0x00000014U)                   /*!< the base address of DMA channel CHXMADDR register */
+
+/* DMA channel shift bit */
+#define DMA_CHCTL(channel)                REG32(DMA_CHXCTL_BASE + (uint32_t)0x0000014U * (uint32_t)(channel))         /*!< the address of DMA channel CHXCTL register */
+#define DMA_CHCNT(channel)                REG32(DMA_CHXCNT_BASE + (uint32_t)0x0000014U * (uint32_t)(channel))         /*!< the address of DMA channel CHXCNT register */
+#define DMA_CHPADDR(channel)              REG32(DMA_CHXPADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel))       /*!< the address of DMA channel CHXPADDR register */
+#define DMA_CHMADDR(channel)              REG32(DMA_CHXMADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel))       /*!< the address of DMA channel CHXMADDR register */
+
+/* DMA_INTF register */
+/* interrupt flag bits */
+#define DMA_INT_FLAG_G                    DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
+#define DMA_INT_FLAG_FTF                  DMA_INTF_FTFIF                                  /*!< full transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_HTF                  DMA_INTF_HTFIF                                  /*!< half transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_ERR                  DMA_INTF_ERRIF                                  /*!< error interrupt flag of channel */
+
+/* flag bits */
+#define DMA_FLAG_G                        DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
+#define DMA_FLAG_FTF                      DMA_INTF_FTFIF                                  /*!< full transfer finish flag of channel */
+#define DMA_FLAG_HTF                      DMA_INTF_HTFIF                                  /*!< half transfer finish flag of channel */
+#define DMA_FLAG_ERR                      DMA_INTF_ERRIF                                  /*!< error flag of channel */
+
+/* DMA_CHxCTL register */
+/* interrupt enable bits */
+#define DMA_INT_FTF                       DMA_CHXCTL_FTFIE                                /*!< enable bit for channel full transfer finish interrupt */
+#define DMA_INT_HTF                       DMA_CHXCTL_HTFIE                                /*!< enable bit for channel half transfer finish interrupt */
+#define DMA_INT_ERR                       DMA_CHXCTL_ERRIE                                /*!< enable bit for channel error interrupt */
+
+/* transfer direction */
+#define DMA_PERIPHERAL_TO_MEMORY          ((uint32_t)0x00000000U)                         /*!< read from peripheral and write to memory */
+#define DMA_MEMORY_TO_PERIPHERAL          ((uint32_t)0x00000001U)                         /*!< read from memory and write to peripheral */
+
+/* peripheral increasing mode */
+#define DMA_PERIPH_INCREASE_DISABLE       ((uint32_t)0x00000000U)                         /*!< next address of peripheral is fixed address mode */
+#define DMA_PERIPH_INCREASE_ENABLE        ((uint32_t)0x00000001U)                         /*!< next address of peripheral is increasing address mode */
+
+/* memory increasing mode */
+#define DMA_MEMORY_INCREASE_DISABLE       ((uint32_t)0x00000000U)                         /*!< next address of memory is fixed address mode */
+#define DMA_MEMORY_INCREASE_ENABLE        ((uint32_t)0x00000001U)                         /*!< next address of memory is increasing address mode */
+
+/* transfer data size of peripheral */
+#define CHCTL_PWIDTH(regval)              (BITS(8,9) & ((regval) << 8))                   /*!< transfer data size of peripheral */
+#define DMA_PERIPHERAL_WIDTH_8BIT         CHCTL_PWIDTH(0)                                 /*!< transfer data size of peripheral is 8-bit */
+#define DMA_PERIPHERAL_WIDTH_16BIT        CHCTL_PWIDTH(1)                                 /*!< transfer data size of peripheral is 16-bit */
+#define DMA_PERIPHERAL_WIDTH_32BIT        CHCTL_PWIDTH(2)                                 /*!< transfer data size of peripheral is 32-bit */
+
+/* transfer data size of memory */
+#define CHCTL_MWIDTH(regval)              (BITS(10,11) & ((regval) << 10))                /*!< transfer data size of memory */
+#define DMA_MEMORY_WIDTH_8BIT             CHCTL_MWIDTH(0)                                 /*!< transfer data size of memory is 8-bit */
+#define DMA_MEMORY_WIDTH_16BIT            CHCTL_MWIDTH(1)                                 /*!< transfer data size of memory is 16-bit */
+#define DMA_MEMORY_WIDTH_32BIT            CHCTL_MWIDTH(2)                                 /*!< transfer data size of memory is 32-bit */
+
+/* channel priority level */
+#define CHCTL_PRIO(regval)                (BITS(12,13) & ((uint32_t)(regval) << 12))      /*!< DMA channel priority level */
+#define DMA_PRIORITY_LOW                  CHCTL_PRIO(0)                                   /*!< low priority */
+#define DMA_PRIORITY_MEDIUM               CHCTL_PRIO(1)                                   /*!< medium priority */
+#define DMA_PRIORITY_HIGH                 CHCTL_PRIO(2)                                   /*!< high priority */
+#define DMA_PRIORITY_ULTRA_HIGH           CHCTL_PRIO(3)                                   /*!< ultra high priority */
+
+/* DMA_CHxCNT register */
+/* transfer counter */
+#define DMA_CHANNEL_CNT_MASK              DMA_CHXCNT_CNT
+
+/* function declarations */
+/* deinitialize DMA a channel registers */
+void dma_deinit(dma_channel_enum channelx);
+/* initialize the parameters of DMA struct with the default values */
+void dma_struct_para_init(dma_parameter_struct* init_struct);
+/* initialize DMA channel */
+void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct);
+/* enable DMA circulation mode */
+void dma_circulation_enable(dma_channel_enum channelx);
+/* disable DMA circulation mode */
+void dma_circulation_disable(dma_channel_enum channelx);
+/* enable memory to memory mode */
+void dma_memory_to_memory_enable(dma_channel_enum channelx);
+/* disable memory to memory mode */
+void dma_memory_to_memory_disable(dma_channel_enum channelx);
+/* enable DMA channel */
+void dma_channel_enable(dma_channel_enum channelx);
+/* disable DMA channel */
+void dma_channel_disable(dma_channel_enum channelx);
+
+/* set DMA peripheral base address */
+void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
+/* set DMA memory base address */
+void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
+/* set the number of remaining data to be transferred by the DMA */
+void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
+/* get the number of remaining data to be transferred by the DMA */
+uint32_t dma_transfer_number_get(dma_channel_enum channelx);
+/* configure priority level of DMA channel */
+void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
+/* configure transfer data size of memory */
+void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth);
+/* configure transfer data size of peripheral */
+void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth);
+/* enable next address increasement algorithm of memory */
+void dma_memory_increase_enable(dma_channel_enum channelx);
+/* disable next address increasement algorithm of memory */
+void dma_memory_increase_disable(dma_channel_enum channelx);
+/* enable next address increasement algorithm of peripheral */
+void dma_periph_increase_enable(dma_channel_enum channelx);
+/* disable next address increasement algorithm of peripheral */
+void dma_periph_increase_disable(dma_channel_enum channelx);
+/* configure the direction of data transfer on the channel */
+void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction);
+
+/* check DMA flag is set or not */
+FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
+/* clear DMA a channel flag */
+void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
+/* check DMA flag and interrupt enable bit is set or not */
+FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
+/* clear DMA a channel flag */
+void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
+/* enable DMA interrupt */
+void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
+/* disable DMA interrupt */
+void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source);
+
+#endif /* GD32F3X0_DMA_H */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_exti.h

@@ -0,0 +1,286 @@
+/*!
+    \file  gd32f3x0_exti.h
+    \brief definitions for the EXTI
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.1, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_EXTI_H
+#define GD32F3X0_EXTI_H
+
+#include "gd32f3x0.h"
+
+/* EXTI definitions */
+#define EXTI                         EXTI_BASE
+
+/* registers definitions */
+#define EXTI_INTEN                   REG32(EXTI + 0x00000000U)/*!< interrupt enable register */
+#define EXTI_EVEN                    REG32(EXTI + 0x00000004U)/*!< event enable register */
+#define EXTI_RTEN                    REG32(EXTI + 0x00000008U)/*!< rising edge trigger enable register */
+#define EXTI_FTEN                    REG32(EXTI + 0x0000000CU)/*!< falling trigger enable register */
+#define EXTI_SWIEV                   REG32(EXTI + 0x00000010U)/*!< software interrupt event register */
+#define EXTI_PD                      REG32(EXTI + 0x00000014U)/*!< pending register */
+
+/* bits definitions */
+/* EXTI_INTEN */
+#define EXTI_INTEN_INTEN0            BIT(0)                   /*!< interrupt from line 0 */
+#define EXTI_INTEN_INTEN1            BIT(1)                   /*!< interrupt from line 1 */
+#define EXTI_INTEN_INTEN2            BIT(2)                   /*!< interrupt from line 2 */
+#define EXTI_INTEN_INTEN3            BIT(3)                   /*!< interrupt from line 3 */
+#define EXTI_INTEN_INTEN4            BIT(4)                   /*!< interrupt from line 4 */
+#define EXTI_INTEN_INTEN5            BIT(5)                   /*!< interrupt from line 5 */
+#define EXTI_INTEN_INTEN6            BIT(6)                   /*!< interrupt from line 6 */
+#define EXTI_INTEN_INTEN7            BIT(7)                   /*!< interrupt from line 7 */
+#define EXTI_INTEN_INTEN8            BIT(8)                   /*!< interrupt from line 8 */
+#define EXTI_INTEN_INTEN9            BIT(9)                   /*!< interrupt from line 9 */
+#define EXTI_INTEN_INTEN10           BIT(10)                  /*!< interrupt from line 10 */
+#define EXTI_INTEN_INTEN11           BIT(11)                  /*!< interrupt from line 11 */
+#define EXTI_INTEN_INTEN12           BIT(12)                  /*!< interrupt from line 12 */
+#define EXTI_INTEN_INTEN13           BIT(13)                  /*!< interrupt from line 13 */
+#define EXTI_INTEN_INTEN14           BIT(14)                  /*!< interrupt from line 14 */
+#define EXTI_INTEN_INTEN15           BIT(15)                  /*!< interrupt from line 15 */
+#define EXTI_INTEN_INTEN16           BIT(16)                  /*!< interrupt from line 16 */
+#define EXTI_INTEN_INTEN17           BIT(17)                  /*!< interrupt from line 17 */
+#define EXTI_INTEN_INTEN18           BIT(18)                  /*!< interrupt from line 18 */
+#define EXTI_INTEN_INTEN19           BIT(19)                  /*!< interrupt from line 19 */
+#define EXTI_INTEN_INTEN20           BIT(20)                  /*!< interrupt from line 20 */
+#define EXTI_INTEN_INTEN21           BIT(21)                  /*!< interrupt from line 21 */
+#define EXTI_INTEN_INTEN22           BIT(22)                  /*!< interrupt from line 22 */
+#define EXTI_INTEN_INTEN23           BIT(23)                  /*!< interrupt from line 23 */
+#define EXTI_INTEN_INTEN24           BIT(24)                  /*!< interrupt from line 24 */
+#define EXTI_INTEN_INTEN25           BIT(25)                  /*!< interrupt from line 25 */
+#define EXTI_INTEN_INTEN26           BIT(26)                  /*!< interrupt from line 26 */
+#define EXTI_INTEN_INTEN27           BIT(27)                  /*!< interrupt from line 27 */
+
+/* EXTI_EVEN */
+#define EXTI_EVEN_EVEN0              BIT(0)                   /*!< event from line 0 */
+#define EXTI_EVEN_EVEN1              BIT(1)                   /*!< event from line 1 */
+#define EXTI_EVEN_EVEN2              BIT(2)                   /*!< event from line 2 */
+#define EXTI_EVEN_EVEN3              BIT(3)                   /*!< event from line 3 */
+#define EXTI_EVEN_EVEN4              BIT(4)                   /*!< event from line 4 */
+#define EXTI_EVEN_EVEN5              BIT(5)                   /*!< event from line 5 */
+#define EXTI_EVEN_EVEN6              BIT(6)                   /*!< event from line 6 */
+#define EXTI_EVEN_EVEN7              BIT(7)                   /*!< event from line 7 */
+#define EXTI_EVEN_EVEN8              BIT(8)                   /*!< event from line 8 */
+#define EXTI_EVEN_EVEN9              BIT(9)                   /*!< event from line 9 */
+#define EXTI_EVEN_EVEN10             BIT(10)                  /*!< event from line 10 */
+#define EXTI_EVEN_EVEN11             BIT(11)                  /*!< event from line 11 */
+#define EXTI_EVEN_EVEN12             BIT(12)                  /*!< event from line 12 */
+#define EXTI_EVEN_EVEN13             BIT(13)                  /*!< event from line 13 */
+#define EXTI_EVEN_EVEN14             BIT(14)                  /*!< event from line 14 */
+#define EXTI_EVEN_EVEN15             BIT(15)                  /*!< event from line 15 */
+#define EXTI_EVEN_EVEN16             BIT(16)                  /*!< event from line 16 */
+#define EXTI_EVEN_EVEN17             BIT(17)                  /*!< event from line 17 */
+#define EXTI_EVEN_EVEN18             BIT(18)                  /*!< event from line 18 */
+#define EXTI_EVEN_EVEN19             BIT(19)                  /*!< event from line 19 */
+#define EXTI_EVEN_EVEN20             BIT(20)                  /*!< event from line 20 */
+#define EXTI_EVEN_EVEN21             BIT(21)                  /*!< event from line 21 */
+#define EXTI_EVEN_EVEN22             BIT(22)                  /*!< event from line 22 */
+#define EXTI_EVEN_EVEN23             BIT(23)                  /*!< event from line 23 */
+#define EXTI_EVEN_EVEN24             BIT(24)                  /*!< event from line 24 */
+#define EXTI_EVEN_EVEN25             BIT(25)                  /*!< event from line 25 */
+#define EXTI_EVEN_EVEN26             BIT(26)                  /*!< event from line 26 */
+#define EXTI_EVEN_EVEN27             BIT(27)                  /*!< event from line 27 */
+
+/* EXTI_RTEN */
+#define EXTI_RTEN_RTEN0              BIT(0)                   /*!< rising edge from line 0 */
+#define EXTI_RTEN_RTEN1              BIT(1)                   /*!< rising edge from line 1 */
+#define EXTI_RTEN_RTEN2              BIT(2)                   /*!< rising edge from line 2 */
+#define EXTI_RTEN_RTEN3              BIT(3)                   /*!< rising edge from line 3 */
+#define EXTI_RTEN_RTEN4              BIT(4)                   /*!< rising edge from line 4 */
+#define EXTI_RTEN_RTEN5              BIT(5)                   /*!< rising edge from line 5 */
+#define EXTI_RTEN_RTEN6              BIT(6)                   /*!< rising edge from line 6 */
+#define EXTI_RTEN_RTEN7              BIT(7)                   /*!< rising edge from line 7 */
+#define EXTI_RTEN_RTEN8              BIT(8)                   /*!< rising edge from line 8 */
+#define EXTI_RTEN_RTEN9              BIT(9)                   /*!< rising edge from line 9 */
+#define EXTI_RTEN_RTEN10             BIT(10)                  /*!< rising edge from line 10 */
+#define EXTI_RTEN_RTEN11             BIT(11)                  /*!< rising edge from line 11 */
+#define EXTI_RTEN_RTEN12             BIT(12)                  /*!< rising edge from line 12 */
+#define EXTI_RTEN_RTEN13             BIT(13)                  /*!< rising edge from line 13 */
+#define EXTI_RTEN_RTEN14             BIT(14)                  /*!< rising edge from line 14 */
+#define EXTI_RTEN_RTEN15             BIT(15)                  /*!< rising edge from line 15 */
+#define EXTI_RTEN_RTEN16             BIT(16)                  /*!< rising edge from line 16 */
+#define EXTI_RTEN_RTEN17             BIT(17)                  /*!< rising edge from line 17 */
+#define EXTI_RTEN_RTEN18             BIT(18)                  /*!< rising edge from line 18 */
+#define EXTI_RTEN_RTEN19             BIT(19)                  /*!< rising edge from line 19 */
+#define EXTI_RTEN_RTEN21             BIT(21)                  /*!< rising edge from line 21 */
+#define EXTI_RTEN_RTEN22             BIT(22)                  /*!< rising edge from line 22 */
+
+/* EXTI_FTEN */
+#define EXTI_FTEN_FTEN0              BIT(0)                   /*!< falling edge from line 0 */
+#define EXTI_FTEN_FTEN1              BIT(1)                   /*!< falling edge from line 1 */
+#define EXTI_FTEN_FTEN2              BIT(2)                   /*!< falling edge from line 2 */
+#define EXTI_FTEN_FTEN3              BIT(3)                   /*!< falling edge from line 3 */
+#define EXTI_FTEN_FTEN4              BIT(4)                   /*!< falling edge from line 4 */
+#define EXTI_FTEN_FTEN5              BIT(5)                   /*!< falling edge from line 5 */
+#define EXTI_FTEN_FTEN6              BIT(6)                   /*!< falling edge from line 6 */
+#define EXTI_FTEN_FTEN7              BIT(7)                   /*!< falling edge from line 7 */
+#define EXTI_FTEN_FTEN8              BIT(8)                   /*!< falling edge from line 8 */
+#define EXTI_FTEN_FTEN9              BIT(9)                   /*!< falling edge from line 9 */
+#define EXTI_FTEN_FTEN10             BIT(10)                  /*!< falling edge from line 10 */
+#define EXTI_FTEN_FTEN11             BIT(11)                  /*!< falling edge from line 11 */
+#define EXTI_FTEN_FTEN12             BIT(12)                  /*!< falling edge from line 12 */
+#define EXTI_FTEN_FTEN13             BIT(13)                  /*!< falling edge from line 13 */
+#define EXTI_FTEN_FTEN14             BIT(14)                  /*!< falling edge from line 14 */
+#define EXTI_FTEN_FTEN15             BIT(15)                  /*!< falling edge from line 15 */
+#define EXTI_FTEN_FTEN16             BIT(16)                  /*!< falling edge from line 16 */
+#define EXTI_FTEN_FTEN17             BIT(17)                  /*!< falling edge from line 17 */
+#define EXTI_FTEN_FTEN18             BIT(18)                  /*!< falling edge from line 18 */
+#define EXTI_FTEN_FTEN19             BIT(19)                  /*!< falling edge from line 19 */
+#define EXTI_FTEN_FTEN21             BIT(21)                  /*!< falling edge from line 21 */
+#define EXTI_FTEN_FTEN22             BIT(22)                  /*!< falling edge from line 22 */
+
+/* EXTI_SWIEV */
+#define EXTI_SWIEV_SWIEV0            BIT(0)                   /*!< software interrupt/event request from line 0 */
+#define EXTI_SWIEV_SWIEV1            BIT(1)                   /*!< software interrupt/event request from line 1 */
+#define EXTI_SWIEV_SWIEV2            BIT(2)                   /*!< software interrupt/event request from line 2 */
+#define EXTI_SWIEV_SWIEV3            BIT(3)                   /*!< software interrupt/event request from line 3 */
+#define EXTI_SWIEV_SWIEV4            BIT(4)                   /*!< software interrupt/event request from line 4 */
+#define EXTI_SWIEV_SWIEV5            BIT(5)                   /*!< software interrupt/event request from line 5 */
+#define EXTI_SWIEV_SWIEV6            BIT(6)                   /*!< software interrupt/event request from line 6 */
+#define EXTI_SWIEV_SWIEV7            BIT(7)                   /*!< software interrupt/event request from line 7 */
+#define EXTI_SWIEV_SWIEV8            BIT(8)                   /*!< software interrupt/event request from line 8 */
+#define EXTI_SWIEV_SWIEV9            BIT(9)                   /*!< software interrupt/event request from line 9 */
+#define EXTI_SWIEV_SWIEV10           BIT(10)                  /*!< software interrupt/event request from line 10 */
+#define EXTI_SWIEV_SWIEV11           BIT(11)                  /*!< software interrupt/event request from line 11 */
+#define EXTI_SWIEV_SWIEV12           BIT(12)                  /*!< software interrupt/event request from line 12 */
+#define EXTI_SWIEV_SWIEV13           BIT(13)                  /*!< software interrupt/event request from line 13 */
+#define EXTI_SWIEV_SWIEV14           BIT(14)                  /*!< software interrupt/event request from line 14 */
+#define EXTI_SWIEV_SWIEV15           BIT(15)                  /*!< software interrupt/event request from line 15 */
+#define EXTI_SWIEV_SWIEV16           BIT(16)                  /*!< software interrupt/event request from line 16 */
+#define EXTI_SWIEV_SWIEV17           BIT(17)                  /*!< software interrupt/event request from line 17 */
+#define EXTI_SWIEV_SWIEV18           BIT(18)                  /*!< software interrupt/event request from line 18 */
+#define EXTI_SWIEV_SWIEV19           BIT(19)                  /*!< software interrupt/event request from line 19 */
+#define EXTI_SWIEV_SWIEV21           BIT(21)                  /*!< software interrupt/event request from line 21 */
+#define EXTI_SWIEV_SWIEV22           BIT(22)                  /*!< software interrupt/event request from line 22 */
+
+/* EXTI_PD */
+#define EXTI_PD_PD0                  BIT(0)                   /*!< interrupt/event pending status from line 0 */
+#define EXTI_PD_PD1                  BIT(1)                   /*!< interrupt/event pending status from line 1 */
+#define EXTI_PD_PD2                  BIT(2)                   /*!< interrupt/event pending status from line 2 */
+#define EXTI_PD_PD3                  BIT(3)                   /*!< interrupt/event pending status from line 3 */
+#define EXTI_PD_PD4                  BIT(4)                   /*!< interrupt/event pending status from line 4 */
+#define EXTI_PD_PD5                  BIT(5)                   /*!< interrupt/event pending status from line 5 */
+#define EXTI_PD_PD6                  BIT(6)                   /*!< interrupt/event pending status from line 6 */
+#define EXTI_PD_PD7                  BIT(7)                   /*!< interrupt/event pending status from line 7 */
+#define EXTI_PD_PD8                  BIT(8)                   /*!< interrupt/event pending status from line 8 */
+#define EXTI_PD_PD9                  BIT(9)                   /*!< interrupt/event pending status from line 9 */
+#define EXTI_PD_PD10                 BIT(10)                  /*!< interrupt/event pending status from line 10 */
+#define EXTI_PD_PD11                 BIT(11)                  /*!< interrupt/event pending status from line 11 */
+#define EXTI_PD_PD12                 BIT(12)                  /*!< interrupt/event pending status from line 12 */
+#define EXTI_PD_PD13                 BIT(13)                  /*!< interrupt/event pending status from line 13 */
+#define EXTI_PD_PD14                 BIT(14)                  /*!< interrupt/event pending status from line 14 */
+#define EXTI_PD_PD15                 BIT(15)                  /*!< interrupt/event pending status from line 15 */
+#define EXTI_PD_PD16                 BIT(16)                  /*!< interrupt/event pending status from line 16 */
+#define EXTI_PD_PD17                 BIT(17)                  /*!< interrupt/event pending status from line 17 */
+#define EXTI_PD_PD18                 BIT(18)                  /*!< interrupt/event pending status from line 18 */
+#define EXTI_PD_PD19                 BIT(19)                  /*!< interrupt/event pending status from line 19 */
+#define EXTI_PD_PD21                 BIT(21)                  /*!< interrupt/event pending status from line 21 */
+#define EXTI_PD_PD22                 BIT(22)                  /*!< interrupt/event pending status from line 22 */
+
+/* constants definitions */
+/* EXTI line number */
+typedef enum
+{ 
+    EXTI_0      = BIT(0),                                     /*!< EXTI line 0 */
+    EXTI_1      = BIT(1),                                     /*!< EXTI line 1 */
+    EXTI_2      = BIT(2),                                     /*!< EXTI line 2 */
+    EXTI_3      = BIT(3),                                     /*!< EXTI line 3 */
+    EXTI_4      = BIT(4),                                     /*!< EXTI line 4 */
+    EXTI_5      = BIT(5),                                     /*!< EXTI line 5 */
+    EXTI_6      = BIT(6),                                     /*!< EXTI line 6 */
+    EXTI_7      = BIT(7),                                     /*!< EXTI line 7 */
+    EXTI_8      = BIT(8),                                     /*!< EXTI line 8 */
+    EXTI_9      = BIT(9),                                     /*!< EXTI line 9 */
+    EXTI_10     = BIT(10),                                    /*!< EXTI line 10 */
+    EXTI_11     = BIT(11),                                    /*!< EXTI line 11 */
+    EXTI_12     = BIT(12),                                    /*!< EXTI line 12 */
+    EXTI_13     = BIT(13),                                    /*!< EXTI line 13 */
+    EXTI_14     = BIT(14),                                    /*!< EXTI line 14 */
+    EXTI_15     = BIT(15),                                    /*!< EXTI line 15 */
+    EXTI_16     = BIT(16),                                    /*!< EXTI line 16 */
+    EXTI_17     = BIT(17),                                    /*!< EXTI line 17 */
+    EXTI_18     = BIT(18),                                    /*!< EXTI line 18 */
+    EXTI_19     = BIT(19),                                    /*!< EXTI line 19 */
+    EXTI_20     = BIT(20),                                    /*!< EXTI line 20 */    
+    EXTI_21     = BIT(21),                                    /*!< EXTI line 21 */
+    EXTI_22     = BIT(22),                                    /*!< EXTI line 22 */
+    EXTI_23     = BIT(23),                                    /*!< EXTI line 23 */
+    EXTI_24     = BIT(24),                                    /*!< EXTI line 24 */
+    EXTI_25     = BIT(25),                                    /*!< EXTI line 25 */
+    EXTI_26     = BIT(26),                                    /*!< EXTI line 26 */
+    EXTI_27     = BIT(27),                                    /*!< EXTI line 27 */
+}exti_line_enum;
+
+/* external interrupt and event */
+typedef enum
+{
+    EXTI_INTERRUPT   = 0,                                     /*!< EXTI interrupt mode */
+    EXTI_EVENT                                                /*!< EXTI event mode */
+}exti_mode_enum;
+
+/* interrupt trigger mode */
+typedef enum
+{ 
+    EXTI_TRIG_RISING = 0,                                     /*!< EXTI rising edge trigger */
+    EXTI_TRIG_FALLING,                                        /*!< EXTI falling edge trigger */
+    EXTI_TRIG_BOTH,                                           /*!< EXTI rising and falling edge trigger */
+    EXTI_TRIG_NONE                                            /*!< without rising edge or falling edge trigger */
+}exti_trig_type_enum;
+
+/* function declarations */
+/* deinitialize the EXTI */
+void exti_deinit(void);
+/* initialize the EXTI, enable the configuration of EXTI initialize */
+void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
+/* enable the interrupts from EXTI line x */
+void exti_interrupt_enable(exti_line_enum linex);
+/* disable the interrupts from EXTI line x */
+void exti_interrupt_disable(exti_line_enum linex);
+/* enable the events from EXTI line x */
+void exti_event_enable(exti_line_enum linex);
+/* disable the events from EXTI line x */
+void exti_event_disable(exti_line_enum linex);
+
+/* enable EXTI software interrupt event */
+void exti_software_interrupt_enable(exti_line_enum linex);
+/* disable EXTI software interrupt event */
+void exti_software_interrupt_disable(exti_line_enum linex);
+/* get EXTI line x pending flag */
+FlagStatus exti_flag_get(exti_line_enum linex);
+/* clear EXTI line x pending flag */
+void exti_flag_clear(exti_line_enum linex);
+/* get EXTI line x flag when the interrupt flag is set */
+FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
+/* clear EXTI line x pending flag */
+void exti_interrupt_flag_clear(exti_line_enum linex);
+
+#endif /* GD32F3X0_EXTI_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_fmc.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_fmc.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_fmc.h
+    \file  gd32f3x0_fmc.h
     \brief definitions for the FMC
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,34 +33,34 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_FMC_H
-#define GD32F1X0_FMC_H
 
-#include "gd32f1x0.h"
+#ifndef GD32F3X0_FMC_H
+#define GD32F3X0_FMC_H
+
+#include "gd32f3x0.h"
 
 /* FMC and option byte definition */
 #define FMC                     FMC_BASE                    /*!< FMC register base address */
 #define OB                      OB_BASE                     /*!< option byte base address */
 
 /* registers definitions */
-#define FMC_WS                  REG32((FMC) + 0x00U)        /*!< FMC wait state register */
-#define FMC_KEY                 REG32((FMC) + 0x04U)        /*!< FMC unlock key register */
-#define FMC_OBKEY               REG32((FMC) + 0x08U)        /*!< FMC option bytes unlock key register */
-#define FMC_STAT                REG32((FMC) + 0x0CU)        /*!< FMC status register */
-#define FMC_CTL                 REG32((FMC) + 0x10U)        /*!< FMC control register */
-#define FMC_ADDR                REG32((FMC) + 0x14U)        /*!< FMC address register */
-#define FMC_OBSTAT              REG32((FMC) + 0x1CU)        /*!< FMC option bytes status register */
-#define FMC_WP                  REG32((FMC) + 0x20U)        /*!< FMC write protection register */
-#define FMC_WSEN                REG32((FMC) + 0xFCU)        /*!< FMC wait state enable register  */
-#define FMC_PID                 REG32((FMC) + 0x100U)       /*!< FMC product ID register */
-
-#define OP_BYTE(x)              REG8((OB) + ((uint32_t)((uint32_t)0x02U * (x))))     /*!< option byte value */
-#define OB_SPC                  REG8((OB) + 0x00U)                                   /*!< option byte security protection value */
-#define OB_USER                 REG8((OB) + 0x02U)                                   /*!< option byte user value */
-#define OB_DATA0                REG8((OB) + 0x04U)                                   /*!< option byte data0 value */
-#define OB_DATA1                REG8((OB) + 0x06U)                                   /*!< option byte data1 value */
-#define OB_WP0                  REG8((OB) + 0x08U)                                   /*!< option byte write protection 0 value */
-#define OB_WP1                  REG8((OB) + 0x0AU)                                   /*!< option byte write protection 1 value */
+#define FMC_WS                  REG32(FMC + 0x00000000U)    /*!< FMC wait state register */
+#define FMC_KEY                 REG32(FMC + 0x00000004U)    /*!< FMC unlock key register */
+#define FMC_OBKEY               REG32(FMC + 0x00000008U)    /*!< FMC option bytes unlock key register */
+#define FMC_STAT                REG32(FMC + 0x0000000CU)    /*!< FMC status register */
+#define FMC_CTL                 REG32(FMC + 0x00000010U)    /*!< FMC control register */
+#define FMC_ADDR                REG32(FMC + 0x00000014U)    /*!< FMC address register */
+#define FMC_OBSTAT              REG32(FMC + 0x0000001CU)    /*!< FMC option bytes status register */
+#define FMC_WP                  REG32(FMC + 0x00000020U)    /*!< FMC write protection register */
+#define FMC_WSEN                REG32(FMC + 0x000000FCU)    /*!< FMC wait state enable register  */
+#define FMC_PID                 REG32(FMC + 0x00000100U)    /*!< FMC product ID register */
+
+#define OB_SPC                  REG16(OB + 0x00000000U)     /*!< option byte security protection value */
+#define OB_USER                 REG16(OB + 0x00000002U)     /*!< option byte user value*/
+#define OB_DATA0                REG16(OB + 0x00000004U)     /*!< option byte data bit[7:0] value*/
+#define OB_DATA1                REG16(OB + 0x00000006U)     /*!< option byte data bit[15:8] value*/
+#define OB_WP0                  REG16(OB + 0x00000008U)     /*!< option byte write protection 0 */
+#define OB_WP1                  REG16(OB + 0x0000000AU)     /*!< option byte write protection 1 */
 
 /* bits definitions */
 /* FMC_WS */
@@ -79,7 +76,7 @@ OF SUCH DAMAGE.
 #define FMC_STAT_BUSY           BIT(0)                      /*!< flash busy flag bit */
 #define FMC_STAT_PGERR          BIT(2)                      /*!< flash program error flag bit */
 #define FMC_STAT_WPERR          BIT(4)                      /*!< flash write protection error flag bit */
-#define FMC_STAT_ENDF           BIT(5)                      /*!< flash end of operation flag bit */
+#define FMC_STAT_ENDF           BIT(5)                      /*!< end of operation flag bit */
 
 /* FMC_CTL */
 #define FMC_CTL_PG              BIT(0)                      /*!< main flash program command bit */
@@ -99,16 +96,14 @@ OF SUCH DAMAGE.
 
 /* FMC_OBSTAT */
 #define FMC_OBSTAT_OBERR        BIT(0)                      /*!< option bytes read error bit */
-#define FMC_OBSTAT_PLVL_BIT0    BIT(1)                      /*!< protection level bit 0 */
-#define FMC_OBSTAT_PLVL_BIT1    BIT(2)                      /*!< protection level bit 1 */
+#define FMC_OBSTAT_PLEVEL_BIT0  BIT(1)                      /*!< protection level bit 0 */
+#define FMC_OBSTAT_PLEVEL_BIT1  BIT(2)                      /*!< protection level bit 1 */
 #define FMC_OBSTAT_USER         BITS(8,15)                  /*!< option bytes user bits */
 #define FMC_OBSTAT_DATA         BITS(16,31)                 /*!< option byte data bits */
 
 /* FMC_WSEN */
 #define FMC_WSEN_WSEN           BIT(0)                      /*!< FMC wait state enable bit */
-#ifdef GD32F170_190
 #define FMC_WSEN_BPEN           BIT(1)                      /*!< FMC bit program enable bit */
-#endif /* GD32F170_190 */
 
 /* FMC_PID */
 #define FMC_PID_PID             BITS(0,31)                  /*!< product ID bits */
@@ -125,97 +120,69 @@ typedef enum
     FMC_OB_HSPC                                             /*!< option byte security protection code high */
 }fmc_state_enum;
 
+/* option byte parameter */
+typedef struct 
+{
+    uint8_t spc;                                            /*!< option byte parameter spc */
+    uint8_t user;                                           /*!< option byte parameter user */
+    uint8_t data0;                                          /*!< option byte parameter data0 */
+    uint8_t data1;                                          /*!< option byte parameter data1 */
+    uint8_t wp0;                                            /*!< option byte parameter wp0 */
+    uint8_t wp1;                                            /*!< option byte parameter wp1 */
+}ob_parm_struct;
+
 /* unlock key */
-#define UNLOCK_KEY0                ((uint32_t)0x45670123U)  /*!< unlock key 0 */
-#define UNLOCK_KEY1                ((uint32_t)0xCDEF89ABU)  /*!< unlock key 1 */
+#define UNLOCK_KEY0             ((uint32_t)0x45670123U)     /*!< unlock key 0 */
+#define UNLOCK_KEY1             ((uint32_t)0xCDEF89ABU)     /*!< unlock key 1 */
 
 /* wait state counter value */
-#define WS_WSCNT_0                 ((uint8_t)0x00U)         /*!< 0 wait state added */
-#define WS_WSCNT_1                 ((uint8_t)0x01U)         /*!< 1 wait state added */
-#define WS_WSCNT_2                 ((uint8_t)0x02U)         /*!< 2 wait state added */
+#define WS_WSCNT_0              ((uint8_t)0x00U)            /*!< 0 wait state added */
+#define WS_WSCNT_1              ((uint8_t)0x01U)            /*!< 1 wait state added */
+#define WS_WSCNT_2              ((uint8_t)0x02U)            /*!< 2 wait state added */
 
 /* read protect configure */
-#define FMC_NSPC                   ((uint8_t)0xA5U)         /*!< no security protection */
-#define FMC_LSPC                   ((uint8_t)0xBBU)         /*!< low security protection, any value except 0xA5 or 0xCC */
-#define FMC_HSPC                   ((uint8_t)0xCCU)         /*!< high security protection */
-
-/* option byte write protection mask */
-#define OB_LWP                     ((uint16_t)0x00FFU)  /*!< write protection low bits */
-#define OB_HWP                     ((uint16_t)0xFF00U)  /*!< write protection high bits */
+#define FMC_NSPC                ((uint8_t)0xA5U)            /*!< no security protection */
+#define FMC_LSPC                ((uint8_t)0xBBU)            /*!< low security protection, any value except 0xA5 or 0xCC */
+#define FMC_HSPC                ((uint8_t)0xCCU)            /*!< high security protection */
 
-/* option byte software/hardware free watchdog timer */  
-#define OB_FWDGT_HW                ((uint8_t)(~BIT(0)))     /*!< hardware free watchdog timer */
-#define OB_FWDGT_SW                ((uint8_t)BIT(0))        /*!< software free watchdog timer */
+/* option byte write protection */
+#define OB_LWP                  ((uint32_t)0x000000FFU)     /*!< write protection low bits */
+#define OB_HWP                  ((uint32_t)0x0000FF00U)     /*!< write protection high bits */
 
-/* option byte reset or not entering deep sleep mode */
-#define OB_DEEPSLEEP_RST           ((uint8_t)(~BIT(1)))     /*!< generate a reset instead of entering deepsleep mode */
-#define OB_DEEPSLEEP_NRST          ((uint8_t)BIT(1))        /*!< no reset when entering deepsleep mode */
-
-/* option byte reset or not entering standby mode */
-#define OB_STDBY_RST               ((uint8_t)(~BIT(2)))     /*!< generate a reset instead of entering standby mode */
-#define OB_STDBY_NRST              ((uint8_t)BIT(2))        /*!< no reset when entering standby mode */
-
-/* option byte OB_BOOT1_n set */
-#define OB_BOOT1_SET_1             ((uint8_t)(~BIT(4)))     /*!< BOOT1 bit is 1 */
-#define OB_BOOT1_SET_0             ((uint8_t)BIT(4))        /*!< BOOT1 bit is 0 */
-
-/* option byte VDDA monitor enable/disable */
-#define OB_VDDA_DISABLE            ((uint8_t)(~BIT(5)))     /*!< disable VDDA monitor */
-#define OB_VDDA_ENABLE             ((uint8_t)BIT(5))        /*!< enable VDDA monitor */
-
-/* option byte SRAM parity enable/disable */
-#define OB_SRAM_PARITY_ENABLE      ((uint8_t)(~BIT(6)))     /*!< enable SRAM parity check */
-#define OB_SRAM_PARITY_DISABLE     ((uint8_t)BIT(6))        /*!< disable SRAM parity check */
+#define OB_FWDGT_HW             ((uint8_t)(~BIT(0)))        /*!< hardware free watchdog timer */
+#define OB_DEEPSLEEP_RST        ((uint8_t)(~BIT(1)))        /*!< generate a reset instead of entering deepsleep mode */
+#define OB_STDBY_RST            ((uint8_t)(~BIT(2)))        /*!< generate a reset instead of entering standby mode */
+#define OB_BOOT1_SET_1          ((uint8_t)(~BIT(4)))        /*!< BOOT1 bit is 1 */
+#define OB_VDDA_DISABLE         ((uint8_t)(~BIT(5)))        /*!< disable VDDA monitor */
+#define OB_SRAM_PARITY_ENABLE   ((uint8_t)(~BIT(6)))        /*!< enable SRAM parity check */
 
 /* option byte security protection level in FMC_OBSTAT register */
-#define OB_OBSTAT_PLEVEL_NO        ((uint32_t)0x00000000U)  /*!< no security protection */
-#define OB_OBSTAT_PLEVEL_LOW       ((uint32_t)0x00000002U)  /*!< low security protection */
-#define OB_OBSTAT_PLEVEL_HIGH      ((uint32_t)0x00000006U)  /*!< high security protection */
+#define OB_OBSTAT_PLEVEL_NO     ((uint32_t)0x00000000U)     /*!< no security protection */
+#define OB_OBSTAT_PLEVEL_LOW    ((uint32_t)0x00000002U)     /*!< low security protection */
+#define OB_OBSTAT_PLEVEL_HIGH   ((uint32_t)0x00000006U)     /*!< high security protection */
 
-/* option byte user mask */
-#define OB_USER_MASK               ((uint8_t)0x88U)         /*!< OB_USER reserved bit mask */
+#define OB_USER_DEFAULT         ((uint8_t)0xDFU)            /*!< OB_USER default value */
 
-/* option byte data mask */
-#define OB_LDATA                   ((uint16_t)0x00FFU)  /*!< option byte data address 0 */
-#define OB_HDATA                   ((uint16_t)0xFF00U)  /*!< option byte data address 1 */
+/* option byte parameter address */
+#define OB_SPC_ADDR             (uint32_t)(OB + 0x00000000U)/*!< option byte spc address */
+#define OB_USER_ADDR            (uint32_t)(OB + 0x00000002U)/*!< option byte user address */
+#define OB_DATA_ADDR0           (uint32_t)(OB + 0x00000004U)/*!< option byte data address 0 */
+#define OB_DATA_ADDR1           (uint32_t)(OB + 0x00000006U)/*!< option byte data address 1 */
+#define OB_WP_ADDR0             (uint32_t)(OB + 0x00000008U)/*!< option byte wp address 0 */
+#define OB_WP_ADDR1             (uint32_t)(OB + 0x0000000AU)/*!< option byte wp address 1 */
 
 /* FMC flags */
-#define FMC_FLAG_BUSY              FMC_STAT_BUSY            /*!< FMC busy flag */
-#define FMC_FLAG_PGERR             FMC_STAT_PGERR           /*!< FMC programming error flag */
-#define FMC_FLAG_WPERR             FMC_STAT_WPERR           /*!< FMC write protection error flag */
-#define FMC_FLAG_END               FMC_STAT_ENDF            /*!< FMC end of programming flag */
+#define FMC_FLAG_BUSY           FMC_STAT_BUSY               /*!< FMC busy flag */
+#define FMC_FLAG_PGERR          FMC_STAT_PGERR              /*!< FMC programming error flag */
+#define FMC_FLAG_WPERR          FMC_STAT_WPERR              /*!< FMC write protection error flag */
+#define FMC_FLAG_END            FMC_STAT_ENDF               /*!< FMC end of programming flag */
 
 /* FMC interrupt enable */
-#define FMC_INT_END                FMC_CTL_ENDIE            /*!< enable FMC end of operation interrupt */
-#define FMC_INT_ERR                FMC_CTL_ERRIE            /*!< enable FMC error interrupt */
-
-/* FMC interrupt flags */
-#define FMC_INT_FLAG_PGERR         FMC_STAT_PGERR           /*!< FMC programming error interrupt flag */
-#define FMC_INT_FLAG_WPERR         FMC_STAT_WPERR           /*!< FMC write protection error interrupt flag */
-#define FMC_INT_FLAG_END           FMC_STAT_ENDF            /*!< FMC end of programming interrupt flag */
-
-/* option bytes write protection */
-#define OB_WP_NONE                 ((uint16_t)0x0000U)      /*!< disable all erase/program protection */
-#define OB_WP_0                    ((uint16_t)0x0001U)      /*!< erase/program protection of sector 0 */
-#define OB_WP_1                    ((uint16_t)0x0002U)      /*!< erase/program protection of sector 1 */
-#define OB_WP_2                    ((uint16_t)0x0004U)      /*!< erase/program protection of sector 2 */
-#define OB_WP_3                    ((uint16_t)0x0008U)      /*!< erase/program protection of sector 3 */
-#define OB_WP_4                    ((uint16_t)0x0010U)      /*!< erase/program protection of sector 4 */
-#define OB_WP_5                    ((uint16_t)0x0020U)      /*!< erase/program protection of sector 5 */
-#define OB_WP_6                    ((uint16_t)0x0040U)      /*!< erase/program protection of sector 6 */
-#define OB_WP_7                    ((uint16_t)0x0080U)      /*!< erase/program protection of sector 7 */
-#define OB_WP_8                    ((uint16_t)0x0100U)      /*!< erase/program protection of sector 8 */
-#define OB_WP_9                    ((uint16_t)0x0200U)      /*!< erase/program protection of sector 9 */
-#define OB_WP_10                   ((uint16_t)0x0400U)      /*!< erase/program protection of sector 10 */
-#define OB_WP_11                   ((uint16_t)0x0800U)      /*!< erase/program protection of sector 11 */
-#define OB_WP_12                   ((uint16_t)0x1000U)      /*!< erase/program protection of sector 12 */
-#define OB_WP_13                   ((uint16_t)0x2000U)      /*!< erase/program protection of sector 13 */
-#define OB_WP_14                   ((uint16_t)0x4000U)      /*!< erase/program protection of sector 14 */
-#define OB_WP_15                   ((uint16_t)0x8000U)      /*!< erase/program protection of sector 15 */
-#define OB_WP_ALL                  ((uint16_t)0xFFFFU)      /*!< erase/program protection of all sectors */
+#define FMC_INTEN_END           FMC_CTL_ENDIE               /*!< enable FMC end of operation interrupt */
+#define FMC_INTEN_ERR           FMC_CTL_ERRIE               /*!< enable FMC error interrupt */
 
 /* FMC time out */
-#define FMC_TIMEOUT_COUNT          ((uint32_t)0x000F0000U)  /*!< count to judge of FMC timeout */
+#define FMC_TIMEOUT_COUNT       ((uint32_t)0x000F0000U)     /*!< count to judge of FMC timeout */
 
 /* function declarations */
 /* FMC main memory programming functions */
@@ -237,10 +204,8 @@ fmc_state_enum fmc_mass_erase(void);
 fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
 /* FMC program a half word at the corresponding address */
 fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
-#ifdef GD32F170_190
 /* FMC program a word at the corresponding address without erasing */
 fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data);
-#endif /* GD32F170_190 */
 
 /* FMC option bytes programming functions */
 /* unlock the option byte operation */
@@ -258,7 +223,7 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
 /* write the FMC option byte user */
 fmc_state_enum ob_user_write(uint8_t ob_user);
 /* write the FMC option byte data */
-fmc_state_enum ob_data_program(uint16_t ob_data);
+fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
 /* get the FMC option byte OB_USER */
 uint8_t ob_user_get(void);
 /* get the FMC option byte OB_DATA */
@@ -277,9 +242,17 @@ void fmc_interrupt_disable(uint32_t interrupt);
 FlagStatus fmc_flag_get(uint32_t flag);
 /* clear the FMC pending flag */
 void fmc_flag_clear(uint32_t flag);
-/* get FMC interrupt flag state */
+/* get interrupt flag set or reset */
 FlagStatus fmc_interrupt_flag_get(uint32_t flag);
-/* clear FMC interrupt flag state */
+/* clear the FMC interrupt pending flag */
 void fmc_interrupt_flag_clear(uint32_t flag);
-
-#endif /* GD32F1X0_FMC_H */
+/* return the FMC state */
+fmc_state_enum fmc_state_get(void);
+/* check FMC ready or not */
+fmc_state_enum fmc_ready_wait(uint32_t timeout);
+/* get current option byte value */
+void ob_parm_get(ob_parm_struct *ob_parm);
+/* modify the target option byte depending on the original value */
+void ob_value_modify(uint32_t address, uint16_t value,ob_parm_struct *ob_parm);
+
+#endif /* GD32F3X0_FMC_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_fwdgt.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_fwdgt.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_fwdgt.h
-    \brief definitions for the FWDGT 
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \file  gd32f3x0_fwdgt.h
+    \brief definitions for the FWDGT
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,76 +33,79 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_FWDGT_H
-#define GD32F1X0_FWDGT_H
 
-#include "gd32f1x0.h"
+#ifndef GD32F3X0_FWDGT_H
+#define GD32F3X0_FWDGT_H
+
+#include "gd32f3x0.h"
 
 /* FWDGT definitions */
 #define FWDGT                       FWDGT_BASE
 
 /* registers definitions */
-#define FWDGT_CTL                   REG32((FWDGT) + 0x00U)           /*!< FWDGT control register */
-#define FWDGT_PSC                   REG32((FWDGT) + 0x04U)           /*!< FWDGT prescaler register */
-#define FWDGT_RLD                   REG32((FWDGT) + 0x08U)           /*!< FWDGT reload register */
-#define FWDGT_STAT                  REG32((FWDGT) + 0x0CU)           /*!< FWDGT status register */
-#define FWDGT_WND                   REG32((FWDGT) + 0x10U)           /*!< FWDGT window register */
+#define FWDGT_CTL                   REG32(FWDGT + 0x00000000U)                 /*!< FWDGT control register */
+#define FWDGT_PSC                   REG32(FWDGT + 0x00000004U)                 /*!< FWDGT prescaler register */
+#define FWDGT_RLD                   REG32(FWDGT + 0x00000008U)                 /*!< FWDGT reload register */
+#define FWDGT_STAT                  REG32(FWDGT + 0x0000000CU)                 /*!< FWDGT status register */
+#define FWDGT_WND                   REG32(FWDGT + 0x00000010U)                 /*!< FWDGT window register */
 
 /* bits definitions */
 /* FWDGT_CTL */
-#define FWDGT_CTL_CMD               BITS(0,15)                      /*!< FWDGT command value */
+#define FWDGT_CTL_CMD               BITS(0,15)                                 /*!< FWDGT command value */
 
 /* FWDGT_PSC */
-#define FWDGT_PSC_PSC               BITS(0,2)                       /*!< FWDGT prescaler divider value */
+#define FWDGT_PSC_PSC               BITS(0,2)                                  /*!< FWDGT prescaler divider value */
 
 /* FWDGT_RLD */
-#define FWDGT_RLD_RLD               BITS(0,11)                      /*!< FWDGT counter reload value */
+#define FWDGT_RLD_RLD               BITS(0,11)                                 /*!< FWDGT counter reload value */
 
 /* FWDGT_STAT */
-#define FWDGT_STAT_PUD              BIT(0)                          /*!< FWDGT prescaler divider value update */
-#define FWDGT_STAT_RUD              BIT(1)                          /*!< FWDGT counter reload value update */
-#define FWDGT_STAT_WUD              BIT(2)                          /*!< FWDGT counter window value update */
+#define FWDGT_STAT_PUD              BIT(0)                                     /*!< FWDGT prescaler divider value update */
+#define FWDGT_STAT_RUD              BIT(1)                                     /*!< FWDGT counter reload value update */
+#define FWDGT_STAT_WUD              BIT(2)                                     /*!< FWDGT counter window value update */
 
 /* FWDGT_WND */
-#define FWDGT_WND_WND               BITS(0,11)                      /*!< FWDGT counter window value */
+#define FWDGT_WND_WND               BITS(0,11)                                 /*!< FWDGT counter window value */
 
 /* constants definitions */
-/* ctl register value */
-#define CTL_CMD(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0U))  /*!< write value to FWDGT_CTL_CMD bit field */
+/* FWDGT_CTL register value */
+#define CTL_CMD(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0U))   /*!< write value to FWDGT_CTL_CMD bit field */
 
-/* psc register value */
+/* FWDGT_PSC register value */
 #define PSC_PSC(regval)             (BITS(0,2) & ((uint32_t)(regval) << 0U))
-#define FWDGT_PSC_DIV4              ((uint8_t)PSC_PSC(0))           /*!< FWDGT prescaler set to 4 */
-#define FWDGT_PSC_DIV8              ((uint8_t)PSC_PSC(1))           /*!< FWDGT prescaler set to 8 */
-#define FWDGT_PSC_DIV16             ((uint8_t)PSC_PSC(2))           /*!< FWDGT prescaler set to 16 */
-#define FWDGT_PSC_DIV32             ((uint8_t)PSC_PSC(3))           /*!< FWDGT prescaler set to 32 */
-#define FWDGT_PSC_DIV64             ((uint8_t)PSC_PSC(4))           /*!< FWDGT prescaler set to 64 */
-#define FWDGT_PSC_DIV128            ((uint8_t)PSC_PSC(5))           /*!< FWDGT prescaler set to 128 */
-#define FWDGT_PSC_DIV256            ((uint8_t)PSC_PSC(6))           /*!< FWDGT prescaler set to 256 */
+#define FWDGT_PSC_DIV4              ((uint8_t)PSC_PSC(0))                      /*!< FWDGT prescaler set to 4 */
+#define FWDGT_PSC_DIV8              ((uint8_t)PSC_PSC(1))                      /*!< FWDGT prescaler set to 8 */
+#define FWDGT_PSC_DIV16             ((uint8_t)PSC_PSC(2))                      /*!< FWDGT prescaler set to 16 */
+#define FWDGT_PSC_DIV32             ((uint8_t)PSC_PSC(3))                      /*!< FWDGT prescaler set to 32 */
+#define FWDGT_PSC_DIV64             ((uint8_t)PSC_PSC(4))                      /*!< FWDGT prescaler set to 64 */
+#define FWDGT_PSC_DIV128            ((uint8_t)PSC_PSC(5))                      /*!< FWDGT prescaler set to 128 */
+#define FWDGT_PSC_DIV256            ((uint8_t)PSC_PSC(6))                      /*!< FWDGT prescaler set to 256 */
 
-/* rld register value */
-#define RLD_RLD(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0U))  /*!< write value to FWDGT_RLD_RLD bit field */
+/* FWDGT_RLD register value */
+#define RLD_RLD(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0U))   /*!< write value to FWDGT_RLD_RLD bit field */
 
-/* wnd register value */
-#define WND_WND(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0U))  /*!< write value to FWDGT_WND_WND bit field */
+/* FWDGT_WND register value */
+#define WND_WND(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0U))   /*!< write value to FWDGT_WND_WND bit field */
 
 /* control value */
-#define FWDGT_WRITEACCESS_ENABLE    ((uint16_t)0x5555U)              /*!< FWDGT_CTL bits write access enable value */
-#define FWDGT_WRITEACCESS_DISABLE   ((uint16_t)0x0000U)              /*!< FWDGT_CTL bits write access disable value */
-#define FWDGT_KEY_RELOAD            ((uint16_t)0xAAAAU)              /*!< FWDGT_CTL bits fwdgt counter reload value */
-#define FWDGT_KEY_ENABLE            ((uint16_t)0xCCCCU)              /*!< FWDGT_CTL bits fwdgt counter enable value */
+#define FWDGT_WRITEACCESS_ENABLE    ((uint16_t)0x5555U)                        /*!< FWDGT_CTL bits write access enable value */
+#define FWDGT_WRITEACCESS_DISABLE   ((uint16_t)0x0000U)                        /*!< FWDGT_CTL bits write access disable value */
+#define FWDGT_KEY_RELOAD            ((uint16_t)0xAAAAU)                        /*!< FWDGT_CTL bits fwdgt counter reload value */
+#define FWDGT_KEY_ENABLE            ((uint16_t)0xCCCCU)                        /*!< FWDGT_CTL bits fwdgt counter enable value */
 
 /* FWDGT timeout value */
-#define FWDGT_WND_TIMEOUT           ((uint32_t)0x000FFFFFU)          /*!< FWDGT_WND register write operation state flag timeout */
-#define FWDGT_PSC_TIMEOUT           ((uint32_t)0x000FFFFFU)          /*!< FWDGT_PSC register write operation state flag timeout */
-#define FWDGT_RLD_TIMEOUT           ((uint32_t)0x000FFFFFU)          /*!< FWDGT_RLD register write operation state flag timeout */
+#define FWDGT_WND_TIMEOUT           ((uint32_t)0x000FFFFFU)                    /*!< FWDGT_WND register write operation state flag timeout */
+#define FWDGT_PSC_TIMEOUT           ((uint32_t)0x000FFFFFU)                    /*!< FWDGT_PSC register write operation state flag timeout */
+#define FWDGT_RLD_TIMEOUT           ((uint32_t)0x000FFFFFU)                    /*!< FWDGT_RLD register write operation state flag timeout */
 
 /* FWDGT flag definitions */
-#define FWDGT_FLAG_PUD              FWDGT_STAT_PUD                   /*!< a write operation to FWDGT_PSC register is on going */
-#define FWDGT_FLAG_RUD              FWDGT_STAT_RUD                   /*!< a write operation to FWDGT_RLD register is on going */
-#define FWDGT_FLAG_WUD              FWDGT_STAT_WUD                   /*!< a write operation to FWDGT_WND register is on going */
+#define FWDGT_FLAG_PUD              FWDGT_STAT_PUD                             /*!< a write operation to FWDGT_PSC register is on going */
+#define FWDGT_FLAG_RUD              FWDGT_STAT_RUD                             /*!< a write operation to FWDGT_RLD register is on going */
+#define FWDGT_FLAG_WUD              FWDGT_STAT_WUD                             /*!< a write operation to FWDGT_WND register is on going */
 
 /* function declarations */
+/* enable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_enable(void);
 /* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
 void fwdgt_write_disable(void);
 /* start the free watchdog timer counter */
@@ -121,4 +121,4 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
 /* get flag state of FWDGT */
 FlagStatus fwdgt_flag_get(uint16_t flag);
 
-#endif /* GD32F1X0_FWDGT_H */
+#endif /* GD32F3X0_FWDGT_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_gpio.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_gpio.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_gpio.h
+    \file  gd32f3x0_gpio.h
     \brief definitions for the GPIO
-    
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,10 +33,10 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_GPIO_H
-#define GD32F1X0_GPIO_H
+#ifndef GD32F3X0_GPIO_H
+#define GD32F3X0_GPIO_H
 
-#include "gd32f1x0.h"
+#include "gd32f3x0.h"
 
 /* GPIOx(x=A,B,C,D,F) definitions */
 #define GPIOA                      (GPIO_BASE + 0x00000000U)
@@ -51,7 +48,7 @@ OF SUCH DAMAGE.
 /* registers definitions */
 #define GPIO_CTL(gpiox)            REG32((gpiox) + 0x00000000U)    /*!< GPIO port control register */
 #define GPIO_OMODE(gpiox)          REG32((gpiox) + 0x00000004U)    /*!< GPIO port output mode register */
-#define GPIO_OSPD(gpiox)           REG32((gpiox) + 0x00000008U)    /*!< GPIO port output speed register */
+#define GPIO_OSPD0(gpiox)          REG32((gpiox) + 0x00000008U)    /*!< GPIO port output speed register 0 */
 #define GPIO_PUD(gpiox)            REG32((gpiox) + 0x0000000CU)    /*!< GPIO port pull-up/pull-down register */
 #define GPIO_ISTAT(gpiox)          REG32((gpiox) + 0x00000010U)    /*!< GPIO port input status register */
 #define GPIO_OCTL(gpiox)           REG32((gpiox) + 0x00000014U)    /*!< GPIO port output control register */
@@ -61,6 +58,7 @@ OF SUCH DAMAGE.
 #define GPIO_AFSEL1(gpiox)         REG32((gpiox) + 0x00000024U)    /*!< GPIO alternate function selected register 1 */
 #define GPIO_BC(gpiox)             REG32((gpiox) + 0x00000028U)    /*!< GPIO bit clear register */
 #define GPIO_TG(gpiox)             REG32((gpiox) + 0x0000002CU)    /*!< GPIO port bit toggle register */
+#define GPIO_OSPD1(gpiox)          REG32((gpiox) + 0x0000003CU)    /*!< GPIO port output speed register 1 */
 
 /* bits definitions */
 /* GPIO_CTL */
@@ -99,23 +97,23 @@ OF SUCH DAMAGE.
 #define GPIO_OMODE_OM14            BIT(14)               /*!< pin 14 output mode bit */
 #define GPIO_OMODE_OM15            BIT(15)               /*!< pin 15 output mode bit */
 
-/* GPIO_OSPD */
-#define GPIO_OSPD_OSPD0            BITS(0,1)             /*!< pin 0 output max speed bits */
-#define GPIO_OSPD_OSPD1            BITS(2,3)             /*!< pin 1 output max speed bits */
-#define GPIO_OSPD_OSPD2            BITS(4,5)             /*!< pin 2 output max speed bits */
-#define GPIO_OSPD_OSPD3            BITS(6,7)             /*!< pin 3 output max speed bits */
-#define GPIO_OSPD_OSPD4            BITS(8,9)             /*!< pin 4 output max speed bits */
-#define GPIO_OSPD_OSPD5            BITS(10,11)           /*!< pin 5 output max speed bits */
-#define GPIO_OSPD_OSPD6            BITS(12,13)           /*!< pin 6 output max speed bits */
-#define GPIO_OSPD_OSPD7            BITS(14,15)           /*!< pin 7 output max speed bits */
-#define GPIO_OSPD_OSPD8            BITS(16,17)           /*!< pin 8 output max speed bits */
-#define GPIO_OSPD_OSPD9            BITS(18,19)           /*!< pin 9 output max speed bits */
-#define GPIO_OSPD_OSPD10           BITS(20,21)           /*!< pin 10 output max speed bits */
-#define GPIO_OSPD_OSPD11           BITS(22,23)           /*!< pin 11 output max speed bits */
-#define GPIO_OSPD_OSPD12           BITS(24,25)           /*!< pin 12 output max speed bits */
-#define GPIO_OSPD_OSPD13           BITS(26,27)           /*!< pin 13 output max speed bits */
-#define GPIO_OSPD_OSPD14           BITS(28,29)           /*!< pin 14 output max speed bits */
-#define GPIO_OSPD_OSPD15           BITS(30,31)           /*!< pin 15 output max speed bits */
+/* GPIO_OSPD0 */
+#define GPIO_OSPD0_OSPD0           BITS(0,1)             /*!< pin 0 output max speed bits */
+#define GPIO_OSPD0_OSPD1           BITS(2,3)             /*!< pin 1 output max speed bits */
+#define GPIO_OSPD0_OSPD2           BITS(4,5)             /*!< pin 2 output max speed bits */
+#define GPIO_OSPD0_OSPD3           BITS(6,7)             /*!< pin 3 output max speed bits */
+#define GPIO_OSPD0_OSPD4           BITS(8,9)             /*!< pin 4 output max speed bits */
+#define GPIO_OSPD0_OSPD5           BITS(10,11)           /*!< pin 5 output max speed bits */
+#define GPIO_OSPD0_OSPD6           BITS(12,13)           /*!< pin 6 output max speed bits */
+#define GPIO_OSPD0_OSPD7           BITS(14,15)           /*!< pin 7 output max speed bits */
+#define GPIO_OSPD0_OSPD8           BITS(16,17)           /*!< pin 8 output max speed bits */
+#define GPIO_OSPD0_OSPD9           BITS(18,19)           /*!< pin 9 output max speed bits */
+#define GPIO_OSPD0_OSPD10          BITS(20,21)           /*!< pin 10 output max speed bits */
+#define GPIO_OSPD0_OSPD11          BITS(22,23)           /*!< pin 11 output max speed bits */
+#define GPIO_OSPD0_OSPD12          BITS(24,25)           /*!< pin 12 output max speed bits */
+#define GPIO_OSPD0_OSPD13          BITS(26,27)           /*!< pin 13 output max speed bits */
+#define GPIO_OSPD0_OSPD14          BITS(28,29)           /*!< pin 14 output max speed bits */
+#define GPIO_OSPD0_OSPD15          BITS(30,31)           /*!< pin 15 output max speed bits */
 
 /* GPIO_PUD */
 #define GPIO_PUD_PUD0              BITS(0,1)             /*!< pin 0 pull-up or pull-down bits */
@@ -262,7 +260,6 @@ OF SUCH DAMAGE.
 #define GPIO_BC_CR14               BIT(14)               /*!< pin 14 clear bit */
 #define GPIO_BC_CR15               BIT(15)               /*!< pin 15 clear bit */
 
-#ifdef GD32F170_190
 /* GPIO_TG */
 #define GPIO_TG_TG0                BIT(0)                /*!< pin 0 toggle bit */
 #define GPIO_TG_TG1                BIT(1)                /*!< pin 1 toggle bit */
@@ -281,7 +278,23 @@ OF SUCH DAMAGE.
 #define GPIO_TG_TG14               BIT(14)               /*!< pin 14 toggle bit */
 #define GPIO_TG_TG15               BIT(15)               /*!< pin 15 toggle bit */
 
-#endif /* GD32F170_190 */
+/* GPIO_OSPD1 */
+#define GPIO_OSPD1_SPD0            BIT(0)                /*!< set pin 0 very high output speed when OSPD0 is "11" */
+#define GPIO_OSPD1_SPD1            BIT(1)                /*!< set pin 1 very high output speed when OSPD1 is "11" */
+#define GPIO_OSPD1_SPD2            BIT(2)                /*!< set pin 2 very high output speed when OSPD2 is "11" */
+#define GPIO_OSPD1_SPD3            BIT(3)                /*!< set pin 3 very high output speed when OSPD3 is "11" */
+#define GPIO_OSPD1_SPD4            BIT(4)                /*!< set pin 4 very high output speed when OSPD4 is "11" */
+#define GPIO_OSPD1_SPD5            BIT(5)                /*!< set pin 5 very high output speed when OSPD5 is "11" */
+#define GPIO_OSPD1_SPD6            BIT(6)                /*!< set pin 6 very high output speed when OSPD6 is "11" */
+#define GPIO_OSPD1_SPD7            BIT(7)                /*!< set pin 7 very high output speed when OSPD7 is "11" */
+#define GPIO_OSPD1_SPD8            BIT(8)                /*!< set pin 8 very high output speed when OSPD8 is "11" */
+#define GPIO_OSPD1_SPD9            BIT(9)                /*!< set pin 9 very high output speed when OSPD9 is "11" */
+#define GPIO_OSPD1_SPD10           BIT(10)               /*!< set pin 10 very high output speed when OSPD10 is "11" */
+#define GPIO_OSPD1_SPD11           BIT(11)               /*!< set pin 11 very high output speed when OSPD11 is "11" */
+#define GPIO_OSPD1_SPD12           BIT(12)               /*!< set pin 12 very high output speed when OSPD12 is "11" */
+#define GPIO_OSPD1_SPD13           BIT(13)               /*!< set pin 13 very high output speed when OSPD13 is "11" */
+#define GPIO_OSPD1_SPD14           BIT(14)               /*!< set pin 14 very high output speed when OSPD14 is "11" */
+#define GPIO_OSPD1_SPD15           BIT(15)               /*!< set pin 15 very high output speed when OSPD15 is "11" */
 
 /* constants definitions */
 typedef FlagStatus bit_status;
@@ -335,10 +348,11 @@ typedef FlagStatus bit_status;
 #define GPIO_OTYPE_OD              ((uint8_t)(0x01U))    /*!< open drain mode */
 
 /* GPIO output max speed value */
-#define OSPD_OSPD(regval)          (BITS(0,1) & ((uint32_t)(regval) << 0))
-#define GPIO_OSPEED_2MHZ           OSPD_OSPD(0)          /*!< output max speed 2M */
-#define GPIO_OSPEED_10MHZ          OSPD_OSPD(1)          /*!< output max speed 10M */
-#define GPIO_OSPEED_50MHZ          OSPD_OSPD(3)          /*!< output max speed 50M */
+#define OSPD_OSPD0(regval)         (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define GPIO_OSPEED_2MHZ           OSPD_OSPD0(0)                     /*!< output max speed 2MHz */
+#define GPIO_OSPEED_10MHZ          OSPD_OSPD0(1)                     /*!< output max speed 10MHz */
+#define GPIO_OSPEED_50MHZ          OSPD_OSPD0(3)                     /*!< output max speed 50MHz */
+#define GPIO_OSPEED_MAX            ((uint32_t)0x0000FFFFU)           /*!< GPIO very high output speed, max speed more than 50MHz */
 
 /* GPIO alternate function values */
 #define GPIO_AFR_SET(n, af)        ((uint32_t)((uint32_t)(af) << (4U * (n))))
@@ -346,16 +360,14 @@ typedef FlagStatus bit_status;
  
 /* GPIO alternate function */
 #define AF(regval)                 (BITS(0,3) & ((uint32_t)(regval) << 0)) 
-#define GPIO_AF_0                  AF(0)                 /*!< alternate function 0 selected */
-#define GPIO_AF_1                  AF(1)                 /*!< alternate function 1 selected */
-#define GPIO_AF_2                  AF(2)                 /*!< alternate function 2 selected */
-#define GPIO_AF_3                  AF(3)                 /*!< alternate function 3 selected */
-#define GPIO_AF_4                  AF(4)                 /*!< alternate function 4 selected (port A,B only) */
-#define GPIO_AF_5                  AF(5)                 /*!< alternate function 5 selected (port A,B only) */
-#define GPIO_AF_6                  AF(6)                 /*!< alternate function 6 selected (port A,B only) */
-#define GPIO_AF_7                  AF(7)                 /*!< alternate function 7 selected (port A only) */
-#define GPIO_AF_9                  AF(9)                 /*!< alternate function 9 selected (port A,B only) */
-#define GPIO_AF_11                 AF(11)                /*!< alternate function 11 selected */
+#define GPIO_AF_0                   AF(0)                /*!< alternate function 0 selected */
+#define GPIO_AF_1                   AF(1)                /*!< alternate function 1 selected */
+#define GPIO_AF_2                   AF(2)                /*!< alternate function 2 selected */
+#define GPIO_AF_3                   AF(3)                /*!< alternate function 3 selected */
+#define GPIO_AF_4                   AF(4)                /*!< alternate function 4 selected (port A,B only) */
+#define GPIO_AF_5                   AF(5)                /*!< alternate function 5 selected (port A,B only) */
+#define GPIO_AF_6                   AF(6)                /*!< alternate function 6 selected (port A,B only) */
+#define GPIO_AF_7                   AF(7)                /*!< alternate function 7 selected (port A,B only) */
 
 /* function declarations */
 /* reset GPIO port */
@@ -388,13 +400,9 @@ void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin);
 /* lock GPIO pin bit */
 void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
 
-#ifdef GD32F170_190
-
 /* toggle GPIO pin status */
 void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
 /* toggle GPIO port status */
 void gpio_port_toggle(uint32_t gpio_periph);
 
-#endif /* GD32F170_190 */
-
-#endif /* GD32F1X0_GPIO_H */
+#endif /* GD32F3X0_GPIO_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_i2c.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_i2c.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_i2c.h
+    \file  gd32f3x0_i2c.h
     \brief definitions for the I2C
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,17 +33,15 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_I2C_H
-#define GD32F1X0_I2C_H
 
-#include "gd32f1x0.h"
+#ifndef GD32F3X0_I2C_H
+#define GD32F3X0_I2C_H
+
+#include "gd32f3x0.h"
 
 /* I2Cx(x=0,1) definitions */
-#define I2C0                          I2C_BASE                   /*!< I2C0 base address */
-#define I2C1                          (I2C_BASE + 0x00000400U)   /*!< I2C1 base address */
-#ifdef GD32F170_190
-#define I2C2                          (I2C_BASE + 0x00006C00U)   /*!< I2C2 base address */
-#endif /* GD32F170_190 */
+#define I2C0                          I2C_BASE                       /*!< I2C0 base address */
+#define I2C1                          (I2C_BASE+0x00000400U)         /*!< I2C1 base address */
 
 /* registers definitions */
 #define I2C_CTL0(i2cx)                REG32((i2cx) + 0x00000000U)      /*!< I2C control register 0 */
@@ -58,9 +53,7 @@ OF SUCH DAMAGE.
 #define I2C_STAT1(i2cx)               REG32((i2cx) + 0x00000018U)      /*!< I2C transfer status register */
 #define I2C_CKCFG(i2cx)               REG32((i2cx) + 0x0000001CU)      /*!< I2C clock configure register */
 #define I2C_RT(i2cx)                  REG32((i2cx) + 0x00000020U)      /*!< I2C rise time register */
-#ifdef GD32F170_190
-#define I2C_SAMCS(i2cx)               REG32((i2cx) + 0x00000080U)      /*!< I2C SAM control and status register */
-#endif /* GD32F170_190 */
+#define I2C_FMPCFG(i2cx)              REG32((i2cx) + 0x00000090U)      /*!< I2C fast-mode-plus configure register */
 
 /* bits definitions */
 /* I2Cx_CTL0 */
@@ -127,28 +120,15 @@ OF SUCH DAMAGE.
 #define I2C_STAT1_PECV                BITS(8,15)    /*!< packet error checking value */
 
 /* I2Cx_CKCFG */
-#define I2C_CKCFG_CLKC                BITS(0,11)    /*!< clock control register in fast/standard mode (master mode) */
-#define I2C_CKCFG_DTCY                BIT(14)       /*!< duty cycle of fast mode */
+#define I2C_CKCFG_CLKC                BITS(0,11)    /*!< clock control register in fast/standard mode or fast mode plus(master mode) */
+#define I2C_CKCFG_DTCY                BIT(14)       /*!< duty cycle of fast mode or fast mode plus */
 #define I2C_CKCFG_FAST                BIT(15)       /*!< I2C speed selection in master mode */
 
 /* I2Cx_RT */
-#define I2C_RT_RISETIME               BITS(0,6)     /*!< maximum rise time in fast/standard mode (master mode) */
-
-#ifdef GD32F170_190
-/* I2Cx_SAMCS */
-#define I2C_SAMCS_SAMEN               BIT(0)        /*!< SAM_V interface enable */
-#define I2C_SAMCS_STOEN               BIT(1)        /*!< SAM_V interface timeout detect enable */
-#define I2C_SAMCS_TFFIE               BIT(4)        /*!< txframe fall interrupt enable */
-#define I2C_SAMCS_TFRIE               BIT(5)        /*!< txframe rise interrupt enable */
-#define I2C_SAMCS_RFFIE               BIT(6)        /*!< rxframe fall interrupt enable */
-#define I2C_SAMCS_RFRIE               BIT(7)        /*!< rxframe rise interrupt enable */
-#define I2C_SAMCS_TXF                 BIT(8)        /*!< level of txframe signal */
-#define I2C_SAMCS_RXF                 BIT(9)        /*!< level of rxframe signal */
-#define I2C_SAMCS_TFF                 BIT(12)       /*!< txframe fall flag */
-#define I2C_SAMCS_TFR                 BIT(13)       /*!< txframe rise flag */
-#define I2C_SAMCS_RFF                 BIT(14)       /*!< rxframe fall flag */
-#define I2C_SAMCS_RFR                 BIT(15)       /*!< rxframe rise flag */
-#endif /* GD32F170_190 */
+#define I2C_RT_RISETIME               BITS(0,6)     /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */
+
+/* I2Cx_FMPCFG */
+#define I2C_FMPCFG_FMPEN              BIT(0)        /*!< fast mode plus enable bit */
 
 /* constants definitions */
 /* define the I2C bit position and its register index offset */
@@ -164,10 +144,6 @@ OF SUCH DAMAGE.
 #define I2C_CTL1_REG_OFFSET           (0x00000004U)         /*!< CTL1 register offset */
 #define I2C_STAT0_REG_OFFSET          (0x00000014U)         /*!< STAT0 register offset */
 #define I2C_STAT1_REG_OFFSET          (0x00000018U)         /*!< STAT1 register offset */
-#ifdef GD32F170_190
-#define I2C_SAMCS_REG_OFFSET          (0x00000080U)         /*!< SAMCS register offset */
-#endif /*GD32F170_190*/
-
 /* I2C flags */
 typedef enum
 {
@@ -193,14 +169,7 @@ typedef enum
     I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U),                  /*!< general call address (00h) received */
     I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U),                /*!< default address of SMBus device */
     I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U),                /*!< SMBus host header detected in slave mode */
-    I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U),                  /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
-#ifdef GD32F170_190
-    /* flags in SAMCS register */
-    I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U),                  /*!< txframe fall flag */
-    I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U),                  /*!< txframe rise flag */
-    I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U),                  /*!< rxframe fall flag */
-    I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U)                  /*!< rxframe rise flag */
-#endif /*GD32F170_190*/
+    I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U)                  /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
 }i2c_flag_enum;
 
 /* I2C interrupt flags */
@@ -221,13 +190,6 @@ typedef enum
     I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U),       /*!< PEC error when receiving data interrupt flag */
     I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U),        /*!< timeout signal in SMBus mode interrupt flag */
     I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U),       /*!< SMBus Alert status interrupt flag */
-#ifdef GD32F170_190
-    /* interrupt flags in SAMCS register */
-    I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U),         /*!< txframe fall interrupt flag */ 
-    I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U),         /*!< txframe rise interrupt  flag */
-    I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U),         /*!< rxframe fall interrupt flag */
-    I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U)         /*!< rxframe rise interrupt flag */
-#endif /*GD32F170_190*/
 }i2c_interrupt_flag_enum;
 
 /* I2C interrupt enable or disable */
@@ -237,13 +199,6 @@ typedef enum
     I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U),                     /*!< error interrupt enable */
     I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U),                      /*!< event interrupt enable */
     I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U),                    /*!< buffer interrupt enable */
-#ifdef GD32F170_190
-    /* interrupt in SAMCS register */
-    I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U),                    /*!< txframe fall interrupt enable  */
-    I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U),                    /*!< txframe rise interrupt  enable */
-    I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U),                    /*!< rxframe fall interrupt enable */
-    I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U)                     /*!< rxframe rise interrupt enable */
-#endif /*GD32F170_190*/
 }i2c_interrupt_enum;
 
 /* SMBus/I2C mode switch and SMBus type selection */
@@ -315,9 +270,9 @@ typedef enum
 /* receive I2C data */
 #define DATA_RECV(regval)             GET_BITS((uint32_t)(regval), 0, 7)
 
-/* I2C duty cycle in fast mode */
-#define I2C_DTCY_2                    ((uint32_t)0x00000000U)                  /*!< in I2C fast mode Tlow/Thigh = 2 */
-#define I2C_DTCY_16_9                 I2C_CKCFG_DTCY                           /*!< in I2C fast mode Tlow/Thigh = 16/9 */
+/* I2C duty cycle in fast mode or fast mode plus */
+#define I2C_DTCY_2                    ((uint32_t)0x00000000U)                  /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */
+#define I2C_DTCY_16_9                 I2C_CKCFG_DTCY                           /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */
 
 /* address mode for the I2C slave */
 #define I2C_ADDFORMAT_7BITS           ((uint32_t)0x00000000U)                  /*!< address:7 bits */
@@ -389,16 +344,4 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
 /* clear I2C interrupt flag */
 void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
-
-#ifdef GD32F170_190
-/* enable SAM_V interface */
-void i2c_sam_enable(uint32_t i2c_periph);
-/* disable SAM_V interface */
-void i2c_sam_disable(uint32_t i2c_periph);
-/* enable SAM_V interface timeout detect */
-void i2c_sam_timeout_enable(uint32_t i2c_periph);
-/* disable SAM_V interface timeout detect */
-void i2c_sam_timeout_disable(uint32_t i2c_periph);
-#endif /*GD32F170_190*/
-
-#endif /* GD32F1X0_I2C_H */
+#endif /* GD32F3X0_I2C_H */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_libopt.h

@@ -0,0 +1,66 @@
+/*!
+    \file  gd32f3x0_libopt.h
+    \brief library optional for gd32f3x0
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_LIBOPT_H
+#define GD32F3X0_LIBOPT_H
+
+#include "gd32f3x0_adc.h"
+#include "gd32f3x0_crc.h"
+#include "gd32f3x0_ctc.h"
+#include "gd32f3x0_dbg.h"
+#include "gd32f3x0_dma.h"
+#include "gd32f3x0_exti.h"
+#include "gd32f3x0_fmc.h"
+#include "gd32f3x0_gpio.h"
+#include "gd32f3x0_syscfg.h"
+#include "gd32f3x0_i2c.h"
+#include "gd32f3x0_fwdgt.h"
+#include "gd32f3x0_pmu.h"
+#include "gd32f3x0_rcu.h"
+#include "gd32f3x0_rtc.h"
+#include "gd32f3x0_spi.h"
+#include "gd32f3x0_timer.h"
+#include "gd32f3x0_usart.h"
+#include "gd32f3x0_wwdgt.h"
+#include "gd32f3x0_misc.h"
+#include "gd32f3x0_tsi.h"
+
+#ifdef GD32F350
+#include "gd32f3x0_cec.h"
+#include "gd32f3x0_cmp.h"
+#include "gd32f3x0_dac.h"
+#endif /* GD32F350 */
+
+#endif /* GD32F3X0_LIBOPT_H */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_misc.h

@@ -0,0 +1,92 @@
+/*!
+    \file  gd32f3x0_misc.h
+    \brief definitions for the MISC
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_MISC_H
+#define GD32F3X0_MISC_H
+
+#include "gd32f3x0.h"
+
+/* constants definitions */
+/* set the RAM and FLASH base address */
+#define NVIC_VECTTAB_RAM            ((uint32_t)0x20000000)                      /*!< RAM base address */
+#define NVIC_VECTTAB_FLASH          ((uint32_t)0x08000000)                      /*!< Flash base address */
+
+/* set the NVIC vector table offset mask */
+#define NVIC_VECTTAB_OFFSET_MASK    ((uint32_t)0x1FFFFF80)                      /*!< NVIC vector table offset mask */
+
+/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
+#define NVIC_AIRCR_VECTKEY_MASK     ((uint32_t)0x05FA0000)                      /*!< NVIC VECTKEY mask */
+
+/* priority group - define the pre-emption priority and the subpriority */
+#define NVIC_PRIGROUP_PRE0_SUB4     ((uint32_t)0x00000700)                      /*!< 0 bits for pre-emption priority 4 bits for subpriority */
+#define NVIC_PRIGROUP_PRE1_SUB3     ((uint32_t)0x00000600)                      /*!< 1 bits for pre-emption priority 3 bits for subpriority */
+#define NVIC_PRIGROUP_PRE2_SUB2     ((uint32_t)0x00000500)                      /*!< 2 bits for pre-emption priority 2 bits for subpriority */
+#define NVIC_PRIGROUP_PRE3_SUB1     ((uint32_t)0x00000400)                      /*!< 3 bits for pre-emption priority 1 bits for subpriority */
+#define NVIC_PRIGROUP_PRE4_SUB0     ((uint32_t)0x00000300)                      /*!< 4 bits for pre-emption priority 0 bits for subpriority */
+
+/* choose the method to enter or exit the lowpower mode */
+#define SCB_SCR_SLEEPONEXIT         ((uint8_t)0x02)                             /*!< choose the the system whether enter low power mode by exiting from ISR */
+#define SCB_SCR_SLEEPDEEP           ((uint8_t)0x04)                             /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
+#define SCB_SCR_SEVONPEND           ((uint8_t)0x10)                             /*!< choose the interrupt source that can wake up the lowpower mode */
+
+#define SCB_LPM_SLEEP_EXIT_ISR      SCB_SCR_SLEEPONEXIT                         /*!< low power mode by exiting from ISR */
+#define SCB_LPM_DEEPSLEEP           SCB_SCR_SLEEPDEEP                           /*!< DEEPSLEEP mode or SLEEP mode */
+#define SCB_LPM_WAKE_BY_ALL_INT     SCB_SCR_SEVONPEND                           /*!< wakeup by all interrupt */
+
+/* choose the systick clock source */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU)                     /*!< systick clock source is from HCLK/8 */
+#define SYSTICK_CLKSOURCE_HCLK      ((uint32_t)0x00000004U)                     /*!< systick clock source is from HCLK */
+
+/* function declarations */
+/* set the priority group */
+void nvic_priority_group_set(uint32_t nvic_prigroup);
+
+/* enable NVIC request */
+void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
+/* disable NVIC request */
+void nvic_irq_disable(uint8_t nvic_irq);
+
+/* set the NVIC vector table base address */
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
+
+/* set the state of the low power mode */
+void system_lowpower_set(uint8_t lowpower_mode);
+/* reset the state of the low power mode */
+void system_lowpower_reset(uint8_t lowpower_mode);
+
+/* set the systick clock source */
+void systick_clksource_set(uint32_t systick_clksource);
+
+#endif /* GD32F3X0_MISC_H */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_pmu.h

@@ -0,0 +1,197 @@
+/*!
+    \file  gd32f3x0_pmu.h
+    \brief definitions for the PMU
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_PMU_H
+#define GD32F3X0_PMU_H
+
+#include "gd32f3x0.h"
+
+/* PMU definitions */
+#define PMU                           PMU_BASE                 /*!< PMU base address */
+
+/* registers definitions */
+#define PMU_CTL                       REG32(PMU + 0x00000000U) /*!< PMU control register */
+#define PMU_CS                        REG32(PMU + 0x00000004U) /*!< PMU control and status register */
+
+/* bits definitions */
+/* PMU_CTL */
+#define PMU_CTL_LDOLP                 BIT(0)                   /*!< LDO low power mode */
+#define PMU_CTL_STBMOD                BIT(1)                   /*!< standby mode */
+#define PMU_CTL_WURST                 BIT(2)                   /*!< wakeup flag reset */
+#define PMU_CTL_STBRST                BIT(3)                   /*!< standby flag reset */
+#define PMU_CTL_LVDEN                 BIT(4)                   /*!< low voltage detector enable */
+#define PMU_CTL_LVDT                  BITS(5,7)                /*!< low voltage detector threshold */
+#define PMU_CTL_BKPWEN                BIT(8)                   /*!< backup domain write enable */
+#define PMU_CTL_LDLP                  BIT(10)                  /*!< low-driver mode when use low power LDO */
+#define PMU_CTL_LDNP                  BIT(11)                  /*!< low-driver mode when use normal power LDO */
+#define PMU_CTL_LDOVS                 BITS(14,15)              /*!< LDO output voltage select */
+#define PMU_CTL_HDEN                  BIT(16)                  /*!< high-driver mode enable */
+#define PMU_CTL_HDS                   BIT(17)                  /*!< high-driver mode switch */
+#define PMU_CTL_LDEN                  BITS(18,19)              /*!< low-driver mode enable in deep-sleep mode */
+
+/* PMU_CS */
+#define PMU_CS_WUF                    BIT(0)                   /*!< wakeup flag */
+#define PMU_CS_STBF                   BIT(1)                   /*!< standby flag */
+#define PMU_CS_LVDF                   BIT(2)                   /*!< low voltage detector status flag */
+#define PMU_CS_WUPEN0                 BIT(8)                   /*!< wakeup pin enable */
+#define PMU_CS_WUPEN1                 BIT(9)                   /*!< wakeup pin enable */
+#define PMU_CS_WUPEN4                 BIT(12)                  /*!< wakeup pin enable */
+#define PMU_CS_WUPEN5                 BIT(13)                  /*!< wakeup pin enable */
+#define PMU_CS_WUPEN6                 BIT(14)                  /*!< wakeup pin enable */
+#define PMU_CS_LDOVSRF                BIT(15)                  /*!< LDO voltage select ready flag */
+#define PMU_CS_HDRF                   BIT(16)                  /*!< high-driver ready flag */
+#define PMU_CS_HDSRF                  BIT(17)                  /*!< high-driver switch ready flag */
+#define PMU_CS_LDRF                   BITS(18,19)              /*!< low-driver mode ready flag */
+
+/* constants definitions */
+/* PMU low voltage detector threshold definitions */
+#define CTL_LVDT(regval)              (BITS(5,7)&((uint32_t)(regval)<<5))
+#define PMU_LVDT_0                    CTL_LVDT(0)              /*!< voltage threshold is 2.1V */
+#define PMU_LVDT_1                    CTL_LVDT(1)              /*!< voltage threshold is 2.3V */
+#define PMU_LVDT_2                    CTL_LVDT(2)              /*!< voltage threshold is 2.4V */
+#define PMU_LVDT_3                    CTL_LVDT(3)              /*!< voltage threshold is 2.6V */
+#define PMU_LVDT_4                    CTL_LVDT(4)              /*!< voltage threshold is 2.7V */
+#define PMU_LVDT_5                    CTL_LVDT(5)              /*!< voltage threshold is 2.9V */
+#define PMU_LVDT_6                    CTL_LVDT(6)              /*!< voltage threshold is 3.0V */
+#define PMU_LVDT_7                    CTL_LVDT(7)              /*!< voltage threshold is 3.1V */
+
+/* PMU LDO output voltage select definitions */
+#define CTL_LDOVS(regval)             (BITS(14,15)&((uint32_t)(regval)<<14))
+#define PMU_LDOVS_LOW                 CTL_LDOVS(1)             /*!< LDO output voltage low mode */
+#define PMU_LDOVS_MID                 CTL_LDOVS(2)             /*!< LDO output voltage mid mode */
+#define PMU_LDOVS_HIGH                CTL_LDOVS(3)             /*!< LDO output voltage high mode */
+
+/* PMU low-driver mode enable in deep-sleep mode */
+#define CTL_LDEN(regval)              (BITS(18,19)&((uint32_t)(regval)<<18))
+#define PMU_LOWDRIVER_DISABLE         CTL_LDEN(0)              /*!< low-driver mode disable in deep-sleep mode */
+#define PMU_LOWDRIVER_ENABLE          CTL_LDEN(3)              /*!< low-driver mode enable in deep-sleep mode */
+
+/* PMU high-driver mode switch */
+#define PMU_HIGHDR_SWITCH_NONE        ((uint32_t)0x00000000U)  /*!< no high-driver mode switch */
+#define PMU_HIGHDR_SWITCH_EN          PMU_CTL_HDS              /*!< high-driver mode switch */
+
+/* PMU low-driver mode when use normal power LDO */
+#define PMU_NORMALDR_NORMALPWR        ((uint32_t)0x00000000U)  /*!< normal-driver when use normal power LDO */
+#define PMU_LOWDR_NORMALPWR           PMU_CTL_LDNP             /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
+
+/* PMU low-driver mode when use low power LDO */
+#define PMU_NORMALDR_LOWPWR           ((uint32_t)0x00000000U)  /*!< normal-driver when use low power LDO */
+#define PMU_LOWDR_LOWPWR              PMU_CTL_LDLP             /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */
+
+/* PMU ldo definitions */
+#define PMU_LDO_NORMAL                ((uint32_t)0x00000000U)  /*!< LDO operates normally when PMU enter deepsleep mode */
+#define PMU_LDO_LOWPOWER              PMU_CTL_LDOLP            /*!< LDO work at low power status when PMU enter deepsleep mode */
+
+/* PMU low power mode ready flag definitions */
+#define CS_LDRF(regval)               (BITS(18,19)&((uint32_t)(regval)<<18))
+#define PMU_LDRF_NORMAL               CS_LDRF(0)               /*!< normal-driver in deep-sleep mode */
+#define PMU_LDRF_LOWDRIVER            CS_LDRF(3)               /*!< low-driver mode in deep-sleep mode */
+
+/* PMU flag definitions */
+#define PMU_FLAG_WAKEUP               PMU_CS_WUF               /*!< wakeup flag status */
+#define PMU_FLAG_STANDBY              PMU_CS_STBF              /*!< standby flag status */
+#define PMU_FLAG_LVD                  PMU_CS_LVDF              /*!< LVD flag status */
+#define PMU_FLAG_LDOVSR               PMU_CS_LDOVSRF           /*!< LDO voltage select ready flag */
+#define PMU_FLAG_HDR                  PMU_CS_HDRF              /*!< high-driver ready flag */
+#define PMU_FLAG_HDSR                 PMU_CS_HDSRF             /*!< high-driver switch ready flag */
+#define PMU_FLAG_LDR                  PMU_CS_LDRF              /*!< low-driver mode ready flag */
+
+/* PMU WKUP pin definitions */
+#define PMU_WAKEUP_PIN0               PMU_CS_WUPEN0            /*!< WKUP Pin 0 (PA0) enable */
+#define PMU_WAKEUP_PIN1               PMU_CS_WUPEN1            /*!< WKUP Pin 1 (PC13) enable */
+#define PMU_WAKEUP_PIN4               PMU_CS_WUPEN4            /*!< WKUP Pin 4 (PC5) enable */
+#define PMU_WAKEUP_PIN5               PMU_CS_WUPEN5            /*!< WKUP Pin 5 (PB5) enable */
+#define PMU_WAKEUP_PIN6               PMU_CS_WUPEN6            /*!< WKUP Pin 6 (PB15) enable */
+
+/* PMU flag reset definitions */
+#define PMU_FLAG_RESET_WAKEUP         PMU_CTL_WURST            /*!< wakeup flag reset */
+#define PMU_FLAG_RESET_STANDBY        PMU_CTL_STBRST           /*!< standby flag reset */
+
+/* PMU command constants definitions */
+#define WFI_CMD                       ((uint8_t)0x00U)         /*!< use WFI command */
+#define WFE_CMD                       ((uint8_t)0x01U)         /*!< use WFE command */
+
+/* function declarations */
+/* function configuration */
+/* reset PMU registers */
+void pmu_deinit(void);
+/* select low voltage detector threshold */
+void pmu_lvd_select(uint32_t lvdt_n);
+/* select LDO output voltage */
+void pmu_ldo_output_select(uint32_t ldo_output);
+/* disable PMU lvd */
+void pmu_lvd_disable(void);
+
+/* functions of low-driver mode and high-driver mode in deep-sleep mode */
+/* enable low-driver mode in deep-sleep mode */
+void pmu_lowdriver_mode_enable(void);
+/* disable low-driver mode in deep-sleep mode */
+void pmu_lowdriver_mode_disable(void);
+/* enable high-driver mode */
+void pmu_highdriver_mode_enable(void);
+/* disable high-driver mode */
+void pmu_highdriver_mode_disable(void);
+/* switch high-driver mode */
+void pmu_highdriver_switch_select(uint32_t highdr_switch);
+/* in deep-sleep mode, low-driver mode when use low power LDO */
+void pmu_lowpower_driver_config(uint32_t mode);
+/* in deep-sleep mode, low-driver mode when use normal power LDO */
+void pmu_normalpower_driver_config(uint32_t mode);
+
+/* set PMU mode */
+/* PMU work in sleep mode */
+void pmu_to_sleepmode(uint8_t sleepmodecmd);
+/* PMU work in deepsleep mode */
+void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
+/* PMU work in standby mode */
+void pmu_to_standbymode(uint8_t standbymodecmd);
+/* enable PMU wakeup pin */
+void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
+/* disable PMU wakeup pin */
+void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
+
+/* backup related functions */
+/* enable backup domain write */
+void pmu_backup_write_enable(void);
+/* disable backup domain write */
+void pmu_backup_write_disable(void);
+
+/* flag functions */
+/* clear flag bit */
+void pmu_flag_clear(uint32_t flag_clear);
+/* get flag state */
+FlagStatus pmu_flag_get(uint32_t flag);
+
+#endif /* GD32F3X0_PMU_H */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_rcu.h

@@ -0,0 +1,797 @@
+/*!
+    \file  gd32f3x0_rcu.h
+    \brief definitions for the RCU
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_RCU_H
+#define GD32F3X0_RCU_H
+
+#include "gd32f3x0.h"
+
+/* RCU definitions */
+#define RCU                         RCU_BASE
+
+/* registers definitions */
+#define RCU_CTL0                    REG32(RCU + 0x00000000U)        /*!< control register 0 */
+#define RCU_CFG0                    REG32(RCU + 0x00000004U)        /*!< configuration register 0 */
+#define RCU_INT                     REG32(RCU + 0x00000008U)        /*!< interrupt register */
+#define RCU_APB2RST                 REG32(RCU + 0x0000000CU)        /*!< APB2 reset register */
+#define RCU_APB1RST                 REG32(RCU + 0x00000010U)        /*!< APB1 reset register */
+#define RCU_AHBEN                   REG32(RCU + 0x00000014U)        /*!< AHB enable register */
+#define RCU_APB2EN                  REG32(RCU + 0x00000018U)        /*!< APB2 enable register */
+#define RCU_APB1EN                  REG32(RCU + 0x0000001CU)        /*!< APB1 enable register  */
+#define RCU_BDCTL                   REG32(RCU + 0x00000020U)        /*!< backup domain control register */
+#define RCU_RSTSCK                  REG32(RCU + 0x00000024U)        /*!< reset source /clock register */
+#define RCU_AHBRST                  REG32(RCU + 0x00000028U)        /*!< AHB reset register */
+#define RCU_CFG1                    REG32(RCU + 0x0000002CU)        /*!< configuration register 1 */
+#define RCU_CFG2                    REG32(RCU + 0x00000030U)        /*!< configuration register 2 */
+#define RCU_CTL1                    REG32(RCU + 0x00000034U)        /*!< control register 1 */
+#define RCU_ADDCTL                  REG32(RCU + 0x000000C0U)        /*!< additional clock control register */
+#define RCU_ADDINT                  REG32(RCU + 0x000000CCU)        /*!< additional clock interrupt register */
+#define RCU_ADDAPB1EN               REG32(RCU + 0x000000F8U)        /*!< APB1 additional enable register */
+#define RCU_ADDAPB1RST              REG32(RCU + 0x000000FCU)        /*!< APB1 additional reset register */
+#define RCU_VKEY                    REG32(RCU + 0x00000100U)        /*!< voltage key register */
+#define RCU_DSV                     REG32(RCU + 0x00000134U)        /*!< deep-sleep mode voltage register */
+
+/* bits definitions */
+/* RCU_CTL0 */
+#define RCU_CTL0_IRC8MEN            BIT(0)                    /*!< internal high speed oscillator enable */
+#define RCU_CTL0_IRC8MSTB           BIT(1)                    /*!< IRC8M high speed internal oscillator stabilization flag */
+#define RCU_CTL0_IRC8MADJ           BITS(3,7)                 /*!< high speed internal oscillator clock trim adjust value */
+#define RCU_CTL0_IRC8MCALIB         BITS(8,15)                /*!< high speed internal oscillator calibration value register */
+#define RCU_CTL0_HXTALEN            BIT(16)                   /*!< external high speed oscillator enable */
+#define RCU_CTL0_HXTALSTB           BIT(17)                   /*!< external crystal oscillator clock stabilization flag */
+#define RCU_CTL0_HXTALBPS           BIT(18)                   /*!< external crystal oscillator clock bypass mode enable */
+#define RCU_CTL0_CKMEN              BIT(19)                   /*!< HXTAL clock monitor enable */
+#define RCU_CTL0_PLLEN              BIT(24)                   /*!< PLL enable */
+#define RCU_CTL0_PLLSTB             BIT(25)                   /*!< PLL clock stabilization flag */
+
+/* RCU_CFG0 */
+#define RCU_CFG0_SCS                BITS(0,1)                 /*!< system clock switch */
+#define RCU_CFG0_SCSS               BITS(2,3)                 /*!< system clock switch status */
+#define RCU_CFG0_AHBPSC             BITS(4,7)                 /*!< AHB prescaler selection */
+#define RCU_CFG0_APB1PSC            BITS(8,10)                /*!< APB1 prescaler selection */
+#define RCU_CFG0_APB2PSC            BITS(11,13)               /*!< APB2 prescaler selection */
+#define RCU_CFG0_ADCPSC             BITS(14,15)               /*!< ADC clock prescaler selection */
+#define RCU_CFG0_PLLSEL             BIT(16)                   /*!< PLL clock source selection */
+#define RCU_CFG0_PLLPREDV           BIT(17)                   /*!< divider for PLL source clock selection */
+#define RCU_CFG0_PLLMF              (BIT(27) | BITS(18,21))   /*!< PLL multiply factor */
+#define RCU_CFG0_USBFSPSC           BITS(22,23)               /*!< USBFS clock prescaler selection */
+#define RCU_CFG0_CKOUTSEL           BITS(24,26)               /*!< CK_OUT clock source selection */
+#define RCU_CFG0_PLLMF4             BIT(27)                   /*!< bit 4 of PLLMF */
+#define RCU_CFG0_CKOUTDIV           BITS(28,30)               /*!< CK_OUT divider which the CK_OUT frequency can be reduced */
+#define RCU_CFG0_PLLDV              BIT(31)                   /*!< CK_PLL divide by 1 or 2 */
+
+/* RCU_INT */
+#define RCU_INT_IRC40KSTBIF         BIT(0)                    /*!< IRC40K stabilization interrupt flag */
+#define RCU_INT_LXTALSTBIF          BIT(1)                    /*!< LXTAL stabilization interrupt flag */
+#define RCU_INT_IRC8MSTBIF          BIT(2)                    /*!< IRC8M stabilization interrupt flag */
+#define RCU_INT_HXTALSTBIF          BIT(3)                    /*!< HXTAL stabilization interrupt flag */
+#define RCU_INT_PLLSTBIF            BIT(4)                    /*!< PLL stabilization interrupt flag */
+#define RCU_INT_IRC28MSTBIF         BIT(5)                    /*!< IRC28M stabilization interrupt flag */
+#define RCU_INT_CKMIF               BIT(7)                    /*!< HXTAL clock stuck interrupt flag */
+#define RCU_INT_IRC40KSTBIE         BIT(8)                    /*!< IRC40K stabilization interrupt enable */
+#define RCU_INT_LXTALSTBIE          BIT(9)                    /*!< LXTAL stabilization interrupt enable */
+#define RCU_INT_IRC8MSTBIE          BIT(10)                   /*!< IRC8M stabilization interrupt enable */
+#define RCU_INT_HXTALSTBIE          BIT(11)                   /*!< HXTAL stabilization interrupt enable */
+#define RCU_INT_PLLSTBIE            BIT(12)                   /*!< PLL stabilization interrupt enable */
+#define RCU_INT_IRC28MSTBIE         BIT(13)                   /*!< IRC28M stabilization interrupt enable */
+#define RCU_INT_IRC40KSTBIC         BIT(16)                   /*!< IRC40K stabilization interrupt clear */
+#define RCU_INT_LXTALSTBIC          BIT(17)                   /*!< LXTAL stabilization interrupt clear */
+#define RCU_INT_IRC8MSTBIC          BIT(18)                   /*!< IRC8M stabilization interrupt clear */
+#define RCU_INT_HXTALSTBIC          BIT(19)                   /*!< HXTAL stabilization interrupt clear */
+#define RCU_INT_PLLSTBIC            BIT(20)                   /*!< PLL stabilization interrupt clear */
+#define RCU_INT_IRC28MSTBIC         BIT(21)                   /*!< IRC28M stabilization interrupt clear */
+#define RCU_INT_CKMIC               BIT(23)                   /*!< HXTAL clock stuck interrupt clear */
+
+/* RCU_APB2RST */
+#define RCU_APB2RST_CFGRST          BIT(0)                    /*!< system configuration reset */
+#define RCU_APB2RST_ADCRST          BIT(9)                    /*!< ADC reset */
+#define RCU_APB2RST_TIMER0RST       BIT(11)                   /*!< TIMER0 reset */
+#define RCU_APB2RST_SPI0RST         BIT(12)                   /*!< SPI0 reset */
+#define RCU_APB2RST_USART0RST       BIT(14)                   /*!< USART0 reset */
+#define RCU_APB2RST_TIMER14RST      BIT(16)                   /*!< TIMER14 reset */
+#define RCU_APB2RST_TIMER15RST      BIT(17)                   /*!< TIMER15 reset */
+#define RCU_APB2RST_TIMER16RST      BIT(18)                   /*!< TIMER16 reset */
+
+/* RCU_APB1RST */
+#define RCU_APB1RST_TIMER1RST       BIT(0)                    /*!< TIMER1 timer reset */
+#define RCU_APB1RST_TIMER2RST       BIT(1)                    /*!< TIMER2 timer reset */
+#define RCU_APB1RST_TIMER5RST       BIT(4)                    /*!< TIMER5 timer reset */
+#define RCU_APB1RST_TIMER13RST      BIT(8)                    /*!< TIMER13 timer reset */
+#define RCU_APB1RST_WWDGTRST        BIT(11)                   /*!< window watchdog timer reset */
+#define RCU_APB1RST_SPI1RST         BIT(14)                   /*!< SPI1 reset */
+#define RCU_APB1RST_USART1RST       BIT(17)                   /*!< USART1 reset */
+#define RCU_APB1RST_I2C0RST         BIT(21)                   /*!< I2C0 reset */
+#define RCU_APB1RST_I2C1RST         BIT(22)                   /*!< I2C1 reset */
+#define RCU_APB1RST_PMURST          BIT(28)                   /*!< power control reset */
+#define RCU_APB1RST_DACRST          BIT(29)                   /*!< DAC reset */
+#define RCU_APB1RST_CECRST          BIT(30)                   /*!< HDMI CEC reset */
+
+/* RCU_AHBEN */
+#define RCU_AHBEN_DMAEN             BIT(0)                    /*!< DMA clock enable */
+#define RCU_AHBEN_SRAMSPEN          BIT(2)                    /*!< SRAM interface clock enable */
+#define RCU_AHBEN_FMCSPEN           BIT(4)                    /*!< FMC clock enable */
+#define RCU_AHBEN_CRCEN             BIT(6)                    /*!< CRC clock enable */
+#define RCU_AHBEN_USBFS             BIT(12)                   /*!< USBFS clock enable */
+#define RCU_AHBEN_PAEN              BIT(17)                   /*!< GPIO port A clock enable */
+#define RCU_AHBEN_PBEN              BIT(18)                   /*!< GPIO port B clock enable */
+#define RCU_AHBEN_PCEN              BIT(19)                   /*!< GPIO port C clock enable */
+#define RCU_AHBEN_PDEN              BIT(20)                   /*!< GPIO port D clock enable */
+#define RCU_AHBEN_PFEN              BIT(22)                   /*!< GPIO port F clock enable */
+#define RCU_AHBEN_TSIEN             BIT(24)                   /*!< TSI clock enable */
+
+/* RCU_APB2EN */
+#define RCU_APB2EN_CFGCMPEN         BIT(0)                    /*!< system configuration and comparator clock enable */
+#define RCU_APB2EN_ADCEN            BIT(9)                    /*!< ADC interface clock enable */
+#define RCU_APB2EN_TIMER0EN         BIT(11)                   /*!< TIMER0 timer clock enable */
+#define RCU_APB2EN_SPI0EN           BIT(12)                   /*!< SPI0 clock enable */
+#define RCU_APB2EN_USART0EN         BIT(14)                   /*!< USART0 clock enable */
+#define RCU_APB2EN_TIMER14EN        BIT(16)                   /*!< TIMER14 timer clock enable */
+#define RCU_APB2EN_TIMER15EN        BIT(17)                   /*!< TIMER15 timer clock enable */
+#define RCU_APB2EN_TIMER16EN        BIT(18)                   /*!< TIMER16 timer clock enable */
+
+/* RCU_APB1EN */
+#define RCU_APB1EN_TIMER1EN         BIT(0)                    /*!< TIMER1 timer clock enable */
+#define RCU_APB1EN_TIMER2EN         BIT(1)                    /*!< TIMER2 timer clock enable */
+#define RCU_APB1EN_TIMER5EN         BIT(4)                    /*!< TIMER5 timer clock enable */
+#define RCU_APB1EN_TIMER13EN        BIT(8)                    /*!< TIMER13 timer clock enable */
+#define RCU_APB1EN_WWDGTEN          BIT(11)                   /*!< window watchdog timer clock enable */
+#define RCU_APB1EN_SPI1EN           BIT(14)                   /*!< SPI1 clock enable */
+#define RCU_APB1EN_USART1EN         BIT(17)                   /*!< USART1 clock enable */
+#define RCU_APB1EN_I2C0EN           BIT(21)                   /*!< I2C0 clock enable */
+#define RCU_APB1EN_I2C1EN           BIT(22)                   /*!< I2C1 clock enable */
+#define RCU_APB1EN_PMUEN            BIT(28)                   /*!< power interface clock enable */
+#define RCU_APB1EN_DACEN            BIT(29)                   /*!< DAC interface clock enable */
+#define RCU_APB1EN_CECEN            BIT(30)                   /*!< HDMI CEC interface clock enable */
+
+/* RCU_BDCTL */
+#define RCU_BDCTL_LXTALEN           BIT(0)                    /*!< LXTAL enable */
+#define RCU_BDCTL_LXTALSTB          BIT(1)                    /*!< external low-speed oscillator stabilization */
+#define RCU_BDCTL_LXTALBPS          BIT(2)                    /*!< LXTAL bypass mode enable */
+#define RCU_BDCTL_LXTALDRI          BITS(3,4)                 /*!< LXTAL drive capability */
+#define RCU_BDCTL_RTCSRC            BITS(8,9)                 /*!< RTC clock entry selection */
+#define RCU_BDCTL_RTCEN             BIT(15)                   /*!< RTC clock enable */
+#define RCU_BDCTL_BKPRST            BIT(16)                   /*!< backup domain reset */
+
+/* RCU_RSTSCK */
+#define RCU_RSTSCK_IRC40KEN         BIT(0)                    /*!< IRC40K enable */
+#define RCU_RSTSCK_IRC40KSTB        BIT(1)                    /*!< IRC40K stabilization */
+#define RCU_RSTSCK_V12RSTF          BIT(23)                   /*!< V12 domain power reset flag */
+#define RCU_RSTSCK_RSTFC            BIT(24)                   /*!< reset flag clear */
+#define RCU_RSTSCK_OBLRSTF          BIT(25)                   /*!< option byte loader reset flag */
+#define RCU_RSTSCK_EPRSTF           BIT(26)                   /*!< external pin reset flag */
+#define RCU_RSTSCK_PORRSTF          BIT(27)                   /*!< power reset flag */
+#define RCU_RSTSCK_SWRSTF           BIT(28)                   /*!< software reset flag */
+#define RCU_RSTSCK_FWDGTRSTF        BIT(29)                   /*!< free watchdog timer reset flag */
+#define RCU_RSTSCK_WWDGTRSTF        BIT(30)                   /*!< window watchdog timer reset flag */
+#define RCU_RSTSCK_LPRSTF           BIT(31)                   /*!< low-power reset flag */
+
+/* RCU_AHBRST */
+#define RCU_AHBRST_USBFSRST         BIT(12)                   /*!< USBFS reset */
+#define RCU_AHBRST_PARST            BIT(17)                   /*!< GPIO port A reset */
+#define RCU_AHBRST_PBRST            BIT(18)                   /*!< GPIO port B reset */
+#define RCU_AHBRST_PCRST            BIT(19)                   /*!< GPIO port C reset */
+#define RCU_AHBRST_PDRST            BIT(20)                   /*!< GPIO port D reset */
+#define RCU_AHBRST_PFRST            BIT(22)                   /*!< GPIO port F reset */
+#define RCU_AHBRST_TSIRST           BIT(24)                   /*!< TSI unit reset */
+
+/* RCU_CFG1 */
+#define RCU_CFG1_PREDV              BITS(0,3)                 /*!< CK_HXTAL divider previous PLL */
+#define RCU_CFG1_PLLPRESEL          BIT(30)                   /*!< PLL clock source preselection */
+#define RCU_CFG1_PLLMF5             BIT(31)                   /*!< bit 5 of PLLMF */
+
+/* RCU_CFG2 */
+#define RCU_CFG2_USART0SEL          BITS(0,1)                 /*!< CK_USART0 clock source selection */
+#define RCU_CFG2_CECSEL             BIT(6)                    /*!< CK_CEC clock source selection */
+#define RCU_CFG2_ADCSEL             BIT(8)                    /*!< CK_ADC clock source selection */
+#define RCU_CFG2_IRC28MDIV          BIT(16)                   /*!< CK_IRC28M divider 2 or not */
+#define RCU_CFG2_USBFSPSC2          BIT(30)                   /*!< bit 2 of USBFSPSC */
+#define RCU_CFG2_ADCPSC2            BIT(31)                   /*!< bit 2 of ADCPSC */
+
+/* RCU_CTL1 */
+#define RCU_CTL1_IRC28MEN           BIT(0)                    /*!< IRC28M internal 28M RC oscillator enable */
+#define RCU_CTL1_IRC28MSTB          BIT(1)                    /*!< IRC28M internal 28M RC oscillator stabilization flag */
+#define RCU_CTL1_IRC28MADJ          BITS(3,7)                 /*!< internal 28M RC oscillator clock trim adjust value */
+#define RCU_CTL1_IRC28MCALIB        BITS(8,15)                /*!< internal 28M RC oscillator calibration value register */
+
+/* RCU_ADDCTL */
+#define RCU_ADDCTL_CK48MSEL         BIT(0)                    /*!< 48M clock selection */
+#define RCU_ADDCTL_IRC48MEN         BIT(16)                   /*!< IRC48M internal 48M RC oscillator enable */
+#define RCU_ADDCTL_IRC48MSTB        BIT(17)                   /*!< internal 48M RC oscillator stabilization flag */
+#define RCU_ADDCTL_IRC48MCALIB      BITS(24,31)               /*!< internal 48M RC oscillator calibration value register */
+
+/* RCU_ADDINT */
+#define RCU_ADDINT_IRC48MSTBIF      BIT(6)                    /*!< IRC48M stabilization interrupt flag */
+#define RCU_ADDINT_IRC48MSTBIE      BIT(14)                   /*!< IRC48M stabilization interrupt enable */
+#define RCU_ADDINT_IRC48MSTBIC      BIT(22)                   /*!< IRC48M stabilization interrupt clear */
+
+/* RCU_ADDAPB1EN */
+#define RCU_ADDAPB1EN_CTCEN         BIT(27)                   /*!< CTC unit clock enable */
+
+/* RCU_ADDAPB1RST */
+#define RCU_ADDAPB1RST_CTCRST       BIT(27)                   /*!< CTC unit reset */
+
+/* RCU_VKEY */
+#define RCU_VKEY_KEY                BITS(0,31)                /*!< key of RCU_DSV register */
+
+/* RCU_DSV */
+#define RCU_DSV_DSLPVS              BITS(0,1)                 /*!< deep-sleep mode voltage select */
+
+/* constants definitions */
+/* define the peripheral clock enable bit position and its register index offset */
+#define RCU_REGIDX_BIT(regidx, bitpos)      (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos))
+#define RCU_REG_VAL(periph)                 (REG32(RCU + ((uint32_t)(periph)>>6)))
+#define RCU_BIT_POS(val)                    ((uint32_t)(val) & (uint32_t)0x0000001FU)
+/* define the voltage key unlock value */
+#define RCU_VKEY_UNLOCK                     ((uint32_t)0x1A2B3C4DU)
+
+/* register index */
+typedef enum
+{
+    /* peripherals enable */
+    IDX_AHBEN      = ((uint32_t)0x00000014U),
+    IDX_APB2EN     = ((uint32_t)0x00000018U),
+    IDX_APB1EN     = ((uint32_t)0x0000001CU),
+    IDX_ADDAPB1EN  = ((uint32_t)0x000000F8U),
+    /* peripherals reset */
+    IDX_AHBRST     = ((uint32_t)0x00000028U),
+    IDX_APB2RST    = ((uint32_t)0x0000000CU),
+    IDX_APB1RST    = ((uint32_t)0x00000010U),
+    IDX_ADDAPB1RST = ((uint32_t)0x000000FCU),
+    /* clock stabilization */
+    IDX_CTL0       = ((uint32_t)0x00000000U),
+    IDX_BDCTL      = ((uint32_t)0x00000020U),
+    IDX_CTL1       = ((uint32_t)0x00000034U),
+    IDX_ADDCTL     = ((uint32_t)0x000000C0U),
+    /* peripheral reset */
+    IDX_RSTSCK     = ((uint32_t)0x00000024U),
+    /* clock stabilization and stuck interrupt */
+    IDX_INT        = ((uint32_t)0x00000008U),
+    IDX_ADDINT     = ((uint32_t)0x000000CCU),
+    /* configuration register */
+    IDX_CFG0       = ((uint32_t)0x00000004U),
+    IDX_CFG2       = ((uint32_t)0x00000030U)
+}reg_idx;
+
+/* peripheral clock enable */
+typedef enum
+{
+    /* AHB peripherals */
+    RCU_DMA     = RCU_REGIDX_BIT(IDX_AHBEN, 0U),                  /*!< DMA clock */
+    RCU_CRC     = RCU_REGIDX_BIT(IDX_AHBEN, 6U),                  /*!< CRC clock */
+    RCU_GPIOA   = RCU_REGIDX_BIT(IDX_AHBEN, 17U),                 /*!< GPIOA clock */
+    RCU_GPIOB   = RCU_REGIDX_BIT(IDX_AHBEN, 18U),                 /*!< GPIOB clock */
+    RCU_GPIOC   = RCU_REGIDX_BIT(IDX_AHBEN, 19U),                 /*!< GPIOC clock */
+    RCU_GPIOD   = RCU_REGIDX_BIT(IDX_AHBEN, 20U),                 /*!< GPIOD clock */
+    RCU_GPIOF   = RCU_REGIDX_BIT(IDX_AHBEN, 22U),                 /*!< GPIOF clock */
+    RCU_TSI     = RCU_REGIDX_BIT(IDX_AHBEN, 24U),                 /*!< TSI clock */
+    
+    /* APB2 peripherals */
+    RCU_CFGCMP  = RCU_REGIDX_BIT(IDX_APB2EN, 0U),                 /*!< CFGCMP clock */
+    RCU_ADC     = RCU_REGIDX_BIT(IDX_APB2EN, 9U),                 /*!< ADC clock */
+    RCU_TIMER0  = RCU_REGIDX_BIT(IDX_APB2EN, 11U),                /*!< TIMER0 clock */
+    RCU_SPI0    = RCU_REGIDX_BIT(IDX_APB2EN, 12U),                /*!< SPI0 clock */
+    RCU_USART0  = RCU_REGIDX_BIT(IDX_APB2EN, 14U),                /*!< USART0 clock */
+    RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U),                /*!< TIMER14 clock */
+    RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U),                /*!< TIMER15 clock */
+    RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U),                /*!< TIMER16 clock */
+    
+    /* APB1 peripherals */
+    RCU_TIMER1  = RCU_REGIDX_BIT(IDX_APB1EN, 0U),                 /*!< TIMER1 clock */
+    RCU_TIMER2  = RCU_REGIDX_BIT(IDX_APB1EN, 1U),                 /*!< TIMER2 clock */
+    RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U),                 /*!< TIMER13 clock */
+    RCU_WWDGT   = RCU_REGIDX_BIT(IDX_APB1EN, 11U),                /*!< WWDGT clock */
+    RCU_SPI1    = RCU_REGIDX_BIT(IDX_APB1EN, 14U),                /*!< SPI1 clock */
+    RCU_USART1  = RCU_REGIDX_BIT(IDX_APB1EN, 17U),                /*!< USART1 clock */
+    RCU_I2C0    = RCU_REGIDX_BIT(IDX_APB1EN, 21U),                /*!< I2C0 clock */
+    RCU_I2C1    = RCU_REGIDX_BIT(IDX_APB1EN, 22U),                /*!< I2C1 clock */
+    RCU_PMU     = RCU_REGIDX_BIT(IDX_APB1EN, 28U),                /*!< PMU clock */
+#if defined(GD32F350)
+    RCU_DAC     = RCU_REGIDX_BIT(IDX_APB1EN, 29U),                /*!< DAC clock */
+    RCU_CEC     = RCU_REGIDX_BIT(IDX_APB1EN, 30U),                /*!< CEC clock */
+    RCU_TIMER5  = RCU_REGIDX_BIT(IDX_APB1EN, 4U),                 /*!< TIMER5 clock */
+    RCU_USBFS   = RCU_REGIDX_BIT(IDX_AHBEN, 12U),                 /*!< USBFS clock */
+#endif /* GD32F350 */
+    RCU_RTC     = RCU_REGIDX_BIT(IDX_BDCTL, 15U),                 /*!< RTC clock */
+    
+    /* RCU_ADDAPB1EN */
+    RCU_CTC     = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 27U)              /*!< CTC clock */
+}rcu_periph_enum;
+
+/* peripheral clock enable when sleep mode*/
+typedef enum
+{
+    /* AHB peripherals */
+    RCU_SRAM_SLP     = RCU_REGIDX_BIT(IDX_AHBEN, 2U),             /*!< SRAM clock */
+    RCU_FMC_SLP      = RCU_REGIDX_BIT(IDX_AHBEN, 4U),             /*!< FMC clock */
+}rcu_periph_sleep_enum;
+
+/* peripherals reset */
+typedef enum
+{
+    /* AHB peripherals reset */
+    RCU_GPIOARST   = RCU_REGIDX_BIT(IDX_AHBRST, 17U),             /*!< GPIOA reset */
+    RCU_GPIOBRST   = RCU_REGIDX_BIT(IDX_AHBRST, 18U),             /*!< GPIOB reset */
+    RCU_GPIOCRST   = RCU_REGIDX_BIT(IDX_AHBRST, 19U),             /*!< GPIOC reset */
+    RCU_GPIODRST   = RCU_REGIDX_BIT(IDX_AHBRST, 20U),             /*!< GPIOD reset */
+    RCU_GPIOFRST   = RCU_REGIDX_BIT(IDX_AHBRST, 22U),             /*!< GPIOF reset */
+    RCU_TSIRST     = RCU_REGIDX_BIT(IDX_AHBRST, 24U),             /*!< TSI reset */
+    
+    /* APB2 peripherals reset */
+    RCU_CFGCMPRST  = RCU_REGIDX_BIT(IDX_APB2RST, 0U),             /*!< CFGCMP reset */
+    RCU_ADCRST     = RCU_REGIDX_BIT(IDX_APB2RST, 9U),             /*!< ADC reset */
+    RCU_TIMER0RST  = RCU_REGIDX_BIT(IDX_APB2RST, 11U),            /*!< TIMER0 reset */
+    RCU_SPI0RST    = RCU_REGIDX_BIT(IDX_APB2RST, 12U),            /*!< SPI0 reset */
+    RCU_USART0RST  = RCU_REGIDX_BIT(IDX_APB2RST, 14U),            /*!< USART0 reset */
+    RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U),            /*!< TIMER14 reset */
+    RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U),            /*!< TIMER15 reset */
+    RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U),            /*!< TIMER16 reset */
+    
+    /* APB1 peripherals reset */
+    RCU_TIMER1RST  = RCU_REGIDX_BIT(IDX_APB1RST, 0U),             /*!< TIMER1 reset */
+    RCU_TIMER2RST  = RCU_REGIDX_BIT(IDX_APB1RST, 1U),             /*!< TIMER2 reset */
+    RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U),             /*!< TIMER13 reset */
+    RCU_WWDGTRST   = RCU_REGIDX_BIT(IDX_APB1RST, 11U),            /*!< WWDGT reset */
+    RCU_SPI1RST    = RCU_REGIDX_BIT(IDX_APB1RST, 14U),            /*!< SPI1 reset */
+    RCU_USART1RST  = RCU_REGIDX_BIT(IDX_APB1RST, 17U),            /*!< USART1 reset */
+    RCU_I2C0RST    = RCU_REGIDX_BIT(IDX_APB1RST, 21U),            /*!< I2C0 reset */
+    RCU_I2C1RST    = RCU_REGIDX_BIT(IDX_APB1RST, 22U),            /*!< I2C1 reset */
+    RCU_PMURST     = RCU_REGIDX_BIT(IDX_APB1RST, 28U),            /*!< PMU reset */
+#if defined(GD32F350)
+    RCU_DACRST     = RCU_REGIDX_BIT(IDX_APB1RST, 29U),            /*!< DAC reset */
+    RCU_CECRST     = RCU_REGIDX_BIT(IDX_APB1RST, 30U),            /*!< CEC reset */
+    RCU_TIMER5RST  = RCU_REGIDX_BIT(IDX_APB1RST, 4U),             /*!< TIMER5 reset */
+    RCU_USBFSRST   = RCU_REGIDX_BIT(IDX_AHBRST, 12U),             /*!< USBFS reset */
+#endif /* GD32F350 */
+    /* RCU_ADDAPB1RST */
+    RCU_CTCRST     = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 27U),         /*!< CTC reset */
+}rcu_periph_reset_enum;
+
+/* clock stabilization and peripheral reset flags */
+typedef enum
+{
+    RCU_FLAG_IRC40KSTB    = RCU_REGIDX_BIT(IDX_RSTSCK, 1U),       /*!< IRC40K stabilization flags */
+    RCU_FLAG_LXTALSTB     = RCU_REGIDX_BIT(IDX_BDCTL, 1U),        /*!< LXTAL stabilization flags */
+    RCU_FLAG_IRC8MSTB     = RCU_REGIDX_BIT(IDX_CTL0, 1U),         /*!< IRC8M stabilization flags */
+    RCU_FLAG_HXTALSTB     = RCU_REGIDX_BIT(IDX_CTL0, 17U),        /*!< HXTAL stabilization flags */
+    RCU_FLAG_PLLSTB       = RCU_REGIDX_BIT(IDX_CTL0, 25U),        /*!< PLL stabilization flags */
+    RCU_FLAG_IRC28MSTB    = RCU_REGIDX_BIT(IDX_CTL1, 1U),         /*!< IRC28M stabilization flags */
+    RCU_FLAG_IRC48MSTB    = RCU_REGIDX_BIT(IDX_ADDCTL, 17U),      /*!< IRC48M stabilization flags */
+
+    RCU_FLAG_V12RST       = RCU_REGIDX_BIT(IDX_RSTSCK, 23U),      /*!< V12 reset flags */
+    RCU_FLAG_OBLRST       = RCU_REGIDX_BIT(IDX_RSTSCK, 25U),      /*!< OBL reset flags */
+    RCU_FLAG_EPRST        = RCU_REGIDX_BIT(IDX_RSTSCK, 26U),      /*!< EPR reset flags */
+    RCU_FLAG_PORRST       = RCU_REGIDX_BIT(IDX_RSTSCK, 27U),      /*!< power reset flags */
+    RCU_FLAG_SWRST        = RCU_REGIDX_BIT(IDX_RSTSCK, 28U),      /*!< SW reset flags */
+    RCU_FLAG_FWDGTRST     = RCU_REGIDX_BIT(IDX_RSTSCK, 29U),      /*!< FWDGT reset flags */
+    RCU_FLAG_WWDGTRST     = RCU_REGIDX_BIT(IDX_RSTSCK, 30U),      /*!< WWDGT reset flags */
+    RCU_FLAG_LPRST        = RCU_REGIDX_BIT(IDX_RSTSCK, 31U)       /*!< LP reset flags */
+}rcu_flag_enum;
+
+/* clock stabilization and ckm interrupt flags */
+typedef enum
+{
+    RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U),         /*!< IRC40K stabilization interrupt flag */
+    RCU_INT_FLAG_LXTALSTB  = RCU_REGIDX_BIT(IDX_INT, 1U),         /*!< LXTAL stabilization interrupt flag */
+    RCU_INT_FLAG_IRC8MSTB  = RCU_REGIDX_BIT(IDX_INT, 2U),         /*!< IRC8M stabilization interrupt flag */
+    RCU_INT_FLAG_HXTALSTB  = RCU_REGIDX_BIT(IDX_INT, 3U),         /*!< HXTAL stabilization interrupt flag */
+    RCU_INT_FLAG_PLLSTB    = RCU_REGIDX_BIT(IDX_INT, 4U),         /*!< PLL stabilization interrupt flag */
+    RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U),         /*!< IRC28M stabilization interrupt flag */
+    RCU_INT_FLAG_CKM       = RCU_REGIDX_BIT(IDX_INT, 7U),         /*!< CKM interrupt flag */
+    RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 6U)       /*!< IRC48M stabilization interrupt flag */
+}rcu_int_flag_enum;
+
+/* clock stabilization and stuck interrupt flags clear */
+typedef enum
+{
+    RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U),    /*!< IRC40K stabilization interrupt flags clear */
+    RCU_INT_FLAG_LXTALSTB_CLR  = RCU_REGIDX_BIT(IDX_INT, 17U),    /*!< LXTAL stabilization interrupt flags clear */
+    RCU_INT_FLAG_IRC8MSTB_CLR  = RCU_REGIDX_BIT(IDX_INT, 18U),    /*!< IRC8M stabilization interrupt flags clear */
+    RCU_INT_FLAG_HXTALSTB_CLR  = RCU_REGIDX_BIT(IDX_INT, 19U),    /*!< HXTAL stabilization interrupt flags clear */
+    RCU_INT_FLAG_PLLSTB_CLR    = RCU_REGIDX_BIT(IDX_INT, 20U),    /*!< PLL stabilization interrupt flags clear */
+    RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U),    /*!< IRC28M stabilization interrupt flags clear */
+    RCU_INT_FLAG_CKM_CLR       = RCU_REGIDX_BIT(IDX_INT, 23U),    /*!< CKM interrupt flags clear */
+    RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(IDX_ADDCTL, 22U)  /*!< IRC48M stabilization interrupt flag clear */
+}rcu_int_flag_clear_enum;
+
+/* clock stabilization interrupt enable or disable */
+typedef enum
+{
+    RCU_INT_IRC40KSTB       = RCU_REGIDX_BIT(IDX_INT, 8U),        /*!< IRC40K stabilization interrupt */
+    RCU_INT_LXTALSTB        = RCU_REGIDX_BIT(IDX_INT, 9U),        /*!< LXTAL stabilization interrupt */
+    RCU_INT_IRC8MSTB        = RCU_REGIDX_BIT(IDX_INT, 10U),       /*!< IRC8M stabilization interrupt */
+    RCU_INT_HXTALSTB        = RCU_REGIDX_BIT(IDX_INT, 11U),       /*!< HXTAL stabilization interrupt */
+    RCU_INT_PLLSTB          = RCU_REGIDX_BIT(IDX_INT, 12U),       /*!< PLL stabilization interrupt */
+    RCU_INT_IRC28MSTB       = RCU_REGIDX_BIT(IDX_INT, 13U),       /*!< IRC28M stabilization interrupt */
+    RCU_INT_IRC48MSTB       = RCU_REGIDX_BIT(IDX_ADDINT, 14U)     /*!< IRC48M stabilization interrupt */
+}rcu_int_enum;
+
+/* ADC clock source */
+typedef enum
+{
+    RCU_ADCCK_IRC28M_DIV2   = 0U,                                 /*!< ADC clock source select IRC28M/2 */
+    RCU_ADCCK_IRC28M,                                             /*!< ADC clock source select IRC28M */
+    RCU_ADCCK_APB2_DIV2,                                          /*!< ADC clock source select APB2/2 */
+    RCU_ADCCK_AHB_DIV3,                                           /*!< ADC clock source select AHB/3 */
+    RCU_ADCCK_APB2_DIV4,                                          /*!< ADC clock source select APB2/4 */
+    RCU_ADCCK_AHB_DIV5,                                           /*!< ADC clock source select AHB/5 */
+    RCU_ADCCK_APB2_DIV6,                                          /*!< ADC clock source select APB2/6 */
+    RCU_ADCCK_AHB_DIV7,                                           /*!< ADC clock source select AHB/7 */
+    RCU_ADCCK_APB2_DIV8,                                          /*!< ADC clock source select APB2/8 */
+    RCU_ADCCK_AHB_DIV9                                            /*!< ADC clock source select AHB/9 */
+}rcu_adc_clock_enum;
+
+/* oscillator types */
+typedef enum
+{
+    RCU_HXTAL   = RCU_REGIDX_BIT(IDX_CTL0, 16U),                  /*!< HXTAL */
+    RCU_LXTAL   = RCU_REGIDX_BIT(IDX_BDCTL, 0U),                  /*!< LXTAL */
+    RCU_IRC8M   = RCU_REGIDX_BIT(IDX_CTL0, 0U),                   /*!< IRC8M */
+    RCU_IRC28M  = RCU_REGIDX_BIT(IDX_CTL1, 0U),                   /*!< IRC28M */
+    RCU_IRC48M  = RCU_REGIDX_BIT(IDX_ADDCTL, 16U),                /*!< IRC48M */
+    RCU_IRC40K  = RCU_REGIDX_BIT(IDX_RSTSCK, 0U),                 /*!< IRC40K */
+    RCU_PLL_CK  = RCU_REGIDX_BIT(IDX_CTL0, 24U)                   /*!< PLL */
+}rcu_osci_type_enum;
+
+/* rcu clock frequency */
+typedef enum
+{
+    CK_SYS      = 0U,                                             /*!< system clock */
+    CK_AHB,                                                       /*!< AHB clock */
+    CK_APB1,                                                      /*!< APB1 clock */
+    CK_APB2,                                                      /*!< APB2 clock */
+    CK_ADC,                                                       /*!< ADC clock */
+    CK_CEC,                                                       /*!< CEC clock */
+    CK_USART                                                      /*!< USART clock */
+}rcu_clock_freq_enum;
+
+/* system clock source select */
+#define CFG0_SCS(regval)            (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define RCU_CKSYSSRC_IRC8M          CFG0_SCS(0)                   /*!< system clock source select IRC8M */
+#define RCU_CKSYSSRC_HXTAL          CFG0_SCS(1)                   /*!< system clock source select HXTAL */
+#define RCU_CKSYSSRC_PLL            CFG0_SCS(2)                   /*!< system clock source select PLL */
+
+/* system clock source select status */
+#define CFG0_SCSS(regval)           (BITS(2,3) & ((uint32_t)(regval) << 2))
+#define RCU_SCSS_IRC8M              CFG0_SCSS(0)                  /*!< system clock source select IRC8M */
+#define RCU_SCSS_HXTAL              CFG0_SCSS(1)                  /*!< system clock source select HXTAL */
+#define RCU_SCSS_PLL                CFG0_SCSS(2)                  /*!< system clock source select PLL */
+
+/* AHB prescaler selection */
+#define CFG0_AHBPSC(regval)         (BITS(4,7) & ((uint32_t)(regval) << 4))
+#define RCU_AHB_CKSYS_DIV1          CFG0_AHBPSC(0)                /*!< AHB prescaler select CK_SYS */
+#define RCU_AHB_CKSYS_DIV2          CFG0_AHBPSC(8)                /*!< AHB prescaler select CK_SYS/2 */
+#define RCU_AHB_CKSYS_DIV4          CFG0_AHBPSC(9)                /*!< AHB prescaler select CK_SYS/4 */
+#define RCU_AHB_CKSYS_DIV8          CFG0_AHBPSC(10)               /*!< AHB prescaler select CK_SYS/8 */
+#define RCU_AHB_CKSYS_DIV16         CFG0_AHBPSC(11)               /*!< AHB prescaler select CK_SYS/16 */
+#define RCU_AHB_CKSYS_DIV64         CFG0_AHBPSC(12)               /*!< AHB prescaler select CK_SYS/64 */
+#define RCU_AHB_CKSYS_DIV128        CFG0_AHBPSC(13)               /*!< AHB prescaler select CK_SYS/128 */
+#define RCU_AHB_CKSYS_DIV256        CFG0_AHBPSC(14)               /*!< AHB prescaler select CK_SYS/256 */
+#define RCU_AHB_CKSYS_DIV512        CFG0_AHBPSC(15)               /*!< AHB prescaler select CK_SYS/512 */
+
+/* APB1 prescaler selection */
+#define CFG0_APB1PSC(regval)        (BITS(8,10) & ((uint32_t)(regval) << 8))
+#define RCU_APB1_CKAHB_DIV1         CFG0_APB1PSC(0)               /*!< APB1 prescaler select CK_AHB */
+#define RCU_APB1_CKAHB_DIV2         CFG0_APB1PSC(4)               /*!< APB1 prescaler select CK_AHB/2 */
+#define RCU_APB1_CKAHB_DIV4         CFG0_APB1PSC(5)               /*!< APB1 prescaler select CK_AHB/4 */
+#define RCU_APB1_CKAHB_DIV8         CFG0_APB1PSC(6)               /*!< APB1 prescaler select CK_AHB/8 */
+#define RCU_APB1_CKAHB_DIV16        CFG0_APB1PSC(7)               /*!< APB1 prescaler select CK_AHB/16 */
+
+/* APB2 prescaler selection */
+#define CFG0_APB2PSC(regval)        (BITS(11,13) & ((uint32_t)(regval) << 11))
+#define RCU_APB2_CKAHB_DIV1         CFG0_APB2PSC(0)               /*!< APB2 prescaler select CK_AHB */
+#define RCU_APB2_CKAHB_DIV2         CFG0_APB2PSC(4)               /*!< APB2 prescaler select CK_AHB/2 */
+#define RCU_APB2_CKAHB_DIV4         CFG0_APB2PSC(5)               /*!< APB2 prescaler select CK_AHB/4 */
+#define RCU_APB2_CKAHB_DIV8         CFG0_APB2PSC(6)               /*!< APB2 prescaler select CK_AHB/8 */
+#define RCU_APB2_CKAHB_DIV16        CFG0_APB2PSC(7)               /*!< APB2 prescaler select CK_AHB/16 */
+
+/* ADC clock prescaler selection */
+#define CFG0_ADCPSC(regval)         (BITS(14,15) & ((uint32_t)(regval) << 14))
+#define RCU_ADC_CKAPB2_DIV2         CFG0_ADCPSC(0)                /*!< ADC clock prescaler select CK_APB2/2 */
+#define RCU_ADC_CKAPB2_DIV4         CFG0_ADCPSC(1)                /*!< ADC clock prescaler select CK_APB2/4 */
+#define RCU_ADC_CKAPB2_DIV6         CFG0_ADCPSC(2)                /*!< ADC clock prescaler select CK_APB2/6 */
+#define RCU_ADC_CKAPB2_DIV8         CFG0_ADCPSC(3)                /*!< ADC clock prescaler select CK_APB2/8 */
+
+/* PLL clock source selection */
+#define RCU_PLLSRC_IRC8M_DIV2       ((uint32_t)0x00000000U)       /*!< PLL clock source select IRC8M/2 */
+#define RCU_PLLSRC_HXTAL_IRC48M     RCU_CFG0_PLLSEL               /*!< PLL clock source select HXTAL or IRC48M*/
+
+/* PLL clock source preselection */
+#define RCU_PLLPRESEL_HXTAL         ((uint32_t)0x00000000U)       /*!< PLL clock source preselection HXTAL */
+#define RCU_PLLPRESEL_IRC48M        RCU_CFG1_PLLPRESEL            /*!< PLL clock source preselection IRC48M */
+
+/* HXTAL or IRC48M divider for PLL source clock selection */
+#define RCU_PLLPREDV                ((uint32_t)0x00000000U)       /*!< HXTAL or IRC48M clock selected */
+#define RCU_PLLPREDV_DIV2           RCU_CFG0_PLLPREDV             /*!< (HXTAL or IRC48M) /2 clock selected */
+
+/* PLL multiply factor */
+#define CFG0_PLLMF(regval)          (BITS(18,21) & ((uint32_t)(regval) << 18))
+#define RCU_PLL_MUL2                CFG0_PLLMF(0)                       /*!< PLL source clock multiply by 2 */
+#define RCU_PLL_MUL3                CFG0_PLLMF(1)                       /*!< PLL source clock multiply by 3 */
+#define RCU_PLL_MUL4                CFG0_PLLMF(2)                       /*!< PLL source clock multiply by 4 */
+#define RCU_PLL_MUL5                CFG0_PLLMF(3)                       /*!< PLL source clock multiply by 5 */
+#define RCU_PLL_MUL6                CFG0_PLLMF(4)                       /*!< PLL source clock multiply by 6 */
+#define RCU_PLL_MUL7                CFG0_PLLMF(5)                       /*!< PLL source clock multiply by 7 */
+#define RCU_PLL_MUL8                CFG0_PLLMF(6)                       /*!< PLL source clock multiply by 8 */
+#define RCU_PLL_MUL9                CFG0_PLLMF(7)                       /*!< PLL source clock multiply by 9 */
+#define RCU_PLL_MUL10               CFG0_PLLMF(8)                       /*!< PLL source clock multiply by 10 */
+#define RCU_PLL_MUL11               CFG0_PLLMF(9)                       /*!< PLL source clock multiply by 11 */
+#define RCU_PLL_MUL12               CFG0_PLLMF(10)                      /*!< PLL source clock multiply by 12 */
+#define RCU_PLL_MUL13               CFG0_PLLMF(11)                      /*!< PLL source clock multiply by 13 */
+#define RCU_PLL_MUL14               CFG0_PLLMF(12)                      /*!< PLL source clock multiply by 14 */
+#define RCU_PLL_MUL15               CFG0_PLLMF(13)                      /*!< PLL source clock multiply by 15 */
+#define RCU_PLL_MUL16               CFG0_PLLMF(14)                      /*!< PLL source clock multiply by 16 */
+#define RCU_PLL_MUL17               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0))   /*!< PLL source clock multiply by 17 */
+#define RCU_PLL_MUL18               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1))   /*!< PLL source clock multiply by 18 */
+#define RCU_PLL_MUL19               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2))   /*!< PLL source clock multiply by 19 */
+#define RCU_PLL_MUL20               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3))   /*!< PLL source clock multiply by 20 */
+#define RCU_PLL_MUL21               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4))   /*!< PLL source clock multiply by 21 */
+#define RCU_PLL_MUL22               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5))   /*!< PLL source clock multiply by 22 */
+#define RCU_PLL_MUL23               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6))   /*!< PLL source clock multiply by 23 */
+#define RCU_PLL_MUL24               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7))   /*!< PLL source clock multiply by 24 */
+#define RCU_PLL_MUL25               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8))   /*!< PLL source clock multiply by 25 */
+#define RCU_PLL_MUL26               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9))   /*!< PLL source clock multiply by 26 */
+#define RCU_PLL_MUL27               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10))  /*!< PLL source clock multiply by 27 */
+#define RCU_PLL_MUL28               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11))  /*!< PLL source clock multiply by 28 */
+#define RCU_PLL_MUL29               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12))  /*!< PLL source clock multiply by 29 */
+#define RCU_PLL_MUL30               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13))  /*!< PLL source clock multiply by 30 */
+#define RCU_PLL_MUL31               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14))  /*!< PLL source clock multiply by 31 */
+#define RCU_PLL_MUL32               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15))  /*!< PLL source clock multiply by 32 */
+#define RCU_PLL_MUL33               (CFG0_PLLMF(0) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 33 */
+#define RCU_PLL_MUL34               (CFG0_PLLMF(1) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 34 */
+#define RCU_PLL_MUL35               (CFG0_PLLMF(2) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 35 */
+#define RCU_PLL_MUL36               (CFG0_PLLMF(3) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 36 */
+#define RCU_PLL_MUL37               (CFG0_PLLMF(4) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 37 */
+#define RCU_PLL_MUL38               (CFG0_PLLMF(5) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 38 */
+#define RCU_PLL_MUL39               (CFG0_PLLMF(6) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 39 */
+#define RCU_PLL_MUL40               (CFG0_PLLMF(7) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 40 */
+#define RCU_PLL_MUL41               (CFG0_PLLMF(8) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 41 */
+#define RCU_PLL_MUL42               (CFG0_PLLMF(9) | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 42 */
+#define RCU_PLL_MUL43               (CFG0_PLLMF(10) | RCU_CFG1_PLLMF5)  /*!< PLL source clock multiply by 43 */
+#define RCU_PLL_MUL44               (CFG0_PLLMF(11) | RCU_CFG1_PLLMF5)  /*!< PLL source clock multiply by 44 */
+#define RCU_PLL_MUL45               (CFG0_PLLMF(12) | RCU_CFG1_PLLMF5)  /*!< PLL source clock multiply by 45 */
+#define RCU_PLL_MUL46               (CFG0_PLLMF(13) | RCU_CFG1_PLLMF5)  /*!< PLL source clock multiply by 46 */
+#define RCU_PLL_MUL47               (CFG0_PLLMF(14) | RCU_CFG1_PLLMF5)  /*!< PLL source clock multiply by 47 */
+#define RCU_PLL_MUL48               (CFG0_PLLMF(15) | RCU_CFG1_PLLMF5)  /*!< PLL source clock multiply by 48 */
+#define RCU_PLL_MUL49               (RCU_CFG0_PLLMF4 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 49 */
+#define RCU_PLL_MUL50               (RCU_PLL_MUL18 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 50 */
+#define RCU_PLL_MUL51               (RCU_PLL_MUL19 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 51 */
+#define RCU_PLL_MUL52               (RCU_PLL_MUL20 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 52 */
+#define RCU_PLL_MUL53               (RCU_PLL_MUL21 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 53 */
+#define RCU_PLL_MUL54               (RCU_PLL_MUL22 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 54 */
+#define RCU_PLL_MUL55               (RCU_PLL_MUL23 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 55 */
+#define RCU_PLL_MUL56               (RCU_PLL_MUL24 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 56 */
+#define RCU_PLL_MUL57               (RCU_PLL_MUL25 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 57 */
+#define RCU_PLL_MUL58               (RCU_PLL_MUL26 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 58 */
+#define RCU_PLL_MUL59               (RCU_PLL_MUL27 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 59 */
+#define RCU_PLL_MUL60               (RCU_PLL_MUL28 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 60 */
+#define RCU_PLL_MUL61               (RCU_PLL_MUL29 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 61 */
+#define RCU_PLL_MUL62               (RCU_PLL_MUL30 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 62 */
+#define RCU_PLL_MUL63               (RCU_PLL_MUL31 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 63 */
+#define RCU_PLL_MUL64               (RCU_PLL_MUL32 | RCU_CFG1_PLLMF5)   /*!< PLL source clock multiply by 64 */
+
+/* USBFS clock prescaler selection */
+#define CFG0_USBFSPSC(regval)       (BITS(22,23) & ((uint32_t)(regval) << 22))
+#define RCU_USBFS_CKPLL_DIV1_5      CFG0_USBFSPSC(0)                      /*!< USBFS clock prescaler select CK_PLL/1.5 */
+#define RCU_USBFS_CKPLL_DIV1        CFG0_USBFSPSC(1)                      /*!< USBFS clock prescaler select CK_PLL */
+#define RCU_USBFS_CKPLL_DIV2_5      CFG0_USBFSPSC(2)                      /*!< USBFS clock prescaler select CK_PLL/2.5 */
+#define RCU_USBFS_CKPLL_DIV2        CFG0_USBFSPSC(3)                      /*!< USBFS clock prescaler select CK_PLL/2 */
+#define RCU_USBFS_CKPLL_DIV3        RCU_CFG2_USBFSPSC2                    /*!< USBFS clock prescaler select CK_PLL/3 */
+#define RCU_USBFS_CKPLL_DIV3_5      (CFG0_USBFSPSC(1)|RCU_CFG2_USBFSPSC2) /*!< USBFS clock prescaler select CK_PLL/3.5 */
+
+/* CK_OUT clock source selection */
+#define CFG0_CKOUTSEL(regval)       (BITS(24,26) & ((uint32_t)(regval) << 24))
+#define RCU_CKOUTSRC_NONE           CFG0_CKOUTSEL(0)                      /*!< no clock selected */
+#define RCU_CKOUTSRC_IRC28M         CFG0_CKOUTSEL(1)                      /*!< CK_OUT clock source select IRC28M */
+#define RCU_CKOUTSRC_IRC40K         CFG0_CKOUTSEL(2)                      /*!< CK_OUT clock source select IRC40K */
+#define RCU_CKOUTSRC_LXTAL          CFG0_CKOUTSEL(3)                      /*!< CK_OUT clock source select LXTAL */
+#define RCU_CKOUTSRC_CKSYS          CFG0_CKOUTSEL(4)                      /*!< CK_OUT clock source select CKSYS */
+#define RCU_CKOUTSRC_IRC8M          CFG0_CKOUTSEL(5)                      /*!< CK_OUT clock source select IRC8M */
+#define RCU_CKOUTSRC_HXTAL          CFG0_CKOUTSEL(6)                      /*!< CK_OUT clock source select HXTAL */
+#define RCU_CKOUTSRC_CKPLL_DIV1     (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7))   /*!< CK_OUT clock source select CK_PLL */
+#define RCU_CKOUTSRC_CKPLL_DIV2     CFG0_CKOUTSEL(7)                      /*!< CK_OUT clock source select CK_PLL/2 */
+
+/* CK_OUT divider */
+#define CFG0_CKOUTDIV(regval)       (BITS(28,30) & ((uint32_t)(regval) << 28))
+#define RCU_CKOUT_DIV1              CFG0_CKOUTDIV(0)                      /*!< CK_OUT is divided by 1 */
+#define RCU_CKOUT_DIV2              CFG0_CKOUTDIV(1)                      /*!< CK_OUT is divided by 2 */
+#define RCU_CKOUT_DIV4              CFG0_CKOUTDIV(2)                      /*!< CK_OUT is divided by 4 */
+#define RCU_CKOUT_DIV8              CFG0_CKOUTDIV(3)                      /*!< CK_OUT is divided by 8 */
+#define RCU_CKOUT_DIV16             CFG0_CKOUTDIV(4)                      /*!< CK_OUT is divided by 16 */
+#define RCU_CKOUT_DIV32             CFG0_CKOUTDIV(5)                      /*!< CK_OUT is divided by 32 */
+#define RCU_CKOUT_DIV64             CFG0_CKOUTDIV(6)                      /*!< CK_OUT is divided by 64 */
+#define RCU_CKOUT_DIV128            CFG0_CKOUTDIV(7)                      /*!< CK_OUT is divided by 128 */
+
+/* CK_PLL divide by 1 or 2 for CK_OUT */
+#define RCU_PLLDV_CKPLL_DIV2        ((uint32_t)0x00000000U)               /*!< CK_PLL divide by 2 for CK_OUT */
+#define RCU_PLLDV_CKPLL             RCU_CFG0_PLLDV                        /*!< CK_PLL divide by 1 for CK_OUT */
+
+/* LXTAL drive capability */
+#define BDCTL_LXTALDRI(regval)      (BITS(3,4) & ((uint32_t)(regval) << 3))
+#define RCU_LXTAL_LOWDRI            BDCTL_LXTALDRI(0)                     /*!< lower driving capability */
+#define RCU_LXTAL_MED_LOWDRI        BDCTL_LXTALDRI(1)                     /*!< medium low driving capability */
+#define RCU_LXTAL_MED_HIGHDRI       BDCTL_LXTALDRI(2)                     /*!< medium high driving capability */
+#define RCU_LXTAL_HIGHDRI           BDCTL_LXTALDRI(3)                     /*!< higher driving capability */
+
+/* RTC clock entry selection */
+#define BDCTL_RTCSRC(regval)        (BITS(8,9) & ((uint32_t)(regval) << 8))
+#define RCU_RTCSRC_NONE             BDCTL_RTCSRC(0)                       /*!< no clock selected */
+#define RCU_RTCSRC_LXTAL            BDCTL_RTCSRC(1)                       /*!< LXTAL selected as RTC source clock */
+#define RCU_RTCSRC_IRC40K           BDCTL_RTCSRC(2)                       /*!< IRC40K selected as RTC source clock */
+#define RCU_RTCSRC_HXTAL_DIV32      BDCTL_RTCSRC(3)                       /*!< HXTAL/32 selected as RTC source clock */
+
+/* CK_HXTAL divider previous PLL */
+#define CFG1_PREDV(regval)         (BITS(0,3) & ((uint32_t)(regval) << 0))
+#define RCU_PLL_PREDV1              CFG1_PREDV(0)                         /*!< PLL not divided */
+#define RCU_PLL_PREDV2              CFG1_PREDV(1)                         /*!< PLL divided by 2 */
+#define RCU_PLL_PREDV3              CFG1_PREDV(2)                         /*!< PLL divided by 3 */
+#define RCU_PLL_PREDV4              CFG1_PREDV(3)                         /*!< PLL divided by 4 */
+#define RCU_PLL_PREDV5              CFG1_PREDV(4)                         /*!< PLL divided by 5 */
+#define RCU_PLL_PREDV6              CFG1_PREDV(5)                         /*!< PLL divided by 6 */
+#define RCU_PLL_PREDV7              CFG1_PREDV(6)                         /*!< PLL divided by 7 */
+#define RCU_PLL_PREDV8              CFG1_PREDV(7)                         /*!< PLL divided by 8 */
+#define RCU_PLL_PREDV9              CFG1_PREDV(8)                         /*!< PLL divided by 9 */
+#define RCU_PLL_PREDV10             CFG1_PREDV(9)                         /*!< PLL divided by 10 */
+#define RCU_PLL_PREDV11             CFG1_PREDV(10)                        /*!< PLL divided by 11 */
+#define RCU_PLL_PREDV12             CFG1_PREDV(11)                        /*!< PLL divided by 12 */
+#define RCU_PLL_PREDV13             CFG1_PREDV(12)                        /*!< PLL divided by 13 */
+#define RCU_PLL_PREDV14             CFG1_PREDV(13)                        /*!< PLL divided by 14 */
+#define RCU_PLL_PREDV15             CFG1_PREDV(14)                        /*!< PLL divided by 15 */
+#define RCU_PLL_PREDV16             CFG1_PREDV(15)                        /*!< PLL divided by 16 */
+
+/* USART0 clock source selection */
+#define CFG2_USART0SEL(regval)      (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define RCU_USART0SRC_CKAPB2        CFG2_USART0SEL(0)                     /*!< CK_USART0 select CK_APB2 */
+#define RCU_USART0SRC_CKSYS         CFG2_USART0SEL(1)                     /*!< CK_USART0 select CK_SYS */
+#define RCU_USART0SRC_LXTAL         CFG2_USART0SEL(2)                     /*!< CK_USART0 select LXTAL */
+#define RCU_USART0SRC_IRC8M         CFG2_USART0SEL(3)                     /*!< CK_USART0 select IRC8M */
+
+/* CEC clock source selection */
+#define RCU_CECSRC_IRC8M_DIV244     ((uint32_t)0x00000000U)               /*!< CK_CEC clock source select IRC8M/244 */
+#define RCU_CECSRC_LXTAL            RCU_CFG2_CECSEL                       /*!< CK_CEC clock source select LXTAL */
+
+/* ADC clock source selection */
+#define RCU_ADCSRC_IRC28M           ((uint32_t)0x00000000U)               /*!< ADC clock source select */
+#define RCU_ADCSRC_AHB_APB2DIV      RCU_CFG2_ADCSEL                       /*!< ADC clock source select */
+
+/* IRC28M clock divider for ADC */
+#define RCU_ADC_IRC28M_DIV2         ((uint32_t)0x00000000U)               /*!< IRC28M/2 select to ADC clock */
+#define RCU_ADC_IRC28M_DIV1         RCU_CFG2_IRC28MDIV                    /*!< IRC28M select to ADC clock */
+
+/* CK48M clock source selection */ 
+#define RCU_CK48MSRC_PLL48M         ((uint32_t)0x00000000U)               /*!< CK48M source clock select PLL48M */
+#define RCU_CK48MSRC_IRC48M         RCU_ADDCTL_CK48MSEL                   /*!< CK48M source clock select IRC48M */
+
+/* Deep-sleep mode voltage */
+#define DSV_DSLPVS(regval)          (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define RCU_DEEPSLEEP_V_1_0         DSV_DSLPVS(0)                         /*!< core voltage is 1.0V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_0_9         DSV_DSLPVS(1)                         /*!< core voltage is 0.9V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_0_8         DSV_DSLPVS(2)                         /*!< core voltage is 0.8V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_0_7         DSV_DSLPVS(3)                         /*!< core voltage is 0.7V in deep-sleep mode */
+
+/* function declarations */
+/* deinitialize the RCU */
+void rcu_deinit(void);
+/* enable the peripherals clock */
+void rcu_periph_clock_enable(rcu_periph_enum periph);
+/* disable the peripherals clock */
+void rcu_periph_clock_disable(rcu_periph_enum periph);
+/* enable the peripherals clock when sleep mode */
+void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
+/* disable the peripherals clock when sleep mode */
+void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
+/* reset the peripherals */
+void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
+/* disable reset the peripheral */
+void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
+/* reset the BKP */
+void rcu_bkp_reset_enable(void);
+/* disable the BKP reset */
+void rcu_bkp_reset_disable(void);
+
+/* configure the system clock source */
+void rcu_system_clock_source_config(uint32_t ck_sys);
+/* get the system clock source */
+uint32_t rcu_system_clock_source_get(void);
+/* configure the AHB prescaler selection */
+void rcu_ahb_clock_config(uint32_t ck_ahb);
+/* configure the APB1 prescaler selection */
+void rcu_apb1_clock_config(uint32_t ck_apb1);
+/* configure the APB2 prescaler selection */
+void rcu_apb2_clock_config(uint32_t ck_apb2);
+/* configure the ADC clock source and prescaler selection */
+void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc);
+/* configure the USBFS prescaler selection */
+void rcu_usbfs_clock_config(uint32_t ck_usbfs);
+/* configure the CK_OUT clock source and divider */
+void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div);
+
+/* configure the PLL clock source preselection */
+void rcu_pll_preselection_config(uint32_t pll_presel);
+/* configure the PLL clock source selection and PLL multiply factor */
+void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
+/* configure the USART clock source selection */
+void rcu_usart_clock_config(uint32_t ck_usart);
+/* configure the CEC clock source selection */
+void rcu_cec_clock_config(uint32_t ck_cec);
+/* configure the RTC clock source selection */
+void rcu_rtc_clock_config(uint32_t rtc_clock_source);
+/* configure the CK48M clock selection */
+void rcu_ck48m_clock_config(uint32_t ck48m_clock_source);
+/* configure the HXTAL divider used as input of PLL */
+void rcu_hxtal_prediv_config(uint32_t hxtal_prediv);
+/* configure the LXTAL drive capability */
+void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap);
+
+/* get the clock stabilization and periphral reset flags */
+FlagStatus rcu_flag_get(rcu_flag_enum flag);
+/* clear the reset flag */
+void rcu_all_reset_flag_clear(void);
+/* get the clock stabilization interrupt and ckm flags */
+FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
+/* clear the interrupt flags */
+void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
+/* enable the stabilization interrupt */
+void rcu_interrupt_enable(rcu_int_enum stab_int);
+/* disable the stabilization interrupt */
+void rcu_interrupt_disable(rcu_int_enum stab_int);
+
+/* wait until oscillator stabilization flags is SET */
+ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
+/* turn on the oscillator */
+void rcu_osci_on(rcu_osci_type_enum osci);
+/* turn off the oscillator */
+void rcu_osci_off(rcu_osci_type_enum osci);
+/* enable the oscillator bypass mode */
+void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
+/* disable the oscillator bypass mode */
+void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
+/* enable the HXTAL clock monitor */
+void rcu_hxtal_clock_monitor_enable(void);
+/* disable the HXTAL clock monitor */
+void rcu_hxtal_clock_monitor_disable(void);
+
+/* set the IRC8M adjust value */
+void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval);
+/* set the IRC28M adjust value */
+void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval);
+/* unlock the voltage key */
+void rcu_voltage_key_unlock(void);
+/* set the deep sleep mode voltage */
+void rcu_deepsleep_voltage_set(uint32_t dsvol);
+
+/* get the system clock, bus and peripheral clock frequency */
+uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
+
+#endif /* GD32F3X0_RCU_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_rtc.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_rtc.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_rtc.h
+    \file  gd32f3x0_rtc.h
     \brief definitions for the RTC 
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,460 +33,459 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_RTC_H
-#define GD32F1X0_RTC_H
+#ifndef GD32F3X0_RTC_H
+#define GD32F3X0_RTC_H
 
-#include "gd32f1x0.h"
+#include "gd32f3x0.h"
 
 /* RTC definitions */
 #define RTC                                RTC_BASE
 
 /* registers definitions */
-#define RTC_TIME                           REG32((RTC) + 0x00U)                       /*!< RTC time of day register */
-#define RTC_DATE                           REG32((RTC) + 0x04U)                       /*!< RTC date register */
-#define RTC_CTL                            REG32((RTC) + 0x08U)                       /*!< RTC control register */
-#define RTC_STAT                           REG32((RTC) + 0x0CU)                       /*!< RTC status register */
-#define RTC_PSC                            REG32((RTC) + 0x10U)                       /*!< RTC time prescaler register */
-#define RTC_ALRM0TD                        REG32((RTC) + 0x1CU)                       /*!< RTC alarm 0 time and date register */
-#define RTC_WPK                            REG32((RTC) + 0x24U)                       /*!< RTC write protection key register */
-#define RTC_SS                             REG32((RTC) + 0x28U)                       /*!< RTC sub second register */
-#define RTC_SHIFTCTL                       REG32((RTC) + 0x2CU)                       /*!< RTC shift function control register */
-#define RTC_TTS                            REG32((RTC) + 0x30U)                       /*!< RTC time of timestamp register */
-#define RTC_DTS                            REG32((RTC) + 0x34U)                       /*!< RTC date of timestamp register */
-#define RTC_SSTS                           REG32((RTC) + 0x38U)                       /*!< RTC sub second of timestamp register */
-#define RTC_HRFC                           REG32((RTC) + 0x3CU)                       /*!< RTC high resolution frequency compensation registor */
-#define RTC_TAMP                           REG32((RTC) + 0x40U)                       /*!< RTC tamper register */
-#define RTC_ALRM0SS                        REG32((RTC) + 0x44U)                       /*!< RTC alarm 0 sub second register */
-#define RTC_BKP0                           REG32((RTC) + 0x50U)                       /*!< RTC backup register */
-#define RTC_BKP1                           REG32((RTC) + 0x54U)                       /*!< RTC backup register */
-#define RTC_BKP2                           REG32((RTC) + 0x58U)                       /*!< RTC backup register */
-#define RTC_BKP3                           REG32((RTC) + 0x5CU)                       /*!< RTC backup register */
-#define RTC_BKP4                           REG32((RTC) + 0x60U)                       /*!< RTC backup register */
+#define RTC_TIME                           REG32(RTC + 0x00000000U)                    /*!< RTC time of day register */
+#define RTC_DATE                           REG32(RTC + 0x00000004U)                    /*!< RTC date register */
+#define RTC_CTL                            REG32(RTC + 0x00000008U)                    /*!< RTC control register */
+#define RTC_STAT                           REG32(RTC + 0x0000000CU)                    /*!< RTC status register */
+#define RTC_PSC                            REG32(RTC + 0x00000010U)                    /*!< RTC time prescaler register */
+#define RTC_ALRM0TD                        REG32(RTC + 0x0000001CU)                    /*!< RTC alarm 0 time and date register */
+#define RTC_WPK                            REG32(RTC + 0x00000024U)                    /*!< RTC write protection key register */
+#define RTC_SS                             REG32(RTC + 0x00000028U)                    /*!< RTC sub second register */
+#define RTC_SHIFTCTL                       REG32(RTC + 0x0000002CU)                    /*!< RTC shift function control register */
+#define RTC_TTS                            REG32(RTC + 0x00000030U)                    /*!< RTC time of timestamp register */
+#define RTC_DTS                            REG32(RTC + 0x00000034U)                    /*!< RTC date of timestamp register */
+#define RTC_SSTS                           REG32(RTC + 0x00000038U)                    /*!< RTC sub second of timestamp register */
+#define RTC_HRFC                           REG32(RTC + 0x0000003CU)                    /*!< RTC high resolution frequency compensation registor */
+#define RTC_TAMP                           REG32(RTC + 0x00000040U)                    /*!< RTC tamper register */
+#define RTC_ALRM0SS                        REG32(RTC + 0x00000044U)                    /*!< RTC alarm 0 sub second register */
+#define RTC_BKP0                           REG32(RTC + 0x00000050U)                    /*!< RTC backup 0 register */
+#define RTC_BKP1                           REG32(RTC + 0x00000054U)                    /*!< RTC backup 1 register */
+#define RTC_BKP2                           REG32(RTC + 0x00000058U)                    /*!< RTC backup 2 register */
+#define RTC_BKP3                           REG32(RTC + 0x0000005CU)                    /*!< RTC backup 3 register */
+#define RTC_BKP4                           REG32(RTC + 0x00000060U)                    /*!< RTC backup 4 register */
 
 /* bits definitions */
 /* RTC_TIME */
-#define RTC_TIME_SCU                       BITS(0,3)                                  /*!< second units in BCD code */
-#define RTC_TIME_SCT                       BITS(4,6)                                  /*!< second tens in BCD code */
-#define RTC_TIME_MNU                       BITS(8,11)                                 /*!< minute units in BCD code */
-#define RTC_TIME_MNT                       BITS(12,14)                                /*!< minute tens in BCD code */
-#define RTC_TIME_HRU                       BITS(16,19)                                /*!< hour units in BCD code */
-#define RTC_TIME_HRT                       BITS(20,21)                                /*!< hour tens in BCD code */
-#define RTC_TIME_PM                        BIT(22)                                    /*!< AM/PM notation */
+#define RTC_TIME_SCU                       BITS(0,3)                                   /*!< second units in BCD code */
+#define RTC_TIME_SCT                       BITS(4,6)                                   /*!< second tens in BCD code */
+#define RTC_TIME_MNU                       BITS(8,11)                                  /*!< minute units in BCD code */
+#define RTC_TIME_MNT                       BITS(12,14)                                 /*!< minute tens in BCD code */
+#define RTC_TIME_HRU                       BITS(16,19)                                 /*!< hour units in BCD code */
+#define RTC_TIME_HRT                       BITS(20,21)                                 /*!< hour tens in BCD code */
+#define RTC_TIME_PM                        BIT(22)                                     /*!< AM/PM notation */
 
 /* RTC_DATE */
-#define RTC_DATE_DAYU                      BITS(0,3)                                  /*!< date units in BCD code */
-#define RTC_DATE_DAYT                      BITS(4,5)                                  /*!< date tens in BCD code */
-#define RTC_DATE_MONU                      BITS(8,11)                                 /*!< month units in BCD code */
-#define RTC_DATE_MONT                      BIT(12)                                    /*!< month tens in BCD code */
-#define RTC_DATE_DOW                       BITS(13,15)                                /*!< day of week units */
-#define RTC_DATE_YRU                       BITS(16,19)                                /*!< year units in BCD code */
-#define RTC_DATE_YRT                       BITS(20,23)                                /*!< year tens in BCD code */
+#define RTC_DATE_DAYU                      BITS(0,3)                                   /*!< date units in BCD code */
+#define RTC_DATE_DAYT                      BITS(4,5)                                   /*!< date tens in BCD code */
+#define RTC_DATE_MONU                      BITS(8,11)                                  /*!< month units in BCD code */
+#define RTC_DATE_MONT                      BIT(12)                                     /*!< month tens in BCD code */
+#define RTC_DATE_DOW                       BITS(13,15)                                 /*!< day of week units */
+#define RTC_DATE_YRU                       BITS(16,19)                                 /*!< year units in BCD code */
+#define RTC_DATE_YRT                       BITS(20,23)                                 /*!< year tens in BCD code */
 
 /* RTC_CTL */
-#define RTC_CTL_TSEG                       BIT(3)                                     /*!< valid event edge of time-stamp */
-#define RTC_CTL_REFEN                      BIT(4)                                     /*!< reference clock detection function enable */
-#define RTC_CTL_BPSHAD                     BIT(5)                                     /*!< shadow registers bypass control */
-#define RTC_CTL_CS                         BIT(6)                                     /*!< display format of clock system */
-#define RTC_CTL_ALRM0EN                    BIT(8)                                     /*!< alarm function enable */
-#define RTC_CTL_TSEN                       BIT(11)                                    /*!< time-stamp function enable */
-#define RTC_CTL_ALRM0IE                    BIT(12)                                    /*!< RTC alarm interrupt enable */
-#define RTC_CTL_TSIE                       BIT(15)                                    /*!< time-stamp interrupt enable */
-#define RTC_CTL_A1H                        BIT(16)                                    /*!< add 1 hour(summer time change) */
-#define RTC_CTL_S1H                        BIT(17)                                    /*!< subtract 1 hour(winter time change) */
-#define RTC_CTL_DSM                        BIT(18)                                    /*!< daylight saving mark */
-#define RTC_CTL_COS                        BIT(19)                                    /*!< calibration output selection */
-#define RTC_CTL_OPOL                       BIT(20)                                    /*!< output polarity */
-#define RTC_CTL_OS                         BITS(21,22)                                /*!< output selection */
-#define RTC_CTL_COEN                       BIT(23)                                    /*!< calibration output enable */
+#define RTC_CTL_TSEG                       BIT(3)                                      /*!< valid event edge of time-stamp */
+#define RTC_CTL_REFEN                      BIT(4)                                      /*!< reference clock detection function enable */
+#define RTC_CTL_BPSHAD                     BIT(5)                                      /*!< shadow registers bypass control */
+#define RTC_CTL_CS                         BIT(6)                                      /*!< display format of clock system */
+#define RTC_CTL_ALRM0EN                    BIT(8)                                      /*!< alarm function enable */
+#define RTC_CTL_TSEN                       BIT(11)                                     /*!< time-stamp function enable */
+#define RTC_CTL_ALRM0IE                    BIT(12)                                     /*!< RTC alarm interrupt enable */
+#define RTC_CTL_TSIE                       BIT(15)                                     /*!< time-stamp interrupt enable */
+#define RTC_CTL_A1H                        BIT(16)                                     /*!< add 1 hour(summer time change) */
+#define RTC_CTL_S1H                        BIT(17)                                     /*!< subtract 1 hour(winter time change) */
+#define RTC_CTL_DSM                        BIT(18)                                     /*!< daylight saving mark */
+#define RTC_CTL_COS                        BIT(19)                                     /*!< calibration output selection */
+#define RTC_CTL_OPOL                       BIT(20)                                     /*!< output polarity */
+#define RTC_CTL_OS                         BITS(21,22)                                 /*!< output selection */
+#define RTC_CTL_COEN                       BIT(23)                                     /*!< calibration output enable */
 
 /* RTC_STAT */
-#define RTC_STAT_ALRM0WF                   BIT(0)                                     /*!< alarm configuration can be write flag */
-#define RTC_STAT_SOPF                      BIT(3)                                     /*!< shift function operation pending flag */
-#define RTC_STAT_YCM                       BIT(4)                                     /*!< year configuration mark status flag */
-#define RTC_STAT_RSYNF                     BIT(5)                                     /*!< register synchronization flag */
-#define RTC_STAT_INITF                     BIT(6)                                     /*!< initialization state flag */
-#define RTC_STAT_INITM                     BIT(7)                                     /*!< enter initialization mode */
-#define RTC_STAT_ALRM0F                    BIT(8)                                     /*!< alarm occurs flag */
-#define RTC_STAT_TSF                       BIT(11)                                    /*!< time-stamp flag */
-#define RTC_STAT_TSOVRF                    BIT(12)                                    /*!< time-stamp overflow flag */
-#define RTC_STAT_TP0F                      BIT(13)                                    /*!< RTC tamp 0 detected flag */
-#define RTC_STAT_TP1F                      BIT(14)                                    /*!< RTC tamp 1 detected flag */
-#define RTC_STAT_SCPF                      BIT(16)                                    /*!< recalibration pending flag */
+#define RTC_STAT_ALRM0WF                   BIT(0)                                      /*!< alarm configuration can be write flag */
+#define RTC_STAT_SOPF                      BIT(3)                                      /*!< shift function operation pending flag */
+#define RTC_STAT_YCM                       BIT(4)                                      /*!< year configuration mark status flag */
+#define RTC_STAT_RSYNF                     BIT(5)                                      /*!< register synchronization flag */
+#define RTC_STAT_INITF                     BIT(6)                                      /*!< initialization state flag */
+#define RTC_STAT_INITM                     BIT(7)                                      /*!< enter initialization mode */
+#define RTC_STAT_ALRM0F                    BIT(8)                                      /*!< alarm occurs flag */
+#define RTC_STAT_TSF                       BIT(11)                                     /*!< time-stamp flag */
+#define RTC_STAT_TSOVRF                    BIT(12)                                     /*!< time-stamp overflow flag */
+#define RTC_STAT_TP0F                      BIT(13)                                     /*!< RTC tamp 0 detected flag */
+#define RTC_STAT_TP1F                      BIT(14)                                     /*!< RTC tamp 1 detected flag */
+#define RTC_STAT_SCPF                      BIT(16)                                     /*!< recalibration pending flag */
 
 /* RTC_PSC */
-#define RTC_PSC_FACTOR_S                   BITS(0,14)                                 /*!< synchronous prescaler factor */
-#define RTC_PSC_FACTOR_A                   BITS(16,22)                                /*!< asynchronous prescaler factor */
+#define RTC_PSC_FACTOR_S                   BITS(0,14)                                  /*!< synchronous prescaler factor */
+#define RTC_PSC_FACTOR_A                   BITS(16,22)                                 /*!< asynchronous prescaler factor */
 
 /* RTC_ALRM0TD */
-#define RTC_ALRM0TD_SCU                    BITS(0,3)                                  /*!< second units in BCD code */
-#define RTC_ALRM0TD_SCT                    BITS(4,6)                                  /*!< second tens in BCD code */
-#define RTC_ALRM0TD_MSKS                   BIT(7)                                     /*!< alarm second mask bit */
-#define RTC_ALRM0TD_MNU                    BITS(8,11)                                 /*!< minutes units in BCD code */
-#define RTC_ALRM0TD_MNT                    BITS(12,14)                                /*!< minutes tens in BCD code */
-#define RTC_ALRM0TD_MSKM                   BIT(15)                                    /*!< alarm minutes mask bit */
-#define RTC_ALRM0TD_HRU                    BITS(16,19)                                /*!< hour units in BCD code */
-#define RTC_ALRM0TD_HRT                    BITS(20,21)                                /*!< hour units in BCD code */
-#define RTC_ALRM0TD_PM                     BIT(22)                                    /*!< AM/PM flag */
-#define RTC_ALRM0TD_MSKH                   BIT(23)                                    /*!< alarm hour mask bit */
-#define RTC_ALRM0TD_DAYU                   BITS(24,27)                                /*!< date units or week day in BCD code */
-#define RTC_ALRM0TD_DAYT                   BITS(28,29)                                /*!< date tens in BCD code */
-#define RTC_ALRM0TD_DOWS                   BIT(30)                                    /*!< day of week  selection */
-#define RTC_ALRM0TD_MSKD                   BIT(31)                                    /*!< alarm date mask bit */
+#define RTC_ALRM0TD_SCU                    BITS(0,3)                                   /*!< second units in BCD code */
+#define RTC_ALRM0TD_SCT                    BITS(4,6)                                   /*!< second tens in BCD code */
+#define RTC_ALRM0TD_MSKS                   BIT(7)                                      /*!< alarm second mask bit */
+#define RTC_ALRM0TD_MNU                    BITS(8,11)                                  /*!< minutes units in BCD code */
+#define RTC_ALRM0TD_MNT                    BITS(12,14)                                 /*!< minutes tens in BCD code */
+#define RTC_ALRM0TD_MSKM                   BIT(15)                                     /*!< alarm minutes mask bit */
+#define RTC_ALRM0TD_HRU                    BITS(16,19)                                 /*!< hour units in BCD code */
+#define RTC_ALRM0TD_HRT                    BITS(20,21)                                 /*!< hour units in BCD code */
+#define RTC_ALRM0TD_PM                     BIT(22)                                     /*!< AM/PM flag */
+#define RTC_ALRM0TD_MSKH                   BIT(23)                                     /*!< alarm hour mask bit */
+#define RTC_ALRM0TD_DAYU                   BITS(24,27)                                 /*!< date units or week day in BCD code */
+#define RTC_ALRM0TD_DAYT                   BITS(28,29)                                 /*!< date tens in BCD code */
+#define RTC_ALRM0TD_DOWS                   BIT(30)                                     /*!< day of week  selection */
+#define RTC_ALRM0TD_MSKD                   BIT(31)                                     /*!< alarm date mask bit */
 
 /* RTC_WPK */
-#define RTC_WPK_WPK                        BITS(0,7)                                  /*!< key for write protection */
+#define RTC_WPK_WPK                        BITS(0,7)                                   /*!< key for write protection */
 
 /* RTC_SS */
-#define RTC_SS_SSC                         BITS(0,15)                                 /*!< sub second value */
+#define RTC_SS_SSC                         BITS(0,15)                                  /*!< sub second value */
 
 /* RTC_SHIFTCTL */
-#define RTC_SHIFTCTL_SFS                   BITS(0,14)                                 /*!< subtract a fraction of a second */
-#define RTC_SHIFTCTL_A1S                   BIT(31)                                    /*!< one second add */
+#define RTC_SHIFTCTL_SFS                   BITS(0,14)                                  /*!< subtract a fraction of a second */
+#define RTC_SHIFTCTL_A1S                   BIT(31)                                     /*!< one second add */
 
 /* RTC_TTS */
-#define RTC_TTS_SCU                        BITS(0,3)                                  /*!< second units in BCD code */
-#define RTC_TTS_SCT                        BITS(4,6)                                  /*!< second units in BCD code */
-#define RTC_TTS_MNU                        BITS(8,11)                                 /*!< minute units in BCD code */
-#define RTC_TTS_MNT                        BITS(12,14)                                /*!< minute tens in BCD code */
-#define RTC_TTS_HRU                        BITS(16,19)                                /*!< hour units in BCD code */
-#define RTC_TTS_HRT                        BITS(20,21)                                /*!< hour tens in BCD code */
-#define RTC_TTS_PM                         BIT(22)                                    /*!< AM/PM notation */
+#define RTC_TTS_SCU                        BITS(0,3)                                   /*!< second units in BCD code */
+#define RTC_TTS_SCT                        BITS(4,6)                                   /*!< second units in BCD code */
+#define RTC_TTS_MNU                        BITS(8,11)                                  /*!< minute units in BCD code */
+#define RTC_TTS_MNT                        BITS(12,14)                                 /*!< minute tens in BCD code */
+#define RTC_TTS_HRU                        BITS(16,19)                                 /*!< hour units in BCD code */
+#define RTC_TTS_HRT                        BITS(20,21)                                 /*!< hour tens in BCD code */
+#define RTC_TTS_PM                         BIT(22)                                     /*!< AM/PM notation */
 
 /* RTC_DTS */
-#define RTC_DTS_DAYU                       BITS(0,3)                                  /*!< date units in BCD code */
-#define RTC_DTS_DAYT                       BITS(4,5)                                  /*!< date tens in BCD code */
-#define RTC_DTS_MONU                       BITS(8,11)                                 /*!< month units in BCD code */
-#define RTC_DTS_MONT                       BIT(12)                                    /*!< month tens in BCD code */
-#define RTC_DTS_DOW                        BITS(13,15)                                /*!< day of week units */
+#define RTC_DTS_DAYU                       BITS(0,3)                                   /*!< date units in BCD code */
+#define RTC_DTS_DAYT                       BITS(4,5)                                   /*!< date tens in BCD code */
+#define RTC_DTS_MONU                       BITS(8,11)                                  /*!< month units in BCD code */
+#define RTC_DTS_MONT                       BIT(12)                                     /*!< month tens in BCD code */
+#define RTC_DTS_DOW                        BITS(13,15)                                 /*!< day of week units */
 
 /* RTC_SSTS */
-#define RTC_SSTS_SSC                       BITS(0,15)                                 /*!< timestamp sub second units */
+#define RTC_SSTS_SSC                       BITS(0,15)                                  /*!< timestamp sub second units */
 
 /* RTC_HRFC */
-#define RTC_HRFC_CMSK                      BITS(0,8)                                  /*!< calibration mask number */
-#define RTC_HRFC_CWND16                    BIT(13)                                    /*!< calibration window select 16 seconds */
-#define RTC_HRFC_CWND8                     BIT(14)                                    /*!< calibration window select 16 seconds */
-#define RTC_HRFC_FREQI                     BIT(15)                                    /*!< increase RTC frequency by 488.5ppm */
+#define RTC_HRFC_CMSK                      BITS(0,8)                                   /*!< calibration mask number */
+#define RTC_HRFC_CWND16                    BIT(13)                                     /*!< calibration window select 16 seconds */
+#define RTC_HRFC_CWND8                     BIT(14)                                     /*!< calibration window select 16 seconds */
+#define RTC_HRFC_FREQI                     BIT(15)                                     /*!< increase RTC frequency by 488.5ppm */
 
 /* RTC_TAMP */
-#define RTC_TAMP_TP0EN                     BIT(0)                                     /*!< tamper 0 detection enable */
-#define RTC_TAMP_TP0EG                     BIT(1)                                     /*!< tamper 0 event trigger edge for RTC tamp 0 input */
-#define RTC_TAMP_TPIE                      BIT(2)                                     /*!< tamper detection interrupt enable */
-#define RTC_TAMP_TP1EN                     BIT(3)                                     /*!< tamper 1 detection enable */
-#define RTC_TAMP_TP1EG                     BIT(4)                                     /*!< tamper 1 event trigger edge for RTC tamp 1 input */
-#define RTC_TAMP_TPTS                      BIT(7)                                     /*!< make tamper function used for timestamp function */
-#define RTC_TAMP_FREQ                      BITS(8,10)                                 /*!< sample frequency of tamper event detection */
-#define RTC_TAMP_FLT                       BITS(11,12)                                /*!< RTC tamp x filter count setting */
-#define RTC_TAMP_PRCH                      BITS(13,14)                                /*!< precharge duration time of RTC tamp x */
-#define RTC_TAMP_DISPU                     BIT(15)                                    /*!< RTC tamp x pull up disable bit */
-#define RTC_TAMP_PC13VAL                   BIT(18)                                    /*!< alarm output type control/PC13 output value */
-#define RTC_TAMP_PC13MDE                   BIT(19)                                    /*!< PC13 mode */
-#define RTC_TAMP_PC14VAL                   BIT(20)                                    /*!< PC14 output value */
-#define RTC_TAMP_PC14MDE                   BIT(21)                                    /*!< PC14 mode */
-#define RTC_TAMP_PC15VAL                   BIT(22)                                    /*!< PC15 output value */
-#define RTC_TAMP_PC15MDE                   BIT(23)                                    /*!< PC15 mode */
+#define RTC_TAMP_TP0EN                     BIT(0)                                      /*!< tamper 0 detection enable */
+#define RTC_TAMP_TP0EG                     BIT(1)                                      /*!< tamper 0 event trigger edge for RTC tamp 0 input */
+#define RTC_TAMP_TPIE                      BIT(2)                                      /*!< tamper detection interrupt enable */
+#define RTC_TAMP_TP1EN                     BIT(3)                                      /*!< tamper 1 detection enable */
+#define RTC_TAMP_TP1EG                     BIT(4)                                      /*!< tamper 1 event trigger edge for RTC tamp 1 input */
+#define RTC_TAMP_TPTS                      BIT(7)                                      /*!< make tamper function used for timestamp function */
+#define RTC_TAMP_FREQ                      BITS(8,10)                                  /*!< sample frequency of tamper event detection */
+#define RTC_TAMP_FLT                       BITS(11,12)                                 /*!< RTC tamp x filter count setting */
+#define RTC_TAMP_PRCH                      BITS(13,14)                                 /*!< precharge duration time of RTC tamp x */
+#define RTC_TAMP_DISPU                     BIT(15)                                     /*!< RTC tamp x pull up disable bit */
+#define RTC_TAMP_PC13VAL                   BIT(18)                                     /*!< alarm output type control/PC13 output value */
+#define RTC_TAMP_PC13MDE                   BIT(19)                                     /*!< PC13 mode */
+#define RTC_TAMP_PC14VAL                   BIT(20)                                     /*!< PC14 output value */
+#define RTC_TAMP_PC14MDE                   BIT(21)                                     /*!< PC14 mode */
+#define RTC_TAMP_PC15VAL                   BIT(22)                                     /*!< PC15 output value */
+#define RTC_TAMP_PC15MDE                   BIT(23)                                     /*!< PC15 mode */
 
 /* RTC_ALRM0SS */
-#define RTC_ALRM0SS_SSC                    BITS(0,14)                                 /*!< alarm sub second value */
-#define RTC_ALRM0SS_MASKSSC                BITS(24,27)                                /*!< mask control bit of SS */
+#define RTC_ALRM0SS_SSC                    BITS(0,14)                                  /*!< alarm sub second value */
+#define RTC_ALRM0SS_MASKSSC                BITS(24,27)                                 /*!< mask control bit of SS */
 
 /* RTC_BKP0 */
-#define RTC_BKP0_DATA                      BITS(0,31)                                 /*!< backup domain registers */
+#define RTC_BKP0_DATA                      BITS(0,31)                                  /*!< backup domain registers */
 
 /* RTC_BKP1 */
-#define RTC_BKP1_DATA                      BITS(0,31)                                 /*!< backup domain registers */
+#define RTC_BKP1_DATA                      BITS(0,31)                                  /*!< backup domain registers */
 
 /* RTC_BKP2 */
-#define RTC_BKP2_DATA                      BITS(0,31)                                 /*!< backup domain registers */
+#define RTC_BKP2_DATA                      BITS(0,31)                                  /*!< backup domain registers */
 
 /* RTC_BKP3 */
-#define RTC_BKP3_DATA                      BITS(0,31)                                 /*!< backup domain registers */
+#define RTC_BKP3_DATA                      BITS(0,31)                                  /*!< backup domain registers */
 
 /* RTC_BKP4 */
-#define RTC_BKP4_DATA                      BITS(0,31)                                 /*!< backup domain registers */
-
+#define RTC_BKP4_DATA                      BITS(0,31)                                  /*!< backup domain registers */
 
 /* constants definitions */
 /* structure for initialization of the RTC */
 typedef struct
 {
-    uint8_t rtc_year;                                                                 /*!< RTC year value: 0x0 - 0x99(BCD format) */
-    uint8_t rtc_month;                                                                /*!< RTC month value */
-    uint8_t rtc_date;                                                                 /*!< RTC date value: 0x1 - 0x31(BCD format) */
-    uint8_t rtc_day_of_week;                                                          /*!< RTC weekday value */
-    uint8_t rtc_hour;                                                                 /*!< RTC hour value */
-    uint8_t rtc_minute;                                                               /*!< RTC minute value: 0x0 - 0x59(BCD format) */
-    uint8_t rtc_second;                                                               /*!< RTC second value: 0x0 - 0x59(BCD format) */
-    uint16_t rtc_factor_asyn;                                                         /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */
-    uint16_t rtc_factor_syn;                                                          /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */
-    uint32_t rtc_am_pm;                                                               /*!< RTC AM/PM value */
-    uint32_t rtc_display_format;                                                      /*!< RTC time notation */
+    uint8_t rtc_year;                                                                  /*!< RTC year value: 0x0 - 0x99(BCD format) */
+    uint8_t rtc_month;                                                                 /*!< RTC month value */
+    uint8_t rtc_date;                                                                  /*!< RTC date value: 0x1 - 0x31(BCD format) */
+    uint8_t rtc_day_of_week;                                                           /*!< RTC weekday value */
+    uint8_t rtc_hour;                                                                  /*!< RTC hour value */
+    uint8_t rtc_minute;                                                                /*!< RTC minute value: 0x0 - 0x59(BCD format) */
+    uint8_t rtc_second;                                                                /*!< RTC second value: 0x0 - 0x59(BCD format) */
+    uint16_t rtc_factor_asyn;                                                          /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */
+    uint16_t rtc_factor_syn;                                                           /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */
+    uint32_t rtc_am_pm;                                                                /*!< RTC AM/PM value */
+    uint32_t rtc_display_format;                                                       /*!< RTC time notation */
 }rtc_parameter_struct;
 
 /* structure for RTC alarm configuration */
 typedef struct
 {
-    uint32_t rtc_alarm_mask;                                                          /*!< RTC alarm mask */
-    uint32_t rtc_weekday_or_date;                                                     /*!< specify RTC alarm is on date or weekday */
-    uint8_t rtc_alarm_day;                                                            /*!< RTC alarm date or weekday value*/
-    uint8_t rtc_alarm_hour;                                                           /*!< RTC alarm hour value */
-    uint8_t rtc_alarm_minute;                                                         /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */
-    uint8_t rtc_alarm_second;                                                         /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */
-    uint32_t rtc_am_pm;                                                               /*!< RTC alarm AM/PM value */
+    uint32_t rtc_alarm_mask;                                                           /*!< RTC alarm mask */
+    uint32_t rtc_weekday_or_date;                                                      /*!< specify RTC alarm is on date or weekday */
+    uint8_t rtc_alarm_day;                                                             /*!< RTC alarm date or weekday value*/
+    uint8_t rtc_alarm_hour;                                                            /*!< RTC alarm hour value */
+    uint8_t rtc_alarm_minute;                                                          /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */
+    uint8_t rtc_alarm_second;                                                          /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */
+    uint32_t rtc_am_pm;                                                                /*!< RTC alarm AM/PM value */
 }rtc_alarm_struct;
 
 /* structure for RTC time-stamp configuration */
 typedef struct
 {
-    uint8_t rtc_timestamp_month;                                                      /*!< RTC time-stamp month value */
-    uint8_t rtc_timestamp_date;                                                       /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */
-    uint8_t rtc_timestamp_day;                                                        /*!< RTC time-stamp weekday value */
-    uint8_t rtc_timestamp_hour;                                                       /*!< RTC time-stamp hour value */
-    uint8_t rtc_timestamp_minute;                                                     /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */
-    uint8_t rtc_timestamp_second;                                                     /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */
-    uint32_t rtc_am_pm;                                                               /*!< RTC time-stamp AM/PM value */
+    uint8_t rtc_timestamp_month;                                                       /*!< RTC time-stamp month value */
+    uint8_t rtc_timestamp_date;                                                        /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */
+    uint8_t rtc_timestamp_day;                                                         /*!< RTC time-stamp weekday value */
+    uint8_t rtc_timestamp_hour;                                                        /*!< RTC time-stamp hour value */
+    uint8_t rtc_timestamp_minute;                                                      /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */
+    uint8_t rtc_timestamp_second;                                                      /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */
+    uint32_t rtc_am_pm;                                                                /*!< RTC time-stamp AM/PM value */
 }rtc_timestamp_struct;
 
 /* structure for RTC tamper configuration */
 typedef struct
 {
-    uint32_t rtc_tamper_source;                                                       /*!< RTC tamper source */
-    uint32_t rtc_tamper_trigger;                                                      /*!< RTC tamper trigger */
-    uint32_t rtc_tamper_filter;                                                       /*!< RTC tamper consecutive samples needed during a voltage level detection */
-    uint32_t rtc_tamper_sample_frequency;                                             /*!< RTC tamper sampling frequency during a voltage level detection */
-    ControlStatus rtc_tamper_precharge_enable;                                        /*!< RTC tamper precharge feature during a voltage level detection */
-    uint32_t rtc_tamper_precharge_time;                                               /*!< RTC tamper precharge duration if precharge feature is enabled */
-    ControlStatus rtc_tamper_with_timestamp;                                          /*!< RTC tamper time-stamp feature */
+    uint32_t rtc_tamper_source;                                                        /*!< RTC tamper source */
+    uint32_t rtc_tamper_trigger;                                                       /*!< RTC tamper trigger */
+    uint32_t rtc_tamper_filter;                                                        /*!< RTC tamper consecutive samples needed during a voltage level detection */
+    uint32_t rtc_tamper_sample_frequency;                                              /*!< RTC tamper sampling frequency during a voltage level detection */
+    ControlStatus rtc_tamper_precharge_enable;                                         /*!< RTC tamper precharge feature during a voltage level detection */
+    uint32_t rtc_tamper_precharge_time;                                                /*!< RTC tamper precharge duration if precharge feature is enabled */
+    ControlStatus rtc_tamper_with_timestamp;                                           /*!< RTC tamper time-stamp feature */
 }rtc_tamper_struct; 
 
 /* time register value */
-#define TIME_SC(regval)                    (BITS(0,6) & ((uint32_t)(regval) << 0U))   /*!< write value to RTC_TIME_SC bit field */
-#define GET_TIME_SC(regval)                GET_BITS((regval),0,6)                     /*!< get value of RTC_TIME_SC bit field */
+#define TIME_SC(regval)                    (BITS(0,6) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_TIME_SC bit field */
+#define GET_TIME_SC(regval)                GET_BITS((regval),0,6)                      /*!< get value of RTC_TIME_SC bit field */
 
-#define TIME_MN(regval)                    (BITS(8,14) & ((uint32_t)(regval) << 8U))  /*!< write value to RTC_TIME_MN bit field */
-#define GET_TIME_MN(regval)                GET_BITS((regval),8,14)                    /*!< get value of RTC_TIME_MN bit field */
+#define TIME_MN(regval)                    (BITS(8,14) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_TIME_MN bit field */
+#define GET_TIME_MN(regval)                GET_BITS((regval),8,14)                     /*!< get value of RTC_TIME_MN bit field */
 
-#define TIME_HR(regval)                    (BITS(16,21) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_TIME_HR bit field */
-#define GET_TIME_HR(regval)                GET_BITS((regval),16,21)                   /*!< get value of RTC_TIME_HR bit field */
+#define TIME_HR(regval)                    (BITS(16,21) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_TIME_HR bit field */
+#define GET_TIME_HR(regval)                GET_BITS((regval),16,21)                    /*!< get value of RTC_TIME_HR bit field */
 
-#define RTC_AM                             ((uint32_t)0x00000000U)                    /*!< AM format */
-#define RTC_PM                             RTC_TIME_PM                                /*!< PM format */
+#define RTC_AM                             ((uint32_t)0x00000000U)                      /*!< AM format */
+#define RTC_PM                             RTC_TIME_PM                                 /*!< PM format */
 
 /* date register value */
-#define DATE_DAY(regval)                   (BITS(0,5) & ((uint32_t)(regval) << 0U))   /*!< write value to RTC_DATE_DAY bit field */
-#define GET_DATE_DAY(regval)               GET_BITS((regval),0,5)                     /*!< get value of RTC_DATE_DAY bit field */
-
-#define DATE_MON(regval)                   (BITS(8,12) & ((uint32_t)(regval) << 8U))  /*!< write value to RTC_DATE_MON bit field */
-#define GET_DATE_MON(regval)               GET_BITS((regval),8,12)                    /*!< get value of RTC_DATE_MON bit field */
-#define RTC_JAN                            ((uint8_t)0x01U)                           /*!< Janurary */
-#define RTC_FEB                            ((uint8_t)0x02U)                           /*!< February */
-#define RTC_MAR                            ((uint8_t)0x03U)                           /*!< March */
-#define RTC_APR                            ((uint8_t)0x04U)                           /*!< April */
-#define RTC_MAY                            ((uint8_t)0x05U)                           /*!< May */
-#define RTC_JUN                            ((uint8_t)0x06U)                           /*!< June */
-#define RTC_JUL                            ((uint8_t)0x07U)                           /*!< July */
-#define RTC_AUG                            ((uint8_t)0x08U)                           /*!< August */
-#define RTC_SEP                            ((uint8_t)0x09U)                           /*!< September */
-#define RTC_OCT                            ((uint8_t)0x10U)                           /*!< October */
-#define RTC_NOV                            ((uint8_t)0x11U)                           /*!< November */
-#define RTC_DEC                            ((uint8_t)0x12U)                           /*!< December */
-                                                                                
-#define DATE_DOW(regval)                   (BITS(13,15) & ((uint32_t)(regval) << 13U))/*!< write value to RTC_DATE_DOW bit field */
-#define GET_DATE_DOW(regval)               GET_BITS((regval),13,15)                   /*!< get value of RTC_DATE_DOW bit field */
-#define RTC_MONDAY                         ((uint8_t)0x01)                            /*!< Monday */
-#define RTC_TUESDAY                        ((uint8_t)0x02)                            /*!< Tuesday */
-#define RTC_WEDSDAY                        ((uint8_t)0x03)                            /*!< Wednesday */
-#define RTC_THURSDAY                       ((uint8_t)0x04)                            /*!< Thursday */
-#define RTC_FRIDAY                         ((uint8_t)0x05)                            /*!< Friday */
-#define RTC_SATURDAY                       ((uint8_t)0x06)                            /*!< Saturday */
-#define RTC_SUNDAY                         ((uint8_t)0x07)                            /*!< Sunday */
-
-#define DATE_YR(regval)                    (BITS(16,23) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_DATE_YR bit field */
-#define GET_DATE_YR(regval)                GET_BITS((regval),16,23)                   /*!< get value of RTC_DATE_YR bit field */
+#define DATE_DAY(regval)                   (BITS(0,5) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_DATE_DAY bit field */
+#define GET_DATE_DAY(regval)               GET_BITS((regval),0,5)                      /*!< get value of RTC_DATE_DAY bit field */
+
+#define DATE_MON(regval)                   (BITS(8,12) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_DATE_MON bit field */
+#define GET_DATE_MON(regval)               GET_BITS((regval),8,12)                     /*!< get value of RTC_DATE_MON bit field */
+#define RTC_JAN                            ((uint8_t)0x01U)                            /*!< Janurary */
+#define RTC_FEB                            ((uint8_t)0x02U)                            /*!< February */
+#define RTC_MAR                            ((uint8_t)0x03U)                            /*!< March */
+#define RTC_APR                            ((uint8_t)0x04U)                            /*!< April */
+#define RTC_MAY                            ((uint8_t)0x05U)                            /*!< May */
+#define RTC_JUN                            ((uint8_t)0x06U)                            /*!< June */
+#define RTC_JUL                            ((uint8_t)0x07U)                            /*!< July */
+#define RTC_AUG                            ((uint8_t)0x08U)                            /*!< August */
+#define RTC_SEP                            ((uint8_t)0x09U)                            /*!< September */
+#define RTC_OCT                            ((uint8_t)0x10U)                            /*!< October */
+#define RTC_NOV                            ((uint8_t)0x11U)                            /*!< November */
+#define RTC_DEC                            ((uint8_t)0x12U)                            /*!< December */
+
+#define DATE_DOW(regval)                   (BITS(13,15) & ((uint32_t)(regval) << 13U))  /*!< write value to RTC_DATE_DOW bit field */
+#define GET_DATE_DOW(regval)               GET_BITS((regval),13,15)                    /*!< get value of RTC_DATE_DOW bit field */
+#define RTC_MONDAY                         ((uint8_t)0x01U)                            /*!< Monday */
+#define RTC_TUESDAY                        ((uint8_t)0x02U)                            /*!< Tuesday */
+#define RTC_WEDSDAY                        ((uint8_t)0x03U)                            /*!< Wednesday */
+#define RTC_THURSDAY                       ((uint8_t)0x04U)                            /*!< Thursday */
+#define RTC_FRIDAY                         ((uint8_t)0x05U)                            /*!< Friday */
+#define RTC_SATURDAY                       ((uint8_t)0x06U)                            /*!< Saturday */
+#define RTC_SUNDAY                         ((uint8_t)0x07U)                            /*!< Sunday */
+
+#define DATE_YR(regval)                    (BITS(16,23) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_DATE_YR bit field */
+#define GET_DATE_YR(regval)                GET_BITS((regval),16,23)                    /*!< get value of RTC_DATE_YR bit field */
 
 /* ctl register value */
-#define CTL_OS(regval)                     (BITS(21,22) & ((uint32_t)(regval) << 21U))/*!< write value to RTC_CTL_OS bit field */
-#define RTC_OS_DISABLE                     CTL_OS(0)                                  /*!< disable output RTC_ALARM */
-#define RTC_OS_ENABLE                      CTL_OS(1)                                  /*!< enable alarm flag output */
-
-#define RTC_CALIBRATION_512HZ              RTC_CTL_COEN                               /*!< calibration output of 512Hz is enable */
-#define RTC_CALIBRATION_1HZ                RTC_CTL_COEN | RTC_CTL_COS                 /*!< calibration output of 1Hz is enable */
-#define RTC_ALARM_HIGH                     RTC_CTL_OS_ENABLE                          /*!< enable alarm flag output with high level */
-#define RTC_ALARM_LOW                      RTC_CTL_OS_ENABLE | RTC_CTL_OPOL           /*!< enable alarm flag output with low level*/
+#define CTL_OS(regval)                     (BITS(21,22) & ((uint32_t)(regval) << 21U))   /*!< write value to RTC_CTL_OS bit field */
+#define RTC_OS_DISABLE                     CTL_OS(0)                                   /*!< disable output RTC_ALARM */
+#define RTC_OS_ENABLE                      CTL_OS(1)                                   /*!< enable alarm flag output */
 
-#define RTC_24HOUR                         ((uint32_t)0x00000000U)                    /*!< 24-hour format */
-#define RTC_12HOUR                         RTC_CTL_CS                                 /*!< 12-hour format */
+#define RTC_CALIBRATION_512HZ              RTC_CTL_COEN                                /*!< calibration output of 512Hz is enable */
+#define RTC_CALIBRATION_1HZ                RTC_CTL_COEN | RTC_CTL_COS                  /*!< calibration output of 1Hz is enable */
+#define RTC_ALARM_HIGH                     RTC_CTL_OS_ENABLE                           /*!< enable alarm flag output with high level */
+#define RTC_ALARM_LOW                      RTC_CTL_OS_ENABLE | RTC_CTL_OPOL            /*!< enable alarm flag output with low level*/
 
-#define RTC_TIMESTAMP_RISING_EDGE          ((uint32_t)0x00000000U)                    /*!< rising edge is valid event edge for time-stamp event */
-#define RTC_TIMESTAMP_FALLING_EDGE         RTC_CTL_TSEG                               /*!< falling edge is valid event edge for time-stamp event */
+#define RTC_24HOUR                         ((uint32_t)0x00000000U)                     /*!< 24-hour format */
+#define RTC_12HOUR                         RTC_CTL_CS                                  /*!< 12-hour format */
 
+#define RTC_TIMESTAMP_RISING_EDGE          ((uint32_t)0x00000000U)                     /*!< rising edge is valid event edge for time-stamp event */
+#define RTC_TIMESTAMP_FALLING_EDGE         RTC_CTL_TSEG                                /*!< falling edge is valid event edge for time-stamp event */
+ 
 /* psc register value */
-#define PSC_FACTOR_S(regval)               (BITS(0,14) & ((uint32_t)(regval) << 0U))  /*!< write value to RTC_PSC_FACTOR_S bit field */
-#define GET_PSC_FACTOR_S(regval)           GET_BITS((regval),0,14)                    /*!< get value of RTC_PSC_FACTOR_S bit field */
+#define PSC_FACTOR_S(regval)               (BITS(0,14) & ((uint32_t)(regval) << 0U))    /*!< write value to RTC_PSC_FACTOR_S bit field */
+#define GET_PSC_FACTOR_S(regval)           GET_BITS((regval),0,14)                     /*!< get value of RTC_PSC_FACTOR_S bit field */
 
-#define PSC_FACTOR_A(regval)               (BITS(16,22) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_PSC_FACTOR_A bit field */
-#define GET_PSC_FACTOR_A(regval)           GET_BITS((regval),16,22)                   /*!< get value of RTC_PSC_FACTOR_A bit field */
+#define PSC_FACTOR_A(regval)               (BITS(16,22) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_PSC_FACTOR_A bit field */
+#define GET_PSC_FACTOR_A(regval)           GET_BITS((regval),16,22)                    /*!< get value of RTC_PSC_FACTOR_A bit field */
 
 /* alrm0td register value */
-#define ALRM0TD_SC(regval)                 (BITS(0,6) & ((uint32_t)(regval)<< 0U))    /*!< write value to RTC_ALRM0TD_SC bit field */
-#define GET_ALRM0TD_SC(regval)             GET_BITS((regval),0,6)                     /*!< get value of RTC_ALRM0TD_SC bit field */
+#define ALRM0TD_SC(regval)                 (BITS(0,6) & ((uint32_t)(regval)<< 0U))      /*!< write value to RTC_ALRM0TD_SC bit field */
+#define GET_ALRM0TD_SC(regval)             GET_BITS((regval),0,6)                      /*!< get value of RTC_ALRM0TD_SC bit field */
 
-#define ALRM0TD_MN(regval)                 (BITS(8,14) & ((uint32_t)(regval) << 8U))  /*!< write value to RTC_ALRM0TD_MN bit field */
-#define GET_ALRM0TD_MN(regval)             GET_BITS((regval),8,14)                    /*!< get value of RTC_ALRM0TD_MN bit field */
+#define ALRM0TD_MN(regval)                 (BITS(8,14) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_ALRM0TD_MN bit field */
+#define GET_ALRM0TD_MN(regval)             GET_BITS((regval),8,14)                     /*!< get value of RTC_ALRM0TD_MN bit field */
 
-#define ALRM0TD_HR(regval)                 (BITS(16,21) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_ALRM0TD_HR bit field */
-#define GET_ALRM0TD_HR(regval)             GET_BITS((regval),16,21)                   /*!< get value of RTC_ALRM0TD_HR bit field */
+#define ALRM0TD_HR(regval)                 (BITS(16,21) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_ALRM0TD_HR bit field */
+#define GET_ALRM0TD_HR(regval)             GET_BITS((regval),16,21)                    /*!< get value of RTC_ALRM0TD_HR bit field */
 
-#define ALRM0TD_DAY(regval)                (BITS(24,29) & ((uint32_t)(regval) << 24U))/*!< write value to RTC_ALRM0TD_DAY bit field */
-#define GET_ALRM0TD_DAY(regval)            GET_BITS((regval),24,29)                   /*!< get value of RTC_ALRM0TD_DAY bit field */
+#define ALRM0TD_DAY(regval)                (BITS(24,29) & ((uint32_t)(regval) << 24U))  /*!< write value to RTC_ALRM0TD_DAY bit field */
+#define GET_ALRM0TD_DAY(regval)            GET_BITS((regval),24,29)                    /*!< get value of RTC_ALRM0TD_DAY bit field */
 
-#define RTC_ALARM_NONE_MASK                ((uint32_t)0x00000000U)                    /*!< alarm none mask */
-#define RTC_ALARM_DATE_MASK                RTC_ALRM0TD_MSKD                           /*!< alarm date mask */
-#define RTC_ALARM_HOUR_MASK                RTC_ALRM0TD_MSKH                           /*!< alarm hour mask */
-#define RTC_ALARM_MINUTE_MASK              RTC_ALRM0TD_MSKM                           /*!< alarm minute mask */
-#define RTC_ALARM_SECOND_MASK              RTC_ALRM0TD_MSKS                           /*!< alarm second mask */
+#define RTC_ALARM_NONE_MASK                ((uint32_t)0x00000000U)                     /*!< alarm none mask */
+#define RTC_ALARM_DATE_MASK                RTC_ALRM0TD_MSKD                            /*!< alarm date mask */
+#define RTC_ALARM_HOUR_MASK                RTC_ALRM0TD_MSKH                            /*!< alarm hour mask */
+#define RTC_ALARM_MINUTE_MASK              RTC_ALRM0TD_MSKM                            /*!< alarm minute mask */
+#define RTC_ALARM_SECOND_MASK              RTC_ALRM0TD_MSKS                            /*!< alarm second mask */
 #define RTC_ALARM_ALL_MASK                 (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS)    /*!< alarm all mask */
 
-#define RTC_ALARM_DATE_SELECTED            ((uint32_t)0x00000000U)                    /*!< alarm date format selected */
-#define RTC_ALARM_WEEKDAY_SELECTED         RTC_ALRM0TD_DOWS                           /*!< alarm weekday format selected */
+#define RTC_ALARM_DATE_SELECTED            ((uint32_t)0x00000000U)                     /*!< alarm date format selected */
+#define RTC_ALARM_WEEKDAY_SELECTED         RTC_ALRM0TD_DOWS                            /*!< alarm weekday format selected */
 
 /* wpk register value */
-#define WPK_WPK(regval)                    (BITS(0,7) & ((uint32_t)(regval) << 0U))   /*!< write value to RTC_WPK_WPK bit field */
+#define WPK_WPK(regval)                    (BITS(0,7) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_WPK_WPK bit field */
 
 /* ss register value */
-#define SS_SSC(regval)                     (BITS(0,15) & ((uint32_t)(regval) << 0U))  /*!< write value to RTC_SS_SSC bit field */
+#define SS_SSC(regval)                     (BITS(0,15) & ((uint32_t)(regval) << 0U))    /*!< write value to RTC_SS_SSC bit field */
 
 /* shiftctl register value */
-#define SHIFTCTL_SFS(regval)               (BITS(0,14) & ((uint32_t)(regval) << 0U))  /*!< write value to RTC_SHIFTCTL_SFS bit field */
+#define SHIFTCTL_SFS(regval)               (BITS(0,14) & ((uint32_t)(regval) << 0U))    /*!< write value to RTC_SHIFTCTL_SFS bit field */
 
-#define RTC_SHIFT_ADD1S_RESET              ((uint32_t)0x00000000U)                    /*!< not add 1 second */
-#define RTC_SHIFT_ADD1S_SET                RTC_SHIFTCTL_A1S                           /*!< add one second to the clock */
+#define RTC_SHIFT_ADD1S_RESET              ((uint32_t)0x00000000U)                     /*!< not add 1 second */
+#define RTC_SHIFT_ADD1S_SET                RTC_SHIFTCTL_A1S                            /*!< add one second to the clock */
 
 /* tts register value */
-#define TTS_SC(regval)                     (BITS(0,6) & ((uint32_t)(regval) << 0U))   /*!< write value to RTC_TTS_SC bit field */
-#define GET_TTS_SC(regval)                 GET_BITS((regval),0,6)                     /*!< get value of RTC_TTS_SC bit field */
+#define TTS_SC(regval)                     (BITS(0,6) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_TTS_SC bit field */
+#define GET_TTS_SC(regval)                 GET_BITS((regval),0,6)                      /*!< get value of RTC_TTS_SC bit field */
 
-#define TTS_MN(regval)                     (BITS(8,14) & ((uint32_t)(regval) << 8U))  /*!< write value to RTC_TTS_MN bit field */
-#define GET_TTS_MN(regval)                 GET_BITS((regval),8,14)                    /*!< get value of RTC_TTS_MN bit field */
+#define TTS_MN(regval)                     (BITS(8,14) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_TTS_MN bit field */
+#define GET_TTS_MN(regval)                 GET_BITS((regval),8,14)                     /*!< get value of RTC_TTS_MN bit field */
 
-#define TTS_HR(regval)                     (BITS(16,21) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_TTS_HR bit field */
-#define GET_TTS_HR(regval)                 GET_BITS((regval),16,21)                   /*!< get value of RTC_TTS_HR bit field */
+#define TTS_HR(regval)                     (BITS(16,21) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_TTS_HR bit field */
+#define GET_TTS_HR(regval)                 GET_BITS((regval),16,21)                    /*!< get value of RTC_TTS_HR bit field */
 
 /* dts register value */
-#define DTS_DAY(regval)                    (BITS(0,5) & ((uint32_t)(regval) << 0U))   /*!< write value to RTC_DTS_DAY bit field */
-#define GET_DTS_DAY(regval)                GET_BITS((regval),0,5)                     /*!< get value of RTC_DTS_DAY bit field */
+#define DTS_DAY(regval)                    (BITS(0,5) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_DTS_DAY bit field */
+#define GET_DTS_DAY(regval)                GET_BITS((regval),0,5)                      /*!< get value of RTC_DTS_DAY bit field */
 
-#define DTS_MON(regval)                    (BITS(8,12) & ((uint32_t)(regval) << 8U))  /*!< write value to RTC_DTS_MON bit field */
-#define GET_DTS_MON(regval)                GET_BITS((regval),8,12)                    /*!< get value of RTC_DTS_MON bit field */
+#define DTS_MON(regval)                    (BITS(8,12) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_DTS_MON bit field */
+#define GET_DTS_MON(regval)                GET_BITS((regval),8,12)                     /*!< get value of RTC_DTS_MON bit field */
 
-#define DTS_DOW(regval)                    (BITS(13,15) & ((uint32_t)(regval) << 13U))/*!< write value to RTC_DTS_DOW bit field */
-#define GET_DTS_DOW(regval)                GET_BITS((regval),13,15)                   /*!< get value of RTC_DTS_DOW bit field */
+#define DTS_DOW(regval)                    (BITS(13,15) & ((uint32_t)(regval) << 13U))  /*!< write value to RTC_DTS_DOW bit field */
+#define GET_DTS_DOW(regval)                GET_BITS((regval),13,15)                    /*!< get value of RTC_DTS_DOW bit field */
 
 /* ssts register value */
-#define SSTS_SSC(regval)                   (BITS(0,15) & ((uint32_t)(regval) << 0U))  /*!< write value to RTC_SSTS_SSC bit field */
+#define SSTS_SSC(regval)                   (BITS(0,15) & ((uint32_t)(regval) << 0U))    /*!< write value to RTC_SSTS_SSC bit field */
 
 /* hrfc register value */
-#define HRFC_CMSK(regval)                  (BITS(0,8) & ((uint32_t)(regval) << 0U))   /*!< write value to RTC_HRFC_CMSK bit field */
+#define HRFC_CMSK(regval)                  (BITS(0,8) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_HRFC_CMSK bit field */
 
-#define RTC_CALIBRATION_WINDOW_32S         ((uint32_t)0x00000000U)                    /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */
-#define RTC_CALIBRATION_WINDOW_16S         RTC_HRFC_CWND16                            /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */
-#define RTC_CALIBRATION_WINDOW_8S          RTC_HRFC_CWND8                             /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */
+#define RTC_CALIBRATION_WINDOW_32S         ((uint32_t)0x00000000U)                     /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */
+#define RTC_CALIBRATION_WINDOW_16S         RTC_HRFC_CWND16                             /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */
+#define RTC_CALIBRATION_WINDOW_8S          RTC_HRFC_CWND8                              /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */
 
-#define RTC_CALIBRATION_PLUS_SET           RTC_HRFC_FREQI                             /*!< increase RTC frequency by 488.5ppm */
-#define RTC_CALIBRATION_PLUS_RESET         ((uint32_t)0x00000000U)                    /*!< no effect */
+#define RTC_CALIBRATION_PLUS_SET           RTC_HRFC_FREQI                              /*!< increase RTC frequency by 488.5ppm */
+#define RTC_CALIBRATION_PLUS_RESET         ((uint32_t)0x00000000U)                     /*!< no effect */
 
 /* tamp register value */
-#define TAMP_FREQ(regval)                  (BITS(8,10) & ((uint32_t)(regval) << 8U))  /*!< write value to RTC_TAMP_FREQ bit field */
-#define RTC_FREQ_DIV32768                  TAMP_FREQ(0)                               /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */
-#define RTC_FREQ_DIV16384                  TAMP_FREQ(1)                               /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */
-#define RTC_FREQ_DIV8192                   TAMP_FREQ(2)                               /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */
-#define RTC_FREQ_DIV4096                   TAMP_FREQ(3)                               /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */
-#define RTC_FREQ_DIV2048                   TAMP_FREQ(4)                               /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */
-#define RTC_FREQ_DIV1024                   TAMP_FREQ(5)                               /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */
-#define RTC_FREQ_DIV512                    TAMP_FREQ(6)                               /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */
-#define RTC_FREQ_DIV256                    TAMP_FREQ(7)                               /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */
-
-#define TAMP_FLT(regval)                   (BITS(11,12) & ((uint32_t)(regval) << 11U))/*!< write value to RTC_TAMP_FLT bit field */
-#define RTC_FLT_EDGE                       TAMP_FLT(0)                                /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */
-#define RTC_FLT_2S                         TAMP_FLT(1)                                /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event  */
-#define RTC_FLT_4S                         TAMP_FLT(2)                                /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */
-#define RTC_FLT_8S                         TAMP_FLT(3)                                /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event  */
-
-#define TAMP_PRCH(regval)                  (BITS(13,14 ) & ((uint32_t)(regval) << 13U))/*!< write value to RTC_TAMP_PRCH bit field */
-#define RTC_PRCH_1C                        TAMP_PRCH(0)                               /*!< 1 RTC clock prechagre time before each sampling */
-#define RTC_PRCH_2C                        TAMP_PRCH(1)                               /*!< 2 RTC clock prechagre time before each sampling  */
-#define RTC_PRCH_4C                        TAMP_PRCH(2)                               /*!< 4 RTC clock prechagre time before each sampling */
-#define RTC_PRCH_8C                        TAMP_PRCH(3)                               /*!< 8 RTC clock prechagre time before each sampling */
-
-#define RTC_TAMPER0                        RTC_TAMP_TP0EN                             /*!< tamper 0 detection enable */
-#define RTC_TAMPER1                        RTC_TAMP_TP1EN                             /*!< tamper 1 detection enable */
-
-#define RTC_TAMPER_TRIGGER_EDGE_RISING     ((uint32_t)0x00000000U)                    /*!< tamper detection is in rising edge mode */
-#define RTC_TAMPER_TRIGGER_EDGE_FALLING    RTC_TAMP_TP0EG                             /*!< tamper detection is in falling edge mode */
-#define RTC_TAMPER_TRIGGER_LEVEL_LOW       ((uint32_t)0x00000000U)                    /*!< tamper detection is in low level mode */
-#define RTC_TAMPER_TRIGGER_LEVEL_HIGH      RTC_TAMP_TP0EG                             /*!< tamper detection is in high level mode */
-
-#define RTC_TAMPER_TRIGGER_POS             ((uint32_t)0x00000001U)                    /* shift position of trigger relative to source */
-
-#define RTC_ALARM_OUTPUT_OD                ((uint32_t)0x00000000U)                    /*!< RTC alarm output open-drain mode */
-#define RTC_ALARM_OUTPUT_PP                RTC_TAMP_PC13VAL                           /*!< RTC alarm output push-pull mode */
+#define TAMP_FREQ(regval)                  (BITS(8,10) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_TAMP_FREQ bit field */
+#define RTC_FREQ_DIV32768                  TAMP_FREQ(0)                                /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV16384                  TAMP_FREQ(1)                                /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV8192                   TAMP_FREQ(2)                                /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV4096                   TAMP_FREQ(3)                                /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV2048                   TAMP_FREQ(4)                                /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV1024                   TAMP_FREQ(5)                                /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV512                    TAMP_FREQ(6)                                /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV256                    TAMP_FREQ(7)                                /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */
+
+#define TAMP_FLT(regval)                   (BITS(11,12) & ((uint32_t)(regval) << 11U))  /*!< write value to RTC_TAMP_FLT bit field */
+#define RTC_FLT_EDGE                       TAMP_FLT(0)                                 /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */
+#define RTC_FLT_2S                         TAMP_FLT(1)                                 /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event  */
+#define RTC_FLT_4S                         TAMP_FLT(2)                                 /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */
+#define RTC_FLT_8S                         TAMP_FLT(3)                                 /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event  */
+
+#define TAMP_PRCH(regval)                  (BITS(13,14) & ((uint32_t)(regval) << 13U))  /*!< write value to RTC_TAMP_PRCH bit field */
+#define RTC_PRCH_1C                        TAMP_PRCH(0)                                /*!< 1 RTC clock prechagre time before each sampling */
+#define RTC_PRCH_2C                        TAMP_PRCH(1)                                /*!< 2 RTC clock prechagre time before each sampling  */
+#define RTC_PRCH_4C                        TAMP_PRCH(2)                                /*!< 4 RTC clock prechagre time before each sampling */
+#define RTC_PRCH_8C                        TAMP_PRCH(3)                                /*!< 8 RTC clock prechagre time before each sampling */
+
+#define RTC_TAMPER0                        RTC_TAMP_TP0EN                              /*!< tamper 0 detection enable */
+#define RTC_TAMPER1                        RTC_TAMP_TP1EN                              /*!< tamper 1 detection enable */
+
+#define RTC_TAMPER_TRIGGER_EDGE_RISING     ((uint32_t)0x00000000U)                     /*!< tamper detection is in rising edge mode */
+#define RTC_TAMPER_TRIGGER_EDGE_FALLING    RTC_TAMP_TP0EG                              /*!< tamper detection is in falling edge mode */
+#define RTC_TAMPER_TRIGGER_LEVEL_LOW       ((uint32_t)0x00000000U)                     /*!< tamper detection is in low level mode */
+#define RTC_TAMPER_TRIGGER_LEVEL_HIGH      RTC_TAMP_TP0EG                              /*!< tamper detection is in high level mode */
+
+#define RTC_TAMPER_TRIGGER_POS             ((uint32_t)0x00000001U)                     /* shift position of trigger relative to source */
+
+#define RTC_ALARM_OUTPUT_OD                ((uint32_t)0x00000000U)                     /*!< RTC alarm output open-drain mode */
+#define RTC_ALARM_OUTPUT_PP                RTC_TAMP_PC13VAL                            /*!< RTC alarm output push-pull mode */
 
 /* alrm0ss register value */
-#define ALRM0SS_SSC(regval)                (BITS(0,14) & ((uint32_t)(regval)<< 0U))   /*!< write value to RTC_ALRM0SS_SSC bit field */
-
-#define ALRM0SS_MASKSSC(regval)            (BITS(24,27) & ((uint32_t)(regval) << 24U))/*!< write value to RTC_ALRM0SS_MASKSSC bit field */
-#define RTC_MASKSSC_0_14                   ALRM0SS_MASKSSC(0)                         /*!< mask alarm subsecond configuration */
-#define RTC_MASKSSC_1_14                   ALRM0SS_MASKSSC(1)                         /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */
-#define RTC_MASKSSC_2_14                   ALRM0SS_MASKSSC(2)                         /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */
-#define RTC_MASKSSC_3_14                   ALRM0SS_MASKSSC(3)                         /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */
-#define RTC_MASKSSC_4_14                   ALRM0SS_MASKSSC(4)                         /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */
-#define RTC_MASKSSC_5_14                   ALRM0SS_MASKSSC(5)                         /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */
-#define RTC_MASKSSC_6_14                   ALRM0SS_MASKSSC(6)                         /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */
-#define RTC_MASKSSC_7_14                   ALRM0SS_MASKSSC(7)                         /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */
-#define RTC_MASKSSC_8_14                   ALRM0SS_MASKSSC(8)                         /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */
-#define RTC_MASKSSC_9_14                   ALRM0SS_MASKSSC(9)                         /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */
-#define RTC_MASKSSC_10_14                  ALRM0SS_MASKSSC(10)                        /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */
-#define RTC_MASKSSC_11_14                  ALRM0SS_MASKSSC(11)                        /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */
-#define RTC_MASKSSC_12_14                  ALRM0SS_MASKSSC(12)                        /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */
-#define RTC_MASKSSC_13_14                  ALRM0SS_MASKSSC(13)                        /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */
-#define RTC_MASKSSC_14                     ALRM0SS_MASKSSC(14)                        /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */
-#define RTC_MASKSSC_NONE                   ALRM0SS_MASKSSC(15)                        /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */
+#define ALRM0SS_SSC(regval)                (BITS(0,14) & ((uint32_t)(regval)<< 0U))     /*!< write value to RTC_ALRM0SS_SSC bit field */
+
+#define ALRM0SS_MASKSSC(regval)            (BITS(24,27) & ((uint32_t)(regval) << 24U))  /*!< write value to RTC_ALRM0SS_MASKSSC bit field */
+#define RTC_MASKSSC_0_14                   ALRM0SS_MASKSSC(0)                          /*!< mask alarm subsecond configuration */
+#define RTC_MASKSSC_1_14                   ALRM0SS_MASKSSC(1)                          /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */
+#define RTC_MASKSSC_2_14                   ALRM0SS_MASKSSC(2)                          /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */
+#define RTC_MASKSSC_3_14                   ALRM0SS_MASKSSC(3)                          /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */
+#define RTC_MASKSSC_4_14                   ALRM0SS_MASKSSC(4)                          /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */
+#define RTC_MASKSSC_5_14                   ALRM0SS_MASKSSC(5)                          /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */
+#define RTC_MASKSSC_6_14                   ALRM0SS_MASKSSC(6)                          /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */
+#define RTC_MASKSSC_7_14                   ALRM0SS_MASKSSC(7)                          /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */
+#define RTC_MASKSSC_8_14                   ALRM0SS_MASKSSC(8)                          /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */
+#define RTC_MASKSSC_9_14                   ALRM0SS_MASKSSC(9)                          /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */
+#define RTC_MASKSSC_10_14                  ALRM0SS_MASKSSC(10)                         /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */
+#define RTC_MASKSSC_11_14                  ALRM0SS_MASKSSC(11)                         /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */
+#define RTC_MASKSSC_12_14                  ALRM0SS_MASKSSC(12)                         /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */
+#define RTC_MASKSSC_13_14                  ALRM0SS_MASKSSC(13)                         /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */
+#define RTC_MASKSSC_14                     ALRM0SS_MASKSSC(14)                         /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */
+#define RTC_MASKSSC_NONE                   ALRM0SS_MASKSSC(15)                         /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */
 
 /* RTC interrupt source */
-#define RTC_INT_TIMESTAMP                  RTC_CTL_TSIE                               /*!< time-stamp interrupt enable */
-#define RTC_INT_ALARM                      RTC_CTL_ALRM0IE                            /*!< RTC alarm interrupt enable */
-#define RTC_INT_TAMP                       RTC_TAMP_TPIE                              /*!< tamper detection interrupt enable */
+#define RTC_INT_TIMESTAMP                  RTC_CTL_TSIE                                /*!< time-stamp interrupt enable */
+#define RTC_INT_ALARM                      RTC_CTL_ALRM0IE                             /*!< RTC alarm interrupt enable */
+#define RTC_INT_TAMP                       RTC_TAMP_TPIE                               /*!< tamper detection interrupt enable */
 
 /* write protect key */
-#define RTC_UNLOCK_KEY1                    ((uint8_t)0xCAU)                           /*!< RTC unlock key1 */
-#define RTC_UNLOCK_KEY2                    ((uint8_t)0x53U)                           /*!< RTC unlock key2 */
-#define RTC_LOCK_KEY                       ((uint8_t)0xFFU)                           /*!< RTC lock key */
+#define RTC_UNLOCK_KEY1                    ((uint8_t)0xCAU)                            /*!< RTC unlock key1 */
+#define RTC_UNLOCK_KEY2                    ((uint8_t)0x53U)                            /*!< RTC unlock key2 */
+#define RTC_LOCK_KEY                       ((uint8_t)0xFFU)                            /*!< RTC lock key */
 
 /* registers reset value */
-#define RTC_REGISTER_RESET                 ((uint32_t)0x00000000U)                    /*!< RTC common register reset value */
-#define RTC_DATE_RESET                     ((uint32_t)0x00002101U)                    /*!< RTC_DATE register reset value */
-#define RTC_STAT_RESET                     ((uint32_t)0x00000007U)                    /*!< RTC_STAT register reset value */
-#define RTC_PSC_RESET                      ((uint32_t)0x007F00FFU)                    /*!< RTC_PSC register reset value */
+#define RTC_REGISTER_RESET                 ((uint32_t)0x00000000U)                     /*!< RTC common register reset value */
+#define RTC_DATE_RESET                     ((uint32_t)0x00002101U)                     /*!< RTC_DATE register reset value */
+#define RTC_STAT_RESET                     ((uint32_t)0x00000007U)                     /*!< RTC_STAT register reset value */
+#define RTC_PSC_RESET                      ((uint32_t)0x007F00FFU)                     /*!< RTC_PSC register reset value */
 
 /* RTC timeout value */
-#define RTC_INITM_TIMEOUT                  ((uint32_t)0x00004000U)                    /*!< initialization state flag timeout */
-#define RTC_RSYNF_TIMEOUT                  ((uint32_t)0x00008000U)                    /*!< register synchronization flag timeout */
-#define RTC_HRFC_TIMEOUT                   ((uint32_t)0x00001000U)                    /*!< recalibration pending flag timeout */
-#define RTC_SHIFTCTL_TIMEOUT               ((uint32_t)0x00001000U)                    /*!< shift function operation pending flag timeout */
-#define RTC_ALRM0WF_TIMEOUT                ((uint32_t)0x00008000U)                    /*!< alarm configuration can be write flag timeout */
+#define RTC_INITM_TIMEOUT                  ((uint32_t)0x00004000U)                     /*!< initialization state flag timeout */
+#define RTC_RSYNF_TIMEOUT                  ((uint32_t)0x00008000U)                     /*!< register synchronization flag timeout */
+#define RTC_HRFC_TIMEOUT                   ((uint32_t)0x00001000U)                     /*!< recalibration pending flag timeout */
+#define RTC_SHIFTCTL_TIMEOUT               ((uint32_t)0x00001000U)                     /*!< shift function operation pending flag timeout */
+#define RTC_ALRM0WF_TIMEOUT                ((uint32_t)0x00008000U)                     /*!< alarm configuration can be write flag timeout */
 
 /* RTC flag */
-#define RTC_FLAG_RECALIBRATION             RTC_STAT_SCPF                              /*!< recalibration pending flag */
-#define RTC_FLAG_TAMP1                     RTC_STAT_TP1F                              /*!< tamper 1 event flag */
-#define RTC_FLAG_TAMP0                     RTC_STAT_TP0F                              /*!< tamper 0 event flag */
-#define RTC_FLAG_TIMESTAMP_OVERFLOW        RTC_STAT_TSOVRF                            /*!< time-stamp overflow event flag */
-#define RTC_FLAG_TIMESTAMP                 RTC_STAT_TSF                               /*!< time-stamp event flag */
-#define RTC_FLAG_ALARM0                    RTC_STAT_ALRM0F                            /*!< alarm event flag */
-#define RTC_FLAG_INIT                      RTC_STAT_INITF                             /*!< init mode event flag */
-#define RTC_FLAG_RSYN                      RTC_STAT_RSYNF                             /*!< registers synchronized flag */
-#define RTC_FLAG_YCM                       RTC_STAT_YCM                               /*!< year parameter configured event flag */
-#define RTC_FLAG_SHIFT                     RTC_STAT_SOPF                              /*!< shift operation pending flag */
-#define RTC_FLAG_ALARM0_WRITTEN            RTC_STAT_ALRM0WF                           /*!< alarm written available flag */
+#define RTC_FLAG_RECALIBRATION             RTC_STAT_SCPF                               /*!< recalibration pending flag */
+#define RTC_FLAG_TAMP1                     RTC_STAT_TP1F                               /*!< tamper 1 event flag */
+#define RTC_FLAG_TAMP0                     RTC_STAT_TP0F                               /*!< tamper 0 event flag */
+#define RTC_FLAG_TIMESTAMP_OVERFLOW        RTC_STAT_TSOVRF                             /*!< time-stamp overflow event flag */
+#define RTC_FLAG_TIMESTAMP                 RTC_STAT_TSF                                /*!< time-stamp event flag */
+#define RTC_FLAG_ALARM0                    RTC_STAT_ALRM0F                             /*!< alarm event flag */
+#define RTC_FLAG_INIT                      RTC_STAT_INITF                              /*!< init mode event flag */
+#define RTC_FLAG_RSYN                      RTC_STAT_RSYNF                              /*!< registers synchronized flag */
+#define RTC_FLAG_YCM                       RTC_STAT_YCM                                /*!< year parameter configured event flag */
+#define RTC_FLAG_SHIFT                     RTC_STAT_SOPF                               /*!< shift operation pending flag */
+#define RTC_FLAG_ALARM0_WRITTEN            RTC_STAT_ALRM0WF                            /*!< alarm written available flag */
 
 /* function declarations */
 /* reset most of the RTC registers */
@@ -511,7 +507,7 @@ uint32_t rtc_subsecond_get(void);
 /* configure RTC alarm */
 void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time);
 /* configure subsecond of RTC alarm */
-void rtc_alarm_subsecond_config(uint32_t mask_subsecond,  uint32_t subsecond);
+void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond);
 /* get RTC alarm */
 void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time);
 /* get RTC alarm subsecond */
@@ -551,7 +547,7 @@ ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus)
 /* ajust the daylight saving time by adding or substracting one hour from the current time */
 void rtc_hour_adjust(uint32_t operation);
 /* ajust RTC second or subsecond value of current time */
-ErrStatus rtc_second_ajust(uint32_t add, uint32_t minus);
+ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus);
 /* enable RTC bypass shadow registers function */
 void rtc_bypass_shadow_enable(void);
 /* disable RTC bypass shadow registers function */
@@ -561,4 +557,4 @@ ErrStatus rtc_refclock_detection_enable(void);
 /* disable RTC reference clock detection function */
 ErrStatus rtc_refclock_detection_disable(void);
 
-#endif /* GD32F1X0_RTC_H */
+#endif /* GD32F3X0_RTC_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_spi.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_spi.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_spi.h
+    \file  gd32f3x0_spi.h
     \brief definitions for the SPI
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,98 +33,96 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_SPI_H
-#define GD32F1X0_SPI_H
+#ifndef GD32F3X0_SPI_H
+#define GD32F3X0_SPI_H
 
-#include "gd32f1x0.h"
+#include "gd32f3x0.h"
 
-/* SPIx(x=0,1,2) definitions */
+/* SPIx(x=0,1) definitions */
 #define SPI0                            (SPI_BASE + 0x0000F800U)
 #define SPI1                            SPI_BASE
-#define SPI2                            (SPI_BASE + 0x00000400U)
-
-/* registers definitions */
-#define SPI_CTL0(spix)                  REG32((spix) + 0x00000000U)            /*!< SPI control register 0 */
-#define SPI_CTL1(spix)                  REG32((spix) + 0x00000004U)            /*!< SPI control register 1 */
-#define SPI_STAT(spix)                  REG32((spix) + 0x00000008U)            /*!< SPI status register */
-#define SPI_DATA(spix)                  REG32((spix) + 0x0000000CU)            /*!< SPI data register */
-#define SPI_CRCPOLY(spix)               REG32((spix) + 0x00000010U)            /*!< SPI CRC polynomial register */
-#define SPI_RCRC(spix)                  REG32((spix) + 0x00000014U)            /*!< SPI receive CRC register */
-#define SPI_TCRC(spix)                  REG32((spix) + 0x00000018U)            /*!< SPI transmit CRC register */
-#define SPI_I2SCTL(spix)                REG32((spix) + 0x0000001CU)            /*!< SPI I2S control register */
-#define SPI_I2SPSC(spix)                REG32((spix) + 0x00000020U)            /*!< SPI I2S clock prescaler register */
-#ifdef GD32F170_190
-#define SPI_QCTL(spix)                  REG32((spix) + 0x00000080U)            /*!< SPI quad mode control register(only available in SPI1) */
-#endif /* GD32F170_190 */ 
+
+/* SPI registers definitions */
+#define SPI_CTL0(spix)                  REG32((spix) + 0x00000000U)             /*!< SPI control register 0 */
+#define SPI_CTL1(spix)                  REG32((spix) + 0x00000004U)             /*!< SPI control register 1*/
+#define SPI_STAT(spix)                  REG32((spix) + 0x00000008U)             /*!< SPI status register */
+#define SPI_DATA(spix)                  REG32((spix) + 0x0000000CU)             /*!< SPI data register */
+#define SPI_CRCPOLY(spix)               REG32((spix) + 0x00000010U)             /*!< SPI CRC polynomial register */
+#define SPI_RCRC(spix)                  REG32((spix) + 0x00000014U)             /*!< SPI receive CRC register */
+#define SPI_TCRC(spix)                  REG32((spix) + 0x00000018U)             /*!< SPI transmit CRC register */
+#define SPI_I2SCTL(spix)                REG32((spix) + 0x0000001CU)             /*!< SPI I2S control register */
+#define SPI_I2SPSC(spix)                REG32((spix) + 0x00000020U)             /*!< SPI I2S clock prescaler register */
+#define SPI_QCTL(spix)                  REG32((spix) + 0x00000080U)             /*!< SPI quad mode control register(only SPI1) */
 
 /* bits definitions */
 /* SPI_CTL0 */
-#define SPI_CTL0_CKPH                   BIT(0)                                 /*!< clock phase selection */
-#define SPI_CTL0_CKPL                   BIT(1)                                 /*!< clock polarity selection */
-#define SPI_CTL0_MSTMOD                 BIT(2)                                 /*!< master mode enable */
-#define SPI_CTL0_PSC                    BITS(3,5)                              /*!< master clock prescaler selection */
-#define SPI_CTL0_SPIEN                  BIT(6)                                 /*!< SPI enable*/
-#define SPI_CTL0_LF                     BIT(7)                                 /*!< LSB first mode */
-#define SPI_CTL0_SWNSS                  BIT(8)                                 /*!< NSS pin selection in NSS software mode */
-#define SPI_CTL0_SWNSSEN                BIT(9)                                 /*!< NSS software mode selection */
-#define SPI_CTL0_RO                     BIT(10)                                /*!< receive only */
-#define SPI_CTL0_FF16                   BIT(11)                                /*!< data frame size */
-#define SPI_CTL0_CRCNT                  BIT(12)                                /*!< CRC next transfer */
-#define SPI_CTL0_CRCEN                  BIT(13)                                /*!< CRC calculation enable */
-#define SPI_CTL0_BDOEN                  BIT(14)                                /*!< bidirectional transmit output enable */
-#define SPI_CTL0_BDEN                   BIT(15)                                /*!< bidirectional enable */
+#define SPI_CTL0_CKPH                   BIT(0)                                  /*!< clock phase selection*/
+#define SPI_CTL0_CKPL                   BIT(1)                                  /*!< clock polarity selection */
+#define SPI_CTL0_MSTMOD                 BIT(2)                                  /*!< master mode enable */
+#define SPI_CTL0_PSC                    BITS(3,5)                               /*!< master clock prescaler selection */
+#define SPI_CTL0_SPIEN                  BIT(6)                                  /*!< SPI enable*/
+#define SPI_CTL0_LF                     BIT(7)                                  /*!< LSB first mode */
+#define SPI_CTL0_SWNSS                  BIT(8)                                  /*!< NSS pin selection in NSS software mode */
+#define SPI_CTL0_SWNSSEN                BIT(9)                                  /*!< NSS software mode selection */
+#define SPI_CTL0_RO                     BIT(10)                                 /*!< receive only */
+#define SPI_CTL0_FF16                   BIT(11)                                 /*!< data frame size */
+#define SPI_CTL0_CRCNT                  BIT(12)                                 /*!< CRC next transfer */
+#define SPI_CTL0_CRCEN                  BIT(13)                                 /*!< CRC calculation enable */
+#define SPI_CTL0_BDOEN                  BIT(14)                                 /*!< bidirectional transmit output enable*/
+#define SPI_CTL0_BDEN                   BIT(15)                                 /*!< bidirectional enable */
 
 /* SPI_CTL1 */
-#define SPI_CTL1_DMAREN                 BIT(0)                                 /*!< receive buffer dma enable */
-#define SPI_CTL1_DMATEN                 BIT(1)                                 /*!< transmit buffer dma enable */
-#define SPI_CTL1_NSSDRV                 BIT(2)                                 /*!< drive NSS output */
-#define SPI_CTL1_ERRIE                  BIT(5)                                 /*!< errors interrupt enable */
-#define SPI_CTL1_RBNEIE                 BIT(6)                                 /*!< receive buffer not empty interrupt enable */
-#define SPI_CTL1_TBEIE                  BIT(7)                                 /*!< transmit buffer empty interrupt enable */
+#define SPI_CTL1_DMAREN                 BIT(0)                                  /*!< receive buffer dma enable */
+#define SPI_CTL1_DMATEN                 BIT(1)                                  /*!< transmit buffer dma enable */
+#define SPI_CTL1_NSSDRV                 BIT(2)                                  /*!< drive NSS output */
+#define SPI_CTL1_NSSP                   BIT(3)                                  /*!< SPI NSS pulse mode enable */
+#define SPI_CTL1_TMOD                   BIT(4)                                  /*!< SPI TI mode enable */
+#define SPI_CTL1_ERRIE                  BIT(5)                                  /*!< errors interrupt enable */
+#define SPI_CTL1_RBNEIE                 BIT(6)                                  /*!< receive buffer not empty interrupt enable */
+#define SPI_CTL1_TBEIE                  BIT(7)                                  /*!< transmit buffer empty interrupt enable */
 
 /* SPI_STAT */
-#define SPI_STAT_RBNE                   BIT(0)                                 /*!< receive buffer not empty */
-#define SPI_STAT_TBE                    BIT(1)                                 /*!< transmit buffer empty */
-#define SPI_STAT_I2SCH                  BIT(2)                                 /*!< I2S channel side */
-#define SPI_STAT_TXURERR                BIT(3)                                 /*!< I2S transmission underrun error bit */
-#define SPI_STAT_CRCERR                 BIT(4)                                 /*!< SPI CRC error bit */
-#define SPI_STAT_CONFERR                BIT(5)                                 /*!< SPI configuration error bit */
-#define SPI_STAT_RXORERR                BIT(6)                                 /*!< SPI reception overrun error bit */
-#define SPI_STAT_TRANS                  BIT(7)                                 /*!< transmitting on-going bit */
+#define SPI_STAT_RBNE                   BIT(0)                                  /*!< receive buffer not empty */
+#define SPI_STAT_TBE                    BIT(1)                                  /*!< transmit buffer empty */
+#define SPI_STAT_I2SCH                  BIT(2)                                  /*!< I2S channel side */
+#define SPI_STAT_TXURERR                BIT(3)                                  /*!< I2S transmission underrun error bit */
+#define SPI_STAT_CRCERR                 BIT(4)                                  /*!< SPI CRC error bit */
+#define SPI_STAT_CONFERR                BIT(5)                                  /*!< SPI configuration error bit */
+#define SPI_STAT_RXORERR                BIT(6)                                  /*!< SPI reception overrun error bit */
+#define SPI_STAT_TRANS                  BIT(7)                                  /*!< transmitting on-going bit */
+#define SPI_STAT_FERR                   BIT(8)                                  /*!< format error bit */
 
 /* SPI_DATA */
-#define SPI_DATA_DATA                   BITS(0,15)                             /*!< data transfer register */
+#define SPI_DATA_DATA                   BITS(0,15)                              /*!< data transfer register */
 
 /* SPI_CRCPOLY */
-#define SPI_CRCPOLY_CRCPOLY             BITS(0,15)                             /*!< CRC polynomial value */
+#define SPI_CRCPOLY_CRCPOLY             BITS(0,15)                              /*!< CRC polynomial value */
 
 /* SPI_RCRC */
-#define SPI_RCRC_RCRC                   BITS(0,15)                             /*!< RX CRC value */
+#define SPI_RCRC_RCRC                   BITS(0,15)                              /*!< RX CRC value */
 
 /* SPI_TCRC */
-#define SPI_TCRC_TCRC                   BITS(0,15)                             /*!< TX CRC value */
+#define SPI_TCRC_TCRC                   BITS(0,15)                              /*!< TX CRC value */
 
 /* SPI_I2SCTL */
-#define SPI_I2SCTL_CHLEN                BIT(0)                                 /*!< channel length */
-#define SPI_I2SCTL_DTLEN                BITS(1,2)                              /*!< data length */
-#define SPI_I2SCTL_CKPL                 BIT(3)                                 /*!< idle state clock polarity */
-#define SPI_I2SCTL_I2SSTD               BITS(4,5)                              /*!< I2S standard selection */
-#define SPI_I2SCTL_PCMSMOD              BIT(7)                                 /*!< PCM frame synchronization mode */
-#define SPI_I2SCTL_I2SOPMOD             BITS(8,9)                              /*!< I2S operation mode */
-#define SPI_I2SCTL_I2SEN                BIT(10)                                /*!< I2S enable */
-#define SPI_I2SCTL_I2SSEL               BIT(11)                                /*!< I2S mode selection */
-
-/* SPI_I2S_PSC */
-#define SPI_I2SPSC_DIV                  BITS(0,7)                              /*!< dividing factor for the prescaler */
-#define SPI_I2SPSC_OF                   BIT(8)                                 /*!< odd factor for the prescaler */
-#define SPI_I2SPSC_MCKOEN               BIT(9)                                 /*!< I2S MCK output enable */
-
-#ifdef GD32F170_190
-/* SPI_QCTL(only available in SPI1) */
-#define SPI_QCTL_QMOD                   BIT(0)                                 /*!< quad-SPI mode enable */
-#define SPI_QCTL_QRD                    BIT(1)                                 /*!< quad-SPI mode read select */
-#define SPI_QCTL_IO23_DRV               BIT(2)                                 /*!< drive SPI_IO2 and SPI_IO3 enable */
-#endif /* GD32F170_190 */ 
+#define SPI_I2SCTL_CHLEN                BIT(0)                                  /*!< channel length */
+#define SPI_I2SCTL_DTLEN                BITS(1,2)                               /*!< data length */
+#define SPI_I2SCTL_CKPL                 BIT(3)                                  /*!< idle state clock polarity */
+#define SPI_I2SCTL_I2SSTD               BITS(4,5)                               /*!< I2S standard selection */
+#define SPI_I2SCTL_PCMSMOD              BIT(7)                                  /*!< PCM frame synchronization mode */
+#define SPI_I2SCTL_I2SOPMOD             BITS(8,9)                               /*!< I2S operation mode */
+#define SPI_I2SCTL_I2SEN                BIT(10)                                 /*!< I2S enable */
+#define SPI_I2SCTL_I2SSEL               BIT(11)                                 /*!< I2S mode selection */
+
+/* SPI_I2SPSC */
+#define SPI_I2SPSC_DIV                  BITS(0,7)                               /*!< dividing factor for the prescaler */
+#define SPI_I2SPSC_OF                   BIT(8)                                  /*!< odd factor for the prescaler */
+#define SPI_I2SPSC_MCKOEN               BIT(9)                                  /*!< I2S MCK output enable */
+
+/* SPI_QCTL(only for SPI1) */
+#define SPI_QCTL_QMOD                   BIT(0)                                  /*!< quad-SPI mode enable */
+#define SPI_QCTL_QRD                    BIT(1)                                  /*!< quad-SPI mode read select */
+#define SPI_QCTL_IO23_DRV               BIT(2)                                  /*!< drive SPI_IO2 and SPI_IO3 enable */
 
 /* constants definitions */
 /* SPI and I2S parameter struct definitions */
@@ -140,7 +135,7 @@ typedef struct
     uint32_t endian;                                                            /*!< SPI big endian or little endian */
     uint32_t clock_polarity_phase;                                              /*!< SPI clock phase and polarity */
     uint32_t prescale;                                                          /*!< SPI prescale factor */
-}spi_parameter_struct;                                                         
+}spi_parameter_struct;
 
 /* SPI mode definitions */
 #define SPI_MASTER                      (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)      /*!< SPI as master */
@@ -154,7 +149,7 @@ typedef struct
 #define SPI_TRANSMODE_FULLDUPLEX        ((uint32_t)0x00000000U)                 /*!< SPI receive and send data at fullduplex communication */
 #define SPI_TRANSMODE_RECEIVEONLY       SPI_CTL0_RO                             /*!< SPI only receive data */
 #define SPI_TRANSMODE_BDRECEIVE         SPI_CTL0_BDEN                           /*!< bidirectional receive data */
-#define SPI_TRANSMODE_BDTRANSMIT        (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)        /*!< bidirectional transmit data */
+#define SPI_TRANSMODE_BDTRANSMIT        (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)        /*!< bidirectional transmit data*/
 
 /* SPI frame size */
 #define SPI_FRAMESIZE_16BIT             SPI_CTL0_FF16                           /*!< SPI frame size is 16 bits */
@@ -185,6 +180,7 @@ typedef struct
 #define SPI_PSC_128                     CTL0_PSC(6)                             /*!< SPI clock prescale factor is 128 */
 #define SPI_PSC_256                     CTL0_PSC(7)                             /*!< SPI clock prescale factor is 256 */
 
+#ifdef GD32F350
 /* I2S audio sample rate */
 #define I2S_AUDIOSAMPLE_8K              ((uint32_t)8000U)                       /*!< I2S audio sample rate is 8KHz */
 #define I2S_AUDIOSAMPLE_11K             ((uint32_t)11025U)                      /*!< I2S audio sample rate is 11KHz */
@@ -225,6 +221,7 @@ typedef struct
 /* I2S clock polarity */
 #define I2S_CKPL_LOW                    ((uint32_t)0x00000000U)                 /*!< I2S clock polarity low level */
 #define I2S_CKPL_HIGH                   SPI_I2SCTL_CKPL                         /*!< I2S clock polarity high level */
+#endif /* GD32F350 */
 
 /* SPI DMA constants definitions */                                    
 #define SPI_DMA_TRANSMIT                ((uint8_t)0x00U)                        /*!< SPI transmit data use DMA */
@@ -246,20 +243,27 @@ typedef struct
 #define SPI_INT_FLAG_CONFERR            ((uint8_t)0x03U)                        /*!< config error interrupt flag */
 #define SPI_INT_FLAG_CRCERR             ((uint8_t)0x04U)                        /*!< CRC error interrupt flag */
 #define I2S_INT_FLAG_TXURERR            ((uint8_t)0x05U)                        /*!< underrun error interrupt flag */
-    
-/* SPI/I2S flag definitions */                                                  
+#define SPI_I2S_INT_FLAG_FERR           ((uint8_t)0x06U)                        /*!< format error interrupt flag */
+
+/* SPI flag definitions */                                                  
 #define SPI_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
 #define SPI_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
 #define SPI_FLAG_CRCERR                 SPI_STAT_CRCERR                         /*!< CRC error flag */
 #define SPI_FLAG_CONFERR                SPI_STAT_CONFERR                        /*!< mode config error flag */
 #define SPI_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< receive overrun error flag */
 #define SPI_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
+#define SPI_FLAG_FERR                   SPI_STAT_FERR                           /*!< format error interrupt flag */
+
+#ifdef GD32F350
+/* I2S flag definitions */ 
 #define I2S_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
 #define I2S_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
 #define I2S_FLAG_CH                     SPI_STAT_I2SCH                          /*!< channel side flag */
 #define I2S_FLAG_TXURERR                SPI_STAT_TXURERR                        /*!< underrun error flag */
 #define I2S_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< overrun error flag */
 #define I2S_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
+#define I2S_FLAG_FERR                   SPI_STAT_FERR                           /*!< format error interrupt flag */
+#endif /* GD32F350 */
 
 /* function declarations */
 /* SPI/I2S deinitialization and initialization functions */
@@ -274,6 +278,7 @@ void spi_enable(uint32_t spi_periph);
 /* disable SPI */
 void spi_disable(uint32_t spi_periph);
 
+#ifdef GD32F350
 /* initialize I2S parameter */
 void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
 /* configure I2S prescaler */
@@ -282,6 +287,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
 void i2s_enable(uint32_t spi_periph);
 /* disable I2S */
 void i2s_disable(uint32_t spi_periph);
+#endif /* GD32F350 */
 
 /* NSS functions */
 /* enable SPI NSS output */
@@ -293,7 +299,6 @@ void spi_nss_internal_high(uint32_t spi_periph);
 /* SPI NSS pin low level in software mode */
 void spi_nss_internal_low(uint32_t spi_periph);
 
-/* DMA functions */
 /* enable SPI DMA */
 void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
 /* disable SPI DMA */
@@ -322,7 +327,18 @@ void spi_crc_next(uint32_t spi_periph);
 /* get SPI CRC send value or receive value */
 uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
 
-#ifdef GD32F170_190 
+/* SPI TI mode functions */
+/* enable SPI TI mode */
+void spi_ti_mode_enable(uint32_t spi_periph);
+/* disable SPI TI mode */
+void spi_ti_mode_disable(uint32_t spi_periph);
+
+/* SPI NSS pulse mode functions */
+/* enable SPI NSS pulse mode */
+void spi_nssp_mode_enable(uint32_t spi_periph);
+/* disable SPI NSS pulse mode */
+void spi_nssp_mode_disable(uint32_t spi_periph);
+
 /* quad wire SPI functions */
 /* enable quad wire SPI */
 void qspi_enable(uint32_t spi_periph);
@@ -336,9 +352,8 @@ void qspi_read_enable(uint32_t spi_periph);
 void qspi_io23_output_enable(uint32_t spi_periph);
 /* disable quad wire SPI_IO2 and SPI_IO3 pin output */
 void qspi_io23_output_disable(uint32_t spi_periph);
-#endif /* GD32F170_190 */
 
-/* flag and interrupt functions */ 
+/* flag and interrupt functions */
 /* enable SPI and I2S interrupt */
 void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
 /* disable SPI and I2S interrupt */
@@ -350,4 +365,4 @@ FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
 /* clear SPI CRC error flag status */
 void spi_crc_error_clear(uint32_t spi_periph);
 
-#endif /* GD32F1X0_SPI_H */
+#endif /* GD32F3X0_SPI_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_syscfg.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_syscfg.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_syscfg.h
+    \file  gd32f3x0_syscfg.h
     \brief definitions for the SYSCFG
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,24 +33,22 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_SYSCFG_H
-#define GD32F1X0_SYSCFG_H
+#ifndef GD32F3X0_SYSCFG_H
+#define GD32F3X0_SYSCFG_H
 
-#include "gd32f1x0.h"
+#include "gd32f3x0.h"
 
 /* SYSCFG definitions */
 #define SYSCFG                              SYSCFG_BASE
 
 /* registers definitions */
-#define SYSCFG_CFG0                         REG32(SYSCFG + 0x00U)               /*!< system configuration register 0 */
-#ifdef GD32F170_190
-#define SYSCFG_CFG1                         REG32(SYSCFG + 0x04U)               /*!< system configuration register 1 */
-#endif /* GD32F170_190 */
-#define SYSCFG_EXTISS0                      REG32(SYSCFG + 0x08U)               /*!< EXTI sources selection register 0 */
-#define SYSCFG_EXTISS1                      REG32(SYSCFG + 0x0CU)               /*!< EXTI sources selection register 1 */
-#define SYSCFG_EXTISS2                      REG32(SYSCFG + 0x10U)               /*!< EXTI sources selection register 2 */
-#define SYSCFG_EXTISS3                      REG32(SYSCFG + 0x14U)               /*!< EXTI sources selection register 3 */
-#define SYSCFG_CFG2                         REG32(SYSCFG + 0x18U)               /*!< system configuration register 2 */
+#define SYSCFG_CFG0                         REG32(SYSCFG + 0x00000000U)         /*!< system configuration register 0 */
+#define SYSCFG_EXTISS0                      REG32(SYSCFG + 0x00000008U)         /*!< EXTI sources selection register 0 */
+#define SYSCFG_EXTISS1                      REG32(SYSCFG + 0x0000000CU)         /*!< EXTI sources selection register 1 */
+#define SYSCFG_EXTISS2                      REG32(SYSCFG + 0x00000010U)         /*!< EXTI sources selection register 2 */
+#define SYSCFG_EXTISS3                      REG32(SYSCFG + 0x00000014U)         /*!< EXTI sources selection register 3 */
+#define SYSCFG_CFG2                         REG32(SYSCFG + 0x00000018U)         /*!< system configuration register 2 */
+#define SYSCFG_CPSCTL                       REG32(SYSCFG + 0x00000020U)         /*!< system I/O compensation control register */
 
 /* SYSCFG_CFG0 bits definitions */
 #define SYSCFG_CFG0_BOOT_MODE               BITS(0,1)                           /*!< SYSCFG memory remap config */
@@ -64,11 +59,6 @@ OF SUCH DAMAGE.
 #define SYSCFG_CFG0_TIMER16_DMA_RMP         BIT(12)                             /*!< TIMER 16 DMA remap config */
 #define SYSCFG_CFG0_PB9_HCCE                BIT(19)                             /*!< PB9 pin high current capability enable */
 
-#ifdef GD32F170_190
-/* SYSCFG_CFG1 bits definitions */
-#define SYSCFG_CFG1_SLCD_DECA               BITS(1,3)                           /*!< decouping capacitance connection for LCD */
-#endif /* GD32F170_190 */
-
 /* SYSCFG_EXTISS0 bits definitions */
 #define SYSCFG_EXTISS0_EXTI0_SS             BITS(0,3)                           /*!< EXTI 0 configuration */
 #define SYSCFG_EXTISS0_EXTI1_SS             BITS(4,7)                           /*!< EXTI 1 configuration */
@@ -99,6 +89,10 @@ OF SUCH DAMAGE.
 #define SYSCFG_CFG2_LVD_LOCK                BIT(2)                              /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */
 #define SYSCFG_CFG2_SRAM_PCEF               BIT(8)                              /*!< SRAM parity check error flag */
 
+/* SYSCFG_CPSCTL bits definitions */
+#define SYSCFG_CPSCTL_CPS_EN                BIT(0)                              /*!< I/O compensation cell enable */
+#define SYSCFG_CPSCTL_CPS_RDY               BIT(8)                              /*!< I/O compensation cell is ready or not */
+
 /* constants definitions */
 /* DMA remap definitions */
 #define SYSCFG_DMA_REMAP_ADC                SYSCFG_CFG0_ADC_DMA_RMP             /*!< ADC DMA remap */
@@ -121,7 +115,7 @@ OF SUCH DAMAGE.
 #define EXTI_SS_MASK                        BITS(0,3)                           /*!< EXTI source select mask */
 
 /* EXTI source select jumping step definition */
-#define EXTI_SS_JSTEP                       ((uint8_t)(0x04U))                  /*!< EXTI source select jumping step */
+#define EXTI_SS_JSTEP                       ((uint8_t)0x04U)                    /*!< EXTI source select jumping step */
 
 /* EXTI source select moving step definition */
 #define EXTI_SS_MSTEP(pin)                  (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP))   /*!< EXTI source select moving step */
@@ -159,20 +153,10 @@ OF SUCH DAMAGE.
 /* SRAM parity check error flag definitions */
 #define SYSCFG_SRAM_PCEF                    SYSCFG_CFG2_SRAM_PCEF               /*!< SRAM parity check error flag */
 
-#ifdef GD32F170_190
-#define SYSCFG_LCD_DECA(regval)             (BITS(1,3) & ((uint32_t)(regval) << 1))
-#define SYSCFG_VLCD_RAIL1                   SYSCFG_LCD_DECA(2)                  /*!< VLCD rail1 */
-#define SYSCFG_VLCD_RAIL2                   SYSCFG_LCD_DECA(1)                  /*!< VLCD rail2 */
-#define SYSCFG_VLCD_RAIL3                   SYSCFG_LCD_DECA(4)                  /*!< VLCD rail3 */
-
-/* VLCD bias definition */
-#define VLCD_BIAS1_2_RAIL1                  ((uint8_t)0)                        /*!< VLCD bias is 1/2, using VLCDrail1 */
-#define VLCD_BIAS1_2_RAIL2                  ((uint8_t)1)                        /*!< VLCD bias is 1/2, using VLCDrail2 */
-#define VLCD_BIAS1_2_RAIL3                  ((uint8_t)2)                        /*!< VLCD bias is 1/2, using VLCDrail3 */
-#define VLCD_BIAS1_3_RAIL1_2                ((uint8_t)3)                        /*!< VLCD bias is 1/3, using VLCDrail1 and VLCDrail2 */
-#define VLCD_BIAS1_3_RAIL1_3                ((uint8_t)4)                        /*!< VLCD bias is 1/3, using VLCDrail1 and VLCDrail3 */
-#define VLCD_BIAS1_4_RAILALL                ((uint8_t)5)                        /*!< VLCD bias is 1/4, using all VLCDrails */
-#endif /* GD32F170_190 */
+/* I/O compensation cell enable/disable */
+#define SYSCFG_COMPENSATION(regval)         (BIT(0) & ((uint32_t)(regval) << 0))
+#define SYSCFG_COMPENSATION_DISABLE         SYSCFG_COMPENSATION(0)              /*!< I/O compensation cell is power-down */
+#define SYSCFG_COMPENSATION_ENABLE          SYSCFG_COMPENSATION(1)              /*!< I/O compensation cell is enabled */
 
 /* function declarations */
 /* deinit syscfg module */
@@ -198,9 +182,9 @@ FlagStatus syscfg_flag_get(uint32_t syscfg_flag);
 /* clear the flag in SYSCFG_CFG2 by writing 1 */
 void syscfg_flag_clear(uint32_t syscfg_flag);
 
-#ifdef GD32F170_190
-/* configure the VLCD intermediate voltage rail */
-void syscfg_vlcd_rail_config(uint8_t vlcd_bias);
-#endif /* GD32F170_190 */
+/* configure the I/O compensation cell */
+void syscfg_compensation_config(uint32_t syscfg_compensation);
+/* check if the I/O compensation cell ready flag is set or not */
+FlagStatus syscfg_cps_rdy_flag_get(void);
 
-#endif /* GD32F1X0_SYSCFG_H */
+#endif /* GD32F3X0_SYSCFG_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_timer.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_timer.h

@@ -1,17 +1,15 @@
 /*!
-    \file  gd32f1x0_timer.h
+    \file  gd32f3x0_timer.h
     \brief definitions for the TIMER
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
     Copyright (c) 2019, GigaDevice Semiconductor Inc.
 
+
     Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:
 
@@ -36,16 +34,18 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_TIMER_H
-#define GD32F1X0_TIMER_H
+#ifndef GD32F3X0_TIMER_H
+#define GD32F3X0_TIMER_H
 
-#include "gd32f1x0.h"
+#include "gd32f3x0.h"
 
-/* TIMERx(x=0,1,2,5,13,14,15,16) definitions,, TIMER5 just for GD32F150 and GD32F190 */
+/* TIMERx(x=0,1,2,5,13..16) definitions */
 #define TIMER0                           (TIMER_BASE + 0x00012C00U)
 #define TIMER1                           (TIMER_BASE + 0x00000000U)
 #define TIMER2                           (TIMER_BASE + 0x00000400U)
+#ifdef GD32F350
 #define TIMER5                           (TIMER_BASE + 0x00001000U)
+#endif
 #define TIMER13                          (TIMER_BASE + 0x00002000U)
 #define TIMER14                          (TIMER_BASE + 0x00014000U)
 #define TIMER15                          (TIMER_BASE + 0x00014400U)
@@ -334,7 +334,7 @@ typedef struct
 #define TIMER_INT_FLAG_CH3                  TIMER_INTF_CH3IF                        /*!< channel 3 interrupt flag */
 #define TIMER_INT_FLAG_CMT                  TIMER_INTF_CMTIF                        /*!< channel commutation interrupt flag */
 #define TIMER_INT_FLAG_TRG                  TIMER_INTF_TRGIF                        /*!< trigger interrupt flag */
-#define TIMER_INT_FLAG_BRK                  TIMER_INTF_BRKIF                        /*!< break interrupt flag */
+#define TIMER_INT_FLAG_BRK                  TIMER_INTF_BRKIF
 
 /* TIMER DMA source enable */
 #define TIMER_DMA_UPD                       ((uint16_t)TIMER_DMAINTEN_UPDEN)        /*!< update DMA enable */
@@ -420,9 +420,9 @@ typedef struct
 
 /* specify division ratio between TIMER clock and dead-time and sampling clock */
 #define CTL0_CKDIV(regval)                  ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
-#define TIMER_CKDIV_DIV1                    CTL0_CKDIV(0)                           /*!< clock division value is 1, fDTS = fTIMER_CK */
-#define TIMER_CKDIV_DIV2                    CTL0_CKDIV(1)                           /*!< clock division value is 2, fDTS = fTIMER_CK/2 */
-#define TIMER_CKDIV_DIV4                    CTL0_CKDIV(2)                           /*!< clock division value is 4, fDTS = fTIMER_CK/4 */
+#define TIMER_CKDIV_DIV1                    CTL0_CKDIV(0)                           /*!< clock division value is 1, fDTS=fTIMER_CK */
+#define TIMER_CKDIV_DIV2                    CTL0_CKDIV(1)                           /*!< clock division value is 2, fDTS= fTIMER_CK/2 */
+#define TIMER_CKDIV_DIV4                    CTL0_CKDIV(2)                           /*!< clock division value is 4, fDTS= fTIMER_CK/4 */
 
 /* single pulse mode */
 #define TIMER_SP_MODE_SINGLE                ((uint8_t)0x00U)                        /*!< single pulse mode */
@@ -437,8 +437,8 @@ typedef struct
 #define TIMER_ROS_STATE_DISABLE             ((uint32_t)0x00000000U)                 /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */
 
 /* idle mode off-state configure */                                                 
-#define TIMER_IOS_STATE_ENABLE              ((uint16_t)0x00000400U)                     /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
-#define TIMER_IOS_STATE_DISABLE             ((uint16_t)0x00000000U)                     /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */
+#define TIMER_IOS_STATE_ENABLE              ((uint16_t)0x0400U)                     /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
+#define TIMER_IOS_STATE_DISABLE             ((uint16_t)0x0000U)                     /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */
 
 /* break input polarity */
 #define TIMER_BREAK_POLARITY_LOW            ((uint16_t)0x0000U)                     /*!< break input polarity is low */
@@ -482,8 +482,8 @@ typedef struct
 #define TIMER_OCN_POLARITY_LOW              ((uint16_t)0x0008U)                     /*!< channel complementary output polarity is low */
 
 /* idle state of channel output */ 
-#define TIMER_OC_IDLE_STATE_HIGH            ((uint16_t)0x0100U)                     /*!< idle state of channel output is high */
-#define TIMER_OC_IDLE_STATE_LOW             ((uint16_t)0x0000U)                     /*!< idle state of channel output is low */
+#define TIMER_OC_IDLE_STATE_HIGH            ((uint16_t)0x0100)                      /*!< idle state of channel output is high */
+#define TIMER_OC_IDLE_STATE_LOW             ((uint16_t)0x0000)                      /*!< idle state of channel output is low */
 
 /* idle state of channel complementary output */ 
 #define TIMER_OCN_IDLE_STATE_HIGH           ((uint16_t)0x0200U)                     /*!< idle state of channel complementary output is high */
@@ -504,8 +504,8 @@ typedef struct
 #define TIMER_OC_SHADOW_DISABLE             ((uint16_t)0x0000U)                     /*!< channel output shadow state disable */
 
 /* channel output compare fast enable */
-#define TIMER_OC_FAST_ENABLE                ((uint16_t)0x0004U)                     /*!< channel output fast function enable */
-#define TIMER_OC_FAST_DISABLE               ((uint16_t)0x0000U)                     /*!< channel output fast function disable */
+#define TIMER_OC_FAST_ENABLE                ((uint16_t)0x0004)                      /*!< channel output fast function enable */
+#define TIMER_OC_FAST_DISABLE               ((uint16_t)0x0000)                      /*!< channel output fast function disable */
 
 /* channel output compare clear enable */
 #define TIMER_OC_CLEAR_ENABLE               ((uint16_t)0x0080U)                     /*!< channel output clear function enable */
@@ -765,4 +765,4 @@ void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel);
 /* configure TIMER output value selection */
 void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel);
 
-#endif /* GD32F1X0_TIMER_H */
+#endif /* GD32F3X0_TIMER_H */

Librarys/GD32F3x0_Drivers/Include/gd32f3x0_tsi.h

@@ -0,0 +1,388 @@
+/*!
+    \file  gd32f3x0_tsi.h
+    \brief definitions for the TSI
+    
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F3X0_TSI_H
+#define GD32F3X0_TSI_H
+
+#include "gd32f3x0.h"
+
+/* TSI definitions */
+#define TSI                     TSI_BASE                /*!< TSI base address */
+
+/* registers definitions */
+#define TSI_CTL0                REG32(TSI + 0x00000000U)/*!< TSI control register0 */
+#define TSI_INTEN               REG32(TSI + 0x00000004U)/*!< TSI interrupt enable register */
+#define TSI_INTC                REG32(TSI + 0x00000008U)/*!< TSI interrupt flag clear register */
+#define TSI_INTF                REG32(TSI + 0x0000000CU)/*!< TSI interrupt flag register */
+#define TSI_PHM                 REG32(TSI + 0x00000010U)/*!< TSI pin hysteresis mode register */
+#define TSI_ASW                 REG32(TSI + 0x00000018U)/*!< TSI analog switch register */
+#define TSI_SAMPCFG             REG32(TSI + 0x00000020U)/*!< TSI sample configuration register */
+#define TSI_CHCFG               REG32(TSI + 0x00000028U)/*!< TSI channel configuration register */
+#define TSI_GCTL                REG32(TSI + 0x00000030U)/*!< TSI group control register */
+#define TSI_G0CYCN              REG32(TSI + 0x00000034U)/*!< TSI group 0 cycle number register */
+#define TSI_G1CYCN              REG32(TSI + 0x00000038U)/*!< TSI group 1 cycle number register */
+#define TSI_G2CYCN              REG32(TSI + 0x0000003CU)/*!< TSI group 2 cycle number register */
+#define TSI_G3CYCN              REG32(TSI + 0x00000040U)/*!< TSI group 3 cycle number register */
+#define TSI_G4CYCN              REG32(TSI + 0x00000044U)/*!< TSI group 4 cycle number register */
+#define TSI_G5CYCN              REG32(TSI + 0x00000048U)/*!< TSI group 5 cycle number register */
+#define TSI_CTL1                REG32(TSI + 0x00000300U)/*!< TSI control registers1 */
+
+/* bits definitions */
+/* TSI_CTL0 */
+#define TSI_CTL0_TSIEN          BIT(0)                  /*!< TSI enable */
+#define TSI_CTL0_TSIS           BIT(1)                  /*!< TSI start */
+#define TSI_CTL0_TRGMOD         BIT(2)                  /*!< trigger mode selection */
+#define TSI_CTL0_EGSEL          BIT(3)                  /*!< edge selection */
+#define TSI_CTL0_PINMOD         BIT(4)                  /*!< pin mode */
+#define TSI_CTL0_MCN            BITS(5,7)               /*!< max cycle number of a sequence */
+#define TSI_CTL0_CTCDIV         BITS(12,14)             /*!< CTCLK clock division factor */
+#define TSI_CTL0_ECDIV          BIT(15)                 /*!< ECCLK clock division factor */
+#define TSI_CTL0_ECEN           BIT(16)                 /*!< extend charge state enable */
+#define TSI_CTL0_ECDT           BITS(17,23)             /*!< extend charge State maximum duration time */
+#define TSI_CTL0_CTDT           BITS(24,27)             /*!< charge transfer state duration time */
+#define TSI_CTL0_CDT            BITS(28,31)             /*!< charge state duration time */
+
+/* TSI_INTEN */
+#define TSI_INTEN_CTCFIE        BIT(0)                  /*!< charge transfer complete flag interrupt enable */
+#define TSI_INTEN_MNERRIE       BIT(1)                  /*!< max cycle number error interrupt enable */
+
+/* TSI_INTC */
+#define TSI_INTC_CCTCF          BIT(0)                  /*!< clear charge transfer complete flag */
+#define TSI_INTC_CMNERR         BIT(1)                  /*!< clear max cycle number error */
+
+/* TSI_INTF */
+#define TSI_INTF_CTCF           BIT(0)                  /*!< charge transfer complete flag */
+#define TSI_INTF_MNERR          BIT(1)                  /*!< max cycle number error */
+
+/* TSI_PHM */
+#define TSI_PHM_G0P0            BIT(0)                  /*!< pin G0P0 Schmitt trigger hysteresis state */
+#define TSI_PHM_G0P1            BIT(1)                  /*!< pin G0P1 Schmitt trigger hysteresis state */
+#define TSI_PHM_G0P2            BIT(2)                  /*!< pin G0P2 Schmitt trigger hysteresis state */
+#define TSI_PHM_G0P3            BIT(3)                  /*!< pin G0P3 Schmitt trigger hysteresis state */
+#define TSI_PHM_G1P0            BIT(4)                  /*!< pin G1P0 Schmitt trigger hysteresis state */
+#define TSI_PHM_G1P1            BIT(5)                  /*!< pin G1P1 Schmitt trigger hysteresis state */
+#define TSI_PHM_G1P2            BIT(6)                  /*!< pin G1P2 Schmitt trigger hysteresis state */
+#define TSI_PHM_G1P3            BIT(7)                  /*!< pin G1P3 Schmitt trigger hysteresis state */
+#define TSI_PHM_G2P0            BIT(8)                  /*!< pin G2P0 Schmitt trigger hysteresis state */
+#define TSI_PHM_G2P1            BIT(9)                  /*!< pin G2P1 Schmitt trigger hysteresis state */
+#define TSI_PHM_G2P2            BIT(10)                 /*!< pin G2P2 Schmitt trigger hysteresis state */
+#define TSI_PHM_G2P3            BIT(11)                 /*!< pin G2P3 Schmitt trigger hysteresis state */
+#define TSI_PHM_G3P0            BIT(12)                 /*!< pin G3P0 Schmitt trigger hysteresis state */
+#define TSI_PHM_G3P1            BIT(13)                 /*!< pin G3P1 Schmitt trigger hysteresis state */
+#define TSI_PHM_G3P2            BIT(14)                 /*!< pin G3P2 Schmitt trigger hysteresis state */
+#define TSI_PHM_G3P3            BIT(15)                 /*!< pin G3P3 Schmitt trigger hysteresis state */
+#define TSI_PHM_G4P0            BIT(16)                 /*!< pin G4P0 Schmitt trigger hysteresis state */
+#define TSI_PHM_G4P1            BIT(17)                 /*!< pin G4P1 Schmitt trigger hysteresis state */
+#define TSI_PHM_G4P2            BIT(18)                 /*!< pin G4P2 Schmitt trigger hysteresis state */
+#define TSI_PHM_G4P3            BIT(19)                 /*!< pin G4P3 Schmitt trigger hysteresis state */
+#define TSI_PHM_G5P0            BIT(20)                 /*!< pin G5P0 Schmitt trigger hysteresis state */
+#define TSI_PHM_G5P1            BIT(21)                 /*!< pin G5P1 Schmitt trigger hysteresis state */
+#define TSI_PHM_G5P2            BIT(22)                 /*!< pin G5P2 Schmitt trigger hysteresis state */
+#define TSI_PHM_G5P3            BIT(23)                 /*!< pin G5P3 Schmitt trigger hysteresis state */
+
+/* TSI_ASW */
+#define TSI_ASW_G0P0            BIT(0)                  /*!< pin G0P0 analog switch state */
+#define TSI_ASW_G0P1            BIT(1)                  /*!< pin G0P1 analog switch state */
+#define TSI_ASW_G0P2            BIT(2)                  /*!< pin G0P2 analog switch state */
+#define TSI_ASW_G0P3            BIT(3)                  /*!< pin G0P3 analog switch state */
+#define TSI_ASW_G1P0            BIT(4)                  /*!< pin G1P0 analog switch state */
+#define TSI_ASW_G1P1            BIT(5)                  /*!< pin G1P1 analog switch state */
+#define TSI_ASW_G1P2            BIT(6)                  /*!< pin G1P2 analog switch state */
+#define TSI_ASW_G1P3            BIT(7)                  /*!< pin G1P3 analog switch state */
+#define TSI_ASW_G2P0            BIT(8)                  /*!< pin G2P0 analog switch state */
+#define TSI_ASW_G2P1            BIT(9)                  /*!< pin G2P1 analog switch state */
+#define TSI_ASW_G2P2            BIT(10)                 /*!< pin G2P2 analog switch state */
+#define TSI_ASW_G2P3            BIT(11)                 /*!< pin G2P3 analog switch state */
+#define TSI_ASW_G3P0            BIT(12)                 /*!< pin G3P0 analog switch state */
+#define TSI_ASW_G3P1            BIT(13)                 /*!< pin G3P1 analog switch state */
+#define TSI_ASW_G3P2            BIT(14)                 /*!< pin G3P2 analog switch state */
+#define TSI_ASW_G3P3            BIT(15)                 /*!< pin G3P3 analog switch state */
+#define TSI_ASW_G4P0            BIT(16)                 /*!< pin G4P0 analog switch state */
+#define TSI_ASW_G4P1            BIT(17)                 /*!< pin G4P1 analog switch state */
+#define TSI_ASW_G4P2            BIT(18)                 /*!< pin G4P2 analog switch state */
+#define TSI_ASW_G4P3            BIT(19)                 /*!< pin G4P3 analog switch state */
+#define TSI_ASW_G5P0            BIT(20)                 /*!< pin G5P0 analog switch state */
+#define TSI_ASW_G5P1            BIT(21)                 /*!< pin G5P1 analog switch state */
+#define TSI_ASW_G5P2            BIT(22)                 /*!< pin G5P2 analog switch state */
+#define TSI_ASW_G5P3            BIT(23)                 /*!< pin G5P3 analog switch state */
+
+/* TSI_SAMPCFG */
+#define TSI_SAMPCFG_G0P0        BIT(0)                  /*!< pin G0P0 sample pin mode */
+#define TSI_SAMPCFG_G0P1        BIT(1)                  /*!< pin G0P1 sample pin mode */
+#define TSI_SAMPCFG_G0P2        BIT(2)                  /*!< pin G0P2 sample pin mode */
+#define TSI_SAMPCFG_G0P3        BIT(3)                  /*!< pin G0P3 sample pin mode */
+#define TSI_SAMPCFG_G1P0        BIT(4)                  /*!< pin G1P0 sample pin mode */
+#define TSI_SAMPCFG_G1P1        BIT(5)                  /*!< pin G1P1 sample pin mode */
+#define TSI_SAMPCFG_G1P2        BIT(6)                  /*!< pin G1P2 sample pin mode */
+#define TSI_SAMPCFG_G1P3        BIT(7)                  /*!< pin G1P3 sample pin mode */
+#define TSI_SAMPCFG_G2P0        BIT(8)                  /*!< pin G2P0 sample pin mode */
+#define TSI_SAMPCFG_G2P1        BIT(9)                  /*!< pin G2P1 sample pin mode */
+#define TSI_SAMPCFG_G2P2        BIT(10)                 /*!< pin G2P2 sample pin mode */
+#define TSI_SAMPCFG_G2P3        BIT(11)                 /*!< pin G2P3 sample pin mode */
+#define TSI_SAMPCFG_G3P0        BIT(12)                 /*!< pin G3P0 sample pin mode */
+#define TSI_SAMPCFG_G3P1        BIT(13)                 /*!< pin G3P1 sample pin mode */
+#define TSI_SAMPCFG_G3P2        BIT(14)                 /*!< pin G3P2 sample pin mode */
+#define TSI_SAMPCFG_G3P3        BIT(15)                 /*!< pin G3P3 sample pin mode */
+#define TSI_SAMPCFG_G4P0        BIT(16)                 /*!< pin G4P0 sample pin mode */
+#define TSI_SAMPCFG_G4P1        BIT(17)                 /*!< pin G4P1 sample pin mode */
+#define TSI_SAMPCFG_G4P2        BIT(18)                 /*!< pin G4P2 sample pin mode */
+#define TSI_SAMPCFG_G4P3        BIT(19)                 /*!< pin G4P3 sample pin mode */
+#define TSI_SAMPCFG_G5P0        BIT(20)                 /*!< pin G5P0 sample pin mode */
+#define TSI_SAMPCFG_G5P1        BIT(21)                 /*!< pin G5P1 sample pin mode */
+#define TSI_SAMPCFG_G5P2        BIT(22)                 /*!< pin G5P2 sample pin mode */
+#define TSI_SAMPCFG_G5P3        BIT(23)                 /*!< pin G5P3 sample pin mode */
+
+/* TSI_CHCFG */
+#define TSI_CHCFG_G0P0          BIT(0)                  /*!< pin G0P0 channel pin mode */
+#define TSI_CHCFG_G0P1          BIT(1)                  /*!< pin G0P1 channel pin mode */
+#define TSI_CHCFG_G0P2          BIT(2)                  /*!< pin G0P2 channel pin mode */
+#define TSI_CHCFG_G0P3          BIT(3)                  /*!< pin G0P3 channel pin mode */
+#define TSI_CHCFG_G1P0          BIT(4)                  /*!< pin G1P0 channel pin mode */
+#define TSI_CHCFG_G1P1          BIT(5)                  /*!< pin G1P1 channel pin mode */
+#define TSI_CHCFG_G1P2          BIT(6)                  /*!< pin G1P2 channel pin mode */
+#define TSI_CHCFG_G1P3          BIT(7)                  /*!< pin G1P3 channel pin mode */
+#define TSI_CHCFG_G2P0          BIT(8)                  /*!< pin G2P0 channel pin mode */
+#define TSI_CHCFG_G2P1          BIT(9)                  /*!< pin G2P1 channel pin mode */
+#define TSI_CHCFG_G2P2          BIT(10)                 /*!< pin G2P2 channel pin mode */
+#define TSI_CHCFG_G2P3          BIT(11)                 /*!< pin G2P3 channel pin mode */
+#define TSI_CHCFG_G3P0          BIT(12)                 /*!< pin G3P0 channel pin mode */
+#define TSI_CHCFG_G3P1          BIT(13)                 /*!< pin G3P1 channel pin mode */
+#define TSI_CHCFG_G3P2          BIT(14)                 /*!< pin G3P2 channel pin mode */
+#define TSI_CHCFG_G3P3          BIT(15)                 /*!< pin G3P3 channel pin mode */
+#define TSI_CHCFG_G4P0          BIT(16)                 /*!< pin G4P0 channel pin mode */
+#define TSI_CHCFG_G4P1          BIT(17)                 /*!< pin G4P1 channel pin mode */
+#define TSI_CHCFG_G4P2          BIT(18)                 /*!< pin G4P2 channel pin mode */
+#define TSI_CHCFG_G4P3          BIT(19)                 /*!< pin G4P3 channel pin mode */
+#define TSI_CHCFG_G5P0          BIT(20)                 /*!< pin G5P0 channel pin mode */
+#define TSI_CHCFG_G5P1          BIT(21)                 /*!< pin G5P1 channel pin mode */
+#define TSI_CHCFG_G5P2          BIT(22)                 /*!< pin G5P2 channel pin mode */
+#define TSI_CHCFG_G5P3          BIT(23)                 /*!< pin G5P3 channel pin mode */
+
+/* TSI_GCTL */
+#define TSI_GCTL_GE0            BIT(0)                  /*!< group0 enable */
+#define TSI_GCTL_GE1            BIT(1)                  /*!< group1 enable */
+#define TSI_GCTL_GE2            BIT(2)                  /*!< group2 enable */
+#define TSI_GCTL_GE3            BIT(3)                  /*!< group3 enable */
+#define TSI_GCTL_GE4            BIT(4)                  /*!< group4 enable */
+#define TSI_GCTL_GE5            BIT(5)                  /*!< group5 enable */
+#define TSI_GCTL_GC0            BIT(16)                 /*!< group0 complete */
+#define TSI_GCTL_GC1            BIT(17)                 /*!< group1 complete */
+#define TSI_GCTL_GC2            BIT(18)                 /*!< group2 complete */
+#define TSI_GCTL_GC3            BIT(19)                 /*!< group3 complete */
+#define TSI_GCTL_GC4            BIT(20)                 /*!< group4 complete */
+#define TSI_GCTL_GC5            BIT(21)                 /*!< group5 complete */
+
+/* TSI_CTL1 */
+#define TSI_CTL1_CTCDIV         BIT(24)                 /*!< CTCLK clock division factor */
+#define TSI_CTL1_ECDIV          BITS(28,29)             /*!< ECCLK clock division factor */
+
+/* constants definitions */
+/* TSI interrupt enable bit */
+#define TSI_INT_CCTCF           TSI_INTEN_CTCFIE        /*!< charge transfer complete flag interrupt enable */
+#define TSI_INT_MNERR           TSI_INTEN_MNERRIE       /*!< max cycle number error interrupt enable */
+
+/* I2C interrupt flags */
+#define TSI_INT_FLAG_CTCF       TSI_INTF_CTCF           /*!< charge transfer complete flag */
+#define TSI_INT_FLAG_MNERR      TSI_INTF_MNERR          /*!< max cycle number error */
+
+/* I2C flags */
+#define TSI_FLAG_CTCF           TSI_INTF_CTCF           /*!< charge transfer complete flag */
+#define TSI_FLAG_MNERR          TSI_INTF_MNERR          /*!< max cycle number error */
+
+/* CTCLK clock division factor */
+#define TSI_CTCDIV_DIV1         ((uint32_t)0x00000000U) /*!< fCTCLK = fHCLK */
+#define TSI_CTCDIV_DIV2         ((uint32_t)0x00000001U) /*!< fCTCLK = fHCLK/2 */
+#define TSI_CTCDIV_DIV4         ((uint32_t)0x00000002U) /*!< fCTCLK = fHCLK/4 */
+#define TSI_CTCDIV_DIV8         ((uint32_t)0x00000003U) /*!< fCTCLK = fHCLK/8 */
+#define TSI_CTCDIV_DIV16        ((uint32_t)0x00000004U) /*!< fCTCLK = fHCLK/16 */
+#define TSI_CTCDIV_DIV32        ((uint32_t)0x00000005U) /*!< fCTCLK = fHCLK/32 */
+#define TSI_CTCDIV_DIV64        ((uint32_t)0x00000006U) /*!< fCTCLK = fHCLK/64 */
+#define TSI_CTCDIV_DIV128       ((uint32_t)0x00000007U) /*!< fCTCLK = fHCLK/128 */
+#define TSI_CTCDIV_DIV256       ((uint32_t)0x00000008U) /*!< fCTCLK = fHCLK/256 */
+#define TSI_CTCDIV_DIV512       ((uint32_t)0x00000009U) /*!< fCTCLK = fHCLK/512 */
+#define TSI_CTCDIV_DIV1024      ((uint32_t)0x0000000AU) /*!< fCTCLK = fHCLK/1024 */
+#define TSI_CTCDIV_DIV2048      ((uint32_t)0x0000000BU) /*!< fCTCLK = fHCLK/2048 */
+#define TSI_CTCDIV_DIV4096      ((uint32_t)0x0000000CU) /*!< fCTCLK = fHCLK/4096 */
+#define TSI_CTCDIV_DIV8192      ((uint32_t)0x0000000DU) /*!< fCTCLK = fHCLK/8192 */
+#define TSI_CTCDIV_DIV16384     ((uint32_t)0x0000000EU) /*!< fCTCLK = fHCLK/16384 */
+#define TSI_CTCDIV_DIV32768     ((uint32_t)0x0000000FU) /*!< fCTCLK = fHCLK/32768 */
+
+/* charge transfer state duration Time */
+#define CTL_CTDT(regval)        (BITS(24,27) & ((uint32_t)(regval) << 24U))
+#define TSI_TRANSFER_1CTCLK     CTL_CTDT(0)             /*!< the duration time of transfer state is 1 CTCLK */
+#define TSI_TRANSFER_2CTCLK     CTL_CTDT(1)             /*!< the duration time of transfer state is 2 CTCLK */
+#define TSI_TRANSFER_3CTCLK     CTL_CTDT(2)             /*!< the duration time of transfer state is 3 CTCLK */
+#define TSI_TRANSFER_4CTCLK     CTL_CTDT(3)             /*!< the duration time of transfer state is 4 CTCLK */
+#define TSI_TRANSFER_5CTCLK     CTL_CTDT(4)             /*!< the duration time of transfer state is 5 CTCLK */
+#define TSI_TRANSFER_6CTCLK     CTL_CTDT(5)             /*!< the duration time of transfer state is 6 CTCLK */
+#define TSI_TRANSFER_7CTCLK     CTL_CTDT(6)             /*!< the duration time of transfer state is 7 CTCLK */
+#define TSI_TRANSFER_8CTCLK     CTL_CTDT(7)             /*!< the duration time of transfer state is 8 CTCLK */
+#define TSI_TRANSFER_9CTCLK     CTL_CTDT(8)             /*!< the duration time of transfer state is 9 CTCLK */
+#define TSI_TRANSFER_10CTCLK    CTL_CTDT(9)             /*!< the duration time of transfer state is 10 CTCLK */
+#define TSI_TRANSFER_11CTCLK    CTL_CTDT(10)            /*!< the duration time of transfer state is 11 CTCLK */
+#define TSI_TRANSFER_12CTCLK    CTL_CTDT(11)            /*!< the duration time of transfer state is 12 CTCLK */
+#define TSI_TRANSFER_13CTCLK    CTL_CTDT(12)            /*!< the duration time of transfer state is 13 CTCLK */
+#define TSI_TRANSFER_14CTCLK    CTL_CTDT(13)            /*!< the duration time of transfer state is 14 CTCLK */
+#define TSI_TRANSFER_15CTCLK    CTL_CTDT(14)            /*!< the duration time of transfer state is 15 CTCLK */
+#define TSI_TRANSFER_16CTCLK    CTL_CTDT(15)            /*!< the duration time of transfer state is 16 CTCLK */
+
+/* charge state duration time */
+#define CTL_CDT(regval)         (BITS(28,31) & ((uint32_t)(regval) << 28U))
+#define TSI_CHARGE_1CTCLK       CTL_CDT(0)              /*!< the duration time of charge state is 1 CTCLK */
+#define TSI_CHARGE_2CTCLK       CTL_CDT(1)              /*!< the duration time of charge state is 2 CTCLK */
+#define TSI_CHARGE_3CTCLK       CTL_CDT(2)              /*!< the duration time of charge state is 3 CTCLK */
+#define TSI_CHARGE_4CTCLK       CTL_CDT(3)              /*!< the duration time of charge state is 4 CTCLK */
+#define TSI_CHARGE_5CTCLK       CTL_CDT(4)              /*!< the duration time of charge state is 5 CTCLK */
+#define TSI_CHARGE_6CTCLK       CTL_CDT(5)              /*!< the duration time of charge state is 6 CTCLK */
+#define TSI_CHARGE_7CTCLK       CTL_CDT(6)              /*!< the duration time of charge state is 7 CTCLK */
+#define TSI_CHARGE_8CTCLK       CTL_CDT(7)              /*!< the duration time of charge state is 8 CTCLK */
+#define TSI_CHARGE_9CTCLK       CTL_CDT(8)              /*!< the duration time of charge state is 9 CTCLK */
+#define TSI_CHARGE_10CTCLK      CTL_CDT(9)              /*!< the duration time of charge state is 10 CTCLK */
+#define TSI_CHARGE_11CTCLK      CTL_CDT(10)             /*!< the duration time of charge state is 11 CTCLK */
+#define TSI_CHARGE_12CTCLK      CTL_CDT(11)             /*!< the duration time of charge state is 12 CTCLK */
+#define TSI_CHARGE_13CTCLK      CTL_CDT(12)             /*!< the duration time of charge state is 13 CTCLK */
+#define TSI_CHARGE_14CTCLK      CTL_CDT(13)             /*!< the duration time of charge state is 14 CTCLK */
+#define TSI_CHARGE_15CTCLK      CTL_CDT(14)             /*!< the duration time of charge state is 15 CTCLK */
+#define TSI_CHARGE_16CTCLK      CTL_CDT(15)             /*!< the duration time of charge state is 16 CTCLK */
+
+/* max cycle number of a sequence */
+#define CTL_MCN(regval)         (BITS(5,7) & ((uint32_t)(regval) << 5U))
+#define TSI_MAXNUM255           CTL_MCN(0)              /*!< the max cycle number of a sequence is 255 */
+#define TSI_MAXNUM511           CTL_MCN(1)              /*!< the max cycle number of a sequence is 511 */
+#define TSI_MAXNUM1023          CTL_MCN(2)              /*!< the max cycle number of a sequence is 1023 */
+#define TSI_MAXNUM2047          CTL_MCN(3)              /*!< the max cycle number of a sequence is 2047 */
+#define TSI_MAXNUM4095          CTL_MCN(4)              /*!< the max cycle number of a sequence is 4095 */
+#define TSI_MAXNUM8191          CTL_MCN(5)              /*!< the max cycle number of a sequence is 8191 */
+#define TSI_MAXNUM16383         CTL_MCN(6)              /*!< the max cycle number of a sequence is 16383 */
+
+/* ECCLK clock division factor */
+#define TSI_EXTEND_DIV1         ((uint32_t)0x00000000U) /*!< fECCLK = fHCLK */
+#define TSI_EXTEND_DIV2         ((uint32_t)0x00000001U) /*!< fECCLK = fHCLK/2 */
+#define TSI_EXTEND_DIV3         ((uint32_t)0x00000002U) /*!< fECCLK = fHCLK/3 */
+#define TSI_EXTEND_DIV4         ((uint32_t)0x00000003U) /*!< fECCLK = fHCLK/4 */
+#define TSI_EXTEND_DIV5         ((uint32_t)0x00000004U) /*!< fECCLK = fHCLK/5 */
+#define TSI_EXTEND_DIV6         ((uint32_t)0x00000005U) /*!< fECCLK = fHCLK/6 */
+#define TSI_EXTEND_DIV7         ((uint32_t)0x00000006U) /*!< fECCLK = fHCLK/7 */
+#define TSI_EXTEND_DIV8         ((uint32_t)0x00000007U) /*!< fECCLK = fHCLK/8 */
+
+/* extend charge state maximum duration time */
+#define TSI_EXTENDMAX(regval)   (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */
+
+/* hardware trigger mode */
+#define TSI_FALLING_TRIGGER     0x00U                   /*!< falling edge trigger TSI charge transfer sequence */
+#define TSI_RISING_TRIGGER      0x01U                   /*!< rising edge trigger TSI charge transfer sequence */
+
+/* pin mode */
+#define TSI_OUTPUT_LOW          0x00U                   /*!< TSI pin will output low when IDLE */
+#define TSI_INPUT_FLOATING      0x01U                   /*!< TSI pin will keep input_floating when IDLE */
+
+/* function declarations */
+/* reset TSI peripheral */
+void tsi_deinit(void);
+/* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */
+void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number);
+/* enable TSI module */
+void tsi_enable(void);
+/* disable TSI module */
+void tsi_disable(void);
+/* enable sample pin */
+void tsi_sample_pin_enable(uint32_t sample);
+/* disable sample pin */
+void tsi_sample_pin_disable(uint32_t sample);
+/* enable channel pin */
+void tsi_channel_pin_enable(uint32_t channel);
+/* disable channel pin */
+void tsi_channel_pin_disable(uint32_t channel);
+
+/* configure TSI triggering by software */
+void tsi_sofeware_mode_config(void);
+/* start a charge-transfer sequence when TSI is in software trigger mode */
+void tsi_software_start(void);
+/* stop a charge-transfer sequence when TSI is in software trigger mode */
+void tsi_software_stop(void);
+/* configure TSI triggering by hardware */
+void tsi_hardware_mode_config(uint8_t trigger_edge);
+/* configure TSI pin mode when charge-transfer sequence is IDLE */
+void tsi_pin_mode_config(uint8_t pin_mode);
+/* configure extend charge state */
+void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration);
+
+/* configure charge plus and transfer plus */
+void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration);
+/* configure the max cycle number of a charge-transfer sequence */
+void tsi_max_number_config(uint32_t max_number);
+/* switch on hysteresis pin */
+void tsi_hysteresis_on(uint32_t group_pin);
+/* switch off hysteresis pin */
+void tsi_hysteresis_off(uint32_t group_pin);
+/* switch on analog pin */
+void tsi_analog_on(uint32_t group_pin);
+/* switch off analog pin */
+void tsi_analog_off(uint32_t group_pin);
+
+/* enable TSI interrupt */
+void tsi_interrupt_enable(uint32_t source);
+/* disable TSI interrupt */
+void tsi_interrupt_disable(uint32_t source);
+/* clear interrupt flag */
+void tsi_interrupt_flag_clear(uint32_t flag);
+/* get TSI interrupt flag */
+FlagStatus tsi_interrupt_flag_get(uint32_t flag);
+
+/* clear flag */
+void tsi_flag_clear(uint32_t flag);
+/* get flag */
+FlagStatus tsi_flag_get(uint32_t flag);
+
+/* enbale group */
+void tsi_group_enable(uint32_t group);
+/* disbale group */
+void tsi_group_disable(uint32_t group);
+/* get group complete status */
+FlagStatus tsi_group_status_get(uint32_t group);
+/* get the cycle number for group0 as soon as a charge-transfer sequence completes */
+uint16_t tsi_group0_cycle_get(void);
+/* get the cycle number for group1 as soon as a charge-transfer sequence completes */
+uint16_t tsi_group1_cycle_get(void);
+/* get the cycle number for group2 as soon as a charge-transfer sequence completes */
+uint16_t tsi_group2_cycle_get(void);
+/* get the cycle number for group3 as soon as a charge-transfer sequence completes */
+uint16_t tsi_group3_cycle_get(void);
+/* get the cycle number for group4 as soon as a charge-transfer sequence completes */
+uint16_t tsi_group4_cycle_get(void);
+/* get the cycle number for group5 as soon as a charge-transfer sequence completes */
+uint16_t tsi_group5_cycle_get(void);
+
+#endif /* GD32F3X0_TSI_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_usart.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_usart.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_usart.h
+    \file  gd32f3x0_usart.h
     \brief definitions for the USART
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,177 +33,189 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_USART_H
-#define GD32F1X0_USART_H
+#ifndef GD32F3X0_USART_H
+#define GD32F3X0_USART_H
 
-#include "gd32f1x0.h"
+#include "gd32f3x0.h"
 
 /* USARTx(x=0,1) definitions */
 #define USART0                        (USART_BASE + 0x0000F400U)
 #define USART1                        USART_BASE
 
 /* registers definitions */
-#define USART_CTL0(usartx)            REG32((usartx) + 0x00000000U)        /*!< USART control register 0 */
-#define USART_CTL1(usartx)            REG32((usartx) + 0x00000004U)        /*!< USART control register 1 */
-#define USART_CTL2(usartx)            REG32((usartx) + 0x00000008U)        /*!< USART control register 2 */
-#define USART_BAUD(usartx)            REG32((usartx) + 0x0000000CU)        /*!< USART baud rate register */
-#define USART_GP(usartx)              REG32((usartx) + 0x00000010U)        /*!< USART guard time and prescaler register */
-#define USART_RT(usartx)              REG32((usartx) + 0x00000014U)        /*!< USART receiver timeout register */
-#define USART_CMD(usartx)             REG32((usartx) + 0x00000018U)        /*!< USART command register */
-#define USART_STAT(usartx)            REG32((usartx) + 0x0000001CU)        /*!< USART status register */
-#define USART_INTC(usartx)            REG32((usartx) + 0x00000020U)        /*!< USART status clear register */
-#define USART_RDATA(usartx)           REG32((usartx) + 0x00000024U)        /*!< USART receive data register */
-#define USART_TDATA(usartx)           REG32((usartx) + 0x00000028U)        /*!< USART transmit data register */
+#define USART_CTL0(usartx)            REG32((usartx) + 0x00000000U)  /*!< USART control register 0 */
+#define USART_CTL1(usartx)            REG32((usartx) + 0x00000004U)  /*!< USART control register 1 */
+#define USART_CTL2(usartx)            REG32((usartx) + 0x00000008U)  /*!< USART control register 2 */
+#define USART_BAUD(usartx)            REG32((usartx) + 0x0000000CU)  /*!< USART baud rate register */
+#define USART_GP(usartx)              REG32((usartx) + 0x00000010U)  /*!< USART guard time and prescaler register */
+#define USART_RT(usartx)              REG32((usartx) + 0x00000014U)  /*!< USART receiver timeout register */
+#define USART_CMD(usartx)             REG32((usartx) + 0x00000018U)  /*!< USART command register */
+#define USART_STAT(usartx)            REG32((usartx) + 0x0000001CU)  /*!< USART status register */
+#define USART_INTC(usartx)            REG32((usartx) + 0x00000020U)  /*!< USART status clear register */
+#define USART_RDATA(usartx)           REG32((usartx) + 0x00000024U)  /*!< USART receive data register */
+#define USART_TDATA(usartx)           REG32((usartx) + 0x00000028U)  /*!< USART transmit data register */
+#define USART_RFCS(usartx)            REG32((usartx) + 0x000000D0U)  /*!< USART receive FIFO control and status register */
 
 /* bits definitions */
 /* USARTx_CTL0 */
-#define USART_CTL0_UEN                BIT(0)       /*!< USART enable */
-#define USART_CTL0_UESM               BIT(1)       /*!< USART enable in deep-sleep mode */
-#define USART_CTL0_REN                BIT(2)       /*!< receiver enable */
-#define USART_CTL0_TEN                BIT(3)       /*!< transmitter enable */
-#define USART_CTL0_IDLEIE             BIT(4)       /*!< idle line detected interrupt enable */
-#define USART_CTL0_RBNEIE             BIT(5)       /*!< read data buffer not empty interrupt and overrun error interrupt enable */
-#define USART_CTL0_TCIE               BIT(6)       /*!< transmission complete interrupt enable */
-#define USART_CTL0_TBEIE              BIT(7)       /*!< transmitter register empty interrupt enable */
-#define USART_CTL0_PERRIE             BIT(8)       /*!< parity error interrupt enable */
-#define USART_CTL0_PM                 BIT(9)       /*!< parity mode */
-#define USART_CTL0_PCEN               BIT(10)      /*!< parity control enable */
-#define USART_CTL0_WM                 BIT(11)      /*!< wakeup method in mute mode */
-#define USART_CTL0_WL                 BIT(12)      /*!< word length */
-#define USART_CTL0_MEN                BIT(13)      /*!< mute mode enable */
-#define USART_CTL0_AMIE               BIT(14)      /*!< address match interrupt enable */
-#define USART_CTL0_OVSMOD             BIT(15)      /*!< oversample mode */
-#define USART_CTL0_DED                BITS(16,20)  /*!< driver enable deassertion time */
-#define USART_CTL0_DEA                BITS(21,25)  /*!< driver enable assertion time */
-#define USART_CTL0_RTIE               BIT(26)      /*!< receiver timeout interrupt enable */
-#define USART_CTL0_EBIE               BIT(27)      /*!< end of block interrupt enable */
+#define USART_CTL0_UEN                BIT(0)                         /*!< USART enable */
+#define USART_CTL0_UESM               BIT(1)                         /*!< USART enable in deep-sleep mode */
+#define USART_CTL0_REN                BIT(2)                         /*!< receiver enable */
+#define USART_CTL0_TEN                BIT(3)                         /*!< transmitter enable */
+#define USART_CTL0_IDLEIE             BIT(4)                         /*!< idle line detected interrupt enable */
+#define USART_CTL0_RBNEIE             BIT(5)                         /*!< read data buffer not empty interrupt and overrun error interrupt enable */
+#define USART_CTL0_TCIE               BIT(6)                         /*!< transmission complete interrupt enable */
+#define USART_CTL0_TBEIE              BIT(7)                         /*!< transmitter register empty interrupt enable */
+#define USART_CTL0_PERRIE             BIT(8)                         /*!< parity error interrupt enable */
+#define USART_CTL0_PM                 BIT(9)                         /*!< parity mode */
+#define USART_CTL0_PCEN               BIT(10)                        /*!< parity control enable */
+#define USART_CTL0_WM                 BIT(11)                        /*!< wakeup method in mute mode */
+#define USART_CTL0_WL                 BIT(12)                        /*!< word length */
+#define USART_CTL0_MEN                BIT(13)                        /*!< mute mode enable */
+#define USART_CTL0_AMIE               BIT(14)                        /*!< address match interrupt enable */
+#define USART_CTL0_OVSMOD             BIT(15)                        /*!< oversample mode */
+#define USART_CTL0_DED                BITS(16,20)                    /*!< driver enable deassertion time */
+#define USART_CTL0_DEA                BITS(21,25)                    /*!< driver enable assertion time */
+#define USART_CTL0_RTIE               BIT(26)                        /*!< receiver timeout interrupt enable */
+#define USART_CTL0_EBIE               BIT(27)                        /*!< end of block interrupt enable */
 
 /* USARTx_CTL1 */
-#define USART_CTL1_ADDM               BIT(4)       /*!< address detection mode */
-#define USART_CTL1_LBLEN              BIT(5)       /*!< LIN break frame length */
-#define USART_CTL1_LBDIE              BIT(6)       /*!< LIN break detection interrupt enable */
-#define USART_CTL1_CLEN               BIT(8)       /*!< last bit clock pulse */
-#define USART_CTL1_CPH                BIT(9)       /*!< clock phase */
-#define USART_CTL1_CPL                BIT(10)      /*!< clock polarity */
-#define USART_CTL1_CKEN               BIT(11)      /*!< ck pin enable */
-#define USART_CTL1_STB                BITS(12,13)  /*!< stop bits length */
-#define USART_CTL1_LMEN               BIT(14)      /*!< LIN mode enable */
-#define USART_CTL1_STRP               BIT(15)      /*!< swap TX/RX pins */
-#define USART_CTL1_RINV               BIT(16)      /*!< RX pin level inversion */
-#define USART_CTL1_TINV               BIT(17)      /*!< TX pin level inversion */
-#define USART_CTL1_DINV               BIT(18)      /*!< data bit level inversion */
-#define USART_CTL1_MSBF               BIT(19)      /*!< most significant bit first */
-#define USART_CTL1_ABDEN              BIT(20)      /*!< auto baud rate enable */
-#define USART_CTL1_ABDM               BITS(21,22)  /*!< auto baud rate mode */
-#define USART_CTL1_RTEN               BIT(23)      /*!< receiver timeout enable */
-#define USART_CTL1_ADDR               BITS(24,31)  /*!< address of the USART terminal */
-
-/* USARTx_CTL2  */
-#define USART_CTL2_ERRIE              BIT(0)       /*!< error interrupt enable in multibuffer communication */
-#define USART_CTL2_IREN               BIT(1)       /*!< IrDA mode enable */
-#define USART_CTL2_IRLP               BIT(2)       /*!< IrDA low-power */
-#define USART_CTL2_HDEN               BIT(3)       /*!< half-duplex enable */
-#define USART_CTL2_NKEN               BIT(4)       /*!< NACK enable in smartcard mode */
-#define USART_CTL2_SCEN               BIT(5)       /*!< smartcard mode enable */
-#define USART_CTL2_DENR               BIT(6)       /*!< DMA enable for reception */
-#define USART_CTL2_DENT               BIT(7)       /*!< DMA enable for transmission */
-#define USART_CTL2_RTSEN              BIT(8)       /*!< RTS enable */
-#define USART_CTL2_CTSEN              BIT(9)       /*!< CTS enable */
-#define USART_CTL2_CTSIE              BIT(10)      /*!< CTS interrupt enable */
-#define USART_CTL2_OSB                BIT(11)      /*!< one sample bit mode */
-#define USART_CTL2_OVRD               BIT(12)      /*!< overrun disable */
-#define USART_CTL2_DDRE               BIT(13)      /*!< disable DMA on reception error */
-#define USART_CTL2_DEM                BIT(14)      /*!< driver enable mode */
-#define USART_CTL2_DEP                BIT(15)      /*!< driver enable polarity mode */
-#define USART_CTL2_SCRTNUM            BITS(17,19)  /*!< smartcard auto-retry number */
-#define USART_CTL2_WUM                BITS(20,21)  /*!< wakeup mode from deep-sleep mode */
-#define USART_CTL2_WUIE               BIT(22)      /*!< wakeup from deep-sleep mode interrupt enable */
+#define USART_CTL1_ADDM               BIT(4)                         /*!< address detection mode */
+#define USART_CTL1_LBLEN              BIT(5)                         /*!< LIN break frame length */
+#define USART_CTL1_LBDIE              BIT(6)                         /*!< LIN break detection interrupt enable */
+#define USART_CTL1_CLEN               BIT(8)                         /*!< last bit clock pulse */
+#define USART_CTL1_CPH                BIT(9)                         /*!< clock phase */
+#define USART_CTL1_CPL                BIT(10)                        /*!< clock polarity */
+#define USART_CTL1_CKEN               BIT(11)                        /*!< ck pin enable */
+#define USART_CTL1_STB                BITS(12,13)                    /*!< stop bits length */
+#define USART_CTL1_LMEN               BIT(14)                        /*!< LIN mode enable */
+#define USART_CTL1_STRP               BIT(15)                        /*!< swap TX/RX pins */
+#define USART_CTL1_RINV               BIT(16)                        /*!< RX pin level inversion */
+#define USART_CTL1_TINV               BIT(17)                        /*!< TX pin level inversion */
+#define USART_CTL1_DINV               BIT(18)                        /*!< data bit level inversion */
+#define USART_CTL1_MSBF               BIT(19)                        /*!< most significant bit first */
+#define USART_CTL1_ABDEN              BIT(20)                        /*!< auto baud rate enable */
+#define USART_CTL1_ABDM               BITS(21,22)                    /*!< auto baud rate mode */
+#define USART_CTL1_RTEN               BIT(23)                        /*!< receiver timeout enable */
+#define USART_CTL1_ADDR               BITS(24,31)                    /*!< address of the USART terminal */
+
+/* USARTx_CTL2 */
+#define USART_CTL2_ERRIE              BIT(0)                         /*!< error interrupt enable in multibuffer communication */
+#define USART_CTL2_IREN               BIT(1)                         /*!< IrDA mode enable */
+#define USART_CTL2_IRLP               BIT(2)                         /*!< IrDA low-power */
+#define USART_CTL2_HDEN               BIT(3)                         /*!< half-duplex enable */
+#define USART_CTL2_NKEN               BIT(4)                         /*!< NACK enable in smartcard mode */
+#define USART_CTL2_SCEN               BIT(5)                         /*!< smartcard mode enable */
+#define USART_CTL2_DENR               BIT(6)                         /*!< DMA enable for reception */
+#define USART_CTL2_DENT               BIT(7)                         /*!< DMA enable for transmission */
+#define USART_CTL2_RTSEN              BIT(8)                         /*!< RTS enable */
+#define USART_CTL2_CTSEN              BIT(9)                         /*!< CTS enable */
+#define USART_CTL2_CTSIE              BIT(10)                        /*!< CTS interrupt enable */
+#define USART_CTL2_OSB                BIT(11)                        /*!< one sample bit mode */
+#define USART_CTL2_OVRD               BIT(12)                        /*!< overrun disable */
+#define USART_CTL2_DDRE               BIT(13)                        /*!< disable DMA on reception error */
+#define USART_CTL2_DEM                BIT(14)                        /*!< driver enable mode */
+#define USART_CTL2_DEP                BIT(15)                        /*!< driver enable polarity mode */
+#define USART_CTL2_SCRTNUM            BITS(17,19)                    /*!< smartcard auto-retry number */
+#define USART_CTL2_WUM                BITS(20,21)                    /*!< wakeup mode from deep-sleep mode */
+#define USART_CTL2_WUIE               BIT(22)                        /*!< wakeup from deep-sleep mode interrupt enable */
 
 /* USARTx_BAUD */
-#define USART_BAUD_FRADIV             BITS(0,3)    /*!< fraction of baud-rate divider */
-#define USART_BAUD_INTDIV             BITS(4,15)   /*!< integer of baud-rate divider */
+#define USART_BAUD_FRADIV             BITS(0,3)                      /*!< fraction of baud-rate divider */
+#define USART_BAUD_INTDIV             BITS(4,15)                     /*!< integer of baud-rate divider */
 
 /* USARTx_GP */
-#define USART_GP_PSC                  BITS(0,7)    /*!< prescaler value for dividing the system clock */
-#define USART_GP_GUAT                 BITS(8,15)   /*!< guard time value in smartcard mode */
+#define USART_GP_PSC                  BITS(0,7)                      /*!< prescaler value for dividing the system clock */
+#define USART_GP_GUAT                 BITS(8,15)                     /*!< guard time value in smartcard mode */
 
 /* USARTx_RT */
-#define USART_RT_RT                   BITS(0,23)   /*!< receiver timeout threshold */
-#define USART_RT_BL                   BITS(24,31)  /*!< block length */
+#define USART_RT_RT                   BITS(0,23)                     /*!< receiver timeout threshold */
+#define USART_RT_BL                   BITS(24,31)                    /*!< block length */
 
 /* USARTx_CMD */
-#define USART_CMD_ABDCMD              BIT(0)       /*!< auto baudrate detection command */
-#define USART_CMD_SBKCMD              BIT(1)       /*!< send break command */
-#define USART_CMD_MMCMD               BIT(2)       /*!< mute mode command */
-#define USART_CMD_RXFCMD              BIT(3)       /*!< receive data flush command */
-#define USART_CMD_TXFCMD              BIT(4)       /*!< transmit data flush request */
+#define USART_CMD_ABDCMD              BIT(0)                         /*!< auto baudrate detection command */
+#define USART_CMD_SBKCMD              BIT(1)                         /*!< send break command */
+#define USART_CMD_MMCMD               BIT(2)                         /*!< mute mode command */
+#define USART_CMD_RXFCMD              BIT(3)                         /*!< receive data flush command */
+#define USART_CMD_TXFCMD              BIT(4)                         /*!< transmit data flush request */
 
 /* USARTx_STAT */
-#define USART_STAT_PERR               BIT(0)       /*!< parity error flag */
-#define USART_STAT_FERR               BIT(1)       /*!< frame error flag */
-#define USART_STAT_NERR               BIT(2)       /*!< noise error flag */
-#define USART_STAT_ORERR              BIT(3)       /*!< overrun error */
-#define USART_STAT_IDLEF              BIT(4)       /*!< idle line detected flag */
-#define USART_STAT_RBNE               BIT(5)       /*!< read data buffer not empty */
-#define USART_STAT_TC                 BIT(6)       /*!< transmission completed */
-#define USART_STAT_TBE                BIT(7)       /*!< transmit data register empty */
-#define USART_STAT_LBDF               BIT(8)       /*!< LIN break detected flag */
-#define USART_STAT_CTSF               BIT(9)       /*!< CTS change flag */
-#define USART_STAT_CTS                BIT(10)      /*!< CTS level */
-#define USART_STAT_RTF                BIT(11)      /*!< receiver timeout flag */
-#define USART_STAT_EBF                BIT(12)      /*!< end of block flag */
-#define USART_STAT_ABDE               BIT(14)      /*!< auto baudrate detection error */
-#define USART_STAT_ABDF               BIT(15)      /*!< auto baudrate detection flag */
-#define USART_STAT_BSY                BIT(16)      /*!< busy flag */
-#define USART_STAT_AMF                BIT(17)      /*!< address match flag */
-#define USART_STAT_SBF                BIT(18)      /*!< send break flag */
-#define USART_STAT_RWU                BIT(19)      /*!< receiver wakeup from mute mode */
-#define USART_STAT_WUF                BIT(20)      /*!< wakeup from deep-sleep mode flag */
-#define USART_STAT_TEA                BIT(21)      /*!< transmit enable acknowledge flag */
-#define USART_STAT_REA                BIT(22)      /*!< receive enable acknowledge flag */
+#define USART_STAT_PERR               BIT(0)                         /*!< parity error flag */
+#define USART_STAT_FERR               BIT(1)                         /*!< frame error flag */
+#define USART_STAT_NERR               BIT(2)                         /*!< noise error flag */
+#define USART_STAT_ORERR              BIT(3)                         /*!< overrun error */
+#define USART_STAT_IDLEF              BIT(4)                         /*!< idle line detected flag */
+#define USART_STAT_RBNE               BIT(5)                         /*!< read data buffer not empty */
+#define USART_STAT_TC                 BIT(6)                         /*!< transmission completed */
+#define USART_STAT_TBE                BIT(7)                         /*!< transmit data register empty */
+#define USART_STAT_LBDF               BIT(8)                         /*!< LIN break detected flag */
+#define USART_STAT_CTSF               BIT(9)                         /*!< CTS change flag */
+#define USART_STAT_CTS                BIT(10)                        /*!< CTS level */
+#define USART_STAT_RTF                BIT(11)                        /*!< receiver timeout flag */
+#define USART_STAT_EBF                BIT(12)                        /*!< end of block flag */
+#define USART_STAT_ABDE               BIT(14)                        /*!< auto baudrate detection error */
+#define USART_STAT_ABDF               BIT(15)                        /*!< auto baudrate detection flag */
+#define USART_STAT_BSY                BIT(16)                        /*!< busy flag */
+#define USART_STAT_AMF                BIT(17)                        /*!< address match flag */
+#define USART_STAT_SBF                BIT(18)                        /*!< send break flag */
+#define USART_STAT_RWU                BIT(19)                        /*!< receiver wakeup from mute mode */
+#define USART_STAT_WUF                BIT(20)                        /*!< wakeup from deep-sleep mode flag */
+#define USART_STAT_TEA                BIT(21)                        /*!< transmit enable acknowledge flag */
+#define USART_STAT_REA                BIT(22)                        /*!< receive enable acknowledge flag */
 
 /* USARTx_INTC */
-#define USART_INTC_PEC                 BIT(0)      /*!< parity error clear */
-#define USART_INTC_FEC                 BIT(1)      /*!< frame error flag clear */
-#define USART_INTC_NEC                 BIT(2)      /*!< noise detected clear */
-#define USART_INTC_OREC                BIT(3)      /*!< overrun error clear */
-#define USART_INTC_IDLEC               BIT(4)      /*!< idle line detected clear */
-#define USART_INTC_TCC                 BIT(6)      /*!< transmission complete clear */
-#define USART_INTC_LBDC                BIT(8)      /*!< LIN break detected clear */
-#define USART_INTC_CTSC                BIT(9)      /*!< CTS change clear */
-#define USART_INTC_RTC                 BIT(11)     /*!< receiver timeout clear */
-#define USART_INTC_EBC                 BIT(12)     /*!< end of timeout clear */
-#define USART_INTC_AMC                 BIT(17)     /*!< address match clear */
-#define USART_INTC_WUC                 BIT(20)     /*!< wakeup from deep-sleep mode clear */
+#define USART_INTC_PEC                BIT(0)                         /*!< parity error clear */
+#define USART_INTC_FEC                BIT(1)                         /*!< frame error flag clear */
+#define USART_INTC_NEC                BIT(2)                         /*!< noise detected clear */
+#define USART_INTC_OREC               BIT(3)                         /*!< overrun error clear */
+#define USART_INTC_IDLEC              BIT(4)                         /*!< idle line detected clear */
+#define USART_INTC_TCC                BIT(6)                         /*!< transmission complete clear */
+#define USART_INTC_LBDC               BIT(8)                         /*!< LIN break detected clear */
+#define USART_INTC_CTSC               BIT(9)                         /*!< CTS change clear */
+#define USART_INTC_RTC                BIT(11)                        /*!< receiver timeout clear */
+#define USART_INTC_EBC                BIT(12)                        /*!< end of timeout clear */
+#define USART_INTC_AMC                BIT(17)                        /*!< address match clear */
+#define USART_INTC_WUC                BIT(20)                        /*!< wakeup from deep-sleep mode clear */
 
 /* USARTx_RDATA */
-#define USART_RDATA_RDATA             BITS(0,8)    /*!< receive data value */
+#define USART_RDATA_RDATA             BITS(0,8)                      /*!< receive data value */
 
 /* USARTx_TDATA */
-#define USART_TDATA_TDATA             BITS(0,8)    /*!< transmit data value */
+#define USART_TDATA_TDATA             BITS(0,8)                      /*!< transmit data value */
+
+/* USARTx_RFCS */
+#define USART_RFCS_ELNACK             BIT(0)                         /*!< early NACK */
+#define USART_RFCS_RFEN               BIT(8)                         /*!< receive FIFO enable */
+#define USART_RFCS_RFFIE              BIT(9)                         /*!< receive FIFO full interrupt enable */
+#define USART_RFCS_RFE                BIT(10)                        /*!< receive FIFO empty flag */
+#define USART_RFCS_RFF                BIT(11)                        /*!< receive FIFO full flag */
+#define USART_RFCS_RFCNT              BITS(12,14)                    /*!< receive FIFO counter number */
+#define USART_RFCS_RFFINT             BIT(15)                        /*!< receive FIFO full interrupt flag */
 
 /* constants definitions */
+
 /* define the USART bit position and its register index offset */
-#define USART_REGIDX_BIT(regidx, bitpos)     (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
-#define USART_REG_VAL(usartx, offset)        (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
-#define USART_BIT_POS(val)                   ((uint32_t)(val) & 0x1FU)
+#define USART_REGIDX_BIT(regidx, bitpos)    (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define USART_REG_VAL(usartx, offset)       (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
+#define USART_BIT_POS(val)                  ((uint32_t)(val) & 0x0000001FU)
 #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)   (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
                                                               | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
 #define USART_REG_VAL2(usartx, offset)       (REG32((usartx) + ((uint32_t)(offset) >> 22)))
-#define USART_BIT_POS2(val)                  (((uint32_t)(val) & 0x1F0000U) >> 16)
+#define USART_BIT_POS2(val)                  (((uint32_t)(val) & 0x001F0000U) >> 16)
 
 /* register offset */
-#define USART_CTL0_REG_OFFSET              0x00U                           /*!< CTL0 register offset */
-#define USART_CTL1_REG_OFFSET              0x04U                           /*!< CTL1 register offset */
-#define USART_CTL2_REG_OFFSET              0x08U                           /*!< CTL2 register offset */
-#define USART_STAT_REG_OFFSET              0x1CU                           /*!< STAT register offset */
+#define USART_CTL0_REG_OFFSET              (0x00000000U)                   /*!< CTL0 register offset */
+#define USART_CTL1_REG_OFFSET              (0x00000004U)                   /*!< CTL1 register offset */
+#define USART_CTL2_REG_OFFSET              (0x00000008U)                   /*!< CTL2 register offset */
+#define USART_STAT_REG_OFFSET              (0x0000001CU)                   /*!< STAT register offset */
+#define USART_RFCS_REG_OFFSET              (0x000000D0U)                   /*!< RFCS register offset */
 
 /* USART flags */
 typedef enum{
     /* flags in STAT register */
     USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U),         /*!< receive enable acknowledge flag */
     USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U),         /*!< transmit enable acknowledge flag */
-    USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U),          /*!< wakeup from Deep-sleep mode flag */
+    USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U),          /*!< wakeup from deep-sleep mode flag */
     USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U),         /*!< receiver wakeup from mute mode */
     USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U),          /*!< send break flag */
     USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U),          /*!< ADDR match flag */
@@ -226,143 +235,151 @@ typedef enum{
     USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U),         /*!< noise error flag */
     USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U),         /*!< frame error flag */
     USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U),         /*!< parity error flag */
+    /* flags in RFCS register */
+    USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U),         /*!< receive FIFO full flag */
+    USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U),         /*!< receive FIFO empty flag */
 }usart_flag_enum;
 
 /* USART interrupt flags */
 typedef enum
 {
     /* interrupt flags in CTL0 register */
-    USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U),       /*!< end of block interrupt and flag */
-    USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U),       /*!< receiver timeout interrupt and flag */
-    USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U),       /*!< address match interrupt and flag */
-    USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U),       /*!< parity error interrupt and flag */
-    USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U),        /*!< transmitter buffer empty interrupt and flag */
-    USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U),         /*!< transmission complete interrupt and flag */
-    USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U),       /*!< read data buffer not empty interrupt and flag */
-    USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
-    USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U),       /*!< IDLE line detected interrupt and flag */
+    USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U),       /*!< end of block interrupt flag */
+    USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U),       /*!< receiver timeout interrupt flag */
+    USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U),       /*!< address match interrupt flag */
+    USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U),       /*!< parity error interrupt flag */
+    USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U),        /*!< transmitter buffer empty interrupt flag */
+    USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U),         /*!< transmission complete interrupt flag */
+    USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U),       /*!< read data buffer not empty interrupt flag */
+    USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< overrun error interrupt flag */
+    USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U),       /*!< IDLE line detected interrupt flag */
     /* interrupt flags in CTL1 register */
-    USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U),        /*!< LIN break detected interrupt and flag */
+    USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U),        /*!< LIN break detected interrupt flag */
     /* interrupt flags in CTL2 register */
-    USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U),       /*!< wakeup from deep-sleep mode interrupt and flag */
-    USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),       /*!< CTS interrupt and flag */
-    USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U),   /*!< error interrupt and noise error flag */
-    USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U),  /*!< error interrupt and overrun error */
-    USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U),   /*!< error interrupt and frame error flag */
+    USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U),       /*!< wakeup from deep-sleep mode interrupt flag */
+    USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),       /*!< CTS interrupt flag */
+    USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U),   /*!< noise error interrupt flag */
+    USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U),  /*!< overrun error interrupt flag */
+    USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U),   /*!< frame error interrupt flag */
+    /* interrupt flags in RFCS register */
+    USART_INT_FLAG_RFFINT = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U),    /*!< receive FIFO full interrupt flag */
 }usart_interrupt_flag_enum;
 
 /* USART interrupt enable or disable */
 typedef enum
 {
     /* interrupt in CTL0 register */
-    USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U),         /*!< end of block interrupt */
-    USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U),         /*!< receiver timeout interrupt */
-    USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U),         /*!< address match interrupt */
-    USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),        /*!< parity error interrupt */
-    USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U),         /*!< transmitter buffer empty interrupt */
-    USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U),          /*!< transmission complete interrupt */
-    USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),        /*!< read data buffer not empty interrupt and overrun error interrupt */
-    USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),        /*!< IDLE line detected interrupt */
+    USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U),     /*!< end of block interrupt */
+    USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U),     /*!< receiver timeout interrupt */
+    USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U),     /*!< address match interrupt */
+    USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),    /*!< parity error interrupt */
+    USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U),     /*!< transmitter buffer empty interrupt */
+    USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U),      /*!< transmission complete interrupt */
+    USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),    /*!< read data buffer not empty interrupt and overrun error interrupt */
+    USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),    /*!< IDLE line detected interrupt */
     /* interrupt in CTL1 register */
-    USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U),         /*!< LIN break detected interrupt */
+    USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U),     /*!< LIN break detected interrupt */
     /* interrupt in CTL2 register */
-    USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U),         /*!< wakeup from deep-sleep mode interrupt */
-    USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U),        /*!< CTS interrupt */
-    USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),         /*!< error interrupt */
+    USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U),     /*!< wakeup from deep-sleep mode interrupt */
+    USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U),    /*!< CTS interrupt */
+    USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),     /*!< error interrupt */
+    /* interrupt in RFCS register */
+    USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U),     /*!< receive FIFO full interrupt */
 }usart_interrupt_enum;
 
 /* USART invert configure */
 typedef enum {
     /* data bit level inversion */
-    USART_DINV_ENABLE,                                                 /*!< data bit level inversion */
-    USART_DINV_DISABLE,                                                /*!< data bit level not inversion */
+    USART_DINV_ENABLE,                                               /*!< data bit level inversion */
+    USART_DINV_DISABLE,                                              /*!< data bit level not inversion */
     /* TX pin level inversion */
-    USART_TXPIN_ENABLE,                                                /*!< TX pin level inversion */
-    USART_TXPIN_DISABLE,                                               /*!< TX pin level not inversion */
+    USART_TXPIN_ENABLE,                                              /*!< TX pin level inversion */               
+    USART_TXPIN_DISABLE,                                             /*!< TX pin level not inversion */
     /* RX pin level inversion */
-    USART_RXPIN_ENABLE,                                                /*!< RX pin level inversion */
-    USART_RXPIN_DISABLE,                                               /*!< RX pin level not inversion */
+    USART_RXPIN_ENABLE,                                              /*!< RX pin level inversion */
+    USART_RXPIN_DISABLE,                                             /*!< RX pin level not inversion */
     /* swap TX/RX pins */
-    USART_SWAP_ENABLE,                                                 /*!< swap TX/RX pins */
-    USART_SWAP_DISABLE,                                                /*!< not swap TX/RX pins */
+    USART_SWAP_ENABLE,                                               /*!< swap TX/RX pins */                
+    USART_SWAP_DISABLE,                                              /*!< not swap TX/RX pins */
 }usart_invert_enum;
 
 /* USART receiver configure */
 #define CTL0_REN(regval)              (BIT(2) & ((uint32_t)(regval) << 2))
-#define USART_RECEIVE_ENABLE          CTL0_REN(1)                      /*!< enable receiver */
-#define USART_RECEIVE_DISABLE         CTL0_REN(0)                      /*!< disable receiver */
+#define USART_RECEIVE_ENABLE          CTL0_REN(1)                    /*!< enable receiver */
+#define USART_RECEIVE_DISABLE         CTL0_REN(0)                    /*!< disable receiver */
 
 /* USART transmitter configure */
 #define CTL0_TEN(regval)              (BIT(3) & ((uint32_t)(regval) << 3))
-#define USART_TRANSMIT_ENABLE         CTL0_TEN(1)                      /*!< enable transmitter */
-#define USART_TRANSMIT_DISABLE        CTL0_TEN(0)                      /*!< disable transmitter */
+#define USART_TRANSMIT_ENABLE         CTL0_TEN(1)                    /*!< enable transmitter */
+#define USART_TRANSMIT_DISABLE        CTL0_TEN(0)                    /*!< disable transmitter */
 
 /* USART parity bits definitions */
 #define CTL0_PM(regval)               (BITS(9,10) & ((uint32_t)(regval) << 9))
-#define USART_PM_NONE                 CTL0_PM(0)                       /*!< no parity */
-#define USART_PM_EVEN                 CTL0_PM(2)                       /*!< even parity */
-#define USART_PM_ODD                  CTL0_PM(3)                       /*!< odd parity */
+#define USART_PM_NONE                 CTL0_PM(0)                     /*!< no parity */
+#define USART_PM_EVEN                 CTL0_PM(2)                     /*!< even parity */
+#define USART_PM_ODD                  CTL0_PM(3)                     /*!< odd parity */
 
 /* USART wakeup method in mute mode */
 #define CTL0_WM(regval)               (BIT(11) & ((uint32_t)(regval) << 11))
-#define USART_WM_IDLE                 CTL0_WM(0)                       /*!< idle line */
-#define USART_WM_ADDR                 CTL0_WM(1)                       /*!< address match */
+#define USART_WM_IDLE                 CTL0_WM(0)                     /*!< idle line */
+#define USART_WM_ADDR                 CTL0_WM(1)                     /*!< address match */
 
 /* USART word length definitions */
 #define CTL0_WL(regval)               (BIT(12) & ((uint32_t)(regval) << 12))
-#define USART_WL_8BIT                 CTL0_WL(0)                       /*!< 8 bits */
-#define USART_WL_9BIT                 CTL0_WL(1)                       /*!< 9 bits */
+#define USART_WL_8BIT                 CTL0_WL(0)                     /*!< 8 bits */
+#define USART_WL_9BIT                 CTL0_WL(1)                     /*!< 9 bits */
 
 /* USART oversample mode */
 #define CTL0_OVSMOD(regval)           (BIT(15) & ((uint32_t)(regval) << 15))
-#define USART_OVSMOD_8                CTL0_OVSMOD(1)                   /*!< oversampling by 8 */
-#define USART_OVSMOD_16               CTL0_OVSMOD(0)                   /*!< oversampling by 16 */
+#define USART_OVSMOD_8                CTL0_OVSMOD(1)                 /*!< oversampling by 8 */
+#define USART_OVSMOD_16               CTL0_OVSMOD(0)                 /*!< oversampling by 16 */
 
 /* USART address detection mode */
 #define CTL1_ADDM(regval)             (BIT(4) & ((uint32_t)(regval) << 4))
-#define USART_ADDM_4BIT               CTL1_ADDM(0)                     /*!< 4-bit address detection */
-#define USART_ADDM_FULLBIT            CTL1_ADDM(1)                     /*!< full-bit address detection */
+#define USART_ADDM_4BIT               CTL1_ADDM(0)                   /*!< 4-bit address detection */
+#define USART_ADDM_FULLBIT            CTL1_ADDM(1)                   /*!< full-bit address detection */
 
 /* USART LIN break frame length */
 #define CTL1_LBLEN(regval)            (BIT(5) & ((uint32_t)(regval) << 5))
-#define USART_LBLEN_10B               CTL1_LBLEN(0)                    /*!< 10 bits break detection */
-#define USART_LBLEN_11B               CTL1_LBLEN(1)                    /*!< 11 bits break detection */
+#define USART_LBLEN_10B               CTL1_LBLEN(0)                  /*!< 10 bits break detection */
+#define USART_LBLEN_11B               CTL1_LBLEN(1)                  /*!< 11 bits break detection */
 
 /* USART last bit clock pulse */
 #define CTL1_CLEN(regval)             (BIT(8) & ((uint32_t)(regval) << 8))
-#define USART_CLEN_NONE               CTL1_CLEN(0)                     /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */
-#define USART_CLEN_EN                 CTL1_CLEN(1)                     /*!< clock pulse of the last data bit (MSB) is output to the CK pin */
+#define USART_CLEN_NONE               CTL1_CLEN(0)                   /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */
+#define USART_CLEN_EN                 CTL1_CLEN(1)                   /*!< clock pulse of the last data bit (MSB) is output to the CK pin */
 
 /* USART clock phase */
 #define CTL1_CPH(regval)              (BIT(9) & ((uint32_t)(regval) << 9))
-#define USART_CPH_1CK                 CTL1_CPH(0)                      /*!< first clock transition is the first data capture edge */
-#define USART_CPH_2CK                 CTL1_CPH(1)                      /*!< second clock transition is the first data capture edge */
+#define USART_CPH_1CK                 CTL1_CPH(0)                    /*!< first clock transition is the first data capture edge */
+#define USART_CPH_2CK                 CTL1_CPH(1)                    /*!< second clock transition is the first data capture edge */
 
 /* USART clock polarity */
 #define CTL1_CPL(regval)              (BIT(10) & ((uint32_t)(regval) << 10))
-#define USART_CPL_LOW                 CTL1_CPL(0)                      /*!< steady low value on CK pin */
-#define USART_CPL_HIGH                CTL1_CPL(1)                      /*!< steady high value on CK pin */
+#define USART_CPL_LOW                 CTL1_CPL(0)                    /*!< steady low value on CK pin */
+#define USART_CPL_HIGH                CTL1_CPL(1)                    /*!< steady high value on CK pin */
 
 /* USART stop bits definitions */
 #define CTL1_STB(regval)              (BITS(12,13) & ((uint32_t)(regval) << 12))
-#define USART_STB_1BIT                CTL1_STB(0)                      /*!< 1 bit */
-#define USART_STB_2BIT                CTL1_STB(2)                      /*!< 2 bits */
-#define USART_STB_1_5BIT              CTL1_STB(3)                      /*!< 1.5 bits */
+#define USART_STB_1BIT                CTL1_STB(0)                    /*!< 1 bit */
+#define USART_STB_0_5BIT              CTL1_STB(1)                    /*!< 0.5 bit */
+#define USART_STB_2BIT                CTL1_STB(2)                    /*!< 2 bits */
+#define USART_STB_1_5BIT              CTL1_STB(3)                    /*!< 1.5 bits */
 
 /* USART data is transmitted/received with the LSB/MSB first */
 #define CTL1_MSBF(regval)             (BIT(19) & ((uint32_t)(regval) << 19))
-#define USART_MSBF_LSB                CTL1_MSBF(0)                     /*!< LSB first */
-#define USART_MSBF_MSB                CTL1_MSBF(1)                     /*!< MSB first */
+#define USART_MSBF_LSB                CTL1_MSBF(0)                   /*!< LSB first */
+#define USART_MSBF_MSB                CTL1_MSBF(1)                   /*!< MSB first */
 
 /* USART auto baud rate detection mode bits definitions */
 #define CTL1_ABDM(regval)             (BITS(21,22) & ((uint32_t)(regval) << 21))
-#define USART_ABDM_FTOR               CTL1_ABDM(0)                     /*!< falling edge to rising edge measurement */
-#define USART_ABDM_FTOF               CTL1_ABDM(1)                     /*!< falling edge to falling edge measurement */
+#define USART_ABDM_FTOR               CTL1_ABDM(0)                   /*!< falling edge to rising edge measurement */
+#define USART_ABDM_FTOF               CTL1_ABDM(1)                   /*!< falling edge to falling edge measurement */
 
 /* USART IrDA low-power enable */
 #define CTL2_IRLP(regval)             (BIT(2) & ((uint32_t)(regval) << 2))
-#define USART_IRLP_LOW                CTL2_IRLP(1)                     /*!< low-power */
-#define USART_IRLP_NORMAL             CTL2_IRLP(0)                     /*!< normal */
+#define USART_IRLP_LOW                CTL2_IRLP(1)                   /*!< low-power */
+#define USART_IRLP_NORMAL             CTL2_IRLP(0)                   /*!< normal */
 
 /* DMA enable for reception */
 #define CTL2_DENR(regval)             (BIT(6) & ((uint32_t)(regval) << 6))
@@ -386,19 +403,19 @@ typedef enum {
 
 /* USART one sample bit method configure */
 #define CTL2_OSB(regval)              (BIT(11) & ((uint32_t)(regval) << 11))
-#define USART_OSB_1BIT                CTL2_OSB(1)                     /*!< 1 sample bit */
-#define USART_OSB_3BIT                CTL2_OSB(0)                     /*!< 3 sample bits */
+#define USART_OSB_1BIT                CTL2_OSB(1)                    /*!< 1 sample bit */
+#define USART_OSB_3BIT                CTL2_OSB(0)                    /*!< 3 sample bits */
 
 /* USART driver enable polarity mode */
 #define CTL2_DEP(regval)              (BIT(15) & ((uint32_t)(regval) << 15))
-#define USART_DEP_HIGH                CTL2_DEP(0)                      /*!< DE signal is active high */
-#define USART_DEP_LOW                 CTL2_DEP(1)                      /*!< DE signal is active low */
+#define USART_DEP_HIGH                CTL2_DEP(0)                    /*!< DE signal is active high */
+#define USART_DEP_LOW                 CTL2_DEP(1)                    /*!< DE signal is active low */
 
 /* USART wakeup mode from deep-sleep mode */
 #define CTL2_WUM(regval)              (BITS(20,21) & ((uint32_t)(regval) << 20))
-#define USART_WUM_ADDR                CTL2_WUM(0)                      /*!< WUF active on address match */
-#define USART_WUM_STARTB              CTL2_WUM(2)                      /*!< WUF active on start bit */
-#define USART_WUM_RBNE                CTL2_WUM(3)                      /*!< WUF active on RBNE */
+#define USART_WUM_ADDR                CTL2_WUM(0)                    /*!< WUF active on address match */
+#define USART_WUM_STARTB              CTL2_WUM(2)                    /*!< WUF active on start bit */
+#define USART_WUM_RBNE                CTL2_WUM(3)                    /*!< WUF active on RBNE */
 
 /* function declarations */
 /* initialization functions */
@@ -412,8 +429,6 @@ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
 /* configure USART stop bit length */
 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
-
-/* USART normal mode communication */
 /* enable USART */
 void usart_enable(uint32_t usart_periph);
 /* disable USART */
@@ -422,96 +437,102 @@ void usart_disable(uint32_t usart_periph);
 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
 /* configure USART receiver */
 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
-/* USART transmit data function */
-void usart_data_transmit(uint32_t usart_periph, uint32_t data);
-/* USART receive data function */
-uint16_t usart_data_receive(uint32_t usart_periph);
+
+/* USART normal mode communication */
 /* data is transmitted/received with the LSB/MSB first */
 void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
 /* configure USART inverted */
 void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
-/* overrun function is enabled */
+/* enable the USART overrun function */
 void usart_overrun_enable(uint32_t usart_periph);
-/* overrun function is disabled */
-void usart_overrun_disable(uint32_t usart_periph);    
+/* disable the USART overrun function */
+void usart_overrun_disable(uint32_t usart_periph);
 /* configure the USART oversample mode */
 void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
-/* sample bit method configure */
+/* configure sample bit method */
 void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb);
+/* enable receiver timeout */
+void usart_receiver_timeout_enable(uint32_t usart_periph);
+/* disable receiver timeout */
+void usart_receiver_timeout_disable(uint32_t usart_periph);
+/* configure receiver timeout threshold */
+void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
+/* USART transmit data function */
+void usart_data_transmit(uint32_t usart_periph, uint32_t data);
+/* USART receive data function */
+uint16_t usart_data_receive(uint32_t usart_periph);
 
 /* auto baud rate detection */
-/* auto baud rate detection enable */
+/* enable auto baud rate detection */
 void usart_autobaud_detection_enable(uint32_t usart_periph);
-/* auto baud rate detection disable */
+/* disable auto baud rate detection */
 void usart_autobaud_detection_disable(uint32_t usart_periph);
-/* auto baud rate detection mode configure */
+/* configure auto baud rate detection mode */
 void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod);
 
 /* multi-processor communication */
+/* configure the address of the USART in wake up by address match mode */
+void usart_address_config(uint32_t usart_periph, uint8_t addr);
+/* configure address detection mode */
+void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
 /* enable mute mode */
 void usart_mute_mode_enable(uint32_t usart_periph);
 /* disable mute mode */
 void usart_mute_mode_disable(uint32_t usart_periph);
 /* configure wakeup method in mute mode */
 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
-/* address detection mode configure */
-void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
-/* configure address of the USART */
-void usart_address_config(uint32_t usart_periph, uint8_t addr);
-/* enable receiver timeout */
-void usart_receiver_timeout_enable(uint32_t usart_periph);
-/* disable receiver timeout */
-void usart_receiver_timeout_disable(uint32_t usart_periph);
-/* configure receiver timeout threshold */
-void usart_receiver_timeout_config(uint32_t usart_periph, uint32_t rtimeout);
 
 /* LIN mode communication */
-/* LIN mode enable */
+/* enable LIN mode */
 void usart_lin_mode_enable(uint32_t usart_periph);
-/* LIN mode disable */
+/* disable LIN mode */
 void usart_lin_mode_disable(uint32_t usart_periph);
-/* LIN break detection length */
+/* configure LIN break frame length */
 void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
 
 /* half-duplex communication */
-/* half-duplex enable */
+/* enable half-duplex mode */
 void usart_halfduplex_enable(uint32_t usart_periph);
-/* half-duplex disable */
+/* disable half-duplex mode */
 void usart_halfduplex_disable(uint32_t usart_periph);
 
 /* synchronous communication */
-/* clock enable */
+/* enable USART clock */
 void usart_clock_enable(uint32_t usart_periph);
-/* clock disable*/
+/* disable USART clock */
 void usart_clock_disable(uint32_t usart_periph);
 /* configure USART synchronous mode parameters */
 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
 
 /* smartcard communication */
-/* smartcard mode enable */
+/* configure guard time value in smartcard mode */
+void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
+/* enable smartcard mode */
 void usart_smartcard_mode_enable(uint32_t usart_periph);
-/* smartcard mode disable */
+/* disable smartcard mode */
 void usart_smartcard_mode_disable(uint32_t usart_periph);
-/* NACK enable in smartcard mode */
+/* enable NACK in smartcard mode */
 void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
-/* NACK disable in smartcard mode */
+/* disable NACK in smartcard mode */
 void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
-/* guard time value configure in smartcard mode */
-void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
-/* block length configure */
-void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
-/* smartcard auto-retry number configure */
+/* enable early NACK in smartcard mode */
+void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph);
+/* disable early NACK in smartcard mode */
+void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph);
+/* configure smartcard auto-retry number */
 void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
+/* configure block length */
+void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
 
 /* IrDA communication */
 /* enable IrDA mode */
 void usart_irda_mode_enable(uint32_t usart_periph);
 /* disable IrDA mode */
 void usart_irda_mode_disable(uint32_t usart_periph);
+/* configure the peripheral clock prescaler in USART IrDA low-power mode or SmartCard mode */
+void usart_prescaler_config(uint32_t usart_periph, uint32_t psc);
 /* configure IrDA low-power */
 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
-/* configure the peripheral clock prescaler */
-void usart_prescaler_config(uint32_t usart_periph, uint32_t psc);
 
 /* hardware flow communication */
 /* configure hardware flow control RTS */
@@ -519,13 +540,13 @@ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
 /* configure hardware flow control CTS */
 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
 
-/* RS485 driver enable */
+/* enable RS485 driver */
 void usart_rs485_driver_enable(uint32_t usart_periph);
-/* RS485 driver disable */
+/* disable RS485 driver */
 void usart_rs485_driver_disable(uint32_t usart_periph);
-/* driver enable assertion time configure */
+/* configure driver enable assertion time */
 void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime);
-/* driver enable de-assertion time configure */
+/* configure driver enable de-assertion time */
 void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime);
 /* configure driver enable polarity mode */
 void usart_depolarity_config(uint32_t usart_periph, uint32_t dep);
@@ -540,27 +561,35 @@ void usart_reception_error_dma_disable(uint32_t usart_periph);
 /* enable DMA on reception error */
 void usart_reception_error_dma_enable(uint32_t usart_periph);
 
-/* USART be able to wake up the mcu from deep-sleep mode */
+/* enable USART to wakeup the mcu from deep-sleep mode */
 void usart_wakeup_enable(uint32_t usart_periph);
-/* USART be not able to wake up the mcu from deep-sleep mode */
+/* disable USART to wakeup the mcu from deep-sleep mode */
 void usart_wakeup_disable(uint32_t usart_periph);
-/* wakeup mode from deep-sleep mode */
+/* configure the USART wakeup mode from deep-sleep mode */
 void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum);
+/* enable USART command */
+void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype);
 
-/* flag functions */
-/* get flag in STAT register */
+/* USART receive FIFO */
+/* enable receive FIFO */
+void usart_receive_fifo_enable(uint32_t usart_periph);
+/* disable receive FIFO */
+void usart_receive_fifo_disable(uint32_t usart_periph);
+/* read receive FIFO counter number */
+uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph);
+
+/* flag & interrupt functions */
+/* get flag in STAT/RFCS register */
 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
 /* clear flag in STAT register */
 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
-
 /* enable USART interrupt */
-void usart_interrupt_enable(uint32_t usart_periph, uint32_t inttype);
+void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt);
 /* disable USART interrupt */
-void usart_interrupt_disable(uint32_t usart_periph, uint32_t inttype);
-/* enable USART command */
-void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype);
+void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt);
 /* get USART interrupt and flag status */
-FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
-/* clear interrupt flag in STAT register */
-void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag);
-#endif /* GD32F1X0_USART_H */
+FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
+/* clear USART interrupt flag */
+void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
+
+#endif /* GD32F3X0_USART_H */

Librarys/GD32F1x0_Drivers/inc/gd32f1x0_wwdgt.h → Librarys/GD32F3x0_Drivers/Include/gd32f3x0_wwdgt.h

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_wwdgt.h
+    \file  gd32f3x0_wwdgt.h
     \brief definitions for the WWDGT 
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,44 +33,44 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#ifndef GD32F1X0_WWDGT_H
-#define GD32F1X0_WWDGT_H
+#ifndef GD32F3X0_WWDGT_H
+#define GD32F3X0_WWDGT_H
 
-#include "gd32f1x0.h"
+#include "gd32f3x0.h"
 
 /* WWDGT definitions */
 #define WWDGT                       WWDGT_BASE
 
 /* registers definitions */
-#define WWDGT_CTL                   REG32((WWDGT) + 0x00U)           /*!< WWDGT control register */
-#define WWDGT_CFG                   REG32((WWDGT) + 0x04U)           /*!< WWDGT configuration register */
-#define WWDGT_STAT                  REG32((WWDGT) + 0x08U)           /*!< WWDGT status register */
+#define WWDGT_CTL                   REG32(WWDGT + 0x00000000U)                     /*!< WWDGT control register */
+#define WWDGT_CFG                   REG32(WWDGT + 0x00000004U)                     /*!< WWDGT configuration register */
+#define WWDGT_STAT                  REG32(WWDGT + 0x00000008U)                     /*!< WWDGT status register */
 
 /* bits definitions */
 /* WWDGT_CTL */
-#define WWDGT_CTL_CNT               BITS(0,6)                       /*!< WWDGT counter value */
-#define WWDGT_CTL_WDGTEN            BIT(7)                          /*!< WWDGT counter enable */
+#define WWDGT_CTL_CNT               BITS(0,6)                                      /*!< WWDGT counter value */
+#define WWDGT_CTL_WDGTEN            BIT(7)                                         /*!< WWDGT counter enable */
 
 /* WWDGT_CFG */
-#define WWDGT_CFG_WIN               BITS(0,6)                       /*!< WWDGT counter window value */
-#define WWDGT_CFG_PSC               BITS(7,8)                       /*!< WWDGT prescaler divider value */
-#define WWDGT_CFG_EWIE              BIT(9)                          /*!< early wakeup interrupt enable */
+#define WWDGT_CFG_WIN               BITS(0,6)                                      /*!< WWDGT counter window value */
+#define WWDGT_CFG_PSC               BITS(7,8)                                      /*!< WWDGT prescaler divider value */
+#define WWDGT_CFG_EWIE              BIT(9)                                         /*!< WWDGT early wakeup interrupt enable */
 
 /* WWDGT_STAT */
-#define WWDGT_STAT_EWIF             BIT(0)                          /*!< early wakeup interrupt flag */
+#define WWDGT_STAT_EWIF             BIT(0)                                         /*!< WWDGT early wakeup interrupt flag */
 
 /* constants definitions */
-/* ctl register value */
-#define CTL_CNT(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0U))   /*!< write value to WWDGT_CTL_CNT bit field */
+/* WWDGT_CTL register value */
+#define CTL_CNT(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0U))       /*!< write value to WWDGT_CTL_CNT bit field */
 
-/* cfg register value */
-#define CFG_WIN(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0U))   /*!< write value to WWDGT_CFG_WIN bit field */
+/* WWDGT_CFG register value */
+#define CFG_WIN(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0U))       /*!< write value to WWDGT_CFG_WIN bit field */
 
-#define CFG_PSC(regval)             (BITS(7,8) & ((uint32_t)(regval) << 7U))   /*!< write value to WWDGT_CFG_PSC bit field */
-#define WWDGT_CFG_PSC_DIV1          ((uint32_t)CFG_PSC(0))          /*!< the time base of WWDGT = (PCLK1/4096)/1 */
-#define WWDGT_CFG_PSC_DIV2          ((uint32_t)CFG_PSC(1))          /*!< the time base of WWDGT = (PCLK1/4096)/2 */
-#define WWDGT_CFG_PSC_DIV4          ((uint32_t)CFG_PSC(2))          /*!< the time base of WWDGT = (PCLK1/4096)/4 */
-#define WWDGT_CFG_PSC_DIV8          ((uint32_t)CFG_PSC(3))          /*!< the time base of WWDGT = (PCLK1/4096)/8 */
+#define CFG_PSC(regval)             (BITS(7,8) & ((uint32_t)(regval) << 7U))       /*!< write value to WWDGT_CFG_PSC bit field */
+#define WWDGT_CFG_PSC_DIV1          ((uint32_t)CFG_PSC(0))                         /*!< the time base of WWDGT = (PCLK1/4096)/1 */
+#define WWDGT_CFG_PSC_DIV2          ((uint32_t)CFG_PSC(1))                         /*!< the time base of WWDGT = (PCLK1/4096)/2 */
+#define WWDGT_CFG_PSC_DIV4          ((uint32_t)CFG_PSC(2))                         /*!< the time base of WWDGT = (PCLK1/4096)/4 */
+#define WWDGT_CFG_PSC_DIV8          ((uint32_t)CFG_PSC(3))                         /*!< the time base of WWDGT = (PCLK1/4096)/8 */
 
 /* function declarations */
 /* reset the window watchdog timer configuration */
@@ -93,4 +90,4 @@ FlagStatus wwdgt_flag_get(void);
 /* clear early wakeup interrupt state of WWDGT */
 void wwdgt_flag_clear(void);
 
-#endif /* GD32F1X0_WWDGT_H */
+#endif /* GD32F3X0_WWDGT_H */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_adc.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_adc.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_adc.c
+    \file  gd32f3x0_adc.c
     \brief ADC driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_adc.h"
+#include "gd32f3x0_adc.h"
 
 /*!
     \brief      reset ADC
@@ -142,7 +139,7 @@ void adc_tempsensor_vrefint_disable(void)
 }
 
 /*!
-    \brief      enable the vbat channel
+    \brief      enable the Vbat channel
     \param[in]  none
     \param[out] none
     \retval     none
@@ -154,7 +151,7 @@ void adc_vbat_enable(void)
 }
 
 /*!
-    \brief      disable the vbat channel
+    \brief      disable the Vbat channel
     \param[in]  none
     \param[out] none
     \retval     none
@@ -310,12 +307,6 @@ void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_t
 {
     uint32_t rsq,sampt;
     
-#ifdef GD32F130_150
-    if(ADC_CHANNEL_18 == channel){
-        channel = ADC_CHANNEL_0;
-    }
-#endif
-    
     /* configure ADC regular sequence */
     if(rank < 6U){
         rsq = ADC_RSQ2;
@@ -333,7 +324,6 @@ void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_t
         rsq |= ((uint32_t)channel << (5U*(rank-12U)));
         ADC_RSQ0 = rsq;
     }else{
-	    /* illegal parameters */
     }
     
     /* configure ADC sampling time */
@@ -342,7 +332,7 @@ void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_t
         sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
         sampt |= (uint32_t)(sample_time << (3U*channel));
         ADC_SAMPT1 = sampt;
-    }else if(channel < 18U){
+    }else if(channel < 19U){
         sampt = ADC_SAMPT0;
         sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
         sampt |= (uint32_t)(sample_time << (3U*(channel-10U)));
@@ -391,8 +381,8 @@ void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_
         ADC_SAMPT1 = sampt;
     }else if(channel < 19U){
         sampt = ADC_SAMPT0;
-        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
-        sampt |= ((uint32_t)sample_time << (3U*(channel-10U)));
+        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel - 10U))));
+        sampt |= ((uint32_t)sample_time << (3U*(channel - 10U)));
         ADC_SAMPT0 = sampt;
     }else{
         /* illegal parameters */
@@ -633,7 +623,7 @@ FlagStatus adc_interrupt_flag_get(uint32_t flag)
     case ADC_INT_FLAG_WDE:
         state = ADC_STAT & ADC_STAT_WDE;
         if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){
-          interrupt_flag = SET;
+            interrupt_flag = SET;
         }
         break;
     case ADC_INT_FLAG_EOC:
@@ -795,7 +785,6 @@ void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_thresho
     ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold);
 }
 
-#ifdef GD32F170_190
 /*!
     \brief      configure ADC resolution 
     \param[in]  resolution: ADC resolution
@@ -878,4 +867,3 @@ void adc_oversample_mode_disable(void)
 {
     ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
 }
-#endif /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_cec.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_cec.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_cec.c
+    \file  gd32f3x0_cec.c
     \brief CEC driver
     
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,9 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_cec.h"
+#ifdef GD32F350
+
+#include "gd32f3x0_cec.h"
 
 /*!
     \brief      reset HDMI-CEC controller
@@ -52,7 +51,7 @@ void cec_deinit(void)
 
 /*!
     \brief      configure signal free time,the signal free time counter start option,own address 
-    \param[in]  sftopt: signal free time counter start option
+    \param[in]  sftmopt: signal free time counter start option
                 only one parameter can be selected which is shown as below:
       \arg        CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted
       \arg        CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end
@@ -73,14 +72,14 @@ void cec_deinit(void)
     \param[out] none
     \retval     none
 */
-void cec_init(uint32_t sftopt, uint32_t sft, uint32_t address)
+void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address)
 {
     uint32_t cfg;
     cfg = CEC_CFG;
-    /* clear SFTOPT bit,SFT[2:0] */
+    /* clear SFTMOPT bit,SFT[2:0] */
     cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT);
-    /* assign SFTOPT bit,SFT[2:0] */
-    cfg |= (sftopt | sft);
+    /* assign SFTMOPT bit,SFT[2:0] */
+    cfg |= (sftmopt | sft);
     CEC_CFG = cfg;
     if(CEC_OWN_ADDRESS_CLEAR == address){
         CEC_CFG &= ~CEC_CFG_OAD;
@@ -196,7 +195,7 @@ void cec_listen_mode_disable(void)
 /*!
     \brief      configure and clear own address.the controller can be configured to multiple own address 
     \param[in]  address: own address
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        CEC_OWN_ADDRESS_CLEAR: own address is cleared
       \arg        CEC_OWN_ADDRESSx(x=0..14): own address is x
     \param[out] none
@@ -213,7 +212,7 @@ void cec_own_address_config(uint32_t address)
 
 /*!
     \brief      configure signal free time and the signal free time counter start option 
-    \param[in]  sftopt: signal free time counter start option
+    \param[in]  sftmopt: signal free time counter start option
                 only one parameter can be selected which is shown as below:
       \arg        CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted
       \arg        CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end
@@ -230,14 +229,14 @@ void cec_own_address_config(uint32_t address)
     \param[out] none
     \retval     none
 */
-void cec_sft_config(uint32_t sftopt, uint32_t sft)
+void cec_sft_config(uint32_t sftmopt, uint32_t sft)
 {
     uint32_t cfg;
     cfg = CEC_CFG;
-    /* clear SFTOPT bit,SFT[2:0] */
+    /* clear SFTMOPT bit,SFT[2:0] */
     cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT);
-    /* assign SFTOPT bit,SFT[2:0] */
-    cfg |= (sftopt | sft);
+    /* assign SFTMOPT bit,SFT[2:0] */
+    cfg |= (sftmopt | sft);
     CEC_CFG = cfg;
 }
 
@@ -262,9 +261,9 @@ void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe,
 {
     uint32_t cfg;
     cfg = CEC_CFG;
-    /* clear BCNG bit, BPLEG bit, BREG bit */
+    /* clear BCNG bit, RLBPEGEN bit, RBREGEN bit */
     cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG);
-    /* assign BCNG bit, BPLEG bit, BREG bit */
+    /* assign BCNG bit, RLBPEGEN bit, RBREGEN bit */
     cfg |= (broadcast | singlecast_lbpe | singlecast_bre);
     CEC_CFG = cfg;
 }
@@ -322,76 +321,20 @@ void cec_data_send(uint8_t data)
 
 /*!
     \brief      receive a data by the CEC peripheral
-    \param[in]  none
+    \param[in]  data: the data to receive
     \param[out] none
-    \retval     data: the data to receive
+    \retval     none
 */
 uint8_t cec_data_receive(void)
 {
     return (uint8_t)CEC_RDATA;
 }
 
-/*!
-    \brief      get CEC interrupt flag
-    \param[in]  flag:  specify which flag
-                only one parameter can be selected which is shown as below:
-      \arg        CEC_INT_FLAG_BR: Rx-byte data received
-      \arg        CEC_INT_FLAG_REND: end of reception
-      \arg        CEC_INT_FLAG_RO: RX overrun
-      \arg        CEC_INT_FLAG_BRE: bit rising error
-      \arg        CEC_INT_FLAG_BPSE: short bit period error
-      \arg        CEC_INT_FLAG_BPLE: long bit period error
-      \arg        CEC_INT_FLAG_RAE: Rx ACK error
-      \arg        CEC_INT_FLAG_ARBF: arbitration lost
-      \arg        CEC_INT_FLAG_TBR: Tx-byte data request
-      \arg        CEC_INT_FLAG_TEND: transmission successfully end
-      \arg        CEC_INT_FLAG_TU: Tx data buffer underrun
-      \arg        CEC_INT_FLAG_TERR: Tx-error
-      \arg        CEC_INT_FLAG_TAERR: Tx ACK error flag
-    \param[out] none
-    \retval     FlagStatus: SET or RESET
-*/
-FlagStatus cec_interrupt_flag_get(uint32_t flag)
-{
-    uint32_t interrupt_enable = 0U,interrupt_flag = 0U;
-    interrupt_flag = (CEC_INTF & flag);
-    interrupt_enable = (CEC_INTEN & flag);
-    if(interrupt_flag && interrupt_enable){
-        return SET;
-    }else{
-        return RESET;
-    }
-}
-
-/*!
-    \brief      clear CEC interrupt flag
-    \param[in]  flag:  specify which flag
-                only one parameter can be selected which is shown as below:
-      \arg        CEC_INT_FLAG_BR: Rx-byte data received
-      \arg        CEC_INT_FLAG_REND: end of reception
-      \arg        CEC_INT_FLAG_RO: RX overrun
-      \arg        CEC_INT_FLAG_BRE: bit rising error
-      \arg        CEC_INT_FLAG_BPSE: short bit period error
-      \arg        CEC_INT_FLAG_BPLE: long bit period error
-      \arg        CEC_INT_FLAG_RAE: Rx ACK error
-      \arg        CEC_INT_FLAG_ARBF: arbitration lost
-      \arg        CEC_INT_FLAG_TBR: Tx-byte data request
-      \arg        CEC_INT_FLAG_TEND: transmission successfully end
-      \arg        CEC_INT_FLAG_TU: Tx data buffer underrun
-      \arg        CEC_INT_FLAG_TERR: Tx-error
-      \arg        CEC_INT_FLAG_TAERR: Tx ACK error flag
-    \param[out] none
-    \retval     none
-*/
-void cec_interrupt_flag_clear(uint32_t flag)
-{
-    CEC_INTF = flag;
-}
 
 /*!
     \brief      enable interrupt
     \param[in]  flag: specify which flag
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        CEC_INT_BR: enable Rx-byte data received interrupt
       \arg        CEC_INT_REND: enable end of reception interrupt
       \arg        CEC_INT_RO: enable RX overrun interrupt
@@ -404,7 +347,7 @@ void cec_interrupt_flag_clear(uint32_t flag)
       \arg        CEC_INT_TEND: enable transmission successfully end interrupt
       \arg        CEC_INT_TU: enable Tx data buffer underrun interrupt
       \arg        CEC_INT_TERR: enable Tx-error interrupt 
-      \arg        CEC_INT_TAERR: enable Tx ACK error  interrupt
+      \arg        CEC_INT_TAERR: enable Tx ACK error interrupt
     \param[out] none
     \retval     none
 */
@@ -416,7 +359,7 @@ void cec_interrupt_enable(uint32_t flag)
 /*!
     \brief      disable interrupt
     \param[in]  flag: specify which flag
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        CEC_INT_BR: disable Rx-byte data received interrupt
       \arg        CEC_INT_REND: disable end of reception interrupt
       \arg        CEC_INT_RO: disable RX overrun interrupt
@@ -430,6 +373,7 @@ void cec_interrupt_enable(uint32_t flag)
       \arg        CEC_INT_TU: disable Tx data buffer underrun interrupt
       \arg        CEC_INT_TERR: disable Tx-error interrupt 
       \arg        CEC_INT_TAERR: disable Tx ACK error  interrupt
+
     \param[out] none
     \retval     none
 */
@@ -438,10 +382,11 @@ void cec_interrupt_disable(uint32_t flag)
     CEC_INTEN &= ~flag;
 }
 
+
 /*!
     \brief      get CEC status
     \param[in]  flag:  specify which flag
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        CEC_FLAG_BR: Rx-byte data received
       \arg        CEC_FLAG_REND: end of reception
       \arg        CEC_FLAG_RO: RX overrun
@@ -470,7 +415,7 @@ FlagStatus cec_flag_get(uint32_t flag)
 /*!
     \brief      clear CEC status
     \param[in]  flag:  specify which flag
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        CEC_FLAG_BR: Rx-byte data received
       \arg        CEC_FLAG_REND: end of reception
       \arg        CEC_FLAG_RO: RX overrun
@@ -483,7 +428,8 @@ FlagStatus cec_flag_get(uint32_t flag)
       \arg        CEC_FLAG_TEND: transmission successfully end
       \arg        CEC_FLAG_TU: Tx data buffer underrun
       \arg        CEC_FLAG_TERR: Tx-error
-      \arg        CEC_FLAG_TAERR Tx ACK error flag
+      \arg        CEC_FLAG_TAERR: Tx ACK error flag
+
     \param[out] none
     \retval     FlagStatus: SET or RESET
 */
@@ -491,3 +437,63 @@ void cec_flag_clear(uint32_t flag)
 {
     CEC_INTF |= flag;
 }
+
+/*!
+    \brief      get CEC int flag and status
+    \param[in]  flag:  specify which flag
+                one or more parameters can be selected which are shown as below:
+      \arg        CEC_INT_FLAG_BR: Rx-byte data received
+      \arg        CEC_INT_FLAG_REND: end of reception
+      \arg        CEC_INT_FLAG_RO: RX overrun
+      \arg        CEC_INT_FLAG_BRE: bit rising error
+      \arg        CEC_INT_FLAG_BPSE: short bit period error
+      \arg        CEC_INT_FLAG_BPLE: long bit period error
+      \arg        CEC_INT_FLAG_RAE: Rx ACK error
+      \arg        CEC_INT_FLAG_ARBF: arbitration lost
+      \arg        CEC_INT_FLAG_TBR: Tx-byte data request
+      \arg        CEC_INT_FLAG_TEND: transmission successfully end
+      \arg        CEC_INT_FLAG_TU: Tx data buffer underrun
+      \arg        CEC_INT_FLAG_TERR: Tx-error
+      \arg        CEC_INT_FLAG_TAERR: Tx ACK error flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus cec_interrupt_flag_get(uint32_t flag)
+{
+    uint32_t interrupt_enable = 0U,interrupt_flag = 0U;
+    interrupt_flag = (CEC_INTF & flag);
+    interrupt_enable = (CEC_INTEN & flag);
+    if(interrupt_flag && interrupt_enable){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear CEC int flag and status
+    \param[in]  flag:  specify which flag
+                one or more parameters can be selected which are shown as below:
+      \arg        CEC_INT_FLAG_BR: Rx-byte data received
+      \arg        CEC_INT_FLAG_REND: end of reception
+      \arg        CEC_INT_FLAG_RO: RX overrun
+      \arg        CEC_INT_FLAG_BRE: bit rising error
+      \arg        CEC_INT_FLAG_BPSE: short bit period error
+      \arg        CEC_INT_FLAG_BPLE: long bit period error
+      \arg        CEC_INT_FLAG_RAE: Rx ACK error
+      \arg        CEC_INT_FLAG_ARBF: arbitration lost
+      \arg        CEC_INT_FLAG_TBR: Tx-byte data request
+      \arg        CEC_INT_FLAG_TEND: transmission successfully end
+      \arg        CEC_INT_FLAG_TU: Tx data buffer underrun
+      \arg        CEC_INT_FLAG_TERR: Tx-error
+      \arg        CEC_INT_FLAG_TAERR: Tx ACK error flag
+    \param[out] none
+    \retval     none
+*/
+void cec_interrupt_flag_clear(uint32_t flag)
+{
+    CEC_INTF = flag;
+}
+
+
+#endif

Librarys/GD32F1x0_Drivers/src/gd32f1x0_cmp.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_cmp.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_cmp.c
+    \file  gd32f3x0_cmp.c
     \brief CMP driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=5,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=5,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=5,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_cmp.h"
+#include "gd32f3x0_cmp.h"
 
 /*!
     \brief      deinitialize comparator 
@@ -54,12 +51,12 @@ void cmp_deinit(void)
     \param[in]  cmp_periph
       \arg        CMP0: comparator 0
       \arg        CMP1: comparator 1
-    \param[in]  cmp_operating_mode
+    \param[in]  operating_mode
       \arg        CMP_HIGHSPEED: high speed mode
       \arg        CMP_MIDDLESPEED: medium speed mode
       \arg        CMP_LOWSPEED: low speed mode
       \arg        CMP_VERYLOWSPEED: very-low speed mode
-    \param[in]  cmp_inverting_input 
+    \param[in]  inverting_input 
       \arg        CMP_1_4VREFINT: VREFINT *1/4 input
       \arg        CMP_1_2VREFINT: VREFINT *1/2 input
       \arg        CMP_3_4VREFINT: VREFINT *3/4 input
@@ -67,7 +64,7 @@ void cmp_deinit(void)
       \arg        CMP_DAC: PA4 (DAC) input
       \arg        CMP_PA5: PA5 input
       \arg        CMP_PA_0_2: PA0 or PA2 input
-    \param[in]  cmp_hysteresis
+    \param[in]  hysteresis
       \arg        CMP_HYSTERESIS_NO: output no hysteresis
       \arg        CMP_HYSTERESIS_LOW: output low hysteresis
       \arg        CMP_HYSTERESIS_MIDDLE: output middle hysteresis
@@ -75,19 +72,16 @@ void cmp_deinit(void)
     \param[out] none
     \retval     none
 */
-void cmp_mode_init(uint32_t cmp_periph, \
-                   operating_mode_enum cmp_operating_mode, \
-                   inverting_input_enum cmp_inverting_input, \
-                   cmp_hysteresis_enum output_hysteresis)
+void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis)
 {
     if(CMP0 == cmp_periph){
         /* initialize comparator 0 mode */
         CMP_CS &= ~(uint32_t)(CMP_CS_CMP0M | CMP_CS_CMP0MSEL | CMP_CS_CMP0HST ); 
-        CMP_CS |= CS_CMP0M(cmp_operating_mode) | CS_CMP0MSEL(cmp_inverting_input) | CS_CMP0HST(output_hysteresis);
+        CMP_CS |= CS_CMP0M(operating_mode) | CS_CMP0MSEL(inverting_input) | CS_CMP0HST(output_hysteresis);
     }else{
         /* initialize comparator 1 mode */
         CMP_CS &= ~(uint32_t)(CMP_CS_CMP1M | CMP_CS_CMP1MSEL | CMP_CS_CMP1HST );
-        CMP_CS |= CS_CMP1M(cmp_operating_mode) | CS_CMP1MSEL(cmp_inverting_input) | CS_CMP1HST(output_hysteresis);
+        CMP_CS |= CS_CMP1M(operating_mode) | CS_CMP1MSEL(inverting_input) | CS_CMP1HST(output_hysteresis);
     }
 }
 
@@ -96,7 +90,7 @@ void cmp_mode_init(uint32_t cmp_periph, \
     \param[in]  cmp_periph
       \arg        CMP0: comparator 0
       \arg        CMP1: comparator 1
-    \param[in]  cmp_output 
+    \param[in]  output_slection 
       \arg        CMP_OUTPUT_NONE: output no selection
       \arg        CMP_OUTPUT_TIMER0BKIN: TIMER 0 break input
       \arg        CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture 
@@ -105,34 +99,32 @@ void cmp_mode_init(uint32_t cmp_periph, \
       \arg        CMP_OUTPUT_TIMER1OCPRECLR: TIMER 1 OCPRE_CLR input
       \arg        CMP_OUTPUT_TIMER2IC0: TIMER 2 channel0 input capture
       \arg        CMP_OUTPUT_TIMER2OCPRECLR: TIMER 2 OCPRE_CLR input
-    \param[in]  cmp_output_polarity 
+    \param[in]  output_polarity 
       \arg        CMP_OUTPUT_POLARITY_INVERTED: output is inverted
       \arg        CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted
     \param[out] none
     \retval     none
 */
-void cmp_output_init(uint32_t cmp_periph, \
-                     cmp_output_enum cmp_output_slection, \
-                     uint32_t cmp_output_polarity)
+void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity)
 {
+    /* initialize comparator 0 output */
     if(CMP0 == cmp_periph){
-        /* initialize comparator 0 output */
         CMP_CS &= ~(uint32_t)CMP_CS_CMP0OSEL;
-        CMP_CS |= CS_CMP0OSEL(cmp_output_slection);
+        CMP_CS |= CS_CMP0OSEL(output_slection);
         /* output polarity */
-        if(CMP_OUTPUT_POLARITY_INVERTED == cmp_output_polarity){
+        if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
             CMP_CS |= CMP_CS_CMP0PL;
-        }else{
+        }else{ 
             CMP_CS &= ~CMP_CS_CMP0PL;
         }
     }else{
         /* initialize comparator 1 output */
         CMP_CS &= ~(uint32_t)CMP_CS_CMP1OSEL;
-        CMP_CS |= CS_CMP1OSEL(cmp_output_slection);
+        CMP_CS |= CS_CMP1OSEL(output_slection);
         /* output polarity */
-        if(CMP_OUTPUT_POLARITY_INVERTED == cmp_output_polarity){
+        if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
             CMP_CS |= CMP_CS_CMP1PL;
-        }else{
+        }else{ 
             CMP_CS &= ~CMP_CS_CMP1PL;
         }
     }
@@ -227,8 +219,10 @@ void cmp_window_disable(void)
 void cmp_lock_enable(uint32_t cmp_periph)
 {
     if(CMP0 == cmp_periph){
+        /* lock CMP0 */
         CMP_CS |= CMP_CS_CMP0LK;
     }else{
+        /* lock CMP1 */
         CMP_CS |= CMP_CS_CMP1LK;
     }
 }

Librarys/GD32F1x0_Drivers/src/gd32f1x0_crc.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_crc.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_crc.c
+    \file  gd32f3x0_crc.c
     \brief CRC driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_crc.h"
+#include "gd32f3x0_crc.h"
 
 /*!
     \brief      deinit CRC calculation unit
@@ -49,6 +46,7 @@ void crc_deinit(void)
     CRC_IDATA = (uint32_t)0xFFFFFFFFU;
     CRC_DATA  = (uint32_t)0xFFFFFFFFU;
     CRC_FDATA = (uint32_t)0x00000000U;
+    CRC_POLY  = (uint32_t)0x04C11DB7U;
     CRC_CTL   = CRC_CTL_RST;   
 }
 
@@ -93,10 +91,10 @@ void crc_data_register_reset(void)
     \retval     32-bit value of the data register
 */
 uint32_t crc_data_register_read(void)
-{   
+{
     uint32_t data;
     data = CRC_DATA;
-    return (data);    
+    return (data);
 }
 
 /*!
@@ -106,10 +104,10 @@ uint32_t crc_data_register_read(void)
     \retval     8-bit value of the free data register
 */
 uint8_t crc_free_data_register_read(void)
-{   
+{
     uint8_t fdata;
     fdata = (uint8_t)CRC_FDATA;
-    return (fdata);    
+    return (fdata);
 }
 
 /*!
@@ -120,7 +118,7 @@ uint8_t crc_free_data_register_read(void)
 */
 void crc_free_data_register_write(uint8_t free_data)
 {
-    CRC_FDATA = (uint32_t)free_data;    
+    CRC_FDATA = (uint32_t)free_data;
 }
 
 /*!
@@ -151,6 +149,35 @@ void crc_input_data_reverse_config(uint32_t data_reverse)
     CRC_CTL |= (uint32_t)data_reverse;
 }
 
+/*!
+    \brief      configure the CRC size of polynomial function
+    \param[in]  poly_size: size of polynomial
+                only one parameter can be selected which is shown as below:
+      \arg        CRC_CTL_PS_32: 32-bit polynomial for CRC calculation
+      \arg        CRC_CTL_PS_16: 16-bit polynomial for CRC calculation
+      \arg        CRC_CTL_PS_8: 8-bit polynomial for CRC calculation
+      \arg        CRC_CTL_PS_7: 7-bit polynomial for CRC calculation
+    \param[out] none
+    \retval     none
+*/
+void crc_polynomial_size_set(uint32_t poly_size)
+{
+    CRC_CTL &= (uint32_t)(~(CRC_CTL_PS));
+    CRC_CTL |= (uint32_t)poly_size;
+}
+
+/*!
+    \brief      configure the CRC polynomial value function
+    \param[in]  poly: configurable polynomial value
+    \param[out] none
+    \retval     none
+*/
+void crc_polynomial_set(uint32_t poly)
+{
+    CRC_POLY &= (uint32_t)(~CRC_POLY_POLY);
+    CRC_POLY = poly;
+}
+
 /*!
     \brief      CRC calculate a 32-bit data
     \param[in]  sdata: specify 32-bit data
@@ -160,7 +187,7 @@ void crc_input_data_reverse_config(uint32_t data_reverse)
 uint32_t crc_single_data_calculate(uint32_t sdata)
 {
     CRC_DATA = sdata;
-    return (CRC_DATA);
+    return(CRC_DATA);
 }
 
 /*!

Librarys/GD32F3x0_Drivers/Source/gd32f3x0_ctc.c

@@ -0,0 +1,382 @@
+/*!
+    \file  gd32f3x0_ctc.c
+    \brief CTC driver
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f3x0_ctc.h"
+
+#define CTC_FLAG_MASK            ((uint32_t)0x00000700U)
+
+/*!
+    \brief      reset CTC clock trim controller
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ctc_deinit(void)
+{
+    /* reset CTC */
+    rcu_periph_reset_enable(RCU_CTCRST);
+    rcu_periph_reset_disable(RCU_CTCRST);
+}
+
+/*!
+    \brief      configure reference signal source polarity
+    \param[in]  polarity:
+                only one parameter can be selected which is shown as below:
+      \arg        CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge
+      \arg        CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge
+    \param[out] none
+    \retval     none
+*/
+void ctc_refsource_polarity_config(uint32_t polarity)
+{
+    CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL);
+    CTC_CTL1 |= (uint32_t)polarity;
+}
+
+/*!
+    \brief      select reference signal source
+    \param[in]  refs:
+                only one parameter can be selected which is shown as below:
+      \arg        CTC_REFSOURCE_GPIO: GPIO is selected
+      \arg        CTC_REFSOURCE_LXTAL: LXTAL is clock selected
+      \arg        CTC_REFSOURCE_USBSOF: USBSOF is selected
+    \param[out] none
+    \retval     none
+*/
+void ctc_refsource_signal_select(uint32_t refs)
+{
+    CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL);
+    CTC_CTL1 |= (uint32_t)refs;
+}
+
+/*!
+    \brief      configure reference signal source prescaler
+    \param[in]  prescaler:
+                only one parameter can be selected which is shown as below:
+      \arg        CTC_REFSOURCE_PSC_OFF: reference signal not divided
+      \arg        CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2
+      \arg        CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4
+      \arg        CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8
+      \arg        CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16
+      \arg        CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32
+      \arg        CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64
+      \arg        CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128
+    \param[out] none
+    \retval     none
+*/
+void ctc_refsource_prescaler_config(uint32_t prescaler)
+{
+    CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC);
+    CTC_CTL1 |= (uint32_t)prescaler;
+}
+
+/*!
+    \brief      configure clock trim base limit value
+    \param[in]  limit_value: 8-bit clock trim base limit value
+      \arg        0x00-0xFF
+    \param[out] none
+    \retval     none
+*/
+void ctc_clock_limit_value_config(uint8_t limit_value)
+{
+    CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM);
+    CTC_CTL1 |= CTL1_CKLIM(limit_value);
+}
+
+/*!
+    \brief      configure CTC counter reload value
+    \param[in]  reload_value: 16-bit CTC counter reload value
+      \arg        0x0000-0xFFFF
+    \param[out] none
+    \retval     none
+*/
+void ctc_counter_reload_value_config(uint16_t reload_value)
+{
+    CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE);
+    CTC_CTL1 |= (uint32_t)reload_value;
+}
+
+/*!
+    \brief      enable CTC trim counter
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ctc_counter_enable(void)
+{
+    CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN;
+}
+
+/*!
+    \brief      disable CTC trim counter
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ctc_counter_disable(void)
+{
+    CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN);
+}
+
+/*!
+    \brief      configure the IRC48M trim value
+    \param[in]  trim_value: 8-bit IRC48M trim value
+      \arg        0x00-0x3F
+    \param[out] none
+    \retval     none
+*/
+void ctc_irc48m_trim_value_config(uint8_t trim_value)
+{
+    /* clear TRIMVALUE bits */
+    CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE);
+    /* set TRIMVALUE bits */
+    CTC_CTL0 |= CTL0_TRIMVALUE(trim_value);
+}
+
+/*!
+    \brief      generate software reference source sync pulse
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ctc_software_refsource_pulse_generate(void)
+{
+    CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL;
+}
+
+/*!
+    \brief      configure hardware automatically trim mode
+    \param[in]  hardmode:
+                only one parameter can be selected which is shown as below:
+      \arg        CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable
+      \arg        CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable
+    \param[out] none
+    \retval     none
+*/
+void ctc_hardware_trim_mode_config(uint32_t hardmode)
+{
+    CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM);
+    CTC_CTL0 |= (uint32_t)hardmode;
+}
+
+/*!
+    \brief      read CTC counter capture value when reference sync pulse occurred
+    \param[in]  none
+    \param[out] none
+    \retval     the 16-bit CTC counter capture value
+*/
+uint16_t ctc_counter_capture_value_read(void)
+{
+    uint16_t capture_value = 0U;
+    capture_value = (uint16_t)GET_STAT_REFCAP(CTC_STAT);
+    return (capture_value);
+}
+
+/*!
+    \brief      read CTC trim counter direction when reference sync pulse occurred
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+      \arg        SET: CTC trim counter direction is down-counting
+      \arg        RESET: CTC trim counter direction is up-counting
+*/
+FlagStatus ctc_counter_direction_read(void)
+{
+    FlagStatus ret_status = RESET;
+    if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){
+        ret_status = SET;
+    }
+    return ret_status;
+}
+
+/*!
+    \brief      read CTC counter reload value
+    \param[in]  none
+    \param[out] none
+    \retval     the 16-bit CTC counter reload value
+*/
+uint16_t ctc_counter_reload_value_read(void)
+{
+    uint16_t reload_value = 0U;
+    reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE);
+    return (reload_value);
+}
+
+/*!
+    \brief      read the IRC48M trim value
+    \param[in]  none
+    \param[out] none
+    \retval     the 8-bit IRC48M trim value
+*/
+uint8_t ctc_irc48m_trim_value_read(void)
+{
+    uint8_t trim_value = 0U;
+    trim_value = (uint8_t)GET_CTL0_TRIMVALUE(CTC_CTL0);
+    return (trim_value);
+}
+
+/*!
+    \brief      enable the CTC interrupt
+    \param[in]  interrupt: CTC interrupt enable
+                one or more parameters can be selected which are shown as below:
+      \arg        CTC_INT_CKOK: clock trim OK interrupt enable
+      \arg        CTC_INT_CKWARN: clock trim warning interrupt enable
+      \arg        CTC_INT_ERR: error interrupt enable
+      \arg        CTC_INT_EREF: expect reference interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void ctc_interrupt_enable(uint32_t interrupt)
+{
+    CTC_CTL0 |= (uint32_t)interrupt; 
+}
+
+/*!
+    \brief      disable the CTC interrupt
+    \param[in]  interrupt: CTC interrupt enable source
+                one or more parameters can be selected which are shown as below:
+      \arg        CTC_INT_CKOK: clock trim OK interrupt enable
+      \arg        CTC_INT_CKWARN: clock trim warning interrupt enable
+      \arg        CTC_INT_ERR: error interrupt enable
+      \arg        CTC_INT_EREF: expect reference interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void ctc_interrupt_disable(uint32_t interrupt)
+{
+    CTC_CTL0 &= (uint32_t)(~(interrupt)); 
+}
+
+/*!
+    \brief      get CTC flag
+    \param[in]  flag: the CTC flag
+                only one parameter can be selected which is shown as below:
+      \arg        CTC_FLAG_CKOK: clock trim OK flag
+      \arg        CTC_FLAG_CKWARN: clock trim warning flag 
+      \arg        CTC_FLAG_ERR: error flag 
+      \arg        CTC_FLAG_EREF: expect reference flag
+      \arg        CTC_FLAG_CKERR: clock trim error bit
+      \arg        CTC_FLAG_REFMISS: reference sync pulse miss
+      \arg        CTC_FLAG_TRIMERR: trim value error bit
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus ctc_flag_get(uint32_t flag)
+{
+    FlagStatus ret_status = RESET;
+    
+    if(RESET != (CTC_STAT & flag)){
+        ret_status = SET;
+    }
+    return ret_status;
+}
+
+/*!
+    \brief      clear CTC flag
+    \param[in]  flag: the CTC flag
+                only one parameter can be selected which is shown as below:
+      \arg        CTC_FLAG_CKOK: clock trim OK flag
+      \arg        CTC_FLAG_CKWARN: clock trim warning flag 
+      \arg        CTC_FLAG_ERR: error flag 
+      \arg        CTC_FLAG_EREF: expect reference flag
+      \arg        CTC_FLAG_CKERR: clock trim error bit
+      \arg        CTC_FLAG_REFMISS: reference sync pulse miss
+      \arg        CTC_FLAG_TRIMERR: trim value error bit
+    \param[out] none
+    \retval     none
+*/
+void ctc_flag_clear(uint32_t flag)
+{
+    if(flag & CTC_FLAG_MASK){
+        CTC_INTC |= CTC_INTC_ERRIC;
+    }else{
+        CTC_INTC |= flag;
+    }
+}
+
+/*!
+    \brief      get CTC interrupt flag
+    \param[in]  interrupt: the CTC interrupt flag
+                only one parameter can be selected which is shown as below:
+      \arg        CTC_INT_FLAG_CKOK: clock trim OK interrupt
+      \arg        CTC_INT_FLAG_CKWARN: clock trim warning interrupt 
+      \arg        CTC_INT_FLAG_ERR: error interrupt 
+      \arg        CTC_INT_FLAG_EREF: expect reference interrupt
+      \arg        CTC_INT_FLAG_CKERR: clock trim error bit interrupt
+      \arg        CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt 
+      \arg        CTC_INT_FLAG_TRIMERR: trim value error interrupt
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus ctc_interrupt_flag_get(uint32_t interrupt)
+{
+    uint32_t ctc_int = 0U, intenable = 0U;
+    FlagStatus ret_status = RESET;
+
+    if(interrupt & CTC_FLAG_MASK){
+        intenable = CTC_CTL0 & CTC_INT_ERR;
+    }else{
+        intenable = CTC_CTL0 & interrupt;
+    }
+    ctc_int = CTC_STAT & interrupt;
+
+    if(ctc_int && intenable){
+        ret_status = SET;
+    }
+    return ret_status;
+}
+
+/*!
+    \brief      clear CTC interrupt flag
+    \param[in]  interrupt: the CTC interrupt flag
+                only one parameter can be selected which is shown as below:
+      \arg        CTC_INT_FLAG_CKOK: clock trim OK interrupt
+      \arg        CTC_INT_FLAG_CKWARN: clock trim warning interrupt 
+      \arg        CTC_INT_FLAG_ERR: error interrupt 
+      \arg        CTC_INT_FLAG_EREF: expect reference interrupt 
+      \arg        CTC_INT_FLAG_CKERR: clock trim error bit interrupt
+      \arg        CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt 
+      \arg        CTC_INT_FLAG_TRIMERR: trim value error interrupt
+    \param[out] none
+    \retval     none
+*/ 
+void ctc_interrupt_flag_clear(uint32_t interrupt)
+{
+    if(interrupt & CTC_FLAG_MASK){
+        CTC_INTC |= CTC_INTC_ERRIC;
+    }else{
+        CTC_INTC |= interrupt;
+    }
+}

Librarys/GD32F3x0_Drivers/Source/gd32f3x0_dac.c

@@ -0,0 +1,387 @@
+/*!
+    \file  gd32f3x0_dac.c
+    \brief DAC driver
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifdef GD32F350
+#include "gd32f3x0_dac.h"
+
+/*!
+    \brief      deinitialize DAC
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_deinit(void)
+{
+    rcu_periph_reset_enable(RCU_DACRST);
+    rcu_periph_reset_disable(RCU_DACRST);
+}
+
+/*!
+    \brief      enable DAC
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_enable(void)
+{
+    DAC_CTL |= DAC_CTL_DEN;
+}
+
+/*!
+    \brief      disable DAC
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_disable(void)
+{
+    DAC_CTL &= ~DAC_CTL_DEN;
+}
+
+/*!
+    \brief      enable DAC DMA
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_dma_enable(void)
+{
+    DAC_CTL |= DAC_CTL_DDMAEN;
+}
+
+/*!
+    \brief      disable DAC DMA
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_dma_disable(void)
+{
+    DAC_CTL &= ~DAC_CTL_DDMAEN;
+}
+
+/*!
+    \brief      enable DAC output buffer
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_output_buffer_enable(void)
+{
+    DAC_CTL &= ~DAC_CTL_DBOFF;
+}
+
+/*!
+    \brief      disable DAC output buffer
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_output_buffer_disable(void)
+{
+    DAC_CTL |= DAC_CTL_DBOFF;
+}
+
+/*!
+    \brief      enable DAC trigger
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_trigger_enable(void)
+{
+    DAC_CTL |= DAC_CTL_DTEN;
+}
+
+/*!
+    \brief      disable DAC trigger
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_trigger_disable(void)
+{
+    DAC_CTL &= ~DAC_CTL_DTEN;
+}
+
+/*!
+    \brief      enable DAC software trigger
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_software_trigger_enable(void)
+{
+    DAC_SWT |= DAC_SWT_SWTR;
+}
+
+/*!
+    \brief      disable DAC software trigger
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_software_trigger_disable(void)
+{
+    DAC_SWT &= ~DAC_SWT_SWTR;
+}
+
+/*!
+    \brief      enable DAC interrupt(DAC DMA underrun interrupt)
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_interrupt_enable(void)
+{
+    DAC_CTL |= DAC_CTL_DDUDRIE;
+}
+
+/*!
+    \brief      disable DAC interrupt(DAC DMA underrun interrupt)
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_interrupt_disable(void)
+{
+    DAC_CTL &= ~DAC_CTL_DDUDRIE;
+}
+
+/*!
+    \brief      set DAC tgigger source
+    \param[in]  triggersource: external triggers of DAC
+      \arg        DAC_TRIGGER_T1_TRGO: trigger source is TIMER1 TRGO
+      \arg        DAC_TRIGGER_T2_TRGO: trigger source is TIMER2 TRGO
+      \arg        DAC_TRIGGER_T5_TRGO: trigger source is TIMER5 TRGO
+      \arg        DAC_TRIGGER_T14_TRGO: trigger source is TIMER14 TRGO
+      \arg        DAC_TRIGGER_EXTI_9: trigger source is EXTI interrupt line9 event
+      \arg        DAC_TRIGGER_SOFTWARE: software trigger
+    \param[out] none
+    \retval     none
+*/
+void dac_trigger_source_config(uint32_t triggersource)
+{
+    DAC_CTL &= ~DAC_CTL_DTSEL;
+    DAC_CTL |= triggersource;
+}
+
+/*!
+    \brief      configure DAC wave mode
+    \param[in]  wave_mode
+      \arg        DAC_WAVE_DISABLE: wave disable
+      \arg        DAC_WAVE_MODE_LFSR: LFSR noise mode
+      \arg        DAC_WAVE_MODE_TRIANGLE: triangle noise mode
+    \param[out] none
+    \retval     none
+*/
+void dac_wave_mode_config(uint32_t wave_mode)
+{
+    DAC_CTL &= ~DAC_CTL_DWM;
+    DAC_CTL |= wave_mode;
+}
+
+/*!
+    \brief      configure DAC wave bit width
+    \param[in]  bit_width
+      \arg        DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
+      \arg        DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
+      \arg        DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
+      \arg        DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
+      \arg        DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
+      \arg        DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
+      \arg        DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
+      \arg        DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
+      \arg        DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
+      \arg        DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
+      \arg        DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
+      \arg        DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
+    \param[out] none
+    \retval     none
+*/
+void dac_wave_bit_width_config(uint32_t bit_width)
+{
+    DAC_CTL &= ~DAC_CTL_DWBW;
+    DAC_CTL |= bit_width;
+}
+
+/*!
+    \brief      configure DAC LFSR noise mode
+    \param[in]  unmask_bits
+      \arg        DAC_LFSR_BIT0: unmask the LFSR bit0
+      \arg        DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
+      \arg        DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
+      \arg        DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
+      \arg        DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
+      \arg        DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
+      \arg        DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
+      \arg        DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
+      \arg        DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
+      \arg        DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
+      \arg        DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
+      \arg        DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
+    \param[out] none
+    \retval     none
+*/
+void dac_lfsr_noise_config(uint32_t unmask_bits)
+{
+    DAC_CTL &= ~DAC_CTL_DWBW;
+    DAC_CTL |= unmask_bits;
+}
+
+/*!
+    \brief      configure DAC triangle noise mode
+    \param[in]  amplitude
+      \arg        DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
+      \arg        DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
+      \arg        DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
+      \arg        DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
+      \arg        DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
+      \arg        DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
+      \arg        DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
+      \arg        DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
+      \arg        DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
+      \arg        DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
+      \arg        DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
+      \arg        DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
+    \param[out] none
+    \retval     none
+*/
+void dac_triangle_noise_config(uint32_t amplitude)
+{
+    DAC_CTL &= ~DAC_CTL_DWBW;
+    DAC_CTL |= amplitude;
+}
+
+/*!
+    \brief      get DAC output value
+    \param[in]  none
+    \param[out] none
+    \retval     DAC output data
+*/
+uint16_t dac_output_value_get(void)
+{
+    uint16_t data = 0U;
+    data = (uint16_t)DAC_DO;
+    return data;
+}
+
+/*!
+    \brief      get the specified DAC flag(DAC DMA underrun flag)
+    \param[in]  none
+    \param[out] none
+    \retval     the state of dac bit(SET or RESET)
+*/
+FlagStatus dac_flag_get(void)
+{
+    /* check the DMA underrun flag */
+    if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear the specified DAC flag(DAC DMA underrun flag)
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_flag_clear(void)
+{
+    DAC_STAT |= DAC_STAT_DDUDR;
+}
+
+/*!
+    \brief      get the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
+    \param[in]  none
+    \param[out] none
+    \retval     the state of DAC interrupt flag(SET or RESET)
+*/
+FlagStatus dac_interrupt_flag_get(void)
+{
+    FlagStatus temp_flag = RESET;
+    uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
+    /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
+    ddudr_flag = DAC_STAT & DAC_STAT_DDUDR;
+    ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE;
+        if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
+        temp_flag = SET;
+    }
+    return temp_flag;
+}
+
+/*!
+    \brief      clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_interrupt_flag_clear(void)
+{
+    DAC_STAT |= DAC_STAT_DDUDR;
+}
+
+/*!
+    \brief      set DAC data holding register value
+    \param[in]  dac_align
+      \arg        DAC_ALIGN_8B_R: data right 8b alignment
+      \arg        DAC_ALIGN_12B_R: data right 12b alignment
+      \arg        DAC_ALIGN_12B_L: data left 12b alignment
+    \param[in]  data: data to be loaded
+    \param[out] none
+    \retval     none
+*/
+void dac_data_set(uint32_t dac_align, uint16_t data)
+{
+    switch(dac_align){
+        /* data right 12b alignment */
+        case DAC_ALIGN_12B_R:
+            DAC_R12DH = data;
+            break;
+        /* data left 12b alignment */
+        case DAC_ALIGN_12B_L:
+            DAC_L12DH = data;
+            break;
+        /* data right 8b alignment */
+        case DAC_ALIGN_8B_R:
+            DAC_R8DH = data;
+            break;
+        default:
+            break;
+    }
+}
+#endif /* GD32F350 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_dbg.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_dbg.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_dbg.c
+    \file  gd32f3x0_dbg.c
     \brief DBG driver
-    
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_dbg.h"
+#include "gd32f3x0_dbg.h"
 
 #define DBG_RESET_VAL       ((uint32_t)0x00000000U)   /*!< DBG reset value */
 
@@ -95,14 +92,16 @@ void dbg_low_power_disable(uint32_t dbg_low_power)
 
 /*!
     \brief      enable peripheral behavior when the mcu is in debug mode
-    \param[in]  dbg_periph: refer to dbg_periph_enum
-                only one parameter can be selected which is shown as below:
-      \arg        DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
-      \arg        DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
-      \arg        DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted(170_190 series only)
-      \arg        DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus when core is halted
-      \arg        DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16): hold TIMERx counter when core is halted
-      \arg        DBG_RTC_HOLD : hold RTC calendar and wakeup counter when core is halted
+    \param[in]  dbg_periph: refer to dbg_periph_enum 
+                only one parameter can be selected which are shown as below:
+      \arg        DBG_SLEEP_HOLD: keep debugger connection during sleep mode
+      \arg        DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
+      \arg        DBG_STANDBY_HOLD: keep debugger connection during standby mode
+      \arg        DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
+      \arg        DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
+      \arg        DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted
+      \arg        DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
+      \arg        DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
     \param[out] none
     \retval     none
 */
@@ -113,14 +112,16 @@ void dbg_periph_enable(dbg_periph_enum dbg_periph)
 
 /*!
     \brief      disable peripheral behavior when the mcu is in debug mode
-    \param[in]  dbg_periph: refer to dbg_periph_enum
-                only one parameter can be selected which is shown as below:
-      \arg        DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
-      \arg        DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
-      \arg        DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted(170_190 series only)
-      \arg        DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus when core is halted
-      \arg        DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16): hold TIMERx counter when core is halted
-      \arg        DBG_RTC_HOLD : hold RTC calendar and wakeup counter when core is halted
+    \param[in]  dbg_periph: refer to dbg_periph_enum 
+                only one parameter can be selected which are shown as below:
+      \arg        DBG_SLEEP_HOLD: keep debugger connection during sleep mode
+      \arg        DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
+      \arg        DBG_STANDBY_HOLD: keep debugger connection during standby mode
+      \arg        DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
+      \arg        DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
+      \arg        DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted
+      \arg        DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
+      \arg        DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
     \param[out] none
     \retval     none
 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_dma.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_dma.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_dma.c
+    \file  gd32f3x0_dma.c
     \brief DMA driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_dma.h"
+#include "gd32f3x0_dma.h"
 
 /*!
     \brief      deinitialize DMA a channel registers 
@@ -55,7 +52,7 @@ void dma_deinit(dma_channel_enum channelx)
     DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
     DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
     DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
-    DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
+    DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
 }
 
 /*!
@@ -68,14 +65,14 @@ void dma_struct_para_init(dma_parameter_struct* init_struct)
 {
     /* set the DMA struct with the default values */
     init_struct->periph_addr  = 0U;
-    init_struct->periph_width = 0U;
-    init_struct->periph_inc   = DMA_PERIPH_INCREASE_DISABLE;
+    init_struct->periph_width = 0U; 
+    init_struct->periph_inc   = (uint8_t)DMA_PERIPH_INCREASE_DISABLE;
     init_struct->memory_addr  = 0U;
     init_struct->memory_width = 0U;
-    init_struct->memory_inc   = DMA_MEMORY_INCREASE_DISABLE;
-    init_struct->direction    = DMA_PERIPHERAL_TO_MEMORY;
+    init_struct->memory_inc   = (uint8_t)DMA_MEMORY_INCREASE_DISABLE;
     init_struct->number       = 0U;
-    init_struct->priority     = DMA_PRIORITY_LOW;
+    init_struct->direction    = (uint8_t)DMA_PERIPHERAL_TO_MEMORY;
+    init_struct->priority     = (uint32_t)DMA_PRIORITY_LOW;
 }
 
 /*!
@@ -85,34 +82,37 @@ void dma_struct_para_init(dma_parameter_struct* init_struct)
       \arg        DMA_CHx(x=0..6)
     \param[in]  init_struct: the data needed to initialize DMA channel
                   periph_addr: peripheral base address
-                  periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
-                  periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE 
+                  periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT
+                  periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE 
                   memory_addr: memory base address
-                  memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
-                  memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
-                  direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
+                  memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT
+                  memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE
+                  direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL
                   number: the number of remaining data to be transferred by the DMA
-                  priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
+                  priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
     \param[out] none
     \retval     none
 */
 void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct)
 {
     uint32_t ctl;
+    
+    dma_channel_disable(channelx);
+    
     /* configure peripheral base address */
     DMA_CHPADDR(channelx) = init_struct->periph_addr;
-
+    
     /* configure memory base address */
     DMA_CHMADDR(channelx) = init_struct->memory_addr;
-
+    
     /* configure the number of remaining data to be transferred */
-    DMA_CHCNT(channelx) = init_struct->number;
-
-    /* configure peripheral transfer width,memory transfer width, */
+    DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK);
+    
+    /* configure peripheral transfer width,memory transfer width,channel priotity */
     ctl = DMA_CHCTL(channelx);
     ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
     ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority);
-    DMA_CHCTL(channelx)=ctl;
+    DMA_CHCTL(channelx) = ctl;
 
     /* configure peripheral increasing mode */
     if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){
@@ -127,22 +127,22 @@ void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct)
     }else{
         DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
     }
-
+    
     /* configure the direction of  data transfer */
     if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){
         DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
     }else{
         DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
-    }
+    } 
 }
 
 /*!
     \brief      enable DMA circulation mode  
-    \param[in]  channelx: specify which DMA channel
+    \param[in]  channelx: specify which DMA channel to set 
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
-    \retval     none
+    \retval     none 
 */
 void dma_circulation_enable(dma_channel_enum channelx)
 {
@@ -151,11 +151,11 @@ void dma_circulation_enable(dma_channel_enum channelx)
 
 /*!
     \brief      disable DMA circulation mode  
-    \param[in]  channelx: specify which DMA channel
+    \param[in]  channelx: specify which DMA channel to set 
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
-    \retval     none
+    \retval     none 
 */
 void dma_circulation_disable(dma_channel_enum channelx)
 {
@@ -164,7 +164,7 @@ void dma_circulation_disable(dma_channel_enum channelx)
 
 /*!
     \brief      enable memory to memory mode
-    \param[in]  channelx: specify which DMA channel
+    \param[in]  channelx: specify which DMA channel to set 
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
@@ -177,7 +177,7 @@ void dma_memory_to_memory_enable(dma_channel_enum channelx)
 
 /*!
     \brief      disable memory to memory mode
-    \param[in]  channelx: specify which DMA channel
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
@@ -189,12 +189,12 @@ void dma_memory_to_memory_disable(dma_channel_enum channelx)
 }
 
 /*!
-    \brief      enable DMA channel 
-    \param[in]  channelx: specify which DMA channel
+    \brief      enable DMA channel
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
-    \retval     none
+    \retval     none 
 */
 void dma_channel_enable(dma_channel_enum channelx)
 {
@@ -202,12 +202,12 @@ void dma_channel_enable(dma_channel_enum channelx)
 }
 
 /*!
-    \brief      disable DMA channel 
-    \param[in]  channelx: specify which DMA channel
+    \brief      disable DMA channel
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
-    \retval     none
+    \retval     none 
 */
 void dma_channel_disable(dma_channel_enum channelx)
 {
@@ -215,13 +215,13 @@ void dma_channel_disable(dma_channel_enum channelx)
 }
 
 /*!
-    \brief      set DMA peripheral base address  
+    \brief      set DMA peripheral base address
     \param[in]  channelx: specify which DMA channel to set peripheral base address
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[in]  address: peripheral base address
     \param[out] none
-    \retval     none
+    \retval     none 
 */
 void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
 {
@@ -229,13 +229,13 @@ void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
 }
 
 /*!
-    \brief      set DMA Memory base address  
-    \param[in]  channelx: specify which DMA channel to set Memory base address
+    \brief      set DMA memory base address
+    \param[in]  channelx: specify which DMA channel to set memory base address
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
-    \param[in]  address: Memory base address
+    \param[in]  address: memory base address
     \param[out] none
-    \retval     none
+    \retval     none 
 */
 void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
 {
@@ -243,7 +243,7 @@ void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
 }
 
 /*!
-    \brief      set the number of remaining data to be transferred by the DMA  
+    \brief      set the number of remaining data to be transferred by the DMA
     \param[in]  channelx: specify which DMA channel to set number
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
@@ -253,16 +253,16 @@ void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
 */
 void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number)
 {
-    DMA_CHCNT(channelx) = number;
+    DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK);
 }
 
 /*!
-    \brief      get the number of remaining data to be transferred by the DMA  
+    \brief      get the number of remaining data to be transferred by the DMA
     \param[in]  channelx: specify which DMA channel to set number
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
-    \retval     uint32_t: the number of remaining data to be transferred by the DMA
+    \retval     the number of remaining data to be transferred by the DMA
 */
 uint32_t dma_transfer_number_get(dma_channel_enum channelx)
 {
@@ -270,22 +270,23 @@ uint32_t dma_transfer_number_get(dma_channel_enum channelx)
 }
 
 /*!
-    \brief      configure priority level of DMA channel   
-    \param[in]  channelx: specify which DMA channel
+    \brief      configure priority level of DMA channel
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
-    \param[in]  priority: priority Level of this channel
+    \param[in]  priority: priority level of this channel
                 only one parameter can be selected which is shown as below:
       \arg        DMA_PRIORITY_LOW: low priority
       \arg        DMA_PRIORITY_MEDIUM: medium priority
       \arg        DMA_PRIORITY_HIGH: high priority
       \arg        DMA_PRIORITY_ULTRA_HIGH: ultra high priority
     \param[out] none
-    \retval     none
+    \retval     none 
 */
 void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
 {
     uint32_t ctl;
+    
     /* acquire DMA_CHxCTL register */
     ctl = DMA_CHCTL(channelx);
     /* assign regiser */
@@ -295,56 +296,58 @@ void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
 }
 
 /*!
-    \brief      configure transfer data size of memory 
-    \param[in]  channelx: specify which DMA channel
+    \brief      configure transfer data width of memory
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
-    \param[in]  msize: transfer data size of memory
+    \param[in]  mwidth: transfer data width of memory
                 only one parameter can be selected which is shown as below:
-      \arg        DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit
-      \arg        DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit
-      \arg        DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit
+      \arg        DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
+      \arg        DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
+      \arg        DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
     \param[out] none
     \retval     none
 */
-void dma_memory_width_config (dma_channel_enum channelx, uint32_t msize)
+void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth)
 {
     uint32_t ctl;
+    
     /* acquire DMA_CHxCTL register */
     ctl = DMA_CHCTL(channelx);
     /* assign regiser */
     ctl &= ~DMA_CHXCTL_MWIDTH;
-    ctl |= msize;
+    ctl |= mwidth;
     DMA_CHCTL(channelx) = ctl;
 }
 
 /*!
-    \brief      configure transfer data size of peripheral 
+    \brief      configure transfer data width of peripheral
     \param[in]  channelx: specify which DMA channel
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
-    \param[in]  msize: transfer data size of peripheral
+    \param[in]  pwidth: transfer data width of peripheral
                 only one parameter can be selected which is shown as below:
-      \arg        DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit
-      \arg        DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit
-      \arg        DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit
+      \arg        DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
+      \arg        DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
+      \arg        DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
     \param[out] none
     \retval     none
 */
-void dma_periph_width_config (dma_channel_enum channelx, uint32_t psize)
+void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth)
 {
     uint32_t ctl;
+    
     /* acquire DMA_CHxCTL register */
     ctl = DMA_CHCTL(channelx);
     /* assign regiser */
     ctl &= ~DMA_CHXCTL_PWIDTH;
-    ctl |= psize;
+    ctl |= pwidth;
     DMA_CHCTL(channelx) = ctl;
 }
 
 /*!
-    \brief      enable next address increasement algorithm of memory  
-    \param[in]  channelx: specify which DMA channel
+    \brief      enable next address increasement algorithm of memory
+    \param[in]  channelx: specify which DMA channel to set 
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
@@ -356,8 +359,8 @@ void dma_memory_increase_enable(dma_channel_enum channelx)
 }
 
 /*!
-    \brief      disable next address increasement algorithm of memory  
-    \param[in]  channelx: specify which DMA channel
+    \brief      disable next address increasement algorithm of memory
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
@@ -369,8 +372,8 @@ void dma_memory_increase_disable(dma_channel_enum channelx)
 }
 
 /*!
-    \brief      enable next address increasement algorithm of peripheral  
-    \param[in]  channelx: specify which DMA channel
+    \brief      enable next address increasement algorithm of peripheral
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
@@ -382,8 +385,8 @@ void dma_periph_increase_enable(dma_channel_enum channelx)
 }
 
 /*!
-    \brief      disable next address increasement algorithm of peripheral  
-    \param[in]  channelx: specify which DMA channel
+    \brief      disable next address increasement algorithm of peripheral
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[out] none
@@ -395,8 +398,8 @@ void dma_periph_increase_disable(dma_channel_enum channelx)
 }
 
 /*!
-    \brief      configure the direction of  data transfer on the channel  
-    \param[in]  channelx: specify which DMA channel
+    \brief      configure the direction of data transfer on the channel
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[in]  direction: specify the direction of  data transfer
@@ -416,50 +419,86 @@ void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction
 }
 
 /*!
-    \brief      check DMA flag and interrupt enable bit is set or not 
+    \brief      check DMA flag is set or not
     \param[in]  channelx: specify which DMA channel to get flag
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[in]  flag: specify get which flag
                 only one parameter can be selected which is shown as below:
-      \arg        DMA_INT_FLAG_G: global interrupt flag of channel
-      \arg        DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
-      \arg        DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
-      \arg        DMA_INT_FLAG_ERR: error interrupt flag of channel
+      \arg        DMA_FLAG_G: global interrupt flag of channel
+      \arg        DMA_FLAG_FTF: full transfer finish flag of channel
+      \arg        DMA_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_FLAG_ERR: error flag of channel
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
+{
+    FlagStatus reval;
+
+    if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
+        reval = SET;
+    }else{
+        reval = RESET;
+    }
+    
+    return reval;
+}
+
+/*!
+    \brief      clear DMA a channel flag
+    \param[in]  channelx: specify which DMA channel to clear flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..6)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_FLAG_G: global interrupt flag of channel
+      \arg        DMA_FLAG_FTF: full transfer finish flag of channel
+      \arg        DMA_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_FLAG_ERR: error flag of channel
+    \param[out] none
+    \retval     none
+*/
+void dma_flag_clear(dma_channel_enum channelx, uint32_t flag)
+{
+    DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
+}
+
+/*!
+    \brief      check DMA flag and interrupt enable bit is set or not  
+    \param[in]  channelx: specify which DMA channel to get flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..6)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_INT_FLAG_FTF: transfer finish flag of channel
+      \arg        DMA_INT_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_INT_FLAG_ERR: error flag of channel
     \param[out] none
     \retval     FlagStatus: SET or RESET
 */
 FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
 {
     uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
-    uint32_t gif_check = 0x0FU, gif_enable = 0x0EU;
-
+    
     switch(flag){
         case DMA_INT_FLAG_FTF:
             interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
-            interrupt_flag = interrupt_flag >> ((channelx) * 4U);
             interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
             break;
         case DMA_INT_FLAG_HTF:
             interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
-            interrupt_flag = interrupt_flag >> ((channelx) * 4U);
             interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
             break;
         case DMA_INT_FLAG_ERR:
             interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
-            interrupt_flag = interrupt_flag >> ((channelx) * 4U);
-            interrupt_enable = DMA_CHCTL( channelx) & DMA_CHXCTL_ERRIE;
+            interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE;
             break;
-        case DMA_INT_FLAG_G:
-            interrupt_flag = DMA_INTF & DMA_FLAG_ADD(gif_check, channelx);
-            interrupt_flag = interrupt_flag >> ((channelx) * 4U);
-            interrupt_enable = DMA_CHCTL(channelx) & gif_enable;
-             break;    
         default:
             break;
-    }
-
-    if(interrupt_flag & interrupt_enable){
+        }
+    
+    if(interrupt_flag && interrupt_enable){
         return SET;
     }else{
         return RESET;
@@ -467,32 +506,34 @@ FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
 }
 
 /*!
-    \brief      clear DMA a channel flag
+    \brief      clear DMA a channel interrupt flag
     \param[in]  channelx: specify which DMA channel to clear flag
+                only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
     \param[in]  flag: specify get which flag
                 only one parameter can be selected which is shown as below:
       \arg        DMA_INT_FLAG_G: global interrupt flag of channel
-      \arg        DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
-      \arg        DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
-      \arg        DMA_INT_FLAG_ERR: error interrupt flag of channel
+      \arg        DMA_INT_FLAG_FTF: transfer finish flag of channel
+      \arg        DMA_INT_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_INT_FLAG_ERR: error flag of channel
     \param[out] none
     \retval     none
 */
 void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag)
 {
-    DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
+    DMA_INTC |= DMA_FLAG_ADD(flag,channelx);
 }
 
 /*!
     \brief      enable DMA interrupt
-    \param[in]  channelx: specify which DMA channel 
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
-    \param[in]  source: specify which interrupt to enbale
+    \param[in]  source: specify which interrupt to enable
                 only one parameter can be selected which is shown as below:
       \arg        DMA_INT_ERR: channel error interrupt
-      \arg        DMA_INT_HTF: channel transfer half complete interrupt
-      \arg        DMA_INT_FTF: channel transfer complete interrupt
+      \arg        DMA_INT_HTF: channel half transfer finish interrupt
+      \arg        DMA_INT_FTF: channel full transfer finish interrupt
     \param[out] none
     \retval     none
 */
@@ -503,14 +544,14 @@ void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source)
 
 /*!
     \brief      disable DMA interrupt
-    \param[in]  channelx: specify which DMA channel
+    \param[in]  channelx: specify which DMA channel to set
                 only one parameter can be selected which is shown as below:
       \arg        DMA_CHx(x=0..6)
-    \param[in]  source: specify which interrupt to disbale
+    \param[in]  source: specify which interrupt to disable
                 only one parameter can be selected which is shown as below:
       \arg        DMA_INT_ERR: channel error interrupt
-      \arg        DMA_INT_HTF: channel transfer half complete interrupt
-      \arg        DMA_INT_FTF: for channel transfer complete interrupt
+      \arg        DMA_INT_HTF: channel half transfer finish interrupt
+      \arg        DMA_INT_FTF: channel full transfer finish interrupt
     \param[out] none
     \retval     none
 */
@@ -518,49 +559,3 @@ void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source)
 {
     DMA_CHCTL(channelx) &= ~source;
 }
-
-/*!
-    \brief      check DMA flag is set or not
-    \param[in]  channelx: specify which DMA channel to get flag
-                only one parameter can be selected which is shown as below:
-      \arg        DMA_CHx(x=0..6)
-    \param[in]  flag: specify get which flag
-                only one parameter can be selected which is shown as below:
-      \arg        DMA_FLAG_G: global interrupt flag of channel
-      \arg        DMA_FLAG_FTF: full transfer finish flag of channel
-      \arg        DMA_FLAG_HTF: half transfer finish flag of channel
-      \arg        DMA_FLAG_ERR: error flag of channel
-    \param[out] none
-    \retval     FlagStatus: SET or RESET
-*/
-FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
-{
-    FlagStatus reval;
-
-    if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
-        reval = SET;
-    }else{
-        reval = RESET;
-    }
-
-    return reval;
-}
-
-/*!
-    \brief      clear DMA a channel flag
-    \param[in]  channelx: specify which DMA channel to clear flag
-                only one parameter can be selected which is shown as below:
-      \arg        DMA_CHx(x=0..6)
-    \param[in]  flag: specify get which flag
-                only one parameter can be selected which is shown as below:
-      \arg        DMA_FLAG_G: global interrupt flag of channel
-      \arg        DMA_FLAG_FTF: full transfer finish flag of channel
-      \arg        DMA_FLAG_HTF: half transfer finish flag of channel
-      \arg        DMA_FLAG_ERR: error flag of channel
-    \param[out] none
-    \retval     none
-*/
-void dma_flag_clear(dma_channel_enum channelx, uint32_t flag)
-{
-    DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
-}

Librarys/GD32F1x0_Drivers/src/gd32f1x0_exti.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_exti.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_exti.c
+    \file  gd32f3x0_exti.c
     \brief EXTI driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.1, firmware for GD32F3x0
 */
 
 /*
@@ -36,13 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_exti.h"
-
-#define EXTI_INTEN_RESET_VAL    ((uint32_t)0x0F900000U)
-#define EXTI_EVEN_RESET_VAL     ((uint32_t)0x00000000U)
-#define EXTI_RTEN_RESET_VAL     ((uint32_t)0x00000000U)
-#define EXTI_FTEN_RESET_VAL     ((uint32_t)0x00000000U)
-#define EXTI_SWIEV_RESET_VAL    ((uint32_t)0x00000000U)
+#include "gd32f3x0_exti.h"
 
 /*!
     \brief      deinitialize the EXTI
@@ -52,20 +43,19 @@ OF SUCH DAMAGE.
 */
 void exti_deinit(void)
 {
-    /* reset the value of the EXTI registers */
-    EXTI_INTEN = EXTI_INTEN_RESET_VAL;
-    EXTI_EVEN  = EXTI_EVEN_RESET_VAL;
-    EXTI_RTEN  = EXTI_RTEN_RESET_VAL;
-    EXTI_FTEN  = EXTI_FTEN_RESET_VAL;
-    EXTI_SWIEV = EXTI_SWIEV_RESET_VAL;
+    /* reset the value of all the EXTI registers */
+    EXTI_INTEN = (uint32_t)0x0F940000U;
+    EXTI_EVEN  = (uint32_t)0x00000000U;
+    EXTI_RTEN  = (uint32_t)0x00000000U;
+    EXTI_FTEN  = (uint32_t)0x00000000U;
+    EXTI_SWIEV = (uint32_t)0x00000000U;
 }
 
 /*!
-    \brief      initialize the EXTI
+    \brief      initialize the EXTI, enable the configuration of EXTI initialize
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..19,21,22): EXTI line x
     \param[in]  mode: interrupt or event mode, refer to exti_mode_enum
                 only one parameter can be selected which is shown as below:
       \arg        EXTI_INTERRUPT: interrupt mode
@@ -75,10 +65,13 @@ void exti_deinit(void)
       \arg        EXTI_TRIG_RISING: rising edge trigger
       \arg        EXTI_TRIG_FALLING: falling trigger
       \arg        EXTI_TRIG_BOTH: rising and falling trigger
+      \arg        EXTI_TRIG_NONE: without rising edge or falling edge trigger
     \param[out] none
     \retval     none
 */
-void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
+void exti_init(exti_line_enum linex, \
+                exti_mode_enum mode, \
+                exti_trig_type_enum trig_type)
 {
     /* reset the EXTI line x */
     EXTI_INTEN &= ~(uint32_t)linex;
@@ -112,6 +105,7 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr
         EXTI_RTEN |= (uint32_t)linex;
         EXTI_FTEN |= (uint32_t)linex;
         break;
+    case EXTI_TRIG_NONE:
     default:
         break;
     }
@@ -121,8 +115,7 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr
     \brief      enable the interrupts from EXTI line x
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..27): EXTI line x
     \param[out] none
     \retval     none
 */
@@ -132,39 +125,36 @@ void exti_interrupt_enable(exti_line_enum linex)
 }
 
 /*!
-    \brief      enable the events from EXTI line x
-    \param[in]  linex: EXTI line number, refer to exti_line_enum 
+    \brief      disable the interrupt from EXTI line x
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..27): EXTI line x
     \param[out] none
     \retval     none
 */
-void exti_event_enable(exti_line_enum linex)
+void exti_interrupt_disable(exti_line_enum linex)
 {
-    EXTI_EVEN |= (uint32_t)linex;
+    EXTI_INTEN &= ~(uint32_t)linex;
 }
 
 /*!
-    \brief      disable the interrupt from EXTI line x
+    \brief      enable the events from EXTI line x
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..27): EXTI line x
     \param[out] none
     \retval     none
 */
-void exti_interrupt_disable(exti_line_enum linex)
+void exti_event_enable(exti_line_enum linex)
 {
-    EXTI_INTEN &= ~(uint32_t)linex;
+    EXTI_EVEN |= (uint32_t)linex;
 }
 
 /*!
     \brief      disable the events from EXTI line x
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..27): EXTI line x
     \param[out] none
     \retval     none
 */
@@ -174,96 +164,92 @@ void exti_event_disable(exti_line_enum linex)
 }
 
 /*!
-    \brief      get EXTI lines flag
+    \brief      enable EXTI software interrupt event
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..19,21,22): EXTI line x
     \param[out] none
-    \retval     FlagStatus: status of flag (RESET or SET)
+    \retval     none
 */
-FlagStatus exti_flag_get(exti_line_enum linex)
+void exti_software_interrupt_enable(exti_line_enum linex)
 {
-    if(RESET != (EXTI_PD & (uint32_t)linex)){
-        return SET;
-    }else{
-        return RESET;
-    } 
+    EXTI_SWIEV |= (uint32_t)linex;
 }
 
 /*!
-    \brief      clear EXTI lines pending flag
+    \brief      disable EXTI software interrupt event
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..19,21,22): EXTI line x
     \param[out] none
     \retval     none
 */
-void exti_flag_clear(exti_line_enum linex)
+void exti_software_interrupt_disable(exti_line_enum linex)
 {
-    EXTI_PD = (uint32_t)linex;
+    EXTI_SWIEV &= ~(uint32_t)linex;
 }
 
 /*!
-    \brief      get EXTI lines flag when the interrupt flag is set
+    \brief      get EXTI line x pending flag
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..19,21,22): EXTI line x
     \param[out] none
     \retval     FlagStatus: status of flag (RESET or SET)
 */
-FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
+FlagStatus exti_flag_get(exti_line_enum linex)
 {
-    uint32_t flag_left, flag_right;
-    flag_left = EXTI_PD & (uint32_t)linex;
-    flag_right = EXTI_INTEN & (uint32_t)linex;
-    if((RESET != flag_left) && (RESET != flag_right)){
+    if(RESET != (EXTI_PD & (uint32_t)linex)){
         return SET;
     }else{
         return RESET;
-    }
+    } 
 }
 
 /*!
-    \brief      clear EXTI lines pending flag
+    \brief      clear EXTI line x pending flag
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..19,21,22): EXTI line x
     \param[out] none
     \retval     none
 */
-void exti_interrupt_flag_clear(exti_line_enum linex)
+void exti_flag_clear(exti_line_enum linex)
 {
     EXTI_PD = (uint32_t)linex;
 }
 
 /*!
-    \brief      enable EXTI software interrupt event
+    \brief      get EXTI line x flag when the interrupt flag is set
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..19,21,22): EXTI line x
     \param[out] none
-    \retval     none
+    \retval     FlagStatus: status of flag (RESET or SET)
 */
-void exti_software_interrupt_enable(exti_line_enum linex)
+FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
 {
-    EXTI_SWIEV |= (uint32_t)linex;
+    uint32_t flag_left, flag_right;
+    
+    flag_left = EXTI_PD & (uint32_t)linex;
+    flag_right = EXTI_INTEN & (uint32_t)linex;
+    
+    if((RESET != flag_left) && (RESET != flag_right)){
+        return SET;
+    }else{
+        return RESET;
+    }
 }
 
 /*!
-    \brief      disable EXTI software interrupt event
+    \brief      clear EXTI line x pending flag
     \param[in]  linex: EXTI line number, refer to exti_line_enum
                 only one parameter can be selected which is shown as below:
-      \arg        EXTI_x (x=0..19,21,22,25,27): EXTI line x (for GD32F130xx and GD32F150xx devices)
-      \arg        EXTI_x (x=0..17,19,21,22,25,27): EXTI line x (for GD32F170xx and GD32F190xx devices)
+      \arg        EXTI_x (x=0..19,21,22): EXTI line x
     \param[out] none
     \retval     none
 */
-void exti_software_interrupt_disable(exti_line_enum linex)
+void exti_interrupt_flag_clear(exti_line_enum linex)
 {
-    EXTI_SWIEV &= ~(uint32_t)linex;
+    EXTI_PD = (uint32_t)linex;
 }

Librarys/GD32F1x0_Drivers/src/gd32f1x0_fmc.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_fmc.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_fmc.c
+    \file  gd32f3x0_fmc.c
     \brief FMC driver
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,12 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_fmc.h"
-
-/* return the FMC state */
-static fmc_state_enum fmc_state_get(void);
-/* check FMC ready or not */
-static fmc_state_enum fmc_ready_wait(uint32_t timeout);
+#include "gd32f3x0_fmc.h"
 
 /* FMC main memory programming functions */
 
@@ -77,6 +69,7 @@ void fmc_lock(void)
 /*!
     \brief      set the wait state counter value
     \param[in]  wscnt: wait state counter value
+                only one parameter can be selected which is shown as below:
       \arg        WS_WSCNT_0: 0 wait state added
       \arg        WS_WSCNT_1: 1 wait state added
       \arg        WS_WSCNT_2: 2 wait state added
@@ -86,7 +79,7 @@ void fmc_lock(void)
 void fmc_wscnt_set(uint8_t wscnt)
 {
     uint32_t reg;
-
+    
     reg = FMC_WS;
     /* set the wait state counter value */
     reg &= ~FMC_WS_WSCNT;
@@ -101,8 +94,14 @@ void fmc_wscnt_set(uint8_t wscnt)
 */
 void fmc_wait_state_enable(void)
 {
+    /* unlock the main flash */
+    fmc_unlock();
+
     /* set the WSEN bit in register FMC_WSEN */
     FMC_WSEN |= FMC_WSEN_WSEN;
+
+    /* lock the main flash after operation */
+    fmc_lock();
 }
 
 /*!
@@ -113,24 +112,27 @@ void fmc_wait_state_enable(void)
 */
 void fmc_wait_state_disable(void)
 {
+    /* unlock the main flash */
+    fmc_unlock();
+
     /* reset the WSEN bit in register FMC_WSEN */
     FMC_WSEN &= ~FMC_WSEN_WSEN;
+
+    /* lock the main flash after operation */
+    fmc_lock();
 }
 
 /*!
-    \brief      FMC erase page
-    \param[in]  page_address: target page address
+    \brief      erase page
+    \param[in]  page_address: target page start address
     \param[out] none
-    \retval     state of FMC
-      \arg        FMC_READY: the operation has been completed
-      \arg        FMC_WPERR: erase/program protection error
-      \arg        FMC_TOERR: timeout error
+    \retval     fmc_state
 */
 fmc_state_enum fmc_page_erase(uint32_t page_address)
 {
     fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
-    if(FMC_READY == fmc_state){
+  
+    if(FMC_READY == fmc_state){ 
         /* start page erase */
         FMC_CTL |= FMC_CTL_PER;
         FMC_ADDR = page_address;
@@ -138,116 +140,103 @@ fmc_state_enum fmc_page_erase(uint32_t page_address)
 
         /* wait for the FMC ready */
         fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+    
         /* reset the PER bit */
         FMC_CTL &= ~FMC_CTL_PER;
     }
-
+    
     /* return the FMC state  */
     return fmc_state;
 }
 
 /*!
-    \brief      FMC erase whole chip
+    \brief      erase whole chip
     \param[in]  none
     \param[out] none
-    \retval     state of FMC
-      \arg        FMC_READY: the operation has been completed
-      \arg        FMC_WPERR: erase/program protection error
-      \arg        FMC_TOERR: timeout error
+    \retval     fmc_state
 */
 fmc_state_enum fmc_mass_erase(void)
 {
     fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+  
     if(FMC_READY == fmc_state){ 
         /* start chip erase */
         FMC_CTL |= FMC_CTL_MER; 
         FMC_CTL |= FMC_CTL_START;
-
+    
         /* wait for the FMC ready */
         fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
 
         /* reset the MER bit */
         FMC_CTL &= ~FMC_CTL_MER;
     }
-
+    
     /* return the fmc state  */
     return fmc_state;
 }
 
 /*!
-    \brief      FMC program a word at the corresponding address
+    \brief      program a word at the corresponding address
     \param[in]  address: address to program
     \param[in]  data: word to program
     \param[out] none
-    \retval     state of FMC
-      \arg        FMC_READY: the operation has been completed
-      \arg        FMC_PGERR: program error
-      \arg        FMC_WPERR: erase/program protection error
-      \arg        FMC_TOERR: timeout error
+    \retval     fmc_state
 */
 fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
 {
     fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+  
     if(FMC_READY == fmc_state){ 
         /* set the PG bit to start program */
-        FMC_CTL |= FMC_CTL_PG;
+        FMC_CTL |= FMC_CTL_PG; 
+  
         REG32(address) = data;
 
         /* wait for the FMC ready */
         fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+    
         /* reset the PG bit */
-        FMC_CTL &= ~FMC_CTL_PG;
-    }
-
+        FMC_CTL &= ~FMC_CTL_PG; 
+    } 
+  
     /* return the FMC state */
     return fmc_state;
 }
 
 /*!
-    \brief      FMC program a half word at the corresponding address
+    \brief      program a half word at the corresponding address
     \param[in]  address: address to program
     \param[in]  data: word to program
     \param[out] none
-    \retval     state of FMC
-      \arg        FMC_READY: the operation has been completed
-      \arg        FMC_PGERR: program error
-      \arg        FMC_WPERR: erase/program protection error
-      \arg        FMC_TOERR: timeout error
+    \retval     fmc_state
 */
 fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
 {
     fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
-    if(FMC_READY == fmc_state){
+  
+    if(FMC_READY == fmc_state){ 
         /* set the PG bit to start program */
-        FMC_CTL |= FMC_CTL_PG;
+        FMC_CTL |= FMC_CTL_PG; 
+  
         REG16(address) = data;
 
         /* wait for the FMC ready */
         fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+    
         /* reset the PG bit */
-        FMC_CTL &= ~FMC_CTL_PG;
-    }
-
+        FMC_CTL &= ~FMC_CTL_PG; 
+    } 
+  
     /* return the FMC state */
     return fmc_state;
 }
 
-#ifdef GD32F170_190
 /*!
-    \brief      FMC program a word at the corresponding address without erasing
+    \brief      program a word at the corresponding address without erasing
     \param[in]  address: address to program
     \param[in]  data: word to program
     \param[out] none
-    \retval     state of FMC
-      \arg        FMC_READY: the operation has been completed
-      \arg        FMC_WPERR: erase/program protection error
-      \arg        FMC_TOERR: timeout error
+    \retval     fmc_state
 */
 fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data)
 {
@@ -257,19 +246,19 @@ fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data)
     if(FMC_READY == fmc_state){
         /* set the PG bit to start program */
         FMC_CTL |= FMC_CTL_PG;
+
         REG32(address) = data;
 
         /* wait for the FMC ready */
         fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+    
         /* reset the PG bit */
         FMC_CTL &= ~FMC_CTL_PG;
     }
-
+  
     /* return the FMC state */
     return fmc_state;
 }
-#endif /* GD32F170_190 */
 
 /* FMC option bytes programming functions */
 
@@ -319,15 +308,12 @@ void ob_reset(void)
                 programmer must ensure FMC & option byte are both unlocked before calling this function
     \param[in]  none
     \param[out] none
-    \retval     state of FMC
-      \arg        FMC_READY: the operation has been completed
-      \arg        FMC_PGERR: program error
-      \arg        FMC_TOERR: timeout error
-      \arg        FMC_OB_HSPC: option byte security protection code high
+    \retval     fmc_state
 */
 fmc_state_enum ob_erase(void)
 {
-    uint8_t fmc_spc;
+    uint16_t fmc_spc;
+    
     uint32_t fmc_plevel = ob_obstat_plevel_get();
     fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
 
@@ -337,7 +323,7 @@ fmc_state_enum ob_erase(void)
     }else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel){
         fmc_spc = FMC_LSPC;
     }else{
-        fmc_spc   = FMC_HSPC;
+        fmc_spc = FMC_HSPC;
         fmc_state = FMC_OB_HSPC;
     }
 
@@ -348,86 +334,110 @@ fmc_state_enum ob_erase(void)
 
         /* wait for the FMC ready */
         fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+    
         if(FMC_READY == fmc_state){
-            /* reset the OBER bit and enable the option bytes programming */
+            /* reset the OBER bit */
             FMC_CTL &= ~FMC_CTL_OBER;
+       
+            /* set the OBPG bit */
             FMC_CTL |= FMC_CTL_OBPG;
 
             /* restore the last get option byte security protection code */
             OB_SPC = fmc_spc;
+            OB_USER = OB_USER_DEFAULT;
 
             /* wait for the FMC ready */
             fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
-            /* reset the OBPG bit */
-            FMC_CTL &= ~FMC_CTL_OBPG;
+ 
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
+            }
         }else{
             if(FMC_TOERR != fmc_state){
-                /* reset the OBER bit */
-                FMC_CTL &= ~FMC_CTL_OBER;
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
             }
-        }
+        }  
     }
     /* return the FMC state */
     return fmc_state;
 }
 
 /*!
-    \brief      enable option byte write protection (OB_WP)
-    \param[in]  ob_wp: specify sector to be write protected
-                one or more parameters can be selected which are shown as below:
-      \arg        OB_WP_NONE: disable all write protection
-      \arg        OB_WP_x(x=0..15): write protect specify sector
-      \arg        OB_WP_ALL: write protect all sector
+    \brief      enable option byte write protection(OB_WP) depending on current option byte 
+    \param[in]  ob_wp: write protection configuration data
+                       setting the bit of ob_wp means enabling the corresponding sector write protection
     \param[out] none
-    \retval     state of FMC
-      \arg        FMC_READY: the operation has been completed
-      \arg        FMC_PGERR: program error
-      \arg        FMC_TOERR: timeout error
+    \retval     fmc_state
 */
-
 fmc_state_enum ob_write_protection_enable(uint16_t ob_wp)
 {
-    uint8_t i;
-    uint8_t op_byte[6];
+    uint8_t ob_wrp0, ob_wrp1;
+    ob_parm_struct ob_parm;
     fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-    for(i = 0U; i < 6U; i++){
-        op_byte[i] = OP_BYTE(i);
-    }
-    op_byte[4] = ~((uint8_t)(ob_wp & OB_LWP));
-    op_byte[5] = ~((uint8_t)((ob_wp & OB_HWP) >> 8));
-
-    if(FMC_READY == fmc_state){
-        /* start erase the option byte */
-        FMC_CTL |= FMC_CTL_OBER;
-        FMC_CTL |= FMC_CTL_START;
-
-        /* wait for the FMC ready */
-        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+    ob_parm_get(&ob_parm);
+    ob_wp   = (uint16_t)(~ob_wp);
+    ob_wrp0 = (uint8_t)(ob_wp & OB_LWP);
+    ob_wrp1 = (uint8_t)((ob_wp & OB_HWP) >> 8U);
+    
+    if(0xFFU == (uint8_t)OB_WP0){
+        if (0xFFU == (uint8_t)OB_WP1){
+            if(FMC_READY == fmc_state){
+                /* set the OBPG bit*/
+                FMC_CTL |= FMC_CTL_OBPG;
+
+                if(0xFFU != ob_wrp0){
+                    OB_WP0 = ob_wrp0 ;
+                    /* wait for the FMC ready */
+                    fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+                }
+                
+                if((FMC_READY == fmc_state) && (0xFFU != ob_wrp1)){
+                    OB_WP1 = ob_wrp1 ;
+                    /* wait for the FMC ready */
+                    fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+                }
+                
+                if(FMC_TOERR != fmc_state){
+                    /* reset the OBPG bit */
+                    FMC_CTL &= ~FMC_CTL_OBPG;
+                }
+            } 
+        }
+    }else{
         if(FMC_READY == fmc_state){
-            /* reset the OBER bit and enable the option bytes programming */
-            FMC_CTL &= ~FMC_CTL_OBER;
-            FMC_CTL |= FMC_CTL_OBPG;
-
-            for(i = 0U; i < 6U; i++){
-                OP_BYTE(i) = op_byte[i];
+            /* start erase the option byte */
+            FMC_CTL |= FMC_CTL_OBER;
+            FMC_CTL |= FMC_CTL_START;
+        
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        
+            if(FMC_READY == fmc_state){
+            
+                /* reset the OBER bit */
+                FMC_CTL &= ~FMC_CTL_OBER;
+          
+                /* enable the option bytes programming */
+                FMC_CTL |= FMC_CTL_OBPG;
+           
+                ob_value_modify(OB_WP_ADDR0, ob_wp ,&ob_parm);
                 /* wait for the FMC ready */
-                fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-                if(FMC_READY != fmc_state){
-                    break;
+                fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); 
+        
+                if(FMC_TOERR != fmc_state){
+                    /* reset the OBPG bit */
+                    FMC_CTL &= ~FMC_CTL_OBPG;
+                }
+            }else{
+                if(FMC_TOERR != fmc_state){
+                    /* reset the OBER bit */
+                    FMC_CTL &= ~FMC_CTL_OBER;
                 }
             }
-
-            /* reset the OBPG bit */
-            FMC_CTL &= ~FMC_CTL_OBPG;
-        }else{
-            /* reset the OBER bit */
-            FMC_CTL &= ~FMC_CTL_OBER;
         }
     }
-
     /* return the FMC state */
     return fmc_state;
 }
@@ -440,60 +450,57 @@ fmc_state_enum ob_write_protection_enable(uint16_t ob_wp)
       \arg        FMC_LSPC: low security protection
       \arg        FMC_HSPC: high security protection
     \param[out] none
-    \retval     state of FMC
-      \arg        FMC_READY: the operation has been completed
-      \arg        FMC_PGERR: program error
-      \arg        FMC_TOERR: timeout error
-      \arg        FMC_OB_HSPC: option byte security protection code high
+    \retval     fmc_state
 */
 fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
 {
-    uint8_t i;
-    uint8_t op_byte[6];
     fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-    for(i = 0U; i < 6U; i++){
-        op_byte[i] = OP_BYTE(i);
+    
+    ob_parm_struct ob_parm;
+    ob_parm_get(&ob_parm);
+
+    /* the OB_SPC byte cannot be reprogrammed if protection level is high */
+    if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()){
+        fmc_state = FMC_OB_HSPC;
     }
-    op_byte[0] = ob_spc;
 
     if(FMC_READY == fmc_state){
         /* start erase the option byte */
         FMC_CTL |= FMC_CTL_OBER;
         FMC_CTL |= FMC_CTL_START;
-
+    
         /* wait for the FMC ready */
         fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+    
         if(FMC_READY == fmc_state){
-            /* reset the OBER bit and enable the option bytes programming */
+        
+            /* reset the OBER bit */
             FMC_CTL &= ~FMC_CTL_OBER;
+      
+            /* enable the option bytes programming */
             FMC_CTL |= FMC_CTL_OBPG;
-
-            for(i = 0U; i < 6U; i++){
-                OP_BYTE(i) = op_byte[i];
-                /* wait for the FMC ready */
-                fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-                if(FMC_READY != fmc_state){
-                    break;
-                }
+       
+            ob_value_modify(OB_SPC_ADDR, (uint16_t)ob_spc ,&ob_parm);
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); 
+    
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
             }
-
-            /* reset the OBPG bit */
-            FMC_CTL &= ~FMC_CTL_OBPG;
         }else{
-            /* reset the OBER bit */
-            FMC_CTL &= ~FMC_CTL_OBER;
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBER bit */
+                FMC_CTL &= ~FMC_CTL_OBER;
+            }
         }
     }
-
     /* return the FMC state */
     return fmc_state;
 }
 
 /*!
-    \brief      program the FMC user option byte
-                this function can only clear the corresponding bits to be 0 rather than 1.
-                the function ob_erase is used to set all the bits to be 1.
+    \brief      program the FMC user option byte depending on current option byte
     \param[in]  ob_user: user option byte
                 one or more parameters (bitwise AND) can be selected which are shown as below:
       \arg        OB_FWDGT_HW: hardware free watchdog timer
@@ -503,21 +510,15 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
       \arg        OB_VDDA_DISABLE: disable VDDA monitor
       \arg        OB_SRAM_PARITY_ENABLE: enable sram parity check
     \param[out] none
-    \retval     state of FMC
-      \arg        FMC_READY: the operation has been completed
-      \arg        FMC_PGERR: program error
-      \arg        FMC_TOERR: timeout error
+    \retval     fmc_state
 */
 fmc_state_enum ob_user_write(uint8_t ob_user)
 {
-    uint8_t i;
-    uint8_t op_byte[6];
+    /* check whether FMC is ready or not */
     fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-    for(i = 0U; i < 6U; i++){
-        op_byte[i] = OP_BYTE(i);
-    }
-    op_byte[1] = (ob_user | OB_USER_MASK);
-
+    ob_parm_struct ob_parm;
+    ob_parm_get(&ob_parm);
+    
     if(FMC_READY == fmc_state){
         /* start erase the option byte */
         FMC_CTL |= FMC_CTL_OBER;
@@ -525,77 +526,97 @@ fmc_state_enum ob_user_write(uint8_t ob_user)
 
         /* wait for the FMC ready */
         fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+    
         if(FMC_READY == fmc_state){
-            /* reset the OBER bit and enable the option bytes programming */
+            /* reset the OBER bit */
             FMC_CTL &= ~FMC_CTL_OBER;
+       
+            /* set the OBPG bit */
             FMC_CTL |= FMC_CTL_OBPG;
 
-            for(i = 0U; i < 6U; i++){
-                OP_BYTE(i) = op_byte[i];
-                /* wait for the FMC ready */
-                fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-                if(FMC_READY != fmc_state){
-                    break;
-                }
-            }
+            /* restore the last get option byte security protection code */
+            ob_value_modify(OB_USER_ADDR, (uint16_t)ob_user, &ob_parm);
 
-            /* reset the OBPG bit */
-            FMC_CTL &= ~FMC_CTL_OBPG;
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+ 
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
+            }
         }else{
-            /* reset the OBER bit */
-            FMC_CTL &= ~FMC_CTL_OBER;
-        }
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
+            }
+        }  
     }
-
     /* return the FMC state */
     return fmc_state;
 }
 
 /*!
     \brief      program the FMC data option byte
+    \param[in]  address: OB_DATA_ADDR0 or OB_DATA_ADDR1
+                only one parameter can be selected which is shown as below:
+      \arg        OB_DATA_ADDR0: option byte data address 0
+      \arg        OB_DATA_ADDR1: option byte data address 1
     \param[in]  data: the byte to be programmed
     \param[out] none
     \retval     fmc_state
 */
-fmc_state_enum ob_data_program(uint16_t ob_data)
-{
-    uint8_t i;
-    uint8_t op_byte[6];
+fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
+{   
     fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-    for(i = 0U; i < 6U; i++){
-        op_byte[i] = OP_BYTE(i);
-    }
-    op_byte[2] = (uint8_t)(ob_data & OB_LDATA);
-    op_byte[3] = (uint8_t)((ob_data & OB_HDATA) >> 8);
-
-    if(FMC_READY == fmc_state){
-        /* start erase the option byte */
-        FMC_CTL |= FMC_CTL_OBER;
-        FMC_CTL |= FMC_CTL_START;
-
-        /* wait for the FMC ready */
-        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-
+    ob_parm_struct ob_parm;
+    ob_parm_get(&ob_parm);
+    if(0xFFU == REG8(address))
+    {
         if(FMC_READY == fmc_state){
-            /* reset the OBER bit and enable the option bytes programming */
-            FMC_CTL &= ~FMC_CTL_OBER;
-            FMC_CTL |= FMC_CTL_OBPG;
+            /* set the OBPG bit */
+            FMC_CTL |= FMC_CTL_OBPG; 
+             
+            REG16(address) = data ;
+        
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
+            }
+        }
+    }else{
+        if(FMC_READY == fmc_state){
+            /* start erase the option byte */
+            FMC_CTL |= FMC_CTL_OBER;
+            FMC_CTL |= FMC_CTL_START;
+        
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        
+            if(FMC_READY == fmc_state){
+            
+                /* reset the OBER bit */
+                FMC_CTL &= ~FMC_CTL_OBER;
+          
+                /* enable the option bytes programming */
+                FMC_CTL |= FMC_CTL_OBPG;
 
-            for(i = 0U; i < 6U; i++){
-                OP_BYTE(i) = op_byte[i];
+                ob_value_modify(address, (uint16_t)data ,&ob_parm);
                 /* wait for the FMC ready */
-                fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
-                if(FMC_READY != fmc_state){
-                    break;
+                fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); 
+        
+                if(FMC_TOERR != fmc_state){
+                    /* reset the OBPG bit */
+                    FMC_CTL &= ~FMC_CTL_OBPG;
+                }
+            }else{
+                if(FMC_TOERR != fmc_state){
+                    /* reset the OBER bit */
+                    FMC_CTL &= ~FMC_CTL_OBER;
                 }
             }
-
-            /* reset the OBPG bit */
-            FMC_CTL &= ~FMC_CTL_OBPG;
-        }else{
-            /* reset the OBER bit */
-            FMC_CTL &= ~FMC_CTL_OBER;
         }
     }
 
@@ -611,7 +632,7 @@ fmc_state_enum ob_data_program(uint16_t ob_data)
 */
 uint8_t ob_user_get(void)
 {
-    return (uint8_t)(FMC_OBSTAT >> 8);
+    return (uint8_t)(FMC_OBSTAT >> 8U);
 }
 
 /*!
@@ -622,7 +643,7 @@ uint8_t ob_user_get(void)
 */
 uint16_t ob_data_get(void)
 {
-    return (uint16_t)(FMC_OBSTAT >> 16);
+    return (uint16_t)(FMC_OBSTAT >> 16U);
 }
 
 /*!
@@ -644,7 +665,7 @@ uint16_t ob_write_protection_get(void)
 */
 uint32_t ob_obstat_plevel_get(void)
 {
-    return (FMC_OBSTAT & (FMC_OBSTAT_PLVL_BIT0 | FMC_OBSTAT_PLVL_BIT1));
+    return (FMC_OBSTAT & (FMC_OBSTAT_PLEVEL_BIT0 | FMC_OBSTAT_PLEVEL_BIT1));
 }
 
 /* FMC interrupts and flags management functions */
@@ -652,8 +673,8 @@ uint32_t ob_obstat_plevel_get(void)
     \brief      enable FMC interrupt
     \param[in]  interrupt: the FMC interrupt source
                 one or more parameters can be selected which are shown as below:
-      \arg        FMC_INT_END: FMC end of operation interrupt
-      \arg        FMC_INT_ERR: FMC error interrupt
+      \arg        FMC_INTEN_END: FMC end of operation interrupt
+      \arg        FMC_INTEN_ERR: FMC error interrupt
     \param[out] none
     \retval     none
 */
@@ -666,8 +687,8 @@ void fmc_interrupt_enable(uint32_t interrupt)
     \brief      disable FMC interrupt
     \param[in]  interrupt: the FMC interrupt source
                 one or more parameters can be selected which are shown as below:
-      \arg        FMC_INT_END: FMC end of operation interrupt
-      \arg        FMC_INT_ERR: FMC error interrupt
+      \arg        FMC_INTEN_END: FMC end of operation interrupt
+      \arg        FMC_INTEN_ERR: FMC error interrupt
     \param[out] none
     \retval     none
 */
@@ -695,13 +716,13 @@ FlagStatus fmc_flag_get(uint32_t flag)
         status = SET;
     }
     /* return the state of corresponding FMC flag */
-    return status;
+    return status; 
 }
 
 /*!
     \brief      clear the FMC pending flag by writing 1
     \param[in]  flag: clear FMC flag
-                one or more parameters can be selected which are shown as below:
+                only one parameter can be selected which is shown as below:
       \arg        FMC_FLAG_PGERR: FMC programming error flag
       \arg        FMC_FLAG_WPERR: FMC write protection error flag
       \arg        FMC_FLAG_END: fmc end of programming flag
@@ -711,16 +732,16 @@ FlagStatus fmc_flag_get(uint32_t flag)
 void fmc_flag_clear(uint32_t flag)
 {
     /* clear the flags */
-    FMC_STAT |= flag;
+    FMC_STAT = flag;
 }
 
 /*!
-    \brief      get FMC interrupt flag state
-    \param[in]  flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum
+    \brief      get flag set or reset
+    \param[in]  flag: check FMC flag
                 only one parameter can be selected which is shown as below:
-      \arg        FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit
-      \arg        FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit
-      \arg        FMC_INT_FLAG_END: FMC end of operation interrupt flag bit
+      \arg        FMC_FLAG_PGERR: FMC programming error flag
+      \arg        FMC_FLAG_WPERR: FMC write protection error flag
+      \arg        FMC_FLAG_END: FMC end of programming flag
     \param[out] none
     \retval     FlagStatus: SET or RESET
 */
@@ -732,23 +753,23 @@ FlagStatus fmc_interrupt_flag_get(uint32_t flag)
         status = SET;
     }
     /* return the state of corresponding FMC flag */
-    return status;
+    return status; 
 }
 
 /*!
-    \brief      clear FMC interrupt flag state
-    \param[in]  flag: FMC interrupt flags, refer to can_interrupt_flag_enum
-                one or more parameters can be selected which are shown as below:
-      \arg        FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit
-      \arg        FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit
-      \arg        FMC_INT_FLAG_END: FMC end of operation interrupt flag bit
+    \brief      clear the FMC pending flag by writing 1
+    \param[in]  flag: clear FMC flag
+                only one parameter can be selected which is shown as below:
+      \arg        FMC_FLAG_PGERR: FMC programming error flag
+      \arg        FMC_FLAG_WPERR: FMC write protection error flag
+      \arg        FMC_FLAG_END: fmc end of programming flag
     \param[out] none
     \retval     none
 */
 void fmc_interrupt_flag_clear(uint32_t flag)
 {
     /* clear the flags */
-    FMC_STAT |= flag;
+    FMC_STAT = flag;
 }
 
 /*!
@@ -757,7 +778,7 @@ void fmc_interrupt_flag_clear(uint32_t flag)
     \param[out] none
     \retval     fmc_state
 */
-static fmc_state_enum fmc_state_get(void)
+fmc_state_enum fmc_state_get(void)
 {
     fmc_state_enum fmc_state = FMC_READY;
   
@@ -768,7 +789,7 @@ static fmc_state_enum fmc_state_get(void)
             fmc_state = FMC_WPERR;
         }else{
             if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)){
-                fmc_state = FMC_PGERR;
+                fmc_state = FMC_PGERR; 
             }
         }
     }
@@ -782,10 +803,10 @@ static fmc_state_enum fmc_state_get(void)
     \param[out] none
     \retval     fmc_state
 */
-static fmc_state_enum fmc_ready_wait(uint32_t timeout)
+fmc_state_enum fmc_ready_wait(uint32_t timeout)
 {
     fmc_state_enum fmc_state = FMC_BUSY;
-
+  
     /* wait for FMC ready */
     do{
         /* get FMC state */
@@ -799,3 +820,69 @@ static fmc_state_enum fmc_ready_wait(uint32_t timeout)
     /* return the FMC state */
     return fmc_state;
 }
+
+/*!
+    \brief      get current option byte value
+    \param[in]  ob_parm: pointer to option byte parameter struct
+    \param[out] ob_parm: pointer to option byte parameter struct
+    \retval     none
+*/
+void ob_parm_get(ob_parm_struct *ob_parm)
+{
+    /* get current option byte value */
+    ob_parm->spc = (uint8_t)OB_SPC;
+    ob_parm->user = (uint8_t)OB_USER;
+    ob_parm->data0 = (uint8_t)OB_DATA0;
+    ob_parm->data1 = (uint8_t)OB_DATA1;
+    ob_parm->wp0 = (uint8_t)OB_WP0;
+    ob_parm->wp1 = (uint8_t)OB_WP1;
+}
+
+/*!
+    \brief      modify the target option byte depending on the original value
+    \param[in]  address: target option byte address
+    \param[in]  value: target option byte value
+    \param[in]  ob_parm: pointer to option byte parameter struct
+    \param[out] none
+    \retval     none
+*/
+void ob_value_modify(uint32_t address, uint16_t value,ob_parm_struct *ob_parm)
+{
+    uint8_t spc, user, data0, data1, wp0, wp1;
+    /* store the original option bytes */
+    spc = ob_parm->spc;
+    user = ob_parm->user;
+    data0 = ob_parm->data0;
+    data1 = ob_parm->data1;
+    wp0 = ob_parm->wp0;
+    wp1 = ob_parm->wp1;
+    
+    /* bring in the target option byte */
+    if(OB_SPC_ADDR == address){
+        spc = (uint8_t)value;
+    }else if(OB_DATA_ADDR0 == address){
+        data0 = (uint8_t)value;
+    }else if(OB_DATA_ADDR1 == address){
+        data1 = (uint8_t)value;
+    }else if(OB_USER_ADDR == address){
+        user =  user & (uint8_t)value;
+    }else{
+        wp0 = wp0 & ((uint8_t) (value));
+        wp1 = wp1 & ((uint8_t) (value >> 8U));
+    }
+    /* basing on original value, modify the target option byte */
+    OB_SPC = spc;
+    OB_USER = user;
+    if(0xFFU != data0){
+        OB_DATA0 = data0;
+    }
+    if(0xFFU != data1){
+        OB_DATA1 = data1;
+    }
+    if(0xFFU != wp0){
+        OB_WP0 = wp0;
+    }
+    if(0xFFU != wp1){
+        OB_WP1 = wp1;  
+    }
+}

Librarys/GD32F1x0_Drivers/src/gd32f1x0_fwdgt.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_fwdgt.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_fwdgt.c
+    \file  gd32f3x0_fwdgt.c
     \brief FWDGT driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,28 +33,28 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_fwdgt.h"
+#include "gd32f3x0_fwdgt.h"
 
 /*!
-    \brief      disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
+    \brief      enable write access to FWDGT_PSC and FWDGT_RLD
     \param[in]  none
     \param[out] none
     \retval     none
 */
-void fwdgt_write_disable(void)
+void fwdgt_write_enable(void)
 {
-    FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
+    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
 }
 
 /*!
-    \brief      reload the counter of FWDGT
+    \brief      disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
     \param[in]  none
     \param[out] none
     \retval     none
 */
-void fwdgt_counter_reload(void)
+void fwdgt_write_disable(void)
 {
-    FWDGT_CTL = FWDGT_KEY_RELOAD;
+    FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
 }
 
 /*!
@@ -88,9 +85,9 @@ ErrStatus fwdgt_window_value_config(uint16_t window_value)
     /* wait until the WUD flag to be reset */
     do{
         flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
-    }while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
+    }while((--time_index > 0U) && (RESET != flag_status));
 
-    if ((uint32_t)RESET != flag_status){
+    if (RESET != flag_status){
         return ERROR; 
     }
     
@@ -99,10 +96,23 @@ ErrStatus fwdgt_window_value_config(uint16_t window_value)
     return SUCCESS;
 }
 
+/*!
+    \brief      reload the counter of FWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_counter_reload(void)
+{
+    FWDGT_CTL = FWDGT_KEY_RELOAD;
+}
+
+
 /*!
     \brief      configure counter reload value, and prescaler divider value
     \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
     \param[in]  prescaler_div: FWDGT prescaler value
+                only one parameter can be selected which is shown as below:
       \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
       \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
       \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
@@ -124,9 +134,9 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
     /* wait until the PUD flag to be reset */
     do{
         flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
-    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+    }while((--timeout > 0U) && (RESET != flag_status));
     
-    if ((uint32_t)RESET != flag_status){
+    if (RESET != flag_status){
         return ERROR;
     }
     
@@ -137,9 +147,9 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
     /* wait until the RUD flag to be reset */
     do{
         flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
-    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+    }while((--timeout > 0U) && (RESET != flag_status));
    
-    if ((uint32_t)RESET != flag_status){
+    if (RESET != flag_status){
         return ERROR;
     }
     
@@ -153,7 +163,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
 
 /*!
     \brief      get flag state of FWDGT
-    \param[in]  flag: flag to get 
+    \param[in]  flag: flag to get
+                only one parameter can be selected which is shown as below:
       \arg        FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
       \arg        FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
       \arg        FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
@@ -162,9 +173,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
 */
 FlagStatus fwdgt_flag_get(uint16_t flag)
 {
-    if(FWDGT_STAT & flag){
+  if(FWDGT_STAT & flag){
         return SET;
-    }
-    
+  }
     return RESET;
 }

Librarys/GD32F1x0_Drivers/src/gd32f1x0_gpio.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_gpio.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_gpio.c
+    \file  gd32f3x0_gpio.c
     \brief GPIO driver
-    
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_gpio.h"
+#include "gd32f3x0_gpio.h"
 
 /*!
     \brief      reset GPIO port
@@ -141,6 +138,7 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u
       \arg        GPIO_OSPEED_2MHZ: output max speed 2MHz 
       \arg        GPIO_OSPEED_10MHZ: output max speed 10MHz 
       \arg        GPIO_OSPEED_50MHZ: output max speed 50MHz
+      \arg        GPIO_OSPEED_MAX: GPIO very high output speed, max speed more than 50MHz
     \param[in]  pin: GPIO pin
                 one or more parameters can be selected which are shown as below:
       \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
@@ -150,26 +148,41 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u
 void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
 {
     uint16_t i;
-    uint32_t ospeed;
+    uint32_t ospeed0,ospeed1;
 
-    if(0x1U == otype){
+    if(GPIO_OTYPE_OD == otype){
         GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
     }else{
         GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
     }
 
     /* get the specified pin output speed bits value */
-    ospeed = GPIO_OSPD(gpio_periph);
-
-    for(i = 0U;i < 16U;i++){
-        if((1U << i) & pin){
-            /* clear the specified pin output speed bits */
-            ospeed &= ~GPIO_OSPEED_MASK(i);
-            /* set the specified pin output speed bits */
-            ospeed |= GPIO_OSPEED_SET(i,speed);
+    ospeed0 = GPIO_OSPD0(gpio_periph);
+
+    if(GPIO_OSPEED_MAX == speed){
+        ospeed1 = GPIO_OSPD1(gpio_periph);
+        
+        for(i = 0U;i < 16U;i++){
+            if((1U << i) & pin){
+                /* enable very high output speed function of the pin when the corresponding OSPDy(y=0..15) 
+                   is "11" (output max speed 50MHz) */
+                ospeed0 |= GPIO_OSPEED_SET(i,0x03);
+                ospeed1 |= (1U << i);
+            }
         }
+        GPIO_OSPD0(gpio_periph) = ospeed0;
+        GPIO_OSPD1(gpio_periph) = ospeed1;
+    }else{
+        for(i = 0U;i < 16U;i++){
+            if((1U << i) & pin){
+                /* clear the specified pin output speed bits */
+                ospeed0 &= ~GPIO_OSPEED_MASK(i);
+                /* set the specified pin output speed bits */
+                ospeed0 |= GPIO_OSPEED_SET(i,speed);
+            }
+        }
+        GPIO_OSPD0(gpio_periph) = ospeed0;
     }
-    GPIO_OSPD(gpio_periph) = ospeed;
 }
 
 /*!
@@ -310,22 +323,20 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph)
 
 /*!
     \brief      set GPIO alternate function
-    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,F) 
+    \param[in]  gpio_periph: GPIOx(x = A,B,C) 
                 only one parameter can be selected which is shown as below:
       \arg        GPIOx(x = A,B,C)
     \param[in]  alt_func_num: GPIO pin af function, please refer to specific device datasheet
                 only one parameter can be selected which is shown as below:
-      \arg        GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, I2S0, SPI1, SPI2, I2S2, CK_OUT, 
-                             SWDIO, SWCLK, USART0, CEC, IFRP, I2C0, I2C1, TSI, EVENTOUT
-      \arg        GPIO_AF_1: USART0, USART1, IFRP, CEC, TIMER2, TIMER14, I2C0, I2C1, I2C2, EVENTOUT
-      \arg        GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, EVENTOUT
-      \arg        GPIO_AF_3: TSI, I2C0, TIMER14, EVENTOUT
-      \arg        GPIO_AF_4(port A,B only): TIMER13, I2C0, I2C1, I2C2, USART1
-      \arg        GPIO_AF_5(port A,B only): TIMER15, TIMER16, SPI2, I2S2, I2C0, I2C1
-      \arg        GPIO_AF_6(port A,B only): SPI1, EVENTOUT 
-      \arg        GPIO_AF_7(port A only): CMP0, CMP1
-      \arg        GPIO_AF_9(port A,B only): CAN0, CAN1 (for GD32F170xx and GD32F190xx devices)
-      \arg        GPIO_AF_11: SLCD (for GD32F170xx and GD32F190xx devices)
+      \arg        GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, CEC,
+                              IFRP, TSI, CTC, I2C0, I2C1, SWDIO, SWCLK
+      \arg        GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1, IFRP, CEC
+      \arg        GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0
+      \arg        GPIO_AF_3: TSI, I2C0, TIMER14
+      \arg        GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13
+      \arg        GPIO_AF_5(port A,B only): TIMER15, TIMER16, USBFS, I2S0
+      \arg        GPIO_AF_6(port A,B only): CTC, SPI1
+      \arg        GPIO_AF_7(port A,B only): CMP0, CMP1
     \param[in]  pin: GPIO pin
                 one or more parameters can be selected which are shown as below:
       \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
@@ -384,7 +395,6 @@ void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
     lock = GPIO_LOCK(gpio_periph);
 }
 
-#ifdef GD32F170_190
 /*!
     \brief      toggle GPIO pin status
     \param[in]  gpio_periph: GPIOx(x = A,B,C,D,F) 
@@ -412,5 +422,3 @@ void gpio_port_toggle(uint32_t gpio_periph)
 {
     GPIO_TG(gpio_periph) = 0x0000FFFFU;
 }
-
-#endif /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_i2c.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_i2c.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_i2c.c
+    \file  gd32f3x0_i2c.c
     \brief I2C driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,20 +33,21 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_i2c.h"
+#include "gd32f3x0_i2c.h"
 
-#define I2CCLK_MAX                ((uint32_t)0x00000048U)             /*!< i2cclk max value */
-#define I2CCLK_MIN                ((uint32_t)0x00000002U)             /*!< i2cclk minimum value */
-#define I2C_FLAG_MASK             ((uint32_t)0x0000FFFFU)             /*!< i2c flag mask */
-#define I2C_ADDRESS_MASK          ((uint32_t)0x000003FFU)             /*!< i2c address mask */
-#define I2C_ADDRESS2_MASK         ((uint32_t)0x000000FEU)             /*!< the second i2c address mask */
+/* I2C register bit mask */
+#define I2CCLK_MAX                    ((uint32_t)0x0000003FU)             /*!< i2cclk maximum value */
+#define I2CCLK_MIN                    ((uint32_t)0x00000002U)             /*!< i2cclk minimum value */
+#define I2C_FLAG_MASK                 ((uint32_t)0x0000FFFFU)             /*!< i2c flag mask */
+#define I2C_ADDRESS_MASK              ((uint32_t)0x000003FFU)             /*!< i2c address mask */
+#define I2C_ADDRESS2_MASK             ((uint32_t)0x000000FEU)             /*!< the second i2c address mask */
 
 /* I2C register bit offset */
-#define STAT1_PECV_OFFSET         ((uint32_t)0x00000008U)                      /* bit offset of PECV in I2C_STAT1 */
+#define STAT1_PECV_OFFSET             ((uint32_t)8U)                      /* bit offset of PECV in I2C_STAT1 */
 
 /*!
     \brief      reset I2C
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -66,13 +64,6 @@ void i2c_deinit(uint32_t i2c_periph)
         rcu_periph_reset_enable(RCU_I2C1RST);
         rcu_periph_reset_disable(RCU_I2C1RST);
         break;
-#ifdef GD32F170_190
-    case I2C2:
-        /* reset I2C2 */
-        rcu_periph_reset_enable(RCU_I2C2RST);
-        rcu_periph_reset_disable(RCU_I2C2RST);
-        break;
-#endif /* GD32F170_190 */
     default:
         break;
     }
@@ -80,7 +71,7 @@ void i2c_deinit(uint32_t i2c_periph)
 
 /*!
     \brief      configure I2C clock
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
                           and fast mode plus (up to 1MHz)
     \param[in]  dutycyc: duty cycle in fast mode or fast mode plus
@@ -143,13 +134,28 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
         I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
         I2C_CKCFG(i2c_periph) |= clkc;
     }else{
-        /* illegal parameters */
+        /* fast mode plus, the maximum SCL rise time is 120ns */
+        I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U);
+        if(I2C_DTCY_2 == dutycyc){
+            /* I2C duty cycle is 2 */
+            clkc = (uint32_t)(pclk1/(clkspeed*3U));
+            I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
+        }else{
+            /* I2C duty cycle is 16/9 */
+            clkc = (uint32_t)(pclk1/(clkspeed*25U));
+            I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
+        }
+        /* enable fast mode */
+        I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
+        I2C_CKCFG(i2c_periph) |= clkc;
+        /* enable I2C fast mode plus */
+        I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN;
     }
 }
 
 /*!
     \brief      configure I2C address 
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  mode:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_I2CMODE_ENABLE: I2C mode
@@ -166,7 +172,7 @@ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat
 {
     /* SMBus/I2C mode selected */
     uint32_t ctl = 0U;
-
+    
     ctl = I2C_CTL0(i2c_periph);
     ctl &= ~(I2C_CTL0_SMBEN); 
     ctl |= mode;
@@ -178,7 +184,7 @@ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat
 
 /*!
     \brief      SMBus type selection
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  type:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_SMBUS_DEVICE: device
@@ -197,7 +203,7 @@ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
 
 /*!
     \brief      whether or not to send an ACK
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  ack:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_ACK_ENABLE: ACK will be sent
@@ -216,7 +222,7 @@ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
 
 /*!
     \brief      configure I2C position of ACK and PEC when receiving
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  pos:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
@@ -235,8 +241,8 @@ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
 }
 
 /*!
-    \brief      master send slave address
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \brief      master sends slave address
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  addr: slave address  
     \param[in]  trandirection: transmitter or receiver
                 only one parameter can be selected which is shown as below:
@@ -259,7 +265,7 @@ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandire
 
 /*!
     \brief      enable dual-address mode
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  addr: the second address in dual-address mode
     \param[out] none
     \retval     none
@@ -273,7 +279,7 @@ void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr)
 
 /*!
     \brief      disable dual-address mode
-    \param[in]  i2c_periph: I2Cx(x=0,1,2) 
+    \param[in]  i2c_periph: I2Cx(x=0,1) 
     \param[out] none
     \retval     none
 */
@@ -284,7 +290,7 @@ void i2c_dualaddr_disable(uint32_t i2c_periph)
 
 /*!
     \brief      enable I2C
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1) 
     \param[out] none
     \retval     none
 */
@@ -295,7 +301,7 @@ void i2c_enable(uint32_t i2c_periph)
 
 /*!
     \brief      disable I2C
-    \param[in]  i2c_periph: I2Cx(x=0,1,2) 
+    \param[in]  i2c_periph: I2Cx(x=0,1) 
     \param[out] none
     \retval     none
 */
@@ -306,7 +312,7 @@ void i2c_disable(uint32_t i2c_periph)
 
 /*!
     \brief      generate a START condition on I2C bus
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -317,7 +323,7 @@ void i2c_start_on_bus(uint32_t i2c_periph)
 
 /*!
     \brief      generate a STOP condition on I2C bus
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -328,7 +334,7 @@ void i2c_stop_on_bus(uint32_t i2c_periph)
 
 /*!
     \brief      I2C transmit data function
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  data: data of transmission 
     \param[out] none
     \retval     none
@@ -340,7 +346,7 @@ void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
 
 /*!
     \brief      I2C receive data function
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[out] none
     \retval     data of received
 */
@@ -351,8 +357,8 @@ uint8_t i2c_data_receive(uint32_t i2c_periph)
 
 /*!
     \brief      enable I2C DMA mode 
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
-    \param[in]  dmastate: 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  dmastate:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_DMA_ON: DMA mode enable
       \arg        I2C_DMA_OFF: DMA mode disable
@@ -365,14 +371,14 @@ void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
     uint32_t ctl = 0U;
     
     ctl = I2C_CTL1(i2c_periph);
-    ctl &= ~(I2C_CTL1_DMAON);
+    ctl &= ~(I2C_CTL1_DMAON); 
     ctl |= dmastate;
     I2C_CTL1(i2c_periph) = ctl;
 }
 
 /*!
     \brief      configure whether next DMA EOT is DMA last transfer or not
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  dmalast:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_DMALST_ON: next DMA EOT is the last transfer
@@ -393,7 +399,7 @@ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast)
 
 /*!
     \brief      whether to stretch SCL low when data is not ready in slave mode 
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  stretchpara:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
@@ -414,7 +420,7 @@ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
 
 /*!
     \brief      whether or not to response to a general call 
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  gcallpara:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_GCEN_ENABLE: slave will response to a general call
@@ -426,16 +432,16 @@ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
 {
     /* configure slave response to a general call enable or disable */
     uint32_t ctl = 0U;
-
+    
     ctl = I2C_CTL0(i2c_periph);
-    ctl &= ~(I2C_CTL0_GCEN);
+    ctl &= ~(I2C_CTL0_GCEN); 
     ctl |= gcallpara;
     I2C_CTL0(i2c_periph) = ctl;
 }
 
 /*!
     \brief      software reset I2C 
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  sreset:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_SRESET_SET: I2C is under reset
@@ -447,16 +453,16 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
 {
     /* modify CTL0 and configure software reset I2C state */
     uint32_t ctl = 0U;
-
+    
     ctl = I2C_CTL0(i2c_periph);
-    ctl &= ~(I2C_CTL0_SRESET);
+    ctl &= ~(I2C_CTL0_SRESET); 
     ctl |= sreset;
     I2C_CTL0(i2c_periph) = ctl;
 }
 
 /*!
     \brief      whether to enable I2C PEC calculation or not
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  pecpara:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_PEC_ENABLE: PEC calculation on 
@@ -468,7 +474,7 @@ void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
 {
     /* on/off PEC calculation */
     uint32_t ctl = 0U;
-
+    
     ctl = I2C_CTL0(i2c_periph);
     ctl &= ~(I2C_CTL0_PECEN);
     ctl |= pecstate;
@@ -477,7 +483,7 @@ void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
 
 /*!
     \brief      I2C whether to transfer PEC value
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  pecpara:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_PECTRANS_ENABLE: transfer PEC 
@@ -489,7 +495,7 @@ void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
 {
     /* whether to transfer PEC */
     uint32_t ctl = 0U;
-
+    
     ctl = I2C_CTL0(i2c_periph);
     ctl &= ~(I2C_CTL0_PECTRANS);
     ctl |= pecpara;
@@ -498,7 +504,7 @@ void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
 
 /*!
     \brief      get packet error checking value 
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[out] none
     \retval     PEC value
 */
@@ -509,7 +515,7 @@ uint8_t i2c_pec_value_get(uint32_t i2c_periph)
 
 /*!
     \brief      I2C issue alert through SMBA pin 
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  smbuspara:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_SALTSEND_ENABLE: issue alert through SMBA pin 
@@ -521,7 +527,7 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
 {
     /* issue alert through SMBA pin configure*/
     uint32_t ctl = 0U;
-
+    
     ctl = I2C_CTL0(i2c_periph);
     ctl &= ~(I2C_CTL0_SALT);
     ctl |= smbuspara;
@@ -530,7 +536,7 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
 
 /*!
     \brief      whether ARP is enabled under SMBus
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  arpstate:
                 only one parameter can be selected which is shown as below:
       \arg        I2C_ARP_ENABLE: enable ARP
@@ -542,7 +548,7 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
 {
     /* enable or disable I2C ARP protocol */
     uint32_t ctl = 0U;
-
+    
     ctl = I2C_CTL0(i2c_periph);
     ctl &= ~(I2C_CTL0_ARPEN);
     ctl |= arpstate;
@@ -551,7 +557,7 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
 
 /*!
     \brief      check I2C flag is set or not
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  flag: I2C flags, refer to i2c_flag_enum
                 only one parameter can be selected which is shown as below:
       \arg        I2C_FLAG_SBSEND: start condition send out 
@@ -575,10 +581,6 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
       \arg        I2C_FLAG_DEFSMB: default address of SMBus device
       \arg        I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
       \arg        I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode
-      \arg        I2C_FLAG_TFF: txframe fall flag (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_FLAG_TFR: txframe rise flag (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_FLAG_RFF: rxframe fall flag (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_FLAG_RFR: rxframe rise flag (only for GD32F170xx and GD32F190xx devices)
     \param[out] none
     \retval     FlagStatus: SET or RESET
 */
@@ -593,7 +595,7 @@ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
 
 /*!
     \brief      clear I2C flag
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  flag: I2C flags, refer to i2c_flag_enum
                 only one parameter can be selected which is shown as below:
       \arg       I2C_FLAG_SMBALT: SMBus Alert status
@@ -604,10 +606,6 @@ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
       \arg       I2C_FLAG_LOSTARB: arbitration lost in master mode   
       \arg       I2C_FLAG_BERR: a bus error   
       \arg       I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
-      \arg       I2C_FLAG_TFF: txframe fall flag (only for GD32F170xx and GD32F190xx devices)
-      \arg       I2C_FLAG_TFR: txframe rise flag (only for GD32F170xx and GD32F190xx devices)
-      \arg       I2C_FLAG_RFF: rxframe fall flag (only for GD32F170xx and GD32F190xx devices)
-      \arg       I2C_FLAG_RFR: rxframe rise flag (only for GD32F170xx and GD32F190xx devices)
     \param[out] none
     \retval     none
 */
@@ -624,16 +622,12 @@ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag)
 
 /*!
     \brief      enable I2C interrupt
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  interrupt: I2C interrupts, refer to i2c_interrupt_enum
                 only one parameter can be selected which is shown as below:
       \arg        I2C_INT_ERR: error interrupt enable 
       \arg        I2C_INT_EV: event interrupt enable 
       \arg        I2C_INT_BUF: buffer interrupt enable
-      \arg        I2C_INT_TFF: txframe fall interrupt enable (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_TFR: txframe rise interrupt enable (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_RFF: rxframe fall interrupt enable (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_RFR: rxframe rise interrupt enable (only for GD32F170xx and GD32F190xx devices)
     \param[out] none
     \retval     none
 */
@@ -644,16 +638,12 @@ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
 
 /*!
     \brief      disable I2C interrupt
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  interrupt: interrupt type 
                 only one parameter can be selected which is shown as below:
       \arg        I2C_INT_ERR: error interrupt enable 
       \arg        I2C_INT_EV: event interrupt enable 
-      \arg        I2C_INT_BUF: buffer interrupt enable 
-      \arg        I2C_INT_TFF: txframe fall interrupt enable (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_TFR: txframe rise interrupt enable (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_RFF: rxframe fall interrupt enable (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_RFR: rxframe rise interrupt enable (only for GD32F170xx and GD32F190xx devices)
+      \arg        I2C_INT_BUF: buffer interrupt enable  
     \param[out] none
     \retval     none
 */
@@ -664,7 +654,7 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
 
 /*!
     \brief      check I2C interrupt flag
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
+    \param[in]  i2c_periph: I2Cx(x=0,1)
     \param[in]  int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
                 only one parameter can be selected which is shown as below:
       \arg        I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
@@ -681,20 +671,16 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
       \arg        I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
       \arg        I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
       \arg        I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
-      \arg        I2C_INT_FLAG_TFF: txframe fall interrupt flag (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_FLAG_TFR: txframe rise interrupt flag (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_FLAG_RFF: rxframe fall interrupt flag (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_FLAG_RFR: rxframe rise interrupt flag (only for GD32F170xx and GD32F190xx devices)
     \param[out] none
     \retval     FlagStatus: SET or RESET
 */
 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag)
 {
     uint32_t intenable = 0U, flagstatus = 0U, bufie;
-
+    
     /* check BUFIE */
     bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
-
+    
     /* get the interrupt enable bit status */
     intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
     /* get the corresponding flag bit status */
@@ -707,7 +693,6 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i
             intenable = 0U;
         }
     }
-
     if((0U != flagstatus) && (0U != intenable)){
         return SET;
     }else{
@@ -717,8 +702,8 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i
 
 /*!
     \brief      clear I2C interrupt flag
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
-    \param[in]  int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
                 only one parameter can be selected which is shown as below:
       \arg        I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
       \arg        I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
@@ -728,10 +713,6 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i
       \arg        I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
       \arg        I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
       \arg        I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
-      \arg        I2C_INT_FLAG_TFF: txframe fall interrupt flag (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_FLAG_TFR: txframe rise interrupt flag (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_FLAG_RFF: rxframe fall interrupt flag (only for GD32F170xx and GD32F190xx devices)
-      \arg        I2C_INT_FLAG_RFR: rxframe rise interrupt flag (only for GD32F170xx and GD32F190xx devices)
     \param[out] none
     \retval     none
 */
@@ -746,51 +727,3 @@ void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_f
     }
 }
 
-#ifdef GD32F170_190
-
-/*!
-    \brief      enable SAM_V interface
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
-    \param[out] none
-    \retval     none
-*/
-void i2c_sam_enable(uint32_t i2c_periph)
-{
-    I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN;
-}
-
-/*!
-    \brief      disable SAM_V interface
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
-    \param[out] none
-    \retval     none
-*/
-void i2c_sam_disable(uint32_t i2c_periph)
-{
-    I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN);
-}
-
-/*!
-    \brief      enable SAM_V interface timeout detect
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
-    \param[out] none
-    \retval     none
-*/
-void i2c_sam_timeout_enable(uint32_t i2c_periph)
-{
-    I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN;
-}
-
-/*!
-    \brief      disable SAM_V interface timeout detect
-    \param[in]  i2c_periph: I2Cx(x=0,1,2)
-    \param[out] none
-    \retval     none
-*/
-void i2c_sam_timeout_disable(uint32_t i2c_periph)
-{
-    I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN);
-}
-
-#endif /* GD32F170_190 */
-

Librarys/GD32F1x0_Drivers/src/gd32f1x0_misc.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_misc.c

@@ -1,22 +1,44 @@
 /*!
-    \file  gd32f1x0_misc.c
+    \file  gd32f3x0_misc.c
     \brief MISC driver
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
-    Copyright (C) 2017 GigaDevice
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
 
-    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_misc.h"
+#include "gd32f3x0_misc.h"
 
 /*!
     \brief      set the priority group
     \param[in]  nvic_prigroup: the NVIC priority group
+                only one parameter can be selected which is shown as below:
       \arg        NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
       \arg        NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
       \arg        NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
@@ -39,35 +61,49 @@ void nvic_priority_group_set(uint32_t nvic_prigroup)
     \param[out] none
     \retval     none
 */
-void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, 
+void nvic_irq_enable(uint8_t nvic_irq, 
+                     uint8_t nvic_irq_pre_priority, 
                      uint8_t nvic_irq_sub_priority)
 {
     uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
+
     /* use the priority group value to get the temp_pre and the temp_sub */
-    if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE0_SUB4){
+    switch ((SCB->AIRCR) & (uint32_t)0x700U) {
+    case NVIC_PRIGROUP_PRE0_SUB4:
         temp_pre = 0U;
         temp_sub = 0x4U;
-    }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE1_SUB3){
+        break;
+    case NVIC_PRIGROUP_PRE1_SUB3:
         temp_pre = 1U;
         temp_sub = 0x3U;
-    }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE2_SUB2){
+        break;
+    case NVIC_PRIGROUP_PRE2_SUB2:
         temp_pre = 2U;
         temp_sub = 0x2U;
-    }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE3_SUB1){
+        break;
+    case NVIC_PRIGROUP_PRE3_SUB1:
         temp_pre = 3U;
         temp_sub = 0x1U;
-    }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE4_SUB0){
+        break;
+    case NVIC_PRIGROUP_PRE4_SUB0:
         temp_pre = 4U;
         temp_sub = 0x0U;
-    }else{
+        break;
+    default:
+        nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
+        temp_pre = 2U;
+        temp_sub = 0x2U;
+        break;
     }
+
     /* get the temp_priority to fill the NVIC->IP register */
     temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
     temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
     temp_priority = temp_priority << 0x04U;
     NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
+
     /* enable the selected IRQ */
-    NVIC->ISER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
+    NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
 }
 
 /*!
@@ -79,12 +115,13 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
 void nvic_irq_disable(uint8_t nvic_irq)
 {
     /* disable the selected IRQ.*/
-    NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
+    NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
 }
 
 /*!
     \brief      set the NVIC vector table base address
     \param[in]  nvic_vict_tab: the RAM or FLASH base address
+                only one parameter can be selected which is shown as below:
       \arg        NVIC_VECTTAB_RAM: RAM base address
       \are        NVIC_VECTTAB_FLASH: Flash base address
     \param[in]  offset: Vector Table offset
@@ -99,6 +136,7 @@ void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
 /*!
     \brief      set the state of the low power mode
     \param[in]  lowpower_mode: the low power mode state
+                only one parameter can be selected which is shown as below:
       \arg        SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power 
                     mode by exiting from ISR
       \arg        SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
@@ -115,6 +153,7 @@ void system_lowpower_set(uint8_t lowpower_mode)
 /*!
     \brief      reset the state of the low power mode
     \param[in]  lowpower_mode: the low power mode state
+                only one parameter can be selected which is shown as below:
       \arg        SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power 
                     mode by exiting from ISR
       \arg        SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
@@ -131,6 +170,7 @@ void system_lowpower_reset(uint8_t lowpower_mode)
 /*!
     \brief      set the systick clock source
     \param[in]  systick_clksource: the systick clock source needed to choose
+                only one parameter can be selected which is shown as below:
       \arg        SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
       \arg        SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
     \param[out] none

Librarys/GD32F1x0_Drivers/src/gd32f1x0_pmu.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_pmu.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_pmu.c
+    \file  gd32f3x0_pmu.c
     \brief PMU driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,8 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_pmu.h"
+#include "gd32f3x0_pmu.h"
+
 
 /*!
     \brief      reset PMU register
@@ -55,14 +53,14 @@ void pmu_deinit(void)
     \brief      select low voltage detector threshold
     \param[in]  lvdt_n:
                 only one parameter can be selected which is shown as below:
-      \arg        PMU_LVDT_0: voltage threshold is 2.2V (GD32F130_150) or 2.4V (GD32F170_190)
-      \arg        PMU_LVDT_1: voltage threshold is 2.3V (GD32F130_150) or 2.7V (GD32F170_190)
-      \arg        PMU_LVDT_2: voltage threshold is 2.4V (GD32F130_150) or 3.0V (GD32F170_190)
-      \arg        PMU_LVDT_3: voltage threshold is 2.5V (GD32F130_150) or 3.3V (GD32F170_190)
-      \arg        PMU_LVDT_4: voltage threshold is 2.6V (GD32F130_150) or 3.6V (GD32F170_190)
-      \arg        PMU_LVDT_5: voltage threshold is 2.7V (GD32F130_150) or 3.9V (GD32F170_190)
-      \arg        PMU_LVDT_6: voltage threshold is 2.8V (GD32F130_150) or 4.2V (GD32F170_190)
-      \arg        PMU_LVDT_7: voltage threshold is 2.9V (GD32F130_150) or 4.5V (GD32F170_190)
+      \arg        PMU_LVDT_0: voltage threshold is 2.1V
+      \arg        PMU_LVDT_1: voltage threshold is 2.3V
+      \arg        PMU_LVDT_2: voltage threshold is 2.4V
+      \arg        PMU_LVDT_3: voltage threshold is 2.6V
+      \arg        PMU_LVDT_4: voltage threshold is 2.7V
+      \arg        PMU_LVDT_5: voltage threshold is 2.9V
+      \arg        PMU_LVDT_6: voltage threshold is 3.0V
+      \arg        PMU_LVDT_7: voltage threshold is 3.1V
     \param[out] none
     \retval     none
 */
@@ -76,7 +74,23 @@ void pmu_lvd_select(uint32_t lvdt_n)
     PMU_CTL |= lvdt_n;
     /* enable LVD */
     PMU_CTL |= PMU_CTL_LVDEN;
+}
 
+/*!
+    \brief      select LDO output voltage
+                these bits set by software when the main PLL closed
+    \param[in]  ldo_output:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_LDOVS_LOW: LDO output voltage low mode
+      \arg        PMU_LDOVS_MID: LDO output voltage mid mode
+      \arg        PMU_LDOVS_HIGH: LDO output voltage high mode
+    \param[out] none
+    \retval     none
+*/
+void pmu_ldo_output_select(uint32_t ldo_output)
+{
+    PMU_CTL &= ~PMU_CTL_LDOVS;
+    PMU_CTL |= ldo_output;
 }
 
 /*!
@@ -91,18 +105,114 @@ void pmu_lvd_disable(void)
     PMU_CTL &= ~PMU_CTL_LVDEN;
 }
 
+/*!
+    \brief      enable low-driver mode in deep-sleep mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_lowdriver_mode_enable(void)
+{
+    PMU_CTL &= ~PMU_CTL_LDEN;  
+    PMU_CTL |= PMU_LOWDRIVER_ENABLE;
+}
+
+/*!
+    \brief      disable low-driver mode in deep-sleep mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_lowdriver_mode_disable(void)
+{
+    PMU_CTL &= ~PMU_CTL_LDEN;
+    PMU_CTL |= PMU_LOWDRIVER_DISABLE;
+}
+
+/*!
+    \brief      enable high-driver mode
+                this bit set by software only when IRC8M or HXTAL used as system clock
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_highdriver_mode_enable(void)
+{
+    PMU_CTL |= PMU_CTL_HDEN;
+}
+
+/*!
+    \brief      disable high-driver mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_highdriver_mode_disable(void)
+{
+    PMU_CTL &= ~PMU_CTL_HDEN;
+}
+
+/*!
+    \brief      switch high-driver mode
+                this bit set by software only when IRC8M or HXTAL used as system clock
+    \param[in]  highdr_switch:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch
+      \arg        PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch
+    \param[out] none
+    \retval     none
+*/
+void pmu_highdriver_switch_select(uint32_t highdr_switch)
+{
+    /* wait for HDRF flag to be set */
+    while(SET != pmu_flag_get(PMU_FLAG_HDR)){
+    }
+    PMU_CTL &= ~PMU_CTL_HDS;
+    PMU_CTL |= highdr_switch;
+}
+
+/*!
+    \brief      low-driver mode when use low power LDO
+    \param[in]  mode:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_NORMALDR_LOWPWR: normal-driver when use low power LDO
+      \arg        PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
+    \param[out] none
+    \retval     none
+*/
+void pmu_lowpower_driver_config(uint32_t mode)
+{
+    PMU_CTL &= ~PMU_CTL_LDLP;
+    PMU_CTL |= mode;
+}
+
+/*!
+    \brief      low-driver mode when use normal power LDO
+    \param[in]  mode:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_NORMALDR_NORMALPWR: normal-driver when use low power LDO
+      \arg        PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
+    \param[out] none
+    \retval     none
+*/
+void pmu_normalpower_driver_config(uint32_t mode)
+{
+    PMU_CTL &= ~PMU_CTL_LDNP;
+    PMU_CTL |= mode;
+}
+
 /*!
     \brief      PMU work at sleep mode
     \param[in]  sleepmodecmd:
                 only one parameter can be selected which is shown as below:
-      \arg        WFI_CMD:  use WFI command
-      \arg        WFE_CMD:  use WFE command
+      \arg        WFI_CMD: use WFI command
+      \arg        WFE_CMD: use WFE command
     \param[out] none
     \retval     none
 */
 void pmu_to_sleepmode(uint8_t sleepmodecmd)
 {
-    /* clear sleepdeep bit of Cortex-M3 system control register */
+    /* clear sleepdeep bit of Cortex-M4 system control register */
     SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
     
     /* select WFI or WFE command to enter sleep mode */
@@ -128,16 +238,16 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd)
 */
 void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
 {
-    static uint32_t reg_snap[ 4 ];
+    static uint32_t reg_snap[ 4 ];  
     /* clear stbmod and ldolp bits */
     PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
     
     /* set ldolp bit according to pmu_ldo */
     PMU_CTL |= ldo;
     
-    /* set sleepdeep bit of Cortex-M3 system control register */
+    /* set sleepdeep bit of Cortex-M4 system control register */
     SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-    
+
     reg_snap[ 0 ] = REG32( 0xE000E010U );
     reg_snap[ 1 ] = REG32( 0xE000E100U );
     reg_snap[ 2 ] = REG32( 0xE000E104U );
@@ -147,8 +257,8 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
     REG32( 0xE000E180U )  = 0XB7FFEF19U;
     REG32( 0xE000E184U )  = 0XFFFFFBFFU;
     REG32( 0xE000E188U )  = 0xFFFFFFFFU;
-    
-     /* select WFI or WFE command to enter deepsleep mode */
+  
+    /* select WFI or WFE command to enter deepsleep mode */
     if(WFI_CMD == deepsleepmodecmd){
         __WFI();
     }else{
@@ -156,13 +266,13 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
         __WFE();
         __WFE();
     }
-    
+
     REG32( 0xE000E010U ) = reg_snap[ 0 ] ; 
     REG32( 0xE000E100U ) = reg_snap[ 1 ] ;
     REG32( 0xE000E104U ) = reg_snap[ 2 ] ;
     REG32( 0xE000E108U ) = reg_snap[ 3 ] ;   
     
-    /* reset sleepdeep bit of Cortex-M3 system control register */
+    /* reset sleepdeep bit of Cortex-M4 system control register */
     SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 }
 
@@ -177,7 +287,7 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
 */
 void pmu_to_standbymode(uint8_t standbymodecmd)
 {
-    /* set sleepdeep bit of Cortex-M3 system control register */
+    /* set sleepdeep bit of Cortex-M4 system control register */
     SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 
     /* set stbmod bit */
@@ -198,12 +308,15 @@ void pmu_to_standbymode(uint8_t standbymodecmd)
     \brief      enable wakeup pin
     \param[in]  wakeup_pin:
                 one or more parameters can be selected which are shown as below:
-      \arg        PMU_WAKEUP_PIN0: wakeup pin 0
-      \arg        PMU_WAKEUP_PIN1: wakeup pin 1
+      \arg        PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) 
+      \arg        PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) 
+      \arg        PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5) 
+      \arg        PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) 
+      \arg        PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) 
     \param[out] none
     \retval     none
 */
-void pmu_wakeup_pin_enable(uint32_t wakeup_pin )
+void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
 {
     PMU_CS |= wakeup_pin;
 }
@@ -212,15 +325,17 @@ void pmu_wakeup_pin_enable(uint32_t wakeup_pin )
     \brief      disable wakeup pin
     \param[in]  wakeup_pin:
                 one or more parameters can be selected which are shown as below:
-      \arg        PMU_WAKEUP_PIN0: wakeup pin 0
-      \arg        PMU_WAKEUP_PIN1: wakeup pin 1
+      \arg        PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) 
+      \arg        PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) 
+      \arg        PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5) 
+      \arg        PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) 
+      \arg        PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
     \param[out] none
     \retval     none
 */
-void pmu_wakeup_pin_disable(uint32_t wakeup_pin )
+void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
 {
     PMU_CS &= ~(wakeup_pin);
-
 }
 
 /*!
@@ -256,35 +371,37 @@ void pmu_backup_write_disable(void)
 */
 void pmu_flag_clear(uint32_t flag_clear)
 {
-    switch(flag_clear){
-    case PMU_FLAG_RESET_WAKEUP:
+    if(RESET != (flag_clear & PMU_FLAG_RESET_WAKEUP)){
         /* reset wakeup flag */
         PMU_CTL |= PMU_CTL_WURST;
-        break;
-    case PMU_FLAG_RESET_STANDBY:
+    }
+    if(RESET != (flag_clear & PMU_FLAG_RESET_STANDBY)){
         /* reset standby flag */
         PMU_CTL |= PMU_CTL_STBRST;
-        break;
-    default :
-        break;
     }
 }
 
 /*!
     \brief      get flag state
-    \param[in]  flag:         
+    \param[in]  flag:
                 only one parameter can be selected which is shown as below:
-      \arg        PMU_FLAG_WAKEUP: wakeup flag 
-      \arg        PMU_FLAG_STANDBY: standby flag 
-      \arg        PMU_FLAG_LVD: lvd flag 
+      \arg        PMU_FLAG_WAKEUP: wakeup flag
+      \arg        PMU_FLAG_STANDBY: standby flag
+      \arg        PMU_FLAG_LVD: lvd flag
+      \arg        PMU_FLAG_LDOVSR: LDO voltage select ready flag
+      \arg        PMU_FLAG_HDR: high-driver ready flag
+      \arg        PMU_FLAG_HDSR: high-driver switch ready flag
+      \arg        PMU_FLAG_LDR: low-driver mode ready flag 
     \param[out] none
     \retval     FlagStatus SET or RESET
 */
-FlagStatus pmu_flag_get(uint32_t flag )
+FlagStatus pmu_flag_get(uint32_t flag)
 {
+    FlagStatus ret_status = RESET;
+    
     if(PMU_CS & flag){
-        return  SET;
-    }else{
-        return  RESET;
+        ret_status = SET;
     }
+    
+    return ret_status;
 }

Librarys/GD32F1x0_Drivers/src/gd32f1x0_rcu.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_rcu.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_rcu.c
+    \file  gd32f3x0_rcu.c
     \brief RCU driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,15 +33,16 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_rcu.h"
+#include "gd32f3x0_rcu.h"
 
-#define SEL_IRC8M                   0x00U
-#define SEL_HXTAL                   0x01U
-#define SEL_PLL                     0x02U
+/* define clock source */
+#define SEL_IRC8M                    ((uint32_t)0x00000000U)
+#define SEL_HXTAL                    ((uint32_t)0x00000001U)
+#define SEL_PLL                      ((uint32_t)0x00000002U)
 
 /* define startup timeout count */
-#define OSC_STARTUP_TIMEOUT         ((uint32_t)0xFFFFFU)
-#define LXTAL_STARTUP_TIMEOUT       ((uint32_t)0x3FFFFFFU)
+#define OSC_STARTUP_TIMEOUT          ((uint32_t)0x000FFFFFU)
+#define LXTAL_STARTUP_TIMEOUT        ((uint32_t)0x03FFFFFFU)
 
 /*!
     \brief      deinitialize the RCU
@@ -59,29 +57,22 @@ void rcu_deinit(void)
     while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
     }
     /* reset RCU */
-#ifdef GD32F130_150
     RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
                   RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
-#elif defined (GD32F170_190)
-    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
-                  RCU_CFG0_ADCPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
-#endif /* GD32F130_150 */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLPREDV);
-#ifdef GD32F130_150
-    RCU_CFG0 &= ~(RCU_CFG0_USBDPSC);
-#endif /* GD32F130_150 */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
+#if (defined(GD32F350))
+    RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC);
+    RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2);
+#endif /* GD32F350 */
     RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
-    RCU_CFG1 &= ~RCU_CFG1_HXTALPREDV;
-    RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_CECSEL | RCU_CFG2_ADCSEL);
-#ifdef GD32F130_150
-    RCU_CTL1 &= ~RCU_CTL1_IRC14MEN;
-#elif defined (GD32F170_190)
+    RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL);
+    RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
     RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
+    RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
     RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
-    RCU_CFG3 &= ~RCU_CFG3_CKOUT1SEL;
-    RCU_CFG3 &= ~RCU_CFG3_CKOUT1DIV;
-#endif /* GD32F130_150 */
+    RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN;
     RCU_INT = 0x00000000U;
+    RCU_ADDINT = 0x00000000U;
 }
 
 /*!
@@ -94,18 +85,16 @@ void rcu_deinit(void)
       \arg        RCU_TSI: TSI clock
       \arg        RCU_CFGCMP: CFGCMP clock
       \arg        RCU_ADC: ADC clock
-      \arg        RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock
-      \arg        RCU_SPIx (x=0,1,2): SPI clock
+      \arg        RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350)
+      \arg        RCU_SPIx (x=0,1): SPI clock
       \arg        RCU_USARTx (x=0,1): USART clock
-      \arg        RCU_SLCD: SLCD clock, only in GD32F170_190
       \arg        RCU_WWDGT: WWDGT clock
-      \arg        RCU_I2Cx (x=0,1,2): I2C clock
-      \arg        RCU_USBD: USBD clock, only in GD32F130_150
-      \arg        RCU_CANx (x=0,1): CAN clock, only in GD32F170_190
+      \arg        RCU_I2Cx (x=0,1): I2C clock
+      \arg        RCU_USBFS: USBFS clock (only for GD32F350)
       \arg        RCU_PMU: PMU clock
-      \arg        RCU_DAC: DAC clock
-      \arg        RCU_CEC: CEC clock
-      \arg        RCU_OPAIVREF: OPAIVREF clock, only in GD32F170_190
+      \arg        RCU_DAC: DAC clock (only for GD32F350)
+      \arg        RCU_CEC: CEC clock (only for GD32F350)
+      \arg        RCU_CTC: CTC clock
       \arg        RCU_RTC: RTC clock
     \param[out] none
     \retval     none
@@ -125,18 +114,16 @@ void rcu_periph_clock_enable(rcu_periph_enum periph)
       \arg        RCU_TSI: TSI clock
       \arg        RCU_CFGCMP: CFGCMP clock
       \arg        RCU_ADC: ADC clock
-      \arg        RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock
-      \arg        RCU_SPIx (x=0,1,2): SPI clock
+      \arg        RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350)
+      \arg        RCU_SPIx (x=0,1): SPI clock
       \arg        RCU_USARTx (x=0,1): USART clock
-      \arg        RCU_SLCD: SLCD clock, only in GD32F170_190
       \arg        RCU_WWDGT: WWDGT clock
-      \arg        RCU_I2Cx (x=0,1,2): I2C clock
-      \arg        RCU_USBD: USBD clock only in GD32F130_150
-      \arg        RCU_CANx (x=0,1): CAN clock, only in GD32F170_190
+      \arg        RCU_I2Cx (x=0,1): I2C clock
+      \arg        RCU_USBFS: USBFS clock (only for GD32F350)
       \arg        RCU_PMU: PMU clock
-      \arg        RCU_DAC: DAC clock
-      \arg        RCU_CEC: CEC clock
-      \arg        RCU_OPAIVREF: OPAIVREF clock, only in GD32F170_190
+      \arg        RCU_DAC: DAC clock (only for GD32F350)
+      \arg        RCU_CEC: CEC clock (only for GD32F350)
+      \arg        RCU_CTC: CTC clock
       \arg        RCU_RTC: RTC clock
     \param[out] none
     \retval     none
@@ -173,7 +160,6 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
 {
     RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
 }
-
 /*!
     \brief      reset the peripherals
     \param[in]  periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
@@ -182,18 +168,16 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
       \arg        RCU_TSIRST: reset TSI
       \arg        RCU_CFGCMPRST: reset CFGCMP
       \arg        RCU_ADCRST: reset ADC
-      \arg        RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER
-      \arg        RCU_SPIxRST (x=0,1,2): reset SPI
+      \arg        RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350)
+      \arg        RCU_SPIxRST (x=0,1): reset SPI
       \arg        RCU_USARTxRST (x=0,1): reset USART
-      \arg        RCU_SLCDRST: reset SLCD, only in GD32F170_190
       \arg        RCU_WWDGTRST: reset WWDGT
-      \arg        RCU_I2CxRST (x=0,1,2): reset I2C
-      \arg        RCU_USBDRST: reset USBD, only in GD32F130_150
-      \arg        RCU_CANxRST (x=0,1): reset CAN, only in GD32F170_190
+      \arg        RCU_I2CxRST (x=0,1): reset I2C
+      \arg        RCU_USBFSRST: reset USBFS (only for GD32F350)
       \arg        RCU_PMURST: reset PMU
-      \arg        RCU_DACRST: reset DAC
-      \arg        RCU_CECRST: reset CEC
-      \arg        RCU_OPAIVREFRST: reset OPAIVREF, only in GD32F170_190
+      \arg        RCU_DACRST: reset DAC (only for GD32F350)
+      \arg        RCU_CECRST: reset CEC (only for GD32F350)
+      \arg        RCU_CTCRST: reset CTC
     \param[out] none
     \retval     none
 */
@@ -210,18 +194,16 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
       \arg        RCU_TSIRST: reset TSI
       \arg        RCU_CFGCMPRST: reset CFGCMP
       \arg        RCU_ADCRST: reset ADC
-      \arg        RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER
+      \arg        RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350)
       \arg        RCU_SPIxRST (x=0,1,2): reset SPI
       \arg        RCU_USARTxRST (x=0,1): reset USART
-      \arg        RCU_SLCDRST: reset SLCD, only in GD32F170_190
       \arg        RCU_WWDGTRST: reset WWDGT
       \arg        RCU_I2CxRST (x=0,1,2): reset I2C
-      \arg        RCU_USBDRST: reset USBD, only in GD32F130_150
-      \arg        RCU_CANxRST (x=0,1): reset CAN, only in GD32F170_190
+      \arg        RCU_USBFSRST: reset USBFS (only for GD32F350)
       \arg        RCU_PMURST: reset PMU
-      \arg        RCU_DACRST: reset DAC
-      \arg        RCU_CECRST: reset CEC
-      \arg        RCU_OPAIVREFRST: reset OPAIVREF, only in GD32F170_190
+      \arg        RCU_DACRST: reset DAC (only for GD32F350)
+      \arg        RCU_CECRST: reset CEC (only for GD32F350)
+      \arg        RCU_CTCRST: reset CTC
     \param[out] none
     \retval     none
 */
@@ -231,7 +213,7 @@ void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
 }
 
 /*!
-    \brief      reset the BKP domain
+    \brief      reset the BKP
     \param[in]  none
     \param[out] none
     \retval     none
@@ -242,7 +224,7 @@ void rcu_bkp_reset_enable(void)
 }
 
 /*!
-    \brief      disable the BKP domain reset
+    \brief      disable the BKP reset
     \param[in]  none
     \param[out] none
     \retval     none
@@ -283,7 +265,7 @@ void rcu_system_clock_source_config(uint32_t ck_sys)
 */
 uint32_t rcu_system_clock_source_get(void)
 {
-    return (RCU_CFG0 & 0x0000000CU);
+    return (RCU_CFG0 & RCU_CFG0_SCSS);
 }
 
 /*!
@@ -349,13 +331,16 @@ void rcu_apb2_clock_config(uint32_t ck_apb2)
     \brief      configure the ADC clock prescaler selection
     \param[in]  ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum
                 only one parameter can be selected which is shown as below:
-      \arg        RCU_ADCCK_IRC14M: select CK_IRC14M as CK_ADC, only in GD32F130_150
-      \arg        RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC, only in GD32F170_190
-      \arg        RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC, only in GD32F170_190
+      \arg        RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC
+      \arg        RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC
       \arg        RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC
+      \arg        RCU_ADCCK_AHB_DIV3: select CK_AHB/3 as CK_ADC
       \arg        RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC
+      \arg        RCU_ADCCK_AHB_DIV5: select CK_AHB/5 as CK_ADC
       \arg        RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC
+      \arg        RCU_ADCCK_AHB_DIV7: select CK_AHB/7 as CK_ADC
       \arg        RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC
+      \arg        RCU_ADCCK_AHB_DIV9: select CK_AHB/9 as CK_ADC
     \param[out] none
     \retval     none
 */
@@ -363,18 +348,10 @@ void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc)
 {
     /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */
     RCU_CFG0 &= ~RCU_CFG0_ADCPSC;
-#ifdef GD32F130_150
-    RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
-#elif defined (GD32F170_190)
-    RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV);
-#endif /* GD32F130_150 */
+    RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2);
+
     /* set the ADC clock according to ck_adc */
     switch(ck_adc){
-#ifdef GD32F130_150
-    case RCU_ADCCK_IRC14M:
-        RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
-        break;
-#elif defined (GD32F170_190)
     case RCU_ADCCK_IRC28M_DIV2:
         RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
         RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
@@ -383,45 +360,68 @@ void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc)
         RCU_CFG2 |= RCU_CFG2_IRC28MDIV;
         RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
         break;
-#endif /* GD32F130_150 */
     case RCU_ADCCK_APB2_DIV2:
         RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
         RCU_CFG2 |= RCU_CFG2_ADCSEL;
         break;
+    case RCU_ADCCK_AHB_DIV3:
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
+        RCU_CFG2 |= RCU_CFG2_ADCPSC2;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
     case RCU_ADCCK_APB2_DIV4:
         RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
         RCU_CFG2 |= RCU_CFG2_ADCSEL;
         break;
+    case RCU_ADCCK_AHB_DIV5: 
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
+        RCU_CFG2 |= RCU_CFG2_ADCPSC2;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
     case RCU_ADCCK_APB2_DIV6: 
         RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
         RCU_CFG2 |= RCU_CFG2_ADCSEL;
         break;
+    case RCU_ADCCK_AHB_DIV7: 
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
+        RCU_CFG2 |= RCU_CFG2_ADCPSC2;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
     case RCU_ADCCK_APB2_DIV8: 
         RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
         RCU_CFG2 |= RCU_CFG2_ADCSEL;
         break;
+    case RCU_ADCCK_AHB_DIV9: 
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
+        RCU_CFG2 |= RCU_CFG2_ADCPSC2;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
     default:
         break;
     }
 }
 
-#ifdef GD32F130_150
 /*!
-    \brief      configure the USBD clock prescaler selection
-    \param[in]  ck_usbd: USBD clock prescaler selection
+    \brief      configure the USBFS clock prescaler selection
+    \param[in]  ck_usbfs: USBFS clock prescaler selection
                 only one parameter can be selected which is shown as below:
-      \arg        RCU_USBD_CKPLL_DIV1_5: select CK_PLL/1.5 as CK_USBD
-      \arg        RCU_USBD_CKPLL_DIV1: select CK_PLL as CK_USBD
-      \arg        RCU_USBD_CKPLL_DIV2_5: select CK_PLL/2.5 as CK_USBD
-      \arg        RCU_USBD_CKPLL_DIV2: select CK_PLL/2 as CK_USBD
+      \arg        RCU_USBFS_CKPLL_DIV1_5: select CK_PLL/1.5 as CK_USBFS
+      \arg        RCU_USBFS_CKPLL_DIV1: select CK_PLL as CK_USBFS
+      \arg        RCU_USBFS_CKPLL_DIV2_5: select CK_PLL/2.5 as CK_USBFS
+      \arg        RCU_USBFS_CKPLL_DIV2: select CK_PLL/2 as CK_USBFS
+      \arg        RCU_USBFS_CKPLL_DIV3: select CK_PLL/3 as CK_USBFS
+      \arg        RCU_USBFS_CKPLL_DIV3_5: select CK_PLL/3.5 as CK_USBFS
     \param[out] none
     \retval     none
 */
-void rcu_usbd_clock_config(uint32_t ck_usbd)
+void rcu_usbfs_clock_config(uint32_t ck_usbfs)
 {
-    /* reset the USBDPSC bits and set according to ck_usbd */
-    RCU_CFG0 &= ~RCU_CFG0_USBDPSC;
-    RCU_CFG0 |= ck_usbd;
+    /* reset the USBFSPSC bits and set according to ck_usbfs */
+    RCU_CFG0 &= ~RCU_CFG0_USBFSPSC;
+    RCU_CFG2 &= ~RCU_CFG2_USBFSPSC2;
+
+    RCU_CFG0 |= (ck_usbfs & (~RCU_CFG2_USBFSPSC2));
+    RCU_CFG2 |= (ck_usbfs & RCU_CFG2_USBFSPSC2);
 }
 
 /*!
@@ -429,7 +429,7 @@ void rcu_usbd_clock_config(uint32_t ck_usbd)
     \param[in]  ckout_src: CK_OUT clock source selection
                 only one parameter can be selected which is shown as below:
       \arg        RCU_CKOUTSRC_NONE: no clock selected
-      \arg        RCU_CKOUTSRC_IRC14M: IRC14M selected
+      \arg        RCU_CKOUTSRC_IRC28M: IRC28M selected
       \arg        RCU_CKOUTSRC_IRC40K: IRC40K selected
       \arg        RCU_CKOUTSRC_LXTAL: LXTAL selected
       \arg        RCU_CKOUTSRC_CKSYS: CKSYS selected
@@ -437,8 +437,7 @@ void rcu_usbd_clock_config(uint32_t ck_usbd)
       \arg        RCU_CKOUTSRC_HXTAL: HXTAL selected
       \arg        RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected
       \arg        RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected
-    \param[in]  ckout_div: CK_OUT divider
-                only one parameter can be selected which is shown as below:
+    \param[in]  ckout_div: CK_OUT divider 
       \arg        RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x
     \param[out] none
     \retval     none
@@ -451,88 +450,40 @@ void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div)
     ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
     RCU_CFG0 = (ckout | ckout_src | ckout_div);
 }
-#elif defined (GD32F170_190)
-/*!
-    \brief      configure the CK_OUT0 clock source and divider
-    \param[in]  ckout0_src: CK_OUT0 clock source selection
-                only one parameter can be selected which is shown as below:
-      \arg        RCU_CKOUT0SRC_NONE: no clock selected
-      \arg        RCU_CKOUT0SRC_IRC28M: IRC28M selected
-      \arg        RCU_CKOUT0SRC_IRC40K: IRC40K selected
-      \arg        RCU_CKOUT0SRC_LXTAL: LXTAL selected
-      \arg        RCU_CKOUT0SRC_CKSYS: CKSYS selected
-      \arg        RCU_CKOUT0SRC_IRC8M: IRC8M selected
-      \arg        RCU_CKOUT0SRC_HXTAL: HXTAL selected
-      \arg        RCU_CKOUT0SRC_CKPLL_DIV1: CK_PLL selected
-      \arg        RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected
-    \param[in]  ckout0_div: CK_OUT0 divider
-                only one parameter can be selected which is shown as below:
-      \arg        RCU_CKOUT0_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT0 is divided by x
-    \param[out] none
-    \retval     none
-*/
-void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div)
-{
-    uint32_t ckout0 = 0U;
-    ckout0 = RCU_CFG0;
-    /* reset the CKOUT0SEL, CKOUT0DIV and PLLDV bits and set according to ckout0_src and ckout0_div */
-    ckout0 &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
-    RCU_CFG0 = (ckout0 | ckout0_src | ckout0_div);
-}
 
 /*!
-    \brief      configure the CK_OUT1 clock source and divider
-    \param[in]  ckout1_src: CK_OUT1 clock source selection
-                only one parameter can be selected which is shown as below:
-      \arg        RCU_CKOUT1SRC_NONE: no clock selected
-      \arg        RCU_CKOUT1SRC_IRC28M: IRC28M selected
-      \arg        RCU_CKOUT1SRC_IRC40K: IRC40K selected
-      \arg        RCU_CKOUT1SRC_LXTAL: LXTAL selected
-      \arg        RCU_CKOUT1SRC_CKSYS: CKSYS selected
-      \arg        RCU_CKOUT1SRC_IRC8M: IRC8M selected
-      \arg        RCU_CKOUT1SRC_HXTAL: HXTAL selected
-      \arg        RCU_CKOUT1SRC_CKPLL_DIV1: CK_PLL selected
-      \arg        RCU_CKOUT1SRC_CKPLL_DIV2: CK_PLL/2 selected
-    \param[in]  ckout1_div: CK_OUT1 divider
+    \brief      configure the PLL clock source preselection
+    \param[in]  pll_presel: PLL clock source preselection
                 only one parameter can be selected which is shown as below:
-      \arg        RCU_CKOUT1_DIVx(x=1..64): CK_OUT1 is divided by x
+      \arg        RCU_PLLPRESEL_IRC48M: select IRC48M as PLL preselection clock
+      \arg        RCU_PLLPRESEL_HXTAL: select HXTAL as PLL preselection clock
     \param[out] none
     \retval     none
 */
-void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div)
+void rcu_pll_preselection_config(uint32_t pll_presel)
 {
-    uint32_t ckout1 = 0U;
-    ckout1 = RCU_CFG3;
-    /* reset the CKOUT1SRC, CKOUT1DIV bits and set according to ckout1_src and ckout1_div */
-    ckout1 &= ~(RCU_CFG3_CKOUT1SEL | RCU_CFG3_CKOUT1DIV);
-    if(RCU_CKOUT1SRC_CKPLL_DIV1 == ckout1_src){
-        RCU_CFG0 |= RCU_CFG0_PLLDV;
-        ckout1_src = CFG3_CKOUT1SEL(7);
-    }else if(RCU_CKOUT1SRC_CKPLL_DIV2 == ckout1_src){
-        RCU_CFG0 &= ~RCU_CFG0_PLLDV;
-        ckout1_src = CFG3_CKOUT1SEL(7);
-    }else{
-    }
-    RCU_CFG3 = (ckout1 | ckout1_src | ckout1_div);
+    RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL);
+    RCU_CFG1 |= pll_presel;
 }
-#endif /* GD32F130_150 */
 
 /*!
     \brief      configure the PLL clock source selection and PLL multiply factor
     \param[in]  pll_src: PLL clock source selection
                 only one parameter can be selected which is shown as below:
       \arg        RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock
-      \arg        RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock
+      \arg        RCU_PLLSRC_HXTAL_IRC48M: select HXTAL or IRC48M as PLL source clock
     \param[in]  pll_mul: PLL multiply factor
                 only one parameter can be selected which is shown as below:
-      \arg        RCU_PLL_MULx(x=2..32): PLL source clock * x
+      \arg        RCU_PLL_MULx(x=2..64): PLL source clock * x
     \param[out] none
     \retval     none
 */
 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
 {
     RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
-    RCU_CFG0 |= (pll_src | pll_mul);
+    RCU_CFG1 &= ~(RCU_CFG1_PLLMF5);
+    RCU_CFG0 |= (pll_src | (pll_mul & (~RCU_CFG1_PLLMF5)));
+    RCU_CFG1 |= (pll_mul & RCU_CFG1_PLLMF5);
 }
 
 /*!
@@ -587,31 +538,30 @@ void rcu_rtc_clock_config(uint32_t rtc_clock_source)
     RCU_BDCTL |= rtc_clock_source;
 }
 
-#ifdef GD32F170_190
 /*!
-    \brief      configure the SLCD clock source selection
-    \param[in]  slcd_clock_source: SLCD clock source selection
+    \brief      configure the CK48M clock source selection
+    \param[in]  ck48m_clock_source: CK48M clock source selection
                 only one parameter can be selected which is shown as below:
-      \arg        RCU_SLCDSRC_NONE: no clock selected
-      \arg        RCU_SLCDSRC_LXTAL: CK_LXTAL selected as SLCD source clock
-      \arg        RCU_SLCDSRC_IRC40K: CK_IRC40K selected as SLCD source clock
-      \arg        RCU_SLCDSRC_HXTAL_DIV32: CK_HXTAL/32 selected as SLCD source clock
+      \arg        RCU_CK48MSRC_PLL48M: CK_PLL48M selected as CK48M source clock
+      \arg        RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock
     \param[out] none
     \retval     none
 */
-void rcu_slcd_clock_config(uint32_t slcd_clock_source)
+void rcu_ck48m_clock_config(uint32_t ck48m_clock_source)
 {
-    /* reset the bits and set according to rtc_clock_source */
-    RCU_BDCTL &= ~RCU_BDCTL_RTCSRC;
-    RCU_BDCTL |= slcd_clock_source;
+    uint32_t reg;
+    
+    reg = RCU_ADDCTL;
+    /* reset the CK48MSEL bit and set according to ck48m_clock_source */
+    reg &= ~RCU_ADDCTL_CK48MSEL;
+    RCU_ADDCTL = (reg | ck48m_clock_source);
 }
-#endif /* GD32F170_190 */
 
 /*!
     \brief      configure the HXTAL divider used as input of PLL
     \param[in]  hxtal_prediv: HXTAL divider used as input of PLL
                 only one parameter can be selected which is shown as below:
-      \arg        RCU_PLL_HXTAL_DIVx(x=1..16): HXTAL divided x used as input of PLL
+      \arg        RCU_PLL_PREDVx(x=1..16): HXTAL or IRC48M divided x used as input of PLL
     \param[out] none
     \retval     none
 */
@@ -620,7 +570,7 @@ void rcu_hxtal_prediv_config(uint32_t hxtal_prediv)
     uint32_t prediv = 0U;
     prediv = RCU_CFG1;
     /* reset the HXTALPREDV bits and set according to hxtal_prediv */
-    prediv &= ~RCU_CFG1_HXTALPREDV;
+    prediv &= ~RCU_CFG1_PREDV;
     RCU_CFG1 = (prediv | hxtal_prediv);
 }
 
@@ -651,16 +601,16 @@ void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)
       \arg        RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
       \arg        RCU_FLAG_HXTALSTB: HXTAL stabilization flag
       \arg        RCU_FLAG_PLLSTB: PLL stabilization flag
-      \arg        RCU_FLAG_IRC14MSTB: IRC14M stabilization flag, only in GD32F130_150
-      \arg        RCU_FLAG_IRC28MSTB: IRC28M stabilization flag, only in GD32F170_190
-      \arg        RCU_FLAG_V12RST: 1.2V domain Power reset flag
+      \arg        RCU_FLAG_IRC28MSTB: IRC28M stabilization flag
+      \arg        RCU_FLAG_IRC48MSTB: IRC48M stabilization flag
+      \arg        RCU_FLAG_V12RST: V12 domain power reset flag
       \arg        RCU_FLAG_OBLRST: option byte loader reset flag
-      \arg        RCU_FLAG_EPRST: external PIN reset flag
+      \arg        RCU_FLAG_EPRST: external pin reset flag
       \arg        RCU_FLAG_PORRST: power reset flag
       \arg        RCU_FLAG_SWRST: software reset flag
       \arg        RCU_FLAG_FWDGTRST: free watchdog timer reset flag
       \arg        RCU_FLAG_WWDGTRST: window watchdog timer reset flag
-      \arg        RCU_FLAG_LPRST: Low-power reset flag
+      \arg        RCU_FLAG_LPRST: low-power reset flag
     \param[out] none
     \retval     FlagStatus: SET or RESET
 */
@@ -693,15 +643,15 @@ void rcu_all_reset_flag_clear(void)
       \arg        RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
       \arg        RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
       \arg        RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
-      \arg        RCU_INT_FLAG_IRC14MSTB: IRC14M stabilization interrupt flag, only in GD32F130_150
-      \arg        RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag, only in GD32F170_190
+      \arg        RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag
+      \arg        RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag
       \arg        RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
     \param[out] none
     \retval     FlagStatus: SET or RESET
 */
 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
 {
-    if(RESET != (RCU_INT & int_flag)){
+    if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
         return SET;
     }else{
         return RESET;
@@ -717,15 +667,15 @@ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
       \arg        RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
       \arg        RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
       \arg        RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
-      \arg        RCU_INT_FLAG_IRC14MSTB_CLR: IRC14M stabilization interrupt flag clear, only in GD32F130_150
-      \arg        RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear, only in GD32F170_190
+      \arg        RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear
       \arg        RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
     \param[out] none
     \retval     none
 */
 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
 {
-    RCU_INT |= (uint32_t)int_flag_clear;
+    RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
 }
 
 /*!
@@ -737,14 +687,14 @@ void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
       \arg        RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
       \arg        RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
       \arg        RCU_INT_PLLSTB: PLL stabilization interrupt enable
-      \arg        RCU_INT_IRC14MSTB: IRC14M stabilization interrupt enable, only in GD32F130_150
-      \arg        RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable, only in GD32F170_190
+      \arg        RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable
+      \arg        RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable
     \param[out] none
     \retval     none
 */
 void rcu_interrupt_enable(rcu_int_enum stab_int)
 {
-    RCU_INT |= (uint32_t)stab_int;
+    RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
 }
 
 
@@ -757,25 +707,25 @@ void rcu_interrupt_enable(rcu_int_enum stab_int)
       \arg        RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable
       \arg        RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable
       \arg        RCU_INT_PLLSTB: PLL stabilization interrupt disable
-      \arg        RCU_INT_IRC14MSTB: IRC14M stabilization interrupt disable, only in GD32F130_150
-      \arg        RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable, only in GD32F170_190
+      \arg        RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable
+      \arg        RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable
     \param[out] none
     \retval     none
 */
 void rcu_interrupt_disable(rcu_int_enum stab_int)
 {
-    RCU_INT &= ~(uint32_t)stab_int;
+    RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
 }
 
 /*!
-    \brief      wait until oscillator stabilization flags is SET or oscillator startup is timeout 
+    \brief      wait until oscillator stabilization flags is SET
     \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
                 only one parameter can be selected which is shown as below:
       \arg        RCU_HXTAL: HXTAL
       \arg        RCU_LXTAL: LXTAL
       \arg        RCU_IRC8M: IRC8M
-      \arg        RCU_IRC14M: IRC14M, only in GD32F130_150
-      \arg        RCU_IRC28M: IRC28M, only in GD32F170_190
+      \arg        RCU_IRC28M: IRC28M
+      \arg        RCU_IRC48M: IRC48M
       \arg        RCU_IRC40K: IRC40K
       \arg        RCU_PLL_CK: PLL
     \param[out] none
@@ -786,16 +736,13 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
     uint32_t stb_cnt = 0U;
     ErrStatus reval = ERROR;
     FlagStatus osci_stat = RESET;
-    
     switch(osci){
-    /* wait HXTAL stable */
     case RCU_HXTAL:
+         /* wait until HXTAL is stabilization and osci_stat is not more than timeout */
         while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
             osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
             stb_cnt++;
         }
-
-        /* check whether flag is set or not */
         if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
             reval = SUCCESS;
         }
@@ -812,6 +759,7 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
             reval = SUCCESS;
         }
         break;
+
     /* wait IRC8M stable */
     case RCU_IRC8M:
         while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
@@ -824,33 +772,32 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
             reval = SUCCESS;
         }
         break;
-#ifdef GD32F130_150
-    /* wait IRC14M stable */
-    case RCU_IRC14M:        
+
+    /* wait IRC28M stable */
+    case RCU_IRC28M:
         while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
-            osci_stat = rcu_flag_get(RCU_FLAG_IRC14MSTB);
+            osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB);
             stb_cnt++;
         }
 
         /* check whether flag is set or not */
-        if(RESET != rcu_flag_get(RCU_FLAG_IRC14MSTB)){
+        if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)){
             reval = SUCCESS;
         }
         break;
-#elif defined (GD32F170_190)
-    /* wait IRC28M stable */
-    case RCU_IRC28M:
+    /* wait IRC48M stable */
+    case RCU_IRC48M:
         while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
-            osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB);
+            osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB);
             stb_cnt++;
         }
 
         /* check whether flag is set or not */
-        if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)){
+        if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){
             reval = SUCCESS;
         }
         break;
-#endif /* GD32F130_150 */
+
     /* wait IRC40K stable */
     case RCU_IRC40K:
         while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
@@ -863,6 +810,7 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
             reval = SUCCESS;
         }
         break;
+
     /* wait PLL stable */
     case RCU_PLL_CK:
         while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
@@ -875,10 +823,10 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
             reval = SUCCESS;
         }
         break;
+   
     default:
         break;
     }
-    
     /* return value */
     return reval;
 }
@@ -890,8 +838,8 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
       \arg        RCU_HXTAL: HXTAL
       \arg        RCU_LXTAL: LXTAL
       \arg        RCU_IRC8M: IRC8M
-      \arg        RCU_IRC14M: IRC14M, only in GD32F130_150
-      \arg        RCU_IRC28M: IRC28M, only in GD32F170_190
+      \arg        RCU_IRC28M: IRC28M
+      \arg        RCU_IRC48M: IRC48M
       \arg        RCU_IRC40K: IRC40K
       \arg        RCU_PLL_CK: PLL
     \param[out] none
@@ -909,8 +857,8 @@ void rcu_osci_on(rcu_osci_type_enum osci)
       \arg        RCU_HXTAL: HXTAL
       \arg        RCU_LXTAL: LXTAL
       \arg        RCU_IRC8M: IRC8M
-      \arg        RCU_IRC14M: IRC14M, only in GD32F130_150
-      \arg        RCU_IRC28M: IRC28M, only in GD32F170_190
+      \arg        RCU_IRC28M: IRC28M
+      \arg        RCU_IRC48M: IRC48M
       \arg        RCU_IRC40K: IRC40K
       \arg        RCU_PLL_CK: PLL
     \param[out] none
@@ -947,11 +895,8 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
         RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
         break;
     case RCU_IRC8M:
-#ifdef GD32F130_150
-    case RCU_IRC14M:
-#elif defined (GD32F170_190)
     case RCU_IRC28M:
-#endif /* GD32F130_150 */
+    case RCU_IRC48M:
     case RCU_IRC40K:
     case RCU_PLL_CK:
         break;
@@ -983,14 +928,11 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
         /* LXTALEN must be reset before disable the oscillator bypass mode */
         reg = RCU_BDCTL;
         RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
-        RCU_BDCTL =(reg & (~RCU_BDCTL_LXTALBPS));
+        RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS));
         break;
     case RCU_IRC8M:
-#ifdef GD32F130_150
-    case RCU_IRC14M:
-#elif defined (GD32F170_190)
     case RCU_IRC28M:
-#endif /* GD32F130_150 */
+    case RCU_IRC48M:
     case RCU_IRC40K:
     case RCU_PLL_CK:
         break;
@@ -1005,7 +947,6 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
     \param[out] none
     \retval     none
 */
-
 void rcu_hxtal_clock_monitor_enable(void)
 {
     RCU_CTL0 |= RCU_CTL0_CKMEN;
@@ -1034,25 +975,9 @@ void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval)
     adjust = RCU_CTL0;
     /* reset the IRC8MADJ bits and set according to irc8m_adjval */
     adjust &= ~RCU_CTL0_IRC8MADJ;
-    RCU_CTL0 = (adjust | ((uint32_t)(irc8m_adjval)<<3));
+    RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval)<<3));
 }
 
-#ifdef GD32F130_150
-/*!
-    \brief      set the IRC14M adjust value
-    \param[in]  irc14m_adjval: IRC14M adjust value, must be between 0 and 0x1F
-    \param[out] none
-    \retval     none
-*/
-void rcu_irc14m_adjust_value_set(uint8_t irc14m_adjval)
-{
-    uint32_t adjust = 0U;
-    adjust = RCU_CTL1;
-    /* reset the IRC14MADJ bits and set according to irc14m_adjval */
-    adjust &= ~RCU_CTL1_IRC14MADJ;
-    RCU_CTL1 = (adjust | ((uint32_t)(irc14m_adjval)<<3));
-}
-#elif defined (GD32F170_190)
 /*!
     \brief      set the IRC28M adjust value
     \param[in]  irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F
@@ -1065,9 +990,8 @@ void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval)
     adjust = RCU_CTL1;
     /* reset the IRC28MADJ bits and set according to irc28m_adjval */
     adjust &= ~RCU_CTL1_IRC28MADJ;
-    RCU_CTL1 = (adjust | ((uint32_t)(irc28m_adjval)<<3));
+    RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval)<<3));
 }
-#endif /* GD32F130_150 */
 
 /*!
     \brief      unlock the voltage key
@@ -1086,15 +1010,10 @@ void rcu_voltage_key_unlock(void)
     \brief      set voltage in deep sleep mode
     \param[in]  dsvol: deep sleep mode voltage
                 only one parameter can be selected which is shown as below:
-      \arg        RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V, only in GD32F130_150
-      \arg        RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V, only in GD32F130_150
-      \arg        RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V, only in GD32F130_150
-      \arg        RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V, only in GD32F130_150
-
-      \arg        RCU_DEEPSLEEP_V_1_8: the core voltage is 1.8V, only in GD32F170_190
-      \arg        RCU_DEEPSLEEP_V_1_6: the core voltage is 1.6V, only in GD32F170_190
-      \arg        RCU_DEEPSLEEP_V_1_4: the core voltage is 1.4V, only in GD32F170_190
-      \arg        RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V, only in GD32F170_190
+      \arg        RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
+      \arg        RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
+      \arg        RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V
+      \arg        RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V
     \param[out] none
     \retval     none
 */
@@ -1105,24 +1024,6 @@ void rcu_deepsleep_voltage_set(uint32_t dsvol)
     RCU_DSV |= dsvol;
 }
 
-#ifdef GD32F130_150
-/*!
-    \brief      set the power down voltage
-    \param[in]  pdvol: power down voltage select
-                only one parameter can be selected which is shown as below:
-      \arg        RCU_PDR_V_2_6: power down voltage is 2.6V
-      \arg        RCU_PDR_V_1_8: power down voltage is 1.8V
-    \param[out] none
-    \retval     none
-*/
-void rcu_power_down_voltage_set(uint32_t pdvol)
-{
-    /* reset the PDRVS bits and set according to pdvol */
-    RCU_PDVSEL &= ~RCU_PDVSEL_PDRVS;
-    RCU_PDVSEL |= pdvol;
-}
-#endif /* GD32F130_150 */
-
 /*!
     \brief      get the system clock, bus and peripheral clock frequency
     \param[in]  clock: the clock frequency which to get
@@ -1139,10 +1040,10 @@ void rcu_power_down_voltage_set(uint32_t pdvol)
 */
 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
 {
-    uint32_t sws = 0U, adcps = 0U, ck_freq = 0U;
+    uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U;
     uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U;
     uint32_t adc_freq = 0U, cec_freq = 0U, usart_freq = 0U;
-    uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
+    uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
     /* exponent of AHB, APB1 and APB2 clock divider */
     const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
     const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
@@ -1163,17 +1064,31 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
         /* get the value of PLLMF[3:0] */
         pllmf = GET_BITS(RCU_CFG0, 18, 21);
         pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
+        pllmf5 = GET_BITS(RCU_CFG1, 31, 31);
         /* high 16 bits */
         if(1U == pllmf4){
             pllmf += 17U;
         }else{
-            pllmf += 2U;
+            if(pllmf == 15U){
+                pllmf += 1U; 
+            }else{                
+                pllmf += 2U;
+            }
+        }
+        if(1U == pllmf5){
+            pllmf += 31U;
         }
-        /* PLL clock source selection, HXTAL or IRC8M/2 */
+            
+        /* PLL clock source selection, HXTAL or IRC48M or IRC8M/2 */
         pllsel = GET_BITS(RCU_CFG0, 16, 16);
+        pllpresel = GET_BITS(RCU_CFG1, 30, 30);
         if(0U != pllsel){
             prediv = (GET_BITS(RCU_CFG1,0, 3) + 1U);
-            cksys_freq = (HXTAL_VALUE / prediv) * pllmf;
+            if(0U == pllpresel){
+                cksys_freq = (HXTAL_VALUE / prediv) * pllmf;
+            }else{
+                cksys_freq = (IRC48M_VALUE / prediv) * pllmf;
+            }
         }else{
             cksys_freq = (IRC8M_VALUE >> 1) * pllmf;
         }
@@ -1214,31 +1129,44 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
         break;
     case CK_ADC:
         /* calculate ADC clock frequency */
-        if(RCU_ADCSRC_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){
-#ifdef GD32F130_150
-            adc_freq = IRC14M_VALUE;
-#elif defined (GD32F170_190)
+        if(RCU_ADCSRC_AHB_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){
             if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){
                 adc_freq = IRC28M_VALUE >> 1;
             }else{
                 adc_freq = IRC28M_VALUE;
             }
-#endif /* GD32F130_150 */
         }else{
-            /* ADC clock select CK_APB2 divided by 2/4/6/8 */
+            /* ADC clock select CK_APB2 divided by 2/4/6/8 or CK_AHB divided by 3/5/7/9 */
             adcps = GET_BITS(RCU_CFG0, 14, 15);
+            adcps2 = GET_BITS(RCU_CFG2, 31, 31);
             switch(adcps){
             case 0:
-                adc_freq = apb2_freq / 2U;
+                if(0U == adcps2){
+                   adc_freq = apb2_freq / 2U;
+                }else{
+                   adc_freq = ahb_freq / 3U;
+                }
                 break;
             case 1:
-                adc_freq = apb2_freq / 4U;
+                if(0U == adcps2){
+                   adc_freq = apb2_freq / 4U;
+                }else{
+                   adc_freq = ahb_freq / 5U;
+                }
                 break;
             case 2:
-                adc_freq = apb2_freq / 6U;
+                if(0U == adcps2){
+                   adc_freq = apb2_freq / 6U;
+                }else{
+                   adc_freq = ahb_freq / 7U;
+                }
                 break;
             case 3:
-                adc_freq = apb2_freq / 8U;
+                if(0U == adcps2){
+                   adc_freq = apb2_freq / 8U;
+                }else{
+                   adc_freq = ahb_freq / 9U;
+                }
                 break;
             default:
                 break;

Librarys/GD32F1x0_Drivers/src/gd32f1x0_rtc.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_rtc.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_rtc.c
+    \file  gd32f3x0_rtc.c
     \brief RTC driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_rtc.h"
+#include "gd32f3x0_rtc.h"
 
 /*!
     \brief      reset most of the RTC registers
@@ -61,7 +58,7 @@ ErrStatus rtc_deinit(void)
     /* enter init mode */
     error_status = rtc_init_mode_enter();
 
-    if(ERROR != error_status){     
+    if(ERROR != error_status){
         /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition.
            in order to read calendar from shadow register, not the real registers being reset */
         RTC_TIME = RTC_REGISTER_RESET;
@@ -78,8 +75,8 @@ ErrStatus rtc_deinit(void)
         RTC_ALRM0SS = RTC_REGISTER_RESET;
 
         /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */
-        RTC_SHIFTCTL   = RTC_REGISTER_RESET;       
-        RTC_HRFC       = RTC_REGISTER_RESET;
+        RTC_SHIFTCTL = RTC_REGISTER_RESET;
+        RTC_HRFC = RTC_REGISTER_RESET;
 
         error_status = rtc_register_sync_wait();  
     }
@@ -114,7 +111,7 @@ ErrStatus rtc_deinit(void)
 ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct)
 {
     ErrStatus error_status = ERROR;
-    uint32_t reg_time = 0U, reg_date = 0U;
+    uint32_t reg_time = 0x00U, reg_date = 0x00U;
 
     reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \
                 DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \
@@ -122,7 +119,7 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct)
                 DATE_DAY(rtc_initpara_struct->rtc_date)); 
     
     reg_time = (rtc_initpara_struct->rtc_am_pm| \
-                TIME_HR(rtc_initpara_struct->rtc_hour)  | \
+                TIME_HR(rtc_initpara_struct->rtc_hour) | \
                 TIME_MN(rtc_initpara_struct->rtc_minute) | \
                 TIME_SC(rtc_initpara_struct->rtc_second)); 
               
@@ -133,7 +130,7 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct)
     /* 2nd: enter init mode */
     error_status = rtc_init_mode_enter();
 
-    if(ERROR != error_status){    
+    if(ERROR != error_status){
         RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn)| \
                                   PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn));
 
@@ -143,14 +140,14 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct)
         RTC_CTL &= (uint32_t)(~RTC_CTL_CS);
         RTC_CTL |=  rtc_initpara_struct->rtc_display_format;
         
-        /* 3rd: exit init mode */  
+        /* 3rd: exit init mode */
         rtc_init_mode_exit();
         
-        /* 4th: wait the RSYNF flag to set */          
+        /* 4th: wait the RSYNF flag to set */
         error_status = rtc_register_sync_wait();
     }
 
-    /* 5th:  enable the write protection */
+    /* 5th: enable the write protection */
     RTC_WPK = RTC_LOCK_KEY;
 
     return error_status;
@@ -169,15 +166,15 @@ ErrStatus rtc_init_mode_enter(void)
     ErrStatus error_status = ERROR;
 
     /* check whether it has been in init mode */
-    if ((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){   
+    if(RESET == (RTC_STAT & RTC_STAT_INITF)){
         RTC_STAT |= RTC_STAT_INITM;
         
         /* wait until the INITF flag to be set */
         do{
            flag_status = RTC_STAT & RTC_STAT_INITF;
-        }while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
+        }while((--time_index > 0x00U) && (RESET == flag_status));
 
-        if ((uint32_t)RESET != flag_status){        
+        if(RESET != flag_status){
             error_status = SUCCESS;
         }
     }else{
@@ -210,7 +207,7 @@ ErrStatus rtc_register_sync_wait(void)
     uint32_t flag_status = RESET;
     ErrStatus error_status = ERROR;
 
-    if ((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){    
+    if(RESET == (RTC_CTL & RTC_CTL_BPSHAD)){
         /* disable the write protection */
         RTC_WPK = RTC_UNLOCK_KEY1;
         RTC_WPK = RTC_UNLOCK_KEY2;
@@ -221,9 +218,9 @@ ErrStatus rtc_register_sync_wait(void)
         /* wait until RSYNF flag to be set */
         do{
             flag_status = RTC_STAT & RTC_STAT_RSYNF;
-        }while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
+        }while((--time_index > 0x00U) && (RESET == flag_status));
 
-        if ((uint32_t)RESET != flag_status){  
+        if(RESET != flag_status){
             error_status = SUCCESS;
         }
         
@@ -259,7 +256,7 @@ ErrStatus rtc_register_sync_wait(void)
 */
 void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct)
 {
-    uint32_t temp_tr = 0U, temp_dr = 0U, temp_pscr = 0U, temp_ctlr = 0U;
+    uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U;
 
     temp_tr = (uint32_t)RTC_TIME;   
     temp_dr = (uint32_t)RTC_DATE;
@@ -288,7 +285,7 @@ void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct)
 */
 uint32_t rtc_subsecond_get(void)
 {
-    uint32_t reg = 0U;
+    uint32_t reg = 0x00U;
     /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */
     reg = (uint32_t)RTC_SS;
     /* read RTC_DATE to unlock the 3 shadow registers */
@@ -317,7 +314,7 @@ uint32_t rtc_subsecond_get(void)
 */
 void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time)
 {
-    uint32_t reg_alrm0td = 0U;
+    uint32_t reg_alrm0td = 0x00U;
 
     reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \
                  rtc_alarm_time->rtc_weekday_or_date | \
@@ -340,11 +337,12 @@ void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time)
 /*!
     \brief      configure subsecond of RTC alarm
     \param[in]  mask_subsecond: alarm subsecond mask
+                only one parameter can be selected which is shown as below:
       \arg        RTC_MASKSSC_0_14: mask alarm subsecond configuration
       \arg        RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared
       \arg        RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared
       \arg        RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared
-      \arg        RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4]], and RTC_ALRM0SS_SSC[3:0] is to be compared
+      \arg        RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared
       \arg        RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared
       \arg        RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared
       \arg        RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared
@@ -360,7 +358,7 @@ void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time)
     \param[out] none
     \retval     none
 */
-void rtc_alarm_subsecond_config(uint32_t mask_subsecond,  uint32_t subsecond)
+void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond)
 {
     /* disable the write protection */
     RTC_WPK = RTC_UNLOCK_KEY1;
@@ -372,6 +370,52 @@ void rtc_alarm_subsecond_config(uint32_t mask_subsecond,  uint32_t subsecond)
     RTC_WPK = RTC_LOCK_KEY;
 }
 
+/*!
+    \brief      get RTC alarm
+    \param[in]  none
+    \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains 
+                parameters for RTC alarm configuration
+                members of the structure and the member values are shown as below:
+                  rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK
+                                  RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK
+                  rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED
+                  rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set
+                                 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY,
+                                    RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set
+                  rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format
+                  rtc_alarm_minute: 0x0 - 0x59(BCD format)
+                  rtc_alarm_second: 0x0 - 0x59(BCD format)
+                  rtc_am_pm: RTC_AM, RTC_PM
+    \retval     none
+*/
+void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time)
+{
+    uint32_t reg_alrm0td = 0x00U;
+
+    /* get the value of RTC_ALRM0TD register */
+    reg_alrm0td = RTC_ALRM0TD;
+
+    /* get alarm parameters and construct the rtc_alarm_struct structure */
+    rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK; 
+    rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM);
+    rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS);
+    rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td);
+    rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td);
+    rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td);
+    rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td);  
+}
+
+/*!
+    \brief      get RTC alarm subsecond
+    \param[in]  none
+    \param[out] none
+    \retval     RTC alarm subsecond value
+*/
+uint32_t rtc_alarm_subsecond_get(void)
+{
+    return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC));
+}
+
 /*!
     \brief      enable RTC alarm
     \param[in]  none
@@ -412,9 +456,9 @@ ErrStatus rtc_alarm_disable(void)
     /* wait until ALRM0WF flag to be set after the alarm is disabled */
     do{
         flag_status = RTC_STAT & RTC_STAT_ALRM0WF;
-    }while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
+    }while((--time_index > 0x00U) && (RESET == flag_status));
     
-    if ((uint32_t)RESET != flag_status){     
+    if(RESET != flag_status){     
         error_status = SUCCESS;
     }
 
@@ -424,55 +468,10 @@ ErrStatus rtc_alarm_disable(void)
     return error_status;
 }
 
-/*!
-    \brief      get RTC alarm
-    \param[in]  none
-    \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains 
-                parameters for RTC alarm configuration
-                members of the structure and the member values are shown as below:
-                  rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK
-                                  RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK
-                  rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED
-                  rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set
-                                 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY,
-                                    RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set
-                  rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format
-                  rtc_alarm_minute: 0x0 - 0x59(BCD format)
-                  rtc_alarm_second: 0x0 - 0x59(BCD format)
-                  rtc_am_pm: RTC_AM, RTC_PM
-    \retval     none
-*/
-void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time)
-{
-    uint32_t reg_alrm0td = 0U;
-
-    /* get the value of RTC_ALRM0TD register */
-    reg_alrm0td = RTC_ALRM0TD;
-
-    /* get alarm parameters and construct the rtc_alarm_struct structure */
-    rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK; 
-    rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM);
-    rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS);
-    rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td);
-    rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td);
-    rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td);
-    rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td);  
-}
-
-/*!
-    \brief      get RTC alarm subsecond
-    \param[in]  none
-    \param[out] none
-    \retval     RTC alarm subsecond value
-*/
-uint32_t rtc_alarm_subsecond_get(void)
-{
-    return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC));
-}
-
 /*!
     \brief      enable RTC time-stamp
     \param[in]  edge: specify which edge to detect of time-stamp
+                only one parameter can be selected which is shown as below:
       \arg        RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event
       \arg        RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event
     \param[out] none
@@ -480,7 +479,7 @@ uint32_t rtc_alarm_subsecond_get(void)
 */
 void rtc_timestamp_enable(uint32_t edge)
 {
-    uint32_t reg_ctl = 0U;
+    uint32_t reg_ctl = 0x00U;
 
     /* clear the bits to be configured in RTC_CTL */
     reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN)));
@@ -536,7 +535,7 @@ void rtc_timestamp_disable(void)
 */
 void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp)
 {
-    uint32_t temp_tts = 0U, temp_dts = 0U;
+    uint32_t temp_tts = 0x00U, temp_dts = 0x00U;
 
     /* get the value of time_stamp registers */
     temp_tts = (uint32_t)RTC_TTS;
@@ -623,6 +622,7 @@ void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper)
 /*!
     \brief      disable RTC tamper
     \param[in]  source: specify which tamper source to be disabled
+                only one parameter can be selected which is shown as below:
       \arg        RTC_TAMPER0
       \arg        RTC_TAMPER1
     \param[out] none
@@ -638,6 +638,7 @@ void rtc_tamper_disable(uint32_t source)
 /*!
     \brief      enable specified RTC interrupt
     \param[in]  interrupt: specify which interrupt source to be enabled
+                only one parameter can be selected which is shown as below:
       \arg        RTC_INT_TIMESTAMP: timestamp interrupt
       \arg        RTC_INT_ALARM: alarm interrupt
       \arg        RTC_INT_TAMP: tamp interrupt
@@ -662,6 +663,7 @@ void rtc_interrupt_enable(uint32_t interrupt)
 /*!
     \brief      disble specified RTC interrupt
     \param[in]  interrupt: specify which interrupt source to be disabled
+                only one parameter can be selected which is shown as below:
       \arg        RTC_INT_TIMESTAMP: timestamp interrupt
       \arg        RTC_INT_ALARM: alarm interrupt
       \arg        RTC_INT_TAMP: tamp interrupt
@@ -686,6 +688,7 @@ void rtc_interrupt_disable(uint32_t interrupt)
 /*!
     \brief      check specified flag
     \param[in]  flag: specify which flag to check
+                only one parameter can be selected which is shown as below:
       \arg        RTC_FLAG_RECALIBRATION: recalibration pending flag
       \arg        RTC_FLAG_TAMP1: tamper 1 event flag
       \arg        RTC_FLAG_TAMP0: tamper 0 event flag
@@ -704,7 +707,7 @@ FlagStatus rtc_flag_get(uint32_t flag)
 {
     FlagStatus flag_state = RESET;
     
-    if ((uint32_t)RESET != (RTC_STAT & flag)){   
+    if(RESET != (RTC_STAT & flag)){   
         flag_state = SET;
     }
     return flag_state;
@@ -730,13 +733,15 @@ void rtc_flag_clear(uint32_t flag)
 /*!
     \brief      configure rtc alternate output source
     \param[in]  source: specify signal to output
-      \arg        RTC_CALIBRATION_512HZ: when the LXTAL freqency is 32768Hz and the RTC_PSC 
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC 
                                          is the default value, output 512Hz signal
-      \arg        RTC_CALIBRATION_1HZ: when the LXTAL freqency is 32768Hz and the RTC_PSC 
-                                       is the default value, output 512Hz signal
+      \arg        RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC 
+                                       is the default value, output 1Hz signal
       \arg        RTC_ALARM_HIGH: when the  alarm flag is set, the output pin is high
       \arg        RTC_ALARM_LOW: when the  Alarm flag is set, the output pin is low
     \param[in]  mode: specify the output pin (PC13) mode when output alarm signal
+                only one parameter can be selected which is shown as below:
       \arg        RTC_ALARM_OUTPUT_OD: open drain mode
       \arg        RTC_ALARM_OUTPUT_PP: push pull mode
     \param[out] none
@@ -753,7 +758,7 @@ void rtc_alter_output_config(uint32_t source, uint32_t mode)
     RTC_CTL |= (uint32_t)(source);
     
     /* alarm output */
-    if((uint32_t)RESET != (source & RTC_OS_ENABLE)){
+    if(RESET != (source & RTC_OS_ENABLE)){
         RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL);
         RTC_TAMP |= (uint32_t)(mode);  
     }
@@ -762,9 +767,52 @@ void rtc_alter_output_config(uint32_t source, uint32_t mode)
     RTC_WPK = RTC_LOCK_KEY;
 }
 
+
+/*!
+    \brief      configure RTC calibration register
+    \param[in]  window: select calibration window
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz
+      \arg        RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz
+      \arg        RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz
+    \param[in]  plus: add RTC clock or not
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock
+      \arg        RTC_CALIBRATION_PLUS_RESET: no effect
+    \param[in]  minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF)
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus)
+{
+    uint32_t time_index = RTC_HRFC_TIMEOUT;
+    ErrStatus error_status = ERROR;
+    uint32_t flag_status = RESET;
+    
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;    
+    
+    /* check if a calibration operation is ongoing */        
+    do{
+        flag_status = RTC_STAT & RTC_STAT_SCPF;
+    }while((--time_index > 0x00U) && (RESET != flag_status));
+    
+    if(RESET == flag_status){
+        RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus));
+        error_status = SUCCESS;
+    }
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+
+    return error_status;
+}
+
 /*!
     \brief      ajust the daylight saving time by adding or substracting one hour from the current time
     \param[in]  operation: hour ajustment operation
+                only one parameter can be selected which is shown as below:
       \arg        RTC_CTL_A1H: add one hour
       \arg        RTC_CTL_S1H: substract one hour
     \param[out] none
@@ -782,6 +830,45 @@ void rtc_hour_adjust(uint32_t operation)
     RTC_WPK = RTC_LOCK_KEY;
 }
 
+/*!
+    \brief      ajust RTC second or subsecond value of current time
+    \param[in]  add: add 1s to current time or not
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_SHIFT_ADD1S_RESET: no effect
+      \arg        RTC_SHIFT_ADD1S_SET: add 1s to current time
+    \param[in]  minus: number of subsecond to minus from current time(0x0 - 0x7FFF)
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus)
+{
+    uint32_t time_index = RTC_SHIFTCTL_TIMEOUT;
+    ErrStatus error_status = ERROR;
+    uint32_t flag_status = RESET;
+    uint32_t temp=0U;
+
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+    
+    /* check if a shift operation is ongoing */    
+    do{
+        flag_status = RTC_STAT & RTC_STAT_SOPF;
+    }while((--time_index > 0x00U) && (RESET != flag_status));
+  
+    temp = RTC_CTL & RTC_CTL_REFEN;
+    /* check if the function of reference clock detection is disabled */
+    if((RESET == flag_status) && (RESET == temp)){  
+        RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus));
+        error_status = rtc_register_sync_wait();        
+    }
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+
+    return error_status;
+}
+
 /*!
     \brief      enable RTC bypass shadow registers function
     \param[in]  none
@@ -876,79 +963,4 @@ ErrStatus rtc_refclock_detection_disable(void)
     return error_status;
 }
 
-/*!
-    \brief      ajust RTC second or subsecond value of current time
-    \param[in]  add: add 1s to current time or not
-      \arg        RTC_SHIFT_ADD1S_RESET: no effect
-      \arg        RTC_SHIFT_ADD1S_SET: add 1s to current time
-    \param[in]  minus: number of subsecond to minus from current time(0x0 - 0x7FFF)
-    \param[out] none
-    \retval     ErrStatus: ERROR or SUCCESS
-*/
-ErrStatus rtc_second_ajust(uint32_t add, uint32_t minus)
-{
-    uint32_t time_index = RTC_SHIFTCTL_TIMEOUT;
-    ErrStatus error_status = ERROR;
-    uint32_t flag_status = RESET;
-    uint32_t temp=0U;    
-
-    /* disable the write protection */
-    RTC_WPK = RTC_UNLOCK_KEY1;
-    RTC_WPK = RTC_UNLOCK_KEY2;
-    
-    /* check if a shift operation is ongoing */    
-    do{
-        flag_status = RTC_STAT & RTC_STAT_SOPF;
-    }while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
-
-    temp = RTC_CTL & RTC_CTL_REFEN;    
-    /* check if the function of reference clock detection is disabled */
-    if(((uint32_t)RESET == flag_status) && (RESET == temp)){  
-        RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus));
-        error_status = rtc_register_sync_wait();        
-    }
 
-    /* enable the write protection */
-    RTC_WPK = RTC_LOCK_KEY;
-
-    return error_status;
-}
-
-/*!
-    \brief      configure RTC calibration register
-    \param[in]  window: select calibration window
-      \arg        RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz
-      \arg        RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz
-      \arg        RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz
-    \param[in]  plus: add RTC clock or not
-      \arg        RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock
-      \arg        RTC_CALIBRATION_PLUS_RESET: no effect
-    \param[in]  minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF)
-    \param[out] none
-    \retval     ErrStatus: ERROR or SUCCESS
-*/
-ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus)
-{
-    uint32_t time_index = RTC_HRFC_TIMEOUT;
-    ErrStatus error_status = ERROR;
-    uint32_t flag_status = RESET;
-    
-    /* disable the write protection */
-    RTC_WPK = RTC_UNLOCK_KEY1;
-    RTC_WPK = RTC_UNLOCK_KEY2;    
-    
-    /* check if a calibration operation is ongoing */        
-    do{
-        flag_status = RTC_STAT & RTC_STAT_SCPF;
-    }while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
-    
-    if((uint32_t)RESET == flag_status){
-        RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus));
-        error_status = SUCCESS;
-    }
-
-    /* enable the write protection */
-    RTC_WPK = RTC_LOCK_KEY;
-
-    return error_status;
-}

Librarys/GD32F1x0_Drivers/src/gd32f1x0_spi.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_spi.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_spi.c
-    \brief SPI driver 
+    \file  gd32f3x0_spi.c
+    \brief SPI driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,7 +33,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_spi.h"
+#include "gd32f3x0_spi.h"
 
 #define SPI_INIT_MASK                   ((uint32_t)0x00003040U)  /*!< SPI parameter initialization mask */
 #define I2S_INIT_MASK                   ((uint32_t)0x0000F047U)  /*!< I2S parameter initialization mask */
@@ -45,7 +42,7 @@ OF SUCH DAMAGE.
 
 /*!
     \brief      reset SPI and I2S 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -62,11 +59,6 @@ void spi_i2s_deinit(uint32_t spi_periph)
         rcu_periph_reset_enable(RCU_SPI1RST);
         rcu_periph_reset_disable(RCU_SPI1RST);
         break;
-    case SPI2:
-        /* reset SPI2 and I2S2 */
-        rcu_periph_reset_enable(RCU_SPI2RST);
-        rcu_periph_reset_disable(RCU_SPI2RST);
-        break;
     default :
         break;
     }
@@ -91,39 +83,39 @@ void spi_struct_para_init(spi_parameter_struct* spi_struct)
 
 /*!
     \brief      initialize SPI parameter
-    \param[in]  spi_periph: SPIx(x=0,1,2)
-    \param[in]  spi_struct: SPI parameter initialization stuct members of the structure
-                            and  the member values are shown as below:
-                  device_mode   : SPI_MASTER, SPI_SLAVE
-                  trans_mode    : SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY,
-                                  SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT
-                  frame_size    : SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT
-                  nss           : SPI_NSS_SOFT, SPI_NSS_HARD
-                  endian        : SPI_ENDIAN_MSB, SPI_ENDIAN_LSB
-                  clock_polarity_phase  : SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE
-                                  SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE
-                  prescale      : SPI_PSC_n (n=2,4,8,16,32,64,128,256)
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  spi_struct: SPI parameter initialization stuct members of the structure 
+                            and the member values are shown as below:
+                  device_mode: SPI_MASTER, SPI_SLAVE
+                  trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY,
+                              SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT
+                  frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT
+                  nss: SPI_NSS_SOFT, SPI_NSS_HARD
+                  endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB
+                  clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE
+                                        SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE
+                  prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
     \param[out] none
     \retval     none
 */
 void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
 {   
     uint32_t reg = 0U;
-    
     reg = SPI_CTL0(spi_periph);
     reg &= SPI_INIT_MASK;
+
     /* select SPI as master or slave */
-    reg |=spi_struct->device_mode;
+    reg |= spi_struct->device_mode;
     /* select SPI transfer mode */
-    reg |=spi_struct->trans_mode;
+    reg |= spi_struct->trans_mode;
     /* select SPI frame size */
-    reg |=spi_struct->frame_size;
+    reg |= spi_struct->frame_size;
     /* select SPI NSS use hardware or software */
-    reg |=spi_struct->nss;
+    reg |= spi_struct->nss;
     /* select SPI LSB or MSB */
-    reg |=spi_struct->endian;
+    reg |= spi_struct->endian;
     /* select SPI polarity and phase */
-    reg |=spi_struct->clock_polarity_phase;
+    reg |= spi_struct->clock_polarity_phase;
     /* select SPI prescale to adjust transmit speed */
     reg |= spi_struct->prescale;
 
@@ -136,7 +128,7 @@ void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
 
 /*!
     \brief      enable SPI
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -147,7 +139,7 @@ void spi_enable(uint32_t spi_periph)
 
 /*!
     \brief      disable SPI 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -157,35 +149,36 @@ void spi_disable(uint32_t spi_periph)
 }
 
 
+#ifdef GD32F350
 /*!
     \brief      initialize I2S parameter 
-    \param[in]  spi_periph: SPIx(only x=0,2)
-    \param[in]  mode: I2S operation mode 
+    \param[in]  spi_periph: SPI0
+    \param[in]  mode: I2S operation mode
                 only one parameter can be selected which is shown as below:
-      \arg        I2S_MODE_SLAVETX : I2S slave transmit mode
-      \arg        I2S_MODE_SLAVERX : I2S slave receive mode
-      \arg        I2S_MODE_MASTERTX : I2S master transmit mode
-      \arg        I2S_MODE_MASTERRX : I2S master receive mode
-    \param[in]  standard: I2S standard 
+      \arg        I2S_MODE_SLAVETX: I2S slave transmit mode
+      \arg        I2S_MODE_SLAVERX: I2S slave receive mode
+      \arg        I2S_MODE_MASTERTX: I2S master transmit mode
+      \arg        I2S_MODE_MASTERRX: I2S master receive mode
+    \param[in]  standard: I2S standard
                 only one parameter can be selected which is shown as below:
-      \arg        I2S_STD_PHILLIPS : I2S phillips standard  
-      \arg        I2S_STD_MSB : I2S MSB standard
-      \arg        I2S_STD_LSB : I2S LSB standard
-      \arg        I2S_STD_PCMSHORT : I2S PCM short standard
-      \arg        I2S_STD_PCMLONG : I2S PCM long standard
-    \param[in]  ckpl: I2S idle state clock polarity 
+      \arg        I2S_STD_PHILLIPS: I2S phillips standard
+      \arg        I2S_STD_MSB: I2S MSB standard
+      \arg        I2S_STD_LSB: I2S LSB standard
+      \arg        I2S_STD_PCMSHORT: I2S PCM short standard
+      \arg        I2S_STD_PCMLONG: I2S PCM long standard
+    \param[in]  ckpl: I2S idle state clock polarity
                 only one parameter can be selected which is shown as below:
-      \arg        I2S_CKPL_LOW : I2S clock polarity low level
-      \arg        I2S_CKPL_HIGH : I2S clock polarity high level
+      \arg        I2S_CKPL_LOW: I2S clock polarity low level
+      \arg        I2S_CKPL_HIGH: I2S clock polarity high level
     \param[out] none
     \retval     none
 */
 void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
 {
-    uint32_t reg= 0U;
-    reg= SPI_I2SCTL(spi_periph);
+    uint32_t reg = 0U;
+    reg = SPI_I2SCTL(spi_periph);
     reg &= I2S_INIT_MASK;
-    
+
     /* enable I2S mode */
     reg |= (uint32_t)SPI_I2SCTL_I2SSEL; 
     /* select I2S mode */
@@ -194,13 +187,14 @@ void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ck
     reg |= (uint32_t)standard;
     /* select I2S polarity */
     reg |= (uint32_t)ckpl;
+
     /* write to SPI_I2SCTL register */
     SPI_I2SCTL(spi_periph) = (uint32_t)reg;
 }
 
 /*!
     \brief      configure I2S prescaler 
-    \param[in]  spi_periph: SPIx(only x=0,2)
+    \param[in]  spi_periph: SPI0
     \param[in]  audiosample: I2S audio sample rate
                 only one parameter can be selected which is shown as below:
       \arg        I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
@@ -235,7 +229,8 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
     SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE;
 
     /* get system clock */
-    i2sclock =rcu_clock_freq_get(CK_SYS);    
+    i2sclock = rcu_clock_freq_get(CK_SYS);
+    
     /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
     if(I2S_MCKOUT_ENABLE == mckout){
         clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
@@ -246,20 +241,23 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
             clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample);
         }
     }
-    /* remove the flaoting point */
-    clks = (clks+5U)/10U;
+    
+    /* remove the floating point */
+    clks = (clks + 5U) / 10U;
     i2sof = (clks & 0x00000001U);
-    i2sdiv = ((clks - i2sof)/2U);
-    i2sof = (i2sof << 8U);
-     
+    i2sdiv = ((clks - i2sof) / 2U);
+    i2sof  = (i2sof << 8U);
+
     /* set the default values */
-    if((i2sdiv<2U) || (i2sdiv>255U)){
+    if((i2sdiv < 2U) || (i2sdiv > 255U)){
         i2sdiv = 2U;
         i2sof = 0U;
     }
+
     /* configure SPI_I2SPSC */
     SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout);
-   /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
+
+    /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
     SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
     /* configure data frame format */
     SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat;
@@ -267,7 +265,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
 
 /*!
     \brief      enable I2S 
-    \param[in]  spi_periph: SPIx(x=0,2)
+    \param[in]  spi_periph: SPI0
     \param[out] none
     \retval     none
 */
@@ -278,7 +276,7 @@ void i2s_enable(uint32_t spi_periph)
 
 /*!
     \brief      disable I2S 
-    \param[in]  spi_periph: SPIx(x=0,2)
+    \param[in]  spi_periph: SPI0
     \param[out] none
     \retval     none
 */
@@ -287,9 +285,11 @@ void i2s_disable(uint32_t spi_periph)
     SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
 }
 
+#endif /* GD32F350 */
+
 /*!
     \brief      enable SPI NSS output 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -300,7 +300,7 @@ void spi_nss_output_enable(uint32_t spi_periph)
 
 /*!
     \brief      disable SPI NSS output 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -310,8 +310,8 @@ void spi_nss_output_disable(uint32_t spi_periph)
 }
 
 /*!
-    \brief      SPI NSS pin high level in software mode
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \brief      pull NSS pin high in software mode
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -321,8 +321,8 @@ void spi_nss_internal_high(uint32_t spi_periph)
 }
 
 /*!
-    \brief      SPI NSS pin low level in software mode
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \brief      pull NSS pin low in software mode
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -333,8 +333,8 @@ void spi_nss_internal_low(uint32_t spi_periph)
 
 /*!
     \brief      enable SPI DMA send or receive 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
-    \param[in]  dma: SPI DMA mode 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  dma: SPI DMA mode
                 only one parameter can be selected which is shown as below:
       \arg        SPI_DMA_TRANSMIT: SPI transmit data using DMA
       \arg        SPI_DMA_RECEIVE: SPI receive data using DMA
@@ -352,8 +352,8 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
 
 /*!
     \brief      disable SPI DMA send or receive 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
-    \param[in]  dma: SPI DMA mode 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  dma: SPI DMA mode
                 only one parameter can be selected which is shown as below:
       \arg        SPI_DMA_TRANSMIT: SPI transmit data using DMA
       \arg        SPI_DMA_RECEIVE: SPI receive data using DMA
@@ -371,7 +371,7 @@ void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
 
 /*!
     \brief      configure SPI/I2S data frame format
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[in]  frame_format: SPI frame size
                 only one parameter can be selected which is shown as below:
       \arg        SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
@@ -383,13 +383,13 @@ void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format
 {
     /* clear SPI_CTL0_FF16 bit */
     SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
-    /* configure SPI_CTL0_FF16 bit */
+    /* confige SPI_CTL0_FF16 bit */
     SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
 }
 
 /*!
     \brief      SPI transmit data
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[in]  data: 16-bit data
     \param[out] none
     \retval     none
@@ -401,7 +401,7 @@ void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
 
 /*!
     \brief      SPI receive data
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     16-bit data
 */
@@ -412,7 +412,7 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph)
 
 /*!
     \brief      configure SPI bidirectional transfer direction
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[in]  transfer_direction: SPI transfer direction
                 only one parameter can be selected which is shown as below:
       \arg        SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
@@ -433,7 +433,7 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di
 
 /*!
     \brief      set CRC polynomial 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[in]  crc_poly: CRC polynomial value
     \param[out] none
     \retval     none
@@ -448,7 +448,7 @@ void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
 
 /*!
     \brief      get SPI CRC polynomial 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     16-bit CRC polynomial
 */
@@ -459,7 +459,7 @@ uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
 
 /*!
     \brief      turn on CRC function 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -470,7 +470,7 @@ void spi_crc_on(uint32_t spi_periph)
 
 /*!
     \brief      turn off CRC function 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -481,7 +481,7 @@ void spi_crc_off(uint32_t spi_periph)
 
 /*!
     \brief      SPI next data is CRC value
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */
@@ -492,7 +492,7 @@ void spi_crc_next(uint32_t spi_periph)
 
 /*!
     \brief      get SPI CRC send value or receive value
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[in]  crc: SPI crc value
       \arg        SPI_CRC_TX: get transmit crc value
       \arg        SPI_CRC_RX: get receive crc value
@@ -508,10 +508,53 @@ uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
     }
 }
 
-#ifdef GD32F170_190
+/*!
+    \brief      enable SPI TI mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_ti_mode_enable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
+}
+
+/*!
+    \brief      disable SPI TI mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_ti_mode_disable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
+}
+
+/*!
+    \brief      enable SPI NSS pulse mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_nssp_mode_enable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
+}
+
+/*!
+    \brief      disable SPI NSS pulse mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_nssp_mode_disable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
+}
+
 /*!
     \brief      enable quad wire SPI
-    \param[in]  spi_periph: SPIx(only x=1)
+    \param[in]  spi_periph: SPI1
     \param[out] none
     \retval     none
 */
@@ -522,7 +565,7 @@ void qspi_enable(uint32_t spi_periph)
 
 /*!
     \brief      disable quad wire SPI 
-    \param[in]  spi_periph: SPIx(only x=1)
+    \param[in]  spi_periph: SPI1
     \param[out] none
     \retval     none
 */
@@ -533,7 +576,7 @@ void qspi_disable(uint32_t spi_periph)
 
 /*!
     \brief      enable quad wire SPI write 
-    \param[in]  spi_periph: SPIx(only x=1)
+    \param[in]  spi_periph: SPI1
     \param[out] none
     \retval     none
 */
@@ -544,7 +587,7 @@ void qspi_write_enable(uint32_t spi_periph)
 
 /*!
     \brief      enable quad wire SPI read 
-    \param[in]  spi_periph: SPIx(only x=1)
+    \param[in]  spi_periph: SPI1
     \param[out] none
     \retval     none
 */
@@ -555,7 +598,7 @@ void qspi_read_enable(uint32_t spi_periph)
 
 /*!
     \brief      enable SPI_IO2 and SPI_IO3 pin output 
-    \param[in]  spi_periph: SPIx(only x=1)
+    \param[in]  spi_periph: SPI1
     \param[out] none
     \retval     none
 */
@@ -566,7 +609,7 @@ void qspi_io23_output_enable(uint32_t spi_periph)
 
  /*!
     \brief      disable SPI_IO2 and SPI_IO3 pin output 
-    \param[in]  spi_periph: SPIx(only x=1)
+    \param[in]  spi_periph: SPI1
     \param[out] none
     \retval     none
 */
@@ -574,17 +617,16 @@ void qspi_io23_output_enable(uint32_t spi_periph)
 {
     SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
 }
-#endif  /* GD32F170_190 */
-
 
 /*!
     \brief      enable SPI and I2S interrupt 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[in]  interrupt: SPI/I2S interrupt
+                only one parameter can be selected which is shown as below:
       \arg        SPI_I2S_INT_TBE: transmit buffer empty interrupt
       \arg        SPI_I2S_INT_RBNE: receive buffer not empty interrupt
-      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error
-                                   and transmission underrun error interrupt
+      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
+                                   transmission underrun error and format error interrupt
     \param[out] none
     \retval     none
 */
@@ -592,31 +634,31 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
 {
     switch(interrupt){
     /* SPI/I2S transmit buffer empty interrupt */
-    case SPI_I2S_INT_TBE :
+    case SPI_I2S_INT_TBE:
         SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
         break;
     /* SPI/I2S receive buffer not empty interrupt */
-    case SPI_I2S_INT_RBNE :
+    case SPI_I2S_INT_RBNE:
         SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
         break;
     /* SPI/I2S error */
-    case SPI_I2S_INT_ERR :
+    case SPI_I2S_INT_ERR:
         SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
         break;
-    default :
+    default:
         break;
     }
 }
 
 /*!
     \brief      disable SPI and I2S interrupt 
-    \param[in]  spi_periph: SPIx(x=0,1,2)
-    \param[in]  interrupt:
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  interrupt: SPI/I2S interrupt
                 only one parameter can be selected which is shown as below:
       \arg        SPI_I2S_INT_TBE: transmit buffer empty interrupt
       \arg        SPI_I2S_INT_RBNE: receive buffer not empty interrupt
-      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error
-                                   and transmission underrun error interrupt
+      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
+                                   transmission underrun error and format error interrupt
     \param[out] none
     \retval     none
 */
@@ -624,24 +666,25 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
 {
     switch(interrupt){
     /* SPI/I2S transmit buffer empty interrupt */
-    case SPI_I2S_INT_TBE :
+    case SPI_I2S_INT_TBE:
         SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
         break;
     /* SPI/I2S receive buffer not empty interrupt */
-    case SPI_I2S_INT_RBNE :
+    case SPI_I2S_INT_RBNE:
         SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
         break;
     /* SPI/I2S error */
-    case SPI_I2S_INT_ERR :
+    case SPI_I2S_INT_ERR:
         SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
         break;
     default :
         break;
     }
 }
+
 /*!
     \brief      get SPI and I2S interrupt flag status
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[in]  interrupt: SPI/I2S interrupt flag status
                 only one parameter can be selected which is shown as below:
       \arg        SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
@@ -650,6 +693,7 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
       \arg        SPI_INT_FLAG_CONFERR: config error interrupt flag
       \arg        SPI_INT_FLAG_CRCERR: CRC error interrupt flag
       \arg        I2S_INT_FLAG_TXURERR: underrun error interrupt flag
+      \arg        SPI_I2S_INT_FLAG_FERR: format error interrupt flag
     \param[out] none
     \retval     FlagStatus: SET or RESET
 */
@@ -689,10 +733,15 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
         reg1 = reg1 & SPI_STAT_TXURERR;
         reg2 = reg2 & SPI_CTL1_ERRIE;
         break;
+    /* SPI/I2S format error interrupt */
+    case SPI_I2S_INT_FLAG_FERR:
+        reg1 = reg1 & SPI_STAT_FERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
     default :
         break;
     }
-    /* get SPI/I2S interrupt flag status */
+    /*get SPI/I2S interrupt flag status */
     if((0U != reg1) && (0U != reg2)){
         return SET;
     }else{
@@ -702,7 +751,7 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
 
 /*!
     \brief      get SPI and I2S flag status
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[in]  flag: SPI/I2S flag status
                 one or more parameters can be selected which are shown as below:
       \arg        SPI_FLAG_TBE: transmit buffer empty flag
@@ -718,6 +767,7 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
       \arg        I2S_FLAG_RXORERR: overrun error flag
       \arg        I2S_FLAG_TXURERR: underrun error flag
       \arg        I2S_FLAG_CH: channel side flag
+      \arg        I2S_FLAG_FERR: format error interrupt flag
     \param[out] none
     \retval     FlagStatus: SET or RESET
 */
@@ -732,7 +782,7 @@ FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
 
 /*!
     \brief      clear SPI CRC error flag status
-    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_periph: SPIx(x=0,1)
     \param[out] none
     \retval     none
 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_syscfg.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_syscfg.c

@@ -1,18 +1,39 @@
 /*!
-    \file  gd32f1x0_syscfg.c
+    \file  gd32f3x0_syscfg.c
     \brief SYSCFG driver
+
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
-    Copyright (C) 2017 GigaDevice
-
-    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_syscfg.h"
+#include "gd32f3x0_syscfg.h"
 
 /*!
     \brief      reset the SYSCFG registers
@@ -29,6 +50,7 @@ void syscfg_deinit(void)
 /*!
     \brief      enable the DMA channels remapping
     \param[in]  syscfg_dma_remap: specify the DMA channels to remap
+                one or more parameters can be selected which is shown as below:
       \arg        SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
       \arg        SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
       \arg        SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
@@ -45,6 +67,7 @@ void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap)
 /*!
     \brief      disable the DMA channels remapping
     \param[in]  syscfg_dma_remap: specify the DMA channels to remap
+                one or more parameters can be selected which is shown as below:
       \arg        SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
       \arg        SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
       \arg        SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
@@ -80,58 +103,13 @@ void syscfg_high_current_disable(void)
     SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE;
 }
 
-#ifdef GD32F170_190
-/*!
-    \brief      configure the VLCD intermediate voltage rail
-    \param[in]  vlcd_bias: specify VLCD bias
-      \arg        VLCD_BIAS1_2_RAIL1: VLCD bias is 1/2, using rail1
-      \arg        VLCD_BIAS1_2_RAIL2: VLCD bias is 1/2, using rail2
-      \arg        VLCD_BIAS1_2_RAIL3: VLCD bias is 1/2, using rail3
-      \arg        VLCD_BIAS1_3_RAIL1_2: VLCD bias is 1/3, using rail1 and rail2
-      \arg        VLCD_BIAS1_3_RAIL1_3: VLCD bias is 1/3, using rail1 and rail3
-      \arg        VLCD_BIAS1_4_RAILALL: VLCD bias is 1/4, using all rails
-    \param[out] none
-    \retval     none
-*/
-void syscfg_vlcd_rail_config(uint8_t vlcd_bias)
-{
-    uint32_t cfg1 = SYSCFG_CFG1;
-
-    /* Clear system configuration register 1 */
-    SYSCFG_CFG1 = 0U;
-
-    switch(vlcd_bias){
-    /* according to VLCD bias, configure rails combination */
-    case VLCD_BIAS1_2_RAIL1:
-        SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL1;
-        break;
-    case VLCD_BIAS1_2_RAIL2:
-        SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL2;
-        break;
-    case VLCD_BIAS1_2_RAIL3:
-        SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL3;
-        break;
-    case VLCD_BIAS1_3_RAIL1_2:
-        SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL2 | SYSCFG_VLCD_RAIL1;
-        break;
-    case VLCD_BIAS1_3_RAIL1_3:
-        SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL3 | SYSCFG_VLCD_RAIL1;
-        break;
-    case VLCD_BIAS1_4_RAILALL:
-        SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL3 | SYSCFG_VLCD_RAIL2 | SYSCFG_VLCD_RAIL1;
-        break;
-    default:
-        SYSCFG_CFG1 = cfg1;
-        break;
-    }
-}
-#endif /* GD32F170_190 */
-
 /*!
     \brief      configure the GPIO pin as EXTI Line
     \param[in]  exti_port: specify the GPIO port used in EXTI
+                only one parameter can be selected which is shown as below:
       \arg        EXTI_SOURCE_GPIOx(x = A,B,C,D,F): EXTI GPIO port
     \param[in]  exti_pin: specify the EXTI line
+                only one parameter can be selected which is shown as below:
       \arg        EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin
     \param[out] none
     \retval     none
@@ -174,7 +152,8 @@ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
 /*!
     \brief      connect TIMER0/14/15/16 break input to the selected parameter
     \param[in]  syscfg_lock: Specify the parameter to be connected
-      \arg        SYSCFG_LOCK_LOCKUP: Cortex-M3 lockup output connected to the break input
+                one or more parameters can be selected which is shown as below:
+      \arg        SYSCFG_LOCK_LOCKUP: Cortex-M4 lockup output connected to the break input
       \arg        SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input
       \arg        SYSCFG_LOCK_LVD: LVD interrupt connected to the break input
     \param[out] none
@@ -212,3 +191,37 @@ void syscfg_flag_clear(uint32_t syscfg_flag)
 {
     SYSCFG_CFG2 |= (uint32_t) syscfg_flag;
 }
+
+/*!
+    \brief      configure the I/O compensation cell
+    \param[in]  syscfg_compensation: specifies the I/O compensation cell mode
+                only one parameter can be selected which is shown as below:
+      \arg        SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled
+      \arg        SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled
+    \param[out] none
+    \retval     none
+*/
+void syscfg_compensation_config(uint32_t syscfg_compensation)
+{
+    uint32_t reg;
+
+    reg = SYSCFG_CPSCTL;
+    /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */
+    reg &= ~SYSCFG_CPSCTL_CPS_EN;
+    SYSCFG_CPSCTL = (reg | syscfg_compensation);
+}
+
+/*!
+    \brief      check if the I/O compensation cell ready flag is set or not
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+  */
+FlagStatus syscfg_cps_rdy_flag_get(void)
+{
+    if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}

Librarys/GD32F1x0_Drivers/src/gd32f1x0_timer.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_timer.c

@@ -1,17 +1,15 @@
 /*!
-    \file  gd32f1x0_timer.c
+    \file  gd32f3x0_timer.c
     \brief TIMER driver
 
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
     Copyright (c) 2019, GigaDevice Semiconductor Inc.
 
+
     Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:
 
@@ -36,11 +34,12 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_timer.h"
+
+#include "gd32f3x0_timer.h"
 
 /*!
     \brief      deinit a TIMER
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[out] none
     \retval     none
 */
@@ -62,11 +61,13 @@ void timer_deinit(uint32_t timer_periph)
         rcu_periph_reset_enable(RCU_TIMER2RST);
         rcu_periph_reset_disable(RCU_TIMER2RST);
         break;
+#ifdef GD32F350
     case TIMER5:
         /* reset TIMER5 */
         rcu_periph_reset_enable(RCU_TIMER5RST);
         rcu_periph_reset_disable(RCU_TIMER5RST);
         break;
+#endif
     case TIMER13:
         /* reset TIMER13 */
         rcu_periph_reset_enable(RCU_TIMER13RST);
@@ -111,7 +112,7 @@ void timer_struct_para_init(timer_parameter_struct* initpara)
 
 /*!
     \brief      initialize TIMER counter
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[in]  timer_initpara: init parameter struct
                 prescaler: prescaler value of the counter clock,0~65535
                 alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH
@@ -155,7 +156,7 @@ void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
 
 /*!
     \brief      enable a TIMER
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[out] none
     \retval     none
 */
@@ -166,7 +167,7 @@ void timer_enable(uint32_t timer_periph)
 
 /*!
     \brief      disable a TIMER
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[out] none
     \retval     none
 */
@@ -177,7 +178,7 @@ void timer_disable(uint32_t timer_periph)
 
 /*!
     \brief      enable the auto reload shadow function
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[out] none
     \retval     none
 */
@@ -199,7 +200,7 @@ void timer_auto_reload_shadow_disable(uint32_t timer_periph)
 
 /*!
     \brief      enable the update event
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[out] none
     \retval     none
 */
@@ -210,7 +211,7 @@ void timer_update_event_enable(uint32_t timer_periph)
 
 /*!
     \brief      disable the update event
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[out] none
     \retval     none
 */
@@ -261,7 +262,7 @@ void timer_counter_down_direction(uint32_t timer_periph)
 
 /*!
     \brief      configure TIMER prescaler
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[in]  prescaler: prescaler value
     \param[in]  pscreload: prescaler reload mode
                 only one parameter can be selected which is shown as below:
@@ -281,8 +282,8 @@ void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t p
 
 /*!
     \brief      configure TIMER repetition register value
-    \param[in]  timer_periph: TIMERx(x=0,14,15,16)
-    \param[in]  repetition: the counter repetition value
+    \param[in]  timer_periph: TIMERx(x=0,15,16)
+    \param[in]  repetition: the counter repetition value,0~255
     \param[out] none
     \retval     none
 */
@@ -293,7 +294,7 @@ void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
  
 /*!
     \brief      configure TIMER autoreload register value
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[in]  autoreload: the counter auto-reload value
     \param[out] none
     \retval     none
@@ -305,7 +306,7 @@ void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
 
 /*!
     \brief      configure TIMER counter register value
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[in]  counter: the counter value
     \param[out] none
     \retval     none
@@ -317,7 +318,7 @@ void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
 
 /*!
     \brief      read TIMER counter value
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[out] none
     \retval     counter value
 */         
@@ -330,7 +331,7 @@ uint32_t timer_counter_read(uint32_t timer_periph)
 
 /*!
     \brief      read TIMER prescaler value
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[out] none
     \retval     prescaler register value
 */         
@@ -343,7 +344,7 @@ uint16_t timer_prescaler_read(uint32_t timer_periph)
 
 /*!
     \brief      configure TIMER single pulse mode
-    \param[in]  timer_periph: TIMERx(x=0..2,14..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,14..16),TIMER5 just for GD32F350
     \param[in]  spmode:
                 only one parameter can be selected which is shown as below:
       \arg        TIMER_SP_MODE_SINGLE: single pulse mode
@@ -364,7 +365,7 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode)
 
 /*!
     \brief      configure TIMER update source 
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
     \param[in]  update:
                 only one parameter can be selected which is shown as below:
       \arg        TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
@@ -409,7 +410,7 @@ void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear)
     \param[in]  timer_periph: please refer to the following parameters 
     \param[in]  interrupt: timer interrupt enable source
                 only one parameter can be selected which is shown as below:
-      \arg        TIMER_INT_UP: update interrupt enable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+      \arg        TIMER_INT_UP: update interrupt enable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
       \arg        TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..2,13..16)
       \arg        TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..2,14)
       \arg        TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..2)
@@ -430,7 +431,7 @@ void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
     \param[in]  timer_periph: please refer to the following parameters
     \param[in]  interrupt: timer interrupt source disable
                 only one parameter can be selected which is shown as below:
-      \arg        TIMER_INT_UP: update interrupt disable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+      \arg        TIMER_INT_UP: update interrupt disable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
       \arg        TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..2,13..16)
       \arg        TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..2,14)
       \arg        TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..2)
@@ -451,7 +452,7 @@ void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
     \param[in]  timer_periph: please refer to the following parameters
     \param[in]  interrupt: the timer interrupt bits
                 only one parameter can be selected which is shown as below:
-      \arg        TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+      \arg        TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
       \arg        TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..2,13..16)
       \arg        TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..2,14)
       \arg        TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..2)
@@ -478,7 +479,7 @@ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
     \param[in]  timer_periph: please refer to the following parameters
     \param[in]  interrupt: the timer interrupt bits
                 only one parameter can be selected which is shown as below:
-      \arg        TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+      \arg        TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
       \arg        TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..2,13..16)
       \arg        TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..2,14)
       \arg        TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..2)
@@ -499,7 +500,7 @@ void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
     \param[in]  timer_periph: please refer to the following parameters
     \param[in]  flag: the timer interrupt flags
                 only one parameter can be selected which is shown as below:
-      \arg        TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+      \arg        TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
       \arg        TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16)
       \arg        TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14)
       \arg        TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2)
@@ -528,7 +529,7 @@ FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
     \param[in]  timer_periph: please refer to the following parameters
     \param[in]  flag: the timer interrupt flags
                 only one parameter can be selected which is shown as below:
-      \arg        TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F150/GD32F190
+      \arg        TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
       \arg        TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16)
       \arg        TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14)
       \arg        TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2)
@@ -553,7 +554,7 @@ void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
     \param[in]  timer_periph: please refer to the following parameters
     \param[in]  dma: specify which DMA to enable
                 one or more parameters can be selected which is shown as below:
-      \arg        TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F150/GD32F190
+      \arg        TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350
       \arg        TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16)
       \arg        TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14)
       \arg        TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2)
@@ -573,7 +574,7 @@ void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
     \param[in]  timer_periph: please refer to the following parameters
     \param[in]  dma: specify which DMA to disable
                 one or more parameters can be selected which are shown as below:
-      \arg        TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F150/GD32F190
+      \arg        TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350
       \arg        TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16)
       \arg        TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14)
       \arg        TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2)
@@ -651,7 +652,7 @@ void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uin
     \param[in]  timer_periph: please refer to the following parameters
     \param[in]  event: the timer software event generation sources
                 one or more parameters can be selected which are shown as below:
-      \arg        TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..2,13..16), TIMER5 just for GD32F150/GD32F190
+      \arg        TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..2,13..16), TIMER5 just for GD32F350
       \arg        TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..2,13..16) 
       \arg        TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..2,14)
       \arg        TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..2) 
@@ -1236,7 +1237,7 @@ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channe
 
 /*!
     \brief      configure TIMER channel complementary output polarity 
-    \param[in]  timer_periph: TIMERx(x=0..2,13..16)
+    \param[in]  timer_periph: TIMERx(x=0..2,14)
     \param[in]  channel: 
                 only one parameter can be selected which is shown as below:
       \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
@@ -1721,12 +1722,12 @@ void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger
 
 /*!
     \brief      select TIMER master mode output trigger source 
-    \param[in]  timer_periph: TIMERx(x=0..2,14),TIMER5 just for GD32F150/GD32F190
+    \param[in]  timer_periph: TIMERx(x=0..2,14),TIMER5 just for GD32F350
     \param[in]  outrigger: 
                 only one parameter can be selected which is shown as below:
-      \arg        TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F150/GD32F190)
-      \arg        TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F150/GD32F190)
-      \arg        TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F150/GD32F190)
+      \arg        TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350)
+      \arg        TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350)
+      \arg        TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350)
       \arg        TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO
       \arg        TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..2,14))
       \arg        TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..2,14))
@@ -2019,8 +2020,6 @@ void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap)
     TIMER_IRMP(timer_periph) = (uint32_t)remap;
 }
 
-#ifdef GD32F170_190
-
 /*!
     \brief      configure TIMER write CHxVAL register selection
     \param[in]  timer_periph: TIMERx(x=0..2,13..16)
@@ -2062,5 +2061,3 @@ void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
         /* illegal parameters */
     }
 }
-
-#endif /* GD32F170_190 */

Librarys/GD32F1x0_Drivers/src/gd32f1x0_tsi.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_tsi.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_tsi.c
+    \file  gd32f3x0_tsi.c
     \brief TSI driver
     
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -35,7 +32,8 @@ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWIS
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
 OF SUCH DAMAGE.
 */
-#include "gd32f1x0_tsi.h"
+
+#include "gd32f3x0_tsi.h"
 
 /*!
     \brief      reset TSI peripheral
@@ -61,6 +59,14 @@ void tsi_deinit(void)
       \arg        TSI_CTCDIV_DIV32:  fCTCLK = fHCLK/32
       \arg        TSI_CTCDIV_DIV64:  fCTCLK = fHCLK/64
       \arg        TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128
+      \arg        TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256
+      \arg        TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512
+      \arg        TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024
+      \arg        TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048
+      \arg        TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096
+      \arg        TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192
+      \arg        TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384
+      \arg        TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768
     \param[in]  charge_duration: charge state duration time
                 only one parameter can be selected which is shown as below:
       \arg        TSI_CHARGE_1CTCLK(x=1..16): the duration time of charge state is x CTCLK
@@ -81,27 +87,70 @@ void tsi_deinit(void)
 */
 void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number)
 {
-    if(RESET == (TSI_CTL & TSI_CTL_TSIS)){
-        uint32_t ctl;
-        ctl = TSI_CTL;
-        /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
-        ctl &= ~(TSI_CTL_CTCDIV|TSI_CTL_CTDT|TSI_CTL_CDT|TSI_CTL_MCN);
-        ctl |= (prescaler|charge_duration|transfer_duration|max_number);
-        TSI_CTL = ctl;
+    uint32_t ctl0,ctl1;
+    if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
+        if(TSI_CTCDIV_DIV256 > prescaler){
+            /* config TSI_CTL0 */
+            ctl0 = TSI_CTL0;
+            /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
+            ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
+            ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
+            TSI_CTL0 = ctl0;
+       
+            /* config TSI_CTL1 */
+            ctl1 = TSI_CTL1;
+            ctl1 &= ~TSI_CTL1_CTCDIV;
+            TSI_CTL1 = ctl1;
+        }else{
+            /* config TSI_CTL0 */
+            ctl0 = TSI_CTL0;
+            prescaler &= ~0x08U;
+            /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
+            ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
+            ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
+            TSI_CTL0 = ctl0;
+       
+            /* config TSI_CTL1 */
+            ctl1 = TSI_CTL1;
+            ctl1 |= TSI_CTL1_CTCDIV;
+            TSI_CTL1 = ctl1;
+        }
     }
 }
 
+/*!
+    \brief      enable TSI module 
+    \param[in]  none
+    \param[out] none
+    \retval     none 
+*/
+void tsi_enable(void)
+{
+    TSI_CTL0 |= TSI_CTL0_TSIEN;
+}
+
+/*!
+    \brief      disable TSI module 
+    \param[in]  none
+    \param[out] none
+    \retval     none 
+*/
+void tsi_disable(void)
+{
+    TSI_CTL0 &= ~TSI_CTL0_TSIEN;
+}
+
 /*!
     \brief      enable sample pin 
     \param[in]  sample: sample pin
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_SAMPCFG_GxPy( x=0..5,y=0..3):pin y of group x is sample pin     
     \param[out] none
     \retval     none 
 */
 void tsi_sample_pin_enable(uint32_t sample)
-{ 
-    if(RESET == (TSI_CTL & TSI_CTL_TSIS)){
+{
+    if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
         TSI_SAMPCFG |= sample;
     }
 }
@@ -109,14 +158,14 @@ void tsi_sample_pin_enable(uint32_t sample)
 /*!
     \brief      disable sample pin 
     \param[in]  sample: sample pin
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_SAMPCFG_GxPy( x=0..5,y=0..3): pin y of group x is sample pin     
     \param[out] none
     \retval     none 
 */
 void tsi_sample_pin_disable(uint32_t sample)
 { 
-    if(RESET == (TSI_CTL & TSI_CTL_TSIS)){
+    if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
         TSI_SAMPCFG &=  ~sample;
     }
 }
@@ -124,7 +173,7 @@ void tsi_sample_pin_disable(uint32_t sample)
 /*!
     \brief      enable channel pin 
     \param[in]  channel: channel pin
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x
     \param[out] none
     \retval     none 
@@ -137,60 +186,49 @@ void tsi_channel_pin_enable(uint32_t channel)
 /*!
     \brief      disable channel pin 
     \param[in]  channel: channel pin
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x
     \param[out] none
     \retval     none 
 */
 void tsi_channel_pin_disable(uint32_t channel)
 {
-    TSI_CHCFG &=  ~channel;
+    TSI_CHCFG &= ~channel;
 }
 
 /*!
-    \brief      configure charge plus and transfer plus 
-    \param[in]  prescaler: CTCLK clock division factor
-                only one parameter can be selected which is shown as below:
-      \arg        TSI_CTCDIV_DIV1:   fCTCLK = fHCLK
-      \arg        TSI_CTCDIV_DIV2:   fCTCLK = fHCLK/2
-      \arg        TSI_CTCDIV_DIV4:   fCTCLK = fHCLK/4
-      \arg        TSI_CTCDIV_DIV8:   fCTCLK = fHCLK/6
-      \arg        TSI_CTCDIV_DIV16:  fCTCLK = fHCLK/8
-      \arg        TSI_CTCDIV_DIV32:  fCTCLK = fHCLK/32
-      \arg        TSI_CTCDIV_DIV64:  fCTCLK = fHCLK/64
-      \arg        TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128
-    \param[in]  charge_duration: charge state duration time
-                only one parameter can be selected which is shown as below:
-      \arg        TSI_CHARGE_xCTCLK(x=1..16): the duration time of charge state is x CTCLK
-    \param[in]  transfer_duration: charge transfer state duration time
-                only one parameter can be selected which is shown as below:
-      \arg        TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK
+    \brief      configure TSI triggering by software 
+    \param[in]  none
     \param[out] none
-    \retval     none
+    \retval     none 
 */
-void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration)
+void tsi_sofeware_mode_config(void)
 {
-    if(RESET == (TSI_CTL & TSI_CTL_TSIS)){
-        uint32_t ctl;
-        ctl = TSI_CTL;
-        /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
-        ctl &= ~(TSI_CTL_CTCDIV|TSI_CTL_CTDT|TSI_CTL_CDT);
-        ctl |= (prescaler|charge_duration|transfer_duration);
-        TSI_CTL = ctl;
+    if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
+        TSI_CTL0 &= ~TSI_CTL0_TRGMOD;
     }
 }
 
 /*!
-    \brief      configure TSI triggering by software 
+    \brief      start a charge-transfer sequence when TSI is in software trigger mode
     \param[in]  none
     \param[out] none
     \retval     none 
 */
-void tsi_sofeware_mode_config(void)
+void tsi_software_start(void)
 {
-    if(RESET == (TSI_CTL & TSI_CTL_TSIS)){
-        TSI_CTL &= ~TSI_CTL_TRGMOD;
-    }
+    TSI_CTL0 |= TSI_CTL0_TSIS;
+}
+
+/*!
+    \brief      stop a charge-transfer sequence when TSI is in software trigger mode
+    \param[in]  none
+    \param[out] none
+    \retval     none 
+*/
+void tsi_software_stop(void)
+{
+    TSI_CTL0 &= ~TSI_CTL0_TSIS;
 }
 
 /*!
@@ -204,14 +242,14 @@ void tsi_sofeware_mode_config(void)
 */
 void tsi_hardware_mode_config(uint8_t trigger_edge)
 {
-    if(RESET == (TSI_CTL & TSI_CTL_TSIS)){
+    if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
         /*enable hardware mode*/
-        TSI_CTL |= TSI_CTL_TRGMOD;
+        TSI_CTL0 |= TSI_CTL0_TRGMOD;
         /*configure the edge type in hardware trigger mode*/
-        if(TSI_FALLING_TRIGGER == (uint32_t)trigger_edge){
-            TSI_CTL &= ~TSI_CTL_EGSEL;
+        if(TSI_FALLING_TRIGGER == trigger_edge){
+            TSI_CTL0 &= ~TSI_CTL0_EGSEL;
         }else{
-            TSI_CTL |= TSI_CTL_EGSEL;
+            TSI_CTL0 |= TSI_CTL0_EGSEL;
         }
     }    
 }
@@ -223,89 +261,19 @@ void tsi_hardware_mode_config(uint8_t trigger_edge)
       \arg        TSI_OUTPUT_LOW:     TSI pin will output low when IDLE 
       \arg        TSI_INPUT_FLOATING: TSI pin will keep input_floating when IDLE
     \param[out] none
-    \retval     none 
+    \retval     none
 */
 void tsi_pin_mode_config(uint8_t pin_mode)
 {
-    if(RESET == (TSI_CTL & TSI_CTL_TSIS)){
+    if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
         if(TSI_OUTPUT_LOW == pin_mode){
-            TSI_CTL &= ~TSI_CTL_PINMOD;
+            TSI_CTL0 &= ~TSI_CTL0_PINMOD;
         }else{
-            TSI_CTL |= TSI_CTL_PINMOD;
+            TSI_CTL0 |= TSI_CTL0_PINMOD;
         }
     }
 }
 
-/*!
-    \brief      configure the max cycle number of a charge-transfer sequence 
-    \param[in]  max_number: max cycle number
-                only one parameter can be selected which is shown as below:
-      \arg        TSI_MAXNUM255:   the max cycle number of a sequence is 255
-      \arg        TSI_MAXNUM511:   the max cycle number of a sequence is 511
-      \arg        TSI_MAXNUM1023:  the max cycle number of a sequence is 1023
-      \arg        TSI_MAXNUM2047:  the max cycle number of a sequence is 2047
-      \arg        TSI_MAXNUM4095:  the max cycle number of a sequence is 4095
-      \arg        TSI_MAXNUM8191:  the max cycle number of a sequence is 8191
-      \arg        TSI_MAXNUM16383: the max cycle number of a sequence is 16383
-    \param[out] none
-    \retval     none 
-*/
-void tsi_max_number_config(uint32_t max_number)
-{
-    if(RESET == (TSI_CTL & TSI_CTL_TSIS)){
-        uint32_t maxnum;
-        maxnum = TSI_CTL;
-        /*configure the max cycle number of a charge-transfer sequence*/
-        maxnum &= ~TSI_CTL_MCN;
-        maxnum |= max_number;
-        TSI_CTL = maxnum;
-    }
-}
-
-/*!
-    \brief      start a charge-transfer sequence when TSI is in software trigger mode
-    \param[in]  none
-    \param[out] none
-    \retval     none 
-*/
-void tsi_software_start(void)
-{
-    TSI_CTL |= TSI_CTL_TSIS;
-}
-
-/*!
-    \brief      stop a charge-transfer sequence when TSI is in software trigger mode
-    \param[in]  none
-    \param[out] none
-    \retval     none 
-*/
-void tsi_software_stop(void)
-{
-    TSI_CTL &= ~TSI_CTL_TSIS;
-}
-
-/*!
-    \brief      enable TSI module 
-    \param[in]  none
-    \param[out] none
-    \retval     none 
-*/
-void tsi_enable(void)
-{
-    TSI_CTL |= TSI_CTL_TSIEN;
-}
-
-/*!
-    \brief      disable TSI module 
-    \param[in]  none
-    \param[out] none
-    \retval     none 
-*/
-void tsi_disable(void)
-{
-    TSI_CTL &= ~TSI_CTL_TSIEN;
-}
-
 /*!
     \brief      configure extend charge state 
     \param[in]  extend: enable or disable extend charge state
@@ -316,39 +284,151 @@ void tsi_disable(void)
                 only one parameter can be selected which is shown as below:
       \arg        TSI_EXTEND_DIV1: fECCLK = fHCLK
       \arg        TSI_EXTEND_DIV2: fECCLK = fHCLK/2
+      \arg        TSI_EXTEND_DIV3: fECCLK = fHCLK/3
+      \arg        TSI_EXTEND_DIV4: fECCLK = fHCLK/4
+      \arg        TSI_EXTEND_DIV5: fECCLK = fHCLK/5
+      \arg        TSI_EXTEND_DIV6: fECCLK = fHCLK/6
+      \arg        TSI_EXTEND_DIV7: fECCLK = fHCLK/7
+      \arg        TSI_EXTEND_DIV8: fECCLK = fHCLK/8
     \param[in]  max_duration: value range 1...128,extend charge state maximum duration time is 1*tECCLK~128*tECCLK
     \param[out] none
     \retval     none 
 */
 void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration)
 {
-    if(RESET == (TSI_CTL & TSI_CTL_TSIS)){
-        uint32_t ctl;
+    uint32_t ctl0,ctl1;
+    if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
         if(DISABLE == extend){
             /*disable extend charge state*/
-            TSI_CTL &= ~TSI_CTL_ECEN;
+            TSI_CTL0 &= ~TSI_CTL0_ECEN;
         }else{
-            /*configure extend charge state maximum duration time*/
-            ctl = TSI_CTL;
-            ctl &= ~TSI_CTL_ECDT;
-            ctl |= TSI_EXTENDMAX((uint32_t)(max_duration-1U));
-            TSI_CTL = ctl;
-            /*configure ECCLK clock division factor*/
-            if(TSI_EXTEND_DIV1 == prescaler){
-                TSI_CTL &= ~TSI_CTL_ECDIV;
+            if(TSI_EXTEND_DIV3 > prescaler){
+                /*configure extend charge state maximum duration time*/
+                ctl0 = TSI_CTL0;
+                ctl0 &= ~TSI_CTL0_ECDT;
+                ctl0 |= TSI_EXTENDMAX((max_duration-1U));
+                TSI_CTL0 = ctl0;
+                /*configure ECCLK clock division factor*/
+                ctl0 = TSI_CTL0;
+                ctl0 &= ~TSI_CTL0_ECDIV;
+                ctl0 |= (uint32_t)prescaler<<15U;
+                TSI_CTL0 = ctl0;
+                /*enable extend charge state*/
+                TSI_CTL0 |= TSI_CTL0_ECEN;
             }else{
-                TSI_CTL |= TSI_CTL_ECDIV;
+                /*configure extend charge state maximum duration time*/
+                ctl0 = TSI_CTL0;
+                ctl0 &= ~TSI_CTL0_ECDT;
+                ctl0 |= TSI_EXTENDMAX((max_duration-1U));
+                TSI_CTL0 = ctl0;
+                /*configure ECCLK clock division factor*/
+                ctl0 = TSI_CTL0;
+                ctl0 &= ~TSI_CTL0_ECDIV;
+                ctl0 |= (prescaler & 0x01U)<<15U;
+                TSI_CTL0 = ctl0;
+                ctl1 = TSI_CTL1;
+                ctl1 &= ~TSI_CTL1_ECDIV;
+                ctl1 |= (prescaler & 0x06U)<<28U;
+                TSI_CTL1 = ctl1;
+                /*enable extend charge state*/
+                TSI_CTL0 |= TSI_CTL0_ECEN;
             }
-            /*enable extend charge state*/
-            TSI_CTL |= TSI_CTL_ECEN;
         }
     }
 }
 
 /*!
-    \brief      switch on hysteresis pin
-    \param[in]  group_pin: select pin which will be switched on hysteresis
+    \brief      configure charge plus and transfer plus 
+    \param[in]  prescaler: CTCLK clock division factor
+                only one parameter can be selected which is shown as below:
+      \arg        TSI_CTCDIV_DIV1:   fCTCLK = fHCLK
+      \arg        TSI_CTCDIV_DIV2:   fCTCLK = fHCLK/2
+      \arg        TSI_CTCDIV_DIV4:   fCTCLK = fHCLK/4
+      \arg        TSI_CTCDIV_DIV8:   fCTCLK = fHCLK/8
+      \arg        TSI_CTCDIV_DIV16:  fCTCLK = fHCLK/16
+      \arg        TSI_CTCDIV_DIV32:  fCTCLK = fHCLK/32
+      \arg        TSI_CTCDIV_DIV64:  fCTCLK = fHCLK/64
+      \arg        TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128
+      \arg        TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256
+      \arg        TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512
+      \arg        TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024
+      \arg        TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048
+      \arg        TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096
+      \arg        TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192
+      \arg        TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384
+      \arg        TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768
+    \param[in]  charge_duration: charge state duration time
+                only one parameter can be selected which is shown as below:
+      \arg        TSI_CHARGE_xCTCLK(x=1..16): the duration time of charge state is x CTCLK
+    \param[in]  transfer_duration: charge transfer state duration time
                 only one parameter can be selected which is shown as below:
+      \arg        TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK
+    \param[out] none
+    \retval     none
+*/
+void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration)
+{
+    uint32_t ctl0,ctl1;
+    if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
+        if(TSI_CTCDIV_DIV256 > prescaler){
+            /* config TSI_CTL0 */
+            ctl0 = TSI_CTL0;
+            /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
+            ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
+            ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
+            TSI_CTL0 = ctl0;
+       
+            /* config TSI_CTL1 */
+            ctl1 = TSI_CTL1;
+            ctl1 &= ~TSI_CTL1_CTCDIV;
+            TSI_CTL1 = ctl1;
+        }else{
+            /* config TSI_CTL */
+            ctl0 = TSI_CTL0;
+            prescaler &= ~0x08U;
+            /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
+            ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
+            ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
+            TSI_CTL0 = ctl0;
+       
+            /* config TSI_CTL2 */
+            ctl1 = TSI_CTL1;
+            ctl1 |= TSI_CTL1_CTCDIV;
+            TSI_CTL1 = ctl1;
+        }
+    }
+}
+
+/*!
+    \brief      configure the max cycle number of a charge-transfer sequence 
+    \param[in]  max_number: max cycle number
+                only one parameter can be selected which is shown as below:
+      \arg        TSI_MAXNUM255:   the max cycle number of a sequence is 255
+      \arg        TSI_MAXNUM511:   the max cycle number of a sequence is 511
+      \arg        TSI_MAXNUM1023:  the max cycle number of a sequence is 1023
+      \arg        TSI_MAXNUM2047:  the max cycle number of a sequence is 2047
+      \arg        TSI_MAXNUM4095:  the max cycle number of a sequence is 4095
+      \arg        TSI_MAXNUM8191:  the max cycle number of a sequence is 8191
+      \arg        TSI_MAXNUM16383: the max cycle number of a sequence is 16383
+    \param[out] none
+    \retval     none 
+*/
+void tsi_max_number_config(uint32_t max_number)
+{
+    if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
+        uint32_t maxnum;
+        maxnum = TSI_CTL0;
+        /*configure the max cycle number of a charge-transfer sequence*/
+        maxnum &= ~TSI_CTL0_MCN;
+        maxnum |= max_number;
+        TSI_CTL0 = maxnum;
+    }
+}
+
+/*!
+    \brief      switch on hysteresis pin
+    \param[in]  group_pin: select pin which will be switched on hysteresis  
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch on hysteresis
     \param[out] none
     \retval     none 
@@ -360,8 +440,8 @@ void tsi_hysteresis_on(uint32_t group_pin)
 
 /*!
     \brief      switch off hysteresis pin
-    \param[in]  group_pin: select pin which will be switched off hysteresis
-                only one parameter can be selected which is shown as below:
+    \param[in]  group_pin: select pin which will be switched off hysteresis 
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch off hysteresis
     \param[out] none
     \retval     none 
@@ -374,7 +454,7 @@ void tsi_hysteresis_off(uint32_t group_pin)
 /*!
     \brief      switch on analog pin 
     \param[in]  group_pin: select pin which will be switched on analog
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch on analog
     \param[out] none
     \retval     none 
@@ -387,7 +467,7 @@ void tsi_analog_on(uint32_t group_pin)
 /*!
     \brief      switch off analog pin 
     \param[in]  group_pin: select pin which will be switched off analog
-                only one parameter can be selected which is shown as below:
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch off analog
     \param[out] none
     \retval     none 
@@ -401,8 +481,8 @@ void tsi_analog_off(uint32_t group_pin)
     \brief      enable TSI interrupt 
     \param[in]  source: select interrupt which will be enabled
                 only one parameter can be selected which is shown as below:
-      \arg        TSI_INT_CTCF: charge-transfer complete flag interrupt enable
-      \arg        TSI_INTEN_MNERR:  max cycle number error interrupt enable
+      \arg        TSI_INT_CCTCF: charge-transfer complete flag interrupt enable
+      \arg        TSI_INT_MNERR:  max cycle number error interrupt enable
     \param[out] none
     \retval     none 
 */
@@ -415,8 +495,8 @@ void tsi_interrupt_enable(uint32_t source)
     \brief      disable TSI interrupt 
     \param[in]  source: select interrupt which will be disabled
                 only one parameter can be selected which is shown as below:
-      \arg        TSI_INT_CTCF: charge-transfer complete flag interrupt disable
-      \arg        TSI_INTEN_MNERR:  max cycle number error interrupt disable
+      \arg        TSI_INT_CCTCF: charge-transfer complete flag interrupt disable
+      \arg        TSI_INT_MNERR: max cycle number error interrupt disable
     \param[out] none
     \retval     none 
 */
@@ -427,9 +507,9 @@ void tsi_interrupt_disable(uint32_t source)
 
 /*!
     \brief      clear TSI interrupt flag
-    \param[in]  source: select flag which will be cleared
+    \param[in]  flag: select flag which will be cleared
                 only one parameter can be selected which is shown as below:
-      \arg        TSI_INT_FLAG_CTC: clear charge-transfer complete flag
+      \arg        TSI_INT_FLAG_CTCF: clear charge-transfer complete flag
       \arg        TSI_INT_FLAG_MNERR: clear max cycle number error
     \param[out] none
     \retval     none
@@ -440,27 +520,64 @@ void tsi_interrupt_flag_clear(uint32_t flag)
 }
 
 /*!
-    \brief      get TSI interrupt flag
-    \param[in]  status:
+    \brief      get TSI interrupt flag  
+    \param[in]  flag:
                 only one parameter can be selected which is shown as below:
-      \arg        TSI_INT_FLAG_CTC: charge-transfer complete flag
-      \arg        TSI_INT_FLAG_MNERR:  max Cycle Number Error
+      \arg        TSI_INT_FLAG_CTCF: charge-transfer complete flag
+      \arg        TSI_INT_FLAG_MNERR: max Cycle Number Error
     \param[out] none
     \retval     FlagStatus:SET or RESET
 */
-FlagStatus tsi_interrupt_flag_get(uint32_t status)
+FlagStatus tsi_interrupt_flag_get(uint32_t flag)
 {
-    if(TSI_INTF & status){
+    uint32_t interrupt_enable = 0U,interrupt_flag = 0U;
+    interrupt_flag = (TSI_INTF & flag);
+    interrupt_enable = (TSI_INTEN & flag);
+    if(interrupt_flag && interrupt_enable){
         return SET;
-    } else {
+    }else{
         return RESET;
     }
 }
 
 /*!
-    \brief      enbale group 
-    \param[in]  group: select group to be enabled
+    \brief      clear flag
+    \param[in]  flag: select flag which will be cleared
                 only one parameter can be selected which is shown as below:
+      \arg        TSI_FLAG_CTCF: clear charge-transfer complete flag
+      \arg        TSI_FLAG_MNERR: clear max cycle number error
+    \param[out] none
+    \retval     none
+*/
+void tsi_flag_clear(uint32_t flag)
+{
+    TSI_INTC |= flag;
+}
+
+/*!
+    \brief      get flag
+    \param[in]  flag:
+                only one parameter can be selected which is shown as below:
+      \arg        TSI_FLAG_CTCF: charge-transfer complete flag
+      \arg        TSI_FLAG_MNERR: max Cycle Number Error
+    \param[out] none
+    \retval     FlagStatus:SET or RESET
+*/
+FlagStatus tsi_flag_get(uint32_t flag)
+{
+    FlagStatus flag_status;
+    if(TSI_INTF & flag){
+        flag_status = SET;
+    }else{
+        flag_status = RESET;
+    }
+    return flag_status;
+}
+
+/*!
+    \brief      enbale group 
+    \param[in]  group: select group to be enabled 
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_GCTL_GEx(x=0..5): the x group will be enabled 
     \param[out] none
     \retval     none 
@@ -472,8 +589,8 @@ void tsi_group_enable(uint32_t group)
 
 /*!
     \brief      disbale group 
-    \param[in]  group: select group to be disabled
-                only one parameter can be selected which is shown as below:
+    \param[in]  group: select group to be disabled 
+                one or more parameters can be selected which are shown as below:
       \arg        TSI_GCTL_GEx(x=0..5):the x group will be disabled 
     \param[out] none
     \retval     none 
@@ -485,7 +602,7 @@ void tsi_group_disable(uint32_t group)
 
 /*!
     \brief      get group complete status
-    \param[in]  group: select group
+    \param[in]  group: select group 
                 only one parameter can be selected which is shown as below:
       \arg        TSI_GCTL_GCx(x=0..5): get the complete status of group x
     \param[out] none
@@ -493,11 +610,13 @@ void tsi_group_disable(uint32_t group)
 */
 FlagStatus tsi_group_status_get(uint32_t group)
 {
+    FlagStatus flag_status;
     if(TSI_GCTL & group){
-        return SET;
+        flag_status = SET;
     }else{
-        return RESET;
+        flag_status = RESET;
     }
+    return flag_status;
 }
 
 /*!

Librarys/GD32F1x0_Drivers/src/gd32f1x0_wwdgt.c → Librarys/GD32F3x0_Drivers/Source/gd32f3x0_wwdgt.c

@@ -1,12 +1,9 @@
 /*!
-    \file  gd32f1x0_wwdgt.c
+    \file  gd32f3x0_wwdgt.c
     \brief WWDGT driver
-
-    \version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
-    \version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
-    \version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-    \version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
+    
+    \version 2017-06-06, V1.0.0, firmware for GD32F3x0
+    \version 2019-06-01, V2.0.0, firmware for GD32F3x0
 */
 
 /*
@@ -36,8 +33,8 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "gd32f1x0_wwdgt.h"
-#include "gd32f1x0_rcu.h"
+#include "gd32f3x0_wwdgt.h"
+#include "gd32f3x0_rcu.h"
 
 /*!
     \brief      reset the window watchdog timer configuration
@@ -52,30 +49,30 @@ void wwdgt_deinit(void)
 }
 
 /*!
-    \brief      configure the window watchdog timer counter value
-    \param[in]  counter_value: 0x00 - 0x7F
+    \brief      start the window watchdog timer counter
+    \param[in]  none
     \param[out] none
     \retval     none
 */
-void wwdgt_counter_update(uint16_t counter_value)
+void wwdgt_enable(void)
 {
-    uint32_t reg = 0U;
-    
-    reg = WWDGT_CTL & (~WWDGT_CTL_CNT);
-    reg |= (uint32_t)(CTL_CNT((uint32_t)counter_value));
-    
-    WWDGT_CTL = (uint32_t)reg;
+    WWDGT_CTL |= WWDGT_CTL_WDGTEN;
 }
 
 /*!
-    \brief      start the window watchdog timer counter
-    \param[in]  none
+    \brief      configure the window watchdog timer counter value
+    \param[in]  counter_value: 0x00 - 0x7F
     \param[out] none
     \retval     none
 */
-void wwdgt_enable(void)
+void wwdgt_counter_update(uint16_t counter_value)
 {
-    WWDGT_CTL |= WWDGT_CTL_WDGTEN;
+    uint32_t reg = 0x0U;
+    
+    reg = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
+    reg |= (uint32_t)(CTL_CNT(counter_value));
+    
+    WWDGT_CTL = (uint32_t)reg;
 }
 
 /*!
@@ -83,6 +80,7 @@ void wwdgt_enable(void)
     \param[in]  counter: 0x00 - 0x7F   
     \param[in]  window: 0x00 - 0x7F
     \param[in]  prescaler: wwdgt prescaler value
+                only one parameter can be selected which is shown as below:
       \arg        WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
       \arg        WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
       \arg        WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
@@ -92,10 +90,10 @@ void wwdgt_enable(void)
 */
 void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
 {
-    uint32_t reg_cfg = 0U, reg_ctl = 0U;
+    uint32_t reg_cfg = 0x0U, reg_ctl = 0x0U;
 
     /* clear WIN and PSC bits, clear CNT bit */
-    reg_cfg = WWDGT_CFG &(~(WWDGT_CFG_WIN | WWDGT_CFG_PSC));
+    reg_cfg = WWDGT_CFG &(~((uint32_t)WWDGT_CFG_WIN|(uint32_t)WWDGT_CFG_PSC));
     reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
   
     /* configure WIN and PSC bits, configure CNT bit */
@@ -103,7 +101,7 @@ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
     reg_cfg |= (uint32_t)(prescaler);
     reg_ctl |= (uint32_t)(CTL_CNT(counter));
     
-    WWDGT_CFG = (uint32_t)reg_cfg;  
+    WWDGT_CFG = (uint32_t)reg_cfg;
     WWDGT_CTL = (uint32_t)reg_ctl;
 }
 
@@ -126,10 +124,9 @@ void wwdgt_interrupt_enable(void)
 */
 FlagStatus wwdgt_flag_get(void)
 {
-    if(WWDGT_STAT & WWDGT_STAT_EWIF){
+  if(WWDGT_STAT & WWDGT_STAT_EWIF){
         return SET;
-    }
-    
+  }
     return RESET;
 }
 

Project/BMS.uvoptx

@@ -22,7 +22,7 @@
   </DaveTm>
 
   <Target>
-    <TargetName>GD32F130C8</TargetName>
+    <TargetName>GD32F330C8</TargetName>
     <ToolsetNumber>0x4</ToolsetNumber>
     <ToolsetName>ARM-ADS</ToolsetName>
     <TargetOption>
@@ -120,7 +120,7 @@
         <SetRegEntry>
           <Number>0</Number>
           <Key>UL2CM3</Key>
-          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F1x0_64 -FS08000000 -FL010000 -FP0($$Device:GD32F130C8$Flash\GD32F1x0_64.FLM))</Name>
+          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0GD32F3x0 -FL010000 -FS08000000 -FP0($$Device:GD32F330C8$Flash\GD32F3x0.FLM)</Name>
         </SetRegEntry>
       </TargetDriverDllRegistry>
       <Breakpoint/>
@@ -190,7 +190,7 @@
   </Group>
 
   <Group>
-    <GroupName>GD32F1x0_Drivers</GroupName>
+    <GroupName>BSP</GroupName>
     <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
@@ -202,8 +202,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
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-      <FilenameWithoutPath>gd32f1x0_adc.c</FilenameWithoutPath>
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-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-  </Group>
-
-  <Group>
-    <GroupName>StartUP</GroupName>
+    <GroupName>StartUp</GroupName>
     <tvExp>1</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>35</FileNumber>
+      <FileNumber>32</FileNumber>
       <FileType>2</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\Librarys\CMSIS\GD32F1x0\Source\startup_gd32f1x0.s</PathWithFileName>
-      <FilenameWithoutPath>startup_gd32f1x0.s</FilenameWithoutPath>
+      <PathWithFileName>..\Librarys\CMSIS\GD32F3x0\Source\startup_gd32f3x0.s</PathWithFileName>
+      <FilenameWithoutPath>startup_gd32f3x0.s</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>36</FileNumber>
+      <FileNumber>33</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\Librarys\CMSIS\GD32F1x0\Source\system_gd32f1x0.c</PathWithFileName>
-      <FilenameWithoutPath>system_gd32f1x0.c</FilenameWithoutPath>
+      <PathWithFileName>..\Librarys\CMSIS\GD32F3x0\Source\system_gd32f3x0.c</PathWithFileName>
+      <FilenameWithoutPath>system_gd32f3x0.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>

Project/BMS.uvprojx

@@ -7,23 +7,23 @@
 
   <Targets>
     <Target>
-      <TargetName>GD32F130C8</TargetName>
+      <TargetName>GD32F330C8</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <pCCUsed>5060750::V5.06 update 6 (build 750)::.\ARMCC</pCCUsed>
       <uAC6>0</uAC6>
       <TargetOption>
         <TargetCommonOption>
-          <Device>GD32F130C8</Device>
+          <Device>GD32F330C8</Device>
           <Vendor>GigaDevice</Vendor>
-          <PackID>GigaDevice.GD32F1x0_DFP.3.2.0</PackID>
+          <PackID>GigaDevice.GD32F3x0_DFP.2.0.0</PackID>
           <PackURL>http://gd32mcu.com/data/documents/pack/</PackURL>
-          <Cpu>IRAM(0x20000000,0x02000) IROM(0x08000000,0x10000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <Cpu>IRAM(0x20000000,0x02000) IROM(0x08000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F1x0_64 -FS08000000 -FL010000 -FP0($$Device:GD32F130C8$Flash\GD32F1x0_64.FLM))</FlashDriverDll>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F3x0 -FS08000000 -FL010000 -FP0($$Device:GD32F330C8$Flash\GD32F3x0.FLM))</FlashDriverDll>
           <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:GD32F130C8$Device\Include\gd32f1x0.h</RegisterFile>
+          <RegisterFile>$$Device:GD32F330C8$Device\Include\gd32f3x0.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -33,7 +33,7 @@
           <SLE66CMisc></SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:GD32F130C8$SVD\GD32F1x0.svd</SFDFile>
+          <SFDFile>$$Device:GD32F330C8$SVD\GD32F3x0.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
@@ -110,13 +110,13 @@
         </CommonProperty>
         <DllOption>
           <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments> -REMAP</SimDllArguments>
+          <SimDllArguments> -REMAP -MPU</SimDllArguments>
           <SimDlgDll>DCM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments></TargetDllArguments>
+          <TargetDllArguments> -MPU</TargetDllArguments>
           <TargetDlgDll>TCM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
         </DllOption>
         <DebugOption>
           <OPTHX>
@@ -174,7 +174,7 @@
             <AdsLsxf>1</AdsLsxf>
             <RvctClst>0</RvctClst>
             <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
@@ -183,7 +183,7 @@
             <hadIRAM>1</hadIRAM>
             <hadXRAM>0</hadXRAM>
             <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
+            <RvdsVP>2</RvdsVP>
             <RvdsMve>0</RvdsMve>
             <RvdsCdeCp>0</RvdsCdeCp>
             <hadIRAM2>0</hadIRAM2>
@@ -339,7 +339,7 @@
               <MiscControls></MiscControls>
               <Define></Define>
               <Undefine></Undefine>
-              <IncludePath>..\Librarys\CMSIS\5.7.0\Include,..\Librarys\CMSIS\GD32F1x0\Include,..\Librarys\GD32F1x0_Drivers\inc</IncludePath>
+              <IncludePath>..\Librarys\CMSIS\5.7.0\Include,..\Librarys\CMSIS\GD32F3x0\Include,..\Librarys\GD32F3x0_Drivers\include</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -391,195 +391,180 @@
           </Files>
         </Group>
         <Group>
-          <GroupName>GD32F1x0_Drivers</GroupName>
+          <GroupName>BSP</GroupName>
           <Files>
             <File>
-              <FileName>gd32f1x0_adc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_adc.c</FilePath>
-            </File>
-            <File>
-              <FileName>gd32f1x0_can.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_can.c</FilePath>
-            </File>
-            <File>
-              <FileName>gd32f1x0_cec.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_cec.c</FilePath>
-            </File>
-            <File>
-              <FileName>gd32f1x0_cmp.c</FileName>
+              <FileName>gpio.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_cmp.c</FilePath>
+              <FilePath>..\Application\bsp\gpio.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_crc.c</FileName>
+              <FileName>irqs.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_crc.c</FilePath>
+              <FilePath>..\Application\bsp\irqs.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_dac.c</FileName>
+              <FileName>spi.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_dac.c</FilePath>
+              <FilePath>..\Application\bsp\spi.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_dbg.c</FileName>
+              <FileName>cs1180.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_dbg.c</FilePath>
+              <FilePath>..\Application\bsp\cs1180.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_dma.c</FileName>
+              <FileName>ml5238.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_dma.c</FilePath>
+              <FilePath>..\Application\bsp\ml5238.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_exti.c</FileName>
+              <FileName>AT24CXX.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_exti.c</FilePath>
+              <FilePath>..\Application\bsp\AT24CXX.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_fmc.c</FileName>
+              <FileName>i2c.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_fmc.c</FilePath>
+              <FilePath>..\Application\bsp\i2c.c</FilePath>
             </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Libs</GroupName>
+        </Group>
+        <Group>
+          <GroupName>GD32F30x_Drivers</GroupName>
+          <Files>
             <File>
-              <FileName>gd32f1x0_fwdgt.c</FileName>
+              <FileName>gd32f3x0_adc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_fwdgt.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_adc.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_gpio.c</FileName>
+              <FileName>gd32f3x0_cec.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_gpio.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_cec.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_i2c.c</FileName>
+              <FileName>gd32f3x0_cmp.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_i2c.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_cmp.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_ivref.c</FileName>
+              <FileName>gd32f3x0_crc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_ivref.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_crc.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_misc.c</FileName>
+              <FileName>gd32f3x0_ctc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_misc.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_ctc.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_opa.c</FileName>
+              <FileName>gd32f3x0_dac.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_opa.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_dac.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_pmu.c</FileName>
+              <FileName>gd32f3x0_dbg.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_pmu.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_dbg.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_rcu.c</FileName>
+              <FileName>gd32f3x0_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_rcu.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_dma.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_rtc.c</FileName>
+              <FileName>gd32f3x0_exti.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_rtc.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_exti.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_slcd.c</FileName>
+              <FileName>gd32f3x0_fmc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_slcd.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_fmc.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_spi.c</FileName>
+              <FileName>gd32f3x0_fwdgt.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_spi.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_fwdgt.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_syscfg.c</FileName>
+              <FileName>gd32f3x0_gpio.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_syscfg.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_gpio.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_timer.c</FileName>
+              <FileName>gd32f3x0_i2c.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_timer.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_i2c.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_tsi.c</FileName>
+              <FileName>gd32f3x0_misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_tsi.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_misc.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_usart.c</FileName>
+              <FileName>gd32f3x0_pmu.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_usart.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_pmu.c</FilePath>
             </File>
             <File>
-              <FileName>gd32f1x0_wwdgt.c</FileName>
+              <FileName>gd32f3x0_rcu.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\GD32F1x0_Drivers\src\gd32f1x0_wwdgt.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_rcu.c</FilePath>
             </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>BSP</GroupName>
-          <Files>
             <File>
-              <FileName>gpio.c</FileName>
+              <FileName>gd32f3x0_rtc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Application\bsp\gpio.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_rtc.c</FilePath>
             </File>
             <File>
-              <FileName>irqs.c</FileName>
+              <FileName>gd32f3x0_spi.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Application\bsp\irqs.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_spi.c</FilePath>
             </File>
             <File>
-              <FileName>spi.c</FileName>
+              <FileName>gd32f3x0_syscfg.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Application\bsp\spi.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_syscfg.c</FilePath>
             </File>
             <File>
-              <FileName>cs1180.c</FileName>
+              <FileName>gd32f3x0_timer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Application\bsp\cs1180.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_timer.c</FilePath>
             </File>
             <File>
-              <FileName>ml5238.c</FileName>
+              <FileName>gd32f3x0_tsi.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Application\bsp\ml5238.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_tsi.c</FilePath>
             </File>
             <File>
-              <FileName>AT24CXX.c</FileName>
+              <FileName>gd32f3x0_usart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Application\bsp\AT24CXX.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_usart.c</FilePath>
             </File>
             <File>
-              <FileName>i2c.c</FileName>
+              <FileName>gd32f3x0_wwdgt.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Application\bsp\i2c.c</FilePath>
+              <FilePath>..\Librarys\GD32F3x0_Drivers\Source\gd32f3x0_wwdgt.c</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
-          <GroupName>Libs</GroupName>
-        </Group>
-        <Group>
-          <GroupName>StartUP</GroupName>
+          <GroupName>StartUp</GroupName>
           <Files>
             <File>
-              <FileName>startup_gd32f1x0.s</FileName>
+              <FileName>startup_gd32f3x0.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\Librarys\CMSIS\GD32F1x0\Source\startup_gd32f1x0.s</FilePath>
+              <FilePath>..\Librarys\CMSIS\GD32F3x0\Source\startup_gd32f3x0.s</FilePath>
             </File>
             <File>
-              <FileName>system_gd32f1x0.c</FileName>
+              <FileName>system_gd32f3x0.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Librarys\CMSIS\GD32F1x0\Source\system_gd32f1x0.c</FilePath>
+              <FilePath>..\Librarys\CMSIS\GD32F3x0\Source\system_gd32f3x0.c</FilePath>
             </File>
           </Files>
         </Group>