|
|
@@ -6,14 +6,14 @@
|
|
|
#define SHARK_UART_BAUDRATE 38400
|
|
|
|
|
|
#define SHARK_UART0_com USART0
|
|
|
-#define SHARK_UART0_tx_port GPIOA
|
|
|
-#define SHARK_UART0_tx_pin GPIO_PIN_9
|
|
|
-#define SHARK_UART0_rx_port GPIOA
|
|
|
-#define SHARK_UART0_rx_pin GPIO_PIN_10
|
|
|
+#define SHARK_UART0_tx_port GPIOB
|
|
|
+#define SHARK_UART0_tx_pin GPIO_PIN_6
|
|
|
+#define SHARK_UART0_rx_port GPIOB
|
|
|
+#define SHARK_UART0_rx_pin GPIO_PIN_7
|
|
|
#define SHARK_UART0_irq USART0_IRQn
|
|
|
#define SHARK_UART0_clk RCU_USART0
|
|
|
-#define SHARK_UART0_tx_gpio_clk RCU_GPIOA
|
|
|
-#define SHARK_UART0_rx_gpio_clk RCU_GPIOA
|
|
|
+#define SHARK_UART0_tx_gpio_clk RCU_GPIOB
|
|
|
+#define SHARK_UART0_rx_gpio_clk RCU_GPIOB
|
|
|
#define SHARK_UART0_tx_dma DMA
|
|
|
#define SHARK_UART0_tx_dma_ch DMA_CH1
|
|
|
#define SHARK_UART0_tx_dma_clk RCU_DMA
|
|
|
@@ -48,6 +48,7 @@ static bool new_prococol = false;
|
|
|
static u64 _rx_time;
|
|
|
#define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(uart->rx_dma_ch))
|
|
|
extern void protocol_recv_frame(uart_enum_t uart_no, char *data, int len);
|
|
|
+extern void protocol_notify_old_frame(uart_enum_t uart_no);
|
|
|
// ================================================================================
|
|
|
static uart_enum_t _uart_index(uint32_t com){
|
|
|
return com == SHARK_UART0_com?SHARK_UART0:SHARK_UART1;
|
|
|
@@ -71,9 +72,9 @@ static void shark_uart_rx(shark_uart_t *uart){
|
|
|
update_dma_w_pos(uart);
|
|
|
if (circle_get_one_data(&uart->rx_queue, &data) != 1) {
|
|
|
if (!new_prococol){//通过老协议发送过来的,需要回复一个信息,告知使用新协议,霍尔移除,通信超时需要reset new_protocol
|
|
|
- if (shark_get_mseconds() - _rx_time >= 30) {
|
|
|
+ if (shark_get_mseconds() >= (30 + _rx_time)) {
|
|
|
_rx_time = 0xFFFFFFFFFFFFL;
|
|
|
- protocol_recv_frame(_uart_index(uart->uart_com), NULL, 0);
|
|
|
+ protocol_notify_old_frame(_uart_index(uart->uart_com));
|
|
|
}
|
|
|
}
|
|
|
break;
|
|
|
@@ -170,42 +171,84 @@ static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
|
|
|
shark_uart_write(uart, &value, 1);
|
|
|
}
|
|
|
|
|
|
-void shark_uart_dma_init(dma_channel_enum channelx, u8 direction, u32 periph_addr, void *memory_addr, u16 length)
|
|
|
-{
|
|
|
- u32 ctl;
|
|
|
-
|
|
|
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
|
|
|
|
|
|
- /* configure peripheral base address */
|
|
|
- DMA_CHPADDR(channelx) = periph_addr;
|
|
|
+static void shark_uart_tx_dma_init(shark_uart_t *uart){
|
|
|
+ dma_parameter_struct dma_init_struct;
|
|
|
+ rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
|
|
|
+ dma_deinit(uart->tx_dma_ch);
|
|
|
+ dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
|
|
|
+ dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
|
|
+ dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
|
|
+ dma_init_struct.periph_addr = (u32) &USART_TDATA(uart->uart_com);
|
|
|
+ dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
|
|
+ dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
|
|
+ dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
|
|
+ dma_init(uart->tx_dma_ch, &dma_init_struct);
|
|
|
+ dma_circulation_disable(uart->tx_dma_ch);
|
|
|
+ dma_memory_to_memory_disable(uart->tx_dma_ch);
|
|
|
+ usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
|
|
|
+}
|
|
|
|
|
|
- /* configure memory base address */
|
|
|
- DMA_CHMADDR(channelx) = (u32) memory_addr;
|
|
|
|
|
|
- /* configure the number of remaining data to be transferred */
|
|
|
- DMA_CHCNT(channelx) = length;
|
|
|
+static void shark_uart_rx_dma_init(shark_uart_t *uart){
|
|
|
+ dma_parameter_struct dma_init_struct;
|
|
|
+ rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
|
|
|
+ dma_deinit(uart->rx_dma_ch);
|
|
|
+ dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
|
|
|
+ dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
|
|
+ dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
|
|
+ dma_init_struct.memory_addr = (u32)uart->rx_queue.buffer;
|
|
|
+ dma_init_struct.number = uart->rx_queue.buffer_len;
|
|
|
+ dma_init_struct.periph_addr = (u32) &USART_RDATA(uart->uart_com);
|
|
|
+ dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
|
|
+ dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
|
|
+ dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
|
|
+ dma_init(uart->rx_dma_ch, &dma_init_struct);
|
|
|
+ dma_circulation_enable(uart->rx_dma_ch);
|
|
|
+ dma_memory_to_memory_disable(uart->rx_dma_ch);
|
|
|
+ dma_channel_enable(uart->rx_dma_ch);
|
|
|
+ usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
|
|
|
+}
|
|
|
|
|
|
- /* configure peripheral transfer width,memory transfer width and priority */
|
|
|
- ctl = DMA_CHCTL(channelx);
|
|
|
- ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
|
|
|
- ctl |= (DMA_PERIPHERAL_WIDTH_8BIT | DMA_MEMORY_WIDTH_8BIT | DMA_PRIORITY_ULTRA_HIGH);
|
|
|
- DMA_CHCTL(channelx) = ctl;
|
|
|
+static void shark_uart_pin_init(shark_uart_t *uart){
|
|
|
+ if (_uart_index(uart->uart_com) == SHARK_UART0) {
|
|
|
+ rcu_periph_clock_enable(SHARK_UART0_clk);
|
|
|
+ rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
|
|
|
+ rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
|
|
|
+ gpio_af_set(SHARK_UART0_tx_port, GPIO_AF_0,SHARK_UART0_tx_pin);
|
|
|
+ gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_tx_pin);
|
|
|
+ gpio_output_options_set(SHARK_UART0_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART0_tx_pin);
|
|
|
+ gpio_af_set(SHARK_UART0_rx_port, GPIO_AF_0,SHARK_UART0_rx_pin);
|
|
|
+ gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART0_rx_pin);
|
|
|
+ gpio_output_options_set(SHARK_UART0_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
|
|
|
+ }else {
|
|
|
+ rcu_periph_clock_enable(SHARK_UART1_clk);
|
|
|
+ rcu_periph_clock_enable(SHARK_UART1_rx_gpio_clk);
|
|
|
+ rcu_periph_clock_enable(SHARK_UART1_tx_gpio_clk);
|
|
|
+ gpio_af_set(SHARK_UART1_tx_port, GPIO_AF_1,SHARK_UART1_tx_pin);
|
|
|
+ gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_tx_pin);
|
|
|
+ gpio_output_options_set(SHARK_UART1_tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SHARK_UART1_tx_pin);
|
|
|
+ gpio_af_set(SHARK_UART1_rx_port, GPIO_AF_1,SHARK_UART1_rx_pin);
|
|
|
+ gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, SHARK_UART1_rx_pin);
|
|
|
+ gpio_output_options_set(SHARK_UART1_rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,SHARK_UART1_rx_pin);
|
|
|
+ }
|
|
|
|
|
|
- /* configure peripheral increasing mode */
|
|
|
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
|
|
|
+}
|
|
|
|
|
|
- /* configure memory increasing mode */
|
|
|
- DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
|
|
|
+static void shark_uart_device_init(shark_uart_t *uart){
|
|
|
+ usart_deinit(uart->uart_com);
|
|
|
+ usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
|
|
|
|
|
|
- /* configure the direction of data transfer */
|
|
|
- if (DMA_PERIPHERAL_TO_MEMORY == direction) {
|
|
|
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
|
|
|
- } else {
|
|
|
- DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
|
|
|
- }
|
|
|
+ usart_word_length_set(uart->uart_com, USART_WL_8BIT);
|
|
|
+ usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
|
|
|
+ usart_parity_config(uart->uart_com, USART_PM_NONE);
|
|
|
+ usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
|
|
|
+ usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
|
|
|
+ usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
|
|
|
+ usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
|
|
|
+
|
|
|
}
|
|
|
|
|
|
-
|
|
|
static u32 shark_uart_handler(void)
|
|
|
{
|
|
|
shark_uart_t *uart = _shark_uart + SHARK_UART0;
|
|
|
@@ -228,6 +271,7 @@ static u8 *tx_cache_addr(uart_enum_t uart_no){
|
|
|
void shark_uart_deinit(uart_enum_t uart_no){
|
|
|
shark_uart_t *uart = _shark_uart + uart_no;
|
|
|
if (uart->uart_com != 0) {
|
|
|
+ usart_disable(uart->uart_com);
|
|
|
usart_deinit(uart->uart_com);
|
|
|
rcu_periph_clock_enable(uart_no == SHARK_UART0?SHARK_UART0_clk:SHARK_UART1_clk);
|
|
|
dma_channel_disable(uart->rx_dma_ch);
|
|
|
@@ -258,47 +302,12 @@ void shark_uart_init(uart_enum_t uart_no)
|
|
|
uart->rx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_rx_dma_ch:SHARK_UART1_rx_dma_ch;
|
|
|
uart->tx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_tx_dma_ch:SHARK_UART1_tx_dma_ch;
|
|
|
|
|
|
- if (uart_no == SHARK_UART0) {
|
|
|
- rcu_periph_clock_enable(SHARK_UART0_clk);
|
|
|
- rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
|
|
|
- rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
|
|
|
-
|
|
|
- gpio_mode_set(SHARK_UART0_tx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, SHARK_UART0_tx_pin);
|
|
|
- gpio_mode_set(SHARK_UART0_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, SHARK_UART0_rx_pin);
|
|
|
- }else {
|
|
|
- rcu_periph_clock_enable(SHARK_UART1_clk);
|
|
|
- rcu_periph_clock_enable(SHARK_UART1_rx_gpio_clk);
|
|
|
- rcu_periph_clock_enable(SHARK_UART1_tx_gpio_clk);
|
|
|
-
|
|
|
- gpio_mode_set(SHARK_UART1_tx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, SHARK_UART1_tx_pin);
|
|
|
- gpio_mode_set(SHARK_UART1_rx_port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, SHARK_UART1_rx_pin);
|
|
|
-
|
|
|
- }
|
|
|
-
|
|
|
- usart_deinit(uart->uart_com);
|
|
|
- usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
|
|
|
-
|
|
|
- usart_word_length_set(uart->uart_com, USART_WL_8BIT);
|
|
|
- usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
|
|
|
- usart_parity_config(uart->uart_com, USART_PM_NONE);
|
|
|
- usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
|
|
|
- usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
|
|
|
- usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
|
|
|
- usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
|
|
|
-
|
|
|
-
|
|
|
- rcu_periph_clock_enable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART1_tx_dma_clk);
|
|
|
- shark_uart_dma_init(uart->tx_dma_ch, DMA_MEMORY_TO_PERIPHERAL, uart->uart_com + 0x04, tx_cache_addr(uart_no), 0);
|
|
|
- dma_circulation_disable(uart->tx_dma_ch);
|
|
|
- usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
|
|
|
-
|
|
|
- rcu_periph_clock_enable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART1_rx_dma_clk);
|
|
|
- shark_uart_dma_init(uart->rx_dma_ch, DMA_PERIPHERAL_TO_MEMORY, uart->uart_com + 0x04, shark_uart_rx_cache, SHARK_UART_TX_MEM_SIZE);
|
|
|
- dma_circulation_enable(uart->rx_dma_ch);
|
|
|
- dma_channel_enable(uart->rx_dma_ch);
|
|
|
- usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
|
|
|
-
|
|
|
+ shark_uart_pin_init(uart);
|
|
|
+ shark_uart_device_init(uart);
|
|
|
+ shark_uart_rx_dma_init(uart);
|
|
|
+ shark_uart_tx_dma_init(uart);
|
|
|
usart_enable(uart->uart_com);
|
|
|
+
|
|
|
if (_uart_task.handler == NULL) {
|
|
|
_uart_task.handler = shark_uart_handler;
|
|
|
shark_task_add(&_uart_task);
|
|
|
@@ -367,3 +376,19 @@ void shark_uart_write_frame(uart_enum_t uart_no, uint8_t *bytes, int len){
|
|
|
shark_uart_tx_end(uart);
|
|
|
}
|
|
|
|
|
|
+void shark_uart_frame_start(uart_enum_t uart_no, uint8_t *bytes, int len){
|
|
|
+ shark_uart_t *uart = _shark_uart + uart_no;
|
|
|
+ shark_uart_tx_start(uart);
|
|
|
+ shark_uart_tx_continue(uart, bytes, len);
|
|
|
+}
|
|
|
+
|
|
|
+void shark_uart_frame_continue(uart_enum_t uart_no, uint8_t *bytes, int len){
|
|
|
+ shark_uart_t *uart = _shark_uart + uart_no;
|
|
|
+ shark_uart_tx_continue(uart, bytes, len);
|
|
|
+}
|
|
|
+
|
|
|
+void shark_uart_frame_end(uart_enum_t uart_no){
|
|
|
+ shark_uart_tx_end(_shark_uart + uart_no);
|
|
|
+}
|
|
|
+
|
|
|
+
|