GD32F10x_Firmware_Library: Data Structures

GD32F10x_Firmware_Library V2.0.0
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Data Structures
Here are the data structures with brief descriptions:
[detail level 12]
C backup_state_struct
C can_filter_parameter_struct
C can_parameter_struct
C can_receive_message_struct
C can_trasnmit_message_struct
C dcd_dev_struct
C dma_parameter_struct
C enet_descriptors_struct
C enet_initpara_struct
C enet_ptp_systime_struct
C exmc_nand_parameter_struct
C exmc_nand_pccard_timing_parameter_struct
C exmc_norsram_parameter_struct
C exmc_norsram_timing_parameter_struct
C exmc_pccard_parameter_struct
C hcd_dev_struct
C spi_parameter_struct
C state_table_struct
C timer_break_parameter_struct
C timer_ic_parameter_struct
C timer_oc_parameter_struct
C timer_parameter_struct
C usb_core_cfgs_struct
C usb_core_handle_struct
C usb_descriptor_configuration_struct
C usb_descriptor_device_struct
C usb_descriptor_endpoint_struct
C usb_descriptor_header_struct
C usb_descriptor_interface_struct
C usb_descriptor_language_id_struct
C usb_device_req_struct
C usb_ep_struct
C usb_hostchannel_struct
▼C usb_setup_union
C _setup_packet_struct
C usbd_core_handle_struct
C usbd_ep_buf_struct
C usbd_int_cb_struct
C usbh_ctrl_struct
C usbh_device_struct
C usbh_hcd_int_cb_struct
C usbh_host_struct
C usbh_state_handle_struct
C usbh_state_regist_table_struct
C usbh_state_stack_struct
C usbh_user_callback_struct
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: backup_state_struct Struct Reference

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backup_state_struct Struct Reference

#include <usbh_core.h>

Data Fields

host_state_enum host_backup_state
enum_state_enum enum_backup_state
ctrl_state_enum ctrl_backup_state
uint8_t | class_req_backup_state
uint8_t | class_backup_state

Detailed Description

Definition at line 179 of file usbh_core.h.

Field Documentation

uint8_t class_backup_state

Definition at line 185 of file usbh_core.h.

uint8_t class_req_backup_state

Definition at line 184 of file usbh_core.h.

ctrl_state_enum ctrl_backup_state

Definition at line 183 of file usbh_core.h.

enum_state_enum enum_backup_state

Definition at line 182 of file usbh_core.h.

host_state_enum host_backup_state

Definition at line 181 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h


GD32F10x_Firmware_Library: can_filter_parameter_struct Struct Reference

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Data Fields
can_filter_parameter_struct Struct Reference

#include <gd32f10x_can.h>

Data Fields

uint16_t | filter_list_high
uint16_t | filter_list_low
uint16_t | filter_mask_high
uint16_t | filter_mask_low
uint16_t | filter_fifo_number
uint16_t | filter_number
uint16_t | filter_mode
uint16_t | filter_bits
ControlStatus | filter_enable

Detailed Description

Definition at line 386 of file gd32f10x_can.h.

Field Documentation

uint16_t filter_bits

filter scale

Definition at line 395 of file gd32f10x_can.h.

ControlStatus filter_enable

filter work or not

Definition at line 396 of file gd32f10x_can.h.

uint16_t filter_fifo_number

receive FIFO associated with the filter

Definition at line 392 of file gd32f10x_can.h.

uint16_t filter_list_high

filter list number high bits

Definition at line 388 of file gd32f10x_can.h.

uint16_t filter_list_low

filter list number low bits

Definition at line 389 of file gd32f10x_can.h.

uint16_t filter_mask_high

filter mask number high bits

Definition at line 390 of file gd32f10x_can.h.

uint16_t filter_mask_low

filter mask number low bits

Definition at line 391 of file gd32f10x_can.h.

uint16_t filter_mode

filter mode, list or mask

Definition at line 394 of file gd32f10x_can.h.

uint16_t filter_number

filter number

Definition at line 393 of file gd32f10x_can.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_can.h


GD32F10x_Firmware_Library: can_parameter_struct Struct Reference

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Data Fields
can_parameter_struct Struct Reference

#include <gd32f10x_can.h>

Data Fields

uint8_t | working_mode
uint8_t | resync_jump_width
uint8_t | time_segment_1
uint8_t | time_segment_2
ControlStatus | time_triggered
ControlStatus | auto_bus_off_recovery
ControlStatus | auto_wake_up
ControlStatus | auto_retrans
ControlStatus | rec_fifo_overwrite
ControlStatus | trans_fifo_order
uint16_t | prescaler

Detailed Description

Definition at line 347 of file gd32f10x_can.h.

Field Documentation

ControlStatus auto_bus_off_recovery

automatic bus-off recovery

Definition at line 354 of file gd32f10x_can.h.

ControlStatus auto_retrans

automatic retransmission mode

Definition at line 356 of file gd32f10x_can.h.

ControlStatus auto_wake_up

automatic wake-up mode

Definition at line 355 of file gd32f10x_can.h.

uint16_t prescaler

baudrate prescaler

Definition at line 359 of file gd32f10x_can.h.

ControlStatus rec_fifo_overwrite

receive FIFO overwrite mode

Definition at line 357 of file gd32f10x_can.h.

uint8_t resync_jump_width

CAN resynchronization jump width

Definition at line 350 of file gd32f10x_can.h.

uint8_t time_segment_1

time segment 1

Definition at line 351 of file gd32f10x_can.h.

uint8_t time_segment_2

time segment 2

Definition at line 352 of file gd32f10x_can.h.

ControlStatus time_triggered

time triggered communication mode

Definition at line 353 of file gd32f10x_can.h.

ControlStatus trans_fifo_order

transmit FIFO order

Definition at line 358 of file gd32f10x_can.h.

uint8_t working_mode

CAN working mode

Definition at line 349 of file gd32f10x_can.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_can.h


GD32F10x_Firmware_Library: can_receive_message_struct Struct Reference

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Data Fields
can_receive_message_struct Struct Reference

#include <gd32f10x_can.h>

Data Fields

uint32_t | rx_sfid
uint32_t | rx_efid
uint8_t | rx_ff
uint8_t | rx_ft
uint8_t | rx_dlen
uint8_t | rx_data [8]
uint8_t | rx_fi

Detailed Description

Definition at line 374 of file gd32f10x_can.h.

Field Documentation

uint8_t rx_data[8]

receive data

Definition at line 381 of file gd32f10x_can.h.

uint8_t rx_dlen

data length

Definition at line 380 of file gd32f10x_can.h.

uint32_t rx_efid

extended format frame identifier

Definition at line 377 of file gd32f10x_can.h.

uint8_t rx_ff

format of frame, standard or extended format

Definition at line 378 of file gd32f10x_can.h.

uint8_t rx_fi

filtering index

Definition at line 382 of file gd32f10x_can.h.

uint8_t rx_ft

type of frame, data or remote

Definition at line 379 of file gd32f10x_can.h.

uint32_t rx_sfid

standard format frame identifier

Definition at line 376 of file gd32f10x_can.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_can.h


GD32F10x_Firmware_Library: can_trasnmit_message_struct Struct Reference

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Data Fields
can_trasnmit_message_struct Struct Reference

#include <gd32f10x_can.h>

Data Fields

uint32_t | tx_sfid
uint32_t | tx_efid
uint8_t | tx_ff
uint8_t | tx_ft
uint8_t | tx_dlen
uint8_t | tx_data [8]

Detailed Description

Definition at line 363 of file gd32f10x_can.h.

Field Documentation

uint8_t tx_data[8]

transmit data

Definition at line 370 of file gd32f10x_can.h.

uint8_t tx_dlen

data length

Definition at line 369 of file gd32f10x_can.h.

uint32_t tx_efid

extended format frame identifier

Definition at line 366 of file gd32f10x_can.h.

uint8_t tx_ff

format of frame, standard or extended format

Definition at line 367 of file gd32f10x_can.h.

uint8_t tx_ft

type of frame, data or remote

Definition at line 368 of file gd32f10x_can.h.

uint32_t tx_sfid

standard format frame identifier

Definition at line 365 of file gd32f10x_can.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_can.h


GD32F10x_Firmware_Library: dcd_dev_struct Struct Reference

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Data Fields
dcd_dev_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | config_num
uint8_t | status
uint8_t | ctl_status
uint8_t | prev_status
uint8_t | connection_status
uint32_t | remote_wakeup
uint32_t | remain_len
uint32_t | sum_len
uint32_t | ctl_len
uint8_t | setup_packet [8 *3]
usb_ep_struct in_ep [USB_MAX_DEV_EPCOUNT]
usb_ep_struct out_ep [USB_MAX_DEV_EPCOUNT]
uint8_t * | dev_desc
uint8_t * | config_desc
uint8_t ** | strings
uint8_t(* | class_init )(void *pudev, uint8_t config_index)
uint8_t(* | class_deinit )(void *pudev, uint8_t config_index)
uint8_t(* | class_req_handler )(void *pudev, usb_device_req_struct *req)
uint8_t(* | class_data_handler )(void *pudev, usb_dir_enum rx_tx, uint8_t ep_num)

Detailed Description

Definition at line 125 of file usb_core.h.

Field Documentation

uint8_t(* class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num)

Definition at line 151 of file usb_core.h.

uint8_t(* class_deinit) (void *pudev, uint8_t config_index)

Definition at line 149 of file usb_core.h.

uint8_t(* class_init) (void *pudev, uint8_t config_index)

Definition at line 148 of file usb_core.h.

uint8_t(* class_req_handler) (void *pudev, usb_device_req_struct *req)

Definition at line 150 of file usb_core.h.

uint8_t* config_desc

Definition at line 144 of file usb_core.h.

uint8_t config_num

Definition at line 127 of file usb_core.h.

uint8_t connection_status

Definition at line 131 of file usb_core.h.

uint32_t ctl_len

Definition at line 137 of file usb_core.h.

uint8_t ctl_status

Definition at line 129 of file usb_core.h.

uint8_t* dev_desc

Definition at line 143 of file usb_core.h.

usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]

Definition at line 140 of file usb_core.h.

usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]

Definition at line 141 of file usb_core.h.

uint8_t prev_status

Definition at line 130 of file usb_core.h.

uint32_t remain_len

Definition at line 135 of file usb_core.h.

uint32_t remote_wakeup

Definition at line 132 of file usb_core.h.

uint8_t setup_packet[8 *3]

Definition at line 138 of file usb_core.h.

uint8_t status

Definition at line 128 of file usb_core.h.

uint8_t* * strings

Definition at line 145 of file usb_core.h.

uint32_t sum_len

Definition at line 136 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_core.h


GD32F10x_Firmware_Library: dma_parameter_struct Struct Reference

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Data Fields
dma_parameter_struct Struct Reference

#include <gd32f10x_dma.h>

Data Fields

uint32_t | periph_addr
uint32_t | periph_width
uint32_t | memory_addr
uint32_t | memory_width
uint32_t | number
uint32_t | priority
uint8_t | periph_inc
uint8_t | memory_inc
uint8_t | direction

Detailed Description

Definition at line 111 of file gd32f10x_dma.h.

Field Documentation

uint8_t direction

channel data transfer direction

Definition at line 121 of file gd32f10x_dma.h.

uint32_t memory_addr

memory base address

Definition at line 115 of file gd32f10x_dma.h.

uint8_t memory_inc

memory increasing mode

Definition at line 120 of file gd32f10x_dma.h.

uint32_t memory_width

transfer data size of memory

Definition at line 116 of file gd32f10x_dma.h.

uint32_t number

channel transfer number

Definition at line 117 of file gd32f10x_dma.h.

uint32_t periph_addr

peripheral base address

Definition at line 113 of file gd32f10x_dma.h.

uint8_t periph_inc

peripheral increasing mode

Definition at line 119 of file gd32f10x_dma.h.

uint32_t periph_width

transfer data size of peripheral

Definition at line 114 of file gd32f10x_dma.h.

uint32_t priority

channel priority level

Definition at line 118 of file gd32f10x_dma.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h


GD32F10x_Firmware_Library: enet_descriptors_struct Struct Reference

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Data Fields
enet_descriptors_struct Struct Reference

#include <gd32f10x_enet.h>

Data Fields

uint32_t | status
uint32_t | control_buffer_size
uint32_t | buffer1_addr
uint32_t | buffer2_next_desc_addr

Detailed Description

Definition at line 860 of file gd32f10x_enet.h.

Field Documentation

uint32_t buffer1_addr

buffer1 address pointer/timestamp low

Definition at line 864 of file gd32f10x_enet.h.

uint32_t buffer2_next_desc_addr

buffer2 or next descriptor address pointer/timestamp high

Definition at line 865 of file gd32f10x_enet.h.

uint32_t control_buffer_size

control and buffer1, buffer2 lengths

Definition at line 863 of file gd32f10x_enet.h.

uint32_t status

status

Definition at line 862 of file gd32f10x_enet.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h


GD32F10x_Firmware_Library: enet_initpara_struct Struct Reference

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Data Fields
enet_initpara_struct Struct Reference

#include <gd32f10x_enet.h>

Data Fields

uint32_t | option_enable
uint32_t | forward_frame
uint32_t | dmabus_mode
uint32_t | dma_maxburst
uint32_t | dma_arbitration
uint32_t | store_forward_mode
uint32_t | dma_function
uint32_t | vlan_config
uint32_t | flow_control
uint32_t | hashtable_high
uint32_t | hashtable_low
uint32_t | framesfilter_mode
uint32_t | halfduplex_param
uint32_t | timer_config
uint32_t | interframegap

Detailed Description

Definition at line 840 of file gd32f10x_enet.h.

Field Documentation

uint32_t dma_arbitration

DMA Tx and Rx arbitration related parameters

Definition at line 846 of file gd32f10x_enet.h.

uint32_t dma_function

DMA control related parameters

Definition at line 848 of file gd32f10x_enet.h.

uint32_t dma_maxburst

DMA max burst related parameters

Definition at line 845 of file gd32f10x_enet.h.

uint32_t dmabus_mode

DMA bus mode related parameters

Definition at line 844 of file gd32f10x_enet.h.

uint32_t flow_control

flow control related parameters

Definition at line 850 of file gd32f10x_enet.h.

uint32_t forward_frame

frame forward related parameters

Definition at line 843 of file gd32f10x_enet.h.

uint32_t framesfilter_mode

frame filter control related parameters

Definition at line 853 of file gd32f10x_enet.h.

uint32_t halfduplex_param

halfduplex related parameters

Definition at line 854 of file gd32f10x_enet.h.

uint32_t hashtable_high

hash list high 32-bit related parameters

Definition at line 851 of file gd32f10x_enet.h.

uint32_t hashtable_low

hash list low 32-bit related parameters

Definition at line 852 of file gd32f10x_enet.h.

uint32_t interframegap

inter frame gap related parameters

Definition at line 856 of file gd32f10x_enet.h.

uint32_t option_enable

select which function to configure

Definition at line 842 of file gd32f10x_enet.h.

uint32_t store_forward_mode

store forward mode related parameters

Definition at line 847 of file gd32f10x_enet.h.

uint32_t timer_config

frame timer related parameters

Definition at line 855 of file gd32f10x_enet.h.

uint32_t vlan_config

VLAN tag related parameters

Definition at line 849 of file gd32f10x_enet.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h


GD32F10x_Firmware_Library: enet_ptp_systime_struct Struct Reference

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Data Fields
enet_ptp_systime_struct Struct Reference

#include <gd32f10x_enet.h>

Data Fields

uint32_t | second
uint32_t | nanosecond
uint32_t | sign

Detailed Description

Definition at line 869 of file gd32f10x_enet.h.

Field Documentation

uint32_t nanosecond

nanosecond of system time

Definition at line 872 of file gd32f10x_enet.h.

uint32_t second

second of system time

Definition at line 871 of file gd32f10x_enet.h.

uint32_t sign

sign of system time

Definition at line 873 of file gd32f10x_enet.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h


GD32F10x_Firmware_Library: exmc_nand_parameter_struct Struct Reference

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Data Fields
exmc_nand_parameter_struct Struct Reference

#include <gd32f10x_exmc.h>

Data Fields

uint32_t | nand_bank
uint32_t | ecc_size
uint32_t | atr_latency
uint32_t | ctr_latency
uint32_t | ecc_logic
uint32_t | databus_width
uint32_t | wait_feature
exmc_nand_pccard_timing_parameter_struct * common_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing

Detailed Description

Definition at line 178 of file gd32f10x_exmc.h.

Field Documentation

uint32_t atr_latency

configure the latency of ALE low to RB low

Definition at line 182 of file gd32f10x_exmc.h.

exmc_nand_pccard_timing_parameter_struct* attribute_space_timing

the timing parameters for NAND flash attribute space

Definition at line 188 of file gd32f10x_exmc.h.

exmc_nand_pccard_timing_parameter_struct* common_space_timing

the timing parameters for NAND flash common space

Definition at line 187 of file gd32f10x_exmc.h.

uint32_t ctr_latency

configure the latency of CLE low to RB low

Definition at line 183 of file gd32f10x_exmc.h.

uint32_t databus_width

the NAND flash databus width

Definition at line 185 of file gd32f10x_exmc.h.

uint32_t ecc_logic

enable or disable the ECC calculation logic

Definition at line 184 of file gd32f10x_exmc.h.

uint32_t ecc_size

the page size for the ECC calculation

Definition at line 181 of file gd32f10x_exmc.h.

uint32_t nand_bank

select the bank of NAND

Definition at line 180 of file gd32f10x_exmc.h.

uint32_t wait_feature

enables or disables the wait feature

Definition at line 186 of file gd32f10x_exmc.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h


GD32F10x_Firmware_Library: exmc_nand_pccard_timing_parameter_struct Struct Reference

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Data Fields
exmc_nand_pccard_timing_parameter_struct Struct Reference

#include <gd32f10x_exmc.h>

Data Fields

uint32_t | databus_hiztime
uint32_t | holdtime
uint32_t | waittime
uint32_t | setuptime

Detailed Description

Definition at line 169 of file gd32f10x_exmc.h.

Field Documentation

uint32_t databus_hiztime

configure the dadtabus HiZ time for write operation

Definition at line 171 of file gd32f10x_exmc.h.

uint32_t holdtime

configure the address hold time(or the data hold time for write operation)

Definition at line 172 of file gd32f10x_exmc.h.

uint32_t setuptime

configure the address setup time

Definition at line 174 of file gd32f10x_exmc.h.

uint32_t waittime

configure the minimum wait time

Definition at line 173 of file gd32f10x_exmc.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h


GD32F10x_Firmware_Library: exmc_norsram_parameter_struct Struct Reference

  • Data Structures
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  • Data Fields
Data Fields
exmc_norsram_parameter_struct Struct Reference

#include <gd32f10x_exmc.h>

Data Fields

uint32_t | norsram_region
uint32_t | write_mode
uint32_t | extended_mode
uint32_t | asyn_wait
uint32_t | nwait_signal
uint32_t | memory_write
uint32_t | nwait_config
uint32_t | wrap_burst_mode
uint32_t | nwait_polarity
uint32_t | burst_mode
uint32_t | databus_width
uint32_t | memory_type
uint32_t | address_data_mux
exmc_norsram_timing_parameter_struct * read_write_timing
exmc_norsram_timing_parameter_struct * write_timing

Detailed Description

Definition at line 148 of file gd32f10x_exmc.h.

Field Documentation

uint32_t address_data_mux

specifies whether the data bus and address bus are multiplexed

Definition at line 162 of file gd32f10x_exmc.h.

uint32_t asyn_wait

enable or disable the asynchronous wait function

Definition at line 153 of file gd32f10x_exmc.h.

uint32_t burst_mode

enable or disable the burst mode

Definition at line 159 of file gd32f10x_exmc.h.

uint32_t databus_width

specifies the databus width of external memory

Definition at line 160 of file gd32f10x_exmc.h.

uint32_t extended_mode

enable or disable the extended mode

Definition at line 152 of file gd32f10x_exmc.h.

uint32_t memory_type

specifies the type of external memory

Definition at line 161 of file gd32f10x_exmc.h.

uint32_t memory_write

enable or disable the write operation

Definition at line 155 of file gd32f10x_exmc.h.

uint32_t norsram_region

select the region of EXMC NOR/SRAM bank

Definition at line 150 of file gd32f10x_exmc.h.

uint32_t nwait_config

NWAIT signal configuration

Definition at line 156 of file gd32f10x_exmc.h.

uint32_t nwait_polarity

specifies the polarity of NWAIT signal from memory

Definition at line 158 of file gd32f10x_exmc.h.

uint32_t nwait_signal

enable or disable the NWAIT signal while in synchronous bust mode

Definition at line 154 of file gd32f10x_exmc.h.

exmc_norsram_timing_parameter_struct* read_write_timing

timing parameters for read and write if the extended mode is not used or the timing parameters for read if the extended mode is used

Definition at line 163 of file gd32f10x_exmc.h.

uint32_t wrap_burst_mode

enable or disable the wrap burst mode

Definition at line 157 of file gd32f10x_exmc.h.

uint32_t write_mode

the write mode, synchronous mode or asynchronous mode

Definition at line 151 of file gd32f10x_exmc.h.

exmc_norsram_timing_parameter_struct* write_timing

timing parameters for write when the extended mode is used

Definition at line 165 of file gd32f10x_exmc.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h


GD32F10x_Firmware_Library: exmc_norsram_timing_parameter_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
exmc_norsram_timing_parameter_struct Struct Reference

#include <gd32f10x_exmc.h>

Data Fields

uint32_t | asyn_access_mode
uint32_t | syn_data_latency
uint32_t | syn_clk_division
uint32_t | bus_latency
uint32_t | asyn_data_setuptime
uint32_t | asyn_address_holdtime
uint32_t | asyn_address_setuptime

Detailed Description

Definition at line 136 of file gd32f10x_exmc.h.

Field Documentation

uint32_t asyn_access_mode

asynchronous access mode

Definition at line 138 of file gd32f10x_exmc.h.

uint32_t asyn_address_holdtime

configure the address hold time,asynchronous access mode valid

Definition at line 143 of file gd32f10x_exmc.h.

uint32_t asyn_address_setuptime

configure the data setup time,asynchronous access mode valid

Definition at line 144 of file gd32f10x_exmc.h.

uint32_t asyn_data_setuptime

configure the data setup time,asynchronous access mode valid

Definition at line 142 of file gd32f10x_exmc.h.

uint32_t bus_latency

configure the bus latency

Definition at line 141 of file gd32f10x_exmc.h.

uint32_t syn_clk_division

configure the clock divide ratio

Definition at line 140 of file gd32f10x_exmc.h.

uint32_t syn_data_latency

configure the data latency

Definition at line 139 of file gd32f10x_exmc.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h


GD32F10x_Firmware_Library: exmc_pccard_parameter_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
exmc_pccard_parameter_struct Struct Reference

#include <gd32f10x_exmc.h>

Data Fields

uint32_t | atr_latency
uint32_t | ctr_latency
uint32_t | wait_feature
exmc_nand_pccard_timing_parameter_struct * common_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * io_space_timing

Detailed Description

Definition at line 192 of file gd32f10x_exmc.h.

Field Documentation

uint32_t atr_latency

configure the latency of ALE low to RB low

Definition at line 194 of file gd32f10x_exmc.h.

exmc_nand_pccard_timing_parameter_struct* attribute_space_timing

the timing parameters for NAND flash attribute space

Definition at line 198 of file gd32f10x_exmc.h.

exmc_nand_pccard_timing_parameter_struct* common_space_timing

the timing parameters for NAND flash common space

Definition at line 197 of file gd32f10x_exmc.h.

uint32_t ctr_latency

configure the latency of CLE low to RB low

Definition at line 195 of file gd32f10x_exmc.h.

exmc_nand_pccard_timing_parameter_struct* io_space_timing

the timing parameters for NAND flash IO space

Definition at line 199 of file gd32f10x_exmc.h.

uint32_t wait_feature

enables or disables the Wait feature

Definition at line 196 of file gd32f10x_exmc.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h


GD32F10x_Firmware_Library: hcd_dev_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
hcd_dev_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | rx_buffer [RX_MAX_DATA_LENGTH]
uint8_t | connect_status
usb_hostchannel_struct host_channel [USB_MAX_FIFOS]
void(* | vbus_drive )(void *pudev, uint8_t state)

Detailed Description

Definition at line 180 of file usb_core.h.

Field Documentation

uint8_t connect_status

Definition at line 183 of file usb_core.h.

usb_hostchannel_struct host_channel[USB_MAX_FIFOS]

Definition at line 184 of file usb_core.h.

uint8_t rx_buffer[RX_MAX_DATA_LENGTH]

Definition at line 182 of file usb_core.h.

void(* vbus_drive) (void *pudev, uint8_t state)

Definition at line 185 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_core.h


GD32F10x_Firmware_Library: spi_parameter_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
spi_parameter_struct Struct Reference

#include <gd32f10x_spi.h>

Data Fields

uint32_t | device_mode
uint32_t | trans_mode
uint32_t | frame_size
uint32_t | nss
uint32_t | endian
uint32_t | clock_polarity_phase
uint32_t | prescale

Detailed Description

Definition at line 98 of file gd32f10x_spi.h.

Field Documentation

uint32_t clock_polarity_phase

SPI clock phase and polarity

Definition at line 105 of file gd32f10x_spi.h.

uint32_t device_mode

SPI master or slave

Definition at line 100 of file gd32f10x_spi.h.

uint32_t endian

SPI big endian or little endian

Definition at line 104 of file gd32f10x_spi.h.

uint32_t frame_size

SPI frame size

Definition at line 102 of file gd32f10x_spi.h.

uint32_t nss

SPI NSS control by handware or software

Definition at line 103 of file gd32f10x_spi.h.

uint32_t prescale

SPI prescale factor

Definition at line 106 of file gd32f10x_spi.h.

uint32_t trans_mode

SPI transtype

Definition at line 101 of file gd32f10x_spi.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h


GD32F10x_Firmware_Library: state_table_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
state_table_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | cur_state
uint8_t | cur_event
uint8_t | next_state
ACT_FUN event_action_fun

Detailed Description

Definition at line 203 of file usbh_core.h.

Field Documentation

uint8_t cur_event

Definition at line 206 of file usbh_core.h.

uint8_t cur_state

Definition at line 205 of file usbh_core.h.

ACT_FUN event_action_fun

Definition at line 208 of file usbh_core.h.

uint8_t next_state

Definition at line 207 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h


GD32F10x_Firmware_Library: timer_break_parameter_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
timer_break_parameter_struct Struct Reference

#include <gd32f10x_timer.h>

Data Fields

uint16_t | runoffstate
uint32_t | ideloffstate
uint16_t | deadtime
uint16_t | breakpolarity
uint16_t | outputautostate
uint16_t | protectmode
uint16_t | breakstate

Detailed Description

Definition at line 237 of file gd32f10x_timer.h.

Field Documentation

uint16_t breakpolarity

break polarity

Definition at line 242 of file gd32f10x_timer.h.

uint16_t breakstate

break enable

Definition at line 245 of file gd32f10x_timer.h.

uint16_t deadtime

dead time

Definition at line 241 of file gd32f10x_timer.h.

uint32_t ideloffstate

idle mode off-state

Definition at line 240 of file gd32f10x_timer.h.

uint16_t outputautostate

output automatic enable

Definition at line 243 of file gd32f10x_timer.h.

uint16_t protectmode

complementary register protect control

Definition at line 244 of file gd32f10x_timer.h.

uint16_t runoffstate

run mode off-state

Definition at line 239 of file gd32f10x_timer.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h


GD32F10x_Firmware_Library: timer_ic_parameter_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
timer_ic_parameter_struct Struct Reference

#include <gd32f10x_timer.h>

Data Fields

uint16_t | icpolarity
uint16_t | icselection
uint16_t | icprescaler
uint16_t | icfilter

Detailed Description

Definition at line 260 of file gd32f10x_timer.h.

Field Documentation

uint16_t icfilter

channel input capture filter control

Definition at line 265 of file gd32f10x_timer.h.

uint16_t icpolarity

channel input polarity

Definition at line 262 of file gd32f10x_timer.h.

uint16_t icprescaler

channel input capture prescaler

Definition at line 264 of file gd32f10x_timer.h.

uint16_t icselection

channel input mode selection

Definition at line 263 of file gd32f10x_timer.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h


GD32F10x_Firmware_Library: timer_oc_parameter_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
timer_oc_parameter_struct Struct Reference

#include <gd32f10x_timer.h>

Data Fields

uint32_t | outputstate
uint16_t | outputnstate
uint16_t | ocpolarity
uint16_t | ocnpolarity
uint16_t | ocidlestate
uint16_t | ocnidlestate

Detailed Description

Definition at line 249 of file gd32f10x_timer.h.

Field Documentation

uint16_t ocidlestate

idle state of channel output

Definition at line 255 of file gd32f10x_timer.h.

uint16_t ocnidlestate

idle state of channel complementary output

Definition at line 256 of file gd32f10x_timer.h.

uint16_t ocnpolarity

channel complementary output polarity

Definition at line 254 of file gd32f10x_timer.h.

uint16_t ocpolarity

channel output polarity

Definition at line 253 of file gd32f10x_timer.h.

uint16_t outputnstate

channel complementary output state

Definition at line 252 of file gd32f10x_timer.h.

uint32_t outputstate

channel output state

Definition at line 251 of file gd32f10x_timer.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h


GD32F10x_Firmware_Library: timer_parameter_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
timer_parameter_struct Struct Reference

#include <gd32f10x_timer.h>

Data Fields

uint16_t | prescaler
uint16_t | alignedmode
uint16_t | counterdirection
uint32_t | period
uint16_t | clockdivision
uint8_t | repetitioncounter

Detailed Description

Definition at line 226 of file gd32f10x_timer.h.

Field Documentation

uint16_t alignedmode

aligned mode

Definition at line 229 of file gd32f10x_timer.h.

uint16_t clockdivision

clock division value

Definition at line 232 of file gd32f10x_timer.h.

uint16_t counterdirection

counter direction

Definition at line 230 of file gd32f10x_timer.h.

uint32_t period

period value

Definition at line 231 of file gd32f10x_timer.h.

uint16_t prescaler

prescaler value

Definition at line 228 of file gd32f10x_timer.h.

uint8_t repetitioncounter

the counter repetition value

Definition at line 233 of file gd32f10x_timer.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h


GD32F10x_Firmware_Library: usb_core_cfgs_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_core_cfgs_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | core_id
uint8_t | core_speed
uint8_t | phy_interface
uint8_t | host_channel_num
uint8_t | dev_endp_num
uint8_t | sof_output
uint8_t | low_power
uint16_t | max_packet_size
uint16_t | max_fifo_size

Detailed Description

Definition at line 60 of file usb_core.h.

Field Documentation

uint8_t core_id

Definition at line 62 of file usb_core.h.

uint8_t core_speed

Definition at line 63 of file usb_core.h.

uint8_t dev_endp_num

Definition at line 66 of file usb_core.h.

uint8_t host_channel_num

Definition at line 65 of file usb_core.h.

uint8_t low_power

Definition at line 68 of file usb_core.h.

uint16_t max_fifo_size

Definition at line 70 of file usb_core.h.

uint16_t max_packet_size

Definition at line 69 of file usb_core.h.

uint8_t phy_interface

Definition at line 64 of file usb_core.h.

uint8_t sof_output

Definition at line 67 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_core.h


GD32F10x_Firmware_Library: usb_core_handle_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_core_handle_struct Struct Reference

#include <usb_core.h>

Data Fields

usb_core_cfgs_struct cfg
void(* | udelay )(const uint32_t usec)
void(* | mdelay )(const uint32_t msec)

Detailed Description

Definition at line 201 of file usb_core.h.

Field Documentation

usb_core_cfgs_struct cfg

Definition at line 203 of file usb_core.h.

void(* mdelay) (const uint32_t msec)

Definition at line 218 of file usb_core.h.

void(* udelay) (const uint32_t usec)

Definition at line 217 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_core.h


GD32F10x_Firmware_Library: usb_descriptor_configuration_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_configuration_struct Struct Reference

#include <usbd_std.h>

Data Fields

usb_descriptor_header_struct Header
uint16_t | wTotalLength
uint8_t | bNumInterfaces
uint8_t | bConfigurationValue
uint8_t | iConfiguration
uint8_t | bmAttributes
uint8_t | bMaxPower

Detailed Description

Definition at line 128 of file usbd_std.h.

Field Documentation

uint8_t bConfigurationValue

configuration index of the current configuration

Definition at line 134 of file usbd_std.h.

uint8_t bmAttributes

configuration attributes

Definition at line 136 of file usbd_std.h.

uint8_t bMaxPower

maximum power consumption of the device while in the current configuration

Definition at line 137 of file usbd_std.h.

uint8_t bNumInterfaces

total number of interfaces in the configuration

Definition at line 133 of file usbd_std.h.

usb_descriptor_header_struct Header

descriptor header, including type and size

Definition at line 130 of file usbd_std.h.

uint8_t iConfiguration

index of a string descriptor describing the configuration

Definition at line 135 of file usbd_std.h.

uint16_t wTotalLength

size of the configuration descriptor header,and all sub descriptors inside the configuration

Definition at line 132 of file usbd_std.h.

The documentation for this struct was generated from the following files:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_std.h
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h


GD32F10x_Firmware_Library: usb_descriptor_device_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_device_struct Struct Reference

#include <usbd_std.h>

Data Fields

usb_descriptor_header_struct Header
uint16_t | bcdUSB
uint8_t | bDeviceClass
uint8_t | bDeviceSubClass
uint8_t | bDeviceProtocol
uint8_t | bMaxPacketSize0
uint16_t | idVendor
uint16_t | idProduct
uint16_t | bcdDevice
uint8_t | iManufacturer
uint8_t | iProduct
uint8_t | iSerialNumber
uint8_t | bNumberConfigurations

Detailed Description

Definition at line 108 of file usbd_std.h.

Field Documentation

uint16_t bcdDevice

product release (version) number

Definition at line 119 of file usbd_std.h.

uint16_t bcdUSB

BCD of the supported USB specification

Definition at line 112 of file usbd_std.h.

uint8_t bDeviceClass

USB device class

Definition at line 113 of file usbd_std.h.

uint8_t bDeviceProtocol

USB device protocol

Definition at line 115 of file usbd_std.h.

uint8_t bDeviceSubClass

USB device subclass

Definition at line 114 of file usbd_std.h.

uint8_t bMaxPacketSize0

size of the control (address 0) endpoint's bank in bytes

Definition at line 116 of file usbd_std.h.

uint8_t bNumberConfigurations

total number of configurations supported by the device

Definition at line 123 of file usbd_std.h.

usb_descriptor_header_struct Header

descriptor header, including type and size

Definition at line 110 of file usbd_std.h.

uint16_t idProduct

unique product ID for the USB product

Definition at line 118 of file usbd_std.h.

uint16_t idVendor

vendor ID for the USB product

Definition at line 117 of file usbd_std.h.

uint8_t iManufacturer

string index for the manufacturer's name

Definition at line 120 of file usbd_std.h.

uint8_t iProduct

string index for the product name/details

Definition at line 121 of file usbd_std.h.

uint8_t iSerialNumber

string index for the product's globally unique hexadecimal serial number

Definition at line 122 of file usbd_std.h.

The documentation for this struct was generated from the following files:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_std.h
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h


GD32F10x_Firmware_Library: usb_descriptor_endpoint_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_endpoint_struct Struct Reference

#include <usbd_std.h>

Data Fields

usb_descriptor_header_struct Header
uint8_t | bEndpointAddress
uint8_t | bmAttributes
uint16_t | wMaxPacketSize
uint8_t | bInterval

Detailed Description

Definition at line 157 of file usbd_std.h.

Field Documentation

uint8_t bEndpointAddress

logical address of the endpoint

Definition at line 161 of file usbd_std.h.

uint8_t bInterval

polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type

Definition at line 164 of file usbd_std.h.

uint8_t bmAttributes

endpoint attributes

Definition at line 162 of file usbd_std.h.

usb_descriptor_header_struct Header

descriptor header, including type and size.

Definition at line 159 of file usbd_std.h.

uint16_t wMaxPacketSize

size of the endpoint bank, in bytes

Definition at line 163 of file usbd_std.h.

The documentation for this struct was generated from the following files:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_std.h
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h


GD32F10x_Firmware_Library: usb_descriptor_header_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_header_struct Struct Reference

#include <usbd_std.h>

Data Fields

uint8_t | bLength
uint8_t | bDescriptorType

Detailed Description

Definition at line 102 of file usbd_std.h.

Field Documentation

uint8_t bDescriptorType

type of the descriptor

Definition at line 105 of file usbd_std.h.

uint8_t bLength

size of the descriptor

Definition at line 104 of file usbd_std.h.

The documentation for this struct was generated from the following files:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_std.h
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h


GD32F10x_Firmware_Library: usb_descriptor_interface_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_interface_struct Struct Reference

#include <usbd_std.h>

Data Fields

usb_descriptor_header_struct Header
uint8_t | bInterfaceNumber
uint8_t | bAlternateSetting
uint8_t | bNumEndpoints
uint8_t | bInterfaceClass
uint8_t | bInterfaceSubClass
uint8_t | bInterfaceProtocol
uint8_t | iInterface

Detailed Description

Definition at line 142 of file usbd_std.h.

Field Documentation

uint8_t bAlternateSetting

alternate setting for the interface number

Definition at line 147 of file usbd_std.h.

uint8_t bInterfaceClass

interface class ID

Definition at line 149 of file usbd_std.h.

uint8_t bInterfaceNumber

index of the interface in the current configuration

Definition at line 146 of file usbd_std.h.

uint8_t bInterfaceProtocol

interface protocol ID

Definition at line 151 of file usbd_std.h.

uint8_t bInterfaceSubClass

interface subclass ID

Definition at line 150 of file usbd_std.h.

uint8_t bNumEndpoints

total number of endpoints in the interface

Definition at line 148 of file usbd_std.h.

usb_descriptor_header_struct Header

descriptor header, including type and size

Definition at line 144 of file usbd_std.h.

uint8_t iInterface

index of the string descriptor describing the interface

Definition at line 152 of file usbd_std.h.

The documentation for this struct was generated from the following files:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_std.h
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h


GD32F10x_Firmware_Library: usb_descriptor_language_id_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_language_id_struct Struct Reference

#include <usbd_std.h>

Data Fields

usb_descriptor_header_struct Header
uint16_t wLANGID

Detailed Description

Definition at line 167 of file usbd_std.h.

Field Documentation

usb_descriptor_header_struct Header

descriptor header, including type and size.

Definition at line 169 of file usbd_std.h.

uint16_t wLANGID

LANGID code

Definition at line 170 of file usbd_std.h.

The documentation for this struct was generated from the following files:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_std.h
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h


GD32F10x_Firmware_Library: usb_device_req_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_device_req_struct Struct Reference

#include <usbd_core.h>

Data Fields

uint8_t | bmRequestType
uint8_t | bRequest
uint16_t | wValue
uint16_t | wIndex
uint16_t | wLength

Detailed Description

Definition at line 115 of file usbd_core.h.

Field Documentation

uint8_t bmRequestType

the property of the request

Definition at line 117 of file usbd_core.h.

uint8_t bRequest

the code of the request

Definition at line 118 of file usbd_core.h.

uint16_t wIndex

USB standard device request index

Definition at line 120 of file usbd_core.h.

uint16_t wLength

the return datas length that the host wants to get

Definition at line 121 of file usbd_core.h.

uint16_t wValue

the value of the request which used to choose the different request in the same code request

Definition at line 119 of file usbd_core.h.

The documentation for this struct was generated from the following files:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_core.h
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_core.h


GD32F10x_Firmware_Library: usb_ep_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_ep_struct Struct Reference

#include <usbd_core.h>

Data Fields

uint8_t | stall
uint32_t | maxpacket
uint8_t * | trs_buf
uint32_t | trs_len
uint32_t | trs_count
uint8_t | endp_type
uint8_t | endp_frame
uint32_t | endp_mps
uint8_t * | xfer_buff
uint32_t | xfer_len
uint32_t | xfer_count
uint32_t | dma_addr

Detailed Description

Definition at line 102 of file usbd_core.h.

Field Documentation

uint32_t dma_addr

Definition at line 111 of file usb_core.h.

uint8_t endp_frame

Definition at line 103 of file usb_core.h.

uint32_t endp_mps

Definition at line 104 of file usb_core.h.

uint8_t endp_type

Definition at line 102 of file usb_core.h.

uint32_t maxpacket

the maxpacket of the endpoint

Definition at line 106 of file usbd_core.h.

uint8_t stall

endpoint stall status

Definition at line 105 of file usbd_core.h.

uint8_t* trs_buf

transaction buffer address

Definition at line 109 of file usbd_core.h.

uint32_t trs_count

transaction data counts

Definition at line 111 of file usbd_core.h.

uint32_t trs_len

transaction buffer length

Definition at line 110 of file usbd_core.h.

uint8_t* xfer_buff

Definition at line 107 of file usb_core.h.

uint32_t xfer_count

Definition at line 109 of file usb_core.h.

uint32_t xfer_len

Definition at line 108 of file usb_core.h.

The documentation for this struct was generated from the following files:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_core.h
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_core.h


GD32F10x_Firmware_Library: usb_hostchannel_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_hostchannel_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | dev_addr
uint8_t | dev_speed
uint8_t | DPID
uint8_t | endp_id
uint8_t | endp_in
uint8_t | endp_type
uint16_t | endp_mps
uint16_t | info
uint8_t * | xfer_buff
uint32_t | xfer_len
uint32_t | xfer_count
uint32_t | err_count
hc_status_enum status
urb_state_enum urb_state
uint8_t | data_tg_in
uint8_t | data_tg_out

Detailed Description

Definition at line 155 of file usb_core.h.

Field Documentation

uint8_t data_tg_in

Definition at line 175 of file usb_core.h.

uint8_t data_tg_out

Definition at line 176 of file usb_core.h.

uint8_t dev_addr

Definition at line 157 of file usb_core.h.

uint8_t dev_speed

Definition at line 158 of file usb_core.h.

uint8_t DPID

Definition at line 159 of file usb_core.h.

uint8_t endp_id

Definition at line 160 of file usb_core.h.

uint8_t endp_in

Definition at line 161 of file usb_core.h.

uint16_t endp_mps

Definition at line 163 of file usb_core.h.

uint8_t endp_type

Definition at line 162 of file usb_core.h.

uint32_t err_count

Definition at line 170 of file usb_core.h.

uint16_t info

Definition at line 164 of file usb_core.h.

hc_status_enum status

Definition at line 172 of file usb_core.h.

urb_state_enum urb_state

Definition at line 173 of file usb_core.h.

uint8_t* xfer_buff

Definition at line 166 of file usb_core.h.

uint32_t xfer_count

Definition at line 168 of file usb_core.h.

uint32_t xfer_len

Definition at line 167 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_core.h


GD32F10x_Firmware_Library: usb_setup_union Union Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Structures | Data Fields
usb_setup_union Union Reference

#include <usb_std.h>

Data Structures

struct _setup_packet_struct

Data Fields

uint8_t | data [8]
struct usb_setup_union::_setup_packet_struct | b

Detailed Description

Definition at line 108 of file usb_std.h.

Field Documentation

struct usb_setup_union::_setup_packet_struct b
uint8_t data[8]

Definition at line 110 of file usb_std.h.

The documentation for this union was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h


GD32F10x_Firmware_Library: usb_setup_union::_setup_packet_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
  • usb_setup_union
  • _setup_packet_struct
Data Fields
usb_setup_union::_setup_packet_struct Struct Reference

#include <usb_std.h>

Data Fields

uint8_t | bmRequestType
uint8_t | bRequest
uint16_t | wValue
uint16_t | wIndex
uint16_t | wLength

Detailed Description

Definition at line 112 of file usb_std.h.

Field Documentation

uint8_t bmRequestType

type of request

Definition at line 114 of file usb_std.h.

uint8_t bRequest

request of setup packet

Definition at line 115 of file usb_std.h.

uint16_t wIndex

index of setup packet

Definition at line 117 of file usb_std.h.

uint16_t wLength

length of setup packet

Definition at line 118 of file usb_std.h.

uint16_t wValue

value of setup packet

Definition at line 116 of file usb_std.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h


GD32F10x_Firmware_Library: usbd_core_handle_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbd_core_handle_struct Struct Reference

#include <usbd_core.h>

Data Fields

uint8_t | config_num
uint8_t | status
uint8_t | prev_status
uint8_t | remote_wakeup
uint8_t | setup_packet [8]
uint32_t | ctl_count
usb_ep_struct | in_ep [EP_COUNT]
usb_ep_struct | out_ep [EP_COUNT]
uint8_t * | dev_desc
uint8_t * | config_desc
void *const * | strings
usbd_status_enum(* | class_init )(void *pudev, uint8_t config_index)
usbd_status_enum(* | class_deinit )(void *pudev, uint8_t config_index)
usbd_status_enum(* | class_req_handler )(void *pudev, usb_device_req_struct *req)
usbd_status_enum(* | class_data_handler )(void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num)

Detailed Description

Definition at line 125 of file usbd_core.h.

Field Documentation

usbd_status_enum(* class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num)

Definition at line 154 of file usbd_core.h.

usbd_status_enum(* class_deinit) (void *pudev, uint8_t config_index)

Definition at line 152 of file usbd_core.h.

usbd_status_enum(* class_init) (void *pudev, uint8_t config_index)

Definition at line 151 of file usbd_core.h.

usbd_status_enum(* class_req_handler) (void *pudev, usb_device_req_struct *req)

Definition at line 153 of file usbd_core.h.

uint8_t* config_desc

configuration descriptor

Definition at line 147 of file usbd_core.h.

uint8_t config_num

the number of the USB device configuration

Definition at line 128 of file usbd_core.h.

uint32_t ctl_count

the datas length of control transfer request

Definition at line 136 of file usbd_core.h.

uint8_t* dev_desc

device descriptor

Definition at line 146 of file usbd_core.h.

usb_ep_struct in_ep[EP_COUNT]

the IN direction endpoints

Definition at line 139 of file usbd_core.h.

usb_ep_struct out_ep[EP_COUNT]

the OUT direction endpoints

Definition at line 140 of file usbd_core.h.

uint8_t prev_status

the previous USB device status

Definition at line 130 of file usbd_core.h.

uint8_t remote_wakeup

the flag that point out the device whether support the remte wakeup function

Definition at line 131 of file usbd_core.h.

uint8_t setup_packet[8]

the buffer used to store the setup packet

Definition at line 135 of file usbd_core.h.

uint8_t status

USB device status

Definition at line 129 of file usbd_core.h.

void* const* strings

configuration strings

Definition at line 148 of file usbd_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_core.h


GD32F10x_Firmware_Library: usbd_ep_buf_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbd_ep_buf_struct Struct Reference

#include <usbd_core.h>

Data Fields

uint16_t | tx_addr
uint16_t | reserved0
uint16_t | tx_count
uint16_t | reserved1
uint16_t | rx_addr
uint16_t | reserved2
uint16_t | rx_count
uint16_t | reserved3

Detailed Description

Definition at line 89 of file usbd_core.h.

Field Documentation

uint16_t reserved0

Definition at line 92 of file usbd_core.h.

uint16_t reserved1

Definition at line 94 of file usbd_core.h.

uint16_t reserved2

Definition at line 96 of file usbd_core.h.

uint16_t reserved3

Definition at line 98 of file usbd_core.h.

uint16_t rx_addr

reception address

Definition at line 95 of file usbd_core.h.

uint16_t rx_count

reception count

Definition at line 97 of file usbd_core.h.

uint16_t tx_addr

transmission address

Definition at line 91 of file usbd_core.h.

uint16_t tx_count

transmission count

Definition at line 93 of file usbd_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_core.h


GD32F10x_Firmware_Library: usbd_int_cb_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbd_int_cb_struct Struct Reference

#include <usbd_int.h>

Data Fields

uint8_t(* SOF )(usbd_core_handle_struct *pudev)

Detailed Description

Definition at line 22 of file usbd_int.h.

Field Documentation

uint8_t(* SOF)(usb_core_handle_struct *pudev)

SOF ISR callback

Definition at line 24 of file usbd_int.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_int.h


GD32F10x_Firmware_Library: usbh_ctrl_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_ctrl_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | hc_in_num
uint8_t | hc_out_num
uint8_t | ep0_size
uint8_t | error_count
uint16_t | length
uint16_t | timer
uint8_t * | buff
usb_setup_union setup

Detailed Description

Definition at line 126 of file usbh_core.h.

Field Documentation

uint8_t* buff

Definition at line 134 of file usbh_core.h.

uint8_t ep0_size

Definition at line 130 of file usbh_core.h.

uint8_t error_count

Definition at line 131 of file usbh_core.h.

uint8_t hc_in_num

Definition at line 128 of file usbh_core.h.

uint8_t hc_out_num

Definition at line 129 of file usbh_core.h.

uint16_t length

Definition at line 132 of file usbh_core.h.

usb_setup_union setup

Definition at line 135 of file usbh_core.h.

uint16_t timer

Definition at line 133 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h


GD32F10x_Firmware_Library: usbh_device_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_device_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | address
uint8_t | speed
usb_descriptor_device_struct dev_desc
usb_descriptor_configuration_struct cfg_desc
usb_descriptor_interface_struct | itf_desc [USBH_MAX_INTERFACES_NUM]
usb_descriptor_endpoint_struct | ep_desc [USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]

Detailed Description

Definition at line 139 of file usbh_core.h.

Field Documentation

uint8_t address

Definition at line 141 of file usbh_core.h.

usb_descriptor_configuration_struct cfg_desc

Definition at line 144 of file usbh_core.h.

usb_descriptor_device_struct dev_desc

Definition at line 143 of file usbh_core.h.

usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]

Definition at line 146 of file usbh_core.h.

usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]

Definition at line 145 of file usbh_core.h.

uint8_t speed

Definition at line 142 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h


GD32F10x_Firmware_Library: usbh_hcd_int_cb_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_hcd_int_cb_struct Struct Reference

#include <usbh_int.h>

Data Fields

uint8_t(* | sof )(usb_core_handle_struct *pudev)
uint8_t(* | device_connected )(usb_core_handle_struct *pudev)
uint8_t(* | device_disconnected )(usb_core_handle_struct *pudev)

Detailed Description

Definition at line 18 of file usbh_int.h.

Field Documentation

uint8_t(* device_connected) (usb_core_handle_struct *pudev)

Definition at line 21 of file usbh_int.h.

uint8_t(* device_disconnected) (usb_core_handle_struct *pudev)

Definition at line 22 of file usbh_int.h.

uint8_t(* sof) (usb_core_handle_struct *pudev)

Definition at line 20 of file usbh_int.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_int.h


GD32F10x_Firmware_Library: usbh_host_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_host_struct Struct Reference

#include <usbh_core.h>

Data Fields

backup_state_struct usbh_backup_state
usbh_ctrl_struct control
usbh_device_struct device
usbh_user_callback_struct * usr_cb
usbh_status_enum(* | class_init )(usb_core_handle_struct *pudev, void *phost)
void(* | class_deinit )(usb_core_handle_struct *pudev, void *phost)

Detailed Description

Definition at line 189 of file usbh_core.h.

Field Documentation

void(* class_deinit) (usb_core_handle_struct *pudev, void *phost)

Definition at line 196 of file usbh_core.h.

usbh_status_enum(* class_init) (usb_core_handle_struct *pudev, void *phost)

Definition at line 195 of file usbh_core.h.

usbh_ctrl_struct control

Definition at line 192 of file usbh_core.h.

usbh_device_struct device

Definition at line 193 of file usbh_core.h.

backup_state_struct usbh_backup_state

Definition at line 191 of file usbh_core.h.

usbh_user_callback_struct* usr_cb

Definition at line 194 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h


GD32F10x_Firmware_Library: usbh_state_handle_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_state_handle_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | usbh_current_state
uint8_t | usbh_current_state_table_size
state_table_struct * usbh_current_state_table
usbh_state_stack_struct stack [MAX_USBH_STATE_STACK_DEEP]
int8_t | usbh_current_state_stack_top
usbh_state_regist_table_struct usbh_regist_state_table [MAX_USBH_STATE_TABLE_NUM]
uint8_t | usbh_regist_state_table_num

Detailed Description

Definition at line 228 of file usbh_core.h.

Field Documentation

usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]

Definition at line 234 of file usbh_core.h.

uint8_t usbh_current_state

Definition at line 230 of file usbh_core.h.

int8_t usbh_current_state_stack_top

Definition at line 235 of file usbh_core.h.

state_table_struct* usbh_current_state_table

Definition at line 232 of file usbh_core.h.

uint8_t usbh_current_state_table_size

Definition at line 231 of file usbh_core.h.

usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]

Definition at line 237 of file usbh_core.h.

uint8_t usbh_regist_state_table_num

Definition at line 238 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h


GD32F10x_Firmware_Library: usbh_state_regist_table_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_state_regist_table_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | id
state_table_struct * table
uint8_t | table_size

Detailed Description

Definition at line 220 of file usbh_core.h.

Field Documentation

uint8_t id

Definition at line 222 of file usbh_core.h.

state_table_struct* table

Definition at line 223 of file usbh_core.h.

uint8_t table_size

Definition at line 224 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h


GD32F10x_Firmware_Library: usbh_state_stack_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_state_stack_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | state
state_table_struct * table
uint8_t | table_size

Detailed Description

Definition at line 212 of file usbh_core.h.

Field Documentation

uint8_t state

Definition at line 214 of file usbh_core.h.

state_table_struct* table

Definition at line 215 of file usbh_core.h.

uint8_t table_size

Definition at line 216 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h


GD32F10x_Firmware_Library: usbh_user_callback_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_user_callback_struct Struct Reference

#include <usbh_core.h>

Data Fields

void(* | init )(void)
void(* | deinit )(void)
void(* | device_connected )(void)
void(* | device_reset )(void)
void(* | device_disconnected )(void)
void(* | over_current_detected )(void)
void(* | device_speed_detected )(uint8_t device_speed)
void(* | device_desc_available )(void *devDesc)
void(* | device_address_set )(void)
void(* | configuration_desc_available )(usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct *ep_desc)
void(* | manufacturer_string )(void *mfc_string)
void(* | product_string )(void *prod_string)
void(* | serial_num_string )(void *serial_string)
void(* | enumeration_finish )(void)
usbh_user_status_enum(* | user_input )(void)
int(* | user_application )(usb_core_handle_struct *pudev, uint8_t id)
void(* | device_not_supported )(void)
void(* | unrecovered_error )(void)

Detailed Description

Definition at line 150 of file usbh_core.h.

Field Documentation

void(* configuration_desc_available) (usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct *ep_desc)

Definition at line 162 of file usbh_core.h.

void(* deinit) (void)

Definition at line 153 of file usbh_core.h.

void(* device_address_set) (void)

Definition at line 160 of file usbh_core.h.

void(* device_connected) (void)

Definition at line 154 of file usbh_core.h.

void(* device_desc_available) (void *devDesc)

Definition at line 159 of file usbh_core.h.

void(* device_disconnected) (void)

Definition at line 156 of file usbh_core.h.

void(* device_not_supported) (void)

Definition at line 174 of file usbh_core.h.

void(* device_reset) (void)

Definition at line 155 of file usbh_core.h.

void(* device_speed_detected) (uint8_t device_speed)

Definition at line 158 of file usbh_core.h.

void(* enumeration_finish) (void)

Definition at line 170 of file usbh_core.h.

void(* init) (void)

Definition at line 152 of file usbh_core.h.

void(* manufacturer_string) (void *mfc_string)

Definition at line 167 of file usbh_core.h.

void(* over_current_detected) (void)

Definition at line 157 of file usbh_core.h.

void(* product_string) (void *prod_string)

Definition at line 168 of file usbh_core.h.

void(* serial_num_string) (void *serial_string)

Definition at line 169 of file usbh_core.h.

void(* unrecovered_error) (void)

Definition at line 175 of file usbh_core.h.

int(* user_application) (usb_core_handle_struct *pudev, uint8_t id)

Definition at line 172 of file usbh_core.h.

usbh_user_status_enum(* user_input) (void)

Definition at line 171 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h


GD32F10x_Firmware_Library: Data Structure Index

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Structure Index
B | C | D | E | H | S | T | U | _
_
dma_parameter_struct
s
usb_core_handle_struct usbd_int_cb_struct
e
usb_descriptor_configuration_struct usbh_ctrl_struct
usb_setup_union::_setup_packet_struct spi_parameter_struct usb_descriptor_device_struct usbh_device_struct
b
enet_descriptors_struct state_table_struct usb_descriptor_endpoint_struct usbh_hcd_int_cb_struct
enet_initpara_struct
t
usb_descriptor_header_struct usbh_host_struct
backup_state_struct enet_ptp_systime_struct usb_descriptor_interface_struct usbh_state_handle_struct
c
exmc_nand_parameter_struct timer_break_parameter_struct usb_descriptor_language_id_struct usbh_state_regist_table_struct
exmc_nand_pccard_timing_parameter_struct timer_ic_parameter_struct usb_device_req_struct usbh_state_stack_struct
can_filter_parameter_struct exmc_norsram_parameter_struct timer_oc_parameter_struct usb_ep_struct usbh_user_callback_struct
can_parameter_struct exmc_norsram_timing_parameter_struct timer_parameter_struct usb_hostchannel_struct
can_receive_message_struct exmc_pccard_parameter_struct
u
usb_setup_union
can_trasnmit_message_struct
h
usbd_core_handle_struct
d
usb_core_cfgs_struct usbd_ep_buf_struct
hcd_dev_struct
dcd_dev_struct
B | C | D | E | H | S | T | U | _


GD32F10x_Firmware_Library: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • address : usbh_device_struct
  • address_data_mux : exmc_norsram_parameter_struct
  • alignedmode : timer_parameter_struct
  • asyn_access_mode : exmc_norsram_timing_parameter_struct
  • asyn_address_holdtime : exmc_norsram_timing_parameter_struct
  • asyn_address_setuptime : exmc_norsram_timing_parameter_struct
  • asyn_data_setuptime : exmc_norsram_timing_parameter_struct
  • asyn_wait : exmc_norsram_parameter_struct
  • atr_latency : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • attribute_space_timing : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • auto_bus_off_recovery : can_parameter_struct
  • auto_retrans : can_parameter_struct
  • auto_wake_up : can_parameter_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • b : usb_setup_union
  • bAlternateSetting : usb_descriptor_interface_struct
  • bcdDevice : usb_descriptor_device_struct
  • bcdUSB : usb_descriptor_device_struct
  • bConfigurationValue : usb_descriptor_configuration_struct
  • bDescriptorType : usb_descriptor_header_struct
  • bDeviceClass : usb_descriptor_device_struct
  • bDeviceProtocol : usb_descriptor_device_struct
  • bDeviceSubClass : usb_descriptor_device_struct
  • bEndpointAddress : usb_descriptor_endpoint_struct
  • bInterfaceClass : usb_descriptor_interface_struct
  • bInterfaceNumber : usb_descriptor_interface_struct
  • bInterfaceProtocol : usb_descriptor_interface_struct
  • bInterfaceSubClass : usb_descriptor_interface_struct
  • bInterval : usb_descriptor_endpoint_struct
  • bLength : usb_descriptor_header_struct
  • bmAttributes : usb_descriptor_configuration_struct , usb_descriptor_endpoint_struct
  • bMaxPacketSize0 : usb_descriptor_device_struct
  • bMaxPower : usb_descriptor_configuration_struct
  • bmRequestType : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • bNumberConfigurations : usb_descriptor_device_struct
  • bNumEndpoints : usb_descriptor_interface_struct
  • bNumInterfaces : usb_descriptor_configuration_struct
  • breakpolarity : timer_break_parameter_struct
  • breakstate : timer_break_parameter_struct
  • bRequest : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • buff : usbh_ctrl_struct
  • buffer1_addr : enet_descriptors_struct
  • buffer2_next_desc_addr : enet_descriptors_struct
  • burst_mode : exmc_norsram_parameter_struct
  • bus_latency : exmc_norsram_timing_parameter_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • cfg : usb_core_handle_struct
  • cfg_desc : usbh_device_struct
  • class_backup_state : backup_state_struct
  • class_data_handler : dcd_dev_struct , usbd_core_handle_struct
  • class_deinit : dcd_dev_struct , usbd_core_handle_struct , usbh_host_struct
  • class_init : dcd_dev_struct , usbd_core_handle_struct , usbh_host_struct
  • class_req_backup_state : backup_state_struct
  • class_req_handler : dcd_dev_struct , usbd_core_handle_struct
  • clock_polarity_phase : spi_parameter_struct
  • clockdivision : timer_parameter_struct
  • common_space_timing : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • config_desc : dcd_dev_struct , usbd_core_handle_struct
  • config_num : dcd_dev_struct , usbd_core_handle_struct
  • configuration_desc_available : usbh_user_callback_struct
  • connect_status : hcd_dev_struct
  • connection_status : dcd_dev_struct
  • control : usbh_host_struct
  • control_buffer_size : enet_descriptors_struct
  • core_id : usb_core_cfgs_struct
  • core_speed : usb_core_cfgs_struct
  • counterdirection : timer_parameter_struct
  • ctl_count : usbd_core_handle_struct
  • ctl_len : dcd_dev_struct
  • ctl_status : dcd_dev_struct
  • ctr_latency : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • ctrl_backup_state : backup_state_struct
  • cur_event : state_table_struct
  • cur_state : state_table_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • data : usb_setup_union
  • data_tg_in : usb_hostchannel_struct
  • data_tg_out : usb_hostchannel_struct
  • databus_hiztime : exmc_nand_pccard_timing_parameter_struct
  • databus_width : exmc_nand_parameter_struct , exmc_norsram_parameter_struct
  • deadtime : timer_break_parameter_struct
  • deinit : usbh_user_callback_struct
  • dev_addr : usb_hostchannel_struct
  • dev_desc : dcd_dev_struct , usbd_core_handle_struct , usbh_device_struct
  • dev_endp_num : usb_core_cfgs_struct
  • dev_speed : usb_hostchannel_struct
  • device : usbh_host_struct
  • device_address_set : usbh_user_callback_struct
  • device_connected : usbh_hcd_int_cb_struct , usbh_user_callback_struct
  • device_desc_available : usbh_user_callback_struct
  • device_disconnected : usbh_hcd_int_cb_struct , usbh_user_callback_struct
  • device_mode : spi_parameter_struct
  • device_not_supported : usbh_user_callback_struct
  • device_reset : usbh_user_callback_struct
  • device_speed_detected : usbh_user_callback_struct
  • direction : dma_parameter_struct
  • dma_addr : usb_ep_struct
  • dma_arbitration : enet_initpara_struct
  • dma_function : enet_initpara_struct
  • dma_maxburst : enet_initpara_struct
  • dmabus_mode : enet_initpara_struct
  • DPID : usb_hostchannel_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • ecc_logic : exmc_nand_parameter_struct
  • ecc_size : exmc_nand_parameter_struct
  • endian : spi_parameter_struct
  • endp_frame : usb_ep_struct
  • endp_id : usb_hostchannel_struct
  • endp_in : usb_hostchannel_struct
  • endp_mps : usb_ep_struct , usb_hostchannel_struct
  • endp_type : usb_ep_struct , usb_hostchannel_struct
  • enum_backup_state : backup_state_struct
  • enumeration_finish : usbh_user_callback_struct
  • ep0_size : usbh_ctrl_struct
  • ep_desc : usbh_device_struct
  • err_count : usb_hostchannel_struct
  • error_count : usbh_ctrl_struct
  • event_action_fun : state_table_struct
  • extended_mode : exmc_norsram_parameter_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • filter_bits : can_filter_parameter_struct
  • filter_enable : can_filter_parameter_struct
  • filter_fifo_number : can_filter_parameter_struct
  • filter_list_high : can_filter_parameter_struct
  • filter_list_low : can_filter_parameter_struct
  • filter_mask_high : can_filter_parameter_struct
  • filter_mask_low : can_filter_parameter_struct
  • filter_mode : can_filter_parameter_struct
  • filter_number : can_filter_parameter_struct
  • flow_control : enet_initpara_struct
  • forward_frame : enet_initpara_struct
  • frame_size : spi_parameter_struct
  • framesfilter_mode : enet_initpara_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • halfduplex_param : enet_initpara_struct
  • hashtable_high : enet_initpara_struct
  • hashtable_low : enet_initpara_struct
  • hc_in_num : usbh_ctrl_struct
  • hc_out_num : usbh_ctrl_struct
  • Header : usb_descriptor_configuration_struct , usb_descriptor_device_struct , usb_descriptor_endpoint_struct , usb_descriptor_interface_struct , usb_descriptor_language_id_struct
  • holdtime : exmc_nand_pccard_timing_parameter_struct
  • host_backup_state : backup_state_struct
  • host_channel : hcd_dev_struct
  • host_channel_num : usb_core_cfgs_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • icfilter : timer_ic_parameter_struct
  • iConfiguration : usb_descriptor_configuration_struct
  • icpolarity : timer_ic_parameter_struct
  • icprescaler : timer_ic_parameter_struct
  • icselection : timer_ic_parameter_struct
  • id : usbh_state_regist_table_struct
  • ideloffstate : timer_break_parameter_struct
  • idProduct : usb_descriptor_device_struct
  • idVendor : usb_descriptor_device_struct
  • iInterface : usb_descriptor_interface_struct
  • iManufacturer : usb_descriptor_device_struct
  • in_ep : dcd_dev_struct , usbd_core_handle_struct
  • info : usb_hostchannel_struct
  • init : usbh_user_callback_struct
  • interframegap : enet_initpara_struct
  • io_space_timing : exmc_pccard_parameter_struct
  • iProduct : usb_descriptor_device_struct
  • iSerialNumber : usb_descriptor_device_struct
  • itf_desc : usbh_device_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • length : usbh_ctrl_struct
  • low_power : usb_core_cfgs_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • manufacturer_string : usbh_user_callback_struct
  • max_fifo_size : usb_core_cfgs_struct
  • max_packet_size : usb_core_cfgs_struct
  • maxpacket : usb_ep_struct
  • mdelay : usb_core_handle_struct
  • memory_addr : dma_parameter_struct
  • memory_inc : dma_parameter_struct
  • memory_type : exmc_norsram_parameter_struct
  • memory_width : dma_parameter_struct
  • memory_write : exmc_norsram_parameter_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • nand_bank : exmc_nand_parameter_struct
  • nanosecond : enet_ptp_systime_struct
  • next_state : state_table_struct
  • norsram_region : exmc_norsram_parameter_struct
  • nss : spi_parameter_struct
  • number : dma_parameter_struct
  • nwait_config : exmc_norsram_parameter_struct
  • nwait_polarity : exmc_norsram_parameter_struct
  • nwait_signal : exmc_norsram_parameter_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • ocidlestate : timer_oc_parameter_struct
  • ocnidlestate : timer_oc_parameter_struct
  • ocnpolarity : timer_oc_parameter_struct
  • ocpolarity : timer_oc_parameter_struct
  • option_enable : enet_initpara_struct
  • out_ep : dcd_dev_struct , usbd_core_handle_struct
  • outputautostate : timer_break_parameter_struct
  • outputnstate : timer_oc_parameter_struct
  • outputstate : timer_oc_parameter_struct
  • over_current_detected : usbh_user_callback_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • period : timer_parameter_struct
  • periph_addr : dma_parameter_struct
  • periph_inc : dma_parameter_struct
  • periph_width : dma_parameter_struct
  • phy_interface : usb_core_cfgs_struct
  • prescale : spi_parameter_struct
  • prescaler : can_parameter_struct , timer_parameter_struct
  • prev_status : dcd_dev_struct , usbd_core_handle_struct
  • priority : dma_parameter_struct
  • product_string : usbh_user_callback_struct
  • protectmode : timer_break_parameter_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • read_write_timing : exmc_norsram_parameter_struct
  • rec_fifo_overwrite : can_parameter_struct
  • remain_len : dcd_dev_struct
  • remote_wakeup : dcd_dev_struct , usbd_core_handle_struct
  • repetitioncounter : timer_parameter_struct
  • reserved0 : usbd_ep_buf_struct
  • reserved1 : usbd_ep_buf_struct
  • reserved2 : usbd_ep_buf_struct
  • reserved3 : usbd_ep_buf_struct
  • resync_jump_width : can_parameter_struct
  • runoffstate : timer_break_parameter_struct
  • rx_addr : usbd_ep_buf_struct
  • rx_buffer : hcd_dev_struct
  • rx_count : usbd_ep_buf_struct
  • rx_data : can_receive_message_struct
  • rx_dlen : can_receive_message_struct
  • rx_efid : can_receive_message_struct
  • rx_ff : can_receive_message_struct
  • rx_fi : can_receive_message_struct
  • rx_ft : can_receive_message_struct
  • rx_sfid : can_receive_message_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • second : enet_ptp_systime_struct
  • serial_num_string : usbh_user_callback_struct
  • setup : usbh_ctrl_struct
  • setup_packet : dcd_dev_struct , usbd_core_handle_struct
  • setuptime : exmc_nand_pccard_timing_parameter_struct
  • sign : enet_ptp_systime_struct
  • SOF : usbd_int_cb_struct
  • sof : usbh_hcd_int_cb_struct
  • sof_output : usb_core_cfgs_struct
  • speed : usbh_device_struct
  • stack : usbh_state_handle_struct
  • stall : usb_ep_struct
  • state : usbh_state_stack_struct
  • status : dcd_dev_struct , enet_descriptors_struct , usb_hostchannel_struct , usbd_core_handle_struct
  • store_forward_mode : enet_initpara_struct
  • strings : dcd_dev_struct , usbd_core_handle_struct
  • sum_len : dcd_dev_struct
  • syn_clk_division : exmc_norsram_timing_parameter_struct
  • syn_data_latency : exmc_norsram_timing_parameter_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • table : usbh_state_regist_table_struct , usbh_state_stack_struct
  • table_size : usbh_state_regist_table_struct , usbh_state_stack_struct
  • time_segment_1 : can_parameter_struct
  • time_segment_2 : can_parameter_struct
  • time_triggered : can_parameter_struct
  • timer : usbh_ctrl_struct
  • timer_config : enet_initpara_struct
  • trans_fifo_order : can_parameter_struct
  • trans_mode : spi_parameter_struct
  • trs_buf : usb_ep_struct
  • trs_count : usb_ep_struct
  • trs_len : usb_ep_struct
  • tx_addr : usbd_ep_buf_struct
  • tx_count : usbd_ep_buf_struct
  • tx_data : can_trasnmit_message_struct
  • tx_dlen : can_trasnmit_message_struct
  • tx_efid : can_trasnmit_message_struct
  • tx_ff : can_trasnmit_message_struct
  • tx_ft : can_trasnmit_message_struct
  • tx_sfid : can_trasnmit_message_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • udelay : usb_core_handle_struct
  • unrecovered_error : usbh_user_callback_struct
  • urb_state : usb_hostchannel_struct
  • usbh_backup_state : usbh_host_struct
  • usbh_current_state : usbh_state_handle_struct
  • usbh_current_state_stack_top : usbh_state_handle_struct
  • usbh_current_state_table : usbh_state_handle_struct
  • usbh_current_state_table_size : usbh_state_handle_struct
  • usbh_regist_state_table : usbh_state_handle_struct
  • usbh_regist_state_table_num : usbh_state_handle_struct
  • user_application : usbh_user_callback_struct
  • user_input : usbh_user_callback_struct
  • usr_cb : usbh_host_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- v -

  • vbus_drive : hcd_dev_struct
  • vlan_config : enet_initpara_struct


GD32F10x_Firmware_Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • wait_feature : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • waittime : exmc_nand_pccard_timing_parameter_struct
  • wIndex : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • wLANGID : usb_descriptor_language_id_struct
  • wLength : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • wMaxPacketSize : usb_descriptor_endpoint_struct
  • working_mode : can_parameter_struct
  • wrap_burst_mode : exmc_norsram_parameter_struct
  • write_mode : exmc_norsram_parameter_struct
  • write_timing : exmc_norsram_parameter_struct
  • wTotalLength : usb_descriptor_configuration_struct
  • wValue : usb_device_req_struct , usb_setup_union::_setup_packet_struct


GD32F10x_Firmware_Library: Data Fields

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  • x
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • xfer_buff : usb_ep_struct , usb_hostchannel_struct
  • xfer_count : usb_ep_struct , usb_hostchannel_struct
  • xfer_len : usb_ep_struct , usb_hostchannel_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- a -

  • address : usbh_device_struct
  • address_data_mux : exmc_norsram_parameter_struct
  • alignedmode : timer_parameter_struct
  • asyn_access_mode : exmc_norsram_timing_parameter_struct
  • asyn_address_holdtime : exmc_norsram_timing_parameter_struct
  • asyn_address_setuptime : exmc_norsram_timing_parameter_struct
  • asyn_data_setuptime : exmc_norsram_timing_parameter_struct
  • asyn_wait : exmc_norsram_parameter_struct
  • atr_latency : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • attribute_space_timing : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • auto_bus_off_recovery : can_parameter_struct
  • auto_retrans : can_parameter_struct
  • auto_wake_up : can_parameter_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- b -

  • b : usb_setup_union
  • bAlternateSetting : usb_descriptor_interface_struct
  • bcdDevice : usb_descriptor_device_struct
  • bcdUSB : usb_descriptor_device_struct
  • bConfigurationValue : usb_descriptor_configuration_struct
  • bDescriptorType : usb_descriptor_header_struct
  • bDeviceClass : usb_descriptor_device_struct
  • bDeviceProtocol : usb_descriptor_device_struct
  • bDeviceSubClass : usb_descriptor_device_struct
  • bEndpointAddress : usb_descriptor_endpoint_struct
  • bInterfaceClass : usb_descriptor_interface_struct
  • bInterfaceNumber : usb_descriptor_interface_struct
  • bInterfaceProtocol : usb_descriptor_interface_struct
  • bInterfaceSubClass : usb_descriptor_interface_struct
  • bInterval : usb_descriptor_endpoint_struct
  • bLength : usb_descriptor_header_struct
  • bmAttributes : usb_descriptor_configuration_struct , usb_descriptor_endpoint_struct
  • bMaxPacketSize0 : usb_descriptor_device_struct
  • bMaxPower : usb_descriptor_configuration_struct
  • bmRequestType : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • bNumberConfigurations : usb_descriptor_device_struct
  • bNumEndpoints : usb_descriptor_interface_struct
  • bNumInterfaces : usb_descriptor_configuration_struct
  • breakpolarity : timer_break_parameter_struct
  • breakstate : timer_break_parameter_struct
  • bRequest : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • buff : usbh_ctrl_struct
  • buffer1_addr : enet_descriptors_struct
  • buffer2_next_desc_addr : enet_descriptors_struct
  • burst_mode : exmc_norsram_parameter_struct
  • bus_latency : exmc_norsram_timing_parameter_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- c -

  • cfg : usb_core_handle_struct
  • cfg_desc : usbh_device_struct
  • class_backup_state : backup_state_struct
  • class_data_handler : dcd_dev_struct , usbd_core_handle_struct
  • class_deinit : dcd_dev_struct , usbd_core_handle_struct , usbh_host_struct
  • class_init : dcd_dev_struct , usbd_core_handle_struct , usbh_host_struct
  • class_req_backup_state : backup_state_struct
  • class_req_handler : dcd_dev_struct , usbd_core_handle_struct
  • clock_polarity_phase : spi_parameter_struct
  • clockdivision : timer_parameter_struct
  • common_space_timing : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • config_desc : dcd_dev_struct , usbd_core_handle_struct
  • config_num : dcd_dev_struct , usbd_core_handle_struct
  • configuration_desc_available : usbh_user_callback_struct
  • connect_status : hcd_dev_struct
  • connection_status : dcd_dev_struct
  • control : usbh_host_struct
  • control_buffer_size : enet_descriptors_struct
  • core_id : usb_core_cfgs_struct
  • core_speed : usb_core_cfgs_struct
  • counterdirection : timer_parameter_struct
  • ctl_count : usbd_core_handle_struct
  • ctl_len : dcd_dev_struct
  • ctl_status : dcd_dev_struct
  • ctr_latency : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • ctrl_backup_state : backup_state_struct
  • cur_event : state_table_struct
  • cur_state : state_table_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- d -

  • data : usb_setup_union
  • data_tg_in : usb_hostchannel_struct
  • data_tg_out : usb_hostchannel_struct
  • databus_hiztime : exmc_nand_pccard_timing_parameter_struct
  • databus_width : exmc_nand_parameter_struct , exmc_norsram_parameter_struct
  • deadtime : timer_break_parameter_struct
  • deinit : usbh_user_callback_struct
  • dev_addr : usb_hostchannel_struct
  • dev_desc : dcd_dev_struct , usbd_core_handle_struct , usbh_device_struct
  • dev_endp_num : usb_core_cfgs_struct
  • dev_speed : usb_hostchannel_struct
  • device : usbh_host_struct
  • device_address_set : usbh_user_callback_struct
  • device_connected : usbh_hcd_int_cb_struct , usbh_user_callback_struct
  • device_desc_available : usbh_user_callback_struct
  • device_disconnected : usbh_hcd_int_cb_struct , usbh_user_callback_struct
  • device_mode : spi_parameter_struct
  • device_not_supported : usbh_user_callback_struct
  • device_reset : usbh_user_callback_struct
  • device_speed_detected : usbh_user_callback_struct
  • direction : dma_parameter_struct
  • dma_addr : usb_ep_struct
  • dma_arbitration : enet_initpara_struct
  • dma_function : enet_initpara_struct
  • dma_maxburst : enet_initpara_struct
  • dmabus_mode : enet_initpara_struct
  • DPID : usb_hostchannel_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- e -

  • ecc_logic : exmc_nand_parameter_struct
  • ecc_size : exmc_nand_parameter_struct
  • endian : spi_parameter_struct
  • endp_frame : usb_ep_struct
  • endp_id : usb_hostchannel_struct
  • endp_in : usb_hostchannel_struct
  • endp_mps : usb_ep_struct , usb_hostchannel_struct
  • endp_type : usb_ep_struct , usb_hostchannel_struct
  • enum_backup_state : backup_state_struct
  • enumeration_finish : usbh_user_callback_struct
  • ep0_size : usbh_ctrl_struct
  • ep_desc : usbh_device_struct
  • err_count : usb_hostchannel_struct
  • error_count : usbh_ctrl_struct
  • event_action_fun : state_table_struct
  • extended_mode : exmc_norsram_parameter_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- f -

  • filter_bits : can_filter_parameter_struct
  • filter_enable : can_filter_parameter_struct
  • filter_fifo_number : can_filter_parameter_struct
  • filter_list_high : can_filter_parameter_struct
  • filter_list_low : can_filter_parameter_struct
  • filter_mask_high : can_filter_parameter_struct
  • filter_mask_low : can_filter_parameter_struct
  • filter_mode : can_filter_parameter_struct
  • filter_number : can_filter_parameter_struct
  • flow_control : enet_initpara_struct
  • forward_frame : enet_initpara_struct
  • frame_size : spi_parameter_struct
  • framesfilter_mode : enet_initpara_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- h -

  • halfduplex_param : enet_initpara_struct
  • hashtable_high : enet_initpara_struct
  • hashtable_low : enet_initpara_struct
  • hc_in_num : usbh_ctrl_struct
  • hc_out_num : usbh_ctrl_struct
  • Header : usb_descriptor_configuration_struct , usb_descriptor_device_struct , usb_descriptor_endpoint_struct , usb_descriptor_interface_struct , usb_descriptor_language_id_struct
  • holdtime : exmc_nand_pccard_timing_parameter_struct
  • host_backup_state : backup_state_struct
  • host_channel : hcd_dev_struct
  • host_channel_num : usb_core_cfgs_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- i -

  • icfilter : timer_ic_parameter_struct
  • iConfiguration : usb_descriptor_configuration_struct
  • icpolarity : timer_ic_parameter_struct
  • icprescaler : timer_ic_parameter_struct
  • icselection : timer_ic_parameter_struct
  • id : usbh_state_regist_table_struct
  • ideloffstate : timer_break_parameter_struct
  • idProduct : usb_descriptor_device_struct
  • idVendor : usb_descriptor_device_struct
  • iInterface : usb_descriptor_interface_struct
  • iManufacturer : usb_descriptor_device_struct
  • in_ep : dcd_dev_struct , usbd_core_handle_struct
  • info : usb_hostchannel_struct
  • init : usbh_user_callback_struct
  • interframegap : enet_initpara_struct
  • io_space_timing : exmc_pccard_parameter_struct
  • iProduct : usb_descriptor_device_struct
  • iSerialNumber : usb_descriptor_device_struct
  • itf_desc : usbh_device_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- l -

  • length : usbh_ctrl_struct
  • low_power : usb_core_cfgs_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- m -

  • manufacturer_string : usbh_user_callback_struct
  • max_fifo_size : usb_core_cfgs_struct
  • max_packet_size : usb_core_cfgs_struct
  • maxpacket : usb_ep_struct
  • mdelay : usb_core_handle_struct
  • memory_addr : dma_parameter_struct
  • memory_inc : dma_parameter_struct
  • memory_type : exmc_norsram_parameter_struct
  • memory_width : dma_parameter_struct
  • memory_write : exmc_norsram_parameter_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- n -

  • nand_bank : exmc_nand_parameter_struct
  • nanosecond : enet_ptp_systime_struct
  • next_state : state_table_struct
  • norsram_region : exmc_norsram_parameter_struct
  • nss : spi_parameter_struct
  • number : dma_parameter_struct
  • nwait_config : exmc_norsram_parameter_struct
  • nwait_polarity : exmc_norsram_parameter_struct
  • nwait_signal : exmc_norsram_parameter_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- o -

  • ocidlestate : timer_oc_parameter_struct
  • ocnidlestate : timer_oc_parameter_struct
  • ocnpolarity : timer_oc_parameter_struct
  • ocpolarity : timer_oc_parameter_struct
  • option_enable : enet_initpara_struct
  • out_ep : dcd_dev_struct , usbd_core_handle_struct
  • outputautostate : timer_break_parameter_struct
  • outputnstate : timer_oc_parameter_struct
  • outputstate : timer_oc_parameter_struct
  • over_current_detected : usbh_user_callback_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- p -

  • period : timer_parameter_struct
  • periph_addr : dma_parameter_struct
  • periph_inc : dma_parameter_struct
  • periph_width : dma_parameter_struct
  • phy_interface : usb_core_cfgs_struct
  • prescale : spi_parameter_struct
  • prescaler : can_parameter_struct , timer_parameter_struct
  • prev_status : dcd_dev_struct , usbd_core_handle_struct
  • priority : dma_parameter_struct
  • product_string : usbh_user_callback_struct
  • protectmode : timer_break_parameter_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- r -

  • read_write_timing : exmc_norsram_parameter_struct
  • rec_fifo_overwrite : can_parameter_struct
  • remain_len : dcd_dev_struct
  • remote_wakeup : dcd_dev_struct , usbd_core_handle_struct
  • repetitioncounter : timer_parameter_struct
  • reserved0 : usbd_ep_buf_struct
  • reserved1 : usbd_ep_buf_struct
  • reserved2 : usbd_ep_buf_struct
  • reserved3 : usbd_ep_buf_struct
  • resync_jump_width : can_parameter_struct
  • runoffstate : timer_break_parameter_struct
  • rx_addr : usbd_ep_buf_struct
  • rx_buffer : hcd_dev_struct
  • rx_count : usbd_ep_buf_struct
  • rx_data : can_receive_message_struct
  • rx_dlen : can_receive_message_struct
  • rx_efid : can_receive_message_struct
  • rx_ff : can_receive_message_struct
  • rx_fi : can_receive_message_struct
  • rx_ft : can_receive_message_struct
  • rx_sfid : can_receive_message_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- s -

  • second : enet_ptp_systime_struct
  • serial_num_string : usbh_user_callback_struct
  • setup : usbh_ctrl_struct
  • setup_packet : dcd_dev_struct , usbd_core_handle_struct
  • setuptime : exmc_nand_pccard_timing_parameter_struct
  • sign : enet_ptp_systime_struct
  • SOF : usbd_int_cb_struct
  • sof : usbh_hcd_int_cb_struct
  • sof_output : usb_core_cfgs_struct
  • speed : usbh_device_struct
  • stack : usbh_state_handle_struct
  • stall : usb_ep_struct
  • state : usbh_state_stack_struct
  • status : dcd_dev_struct , enet_descriptors_struct , usb_hostchannel_struct , usbd_core_handle_struct
  • store_forward_mode : enet_initpara_struct
  • strings : dcd_dev_struct , usbd_core_handle_struct
  • sum_len : dcd_dev_struct
  • syn_clk_division : exmc_norsram_timing_parameter_struct
  • syn_data_latency : exmc_norsram_timing_parameter_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- t -

  • table : usbh_state_regist_table_struct , usbh_state_stack_struct
  • table_size : usbh_state_regist_table_struct , usbh_state_stack_struct
  • time_segment_1 : can_parameter_struct
  • time_segment_2 : can_parameter_struct
  • time_triggered : can_parameter_struct
  • timer : usbh_ctrl_struct
  • timer_config : enet_initpara_struct
  • trans_fifo_order : can_parameter_struct
  • trans_mode : spi_parameter_struct
  • trs_buf : usb_ep_struct
  • trs_count : usb_ep_struct
  • trs_len : usb_ep_struct
  • tx_addr : usbd_ep_buf_struct
  • tx_count : usbd_ep_buf_struct
  • tx_data : can_trasnmit_message_struct
  • tx_dlen : can_trasnmit_message_struct
  • tx_efid : can_trasnmit_message_struct
  • tx_ff : can_trasnmit_message_struct
  • tx_ft : can_trasnmit_message_struct
  • tx_sfid : can_trasnmit_message_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- u -

  • udelay : usb_core_handle_struct
  • unrecovered_error : usbh_user_callback_struct
  • urb_state : usb_hostchannel_struct
  • usbh_backup_state : usbh_host_struct
  • usbh_current_state : usbh_state_handle_struct
  • usbh_current_state_stack_top : usbh_state_handle_struct
  • usbh_current_state_table : usbh_state_handle_struct
  • usbh_current_state_table_size : usbh_state_handle_struct
  • usbh_regist_state_table : usbh_state_handle_struct
  • usbh_regist_state_table_num : usbh_state_handle_struct
  • user_application : usbh_user_callback_struct
  • user_input : usbh_user_callback_struct
  • usr_cb : usbh_host_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- v -

  • vbus_drive : hcd_dev_struct
  • vlan_config : enet_initpara_struct


GD32F10x_Firmware_Library: Data Fields - Variables

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- w -

  • wait_feature : exmc_nand_parameter_struct , exmc_pccard_parameter_struct
  • waittime : exmc_nand_pccard_timing_parameter_struct
  • wIndex : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • wLANGID : usb_descriptor_language_id_struct
  • wLength : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • wMaxPacketSize : usb_descriptor_endpoint_struct
  • working_mode : can_parameter_struct
  • wrap_burst_mode : exmc_norsram_parameter_struct
  • write_mode : exmc_norsram_parameter_struct
  • write_timing : exmc_norsram_parameter_struct
  • wTotalLength : usb_descriptor_configuration_struct
  • wValue : usb_device_req_struct , usb_setup_union::_setup_packet_struct


GD32F10x_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x

- x -

  • xfer_buff : usb_ep_struct , usb_hostchannel_struct
  • xfer_count : usb_ep_struct , usb_hostchannel_struct
  • xfer_len : usb_ep_struct , usb_hostchannel_struct


GD32F10x_Firmware_Library: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
[detail level 123456]
▼ E: |
▼ GD32F10x_Firmware_Library_V2.0.0 |
▼ Firmware |
▼ GD32F10x_standard_peripheral |
▼ Include |
gd32f10x_adc.h | Definitions for the ADC
gd32f10x_bkp.h | Definitions for the BKP
gd32f10x_can.h | Definitions for the CAN
gd32f10x_crc.h | Definitions for the CRC
gd32f10x_dac.h | Definitions for the DAC
gd32f10x_dbg.h | Definitions for the DBG
gd32f10x_dma.h | Definitions for the DMA
gd32f10x_enet.h | Definitions for the ENET
gd32f10x_exmc.h | Definitions for the EXMC
gd32f10x_exti.h | Definitions for the EXTI
gd32f10x_fmc.h | Definitions for the FMC
gd32f10x_fwdgt.h | Definitions for the FWDGT
gd32f10x_gpio.h | Definitions for the GPIO
gd32f10x_i2c.h | Definitions for the I2C
gd32f10x_misc.h | Definitions for the MISC
gd32f10x_pmu.h | Definitions for the PMU
gd32f10x_rcu.h | Definitions for the RCU
gd32f10x_rtc.h | Definitions for the RTC
gd32f10x_sdio.h | Definitions for the SDIO
gd32f10x_spi.h | Definitions for the SPI
gd32f10x_timer.h | Definitions for the TIMER
gd32f10x_usart.h | Definitions for the USART
gd32f10x_wwdgt.h | Definitions for the WWDGT
▼ Source |
gd32f10x_adc.c | ADC driver
gd32f10x_bkp.c | BKP driver
gd32f10x_can.c | CAN driver
gd32f10x_crc.c | CRC driver
gd32f10x_dac.c | DAC driver
gd32f10x_dbg.c | DBG driver
gd32f10x_dma.c | DMA driver
gd32f10x_enet.c | ENET driver
gd32f10x_exmc.c | EXMC driver
gd32f10x_exti.c | EXTI driver
gd32f10x_fmc.c | FMC driver
gd32f10x_fwdgt.c | FWDGT driver
gd32f10x_gpio.c | GPIO driver
gd32f10x_i2c.c | I2C driver
gd32f10x_misc.c | MISC driver
gd32f10x_pmu.c | PMU driver
gd32f10x_rcu.c | RCU driver
gd32f10x_rtc.c | RTC driver
gd32f10x_sdio.c | SDIO driver
gd32f10x_spi.c | SPI driver
gd32f10x_timer.c | TIMER driver
gd32f10x_usart.c | USART driver
gd32f10x_wwdgt.c | WWDGT driver
▼ GD32F10x_usbd_driver |
▼ Include |
usbd_core.h |
usbd_int.h |
usbd_pwr.h | USB device power management functions prototype
usbd_regs.h | USB device registers
usbd_std.h |
▼ Source |
usbd_core.c |
usbd_int.c |
usbd_pwr.c | USB device power management driver
usbd_std.c |
▼ GD32F10x_usbfs_driver |
▼ Include |
usb_core.h | USB core driver header file
usb_defines.h | USB core defines
usb_regs.h | USB FS cell registers definition and handle macros
usb_std.h | USB 2.0 standard defines
usbd_core.h |
usbd_int.h |
usbd_std.h |
usbh_core.h | Header file for usbh_core.c
usbh_ctrl.h | Header file for usbh_ctrl.c
usbh_hcs.h | Header file for usbh_hcs.c
usbh_int.h | USB host mode interrupt handler header file
usbh_std.h | Header file for usbh_std.c
▼ Source |
usb_core.c | USB core driver which can operate in host-mode and device-mode
usbd_core.c |
usbd_int.c |
usbd_std.c |
usbh_core.c | This file implements the functions for the core state machine process
usbh_ctrl.c | This file implements the functions for the control transmit process
usbh_hcs.c | This file implements functions for opening and closing host channels
usbh_int.c | USB host mode interrupt handler file
usbh_std.c | USB 2.0 standard function definition


GD32F10x_Firmware_Library: E: Directory Reference

  • E:
E: Directory Reference

Directories

directory GD32F10x_Firmware_Library_V2.0.0


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0 Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
GD32F10x_Firmware_Library_V2.0.0 Directory Reference

Directories

directory Firmware


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
Firmware Directory Reference

Directories

directory | GD32F10x_standard_peripheral
directory | GD32F10x_usbd_driver
directory | GD32F10x_usbfs_driver


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
GD32F10x_standard_peripheral Directory Reference

Directories

directory | Include
directory | Source


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Include Directory Reference

Files

file | gd32f10x_adc.h [code]
definitions for the ADC
file | gd32f10x_bkp.h [code]
definitions for the BKP
file | gd32f10x_can.h [code]
definitions for the CAN
file | gd32f10x_crc.h [code]
definitions for the CRC
file | gd32f10x_dac.h [code]
definitions for the DAC
file | gd32f10x_dbg.h [code]
definitions for the DBG
file | gd32f10x_dma.h [code]
definitions for the DMA
file | gd32f10x_enet.h [code]
definitions for the ENET
file | gd32f10x_exmc.h [code]
definitions for the EXMC
file | gd32f10x_exti.h [code]
definitions for the EXTI
file | gd32f10x_fmc.h [code]
definitions for the FMC
file | gd32f10x_fwdgt.h [code]
definitions for the FWDGT
file | gd32f10x_gpio.h [code]
definitions for the GPIO
file | gd32f10x_i2c.h [code]
definitions for the I2C
file | gd32f10x_misc.h [code]
definitions for the MISC
file | gd32f10x_pmu.h [code]
definitions for the PMU
file | gd32f10x_rcu.h [code]
definitions for the RCU
file | gd32f10x_rtc.h [code]
definitions for the RTC
file | gd32f10x_sdio.h [code]
definitions for the SDIO
file | gd32f10x_spi.h [code]
definitions for the SPI
file | gd32f10x_timer.h [code]
definitions for the TIMER
file | gd32f10x_usart.h [code]
definitions for the USART
file | gd32f10x_wwdgt.h [code]
definitions for the WWDGT


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_adc.h File Reference

definitions for the ADC More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | ADC0 ADC_BASE
#define | ADC1 (ADC_BASE + 0x400U)
#define | ADC2 (ADC_BASE + 0x1800U)
#define | ADC_STAT(adcx) REG32((adcx) + 0x00U)
#define | ADC_CTL0(adcx) REG32((adcx) + 0x04U)
#define | ADC_CTL1(adcx) REG32((adcx) + 0x08U)
#define | ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU)
#define | ADC_SAMPT1(adcx) REG32((adcx) + 0x10U)
#define | ADC_IOFF0(adcx) REG32((adcx) + 0x14U)
#define | ADC_IOFF1(adcx) REG32((adcx) + 0x18U)
#define | ADC_IOFF2(adcx) REG32((adcx) + 0x1CU)
#define | ADC_IOFF3(adcx) REG32((adcx) + 0x20U)
#define | ADC_WDHT(adcx) REG32((adcx) + 0x24U)
#define | ADC_WDLT(adcx) REG32((adcx) + 0x28U)
#define | ADC_RSQ0(adcx) REG32((adcx) + 0x2CU)
#define | ADC_RSQ1(adcx) REG32((adcx) + 0x30U)
#define | ADC_RSQ2(adcx) REG32((adcx) + 0x34U)
#define | ADC_ISQ(adcx) REG32((adcx) + 0x38U)
#define | ADC_IDATA0(adcx) REG32((adcx) + 0x3CU)
#define | ADC_IDATA1(adcx) REG32((adcx) + 0x40U)
#define | ADC_IDATA2(adcx) REG32((adcx) + 0x44U)
#define | ADC_IDATA3(adcx) REG32((adcx) + 0x48U)
#define | ADC_RDATA(adcx) REG32((adcx) + 0x4CU)
#define | ADC_STAT_WDE BIT(0)
#define | ADC_STAT_EOC BIT(1)
#define | ADC_STAT_EOIC BIT(2)
#define | ADC_STAT_STIC BIT(3)
#define | ADC_STAT_STRC BIT(4)
#define | ADC_CTL0_WDCHSEL BITS(0,4)
#define | ADC_CTL0_EOCIE BIT(5)
#define | ADC_CTL0_WDEIE BIT(6)
#define | ADC_CTL0_EOICIE BIT(7)
#define | ADC_CTL0_SM BIT(8)
#define | ADC_CTL0_WDSC BIT(9)
#define | ADC_CTL0_ICA BIT(10)
#define | ADC_CTL0_DISRC BIT(11)
#define | ADC_CTL0_DISIC BIT(12)
#define | ADC_CTL0_DISNUM BITS(13,15)
#define | ADC_CTL0_SYNCM BITS(16,19)
#define | ADC_CTL0_IWDEN BIT(22)
#define | ADC_CTL0_RWDEN BIT(23)
#define | ADC_CTL0_DRES BITS(24,25)
#define | ADC_CTL1_ADCON BIT(0)
#define | ADC_CTL1_CTN BIT(1)
#define | ADC_CTL1_CLB BIT(2)
#define | ADC_CTL1_RSTCLB BIT(3)
#define | ADC_CTL1_DMA BIT(8)
#define | ADC_CTL1_DAL BIT(11)
#define | ADC_CTL1_ETSIC BITS(12,14)
#define | ADC_CTL1_ETEIC BIT(15)
#define | ADC_CTL1_ETSRC BITS(17,19)
#define | ADC_CTL1_ETERC BIT(20)
#define | ADC_CTL1_SWICST BIT(21)
#define | ADC_CTL1_SWRCST BIT(22)
#define | ADC_CTL1_TSVREN BIT(23)
#define | ADC_SAMPTX_SPTN BITS(0,2)
#define | ADC_IOFFX_IOFF BITS(0,11)
#define | ADC_WDHT_WDHT BITS(0,11)
#define | ADC_WDLT_WDLT BITS(0,11)
#define | ADC_RSQX_RSQN BITS(0,4)
#define | ADC_RSQ0_RL BITS(20,23)
#define | ADC_ISQ_ISQN BITS(0,4)
#define | ADC_ISQ_IL BITS(20,21)
#define | ADC_IDATAX_IDATAN BITS(0,15)
#define | ADC_RDATA_RDATA BITS(0,15)
#define | ADC_RDATA_ADC1RDTR BITS(16,31)
#define | ADC_FLAG_WDE ADC_STAT_WDE
#define | ADC_FLAG_EOC ADC_STAT_EOC
#define | ADC_FLAG_EOIC ADC_STAT_EOIC
#define | ADC_FLAG_STIC ADC_STAT_STIC
#define | ADC_FLAG_STRC ADC_STAT_STRC
#define | CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13))
#define | ADC_SCAN_MODE ADC_CTL0_SM
#define | ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA
#define | CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
#define | ADC_MODE_FREE CTL0_SYNCM(0)
#define | ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1)
#define | ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2)
#define | ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3)
#define | ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4)
#define | ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5)
#define | ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6)
#define | ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7)
#define | ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8)
#define | ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9)
#define | ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define | ADC_DATAALIGN_LEFT ADC_CTL1_DAL
#define | ADC_CONTINUOUS_MODE ADC_CTL1_CTN
#define | CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
#define | ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0)
#define | ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1)
#define | ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2)
#define | ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3)
#define | ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4)
#define | ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5)
#define | ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6)
#define | ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6)
#define | ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7)
#define | ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0)
#define | ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1)
#define | ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2)
#define | ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3)
#define | ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4)
#define | ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5)
#define | ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6)
#define | CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12))
#define | ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0)
#define | ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1)
#define | ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2)
#define | ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3)
#define | ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4)
#define | ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5)
#define | ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6)
#define | ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6)
#define | ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7)
#define | ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0)
#define | ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1)
#define | ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2)
#define | ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3)
#define | ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4)
#define | ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5)
#define | ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6)
#define | SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define | ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0)
#define | ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1)
#define | ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2)
#define | ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3)
#define | ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4)
#define | ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5)
#define | ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6)
#define | ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7)
#define | IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
#define | WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
#define | WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
#define | RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
#define | ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
#define | ADC_REGULAR_CHANNEL ((uint8_t)0x01U)
#define | ADC_INSERTED_CHANNEL ((uint8_t)0x02U)
#define | ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U)
#define | ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U)
#define | ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U)
#define | ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U)
#define | ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U)
#define | ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U)
#define | ADC_CHANNEL_0 ((uint8_t)0x00U)
#define | ADC_CHANNEL_1 ((uint8_t)0x01U)
#define | ADC_CHANNEL_2 ((uint8_t)0x02U)
#define | ADC_CHANNEL_3 ((uint8_t)0x03U)
#define | ADC_CHANNEL_4 ((uint8_t)0x04U)
#define | ADC_CHANNEL_5 ((uint8_t)0x05U)
#define | ADC_CHANNEL_6 ((uint8_t)0x06U)
#define | ADC_CHANNEL_7 ((uint8_t)0x07U)
#define | ADC_CHANNEL_8 ((uint8_t)0x08U)
#define | ADC_CHANNEL_9 ((uint8_t)0x09U)
#define | ADC_CHANNEL_10 ((uint8_t)0x0AU)
#define | ADC_CHANNEL_11 ((uint8_t)0x0BU)
#define | ADC_CHANNEL_12 ((uint8_t)0x0CU)
#define | ADC_CHANNEL_13 ((uint8_t)0x0DU)
#define | ADC_CHANNEL_14 ((uint8_t)0x0EU)
#define | ADC_CHANNEL_15 ((uint8_t)0x0FU)
#define | ADC_CHANNEL_16 ((uint8_t)0x10U)
#define | ADC_CHANNEL_17 ((uint8_t)0x11U)
#define | ADC_INT_WDE ADC_STAT_WDE
#define | ADC_INT_EOC ADC_STAT_EOC
#define | ADC_INT_EOIC ADC_STAT_EOIC

Functions

void | adc_deinit (uint32_t adc_periph)
reset ADC More...
void | adc_enable (uint32_t adc_periph)
enable ADC interface More...
void | adc_disable (uint32_t adc_periph)
disable ADC interface More...
void | adc_calibration_enable (uint32_t adc_periph)
ADC calibration and reset calibration. More...
void | adc_dma_mode_enable (uint32_t adc_periph)
enable DMA request More...
void | adc_dma_mode_disable (uint32_t adc_periph)
disable DMA request More...
void | adc_tempsensor_vrefint_enable (void)
enable the temperature sensor and Vrefint channel More...
void | adc_tempsensor_vrefint_disable (void)
disable the temperature sensor and Vrefint channel More...
void | adc_discontinuous_mode_config (uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
configure ADC discontinuous mode More...
void | adc_mode_config (uint32_t mode)
configure the ADC sync mode More...
void | adc_special_function_config (uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
enable or disable ADC special function More...
void | adc_data_alignment_config (uint32_t adc_periph, uint32_t data_alignment)
configure ADC data alignment More...
void | adc_channel_length_config (uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
configure the length of regular channel group or inserted channel group More...
void | adc_regular_channel_config (uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
configure ADC regular channel More...
void | adc_inserted_channel_config (uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
configure ADC inserted channel More...
void | adc_inserted_channel_offset_config (uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
configure ADC inserted channel offset More...
void | adc_external_trigger_config (uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
enable ADC external trigger More...
void | adc_external_trigger_source_config (uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
configure ADC external trigger source More...
void | adc_software_trigger_enable (uint32_t adc_periph, uint8_t adc_channel_group)
enable ADC software trigger More...
FlagStatus | adc_regular_software_startconv_flag_get (uint32_t adc_periph)
get the bit state of ADCx software start conversion More...
FlagStatus | adc_inserted_software_startconv_flag_get (uint32_t adc_periph)
get the bit state of ADCx software inserted channel start conversion More...
uint16_t | adc_regular_data_read (uint32_t adc_periph)
read ADC regular group data register More...
uint16_t | adc_inserted_data_read (uint32_t adc_periph, uint8_t inserted_channel)
read ADC inserted group data register More...
uint32_t | adc_sync_mode_convert_value_read (void)
read the last ADC0 and ADC1 conversion result data in sync mode More...
FlagStatus | adc_flag_get (uint32_t adc_periph, uint32_t adc_flag)
get the ADC flag bits More...
void | adc_flag_clear (uint32_t adc_periph, uint32_t adc_flag)
clear the ADC flag bits More...
FlagStatus | adc_interrupt_flag_get (uint32_t adc_periph, uint32_t adc_interrupt)
get the ADC interrupt bits More...
void | adc_interrupt_flag_clear (uint32_t adc_periph, uint32_t adc_interrupt)
clear the ADC flag More...
void | adc_interrupt_enable (uint32_t adc_periph, uint32_t adc_interrupt)
enable ADC interrupt More...
void | adc_interrupt_disable (uint32_t adc_periph, uint32_t adc_interrupt)
disable ADC interrupt More...
void | adc_watchdog_single_channel_enable (uint32_t adc_periph, uint8_t adc_channel)
configure ADC analog watchdog single channel More...
void | adc_watchdog_group_channel_enable (uint32_t adc_periph, uint8_t adc_channel_group)
configure ADC analog watchdog group channel More...
void | adc_watchdog_disable (uint32_t adc_periph)
disable ADC analog watchdog More...
void | adc_watchdog_threshold_config (uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
configure ADC analog watchdog threshold More...

Detailed Description

definitions for the ADC

Definition in file gd32f10x_adc.h.

Macro Definition Documentation

#define ADC0 ADC_BASE

Definition at line 19 of file gd32f10x_adc.h.

#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7)

software trigger

Definition at line 173 of file gd32f10x_adc.h.

#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7)

software trigger

Definition at line 154 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6)

external interrupt line 15

Definition at line 171 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1)

timer 0 CC3 event select

Definition at line 166 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0)

timer 0 TRGO event select

Definition at line 165 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3)

timer 1 CC0 event select

Definition at line 168 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2)

timer 1 TRGO event select

Definition at line 167 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4)

timer 2 CC3 event select

Definition at line 169 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5)

timer 3 TRGO event select

Definition at line 170 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6)

timer 7 CC3 event select

Definition at line 172 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6)

external interrupt line 11

Definition at line 153 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0)

timer 0 CC0 event select

Definition at line 146 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1)

timer 0 CC1 event select

Definition at line 147 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2)

timer 0 CC2 event select

Definition at line 148 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3)

timer 1 CC1 event select

Definition at line 149 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4)

timer 2 TRGO event select

Definition at line 150 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5)

timer 3 CC3 event select

Definition at line 151 of file gd32f10x_adc.h.

#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6)

timer 7 TRGO event select

Definition at line 152 of file gd32f10x_adc.h.

#define ADC1 (ADC_BASE + 0x400U)

Definition at line 20 of file gd32f10x_adc.h.

#define ADC2 (ADC_BASE + 0x1800U)

Definition at line 21 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1)

timer 0 CC3 event select

Definition at line 176 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0)

timer 0 TRGO event select

Definition at line 175 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2)

timer 3 CC2 event select

Definition at line 177 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6)

timer 4 CC3 event select

Definition at line 181 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5)

timer 4 TRGO event select

Definition at line 180 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3)

timer 7 CC1 event select

Definition at line 178 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4)

timer 7 CC3 event select

Definition at line 179 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2)

timer 0 CC2 event select

Definition at line 158 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1)

timer 1 CC2 event select

Definition at line 157 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0)

timer 2 CC0 event select

Definition at line 156 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5)

timer 4 CC0 event select

Definition at line 161 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6)

timer 4 CC2 event select

Definition at line 162 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3)

timer 7 CC0 event select

Definition at line 159 of file gd32f10x_adc.h.

#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4)

timer 7 TRGO event select

Definition at line 160 of file gd32f10x_adc.h.

#define ADC_CHANNEL_0 ((uint8_t)0x00U)

ADC channel 0

Definition at line 223 of file gd32f10x_adc.h.

#define ADC_CHANNEL_1 ((uint8_t)0x01U)

ADC channel 1

Definition at line 224 of file gd32f10x_adc.h.

#define ADC_CHANNEL_10 ((uint8_t)0x0AU)

ADC channel 10

Definition at line 233 of file gd32f10x_adc.h.

#define ADC_CHANNEL_11 ((uint8_t)0x0BU)

ADC channel 11

Definition at line 234 of file gd32f10x_adc.h.

#define ADC_CHANNEL_12 ((uint8_t)0x0CU)

ADC channel 12

Definition at line 235 of file gd32f10x_adc.h.

#define ADC_CHANNEL_13 ((uint8_t)0x0DU)

ADC channel 13

Definition at line 236 of file gd32f10x_adc.h.

#define ADC_CHANNEL_14 ((uint8_t)0x0EU)

ADC channel 14

Definition at line 237 of file gd32f10x_adc.h.

#define ADC_CHANNEL_15 ((uint8_t)0x0FU)

ADC channel 15

Definition at line 238 of file gd32f10x_adc.h.

#define ADC_CHANNEL_16 ((uint8_t)0x10U)

ADC channel 16

Definition at line 239 of file gd32f10x_adc.h.

#define ADC_CHANNEL_17 ((uint8_t)0x11U)

ADC channel 17

Definition at line 240 of file gd32f10x_adc.h.

#define ADC_CHANNEL_2 ((uint8_t)0x02U)

ADC channel 2

Definition at line 225 of file gd32f10x_adc.h.

#define ADC_CHANNEL_3 ((uint8_t)0x03U)

ADC channel 3

Definition at line 226 of file gd32f10x_adc.h.

#define ADC_CHANNEL_4 ((uint8_t)0x04U)

ADC channel 4

Definition at line 227 of file gd32f10x_adc.h.

#define ADC_CHANNEL_5 ((uint8_t)0x05U)

ADC channel 5

Definition at line 228 of file gd32f10x_adc.h.

#define ADC_CHANNEL_6 ((uint8_t)0x06U)

ADC channel 6

Definition at line 229 of file gd32f10x_adc.h.

#define ADC_CHANNEL_7 ((uint8_t)0x07U)

ADC channel 7

Definition at line 230 of file gd32f10x_adc.h.

#define ADC_CHANNEL_8 ((uint8_t)0x08U)

ADC channel 8

Definition at line 231 of file gd32f10x_adc.h.

#define ADC_CHANNEL_9 ((uint8_t)0x09U)

ADC channel 9

Definition at line 232 of file gd32f10x_adc.h.

#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U)

disable discontinuous mode of regular & inserted channel

Definition at line 214 of file gd32f10x_adc.h.

#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN

continuous mode

Definition at line 143 of file gd32f10x_adc.h.

#define ADC_CTL0 ( adcx ) REG32((adcx) + 0x04U)

ADC control register 0

Definition at line 25 of file gd32f10x_adc.h.

#define ADC_CTL0_DISIC BIT(12)

discontinuous mode on inserted channels

Definition at line 62 of file gd32f10x_adc.h.

#define ADC_CTL0_DISNUM BITS(13,15)

discontinuous mode channel count

Definition at line 63 of file gd32f10x_adc.h.

#define ADC_CTL0_DISRC BIT(11)

discontinuous mode on regular channels

Definition at line 61 of file gd32f10x_adc.h.

#define ADC_CTL0_DRES BITS(24,25)

ADC data resolution

Definition at line 67 of file gd32f10x_adc.h.

#define ADC_CTL0_EOCIE BIT(5)

interrupt enable for EOC

Definition at line 55 of file gd32f10x_adc.h.

#define ADC_CTL0_EOICIE BIT(7)

interrupt enable for inserted channels

Definition at line 57 of file gd32f10x_adc.h.

#define ADC_CTL0_ICA BIT(10)

automatic inserted group conversion

Definition at line 60 of file gd32f10x_adc.h.

#define ADC_CTL0_IWDEN BIT(22)

analog watchdog enable on inserted channels

Definition at line 65 of file gd32f10x_adc.h.

#define ADC_CTL0_RWDEN BIT(23)

analog watchdog enable on regular channels

Definition at line 66 of file gd32f10x_adc.h.

#define ADC_CTL0_SM BIT(8)

scan mode

Definition at line 58 of file gd32f10x_adc.h.

#define ADC_CTL0_SYNCM BITS(16,19)

sync mode selection

Definition at line 64 of file gd32f10x_adc.h.

#define ADC_CTL0_WDCHSEL BITS(0,4)

analog watchdog channel select bits

Definition at line 54 of file gd32f10x_adc.h.

#define ADC_CTL0_WDEIE BIT(6)

analog watchdog interrupt enable

Definition at line 56 of file gd32f10x_adc.h.

#define ADC_CTL0_WDSC BIT(9)

when in scan mode, analog watchdog is effective on a single channel

Definition at line 59 of file gd32f10x_adc.h.

#define ADC_CTL1 ( adcx ) REG32((adcx) + 0x08U)

ADC control register 1

Definition at line 26 of file gd32f10x_adc.h.

#define ADC_CTL1_ADCON BIT(0)

ADC converter on

Definition at line 70 of file gd32f10x_adc.h.

#define ADC_CTL1_CLB BIT(2)

ADC calibration

Definition at line 72 of file gd32f10x_adc.h.

#define ADC_CTL1_CTN BIT(1)

continuous conversion

Definition at line 71 of file gd32f10x_adc.h.

#define ADC_CTL1_DAL BIT(11)

data alignment

Definition at line 75 of file gd32f10x_adc.h.

#define ADC_CTL1_DMA BIT(8)

direct memory access mode

Definition at line 74 of file gd32f10x_adc.h.

#define ADC_CTL1_ETEIC BIT(15)

external trigger enable for inserted channel

Definition at line 77 of file gd32f10x_adc.h.

#define ADC_CTL1_ETERC BIT(20)

external trigger conversion mode for inserted channels

Definition at line 79 of file gd32f10x_adc.h.

#define ADC_CTL1_ETSIC BITS(12,14)

external trigger select for inserted channel

Definition at line 76 of file gd32f10x_adc.h.

#define ADC_CTL1_ETSRC BITS(17,19)

external trigger select for regular channel

Definition at line 78 of file gd32f10x_adc.h.

#define ADC_CTL1_RSTCLB BIT(3)

reset calibration

Definition at line 73 of file gd32f10x_adc.h.

#define ADC_CTL1_SWICST BIT(21)

start on inserted channel

Definition at line 80 of file gd32f10x_adc.h.

#define ADC_CTL1_SWRCST BIT(22)

start on regular channel

Definition at line 81 of file gd32f10x_adc.h.

#define ADC_CTL1_TSVREN BIT(23)

channel 16 and 17 enable of ADC0

Definition at line 82 of file gd32f10x_adc.h.

#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL

MSB alignment

Definition at line 141 of file gd32f10x_adc.h.

#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)

LSB alignment

Definition at line 140 of file gd32f10x_adc.h.

#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5)

ADC0 and ADC1 work in inserted parallel mode only

Definition at line 133 of file gd32f10x_adc.h.

#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3)

ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode

Definition at line 131 of file gd32f10x_adc.h.

#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4)

ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode

Definition at line 132 of file gd32f10x_adc.h.

#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9)

ADC0 and ADC1 work in trigger rotation mode only

Definition at line 137 of file gd32f10x_adc.h.

#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7)

ADC0 and ADC1 work in follow-up fast mode only

Definition at line 135 of file gd32f10x_adc.h.

#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8)

ADC0 and ADC1 work in follow-up slow mode only

Definition at line 136 of file gd32f10x_adc.h.

#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6)

ADC0 and ADC1 work in regular parallel mode only

Definition at line 134 of file gd32f10x_adc.h.

#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1)

ADC0 and ADC1 work in combined regular parallel + inserted parallel mode

Definition at line 129 of file gd32f10x_adc.h.

#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2)

ADC0 and ADC1 work in combined regular parallel + trigger rotation mode

Definition at line 130 of file gd32f10x_adc.h.

#define ADC_FLAG_EOC ADC_STAT_EOC

end of conversion

Definition at line 115 of file gd32f10x_adc.h.

#define ADC_FLAG_EOIC ADC_STAT_EOIC

inserted channel end of conversion

Definition at line 116 of file gd32f10x_adc.h.

#define ADC_FLAG_STIC ADC_STAT_STIC

inserted channel start flag

Definition at line 117 of file gd32f10x_adc.h.

#define ADC_FLAG_STRC ADC_STAT_STRC

regular channel start flag

Definition at line 118 of file gd32f10x_adc.h.

#define ADC_FLAG_WDE ADC_STAT_WDE

analog watchdog event flag

Definition at line 114 of file gd32f10x_adc.h.

#define ADC_IDATA0 ( adcx ) REG32((adcx) + 0x3CU)

ADC inserted data register 0

Definition at line 39 of file gd32f10x_adc.h.

#define ADC_IDATA1 ( adcx ) REG32((adcx) + 0x40U)

ADC inserted data register 1

Definition at line 40 of file gd32f10x_adc.h.

#define ADC_IDATA2 ( adcx ) REG32((adcx) + 0x44U)

ADC inserted data register 2

Definition at line 41 of file gd32f10x_adc.h.

#define ADC_IDATA3 ( adcx ) REG32((adcx) + 0x48U)

ADC inserted data register 3

Definition at line 42 of file gd32f10x_adc.h.

#define ADC_IDATAX_IDATAN BITS(0,15)

inserted data x

Definition at line 105 of file gd32f10x_adc.h.

#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U)

adc inserted channel group

Definition at line 211 of file gd32f10x_adc.h.

#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U)

adc inserted channel 0

Definition at line 217 of file gd32f10x_adc.h.

#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U)

adc inserted channel 1

Definition at line 218 of file gd32f10x_adc.h.

#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U)

adc inserted channel 2

Definition at line 219 of file gd32f10x_adc.h.

#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U)

adc inserted channel 3

Definition at line 220 of file gd32f10x_adc.h.

#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA

inserted channel group convert automatically

Definition at line 125 of file gd32f10x_adc.h.

#define ADC_INT_EOC ADC_STAT_EOC

end of group conversion interrupt

Definition at line 244 of file gd32f10x_adc.h.

#define ADC_INT_EOIC ADC_STAT_EOIC

end of inserted group conversion interrupt

Definition at line 245 of file gd32f10x_adc.h.

#define ADC_INT_WDE ADC_STAT_WDE

analog watchdog event interrupt

Definition at line 243 of file gd32f10x_adc.h.

#define ADC_IOFF0 ( adcx ) REG32((adcx) + 0x14U)

ADC inserted channel data offset register 0

Definition at line 29 of file gd32f10x_adc.h.

#define ADC_IOFF1 ( adcx ) REG32((adcx) + 0x18U)

ADC inserted channel data offset register 1

Definition at line 30 of file gd32f10x_adc.h.

#define ADC_IOFF2 ( adcx ) REG32((adcx) + 0x1CU)

ADC inserted channel data offset register 2

Definition at line 31 of file gd32f10x_adc.h.

#define ADC_IOFF3 ( adcx ) REG32((adcx) + 0x20U)

ADC inserted channel data offset register 3

Definition at line 32 of file gd32f10x_adc.h.

#define ADC_IOFFX_IOFF BITS(0,11)

data offset for inserted channel x

Definition at line 88 of file gd32f10x_adc.h.

#define ADC_ISQ ( adcx ) REG32((adcx) + 0x38U)

ADC inserted sequence register

Definition at line 38 of file gd32f10x_adc.h.

#define ADC_ISQ_IL BITS(20,21)

inserted sequence length

Definition at line 102 of file gd32f10x_adc.h.

#define ADC_ISQ_ISQN BITS(0,4)

x conversion in regular sequence

Definition at line 101 of file gd32f10x_adc.h.

#define ADC_MODE_FREE CTL0_SYNCM(0)

all the ADCs work independently

Definition at line 128 of file gd32f10x_adc.h.

#define ADC_RDATA ( adcx ) REG32((adcx) + 0x4CU)

ADC regular data register

Definition at line 43 of file gd32f10x_adc.h.

#define ADC_RDATA_ADC1RDTR BITS(16,31)

ADC1 regular channel data

Definition at line 109 of file gd32f10x_adc.h.

#define ADC_RDATA_RDATA BITS(0,15)

regular data

Definition at line 108 of file gd32f10x_adc.h.

#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U)

adc regular channel group

Definition at line 210 of file gd32f10x_adc.h.

#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U)

both regular and inserted channel group

Definition at line 212 of file gd32f10x_adc.h.

#define ADC_RSQ0 ( adcx ) REG32((adcx) + 0x2CU)

ADC regular sequence register 0

Definition at line 35 of file gd32f10x_adc.h.

#define ADC_RSQ0_RL BITS(20,23)

regular channel sequence length

Definition at line 98 of file gd32f10x_adc.h.

#define ADC_RSQ1 ( adcx ) REG32((adcx) + 0x30U)

ADC regular sequence register 1

Definition at line 36 of file gd32f10x_adc.h.

#define ADC_RSQ2 ( adcx ) REG32((adcx) + 0x34U)

ADC regular sequence register 2

Definition at line 37 of file gd32f10x_adc.h.

#define ADC_RSQX_RSQN BITS(0,4)

x conversion in regular sequence

Definition at line 97 of file gd32f10x_adc.h.

#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2)

13.5 sampling cycles

Definition at line 187 of file gd32f10x_adc.h.

#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0)

1.5 sampling cycles

Definition at line 185 of file gd32f10x_adc.h.

#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7)

239.5 sampling cycles

Definition at line 192 of file gd32f10x_adc.h.

#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3)

28.5 sampling cycles

Definition at line 188 of file gd32f10x_adc.h.

#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4)

41.5 sampling cycles

Definition at line 189 of file gd32f10x_adc.h.

#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5)

55.5 sampling cycles

Definition at line 190 of file gd32f10x_adc.h.

#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6)

71.5 sampling cycles

Definition at line 191 of file gd32f10x_adc.h.

#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1)

7.5 sampling cycles

Definition at line 186 of file gd32f10x_adc.h.

#define ADC_SAMPT0 ( adcx ) REG32((adcx) + 0x0CU)

ADC sampling time register 0

Definition at line 27 of file gd32f10x_adc.h.

#define ADC_SAMPT1 ( adcx ) REG32((adcx) + 0x10U)

ADC sampling time register 1

Definition at line 28 of file gd32f10x_adc.h.

#define ADC_SAMPTX_SPTN BITS(0,2)

channel x sample time selection

Definition at line 85 of file gd32f10x_adc.h.

#define ADC_SCAN_MODE ADC_CTL0_SM

scan mode

Definition at line 123 of file gd32f10x_adc.h.

#define ADC_STAT ( adcx ) REG32((adcx) + 0x00U)

ADC status register

Definition at line 24 of file gd32f10x_adc.h.

#define ADC_STAT_EOC BIT(1)

end of conversion

Definition at line 48 of file gd32f10x_adc.h.

#define ADC_STAT_EOIC BIT(2)

inserted channel end of conversion

Definition at line 49 of file gd32f10x_adc.h.

#define ADC_STAT_STIC BIT(3)

inserted channel start flag

Definition at line 50 of file gd32f10x_adc.h.

#define ADC_STAT_STRC BIT(4)

regular channel start flag

Definition at line 51 of file gd32f10x_adc.h.

#define ADC_STAT_WDE BIT(0)

analog watchdog event flag

Definition at line 47 of file gd32f10x_adc.h.

#define ADC_WDHT ( adcx ) REG32((adcx) + 0x24U)

ADC watchdog high threshold register

Definition at line 33 of file gd32f10x_adc.h.

#define ADC_WDHT_WDHT BITS(0,11)

analog watchdog high threshold

Definition at line 91 of file gd32f10x_adc.h.

#define ADC_WDLT ( adcx ) REG32((adcx) + 0x28U)

ADC watchdog low threshold register

Definition at line 34 of file gd32f10x_adc.h.

#define ADC_WDLT_WDLT BITS(0,11)

analog watchdog low threshold

Definition at line 94 of file gd32f10x_adc.h.

#define CTL0_DISNUM ( regval ) (BITS(13,15) & ((uint32_t)(regval) << 13))

write value to ADC_CTL0_DISNUM bit field

Definition at line 121 of file gd32f10x_adc.h.

#define CTL0_SYNCM ( regval ) (BITS(16,19) & ((uint32_t)(regval) << 16))

write value to ADC_CTL0_SYNCM bit field

Definition at line 127 of file gd32f10x_adc.h.

#define CTL1_ETSIC ( regval ) (BITS(12,14) & ((uint32_t)(regval) << 12))

write value to ADC_CTL1_ETSIC bit field

Definition at line 164 of file gd32f10x_adc.h.

#define CTL1_ETSRC ( regval ) (BITS(17,19) & ((uint32_t)(regval) << 17))

write value to ADC_CTL1_ETSRC bit field

Definition at line 145 of file gd32f10x_adc.h.

#define IOFFX_IOFF ( regval ) (BITS(0,11) & ((uint32_t)(regval) << 0))

write value to ADC_IOFFX_IOFF bit field

Definition at line 195 of file gd32f10x_adc.h.

#define ISQ_IL ( regval ) (BITS(20,21) & ((uint32_t)(regval) << 20))

write value to ADC_ISQ_IL bit field

Definition at line 207 of file gd32f10x_adc.h.

#define RSQ0_RL ( regval ) (BITS(20,23) & ((uint32_t)(regval) << 20))

write value to ADC_RSQ0_RL bit field

Definition at line 204 of file gd32f10x_adc.h.

#define SAMPTX_SPT ( regval ) (BITS(0,2) & ((uint32_t)(regval) << 0))

write value to ADC_SAMPTX_SPT bit field

Definition at line 184 of file gd32f10x_adc.h.

#define WDHT_WDHT ( regval ) (BITS(0,11) & ((uint32_t)(regval) << 0))

write value to ADC_WDHT_WDHT bit field

Definition at line 198 of file gd32f10x_adc.h.

#define WDLT_WDLT ( regval ) (BITS(0,11) & ((uint32_t)(regval) << 0))

write value to ADC_WDLT_WDLT bit field

Definition at line 201 of file gd32f10x_adc.h.

Function Documentation

void adc_calibration_enable ( uint32_t adc_periph )

ADC calibration and reset calibration.

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 77 of file gd32f10x_adc.c.

78 {
79 /* reset the selected ADC1 calibration registers */
80 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
81 /* check the RSTCLB bit state */
82 while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
83 }
84 /* enable ADC calibration process */
85 ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
86 /* check the CLB bit state */
87 while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
88 }
89 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_RSTCLB
#define ADC_CTL1_RSTCLB
Definition: gd32f10x_adc.h:73
ADC_CTL1_CLB
#define ADC_CTL1_CLB
Definition: gd32f10x_adc.h:72
void adc_channel_length_config | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group,
 |  | uint32_t | length
 | ) |  |

configure the length of regular channel group or inserted channel group

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] | length | the length of the channel regular channel 1-16 inserted channel 1-4
[out] | none
Return values
none

Definition at line 268 of file gd32f10x_adc.c.

269 {
270 switch(adc_channel_group){
271 case ADC_REGULAR_CHANNEL:
272 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
273 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U));
274
275 break;
276 case ADC_INSERTED_CHANNEL:
277 ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
278 ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-1U));
279
280 break;
281 default:
282 break;
283 }
284 }
RSQ0_RL
#define RSQ0_RL(regval)
Definition: gd32f10x_adc.h:204
ADC_RSQ0_RL
#define ADC_RSQ0_RL
Definition: gd32f10x_adc.h:98
ADC_ISQ_IL
#define ADC_ISQ_IL
Definition: gd32f10x_adc.h:102
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_ISQ
#define ADC_ISQ(adcx)
Definition: gd32f10x_adc.h:38
ISQ_IL
#define ISQ_IL(regval)
Definition: gd32f10x_adc.h:207
ADC_RSQ0
#define ADC_RSQ0(adcx)
Definition: gd32f10x_adc.h:35
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_data_alignment_config | ( | uint32_t | adc_periph,
 |  | uint32_t | data_alignment
 | ) |  |

configure ADC data alignment

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] data_alignment data alignment select only one parameter can be selected
  • ADC_DATAALIGN_RIGHT: LSB alignment
  • ADC_DATAALIGN_LEFT: MSB alignment
[out] | none
Return values
none

Definition at line 245 of file gd32f10x_adc.c.

246 {
247 if(ADC_DATAALIGN_RIGHT != data_alignment){
248 ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
249 }else{
250 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
251 }
252 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_DAL
#define ADC_CTL1_DAL
Definition: gd32f10x_adc.h:75
ADC_DATAALIGN_RIGHT
#define ADC_DATAALIGN_RIGHT
Definition: gd32f10x_adc.h:140
void adc_deinit ( uint32_t adc_periph )

reset ADC

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 22 of file gd32f10x_adc.c.

23 {
24 switch(adc_periph){
25 case ADC0:
26 rcu_periph_reset_enable(RCU_ADC0RST);
27 rcu_periph_reset_disable(RCU_ADC0RST);
28 break;
29 case ADC1:
30 rcu_periph_reset_enable(RCU_ADC1RST);
31 rcu_periph_reset_disable(RCU_ADC1RST);
32 break;
33 #ifndef GD32F10X_CL
34 case ADC2:
35 rcu_periph_reset_enable(RCU_ADC2RST);
36 rcu_periph_reset_disable(RCU_ADC2RST);
37 break;
38 #endif /* GD32F10X_CL */
39 default:
40 break;
41 }
42 }
ADC1
#define ADC1
Definition: gd32f10x_adc.h:20
RCU_ADC0RST
Definition: gd32f10x_rcu.h:485
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
RCU_ADC1RST
Definition: gd32f10x_rcu.h:486
ADC2
#define ADC2
Definition: gd32f10x_adc.h:21
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_disable ( uint32_t adc_periph )

disable ADC interface

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 65 of file gd32f10x_adc.c.

66 {
67 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
68 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f10x_adc.h:70
void adc_discontinuous_mode_config | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group,
 |  | uint8_t | length
 | ) |  |

configure ADC discontinuous mode

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group only one among these parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
  • ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
[in] | length | number of conversions in discontinuous mode,the number can be 1..8 for regular channel ,the number has no effect for inserted channel
[out] | none
Return values
none

Definition at line 153 of file gd32f10x_adc.c.

154 {
155 ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC ));
156 switch(adc_channel_group){
157 case ADC_REGULAR_CHANNEL:
158 /* config the number of conversions in discontinuous mode */
159 ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
160 ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U));
161
162 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
163 break;
164 case ADC_INSERTED_CHANNEL:
165 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
166 break;
167 case ADC_CHANNEL_DISCON_DISABLE:
168 default:
169 break;
170 }
171 }
ADC_CTL0_DISIC
#define ADC_CTL0_DISIC
Definition: gd32f10x_adc.h:62
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL0_DISRC
#define ADC_CTL0_DISRC
Definition: gd32f10x_adc.h:61
ADC_CTL0_DISNUM
#define ADC_CTL0_DISNUM
Definition: gd32f10x_adc.h:63
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_CHANNEL_DISCON_DISABLE
#define ADC_CHANNEL_DISCON_DISABLE
Definition: gd32f10x_adc.h:214
CTL0_DISNUM
#define CTL0_DISNUM(regval)
Definition: gd32f10x_adc.h:121
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_dma_mode_disable ( uint32_t adc_periph )

disable DMA request

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 110 of file gd32f10x_adc.c.

111 {
112 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
113 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f10x_adc.h:74
void adc_dma_mode_enable ( uint32_t adc_periph )

enable DMA request

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 98 of file gd32f10x_adc.c.

99 {
100 ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
101 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f10x_adc.h:74
void adc_enable ( uint32_t adc_periph )

enable ADC interface

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 51 of file gd32f10x_adc.c.

52 {
53 if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
54 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
55 }
56 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f10x_adc.h:70
void adc_external_trigger_config | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group,
 |  | ControlStatus | newvalue
 | ) |  |

enable ADC external trigger

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group one or more parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 435 of file gd32f10x_adc.c.

436 {
437 if(newvalue){
438 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
439 ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
440 }
441 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
442 ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
443 }
444 }else{
445 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
446 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
447 }
448 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
449 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
450 }
451 }
452 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL1_ETEIC
#define ADC_CTL1_ETEIC
Definition: gd32f10x_adc.h:77
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
ADC_CTL1_ETERC
#define ADC_CTL1_ETERC
Definition: gd32f10x_adc.h:79
void adc_external_trigger_source_config | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group,
 |  | uint32_t | external_trigger_source
 | ) |  |

configure ADC external trigger source

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] external_trigger_source regular or inserted group trigger source only one parameter can be selected for regular channel:
  • ADC0_1_EXTTRIG_REGULAR_T0_CH0: timer 0 CC0 event select
  • ADC0_1_EXTTRIG_REGULAR_T0_CH1: timer 0 CC1 event select
  • ADC0_1_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select
  • ADC0_1_EXTTRIG_REGULAR_T1_CH1: timer 1 CC1 event select
  • ADC0_1_EXTTRIG_REGULAR_T2_TRGO: timer 2 TRGO event select
  • ADC0_1_EXTTRIG_REGULAR_T3_CH3: timer 3 CC3 event select
  • ADC0_1_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select
  • ADC0_1_EXTTRIG_REGULAR_EXTI_11 : external interrupt line 11
  • ADC2_EXTTRIG_REGULAR_T2_CH0: timer 2 CC0 event select
  • ADC2_EXTTRIG_REGULAR_T1_CH2: timer 1 CC2 event select
  • ADC2_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select
  • ADC2_EXTTRIG_REGULAR_T7_CH0: timer 7 CC0 event select
  • ADC2_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select
  • ADC2_EXTTRIG_REGULAR_T4_CH0: timer 4 CC0 event select
  • ADC2_EXTTRIG_REGULAR_T4_CH2: timer 4 CC2 event select
  • ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger for inserted channel:
  • ADC0_1_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select
  • ADC0_1_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select
  • ADC0_1_EXTTRIG_INSERTED_T1_TRGO: timer 1 TRGO event select
  • ADC0_1_EXTTRIG_INSERTED_T1_CH0: timer 1 CC0 event select
  • ADC0_1_EXTTRIG_INSERTED_T2_CH3: timer 2 CC3 event select
  • ADC0_1_EXTTRIG_INSERTED_T3_TRGO: timer 3 TRGO event select
  • ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
  • ADC0_1_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select
  • ADC2_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select
  • ADC2_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select
  • ADC2_EXTTRIG_INSERTED_T3_CH2: timer 3 CC2 event select
  • ADC2_EXTTRIG_INSERTED_T7_CH1: timer 7 CC1 event select
  • ADC2_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select
  • ADC2_EXTTRIG_INSERTED_T4_TRGO: timer 4 TRGO event select
  • ADC2_EXTTRIG_INSERTED_T4_CH3: timer 4 CC3 event select
  • ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger
[out] | none
Return values
none

Definition at line 501 of file gd32f10x_adc.c.

502 {
503 switch(adc_channel_group){
504 case ADC_REGULAR_CHANNEL:
505 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
506 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
507 break;
508 case ADC_INSERTED_CHANNEL:
509 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
510 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
511 break;
512 default:
513 break;
514 }
515 }
ADC_CTL1_ETSIC
#define ADC_CTL1_ETSIC
Definition: gd32f10x_adc.h:76
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL1_ETSRC
#define ADC_CTL1_ETSRC
Definition: gd32f10x_adc.h:78
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_flag_clear | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_flag
 | ) |  |

clear the ADC flag bits

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_flag the adc flag bits one or more parameters can be selected
  • ADC_FLAG_WDE: analog watchdog event flag
  • ADC_FLAG_EOC: end of group conversion flag
  • ADC_FLAG_EOIC: end of inserted group conversion flag
  • ADC_FLAG_STIC: start flag of inserted channel group
  • ADC_FLAG_STRC: start flag of regular channel group
[out] | none
Return values
none

Definition at line 669 of file gd32f10x_adc.c.

670 {
671 ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
672 }
ADC_STAT
#define ADC_STAT(adcx)
Definition: gd32f10x_adc.h:24
FlagStatus adc_flag_get | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_flag
 | ) |  |

get the ADC flag bits

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_flag the adc flag bits only one parameter can be selected
  • ADC_FLAG_WDE: analog watchdog event flag
  • ADC_FLAG_EOC: end of group conversion flag
  • ADC_FLAG_EOIC: end of inserted group conversion flag
  • ADC_FLAG_STIC: start flag of inserted channel group
  • ADC_FLAG_STRC: start flag of regular channel group
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 646 of file gd32f10x_adc.c.

647 {
648 FlagStatus reval = RESET;
649 if(ADC_STAT(adc_periph) & adc_flag){
650 reval = SET;
651 }
652 return reval;
653 }
ADC_STAT
#define ADC_STAT(adcx)
Definition: gd32f10x_adc.h:24
void adc_inserted_channel_config | ( | uint32_t | adc_periph,
 |  | uint8_t | rank,
 |  | uint8_t | adc_channel,
 |  | uint32_t | sample_time
 | ) |  |

configure ADC inserted channel

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] | rank | the inserted group sequencer rank,this parameter must be between 0 to 3
[in] adc_channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
[in] sample_time The sample time value only one parameter can be selected
  • ADC_SAMPLETIME_1POINT5: 1.5 cycles
  • ADC_SAMPLETIME_7POINT5: 7.5 cycles
  • ADC_SAMPLETIME_13POINT5: 13.5 cycles
  • ADC_SAMPLETIME_28POINT5: 28.5 cycles
  • ADC_SAMPLETIME_41POINT5: 41.5 cycles
  • ADC_SAMPLETIME_55POINT5: 55.5 cycles
  • ADC_SAMPLETIME_71POINT5: 71.5 cycles
  • ADC_SAMPLETIME_239POINT5: 239.5 cycles
[out] | none
Return values
none

Definition at line 366 of file gd32f10x_adc.c.

367 {
368 uint8_t inserted_length;
369 uint32_t isq,sampt;
370
371 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
372
373 isq = ADC_ISQ(adc_periph);
374 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U-(inserted_length-rank)*5U)));
375 isq |= ((uint32_t)adc_channel << (15U-(inserted_length-rank)*5U));
376 ADC_ISQ(adc_periph) = isq;
377
378 /* ADC sampling time config */
379 if(adc_channel < 10U){
380 sampt = ADC_SAMPT1(adc_periph);
381 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
382 sampt |= (uint32_t) sample_time << (3U*adc_channel);
383 ADC_SAMPT1(adc_periph) = sampt;
384 }else if(adc_channel < 18U){
385 sampt = ADC_SAMPT0(adc_periph);
386 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
387 sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U)));
388 ADC_SAMPT0(adc_periph) = sampt;
389 }else{
390 }
391 }
ADC_SAMPT0
#define ADC_SAMPT0(adcx)
Definition: gd32f10x_adc.h:27
ADC_ISQ
#define ADC_ISQ(adcx)
Definition: gd32f10x_adc.h:38
ADC_SAMPT1
#define ADC_SAMPT1(adcx)
Definition: gd32f10x_adc.h:28
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f10x_adc.h:85
ADC_ISQ_ISQN
#define ADC_ISQ_ISQN
Definition: gd32f10x_adc.h:101
void adc_inserted_channel_offset_config | ( | uint32_t | adc_periph,
 |  | uint8_t | inserted_channel,
 |  | uint16_t | offset
 | ) |  |

configure ADC inserted channel offset

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] inserted_channel : insert channel select only one parameter can be selected
  • ADC_INSERTED_CHANNEL_0: inserted channel0
  • ADC_INSERTED_CHANNEL_1: inserted channel1
  • ADC_INSERTED_CHANNEL_2: inserted channel2
  • ADC_INSERTED_CHANNEL_3: inserted channel3
[in] | offset | : the offset data
[out] | none
Return values
none

Definition at line 407 of file gd32f10x_adc.c.

408 {
409 uint8_t inserted_length;
410 uint32_t num = 0U;
411
412 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
413 num = 3U - (inserted_length - inserted_channel);
414
415 if(num <= 3U){
416 /* calculate the offset of the register */
417 num = num * 4U;
418 /* config the offset of the selected channels */
419 REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
420 }
421 }
ADC_ISQ
#define ADC_ISQ(adcx)
Definition: gd32f10x_adc.h:38
IOFFX_IOFF
#define IOFFX_IOFF(regval)
Definition: gd32f10x_adc.h:195
uint16_t adc_inserted_data_read | ( | uint32_t | adc_periph,
 |  | uint8_t | inserted_channel
 | ) |  |

read ADC inserted group data register

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] inserted_channel : insert channel select only one parameter can be selected
  • ADC_INSERTED_CHANNEL_0: inserted Channel0
  • ADC_INSERTED_CHANNEL_1: inserted channel1
  • ADC_INSERTED_CHANNEL_2: inserted Channel2
  • ADC_INSERTED_CHANNEL_3: inserted Channel3
[out] | none
Return values
the conversion value

Definition at line 596 of file gd32f10x_adc.c.

597 {
598 uint32_t idata;
599 /* read the data of the selected channel */
600 switch(inserted_channel){
601 case ADC_INSERTED_CHANNEL_0:
602 idata = ADC_IDATA0(adc_periph);
603 break;
604 case ADC_INSERTED_CHANNEL_1:
605 idata = ADC_IDATA1(adc_periph);
606 break;
607 case ADC_INSERTED_CHANNEL_2:
608 idata = ADC_IDATA2(adc_periph);
609 break;
610 case ADC_INSERTED_CHANNEL_3:
611 idata = ADC_IDATA3(adc_periph);
612 break;
613 default:
614 idata = 0U;
615 break;
616 }
617 return (uint16_t)idata;
618 }
ADC_INSERTED_CHANNEL_1
#define ADC_INSERTED_CHANNEL_1
Definition: gd32f10x_adc.h:218
ADC_IDATA0
#define ADC_IDATA0(adcx)
Definition: gd32f10x_adc.h:39
ADC_IDATA1
#define ADC_IDATA1(adcx)
Definition: gd32f10x_adc.h:40
ADC_INSERTED_CHANNEL_2
#define ADC_INSERTED_CHANNEL_2
Definition: gd32f10x_adc.h:219
ADC_IDATA2
#define ADC_IDATA2(adcx)
Definition: gd32f10x_adc.h:41
ADC_INSERTED_CHANNEL_3
#define ADC_INSERTED_CHANNEL_3
Definition: gd32f10x_adc.h:220
ADC_IDATA3
#define ADC_IDATA3(adcx)
Definition: gd32f10x_adc.h:42
ADC_INSERTED_CHANNEL_0
#define ADC_INSERTED_CHANNEL_0
Definition: gd32f10x_adc.h:217
FlagStatus adc_inserted_software_startconv_flag_get ( uint32_t adc_periph )

get the bit state of ADCx software inserted channel start conversion

Parameters
[in] | adc_periph | ADCx,x=0,1,2, only one among these parameters can be selected
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 561 of file gd32f10x_adc.c.

562 {
563 FlagStatus reval = RESET;
564 if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){
565 reval = SET;
566 }
567 return reval;
568 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_SWICST
#define ADC_CTL1_SWICST
Definition: gd32f10x_adc.h:80
void adc_interrupt_disable | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_interrupt
 | ) |  |

disable ADC interrupt

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_interrupt the adc interrupt flag one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt flag
  • ADC_INT_EOC: end of group conversion interrupt flag
  • ADC_INT_EOIC: end of inserted group conversion interrupt flag
[out] | none
Return values
none

Definition at line 772 of file gd32f10x_adc.c.

773 {
774 if(0U != (adc_interrupt & ADC_INT_WDE)){
775 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
776 }
777
778 if(0U != (adc_interrupt & ADC_INT_EOC)){
779 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
780 }
781
782 if(0U != (adc_interrupt & ADC_INT_EOIC)){
783 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
784 }
785 }
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f10x_adc.h:57
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f10x_adc.h:245
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f10x_adc.h:244
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f10x_adc.h:243
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f10x_adc.h:55
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f10x_adc.h:56
void adc_interrupt_enable | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_interrupt
 | ) |  |

enable ADC interrupt

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_interrupt the adc interrupt one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt flag
  • ADC_INT_EOC: end of group conversion interrupt flag
  • ADC_INT_EOIC: end of inserted group conversion interrupt flag
[out] | none
Return values
none

Definition at line 745 of file gd32f10x_adc.c.

746 {
747 if(0U != (adc_interrupt & ADC_INT_WDE)){
748 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
749 }
750
751 if(0U != (adc_interrupt & ADC_INT_EOC)){
752 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
753 }
754
755 if(0U != (adc_interrupt & ADC_INT_EOIC)){
756 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
757 }
758 }
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f10x_adc.h:57
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f10x_adc.h:245
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f10x_adc.h:244
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f10x_adc.h:243
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f10x_adc.h:55
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f10x_adc.h:56
void adc_interrupt_flag_clear | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_interrupt
 | ) |  |

clear the ADC flag

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_interrupt the adc status flag one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt
  • ADC_INT_EOC: end of group conversion interrupt
  • ADC_INT_EOIC: end of inserted group conversion interrupt
[out] | none
Return values
none

Definition at line 728 of file gd32f10x_adc.c.

729 {
730 ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
731 }
ADC_STAT
#define ADC_STAT(adcx)
Definition: gd32f10x_adc.h:24
FlagStatus adc_interrupt_flag_get | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_interrupt
 | ) |  |

get the ADC interrupt bits

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_interrupt the adc interrupt bits only oneparameter can be selected
  • ADC_INT_WDE: analog watchdog interrupt
  • ADC_INT_EOC: end of group conversion interrupt
  • ADC_INT_EOIC: end of inserted group conversion interrupt
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 686 of file gd32f10x_adc.c.

687 {
688 FlagStatus interrupt_flag = RESET;
689 uint32_t state;
690 /* check the interrupt bits */
691 switch(adc_interrupt){
692 case ADC_INT_WDE:
693 state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
694 if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
695 interrupt_flag = SET;
696 }
697 break;
698 case ADC_INT_EOC:
699 state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
700 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
701 interrupt_flag = SET;
702 }
703 break;
704 case ADC_INT_EOIC:
705 state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
706 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
707 interrupt_flag = SET;
708 }
709 break;
710 default:
711 break;
712 }
713 return interrupt_flag;
714 }
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f10x_adc.h:57
ADC_STAT_EOC
#define ADC_STAT_EOC
Definition: gd32f10x_adc.h:48
ADC_STAT_EOIC
#define ADC_STAT_EOIC
Definition: gd32f10x_adc.h:49
ADC_STAT
#define ADC_STAT(adcx)
Definition: gd32f10x_adc.h:24
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f10x_adc.h:245
ADC_STAT_WDE
#define ADC_STAT_WDE
Definition: gd32f10x_adc.h:47
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f10x_adc.h:244
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f10x_adc.h:243
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f10x_adc.h:55
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f10x_adc.h:56
void adc_mode_config ( uint32_t mode )

configure the ADC sync mode

Parameters
[in] mode ADC mode only one among these parameters can be selected
  • ADC_MODE_FREE: all the ADCs work independently
  • ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
  • ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
  • ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
  • ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
  • ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
  • ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
  • ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
  • ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
  • ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
[out] none
Return values
none

Definition at line 190 of file gd32f10x_adc.c.

191 {
192 ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
193 ADC_CTL0(ADC0) |= mode;
194 }
ADC_CTL0_SYNCM
#define ADC_CTL0_SYNCM
Definition: gd32f10x_adc.h:64
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_regular_channel_config | ( | uint32_t | adc_periph,
 |  | uint8_t | rank,
 |  | uint8_t | adc_channel,
 |  | uint32_t | sample_time
 | ) |  |

configure ADC regular channel

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] | rank | the regular group sequence rank,this parameter must be between 0 to 15
[in] adc_channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
[in] sample_time the sample time value only one parameter can be selected
  • ADC_SAMPLETIME_1POINT5: 1.5 cycles
  • ADC_SAMPLETIME_7POINT5: 7.5 cycles
  • ADC_SAMPLETIME_13POINT5: 13.5 cycles
  • ADC_SAMPLETIME_28POINT5: 28.5 cycles
  • ADC_SAMPLETIME_41POINT5: 41.5 cycles
  • ADC_SAMPLETIME_55POINT5: 55.5 cycles
  • ADC_SAMPLETIME_71POINT5: 71.5 cycles
  • ADC_SAMPLETIME_239POINT5: 239.5 cycles
[out] | none
Return values
none

Definition at line 307 of file gd32f10x_adc.c.

308 {
309 uint32_t rsq,sampt;
310
311 /* ADC regular sequence config */
312 if(rank < 6U){
313 rsq = ADC_RSQ2(adc_periph);
314 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
315 rsq |= ((uint32_t)adc_channel << (5U*rank));
316 ADC_RSQ2(adc_periph) = rsq;
317 }else if(rank < 12U){
318 rsq = ADC_RSQ1(adc_periph);
319 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
320 rsq |= ((uint32_t)adc_channel << (5U*(rank-6U)));
321 ADC_RSQ1(adc_periph) = rsq;
322 }else if(rank < 16U){
323 rsq = ADC_RSQ0(adc_periph);
324 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
325 rsq |= ((uint32_t)adc_channel << (5U*(rank-12U)));
326 ADC_RSQ0(adc_periph) = rsq;
327 }else{
328 }
329
330 /* ADC sampling time config */
331 if(adc_channel < 10U){
332 sampt = ADC_SAMPT1(adc_periph);
333 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
334 sampt |= (uint32_t)(sample_time << (3U*adc_channel));
335 ADC_SAMPT1(adc_periph) = sampt;
336 }else if(adc_channel < 18U){
337 sampt = ADC_SAMPT0(adc_periph);
338 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
339 sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U)));
340 ADC_SAMPT0(adc_periph) = sampt;
341 }else{
342 }
343 }
ADC_SAMPT0
#define ADC_SAMPT0(adcx)
Definition: gd32f10x_adc.h:27
ADC_SAMPT1
#define ADC_SAMPT1(adcx)
Definition: gd32f10x_adc.h:28
ADC_RSQ2
#define ADC_RSQ2(adcx)
Definition: gd32f10x_adc.h:37
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f10x_adc.h:85
ADC_RSQ0
#define ADC_RSQ0(adcx)
Definition: gd32f10x_adc.h:35
ADC_RSQ1
#define ADC_RSQ1(adcx)
Definition: gd32f10x_adc.h:36
ADC_RSQX_RSQN
#define ADC_RSQX_RSQN
Definition: gd32f10x_adc.h:97
uint16_t adc_regular_data_read ( uint32_t adc_periph )

read ADC regular group data register

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] | none
[out] | none
Return values
the conversion value

Definition at line 578 of file gd32f10x_adc.c.

579 {
580 return (uint16_t)(ADC_RDATA(adc_periph));
581 }
ADC_RDATA
#define ADC_RDATA(adcx)
Definition: gd32f10x_adc.h:43
FlagStatus adc_regular_software_startconv_flag_get ( uint32_t adc_periph )

get the bit state of ADCx software start conversion

Parameters
[in] | adc_periph | ADCx,x=0,1,2, only one among these parameters can be selected
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 545 of file gd32f10x_adc.c.

546 {
547 FlagStatus reval = RESET;
548 if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){
549 reval = SET;
550 }
551 return reval;
552 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_SWRCST
#define ADC_CTL1_SWRCST
Definition: gd32f10x_adc.h:81
void adc_software_trigger_enable | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group
 | ) |  |

enable ADC software trigger

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group one or more parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[out] | none
Return values
none

Definition at line 528 of file gd32f10x_adc.c.

529 {
530 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
531 ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
532 }
533 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
534 ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
535 }
536 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL1_SWRCST
#define ADC_CTL1_SWRCST
Definition: gd32f10x_adc.h:81
ADC_CTL1_SWICST
#define ADC_CTL1_SWICST
Definition: gd32f10x_adc.h:80
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_special_function_config | ( | uint32_t | adc_periph,
 |  | uint32_t | function,
 |  | ControlStatus | newvalue
 | ) |  |

enable or disable ADC special function

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] function the function to config one or more parameters can be selected below
  • ADC_SCAN_MODE: scan mode select
  • ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
  • ADC_CONTINUOUS_MODE: continuous mode select
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 209 of file gd32f10x_adc.c.

210 {
211 if(newvalue){
212 if(0U != (function & ADC_SCAN_MODE)){
213 ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
214 }
215 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
216 ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
217 }
218 if(0U != (function & ADC_CONTINUOUS_MODE)){
219 ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
220 }
221 }else{
222 if(0U != (function & ADC_SCAN_MODE)){
223 ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
224 }
225 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
226 ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
227 }
228 if(0U != (function & ADC_CONTINUOUS_MODE)){
229 ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
230 }
231 }
232 }
ADC_CONTINUOUS_MODE
#define ADC_CONTINUOUS_MODE
Definition: gd32f10x_adc.h:143
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_INSERTED_CHANNEL_AUTO
#define ADC_INSERTED_CHANNEL_AUTO
Definition: gd32f10x_adc.h:125
ADC_SCAN_MODE
#define ADC_SCAN_MODE
Definition: gd32f10x_adc.h:123
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
uint32_t adc_sync_mode_convert_value_read ( void )

read the last ADC0 and ADC1 conversion result data in sync mode

Parameters
[in] | none
[out] | none
Return values
the conversion value

Definition at line 626 of file gd32f10x_adc.c.

627 {
628 /* return conversion value */
629 return ADC_RDATA(ADC0);
630 }
ADC_RDATA
#define ADC_RDATA(adcx)
Definition: gd32f10x_adc.h:43
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_tempsensor_vrefint_disable ( void )

disable the temperature sensor and Vrefint channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 133 of file gd32f10x_adc.c.

134 {
135 /* disable the temperature sensor and Vrefint channel */
136 ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
137 }
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f10x_adc.h:82
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_tempsensor_vrefint_enable ( void )

enable the temperature sensor and Vrefint channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 121 of file gd32f10x_adc.c.

122 {
123 /* enable the temperature sensor and Vrefint channel */
124 ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
125 }
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f10x_adc.h:82
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_watchdog_disable ( uint32_t adc_periph )

disable ADC analog watchdog

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 843 of file gd32f10x_adc.c.

844 {
845 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
846 }
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f10x_adc.h:59
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f10x_adc.h:65
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f10x_adc.h:54
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f10x_adc.h:66
void adc_watchdog_group_channel_enable | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group
 | ) |  |

configure ADC analog watchdog group channel

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group the channel group use analog watchdog only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
  • ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
[out] | none
Return values
none

Definition at line 817 of file gd32f10x_adc.c.

818 {
819 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
820 /* select the group */
821 switch(adc_channel_group){
822 case ADC_REGULAR_CHANNEL:
823 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
824 break;
825 case ADC_INSERTED_CHANNEL:
826 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
827 break;
828 case ADC_REGULAR_INSERTED_CHANNEL:
829 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
830 break;
831 default:
832 break;
833 }
834 }
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f10x_adc.h:59
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f10x_adc.h:65
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_REGULAR_INSERTED_CHANNEL
#define ADC_REGULAR_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:212
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f10x_adc.h:66
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_watchdog_single_channel_enable | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel
 | ) |  |

configure ADC analog watchdog single channel

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
[out] | none
Return values
none

Definition at line 797 of file gd32f10x_adc.c.

798 {
799 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
800
801 ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
802 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
803 }
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f10x_adc.h:59
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f10x_adc.h:65
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f10x_adc.h:54
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f10x_adc.h:66
void adc_watchdog_threshold_config | ( | uint32_t | adc_periph,
 |  | uint16_t | low_threshold,
 |  | uint16_t | high_threshold
 | ) |  |

configure ADC analog watchdog threshold

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] | low_threshold | analog watchdog low threshold,0..4095
[in] | high_threshold | analog watchdog high threshold,0..4095
[out] | none
Return values
none

Definition at line 857 of file gd32f10x_adc.c.

858 {
859 ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
860 ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
861 }
ADC_WDLT
#define ADC_WDLT(adcx)
Definition: gd32f10x_adc.h:34
WDLT_WDLT
#define WDLT_WDLT(regval)
Definition: gd32f10x_adc.h:201
ADC_WDHT
#define ADC_WDHT(adcx)
Definition: gd32f10x_adc.h:33
WDHT_WDHT
#define WDHT_WDHT(regval)
Definition: gd32f10x_adc.h:198
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f10x_bkp.h File Reference

definitions for the BKP More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | BKP BKP_BASE
#define | BKP_DATA0 REG16((BKP) + 0x04U)
#define | BKP_DATA1 REG16((BKP) + 0x08U)
#define | BKP_DATA2 REG16((BKP) + 0x0CU)
#define | BKP_DATA3 REG16((BKP) + 0x10U)
#define | BKP_DATA4 REG16((BKP) + 0x14U)
#define | BKP_DATA5 REG16((BKP) + 0x18U)
#define | BKP_DATA6 REG16((BKP) + 0x1CU)
#define | BKP_DATA7 REG16((BKP) + 0x20U)
#define | BKP_DATA8 REG16((BKP) + 0x24U)
#define | BKP_DATA9 REG16((BKP) + 0x28U)
#define | BKP_DATA10 REG16((BKP) + 0x40U)
#define | BKP_DATA11 REG16((BKP) + 0x44U)
#define | BKP_DATA12 REG16((BKP) + 0x48U)
#define | BKP_DATA13 REG16((BKP) + 0x4CU)
#define | BKP_DATA14 REG16((BKP) + 0x50U)
#define | BKP_DATA15 REG16((BKP) + 0x54U)
#define | BKP_DATA16 REG16((BKP) + 0x58U)
#define | BKP_DATA17 REG16((BKP) + 0x5CU)
#define | BKP_DATA18 REG16((BKP) + 0x60U)
#define | BKP_DATA19 REG16((BKP) + 0x64U)
#define | BKP_DATA20 REG16((BKP) + 0x68U)
#define | BKP_DATA21 REG16((BKP) + 0x6CU)
#define | BKP_DATA22 REG16((BKP) + 0x70U)
#define | BKP_DATA23 REG16((BKP) + 0x74U)
#define | BKP_DATA24 REG16((BKP) + 0x78U)
#define | BKP_DATA25 REG16((BKP) + 0x7CU)
#define | BKP_DATA26 REG16((BKP) + 0x80U)
#define | BKP_DATA27 REG16((BKP) + 0x84U)
#define | BKP_DATA28 REG16((BKP) + 0x88U)
#define | BKP_DATA29 REG16((BKP) + 0x8CU)
#define | BKP_DATA30 REG16((BKP) + 0x90U)
#define | BKP_DATA31 REG16((BKP) + 0x94U)
#define | BKP_DATA32 REG16((BKP) + 0x98U)
#define | BKP_DATA33 REG16((BKP) + 0x9CU)
#define | BKP_DATA34 REG16((BKP) + 0xA0U)
#define | BKP_DATA35 REG16((BKP) + 0xA4U)
#define | BKP_DATA36 REG16((BKP) + 0xA8U)
#define | BKP_DATA37 REG16((BKP) + 0xACU)
#define | BKP_DATA38 REG16((BKP) + 0xB0U)
#define | BKP_DATA39 REG16((BKP) + 0xB4U)
#define | BKP_DATA40 REG16((BKP) + 0xB8U)
#define | BKP_DATA41 REG16((BKP) + 0xBCU)
#define | BKP_OCTL REG16((BKP) + 0x2CU)
#define | BKP_TPCTL REG16((BKP) + 0x30U)
#define | BKP_TPCS REG16((BKP) + 0x34U)
#define | BKP_DATA BITS(0,15)
#define | BKP_OCTL_RCCV BITS(0,6)
#define | BKP_OCTL_COEN BIT(7)
#define | BKP_OCTL_ASOEN BIT(8)
#define | BKP_OCTL_ROSEL BIT(9)
#define | BKP_TPCTL_TPEN BIT(0)
#define | BKP_TPCTL_TPAL BIT(1)
#define | BKP_TPCS_TER BIT(0)
#define | BKP_TPCS_TIR BIT(1)
#define | BKP_TPCS_TPIE BIT(2)
#define | BKP_TPCS_TEF BIT(8)
#define | BKP_TPCS_TIF BIT(9)
#define | BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U)
#define | BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
#define | BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15)
#define | OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
#define | RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U)
#define | RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U)
#define | TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U)
#define | TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U)
#define | BKP_FLAG_TAMPER BKP_TPCS_TEF
#define | BKP_INT_FLAG_TAMPER BKP_TPCS_TIF

Enumerations

enum bkp_data_register_enum {
BKP_DATA_0 = 1, BKP_DATA_1, BKP_DATA_2, BKP_DATA_3,
BKP_DATA_4, BKP_DATA_5, BKP_DATA_6, BKP_DATA_7,
BKP_DATA_8, BKP_DATA_9, BKP_DATA_10, BKP_DATA_11,
BKP_DATA_12, BKP_DATA_13, BKP_DATA_14, BKP_DATA_15,
BKP_DATA_16, BKP_DATA_17, BKP_DATA_18, BKP_DATA_19,
BKP_DATA_20, BKP_DATA_21, BKP_DATA_22, BKP_DATA_23,
BKP_DATA_24, BKP_DATA_25, BKP_DATA_26, BKP_DATA_27,
BKP_DATA_28, BKP_DATA_29, BKP_DATA_30, BKP_DATA_31,
BKP_DATA_32, BKP_DATA_33, BKP_DATA_34, BKP_DATA_35,
BKP_DATA_36, BKP_DATA_37, BKP_DATA_38, BKP_DATA_39,
BKP_DATA_40, BKP_DATA_41
}

Functions

void | bkp_deinit (void)
reset BKP registers More...
void | bkp_write_data (bkp_data_register_enum register_number, uint16_t data)
write BKP data register More...
uint16_t | bkp_read_data (bkp_data_register_enum register_number)
read BKP data register More...
void | bkp_rtc_calibration_output_enable (void)
enable RTC clock calibration output More...
void | bkp_rtc_calibration_output_disable (void)
disable RTC clock calibration output More...
void | bkp_rtc_signal_output_enable (void)
enable RTC alarm or second signal output More...
void | bkp_rtc_signal_output_disable (void)
disable RTC alarm or second signal output More...
void | bkp_rtc_output_select (uint16_t outputsel)
select RTC output More...
void | bkp_rtc_calibration_value_set (uint8_t value)
set RTC clock calibration value More...
void | bkp_tamper_detection_enable (void)
enable tamper detection More...
void | bkp_tamper_detection_disable (void)
disable tamper detection More...
void | bkp_tamper_active_level_set (uint16_t level)
set tamper pin active level More...
void | bkp_tamper_interrupt_enable (void)
enable tamper interrupt More...
void | bkp_tamper_interrupt_disable (void)
disable tamper interrupt More...
FlagStatus | bkp_flag_get (uint16_t flag)
get bkp flag state More...
void | bkp_flag_clear (uint16_t flag)
clear bkp flag state More...
FlagStatus | bkp_interrupt_flag_get (uint16_t flag)
get bkp interrupt flag state More...
void | bkp_interrupt_flag_clear (uint16_t flag)
clear bkp interrupt flag state More...

Detailed Description

definitions for the BKP

Definition in file gd32f10x_bkp.h.

Macro Definition Documentation

#define BKP BKP_BASE

BKP base address

Definition at line 19 of file gd32f10x_bkp.h.

#define BKP_DATA BITS(0,15)

backup data

Definition at line 70 of file gd32f10x_bkp.h.

#define BKP_DATA0 REG16((BKP) + 0x04U)

BKP data register 0

Definition at line 22 of file gd32f10x_bkp.h.

#define BKP_DATA0_9 ( number ) REG16((BKP) + 0x04U + (number) * 0x04U)

Definition at line 91 of file gd32f10x_bkp.h.

#define BKP_DATA1 REG16((BKP) + 0x08U)

BKP data register 1

Definition at line 23 of file gd32f10x_bkp.h.

#define BKP_DATA10 REG16((BKP) + 0x40U)

BKP data register 10

Definition at line 32 of file gd32f10x_bkp.h.

#define BKP_DATA10_41 ( number ) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)

Definition at line 92 of file gd32f10x_bkp.h.

#define BKP_DATA11 REG16((BKP) + 0x44U)

BKP data register 11

Definition at line 33 of file gd32f10x_bkp.h.

#define BKP_DATA12 REG16((BKP) + 0x48U)

BKP data register 12

Definition at line 34 of file gd32f10x_bkp.h.

#define BKP_DATA13 REG16((BKP) + 0x4CU)

BKP data register 13

Definition at line 35 of file gd32f10x_bkp.h.

#define BKP_DATA14 REG16((BKP) + 0x50U)

BKP data register 14

Definition at line 36 of file gd32f10x_bkp.h.

#define BKP_DATA15 REG16((BKP) + 0x54U)

BKP data register 15

Definition at line 37 of file gd32f10x_bkp.h.

#define BKP_DATA16 REG16((BKP) + 0x58U)

BKP data register 16

Definition at line 38 of file gd32f10x_bkp.h.

#define BKP_DATA17 REG16((BKP) + 0x5CU)

BKP data register 17

Definition at line 39 of file gd32f10x_bkp.h.

#define BKP_DATA18 REG16((BKP) + 0x60U)

BKP data register 18

Definition at line 40 of file gd32f10x_bkp.h.

#define BKP_DATA19 REG16((BKP) + 0x64U)

BKP data register 19

Definition at line 41 of file gd32f10x_bkp.h.

#define BKP_DATA2 REG16((BKP) + 0x0CU)

BKP data register 2

Definition at line 24 of file gd32f10x_bkp.h.

#define BKP_DATA20 REG16((BKP) + 0x68U)

BKP data register 20

Definition at line 42 of file gd32f10x_bkp.h.

#define BKP_DATA21 REG16((BKP) + 0x6CU)

BKP data register 21

Definition at line 43 of file gd32f10x_bkp.h.

#define BKP_DATA22 REG16((BKP) + 0x70U)

BKP data register 22

Definition at line 44 of file gd32f10x_bkp.h.

#define BKP_DATA23 REG16((BKP) + 0x74U)

BKP data register 23

Definition at line 45 of file gd32f10x_bkp.h.

#define BKP_DATA24 REG16((BKP) + 0x78U)

BKP data register 24

Definition at line 46 of file gd32f10x_bkp.h.

#define BKP_DATA25 REG16((BKP) + 0x7CU)

BKP data register 25

Definition at line 47 of file gd32f10x_bkp.h.

#define BKP_DATA26 REG16((BKP) + 0x80U)

BKP data register 26

Definition at line 48 of file gd32f10x_bkp.h.

#define BKP_DATA27 REG16((BKP) + 0x84U)

BKP data register 27

Definition at line 49 of file gd32f10x_bkp.h.

#define BKP_DATA28 REG16((BKP) + 0x88U)

BKP data register 28

Definition at line 50 of file gd32f10x_bkp.h.

#define BKP_DATA29 REG16((BKP) + 0x8CU)

BKP data register 29

Definition at line 51 of file gd32f10x_bkp.h.

#define BKP_DATA3 REG16((BKP) + 0x10U)

BKP data register 3

Definition at line 25 of file gd32f10x_bkp.h.

#define BKP_DATA30 REG16((BKP) + 0x90U)

BKP data register 30

Definition at line 52 of file gd32f10x_bkp.h.

#define BKP_DATA31 REG16((BKP) + 0x94U)

BKP data register 31

Definition at line 53 of file gd32f10x_bkp.h.

#define BKP_DATA32 REG16((BKP) + 0x98U)

BKP data register 32

Definition at line 54 of file gd32f10x_bkp.h.

#define BKP_DATA33 REG16((BKP) + 0x9CU)

BKP data register 33

Definition at line 55 of file gd32f10x_bkp.h.

#define BKP_DATA34 REG16((BKP) + 0xA0U)

BKP data register 34

Definition at line 56 of file gd32f10x_bkp.h.

#define BKP_DATA35 REG16((BKP) + 0xA4U)

BKP data register 35

Definition at line 57 of file gd32f10x_bkp.h.

#define BKP_DATA36 REG16((BKP) + 0xA8U)

BKP data register 36

Definition at line 58 of file gd32f10x_bkp.h.

#define BKP_DATA37 REG16((BKP) + 0xACU)

BKP data register 37

Definition at line 59 of file gd32f10x_bkp.h.

#define BKP_DATA38 REG16((BKP) + 0xB0U)

BKP data register 38

Definition at line 60 of file gd32f10x_bkp.h.

#define BKP_DATA39 REG16((BKP) + 0xB4U)

BKP data register 39

Definition at line 61 of file gd32f10x_bkp.h.

#define BKP_DATA4 REG16((BKP) + 0x14U)

BKP data register 4

Definition at line 26 of file gd32f10x_bkp.h.

#define BKP_DATA40 REG16((BKP) + 0xB8U)

BKP data register 40

Definition at line 62 of file gd32f10x_bkp.h.

#define BKP_DATA41 REG16((BKP) + 0xBCU)

BKP data register 41

Definition at line 63 of file gd32f10x_bkp.h.

#define BKP_DATA5 REG16((BKP) + 0x18U)

BKP data register 5

Definition at line 27 of file gd32f10x_bkp.h.

#define BKP_DATA6 REG16((BKP) + 0x1CU)

BKP data register 6

Definition at line 28 of file gd32f10x_bkp.h.

#define BKP_DATA7 REG16((BKP) + 0x20U)

BKP data register 7

Definition at line 29 of file gd32f10x_bkp.h.

#define BKP_DATA8 REG16((BKP) + 0x24U)

BKP data register 8

Definition at line 30 of file gd32f10x_bkp.h.

#define BKP_DATA9 REG16((BKP) + 0x28U)

BKP data register 9

Definition at line 31 of file gd32f10x_bkp.h.

#define BKP_DATA_GET ( regval ) GET_BITS((uint32_t)(regval), 0, 15)

Definition at line 95 of file gd32f10x_bkp.h.

#define BKP_FLAG_TAMPER BKP_TPCS_TEF

tamper event flag

Definition at line 109 of file gd32f10x_bkp.h.

#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF

tamper interrupt flag

Definition at line 112 of file gd32f10x_bkp.h.

#define BKP_OCTL REG16((BKP) + 0x2CU)

RTC signal output control register

Definition at line 64 of file gd32f10x_bkp.h.

#define BKP_OCTL_ASOEN BIT(8)

RTC alarm or second signal output enable

Definition at line 75 of file gd32f10x_bkp.h.

#define BKP_OCTL_COEN BIT(7)

RTC clock calibration output enable

Definition at line 74 of file gd32f10x_bkp.h.

#define BKP_OCTL_RCCV BITS(0,6)

RTC clock calibration value

Definition at line 73 of file gd32f10x_bkp.h.

#define BKP_OCTL_ROSEL BIT(9)

RTC output selection

Definition at line 76 of file gd32f10x_bkp.h.

#define BKP_TPCS REG16((BKP) + 0x34U)

tamper control and status register

Definition at line 66 of file gd32f10x_bkp.h.

#define BKP_TPCS_TEF BIT(8)

tamper event flag

Definition at line 86 of file gd32f10x_bkp.h.

#define BKP_TPCS_TER BIT(0)

tamper event reset

Definition at line 83 of file gd32f10x_bkp.h.

#define BKP_TPCS_TIF BIT(9)

tamper interrupt flag

Definition at line 87 of file gd32f10x_bkp.h.

#define BKP_TPCS_TIR BIT(1)

tamper interrupt reset

Definition at line 84 of file gd32f10x_bkp.h.

#define BKP_TPCS_TPIE BIT(2)

tamper interrupt enable

Definition at line 85 of file gd32f10x_bkp.h.

#define BKP_TPCTL REG16((BKP) + 0x30U)

tamper pin control register

Definition at line 65 of file gd32f10x_bkp.h.

#define BKP_TPCTL_TPAL BIT(1)

tamper pin active level

Definition at line 80 of file gd32f10x_bkp.h.

#define BKP_TPCTL_TPEN BIT(0)

tamper detection enable

Definition at line 79 of file gd32f10x_bkp.h.

#define OCTL_RCCV ( regval ) (BITS(0,6) & ((uint32_t)(regval) << 0))

Definition at line 98 of file gd32f10x_bkp.h.

#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U)

RTC alarm pulse is selected as the RTC output

Definition at line 101 of file gd32f10x_bkp.h.

#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U)

RTC second pulse is selected as the RTC output

Definition at line 102 of file gd32f10x_bkp.h.

#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U)

the tamper pin is active high

Definition at line 105 of file gd32f10x_bkp.h.

#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U)

the tamper pin is active low

Definition at line 106 of file gd32f10x_bkp.h.

Enumeration Type Documentation

enum bkp_data_register_enum
Enumerator
BKP_DATA_0 | BKP data register 0
BKP_DATA_1 | BKP data register 1
BKP_DATA_2 | BKP data register 2
BKP_DATA_3 | BKP data register 3
BKP_DATA_4 | BKP data register 4
BKP_DATA_5 | BKP data register 5
BKP_DATA_6 | BKP data register 6
BKP_DATA_7 | BKP data register 7
BKP_DATA_8 | BKP data register 8
BKP_DATA_9 | BKP data register 9
BKP_DATA_10 | BKP data register 10
BKP_DATA_11 | BKP data register 11
BKP_DATA_12 | BKP data register 12
BKP_DATA_13 | BKP data register 13
BKP_DATA_14 | BKP data register 14
BKP_DATA_15 | BKP data register 15
BKP_DATA_16 | BKP data register 16
BKP_DATA_17 | BKP data register 17
BKP_DATA_18 | BKP data register 18
BKP_DATA_19 | BKP data register 19
BKP_DATA_20 | BKP data register 20
BKP_DATA_21 | BKP data register 21
BKP_DATA_22 | BKP data register 22
BKP_DATA_23 | BKP data register 23
BKP_DATA_24 | BKP data register 24
BKP_DATA_25 | BKP data register 25
BKP_DATA_26 | BKP data register 26
BKP_DATA_27 | BKP data register 27
BKP_DATA_28 | BKP data register 28
BKP_DATA_29 | BKP data register 29
BKP_DATA_30 | BKP data register 30
BKP_DATA_31 | BKP data register 31
BKP_DATA_32 | BKP data register 32
BKP_DATA_33 | BKP data register 33
BKP_DATA_34 | BKP data register 34
BKP_DATA_35 | BKP data register 35
BKP_DATA_36 | BKP data register 36
BKP_DATA_37 | BKP data register 37
BKP_DATA_38 | BKP data register 38
BKP_DATA_39 | BKP data register 39
BKP_DATA_40 | BKP data register 40
BKP_DATA_41 | BKP data register 41

Definition at line 115 of file gd32f10x_bkp.h.

116 {
117 BKP_DATA_0 = 1,
118 BKP_DATA_1,
119 BKP_DATA_2,
120 BKP_DATA_3,
121 BKP_DATA_4,
122 BKP_DATA_5,
123 BKP_DATA_6,
124 BKP_DATA_7,
125 BKP_DATA_8,
126 BKP_DATA_9,
127 BKP_DATA_10,
128 BKP_DATA_11,
129 BKP_DATA_12,
130 BKP_DATA_13,
131 BKP_DATA_14,
132 BKP_DATA_15,
133 BKP_DATA_16,
134 BKP_DATA_17,
135 BKP_DATA_18,
136 BKP_DATA_19,
137 BKP_DATA_20,
138 BKP_DATA_21,
139 BKP_DATA_22,
140 BKP_DATA_23,
141 BKP_DATA_24,
142 BKP_DATA_25,
143 BKP_DATA_26,
144 BKP_DATA_27,
145 BKP_DATA_28,
146 BKP_DATA_29,
147 BKP_DATA_30,
148 BKP_DATA_31,
149 BKP_DATA_32,
150 BKP_DATA_33,
151 BKP_DATA_34,
152 BKP_DATA_35,
153 BKP_DATA_36,
154 BKP_DATA_37,
155 BKP_DATA_38,
156 BKP_DATA_39,
157 BKP_DATA_40,
158 BKP_DATA_41,
159 }bkp_data_register_enum;
BKP_DATA_33
Definition: gd32f10x_bkp.h:150
BKP_DATA_22
Definition: gd32f10x_bkp.h:139
BKP_DATA_29
Definition: gd32f10x_bkp.h:146
BKP_DATA_5
Definition: gd32f10x_bkp.h:122
BKP_DATA_36
Definition: gd32f10x_bkp.h:153
BKP_DATA_30
Definition: gd32f10x_bkp.h:147
BKP_DATA_4
Definition: gd32f10x_bkp.h:121
BKP_DATA_17
Definition: gd32f10x_bkp.h:134
BKP_DATA_24
Definition: gd32f10x_bkp.h:141
BKP_DATA_8
Definition: gd32f10x_bkp.h:125
BKP_DATA_1
Definition: gd32f10x_bkp.h:118
BKP_DATA_13
Definition: gd32f10x_bkp.h:130
BKP_DATA_19
Definition: gd32f10x_bkp.h:136
BKP_DATA_34
Definition: gd32f10x_bkp.h:151
BKP_DATA_6
Definition: gd32f10x_bkp.h:123
BKP_DATA_20
Definition: gd32f10x_bkp.h:137
BKP_DATA_9
Definition: gd32f10x_bkp.h:126
BKP_DATA_35
Definition: gd32f10x_bkp.h:152
BKP_DATA_37
Definition: gd32f10x_bkp.h:154
BKP_DATA_27
Definition: gd32f10x_bkp.h:144
BKP_DATA_2
Definition: gd32f10x_bkp.h:119
BKP_DATA_12
Definition: gd32f10x_bkp.h:129
BKP_DATA_32
Definition: gd32f10x_bkp.h:149
BKP_DATA_40
Definition: gd32f10x_bkp.h:157
bkp_data_register_enum
bkp_data_register_enum
Definition: gd32f10x_bkp.h:115
BKP_DATA_31
Definition: gd32f10x_bkp.h:148
BKP_DATA_38
Definition: gd32f10x_bkp.h:155
BKP_DATA_26
Definition: gd32f10x_bkp.h:143
BKP_DATA_25
Definition: gd32f10x_bkp.h:142
BKP_DATA_14
Definition: gd32f10x_bkp.h:131
BKP_DATA_41
Definition: gd32f10x_bkp.h:158
BKP_DATA_11
Definition: gd32f10x_bkp.h:128
BKP_DATA_23
Definition: gd32f10x_bkp.h:140
BKP_DATA_15
Definition: gd32f10x_bkp.h:132
BKP_DATA_21
Definition: gd32f10x_bkp.h:138
BKP_DATA_3
Definition: gd32f10x_bkp.h:120
BKP_DATA_18
Definition: gd32f10x_bkp.h:135
BKP_DATA_28
Definition: gd32f10x_bkp.h:145
BKP_DATA_7
Definition: gd32f10x_bkp.h:124
BKP_DATA_10
Definition: gd32f10x_bkp.h:127
BKP_DATA_39
Definition: gd32f10x_bkp.h:156
BKP_DATA_16
Definition: gd32f10x_bkp.h:133
BKP_DATA_0
Definition: gd32f10x_bkp.h:117

Function Documentation

void bkp_deinit ( void )

reset BKP registers

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 23 of file gd32f10x_bkp.c.

24 {
25 /* reset BKP domain register*/
26 rcu_bkp_reset_enable();
27 rcu_bkp_reset_disable();
28 }
rcu_bkp_reset_enable
void rcu_bkp_reset_enable(void)
reset the BKP domain
Definition: gd32f10x_rcu.c:223
rcu_bkp_reset_disable
void rcu_bkp_reset_disable(void)
disable the BKP domain reset
Definition: gd32f10x_rcu.c:234
void bkp_flag_clear ( uint16_t flag )

clear bkp flag state

Parameters
[in] flag
  • BKP_FLAG_TAMPER: tamper event flag
[out] none
Return values
none

Definition at line 235 of file gd32f10x_bkp.c.

236 {
237 BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT);
238 }
TAMPER_FLAG_SHIFT
#define TAMPER_FLAG_SHIFT
Definition: gd32f10x_bkp.c:15
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
FlagStatus bkp_flag_get ( uint16_t flag )

get bkp flag state

Parameters
[in] flag
  • BKP_FLAG_TAMPER: tamper event flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 219 of file gd32f10x_bkp.c.

220 {
221 if(RESET != (BKP_TPCS & flag)){
222 return SET;
223 }else{
224 return RESET;
225 }
226 }
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
void bkp_interrupt_flag_clear ( uint16_t flag )

clear bkp interrupt flag state

Parameters
[in] flag
  • BKP_INT_FLAG_TAMPER: tamper interrupt flag
[out] none
Return values
none

Definition at line 263 of file gd32f10x_bkp.c.

264 {
265 BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT);
266 }
TAMPER_FLAG_SHIFT
#define TAMPER_FLAG_SHIFT
Definition: gd32f10x_bkp.c:15
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
FlagStatus bkp_interrupt_flag_get ( uint16_t flag )

get bkp interrupt flag state

Parameters
[in] flag
  • BKP_INT_FLAG_TAMPER: tamper interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 247 of file gd32f10x_bkp.c.

248 {
249 if(RESET != (BKP_TPCS & flag)){
250 return SET;
251 }else{
252 return RESET;
253 }
254 }
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
uint16_t bkp_read_data ( bkp_data_register_enum register_number )

read BKP data register

Parameters
[in] register_number refer to bkp_data_register_enum, only one parameter can be selected
  • BKP_DATA_x(x = 0..41): bkp data register number x
[out] none
Return values
data of BKP data register

Definition at line 56 of file gd32f10x_bkp.c.

57 {
58 uint16_t data = 0U;
59
60 /* get the data from the BKP data register */
61 if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
62 data = BKP_DATA10_41(register_number - 1U);
63 }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
64 data = BKP_DATA0_9(register_number - 1U);
65 }else{
66 /* illegal parameters */
67 }
68 return data;
69 }
BKP_DATA10_41
#define BKP_DATA10_41(number)
Definition: gd32f10x_bkp.h:92
BKP_DATA0_9
#define BKP_DATA0_9(number)
Definition: gd32f10x_bkp.h:91
BKP_DATA_9
Definition: gd32f10x_bkp.h:126
BKP_DATA_41
Definition: gd32f10x_bkp.h:158
BKP_DATA_10
Definition: gd32f10x_bkp.h:127
BKP_DATA_0
Definition: gd32f10x_bkp.h:117
void bkp_rtc_calibration_output_disable ( void )

disable RTC clock calibration output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 88 of file gd32f10x_bkp.c.

89 {
90 BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
91 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_COEN
#define BKP_OCTL_COEN
Definition: gd32f10x_bkp.h:74
void bkp_rtc_calibration_output_enable ( void )

enable RTC clock calibration output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 77 of file gd32f10x_bkp.c.

78 {
79 BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
80 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_COEN
#define BKP_OCTL_COEN
Definition: gd32f10x_bkp.h:74
void bkp_rtc_calibration_value_set ( uint8_t value )

set RTC clock calibration value

Parameters
[in] value RTC clock calibration value
  • 0x00 - 0x7F
[out] none
Return values
none

Definition at line 140 of file gd32f10x_bkp.c.

141 {
142 uint16_t ctl;
143
144 ctl = BKP_OCTL;
145 ctl &= (uint16_t)OCTL_RCCV(0);
146 ctl |= (uint16_t)OCTL_RCCV(value);
147 BKP_OCTL = ctl;
148 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
OCTL_RCCV
#define OCTL_RCCV(regval)
Definition: gd32f10x_bkp.h:98
void bkp_rtc_output_select ( uint16_t outputsel )

select RTC output

Parameters
[in] outputsel RTC output selection
  • RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output
  • RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output
[out] none
Return values
none

Definition at line 123 of file gd32f10x_bkp.c.

124 {
125 uint16_t ctl = 0U;
126
127 ctl = BKP_OCTL;
128 ctl &= (uint16_t)~BKP_OCTL_ROSEL;
129 ctl |= outputsel;
130 BKP_OCTL = ctl;
131 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_ROSEL
#define BKP_OCTL_ROSEL
Definition: gd32f10x_bkp.h:76
void bkp_rtc_signal_output_disable ( void )

disable RTC alarm or second signal output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 110 of file gd32f10x_bkp.c.

111 {
112 BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
113 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_ASOEN
#define BKP_OCTL_ASOEN
Definition: gd32f10x_bkp.h:75
void bkp_rtc_signal_output_enable ( void )

enable RTC alarm or second signal output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 99 of file gd32f10x_bkp.c.

100 {
101 BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
102 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_ASOEN
#define BKP_OCTL_ASOEN
Definition: gd32f10x_bkp.h:75
void bkp_tamper_active_level_set ( uint16_t level )

set tamper pin active level

Parameters
[in] level tamper active level
  • TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high
  • TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low
[out] none
Return values
none

Definition at line 180 of file gd32f10x_bkp.c.

181 {
182 uint16_t ctl = 0U;
183
184 ctl = BKP_TPCTL;
185 ctl &= (uint16_t)~BKP_TPCTL_TPAL;
186 ctl |= level;
187 BKP_TPCTL = ctl;
188 }
BKP_TPCTL
#define BKP_TPCTL
Definition: gd32f10x_bkp.h:65
BKP_TPCTL_TPAL
#define BKP_TPCTL_TPAL
Definition: gd32f10x_bkp.h:80
void bkp_tamper_detection_disable ( void )

disable tamper detection

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 167 of file gd32f10x_bkp.c.

168 {
169 BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN;
170 }
BKP_TPCTL
#define BKP_TPCTL
Definition: gd32f10x_bkp.h:65
BKP_TPCTL_TPEN
#define BKP_TPCTL_TPEN
Definition: gd32f10x_bkp.h:79
void bkp_tamper_detection_enable ( void )

enable tamper detection

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 156 of file gd32f10x_bkp.c.

157 {
158 BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN;
159 }
BKP_TPCTL
#define BKP_TPCTL
Definition: gd32f10x_bkp.h:65
BKP_TPCTL_TPEN
#define BKP_TPCTL_TPEN
Definition: gd32f10x_bkp.h:79
void bkp_tamper_interrupt_disable ( void )

disable tamper interrupt

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 207 of file gd32f10x_bkp.c.

208 {
209 BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE;
210 }
BKP_TPCS_TPIE
#define BKP_TPCS_TPIE
Definition: gd32f10x_bkp.h:85
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
void bkp_tamper_interrupt_enable ( void )

enable tamper interrupt

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 196 of file gd32f10x_bkp.c.

197 {
198 BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE;
199 }
BKP_TPCS_TPIE
#define BKP_TPCS_TPIE
Definition: gd32f10x_bkp.h:85
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
void bkp_write_data | ( | bkp_data_register_enum | register_number,
 |  | uint16_t | data
 | ) |  |

write BKP data register

Parameters
[in] register_number refer to bkp_data_register_enum, only one parameter can be selected
  • BKP_DATA_x(x = 0..41): bkp data register number x
[in] | data | the data to be write in BKP data register
[out] | none
Return values
none

Definition at line 38 of file gd32f10x_bkp.c.

39 {
40 if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
41 BKP_DATA10_41(register_number - 1U) = data;
42 }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
43 BKP_DATA0_9(register_number - 1U) = data;
44 }else{
45 /* illegal parameters */
46 }
47 }
BKP_DATA10_41
#define BKP_DATA10_41(number)
Definition: gd32f10x_bkp.h:92
BKP_DATA0_9
#define BKP_DATA0_9(number)
Definition: gd32f10x_bkp.h:91
BKP_DATA_9
Definition: gd32f10x_bkp.h:126
BKP_DATA_41
Definition: gd32f10x_bkp.h:158
BKP_DATA_10
Definition: gd32f10x_bkp.h:127
BKP_DATA_0
Definition: gd32f10x_bkp.h:117
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_can.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Data Structures | Macros | Enumerations | Functions
gd32f10x_can.h File Reference

definitions for the CAN More...

#include "gd32f10x.h"

Go to the source code of this file.

Data Structures

struct | can_parameter_struct
struct | can_trasnmit_message_struct
struct | can_receive_message_struct
struct | can_filter_parameter_struct

Macros

#define | CAN0 CAN_BASE
#define | CAN1 (CAN0 + 0x00000400U)
#define | CAN_CTL(canx) REG32((canx) + 0x00U)
#define | CAN_STAT(canx) REG32((canx) + 0x04U)
#define | CAN_TSTAT(canx) REG32((canx) + 0x08U)
#define | CAN_RFIFO0(canx) REG32((canx) + 0x0CU)
#define | CAN_RFIFO1(canx) REG32((canx) + 0x10U)
#define | CAN_INTEN(canx) REG32((canx) + 0x14U)
#define | CAN_ERR(canx) REG32((canx) + 0x18U)
#define | CAN_BT(canx) REG32((canx) + 0x1CU)
#define | CAN_TMI0(canx) REG32((canx) + 0x180U)
#define | CAN_TMP0(canx) REG32((canx) + 0x184U)
#define | CAN_TMDATA00(canx) REG32((canx) + 0x188U)
#define | CAN_TMDATA10(canx) REG32((canx) + 0x18CU)
#define | CAN_TMI1(canx) REG32((canx) + 0x190U)
#define | CAN_TMP1(canx) REG32((canx) + 0x194U)
#define | CAN_TMDATA01(canx) REG32((canx) + 0x198U)
#define | CAN_TMDATA11(canx) REG32((canx) + 0x19CU)
#define | CAN_TMI2(canx) REG32((canx) + 0x1A0U)
#define | CAN_TMP2(canx) REG32((canx) + 0x1A4U)
#define | CAN_TMDATA02(canx) REG32((canx) + 0x1A8U)
#define | CAN_TMDATA12(canx) REG32((canx) + 0x1ACU)
#define | CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U)
#define | CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U)
#define | CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U)
#define | CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU)
#define | CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U)
#define | CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U)
#define | CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U)
#define | CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU)
#define | CAN_FCTL(canx) REG32((canx) + 0x200U)
#define | CAN_FMCFG(canx) REG32((canx) + 0x204U)
#define | CAN_FSCFG(canx) REG32((canx) + 0x20CU)
#define | CAN_FAFIFO(canx) REG32((canx) + 0x214U)
#define | CAN_FW(canx) REG32((canx) + 0x21CU)
#define | CAN_F0DATA0(canx) REG32((canx) + 0x240U)
#define | CAN_F1DATA0(canx) REG32((canx) + 0x248U)
#define | CAN_F2DATA0(canx) REG32((canx) + 0x250U)
#define | CAN_F3DATA0(canx) REG32((canx) + 0x258U)
#define | CAN_F4DATA0(canx) REG32((canx) + 0x260U)
#define | CAN_F5DATA0(canx) REG32((canx) + 0x268U)
#define | CAN_F6DATA0(canx) REG32((canx) + 0x270U)
#define | CAN_F7DATA0(canx) REG32((canx) + 0x278U)
#define | CAN_F8DATA0(canx) REG32((canx) + 0x280U)
#define | CAN_F9DATA0(canx) REG32((canx) + 0x288U)
#define | CAN_F10DATA0(canx) REG32((canx) + 0x290U)
#define | CAN_F11DATA0(canx) REG32((canx) + 0x298U)
#define | CAN_F12DATA0(canx) REG32((canx) + 0x2A0U)
#define | CAN_F13DATA0(canx) REG32((canx) + 0x2A8U)
#define | CAN_F14DATA0(canx) REG32((canx) + 0x2B0U)
#define | CAN_F15DATA0(canx) REG32((canx) + 0x2B8U)
#define | CAN_F16DATA0(canx) REG32((canx) + 0x2C0U)
#define | CAN_F17DATA0(canx) REG32((canx) + 0x2C8U)
#define | CAN_F18DATA0(canx) REG32((canx) + 0x2D0U)
#define | CAN_F19DATA0(canx) REG32((canx) + 0x2D8U)
#define | CAN_F20DATA0(canx) REG32((canx) + 0x2E0U)
#define | CAN_F21DATA0(canx) REG32((canx) + 0x2E8U)
#define | CAN_F22DATA0(canx) REG32((canx) + 0x2F0U)
#define | CAN_F23DATA0(canx) REG32((canx) + 0x3F8U)
#define | CAN_F24DATA0(canx) REG32((canx) + 0x300U)
#define | CAN_F25DATA0(canx) REG32((canx) + 0x308U)
#define | CAN_F26DATA0(canx) REG32((canx) + 0x310U)
#define | CAN_F27DATA0(canx) REG32((canx) + 0x318U)
#define | CAN_F0DATA1(canx) REG32((canx) + 0x244U)
#define | CAN_F1DATA1(canx) REG32((canx) + 0x24CU)
#define | CAN_F2DATA1(canx) REG32((canx) + 0x254U)
#define | CAN_F3DATA1(canx) REG32((canx) + 0x25CU)
#define | CAN_F4DATA1(canx) REG32((canx) + 0x264U)
#define | CAN_F5DATA1(canx) REG32((canx) + 0x26CU)
#define | CAN_F6DATA1(canx) REG32((canx) + 0x274U)
#define | CAN_F7DATA1(canx) REG32((canx) + 0x27CU)
#define | CAN_F8DATA1(canx) REG32((canx) + 0x284U)
#define | CAN_F9DATA1(canx) REG32((canx) + 0x28CU)
#define | CAN_F10DATA1(canx) REG32((canx) + 0x294U)
#define | CAN_F11DATA1(canx) REG32((canx) + 0x29CU)
#define | CAN_F12DATA1(canx) REG32((canx) + 0x2A4U)
#define | CAN_F13DATA1(canx) REG32((canx) + 0x2ACU)
#define | CAN_F14DATA1(canx) REG32((canx) + 0x2B4U)
#define | CAN_F15DATA1(canx) REG32((canx) + 0x2BCU)
#define | CAN_F16DATA1(canx) REG32((canx) + 0x2C4U)
#define | CAN_F17DATA1(canx) REG32((canx) + 0x24CU)
#define | CAN_F18DATA1(canx) REG32((canx) + 0x2D4U)
#define | CAN_F19DATA1(canx) REG32((canx) + 0x2DCU)
#define | CAN_F20DATA1(canx) REG32((canx) + 0x2E4U)
#define | CAN_F21DATA1(canx) REG32((canx) + 0x2ECU)
#define | CAN_F22DATA1(canx) REG32((canx) + 0x2F4U)
#define | CAN_F23DATA1(canx) REG32((canx) + 0x2FCU)
#define | CAN_F24DATA1(canx) REG32((canx) + 0x304U)
#define | CAN_F25DATA1(canx) REG32((canx) + 0x30CU)
#define | CAN_F26DATA1(canx) REG32((canx) + 0x314U)
#define | CAN_F27DATA1(canx) REG32((canx) + 0x31CU)
#define | CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U))
#define | CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U))
#define | CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U))
#define | CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U))
#define | CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U)
#define | CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U)
#define | CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U))
#define | CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U))
#define | CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U))
#define | CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U))
#define | CAN_CTL_IWMOD BIT(0)
#define | CAN_CTL_SLPWMOD BIT(1)
#define | CAN_CTL_TFO BIT(2)
#define | CAN_CTL_RFOD BIT(3)
#define | CAN_CTL_ARD BIT(4)
#define | CAN_CTL_AWU BIT(5)
#define | CAN_CTL_ABOR BIT(6)
#define | CAN_CTL_TTC BIT(7)
#define | CAN_CTL_SWRST BIT(15)
#define | CAN_CTL_DFZ BIT(16)
#define | CAN_STAT_IWS BIT(0)
#define | CAN_STAT_SLPWS BIT(1)
#define | CAN_STAT_ERRIF BIT(2)
#define | CAN_STAT_WUIF BIT(3)
#define | CAN_STAT_SLPIF BIT(4)
#define | CAN_STAT_TS BIT(8)
#define | CAN_STAT_RS BIT(9)
#define | CAN_STAT_LASTRX BIT(10)
#define | CAN_STAT_RXL BIT(11)
#define | CAN_TSTAT_MTF0 BIT(0)
#define | CAN_TSTAT_MTFNERR0 BIT(1)
#define | CAN_TSTAT_MAL0 BIT(2)
#define | CAN_TSTAT_MTE0 BIT(3)
#define | CAN_TSTAT_MST0 BIT(7)
#define | CAN_TSTAT_MTF1 BIT(8)
#define | CAN_TSTAT_MTFNERR1 BIT(9)
#define | CAN_TSTAT_MAL1 BIT(10)
#define | CAN_TSTAT_MTE1 BIT(11)
#define | CAN_TSTAT_MST1 BIT(15)
#define | CAN_TSTAT_MTF2 BIT(16)
#define | CAN_TSTAT_MTFNERR2 BIT(17)
#define | CAN_TSTAT_MAL2 BIT(18)
#define | CAN_TSTAT_MTE2 BIT(19)
#define | CAN_TSTAT_MST2 BIT(23)
#define | CAN_TSTAT_NUM BITS(24,25)
#define | CAN_TSTAT_TME0 BIT(26)
#define | CAN_TSTAT_TME1 BIT(27)
#define | CAN_TSTAT_TME2 BIT(28)
#define | CAN_TSTAT_TMLS0 BIT(29)
#define | CAN_TSTAT_TMLS1 BIT(30)
#define | CAN_TSTAT_TMLS2 BIT(31)
#define | CAN_RFIFO0_RFL0 BITS(0,1)
#define | CAN_RFIFO0_RFF0 BIT(3)
#define | CAN_RFIFO0_RFO0 BIT(4)
#define | CAN_RFIFO0_RFD0 BIT(5)
#define | CAN_RFIFO1_RFL1 BITS(0,1)
#define | CAN_RFIFO1_RFF1 BIT(3)
#define | CAN_RFIFO1_RFO1 BIT(4)
#define | CAN_RFIFO1_RFD1 BIT(5)
#define | CAN_INTEN_TMEIE BIT(0)
#define | CAN_INTEN_RFNEIE0 BIT(1)
#define | CAN_INTEN_RFFIE0 BIT(2)
#define | CAN_INTEN_RFOIE0 BIT(3)
#define | CAN_INTEN_RFNEIE1 BIT(4)
#define | CAN_INTEN_RFFIE1 BIT(5)
#define | CAN_INTEN_RFOIE1 BIT(6)
#define | CAN_INTEN_WERRIE BIT(8)
#define | CAN_INTEN_PERRIE BIT(9)
#define | CAN_INTEN_BOIE BIT(10)
#define | CAN_INTEN_ERRNIE BIT(11)
#define | CAN_INTEN_ERRIE BIT(15)
#define | CAN_INTEN_WIE BIT(16)
#define | CAN_INTEN_SLPWIE BIT(17)
#define | CAN_ERR_WERR BIT(0)
#define | CAN_ERR_PERR BIT(1)
#define | CAN_ERR_BOERR BIT(2)
#define | CAN_ERR_ERRN BITS(4,6)
#define | CAN_ERR_TECNT BITS(16,23)
#define | CAN_ERR_RECNT BITS(24,31)
#define | CAN_BT_BAUDPSC BITS(0,9)
#define | CAN_BT_BS1 BITS(16,19)
#define | CAN_BT_BS2 BITS(20,22)
#define | CAN_BT_SJW BITS(24,25)
#define | CAN_BT_LCMOD BIT(30)
#define | CAN_BT_SCMOD BIT(31)
#define | CAN_TMI_TEN BIT(0)
#define | CAN_TMI_FT BIT(1)
#define | CAN_TMI_FF BIT(2)
#define | CAN_TMI_EFID BITS(3,31)
#define | CAN_TMI_SFID BITS(21,31)
#define | CAN_TMP_DLENC BITS(0,3)
#define | CAN_TMP_TSEN BIT(8)
#define | CAN_TMP_TS BITS(16,31)
#define | CAN_TMDATA0_DB0 BITS(0,7)
#define | CAN_TMDATA0_DB1 BITS(8,15)
#define | CAN_TMDATA0_DB2 BITS(16,23)
#define | CAN_TMDATA0_DB3 BITS(24,31)
#define | CAN_TMDATA1_DB4 BITS(0,7)
#define | CAN_TMDATA1_DB5 BITS(8,15)
#define | CAN_TMDATA1_DB6 BITS(16,23)
#define | CAN_TMDATA1_DB7 BITS(24,31)
#define | CAN_RFIFOMI_FT BIT(1)
#define | CAN_RFIFOMI_FF BIT(2)
#define | CAN_RFIFOMI_EFID BITS(3,31)
#define | CAN_RFIFOMI_SFID BITS(21,31)
#define | CAN_RFIFOMP_DLENC BITS(0,3)
#define | CAN_RFIFOMP_FI BITS(8,15)
#define | CAN_RFIFOMP_TS BITS(16,31)
#define | CAN_RFIFOMDATA0_DB0 BITS(0,7)
#define | CAN_RFIFOMDATA0_DB1 BITS(8,15)
#define | CAN_RFIFOMDATA0_DB2 BITS(16,23)
#define | CAN_RFIFOMDATA0_DB3 BITS(24,31)
#define | CAN_RFIFOMDATA1_DB4 BITS(0,7)
#define | CAN_RFIFOMDATA1_DB5 BITS(8,15)
#define | CAN_RFIFOMDATA1_DB6 BITS(16,23)
#define | CAN_RFIFOMDATA1_DB7 BITS(24,31)
#define | CAN_FCTL_FLD BIT(0)
#define | CAN_FCTL_HBC1F BITS(8,13)
#define | CAN_FMCFG_FMOD(regval) BIT(regval)
#define | CAN_FSCFG_FS(regval) BIT(regval)
#define | CAN_FAFIFOR_FAF(regval) BIT(regval)
#define | CAN_FW_FW(regval) BIT(regval)
#define | CAN_FDATA_FD BITS(0,31)
#define | CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define | CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
#define | CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define | CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
#define | CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
#define | CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
#define | CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
#define | STAT_REG_OFFSET ((uint8_t)0x04U)
#define | TSTAT_REG_OFFSET ((uint8_t)0x08U)
#define | RFIFO0_REG_OFFSET ((uint8_t)0x0CU)
#define | RFIFO1_REG_OFFSET ((uint8_t)0x10U)
#define | ERR_REG_OFFSET ((uint8_t)0x18U)
#define | BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
#define | BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
#define | BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
#define | BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
#define | BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
#define | FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
#define | FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
#define | FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
#define | TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
#define | TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
#define | TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
#define | TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
#define | TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
#define | TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
#define | TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
#define | TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
#define | TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
#define | TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
#define | RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31)
#define | RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31)
#define | RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3)
#define | RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15)
#define | RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7)
#define | RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15)
#define | RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23)
#define | RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31)
#define | RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7)
#define | RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15)
#define | RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23)
#define | RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31)
#define | ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
#define | CAN_ERRN_0 ERR_ERRN(0) /* no error */
#define | CAN_ERRN_1 ERR_ERRN(1)
#define | CAN_ERRN_2 ERR_ERRN(2)
#define | CAN_ERRN_3 ERR_ERRN(3)
#define | CAN_ERRN_4 ERR_ERRN(4)
#define | CAN_ERRN_5 ERR_ERRN(5)
#define | CAN_ERRN_6 ERR_ERRN(6)
#define | CAN_ERRN_7 ERR_ERRN(7)
#define | CAN_STATE_PENDING ((uint32_t)0x00000000U)
#define | CAN_NORMAL_MODE ((uint8_t)0x00U)
#define | CAN_LOOPBACK_MODE ((uint8_t)0x01U)
#define | CAN_SILENT_MODE ((uint8_t)0x02U)
#define | CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U)
#define | CAN_BT_SJW_1TQ ((uint8_t)0x00U)
#define | CAN_BT_SJW_2TQ ((uint8_t)0x01U)
#define | CAN_BT_SJW_3TQ ((uint8_t)0x02U)
#define | CAN_BT_SJW_4TQ ((uint8_t)0x03U)
#define | CAN_BT_BS1_1TQ ((uint8_t)0x00U)
#define | CAN_BT_BS1_2TQ ((uint8_t)0x01U)
#define | CAN_BT_BS1_3TQ ((uint8_t)0x02U)
#define | CAN_BT_BS1_4TQ ((uint8_t)0x03U)
#define | CAN_BT_BS1_5TQ ((uint8_t)0x04U)
#define | CAN_BT_BS1_6TQ ((uint8_t)0x05U)
#define | CAN_BT_BS1_7TQ ((uint8_t)0x06U)
#define | CAN_BT_BS1_8TQ ((uint8_t)0x07U)
#define | CAN_BT_BS1_9TQ ((uint8_t)0x08U)
#define | CAN_BT_BS1_10TQ ((uint8_t)0x09U)
#define | CAN_BT_BS1_11TQ ((uint8_t)0x0AU)
#define | CAN_BT_BS1_12TQ ((uint8_t)0x0BU)
#define | CAN_BT_BS1_13TQ ((uint8_t)0x0CU)
#define | CAN_BT_BS1_14TQ ((uint8_t)0x0DU)
#define | CAN_BT_BS1_15TQ ((uint8_t)0x0EU)
#define | CAN_BT_BS1_16TQ ((uint8_t)0x0FU)
#define | CAN_BT_BS2_1TQ ((uint8_t)0x00U)
#define | CAN_BT_BS2_2TQ ((uint8_t)0x01U)
#define | CAN_BT_BS2_3TQ ((uint8_t)0x02U)
#define | CAN_BT_BS2_4TQ ((uint8_t)0x03U)
#define | CAN_BT_BS2_5TQ ((uint8_t)0x04U)
#define | CAN_BT_BS2_6TQ ((uint8_t)0x05U)
#define | CAN_BT_BS2_7TQ ((uint8_t)0x06U)
#define | CAN_BT_BS2_8TQ ((uint8_t)0x07U)
#define | CAN_MAILBOX0 ((uint8_t)0x00U)
#define | CAN_MAILBOX1 ((uint8_t)0x01U)
#define | CAN_MAILBOX2 ((uint8_t)0x02U)
#define | CAN_NOMAILBOX ((uint8_t)0x03U)
#define | CAN_FF_STANDARD ((uint32_t)0x00000000U)
#define | CAN_FF_EXTENDED ((uint32_t)0x00000004U)
#define | CAN_FIFO0 ((uint8_t)0x00U)
#define | CAN_FIFO1 ((uint8_t)0x01U)
#define | CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U)
#define | CAN_SFID_MASK ((uint32_t)0x000007FFU)
#define | CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU)
#define | CAN_MODE_INITIALIZE ((uint8_t)0x01U)
#define | CAN_MODE_NORMAL ((uint8_t)0x02U)
#define | CAN_MODE_SLEEP ((uint8_t)0x04U)
#define | CAN_FILTERBITS_16BIT ((uint8_t)0x00U)
#define | CAN_FILTERBITS_32BIT ((uint8_t)0x01U)
#define | CAN_FILTERMODE_MASK ((uint8_t)0x00U)
#define | CAN_FILTERMODE_LIST ((uint8_t)0x01U)
#define | CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU)
#define | CAN_FT_DATA ((uint32_t)0x00000000U)
#define | CAN_FT_REMOTE ((uint32_t)0x00000002U)
#define | CAN_TIMEOUT ((uint32_t)0x0000FFFFU)
#define | CAN_INT_TME CAN_INTEN_TMEIE
#define | CAN_INT_RFNE0 CAN_INTEN_RFNEIE0
#define | CAN_INT_RFF0 CAN_INTEN_RFFIE0
#define | CAN_INT_RFO0 CAN_INTEN_RFOIE0
#define | CAN_INT_RFNE1 CAN_INTEN_RFNEIE1
#define | CAN_INT_RFF1 CAN_INTEN_RFFIE1
#define | CAN_INT_RFO1 CAN_INTEN_RFOIE1
#define | CAN_INT_WERR CAN_INTEN_WERRIE
#define | CAN_INT_PERR CAN_INTEN_PERRIE
#define | CAN_INT_BO CAN_INTEN_BOIE
#define | CAN_INT_ERRN CAN_INTEN_ERRNIE
#define | CAN_INT_ERR CAN_INTEN_ERRIE
#define | CAN_INT_WAKEUP CAN_INTEN_WIE
#define | CAN_INT_SLPW CAN_INTEN_SLPWIE

Enumerations

enum can_flag_enum {
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U),
CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U),
CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U),
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U)
}
enum can_interrupt_flag_enum {
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U),
CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U),
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U)
}
enum can_error_enum {
CAN_ERROR_NONE = 0, CAN_ERROR_FILL, CAN_ERROR_FORMATE, CAN_ERROR_ACK,
CAN_ERROR_BITRECESSIVE, CAN_ERROR_BITDOMINANTER, CAN_ERROR_CRC, CAN_ERROR_SOFTWARECFG
}
enum can_transmit_state_enum { CAN_TRANSMIT_FAILED = 0, CAN_TRANSMIT_OK = 1, CAN_TRANSMIT_PENDING = 2, CAN_TRANSMIT_NOMAILBOX = 4 }

Functions

void | can_deinit (uint32_t can_periph)
deinitialize CAN More...
ErrStatus | can_init (uint32_t can_periph, can_parameter_struct *can_parameter_init)
initialize CAN More...
void | can_filter_init (can_filter_parameter_struct *can_filter_parameter_init)
initialize CAN filter More...
void | can1_filter_start_bank (uint8_t start_bank)
set CAN1 fliter start bank number More...
void | can_debug_freeze_enable (uint32_t can_periph)
enable CAN debug freeze More...
void | can_debug_freeze_disable (uint32_t can_periph)
disable CAN debug freeze More...
void | can_time_trigger_mode_enable (uint32_t can_periph)
enable CAN time trigger mode More...
void | can_time_trigger_mode_disable (uint32_t can_periph)
disable CAN time trigger mode More...
uint8_t | can_message_transmit (uint32_t can_periph, can_trasnmit_message_struct *transmit_message)
transmit CAN message More...
can_transmit_state_enum | can_transmit_states (uint32_t can_periph, uint8_t mailbox_number)
get CAN transmit state More...
void | can_transmission_stop (uint32_t can_periph, uint8_t mailbox_number)
stop CAN transmission More...
void | can_message_receive (uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message)
CAN receive message. More...
void | can_fifo_release (uint32_t can_periph, uint8_t fifo_number)
release FIFO0 More...
uint8_t | can_receive_message_length_get (uint32_t can_periph, uint8_t fifo_number)
CAN receive message length. More...
ErrStatus | can_working_mode_set (uint32_t can_periph, uint8_t working_mode)
set CAN working mode More...
ErrStatus | can_wakeup (uint32_t can_periph)
wake up CAN More...
can_error_enum | can_error_get (uint32_t can_periph)
get CAN error type More...
uint8_t | can_receive_error_number_get (uint32_t can_periph)
get CAN receive error number More...
uint8_t | can_transmit_error_number_get (uint32_t can_periph)
get CAN transmit error number More...
void | can_interrupt_enable (uint32_t can_periph, uint32_t interrupt)
enable CAN interrupt More...
void | can_interrupt_disable (uint32_t can_periph, uint32_t interrupt)
disable CAN interrupt More...
FlagStatus | can_flag_get (uint32_t can_periph, can_flag_enum flag)
get CAN flag state More...
void | can_flag_clear (uint32_t can_periph, can_flag_enum flag)
clear CAN flag state More...
FlagStatus | can_interrupt_flag_get (uint32_t can_periph, can_interrupt_flag_enum flag)
get CAN interrupt flag state More...
void | can_interrupt_flag_clear (uint32_t can_periph, can_interrupt_flag_enum flag)
clear CAN interrupt flag state More...

Detailed Description

definitions for the CAN

Definition in file gd32f10x_can.h.

Macro Definition Documentation

#define BT_BAUDPSC ( regval ) (BITS(0,9) & ((uint32_t)(regval) << 0))

Definition at line 422 of file gd32f10x_can.h.

#define BT_BS1 ( regval ) (BITS(16,19) & ((uint32_t)(regval) << 16))

Definition at line 425 of file gd32f10x_can.h.

#define BT_BS2 ( regval ) (BITS(20,22) & ((uint32_t)(regval) << 20))

Definition at line 428 of file gd32f10x_can.h.

#define BT_MODE ( regval ) (BITS(30,31) & ((uint32_t)(regval) << 30))

Definition at line 434 of file gd32f10x_can.h.

#define BT_SJW ( regval ) (BITS(24,25) & ((uint32_t)(regval) << 24))

Definition at line 431 of file gd32f10x_can.h.

#define CAN0 CAN_BASE

CAN0 base address

Definition at line 19 of file gd32f10x_can.h.

#define CAN1 (CAN0 + 0x00000400U)

CAN1 base address

Definition at line 20 of file gd32f10x_can.h.

#define CAN_BIT_POS ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 291 of file gd32f10x_can.h.

#define CAN_BIT_POS0 ( val ) (((uint32_t)(val) >> 6) & 0x1FU)

Definition at line 295 of file gd32f10x_can.h.

#define CAN_BIT_POS1 ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 296 of file gd32f10x_can.h.

#define CAN_BT ( canx ) REG32((canx) + 0x1CU)

CAN bit timing register

Definition at line 30 of file gd32f10x_can.h.

#define CAN_BT_BAUDPSC BITS(0,9)

baudrate prescaler

Definition at line 214 of file gd32f10x_can.h.

#define CAN_BT_BS1 BITS(16,19)

bit segment 1

Definition at line 215 of file gd32f10x_can.h.

#define CAN_BT_BS1_10TQ ((uint8_t)0x09U)

10 time quanta

Definition at line 546 of file gd32f10x_can.h.

#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU)

11 time quanta

Definition at line 547 of file gd32f10x_can.h.

#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU)

12 time quanta

Definition at line 548 of file gd32f10x_can.h.

#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU)

13 time quanta

Definition at line 549 of file gd32f10x_can.h.

#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU)

14 time quanta

Definition at line 550 of file gd32f10x_can.h.

#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU)

15 time quanta

Definition at line 551 of file gd32f10x_can.h.

#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU)

16 time quanta

Definition at line 552 of file gd32f10x_can.h.

#define CAN_BT_BS1_1TQ ((uint8_t)0x00U)

1 time quanta

Definition at line 537 of file gd32f10x_can.h.

#define CAN_BT_BS1_2TQ ((uint8_t)0x01U)

2 time quanta

Definition at line 538 of file gd32f10x_can.h.

#define CAN_BT_BS1_3TQ ((uint8_t)0x02U)

3 time quanta

Definition at line 539 of file gd32f10x_can.h.

#define CAN_BT_BS1_4TQ ((uint8_t)0x03U)

4 time quanta

Definition at line 540 of file gd32f10x_can.h.

#define CAN_BT_BS1_5TQ ((uint8_t)0x04U)

5 time quanta

Definition at line 541 of file gd32f10x_can.h.

#define CAN_BT_BS1_6TQ ((uint8_t)0x05U)

6 time quanta

Definition at line 542 of file gd32f10x_can.h.

#define CAN_BT_BS1_7TQ ((uint8_t)0x06U)

7 time quanta

Definition at line 543 of file gd32f10x_can.h.

#define CAN_BT_BS1_8TQ ((uint8_t)0x07U)

8 time quanta

Definition at line 544 of file gd32f10x_can.h.

#define CAN_BT_BS1_9TQ ((uint8_t)0x08U)

9 time quanta

Definition at line 545 of file gd32f10x_can.h.

#define CAN_BT_BS2 BITS(20,22)

bit segment 2

Definition at line 216 of file gd32f10x_can.h.

#define CAN_BT_BS2_1TQ ((uint8_t)0x00U)

1 time quanta

Definition at line 555 of file gd32f10x_can.h.

#define CAN_BT_BS2_2TQ ((uint8_t)0x01U)

2 time quanta

Definition at line 556 of file gd32f10x_can.h.

#define CAN_BT_BS2_3TQ ((uint8_t)0x02U)

3 time quanta

Definition at line 557 of file gd32f10x_can.h.

#define CAN_BT_BS2_4TQ ((uint8_t)0x03U)

4 time quanta

Definition at line 558 of file gd32f10x_can.h.

#define CAN_BT_BS2_5TQ ((uint8_t)0x04U)

5 time quanta

Definition at line 559 of file gd32f10x_can.h.

#define CAN_BT_BS2_6TQ ((uint8_t)0x05U)

6 time quanta

Definition at line 560 of file gd32f10x_can.h.

#define CAN_BT_BS2_7TQ ((uint8_t)0x06U)

7 time quanta

Definition at line 561 of file gd32f10x_can.h.

#define CAN_BT_BS2_8TQ ((uint8_t)0x07U)

8 time quanta

Definition at line 562 of file gd32f10x_can.h.

#define CAN_BT_LCMOD BIT(30)

loopback communication mode

Definition at line 218 of file gd32f10x_can.h.

#define CAN_BT_SCMOD BIT(31)

silent communication mode

Definition at line 219 of file gd32f10x_can.h.

#define CAN_BT_SJW BITS(24,25)

resynchronization jump width

Definition at line 217 of file gd32f10x_can.h.

#define CAN_BT_SJW_1TQ ((uint8_t)0x00U)

1 time quanta

Definition at line 531 of file gd32f10x_can.h.

#define CAN_BT_SJW_2TQ ((uint8_t)0x01U)

2 time quanta

Definition at line 532 of file gd32f10x_can.h.

#define CAN_BT_SJW_3TQ ((uint8_t)0x02U)

3 time quanta

Definition at line 533 of file gd32f10x_can.h.

#define CAN_BT_SJW_4TQ ((uint8_t)0x03U)

4 time quanta

Definition at line 534 of file gd32f10x_can.h.

#define CAN_CTL ( canx ) REG32((canx) + 0x00U)

CAN control register

Definition at line 23 of file gd32f10x_can.h.

#define CAN_CTL_ABOR BIT(6)

automatic bus-off recovery

Definition at line 137 of file gd32f10x_can.h.

#define CAN_CTL_ARD BIT(4)

automatic retransmission disable

Definition at line 135 of file gd32f10x_can.h.

#define CAN_CTL_AWU BIT(5)

automatic wakeup

Definition at line 136 of file gd32f10x_can.h.

#define CAN_CTL_DFZ BIT(16)

CAN debug freeze

Definition at line 140 of file gd32f10x_can.h.

#define CAN_CTL_IWMOD BIT(0)

initial working mode

Definition at line 131 of file gd32f10x_can.h.

#define CAN_CTL_RFOD BIT(3)

receive FIFO overwrite disable

Definition at line 134 of file gd32f10x_can.h.

#define CAN_CTL_SLPWMOD BIT(1)

sleep working mode

Definition at line 132 of file gd32f10x_can.h.

#define CAN_CTL_SWRST BIT(15)

CAN software reset

Definition at line 139 of file gd32f10x_can.h.

#define CAN_CTL_TFO BIT(2)

transmit FIFO order

Definition at line 133 of file gd32f10x_can.h.

#define CAN_CTL_TTC BIT(7)

time triggered communication

Definition at line 138 of file gd32f10x_can.h.

#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU)

mask of extended identifier

Definition at line 582 of file gd32f10x_can.h.

#define CAN_ERR ( canx ) REG32((canx) + 0x18U)

CAN error register

Definition at line 29 of file gd32f10x_can.h.

#define CAN_ERR_BOERR BIT(2)

bus-off error

Definition at line 208 of file gd32f10x_can.h.

#define CAN_ERR_ERRN BITS(4,6)

error number

Definition at line 209 of file gd32f10x_can.h.

#define CAN_ERR_PERR BIT(1)

passive error

Definition at line 207 of file gd32f10x_can.h.

#define CAN_ERR_RECNT BITS(24,31)

receive error count

Definition at line 211 of file gd32f10x_can.h.

#define CAN_ERR_TECNT BITS(16,23)

transmit error count

Definition at line 210 of file gd32f10x_can.h.

#define CAN_ERR_WERR BIT(0)

warning error

Definition at line 206 of file gd32f10x_can.h.

#define CAN_ERRN_0 ERR_ERRN(0) /* no error */

Definition at line 513 of file gd32f10x_can.h.

#define CAN_ERRN_1 ERR_ERRN(1)

fill error

Definition at line 514 of file gd32f10x_can.h.

#define CAN_ERRN_2 ERR_ERRN(2)

format error

Definition at line 515 of file gd32f10x_can.h.

#define CAN_ERRN_3 ERR_ERRN(3)

ACK error

Definition at line 516 of file gd32f10x_can.h.

#define CAN_ERRN_4 ERR_ERRN(4)

bit recessive error

Definition at line 517 of file gd32f10x_can.h.

#define CAN_ERRN_5 ERR_ERRN(5)

bit dominant error

Definition at line 518 of file gd32f10x_can.h.

#define CAN_ERRN_6 ERR_ERRN(6)

CRC error

Definition at line 519 of file gd32f10x_can.h.

#define CAN_ERRN_7 ERR_ERRN(7)

software error

Definition at line 520 of file gd32f10x_can.h.

#define CAN_F0DATA0 ( canx ) REG32((canx) + 0x240U)

CAN filter 0 data 0 register

Definition at line 56 of file gd32f10x_can.h.

#define CAN_F0DATA1 ( canx ) REG32((canx) + 0x244U)

CAN filter 0 data 1 register

Definition at line 84 of file gd32f10x_can.h.

#define CAN_F10DATA0 ( canx ) REG32((canx) + 0x290U)

CAN filter 10 data 0 register

Definition at line 66 of file gd32f10x_can.h.

#define CAN_F10DATA1 ( canx ) REG32((canx) + 0x294U)

CAN filter 10 data 1 register

Definition at line 94 of file gd32f10x_can.h.

#define CAN_F11DATA0 ( canx ) REG32((canx) + 0x298U)

CAN filter 11 data 0 register

Definition at line 67 of file gd32f10x_can.h.

#define CAN_F11DATA1 ( canx ) REG32((canx) + 0x29CU)

CAN filter 11 data 1 register

Definition at line 95 of file gd32f10x_can.h.

#define CAN_F12DATA0 ( canx ) REG32((canx) + 0x2A0U)

CAN filter 12 data 0 register

Definition at line 68 of file gd32f10x_can.h.

#define CAN_F12DATA1 ( canx ) REG32((canx) + 0x2A4U)

CAN filter 12 data 1 register

Definition at line 96 of file gd32f10x_can.h.

#define CAN_F13DATA0 ( canx ) REG32((canx) + 0x2A8U)

CAN filter 13 data 0 register

Definition at line 69 of file gd32f10x_can.h.

#define CAN_F13DATA1 ( canx ) REG32((canx) + 0x2ACU)

CAN filter 13 data 1 register

Definition at line 97 of file gd32f10x_can.h.

#define CAN_F14DATA0 ( canx ) REG32((canx) + 0x2B0U)

CAN filter 14 data 0 register

Definition at line 70 of file gd32f10x_can.h.

#define CAN_F14DATA1 ( canx ) REG32((canx) + 0x2B4U)

CAN filter 14 data 1 register

Definition at line 98 of file gd32f10x_can.h.

#define CAN_F15DATA0 ( canx ) REG32((canx) + 0x2B8U)

CAN filter 15 data 0 register

Definition at line 71 of file gd32f10x_can.h.

#define CAN_F15DATA1 ( canx ) REG32((canx) + 0x2BCU)

CAN filter 15 data 1 register

Definition at line 99 of file gd32f10x_can.h.

#define CAN_F16DATA0 ( canx ) REG32((canx) + 0x2C0U)

CAN filter 16 data 0 register

Definition at line 72 of file gd32f10x_can.h.

#define CAN_F16DATA1 ( canx ) REG32((canx) + 0x2C4U)

CAN filter 16 data 1 register

Definition at line 100 of file gd32f10x_can.h.

#define CAN_F17DATA0 ( canx ) REG32((canx) + 0x2C8U)

CAN filter 17 data 0 register

Definition at line 73 of file gd32f10x_can.h.

#define CAN_F17DATA1 ( canx ) REG32((canx) + 0x24CU)

CAN filter 17 data 1 register

Definition at line 101 of file gd32f10x_can.h.

#define CAN_F18DATA0 ( canx ) REG32((canx) + 0x2D0U)

CAN filter 18 data 0 register

Definition at line 74 of file gd32f10x_can.h.

#define CAN_F18DATA1 ( canx ) REG32((canx) + 0x2D4U)

CAN filter 18 data 1 register

Definition at line 102 of file gd32f10x_can.h.

#define CAN_F19DATA0 ( canx ) REG32((canx) + 0x2D8U)

CAN filter 19 data 0 register

Definition at line 75 of file gd32f10x_can.h.

#define CAN_F19DATA1 ( canx ) REG32((canx) + 0x2DCU)

CAN filter 19 data 1 register

Definition at line 103 of file gd32f10x_can.h.

#define CAN_F1DATA0 ( canx ) REG32((canx) + 0x248U)

CAN filter 1 data 0 register

Definition at line 57 of file gd32f10x_can.h.

#define CAN_F1DATA1 ( canx ) REG32((canx) + 0x24CU)

CAN filter 1 data 1 register

Definition at line 85 of file gd32f10x_can.h.

#define CAN_F20DATA0 ( canx ) REG32((canx) + 0x2E0U)

CAN filter 20 data 0 register

Definition at line 76 of file gd32f10x_can.h.

#define CAN_F20DATA1 ( canx ) REG32((canx) + 0x2E4U)

CAN filter 20 data 1 register

Definition at line 104 of file gd32f10x_can.h.

#define CAN_F21DATA0 ( canx ) REG32((canx) + 0x2E8U)

CAN filter 21 data 0 register

Definition at line 77 of file gd32f10x_can.h.

#define CAN_F21DATA1 ( canx ) REG32((canx) + 0x2ECU)

CAN filter 21 data 1 register

Definition at line 105 of file gd32f10x_can.h.

#define CAN_F22DATA0 ( canx ) REG32((canx) + 0x2F0U)

CAN filter 22 data 0 register

Definition at line 78 of file gd32f10x_can.h.

#define CAN_F22DATA1 ( canx ) REG32((canx) + 0x2F4U)

CAN filter 22 data 1 register

Definition at line 106 of file gd32f10x_can.h.

#define CAN_F23DATA0 ( canx ) REG32((canx) + 0x3F8U)

CAN filter 23 data 0 register

Definition at line 79 of file gd32f10x_can.h.

#define CAN_F23DATA1 ( canx ) REG32((canx) + 0x2FCU)

CAN filter 23 data 1 register

Definition at line 107 of file gd32f10x_can.h.

#define CAN_F24DATA0 ( canx ) REG32((canx) + 0x300U)

CAN filter 24 data 0 register

Definition at line 80 of file gd32f10x_can.h.

#define CAN_F24DATA1 ( canx ) REG32((canx) + 0x304U)

CAN filter 24 data 1 register

Definition at line 108 of file gd32f10x_can.h.

#define CAN_F25DATA0 ( canx ) REG32((canx) + 0x308U)

CAN filter 25 data 0 register

Definition at line 81 of file gd32f10x_can.h.

#define CAN_F25DATA1 ( canx ) REG32((canx) + 0x30CU)

CAN filter 25 data 1 register

Definition at line 109 of file gd32f10x_can.h.

#define CAN_F26DATA0 ( canx ) REG32((canx) + 0x310U)

CAN filter 26 data 0 register

Definition at line 82 of file gd32f10x_can.h.

#define CAN_F26DATA1 ( canx ) REG32((canx) + 0x314U)

CAN filter 26 data 1 register

Definition at line 110 of file gd32f10x_can.h.

#define CAN_F27DATA0 ( canx ) REG32((canx) + 0x318U)

CAN filter 27 data 0 register

Definition at line 83 of file gd32f10x_can.h.

#define CAN_F27DATA1 ( canx ) REG32((canx) + 0x31CU)

CAN filter 27 data 1 register

Definition at line 111 of file gd32f10x_can.h.

#define CAN_F2DATA0 ( canx ) REG32((canx) + 0x250U)

CAN filter 2 data 0 register

Definition at line 58 of file gd32f10x_can.h.

#define CAN_F2DATA1 ( canx ) REG32((canx) + 0x254U)

CAN filter 2 data 1 register

Definition at line 86 of file gd32f10x_can.h.

#define CAN_F3DATA0 ( canx ) REG32((canx) + 0x258U)

CAN filter 3 data 0 register

Definition at line 59 of file gd32f10x_can.h.

#define CAN_F3DATA1 ( canx ) REG32((canx) + 0x25CU)

CAN filter 3 data 1 register

Definition at line 87 of file gd32f10x_can.h.

#define CAN_F4DATA0 ( canx ) REG32((canx) + 0x260U)

CAN filter 4 data 0 register

Definition at line 60 of file gd32f10x_can.h.

#define CAN_F4DATA1 ( canx ) REG32((canx) + 0x264U)

CAN filter 4 data 1 register

Definition at line 88 of file gd32f10x_can.h.

#define CAN_F5DATA0 ( canx ) REG32((canx) + 0x268U)

CAN filter 5 data 0 register

Definition at line 61 of file gd32f10x_can.h.

#define CAN_F5DATA1 ( canx ) REG32((canx) + 0x26CU)

CAN filter 5 data 1 register

Definition at line 89 of file gd32f10x_can.h.

#define CAN_F6DATA0 ( canx ) REG32((canx) + 0x270U)

CAN filter 6 data 0 register

Definition at line 62 of file gd32f10x_can.h.

#define CAN_F6DATA1 ( canx ) REG32((canx) + 0x274U)

CAN filter 6 data 1 register

Definition at line 90 of file gd32f10x_can.h.

#define CAN_F7DATA0 ( canx ) REG32((canx) + 0x278U)

CAN filter 7 data 0 register

Definition at line 63 of file gd32f10x_can.h.

#define CAN_F7DATA1 ( canx ) REG32((canx) + 0x27CU)

CAN filter 7 data 1 register

Definition at line 91 of file gd32f10x_can.h.

#define CAN_F8DATA0 ( canx ) REG32((canx) + 0x280U)

CAN filter 8 data 0 register

Definition at line 64 of file gd32f10x_can.h.

#define CAN_F8DATA1 ( canx ) REG32((canx) + 0x284U)

CAN filter 8 data 1 register

Definition at line 92 of file gd32f10x_can.h.

#define CAN_F9DATA0 ( canx ) REG32((canx) + 0x288U)

CAN filter 9 data 0 register

Definition at line 65 of file gd32f10x_can.h.

#define CAN_F9DATA1 ( canx ) REG32((canx) + 0x28CU)

CAN filter 9 data 1 register

Definition at line 93 of file gd32f10x_can.h.

#define CAN_FAFIFO ( canx ) REG32((canx) + 0x214U)

CAN filter associated FIFO register

Definition at line 54 of file gd32f10x_can.h.

#define CAN_FAFIFOR_FAF ( regval ) BIT(regval)

filter associated with FIFO

Definition at line 279 of file gd32f10x_can.h.

#define CAN_FCTL ( canx ) REG32((canx) + 0x200U)

CAN filter control register

Definition at line 51 of file gd32f10x_can.h.

#define CAN_FCTL_FLD BIT(0)

filter lock disable

Definition at line 269 of file gd32f10x_can.h.

#define CAN_FCTL_HBC1F BITS(8,13)

header bank of CAN1 filter

Definition at line 270 of file gd32f10x_can.h.

#define CAN_FDATA0 | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U)

CAN filter data 0 register

Definition at line 120 of file gd32f10x_can.h.

#define CAN_FDATA1 | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U)

CAN filter data 1 register

Definition at line 121 of file gd32f10x_can.h.

#define CAN_FDATA_FD BITS(0,31)

filter data

Definition at line 285 of file gd32f10x_can.h.

#define CAN_FF_EXTENDED ((uint32_t)0x00000004U)

extended frame

Definition at line 572 of file gd32f10x_can.h.

#define CAN_FF_STANDARD ((uint32_t)0x00000000U)

standard frame

Definition at line 571 of file gd32f10x_can.h.

#define CAN_FIFO0 ((uint8_t)0x00U)

receive FIFO0

Definition at line 575 of file gd32f10x_can.h.

#define CAN_FIFO1 ((uint8_t)0x01U)

receive FIFO1

Definition at line 576 of file gd32f10x_can.h.

#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU)

Definition at line 598 of file gd32f10x_can.h.

#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U)

CAN filter 16 bits

Definition at line 590 of file gd32f10x_can.h.

#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U)

CAN filter 32 bits

Definition at line 591 of file gd32f10x_can.h.

#define CAN_FILTERMODE_LIST ((uint8_t)0x01U)

list mode

Definition at line 595 of file gd32f10x_can.h.

#define CAN_FILTERMODE_MASK ((uint8_t)0x00U)

mask mode

Definition at line 594 of file gd32f10x_can.h.

#define CAN_FMCFG ( canx ) REG32((canx) + 0x204U)

CAN filter mode register

Definition at line 52 of file gd32f10x_can.h.

#define CAN_FMCFG_FMOD ( regval ) BIT(regval)

filter mode, list or mask

Definition at line 273 of file gd32f10x_can.h.

#define CAN_FSCFG ( canx ) REG32((canx) + 0x20CU)

CAN filter scale register

Definition at line 53 of file gd32f10x_can.h.

#define CAN_FSCFG_FS ( regval ) BIT(regval)

filter scale, 32 bits or 16 bits

Definition at line 276 of file gd32f10x_can.h.

#define CAN_FT_DATA ((uint32_t)0x00000000U)

data frame

Definition at line 601 of file gd32f10x_can.h.

#define CAN_FT_REMOTE ((uint32_t)0x00000002U)

remote frame

Definition at line 602 of file gd32f10x_can.h.

#define CAN_FW ( canx ) REG32((canx) + 0x21CU)

CAN filter working register

Definition at line 55 of file gd32f10x_can.h.

#define CAN_FW_FW ( regval ) BIT(regval)

filter working

Definition at line 282 of file gd32f10x_can.h.

#define CAN_INT_BO CAN_INTEN_BOIE

bus-off interrupt enable

Definition at line 617 of file gd32f10x_can.h.

#define CAN_INT_ERR CAN_INTEN_ERRIE

error interrupt enable

Definition at line 619 of file gd32f10x_can.h.

#define CAN_INT_ERRN CAN_INTEN_ERRNIE

error number interrupt enable

Definition at line 618 of file gd32f10x_can.h.

#define CAN_INT_PERR CAN_INTEN_PERRIE

passive error interrupt enable

Definition at line 616 of file gd32f10x_can.h.

#define CAN_INT_RFF0 CAN_INTEN_RFFIE0

receive FIFO0 full interrupt enable

Definition at line 610 of file gd32f10x_can.h.

#define CAN_INT_RFF1 CAN_INTEN_RFFIE1

receive FIFO1 full interrupt enable

Definition at line 613 of file gd32f10x_can.h.

#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0

receive FIFO0 not empty interrupt enable

Definition at line 609 of file gd32f10x_can.h.

#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1

receive FIFO1 not empty interrupt enable

Definition at line 612 of file gd32f10x_can.h.

#define CAN_INT_RFO0 CAN_INTEN_RFOIE0

receive FIFO0 overfull interrupt enable

Definition at line 611 of file gd32f10x_can.h.

#define CAN_INT_RFO1 CAN_INTEN_RFOIE1

receive FIFO1 overfull interrupt enable

Definition at line 614 of file gd32f10x_can.h.

#define CAN_INT_SLPW CAN_INTEN_SLPWIE

sleep working interrupt enable

Definition at line 621 of file gd32f10x_can.h.

#define CAN_INT_TME CAN_INTEN_TMEIE

transmit mailbox empty interrupt enable

Definition at line 608 of file gd32f10x_can.h.

#define CAN_INT_WAKEUP CAN_INTEN_WIE

wakeup interrupt enable

Definition at line 620 of file gd32f10x_can.h.

#define CAN_INT_WERR CAN_INTEN_WERRIE

warning error interrupt enable

Definition at line 615 of file gd32f10x_can.h.

#define CAN_INTEN ( canx ) REG32((canx) + 0x14U)

CAN interrupt enable register

Definition at line 28 of file gd32f10x_can.h.

#define CAN_INTEN_BOIE BIT(10)

bus-off interrupt enable

Definition at line 199 of file gd32f10x_can.h.

#define CAN_INTEN_ERRIE BIT(15)

error interrupt enable

Definition at line 201 of file gd32f10x_can.h.

#define CAN_INTEN_ERRNIE BIT(11)

error number interrupt enable

Definition at line 200 of file gd32f10x_can.h.

#define CAN_INTEN_PERRIE BIT(9)

passive error interrupt enable

Definition at line 198 of file gd32f10x_can.h.

#define CAN_INTEN_RFFIE0 BIT(2)

receive FIFO0 full interrupt enable

Definition at line 192 of file gd32f10x_can.h.

#define CAN_INTEN_RFFIE1 BIT(5)

receive FIFO1 full interrupt enable

Definition at line 195 of file gd32f10x_can.h.

#define CAN_INTEN_RFNEIE0 BIT(1)

receive FIFO0 not empty interrupt enable

Definition at line 191 of file gd32f10x_can.h.

#define CAN_INTEN_RFNEIE1 BIT(4)

receive FIFO1 not empty interrupt enable

Definition at line 194 of file gd32f10x_can.h.

#define CAN_INTEN_RFOIE0 BIT(3)

receive FIFO0 overfull interrupt enable

Definition at line 193 of file gd32f10x_can.h.

#define CAN_INTEN_RFOIE1 BIT(6)

receive FIFO1 overfull interrupt enable

Definition at line 196 of file gd32f10x_can.h.

#define CAN_INTEN_SLPWIE BIT(17)

sleep working interrupt enable

Definition at line 203 of file gd32f10x_can.h.

#define CAN_INTEN_TMEIE BIT(0)

transmit mailbox empty interrupt enable

Definition at line 190 of file gd32f10x_can.h.

#define CAN_INTEN_WERRIE BIT(8)

warning error interrupt enable

Definition at line 197 of file gd32f10x_can.h.

#define CAN_INTEN_WIE BIT(16)

wakeup interrupt enable

Definition at line 202 of file gd32f10x_can.h.

#define CAN_LOOPBACK_MODE ((uint8_t)0x01U)

loopback communication mode

Definition at line 526 of file gd32f10x_can.h.

#define CAN_MAILBOX0 ((uint8_t)0x00U)

mailbox0

Definition at line 565 of file gd32f10x_can.h.

#define CAN_MAILBOX1 ((uint8_t)0x01U)

mailbox1

Definition at line 566 of file gd32f10x_can.h.

#define CAN_MAILBOX2 ((uint8_t)0x02U)

mailbox2

Definition at line 567 of file gd32f10x_can.h.

#define CAN_MODE_INITIALIZE ((uint8_t)0x01U)

CAN initialize mode

Definition at line 585 of file gd32f10x_can.h.

#define CAN_MODE_NORMAL ((uint8_t)0x02U)

CAN normal mode

Definition at line 586 of file gd32f10x_can.h.

#define CAN_MODE_SLEEP ((uint8_t)0x04U)

CAN sleep mode

Definition at line 587 of file gd32f10x_can.h.

#define CAN_NOMAILBOX ((uint8_t)0x03U)

no mailbox empty

Definition at line 568 of file gd32f10x_can.h.

#define CAN_NORMAL_MODE ((uint8_t)0x00U)

normal communication mode

Definition at line 525 of file gd32f10x_can.h.

#define CAN_REG_VAL | ( | canx,
 |  | offset
 | ) | (REG32((canx) + ((uint32_t)(offset) >> 6)))

Definition at line 290 of file gd32f10x_can.h.

#define CAN_REG_VALS | ( | canx,
 |  | offset
 | ) | (REG32((canx) + ((uint32_t)(offset) >> 12)))

Definition at line 294 of file gd32f10x_can.h.

#define CAN_REGIDX_BIT | ( | regidx,
 |  | bitpos
 | ) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))

Definition at line 289 of file gd32f10x_can.h.

#define CAN_REGIDX_BITS | ( | regidx,
 |  | bitpos0,
 |  | bitpos1
 | ) | (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))

Definition at line 293 of file gd32f10x_can.h.

#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U)

mask for frame number in receive FIFOx

Definition at line 579 of file gd32f10x_can.h.

#define CAN_RFIFO0 ( canx ) REG32((canx) + 0x0CU)

CAN receive FIFO0 register

Definition at line 26 of file gd32f10x_can.h.

#define CAN_RFIFO0_RFD0 BIT(5)

receive FIFO0 dequeue

Definition at line 181 of file gd32f10x_can.h.

#define CAN_RFIFO0_RFF0 BIT(3)

receive FIFO0 full

Definition at line 179 of file gd32f10x_can.h.

#define CAN_RFIFO0_RFL0 BITS(0,1)

receive FIFO0 length

Definition at line 178 of file gd32f10x_can.h.

#define CAN_RFIFO0_RFO0 BIT(4)

receive FIFO0 overfull

Definition at line 180 of file gd32f10x_can.h.

#define CAN_RFIFO1 ( canx ) REG32((canx) + 0x10U)

CAN receive FIFO1 register

Definition at line 27 of file gd32f10x_can.h.

#define CAN_RFIFO1_RFD1 BIT(5)

receive FIFO1 dequeue

Definition at line 187 of file gd32f10x_can.h.

#define CAN_RFIFO1_RFF1 BIT(3)

receive FIFO1 full

Definition at line 185 of file gd32f10x_can.h.

#define CAN_RFIFO1_RFL1 BITS(0,1)

receive FIFO1 length

Definition at line 184 of file gd32f10x_can.h.

#define CAN_RFIFO1_RFO1 BIT(4)

receive FIFO1 overfull

Definition at line 186 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA0 | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x1B8U + ((bank) * 0x10U))

CAN receive FIFO mailbox data0 register

Definition at line 126 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA00 ( canx ) REG32((canx) + 0x1B8U)

CAN receive FIFO0 mailbox data0 register

Definition at line 45 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA01 ( canx ) REG32((canx) + 0x1C8U)

CAN receive FIFO1 mailbox data0 register

Definition at line 49 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA0_DB0 BITS(0,7)

receive data byte 0

Definition at line 257 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA0_DB1 BITS(8,15)

receive data byte 1

Definition at line 258 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA0_DB2 BITS(16,23)

receive data byte 2

Definition at line 259 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA0_DB3 BITS(24,31)

receive data byte 3

Definition at line 260 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA1 | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x1BCU + ((bank) * 0x10U))

CAN receive FIFO mailbox data1 register

Definition at line 127 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA10 ( canx ) REG32((canx) + 0x1BCU)

CAN receive FIFO0 mailbox data1 register

Definition at line 46 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA11 ( canx ) REG32((canx) + 0x1CCU)

CAN receive FIFO1 mailbox data1 register

Definition at line 50 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA1_DB4 BITS(0,7)

receive data byte 4

Definition at line 263 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA1_DB5 BITS(8,15)

receive data byte 5

Definition at line 264 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA1_DB6 BITS(16,23)

receive data byte 6

Definition at line 265 of file gd32f10x_can.h.

#define CAN_RFIFOMDATA1_DB7 BITS(24,31)

receive data byte 7

Definition at line 266 of file gd32f10x_can.h.

#define CAN_RFIFOMI | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x1B0U + ((bank) * 0x10U))

CAN receive FIFO mailbox identifier register

Definition at line 124 of file gd32f10x_can.h.

#define CAN_RFIFOMI0 ( canx ) REG32((canx) + 0x1B0U)

CAN receive FIFO0 mailbox identifier register

Definition at line 43 of file gd32f10x_can.h.

#define CAN_RFIFOMI1 ( canx ) REG32((canx) + 0x1C0U)

CAN receive FIFO1 mailbox identifier register

Definition at line 47 of file gd32f10x_can.h.

#define CAN_RFIFOMI_EFID BITS(3,31)

the frame identifier

Definition at line 248 of file gd32f10x_can.h.

#define CAN_RFIFOMI_FF BIT(2)

frame format

Definition at line 247 of file gd32f10x_can.h.

#define CAN_RFIFOMI_FT BIT(1)

frame type

Definition at line 246 of file gd32f10x_can.h.

#define CAN_RFIFOMI_SFID BITS(21,31)

the frame identifier

Definition at line 249 of file gd32f10x_can.h.

#define CAN_RFIFOMP | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x1B4U + ((bank) * 0x10U))

CAN receive FIFO mailbox property register

Definition at line 125 of file gd32f10x_can.h.

#define CAN_RFIFOMP0 ( canx ) REG32((canx) + 0x1B4U)

CAN receive FIFO0 mailbox property register

Definition at line 44 of file gd32f10x_can.h.

#define CAN_RFIFOMP1 ( canx ) REG32((canx) + 0x1C4U)

CAN receive FIFO1 mailbox property register

Definition at line 48 of file gd32f10x_can.h.

#define CAN_RFIFOMP_DLENC BITS(0,3)

receive data length code

Definition at line 252 of file gd32f10x_can.h.

#define CAN_RFIFOMP_FI BITS(8,15)

filter index

Definition at line 253 of file gd32f10x_can.h.

#define CAN_RFIFOMP_TS BITS(16,31)

time stamp

Definition at line 254 of file gd32f10x_can.h.

#define CAN_SFID_MASK ((uint32_t)0x000007FFU)

mask of standard identifier

Definition at line 581 of file gd32f10x_can.h.

#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U)

loopback and silent communication mode

Definition at line 528 of file gd32f10x_can.h.

#define CAN_SILENT_MODE ((uint8_t)0x02U)

silent communication mode

Definition at line 527 of file gd32f10x_can.h.

#define CAN_STAT ( canx ) REG32((canx) + 0x04U)

CAN status register

Definition at line 24 of file gd32f10x_can.h.

#define CAN_STAT_ERRIF BIT(2)

error interrupt flag

Definition at line 145 of file gd32f10x_can.h.

#define CAN_STAT_IWS BIT(0)

initial working state

Definition at line 143 of file gd32f10x_can.h.

#define CAN_STAT_LASTRX BIT(10)

last sample value of rx pin

Definition at line 150 of file gd32f10x_can.h.

#define CAN_STAT_RS BIT(9)

receiving state

Definition at line 149 of file gd32f10x_can.h.

#define CAN_STAT_RXL BIT(11)

CAN rx signal

Definition at line 151 of file gd32f10x_can.h.

#define CAN_STAT_SLPIF BIT(4)

status change interrupt flag of sleep working mode entering

Definition at line 147 of file gd32f10x_can.h.

#define CAN_STAT_SLPWS BIT(1)

sleep working state

Definition at line 144 of file gd32f10x_can.h.

#define CAN_STAT_TS BIT(8)

transmitting state

Definition at line 148 of file gd32f10x_can.h.

#define CAN_STAT_WUIF BIT(3)

status change interrupt flag of wakeup from sleep working mode

Definition at line 146 of file gd32f10x_can.h.

#define CAN_STATE_PENDING ((uint32_t)0x00000000U)

CAN pending

Definition at line 522 of file gd32f10x_can.h.

#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU)

timeout value

Definition at line 605 of file gd32f10x_can.h.

#define CAN_TMDATA0 | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x188U + ((bank) * 0x10U))

CAN transmit mailbox data0 register

Definition at line 116 of file gd32f10x_can.h.

#define CAN_TMDATA00 ( canx ) REG32((canx) + 0x188U)

CAN transmit mailbox0 data0 register

Definition at line 33 of file gd32f10x_can.h.

#define CAN_TMDATA01 ( canx ) REG32((canx) + 0x198U)

CAN transmit mailbox1 data0 register

Definition at line 37 of file gd32f10x_can.h.

#define CAN_TMDATA02 ( canx ) REG32((canx) + 0x1A8U)

CAN transmit mailbox2 data0 register

Definition at line 41 of file gd32f10x_can.h.

#define CAN_TMDATA0_DB0 BITS(0,7)

transmit data byte 0

Definition at line 234 of file gd32f10x_can.h.

#define CAN_TMDATA0_DB1 BITS(8,15)

transmit data byte 1

Definition at line 235 of file gd32f10x_can.h.

#define CAN_TMDATA0_DB2 BITS(16,23)

transmit data byte 2

Definition at line 236 of file gd32f10x_can.h.

#define CAN_TMDATA0_DB3 BITS(24,31)

transmit data byte 3

Definition at line 237 of file gd32f10x_can.h.

#define CAN_TMDATA1 | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x18CU + ((bank) * 0x10U))

CAN transmit mailbox data1 register

Definition at line 117 of file gd32f10x_can.h.

#define CAN_TMDATA10 ( canx ) REG32((canx) + 0x18CU)

CAN transmit mailbox0 data1 register

Definition at line 34 of file gd32f10x_can.h.

#define CAN_TMDATA11 ( canx ) REG32((canx) + 0x19CU)

CAN transmit mailbox1 data1 register

Definition at line 38 of file gd32f10x_can.h.

#define CAN_TMDATA12 ( canx ) REG32((canx) + 0x1ACU)

CAN transmit mailbox2 data1 register

Definition at line 42 of file gd32f10x_can.h.

#define CAN_TMDATA1_DB4 BITS(0,7)

transmit data byte 4

Definition at line 240 of file gd32f10x_can.h.

#define CAN_TMDATA1_DB5 BITS(8,15)

transmit data byte 5

Definition at line 241 of file gd32f10x_can.h.

#define CAN_TMDATA1_DB6 BITS(16,23)

transmit data byte 6

Definition at line 242 of file gd32f10x_can.h.

#define CAN_TMDATA1_DB7 BITS(24,31)

transmit data byte 7

Definition at line 243 of file gd32f10x_can.h.

#define CAN_TMI | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x180U + ((bank) * 0x10U))

CAN transmit mailbox identifier register

Definition at line 114 of file gd32f10x_can.h.

#define CAN_TMI0 ( canx ) REG32((canx) + 0x180U)

CAN transmit mailbox0 identifier register

Definition at line 31 of file gd32f10x_can.h.

#define CAN_TMI1 ( canx ) REG32((canx) + 0x190U)

CAN transmit mailbox1 identifier register

Definition at line 35 of file gd32f10x_can.h.

#define CAN_TMI2 ( canx ) REG32((canx) + 0x1A0U)

CAN transmit mailbox2 identifier register

Definition at line 39 of file gd32f10x_can.h.

#define CAN_TMI_EFID BITS(3,31)

the frame identifier

Definition at line 225 of file gd32f10x_can.h.

#define CAN_TMI_FF BIT(2)

frame format

Definition at line 224 of file gd32f10x_can.h.

#define CAN_TMI_FT BIT(1)

frame type

Definition at line 223 of file gd32f10x_can.h.

#define CAN_TMI_SFID BITS(21,31)

the frame identifier

Definition at line 226 of file gd32f10x_can.h.

#define CAN_TMI_TEN BIT(0)

transmit enable

Definition at line 222 of file gd32f10x_can.h.

#define CAN_TMP | ( | canx,
 |  | bank
 | ) | REG32((canx) + 0x184U + ((bank) * 0x10U))

CAN transmit mailbox property register

Definition at line 115 of file gd32f10x_can.h.

#define CAN_TMP0 ( canx ) REG32((canx) + 0x184U)

CAN transmit mailbox0 property register

Definition at line 32 of file gd32f10x_can.h.

#define CAN_TMP1 ( canx ) REG32((canx) + 0x194U)

CAN transmit mailbox1 property register

Definition at line 36 of file gd32f10x_can.h.

#define CAN_TMP2 ( canx ) REG32((canx) + 0x1A4U)

CAN transmit mailbox2 property register

Definition at line 40 of file gd32f10x_can.h.

#define CAN_TMP_DLENC BITS(0,3)

data length code

Definition at line 229 of file gd32f10x_can.h.

#define CAN_TMP_TS BITS(16,31)

time stamp

Definition at line 231 of file gd32f10x_can.h.

#define CAN_TMP_TSEN BIT(8)

time stamp enable

Definition at line 230 of file gd32f10x_can.h.

#define CAN_TSTAT ( canx ) REG32((canx) + 0x08U)

CAN transmit status register

Definition at line 25 of file gd32f10x_can.h.

#define CAN_TSTAT_MAL0 BIT(2)

mailbox0 arbitration lost

Definition at line 156 of file gd32f10x_can.h.

#define CAN_TSTAT_MAL1 BIT(10)

mailbox1 arbitration lost

Definition at line 161 of file gd32f10x_can.h.

#define CAN_TSTAT_MAL2 BIT(18)

mailbox2 arbitration lost

Definition at line 166 of file gd32f10x_can.h.

#define CAN_TSTAT_MST0 BIT(7)

mailbox0 stop transmitting

Definition at line 158 of file gd32f10x_can.h.

#define CAN_TSTAT_MST1 BIT(15)

mailbox1 stop transmitting

Definition at line 163 of file gd32f10x_can.h.

#define CAN_TSTAT_MST2 BIT(23)

mailbox2 stop transmitting

Definition at line 168 of file gd32f10x_can.h.

#define CAN_TSTAT_MTE0 BIT(3)

mailbox0 transmit error

Definition at line 157 of file gd32f10x_can.h.

#define CAN_TSTAT_MTE1 BIT(11)

mailbox1 transmit error

Definition at line 162 of file gd32f10x_can.h.

#define CAN_TSTAT_MTE2 BIT(19)

mailbox2 transmit error

Definition at line 167 of file gd32f10x_can.h.

#define CAN_TSTAT_MTF0 BIT(0)

mailbox0 transmit finished

Definition at line 154 of file gd32f10x_can.h.

#define CAN_TSTAT_MTF1 BIT(8)

mailbox1 transmit finished

Definition at line 159 of file gd32f10x_can.h.

#define CAN_TSTAT_MTF2 BIT(16)

mailbox2 transmit finished

Definition at line 164 of file gd32f10x_can.h.

#define CAN_TSTAT_MTFNERR0 BIT(1)

mailbox0 transmit finished and no error

Definition at line 155 of file gd32f10x_can.h.

#define CAN_TSTAT_MTFNERR1 BIT(9)

mailbox1 transmit finished and no error

Definition at line 160 of file gd32f10x_can.h.

#define CAN_TSTAT_MTFNERR2 BIT(17)

mailbox2 transmit finished and no error

Definition at line 165 of file gd32f10x_can.h.

#define CAN_TSTAT_NUM BITS(24,25)

mailbox number

Definition at line 169 of file gd32f10x_can.h.

#define CAN_TSTAT_TME0 BIT(26)

transmit mailbox0 empty

Definition at line 170 of file gd32f10x_can.h.

#define CAN_TSTAT_TME1 BIT(27)

transmit mailbox1 empty

Definition at line 171 of file gd32f10x_can.h.

#define CAN_TSTAT_TME2 BIT(28)

transmit mailbox2 empty

Definition at line 172 of file gd32f10x_can.h.

#define CAN_TSTAT_TMLS0 BIT(29)

last sending priority flag for mailbox0

Definition at line 173 of file gd32f10x_can.h.

#define CAN_TSTAT_TMLS1 BIT(30)

last sending priority flag for mailbox1

Definition at line 174 of file gd32f10x_can.h.

#define CAN_TSTAT_TMLS2 BIT(31)

last sending priority flag for mailbox2

Definition at line 175 of file gd32f10x_can.h.

#define ERR_ERRN ( regval ) (BITS(4,6) & ((uint32_t)(regval) << 4))

Definition at line 512 of file gd32f10x_can.h.

#define ERR_REG_OFFSET ((uint8_t)0x18U)

ERR register offset

Definition at line 303 of file gd32f10x_can.h.

#define FCTL_HBC1F ( regval ) (BITS(8,13) & ((uint32_t)(regval) << 8))

Definition at line 443 of file gd32f10x_can.h.

#define FDATA_MASK_HIGH ( regval ) (BITS(16,31) & ((uint32_t)(regval) << 16))

Definition at line 437 of file gd32f10x_can.h.

#define FDATA_MASK_LOW ( regval ) (BITS(0,15) & ((uint32_t)(regval) << 0))

Definition at line 440 of file gd32f10x_can.h.

#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU)

RFIFO0 register offset

Definition at line 301 of file gd32f10x_can.h.

#define RFIFO1_REG_OFFSET ((uint8_t)0x10U)

RFIFO1 register offset

Definition at line 302 of file gd32f10x_can.h.

#define RFIFOMDATA0_DB0 ( regval ) GET_BITS((uint32_t)(regval), 0, 7)

Definition at line 488 of file gd32f10x_can.h.

#define RFIFOMDATA0_DB1 ( regval ) GET_BITS((uint32_t)(regval), 8, 15)

Definition at line 491 of file gd32f10x_can.h.

#define RFIFOMDATA0_DB2 ( regval ) GET_BITS((uint32_t)(regval), 16, 23)

Definition at line 494 of file gd32f10x_can.h.

#define RFIFOMDATA0_DB3 ( regval ) GET_BITS((uint32_t)(regval), 24, 31)

Definition at line 497 of file gd32f10x_can.h.

#define RFIFOMDATA1_DB4 ( regval ) GET_BITS((uint32_t)(regval), 0, 7)

Definition at line 500 of file gd32f10x_can.h.

#define RFIFOMDATA1_DB5 ( regval ) GET_BITS((uint32_t)(regval), 8, 15)

Definition at line 503 of file gd32f10x_can.h.

#define RFIFOMDATA1_DB6 ( regval ) GET_BITS((uint32_t)(regval), 16, 23)

Definition at line 506 of file gd32f10x_can.h.

#define RFIFOMDATA1_DB7 ( regval ) GET_BITS((uint32_t)(regval), 24, 31)

Definition at line 509 of file gd32f10x_can.h.

#define RFIFOMI_EFID ( regval ) GET_BITS((uint32_t)(regval), 3, 31)

Definition at line 476 of file gd32f10x_can.h.

#define RFIFOMI_SFID ( regval ) GET_BITS((uint32_t)(regval), 21, 31)

Definition at line 479 of file gd32f10x_can.h.

#define RFIFOMP_DLENC ( regval ) GET_BITS((uint32_t)(regval), 0, 3)

Definition at line 482 of file gd32f10x_can.h.

#define RFIFOMP_FI ( regval ) GET_BITS((uint32_t)(regval), 8, 15)

Definition at line 485 of file gd32f10x_can.h.

#define STAT_REG_OFFSET ((uint8_t)0x04U)

STAT register offset

Definition at line 299 of file gd32f10x_can.h.

#define TMDATA0_DB0 ( regval ) (BITS(0,7) & ((uint32_t)(regval) << 0))

Definition at line 452 of file gd32f10x_can.h.

#define TMDATA0_DB1 ( regval ) (BITS(8,15) & ((uint32_t)(regval) << 8))

Definition at line 455 of file gd32f10x_can.h.

#define TMDATA0_DB2 ( regval ) (BITS(16,23) & ((uint32_t)(regval) << 16))

Definition at line 458 of file gd32f10x_can.h.

#define TMDATA0_DB3 ( regval ) (BITS(24,31) & ((uint32_t)(regval) << 24))

Definition at line 461 of file gd32f10x_can.h.

#define TMDATA1_DB4 ( regval ) (BITS(0,7) & ((uint32_t)(regval) << 0))

Definition at line 464 of file gd32f10x_can.h.

#define TMDATA1_DB5 ( regval ) (BITS(8,15) & ((uint32_t)(regval) << 8))

Definition at line 467 of file gd32f10x_can.h.

#define TMDATA1_DB6 ( regval ) (BITS(16,23) & ((uint32_t)(regval) << 16))

Definition at line 470 of file gd32f10x_can.h.

#define TMDATA1_DB7 ( regval ) (BITS(24,31) & ((uint32_t)(regval) << 24))

Definition at line 473 of file gd32f10x_can.h.

#define TMI_EFID ( regval ) (BITS(3,31) & ((uint32_t)(regval) << 3))

Definition at line 446 of file gd32f10x_can.h.

#define TMI_SFID ( regval ) (BITS(21,31) & ((uint32_t)(regval) << 21))

Definition at line 449 of file gd32f10x_can.h.

#define TSTAT_REG_OFFSET ((uint8_t)0x08U)

TSTAT register offset

Definition at line 300 of file gd32f10x_can.h.

Enumeration Type Documentation

enum can_error_enum
Enumerator
CAN_ERROR_NONE | no error
CAN_ERROR_FILL | fill error
CAN_ERROR_FORMATE | format error
CAN_ERROR_ACK | ACK error
CAN_ERROR_BITRECESSIVE | bit recessive error
CAN_ERROR_BITDOMINANTER | bit dominant error
CAN_ERROR_CRC | CRC error
CAN_ERROR_SOFTWARECFG | software configure

Definition at line 400 of file gd32f10x_can.h.

401 {
402 CAN_ERROR_NONE = 0,
403 CAN_ERROR_FILL,
404 CAN_ERROR_FORMATE,
405 CAN_ERROR_ACK,
406 CAN_ERROR_BITRECESSIVE,
407 CAN_ERROR_BITDOMINANTER,
408 CAN_ERROR_CRC,
409 CAN_ERROR_SOFTWARECFG,
410 }can_error_enum;
can_error_enum
can_error_enum
Definition: gd32f10x_can.h:400
CAN_ERROR_FORMATE
Definition: gd32f10x_can.h:404
CAN_ERROR_ACK
Definition: gd32f10x_can.h:405
CAN_ERROR_NONE
Definition: gd32f10x_can.h:402
CAN_ERROR_SOFTWARECFG
Definition: gd32f10x_can.h:409
CAN_ERROR_BITDOMINANTER
Definition: gd32f10x_can.h:407
CAN_ERROR_BITRECESSIVE
Definition: gd32f10x_can.h:406
CAN_ERROR_CRC
Definition: gd32f10x_can.h:408
CAN_ERROR_FILL
Definition: gd32f10x_can.h:403
enum can_flag_enum
Enumerator
CAN_FLAG_MTE2 | mailbox 2 transmit error
CAN_FLAG_MTE1 | mailbox 1 transmit error
CAN_FLAG_MTE0 | mailbox 0 transmit error
CAN_FLAG_MTF2 | mailbox 2 transmit finished
CAN_FLAG_MTF1 | mailbox 1 transmit finished
CAN_FLAG_MTF0 | mailbox 0 transmit finished
CAN_FLAG_RFO0 | receive FIFO0 overfull
CAN_FLAG_RFF0 | receive FIFO0 full
CAN_FLAG_RFO1 | receive FIFO1 overfull
CAN_FLAG_RFF1 | receive FIFO1 full
CAN_FLAG_BOERR | bus-off error
CAN_FLAG_PERR | passive error
CAN_FLAG_WERR | warning error

Definition at line 306 of file gd32f10x_can.h.

307 {
308 /* flags in TSTAT register */
309 CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U),
310 CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U),
311 CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U),
312 CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U),
313 CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U),
314 CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U),
315 /* flags in RFIFO0 register */
316 CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U),
317 CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U),
318 /* flags in RFIFO1 register */
319 CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U),
320 CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U),
321 /* flags in ERR register */
322 CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U),
323 CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U),
324 CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U),
325 }can_flag_enum;
CAN_FLAG_MTE1
Definition: gd32f10x_can.h:310
CAN_FLAG_MTE0
Definition: gd32f10x_can.h:311
ERR_REG_OFFSET
#define ERR_REG_OFFSET
Definition: gd32f10x_can.h:303
CAN_REGIDX_BIT
#define CAN_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_can.h:289
CAN_FLAG_MTF2
Definition: gd32f10x_can.h:312
CAN_FLAG_MTF0
Definition: gd32f10x_can.h:314
CAN_FLAG_MTE2
Definition: gd32f10x_can.h:309
CAN_FLAG_BOERR
Definition: gd32f10x_can.h:322
CAN_FLAG_RFO0
Definition: gd32f10x_can.h:316
CAN_FLAG_WERR
Definition: gd32f10x_can.h:324
RFIFO1_REG_OFFSET
#define RFIFO1_REG_OFFSET
Definition: gd32f10x_can.h:302
CAN_FLAG_RFO1
Definition: gd32f10x_can.h:319
CAN_FLAG_MTF1
Definition: gd32f10x_can.h:313
TSTAT_REG_OFFSET
#define TSTAT_REG_OFFSET
Definition: gd32f10x_can.h:300
can_flag_enum
can_flag_enum
Definition: gd32f10x_can.h:306
CAN_FLAG_RFF1
Definition: gd32f10x_can.h:320
RFIFO0_REG_OFFSET
#define RFIFO0_REG_OFFSET
Definition: gd32f10x_can.h:301
CAN_FLAG_RFF0
Definition: gd32f10x_can.h:317
CAN_FLAG_PERR
Definition: gd32f10x_can.h:323
enum can_interrupt_flag_enum
Enumerator
CAN_INT_FLAG_SLPIF | status change interrupt flag of sleep working mode entering
CAN_INT_FLAG_WUIF | status change interrupt flag of wakeup from sleep working mode
CAN_INT_FLAG_ERRIF | error interrupt flag
CAN_INT_FLAG_MTF2 | mailbox 2 transmit finished interrupt flag
CAN_INT_FLAG_MTF1 | mailbox 1 transmit finished interrupt flag
CAN_INT_FLAG_MTF0 | mailbox 0 transmit finished interrupt flag
CAN_INT_FLAG_RFO0 | receive FIFO0 overfull interrupt flag
CAN_INT_FLAG_RFF0 | receive FIFO0 full interrupt flag
CAN_INT_FLAG_RFO1 | receive FIFO1 overfull interrupt flag
CAN_INT_FLAG_RFF1 | receive FIFO1 full interrupt flag

Definition at line 328 of file gd32f10x_can.h.

329 {
330 /* interrupt flags in STAT register */
331 CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U),
332 CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16),
333 CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15),
334 /* interrupt flags in TSTAT register */
335 CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U),
336 CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U),
337 CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U),
338 /* interrupt flags in RFIFO0 register */
339 CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U),
340 CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U),
341 /* interrupt flags in RFIFO0 register */
342 CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U),
343 CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U),
344 }can_interrupt_flag_enum;
CAN_INT_FLAG_RFO0
Definition: gd32f10x_can.h:339
STAT_REG_OFFSET
#define STAT_REG_OFFSET
Definition: gd32f10x_can.h:299
CAN_INT_FLAG_MTF0
Definition: gd32f10x_can.h:337
CAN_REGIDX_BITS
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1)
Definition: gd32f10x_can.h:293
CAN_INT_FLAG_SLPIF
Definition: gd32f10x_can.h:331
can_interrupt_flag_enum
can_interrupt_flag_enum
Definition: gd32f10x_can.h:328
CAN_INT_FLAG_ERRIF
Definition: gd32f10x_can.h:333
CAN_INT_FLAG_RFF1
Definition: gd32f10x_can.h:343
CAN_INT_FLAG_WUIF
Definition: gd32f10x_can.h:332
CAN_INT_FLAG_MTF2
Definition: gd32f10x_can.h:335
CAN_INT_FLAG_MTF1
Definition: gd32f10x_can.h:336
RFIFO1_REG_OFFSET
#define RFIFO1_REG_OFFSET
Definition: gd32f10x_can.h:302
CAN_INT_FLAG_RFO1
Definition: gd32f10x_can.h:342
TSTAT_REG_OFFSET
#define TSTAT_REG_OFFSET
Definition: gd32f10x_can.h:300
CAN_INT_FLAG_RFF0
Definition: gd32f10x_can.h:340
RFIFO0_REG_OFFSET
#define RFIFO0_REG_OFFSET
Definition: gd32f10x_can.h:301
enum can_transmit_state_enum
Enumerator
CAN_TRANSMIT_FAILED | CAN transmitted failure
CAN_TRANSMIT_OK | CAN transmitted success
CAN_TRANSMIT_PENDING | CAN transmitted pending
CAN_TRANSMIT_NOMAILBOX | no empty mailbox to be used for CAN

Definition at line 413 of file gd32f10x_can.h.

414 {
415 CAN_TRANSMIT_FAILED = 0,
416 CAN_TRANSMIT_OK = 1,
417 CAN_TRANSMIT_PENDING = 2,
418 CAN_TRANSMIT_NOMAILBOX = 4,
419 }can_transmit_state_enum;
can_transmit_state_enum
can_transmit_state_enum
Definition: gd32f10x_can.h:413
CAN_TRANSMIT_FAILED
Definition: gd32f10x_can.h:415
CAN_TRANSMIT_NOMAILBOX
Definition: gd32f10x_can.h:418
CAN_TRANSMIT_PENDING
Definition: gd32f10x_can.h:417
CAN_TRANSMIT_OK
Definition: gd32f10x_can.h:416

Function Documentation

void can1_filter_start_bank ( uint8_t start_bank )

set CAN1 fliter start bank number

Parameters
[in] can1_start_bank_number
  • (1..27)
[out] none
Return values
none

Definition at line 220 of file gd32f10x_can.c.

221 {
222 /* filter lock disable */
223 CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
224 /* set CAN1 filter start number */
225 CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F;
226 CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank);
227 /* filter lock enaable */
228 CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
229 }
FCTL_HBC1F
#define FCTL_HBC1F(regval)
Definition: gd32f10x_can.h:443
CAN_FCTL_HBC1F
#define CAN_FCTL_HBC1F
Definition: gd32f10x_can.h:270
CAN_FCTL
#define CAN_FCTL(canx)
Definition: gd32f10x_can.h:51
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
CAN_FCTL_FLD
#define CAN_FCTL_FLD
Definition: gd32f10x_can.h:269
void can_debug_freeze_disable ( uint32_t can_periph )

disable CAN debug freeze

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 261 of file gd32f10x_can.c.

262 {
263 CAN_CTL(can_periph) |= CAN_CTL_DFZ;
264 #ifdef GD32F10x_CL
265 if(CAN0 == can_periph){
266 dbg_periph_disable(DBG_CAN0_HOLD);
267 }else{
268 dbg_periph_disable(DBG_CAN1_HOLD);
269 }
270 #else
271 if(CAN0 == can_periph){
272 dbg_periph_enable(DBG_CAN0_HOLD);
273 }
274 #endif
275 }
DBG_CAN0_HOLD
Definition: gd32f10x_dbg.h:73
dbg_periph_enable
void dbg_periph_enable(dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:68
dbg_periph_disable
void dbg_periph_disable(dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:85
CAN_CTL_DFZ
#define CAN_CTL_DFZ
Definition: gd32f10x_can.h:140
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
void can_debug_freeze_enable ( uint32_t can_periph )

enable CAN debug freeze

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 238 of file gd32f10x_can.c.

239 {
240 CAN_CTL(can_periph) |= CAN_CTL_DFZ;
241 #ifdef GD32F10x_CL
242 if(CAN0 == can_periph){
243 dbg_periph_enable(DBG_CAN0_HOLD);
244 }else{
245 dbg_periph_enable(DBG_CAN1_HOLD);
246 }
247 #else
248 if(CAN0 == can_periph){
249 dbg_periph_enable(DBG_CAN0_HOLD);
250 }
251 #endif
252 }
DBG_CAN0_HOLD
Definition: gd32f10x_dbg.h:73
dbg_periph_enable
void dbg_periph_enable(dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:68
CAN_CTL_DFZ
#define CAN_CTL_DFZ
Definition: gd32f10x_can.h:140
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
void can_deinit ( uint32_t can_periph )

deinitialize CAN

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 22 of file gd32f10x_can.c.

23 {
24 #ifdef GD32F10x_CL
25 if(CAN0 == can_periph){
26 rcu_periph_reset_enable(RCU_CAN0RST);
27 rcu_periph_reset_disable(RCU_CAN0RST);
28 }else{
29 rcu_periph_reset_enable(RCU_CAN1RST);
30 rcu_periph_reset_disable(RCU_CAN1RST);
31 }
32 #else
33 if(CAN0 == can_periph){
34 rcu_periph_reset_enable(RCU_CAN0RST);
35 rcu_periph_reset_disable(RCU_CAN0RST);
36 }
37 #endif
38 }
RCU_CAN0RST
Definition: gd32f10x_rcu.h:468
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
RCU_CAN1RST
Definition: gd32f10x_rcu.h:470
can_error_enum can_error_get ( uint32_t can_periph )

get CAN error type

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
can_error_enum

Definition at line 640 of file gd32f10x_can.c.

641 {
642 can_error_enum error;
643 error = CAN_ERROR_NONE;
644
645 /* get error type */
646 error = (can_error_enum)((CAN_ERR(can_periph) & CAN_ERR_ERRN) >> 4U);
647 return error;
648 }
can_error_enum
can_error_enum
Definition: gd32f10x_can.h:400
CAN_ERR
#define CAN_ERR(canx)
Definition: gd32f10x_can.h:29
CAN_ERROR_NONE
Definition: gd32f10x_can.h:402
CAN_ERR_ERRN
#define CAN_ERR_ERRN
Definition: gd32f10x_can.h:209
void can_fifo_release | ( | uint32_t | can_periph,
 |  | uint8_t | fifo_number
 | ) |  |

release FIFO0

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
  • CAN_FIFOx(x=0,1)
[out] none
Return values
none

Definition at line 510 of file gd32f10x_can.c.

511 {
512 if(CAN_FIFO0 == fifo_number){
513 CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
514 }else if(CAN_FIFO1 == fifo_number){
515 CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
516 }else{
517 /* illegal parameter */
518 }
519 }
CAN_RFIFO1_RFD1
#define CAN_RFIFO1_RFD1
Definition: gd32f10x_can.h:187
CAN_RFIFO1
#define CAN_RFIFO1(canx)
Definition: gd32f10x_can.h:27
CAN_RFIFO0
#define CAN_RFIFO0(canx)
Definition: gd32f10x_can.h:26
CAN_FIFO1
#define CAN_FIFO1
Definition: gd32f10x_can.h:576
CAN_RFIFO0_RFD0
#define CAN_RFIFO0_RFD0
Definition: gd32f10x_can.h:181
CAN_FIFO0
#define CAN_FIFO0
Definition: gd32f10x_can.h:575
void can_filter_init ( can_filter_parameter_struct * can_filter_parameter_init )

initialize CAN filter

Parameters
[in] can_filter_parameter_init struct for CAN filter initialization
  • filter_list_high: 0x0000 - 0xFFFF
  • filter_list_low: 0x0000 - 0xFFFF
  • filter_mask_high: 0x0000 - 0xFFFF
  • filter_mask_low: 0x0000 - 0xFFFF
  • filter_fifo_number: CAN_FIFO0, CAN_FIFO1
  • filter_number: 0 - 27
  • filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST
  • filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT
  • filter_enable: ENABLE or DISABLE
[out] none
Return values
none

Definition at line 148 of file gd32f10x_can.c.

149 {
150 uint32_t val = 0U;
151
152 val = ((uint32_t)1) << (can_filter_parameter_init->filter_number);
153 /* filter lock disable */
154 CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
155 /* disable filter */
156 CAN_FW(CAN0) &= ~(uint32_t)val;
157
158 /* filter 16 bits */
159 if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){
160 /* set filter 16 bits */
161 CAN_FSCFG(CAN0) &= ~(uint32_t)val;
162 /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */
163 CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
164 FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \
165 FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
166 /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */
167 CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
168 FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \
169 FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS);
170 }
171 /* filter 32 bits */
172 if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){
173 /* set filter 32 bits */
174 CAN_FSCFG(CAN0) |= (uint32_t)val;
175 /* 32 bits list or first 32 bits list */
176 CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
177 FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) |
178 FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
179 /* 32 bits mask or second 32 bits list */
180 CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
181 FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) |
182 FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS);
183 }
184
185 /* filter mode */
186 if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){
187 /* mask mode */
188 CAN_FMCFG(CAN0) &= ~(uint32_t)val;
189 }else{
190 /* list mode */
191 CAN_FMCFG(CAN0) |= (uint32_t)val;
192 }
193
194 /* filter FIFO */
195 if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){
196 /* FIFO0 */
197 CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
198 }else{
199 /* FIFO1 */
200 CAN_FAFIFO(CAN0) |= (uint32_t)val;
201 }
202
203 /* filter working */
204 if(ENABLE == can_filter_parameter_init->filter_enable){
205
206 CAN_FW(CAN0) |= (uint32_t)val;
207 }
208
209 /* filter lock enable */
210 CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
211 }
can_filter_parameter_struct::filter_list_high
uint16_t filter_list_high
Definition: gd32f10x_can.h:388
can_filter_parameter_struct::filter_list_low
uint16_t filter_list_low
Definition: gd32f10x_can.h:389
can_filter_parameter_struct::filter_mode
uint16_t filter_mode
Definition: gd32f10x_can.h:394
FDATA_MASK_HIGH
#define FDATA_MASK_HIGH(regval)
Definition: gd32f10x_can.h:437
CAN_FILTERBITS_32BIT
#define CAN_FILTERBITS_32BIT
Definition: gd32f10x_can.h:591
CAN_FSCFG
#define CAN_FSCFG(canx)
Definition: gd32f10x_can.h:53
CAN_FILTER_MASK_16BITS
#define CAN_FILTER_MASK_16BITS
Definition: gd32f10x_can.h:598
CAN_FCTL
#define CAN_FCTL(canx)
Definition: gd32f10x_can.h:51
CAN_FW
#define CAN_FW(canx)
Definition: gd32f10x_can.h:55
can_filter_parameter_struct::filter_mask_low
uint16_t filter_mask_low
Definition: gd32f10x_can.h:391
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
can_filter_parameter_struct::filter_number
uint16_t filter_number
Definition: gd32f10x_can.h:393
CAN_FCTL_FLD
#define CAN_FCTL_FLD
Definition: gd32f10x_can.h:269
CAN_FMCFG
#define CAN_FMCFG(canx)
Definition: gd32f10x_can.h:52
can_filter_parameter_struct::filter_mask_high
uint16_t filter_mask_high
Definition: gd32f10x_can.h:390
CAN_FAFIFO
#define CAN_FAFIFO(canx)
Definition: gd32f10x_can.h:54
CAN_FDATA0
#define CAN_FDATA0(canx, bank)
Definition: gd32f10x_can.h:120
FDATA_MASK_LOW
#define FDATA_MASK_LOW(regval)
Definition: gd32f10x_can.h:440
can_filter_parameter_struct::filter_bits
uint16_t filter_bits
Definition: gd32f10x_can.h:395
can_filter_parameter_struct::filter_enable
ControlStatus filter_enable
Definition: gd32f10x_can.h:396
CAN_FDATA1
#define CAN_FDATA1(canx, bank)
Definition: gd32f10x_can.h:121
CAN_FILTERMODE_MASK
#define CAN_FILTERMODE_MASK
Definition: gd32f10x_can.h:594
CAN_FILTERBITS_16BIT
#define CAN_FILTERBITS_16BIT
Definition: gd32f10x_can.h:590
can_filter_parameter_struct::filter_fifo_number
uint16_t filter_fifo_number
Definition: gd32f10x_can.h:392
CAN_FIFO0
#define CAN_FIFO0
Definition: gd32f10x_can.h:575
void can_flag_clear | ( | uint32_t | can_periph,
 |  | can_flag_enum | flag
 | ) |  |

clear CAN flag state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] flag CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below:
  • CAN_FLAG_MTE2: mailbox 2 transmit error
  • CAN_FLAG_MTE1: mailbox 1 transmit error
  • CAN_FLAG_MTE0: mailbox 0 transmit error
  • CAN_FLAG_MTF2: mailbox 2 transmit finished
  • CAN_FLAG_MTF1: mailbox 1 transmit finished
  • CAN_FLAG_MTF0: mailbox 0 transmit finished
  • CAN_FLAG_RFO0: receive FIFO0 overfull
  • CAN_FLAG_RFF0: receive FIFO0 full
  • CAN_FLAG_RFO1: receive FIFO1 overfull
  • CAN_FLAG_RFF1: receive FIFO1 full
[out] none
Return values
none

Definition at line 784 of file gd32f10x_can.c.

785 {
786 CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag));
787 }
CAN_BIT_POS
#define CAN_BIT_POS(val)
Definition: gd32f10x_can.h:291
CAN_REG_VAL
#define CAN_REG_VAL(canx, offset)
Definition: gd32f10x_can.h:290
FlagStatus can_flag_get | ( | uint32_t | can_periph,
 |  | can_flag_enum | flag
 | ) |  |

get CAN flag state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] flag CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below:
  • CAN_FLAG_MTE2: mailbox 2 transmit error
  • CAN_FLAG_MTE1: mailbox 1 transmit error
  • CAN_FLAG_MTE0: mailbox 0 transmit error
  • CAN_FLAG_MTF2: mailbox 2 transmit finished
  • CAN_FLAG_MTF1: mailbox 1 transmit finished
  • CAN_FLAG_MTF0: mailbox 0 transmit finished
  • CAN_FLAG_RFO0: receive FIFO0 overfull
  • CAN_FLAG_RFF0: receive FIFO0 full
  • CAN_FLAG_RFO1: receive FIFO1 overfull
  • CAN_FLAG_RFF1: receive FIFO1 full
  • CAN_FLAG_BOERR: bus-off error
  • CAN_FLAG_PERR: passive error
  • CAN_FLAG_WERR: warning error
[out] none
Return values
FlagStatus SET or RESET

Definition at line 756 of file gd32f10x_can.c.

757 {
758 if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){
759 return SET;
760 }else{
761 return RESET;
762 }
763 }
CAN_BIT_POS
#define CAN_BIT_POS(val)
Definition: gd32f10x_can.h:291
CAN_REG_VAL
#define CAN_REG_VAL(canx, offset)
Definition: gd32f10x_can.h:290
ErrStatus can_init | ( | uint32_t | can_periph,
 |  | can_parameter_struct * | can_parameter_init
 | ) |  |

initialize CAN

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] can_parameter_init parameters for CAN initializtion
  • working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE
  • resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4)
  • time_segment_1: CAN_BT_BS1_xTQ(1..16)
  • time_segment_2: CAN_BT_BS2_xTQ(1..8)
  • time_triggered: ENABLE or DISABLE
  • auto_bus_off_recovery: ENABLE or DISABLE
  • auto_wake_up: ENABLE or DISABLE
  • auto_retrans: ENABLE or DISABLE
  • rec_fifo_overwrite: ENABLE or DISABLE
  • trans_fifo_order: ENABLE or DISABLE
  • prescaler: 0x0001 - 0x03FF
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 59 of file gd32f10x_can.c.

60 {
61 uint32_t timeout = CAN_TIMEOUT;
62 ErrStatus flag = ERROR;
63
64 /* disable sleep mode */
65 CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
66 /* enable initialize mode */
67 CAN_CTL(can_periph) |= CAN_CTL_IWMOD;
68 /* wait ACK */
69 while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){
70 timeout--;
71 }
72 /* check initialize working success */
73 if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
74 flag = ERROR;
75 }else{
76 /* set the bit timing register */
77 CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \
78 BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \
79 BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
80 BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
81 BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
82 /* time trigger communication mode */
83 if(ENABLE == can_parameter_init->time_triggered){
84 CAN_CTL(can_periph) |= CAN_CTL_TTC;
85 }else{
86 CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
87 }
88 /* automatic bus-off managment */
89 if(ENABLE == can_parameter_init->auto_bus_off_recovery){
90 CAN_CTL(can_periph) |= CAN_CTL_ABOR;
91 }else{
92 CAN_CTL(can_periph) &= ~CAN_CTL_ABOR;
93 }
94 /* automatic wakeup mode */
95 if(ENABLE == can_parameter_init->auto_wake_up){
96 CAN_CTL(can_periph) |= CAN_CTL_AWU;
97 }else{
98 CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
99 }
100 /* automatic retransmission mode */
101 if(ENABLE == can_parameter_init->auto_retrans){
102 CAN_CTL(can_periph) |= CAN_CTL_ARD;
103 }else{
104 CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
105 }
106 /* receive fifo overwrite mode */
107 if(ENABLE == can_parameter_init->rec_fifo_overwrite){
108 CAN_CTL(can_periph) |= CAN_CTL_RFOD;
109 }else{
110 CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
111 }
112 /* transmit fifo order */
113 if(ENABLE == can_parameter_init->trans_fifo_order){
114 CAN_CTL(can_periph) |= CAN_CTL_TFO;
115 }else{
116 CAN_CTL(can_periph) &= ~CAN_CTL_TFO;
117 }
118 /* disable initialize mode */
119 CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD;
120 timeout = CAN_TIMEOUT;
121 /* wait the ACK */
122 while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){
123 timeout--;
124 }
125 /* check exit initialize mode */
126 if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){
127 flag = SUCCESS;
128 }
129 }
130 return flag;
131 }
BT_BS2
#define BT_BS2(regval)
Definition: gd32f10x_can.h:428
can_parameter_struct::auto_wake_up
ControlStatus auto_wake_up
Definition: gd32f10x_can.h:355
can_parameter_struct::time_segment_1
uint8_t time_segment_1
Definition: gd32f10x_can.h:351
BT_BAUDPSC
#define BT_BAUDPSC(regval)
Definition: gd32f10x_can.h:422
CAN_CTL_IWMOD
#define CAN_CTL_IWMOD
Definition: gd32f10x_can.h:131
BT_MODE
#define BT_MODE(regval)
Definition: gd32f10x_can.h:434
CAN_STAT
#define CAN_STAT(canx)
Definition: gd32f10x_can.h:24
CAN_CTL_ABOR
#define CAN_CTL_ABOR
Definition: gd32f10x_can.h:137
BT_BS1
#define BT_BS1(regval)
Definition: gd32f10x_can.h:425
CAN_CTL_RFOD
#define CAN_CTL_RFOD
Definition: gd32f10x_can.h:134
can_parameter_struct::auto_bus_off_recovery
ControlStatus auto_bus_off_recovery
Definition: gd32f10x_can.h:354
can_parameter_struct::resync_jump_width
uint8_t resync_jump_width
Definition: gd32f10x_can.h:350
can_parameter_struct::rec_fifo_overwrite
ControlStatus rec_fifo_overwrite
Definition: gd32f10x_can.h:357
can_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f10x_can.h:359
CAN_CTL_ARD
#define CAN_CTL_ARD
Definition: gd32f10x_can.h:135
CAN_CTL_SLPWMOD
#define CAN_CTL_SLPWMOD
Definition: gd32f10x_can.h:132
CAN_TIMEOUT
#define CAN_TIMEOUT
Definition: gd32f10x_can.h:605
can_parameter_struct::time_triggered
ControlStatus time_triggered
Definition: gd32f10x_can.h:353
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_CTL_AWU
#define CAN_CTL_AWU
Definition: gd32f10x_can.h:136
CAN_STAT_IWS
#define CAN_STAT_IWS
Definition: gd32f10x_can.h:143
BT_SJW
#define BT_SJW(regval)
Definition: gd32f10x_can.h:431
CAN_CTL_TFO
#define CAN_CTL_TFO
Definition: gd32f10x_can.h:133
can_parameter_struct::trans_fifo_order
ControlStatus trans_fifo_order
Definition: gd32f10x_can.h:358
CAN_CTL_TTC
#define CAN_CTL_TTC
Definition: gd32f10x_can.h:138
can_parameter_struct::time_segment_2
uint8_t time_segment_2
Definition: gd32f10x_can.h:352
can_parameter_struct::auto_retrans
ControlStatus auto_retrans
Definition: gd32f10x_can.h:356
CAN_BT
#define CAN_BT(canx)
Definition: gd32f10x_can.h:30
can_parameter_struct::working_mode
uint8_t working_mode
Definition: gd32f10x_can.h:349
void can_interrupt_disable | ( | uint32_t | can_periph,
 |  | uint32_t | interrupt
 | ) |  |

disable CAN interrupt

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] interrupt
  • CAN_INT_TME: transmit mailbox empty interrupt enable
  • CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
  • CAN_INT_RFF0: receive FIFO0 full interrupt enable
  • CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
  • CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
  • CAN_INT_RFF1: receive FIFO1 full interrupt enable
  • CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
  • CAN_INT_WERR: warning error interrupt enable
  • CAN_INT_PERR: passive error interrupt enable
  • CAN_INT_BO: bus-off interrupt enable
  • CAN_INT_ERRN: error number interrupt enable
  • CAN_INT_ERR: error interrupt enable
  • CAN_INT_WU: wakeup interrupt enable
  • CAN_INT_SLPW: sleep working interrupt enable
[out] none
Return values
none

Definition at line 729 of file gd32f10x_can.c.

730 {
731 CAN_INTEN(can_periph) &= ~interrupt;
732 }
CAN_INTEN
#define CAN_INTEN(canx)
Definition: gd32f10x_can.h:28
void can_interrupt_enable | ( | uint32_t | can_periph,
 |  | uint32_t | interrupt
 | ) |  |

enable CAN interrupt

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] interrupt
  • CAN_INT_TME: transmit mailbox empty interrupt enable
  • CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
  • CAN_INT_RFF0: receive FIFO0 full interrupt enable
  • CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
  • CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
  • CAN_INT_RFF1: receive FIFO1 full interrupt enable
  • CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
  • CAN_INT_WERR: warning error interrupt enable
  • CAN_INT_PERR: passive error interrupt enable
  • CAN_INT_BO: bus-off interrupt enable
  • CAN_INT_ERRN: error number interrupt enable
  • CAN_INT_ERR: error interrupt enable
  • CAN_INT_WU: wakeup interrupt enable
  • CAN_INT_SLPW: sleep working interrupt enable
[out] none
Return values
none

Definition at line 702 of file gd32f10x_can.c.

703 {
704 CAN_INTEN(can_periph) |= interrupt;
705 }
CAN_INTEN
#define CAN_INTEN(canx)
Definition: gd32f10x_can.h:28
void can_interrupt_flag_clear | ( | uint32_t | can_periph,
 |  | can_interrupt_flag_enum | flag
 | ) |  |

clear CAN interrupt flag state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] flag CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below:
  • CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
  • CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
  • CAN_INT_FLAG_ERRIF: error interrupt flag
  • CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
  • CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
  • CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
  • CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
  • CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
  • CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
  • CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
[out] none
Return values
none

Definition at line 843 of file gd32f10x_can.c.

844 {
845 CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag));
846 }
CAN_REG_VALS
#define CAN_REG_VALS(canx, offset)
Definition: gd32f10x_can.h:294
CAN_BIT_POS0
#define CAN_BIT_POS0(val)
Definition: gd32f10x_can.h:295
FlagStatus can_interrupt_flag_get | ( | uint32_t | can_periph,
 |  | can_interrupt_flag_enum | flag
 | ) |  |

get CAN interrupt flag state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] flag CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below:
  • CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
  • CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
  • CAN_INT_FLAG_ERRIF: error interrupt flag
  • CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
  • CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
  • CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
  • CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
  • CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
  • CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
  • CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 808 of file gd32f10x_can.c.

809 {
810 FlagStatus ret1 = RESET;
811 FlagStatus ret2 = RESET;
812
813 /* get the staus of interrupt flag */
814 ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)));
815 /* get the staus of interrupt enale bit */
816 ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)));
817 if(ret1 && ret2){
818 return SET;
819 }else{
820 return RESET;
821 }
822 }
CAN_REG_VALS
#define CAN_REG_VALS(canx, offset)
Definition: gd32f10x_can.h:294
CAN_BIT_POS1
#define CAN_BIT_POS1(val)
Definition: gd32f10x_can.h:296
CAN_INTEN
#define CAN_INTEN(canx)
Definition: gd32f10x_can.h:28
CAN_BIT_POS0
#define CAN_BIT_POS0(val)
Definition: gd32f10x_can.h:295
void can_message_receive | ( | uint32_t | can_periph,
 |  | uint8_t | fifo_number,
 |  | can_receive_message_struct * | receive_message
 | ) |  |

CAN receive message.

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] fifo_number
  • CAN_FIFOx(x=0,1)
[out] receive_message struct for CAN receive message
  • rx_sfid: 0x00000000 - 0x000007FF
  • rx_efid: 0x00000000 - 0x1FFFFFFF
  • rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
  • rx_ft: CAN_FT_DATA, CAN_FT_REMOTE
  • rx_dlenc: 1 - 7
  • rx_data[]: 0x00 - 0xFF
  • rx_fi: 0 - 27
Return values
none

Definition at line 465 of file gd32f10x_can.c.

466 {
467 /* get the frame format */
468 receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number));
469 if(CAN_FF_STANDARD == receive_message->rx_ff){
470 /* get standard identifier */
471 receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number)));
472 }else{
473 /* get extended identifier */
474 receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number)));
475 }
476
477 /* get frame type */
478 receive_message -> rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number));
479 /* get recevie data length */
480 receive_message -> rx_dlen = (uint8_t)(RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number)));
481 /* filtering index */
482 receive_message -> rx_fi = (uint8_t)(RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number)));
483
484 /* receive data */
485 receive_message -> rx_data[0] = (uint8_t)(RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number)));
486 receive_message -> rx_data[1] = (uint8_t)(RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number)));
487 receive_message -> rx_data[2] = (uint8_t)(RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number)));
488 receive_message -> rx_data[3] = (uint8_t)(RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number)));
489 receive_message -> rx_data[4] = (uint8_t)(RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number)));
490 receive_message -> rx_data[5] = (uint8_t)(RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number)));
491 receive_message -> rx_data[6] = (uint8_t)(RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number)));
492 receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number)));
493
494 /* release FIFO */
495 if(CAN_FIFO0 == fifo_number){
496 CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
497 }else{
498 CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
499 }
500 }
RFIFOMDATA0_DB0
#define RFIFOMDATA0_DB0(regval)
Definition: gd32f10x_can.h:488
CAN_RFIFOMDATA0
#define CAN_RFIFOMDATA0(canx, bank)
Definition: gd32f10x_can.h:126
CAN_RFIFO1_RFD1
#define CAN_RFIFO1_RFD1
Definition: gd32f10x_can.h:187
RFIFOMDATA1_DB6
#define RFIFOMDATA1_DB6(regval)
Definition: gd32f10x_can.h:506
can_receive_message_struct::rx_ff
uint8_t rx_ff
Definition: gd32f10x_can.h:378
RFIFOMI_SFID
#define RFIFOMI_SFID(regval)
Definition: gd32f10x_can.h:479
CAN_RFIFOMDATA1
#define CAN_RFIFOMDATA1(canx, bank)
Definition: gd32f10x_can.h:127
RFIFOMP_FI
#define RFIFOMP_FI(regval)
Definition: gd32f10x_can.h:485
CAN_RFIFO1
#define CAN_RFIFO1(canx)
Definition: gd32f10x_can.h:27
RFIFOMI_EFID
#define RFIFOMI_EFID(regval)
Definition: gd32f10x_can.h:476
CAN_RFIFO0
#define CAN_RFIFO0(canx)
Definition: gd32f10x_can.h:26
RFIFOMDATA0_DB1
#define RFIFOMDATA0_DB1(regval)
Definition: gd32f10x_can.h:491
RFIFOMDATA1_DB4
#define RFIFOMDATA1_DB4(regval)
Definition: gd32f10x_can.h:500
RFIFOMDATA1_DB5
#define RFIFOMDATA1_DB5(regval)
Definition: gd32f10x_can.h:503
CAN_RFIFOMI
#define CAN_RFIFOMI(canx, bank)
Definition: gd32f10x_can.h:124
CAN_RFIFO0_RFD0
#define CAN_RFIFO0_RFD0
Definition: gd32f10x_can.h:181
CAN_RFIFOMI_FF
#define CAN_RFIFOMI_FF
Definition: gd32f10x_can.h:247
RFIFOMDATA1_DB7
#define RFIFOMDATA1_DB7(regval)
Definition: gd32f10x_can.h:509
CAN_FF_STANDARD
#define CAN_FF_STANDARD
Definition: gd32f10x_can.h:571
RFIFOMDATA0_DB2
#define RFIFOMDATA0_DB2(regval)
Definition: gd32f10x_can.h:494
CAN_RFIFOMI_FT
#define CAN_RFIFOMI_FT
Definition: gd32f10x_can.h:246
RFIFOMP_DLENC
#define RFIFOMP_DLENC(regval)
Definition: gd32f10x_can.h:482
CAN_RFIFOMP
#define CAN_RFIFOMP(canx, bank)
Definition: gd32f10x_can.h:125
RFIFOMDATA0_DB3
#define RFIFOMDATA0_DB3(regval)
Definition: gd32f10x_can.h:497
CAN_FIFO0
#define CAN_FIFO0
Definition: gd32f10x_can.h:575
uint8_t can_message_transmit | ( | uint32_t | can_periph,
 |  | can_trasnmit_message_struct * | transmit_message
 | ) |  |

transmit CAN message

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] transmit_message struct for CAN transmit message
  • tx_sfid: 0x00000000 - 0x000007FF
  • tx_efid: 0x00000000 - 0x1FFFFFFF
  • tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
  • tx_ft: CAN_FT_DATA, CAN_FT_REMOTE
  • tx_dlenc: 1 - 7
  • tx_data[]: 0x00 - 0xFF
[out] none
Return values
mailbox_number

Definition at line 329 of file gd32f10x_can.c.

330 {
331 uint8_t mailbox_number = CAN_MAILBOX0;
332
333 /* select one empty mailbox */
334 if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){
335 mailbox_number = CAN_MAILBOX0;
336 }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){
337 mailbox_number = CAN_MAILBOX1;
338 }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){
339 mailbox_number = CAN_MAILBOX2;
340 }else{
341 mailbox_number = CAN_NOMAILBOX;
342 }
343 if(CAN_NOMAILBOX == mailbox_number){
344 return CAN_NOMAILBOX;
345 }
346
347 CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN;
348 if(CAN_FF_STANDARD == transmit_message->tx_ff){
349 /* set transmit mailbox standard identifier */
350 CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \
351 transmit_message->tx_ft);
352 }else{
353 /* set transmit mailbox extended identifier */
354 CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \
355 transmit_message->tx_ff | \
356 transmit_message->tx_ft);
357 }
358 /* set the data length */
359 CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC);
360 CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
361 /* set the data */
362 CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \
363 TMDATA0_DB2(transmit_message->tx_data[2]) | \
364 TMDATA0_DB1(transmit_message->tx_data[1]) | \
365 TMDATA0_DB0(transmit_message->tx_data[0]);
366 CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \
367 TMDATA1_DB6(transmit_message->tx_data[6]) | \
368 TMDATA1_DB5(transmit_message->tx_data[5]) | \
369 TMDATA1_DB4(transmit_message->tx_data[4]);
370 /* enable transmission */
371 CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN;
372
373 return mailbox_number;
374 }
CAN_TMDATA0
#define CAN_TMDATA0(canx, bank)
Definition: gd32f10x_can.h:116
CAN_TSTAT
#define CAN_TSTAT(canx)
Definition: gd32f10x_can.h:25
TMDATA0_DB3
#define TMDATA0_DB3(regval)
Definition: gd32f10x_can.h:461
CAN_TMI
#define CAN_TMI(canx, bank)
Definition: gd32f10x_can.h:114
can_trasnmit_message_struct::tx_dlen
uint8_t tx_dlen
Definition: gd32f10x_can.h:369
TMDATA1_DB5
#define TMDATA1_DB5(regval)
Definition: gd32f10x_can.h:467
TMDATA0_DB0
#define TMDATA0_DB0(regval)
Definition: gd32f10x_can.h:452
can_trasnmit_message_struct::tx_sfid
uint32_t tx_sfid
Definition: gd32f10x_can.h:365
CAN_TSTAT_TME2
#define CAN_TSTAT_TME2
Definition: gd32f10x_can.h:172
can_trasnmit_message_struct::tx_ff
uint8_t tx_ff
Definition: gd32f10x_can.h:367
CAN_TSTAT_TME1
#define CAN_TSTAT_TME1
Definition: gd32f10x_can.h:171
can_trasnmit_message_struct::tx_efid
uint32_t tx_efid
Definition: gd32f10x_can.h:366
CAN_TMP_DLENC
#define CAN_TMP_DLENC
Definition: gd32f10x_can.h:229
TMDATA0_DB1
#define TMDATA0_DB1(regval)
Definition: gd32f10x_can.h:455
TMDATA1_DB6
#define TMDATA1_DB6(regval)
Definition: gd32f10x_can.h:470
can_trasnmit_message_struct::tx_data
uint8_t tx_data[8]
Definition: gd32f10x_can.h:370
CAN_NOMAILBOX
#define CAN_NOMAILBOX
Definition: gd32f10x_can.h:568
CAN_TMDATA1
#define CAN_TMDATA1(canx, bank)
Definition: gd32f10x_can.h:117
CAN_TSTAT_TME0
#define CAN_TSTAT_TME0
Definition: gd32f10x_can.h:170
CAN_FF_STANDARD
#define CAN_FF_STANDARD
Definition: gd32f10x_can.h:571
CAN_TMP
#define CAN_TMP(canx, bank)
Definition: gd32f10x_can.h:115
CAN_MAILBOX0
#define CAN_MAILBOX0
Definition: gd32f10x_can.h:565
CAN_MAILBOX2
#define CAN_MAILBOX2
Definition: gd32f10x_can.h:567
CAN_MAILBOX1
#define CAN_MAILBOX1
Definition: gd32f10x_can.h:566
TMDATA1_DB7
#define TMDATA1_DB7(regval)
Definition: gd32f10x_can.h:473
TMDATA0_DB2
#define TMDATA0_DB2(regval)
Definition: gd32f10x_can.h:458
TMDATA1_DB4
#define TMDATA1_DB4(regval)
Definition: gd32f10x_can.h:464
TMI_SFID
#define TMI_SFID(regval)
Definition: gd32f10x_can.h:449
TMI_EFID
#define TMI_EFID(regval)
Definition: gd32f10x_can.h:446
CAN_TMI_TEN
#define CAN_TMI_TEN
Definition: gd32f10x_can.h:222
uint8_t can_receive_error_number_get ( uint32_t can_periph )

get CAN receive error number

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
error number

Definition at line 657 of file gd32f10x_can.c.

658 {
659 uint8_t val;
660
661 val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_RECNT) >> 24U);
662 return val;
663 }
CAN_ERR
#define CAN_ERR(canx)
Definition: gd32f10x_can.h:29
CAN_ERR_RECNT
#define CAN_ERR_RECNT
Definition: gd32f10x_can.h:211
uint8_t can_receive_message_length_get | ( | uint32_t | can_periph,
 |  | uint8_t | fifo_number
 | ) |  |

CAN receive message length.

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL \
  • CAN_FIFOx(x=0,1)
[out] none
Return values
message length

Definition at line 530 of file gd32f10x_can.c.

531 {
532 uint8_t val = 0U;
533
534 if(CAN_FIFO0 == fifo_number){
535 val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK);
536 }else if(CAN_FIFO1 == fifo_number){
537 val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK);
538 }else{
539 /* illegal parameter */
540 }
541 return val;
542 }
CAN_RFIF_RFL_MASK
#define CAN_RFIF_RFL_MASK
Definition: gd32f10x_can.h:579
CAN_RFIFO1
#define CAN_RFIFO1(canx)
Definition: gd32f10x_can.h:27
CAN_RFIFO0
#define CAN_RFIFO0(canx)
Definition: gd32f10x_can.h:26
CAN_FIFO1
#define CAN_FIFO1
Definition: gd32f10x_can.h:576
CAN_FIFO0
#define CAN_FIFO0
Definition: gd32f10x_can.h:575
void can_time_trigger_mode_disable ( uint32_t can_periph )

disable CAN time trigger mode

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 303 of file gd32f10x_can.c.

304 {
305 uint8_t mailbox_number;
306
307 /* disable the TCC mode */
308 CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
309 /* reset TSEN bits */
310 for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){
311 CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN;
312 }
313 }
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_TMP
#define CAN_TMP(canx, bank)
Definition: gd32f10x_can.h:115
CAN_CTL_TTC
#define CAN_CTL_TTC
Definition: gd32f10x_can.h:138
CAN_TMP_TSEN
#define CAN_TMP_TSEN
Definition: gd32f10x_can.h:230
void can_time_trigger_mode_enable ( uint32_t can_periph )

enable CAN time trigger mode

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 284 of file gd32f10x_can.c.

285 {
286 uint8_t mailbox_number;
287
288 /* enable the tcc mode */
289 CAN_CTL(can_periph) |= CAN_CTL_TTC;
290 /* enable time stamp */
291 for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){
292 CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN;
293 }
294 }
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_TMP
#define CAN_TMP(canx, bank)
Definition: gd32f10x_can.h:115
CAN_CTL_TTC
#define CAN_CTL_TTC
Definition: gd32f10x_can.h:138
CAN_TMP_TSEN
#define CAN_TMP_TSEN
Definition: gd32f10x_can.h:230
void can_transmission_stop | ( | uint32_t | can_periph,
 |  | uint8_t | mailbox_number
 | ) |  |

stop CAN transmission

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] mailbox_number only one parameter can be selected which is shown as below:
  • CAN_MAILBOXx(x=0,1,2)
[out] none
Return values
none

Definition at line 436 of file gd32f10x_can.c.

437 {
438 if(CAN_MAILBOX0 == mailbox_number){
439 CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
440 }else if(CAN_MAILBOX1 == mailbox_number){
441 CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
442 }else if(CAN_MAILBOX2 == mailbox_number){
443 CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
444 }else{
445 /* illegal parameter*/
446 }
447 }
CAN_TSTAT
#define CAN_TSTAT(canx)
Definition: gd32f10x_can.h:25
CAN_TSTAT_MST1
#define CAN_TSTAT_MST1
Definition: gd32f10x_can.h:163
CAN_TSTAT_MST0
#define CAN_TSTAT_MST0
Definition: gd32f10x_can.h:158
CAN_MAILBOX0
#define CAN_MAILBOX0
Definition: gd32f10x_can.h:565
CAN_MAILBOX2
#define CAN_MAILBOX2
Definition: gd32f10x_can.h:567
CAN_MAILBOX1
#define CAN_MAILBOX1
Definition: gd32f10x_can.h:566
CAN_TSTAT_MST2
#define CAN_TSTAT_MST2
Definition: gd32f10x_can.h:168
uint8_t can_transmit_error_number_get ( uint32_t can_periph )

get CAN transmit error number

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
error number

Definition at line 672 of file gd32f10x_can.c.

673 {
674 uint8_t val;
675
676 val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_TECNT) >> 16U);
677 return val;
678 }
CAN_ERR
#define CAN_ERR(canx)
Definition: gd32f10x_can.h:29
CAN_ERR_TECNT
#define CAN_ERR_TECNT
Definition: gd32f10x_can.h:210
can_transmit_state_enum can_transmit_states | ( | uint32_t | can_periph,
 |  | uint8_t | mailbox_number
 | ) |  |

get CAN transmit state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] mailbox_number
  • CAN_MAILBOX(x=0,1,2)
[out] none
Return values
can_transmit_state_enum

Definition at line 385 of file gd32f10x_can.c.

386 {
387 can_transmit_state_enum state = CAN_TRANSMIT_FAILED;
388 uint32_t val = 0U;
389
390 switch(mailbox_number){
391 case CAN_MAILBOX0:
392 val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0);
393 break;
394 case CAN_MAILBOX1:
395 val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1);
396 break;
397 case CAN_MAILBOX2:
398 val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2);
399 break;
400 default:
401 val = CAN_TRANSMIT_FAILED;
402 break;
403 }
404 switch(val){
405 /* transmit pending */
406 case (CAN_STATE_PENDING):
407 state = CAN_TRANSMIT_PENDING;
408 break;
409 /* transmit succeeded */
410 case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0):
411 state = CAN_TRANSMIT_OK;
412 break;
413 case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1):
414 state = CAN_TRANSMIT_OK;
415 break;
416 case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2):
417 state = CAN_TRANSMIT_OK;
418 break;
419 default:
420 state = CAN_TRANSMIT_FAILED;
421 break;
422 }
423 return state;
424 }
CAN_TSTAT_MTFNERR1
#define CAN_TSTAT_MTFNERR1
Definition: gd32f10x_can.h:160
can_transmit_state_enum
can_transmit_state_enum
Definition: gd32f10x_can.h:413
CAN_TSTAT
#define CAN_TSTAT(canx)
Definition: gd32f10x_can.h:25
CAN_TSTAT_MTF1
#define CAN_TSTAT_MTF1
Definition: gd32f10x_can.h:159
CAN_TRANSMIT_FAILED
Definition: gd32f10x_can.h:415
CAN_TSTAT_TME2
#define CAN_TSTAT_TME2
Definition: gd32f10x_can.h:172
CAN_TSTAT_TME1
#define CAN_TSTAT_TME1
Definition: gd32f10x_can.h:171
CAN_TSTAT_MTF0
#define CAN_TSTAT_MTF0
Definition: gd32f10x_can.h:154
CAN_TRANSMIT_PENDING
Definition: gd32f10x_can.h:417
CAN_TSTAT_TME0
#define CAN_TSTAT_TME0
Definition: gd32f10x_can.h:170
CAN_TSTAT_MTF2
#define CAN_TSTAT_MTF2
Definition: gd32f10x_can.h:164
CAN_MAILBOX0
#define CAN_MAILBOX0
Definition: gd32f10x_can.h:565
CAN_TRANSMIT_OK
Definition: gd32f10x_can.h:416
CAN_MAILBOX2
#define CAN_MAILBOX2
Definition: gd32f10x_can.h:567
CAN_MAILBOX1
#define CAN_MAILBOX1
Definition: gd32f10x_can.h:566
CAN_TSTAT_MTFNERR0
#define CAN_TSTAT_MTFNERR0
Definition: gd32f10x_can.h:155
CAN_STATE_PENDING
#define CAN_STATE_PENDING
Definition: gd32f10x_can.h:522
CAN_TSTAT_MTFNERR2
#define CAN_TSTAT_MTFNERR2
Definition: gd32f10x_can.h:165
ErrStatus can_wakeup ( uint32_t can_periph )

wake up CAN

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 614 of file gd32f10x_can.c.

615 {
616 ErrStatus flag = ERROR;
617 uint32_t timeout = CAN_TIMEOUT;
618
619 /* wakeup */
620 CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
621
622 while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){
623 timeout--;
624 }
625 if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
626 flag = ERROR;
627 }else{
628 flag = SUCCESS;
629 }
630 return flag;
631 }
CAN_STAT
#define CAN_STAT(canx)
Definition: gd32f10x_can.h:24
CAN_CTL_SLPWMOD
#define CAN_CTL_SLPWMOD
Definition: gd32f10x_can.h:132
CAN_TIMEOUT
#define CAN_TIMEOUT
Definition: gd32f10x_can.h:605
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_STAT_SLPWS
#define CAN_STAT_SLPWS
Definition: gd32f10x_can.h:144
ErrStatus can_working_mode_set | ( | uint32_t | can_periph,
 |  | uint8_t | working_mode
 | ) |  |

set CAN working mode

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] can_working_mode
  • CAN_MODE_INITIALIZE
  • CAN_MODE_NORMAL
  • CAN_MODE_SLEEP
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 555 of file gd32f10x_can.c.

556 {
557 ErrStatus flag = ERROR;
558 /* timeout for IWS or also for SLPWS bits */
559 uint32_t timeout = CAN_TIMEOUT;
560
561 if(CAN_MODE_INITIALIZE == working_mode){
562 /* disable sleep mode */
563 CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD);
564 /* set initialize mode */
565 CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD;
566 /* wait the acknowledge */
567 while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
568 timeout--;
569 }
570 if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
571 flag = ERROR;
572 }else{
573 flag = SUCCESS;
574 }
575 }else if(CAN_MODE_NORMAL == working_mode){
576 /* enter normal mode */
577 CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD);
578 /* wait the acknowledge */
579 while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){
580 timeout--;
581 }
582 if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){
583 flag = ERROR;
584 }else{
585 flag = SUCCESS;
586 }
587 }else if(CAN_MODE_SLEEP == working_mode){
588 /* disable initialize mode */
589 CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD);
590 /* set sleep mode */
591 CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD;
592 /* wait the acknowledge */
593 while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){
594 timeout--;
595 }
596 if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
597 flag = ERROR;
598 }else{
599 flag = SUCCESS;
600 }
601 }else{
602 flag = ERROR;
603 }
604 return flag;
605 }
CAN_MODE_NORMAL
#define CAN_MODE_NORMAL
Definition: gd32f10x_can.h:586
CAN_CTL_IWMOD
#define CAN_CTL_IWMOD
Definition: gd32f10x_can.h:131
CAN_STAT
#define CAN_STAT(canx)
Definition: gd32f10x_can.h:24
CAN_MODE_SLEEP
#define CAN_MODE_SLEEP
Definition: gd32f10x_can.h:587
CAN_MODE_INITIALIZE
#define CAN_MODE_INITIALIZE
Definition: gd32f10x_can.h:585
CAN_CTL_SLPWMOD
#define CAN_CTL_SLPWMOD
Definition: gd32f10x_can.h:132
CAN_TIMEOUT
#define CAN_TIMEOUT
Definition: gd32f10x_can.h:605
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_STAT_IWS
#define CAN_STAT_IWS
Definition: gd32f10x_can.h:143
CAN_STAT_SLPWS
#define CAN_STAT_SLPWS
Definition: gd32f10x_can.h:144
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_crc.h File Reference

definitions for the CRC More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | CRC CRC_BASE
#define | CRC_DATA REG32(CRC + 0x00U)
#define | CRC_FDATA REG32(CRC + 0x04U)
#define | CRC_CTL REG32(CRC + 0x08U)
#define | CRC_DATA_DATA BITS(0,31)
#define | CRC_FDATA_FDATA BITS(0,7)
#define | CRC_CTL_RST BIT(0)

Functions

void | crc_deinit (void)
deinit CRC calculation unit More...
void | crc_data_register_reset (void)
reset data register to the value of initializaiton data register More...
uint32_t | crc_data_register_read (void)
read the data register More...
uint8_t | crc_free_data_register_read (void)
read the free data register More...
void | crc_free_data_register_write (uint8_t free_data)
write the free data register More...
uint32_t | crc_single_data_calculate (uint32_t sdata)
CRC calculate a 32-bit data. More...
uint32_t | crc_block_data_calculate (uint32_t array[], uint32_t size)
CRC calculate a 32-bit data array. More...

Detailed Description

definitions for the CRC

Definition in file gd32f10x_crc.h.

Macro Definition Documentation

#define CRC CRC_BASE

Definition at line 19 of file gd32f10x_crc.h.

#define CRC_CTL REG32(CRC + 0x08U)

CRC control register

Definition at line 24 of file gd32f10x_crc.h.

#define CRC_CTL_RST BIT(0)

CRC reset CRC_DATA register bit

Definition at line 34 of file gd32f10x_crc.h.

#define CRC_DATA REG32(CRC + 0x00U)

CRC data register

Definition at line 22 of file gd32f10x_crc.h.

#define CRC_DATA_DATA BITS(0,31)

CRC calculation result bits

Definition at line 28 of file gd32f10x_crc.h.

#define CRC_FDATA REG32(CRC + 0x04U)

CRC free data register

Definition at line 23 of file gd32f10x_crc.h.

#define CRC_FDATA_FDATA BITS(0,7)

CRC free data bits

Definition at line 31 of file gd32f10x_crc.h.

Function Documentation

uint32_t crc_block_data_calculate | ( | uint32_t | array[],
 |  | uint32_t | size
 | ) |  |

CRC calculate a 32-bit data array.

Parameters
[in] | array | pointer to an array of 32 bit data words
[in] | size | size of the array
[out] | none
Return values
32-bit CRC calculate value

Definition at line 95 of file gd32f10x_crc.c.

96 {
97 uint32_t index;
98 for(index = 0U; index < size; index++){
99 CRC_DATA = array[index];
100 }
101 return (CRC_DATA);
102 }
CRC_DATA
#define CRC_DATA
Definition: gd32f10x_crc.h:22
uint32_t crc_data_register_read ( void )

read the data register

Parameters
[in] | none
[out] | none
Return values
32-bit value of the data register

Definition at line 45 of file gd32f10x_crc.c.

46 {
47 uint32_t data;
48 data = CRC_DATA;
49 return (data);
50 }
CRC_DATA
#define CRC_DATA
Definition: gd32f10x_crc.h:22
void crc_data_register_reset ( void )

reset data register to the value of initializaiton data register

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 34 of file gd32f10x_crc.c.

35 {
36 CRC_CTL |= (uint32_t)CRC_CTL_RST;
37 }
CRC_CTL
#define CRC_CTL
Definition: gd32f10x_crc.h:24
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f10x_crc.h:34
void crc_deinit ( void )

deinit CRC calculation unit

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_crc.c.

22 {
23 CRC_DATA = (uint32_t)0xFFFFFFFFU;
24 CRC_FDATA = (uint32_t)0x00000000U;
25 CRC_CTL = (uint32_t)CRC_CTL_RST;
26 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f10x_crc.h:23
CRC_CTL
#define CRC_CTL
Definition: gd32f10x_crc.h:24
CRC_DATA
#define CRC_DATA
Definition: gd32f10x_crc.h:22
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f10x_crc.h:34
uint8_t crc_free_data_register_read ( void )

read the free data register

Parameters
[in] | none
[out] | none
Return values
8-bit value of the free data register

Definition at line 58 of file gd32f10x_crc.c.

59 {
60 uint8_t fdata;
61 fdata = (uint8_t)CRC_FDATA;
62 return (fdata);
63 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f10x_crc.h:23
void crc_free_data_register_write ( uint8_t free_data )

write the free data register

Parameters
[in] | free_data | specify 8-bit data
[out] | none
Return values
none

Definition at line 71 of file gd32f10x_crc.c.

72 {
73 CRC_FDATA = (uint32_t)free_data;
74 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f10x_crc.h:23
uint32_t crc_single_data_calculate ( uint32_t sdata )

CRC calculate a 32-bit data.

Parameters
[in] | sdata | specify 32-bit data
[out] | none
Return values
32-bit CRC calculate value

Definition at line 82 of file gd32f10x_crc.c.

83 {
84 CRC_DATA = sdata;
85 return (CRC_DATA);
86 }
CRC_DATA
#define CRC_DATA
Definition: gd32f10x_crc.h:22
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_dac.h File Reference

definitions for the DAC More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | DAC DAC_BASE
#define | DAC0 0U
#define | DAC1 1U
#define | DAC_CTL REG32(DAC + 0x00U)
#define | DAC_SWT REG32(DAC + 0x04U)
#define | DAC0_R12DH REG32(DAC + 0x08U)
#define | DAC0_L12DH REG32(DAC + 0x0CU)
#define | DAC0_R8DH REG32(DAC + 0x10U)
#define | DAC1_R12DH REG32(DAC + 0x14U)
#define | DAC1_L12DH REG32(DAC + 0x18U)
#define | DAC1_R8DH REG32(DAC + 0x1CU)
#define | DACC_R12DH REG32(DAC + 0x20U)
#define | DACC_L12DH REG32(DAC + 0x24U)
#define | DACC_R8DH REG32(DAC + 0x28U)
#define | DAC0_DO REG32(DAC + 0x2CU)
#define | DAC1_DO REG32(DAC + 0x30U)
#define | DAC_CTL_DEN0 BIT(0)
#define | DAC_CTL_DBOFF0 BIT(1)
#define | DAC_CTL_DTEN0 BIT(2)
#define | DAC_CTL_DTSEL0 BITS(3,5)
#define | DAC_CTL_DWM0 BITS(6,7)
#define | DAC_CTL_DWBW0 BITS(8,11)
#define | DAC_CTL_DDMAEN0 BIT(12)
#define | DAC_CTL_DEN1 BIT(16)
#define | DAC_CTL_DBOFF1 BIT(17)
#define | DAC_CTL_DTEN1 BIT(18)
#define | DAC_CTL_DTSEL1 BITS(19,21)
#define | DAC_CTL_DWM1 BITS(22,23)
#define | DAC_CTL_DWBW1 BITS(24,27)
#define | DAC_CTL_DDMAEN1 BIT(28)
#define | DAC_SWT_SWTR0 BIT(0)
#define | DAC_SWT_SWTR1 BIT(1)
#define | DAC0_R12DH_DAC0_DH BITS(0,11)
#define | DAC0_L12DH_DAC0_DH BITS(4,15)
#define | DAC0_R8DH_DAC0_DH BITS(0,7)
#define | DAC1_R12DH_DAC1_DH BITS(0,11)
#define | DAC1_L12DH_DAC1_DH BITS(4,15)
#define | DAC1_R8DH_DAC1_DH BITS(0,7)
#define | DACC_R12DH_DAC0_DH BITS(0,11)
#define | DACC_R12DH_DAC1_DH BITS(16,27)
#define | DACC_L12DH_DAC0_DH BITS(4,15)
#define | DACC_L12DH_DAC1_DH BITS(20,31)
#define | DACC_R8DH_DAC0_DH BITS(0,7)
#define | DACC_R8DH_DAC1_DH BITS(8,15)
#define | DAC0_DO_DAC0_DO BITS(0,11)
#define | DAC1_DO_DAC1_DO BITS(0,11)
#define | CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
#define | DAC_TRIGGER_T5_TRGO CTL_DTSEL(0)
#define | DAC_TRIGGER_T7_TRGO CTL_DTSEL(1)
#define | DAC_TRIGGER_T6_TRGO CTL_DTSEL(2)
#define | DAC_TRIGGER_T4_TRGO CTL_DTSEL(3)
#define | DAC_TRIGGER_T1_TRGO CTL_DTSEL(4)
#define | DAC_TRIGGER_T3_TRGO CTL_DTSEL(5)
#define | DAC_TRIGGER_EXTI_9 CTL_DTSEL(6)
#define | DAC_TRIGGER_SOFTWARE CTL_DTSEL(7)
#define | CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
#define | DAC_WAVE_DISABLE CTL_DWM(0)
#define | DAC_WAVE_MODE_LFSR CTL_DWM(1)
#define | DAC_WAVE_MODE_TRIANGLE CTL_DWM(2)
#define | DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
#define | DAC_WAVE_BIT_WIDTH_1 DWBW(0)
#define | DAC_WAVE_BIT_WIDTH_2 DWBW(1)
#define | DAC_WAVE_BIT_WIDTH_3 DWBW(2)
#define | DAC_WAVE_BIT_WIDTH_4 DWBW(3)
#define | DAC_WAVE_BIT_WIDTH_5 DWBW(4)
#define | DAC_WAVE_BIT_WIDTH_6 DWBW(5)
#define | DAC_WAVE_BIT_WIDTH_7 DWBW(6)
#define | DAC_WAVE_BIT_WIDTH_8 DWBW(7)
#define | DAC_WAVE_BIT_WIDTH_9 DWBW(8)
#define | DAC_WAVE_BIT_WIDTH_10 DWBW(9)
#define | DAC_WAVE_BIT_WIDTH_11 DWBW(10)
#define | DAC_WAVE_BIT_WIDTH_12 DWBW(11)
#define | DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1
#define | DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2
#define | DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3
#define | DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4
#define | DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5
#define | DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6
#define | DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7
#define | DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8
#define | DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9
#define | DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10
#define | DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11
#define | DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12
#define | DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1
#define | DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2
#define | DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3
#define | DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4
#define | DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5
#define | DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6
#define | DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7
#define | DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8
#define | DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9
#define | DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10
#define | DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11
#define | DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12
#define | DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define | DAC_ALIGN_12B_R DATA_ALIGN(0)
#define | DAC_ALIGN_12B_L DATA_ALIGN(1)
#define | DAC_ALIGN_8B_R DATA_ALIGN(2)

Functions

void | dac_deinit (void)
deinitialize DAC More...
void | dac_enable (uint32_t dac_periph)
enable DAC More...
void | dac_disable (uint32_t dac_periph)
disable DAC More...
void | dac_dma_enable (uint32_t dac_periph)
enable DAC DMA function More...
void | dac_dma_disable (uint32_t dac_periph)
disable DAC DMA function More...
void | dac_output_buffer_enable (uint32_t dac_periph)
enable DAC output buffer More...
void | dac_output_buffer_disable (uint32_t dac_periph)
disable DAC output buffer More...
void | dac_trigger_enable (uint32_t dac_periph)
enable DAC trigger More...
void | dac_trigger_disable (uint32_t dac_periph)
disable DAC trigger More...
void | dac_software_trigger_enable (uint32_t dac_periph)
enable DAC software trigger More...
void | dac_software_trigger_disable (uint32_t dac_periph)
disable DAC software trigger More...
void | dac_trigger_source_config (uint32_t dac_periph, uint32_t triggersource)
set DAC trigger source More...
void | dac_wave_mode_config (uint32_t dac_periph, uint32_t wave_mode)
configure DAC wave mode More...
void | dac_wave_bit_width_config (uint32_t dac_periph, uint32_t bit_width)
configure DAC wave bit width More...
void | dac_lfsr_noise_config (uint32_t dac_periph, uint32_t unmask_bits)
configure DAC LFSR noise mode More...
void | dac_triangle_noise_config (uint32_t dac_periph, uint32_t amplitude)
configure DAC triangle noise mode More...
uint16_t | dac_output_value_get (uint32_t dac_periph)
get DAC output value More...
void | dac_data_set (uint32_t dac_periph, uint32_t dac_align, uint16_t data)
set the DAC specified data holding register value More...
void | dac_concurrent_data_set (uint32_t dac_align, uint16_t data0, uint16_t data1)
set DAC concurrent mode data holding register value More...
void | dac_concurrent_enable (void)
enable DAC concurrent mode More...
void | dac_concurrent_disable (void)
disable DAC concurrent mode More...
void | dac_concurrent_software_trigger_enable (void)
enable DAC concurrent software trigger function More...
void | dac_concurrent_software_trigger_disable (void)
disable DAC concurrent software trigger function More...
void | dac_concurrent_output_buffer_enable (void)
enable DAC concurrent buffer function More...
void | dac_concurrent_output_buffer_disable (void)
disable DAC concurrent buffer function More...

Detailed Description

definitions for the DAC

Definition in file gd32f10x_dac.h.

Macro Definition Documentation

#define CTL_DTSEL ( regval ) (BITS(3,5) & ((uint32_t)(regval) << 3))

Definition at line 97 of file gd32f10x_dac.h.

#define CTL_DWM ( regval ) (BITS(6,7) & ((uint32_t)(regval) << 6))

Definition at line 112 of file gd32f10x_dac.h.

#define DAC DAC_BASE

Definition at line 19 of file gd32f10x_dac.h.

#define DAC0 0U

Definition at line 20 of file gd32f10x_dac.h.

#define DAC0_DO REG32(DAC + 0x2CU)

DAC0 data output register

Definition at line 35 of file gd32f10x_dac.h.

#define DAC0_DO_DAC0_DO BITS(0,11)

DAC0 12-bit output data bits

Definition at line 90 of file gd32f10x_dac.h.

#define DAC0_L12DH REG32(DAC + 0x0CU)

DAC0 12-bit left-aligned data holding register

Definition at line 27 of file gd32f10x_dac.h.

#define DAC0_L12DH_DAC0_DH BITS(4,15)

DAC0 12-bit left-aligned data bits

Definition at line 63 of file gd32f10x_dac.h.

#define DAC0_R12DH REG32(DAC + 0x08U)

DAC0 12-bit right-aligned data holding register

Definition at line 26 of file gd32f10x_dac.h.

#define DAC0_R12DH_DAC0_DH BITS(0,11)

DAC0 12-bit right-aligned data bits

Definition at line 60 of file gd32f10x_dac.h.

#define DAC0_R8DH REG32(DAC + 0x10U)

DAC0 8-bit right-aligned data holding register

Definition at line 28 of file gd32f10x_dac.h.

#define DAC0_R8DH_DAC0_DH BITS(0,7)

DAC0 8-bit right-aligned data bits

Definition at line 66 of file gd32f10x_dac.h.

#define DAC1 1U

Definition at line 21 of file gd32f10x_dac.h.

#define DAC1_DO REG32(DAC + 0x30U)

DAC1 data output register

Definition at line 36 of file gd32f10x_dac.h.

#define DAC1_DO_DAC1_DO BITS(0,11)

DAC1 12-bit output data bits

Definition at line 93 of file gd32f10x_dac.h.

#define DAC1_L12DH REG32(DAC + 0x18U)

DAC1 12-bit left-aligned data holding register

Definition at line 30 of file gd32f10x_dac.h.

#define DAC1_L12DH_DAC1_DH BITS(4,15)

DAC1 12-bit left-aligned data bits

Definition at line 72 of file gd32f10x_dac.h.

#define DAC1_R12DH REG32(DAC + 0x14U)

DAC1 12-bit right-aligned data holding register

Definition at line 29 of file gd32f10x_dac.h.

#define DAC1_R12DH_DAC1_DH BITS(0,11)

DAC1 12-bit right-aligned data bits

Definition at line 69 of file gd32f10x_dac.h.

#define DAC1_R8DH REG32(DAC + 0x1CU)

DAC1 8-bit right-aligned data holding register

Definition at line 31 of file gd32f10x_dac.h.

#define DAC1_R8DH_DAC1_DH BITS(0,7)

DAC1 8-bit right-aligned data bits

Definition at line 75 of file gd32f10x_dac.h.

#define DAC_ALIGN_12B_L DATA_ALIGN(1)

data left 12b alignment

Definition at line 163 of file gd32f10x_dac.h.

#define DAC_ALIGN_12B_R DATA_ALIGN(0)

data right 12b alignment

Definition at line 162 of file gd32f10x_dac.h.

#define DAC_ALIGN_8B_R DATA_ALIGN(2)

data right 8b alignment

Definition at line 164 of file gd32f10x_dac.h.

#define DAC_CTL REG32(DAC + 0x00U)

DAC control register

Definition at line 24 of file gd32f10x_dac.h.

#define DAC_CTL_DBOFF0 BIT(1)

DAC0 output buffer turn on/off bit

Definition at line 41 of file gd32f10x_dac.h.

#define DAC_CTL_DBOFF1 BIT(17)

DAC1 output buffer turn on/turn off bit

Definition at line 48 of file gd32f10x_dac.h.

#define DAC_CTL_DDMAEN0 BIT(12)

DAC0 DMA enable/disable bit

Definition at line 46 of file gd32f10x_dac.h.

#define DAC_CTL_DDMAEN1 BIT(28)

DAC1 DMA enable/disable bit

Definition at line 53 of file gd32f10x_dac.h.

#define DAC_CTL_DEN0 BIT(0)

DAC0 enable/disable bit

Definition at line 40 of file gd32f10x_dac.h.

#define DAC_CTL_DEN1 BIT(16)

DAC1 enable/disable bit

Definition at line 47 of file gd32f10x_dac.h.

#define DAC_CTL_DTEN0 BIT(2)

DAC0 trigger enable/disable bit

Definition at line 42 of file gd32f10x_dac.h.

#define DAC_CTL_DTEN1 BIT(18)

DAC1 trigger enable/disable bit

Definition at line 49 of file gd32f10x_dac.h.

#define DAC_CTL_DTSEL0 BITS(3,5)

DAC0 trigger source selection enable/disable bits

Definition at line 43 of file gd32f10x_dac.h.

#define DAC_CTL_DTSEL1 BITS(19,21)

DAC1 trigger source selection enable/disable bits

Definition at line 50 of file gd32f10x_dac.h.

#define DAC_CTL_DWBW0 BITS(8,11)

DAC0 noise wave bit width

Definition at line 45 of file gd32f10x_dac.h.

#define DAC_CTL_DWBW1 BITS(24,27)

DAC1 noise wave bit width

Definition at line 52 of file gd32f10x_dac.h.

#define DAC_CTL_DWM0 BITS(6,7)

DAC0 noise wave mode

Definition at line 44 of file gd32f10x_dac.h.

#define DAC_CTL_DWM1 BITS(22,23)

DAC1 noise wave mode

Definition at line 51 of file gd32f10x_dac.h.

#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1

unmask the LFSR bit0

Definition at line 133 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11

unmask the LFSR bits[10:0]

Definition at line 143 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12

unmask the LFSR bits[11:0]

Definition at line 144 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2

unmask the LFSR bits[1:0]

Definition at line 134 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3

unmask the LFSR bits[2:0]

Definition at line 135 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4

unmask the LFSR bits[3:0]

Definition at line 136 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5

unmask the LFSR bits[4:0]

Definition at line 137 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6

unmask the LFSR bits[5:0]

Definition at line 138 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7

unmask the LFSR bits[6:0]

Definition at line 139 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8

unmask the LFSR bits[7:0]

Definition at line 140 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9

unmask the LFSR bits[8:0]

Definition at line 141 of file gd32f10x_dac.h.

#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10

unmask the LFSR bits[9:0]

Definition at line 142 of file gd32f10x_dac.h.

#define DAC_SWT REG32(DAC + 0x04U)

DAC software trigger register

Definition at line 25 of file gd32f10x_dac.h.

#define DAC_SWT_SWTR0 BIT(0)

DAC0 software trigger bit, cleared by hardware

Definition at line 56 of file gd32f10x_dac.h.

#define DAC_SWT_SWTR1 BIT(1)

DAC1 software trigger bit, cleared by hardware

Definition at line 57 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1

triangle amplitude is 1

Definition at line 147 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10

triangle amplitude is 1023

Definition at line 156 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7

triangle amplitude is 127

Definition at line 153 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4

triangle amplitude is 15

Definition at line 150 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11

triangle amplitude is 2047

Definition at line 157 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8

triangle amplitude is 255

Definition at line 154 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2

triangle amplitude is 3

Definition at line 148 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5

triangle amplitude is 31

Definition at line 151 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12

triangle amplitude is 4095

Definition at line 158 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9

triangle amplitude is 511

Definition at line 155 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6

triangle amplitude is 63

Definition at line 152 of file gd32f10x_dac.h.

#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3

triangle amplitude is 7

Definition at line 149 of file gd32f10x_dac.h.

#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6)

EXTI interrupt line9 event

Definition at line 108 of file gd32f10x_dac.h.

#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7)

software trigger

Definition at line 109 of file gd32f10x_dac.h.

#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4)

TIMER1 TRGO

Definition at line 106 of file gd32f10x_dac.h.

#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5)

TIMER3 TRGO

Definition at line 107 of file gd32f10x_dac.h.

#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3)

TIMER4 TRGO

Definition at line 105 of file gd32f10x_dac.h.

#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0)

TIMER5 TRGO

Definition at line 98 of file gd32f10x_dac.h.

#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2)

TIMER6 TRGO

Definition at line 104 of file gd32f10x_dac.h.

#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1)

TIMER7 TRGO

Definition at line 100 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_1 DWBW(0)

bit width of the wave signal is 1

Definition at line 119 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_10 DWBW(9)

bit width of the wave signal is 10

Definition at line 128 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_11 DWBW(10)

bit width of the wave signal is 11

Definition at line 129 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_12 DWBW(11)

bit width of the wave signal is 12

Definition at line 130 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_2 DWBW(1)

bit width of the wave signal is 2

Definition at line 120 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_3 DWBW(2)

bit width of the wave signal is 3

Definition at line 121 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_4 DWBW(3)

bit width of the wave signal is 4

Definition at line 122 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_5 DWBW(4)

bit width of the wave signal is 5

Definition at line 123 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_6 DWBW(5)

bit width of the wave signal is 6

Definition at line 124 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_7 DWBW(6)

bit width of the wave signal is 7

Definition at line 125 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_8 DWBW(7)

bit width of the wave signal is 8

Definition at line 126 of file gd32f10x_dac.h.

#define DAC_WAVE_BIT_WIDTH_9 DWBW(8)

bit width of the wave signal is 9

Definition at line 127 of file gd32f10x_dac.h.

#define DAC_WAVE_DISABLE CTL_DWM(0)

wave disable

Definition at line 113 of file gd32f10x_dac.h.

#define DAC_WAVE_MODE_LFSR CTL_DWM(1)

LFSR noise mode

Definition at line 114 of file gd32f10x_dac.h.

#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2)

triangle noise mode

Definition at line 115 of file gd32f10x_dac.h.

#define DACC_L12DH REG32(DAC + 0x24U)

DAC concurrent mode 12-bit left-aligned data holding register

Definition at line 33 of file gd32f10x_dac.h.

#define DACC_L12DH_DAC0_DH BITS(4,15)

DAC concurrent mode DAC0 12-bit left-aligned data bits

Definition at line 82 of file gd32f10x_dac.h.

#define DACC_L12DH_DAC1_DH BITS(20,31)

DAC concurrent mode DAC1 12-bit left-aligned data bits

Definition at line 83 of file gd32f10x_dac.h.

#define DACC_R12DH REG32(DAC + 0x20U)

DAC concurrent mode 12-bit right-aligned data holding register

Definition at line 32 of file gd32f10x_dac.h.

#define DACC_R12DH_DAC0_DH BITS(0,11)

DAC concurrent mode DAC0 12-bit right-aligned data bits

Definition at line 78 of file gd32f10x_dac.h.

#define DACC_R12DH_DAC1_DH BITS(16,27)

DAC concurrent mode DAC1 12-bit right-aligned data bits

Definition at line 79 of file gd32f10x_dac.h.

#define DACC_R8DH REG32(DAC + 0x28U)

DAC concurrent mode 8-bit right-aligned data holding register

Definition at line 34 of file gd32f10x_dac.h.

#define DACC_R8DH_DAC0_DH BITS(0,7)

DAC concurrent mode DAC0 8-bit right-aligned data bits

Definition at line 86 of file gd32f10x_dac.h.

#define DACC_R8DH_DAC1_DH BITS(8,15)

DAC concurrent mode DAC1 8-bit right-aligned data bits

Definition at line 87 of file gd32f10x_dac.h.

#define DATA_ALIGN ( regval ) (BITS(0,1) & ((uint32_t)(regval) << 0))

Definition at line 161 of file gd32f10x_dac.h.

#define DWBW ( regval ) (BITS(8,11) & ((uint32_t)(regval) << 8))

Definition at line 118 of file gd32f10x_dac.h.

Function Documentation

void dac_concurrent_data_set | ( | uint32_t | dac_align,
 |  | uint16_t | data0,
 |  | uint16_t | data1
 | ) |  |

set DAC concurrent mode data holding register value

Parameters
[in] dac_align
  • DAC_ALIGN_8B_R: data right 8b alignment
  • DAC_ALIGN_12B_R: data right 12b alignment
  • DAC_ALIGN_12B_L: data left 12b alignment
[in] | data0 | data to be loaded
[in] | data1 | data to be loaded
[out] | none
Return values
none

Definition at line 487 of file gd32f10x_dac.c.

488 {
489 uint32_t data = 0U;
490 switch(dac_align){
491 /* data right 12b alignment */
492 case DAC_ALIGN_12B_R:
493 data = ((uint32_t)data1 << 16) | data0;
494 DACC_R12DH = data;
495 break;
496 /* data left 12b alignment */
497 case DAC_ALIGN_12B_L:
498 data = ((uint32_t)data1 << 16) | data0;
499 DACC_L12DH = data;
500 break;
501 /* data right 8b alignment */
502 case DAC_ALIGN_8B_R:
503 data = ((uint32_t)data1 << 8) | data0;
504 DACC_R8DH = data;
505 break;
506 default:
507 break;
508 }
509 }
DACC_L12DH
#define DACC_L12DH
Definition: gd32f10x_dac.h:33
DACC_R12DH
#define DACC_R12DH
Definition: gd32f10x_dac.h:32
DACC_R8DH
#define DACC_R8DH
Definition: gd32f10x_dac.h:34
DAC_ALIGN_12B_R
#define DAC_ALIGN_12B_R
Definition: gd32f10x_dac.h:162
DAC_ALIGN_12B_L
#define DAC_ALIGN_12B_L
Definition: gd32f10x_dac.h:163
DAC_ALIGN_8B_R
#define DAC_ALIGN_8B_R
Definition: gd32f10x_dac.h:164
void dac_concurrent_disable ( void )

disable DAC concurrent mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 366 of file gd32f10x_dac.c.

367 {
368 uint32_t ctl = 0U;
369 ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
370 DAC_CTL &= (~ctl);
371 }
DAC_CTL_DEN1
#define DAC_CTL_DEN1
Definition: gd32f10x_dac.h:47
DAC_CTL_DEN0
#define DAC_CTL_DEN0
Definition: gd32f10x_dac.h:40
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
void dac_concurrent_enable ( void )

enable DAC concurrent mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 353 of file gd32f10x_dac.c.

354 {
355 uint32_t ctl = 0U;
356 ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
357 DAC_CTL |= (ctl);
358 }
DAC_CTL_DEN1
#define DAC_CTL_DEN1
Definition: gd32f10x_dac.h:47
DAC_CTL_DEN0
#define DAC_CTL_DEN0
Definition: gd32f10x_dac.h:40
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
void dac_concurrent_output_buffer_disable ( void )

disable DAC concurrent buffer function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 418 of file gd32f10x_dac.c.

419 {
420 uint32_t ctl = 0U;
421 ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
422 DAC_CTL |= (ctl);
423 }
DAC_CTL_DBOFF1
#define DAC_CTL_DBOFF1
Definition: gd32f10x_dac.h:48
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DBOFF0
#define DAC_CTL_DBOFF0
Definition: gd32f10x_dac.h:41
void dac_concurrent_output_buffer_enable ( void )

enable DAC concurrent buffer function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 405 of file gd32f10x_dac.c.

406 {
407 uint32_t ctl = 0U;
408 ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
409 DAC_CTL &= (~ctl);
410 }
DAC_CTL_DBOFF1
#define DAC_CTL_DBOFF1
Definition: gd32f10x_dac.h:48
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DBOFF0
#define DAC_CTL_DBOFF0
Definition: gd32f10x_dac.h:41
void dac_concurrent_software_trigger_disable ( void )

disable DAC concurrent software trigger function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 392 of file gd32f10x_dac.c.

393 {
394 uint32_t swt = 0U;
395 swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
396 DAC_SWT &= (~swt);
397 }
DAC_SWT
#define DAC_SWT
Definition: gd32f10x_dac.h:25
DAC_SWT_SWTR0
#define DAC_SWT_SWTR0
Definition: gd32f10x_dac.h:56
DAC_SWT_SWTR1
#define DAC_SWT_SWTR1
Definition: gd32f10x_dac.h:57
void dac_concurrent_software_trigger_enable ( void )

enable DAC concurrent software trigger function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 379 of file gd32f10x_dac.c.

380 {
381 uint32_t swt = 0U;
382 swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
383 DAC_SWT |= (swt);
384 }
DAC_SWT
#define DAC_SWT
Definition: gd32f10x_dac.h:25
DAC_SWT_SWTR0
#define DAC_SWT_SWTR0
Definition: gd32f10x_dac.h:56
DAC_SWT_SWTR1
#define DAC_SWT_SWTR1
Definition: gd32f10x_dac.h:57
void dac_data_set | ( | uint32_t | dac_periph,
 |  | uint32_t | dac_align,
 |  | uint16_t | data
 | ) |  |

set the DAC specified data holding register value

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] dac_align
  • DAC_ALIGN_8B_R: data right 8b alignment
  • DAC_ALIGN_12B_R: data right 12b alignment
  • DAC_ALIGN_12B_L: data left 12b alignment
[in] | data | data to be loaded
[out] | none
Return values
none

Definition at line 437 of file gd32f10x_dac.c.

438 {
439 if(DAC0 == dac_periph){
440 switch(dac_align){
441 /* data right 12b alignment */
442 case DAC_ALIGN_12B_R:
443 DAC0_R12DH = data;
444 break;
445 /* data left 12b alignment */
446 case DAC_ALIGN_12B_L:
447 DAC0_L12DH = data;
448 break;
449 /* data right 8b alignment */
450 case DAC_ALIGN_8B_R:
451 DAC0_R8DH = data;
452 break;
453 default:
454 break;
455 }
456 }else{
457 switch(dac_align){
458 /* data right 12b alignment */
459 case DAC_ALIGN_12B_R:
460 DAC1_R12DH = data;
461 break;
462 /* data left 12b alignment */
463 case DAC_ALIGN_12B_L:
464 DAC1_L12DH = data;
465 break;
466 /* data right 8b alignment */
467 case DAC_ALIGN_8B_R:
468 DAC1_R8DH = data;
469 break;
470 default:
471 break;
472 }
473 }
474 }
DAC_ALIGN_12B_R
#define DAC_ALIGN_12B_R
Definition: gd32f10x_dac.h:162
DAC1_R8DH
#define DAC1_R8DH
Definition: gd32f10x_dac.h:31
DAC_ALIGN_12B_L
#define DAC_ALIGN_12B_L
Definition: gd32f10x_dac.h:163
DAC_ALIGN_8B_R
#define DAC_ALIGN_8B_R
Definition: gd32f10x_dac.h:164
DAC0_R8DH
#define DAC0_R8DH
Definition: gd32f10x_dac.h:28
DAC0_L12DH
#define DAC0_L12DH
Definition: gd32f10x_dac.h:27
DAC1_R12DH
#define DAC1_R12DH
Definition: gd32f10x_dac.h:29
DAC0_R12DH
#define DAC0_R12DH
Definition: gd32f10x_dac.h:26
DAC1_L12DH
#define DAC1_L12DH
Definition: gd32f10x_dac.h:30
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_deinit ( void )

deinitialize DAC

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_dac.c.

22 {
23 rcu_periph_reset_enable(RCU_DACRST);
24 rcu_periph_reset_disable(RCU_DACRST);
25 }
RCU_DACRST
Definition: gd32f10x_rcu.h:474
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void dac_disable ( uint32_t dac_periph )

disable DAC

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 50 of file gd32f10x_dac.c.

51 {
52 if(DAC0 == dac_periph){
53 DAC_CTL &= ~DAC_CTL_DEN0;
54 }else{
55 DAC_CTL &= ~DAC_CTL_DEN1;
56 }
57 }
DAC_CTL_DEN1
#define DAC_CTL_DEN1
Definition: gd32f10x_dac.h:47
DAC_CTL_DEN0
#define DAC_CTL_DEN0
Definition: gd32f10x_dac.h:40
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_dma_disable ( uint32_t dac_periph )

disable DAC DMA function

Parameters
[in] dac_periph
  • DACx(x=0,1)
[out] none
Return values
none

Definition at line 82 of file gd32f10x_dac.c.

83 {
84 if(DAC0 == dac_periph){
85 DAC_CTL &= ~DAC_CTL_DDMAEN0;
86 }else{
87 DAC_CTL &= ~DAC_CTL_DDMAEN1;
88 }
89 }
DAC_CTL_DDMAEN0
#define DAC_CTL_DDMAEN0
Definition: gd32f10x_dac.h:46
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DDMAEN1
#define DAC_CTL_DDMAEN1
Definition: gd32f10x_dac.h:53
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_dma_enable ( uint32_t dac_periph )

enable DAC DMA function

Parameters
[in] dac_periph
  • DACx(x=0,1)
[out] none
Return values
none

Definition at line 66 of file gd32f10x_dac.c.

67 {
68 if(DAC0 == dac_periph){
69 DAC_CTL |= DAC_CTL_DDMAEN0;
70 }else{
71 DAC_CTL |= DAC_CTL_DDMAEN1;
72 }
73 }
DAC_CTL_DDMAEN0
#define DAC_CTL_DDMAEN0
Definition: gd32f10x_dac.h:46
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DDMAEN1
#define DAC_CTL_DDMAEN1
Definition: gd32f10x_dac.h:53
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_enable ( uint32_t dac_periph )

enable DAC

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 34 of file gd32f10x_dac.c.

35 {
36 if(DAC0 == dac_periph){
37 DAC_CTL |= DAC_CTL_DEN0;
38 }else{
39 DAC_CTL |= DAC_CTL_DEN1;
40 }
41 }
DAC_CTL_DEN1
#define DAC_CTL_DEN1
Definition: gd32f10x_dac.h:47
DAC_CTL_DEN0
#define DAC_CTL_DEN0
Definition: gd32f10x_dac.h:40
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_lfsr_noise_config | ( | uint32_t | dac_periph,
 |  | uint32_t | unmask_bits
 | ) |  |

configure DAC LFSR noise mode

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] unmask_bits
  • DAC_LFSR_BIT0: unmask the LFSR bit0
  • DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
  • DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
  • DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
  • DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
  • DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
  • DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
  • DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
  • DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
  • DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
  • DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
  • DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
[out] none
Return values
none

Definition at line 287 of file gd32f10x_dac.c.

288 {
289 if(DAC0 == dac_periph){
290 DAC_CTL &= ~DAC_CTL_DWBW0;
291 DAC_CTL |= unmask_bits;
292 }else{
293 DAC_CTL &= ~DAC_CTL_DWBW1;
294 DAC_CTL |= unmask_bits << 16;
295 }
296 }
DAC_CTL_DWBW1
#define DAC_CTL_DWBW1
Definition: gd32f10x_dac.h:52
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DWBW0
#define DAC_CTL_DWBW0
Definition: gd32f10x_dac.h:45
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_output_buffer_disable ( uint32_t dac_periph )

disable DAC output buffer

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 114 of file gd32f10x_dac.c.

115 {
116 if(DAC0 == dac_periph){
117 DAC_CTL |= DAC_CTL_DBOFF0;
118 }else{
119 DAC_CTL |= DAC_CTL_DBOFF1;
120 }
121 }
DAC_CTL_DBOFF1
#define DAC_CTL_DBOFF1
Definition: gd32f10x_dac.h:48
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DBOFF0
#define DAC_CTL_DBOFF0
Definition: gd32f10x_dac.h:41
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_output_buffer_enable ( uint32_t dac_periph )

enable DAC output buffer

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 98 of file gd32f10x_dac.c.

99 {
100 if(DAC0 == dac_periph){
101 DAC_CTL &= ~DAC_CTL_DBOFF0;
102 }else{
103 DAC_CTL &= ~DAC_CTL_DBOFF1;
104 }
105 }
DAC_CTL_DBOFF1
#define DAC_CTL_DBOFF1
Definition: gd32f10x_dac.h:48
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DBOFF0
#define DAC_CTL_DBOFF0
Definition: gd32f10x_dac.h:41
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
uint16_t dac_output_value_get ( uint32_t dac_periph )

get DAC output value

Parameters
[in] dac_periph
  • DACx(x=0,1)
[out] none
Return values
DAC output data

Definition at line 336 of file gd32f10x_dac.c.

337 {
338 uint16_t data = 0U;
339 if(DAC0 == dac_periph){
340 data = (uint16_t)DAC0_DO;
341 }else{
342 data = (uint16_t)DAC1_DO;
343 }
344 return data;
345 }
DAC0_DO
#define DAC0_DO
Definition: gd32f10x_dac.h:35
DAC1_DO
#define DAC1_DO
Definition: gd32f10x_dac.h:36
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_software_trigger_disable ( uint32_t dac_periph )

disable DAC software trigger

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 177 of file gd32f10x_dac.c.

178 {
179 if(DAC0 == dac_periph){
180 DAC_SWT &= ~DAC_SWT_SWTR0;
181 }else{
182 DAC_SWT &= ~DAC_SWT_SWTR1;
183 }
184 }
DAC_SWT
#define DAC_SWT
Definition: gd32f10x_dac.h:25
DAC_SWT_SWTR0
#define DAC_SWT_SWTR0
Definition: gd32f10x_dac.h:56
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
DAC_SWT_SWTR1
#define DAC_SWT_SWTR1
Definition: gd32f10x_dac.h:57
void dac_software_trigger_enable ( uint32_t dac_periph )

enable DAC software trigger

Parameters
[in] dac_periph
  • DACx(x =0,1)
Return values
none

Definition at line 161 of file gd32f10x_dac.c.

162 {
163 if(DAC0 == dac_periph){
164 DAC_SWT |= DAC_SWT_SWTR0;
165 }else{
166 DAC_SWT |= DAC_SWT_SWTR1;
167 }
168 }
DAC_SWT
#define DAC_SWT
Definition: gd32f10x_dac.h:25
DAC_SWT_SWTR0
#define DAC_SWT_SWTR0
Definition: gd32f10x_dac.h:56
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
DAC_SWT_SWTR1
#define DAC_SWT_SWTR1
Definition: gd32f10x_dac.h:57
void dac_triangle_noise_config | ( | uint32_t | dac_periph,
 |  | uint32_t | amplitude
 | ) |  |

configure DAC triangle noise mode

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] amplitude
  • DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
  • DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
  • DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
  • DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
  • DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
  • DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
  • DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
  • DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
  • DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
  • DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
  • DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
  • DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
[out] none
Return values
none

Definition at line 318 of file gd32f10x_dac.c.

319 {
320 if(DAC0 == dac_periph){
321 DAC_CTL &= ~DAC_CTL_DWBW0;
322 DAC_CTL |= amplitude;
323 }else{
324 DAC_CTL &= ~DAC_CTL_DWBW1;
325 DAC_CTL |= amplitude << 16;
326 }
327 }
DAC_CTL_DWBW1
#define DAC_CTL_DWBW1
Definition: gd32f10x_dac.h:52
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DWBW0
#define DAC_CTL_DWBW0
Definition: gd32f10x_dac.h:45
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_trigger_disable ( uint32_t dac_periph )

disable DAC trigger

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 146 of file gd32f10x_dac.c.

147 {
148 if(DAC0 == dac_periph){
149 DAC_CTL &= ~DAC_CTL_DTEN0;
150 }else{
151 DAC_CTL &= ~DAC_CTL_DTEN1;
152 }
153 }
DAC_CTL_DTEN0
#define DAC_CTL_DTEN0
Definition: gd32f10x_dac.h:42
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
DAC_CTL_DTEN1
#define DAC_CTL_DTEN1
Definition: gd32f10x_dac.h:49
void dac_trigger_enable ( uint32_t dac_periph )

enable DAC trigger

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 130 of file gd32f10x_dac.c.

131 {
132 if(DAC0 == dac_periph){
133 DAC_CTL |= DAC_CTL_DTEN0;
134 }else{
135 DAC_CTL |= DAC_CTL_DTEN1;
136 }
137 }
DAC_CTL_DTEN0
#define DAC_CTL_DTEN0
Definition: gd32f10x_dac.h:42
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
DAC_CTL_DTEN1
#define DAC_CTL_DTEN1
Definition: gd32f10x_dac.h:49
void dac_trigger_source_config | ( | uint32_t | dac_periph,
 |  | uint32_t | triggersource
 | ) |  |

set DAC trigger source

Parameters
[in] dac_periph
  • DACx(x =0,1)
[in] triggersource external triggers of DAC
  • DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
  • DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F10X_CL)
  • DAC_TRIGGER_T3_TRGO: TIMER3 TRGO
  • DAC_TRIGGER_T4_TRGO: TIMER4 TRGO
  • DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
  • DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
  • DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F10X_MD and GD32F10X_HD and GD32F10X_XD)
  • DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
  • DAC_TRIGGER_SOFTWARE: software trigger
[out] none
Return values
none

Definition at line 203 of file gd32f10x_dac.c.

204 {
205 if(DAC0 == dac_periph){
206 DAC_CTL &= ~DAC_CTL_DTSEL0;
207 DAC_CTL |= triggersource;
208 }else{
209 DAC_CTL &= ~DAC_CTL_DTSEL1;
210 DAC_CTL |= (triggersource << 16);
211 }
212 }
DAC_CTL_DTSEL1
#define DAC_CTL_DTSEL1
Definition: gd32f10x_dac.h:50
DAC_CTL_DTSEL0
#define DAC_CTL_DTSEL0
Definition: gd32f10x_dac.h:43
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_wave_bit_width_config | ( | uint32_t | dac_periph,
 |  | uint32_t | bit_width
 | ) |  |

configure DAC wave bit width

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] bit_width
  • DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
  • DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
  • DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
  • DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
  • DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
  • DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
  • DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
  • DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
  • DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
  • DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
  • DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
  • DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
[out] none
Return values
none

Definition at line 256 of file gd32f10x_dac.c.

257 {
258 if(DAC0 == dac_periph){
259 DAC_CTL &= ~DAC_CTL_DWBW0;
260 DAC_CTL |= bit_width;
261 }else{
262 DAC_CTL &= ~DAC_CTL_DWBW1;
263 DAC_CTL |= bit_width << 16;
264 }
265 }
DAC_CTL_DWBW1
#define DAC_CTL_DWBW1
Definition: gd32f10x_dac.h:52
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DWBW0
#define DAC_CTL_DWBW0
Definition: gd32f10x_dac.h:45
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_wave_mode_config | ( | uint32_t | dac_periph,
 |  | uint32_t | wave_mode
 | ) |  |

configure DAC wave mode

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] wave_mode
  • DAC_WAVE_DISABLE: wave disable
  • DAC_WAVE_MODE_LFSR: LFSR noise mode
  • DAC_WAVE_MODE_TRIANGLE: triangle noise mode
[out] none
Return values
none

Definition at line 225 of file gd32f10x_dac.c.

226 {
227 if(DAC0 == dac_periph){
228 DAC_CTL &= ~DAC_CTL_DWM0;
229 DAC_CTL |= wave_mode;
230 }else{
231 DAC_CTL &= ~DAC_CTL_DWM1;
232 DAC_CTL |= wave_mode << 16;
233 }
234 }
DAC_CTL_DWM1
#define DAC_CTL_DWM1
Definition: gd32f10x_dac.h:51
DAC_CTL_DWM0
#define DAC_CTL_DWM0
Definition: gd32f10x_dac.h:44
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f10x_dbg.h File Reference

definitions for the DBG More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | DBG DBG_BASE
#define | DBG_ID REG32(DBG + 0x00U)
#define | DBG_CTL0 REG32(DBG + 0x04U)
#define | DBG_ID_ID_CODE BITS(0,31)
#define | DBG_CTL0_SLP_HOLD BIT(0)
#define | DBG_CTL0_DSLP_HOLD BIT(1)
#define | DBG_CTL0_STB_HOLD BIT(2)
#define | DBG_CTL0_TRACE_IOEN BIT(5)
#define | DBG_CTL0_TRACE_MODE BITS(6,7)
#define | DBG_CTL0_FWDGT_HOLD BIT(8)
#define | DBG_CTL0_WWDGT_HOLD BIT(9)
#define | DBG_CTL0_TIMER0_HOLD BIT(10)
#define | DBG_CTL0_TIMER1_HOLD BIT(11)
#define | DBG_CTL0_TIMER2_HOLD BIT(12)
#define | DBG_CTL0_TIMER3_HOLD BIT(13)
#define | DBG_CTL0_CAN0_HOLD BIT(14)
#define | DBG_CTL0_I2C0_HOLD BIT(15)
#define | DBG_CTL0_I2C1_HOLD BIT(16)
#define | DBG_CTL0_TIMER4_HOLD BIT(17)
#define | DBG_CTL0_TIMER5_HOLD BIT(18)
#define | DBG_CTL0_TIMER6_HOLD BIT(19)
#define | DBG_CTL0_TIMER7_HOLD BIT(20)
#define | DBG_CTL0_TIMER11_HOLD BIT(25)
#define | DBG_CTL0_TIMER12_HOLD BIT(26)
#define | DBG_CTL0_TIMER13_HOLD BIT(27)
#define | DBG_CTL0_TIMER8_HOLD BIT(28)
#define | DBG_CTL0_TIMER9_HOLD BIT(29)
#define | DBG_CTL0_TIMER10_HOLD BIT(30)
#define | DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD
#define | DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD
#define | DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD
#define | CTL0_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
#define | TRACE_MODE_ASYNC CTL0_TRACE_MODE(0)
#define | TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1)
#define | TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2)
#define | TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3)

Enumerations

enum dbg_periph_enum {
DBG_FWDGT_HOLD = BIT(8), DBG_WWDGT_HOLD = BIT(9), DBG_TIMER0_HOLD = BIT(10), DBG_TIMER1_HOLD = BIT(11),
DBG_TIMER2_HOLD = BIT(12), DBG_TIMER3_HOLD = BIT(13), DBG_CAN0_HOLD = BIT(14), DBG_I2C0_HOLD = BIT(15),
DBG_I2C1_HOLD = BIT(16), DBG_TIMER4_HOLD = BIT(17), DBG_TIMER5_HOLD = BIT(18), DBG_TIMER6_HOLD = BIT(19),
DBG_TIMER7_HOLD = BIT(20)
}

Functions

uint32_t | dbg_id_get (void)
read DBG_ID code register More...
void | dbg_low_power_enable (uint32_t dbg_low_power)
enable low power behavior when the mcu is in debug mode More...
void | dbg_low_power_disable (uint32_t dbg_low_power)
disable low power behavior when the mcu is in debug mode More...
void | dbg_periph_enable (dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode More...
void | dbg_periph_disable (dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode More...
void | dbg_trace_pin_enable (void)
enable trace pin assignment More...
void | dbg_trace_pin_disable (void)
disable trace pin assignment More...
void | dbg_trace_pin_mode_set (uint32_t trace_mode)
trace pin mode selection More...

Detailed Description

definitions for the DBG

Definition in file gd32f10x_dbg.h.

Macro Definition Documentation

#define CTL0_TRACE_MODE ( regval ) (BITS(6,7) & ((uint32_t)(regval) << 6U))

Definition at line 93 of file gd32f10x_dbg.h.

#define DBG DBG_BASE

Definition at line 19 of file gd32f10x_dbg.h.

#define DBG_CTL0 REG32(DBG + 0x04U)

DBG control register 0

Definition at line 23 of file gd32f10x_dbg.h.

#define DBG_CTL0_CAN0_HOLD BIT(14)

debug CAN0 kept when core is halted

Definition at line 41 of file gd32f10x_dbg.h.

#define DBG_CTL0_DSLP_HOLD BIT(1)

keep debugger connection during deepsleep mode

Definition at line 31 of file gd32f10x_dbg.h.

#define DBG_CTL0_FWDGT_HOLD BIT(8)

debug FWDGT kept when core is halted

Definition at line 35 of file gd32f10x_dbg.h.

#define DBG_CTL0_I2C0_HOLD BIT(15)

hold I2C0 smbus when core is halted

Definition at line 42 of file gd32f10x_dbg.h.

#define DBG_CTL0_I2C1_HOLD BIT(16)

hold I2C1 smbus when core is halted

Definition at line 43 of file gd32f10x_dbg.h.

#define DBG_CTL0_SLP_HOLD BIT(0)

keep debugger connection during sleep mode

Definition at line 30 of file gd32f10x_dbg.h.

#define DBG_CTL0_STB_HOLD BIT(2)

keep debugger connection during standby mode

Definition at line 32 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER0_HOLD BIT(10)

hold TIMER0 counter when core is halted

Definition at line 37 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER10_HOLD BIT(30)

hold TIMER10 counter when core is halted

Definition at line 57 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER11_HOLD BIT(25)

hold TIMER11 counter when core is halted

Definition at line 52 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER12_HOLD BIT(26)

hold TIMER12 counter when core is halted

Definition at line 53 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER13_HOLD BIT(27)

hold TIMER13 counter when core is halted

Definition at line 54 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER1_HOLD BIT(11)

hold TIMER1 counter when core is halted

Definition at line 38 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER2_HOLD BIT(12)

hold TIMER2 counter when core is halted

Definition at line 39 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER3_HOLD BIT(13)

hold TIMER3 counter when core is halted

Definition at line 40 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER4_HOLD BIT(17)

hold TIMER4 counter when core is halted

Definition at line 44 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER5_HOLD BIT(18)

hold TIMER5 counter when core is halted

Definition at line 45 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER6_HOLD BIT(19)

hold TIMER6 counter when core is halted

Definition at line 46 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER7_HOLD BIT(20)

hold TIMER7 counter when core is halted

Definition at line 47 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER8_HOLD BIT(28)

hold TIMER8 counter when core is halted

Definition at line 55 of file gd32f10x_dbg.h.

#define DBG_CTL0_TIMER9_HOLD BIT(29)

hold TIMER9 counter when core is halted

Definition at line 56 of file gd32f10x_dbg.h.

#define DBG_CTL0_TRACE_IOEN BIT(5)

enable trace pin assignment

Definition at line 33 of file gd32f10x_dbg.h.

#define DBG_CTL0_TRACE_MODE BITS(6,7)

trace pin mode selection

Definition at line 34 of file gd32f10x_dbg.h.

#define DBG_CTL0_WWDGT_HOLD BIT(9)

debug WWDGT kept when core is halted

Definition at line 36 of file gd32f10x_dbg.h.

#define DBG_ID REG32(DBG + 0x00U)

DBG_ID code register

Definition at line 22 of file gd32f10x_dbg.h.

#define DBG_ID_ID_CODE BITS(0,31)

DBG ID code values

Definition at line 27 of file gd32f10x_dbg.h.

#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD

keep debugger connection during deepsleep mode

Definition at line 62 of file gd32f10x_dbg.h.

#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD

keep debugger connection during sleep mode

Definition at line 61 of file gd32f10x_dbg.h.

#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD

keep debugger connection during standby mode

Definition at line 63 of file gd32f10x_dbg.h.

#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0)

trace pin used for async mode

Definition at line 94 of file gd32f10x_dbg.h.

#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1)

trace pin used for sync mode and data size is 1

Definition at line 95 of file gd32f10x_dbg.h.

#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2)

trace pin used for sync mode and data size is 2

Definition at line 96 of file gd32f10x_dbg.h.

#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3)

trace pin used for sync mode and data size is 4

Definition at line 97 of file gd32f10x_dbg.h.

Enumeration Type Documentation

enum dbg_periph_enum
Enumerator
DBG_FWDGT_HOLD | debug FWDGT kept when core is halted
DBG_WWDGT_HOLD | debug WWDGT kept when core is halted
DBG_TIMER0_HOLD | hold TIMER0 counter when core is halted
DBG_TIMER1_HOLD | hold TIMER1 counter when core is halted
DBG_TIMER2_HOLD | hold TIMER2 counter when core is halted
DBG_TIMER3_HOLD | hold TIMER3 counter when core is halted
DBG_CAN0_HOLD | debug CAN0 kept when core is halted
DBG_I2C0_HOLD | hold I2C0 smbus when core is halted
DBG_I2C1_HOLD | hold I2C1 smbus when core is halted
DBG_TIMER4_HOLD | hold TIMER4 counter when core is halted
DBG_TIMER5_HOLD | hold TIMER5 counter when core is halted
DBG_TIMER6_HOLD | hold TIMER6 counter when core is halted
DBG_TIMER7_HOLD | hold TIMER7 counter when core is halted

Definition at line 65 of file gd32f10x_dbg.h.

66 {
67 DBG_FWDGT_HOLD = BIT(8),
68 DBG_WWDGT_HOLD = BIT(9),
69 DBG_TIMER0_HOLD = BIT(10),
70 DBG_TIMER1_HOLD = BIT(11),
71 DBG_TIMER2_HOLD = BIT(12),
72 DBG_TIMER3_HOLD = BIT(13),
73 DBG_CAN0_HOLD = BIT(14),
74 DBG_I2C0_HOLD = BIT(15),
75 DBG_I2C1_HOLD = BIT(16),
76 DBG_TIMER4_HOLD = BIT(17),
77 DBG_TIMER5_HOLD = BIT(18),
78 DBG_TIMER6_HOLD = BIT(19),
79 DBG_TIMER7_HOLD = BIT(20),
80 #ifdef GD32F10x_CL
81 DBG_CAN1_HOLD = BIT(21),
82 #endif /* GD32F10x_CL */
83 #if (defined(GD32F10x_XD) || defined(GD32F10x_CL))
84 DBG_TIMER11_HOLD = BIT(25),
85 DBG_TIMER12_HOLD = BIT(26),
86 DBG_TIMER13_HOLD = BIT(27),
87 DBG_TIMER8_HOLD = BIT(28),
88 DBG_TIMER9_HOLD = BIT(29),
89 DBG_TIMER10_HOLD = BIT(30),
90 #endif /* GD32F10x_XD || GD32F10x_CL*/
91 }dbg_periph_enum;
DBG_I2C1_HOLD
Definition: gd32f10x_dbg.h:75
dbg_periph_enum
dbg_periph_enum
Definition: gd32f10x_dbg.h:65
DBG_CAN0_HOLD
Definition: gd32f10x_dbg.h:73
DBG_TIMER7_HOLD
Definition: gd32f10x_dbg.h:79
DBG_TIMER4_HOLD
Definition: gd32f10x_dbg.h:76
DBG_WWDGT_HOLD
Definition: gd32f10x_dbg.h:68
DBG_TIMER6_HOLD
Definition: gd32f10x_dbg.h:78
DBG_FWDGT_HOLD
Definition: gd32f10x_dbg.h:67
DBG_TIMER3_HOLD
Definition: gd32f10x_dbg.h:72
DBG_TIMER5_HOLD
Definition: gd32f10x_dbg.h:77
DBG_I2C0_HOLD
Definition: gd32f10x_dbg.h:74
DBG_TIMER2_HOLD
Definition: gd32f10x_dbg.h:71
DBG_TIMER1_HOLD
Definition: gd32f10x_dbg.h:70
DBG_TIMER0_HOLD
Definition: gd32f10x_dbg.h:69

Function Documentation

uint32_t dbg_id_get ( void )

read DBG_ID code register

Parameters
[in] | none
[out] | none
Return values
DBG_ID code

Definition at line 21 of file gd32f10x_dbg.c.

22 {
23 return DBG_ID;
24 }
DBG_ID
#define DBG_ID
Definition: gd32f10x_dbg.h:22
void dbg_low_power_disable ( uint32_t dbg_low_power )

disable low power behavior when the mcu is in debug mode

Parameters
[in] dbg_low_power this parameter can be any combination of the following values:
  • DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
  • DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
  • DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
[out] none
Return values
none

Definition at line 51 of file gd32f10x_dbg.c.

52 {
53 DBG_CTL0 &= ~dbg_low_power;
54 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
void dbg_low_power_enable ( uint32_t dbg_low_power )

enable low power behavior when the mcu is in debug mode

Parameters
[in] dbg_low_power this parameter can be any combination of the following values:
  • DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
  • DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
  • DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
[out] none
Return values
none

Definition at line 36 of file gd32f10x_dbg.c.

37 {
38 DBG_CTL0 |= dbg_low_power;
39 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
void dbg_periph_disable ( dbg_periph_enum dbg_periph )

disable peripheral behavior when the mcu is in debug mode

Parameters
[in] dbg_periph refer to dbg_periph_enum only one parameter can be selected which is shown as below:
  • DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
  • DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
  • DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted
  • DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
  • DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD and CL series): hold TIMERx counter when core is halted
[out] none
Return values
none

Definition at line 85 of file gd32f10x_dbg.c.

86 {
87 DBG_CTL0 &= ~(uint32_t)dbg_periph;
88 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
void dbg_periph_enable ( dbg_periph_enum dbg_periph )

enable peripheral behavior when the mcu is in debug mode

Parameters
[in] dbg_periph refer to dbg_periph_enum only one parameter can be selected which is shown as below:
  • DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
  • DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
  • DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted
  • DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
  • DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted
[out] none
Return values
none

Definition at line 68 of file gd32f10x_dbg.c.

69 {
70 DBG_CTL0 |= (uint32_t)dbg_periph;
71 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
void dbg_trace_pin_disable ( void )

disable trace pin assignment

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 107 of file gd32f10x_dbg.c.

108 {
109 DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
110 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
DBG_CTL0_TRACE_IOEN
#define DBG_CTL0_TRACE_IOEN
Definition: gd32f10x_dbg.h:33
void dbg_trace_pin_enable ( void )

enable trace pin assignment

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 96 of file gd32f10x_dbg.c.

97 {
98 DBG_CTL0 |= DBG_CTL0_TRACE_IOEN;
99 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
DBG_CTL0_TRACE_IOEN
#define DBG_CTL0_TRACE_IOEN
Definition: gd32f10x_dbg.h:33
void dbg_trace_pin_mode_set ( uint32_t trace_mode )

trace pin mode selection

Parameters
[in] trace_mode
  • TRACE_MODE_ASYNC: trace pin used for async mode
  • TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
  • TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
  • TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
[out] none
Return values
none

Definition at line 122 of file gd32f10x_dbg.c.

123 {
124 DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE;
125 DBG_CTL0 |= trace_mode;
126 }
DBG_CTL0_TRACE_MODE
#define DBG_CTL0_TRACE_MODE
Definition: gd32f10x_dbg.h:34
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Data Structures | Macros | Enumerations | Functions
gd32f10x_dma.h File Reference

definitions for the DMA More...

#include "gd32f10x.h"

Go to the source code of this file.

Data Structures

struct dma_parameter_struct

Macros

#define | DMA0 (DMA_BASE)
#define | DMA1 (DMA_BASE + 0x0400U)
#define | DMA_INTF(dmax) REG32((dmax) + 0x00U)
#define | DMA_INTC(dmax) REG32((dmax) + 0x04U)
#define | DMA_CH0CTL(dmax) REG32((dmax) + 0x08U)
#define | DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU)
#define | DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U)
#define | DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U)
#define | DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU)
#define | DMA_CH1CNT(dmax) REG32((dmax) + 0x20U)
#define | DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U)
#define | DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U)
#define | DMA_CH2CTL(dmax) REG32((dmax) + 0x30U)
#define | DMA_CH2CNT(dmax) REG32((dmax) + 0x34U)
#define | DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U)
#define | DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU)
#define | DMA_CH3CTL(dmax) REG32((dmax) + 0x44U)
#define | DMA_CH3CNT(dmax) REG32((dmax) + 0x48U)
#define | DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU)
#define | DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U)
#define | DMA_CH4CTL(dmax) REG32((dmax) + 0x58U)
#define | DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU)
#define | DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U)
#define | DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U)
#define | DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU)
#define | DMA_CH5CNT(dmax) REG32((dmax) + 0x70U)
#define | DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U)
#define | DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U)
#define | DMA_CH6CTL(dmax) REG32((dmax) + 0x80U)
#define | DMA_CH6CNT(dmax) REG32((dmax) + 0x84U)
#define | DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U)
#define | DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU)
#define | DMA_INTF_GIF BIT(0)
#define | DMA_INTF_FTFIF BIT(1)
#define | DMA_INTF_HTFIF BIT(2)
#define | DMA_INTF_ERRIF BIT(3)
#define | DMA_INTC_GIFC BIT(0)
#define | DMA_INTC_FTFIFC BIT(1)
#define | DMA_INTC_HTFIFC BIT(2)
#define | DMA_INTC_ERRIFC BIT(3)
#define | DMA_CHXCTL_CHEN BIT(0)
#define | DMA_CHXCTL_FTFIE BIT(1)
#define | DMA_CHXCTL_HTFIE BIT(2)
#define | DMA_CHXCTL_ERRIE BIT(3)
#define | DMA_CHXCTL_DIR BIT(4)
#define | DMA_CHXCTL_CMEN BIT(5)
#define | DMA_CHXCTL_PNAGA BIT(6)
#define | DMA_CHXCTL_MNAGA BIT(7)
#define | DMA_CHXCTL_PWIDTH BITS(8,9)
#define | DMA_CHXCTL_MWIDTH BITS(10,11)
#define | DMA_CHXCTL_PRIO BITS(12,13)
#define | DMA_CHXCTL_M2M BIT(14)
#define | DMA_CHXCNT_CNT BITS(0,15)
#define | DMA_CHXPADDR_PADDR BITS(0,31)
#define | DMA_CHXMADDR_MADDR BITS(0,31)
#define | DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U))
#define | DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel))
#define | DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel))
#define | DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel))
#define | DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel))
#define | DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U)
#define | DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U)
#define | DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U)
#define | DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U)
#define | DMA_CHINTF_RESET_VALUE
#define | DMA_INT_FLAG_G DMA_INTF_GIF
#define | DMA_INT_FLAG_FTF DMA_INTF_FTFIF
#define | DMA_INT_FLAG_HTF DMA_INTF_HTFIF
#define | DMA_INT_FLAG_ERR DMA_INTF_ERRIF
#define | DMA_FLAG_G DMA_INTF_GIF
#define | DMA_FLAG_FTF DMA_INTF_FTFIF
#define | DMA_FLAG_HTF DMA_INTF_HTFIF
#define | DMA_FLAG_ERR DMA_INTF_ERRIF
#define | DMA_INT_FTF DMA_CHXCTL_FTFIE
#define | DMA_INT_HTF DMA_CHXCTL_HTFIE
#define | DMA_INT_ERR DMA_CHXCTL_ERRIE
#define | DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U)
#define | DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U)
#define | DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U)
#define | DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U)
#define | DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U)
#define | CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8))
#define | DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0)
#define | DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1)
#define | DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2)
#define | CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10))
#define | DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0)
#define | DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1)
#define | DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2)
#define | CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12))
#define | DMA_PRIORITY_LOW CHCTL_PRIO(0)
#define | DMA_PRIORITY_MEDIUM CHCTL_PRIO(1)
#define | DMA_PRIORITY_HIGH CHCTL_PRIO(2)
#define | DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3)
#define | DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U)
#define | DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U)
#define | DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT

Enumerations

enum dma_channel_enum {
DMA_CH0 = 0, DMA_CH1, DMA_CH2, DMA_CH3,
DMA_CH4, DMA_CH5, DMA_CH6
}

Functions

void | dma_deinit (uint32_t dma_periph, dma_channel_enum channelx)
deinitialize DMA a channel registers More...
void | dma_init (uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct)
initialize DMA channel More...
void | dma_circulation_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable DMA circulation mode More...
void | dma_circulation_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable DMA circulation mode More...
void | dma_memory_to_memory_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable memory to memory mode More...
void | dma_memory_to_memory_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable memory to memory mode More...
void | dma_channel_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable DMA channel More...
void | dma_channel_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable DMA channel More...
void | dma_periph_address_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
set DMA peripheral base address More...
void | dma_memory_address_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
set DMA memory base address More...
void | dma_transfer_number_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
set the number of remaining data to be transferred by the DMA More...
uint32_t | dma_transfer_number_get (uint32_t dma_periph, dma_channel_enum channelx)
get the number of remaining data to be transferred by the DMA More...
void | dma_priority_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
configure priority level of DMA channel More...
void | dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
configure transfer data size of memory More...
void | dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
configure transfer data size of peripheral More...
void | dma_memory_increase_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable next address increasement algorithm of memory More...
void | dma_memory_increase_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable next address increasement algorithm of memory More...
void | dma_periph_increase_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable next address increasement algorithm of peripheral More...
void | dma_periph_increase_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable next address increasement algorithm of peripheral More...
void | dma_transfer_direction_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
configure the direction of data transfer on the channel More...
FlagStatus | dma_flag_get (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
check DMA flag is set or not More...
void | dma_flag_clear (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag More...
FlagStatus | dma_interrupt_flag_get (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
check DMA flag and interrupt enable bit is set or not More...
void | dma_interrupt_flag_clear (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag More...
void | dma_interrupt_enable (uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
enable DMA interrupt More...
void | dma_interrupt_disable (uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
disable DMA interrupt More...

Detailed Description

definitions for the DMA

Definition in file gd32f10x_dma.h.

Macro Definition Documentation

#define CHCTL_MWIDTH ( regval ) (BITS(10,11) & ((regval) << 10))

transfer data size of memory

Definition at line 182 of file gd32f10x_dma.h.

#define CHCTL_PRIO ( regval ) (BITS(12,13) & ((regval) << 12))

DMA channel priority level

Definition at line 188 of file gd32f10x_dma.h.

#define CHCTL_PWIDTH ( regval ) (BITS(8,9) & ((regval) << 8))

transfer data size of peripheral

Definition at line 176 of file gd32f10x_dma.h.

#define DMA0 (DMA_BASE)

DMA0 base address

Definition at line 19 of file gd32f10x_dma.h.

#define DMA1 (DMA_BASE + 0x0400U)

DMA1 base address

Definition at line 20 of file gd32f10x_dma.h.

#define DMA_CH0CNT ( dmax ) REG32((dmax) + 0x0CU)

DMA channel 0 counter register

Definition at line 27 of file gd32f10x_dma.h.

#define DMA_CH0CTL ( dmax ) REG32((dmax) + 0x08U)

DMA channel 0 control register

Definition at line 26 of file gd32f10x_dma.h.

#define DMA_CH0MADDR ( dmax ) REG32((dmax) + 0x14U)

DMA channel 0 memory base address register

Definition at line 29 of file gd32f10x_dma.h.

#define DMA_CH0PADDR ( dmax ) REG32((dmax) + 0x10U)

DMA channel 0 peripheral base address register

Definition at line 28 of file gd32f10x_dma.h.

#define DMA_CH1CNT ( dmax ) REG32((dmax) + 0x20U)

DMA channel 1 counter register

Definition at line 32 of file gd32f10x_dma.h.

#define DMA_CH1CTL ( dmax ) REG32((dmax) + 0x1CU)

DMA channel 1 control register

Definition at line 31 of file gd32f10x_dma.h.

#define DMA_CH1MADDR ( dmax ) REG32((dmax) + 0x28U)

DMA channel 1 memory base address register

Definition at line 34 of file gd32f10x_dma.h.

#define DMA_CH1PADDR ( dmax ) REG32((dmax) + 0x24U)

DMA channel 1 peripheral base address register

Definition at line 33 of file gd32f10x_dma.h.

#define DMA_CH2CNT ( dmax ) REG32((dmax) + 0x34U)

DMA channel 2 counter register

Definition at line 37 of file gd32f10x_dma.h.

#define DMA_CH2CTL ( dmax ) REG32((dmax) + 0x30U)

DMA channel 2 control register

Definition at line 36 of file gd32f10x_dma.h.

#define DMA_CH2MADDR ( dmax ) REG32((dmax) + 0x3CU)

DMA channel 2 memory base address register

Definition at line 39 of file gd32f10x_dma.h.

#define DMA_CH2PADDR ( dmax ) REG32((dmax) + 0x38U)

DMA channel 2 peripheral base address register

Definition at line 38 of file gd32f10x_dma.h.

#define DMA_CH3CNT ( dmax ) REG32((dmax) + 0x48U)

DMA channel 3 counter register

Definition at line 42 of file gd32f10x_dma.h.

#define DMA_CH3CTL ( dmax ) REG32((dmax) + 0x44U)

DMA channel 3 control register

Definition at line 41 of file gd32f10x_dma.h.

#define DMA_CH3MADDR ( dmax ) REG32((dmax) + 0x50U)

DMA channel 3 memory base address register

Definition at line 44 of file gd32f10x_dma.h.

#define DMA_CH3PADDR ( dmax ) REG32((dmax) + 0x4CU)

DMA channel 3 peripheral base address register

Definition at line 43 of file gd32f10x_dma.h.

#define DMA_CH4CNT ( dmax ) REG32((dmax) + 0x5CU)

DMA channel 4 counter register

Definition at line 47 of file gd32f10x_dma.h.

#define DMA_CH4CTL ( dmax ) REG32((dmax) + 0x58U)

DMA channel 4 control register

Definition at line 46 of file gd32f10x_dma.h.

#define DMA_CH4MADDR ( dmax ) REG32((dmax) + 0x64U)

DMA channel 4 memory base address register

Definition at line 49 of file gd32f10x_dma.h.

#define DMA_CH4PADDR ( dmax ) REG32((dmax) + 0x60U)

DMA channel 4 peripheral base address register

Definition at line 48 of file gd32f10x_dma.h.

#define DMA_CH5CNT ( dmax ) REG32((dmax) + 0x70U)

DMA channel 5 counter register

Definition at line 52 of file gd32f10x_dma.h.

#define DMA_CH5CTL ( dmax ) REG32((dmax) + 0x6CU)

DMA channel 5 control register

Definition at line 51 of file gd32f10x_dma.h.

#define DMA_CH5MADDR ( dmax ) REG32((dmax) + 0x78U)

DMA channel 5 memory base address register

Definition at line 54 of file gd32f10x_dma.h.

#define DMA_CH5PADDR ( dmax ) REG32((dmax) + 0x74U)

DMA channel 5 peripheral base address register

Definition at line 53 of file gd32f10x_dma.h.

#define DMA_CH6CNT ( dmax ) REG32((dmax) + 0x84U)

DMA channel 6 counter register

Definition at line 57 of file gd32f10x_dma.h.

#define DMA_CH6CTL ( dmax ) REG32((dmax) + 0x80U)

DMA channel 6 control register

Definition at line 56 of file gd32f10x_dma.h.

#define DMA_CH6MADDR ( dmax ) REG32((dmax) + 0x8CU)

DMA channel 6 memory base address register

Definition at line 59 of file gd32f10x_dma.h.

#define DMA_CH6PADDR ( dmax ) REG32((dmax) + 0x88U)

DMA channel 6 peripheral base address register

Definition at line 58 of file gd32f10x_dma.h.

#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT

transfer counter mask

Definition at line 200 of file gd32f10x_dma.h.

#define DMA_CHCNT | ( | dma,
 |  | channel
 | ) | REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel))

the address of DMA channel CHXCNT register

Definition at line 129 of file gd32f10x_dma.h.

#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U)

the reset value of DMA channel CHXCNT register

Definition at line 135 of file gd32f10x_dma.h.

#define DMA_CHCTL | ( | dma,
 |  | channel
 | ) | REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel))

the address of DMA channel CHXCTL register

Definition at line 128 of file gd32f10x_dma.h.

#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U)

the reset value of DMA channel CHXCTL register

Definition at line 134 of file gd32f10x_dma.h.

#define DMA_CHINTF_RESET_VALUE
Value:
(DMA_INTF_GIF | DMA_INTF_FTFIF | \
DMA_INTF_HTFIF | DMA_INTF_ERRIF)
DMA_INTF_HTFIF
#define DMA_INTF_HTFIF
Definition: gd32f10x_dma.h:65
DMA_INTF_ERRIF
#define DMA_INTF_ERRIF
Definition: gd32f10x_dma.h:66
DMA_INTF_GIF
#define DMA_INTF_GIF
Definition: gd32f10x_dma.h:63
DMA_INTF_FTFIF
#define DMA_INTF_FTFIF
Definition: gd32f10x_dma.h:64

clear DMA channel DMA_INTF register

Definition at line 138 of file gd32f10x_dma.h.

#define DMA_CHMADDR | ( | dma,
 |  | channel
 | ) | REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel))

the address of DMA channel CHXMADDR register

Definition at line 131 of file gd32f10x_dma.h.

#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U)

the reset value of DMA channel CHXMADDR register

Definition at line 137 of file gd32f10x_dma.h.

#define DMA_CHPADDR | ( | dma,
 |  | channel
 | ) | REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel))

the address of DMA channel CHXPADDR register

Definition at line 130 of file gd32f10x_dma.h.

#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U)

the reset value of DMA channel CHXPADDR register

Definition at line 136 of file gd32f10x_dma.h.

#define DMA_CHXCNT_CNT BITS(0,15)

transfer counter

Definition at line 89 of file gd32f10x_dma.h.

#define DMA_CHXCTL_CHEN BIT(0)

channel enable

Definition at line 75 of file gd32f10x_dma.h.

#define DMA_CHXCTL_CMEN BIT(5)

circular mode enable

Definition at line 80 of file gd32f10x_dma.h.

#define DMA_CHXCTL_DIR BIT(4)

transfer direction

Definition at line 79 of file gd32f10x_dma.h.

#define DMA_CHXCTL_ERRIE BIT(3)

enable bit for channel error interrupt

Definition at line 78 of file gd32f10x_dma.h.

#define DMA_CHXCTL_FTFIE BIT(1)

enable bit for channel full transfer finish interrupt

Definition at line 76 of file gd32f10x_dma.h.

#define DMA_CHXCTL_HTFIE BIT(2)

enable bit for channel half transfer finish interrupt

Definition at line 77 of file gd32f10x_dma.h.

#define DMA_CHXCTL_M2M BIT(14)

memory to memory mode

Definition at line 86 of file gd32f10x_dma.h.

#define DMA_CHXCTL_MNAGA BIT(7)

next address generation algorithm of memory

Definition at line 82 of file gd32f10x_dma.h.

#define DMA_CHXCTL_MWIDTH BITS(10,11)

transfer data width of memory

Definition at line 84 of file gd32f10x_dma.h.

#define DMA_CHXCTL_PNAGA BIT(6)

next address generation algorithm of peripheral

Definition at line 81 of file gd32f10x_dma.h.

#define DMA_CHXCTL_PRIO BITS(12,13)

priority level

Definition at line 85 of file gd32f10x_dma.h.

#define DMA_CHXCTL_PWIDTH BITS(8,9)

transfer data width of peripheral

Definition at line 83 of file gd32f10x_dma.h.

#define DMA_CHXMADDR_MADDR BITS(0,31)

memory base address

Definition at line 95 of file gd32f10x_dma.h.

#define DMA_CHXPADDR_PADDR BITS(0,31)

peripheral base address

Definition at line 92 of file gd32f10x_dma.h.

#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U)

circular mode disable

Definition at line 164 of file gd32f10x_dma.h.

#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U)

circular mode enable

Definition at line 165 of file gd32f10x_dma.h.

#define DMA_FLAG_ADD | ( | flag,
 |  | shift
 | ) | ((flag) << ((shift) * 4U))

DMA channel flag shift

Definition at line 125 of file gd32f10x_dma.h.

#define DMA_FLAG_ERR DMA_INTF_ERRIF

error flag of channel

Definition at line 152 of file gd32f10x_dma.h.

#define DMA_FLAG_FTF DMA_INTF_FTFIF

full transfer finish flag of channel

Definition at line 150 of file gd32f10x_dma.h.

#define DMA_FLAG_G DMA_INTF_GIF

global interrupt flag of channel

Definition at line 149 of file gd32f10x_dma.h.

#define DMA_FLAG_HTF DMA_INTF_HTFIF

half transfer finish flag of channel

Definition at line 151 of file gd32f10x_dma.h.

#define DMA_INT_ERR DMA_CHXCTL_ERRIE

enable bit for channel error interrupt

Definition at line 158 of file gd32f10x_dma.h.

#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF

error interrupt flag of channel

Definition at line 146 of file gd32f10x_dma.h.

#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF

full transfer finish interrupt flag of channel

Definition at line 144 of file gd32f10x_dma.h.

#define DMA_INT_FLAG_G DMA_INTF_GIF

global interrupt flag of channel

Definition at line 143 of file gd32f10x_dma.h.

#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF

half transfer finish interrupt flag of channel

Definition at line 145 of file gd32f10x_dma.h.

#define DMA_INT_FTF DMA_CHXCTL_FTFIE

enable bit for channel full transfer finish interrupt

Definition at line 156 of file gd32f10x_dma.h.

#define DMA_INT_HTF DMA_CHXCTL_HTFIE

enable bit for channel half transfer finish interrupt

Definition at line 157 of file gd32f10x_dma.h.

#define DMA_INTC ( dmax ) REG32((dmax) + 0x04U)

DMA interrupt flag clear register

Definition at line 24 of file gd32f10x_dma.h.

#define DMA_INTC_ERRIFC BIT(3)

clear error flag of channel

Definition at line 72 of file gd32f10x_dma.h.

#define DMA_INTC_FTFIFC BIT(1)

clear transfer finish flag of channel

Definition at line 70 of file gd32f10x_dma.h.

#define DMA_INTC_GIFC BIT(0)

clear global interrupt flag of channel

Definition at line 69 of file gd32f10x_dma.h.

#define DMA_INTC_HTFIFC BIT(2)

clear half transfer finish flag of channel

Definition at line 71 of file gd32f10x_dma.h.

#define DMA_INTF ( dmax ) REG32((dmax) + 0x00U)

DMA interrupt flag register

Definition at line 23 of file gd32f10x_dma.h.

#define DMA_INTF_ERRIF BIT(3)

error flag of channel

Definition at line 66 of file gd32f10x_dma.h.

#define DMA_INTF_FTFIF BIT(1)

full transfer finish flag of channel

Definition at line 64 of file gd32f10x_dma.h.

#define DMA_INTF_GIF BIT(0)

global interrupt flag of channel

Definition at line 63 of file gd32f10x_dma.h.

#define DMA_INTF_HTFIF BIT(2)

half transfer finish flag of channel

Definition at line 65 of file gd32f10x_dma.h.

#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U)

next address of memory is fixed address mode

Definition at line 172 of file gd32f10x_dma.h.

#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U)

next address of memory is increasing address mode

Definition at line 173 of file gd32f10x_dma.h.

#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U)

disable memory to memory mode

Definition at line 195 of file gd32f10x_dma.h.

#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U)

enable memory to memory mode

Definition at line 196 of file gd32f10x_dma.h.

#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U)

read from memory and write to peripheral

Definition at line 162 of file gd32f10x_dma.h.

#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1)

transfer data size of memory is 16-bit

Definition at line 184 of file gd32f10x_dma.h.

#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2)

transfer data size of memory is 32-bit

Definition at line 185 of file gd32f10x_dma.h.

#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0)

transfer data size of memory is 8-bit

Definition at line 183 of file gd32f10x_dma.h.

#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U)

next address of peripheral is fixed address mode

Definition at line 168 of file gd32f10x_dma.h.

#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U)

next address of peripheral is increasing address mode

Definition at line 169 of file gd32f10x_dma.h.

#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U)

read from peripheral and write to memory

Definition at line 161 of file gd32f10x_dma.h.

#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1)

transfer data size of peripheral is 16-bit

Definition at line 178 of file gd32f10x_dma.h.

#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2)

transfer data size of peripheral is 32-bit

Definition at line 179 of file gd32f10x_dma.h.

#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0)

transfer data size of peripheral is 8-bit

Definition at line 177 of file gd32f10x_dma.h.

#define DMA_PRIORITY_HIGH CHCTL_PRIO(2)

high priority

Definition at line 191 of file gd32f10x_dma.h.

#define DMA_PRIORITY_LOW CHCTL_PRIO(0)

low priority

Definition at line 189 of file gd32f10x_dma.h.

#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1)

medium priority

Definition at line 190 of file gd32f10x_dma.h.

#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3)

ultra high priority

Definition at line 192 of file gd32f10x_dma.h.

Enumeration Type Documentation

enum dma_channel_enum
Enumerator
DMA_CH0 | DMA channel 0
DMA_CH1 | DMA channel 1
DMA_CH2 | DMA channel 2
DMA_CH3 | DMA channel 3
DMA_CH4 | DMA channel 4
DMA_CH5 | DMA channel 5
DMA_CH6 | DMA channel 6

Definition at line 99 of file gd32f10x_dma.h.

100 {
101 DMA_CH0 = 0,
102 DMA_CH1,
103 DMA_CH2,
104 DMA_CH3,
105 DMA_CH4,
106 DMA_CH5,
107 DMA_CH6
108 } dma_channel_enum;
dma_channel_enum
dma_channel_enum
Definition: gd32f10x_dma.h:99
DMA_CH3
Definition: gd32f10x_dma.h:104
DMA_CH4
Definition: gd32f10x_dma.h:105
DMA_CH6
Definition: gd32f10x_dma.h:107
DMA_CH2
Definition: gd32f10x_dma.h:103
DMA_CH5
Definition: gd32f10x_dma.h:106
DMA_CH1
Definition: gd32f10x_dma.h:102
DMA_CH0
Definition: gd32f10x_dma.h:101

Function Documentation

void dma_channel_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable DMA channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 207 of file gd32f10x_dma.c.

208 {
209 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
210 DMA_WRONG_HANDLE
211 }
212
213 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
214 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f10x_dma.h:75
void dma_channel_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable DMA channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 189 of file gd32f10x_dma.c.

190 {
191 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
192 DMA_WRONG_HANDLE
193 }
194
195 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
196 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f10x_dma.h:75
void dma_circulation_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable DMA circulation mode

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 135 of file gd32f10x_dma.c.

136 {
137 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
138 DMA_WRONG_HANDLE
139 }
140
141 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
142 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f10x_dma.h:80
void dma_circulation_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable DMA circulation mode

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 117 of file gd32f10x_dma.c.

118 {
119 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
120 DMA_WRONG_HANDLE
121 }
122
123 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
124 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f10x_dma.h:80
void dma_deinit | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

deinitialize DMA a channel registers

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel is deinitialized
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 28 of file gd32f10x_dma.c.

29 {
30 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
31 DMA_WRONG_HANDLE
32 }
33
34 /* disable DMA a channel */
35 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
36 /* reset DMA channel registers */
37 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
38 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
39 DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
40 DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
41 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
42 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHMADDR
#define DMA_CHMADDR(dma, channel)
Definition: gd32f10x_dma.h:131
DMA_CHCNT
#define DMA_CHCNT(dma, channel)
Definition: gd32f10x_dma.h:129
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_CHCTL_RESET_VALUE
#define DMA_CHCTL_RESET_VALUE
Definition: gd32f10x_dma.h:134
DMA_CHPADDR
#define DMA_CHPADDR(dma, channel)
Definition: gd32f10x_dma.h:130
DMA_CHMADDR_RESET_VALUE
#define DMA_CHMADDR_RESET_VALUE
Definition: gd32f10x_dma.h:137
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f10x_dma.h:75
DMA_INTC
#define DMA_INTC(dmax)
Definition: gd32f10x_dma.h:24
DMA_CHCNT_RESET_VALUE
#define DMA_CHCNT_RESET_VALUE
Definition: gd32f10x_dma.h:135
DMA_CHINTF_RESET_VALUE
#define DMA_CHINTF_RESET_VALUE
Definition: gd32f10x_dma.h:138
DMA_CHPADDR_RESET_VALUE
#define DMA_CHPADDR_RESET_VALUE
Definition: gd32f10x_dma.h:136
void dma_flag_clear | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

clear DMA a channel flag

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to clear flag
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_FLAG_G: global interrupt flag of channel
  • DMA_FLAG_FTF: full transfer finish flag of channel
  • DMA_FLAG_HTF: half transfer finish flag of channel
  • DMA_FLAG_ERR: error flag of channel
[out] none
Return values
none

Definition at line 519 of file gd32f10x_dma.c.

520 {
521 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
522 }
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_INTC
#define DMA_INTC(dmax)
Definition: gd32f10x_dma.h:24
FlagStatus dma_flag_get | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

check DMA flag is set or not

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to get flag
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_FLAG_G: global interrupt flag of channel
  • DMA_FLAG_FTF: full transfer finish flag of channel
  • DMA_FLAG_HTF: half transfer finish flag of channel
  • DMA_FLAG_ERR: error flag of channel
[out] none
Return values
FlagStatus SET or RESET

Definition at line 491 of file gd32f10x_dma.c.

492 {
493 FlagStatus reval;
494
495 if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
496 reval = SET;
497 }else{
498 reval = RESET;
499 }
500
501 return reval;
502 }
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_INTF
#define DMA_INTF(dmax)
Definition: gd32f10x_dma.h:23
void dma_init | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | dma_parameter_struct | init_struct
 | ) |  |

initialize DMA channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel is initialized
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] | init_struct | the data needed to initialize DMA channel periph_addr: peripheral base address periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE memory_addr: memory base address memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL number: the number of remaining data to be transferred by the DMA priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
[out] | none
Return values
none

Definition at line 63 of file gd32f10x_dma.c.

64 {
65 uint32_t ctl;
66
67 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
68 DMA_WRONG_HANDLE
69 }
70
71 /* configure peripheral base address */
72 DMA_CHPADDR(dma_periph, channelx) = init_struct.periph_addr;
73
74 /* configure memory base address */
75 DMA_CHMADDR(dma_periph, channelx) = init_struct.memory_addr;
76
77 /* configure the number of remaining data to be transferred */
78 DMA_CHCNT(dma_periph, channelx) = (init_struct.number & DMA_CHANNEL_CNT_MASK);
79
80 /* configure peripheral transfer width,memory transfer width, */
81 ctl = DMA_CHCTL(dma_periph, channelx);
82 ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
83 ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
84 DMA_CHCTL(dma_periph, channelx) = ctl;
85
86 /* configure peripheral increasing mode */
87 if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
88 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
89 }else{
90 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
91 }
92
93 /* configure memory increasing mode */
94 if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
95 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
96 }else{
97 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
98 }
99
100 /* configure the direction of data transfer */
101 if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
102 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
103 }else{
104 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
105 }
106 }
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f10x_dma.h:84
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHMADDR
#define DMA_CHMADDR(dma, channel)
Definition: gd32f10x_dma.h:131
dma_parameter_struct::priority
uint32_t priority
Definition: gd32f10x_dma.h:118
dma_parameter_struct::memory_width
uint32_t memory_width
Definition: gd32f10x_dma.h:116
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f10x_dma.h:79
dma_parameter_struct::periph_inc
uint8_t periph_inc
Definition: gd32f10x_dma.h:119
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f10x_dma.h:81
DMA_CHCNT
#define DMA_CHCNT(dma, channel)
Definition: gd32f10x_dma.h:129
DMA_PERIPH_INCREASE_ENABLE
#define DMA_PERIPH_INCREASE_ENABLE
Definition: gd32f10x_dma.h:169
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f10x_dma.h:83
DMA_CHANNEL_CNT_MASK
#define DMA_CHANNEL_CNT_MASK
Definition: gd32f10x_dma.h:200
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f10x_dma.h:82
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
dma_parameter_struct::number
uint32_t number
Definition: gd32f10x_dma.h:117
DMA_MEMORY_INCREASE_ENABLE
#define DMA_MEMORY_INCREASE_ENABLE
Definition: gd32f10x_dma.h:173
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f10x_dma.h:85
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f10x_dma.h:161
DMA_CHPADDR
#define DMA_CHPADDR(dma, channel)
Definition: gd32f10x_dma.h:130
dma_parameter_struct::periph_width
uint32_t periph_width
Definition: gd32f10x_dma.h:114
dma_parameter_struct::memory_inc
uint8_t memory_inc
Definition: gd32f10x_dma.h:120
dma_parameter_struct::direction
uint8_t direction
Definition: gd32f10x_dma.h:121
dma_parameter_struct::periph_addr
uint32_t periph_addr
Definition: gd32f10x_dma.h:113
dma_parameter_struct::memory_addr
uint32_t memory_addr
Definition: gd32f10x_dma.h:115
void dma_interrupt_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | source
 | ) |  |

disable DMA interrupt

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] source specify which interrupt to disbale one or more parameters can be selected which are shown as below
  • DMA_INT_FTF: channel full transfer finish interrupt
  • DMA_INT_HTF: channel half transfer finish interrupt
  • DMA_INT_ERR: channel error interrupt
[out] none
Return values
none

Definition at line 623 of file gd32f10x_dma.c.

624 {
625 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
626 DMA_WRONG_HANDLE
627 }
628
629 DMA_CHCTL(dma_periph, channelx) &= ~source;
630 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_interrupt_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | source
 | ) |  |

enable DMA interrupt

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] source specify which interrupt to enbale one or more parameters can be selected which are shown as below
  • DMA_INT_FTF: channel full transfer finish interrupt
  • DMA_INT_HTF: channel half transfer finish interrupt
  • DMA_INT_ERR: channel error interrupt
[out] none
Return values
none

Definition at line 600 of file gd32f10x_dma.c.

601 {
602 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
603 DMA_WRONG_HANDLE
604 }
605
606 DMA_CHCTL(dma_periph, channelx) |= source;
607 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_interrupt_flag_clear | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

clear DMA a channel flag

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to clear flag
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_INT_FLAG_G: global interrupt flag of channel
  • DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
  • DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
  • DMA_INT_FLAG_ERR: error interrupt flag of channel
[out] none
Return values
none

Definition at line 581 of file gd32f10x_dma.c.

582 {
583 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
584 }
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_INTC
#define DMA_INTC(dmax)
Definition: gd32f10x_dma.h:24
FlagStatus dma_interrupt_flag_get | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

check DMA flag and interrupt enable bit is set or not

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to get flag
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
  • DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
  • DMA_INT_FLAG_ERR: error interrupt flag of channel
[out] none
Return values
FlagStatus SET or RESET

Definition at line 538 of file gd32f10x_dma.c.

539 {
540 uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
541
542 switch(flag){
543 case DMA_INT_FLAG_FTF:
544 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
545 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
546 break;
547 case DMA_INT_FLAG_HTF:
548 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
549 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
550 break;
551 case DMA_INT_FLAG_ERR:
552 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
553 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
554 break;
555 default:
556 DMA_WRONG_HANDLE
557 }
558
559 if(interrupt_flag && interrupt_enable){
560 return SET;
561 }else{
562 return RESET;
563 }
564 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_HTFIE
#define DMA_CHXCTL_HTFIE
Definition: gd32f10x_dma.h:77
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_CHXCTL_FTFIE
#define DMA_CHXCTL_FTFIE
Definition: gd32f10x_dma.h:76
DMA_INTF
#define DMA_INTF(dmax)
Definition: gd32f10x_dma.h:23
DMA_INT_FLAG_ERR
#define DMA_INT_FLAG_ERR
Definition: gd32f10x_dma.h:146
DMA_INT_FLAG_FTF
#define DMA_INT_FLAG_FTF
Definition: gd32f10x_dma.h:144
DMA_CHXCTL_ERRIE
#define DMA_CHXCTL_ERRIE
Definition: gd32f10x_dma.h:78
DMA_INT_FLAG_HTF
#define DMA_INT_FLAG_HTF
Definition: gd32f10x_dma.h:145
void dma_memory_address_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | address
 | ) |  |

set DMA memory base address

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to set memory base address
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] | address | memory base address
[out] | none
Return values
none

Definition at line 245 of file gd32f10x_dma.c.

246 {
247 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
248 DMA_WRONG_HANDLE
249 }
250
251 DMA_CHMADDR(dma_periph, channelx) = address;
252 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHMADDR
#define DMA_CHMADDR(dma, channel)
Definition: gd32f10x_dma.h:131
void dma_memory_increase_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable next address increasement algorithm of memory

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 406 of file gd32f10x_dma.c.

407 {
408 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
409 DMA_WRONG_HANDLE
410 }
411
412 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
413 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f10x_dma.h:82
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_memory_increase_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable next address increasement algorithm of memory

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 388 of file gd32f10x_dma.c.

389 {
390 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
391 DMA_WRONG_HANDLE
392 }
393
394 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
395 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f10x_dma.h:82
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_memory_to_memory_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable memory to memory mode

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 171 of file gd32f10x_dma.c.

172 {
173 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
174 DMA_WRONG_HANDLE
175 }
176
177 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
178 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f10x_dma.h:86
void dma_memory_to_memory_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable memory to memory mode

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 153 of file gd32f10x_dma.c.

154 {
155 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
156 DMA_WRONG_HANDLE
157 }
158
159 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
160 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f10x_dma.h:86
void dma_memory_width_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | mwidth
 | ) |  |

configure transfer data size of memory

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] mwidth transfer data width of memory
  • DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
  • DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
  • DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
[out] none
Return values
none

Definition at line 334 of file gd32f10x_dma.c.

335 {
336 uint32_t ctl;
337
338 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
339 DMA_WRONG_HANDLE
340 }
341
342 /* acquire DMA_CHxCTL register */
343 ctl = DMA_CHCTL(dma_periph, channelx);
344 /* assign regiser */
345 ctl &= ~DMA_CHXCTL_MWIDTH;
346 ctl |= mwidth;
347 DMA_CHCTL(dma_periph, channelx) = ctl;
348 }
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f10x_dma.h:84
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_periph_address_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | address
 | ) |  |

set DMA peripheral base address

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to set peripheral base address
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] | address | peripheral base address
[out] | none
Return values
none

Definition at line 226 of file gd32f10x_dma.c.

227 {
228 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
229 DMA_WRONG_HANDLE
230 }
231
232 DMA_CHPADDR(dma_periph, channelx) = address;
233 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHPADDR
#define DMA_CHPADDR(dma, channel)
Definition: gd32f10x_dma.h:130
void dma_periph_increase_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable next address increasement algorithm of peripheral

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 442 of file gd32f10x_dma.c.

443 {
444 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
445 DMA_WRONG_HANDLE
446 }
447
448 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
449 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f10x_dma.h:81
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_periph_increase_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable next address increasement algorithm of peripheral

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 424 of file gd32f10x_dma.c.

425 {
426 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
427 DMA_WRONG_HANDLE
428 }
429
430 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
431 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f10x_dma.h:81
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_periph_width_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | pwidth
 | ) |  |

configure transfer data size of peripheral

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] pwidth transfer data width of peripheral
  • DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
  • DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
  • DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
[out] none
Return values
none

Definition at line 363 of file gd32f10x_dma.c.

364 {
365 uint32_t ctl;
366
367 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
368 DMA_WRONG_HANDLE
369 }
370
371 /* acquire DMA_CHxCTL register */
372 ctl = DMA_CHCTL(dma_periph, channelx);
373 /* assign regiser */
374 ctl &= ~DMA_CHXCTL_PWIDTH;
375 ctl |= pwidth;
376 DMA_CHCTL(dma_periph, channelx) = ctl;
377 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f10x_dma.h:83
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_priority_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | priority
 | ) |  |

configure priority level of DMA channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] priority priority Level of this channel
  • DMA_PRIORITY_LOW: low priority
  • DMA_PRIORITY_MEDIUM: medium priority
  • DMA_PRIORITY_HIGH: high priority
  • DMA_PRIORITY_ULTRA_HIGH: ultra high priority
[out] none
Return values
none

Definition at line 305 of file gd32f10x_dma.c.

306 {
307 uint32_t ctl;
308
309 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
310 DMA_WRONG_HANDLE
311 }
312
313 /* acquire DMA_CHxCTL register */
314 ctl = DMA_CHCTL(dma_periph, channelx);
315 /* assign regiser */
316 ctl &= ~DMA_CHXCTL_PRIO;
317 ctl |= priority;
318 DMA_CHCTL(dma_periph, channelx) = ctl;
319 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f10x_dma.h:85
void dma_transfer_direction_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | direction
 | ) |  |

configure the direction of data transfer on the channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] direction specify the direction of data transfer
  • DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
  • DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
[out] none
Return values
none

Definition at line 463 of file gd32f10x_dma.c.

464 {
465 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
466 DMA_WRONG_HANDLE
467 }
468
469 if(DMA_PERIPHERAL_TO_MEMORY == direction){
470 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
471 } else {
472 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
473 }
474 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f10x_dma.h:79
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f10x_dma.h:161
void dma_transfer_number_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | number
 | ) |  |

set the number of remaining data to be transferred by the DMA

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to set number
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] | number | the number of remaining data to be transferred by the DMA
[out] | none
Return values
none

Definition at line 264 of file gd32f10x_dma.c.

265 {
266 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
267 DMA_WRONG_HANDLE
268 }
269
270 DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
271 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCNT
#define DMA_CHCNT(dma, channel)
Definition: gd32f10x_dma.h:129
DMA_CHANNEL_CNT_MASK
#define DMA_CHANNEL_CNT_MASK
Definition: gd32f10x_dma.h:200
uint32_t dma_transfer_number_get | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

get the number of remaining data to be transferred by the DMA

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to set number
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
uint32_t the number of remaining data to be transferred by the DMA

Definition at line 282 of file gd32f10x_dma.c.

283 {
284 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
285 DMA_WRONG_HANDLE
286 }
287
288 return (uint32_t)DMA_CHCNT(dma_periph, channelx);
289 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCNT
#define DMA_CHCNT(dma, channel)
Definition: gd32f10x_dma.h:129
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Data Structures | Macros | Enumerations | Functions
gd32f10x_enet.h File Reference

definitions for the ENET More...

#include "gd32f10x.h"
#include <stdlib.h>

Go to the source code of this file.

Data Structures

struct | enet_initpara_struct
struct | enet_descriptors_struct
struct | enet_ptp_systime_struct

Macros

#define | IF_USE_EXTERNPHY_LIB 0
#define | ENET_RXBUF_NUM 5U
#define | ENET_TXBUF_NUM 5U
#define | ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE
#define | ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE
#define | DP83848 0
#define | LAN8700 1
#define | PHY_TYPE DP83848
#define | PHY_ADDRESS ((uint16_t)1U)
#define | PHY_READ_TO ((uint32_t)0x0004FFFFU)
#define | PHY_WRITE_TO ((uint32_t)0x0004FFFFU)
#define | PHY_RESETDELAY ((uint32_t)0x008FFFFFU)
#define | PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU)
#define | PHY_REG_BCR 0U
#define | PHY_REG_BSR 1U
#define | PHY_RESET ((uint16_t)0x8000)
#define | PHY_LOOPBACK ((uint16_t)0x4000)
#define | PHY_FULLDUPLEX_100M ((uint16_t)0x2100)
#define | PHY_HALFDUPLEX_100M ((uint16_t)0x2000)
#define | PHY_FULLDUPLEX_10M ((uint16_t)0x0100)
#define | PHY_HALFDUPLEX_10M ((uint16_t)0x0000)
#define | PHY_AUTONEGOTIATION ((uint16_t)0x1000)
#define | PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200)
#define | PHY_POWERDOWN ((uint16_t)0x0800)
#define | PHY_ISOLATE ((uint16_t)0x0400)
#define | PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020)
#define | PHY_LINKED_STATUS ((uint16_t)0x0004)
#define | PHY_JABBER_DETECTION ((uint16_t)0x0002)
#define | PHY_SR 16U
#define | PHY_SPEED_STATUS ((uint16_t)0x0002)
#define | PHY_DUPLEX_STATUS ((uint16_t)0x0004)
#define | ENET ENET_BASE
#define | ENET_MAC_CFG REG32((ENET) + 0x00U)
#define | ENET_MAC_FRMF REG32((ENET) + 0x04U)
#define | ENET_MAC_HLH REG32((ENET) + 0x08U)
#define | ENET_MAC_HLL REG32((ENET) + 0x0CU)
#define | ENET_MAC_PHY_CTL REG32((ENET) + 0x10U)
#define | ENET_MAC_PHY_DATA REG32((ENET) + 0x14U)
#define | ENET_MAC_FCTL REG32((ENET) + 0x18U)
#define | ENET_MAC_FCTH REG32((ENET) + 0x1080U)
#define | ENET_MAC_VLT REG32((ENET) + 0x1CU)
#define | ENET_MAC_RWFF REG32((ENET) + 0x28U)
#define | ENET_MAC_WUM REG32((ENET) + 0x2CU)
#define | ENET_MAC_INTF REG32((ENET) + 0x38U)
#define | ENET_MAC_INTMSK REG32((ENET) + 0x3CU)
#define | ENET_MAC_ADDR0H REG32((ENET) + 0x40U)
#define | ENET_MAC_ADDR0L REG32((ENET) + 0x44U)
#define | ENET_MAC_ADDR1H REG32((ENET) + 0x48U)
#define | ENET_MAC_ADDR1L REG32((ENET) + 0x4CU)
#define | ENET_MAC_ADDT2H REG32((ENET) + 0x50U)
#define | ENET_MAC_ADDR2L REG32((ENET) + 0x54U)
#define | ENET_MAC_ADDR3H REG32((ENET) + 0x58U)
#define | ENET_MAC_ADDR3L REG32((ENET) + 0x5CU)
#define | ENET_MSC_CTL REG32((ENET) + 0x100U)
#define | ENET_MSC_RINTF REG32((ENET) + 0x104U)
#define | ENET_MSC_TINTF REG32((ENET) + 0x108U)
#define | ENET_MSC_RINTMSK REG32((ENET) + 0x10CU)
#define | ENET_MSC_TINTMSK REG32((ENET) + 0x110U)
#define | ENET_MSC_SCCNT REG32((ENET) + 0x14CU)
#define | ENET_MSC_MSCCNT REG32((ENET) + 0x150U)
#define | ENET_MSC_TGFCNT REG32((ENET) + 0x168U)
#define | ENET_MSC_RFCECNT REG32((ENET) + 0x194U)
#define | ENET_MSC_RFAECNT REG32((ENET) + 0x198U)
#define | ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U)
#define | ENET_PTP_TSCTL REG32((ENET) + 0x700U)
#define | ENET_PTP_SSINC REG32((ENET) + 0x704U)
#define | ENET_PTP_TSH REG32((ENET) + 0x708U)
#define | ENET_PTP_TSL REG32((ENET) + 0x70CU)
#define | ENET_PTP_TSUH REG32((ENET) + 0x710U)
#define | ENET_PTP_TSUL REG32((ENET) + 0x714U)
#define | ENET_PTP_TSADDEND REG32((ENET) + 0x718U)
#define | ENET_PTP_ETH REG32((ENET) + 0x71CU)
#define | ENET_PTP_ETL REG32((ENET) + 0x720U)
#define | ENET_DMA_BCTL REG32((ENET) + 0x1000U)
#define | ENET_DMA_TPEN REG32((ENET) + 0x1004U)
#define | ENET_DMA_RPEN REG32((ENET) + 0x1008U)
#define | ENET_DMA_RDTADDR REG32((ENET) + 0x100CU)
#define | ENET_DMA_TDTADDR REG32((ENET) + 0x1010U)
#define | ENET_DMA_STAT REG32((ENET) + 0x1014U)
#define | ENET_DMA_CTL REG32((ENET) + 0x1018U)
#define | ENET_DMA_INTEN REG32((ENET) + 0x101CU)
#define | ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U)
#define | ENET_DMA_CTDADDR REG32((ENET) + 0x1048U)
#define | ENET_DMA_CRDADDR REG32((ENET) + 0x104CU)
#define | ENET_DMA_CTBADDR REG32((ENET) + 0x1050U)
#define | ENET_DMA_CRBADDR REG32((ENET) + 0x1054U)
#define | ENET_MAC_CFG_REN BIT(2)
#define | ENET_MAC_CFG_TEN BIT(3)
#define | ENET_MAC_CFG_DFC BIT(4)
#define | ENET_MAC_CFG_BOL BITS(5,6)
#define | ENET_MAC_CFG_APCD BIT(7)
#define | ENET_MAC_CFG_RTD BIT(9)
#define | ENET_MAC_CFG_IPFCO BIT(10)
#define | ENET_MAC_CFG_DPM BIT(11)
#define | ENET_MAC_CFG_LBM BIT(12)
#define | ENET_MAC_CFG_ROD BIT(13)
#define | ENET_MAC_CFG_SPD BIT(14)
#define | ENET_MAC_CFG_CSD BIT(16)
#define | ENET_MAC_CFG_IGBS BITS(17,19)
#define | ENET_MAC_CFG_JBD BIT(22)
#define | ENET_MAC_CFG_WDD BIT(23)
#define | ENET_MAC_FRMF_PM BIT(0)
#define | ENET_MAC_FRMF_HUF BIT(1)
#define | ENET_MAC_FRMF_HMF BIT(2)
#define | ENET_MAC_FRMF_DAIFLT BIT(3)
#define | ENET_MAC_FRMF_MFD BIT(4)
#define | ENET_MAC_FRMF_BFRMD BIT(5)
#define | ENET_MAC_FRMF_PCFRM BITS(6,7)
#define | ENET_MAC_FRMF_SAIFLT BIT(8)
#define | ENET_MAC_FRMF_SAFLT BIT(9)
#define | ENET_MAC_FRMF_HPFLT BIT(10)
#define | ENET_MAC_FRMF_FAR BIT(31)
#define | ENET_MAC_HLH_HLH BITS(0,31)
#define | ENET_MAC_HLL_HLL BITS(0,31)
#define | ENET_MAC_PHY_CTL_PB BIT(0)
#define | ENET_MAC_PHY_CTL_PW BIT(1)
#define | ENET_MAC_PHY_CTL_CLR BITS(2,4)
#define | ENET_MAC_PHY_CTL_PR BITS(6,10)
#define | ENET_MAC_PHY_CTL_PA BITS(11,15)
#define | ENET_MAC_PHY_DATA_PD BITS(0,15)
#define | ENET_MAC_FCTL_FLCBBKPA BIT(0)
#define | ENET_MAC_FCTL_TFCEN BIT(1)
#define | ENET_MAC_FCTL_RFCEN BIT(2)
#define | ENET_MAC_FCTL_UPFDT BIT(3)
#define | ENET_MAC_FCTL_PLTS BITS(4,5)
#define | ENET_MAC_FCTL_DZQP BIT(7)
#define | ENET_MAC_FCTL_PTM BITS(16,31)
#define | ENET_MAC_FCTH_RFA BITS(0,2)
#define | ENET_MAC_FCTH_RFD BITS(4,6)
#define | ENET_MAC_VLT_VLTI BITS(0,15)
#define | ENET_MAC_VLT_VLTC BIT(16)
#define | ENET_MAC_RWFF_DATA BITS(0,31)
#define | ENET_MAC_WUM_PWD BIT(0)
#define | ENET_MAC_WUM_MPEN BIT(1)
#define | ENET_MAC_WUM_WFEN BIT(2)
#define | ENET_MAC_WUM_MPKR BIT(5)
#define | ENET_MAC_WUM_WUFR BIT(6)
#define | ENET_MAC_WUM_GU BIT(9)
#define | ENET_MAC_WUM_WUFFRPR BIT(31)
#define | ENET_MAC_INTF_WUM BIT(3)
#define | ENET_MAC_INTF_MSC BIT(4)
#define | ENET_MAC_INTF_MSCR BIT(5)
#define | ENET_MAC_INTF_MSCT BIT(6)
#define | ENET_MAC_INTF_TMST BIT(9)
#define | ENET_MAC_INTMSK_WUMIM BIT(3)
#define | ENET_MAC_INTMSK_TMSTIM BIT(9)
#define | ENET_MAC_ADDR0H_ADDR0H BITS(0,15)
#define | ENET_MAC_ADDR0H_MO BIT(31)
#define | ENET_MAC_ADDR0L_ADDR0L BITS(0,31)
#define | ENET_MAC_ADDR1H_ADDR1H BITS(0,15)
#define | ENET_MAC_ADDR1H_MB BITS(24,29)
#define | ENET_MAC_ADDR1H_SAF BIT(30)
#define | ENET_MAC_ADDR1H_AFE BIT(31)
#define | ENET_MAC_ADDR1L_ADDR1L BITS(0,31)
#define | ENET_MAC_ADDR2H_ADDR2H BITS(0,15)
#define | ENET_MAC_ADDR2H_MB BITS(24,29)
#define | ENET_MAC_ADDR2H_SAF BIT(30)
#define | ENET_MAC_ADDR2H_AFE BIT(31)
#define | ENET_MAC_ADDR2L_ADDR2L BITS(0,31)
#define | ENET_MAC_ADDR3H_ADDR3H BITS(0,15)
#define | ENET_MAC_ADDR3H_MB BITS(24,29)
#define | ENET_MAC_ADDR3H_SAF BIT(30)
#define | ENET_MAC_ADDR3H_AFE BIT(31)
#define | ENET_MAC_ADDR3L_ADDR3L BITS(0,31)
#define | ENET_MSC_CTL_CTR BIT(0)
#define | ENET_MSC_CTL_CTSR BIT(1)
#define | ENET_MSC_CTL_RTOR BIT(2)
#define | ENET_MSC_CTL_MCFZ BIT(3)
#define | ENET_MSC_RINTF_RFCE BIT(5)
#define | ENET_MSC_RINTF_RFAE BIT(6)
#define | ENET_MSC_RINTF_RGUF BIT(17)
#define | ENET_MSC_TINTF_TGFSC BIT(14)
#define | ENET_MSC_TINTF_TGFMSC BIT(15)
#define | ENET_MSC_TINTF_TGF BIT(21)
#define | ENET_MSC_RINTMSK_RFCEIM BIT(5)
#define | ENET_MSC_RINTMSK_RFAEIM BIT(6)
#define | ENET_MSC_RINTMSK_RGUFIM BIT(17)
#define | ENET_MSC_TINTMSK_TGFSCIM BIT(14)
#define | ENET_MSC_TINTMSK_TGFMSCIM BIT(15)
#define | ENET_MSC_TINTMSK_TGFIM BIT(21)
#define | ENET_MSC_SCCNT_SCC BITS(0,31)
#define | ENET_MSC_MSCCNT_MSCC BITS(0,31)
#define | ENET_MSC_TGFCNT_TGF BITS(0,31)
#define | ENET_MSC_RFCECNT_RFCER BITS(0,31)
#define | ENET_MSC_RFAECNT_RFAER BITS(0,31)
#define | ENET_MSC_RGUFCNT_RGUF BITS(0,31)
#define | ENET_PTP_TSCTL_TMSEN BIT(0)
#define | ENET_PTP_TSCTL_TMSFCU BIT(1)
#define | ENET_PTP_TSCTL_TMSSTI BIT(2)
#define | ENET_PTP_TSCTL_TMSSTU BIT(3)
#define | ENET_PTP_TSCTL_TMSITEN BIT(4)
#define | ENET_PTP_TSCTL_TMSARU BIT(5)
#define | ENET_PTP_SSINC_STMSSI BITS(0,7)
#define | ENET_PTP_TSH_STMS BITS(0,31)
#define | ENET_PTP_TSL_STMSS BITS(0,30)
#define | ENET_PTP_TSL_STS BIT(31)
#define | ENET_PTP_TSUH_TMSUS BITS(0,31)
#define | ENET_PTP_TSUL_TMSUSS BITS(0,30)
#define | ENET_PTP_TSUL_TMSUPNS BIT(31)
#define | ENET_PTP_TSADDEND_TMSA BITS(0,31)
#define | ENET_PTP_ETH_ETSH BITS(0,31)
#define | ENET_PTP_ETL_ETSL BITS(0,31)
#define | ENET_DMA_BCTL_SWR BIT(0)
#define | ENET_DMA_BCTL_DAB BIT(1)
#define | ENET_DMA_BCTL_DPSL BITS(2,6)
#define | ENET_DMA_BCTL_PGBL BITS(8,13)
#define | ENET_DMA_BCTL_RTPR BITS(14,15)
#define | ENET_DMA_BCTL_FB BIT(16)
#define | ENET_DMA_BCTL_RXDP BITS(17,22)
#define | ENET_DMA_BCTL_UIP BIT(23)
#define | ENET_DMA_BCTL_FPBL BIT(24)
#define | ENET_DMA_BCTL_AA BIT(25)
#define | ENET_DMA_TPEN_TPE BITS(0,31)
#define | ENET_DMA_RPEN_RPE BITS(0,31)
#define | ENET_DMA_RDTADDR_SRT BITS(0,31)
#define | ENET_DMA_TDTADDR_STT BITS(0,31)
#define | ENET_DMA_STAT_TS BIT(0)
#define | ENET_DMA_STAT_TPS BIT(1)
#define | ENET_DMA_STAT_TBU BIT(2)
#define | ENET_DMA_STAT_TJT BIT(3)
#define | ENET_DMA_STAT_RO BIT(4)
#define | ENET_DMA_STAT_TU BIT(5)
#define | ENET_DMA_STAT_RS BIT(6)
#define | ENET_DMA_STAT_RBU BIT(7)
#define | ENET_DMA_STAT_RPS BIT(8)
#define | ENET_DMA_STAT_RWT BIT(9)
#define | ENET_DMA_STAT_ET BIT(10)
#define | ENET_DMA_STAT_FBE BIT(13)
#define | ENET_DMA_STAT_ER BIT(14)
#define | ENET_DMA_STAT_AI BIT(15)
#define | ENET_DMA_STAT_NI BIT(16)
#define | ENET_DMA_STAT_RP BITS(17,19)
#define | ENET_DMA_STAT_TP BITS(20,22)
#define | ENET_DMA_STAT_EB BITS(23,25)
#define | ENET_DMA_STAT_MSC BIT(27)
#define | ENET_DMA_STAT_WUM BIT(28)
#define | ENET_DMA_STAT_TST BIT(29)
#define | ENET_DMA_CTL_SRE BIT(1)
#define | ENET_DMA_CTL_OSF BIT(2)
#define | ENET_DMA_CTL_RTHC BITS(3,4)
#define | ENET_DMA_CTL_FUF BIT(6)
#define | ENET_DMA_CTL_FERF BIT(7)
#define | ENET_DMA_CTL_STE BIT(13)
#define | ENET_DMA_CTL_TTHC BITS(14,16)
#define | ENET_DMA_CTL_FTF BIT(20)
#define | ENET_DMA_CTL_TSFD BIT(21)
#define | ENET_DMA_CTL_DAFRF BIT(24)
#define | ENET_DMA_CTL_RSFD BIT(25)
#define | ENET_DMA_CTL_DTCERFD BIT(26)
#define | ENET_DMA_INTEN_TIE BIT(0)
#define | ENET_DMA_INTEN_TPSIE BIT(1)
#define | ENET_DMA_INTEN_TBUIE BIT(2)
#define | ENET_DMA_INTEN_TJTIE BIT(3)
#define | ENET_DMA_INTEN_ROIE BIT(4)
#define | ENET_DMA_INTEN_TUIE BIT(5)
#define | ENET_DMA_INTEN_RIE BIT(6)
#define | ENET_DMA_INTEN_RBUIE BIT(7)
#define | ENET_DMA_INTEN_RPSIE BIT(8)
#define | ENET_DMA_INTEN_RWTIE BIT(9)
#define | ENET_DMA_INTEN_ETIE BIT(10)
#define | ENET_DMA_INTEN_FBEIE BIT(13)
#define | ENET_DMA_INTEN_ERIE BIT(14)
#define | ENET_DMA_INTEN_AIE BIT(15)
#define | ENET_DMA_INTEN_NIE BIT(16)
#define | ENET_DMA_MFBOCNT_MSFC BITS(0,15)
#define | ENET_DMA_MFBOCNT_OBMFC BIT(16) /* Overflow bit for missed frame counter */
#define | ENET_DMA_MFBOCNT_MSFA BITS(17,27)
#define | ENET_DMA_MFBOCNT_OBFOC BIT(28)
#define | ENET_DMA_CTDADDR_TDAP BITS(0,31)
#define | ENET_DMA_CRDADDR_RDAP BITS(0,31)
#define | ENET_DMA_CTBADDR_TBAP BITS(0,31)
#define | ENET_DMA_CRBADDR_RBAP BITS(0,31)
#define | ENET_TDES0_DB BIT(0)
#define | ENET_TDES0_UFE BIT(1)
#define | ENET_TDES0_EXD BIT(2)
#define | ENET_TDES0_COCNT BITS(3,6)
#define | ENET_TDES0_VFRM BIT(7)
#define | ENET_TDES0_ECO BIT(8)
#define | ENET_TDES0_LCO BIT(9)
#define | ENET_TDES0_NCA BIT(10)
#define | ENET_TDES0_LCA BIT(11)
#define | ENET_TDES0_IPPE BIT(12)
#define | ENET_TDES0_FRMF BIT(13)
#define | ENET_TDES0_JT BIT(14)
#define | ENET_TDES0_ES BIT(15)
#define | ENET_TDES0_IPHE BIT(16)
#define | ENET_TDES0_TTMSS BIT(17)
#define | ENET_TDES0_TCHM BIT(20)
#define | ENET_TDES0_TERM BIT(21)
#define | ENET_TDES0_CM BITS(22,23)
#define | ENET_TDES0_TTSEN BIT(25)
#define | ENET_TDES0_DPAD BIT(26)
#define | ENET_TDES0_DCRC BIT(27)
#define | ENET_TDES0_FSG BIT(28)
#define | ENET_TDES0_LSG BIT(29)
#define | ENET_TDES0_INTC BIT(30)
#define | ENET_TDES0_DAV BIT(31)
#define | ENET_TDES1_TB1S BITS(0,12)
#define | ENET_TDES1_TB2S BITS(16,28)
#define | ENET_TDES2_TB1AP BITS(0,31)
#define | ENET_TDES3_TB2AP BITS(0,31)
#define | ENET_RDES0_PCERR BIT(0)
#define | ENET_RDES0_CERR BIT(1)
#define | ENET_RDES0_DBERR BIT(2)
#define | ENET_RDES0_RERR BIT(3)
#define | ENET_RDES0_RWDT BIT(4)
#define | ENET_RDES0_FRMT BIT(5)
#define | ENET_RDES0_LCO BIT(6)
#define | ENET_RDES0_IPHERR BIT(7)
#define | ENET_RDES0_LDES BIT(8)
#define | ENET_RDES0_FDES BIT(9)
#define | ENET_RDES0_VTAG BIT(10)
#define | ENET_RDES0_OERR BIT(11)
#define | ENET_RDES0_LERR BIT(12)
#define | ENET_RDES0_SAFF BIT(13)
#define | ENET_RDES0_DERR BIT(14)
#define | ENET_RDES0_ERRS BIT(15)
#define | ENET_RDES0_FRML BITS(16,29)
#define | ENET_RDES0_DAFF BIT(30)
#define | ENET_RDES0_DAV BIT(31)
#define | ENET_RDES1_RB1S BITS(0,12)
#define | ENET_RDES1_RCHM BIT(14)
#define | ENET_RDES1_RERM BIT(15)
#define | ENET_RDES1_RB2S BITS(16,28)
#define | ENET_RDES1_DINTC BIT(31)
#define | ENET_RDES2_RB1AP BITS(0,31)
#define | ENET_RDES3_RB2AP BITS(0,31)
#define | ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define | ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6)))
#define | ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define | ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m)))
#define | ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4])
#define | ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0])
#define | ENET_ADDRH_BASE ((ENET) + 0x40U)
#define | ENET_ADDRL_BASE ((ENET) + 0x44U)
#define | ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU))
#define | MAC_FCTL_REG_OFFSET 0x0018U
#define | MAC_WUM_REG_OFFSET 0x002CU
#define | MAC_INTF_REG_OFFSET 0x0038U
#define | MAC_INTMSK_REG_OFFSET 0x003CU
#define | MSC_RINTF_REG_OFFSET 0x0104U
#define | MSC_TINTF_REG_OFFSET 0x0108U
#define | MSC_RINTMSK_REG_OFFSET 0x010CU
#define | MSC_TINTMSK_REG_OFFSET 0x0110U
#define | MSC_SCCNT_REG_OFFSET 0x014CU
#define | MSC_MSCCNT_REG_OFFSET 0x0150U
#define | MSC_TGFCNT_REG_OFFSET 0x0168U
#define | MSC_RFCECNT_REG_OFFSET 0x0194U
#define | MSC_RFAECNT_REG_OFFSET 0x0198U
#define | MSC_RGUFCNT_REG_OFFSET 0x01C4U
#define | DMA_STAT_REG_OFFSET 0x1014U
#define | DMA_INTEN_REG_OFFSET 0x101CU
#define | DMA_TDTADDR_REG_OFFSET 0x1010U
#define | DMA_CTDADDR_REG_OFFSET 0x1048U
#define | DMA_CTBADDR_REG_OFFSET 0x1050U
#define | DMA_RDTADDR_REG_OFFSET 0x100CU
#define | DMA_CRDADDR_REG_OFFSET 0x104CU
#define | DMA_CRBADDR_REG_OFFSET 0x1054U
#define | MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5))
#define | ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0)
#define | ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1)
#define | ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2)
#define | ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3)
#define | MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
#define | ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0)
#define | ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1)
#define | ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2)
#define | ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3)
#define | ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4)
#define | ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5)
#define | ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6)
#define | ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7)
#define | ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U)
#define | ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD
#define | ENET_JABBER_ENABLE ((uint32_t)0x00000000U)
#define | ENET_JABBER_DISABLE ENET_MAC_CFG_JBD
#define | ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U)
#define | ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD
#define | ENET_SPEEDMODE_10M ((uint32_t)0x00000000U)
#define | ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD
#define | ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)
#define | ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD
#define | ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM
#define | ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)
#define | ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM
#define | ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U)
#define | ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO
#define | ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U)
#define | ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)
#define | ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD
#define | ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD
#define | ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U)
#define | ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD
#define | ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC
#define | ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U)
#define | MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
#define | ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0)
#define | ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1)
#define | ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2)
#define | ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3)
#define | ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR
#define | ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U)
#define | ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT
#define | ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT)
#define | ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT
#define | ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT
#define | ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U)
#define | ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD
#define | ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT
#define | ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U)
#define | ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT
#define | ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM
#define | ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U)
#define | ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT)
#define | ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF
#define | ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U)
#define | ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD
#define | ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD
#define | ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF
#define | ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT
#define | ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT)
#define | ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF
#define | ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U)
#define | ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF
#define | MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
#define | ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0)
#define | ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1)
#define | ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2)
#define | ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3)
#define | MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6))
#define | MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11))
#define | MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
#define | MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define | ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0)
#define | ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1)
#define | ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2)
#define | ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3)
#define | ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U)
#define | ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP
#define | ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP
#define | ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT
#define | ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U)
#define | ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN
#define | ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
#define | ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN
#define | ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN
#define | ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
#define | ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN
#define | ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA
#define | ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U)
#define | ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA
#define | MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
#define | MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
#define | ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC
#define | ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
#define | ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR
#define | ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR
#define | ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR
#define | ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD
#define | ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN
#define | ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN
#define | ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU
#define | MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
#define | MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
#define | ENET_ADDRESS_MASK_BYTE0 BIT(24)
#define | ENET_ADDRESS_MASK_BYTE1 BIT(25)
#define | ENET_ADDRESS_MASK_BYTE2 BIT(26)
#define | ENET_ADDRESS_MASK_BYTE3 BIT(27)
#define | ENET_ADDRESS_MASK_BYTE4 BIT(28)
#define | ENET_ADDRESS_MASK_BYTE5 BIT(29)
#define | ENET_ADDRESS_FILTER_SA BIT(30)
#define | ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000)
#define | MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8)
#define | ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0)
#define | ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1)
#define | ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2)
#define | ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3)
#define | ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4)
#define | ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5)
#define | ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6)
#define | MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8)
#define | ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0)
#define | ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1)
#define | ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2)
#define | ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3)
#define | ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4)
#define | ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5)
#define | ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6)
#define | ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR
#define | ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR
#define | ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ
#define | ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN
#define | ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN
#define | PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
#define | GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30)
#define | ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000)
#define | ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS
#define | GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U))
#define | PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0))
#define | ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000)
#define | ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS
#define | DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2))
#define | GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6)
#define | DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
#define | ENET_PGBL_1BEAT DMA_BCTL_PGBL(1)
#define | ENET_PGBL_2BEAT DMA_BCTL_PGBL(2)
#define | ENET_PGBL_4BEAT DMA_BCTL_PGBL(4)
#define | ENET_PGBL_8BEAT DMA_BCTL_PGBL(8)
#define | ENET_PGBL_16BEAT DMA_BCTL_PGBL(16)
#define | ENET_PGBL_32BEAT DMA_BCTL_PGBL(32)
#define | ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL)
#define | ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL)
#define | ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL)
#define | ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL)
#define | ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL)
#define | ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL)
#define | DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14))
#define | ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0)
#define | ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1)
#define | ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2)
#define | ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3)
#define | ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB
#define | ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB
#define | ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000)
#define | DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17))
#define | ENET_RXDP_1BEAT DMA_BCTL_RXDP(1)
#define | ENET_RXDP_2BEAT DMA_BCTL_RXDP(2)
#define | ENET_RXDP_4BEAT DMA_BCTL_RXDP(4)
#define | ENET_RXDP_8BEAT DMA_BCTL_RXDP(8)
#define | ENET_RXDP_16BEAT DMA_BCTL_RXDP(16)
#define | ENET_RXDP_32BEAT DMA_BCTL_RXDP(32)
#define | ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL)
#define | ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL)
#define | ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL)
#define | ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL)
#define | ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL)
#define | ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL)
#define | ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP
#define | ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000)
#define | ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA
#define | ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000)
#define | GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19)
#define | ENET_RX_STATE_STOPPED ((uint32_t)0x00000000)
#define | ENET_RX_STATE_FETCHING BIT(17)
#define | ENET_RX_STATE_WAITING (BIT(17)|BIT(18))
#define | ENET_RX_STATE_SUSPENDED BIT(19)
#define | ENET_RX_STATE_CLOSING (BIT(17)|BIT(19))
#define | ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP
#define | GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22)
#define | ENET_TX_STATE_STOPPED ((uint32_t)0x00000000)
#define | ENET_TX_STATE_FETCHING BIT(20)
#define | ENET_TX_STATE_WAITING BIT(21)
#define | ENET_TX_STATE_READING (BIT(20)|BIT(21))
#define | ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22))
#define | ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP
#define | GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25)
#define | ENET_ERROR_TXDATA_TRANSFER BIT(23)
#define | ENET_ERROR_READ_TRANSFER BIT(24)
#define | ENET_ERROR_DESC_ACCESS BIT(25)
#define | DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3))
#define | ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0)
#define | ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1)
#define | ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2)
#define | ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3)
#define | DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14))
#define | ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0)
#define | ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1)
#define | ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2)
#define | ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3)
#define | ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4)
#define | ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5)
#define | ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6)
#define | ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7)
#define | ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD
#define | ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000)
#define | ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD
#define | ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000)
#define | ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000)
#define | ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF
#define | ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF
#define | ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD
#define | ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000)
#define | ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2)
#define | ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000)
#define | ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2)
#define | ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2)
#define | ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000)
#define | ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2)
#define | ENET_SECONDFRAME_OPT_ENABLE ((uint32_t)0x00000000)
#define | ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000)
#define | ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF
#define | GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15)
#define | GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27)
#define | TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3))
#define | GET_TDES0_COCNT(regval) GET_BITS((regval),3,6)
#define | TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
#define | ENET_CHECKSUM_DISABLE TDES0_CM(0)
#define | ENET_CHECKSUM_IPV4HEADER TDES0_CM(1)
#define | ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2)
#define | ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3)
#define | TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0))
#define | TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16))
#define | RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16))
#define | GET_RDES0_FRML(regval) GET_BITS((regval),16,29)
#define | ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U)
#define | ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC
#define | GET_RDES1_RB1S(regval) GET_BITS((regval),0,12)
#define | GET_RDES1_RB2S(regval) GET_BITS((regval),16,28)
#define | RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define | GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2)
#define | RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
#define | GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11)
#define | MAC_CFG_MASK ((uint32_t)0xFD30810FU)
#define | MAC_FCTL_MASK ((uint32_t)0x0000FF41U)
#define | DMA_CTL_MASK ((uint32_t)0xF8DE3F23U)
#define | DMA_BCTL_MASK ((uint32_t)0xF800007DU)
#define | ETH_DMATXDESC_SIZE 0x10U
#define | ETH_DMARXDESC_SIZE 0x10U
#define | ETH_WAKEUP_REGISTER_LENGTH 8U
#define | ENET_MAX_FRAME_SIZE 1524U
#define | ENET_DELAY_TO ((uint32_t)0x0004FFFFU)
#define | ENET_RESET_TO ((uint32_t)0x000004FFU)
#define | ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U)
#define | ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len))
#define | ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr))
#define | ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr))
#define | _ENET_DELAY_ enet_delay

Enumerations

enum enet_flag_enum {
ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U),
ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U),
ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U),
ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U),
ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U)
}
enum enet_flag_clear_enum {
ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U)
}
enum enet_int_enum {
ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U),
ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U),
ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U),
ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U),
ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U),
ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U)
}
enum enet_int_flag_enum {
ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U),
ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U),
ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U),
ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U)
}
enum enet_int_flag_clear_enum {
ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U)
}
enum enet_desc_reg_enum {
ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET,
ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET
}
enum enet_msc_counter_enum {
ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET,
ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET
}
enum enet_option_enum {
FORWARD_OPTION = BIT(0), DMABUS_OPTION = BIT(1), DMA_MAXBURST_OPTION = BIT(2), DMA_ARBITRATION_OPTION = BIT(3),
STORE_OPTION = BIT(4), DMA_OPTION = BIT(5), VLAN_OPTION = BIT(6), FLOWCTL_OPTION = BIT(7),
HASHH_OPTION = BIT(8), HASHL_OPTION = BIT(9), FILTER_OPTION = BIT(10), HALFDUPLEX_OPTION = BIT(11),
TIMER_OPTION = BIT(12), INTERFRAMEGAP_OPTION = BIT(13)
}
enum enet_mediamode_enum {
ENET_AUTO_NEGOTIATION = 0x01u, ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD, ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM,
ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM)
}
enum | enet_chksumconf_enum { ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) }
enum | enet_frmrecept_enum { ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD }
enum | enet_registers_type_enum { ALL_MAC_REG = 0, ALL_MSC_REG = 22, ALL_PTP_REG = 33, ALL_DMA_REG = 44 }
enum | enet_dmadirection_enum { ENET_DMA_TX = ENET_DMA_STAT_TP, ENET_DMA_RX = ENET_DMA_STAT_RP }
enum | enet_phydirection_enum { ENET_PHY_READ = (uint32_t)0x00000000, ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW }
enum | enet_regdirection_enum { ENET_REG_READ, ENET_REG_WRITE }
enum | enet_macaddress_enum { ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) }
enum enet_descstate_enum {
TXDESC_COLLISION_COUNT, TXDESC_BUFFER_1_ADDR, RXDESC_FRAME_LENGTH, RXDESC_BUFFER_1_SIZE,
RXDESC_BUFFER_2_SIZE, RXDESC_BUFFER_1_ADDR
}
enum enet_ptp_function_enum {
ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)),
ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU
}

Functions

void | enet_deinit (void)
deinitialize the ENET, and reset structure parameters for ENET initialization More...
void | enet_initpara_config (enet_option_enum option, uint32_t para)
configure the parameters which are usually less cared for initialization note – this function must be called before enet_init(), otherwise configuration will be no effect More...
ErrStatus | enet_init (enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept)
initialize ENET peripheral with generally concerned parameters and the less cared parameters More...
ErrStatus | enet_software_reset (void)
reset all core internal registers located in CLK_TX and CLK_RX More...
uint32_t | enet_rxframe_size_get (void)
check receive frame valid and return frame size More...
void | enet_descriptors_chain_init (enet_dmadirection_enum direction)
initialize the DMA Tx/Rx descriptors's parameters in chain mode More...
void | enet_descriptors_ring_init (enet_dmadirection_enum direction)
initialize the DMA Tx/Rx descriptors's parameters in ring mode More...
ErrStatus | enet_frame_receive (uint8_t *buffer, uint32_t bufsize)
handle current received frame data to application buffer More...
ErrStatus | enet_frame_transmit (uint8_t *buffer, uint32_t length)
handle application buffer data to transmit it More...
void | enet_transmit_checksum_config (enet_descriptors_struct *desc, uint32_t checksum)
configure the transmit IP frame checksum offload calculation and insertion More...
void | enet_enable (void)
ENET Tx and Rx function enable (include MAC and DMA module) More...
void | enet_disable (void)
ENET Tx and Rx function disable (include MAC and DMA module) More...
void | enet_mac_address_set (enet_macaddress_enum mac_addr, uint8_t paddr[])
configure MAC address More...
void | enet_mac_address_get (enet_macaddress_enum mac_addr, uint8_t paddr[])
get MAC address More...
FlagStatus | enet_flag_get (enet_flag_enum enet_flag)
get the ENET MAC/MSC/PTP/DMA status flag More...
void | enet_flag_clear (enet_flag_clear_enum enet_flag)
clear the ENET DMA status flag More...
void | enet_interrupt_enable (enet_int_enum enet_int)
enable ENET MAC/MSC/DMA interrupt More...
void | enet_interrupt_disable (enet_int_enum enet_int)
disable ENET MAC/MSC/DMA interrupt More...
FlagStatus | enet_interrupt_flag_get (enet_int_flag_enum int_flag)
get ENET MAC/MSC/DMA interrupt flag More...
void | enet_interrupt_flag_clear (enet_int_flag_clear_enum int_flag_clear)
clear ENET DMA interrupt flag More...
void | enet_tx_enable (void)
ENET Tx function enable (include MAC and DMA module) More...
void | enet_tx_disable (void)
ENET Tx function disable (include MAC and DMA module) More...
void | enet_rx_enable (void)
ENET Rx function enable (include MAC and DMA module) More...
void | enet_rx_disable (void)
ENET Rx function disable (include MAC and DMA module) More...
void | enet_registers_get (enet_registers_type_enum type, uint32_t *preg, uint32_t num)
put registers value into the application buffer More...
uint32_t | enet_debug_status_get (uint32_t mac_debug)
void | enet_address_filter_enable (enet_macaddress_enum mac_addr)
enable the MAC address filter More...
void | enet_address_filter_disable (enet_macaddress_enum mac_addr)
disable the MAC address filter More...
void | enet_address_filter_config (enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type)
configure the MAC address filter More...
ErrStatus | enet_phy_config (void)
PHY interface configuration (configure SMI clock and reset PHY chip) More...
ErrStatus | enet_phy_write_read (enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register More...
ErrStatus | enet_phyloopback_enable (void)
enable the loopback function of PHY chip More...
ErrStatus | enet_phyloopback_disable (void)
disable the loopback function of PHY chip More...
void | enet_forward_feature_enable (uint32_t feature)
enable ENET forward feature More...
void | enet_forward_feature_disable (uint32_t feature)
disable ENET forward feature More...
void | enet_fliter_feature_enable (uint32_t feature)
enable ENET fliter feature More...
void | enet_fliter_feature_disable (uint32_t feature)
disable ENET fliter feature More...
ErrStatus | enet_pauseframe_generate (void)
generate the pause frame, ENET will send pause frame after enable transmit flow control this function only use in full-dulex mode More...
void | enet_pauseframe_detect_config (uint32_t detect)
configure the pause frame detect type More...
void | enet_pauseframe_config (uint32_t pausetime, uint32_t pause_threshold)
configure the pause frame parameters More...
void | enet_flowcontrol_threshold_config (uint32_t deactive, uint32_t active)
configure the threshold of the flow control(deactive and active threshold) More...
void | enet_flowcontrol_feature_enable (uint32_t feature)
enable ENET flow control feature More...
void | enet_flowcontrol_feature_disable (uint32_t feature)
disable ENET flow control feature More...
uint32_t | enet_dmaprocess_state_get (enet_dmadirection_enum direction)
get the dma transmit/receive process state More...
void | enet_dmaprocess_resume (enet_dmadirection_enum direction)
poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception More...
void | enet_rxprocess_check_recovery (void)
check and recover the Rx process More...
ErrStatus | enet_txfifo_flush (void)
flush the ENET transmit FIFO, and wait until the flush operation completes More...
uint32_t | enet_current_desc_address_get (enet_desc_reg_enum addr_get)
get the transmit/receive address of current descriptor, or current buffer, or descriptor table More...
uint32_t | enet_desc_information_get (enet_descriptors_struct *desc, enet_descstate_enum info_get)
get the Tx or Rx descriptor information More...
void | enet_missed_frame_counter_get (uint32_t *rxfifo_drop, uint32_t *rxdma_drop)
get the number of missed frames during receiving More...
FlagStatus | enet_desc_flag_get (enet_descriptors_struct *desc, uint32_t desc_flag)
get the bit flag of ENET DMA descriptor More...
void | enet_desc_flag_set (enet_descriptors_struct *desc, uint32_t desc_flag)
set the bit flag of ENET DMA descriptor More...
void | enet_desc_flag_clear (enet_descriptors_struct *desc, uint32_t desc_flag)
clear the bit flag of ENET DMA descriptor More...
void | enet_rx_desc_immediate_receive_complete_interrupt (enet_descriptors_struct *desc)
when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set More...
void | enet_rx_desc_delay_receive_complete_interrupt (enet_descriptors_struct *desc, uint32_t delay_time)
void | enet_rxframe_drop (void)
drop current receive frame More...
void | enet_dma_feature_enable (uint32_t feature)
enable DMA feature More...
void | enet_dma_feature_disable (uint32_t feature)
disable DMA feature More...
void | enet_ptp_normal_descriptors_chain_init (enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function More...
void | enet_ptp_normal_descriptors_ring_init (enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function More...
ErrStatus | enet_ptpframe_receive_normal_mode (uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[])
receive a packet data with timestamp values to application buffer, when the DMA is in normal mode More...
ErrStatus | enet_ptpframe_transmit_normal_mode (uint8_t *buffer, uint32_t length, uint32_t timestamp[])
send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode More...
void | enet_wum_filter_register_pointer_reset (void)
wakeup frame filter register pointer reset More...
void | enet_wum_filter_config (uint32_t pdata[])
set the remote wakeup frame registers More...
void | enet_wum_feature_enable (uint32_t feature)
enable wakeup management features More...
void | enet_wum_feature_disable (uint32_t feature)
disable wakeup management features More...
void | enet_msc_counters_reset (void)
reset the MAC statistics counters More...
void | enet_msc_feature_enable (uint32_t feature)
enable the MAC statistics counter features More...
void | enet_msc_feature_disable (uint32_t feature)
disable the MAC statistics counter features More...
uint32_t | enet_msc_counters_get (enet_msc_counter_enum counter)
get MAC statistics counter More...
uint32_t | enet_ptp_subsecond_2_nanosecond (uint32_t subsecond)
change subsecond to nanosecond More...
uint32_t | enet_ptp_nanosecond_2_subsecond (uint32_t nanosecond)
change nanosecond to subsecond More...
void | enet_ptp_feature_enable (uint32_t feature)
enable the PTP features More...
void | enet_ptp_feature_disable (uint32_t feature)
disable the PTP features More...
ErrStatus | enet_ptp_timestamp_function_config (enet_ptp_function_enum func)
configure the PTP timestamp function More...
void | enet_ptp_subsecond_increment_config (uint32_t subsecond)
configure system time subsecond increment value More...
void | enet_ptp_timestamp_addend_config (uint32_t add)
adjusting the clock frequency only in fine update mode More...
void | enet_ptp_timestamp_update_config (uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time More...
void | enet_ptp_expected_time_config (uint32_t second, uint32_t nanosecond)
configure the expected target time More...
void | enet_ptp_system_time_get (enet_ptp_systime_struct *systime_struct)
get the current system time More...
void | enet_ptp_pps_output_frequency_config (uint32_t freq)
void | enet_ptp_start (int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg)
configure and start PTP timestamp counter More...
void | enet_ptp_finecorrection_adjfreq (int32_t carry_cfg)
adjust frequency in fine method by configure addend register More...
void | enet_ptp_coarsecorrection_systime_update (enet_ptp_systime_struct *systime_struct)
update system time in coarse method More...
void | enet_ptp_finecorrection_settime (enet_ptp_systime_struct *systime_struct)
set system time in fine method More...
FlagStatus | enet_ptp_flag_get (uint32_t flag)
get the ptp flag status More...
void | enet_initpara_reset (void)
reset the ENET initpara struct, call it before using enet_initpara_config() More...

Detailed Description

definitions for the ENET

Definition in file gd32f10x_enet.h.

Macro Definition Documentation

#define _ENET_DELAY_ enet_delay

Definition at line 1473 of file gd32f10x_enet.h.

#define DMA_BCTL_DPSL ( regval ) (BITS(2,6) & ((uint32_t)(regval) << 2))

write value to ENET_DMA_BCTL_DPSL bit field

Definition at line 1084 of file gd32f10x_enet.h.

#define DMA_BCTL_MASK ((uint32_t)0xF800007DU)

ENET_DMA_BCTL register mask

Definition at line 1238 of file gd32f10x_enet.h.

#define DMA_BCTL_PGBL ( regval ) (BITS(8,13) & ((uint32_t)(regval) << 8))

write value to ENET_DMA_BCTL_PGBL bit field

Definition at line 1087 of file gd32f10x_enet.h.

#define DMA_BCTL_RTPR ( regval ) (BITS(14,15) & ((uint32_t)(regval) << 14))

write value to ENET_DMA_BCTL_RTPR bit field

Definition at line 1101 of file gd32f10x_enet.h.

#define DMA_BCTL_RXDP ( regval ) (BITS(17,22) & ((uint32_t)(regval) << 17))

write value to ENET_DMA_BCTL_RXDP bit field

Definition at line 1111 of file gd32f10x_enet.h.

#define DMA_CRBADDR_REG_OFFSET 0x1054U

DMA current receive buffer address register

Definition at line 559 of file gd32f10x_enet.h.

#define DMA_CRDADDR_REG_OFFSET 0x104CU

DMA current receive descriptor address register

Definition at line 558 of file gd32f10x_enet.h.

#define DMA_CTBADDR_REG_OFFSET 0x1050U

DMA current transmit buffer address register

Definition at line 556 of file gd32f10x_enet.h.

#define DMA_CTDADDR_REG_OFFSET 0x1048U

DMA current transmit descriptor address register

Definition at line 555 of file gd32f10x_enet.h.

#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U)

ENET_DMA_CTL register mask

Definition at line 1237 of file gd32f10x_enet.h.

#define DMA_CTL_RTHC ( regval ) (BITS(3,4) & ((uint32_t)(regval) << 3))

write value to ENET_DMA_CTL_RTHC bit field

Definition at line 1154 of file gd32f10x_enet.h.

#define DMA_CTL_TTHC ( regval ) (BITS(14,16) & ((uint32_t)(regval) << 14))

write value to ENET_DMA_CTL_TTHC bit field

Definition at line 1160 of file gd32f10x_enet.h.

#define DMA_INTEN_REG_OFFSET 0x101CU

DMA interrupt enable register offset

Definition at line 553 of file gd32f10x_enet.h.

#define DMA_RDTADDR_REG_OFFSET 0x100CU

DMA receive descriptor table address register

Definition at line 557 of file gd32f10x_enet.h.

#define DMA_STAT_REG_OFFSET 0x1014U

DMA status register offset

Definition at line 552 of file gd32f10x_enet.h.

#define DMA_TDTADDR_REG_OFFSET 0x1010U

DMA transmit descriptor table address register offset

Definition at line 554 of file gd32f10x_enet.h.

#define DP83848 0

Definition at line 43 of file gd32f10x_enet.h.

#define ENET ENET_BASE

Definition at line 92 of file gd32f10x_enet.h.

#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3)

threshold level is 1024 bytes

Definition at line 1043 of file gd32f10x_enet.h.

#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4)

threshold level is 1280 bytes

Definition at line 1044 of file gd32f10x_enet.h.

#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5)

threshold level is 1536 bytes

Definition at line 1045 of file gd32f10x_enet.h.

#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6)

threshold level is 1792 bytes

Definition at line 1046 of file gd32f10x_enet.h.

#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0)

threshold level is 256 bytes

Definition at line 1040 of file gd32f10x_enet.h.

#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1)

threshold level is 512 bytes

Definition at line 1041 of file gd32f10x_enet.h.

#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2)

threshold level is 768 bytes

Definition at line 1042 of file gd32f10x_enet.h.

#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000)

disable address-aligned

Definition at line 1129 of file gd32f10x_enet.h.

#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA

enabled address-aligned

Definition at line 1128 of file gd32f10x_enet.h.

#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000)

use MAC address[47:0] is to compare with the DA fields of the received frame

Definition at line 1036 of file gd32f10x_enet.h.

#define ENET_ADDRESS_FILTER_SA BIT(30)

use MAC address[47:0] is to compare with the SA fields of the received frame

Definition at line 1035 of file gd32f10x_enet.h.

#define ENET_ADDRESS_MASK_BYTE0 BIT(24)

low register bits [7:0]

Definition at line 1028 of file gd32f10x_enet.h.

#define ENET_ADDRESS_MASK_BYTE1 BIT(25)

low register bits [15:8]

Definition at line 1029 of file gd32f10x_enet.h.

#define ENET_ADDRESS_MASK_BYTE2 BIT(26)

low register bits [23:16]

Definition at line 1030 of file gd32f10x_enet.h.

#define ENET_ADDRESS_MASK_BYTE3 BIT(27)

low register bits [31:24]

Definition at line 1031 of file gd32f10x_enet.h.

#define ENET_ADDRESS_MASK_BYTE4 BIT(28)

high register bits [7:0]

Definition at line 1032 of file gd32f10x_enet.h.

#define ENET_ADDRESS_MASK_BYTE5 BIT(29)

high register bits [15:8]

Definition at line 1033 of file gd32f10x_enet.h.

#define ENET_ADDRH_BASE ((ENET) + 0x40U)

Definition at line 531 of file gd32f10x_enet.h.

#define ENET_ADDRL_BASE ((ENET) + 0x44U)

Definition at line 532 of file gd32f10x_enet.h.

#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB

RxDMA has higher priority than TxDMA

Definition at line 1106 of file gd32f10x_enet.h.

#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0)

receive and transmit priority ratio is 1:1

Definition at line 1102 of file gd32f10x_enet.h.

#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1)

receive and transmit priority ratio is 2:1

Definition at line 1103 of file gd32f10x_enet.h.

#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2)

receive and transmit priority ratio is 3:1

Definition at line 1104 of file gd32f10x_enet.h.

#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3)

receive and transmit priority ratio is 4:1

Definition at line 1105 of file gd32f10x_enet.h.

#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD

the function of the MAC strips the Pad/FCS field on received frames

Definition at line 922 of file gd32f10x_enet.h.

#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U)

the MAC forwards all received frames without modify it

Definition at line 921 of file gd32f10x_enet.h.

#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD

the MAC strips the Pad/FCS field on received frames

Definition at line 920 of file gd32f10x_enet.h.

#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA

the back pressure operation in the MAC

Definition at line 1004 of file gd32f10x_enet.h.

#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U)

disable the back pressure operation in the MAC

Definition at line 1003 of file gd32f10x_enet.h.

#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA

enable the back pressure operation in the MAC

Definition at line 1002 of file gd32f10x_enet.h.

#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3)

min (n, 1)

Definition at line 881 of file gd32f10x_enet.h.

#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0)

min (n, 10)

Definition at line 878 of file gd32f10x_enet.h.

#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2)

min (n, 4)

Definition at line 880 of file gd32f10x_enet.h.

#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1)

min (n, 8)

Definition at line 879 of file gd32f10x_enet.h.

#define ENET_BIT_POS ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 523 of file gd32f10x_enet.h.

#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD

the address filters filter all incoming broadcast frames

Definition at line 944 of file gd32f10x_enet.h.

#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U)

the address filters pass all received broadcast frames

Definition at line 943 of file gd32f10x_enet.h.

#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD

the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode

Definition at line 900 of file gd32f10x_enet.h.

#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U)

the MAC transmitter generates carrier sense error and aborts the transmission

Definition at line 899 of file gd32f10x_enet.h.

#define ENET_CHECKSUM_DISABLE TDES0_CM(0)

checksum insertion disabled

Definition at line 1205 of file gd32f10x_enet.h.

#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1)

only IP header checksum calculation and insertion are enabled

Definition at line 1206 of file gd32f10x_enet.h.

#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3)

TCP/UDP/ICMP checksum insertion fully calculated

Definition at line 1208 of file gd32f10x_enet.h.

#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2)

TCP/UDP/ICMP checksum insertion calculated but pseudo-header

Definition at line 1207 of file gd32f10x_enet.h.

#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U)

the checksum offload function in the receiver is disabled

Definition at line 915 of file gd32f10x_enet.h.

#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO

IP frame checksum offload function enabled for received IP frame

Definition at line 914 of file gd32f10x_enet.h.

#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3)

threshold level is 1024 bytes

Definition at line 1052 of file gd32f10x_enet.h.

#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4)

threshold level is 1280 bytes

Definition at line 1053 of file gd32f10x_enet.h.

#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5)

threshold level is 1536 bytes

Definition at line 1054 of file gd32f10x_enet.h.

#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6)

threshold level is 1792 bytes

Definition at line 1055 of file gd32f10x_enet.h.

#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0)

threshold level is 256 bytes

Definition at line 1049 of file gd32f10x_enet.h.

#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1)

threshold level is 512 bytes

Definition at line 1050 of file gd32f10x_enet.h.

#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2)

threshold level is 768 bytes

Definition at line 1051 of file gd32f10x_enet.h.

#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U)

the deferral check function is disabled

Definition at line 925 of file gd32f10x_enet.h.

#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC

the deferral check function is enabled in the MAC

Definition at line 924 of file gd32f10x_enet.h.

#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU)

ENET delay timeout

Definition at line 1259 of file gd32f10x_enet.h.

#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT

inverse DA filtering result function

Definition at line 948 of file gd32f10x_enet.h.

#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U)

not inverse DA filtering result

Definition at line 947 of file gd32f10x_enet.h.

#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT

inverse DA filtering result

Definition at line 946 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL REG32((ENET) + 0x1000U)

ethernet DMA bus control register

Definition at line 139 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_AA BIT(25)

address-aligned

Definition at line 362 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_DAB BIT(1)

DMA arbitration

Definition at line 354 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_DPSL BITS(2,6)

descriptor skip length

Definition at line 355 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_FB BIT(16)

fixed Burst

Definition at line 358 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_FPBL BIT(24)

four times PGBL mode

Definition at line 361 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_PGBL BITS(8,13)

programmable burst length

Definition at line 356 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_RTPR BITS(14,15)

RxDMA and TxDMA transfer priority ratio

Definition at line 357 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_RXDP BITS(17,22)

RxDMA PGBL

Definition at line 359 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_SWR BIT(0)

software reset

Definition at line 353 of file gd32f10x_enet.h.

#define ENET_DMA_BCTL_UIP BIT(23)

use independent PGBL

Definition at line 360 of file gd32f10x_enet.h.

#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U)

ethernet DMA current receive buffer address register

Definition at line 151 of file gd32f10x_enet.h.

#define ENET_DMA_CRBADDR_RBAP BITS(0,31)

receive buffer address pointer

Definition at line 446 of file gd32f10x_enet.h.

#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU)

ethernet DMA current receive descriptor address register

Definition at line 149 of file gd32f10x_enet.h.

#define ENET_DMA_CRDADDR_RDAP BITS(0,31)

receive descriptor address pointer

Definition at line 440 of file gd32f10x_enet.h.

#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U)

ethernet DMA current transmit buffer address register

Definition at line 150 of file gd32f10x_enet.h.

#define ENET_DMA_CTBADDR_TBAP BITS(0,31)

transmit buffer address pointer

Definition at line 443 of file gd32f10x_enet.h.

#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U)

ethernet DMA current transmit descriptor address register

Definition at line 148 of file gd32f10x_enet.h.

#define ENET_DMA_CTDADDR_TDAP BITS(0,31)

transmit descriptor address pointer

Definition at line 437 of file gd32f10x_enet.h.

#define ENET_DMA_CTL REG32((ENET) + 0x1018U)

ethernet DMA control register

Definition at line 145 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_DAFRF BIT(24)

disable flushing of received frames

Definition at line 409 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_DTCERFD BIT(26)

dropping of TCP/IP checksum error frames disable

Definition at line 411 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_FERF BIT(7)

forward error frames

Definition at line 404 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_FTF BIT(20)

flush transmit FIFO

Definition at line 407 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_FUF BIT(6)

forward undersized good frames

Definition at line 403 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_OSF BIT(2)

operate on second frame

Definition at line 401 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_RSFD BIT(25)

receive store-and-forward

Definition at line 410 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_RTHC BITS(3,4)

receive threshold control

Definition at line 402 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_SRE BIT(1)

start/stop receive enable

Definition at line 400 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_STE BIT(13)

start/stop transmission enable

Definition at line 405 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_TSFD BIT(21)

transmit store-and-forward

Definition at line 408 of file gd32f10x_enet.h.

#define ENET_DMA_CTL_TTHC BITS(14,16)

transmit threshold control

Definition at line 406 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN REG32((ENET) + 0x101CU)

ethernet DMA interrupt enable register

Definition at line 146 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_AIE BIT(15)

abnormal interrupt summary enable

Definition at line 427 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_ERIE BIT(14)

early receive interrupt enable

Definition at line 426 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_ETIE BIT(10)

early transmit interrupt enable

Definition at line 424 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_FBEIE BIT(13)

fatal bus error interrupt enable

Definition at line 425 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_NIE BIT(16)

normal interrupt summary enable

Definition at line 428 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_RBUIE BIT(7)

receive buffer unavailable interrupt enable

Definition at line 421 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_RIE BIT(6)

receive interrupt enable

Definition at line 420 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_ROIE BIT(4)

receive overflow interrupt enable

Definition at line 418 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_RPSIE BIT(8)

receive process stopped interrupt enable

Definition at line 422 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_RWTIE BIT(9)

receive watchdog timeout interrupt enable

Definition at line 423 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_TBUIE BIT(2)

transmit buffer unavailable interrupt enable

Definition at line 416 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_TIE BIT(0)

transmit interrupt enable

Definition at line 414 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_TJTIE BIT(3)

transmit jabber timeout interrupt enable

Definition at line 417 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_TPSIE BIT(1)

transmit process stopped interrupt enable

Definition at line 415 of file gd32f10x_enet.h.

#define ENET_DMA_INTEN_TUIE BIT(5)

transmit underflow interrupt enable

Definition at line 419 of file gd32f10x_enet.h.

#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U)

ethernet DMA missed frame and buffer overflow counter register

Definition at line 147 of file gd32f10x_enet.h.

#define ENET_DMA_MFBOCNT_MSFA BITS(17,27)

missed frames by the application

Definition at line 433 of file gd32f10x_enet.h.

#define ENET_DMA_MFBOCNT_MSFC BITS(0,15)

missed frames by the controller

Definition at line 431 of file gd32f10x_enet.h.

#define ENET_DMA_MFBOCNT_OBFOC BIT(28)

Overflow bit for FIFO overflow counter

Definition at line 434 of file gd32f10x_enet.h.

#define ENET_DMA_MFBOCNT_OBMFC BIT(16) /* Overflow bit for missed frame counter */

Definition at line 432 of file gd32f10x_enet.h.

#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU)

ethernet DMA receive descriptor table address register

Definition at line 142 of file gd32f10x_enet.h.

#define ENET_DMA_RDTADDR_SRT BITS(0,31)

start address of receive table

Definition at line 371 of file gd32f10x_enet.h.

#define ENET_DMA_RPEN REG32((ENET) + 0x1008U)

ethernet DMA receive poll enable register

Definition at line 141 of file gd32f10x_enet.h.

#define ENET_DMA_RPEN_RPE BITS(0,31)

receive poll enable

Definition at line 368 of file gd32f10x_enet.h.

#define ENET_DMA_STAT REG32((ENET) + 0x1014U)

ethernet DMA status register

Definition at line 144 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_AI BIT(15)

abnormal interrupt summary

Definition at line 390 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_EB BITS(23,25)

error bits status

Definition at line 394 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_ER BIT(14)

early receive status

Definition at line 389 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_ET BIT(10)

early transmit status

Definition at line 387 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_FBE BIT(13)

fatal bus error status

Definition at line 388 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_MSC BIT(27)

MSC status

Definition at line 395 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_NI BIT(16)

normal interrupt summary

Definition at line 391 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_RBU BIT(7)

receive buffer unavailable status

Definition at line 384 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_RO BIT(4)

receive overflow status

Definition at line 381 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_RP BITS(17,19)

receive process state

Definition at line 392 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_RPS BIT(8)

receive process stopped status

Definition at line 385 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_RS BIT(6)

receive status

Definition at line 383 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_RWT BIT(9)

receive watchdog timeout status

Definition at line 386 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_TBU BIT(2)

transmit buffer unavailable status

Definition at line 379 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_TJT BIT(3)

transmit jabber timeout status

Definition at line 380 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_TP BITS(20,22)

transmit process state

Definition at line 393 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_TPS BIT(1)

transmit process stopped status

Definition at line 378 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_TS BIT(0)

transmit status

Definition at line 377 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_TST BIT(29)

timestamp trigger status

Definition at line 397 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_TU BIT(5)

transmit underflow status

Definition at line 382 of file gd32f10x_enet.h.

#define ENET_DMA_STAT_WUM BIT(28)

WUM status

Definition at line 396 of file gd32f10x_enet.h.

#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U)

ethernet DMA transmit descriptor table address register

Definition at line 143 of file gd32f10x_enet.h.

#define ENET_DMA_TDTADDR_STT BITS(0,31)

start address of transmit table

Definition at line 374 of file gd32f10x_enet.h.

#define ENET_DMA_TPEN REG32((ENET) + 0x1004U)

ethernet DMA transmit poll enable register

Definition at line 140 of file gd32f10x_enet.h.

#define ENET_DMA_TPEN_TPE BITS(0,31)

transmit poll enable

Definition at line 365 of file gd32f10x_enet.h.

#define ENET_ERROR_DESC_ACCESS BIT(25)

error during descriptor or buffer access

Definition at line 1151 of file gd32f10x_enet.h.

#define ENET_ERROR_READ_TRANSFER BIT(24)

error during write transfer or read transfer

Definition at line 1150 of file gd32f10x_enet.h.

#define ENET_ERROR_TXDATA_TRANSFER BIT(23)

error during data transfer by TxDMA or RxDMA

Definition at line 1149 of file gd32f10x_enet.h.

#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT

HASH or perfect filter function

Definition at line 959 of file gd32f10x_enet.h.

#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000)

AHB can use SINGLE/INCR burst transfer operations

Definition at line 1109 of file gd32f10x_enet.h.

#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB

AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers

Definition at line 1108 of file gd32f10x_enet.h.

#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF

RxDMA does not flush any frames

Definition at line 1177 of file gd32f10x_enet.h.

#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000)

RxDMA flushes all frames

Definition at line 1176 of file gd32f10x_enet.h.

#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2)

the function that all frame received with error except runt error are forwarded to memory

Definition at line 1185 of file gd32f10x_enet.h.

#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000)

RxFIFO drop error frame

Definition at line 1184 of file gd32f10x_enet.h.

#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2)

all frame received with error except runt error are forwarded to memory

Definition at line 1183 of file gd32f10x_enet.h.

#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2)

the function that forwarding undersized good frames

Definition at line 1189 of file gd32f10x_enet.h.

#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000)

RxFIFO drops all frames whose length is less than 64 bytes

Definition at line 1188 of file gd32f10x_enet.h.

#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2)

forward undersized good frames

Definition at line 1187 of file gd32f10x_enet.h.

#define ENET_GET_MACADDR | ( | offset,
 |  | n
 | ) | ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU))

Definition at line 533 of file gd32f10x_enet.h.

#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7)

minimum 40 bit times

Definition at line 891 of file gd32f10x_enet.h.

#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6)

minimum 48 bit times

Definition at line 890 of file gd32f10x_enet.h.

#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5)

minimum 56 bit times

Definition at line 889 of file gd32f10x_enet.h.

#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4)

minimum 64 bit times

Definition at line 888 of file gd32f10x_enet.h.

#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3)

minimum 72 bit times

Definition at line 887 of file gd32f10x_enet.h.

#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2)

minimum 80 bit times

Definition at line 886 of file gd32f10x_enet.h.

#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1)

minimum 88 bit times

Definition at line 885 of file gd32f10x_enet.h.

#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0)

minimum 96 bit times

Definition at line 884 of file gd32f10x_enet.h.

#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD

the maximum transmission byte can be 16384

Definition at line 897 of file gd32f10x_enet.h.

#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U)

the maximum transmission byte is 2048

Definition at line 896 of file gd32f10x_enet.h.

#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)

the MAC operates in normal mode

Definition at line 909 of file gd32f10x_enet.h.

#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM

the MAC operates in loopback mode at the MII

Definition at line 908 of file gd32f10x_enet.h.

#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT

besides the unique multicast address, MAC also use the MAC0 address to detect pause frame

Definition at line 991 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U)

ethernet MAC address 0 high register

Definition at line 108 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15)

MAC address0 high

Definition at line 241 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR0H_MO BIT(31)

always read 1 and must be kept

Definition at line 242 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U)

ethernet MAC address 0 low register

Definition at line 109 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31)

MAC address0 low

Definition at line 245 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U)

ethernet MAC address 1 high register

Definition at line 110 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15)

MAC address1 high

Definition at line 248 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR1H_AFE BIT(31)

address filter enable

Definition at line 251 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR1H_MB BITS(24,29)

mask byte

Definition at line 249 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR1H_SAF BIT(30)

source address filter

Definition at line 250 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU)

ethernet MAC address 1 low register

Definition at line 111 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31)

MAC address1 low

Definition at line 254 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15)

MAC address2 high

Definition at line 257 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR2H_AFE BIT(31)

address filter enable

Definition at line 260 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR2H_MB BITS(24,29)

mask byte

Definition at line 258 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR2H_SAF BIT(30)

source address filter

Definition at line 259 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U)

ethernet MAC address 2 low register

Definition at line 113 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31)

MAC address2 low

Definition at line 263 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U)

ethernet MAC address 3 high register

Definition at line 114 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15)

MAC address3 high

Definition at line 266 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR3H_AFE BIT(31)

address filter enable

Definition at line 269 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR3H_MB BITS(24,29)

mask byte

Definition at line 267 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR3H_SAF BIT(30)

source address filter

Definition at line 268 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU)

ethernet MAC address 3 low register

Definition at line 115 of file gd32f10x_enet.h.

#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31)

MAC address3 low

Definition at line 272 of file gd32f10x_enet.h.

#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U)

ethernet MAC address 2 high register

Definition at line 112 of file gd32f10x_enet.h.

#define ENET_MAC_CFG REG32((ENET) + 0x00U)

ethernet MAC configuration register

Definition at line 95 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_APCD BIT(7)

automatic pad/CRC drop

Definition at line 159 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_BOL BITS(5,6)

back-off limit

Definition at line 158 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_CSD BIT(16)

carrier sense disable

Definition at line 166 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_DFC BIT(4)

defferal check

Definition at line 157 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_DPM BIT(11)

duplex mode

Definition at line 162 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_IGBS BITS(17,19)

inter-frame gap bit selection

Definition at line 167 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_IPFCO BIT(10)

IP frame checksum offload

Definition at line 161 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_JBD BIT(22)

jabber disable

Definition at line 168 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_LBM BIT(12)

loopback mode

Definition at line 163 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_REN BIT(2)

receiver enable

Definition at line 155 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_ROD BIT(13)

receive own disable

Definition at line 164 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_RTD BIT(9)

retry disable

Definition at line 160 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_SPD BIT(14)

fast eneternet speed

Definition at line 165 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_TEN BIT(3)

transmitter enable

Definition at line 156 of file gd32f10x_enet.h.

#define ENET_MAC_CFG_WDD BIT(23)

watchdog disable

Definition at line 169 of file gd32f10x_enet.h.

#define ENET_MAC_FCTH REG32((ENET) + 0x1080U)

ethernet MAC flow control threshold register

Definition at line 102 of file gd32f10x_enet.h.

#define ENET_MAC_FCTH_RFA BITS(0,2)

threshold of active flow control

Definition at line 210 of file gd32f10x_enet.h.

#define ENET_MAC_FCTH_RFD BITS(4,6)

threshold of deactive flow control

Definition at line 211 of file gd32f10x_enet.h.

#define ENET_MAC_FCTL REG32((ENET) + 0x18U)

ethernet MAC flow control register

Definition at line 101 of file gd32f10x_enet.h.

#define ENET_MAC_FCTL_DZQP BIT(7)

disable zero-quanta pause

Definition at line 206 of file gd32f10x_enet.h.

#define ENET_MAC_FCTL_FLCBBKPA BIT(0)

flow control busy(in full duplex mode)/backpressure activate(in half duplex mode)

Definition at line 201 of file gd32f10x_enet.h.

#define ENET_MAC_FCTL_PLTS BITS(4,5)

pause low threshold

Definition at line 205 of file gd32f10x_enet.h.

#define ENET_MAC_FCTL_PTM BITS(16,31)

pause time

Definition at line 207 of file gd32f10x_enet.h.

#define ENET_MAC_FCTL_RFCEN BIT(2)

receive flow control enable

Definition at line 203 of file gd32f10x_enet.h.

#define ENET_MAC_FCTL_TFCEN BIT(1)

transmit flow control enable

Definition at line 202 of file gd32f10x_enet.h.

#define ENET_MAC_FCTL_UPFDT BIT(3)

unicast pause frame detect

Definition at line 204 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF REG32((ENET) + 0x04U)

ethernet MAC frame filter register

Definition at line 96 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_BFRMD BIT(5)

broadcast frame disable

Definition at line 177 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_DAIFLT BIT(3)

destination address inverse filtering enable

Definition at line 175 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_FAR BIT(31)

frames all receive

Definition at line 182 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_HMF BIT(2)

hash multicast filter

Definition at line 174 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_HPFLT BIT(10)

hash or perfect filter

Definition at line 181 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_HUF BIT(1)

hash unicast filter

Definition at line 173 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_MFD BIT(4)

multicast filter disable

Definition at line 176 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_PCFRM BITS(6,7)

pass control frames

Definition at line 178 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_PM BIT(0)

promiscuous mode

Definition at line 172 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_SAFLT BIT(9)

source address filter

Definition at line 180 of file gd32f10x_enet.h.

#define ENET_MAC_FRMF_SAIFLT BIT(8)

source address inverse filtering

Definition at line 179 of file gd32f10x_enet.h.

#define ENET_MAC_HLH REG32((ENET) + 0x08U)

ethernet MAC hash list high register

Definition at line 97 of file gd32f10x_enet.h.

#define ENET_MAC_HLH_HLH BITS(0,31)

hash list high

Definition at line 185 of file gd32f10x_enet.h.

#define ENET_MAC_HLL REG32((ENET) + 0x0CU)

ethernet MAC hash list low register

Definition at line 98 of file gd32f10x_enet.h.

#define ENET_MAC_HLL_HLL BITS(0,31)

hash list low

Definition at line 188 of file gd32f10x_enet.h.

#define ENET_MAC_INTF REG32((ENET) + 0x38U)

ethernet MAC interrupt flag register

Definition at line 106 of file gd32f10x_enet.h.

#define ENET_MAC_INTF_MSC BIT(4)

MSC status

Definition at line 231 of file gd32f10x_enet.h.

#define ENET_MAC_INTF_MSCR BIT(5)

MSC receive status

Definition at line 232 of file gd32f10x_enet.h.

#define ENET_MAC_INTF_MSCT BIT(6)

MSC transmit status

Definition at line 233 of file gd32f10x_enet.h.

#define ENET_MAC_INTF_TMST BIT(9)

timestamp trigger status

Definition at line 234 of file gd32f10x_enet.h.

#define ENET_MAC_INTF_WUM BIT(3)

WUM status

Definition at line 230 of file gd32f10x_enet.h.

#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU)

ethernet MAC interrupt mask register

Definition at line 107 of file gd32f10x_enet.h.

#define ENET_MAC_INTMSK_TMSTIM BIT(9)

timestamp trigger interrupt mask

Definition at line 238 of file gd32f10x_enet.h.

#define ENET_MAC_INTMSK_WUMIM BIT(3)

WUM interrupt mask

Definition at line 237 of file gd32f10x_enet.h.

#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U)

ethernet MAC PHY control register

Definition at line 99 of file gd32f10x_enet.h.

#define ENET_MAC_PHY_CTL_CLR BITS(2,4)

clock range

Definition at line 193 of file gd32f10x_enet.h.

#define ENET_MAC_PHY_CTL_PA BITS(11,15)

PHY address

Definition at line 195 of file gd32f10x_enet.h.

#define ENET_MAC_PHY_CTL_PB BIT(0)

PHY busy

Definition at line 191 of file gd32f10x_enet.h.

#define ENET_MAC_PHY_CTL_PR BITS(6,10)

PHY register

Definition at line 194 of file gd32f10x_enet.h.

#define ENET_MAC_PHY_CTL_PW BIT(1)

PHY write

Definition at line 192 of file gd32f10x_enet.h.

#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U)

ethernet MAC MII data register

Definition at line 100 of file gd32f10x_enet.h.

#define ENET_MAC_PHY_DATA_PD BITS(0,15)

PHY data

Definition at line 198 of file gd32f10x_enet.h.

#define ENET_MAC_RWFF REG32((ENET) + 0x28U)

ethernet MAC remote wakeup frame filter register

Definition at line 104 of file gd32f10x_enet.h.

#define ENET_MAC_RWFF_DATA BITS(0,31)

wakeup frame filter register data

Definition at line 218 of file gd32f10x_enet.h.

#define ENET_MAC_VLT REG32((ENET) + 0x1CU)

ethernet MAC VLAN tag register

Definition at line 103 of file gd32f10x_enet.h.

#define ENET_MAC_VLT_VLTC BIT(16)

12-bit VLAN tag comparison

Definition at line 215 of file gd32f10x_enet.h.

#define ENET_MAC_VLT_VLTI BITS(0,15)

VLAN tag identifier(for receive frames)

Definition at line 214 of file gd32f10x_enet.h.

#define ENET_MAC_WUM REG32((ENET) + 0x2CU)

ethernet MAC wakeup management register

Definition at line 105 of file gd32f10x_enet.h.

#define ENET_MAC_WUM_GU BIT(9)

global unicast

Definition at line 226 of file gd32f10x_enet.h.

#define ENET_MAC_WUM_MPEN BIT(1)

magic packet enable

Definition at line 222 of file gd32f10x_enet.h.

#define ENET_MAC_WUM_MPKR BIT(5)

magic packet received

Definition at line 224 of file gd32f10x_enet.h.

#define ENET_MAC_WUM_PWD BIT(0)

power down

Definition at line 221 of file gd32f10x_enet.h.

#define ENET_MAC_WUM_WFEN BIT(2)

wakeup frame enable

Definition at line 223 of file gd32f10x_enet.h.

#define ENET_MAC_WUM_WUFFRPR BIT(31)

wakeup frame filter register pointer reset

Definition at line 227 of file gd32f10x_enet.h.

#define ENET_MAC_WUM_WUFR BIT(6)

wakeup frame received

Definition at line 225 of file gd32f10x_enet.h.

#define ENET_MAX_FRAME_SIZE 1524U

header + frame_extra + payload + CRC

Definition at line 1256 of file gd32f10x_enet.h.

#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2)

HCLK:20-35 MHz; MDC clock= HCLK/16

Definition at line 970 of file gd32f10x_enet.h.

#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3)

HCLK:35-60 MHz; MDC clock= HCLK/26

Definition at line 971 of file gd32f10x_enet.h.

#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0)

HCLK:60-100 MHz; MDC clock= HCLK/42

Definition at line 968 of file gd32f10x_enet.h.

#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1)

HCLK:100-120 MHz; MDC clock= HCLK/62

Definition at line 969 of file gd32f10x_enet.h.

#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM

full-duplex mode enable

Definition at line 911 of file gd32f10x_enet.h.

#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U)

half-duplex mode enable

Definition at line 912 of file gd32f10x_enet.h.

#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR

counter stop rollover

Definition at line 1058 of file gd32f10x_enet.h.

#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ

MSC counter freeze

Definition at line 1060 of file gd32f10x_enet.h.

#define ENET_MSC_CTL REG32((ENET) + 0x100U)

ethernet MSC control register

Definition at line 117 of file gd32f10x_enet.h.

#define ENET_MSC_CTL_CTR BIT(0)

counter reset

Definition at line 275 of file gd32f10x_enet.h.

#define ENET_MSC_CTL_CTSR BIT(1)

counter stop rollover

Definition at line 276 of file gd32f10x_enet.h.

#define ENET_MSC_CTL_MCFZ BIT(3)

MSC counter freeze

Definition at line 278 of file gd32f10x_enet.h.

#define ENET_MSC_CTL_RTOR BIT(2)

reset on read

Definition at line 277 of file gd32f10x_enet.h.

#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U)

ethernet MSC transmitted good frames after more than a single collision counter register

Definition at line 123 of file gd32f10x_enet.h.

#define ENET_MSC_MSCCNT_MSCC BITS(0,31)

transmitted good frames more one single collision counter

Definition at line 304 of file gd32f10x_enet.h.

#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR

reset on read

Definition at line 1059 of file gd32f10x_enet.h.

#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U)

ethernet MSC received frames with alignment error counter register

Definition at line 126 of file gd32f10x_enet.h.

#define ENET_MSC_RFAECNT_RFAER BITS(0,31)

received frames alignment error counter

Definition at line 313 of file gd32f10x_enet.h.

#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U)

ethernet MSC received frames with CRC error counter register

Definition at line 125 of file gd32f10x_enet.h.

#define ENET_MSC_RFCECNT_RFCER BITS(0,31)

received frames with CRC error counter

Definition at line 310 of file gd32f10x_enet.h.

#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U)

ethernet MSC received good unicast frames counter register

Definition at line 127 of file gd32f10x_enet.h.

#define ENET_MSC_RGUFCNT_RGUF BITS(0,31)

received good unicast frames counter

Definition at line 316 of file gd32f10x_enet.h.

#define ENET_MSC_RINTF REG32((ENET) + 0x104U)

ethernet MSC receive interrupt flag register

Definition at line 118 of file gd32f10x_enet.h.

#define ENET_MSC_RINTF_RFAE BIT(6)

received frames alignment error

Definition at line 282 of file gd32f10x_enet.h.

#define ENET_MSC_RINTF_RFCE BIT(5)

received frames CRC error

Definition at line 281 of file gd32f10x_enet.h.

#define ENET_MSC_RINTF_RGUF BIT(17)

receive good unicast frames

Definition at line 283 of file gd32f10x_enet.h.

#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU)

ethernet MSC receive interrupt mask register

Definition at line 120 of file gd32f10x_enet.h.

#define ENET_MSC_RINTMSK_RFAEIM BIT(6)

received frames alignment error interrupt mask

Definition at line 292 of file gd32f10x_enet.h.

#define ENET_MSC_RINTMSK_RFCEIM BIT(5)

received frame CRC error interrupt mask

Definition at line 291 of file gd32f10x_enet.h.

#define ENET_MSC_RINTMSK_RGUFIM BIT(17)

received good unicast frames interrupt mask

Definition at line 293 of file gd32f10x_enet.h.

#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU)

ethernet MSC transmitted good frames after a single collision counter register

Definition at line 122 of file gd32f10x_enet.h.

#define ENET_MSC_SCCNT_SCC BITS(0,31)

transmitted good frames single collision counter

Definition at line 301 of file gd32f10x_enet.h.

#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U)

ethernet MSC transmitted good frames counter register

Definition at line 124 of file gd32f10x_enet.h.

#define ENET_MSC_TGFCNT_TGF BITS(0,31)

transmitted good frames counter

Definition at line 307 of file gd32f10x_enet.h.

#define ENET_MSC_TINTF REG32((ENET) + 0x108U)

ethernet MSC transmit interrupt flag register

Definition at line 119 of file gd32f10x_enet.h.

#define ENET_MSC_TINTF_TGF BIT(21)

transmitted good frames

Definition at line 288 of file gd32f10x_enet.h.

#define ENET_MSC_TINTF_TGFMSC BIT(15)

transmitted good frames more single collision

Definition at line 287 of file gd32f10x_enet.h.

#define ENET_MSC_TINTF_TGFSC BIT(14)

transmitted good frames single collision

Definition at line 286 of file gd32f10x_enet.h.

#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U)

ethernet MSC transmit interrupt mask register

Definition at line 121 of file gd32f10x_enet.h.

#define ENET_MSC_TINTMSK_TGFIM BIT(21)

transmitted good frames interrupt mask

Definition at line 298 of file gd32f10x_enet.h.

#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15)

transmitted good frames more single collision interrupt mask

Definition at line 297 of file gd32f10x_enet.h.

#define ENET_MSC_TINTMSK_TGFSCIM BIT(14)

transmitted good frames single collision interrupt mask

Definition at line 296 of file gd32f10x_enet.h.

#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF

pass multicast frames that match the hash filtering

Definition at line 954 of file gd32f10x_enet.h.

#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF

HASH multicast filter function

Definition at line 958 of file gd32f10x_enet.h.

#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT)

pass multicast frames that match either the perfect or the hash filtering

Definition at line 953 of file gd32f10x_enet.h.

#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD

all multicast frames are passed

Definition at line 956 of file gd32f10x_enet.h.

#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD

pass all multicast frames function

Definition at line 957 of file gd32f10x_enet.h.

#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U)

pass multicast frames that match the perfect filtering

Definition at line 955 of file gd32f10x_enet.h.

#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF

RxDMA does not flush frames function

Definition at line 1178 of file gd32f10x_enet.h.

#define ENET_NOCOPY_FRAME_RECEIVE ( ) enet_frame_receive(NULL, 0U)

Definition at line 1281 of file gd32f10x_enet.h.

#define ENET_NOCOPY_FRAME_TRANSMIT ( len ) enet_frame_transmit(NULL, (len))

Definition at line 1285 of file gd32f10x_enet.h.

#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE ( ptr ) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr))

Definition at line 1401 of file gd32f10x_enet.h.

#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE | ( | len,
 |  | ptr
 | ) | enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr))

Definition at line 1405 of file gd32f10x_enet.h.

#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2)

pause time minus 144 slot times

Definition at line 984 of file gd32f10x_enet.h.

#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3)

pause time minus 256 slot times

Definition at line 985 of file gd32f10x_enet.h.

#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1)

pause time minus 28 slot times

Definition at line 983 of file gd32f10x_enet.h.

#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0)

pause time minus 4 slot times

Definition at line 982 of file gd32f10x_enet.h.

#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2)

MAC forwards all control frames to application even if they fail the address filter

Definition at line 931 of file gd32f10x_enet.h.

#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3)

MAC forwards control frames that only pass the address filter

Definition at line 932 of file gd32f10x_enet.h.

#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0)

MAC prevents all control frames from reaching the application

Definition at line 929 of file gd32f10x_enet.h.

#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1)

MAC only forwards all other control frames except pause control frame

Definition at line 930 of file gd32f10x_enet.h.

#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16)

maximum number of beats is 16

Definition at line 1092 of file gd32f10x_enet.h.

#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1)

maximum number of beats is 1

Definition at line 1088 of file gd32f10x_enet.h.

#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2)

maximum number of beats is 2

Definition at line 1089 of file gd32f10x_enet.h.

#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32)

maximum number of beats is 32

Definition at line 1093 of file gd32f10x_enet.h.

#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4)

maximum number of beats is 4

Definition at line 1090 of file gd32f10x_enet.h.

#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL)

maximum number of beats is 128

Definition at line 1099 of file gd32f10x_enet.h.

#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL)

maximum number of beats is 16

Definition at line 1096 of file gd32f10x_enet.h.

#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL)

maximum number of beats is 32

Definition at line 1097 of file gd32f10x_enet.h.

#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL)

maximum number of beats is 4

Definition at line 1094 of file gd32f10x_enet.h.

#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL)

maximum number of beats is 64

Definition at line 1098 of file gd32f10x_enet.h.

#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL)

maximum number of beats is 8

Definition at line 1095 of file gd32f10x_enet.h.

#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8)

maximum number of beats is 8

Definition at line 1091 of file gd32f10x_enet.h.

#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U)

promiscuous mode disabled

Definition at line 951 of file gd32f10x_enet.h.

#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM

promiscuous mode enabled

Definition at line 950 of file gd32f10x_enet.h.

#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000)

timestamp update value is added to system time

Definition at line 1080 of file gd32f10x_enet.h.

#define ENET_PTP_ETH REG32((ENET) + 0x71CU)

ethernet PTP expected time high register

Definition at line 136 of file gd32f10x_enet.h.

#define ENET_PTP_ETH_ETSH BITS(0,31)

expected time high

Definition at line 347 of file gd32f10x_enet.h.

#define ENET_PTP_ETL REG32((ENET) + 0x720U)

ethernet PTP expected time low register

Definition at line 137 of file gd32f10x_enet.h.

#define ENET_PTP_ETL_ETSL BITS(0,31)

expected time low

Definition at line 350 of file gd32f10x_enet.h.

#define ENET_PTP_SSINC REG32((ENET) + 0x704U)

ethernet PTP subsecond increment register

Definition at line 130 of file gd32f10x_enet.h.

#define ENET_PTP_SSINC_STMSSI BITS(0,7)

system time subsecond increment

Definition at line 327 of file gd32f10x_enet.h.

#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS

timestamp update value is subtracted from system time

Definition at line 1081 of file gd32f10x_enet.h.

#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS

time value is negative

Definition at line 1073 of file gd32f10x_enet.h.

#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000)

time value is positive

Definition at line 1072 of file gd32f10x_enet.h.

#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN

timestamp interrupt trigger enable

Definition at line 1064 of file gd32f10x_enet.h.

#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U)

ethernet PTP time stamp addend register

Definition at line 135 of file gd32f10x_enet.h.

#define ENET_PTP_TSADDEND_TMSA BITS(0,31)

timestamp addend

Definition at line 344 of file gd32f10x_enet.h.

#define ENET_PTP_TSCTL REG32((ENET) + 0x700U)

ethernet PTP time stamp control register

Definition at line 129 of file gd32f10x_enet.h.

#define ENET_PTP_TSCTL_TMSARU BIT(5)

timestamp addend register update

Definition at line 324 of file gd32f10x_enet.h.

#define ENET_PTP_TSCTL_TMSEN BIT(0)

timestamp enable

Definition at line 319 of file gd32f10x_enet.h.

#define ENET_PTP_TSCTL_TMSFCU BIT(1)

timestamp fine or coarse update

Definition at line 320 of file gd32f10x_enet.h.

#define ENET_PTP_TSCTL_TMSITEN BIT(4)

timestamp interrupt trigger enable

Definition at line 323 of file gd32f10x_enet.h.

#define ENET_PTP_TSCTL_TMSSTI BIT(2)

timestamp system time initialize

Definition at line 321 of file gd32f10x_enet.h.

#define ENET_PTP_TSCTL_TMSSTU BIT(3)

timestamp system time update

Definition at line 322 of file gd32f10x_enet.h.

#define ENET_PTP_TSH REG32((ENET) + 0x708U)

ethernet PTP time stamp high register

Definition at line 131 of file gd32f10x_enet.h.

#define ENET_PTP_TSH_STMS BITS(0,31)

system time second

Definition at line 330 of file gd32f10x_enet.h.

#define ENET_PTP_TSL REG32((ENET) + 0x70CU)

ethernet PTP time stamp low register

Definition at line 132 of file gd32f10x_enet.h.

#define ENET_PTP_TSL_STMSS BITS(0,30)

system time subseconds

Definition at line 333 of file gd32f10x_enet.h.

#define ENET_PTP_TSL_STS BIT(31)

system time sign

Definition at line 334 of file gd32f10x_enet.h.

#define ENET_PTP_TSUH REG32((ENET) + 0x710U)

ethernet PTP time stamp update high register

Definition at line 133 of file gd32f10x_enet.h.

#define ENET_PTP_TSUH_TMSUS BITS(0,31)

timestamp update seconds

Definition at line 337 of file gd32f10x_enet.h.

#define ENET_PTP_TSUL REG32((ENET) + 0x714U)

ethernet PTP time stamp update low register

Definition at line 134 of file gd32f10x_enet.h.

#define ENET_PTP_TSUL_TMSUPNS BIT(31)

timestamp update positive or negative sign

Definition at line 341 of file gd32f10x_enet.h.

#define ENET_PTP_TSUL_TMSUSS BITS(0,30)

timestamp update subseconds

Definition at line 340 of file gd32f10x_enet.h.

#define ENET_RANGE | ( | hclk,
 |  | n,
 |  | m
 | ) | (((hclk) >= (n))&&((hclk) < (m)))

Definition at line 526 of file gd32f10x_enet.h.

#define ENET_RDES0_CERR BIT(1)

CRC error

Definition at line 487 of file gd32f10x_enet.h.

#define ENET_RDES0_DAFF BIT(30)

destination address filter fail

Definition at line 503 of file gd32f10x_enet.h.

#define ENET_RDES0_DAV BIT(31)

descriptor available

Definition at line 504 of file gd32f10x_enet.h.

#define ENET_RDES0_DBERR BIT(2)

dribble bit error

Definition at line 488 of file gd32f10x_enet.h.

#define ENET_RDES0_DERR BIT(14)

descriptor error

Definition at line 500 of file gd32f10x_enet.h.

#define ENET_RDES0_ERRS BIT(15)

error summary

Definition at line 501 of file gd32f10x_enet.h.

#define ENET_RDES0_FDES BIT(9)

first descriptor

Definition at line 495 of file gd32f10x_enet.h.

#define ENET_RDES0_FRML BITS(16,29)

frame length

Definition at line 502 of file gd32f10x_enet.h.

#define ENET_RDES0_FRMT BIT(5)

frame type

Definition at line 491 of file gd32f10x_enet.h.

#define ENET_RDES0_IPHERR BIT(7)

IP frame header error

Definition at line 493 of file gd32f10x_enet.h.

#define ENET_RDES0_LCO BIT(6)

late collision

Definition at line 492 of file gd32f10x_enet.h.

#define ENET_RDES0_LDES BIT(8)

last descriptor

Definition at line 494 of file gd32f10x_enet.h.

#define ENET_RDES0_LERR BIT(12)

length error

Definition at line 498 of file gd32f10x_enet.h.

#define ENET_RDES0_OERR BIT(11)

overflow Error

Definition at line 497 of file gd32f10x_enet.h.

#define ENET_RDES0_PCERR BIT(0)

payload checksum error

Definition at line 486 of file gd32f10x_enet.h.

#define ENET_RDES0_RERR BIT(3)

receive error

Definition at line 489 of file gd32f10x_enet.h.

#define ENET_RDES0_RWDT BIT(4)

receive watchdog timeout

Definition at line 490 of file gd32f10x_enet.h.

#define ENET_RDES0_SAFF BIT(13)

SA filter fail

Definition at line 499 of file gd32f10x_enet.h.

#define ENET_RDES0_VTAG BIT(10)

VLAN tag

Definition at line 496 of file gd32f10x_enet.h.

#define ENET_RDES1_DINTC BIT(31)

disable interrupt on completion

Definition at line 511 of file gd32f10x_enet.h.

#define ENET_RDES1_RB1S BITS(0,12)

receive buffer 1 size

Definition at line 507 of file gd32f10x_enet.h.

#define ENET_RDES1_RB2S BITS(16,28)

receive buffer 2 size

Definition at line 510 of file gd32f10x_enet.h.

#define ENET_RDES1_RCHM BIT(14)

receive chained mode for second address

Definition at line 508 of file gd32f10x_enet.h.

#define ENET_RDES1_RERM BIT(15)

receive end of ring mode

Definition at line 509 of file gd32f10x_enet.h.

#define ENET_RDES2_RB1AP BITS(0,31)

receive buffer 1 address pointer / receive frame timestamp low 32-bit

Definition at line 514 of file gd32f10x_enet.h.

#define ENET_RDES3_RB2AP BITS(0,31)

receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value

Definition at line 517 of file gd32f10x_enet.h.

#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC

RS bit not immediately set after Rx completed

Definition at line 1221 of file gd32f10x_enet.h.

#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U)

RS bit immediately set after Rx completed

Definition at line 1220 of file gd32f10x_enet.h.

#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD

the MAC disables the reception of frames in half-duplex mode

Definition at line 906 of file gd32f10x_enet.h.

#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)

the MAC receives all packets that are given by the PHY while transmitting

Definition at line 905 of file gd32f10x_enet.h.

#define ENET_REG_VAL ( periph ) (REG32(ENET + ((uint32_t)(periph)>>6)))

Definition at line 522 of file gd32f10x_enet.h.

#define ENET_REGIDX_BIT | ( | regidx,
 |  | bitpos
 | ) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))

Definition at line 521 of file gd32f10x_enet.h.

#define ENET_RESET_TO ((uint32_t)0x000004FFU)

ENET reset timeout

Definition at line 1260 of file gd32f10x_enet.h.

#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD

the MAC attempts only 1 transmission

Definition at line 918 of file gd32f10x_enet.h.

#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)

the MAC attempts retries up to 16 times based on the settings of BOL

Definition at line 917 of file gd32f10x_enet.h.

#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR

all received frame are forwarded to application

Definition at line 934 of file gd32f10x_enet.h.

#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U)

only the frame passed the filter can be forwarded to application

Definition at line 935 of file gd32f10x_enet.h.

#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN

decoding function for the received pause frame and process it

Definition at line 996 of file gd32f10x_enet.h.

#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U)

decode function for pause frame is disabled

Definition at line 995 of file gd32f10x_enet.h.

#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN

enable decoding function for the received pause frame and process it

Definition at line 994 of file gd32f10x_enet.h.

#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000)

RxFIFO operates in cut-through mode

Definition at line 1174 of file gd32f10x_enet.h.

#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD

RxFIFO operates in store-and-forward mode

Definition at line 1173 of file gd32f10x_enet.h.

#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19))

closing receive descriptor

Definition at line 1137 of file gd32f10x_enet.h.

#define ENET_RX_STATE_FETCHING BIT(17)

fetching the Rx descriptor

Definition at line 1134 of file gd32f10x_enet.h.

#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP

transferring the receive packet data from recevie buffer to host memory

Definition at line 1138 of file gd32f10x_enet.h.

#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000)

reset or stop rx command issued

Definition at line 1133 of file gd32f10x_enet.h.

#define ENET_RX_STATE_SUSPENDED BIT(19)

Rx descriptor unavailable

Definition at line 1136 of file gd32f10x_enet.h.

#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18))

waiting for receive packet

Definition at line 1135 of file gd32f10x_enet.h.

#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3)

threshold level is 128 Bytes

Definition at line 1158 of file gd32f10x_enet.h.

#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1)

threshold level is 32 Bytes

Definition at line 1156 of file gd32f10x_enet.h.

#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0)

threshold level is 64 Bytes

Definition at line 1155 of file gd32f10x_enet.h.

#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2)

threshold level is 96 Bytes

Definition at line 1157 of file gd32f10x_enet.h.

#define ENET_RXBUF_NUM 5U

ethernet Rx DMA descriptor number

Definition at line 25 of file gd32f10x_enet.h.

#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE

ethernet receive buffer size

Definition at line 33 of file gd32f10x_enet.h.

#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16)

maximum number of beats 16

Definition at line 1116 of file gd32f10x_enet.h.

#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1)

maximum number of beats 1

Definition at line 1112 of file gd32f10x_enet.h.

#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2)

maximum number of beats 2

Definition at line 1113 of file gd32f10x_enet.h.

#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32)

maximum number of beats 32

Definition at line 1117 of file gd32f10x_enet.h.

#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4)

maximum number of beats 4

Definition at line 1114 of file gd32f10x_enet.h.

#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL)

maximum number of beats 128

Definition at line 1123 of file gd32f10x_enet.h.

#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL)

maximum number of beats 16

Definition at line 1120 of file gd32f10x_enet.h.

#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL)

maximum number of beats 32

Definition at line 1121 of file gd32f10x_enet.h.

#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL)

maximum number of beats 4

Definition at line 1118 of file gd32f10x_enet.h.

#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL)

maximum number of beats 64

Definition at line 1122 of file gd32f10x_enet.h.

#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL)

maximum number of beats 8

Definition at line 1119 of file gd32f10x_enet.h.

#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8)

maximum number of beats 8

Definition at line 1115 of file gd32f10x_enet.h.

#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP

RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0]

Definition at line 1125 of file gd32f10x_enet.h.

#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000)

RxDMA/TxDMA uses PGBL[5:0]

Definition at line 1126 of file gd32f10x_enet.h.

#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN

enable timestamp function for transmit and receive frames

Definition at line 1063 of file gd32f10x_enet.h.

#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF

TxDMA controller operate on second frame function

Definition at line 1193 of file gd32f10x_enet.h.

#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000)

TxDMA controller operate on second frame mode disable

Definition at line 1192 of file gd32f10x_enet.h.

#define ENET_SECONDFRAME_OPT_ENABLE ((uint32_t)0x00000000)

TxDMA controller operate on second frame mode enable

Definition at line 1191 of file gd32f10x_enet.h.

#define ENET_SET_MACADDRH ( p ) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4])

Definition at line 529 of file gd32f10x_enet.h.

#define ENET_SET_MACADDRL ( p ) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0])

Definition at line 530 of file gd32f10x_enet.h.

#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD

100 Mbit/s

Definition at line 903 of file gd32f10x_enet.h.

#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U)

10 Mbit/s

Definition at line 902 of file gd32f10x_enet.h.

#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT

filter source address function

Definition at line 940 of file gd32f10x_enet.h.

#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U)

source address function in filter disable

Definition at line 939 of file gd32f10x_enet.h.

#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT

inverse source address filtering result function

Definition at line 941 of file gd32f10x_enet.h.

#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT)

inverse source address filtering result

Definition at line 938 of file gd32f10x_enet.h.

#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT

filter source address

Definition at line 937 of file gd32f10x_enet.h.

#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD

Rx frame with only payload error but no other errors will not be dropped

Definition at line 1170 of file gd32f10x_enet.h.

#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000)

all error frames will be dropped when FERF = 0

Definition at line 1171 of file gd32f10x_enet.h.

#define ENET_TDES0_CM BITS(22,23)

checksum mode

Definition at line 466 of file gd32f10x_enet.h.

#define ENET_TDES0_COCNT BITS(3,6)

collision count

Definition at line 452 of file gd32f10x_enet.h.

#define ENET_TDES0_DAV BIT(31)

DAV bit

Definition at line 473 of file gd32f10x_enet.h.

#define ENET_TDES0_DB BIT(0)

deferred

Definition at line 449 of file gd32f10x_enet.h.

#define ENET_TDES0_DCRC BIT(27)

disable CRC

Definition at line 469 of file gd32f10x_enet.h.

#define ENET_TDES0_DPAD BIT(26)

disable adding pad

Definition at line 468 of file gd32f10x_enet.h.

#define ENET_TDES0_ECO BIT(8)

excessive collision

Definition at line 454 of file gd32f10x_enet.h.

#define ENET_TDES0_ES BIT(15)

error summary

Definition at line 461 of file gd32f10x_enet.h.

#define ENET_TDES0_EXD BIT(2)

excessive deferral

Definition at line 451 of file gd32f10x_enet.h.

#define ENET_TDES0_FRMF BIT(13)

frame flushed

Definition at line 459 of file gd32f10x_enet.h.

#define ENET_TDES0_FSG BIT(28)

first segment

Definition at line 470 of file gd32f10x_enet.h.

#define ENET_TDES0_INTC BIT(30)

interrupt on completion

Definition at line 472 of file gd32f10x_enet.h.

#define ENET_TDES0_IPHE BIT(16)

IP header error

Definition at line 462 of file gd32f10x_enet.h.

#define ENET_TDES0_IPPE BIT(12)

IP payload error

Definition at line 458 of file gd32f10x_enet.h.

#define ENET_TDES0_JT BIT(14)

jabber timeout

Definition at line 460 of file gd32f10x_enet.h.

#define ENET_TDES0_LCA BIT(11)

loss of carrier

Definition at line 457 of file gd32f10x_enet.h.

#define ENET_TDES0_LCO BIT(9)

late collision

Definition at line 455 of file gd32f10x_enet.h.

#define ENET_TDES0_LSG BIT(29)

last segment

Definition at line 471 of file gd32f10x_enet.h.

#define ENET_TDES0_NCA BIT(10)

no carrier

Definition at line 456 of file gd32f10x_enet.h.

#define ENET_TDES0_TCHM BIT(20)

the second address chained mode

Definition at line 464 of file gd32f10x_enet.h.

#define ENET_TDES0_TERM BIT(21)

transmit end of ring mode

Definition at line 465 of file gd32f10x_enet.h.

#define ENET_TDES0_TTMSS BIT(17)

transmit timestamp status

Definition at line 463 of file gd32f10x_enet.h.

#define ENET_TDES0_TTSEN BIT(25)

transmit timestamp function enable

Definition at line 467 of file gd32f10x_enet.h.

#define ENET_TDES0_UFE BIT(1)

underflow error

Definition at line 450 of file gd32f10x_enet.h.

#define ENET_TDES0_VFRM BIT(7)

VLAN frame

Definition at line 453 of file gd32f10x_enet.h.

#define ENET_TDES1_TB1S BITS(0,12)

transmit buffer 1 size

Definition at line 476 of file gd32f10x_enet.h.

#define ENET_TDES1_TB2S BITS(16,28)

transmit buffer 2 size

Definition at line 477 of file gd32f10x_enet.h.

#define ENET_TDES2_TB1AP BITS(0,31)

transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value

Definition at line 480 of file gd32f10x_enet.h.

#define ENET_TDES3_TB2AP BITS(0,31)

transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value

Definition at line 483 of file gd32f10x_enet.h.

#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN

the flow control operation in the MAC

Definition at line 1000 of file gd32f10x_enet.h.

#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U)

disable the flow control operation in the MAC

Definition at line 999 of file gd32f10x_enet.h.

#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN

enable the flow control operation in the MAC

Definition at line 998 of file gd32f10x_enet.h.

#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000)

TxFIFO operates in cut-through mode

Definition at line 1181 of file gd32f10x_enet.h.

#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD

TxFIFO operates in store-and-forward mode

Definition at line 1180 of file gd32f10x_enet.h.

#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP

closing Tx descriptor

Definition at line 1146 of file gd32f10x_enet.h.

#define ENET_TX_STATE_FETCHING BIT(20)

fetching the Tx descriptor

Definition at line 1142 of file gd32f10x_enet.h.

#define ENET_TX_STATE_READING (BIT(20)|BIT(21))

reading the data from host memory buffer and queuing it to transmit buffer

Definition at line 1144 of file gd32f10x_enet.h.

#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000)

reset or stop Tx Command issued

Definition at line 1141 of file gd32f10x_enet.h.

#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22))

Tx descriptor unavailabe or transmit buffer underflow

Definition at line 1145 of file gd32f10x_enet.h.

#define ENET_TX_STATE_WAITING BIT(21)

waiting for status

Definition at line 1143 of file gd32f10x_enet.h.

#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1)

threshold level is 128 Bytes

Definition at line 1162 of file gd32f10x_enet.h.

#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7)

threshold level is 16 Bytes

Definition at line 1168 of file gd32f10x_enet.h.

#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2)

threshold level is 192 Bytes

Definition at line 1163 of file gd32f10x_enet.h.

#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6)

threshold level is 24 Bytes

Definition at line 1167 of file gd32f10x_enet.h.

#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3)

threshold level is 256 Bytes

Definition at line 1164 of file gd32f10x_enet.h.

#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5)

threshold level is 32 Bytes

Definition at line 1166 of file gd32f10x_enet.h.

#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4)

threshold level is 40 Bytes

Definition at line 1165 of file gd32f10x_enet.h.

#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0)

threshold level is 64 Bytes

Definition at line 1161 of file gd32f10x_enet.h.

#define ENET_TXBUF_NUM 5U

ethernet Tx DMA descriptor number

Definition at line 29 of file gd32f10x_enet.h.

#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE

ethernet transmit buffer size

Definition at line 37 of file gd32f10x_enet.h.

#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT)

pass unicast frames that match either the perfect or the hash filtering

Definition at line 961 of file gd32f10x_enet.h.

#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF

pass unicast frames that match the hash filtering

Definition at line 962 of file gd32f10x_enet.h.

#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF

HASH unicast filter function

Definition at line 964 of file gd32f10x_enet.h.

#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U)

pass unicast frames that match the perfect filtering

Definition at line 963 of file gd32f10x_enet.h.

#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U)

only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected

Definition at line 992 of file gd32f10x_enet.h.

#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC

only low 12 bits of the VLAN tag are used for comparison

Definition at line 1010 of file gd32f10x_enet.h.

#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)

all 16 bits of the VLAN tag are used for comparison

Definition at line 1011 of file gd32f10x_enet.h.

#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD

the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes

Definition at line 894 of file gd32f10x_enet.h.

#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U)

the MAC allows no more than 2048 bytes of the frame being received

Definition at line 893 of file gd32f10x_enet.h.

#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR

magic packet received

Definition at line 1016 of file gd32f10x_enet.h.

#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR

wakeup frame filter register poniter reset

Definition at line 1014 of file gd32f10x_enet.h.

#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR

wakeup frame received

Definition at line 1015 of file gd32f10x_enet.h.

#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU

any received unicast frame passed filter is considered to be a wakeup frame

Definition at line 1020 of file gd32f10x_enet.h.

#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN

enable a wakeup event due to magic packet reception

Definition at line 1018 of file gd32f10x_enet.h.

#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD

power down mode

Definition at line 1017 of file gd32f10x_enet.h.

#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN

enable a wakeup event due to wakeup frame reception

Definition at line 1019 of file gd32f10x_enet.h.

#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP

the automatic zero-quanta generation function

Definition at line 989 of file gd32f10x_enet.h.

#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP

disable the automatic zero-quanta generation function

Definition at line 988 of file gd32f10x_enet.h.

#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U)

enable the automatic zero-quanta generation function

Definition at line 987 of file gd32f10x_enet.h.

#define ETH_DMARXDESC_SIZE 0x10U

RxDMA descriptor size

Definition at line 1241 of file gd32f10x_enet.h.

#define ETH_DMATXDESC_SIZE 0x10U

TxDMA descriptor size

Definition at line 1240 of file gd32f10x_enet.h.

#define ETH_WAKEUP_REGISTER_LENGTH 8U

remote wake-up frame register length

Definition at line 1253 of file gd32f10x_enet.h.

#define GET_DMA_BCTL_DPSL ( regval ) GET_BITS((regval),2,6)

get value of ENET_DMA_BCTL_DPSL bit field

Definition at line 1085 of file gd32f10x_enet.h.

#define GET_DMA_MFBOCNT_MSFA ( regval ) GET_BITS((regval),17,27)

get value of ENET_DMA_MFBOCNT_MSFA bit field

Definition at line 1198 of file gd32f10x_enet.h.

#define GET_DMA_MFBOCNT_MSFC ( regval ) GET_BITS((regval),0,15)

get value of ENET_DMA_MFBOCNT_MSFC bit field

Definition at line 1196 of file gd32f10x_enet.h.

#define GET_DMA_STAT_EB ( regval ) GET_BITS((uint32_t)(regval),23,25)

get value of ENET_DMA_STAT_EB bit field

Definition at line 1148 of file gd32f10x_enet.h.

#define GET_DMA_STAT_RP ( regval ) GET_BITS((uint32_t)(regval),17,19)

get value of ENET_DMA_STAT_RP bit field

Definition at line 1132 of file gd32f10x_enet.h.

#define GET_DMA_STAT_TP ( regval ) GET_BITS((uint32_t)(regval),20,22)

get value of ENET_DMA_STAT_TP bit field

Definition at line 1140 of file gd32f10x_enet.h.

#define GET_PTP_TSL_STMSS ( regval ) GET_BITS((uint32_t)(regval),0,30)

get value of ENET_PTP_TSL_STMSS bit field

Definition at line 1070 of file gd32f10x_enet.h.

#define GET_PTP_TSL_STS ( regval ) (((regval) & BIT(31)) >> (31U))

get value of ENET_PTP_TSL_STS bit field

Definition at line 1075 of file gd32f10x_enet.h.

#define GET_RDES0_FRML ( regval ) GET_BITS((regval),16,29)

get value of ENET DMA RDES0 FRML bit field

Definition at line 1217 of file gd32f10x_enet.h.

#define GET_RDES1_RB1S ( regval ) GET_BITS((regval),0,12)

get value of ENET DMA RDES1 RB1S bit field

Definition at line 1223 of file gd32f10x_enet.h.

#define GET_RDES1_RB2S ( regval ) GET_BITS((regval),16,28)

get value of ENET DMA RDES1 RB2S bit field

Definition at line 1225 of file gd32f10x_enet.h.

#define GET_RDES4_IPPLDT ( regval ) GET_BITS((regval),0,2)

get value of ENET DMA RDES4 IPPLDT bit field

Definition at line 1229 of file gd32f10x_enet.h.

#define GET_RDES4_PTPMT ( regval ) GET_BITS((regval),8,11)

get value of ENET DMA RDES4 PTPMT bit field

Definition at line 1232 of file gd32f10x_enet.h.

#define GET_TDES0_COCNT ( regval ) GET_BITS((regval),3,6)

get value of ENET DMA TDES0 CONT bit field

Definition at line 1202 of file gd32f10x_enet.h.

#define IF_USE_EXTERNPHY_LIB 0

Definition at line 19 of file gd32f10x_enet.h.

#define LAN8700 1

Definition at line 44 of file gd32f10x_enet.h.

#define MAC_ADDR0H_ADDR0H ( regval ) (BITS(0,15) & ((uint32_t)(regval) << 0))

write value to ENET_MAC_ADDR0H_ADDR0H bit field

Definition at line 1023 of file gd32f10x_enet.h.

#define MAC_ADDR123H_ADDR123H ( regval ) (BITS(0,15) & ((uint32_t)(regval) << 0))

write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field

Definition at line 1026 of file gd32f10x_enet.h.

#define MAC_CFG_BOL ( regval ) (BITS(5,6) & ((uint32_t)(regval) << 5))

write value to ENET_MAC_CFG_BOL bit field

Definition at line 877 of file gd32f10x_enet.h.

#define MAC_CFG_IGBS ( regval ) (BITS(17,19) & ((uint32_t)(regval) << 17))

write value to ENET_MAC_CFG_IGBS bit field

Definition at line 883 of file gd32f10x_enet.h.

#define MAC_CFG_MASK ((uint32_t)0xFD30810FU)

ENET_MAC_CFG register mask

Definition at line 1235 of file gd32f10x_enet.h.

#define MAC_FCTH_RFA ( regval ) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8)

write value to ENET_MAC_FCTH_RFA bit field

Definition at line 1039 of file gd32f10x_enet.h.

#define MAC_FCTH_RFD ( regval ) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8)

write value to ENET_MAC_FCTH_RFD bit field

Definition at line 1048 of file gd32f10x_enet.h.

#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U)

ENET_MAC_FCTL register mask

Definition at line 1236 of file gd32f10x_enet.h.

#define MAC_FCTL_PLTS ( regval ) (BITS(4,5) & ((uint32_t)(regval) << 4))

write value to ENET_MAC_FCTL_PLTS bit field

Definition at line 981 of file gd32f10x_enet.h.

#define MAC_FCTL_PTM ( regval ) (BITS(16,31) & ((uint32_t)(regval) << 16))

write value to ENET_MAC_FCTL_PTM bit field

Definition at line 1006 of file gd32f10x_enet.h.

#define MAC_FCTL_REG_OFFSET 0x0018U

MAC flow control register offset

Definition at line 536 of file gd32f10x_enet.h.

#define MAC_FRMF_PCFRM ( regval ) (BITS(6,7) & ((uint32_t)(regval) << 6))

write value to ENET_MAC_FRMF_PCFRM bit field

Definition at line 928 of file gd32f10x_enet.h.

#define MAC_INTF_REG_OFFSET 0x0038U

MAC interrupt flag register offset

Definition at line 538 of file gd32f10x_enet.h.

#define MAC_INTMSK_REG_OFFSET 0x003CU

MAC interrupt mask register offset

Definition at line 539 of file gd32f10x_enet.h.

#define MAC_PHY_CTL_CLR ( regval ) (BITS(2,4) & ((uint32_t)(regval) << 2))

write value to ENET_MAC_PHY_CTL_CLR bit field

Definition at line 967 of file gd32f10x_enet.h.

#define MAC_PHY_CTL_PA ( regval ) (BITS(11,15) & ((uint32_t)(regval) << 11))

write value to ENET_MAC_PHY_CTL_PA bit field

Definition at line 975 of file gd32f10x_enet.h.

#define MAC_PHY_CTL_PR ( regval ) (BITS(6,10) & ((uint32_t)(regval) << 6))

write value to ENET_MAC_PHY_CTL_PR bit field

Definition at line 973 of file gd32f10x_enet.h.

#define MAC_PHY_DATA_PD ( regval ) (BITS(0,15) & ((uint32_t)(regval) << 0))

write value to ENET_MAC_PHY_DATA_PD bit field

Definition at line 978 of file gd32f10x_enet.h.

#define MAC_VLT_VLTI ( regval ) (BITS(0,15) & ((uint32_t)(regval) << 0))

write value to ENET_MAC_VLT_VLTI bit field

Definition at line 1008 of file gd32f10x_enet.h.

#define MAC_WUM_REG_OFFSET 0x002CU

MAC wakeup management register offset

Definition at line 537 of file gd32f10x_enet.h.

#define MSC_MSCCNT_REG_OFFSET 0x0150U

MSC transmitted good frames after more than a single collision counter register offset

Definition at line 546 of file gd32f10x_enet.h.

#define MSC_RFAECNT_REG_OFFSET 0x0198U

MSC received frames with alignment error counter register offset

Definition at line 549 of file gd32f10x_enet.h.

#define MSC_RFCECNT_REG_OFFSET 0x0194U

MSC received frames with CRC error counter register offset

Definition at line 548 of file gd32f10x_enet.h.

#define MSC_RGUFCNT_REG_OFFSET 0x01C4U

MSC received good unicast frames counter register offset

Definition at line 550 of file gd32f10x_enet.h.

#define MSC_RINTF_REG_OFFSET 0x0104U

MSC receive interrupt flag register offset

Definition at line 541 of file gd32f10x_enet.h.

#define MSC_RINTMSK_REG_OFFSET 0x010CU

MSC receive interrupt mask register offset

Definition at line 543 of file gd32f10x_enet.h.

#define MSC_SCCNT_REG_OFFSET 0x014CU

MSC transmitted good frames after a single collision counter register offset

Definition at line 545 of file gd32f10x_enet.h.

#define MSC_TGFCNT_REG_OFFSET 0x0168U

MSC transmitted good frames counter register offset

Definition at line 547 of file gd32f10x_enet.h.

#define MSC_TINTF_REG_OFFSET 0x0108U

MSC transmit interrupt flag register offset

Definition at line 542 of file gd32f10x_enet.h.

#define MSC_TINTMSK_REG_OFFSET 0x0110U

MSC transmit interrupt mask register offset

Definition at line 544 of file gd32f10x_enet.h.

#define PHY_ADDRESS ((uint16_t)1U)

phy address determined by the hardware

Definition at line 47 of file gd32f10x_enet.h.

#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020)

auto-negotioation process completed

Definition at line 74 of file gd32f10x_enet.h.

#define PHY_AUTONEGOTIATION ((uint16_t)0x1000)

enable auto-negotiation function

Definition at line 68 of file gd32f10x_enet.h.

#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU)

PHY configure delay

Definition at line 55 of file gd32f10x_enet.h.

#define PHY_DUPLEX_STATUS ((uint16_t)0x0004)

configured information of duplex: full-duplex

Definition at line 85 of file gd32f10x_enet.h.

#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100)

configure speed to 100 Mbit/s and the full-duplex mode

Definition at line 64 of file gd32f10x_enet.h.

#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100)

configure speed to 10 Mbit/s and the full-duplex mode

Definition at line 66 of file gd32f10x_enet.h.

#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000)

configure speed to 100 Mbit/s and the half-duplex mode

Definition at line 65 of file gd32f10x_enet.h.

#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000)

configure speed to 10 Mbit/s and the half-duplex mode

Definition at line 67 of file gd32f10x_enet.h.

#define PHY_ISOLATE ((uint16_t)0x0400)

isolate PHY from MII

Definition at line 71 of file gd32f10x_enet.h.

#define PHY_JABBER_DETECTION ((uint16_t)0x0002)

jabber condition detected

Definition at line 76 of file gd32f10x_enet.h.

#define PHY_LINKED_STATUS ((uint16_t)0x0004)

valid link established

Definition at line 75 of file gd32f10x_enet.h.

#define PHY_LOOPBACK ((uint16_t)0x4000)

enable phy loop-back mode

Definition at line 63 of file gd32f10x_enet.h.

#define PHY_POWERDOWN ((uint16_t)0x0800)

enable the power down mode

Definition at line 70 of file gd32f10x_enet.h.

#define PHY_READ_TO ((uint32_t)0x0004FFFFU)

PHY read timeout

Definition at line 50 of file gd32f10x_enet.h.

#define PHY_REG_BCR 0U

tranceiver basic control register

Definition at line 58 of file gd32f10x_enet.h.

#define PHY_REG_BSR 1U

tranceiver basic status register

Definition at line 59 of file gd32f10x_enet.h.

#define PHY_RESET ((uint16_t)0x8000)

PHY reset

Definition at line 62 of file gd32f10x_enet.h.

#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU)

PHY reset delay

Definition at line 54 of file gd32f10x_enet.h.

#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200)

restart auto-negotiation function

Definition at line 69 of file gd32f10x_enet.h.

#define PHY_SPEED_STATUS ((uint16_t)0x0002)

configured information of speed: 10Mbit/s

Definition at line 84 of file gd32f10x_enet.h.

#define PHY_SR 16U

tranceiver status register

Definition at line 83 of file gd32f10x_enet.h.

#define PHY_TYPE DP83848

Definition at line 45 of file gd32f10x_enet.h.

#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU)

PHY write timeout

Definition at line 51 of file gd32f10x_enet.h.

#define PTP_SSINC_STMSSI ( regval ) (BITS(0,7) & ((uint32_t)(regval) << 0))

write value to ENET_PTP_SSINC_STMSSI bit field

Definition at line 1067 of file gd32f10x_enet.h.

#define PTP_TSUL_TMSUSS ( regval ) (BITS(0,30) & ((uint32_t)(regval) << 0))

write value to ENET_PTP_TSUL_TMSUSS bit field

Definition at line 1078 of file gd32f10x_enet.h.

#define RDES0_FRML ( regval ) (BITS(16,29) & ((uint32_t)(regval) << 16))

write value to ENET DMA RDES0 FRML bit field

Definition at line 1216 of file gd32f10x_enet.h.

#define RDES4_IPPLDT ( regval ) (BITS(0,2) & ((uint32_t)(regval) << 0))

write value to ENET DMA RDES4 IPPLDT bit field

Definition at line 1228 of file gd32f10x_enet.h.

#define RDES4_PTPMT ( regval ) (BITS(8,11) & ((uint32_t)(regval) << 8))

write value to ENET DMA RDES4 PTPMT bit field

Definition at line 1231 of file gd32f10x_enet.h.

#define TDES0_CM ( regval ) (BITS(22,23) & ((uint32_t)(regval) << 22))

write value to ENET DMA TDES0 CM bit field

Definition at line 1204 of file gd32f10x_enet.h.

#define TDES0_CONT ( regval ) (BITS(3,6) & ((uint32_t)(regval) << 3))

write value to ENET DMA TDES0 CONT bit field

Definition at line 1201 of file gd32f10x_enet.h.

#define TDES1_TB1S ( regval ) (BITS(0,12) & ((uint32_t)(regval) << 0))

write value to ENET DMA TDES1 TB1S bit field

Definition at line 1211 of file gd32f10x_enet.h.

#define TDES1_TB2S ( regval ) (BITS(16,28) & ((uint32_t)(regval) << 16))

write value to ENET DMA TDES1 TB2S bit field

Definition at line 1213 of file gd32f10x_enet.h.

Enumeration Type Documentation

enum enet_chksumconf_enum
Enumerator
ENET_NO_AUTOCHECKSUM | disable IP frame checksum function
ENET_AUTOCHECKSUM_DROP_FAILFRAMES | enable IP frame checksum function
ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES | enable IP frame checksum function, and the received frame with only payload error but no other errors will not be dropped

Definition at line 772 of file gd32f10x_enet.h.

773 {
774 ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U,
775 ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO,
776 ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD)
778 }enet_chksumconf_enum;
ENET_AUTOCHECKSUM_DROP_FAILFRAMES
Definition: gd32f10x_enet.h:775
ENET_NO_AUTOCHECKSUM
Definition: gd32f10x_enet.h:774
ENET_DMA_CTL_DTCERFD
#define ENET_DMA_CTL_DTCERFD
Definition: gd32f10x_enet.h:411
ENET_MAC_CFG_IPFCO
#define ENET_MAC_CFG_IPFCO
Definition: gd32f10x_enet.h:161
ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES
Definition: gd32f10x_enet.h:776
enet_chksumconf_enum
enet_chksumconf_enum
Definition: gd32f10x_enet.h:772
enum enet_desc_reg_enum
Enumerator
ENET_RX_DESC_TABLE | RX descriptor table
ENET_RX_CURRENT_DESC | current RX descriptor
ENET_RX_CURRENT_BUFFER | current RX buffer
ENET_TX_DESC_TABLE | TX descriptor table
ENET_TX_CURRENT_DESC | current TX descriptor
ENET_TX_CURRENT_BUFFER | current TX buffer

Definition at line 720 of file gd32f10x_enet.h.

721 {
722 ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET,
723 ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET,
724 ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET,
725 ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET,
726 ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET,
727 ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET
728 }enet_desc_reg_enum;
ENET_RX_CURRENT_DESC
Definition: gd32f10x_enet.h:723
ENET_RX_CURRENT_BUFFER
Definition: gd32f10x_enet.h:724
DMA_CRBADDR_REG_OFFSET
#define DMA_CRBADDR_REG_OFFSET
Definition: gd32f10x_enet.h:559
DMA_CRDADDR_REG_OFFSET
#define DMA_CRDADDR_REG_OFFSET
Definition: gd32f10x_enet.h:558
enet_desc_reg_enum
enet_desc_reg_enum
Definition: gd32f10x_enet.h:720
DMA_RDTADDR_REG_OFFSET
#define DMA_RDTADDR_REG_OFFSET
Definition: gd32f10x_enet.h:557
ENET_TX_CURRENT_DESC
Definition: gd32f10x_enet.h:726
ENET_TX_DESC_TABLE
Definition: gd32f10x_enet.h:725
DMA_TDTADDR_REG_OFFSET
#define DMA_TDTADDR_REG_OFFSET
Definition: gd32f10x_enet.h:554
ENET_TX_CURRENT_BUFFER
Definition: gd32f10x_enet.h:727
DMA_CTDADDR_REG_OFFSET
#define DMA_CTDADDR_REG_OFFSET
Definition: gd32f10x_enet.h:555
ENET_RX_DESC_TABLE
Definition: gd32f10x_enet.h:722
DMA_CTBADDR_REG_OFFSET
#define DMA_CTBADDR_REG_OFFSET
Definition: gd32f10x_enet.h:556
enum enet_descstate_enum
Enumerator
TXDESC_COLLISION_COUNT | the number of collisions occurred before the frame was transmitted
TXDESC_BUFFER_1_ADDR | transmit frame buffer 1 address
RXDESC_FRAME_LENGTH | the byte length of the received frame that was transferred to the buffer
RXDESC_BUFFER_1_SIZE | receive buffer 1 size
RXDESC_BUFFER_2_SIZE | receive buffer 2 size
RXDESC_BUFFER_1_ADDR | receive frame buffer 1 address

Definition at line 829 of file gd32f10x_enet.h.

830 {
831 TXDESC_COLLISION_COUNT,
832 TXDESC_BUFFER_1_ADDR,
833 RXDESC_FRAME_LENGTH,
834 RXDESC_BUFFER_1_SIZE,
835 RXDESC_BUFFER_2_SIZE,
836 RXDESC_BUFFER_1_ADDR
837 }enet_descstate_enum;
RXDESC_FRAME_LENGTH
Definition: gd32f10x_enet.h:833
TXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:832
TXDESC_COLLISION_COUNT
Definition: gd32f10x_enet.h:831
RXDESC_BUFFER_1_SIZE
Definition: gd32f10x_enet.h:834
RXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:836
enet_descstate_enum
enet_descstate_enum
Definition: gd32f10x_enet.h:829
RXDESC_BUFFER_2_SIZE
Definition: gd32f10x_enet.h:835
enum enet_dmadirection_enum
Enumerator
ENET_DMA_TX | DMA transmit direction
ENET_DMA_RX | DMA receive direction

Definition at line 799 of file gd32f10x_enet.h.

800 {
801 ENET_DMA_TX = ENET_DMA_STAT_TP,
802 ENET_DMA_RX = ENET_DMA_STAT_RP
803 }enet_dmadirection_enum;
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
ENET_DMA_STAT_RP
#define ENET_DMA_STAT_RP
Definition: gd32f10x_enet.h:392
enet_dmadirection_enum
enet_dmadirection_enum
Definition: gd32f10x_enet.h:799
ENET_DMA_RX
Definition: gd32f10x_enet.h:802
ENET_DMA_STAT_TP
#define ENET_DMA_STAT_TP
Definition: gd32f10x_enet.h:393
enum enet_flag_clear_enum
Enumerator
ENET_DMA_FLAG_TS_CLR | transmit status flag
ENET_DMA_FLAG_TPS_CLR | transmit process stopped status flag
ENET_DMA_FLAG_TBU_CLR | transmit buffer unavailable status flag
ENET_DMA_FLAG_TJT_CLR | transmit jabber timeout status flag
ENET_DMA_FLAG_RO_CLR | receive overflow status flag
ENET_DMA_FLAG_TU_CLR | transmit underflow status flag
ENET_DMA_FLAG_RS_CLR | receive status flag
ENET_DMA_FLAG_RBU_CLR | receive buffer unavailable status flag
ENET_DMA_FLAG_RPS_CLR | receive process stopped status flag
ENET_DMA_FLAG_RWT_CLR | receive watchdog timeout status flag
ENET_DMA_FLAG_ET_CLR | early transmit status flag
ENET_DMA_FLAG_FBE_CLR | fatal bus error status flag
ENET_DMA_FLAG_ER_CLR | early receive status flag
ENET_DMA_FLAG_AI_CLR | abnormal interrupt summary flag
ENET_DMA_FLAG_NI_CLR | normal interrupt summary flag

Definition at line 608 of file gd32f10x_enet.h.

609 {
610 /* ENET_DMA_STAT register */
611 ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
612 ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
613 ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
614 ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
615 ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
616 ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
617 ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
618 ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
619 ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
620 ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
621 ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
622 ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
623 ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
624 ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
625 ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
626 }enet_flag_clear_enum;
ENET_DMA_FLAG_TPS_CLR
Definition: gd32f10x_enet.h:612
ENET_DMA_FLAG_RWT_CLR
Definition: gd32f10x_enet.h:620
ENET_DMA_FLAG_AI_CLR
Definition: gd32f10x_enet.h:624
ENET_DMA_FLAG_RS_CLR
Definition: gd32f10x_enet.h:617
ENET_DMA_FLAG_TBU_CLR
Definition: gd32f10x_enet.h:613
enet_flag_clear_enum
enet_flag_clear_enum
Definition: gd32f10x_enet.h:608
ENET_DMA_FLAG_RO_CLR
Definition: gd32f10x_enet.h:615
ENET_REGIDX_BIT
#define ENET_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_enet.h:521
ENET_DMA_FLAG_ER_CLR
Definition: gd32f10x_enet.h:623
ENET_DMA_FLAG_ET_CLR
Definition: gd32f10x_enet.h:621
ENET_DMA_FLAG_NI_CLR
Definition: gd32f10x_enet.h:625
ENET_DMA_FLAG_RBU_CLR
Definition: gd32f10x_enet.h:618
ENET_DMA_FLAG_TJT_CLR
Definition: gd32f10x_enet.h:614
DMA_STAT_REG_OFFSET
#define DMA_STAT_REG_OFFSET
Definition: gd32f10x_enet.h:552
ENET_DMA_FLAG_RPS_CLR
Definition: gd32f10x_enet.h:619
ENET_DMA_FLAG_TS_CLR
Definition: gd32f10x_enet.h:611
ENET_DMA_FLAG_FBE_CLR
Definition: gd32f10x_enet.h:622
ENET_DMA_FLAG_TU_CLR
Definition: gd32f10x_enet.h:616
enum enet_flag_enum
Enumerator
ENET_MAC_FLAG_MPKR | magic packet received flag
ENET_MAC_FLAG_WUFR | wakeup frame received flag
ENET_MAC_FLAG_FLOWCONTROL | flow control status flag
ENET_MAC_FLAG_WUM | WUM status flag
ENET_MAC_FLAG_MSC | MSC status flag
ENET_MAC_FLAG_MSCR | MSC receive status flag
ENET_MAC_FLAG_MSCT | MSC transmit status flag
ENET_MAC_FLAG_TMST | timestamp trigger status flag
ENET_MSC_FLAG_RFCE | received frames CRC error flag
ENET_MSC_FLAG_RFAE | received frames alignment error flag
ENET_MSC_FLAG_RGUF | received good unicast frames flag
ENET_MSC_FLAG_TGFSC | transmitted good frames single collision flag
ENET_MSC_FLAG_TGFMSC | transmitted good frames more single collision flag
ENET_MSC_FLAG_TGF | transmitted good frames flag
ENET_DMA_FLAG_TS | transmit status flag
ENET_DMA_FLAG_TPS | transmit process stopped status flag
ENET_DMA_FLAG_TBU | transmit buffer unavailable status flag
ENET_DMA_FLAG_TJT | transmit jabber timeout status flag
ENET_DMA_FLAG_RO | receive overflow status flag
ENET_DMA_FLAG_TU | transmit underflow status flag
ENET_DMA_FLAG_RS | receive status flag
ENET_DMA_FLAG_RBU | receive buffer unavailable status flag
ENET_DMA_FLAG_RPS | receive process stopped status flag
ENET_DMA_FLAG_RWT | receive watchdog timeout status flag
ENET_DMA_FLAG_ET | early transmit status flag
ENET_DMA_FLAG_FBE | fatal bus error status flag
ENET_DMA_FLAG_ER | early receive status flag
ENET_DMA_FLAG_AI | abnormal interrupt summary flag
ENET_DMA_FLAG_NI | normal interrupt summary flag
ENET_DMA_FLAG_EB_DMA_ERROR | error during data transfer by RxDMA/TxDMA flag
ENET_DMA_FLAG_EB_TRANSFER_ERROR | error during write/read transfer flag
ENET_DMA_FLAG_EB_ACCESS_ERROR | error during data buffer/descriptor access flag
ENET_DMA_FLAG_MSC | MSC status flag
ENET_DMA_FLAG_WUM | WUM status flag
ENET_DMA_FLAG_TST | timestamp trigger status flag

Definition at line 562 of file gd32f10x_enet.h.

563 {
564 /* ENET_MAC_WUM register */
565 ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U),
566 ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U),
567 /* ENET_MAC_FCTL register */
568 ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U),
569 /* ENET_MAC_INTF register */
570 ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U),
571 ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U),
572 ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U),
573 ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U),
574 ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U),
575 /* ENET_MSC_RINTF register */
576 ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U),
577 ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U),
578 ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U),
579 /* ENET_MSC_TINTF register */
580 ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U),
581 ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U),
582 ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U),
583 /* ENET_DMA_STAT register */
584 ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
585 ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
586 ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
587 ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
588 ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
589 ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
590 ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
591 ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
592 ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
593 ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
594 ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
595 ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
596 ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
597 ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
598 ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
599 ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U),
600 ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U),
601 ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U),
602 ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U),
603 ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U),
604 ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U),
605 }enet_flag_enum;
ENET_MSC_FLAG_RFCE
Definition: gd32f10x_enet.h:576
ENET_DMA_FLAG_RS
Definition: gd32f10x_enet.h:590
ENET_DMA_FLAG_TS
Definition: gd32f10x_enet.h:584
ENET_DMA_FLAG_TST
Definition: gd32f10x_enet.h:604
ENET_MSC_FLAG_TGFMSC
Definition: gd32f10x_enet.h:581
ENET_MAC_FLAG_MSCR
Definition: gd32f10x_enet.h:572
ENET_DMA_FLAG_RPS
Definition: gd32f10x_enet.h:592
ENET_DMA_FLAG_TPS
Definition: gd32f10x_enet.h:585
ENET_MSC_FLAG_RFAE
Definition: gd32f10x_enet.h:577
ENET_MAC_FLAG_TMST
Definition: gd32f10x_enet.h:574
ENET_MSC_FLAG_TGF
Definition: gd32f10x_enet.h:582
ENET_MAC_FLAG_MPKR
Definition: gd32f10x_enet.h:565
ENET_MAC_FLAG_WUFR
Definition: gd32f10x_enet.h:566
ENET_DMA_FLAG_EB_TRANSFER_ERROR
Definition: gd32f10x_enet.h:600
ENET_DMA_FLAG_TBU
Definition: gd32f10x_enet.h:586
MAC_INTF_REG_OFFSET
#define MAC_INTF_REG_OFFSET
Definition: gd32f10x_enet.h:538
ENET_DMA_FLAG_EB_ACCESS_ERROR
Definition: gd32f10x_enet.h:601
ENET_DMA_FLAG_RO
Definition: gd32f10x_enet.h:588
enet_flag_enum
enet_flag_enum
Definition: gd32f10x_enet.h:562
ENET_MAC_FLAG_MSCT
Definition: gd32f10x_enet.h:573
MSC_RINTF_REG_OFFSET
#define MSC_RINTF_REG_OFFSET
Definition: gd32f10x_enet.h:541
ENET_REGIDX_BIT
#define ENET_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_enet.h:521
ENET_MSC_FLAG_RGUF
Definition: gd32f10x_enet.h:578
ENET_DMA_FLAG_RBU
Definition: gd32f10x_enet.h:591
ENET_DMA_FLAG_FBE
Definition: gd32f10x_enet.h:595
ENET_DMA_FLAG_ER
Definition: gd32f10x_enet.h:596
ENET_DMA_FLAG_NI
Definition: gd32f10x_enet.h:598
ENET_DMA_FLAG_WUM
Definition: gd32f10x_enet.h:603
ENET_MAC_FLAG_MSC
Definition: gd32f10x_enet.h:571
ENET_MAC_FLAG_WUM
Definition: gd32f10x_enet.h:570
MAC_WUM_REG_OFFSET
#define MAC_WUM_REG_OFFSET
Definition: gd32f10x_enet.h:537
DMA_STAT_REG_OFFSET
#define DMA_STAT_REG_OFFSET
Definition: gd32f10x_enet.h:552
MAC_FCTL_REG_OFFSET
#define MAC_FCTL_REG_OFFSET
Definition: gd32f10x_enet.h:536
ENET_DMA_FLAG_ET
Definition: gd32f10x_enet.h:594
ENET_MAC_FLAG_FLOWCONTROL
Definition: gd32f10x_enet.h:568
ENET_DMA_FLAG_AI
Definition: gd32f10x_enet.h:597
ENET_DMA_FLAG_EB_DMA_ERROR
Definition: gd32f10x_enet.h:599
ENET_DMA_FLAG_TJT
Definition: gd32f10x_enet.h:587
ENET_DMA_FLAG_RWT
Definition: gd32f10x_enet.h:593
ENET_DMA_FLAG_MSC
Definition: gd32f10x_enet.h:602
ENET_MSC_FLAG_TGFSC
Definition: gd32f10x_enet.h:580
MSC_TINTF_REG_OFFSET
#define MSC_TINTF_REG_OFFSET
Definition: gd32f10x_enet.h:542
ENET_DMA_FLAG_TU
Definition: gd32f10x_enet.h:589
enum enet_frmrecept_enum
Enumerator
ENET_PROMISCUOUS_MODE | promiscuous mode enabled
ENET_RECEIVEALL | all received frame are forwarded to application
ENET_BROADCAST_FRAMES_PASS | the address filters pass all received broadcast frames
ENET_BROADCAST_FRAMES_DROP | the address filters filter all incoming broadcast frames

Definition at line 781 of file gd32f10x_enet.h.

782 {
783 ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM,
784 ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR,
785 ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U,
786 ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD
787 }enet_frmrecept_enum;
ENET_BROADCAST_FRAMES_DROP
Definition: gd32f10x_enet.h:786
ENET_RECEIVEALL
Definition: gd32f10x_enet.h:784
ENET_MAC_FRMF_BFRMD
#define ENET_MAC_FRMF_BFRMD
Definition: gd32f10x_enet.h:177
enet_frmrecept_enum
enet_frmrecept_enum
Definition: gd32f10x_enet.h:781
ENET_MAC_FRMF_FAR
#define ENET_MAC_FRMF_FAR
Definition: gd32f10x_enet.h:182
ENET_BROADCAST_FRAMES_PASS
Definition: gd32f10x_enet.h:785
ENET_PROMISCUOUS_MODE
Definition: gd32f10x_enet.h:783
ENET_MAC_FRMF_PM
#define ENET_MAC_FRMF_PM
Definition: gd32f10x_enet.h:172
enum enet_int_enum
Enumerator
ENET_MAC_INT_WUMIM | WUM interrupt mask
ENET_MAC_INT_TMSTIM | timestamp trigger interrupt mask
ENET_MSC_INT_RFCEIM | received frame CRC error interrupt mask
ENET_MSC_INT_RFAEIM | received frames alignment error interrupt mask
ENET_MSC_INT_RGUFIM | received good unicast frames interrupt mask
ENET_MSC_INT_TGFSCIM | transmitted good frames single collision interrupt mask
ENET_MSC_INT_TGFMSCIM | transmitted good frames more single collision interrupt mask
ENET_MSC_INT_TGFIM | transmitted good frames interrupt mask
ENET_DMA_INT_TIE | transmit interrupt enable
ENET_DMA_INT_TPSIE | transmit process stopped interrupt enable
ENET_DMA_INT_TBUIE | transmit buffer unavailable interrupt enable
ENET_DMA_INT_TJTIE | transmit jabber timeout interrupt enable
ENET_DMA_INT_ROIE | receive overflow interrupt enable
ENET_DMA_INT_TUIE | transmit underflow interrupt enable
ENET_DMA_INT_RIE | receive interrupt enable
ENET_DMA_INT_RBUIE | receive buffer unavailable interrupt enable
ENET_DMA_INT_RPSIE | receive process stopped interrupt enable
ENET_DMA_INT_RWTIE | receive watchdog timeout interrupt enable
ENET_DMA_INT_ETIE | early transmit interrupt enable
ENET_DMA_INT_FBEIE | fatal bus error interrupt enable
ENET_DMA_INT_ERIE | early receive interrupt enable
ENET_DMA_INT_AIE | abnormal interrupt summary enable
ENET_DMA_INT_NIE | normal interrupt summary enable

Definition at line 629 of file gd32f10x_enet.h.

630 {
631 /* ENET_MAC_INTMSK register */
632 ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U),
633 ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U),
634 /* ENET_MSC_RINTMSK register */
635 ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U),
636 ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U),
637 ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U),
638 /* ENET_MSC_TINTMSK register */
639 ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U),
640 ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U),
641 ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U),
642 /* ENET_DMA_INTEN register */
643 ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U),
644 ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U),
645 ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U),
646 ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U),
647 ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U),
648 ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U),
649 ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U),
650 ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U),
651 ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U),
652 ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U),
653 ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U),
654 ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U),
655 ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U),
656 ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U),
657 ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U),
658 }enet_int_enum;
ENET_MSC_INT_TGFMSCIM
Definition: gd32f10x_enet.h:640
ENET_DMA_INT_TBUIE
Definition: gd32f10x_enet.h:645
ENET_DMA_INT_RWTIE
Definition: gd32f10x_enet.h:652
MSC_TINTMSK_REG_OFFSET
#define MSC_TINTMSK_REG_OFFSET
Definition: gd32f10x_enet.h:544
DMA_INTEN_REG_OFFSET
#define DMA_INTEN_REG_OFFSET
Definition: gd32f10x_enet.h:553
ENET_MSC_INT_RFCEIM
Definition: gd32f10x_enet.h:635
ENET_DMA_INT_TPSIE
Definition: gd32f10x_enet.h:644
enet_int_enum
enet_int_enum
Definition: gd32f10x_enet.h:629
ENET_DMA_INT_TIE
Definition: gd32f10x_enet.h:643
ENET_DMA_INT_NIE
Definition: gd32f10x_enet.h:657
ENET_DMA_INT_ETIE
Definition: gd32f10x_enet.h:653
ENET_DMA_INT_RBUIE
Definition: gd32f10x_enet.h:650
ENET_MSC_INT_TGFSCIM
Definition: gd32f10x_enet.h:639
ENET_REGIDX_BIT
#define ENET_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_enet.h:521
MAC_INTMSK_REG_OFFSET
#define MAC_INTMSK_REG_OFFSET
Definition: gd32f10x_enet.h:539
ENET_MAC_INT_TMSTIM
Definition: gd32f10x_enet.h:633
MSC_RINTMSK_REG_OFFSET
#define MSC_RINTMSK_REG_OFFSET
Definition: gd32f10x_enet.h:543
ENET_MSC_INT_RFAEIM
Definition: gd32f10x_enet.h:636
ENET_DMA_INT_RPSIE
Definition: gd32f10x_enet.h:651
ENET_DMA_INT_TJTIE
Definition: gd32f10x_enet.h:646
ENET_DMA_INT_RIE
Definition: gd32f10x_enet.h:649
ENET_DMA_INT_TUIE
Definition: gd32f10x_enet.h:648
ENET_DMA_INT_FBEIE
Definition: gd32f10x_enet.h:654
ENET_MSC_INT_TGFIM
Definition: gd32f10x_enet.h:641
ENET_MSC_INT_RGUFIM
Definition: gd32f10x_enet.h:637
ENET_DMA_INT_ERIE
Definition: gd32f10x_enet.h:655
ENET_MAC_INT_WUMIM
Definition: gd32f10x_enet.h:632
ENET_DMA_INT_AIE
Definition: gd32f10x_enet.h:656
ENET_DMA_INT_ROIE
Definition: gd32f10x_enet.h:647
enum enet_int_flag_clear_enum
Enumerator
ENET_DMA_INT_FLAG_TS_CLR | transmit status flag
ENET_DMA_INT_FLAG_TPS_CLR | transmit process stopped status flag
ENET_DMA_INT_FLAG_TBU_CLR | transmit buffer unavailable status flag
ENET_DMA_INT_FLAG_TJT_CLR | transmit jabber timeout status flag
ENET_DMA_INT_FLAG_RO_CLR | receive overflow status flag
ENET_DMA_INT_FLAG_TU_CLR | transmit underflow status flag
ENET_DMA_INT_FLAG_RS_CLR | receive status flag
ENET_DMA_INT_FLAG_RBU_CLR | receive buffer unavailable status flag
ENET_DMA_INT_FLAG_RPS_CLR | receive process stopped status flag
ENET_DMA_INT_FLAG_RWT_CLR | receive watchdog timeout status flag
ENET_DMA_INT_FLAG_ET_CLR | early transmit status flag
ENET_DMA_INT_FLAG_FBE_CLR | fatal bus error status flag
ENET_DMA_INT_FLAG_ER_CLR | early receive status flag
ENET_DMA_INT_FLAG_AI_CLR | abnormal interrupt summary flag
ENET_DMA_INT_FLAG_NI_CLR | normal interrupt summary flag

Definition at line 699 of file gd32f10x_enet.h.

700 {
701 /* ENET_DMA_STAT register */
702 ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
703 ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
704 ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
705 ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
706 ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
707 ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
708 ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
709 ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
710 ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
711 ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
712 ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
713 ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
714 ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
715 ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
716 ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
717 }enet_int_flag_clear_enum;
ENET_DMA_INT_FLAG_TJT_CLR
Definition: gd32f10x_enet.h:705
ENET_DMA_INT_FLAG_ET_CLR
Definition: gd32f10x_enet.h:712
ENET_DMA_INT_FLAG_RBU_CLR
Definition: gd32f10x_enet.h:709
ENET_DMA_INT_FLAG_RWT_CLR
Definition: gd32f10x_enet.h:711
ENET_DMA_INT_FLAG_TBU_CLR
Definition: gd32f10x_enet.h:704
ENET_DMA_INT_FLAG_TPS_CLR
Definition: gd32f10x_enet.h:703
ENET_DMA_INT_FLAG_AI_CLR
Definition: gd32f10x_enet.h:715
ENET_DMA_INT_FLAG_ER_CLR
Definition: gd32f10x_enet.h:714
ENET_REGIDX_BIT
#define ENET_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_enet.h:521
ENET_DMA_INT_FLAG_RS_CLR
Definition: gd32f10x_enet.h:708
ENET_DMA_INT_FLAG_TU_CLR
Definition: gd32f10x_enet.h:707
DMA_STAT_REG_OFFSET
#define DMA_STAT_REG_OFFSET
Definition: gd32f10x_enet.h:552
ENET_DMA_INT_FLAG_NI_CLR
Definition: gd32f10x_enet.h:716
ENET_DMA_INT_FLAG_RPS_CLR
Definition: gd32f10x_enet.h:710
ENET_DMA_INT_FLAG_RO_CLR
Definition: gd32f10x_enet.h:706
enet_int_flag_clear_enum
enet_int_flag_clear_enum
Definition: gd32f10x_enet.h:699
ENET_DMA_INT_FLAG_FBE_CLR
Definition: gd32f10x_enet.h:713
ENET_DMA_INT_FLAG_TS_CLR
Definition: gd32f10x_enet.h:702
enum enet_int_flag_enum
Enumerator
ENET_MAC_INT_FLAG_WUM | WUM status flag
ENET_MAC_INT_FLAG_MSC | MSC status flag
ENET_MAC_INT_FLAG_MSCR | MSC receive status flag
ENET_MAC_INT_FLAG_MSCT | MSC transmit status flag
ENET_MAC_INT_FLAG_TMST | timestamp trigger status flag
ENET_MSC_INT_FLAG_RFCE | received frames CRC error flag
ENET_MSC_INT_FLAG_RFAE | received frames alignment error flag
ENET_MSC_INT_FLAG_RGUF | received good unicast frames flag
ENET_MSC_INT_FLAG_TGFSC | transmitted good frames single collision flag
ENET_MSC_INT_FLAG_TGFMSC | transmitted good frames more single collision flag
ENET_MSC_INT_FLAG_TGF | transmitted good frames flag
ENET_DMA_INT_FLAG_TS | transmit status flag
ENET_DMA_INT_FLAG_TPS | transmit process stopped status flag
ENET_DMA_INT_FLAG_TBU | transmit buffer unavailable status flag
ENET_DMA_INT_FLAG_TJT | transmit jabber timeout status flag
ENET_DMA_INT_FLAG_RO | receive overflow status flag
ENET_DMA_INT_FLAG_TU | transmit underflow status flag
ENET_DMA_INT_FLAG_RS | receive status flag
ENET_DMA_INT_FLAG_RBU | receive buffer unavailable status flag
ENET_DMA_INT_FLAG_RPS | receive process stopped status flag
ENET_DMA_INT_FLAG_RWT | receive watchdog timeout status flag
ENET_DMA_INT_FLAG_ET | early transmit status flag
ENET_DMA_INT_FLAG_FBE | fatal bus error status flag
ENET_DMA_INT_FLAG_ER | early receive status flag
ENET_DMA_INT_FLAG_AI | abnormal interrupt summary flag
ENET_DMA_INT_FLAG_NI | normal interrupt summary flag
ENET_DMA_INT_FLAG_MSC | MSC status flag
ENET_DMA_INT_FLAG_WUM | WUM status flag
ENET_DMA_INT_FLAG_TST | timestamp trigger status flag

Definition at line 661 of file gd32f10x_enet.h.

662 {
663 /* ENET_MAC_INTF register */
664 ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U),
665 ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U),
666 ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U),
667 ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U),
668 ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U),
669 /* ENET_MSC_RINTF register */
670 ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U),
671 ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U),
672 ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U),
673 /* ENET_MSC_TINTF register */
674 ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U),
675 ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U),
676 ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U),
677 /* ENET_DMA_STAT register */
678 ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
679 ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
680 ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
681 ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
682 ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
683 ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
684 ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
685 ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
686 ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
687 ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
688 ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
689 ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
690 ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
691 ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
692 ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
693 ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U),
694 ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U),
695 ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U),
696 }enet_int_flag_enum;
ENET_MSC_INT_FLAG_TGFMSC
Definition: gd32f10x_enet.h:675
ENET_DMA_INT_FLAG_NI
Definition: gd32f10x_enet.h:692
ENET_MAC_INT_FLAG_MSCT
Definition: gd32f10x_enet.h:667
ENET_MSC_INT_FLAG_TGF
Definition: gd32f10x_enet.h:676
ENET_MSC_INT_FLAG_RFCE
Definition: gd32f10x_enet.h:670
ENET_DMA_INT_FLAG_TST
Definition: gd32f10x_enet.h:695
ENET_MSC_INT_FLAG_RFAE
Definition: gd32f10x_enet.h:671
ENET_DMA_INT_FLAG_FBE
Definition: gd32f10x_enet.h:689
ENET_MAC_INT_FLAG_MSC
Definition: gd32f10x_enet.h:665
ENET_DMA_INT_FLAG_TPS
Definition: gd32f10x_enet.h:679
ENET_DMA_INT_FLAG_TU
Definition: gd32f10x_enet.h:683
ENET_MAC_INT_FLAG_WUM
Definition: gd32f10x_enet.h:664
MAC_INTF_REG_OFFSET
#define MAC_INTF_REG_OFFSET
Definition: gd32f10x_enet.h:538
ENET_DMA_INT_FLAG_MSC
Definition: gd32f10x_enet.h:693
MSC_RINTF_REG_OFFSET
#define MSC_RINTF_REG_OFFSET
Definition: gd32f10x_enet.h:541
ENET_REGIDX_BIT
#define ENET_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_enet.h:521
ENET_MAC_INT_FLAG_MSCR
Definition: gd32f10x_enet.h:666
ENET_MSC_INT_FLAG_RGUF
Definition: gd32f10x_enet.h:672
ENET_DMA_INT_FLAG_WUM
Definition: gd32f10x_enet.h:694
ENET_DMA_INT_FLAG_ER
Definition: gd32f10x_enet.h:690
ENET_MAC_INT_FLAG_TMST
Definition: gd32f10x_enet.h:668
DMA_STAT_REG_OFFSET
#define DMA_STAT_REG_OFFSET
Definition: gd32f10x_enet.h:552
ENET_DMA_INT_FLAG_RWT
Definition: gd32f10x_enet.h:687
ENET_DMA_INT_FLAG_AI
Definition: gd32f10x_enet.h:691
ENET_DMA_INT_FLAG_RBU
Definition: gd32f10x_enet.h:685
ENET_MSC_INT_FLAG_TGFSC
Definition: gd32f10x_enet.h:674
ENET_DMA_INT_FLAG_RPS
Definition: gd32f10x_enet.h:686
enet_int_flag_enum
enet_int_flag_enum
Definition: gd32f10x_enet.h:661
ENET_DMA_INT_FLAG_ET
Definition: gd32f10x_enet.h:688
ENET_DMA_INT_FLAG_TJT
Definition: gd32f10x_enet.h:681
ENET_DMA_INT_FLAG_RS
Definition: gd32f10x_enet.h:684
ENET_DMA_INT_FLAG_TS
Definition: gd32f10x_enet.h:678
ENET_DMA_INT_FLAG_RO
Definition: gd32f10x_enet.h:682
MSC_TINTF_REG_OFFSET
#define MSC_TINTF_REG_OFFSET
Definition: gd32f10x_enet.h:542
ENET_DMA_INT_FLAG_TBU
Definition: gd32f10x_enet.h:680
enum enet_macaddress_enum
Enumerator
ENET_MAC_ADDRESS0 | MAC address0
ENET_MAC_ADDRESS1 | MAC address1
ENET_MAC_ADDRESS2 | MAC address2
ENET_MAC_ADDRESS3 | MAC address3

Definition at line 820 of file gd32f10x_enet.h.

821 {
822 ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000),
823 ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008),
824 ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010),
825 ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018)
826 }enet_macaddress_enum;
ENET_MAC_ADDRESS0
Definition: gd32f10x_enet.h:822
ENET_MAC_ADDRESS2
Definition: gd32f10x_enet.h:824
enet_macaddress_enum
enet_macaddress_enum
Definition: gd32f10x_enet.h:820
ENET_MAC_ADDRESS1
Definition: gd32f10x_enet.h:823
ENET_MAC_ADDRESS3
Definition: gd32f10x_enet.h:825
enum enet_mediamode_enum
Enumerator
ENET_AUTO_NEGOTIATION | PHY auto negotiation
ENET_100M_FULLDUPLEX | 100Mbit/s, full-duplex
ENET_100M_HALFDUPLEX | 100Mbit/s, half-duplex
ENET_10M_FULLDUPLEX | 10Mbit/s, full-duplex
ENET_10M_HALFDUPLEX | 10Mbit/s, half-duplex
ENET_LOOPBACKMODE | MAC in loopback mode at the MII

Definition at line 761 of file gd32f10x_enet.h.

762 {
763 ENET_AUTO_NEGOTIATION = 0x01u,
764 ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM),
765 ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD ,
766 ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM,
767 ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U,
768 ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM)
769 }enet_mediamode_enum;
ENET_MAC_CFG_DPM
#define ENET_MAC_CFG_DPM
Definition: gd32f10x_enet.h:162
ENET_LOOPBACKMODE
Definition: gd32f10x_enet.h:768
ENET_100M_HALFDUPLEX
Definition: gd32f10x_enet.h:765
ENET_AUTO_NEGOTIATION
Definition: gd32f10x_enet.h:763
ENET_10M_HALFDUPLEX
Definition: gd32f10x_enet.h:767
ENET_MAC_CFG_SPD
#define ENET_MAC_CFG_SPD
Definition: gd32f10x_enet.h:165
ENET_100M_FULLDUPLEX
Definition: gd32f10x_enet.h:764
ENET_10M_FULLDUPLEX
Definition: gd32f10x_enet.h:766
enet_mediamode_enum
enet_mediamode_enum
Definition: gd32f10x_enet.h:761
ENET_MAC_CFG_LBM
#define ENET_MAC_CFG_LBM
Definition: gd32f10x_enet.h:163
enum enet_msc_counter_enum
Enumerator
ENET_MSC_TX_SCCNT | MSC transmitted good frames after a single collision counter
ENET_MSC_TX_MSCCNT | MSC transmitted good frames after more than a single collision counter
ENET_MSC_TX_TGFCNT | MSC transmitted good frames counter
ENET_MSC_RX_RFCECNT | MSC received frames with CRC error counter
ENET_MSC_RX_RFAECNT | MSC received frames with alignment error counter
ENET_MSC_RX_RGUFCNT | MSC received good unicast frames counter

Definition at line 731 of file gd32f10x_enet.h.

732 {
733 ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET,
734 ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET,
735 ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET,
736 ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET,
737 ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET,
738 ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET
739 }enet_msc_counter_enum;
ENET_MSC_TX_TGFCNT
Definition: gd32f10x_enet.h:735
enet_msc_counter_enum
enet_msc_counter_enum
Definition: gd32f10x_enet.h:731
ENET_MSC_RX_RFCECNT
Definition: gd32f10x_enet.h:736
ENET_MSC_TX_SCCNT
Definition: gd32f10x_enet.h:733
MSC_TGFCNT_REG_OFFSET
#define MSC_TGFCNT_REG_OFFSET
Definition: gd32f10x_enet.h:547
MSC_RFAECNT_REG_OFFSET
#define MSC_RFAECNT_REG_OFFSET
Definition: gd32f10x_enet.h:549
ENET_MSC_TX_MSCCNT
Definition: gd32f10x_enet.h:734
ENET_MSC_RX_RFAECNT
Definition: gd32f10x_enet.h:737
MSC_MSCCNT_REG_OFFSET
#define MSC_MSCCNT_REG_OFFSET
Definition: gd32f10x_enet.h:546
MSC_RFCECNT_REG_OFFSET
#define MSC_RFCECNT_REG_OFFSET
Definition: gd32f10x_enet.h:548
MSC_SCCNT_REG_OFFSET
#define MSC_SCCNT_REG_OFFSET
Definition: gd32f10x_enet.h:545
ENET_MSC_RX_RGUFCNT
Definition: gd32f10x_enet.h:738
MSC_RGUFCNT_REG_OFFSET
#define MSC_RGUFCNT_REG_OFFSET
Definition: gd32f10x_enet.h:550
enum enet_option_enum
Enumerator
FORWARD_OPTION | configure the frame forward related parameters
DMABUS_OPTION | configure the DMA bus mode related parameters
DMA_MAXBURST_OPTION | configure the DMA max burst related parameters
DMA_ARBITRATION_OPTION | configure the DMA arbitration related parameters
STORE_OPTION | configure the store forward mode related parameters
DMA_OPTION | configure the DMA control related parameters
VLAN_OPTION | configure the VLAN tag related parameters
FLOWCTL_OPTION | configure the flow control related parameters
HASHH_OPTION | configure the hash list high 32-bit related parameters
HASHL_OPTION | configure the hash list low 32-bit related parameters
FILTER_OPTION | configure the frame filter control related parameters
HALFDUPLEX_OPTION | configure the halfduplex related parameters
TIMER_OPTION | configure the frame timer related parameters
INTERFRAMEGAP_OPTION | configure the inter frame gap related parameters

Definition at line 742 of file gd32f10x_enet.h.

743 {
744 FORWARD_OPTION = BIT(0),
745 DMABUS_OPTION = BIT(1),
746 DMA_MAXBURST_OPTION = BIT(2),
747 DMA_ARBITRATION_OPTION = BIT(3),
748 STORE_OPTION = BIT(4),
749 DMA_OPTION = BIT(5),
750 VLAN_OPTION = BIT(6),
751 FLOWCTL_OPTION = BIT(7),
752 HASHH_OPTION = BIT(8),
753 HASHL_OPTION = BIT(9),
754 FILTER_OPTION = BIT(10),
755 HALFDUPLEX_OPTION = BIT(11),
756 TIMER_OPTION = BIT(12),
757 INTERFRAMEGAP_OPTION = BIT(13),
758 }enet_option_enum;
HALFDUPLEX_OPTION
Definition: gd32f10x_enet.h:755
DMABUS_OPTION
Definition: gd32f10x_enet.h:745
HASHL_OPTION
Definition: gd32f10x_enet.h:753
FLOWCTL_OPTION
Definition: gd32f10x_enet.h:751
HASHH_OPTION
Definition: gd32f10x_enet.h:752
DMA_MAXBURST_OPTION
Definition: gd32f10x_enet.h:746
DMA_ARBITRATION_OPTION
Definition: gd32f10x_enet.h:747
STORE_OPTION
Definition: gd32f10x_enet.h:748
TIMER_OPTION
Definition: gd32f10x_enet.h:756
INTERFRAMEGAP_OPTION
Definition: gd32f10x_enet.h:757
VLAN_OPTION
Definition: gd32f10x_enet.h:750
enet_option_enum
enet_option_enum
Definition: gd32f10x_enet.h:742
DMA_OPTION
Definition: gd32f10x_enet.h:749
FORWARD_OPTION
Definition: gd32f10x_enet.h:744
FILTER_OPTION
Definition: gd32f10x_enet.h:754
enum enet_phydirection_enum
Enumerator
ENET_PHY_READ | read PHY
ENET_PHY_WRITE | write PHY

Definition at line 806 of file gd32f10x_enet.h.

807 {
808 ENET_PHY_READ = (uint32_t)0x00000000,
809 ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW
810 }enet_phydirection_enum;
enet_phydirection_enum
enet_phydirection_enum
Definition: gd32f10x_enet.h:806
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
ENET_MAC_PHY_CTL_PW
#define ENET_MAC_PHY_CTL_PW
Definition: gd32f10x_enet.h:192
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
enum enet_ptp_function_enum
Enumerator
ENET_PTP_SYSTIME_INIT | timestamp initialize
ENET_PTP_SYSTIME_UPDATE | timestamp update
ENET_PTP_ADDEND_UPDATE | addend register update
ENET_PTP_FINEMODE | the system timestamp uses the fine method for updating
ENET_PTP_COARSEMODE | the system timestamp uses the coarse method for updating

Definition at line 1243 of file gd32f10x_enet.h.

1243 {
1244 ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI,
1245 ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU,
1246 ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU,
1247 ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)),
1248 ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU,
1249 }enet_ptp_function_enum;
ENET_PTP_SYSTIME_INIT
Definition: gd32f10x_enet.h:1244
ENET_PTP_TSCTL_TMSSTU
#define ENET_PTP_TSCTL_TMSSTU
Definition: gd32f10x_enet.h:322
ENET_PTP_TSCTL_TMSARU
#define ENET_PTP_TSCTL_TMSARU
Definition: gd32f10x_enet.h:324
ENET_PTP_TSCTL_TMSFCU
#define ENET_PTP_TSCTL_TMSFCU
Definition: gd32f10x_enet.h:320
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
ENET_PTP_FINEMODE
Definition: gd32f10x_enet.h:1247
enet_ptp_function_enum
enet_ptp_function_enum
Definition: gd32f10x_enet.h:1243
ENET_PTP_COARSEMODE
Definition: gd32f10x_enet.h:1248
ENET_PTP_TSCTL_TMSSTI
#define ENET_PTP_TSCTL_TMSSTI
Definition: gd32f10x_enet.h:321
ENET_PTP_SYSTIME_UPDATE
Definition: gd32f10x_enet.h:1245
enum enet_regdirection_enum
Enumerator
ENET_REG_READ | read register
ENET_REG_WRITE | write register

Definition at line 813 of file gd32f10x_enet.h.

814 {
815 ENET_REG_READ,
816 ENET_REG_WRITE
817 }enet_regdirection_enum;
ENET_REG_READ
Definition: gd32f10x_enet.h:815
ENET_REG_WRITE
Definition: gd32f10x_enet.h:816
enet_regdirection_enum
enet_regdirection_enum
Definition: gd32f10x_enet.h:813
enum enet_registers_type_enum
Enumerator
ALL_MAC_REG | MAC register group
ALL_MSC_REG | MSC register group
ALL_PTP_REG | PTP register group
ALL_DMA_REG | DMA register group

Definition at line 790 of file gd32f10x_enet.h.

791 {
792 ALL_MAC_REG = 0,
793 ALL_MSC_REG = 22,
794 ALL_PTP_REG = 33,
795 ALL_DMA_REG = 44,
796 }enet_registers_type_enum;
ALL_MAC_REG
Definition: gd32f10x_enet.h:792
ALL_DMA_REG
Definition: gd32f10x_enet.h:795
ALL_PTP_REG
Definition: gd32f10x_enet.h:794
ALL_MSC_REG
Definition: gd32f10x_enet.h:793
enet_registers_type_enum
enet_registers_type_enum
Definition: gd32f10x_enet.h:790

Function Documentation

void enet_address_filter_config | ( | enet_macaddress_enum | mac_addr,
 |  | uint32_t | addr_mask,
 |  | uint32_t | filter_type
 | ) |  |

configure the MAC address filter

Parameters
[in] mac_addr select which MAC address will be configured, only one parameter can be selected which is shown as below
  • ENET_MAC_ADDRESS1: configure MAC address 1 filter
  • ENET_MAC_ADDRESS2: configure MAC address 2 filter
  • ENET_MAC_ADDRESS3: configure MAC address 3 filter
[in] addr_mask select which MAC address bytes will be mask, one or more parameters can be selected which are shown as below
  • ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits
  • ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits
  • ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits
  • ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits
  • ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits
  • ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits
[in] filter_type select which MAC address filter type will be selected, only one parameter can be selected which is shown as below
  • ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame
  • ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame
[out] none
Return values
none

Definition at line 1375 of file gd32f10x_enet.c.

1376 {
1377 uint32_t reg;
1378
1379 /* get the address filter register value which is to be configured */
1380 reg = REG32(ENET_ADDRH_BASE + mac_addr);
1381
1382 /* clear and configure the address filter register */
1383 reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF);
1384 reg |= (addr_mask | filter_type);
1385 REG32(ENET_ADDRH_BASE + mac_addr) = reg;
1386 }
ENET_MAC_ADDR1H_SAF
#define ENET_MAC_ADDR1H_SAF
Definition: gd32f10x_enet.h:250
ENET_ADDRH_BASE
#define ENET_ADDRH_BASE
Definition: gd32f10x_enet.h:531
ENET_MAC_ADDR1H_MB
#define ENET_MAC_ADDR1H_MB
Definition: gd32f10x_enet.h:249
void enet_address_filter_disable ( enet_macaddress_enum mac_addr )

disable the MAC address filter

Parameters
[in] mac_addr select which MAC address will be disable, only one parameter can be selected which is shown as below
  • ENET_MAC_ADDRESS1: disable MAC address 1 filter
  • ENET_MAC_ADDRESS2: disable MAC address 2 filter
  • ENET_MAC_ADDRESS3: disable MAC address 3 filter
[out] none
Return values
none

Definition at line 1348 of file gd32f10x_enet.c.

1349 {
1350 REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE;
1351 }
ENET_ADDRH_BASE
#define ENET_ADDRH_BASE
Definition: gd32f10x_enet.h:531
ENET_MAC_ADDR1H_AFE
#define ENET_MAC_ADDR1H_AFE
Definition: gd32f10x_enet.h:251
void enet_address_filter_enable ( enet_macaddress_enum mac_addr )

enable the MAC address filter

Parameters
[in] mac_addr select which MAC address will be enable
  • ENET_MAC_ADDRESS1: enable MAC address 1 filter
  • ENET_MAC_ADDRESS2: enable MAC address 2 filter
  • ENET_MAC_ADDRESS3: enable MAC address 3 filter
[out] none
Return values
none

Definition at line 1333 of file gd32f10x_enet.c.

1334 {
1335 REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE;
1336 }
ENET_ADDRH_BASE
#define ENET_ADDRH_BASE
Definition: gd32f10x_enet.h:531
ENET_MAC_ADDR1H_AFE
#define ENET_MAC_ADDR1H_AFE
Definition: gd32f10x_enet.h:251
uint32_t enet_current_desc_address_get ( enet_desc_reg_enum addr_get )

get the transmit/receive address of current descriptor, or current buffer, or descriptor table

Parameters
[in] addr_get choose the address which users want to get, refer to enet_desc_reg_enum, only one parameter can be selected which is shown as below
  • ENET_RX_DESC_TABLE: the start address of the receive descriptor table
  • ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by the RxDMA controller
  • ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller
  • ENET_TX_DESC_TABLE: the start address of the transmit descriptor table
  • ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by the TxDMA controller
  • ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller
[out] none
Return values
address value

Definition at line 1846 of file gd32f10x_enet.c.

1847 {
1848 uint32_t reval = 0U;
1849
1850 reval = REG32((ENET) +(uint32_t)addr_get);
1851 return reval;
1852 }
ENET
#define ENET
Definition: gd32f10x_enet.h:92
uint32_t enet_debug_status_get ( uint32_t mac_debug )
void enet_deinit ( void )

deinitialize the ENET, and reset structure parameters for ENET initialization

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 69 of file gd32f10x_enet.c.

70 {
71 rcu_periph_reset_enable(RCU_ENETRST);
72 rcu_periph_reset_disable(RCU_ENETRST);
73 enet_initpara_reset();
74 }
RCU_ENETRST
Definition: gd32f10x_rcu.h:441
enet_initpara_reset
void enet_initpara_reset(void)
reset the ENET initpara struct, call it before using enet_initpara_config()
Definition: gd32f10x_enet.c:2925
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void enet_desc_flag_clear | ( | enet_descriptors_struct * | desc,
 |  | uint32_t | desc_flag
 | ) |  |

clear the bit flag of ENET DMA descriptor

Parameters
[in] | desc | the descriptor pointer which users want to clear flag
[in] desc_flag the bit flag of ENET DMA descriptor, only one parameter can be selected which is shown as below
  • ENET_TDES0_VFRM: VLAN frame
  • ENET_TDES0_FRMF: frame flushed
  • ENET_TDES0_TCHM: the second address chained mode
  • ENET_TDES0_TERM: transmit end of ring mode
  • ENET_TDES0_TTSEN: transmit timestamp function enable
  • ENET_TDES0_DPAD: disable adding pad
  • ENET_TDES0_DCRC: disable CRC
  • ENET_TDES0_FSG: first segment
  • ENET_TDES0_LSG: last segment
  • ENET_TDES0_INTC: interrupt on completion
  • ENET_TDES0_DAV: DAV bit
  • ENET_RDES0_DAV: descriptor available
[out] | none
Return values
none

Definition at line 2021 of file gd32f10x_enet.c.

2022 {
2023 desc->status &= ~desc_flag;
2024 }
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
FlagStatus enet_desc_flag_get | ( | enet_descriptors_struct * | desc,
 |  | uint32_t | desc_flag
 | ) |  |

get the bit flag of ENET DMA descriptor

Parameters
[in] | desc | the descriptor pointer which users want to get flag
[in] desc_flag the bit flag of ENET DMA descriptor, only one parameter can be selected which is shown as below
  • ENET_TDES0_DB: deferred
  • ENET_TDES0_UFE: underflow error
  • ENET_TDES0_EXD: excessive deferral
  • ENET_TDES0_VFRM: VLAN frame
  • ENET_TDES0_ECO: excessive collision
  • ENET_TDES0_LCO: late collision
  • ENET_TDES0_NCA: no carrier
  • ENET_TDES0_LCA: loss of carrier
  • ENET_TDES0_IPPE: IP payload error
  • ENET_TDES0_FRMF: frame flushed
  • ENET_TDES0_JT: jabber timeout
  • ENET_TDES0_ES: error summary
  • ENET_TDES0_IPHE: IP header error
  • ENET_TDES0_TTMSS: transmit timestamp status
  • ENET_TDES0_TCHM: the second address chained mode
  • ENET_TDES0_TERM: transmit end of ring mode
  • ENET_TDES0_TTSEN: transmit timestamp function enable
  • ENET_TDES0_DPAD: disable adding pad
  • ENET_TDES0_DCRC: disable CRC
  • ENET_TDES0_FSG: first segment
  • ENET_TDES0_LSG: last segment
  • ENET_TDES0_INTC: interrupt on completion
  • ENET_TDES0_DAV: DAV bit
  • ENET_RDES0_PCERR: payload checksum error
  • ENET_RDES0_CERR: CRC error
  • ENET_RDES0_DBERR: dribble bit error
  • ENET_RDES0_RERR: receive error
  • ENET_RDES0_RWDT: receive watchdog timeout
  • ENET_RDES0_FRMT: frame type
  • ENET_RDES0_LCO: late collision
  • ENET_RDES0_IPHERR: IP frame header error
  • ENET_RDES0_LDES: last descriptor
  • ENET_RDES0_FDES: first descriptor
  • ENET_RDES0_VTAG: VLAN tag
  • ENET_RDES0_OERR: overflow error
  • ENET_RDES0_LERR: length error
  • ENET_RDES0_SAFF: SA filter fail
  • ENET_RDES0_DERR: descriptor error
  • ENET_RDES0_ERRS: error summary
  • ENET_RDES0_DAFF: destination address filter fail
  • ENET_RDES0_DAV: descriptor available
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 1965 of file gd32f10x_enet.c.

1966 {
1967 FlagStatus enet_flag = RESET;
1968
1969 if ((uint32_t)RESET != (desc->status & desc_flag)){
1970 enet_flag = SET;
1971 }
1972
1973 return enet_flag;
1974 }
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
void enet_desc_flag_set | ( | enet_descriptors_struct * | desc,
 |  | uint32_t | desc_flag
 | ) |  |

set the bit flag of ENET DMA descriptor

Parameters
[in] | desc | the descriptor pointer which users want to set flag
[in] desc_flag the bit flag of ENET DMA descriptor, only one parameter can be selected which is shown as below
  • ENET_TDES0_VFRM: VLAN frame
  • ENET_TDES0_FRMF: frame flushed
  • ENET_TDES0_TCHM: the second address chained mode
  • ENET_TDES0_TERM: transmit end of ring mode
  • ENET_TDES0_TTSEN: transmit timestamp function enable
  • ENET_TDES0_DPAD: disable adding pad
  • ENET_TDES0_DCRC: disable CRC
  • ENET_TDES0_FSG: first segment
  • ENET_TDES0_LSG: last segment
  • ENET_TDES0_INTC: interrupt on completion
  • ENET_TDES0_DAV: DAV bit
  • ENET_RDES0_DAV: descriptor available
[out] | none
Return values
none

Definition at line 1996 of file gd32f10x_enet.c.

1997 {
1998 desc->status |= desc_flag;
1999 }
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
uint32_t enet_desc_information_get | ( | enet_descriptors_struct * | desc,
 |  | enet_descstate_enum | info_get
 | ) |  |

get the Tx or Rx descriptor information

Parameters
[in] | desc | the descriptor pointer which users want to get information
[in] info_get the descriptor information type which is selected, only one parameter can be selected which is shown as below
  • RXDESC_BUFFER_1_SIZE: receive buffer 1 size
  • RXDESC_BUFFER_2_SIZE: receive buffer 2 size
  • RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer
  • TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted
  • RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame
  • TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame
[out] | none
Return values
descriptor information, if value is 0xFFFFFFFFU, means the false input parameter

Definition at line 1868 of file gd32f10x_enet.c.

1869 {
1870 uint32_t reval = 0xFFFFFFFFU;
1871
1872 switch(info_get){
1873 case RXDESC_BUFFER_1_SIZE:
1874 reval = GET_RDES1_RB1S(desc->control_buffer_size);
1875 break;
1876 case RXDESC_BUFFER_2_SIZE:
1877 reval = GET_RDES1_RB2S(desc->control_buffer_size);
1878 break;
1879 case RXDESC_FRAME_LENGTH:
1880 reval = GET_RDES0_FRML(desc->status);
1881 reval = reval - 4U;
1882
1883 break;
1884 case RXDESC_BUFFER_1_ADDR:
1885 reval = desc->buffer1_addr;
1886 break;
1887 case TXDESC_BUFFER_1_ADDR:
1888 reval = desc->buffer1_addr;
1889 break;
1890 case TXDESC_COLLISION_COUNT:
1891 reval = GET_TDES0_COCNT(desc->status);
1892 break;
1893 default:
1894 break;
1895 }
1896 return reval;
1897 }
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
GET_TDES0_COCNT
#define GET_TDES0_COCNT(regval)
Definition: gd32f10x_enet.h:1202
GET_RDES0_FRML
#define GET_RDES0_FRML(regval)
Definition: gd32f10x_enet.h:1217
RXDESC_FRAME_LENGTH
Definition: gd32f10x_enet.h:833
TXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:832
TXDESC_COLLISION_COUNT
Definition: gd32f10x_enet.h:831
GET_RDES1_RB1S
#define GET_RDES1_RB1S(regval)
Definition: gd32f10x_enet.h:1223
GET_RDES1_RB2S
#define GET_RDES1_RB2S(regval)
Definition: gd32f10x_enet.h:1225
RXDESC_BUFFER_1_SIZE
Definition: gd32f10x_enet.h:834
RXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:836
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
RXDESC_BUFFER_2_SIZE
Definition: gd32f10x_enet.h:835
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
void enet_descriptors_chain_init ( enet_dmadirection_enum direction )

initialize the DMA Tx/Rx descriptors's parameters in chain mode

Parameters
[in] direction the descriptors which users want to init, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA Tx descriptors
  • ENET_DMA_RX: DMA Rx descriptors
[out] none
Return values
none

Definition at line 647 of file gd32f10x_enet.c.

648 {
649 uint32_t num = 0U, count = 0U, maxsize = 0U;
650 uint32_t desc_status = 0U, desc_bufsize = 0U;
651 enet_descriptors_struct *desc, *desc_tab;
652 uint8_t *buf;
653
654 /* if want to initialize DMA Tx descriptors */
655 if (ENET_DMA_TX == direction){
656 /* save a copy of the DMA Tx descriptors */
657 desc_tab = txdesc_tab;
658 buf = &tx_buff[0][0];
659 count = ENET_TXBUF_NUM;
660 maxsize = ENET_TXBUF_SIZE;
661
662 /* select chain mode */
663 desc_status = ENET_TDES0_TCHM;
664
665 /* configure DMA Tx descriptor table address register */
666 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
667 dma_current_txdesc = desc_tab;
668 }else{
669 /* if want to initialize DMA Rx descriptors */
670 /* save a copy of the DMA Rx descriptors */
671 desc_tab = rxdesc_tab;
672 buf = &rx_buff[0][0];
673 count = ENET_RXBUF_NUM;
674 maxsize = ENET_RXBUF_SIZE;
675
676 /* enable receiving */
677 desc_status = ENET_RDES0_DAV;
678 /* select receive chained mode and set buffer1 size */
679 desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
680
681 /* configure DMA Rx descriptor table address register */
682 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
683 dma_current_rxdesc = desc_tab;
684 }
685 dma_current_ptp_rxdesc = NULL;
686 dma_current_ptp_txdesc = NULL;
687
688 /* configure each descriptor */
689 for(num=0U; num < count; num++){
690 /* get the pointer to the next descriptor of the descriptor table */
691 desc = desc_tab + num;
692
693 /* configure descriptors */
694 desc->status = desc_status;
695 desc->control_buffer_size = desc_bufsize;
696 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
697
698 /* if is not the last descriptor */
699 if(num < (count - 1U)){
700 /* configure the next descriptor address */
701 desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
702 }else{
703 /* when it is the last descriptor, the next descriptor address
704 equals to first descriptor address in descriptor table */
705 desc->buffer2_next_desc_addr = (uint32_t) desc_tab;
706 }
707 }
708 }
ENET_RXBUF_NUM
#define ENET_RXBUF_NUM
Definition: gd32f10x_enet.h:25
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_TXBUF_SIZE
#define ENET_TXBUF_SIZE
Definition: gd32f10x_enet.h:37
ENET_TXBUF_NUM
#define ENET_TXBUF_NUM
Definition: gd32f10x_enet.h:29
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_TCHM
#define ENET_TDES0_TCHM
Definition: gd32f10x_enet.h:464
NULL
#define NULL
Definition: usbd_std.h:20
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_RXBUF_SIZE
#define ENET_RXBUF_SIZE
Definition: gd32f10x_enet.h:33
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_descriptors_ring_init ( enet_dmadirection_enum direction )

initialize the DMA Tx/Rx descriptors's parameters in ring mode

Parameters
[in] direction the descriptors which users want to init, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA Tx descriptors
  • ENET_DMA_RX: DMA Rx descriptors
[out] none
Return values
none

Definition at line 719 of file gd32f10x_enet.c.

720 {
721 uint32_t num = 0U, count = 0U, maxsize = 0U;
722 uint32_t desc_status = 0U, desc_bufsize = 0U;
723 enet_descriptors_struct *desc;
724 enet_descriptors_struct *desc_tab;
725 uint8_t *buf;
726
727 /* configure descriptor skip length */
728 ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
729 ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
730
731 /* if want to initialize DMA Tx descriptors */
732 if (ENET_DMA_TX == direction){
733 /* save a copy of the DMA Tx descriptors */
734 desc_tab = txdesc_tab;
735 buf = &tx_buff[0][0];
736 count = ENET_TXBUF_NUM;
737 maxsize = ENET_TXBUF_SIZE;
738
739 /* configure DMA Tx descriptor table address register */
740 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
741 dma_current_txdesc = desc_tab;
742 }else{
743 /* if want to initialize DMA Rx descriptors */
744 /* save a copy of the DMA Rx descriptors */
745 desc_tab = rxdesc_tab;
746 buf = &rx_buff[0][0];
747 count = ENET_RXBUF_NUM;
748 maxsize = ENET_RXBUF_SIZE;
749
750 /* enable receiving */
751 desc_status = ENET_RDES0_DAV;
752 /* set buffer1 size */
753 desc_bufsize = ENET_RXBUF_SIZE;
754
755 /* configure DMA Rx descriptor table address register */
756 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
757 dma_current_rxdesc = desc_tab;
758 }
759 dma_current_ptp_rxdesc = NULL;
760 dma_current_ptp_txdesc = NULL;
761
762 /* configure each descriptor */
763 for(num=0U; num < count; num++){
764 /* get the pointer to the next descriptor of the descriptor table */
765 desc = desc_tab + num;
766
767 /* configure descriptors */
768 desc->status = desc_status;
769 desc->control_buffer_size = desc_bufsize;
770 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
771
772 /* when it is the last descriptor */
773 if(num == (count - 1U)){
774 if (ENET_DMA_TX == direction){
775 /* configure transmit end of ring mode */
776 desc->status |= ENET_TDES0_TERM;
777 }else{
778 /* configure receive end of ring mode */
779 desc->control_buffer_size |= ENET_RDES1_RERM;
780 }
781 }
782 }
783 }
ENET_RXBUF_NUM
#define ENET_RXBUF_NUM
Definition: gd32f10x_enet.h:25
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
ENET_DMA_BCTL_DPSL
#define ENET_DMA_BCTL_DPSL
Definition: gd32f10x_enet.h:355
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_TDES0_TERM
#define ENET_TDES0_TERM
Definition: gd32f10x_enet.h:465
ENET_TXBUF_SIZE
#define ENET_TXBUF_SIZE
Definition: gd32f10x_enet.h:37
ENET_TXBUF_NUM
#define ENET_TXBUF_NUM
Definition: gd32f10x_enet.h:29
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
DMA_BCTL_DPSL
#define DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1084
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
NULL
#define NULL
Definition: usbd_std.h:20
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_RXBUF_SIZE
#define ENET_RXBUF_SIZE
Definition: gd32f10x_enet.h:33
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_disable ( void )

ENET Tx and Rx function disable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 959 of file gd32f10x_enet.c.

960 {
961 enet_tx_disable();
962 enet_rx_disable();
963 }
enet_rx_disable
void enet_rx_disable(void)
ENET Rx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1286
enet_tx_disable
void enet_tx_disable(void)
ENET Tx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1261
void enet_dma_feature_disable ( uint32_t feature )

disable DMA feature

Parameters
[in] feature the feature of DMA mode, one or more parameters can be selected which are shown as below
  • ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function
  • ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function
[out] none
Return values
none

Definition at line 2105 of file gd32f10x_enet.c.

2106 {
2107 ENET_DMA_CTL &= ~feature;
2108 }
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
void enet_dma_feature_enable ( uint32_t feature )

enable DMA feature

Parameters
[in] feature the feature of DMA mode, one or more parameters can be selected which are shown as below
  • ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function
  • ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function
[out] none
Return values
none

Definition at line 2091 of file gd32f10x_enet.c.

2092 {
2093 ENET_DMA_CTL |= feature;
2094 }
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
void enet_dmaprocess_resume ( enet_dmadirection_enum direction )

poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception

Parameters
[in] direction choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA transmit process
  • ENET_DMA_RX: DMA receive process
[out] none
Return values
none

Definition at line 1773 of file gd32f10x_enet.c.

1774 {
1775 if(ENET_DMA_TX == direction){
1776 ENET_DMA_TPEN = 0U;
1777 }else{
1778 ENET_DMA_RPEN = 0U;
1779 }
1780 }
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
ENET_DMA_TPEN
#define ENET_DMA_TPEN
Definition: gd32f10x_enet.h:140
ENET_DMA_RPEN
#define ENET_DMA_RPEN
Definition: gd32f10x_enet.h:141
uint32_t enet_dmaprocess_state_get ( enet_dmadirection_enum direction )

get the dma transmit/receive process state

Parameters
[in] direction choose the direction of dma process which users want to check, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: dma transmit process
  • ENET_DMA_RX: dma receive process
[out] none
Return values
state of dma process, the value range shows below: ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING

Definition at line 1756 of file gd32f10x_enet.c.

1757 {
1758 uint32_t reval;
1759 reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction);
1760 return reval;
1761 }
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
void enet_enable ( void )

ENET Tx and Rx function enable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 947 of file gd32f10x_enet.c.

948 {
949 enet_tx_enable();
950 enet_rx_enable();
951 }
enet_rx_enable
void enet_rx_enable(void)
ENET Rx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1274
enet_tx_enable
void enet_tx_enable(void)
ENET Tx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1248
void enet_flag_clear ( enet_flag_clear_enum enet_flag )

clear the ENET DMA status flag

Parameters
[in] enet_flag ENET DMA flag clear, refer to enet_flag_clear_enum only one parameter can be selected which is shown as below
  • ENET_DMA_FLAG_TS_CLR: transmit status flag clear
  • ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear
  • ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear
  • ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear
  • ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear
  • ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear
  • ENET_DMA_FLAG_RS_CLR: receive status flag clear
  • ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear
  • ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear
  • ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear
  • ENET_DMA_FLAG_ET_CLR: early transmit status flag clear
  • ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear
  • ENET_DMA_FLAG_ER_CLR: early receive status flag clear
  • ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear
  • ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear
[out] none
Return values
none

Definition at line 1081 of file gd32f10x_enet.c.

1082 {
1083 /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */
1084 ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag));
1085 }
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
FlagStatus enet_flag_get ( enet_flag_enum enet_flag )

get the ENET MAC/MSC/PTP/DMA status flag

Parameters
[in] enet_flag ENET status flag, refer to enet_flag_enum, only one parameter can be selected which is shown as below
  • ENET_MAC_FLAG_MPKR: magic packet received flag
  • ENET_MAC_FLAG_WUFR: wakeup frame received flag
  • ENET_MAC_FLAG_FLOWCONTROL: flow control status flag
  • ENET_MAC_FLAG_WUM: WUM status flag
  • ENET_MAC_FLAG_MSC: MSC status flag
  • ENET_MAC_FLAG_MSCR: MSC receive status flag
  • ENET_MAC_FLAG_MSCT: MSC transmit status flag
  • ENET_MAC_FLAG_TMST: time stamp trigger status flag
  • ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag
  • ENET_PTP_FLAG_TTM: target time match flag
  • ENET_MSC_FLAG_RFCE: received frames CRC error flag
  • ENET_MSC_FLAG_RFAE: received frames alignment error flag
  • ENET_MSC_FLAG_RGUF: received good unicast frames flag
  • ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag
  • ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag
  • ENET_MSC_FLAG_TGF: transmitted good frames flag
  • ENET_DMA_FLAG_TS: transmit status flag
  • ENET_DMA_FLAG_TPS: transmit process stopped status flag
  • ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag
  • ENET_DMA_FLAG_TJT: transmit jabber timeout status flag
  • ENET_DMA_FLAG_RO: receive overflow status flag
  • ENET_DMA_FLAG_TU: transmit underflow status flag
  • ENET_DMA_FLAG_RS: receive status flag
  • ENET_DMA_FLAG_RBU: receive buffer unavailable status flag
  • ENET_DMA_FLAG_RPS: receive process stopped status flag
  • ENET_DMA_FLAG_RWT: receive watchdog timeout status flag
  • ENET_DMA_FLAG_ET: early transmit status flag
  • ENET_DMA_FLAG_FBE: fatal bus error status flag
  • ENET_DMA_FLAG_ER: early receive status flag
  • ENET_DMA_FLAG_AI: abnormal interrupt summary flag
  • ENET_DMA_FLAG_NI: normal interrupt summary flag
  • ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag
  • ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag
  • ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag
  • ENET_DMA_FLAG_MSC: MSC status flag
  • ENET_DMA_FLAG_WUM: WUM status flag
  • ENET_DMA_FLAG_TST: timestamp trigger status flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 1050 of file gd32f10x_enet.c.

1051 {
1052 if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){
1053 return SET;
1054 }else{
1055 return RESET;
1056 }
1057 }
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
void enet_fliter_feature_disable ( uint32_t feature )

disable ENET fliter feature

Parameters
[in] feature the feature of ENET fliter mode, one or more parameters can be selected which are shown as below
  • ENET_SRC_FILTER: filter source address function
  • ENET_SRC_FILTER_INVERSE: inverse source address filtering result function
  • ENET_DEST_FILTER_INVERSE: inverse DA filtering result function
  • ENET_MULTICAST_FILTER_PASS: pass all multicast frames function
  • ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function
  • ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function
  • ENET_FILTER_MODE_EITHER: HASH or perfect filter function
[out] none
Return values
none

Definition at line 1612 of file gd32f10x_enet.c.

1613 {
1614 ENET_MAC_FRMF &= ~feature;
1615 }
ENET_MAC_FRMF
#define ENET_MAC_FRMF
Definition: gd32f10x_enet.h:96
void enet_fliter_feature_enable ( uint32_t feature )

enable ENET fliter feature

Parameters
[in] feature the feature of ENET fliter mode, one or more parameters can be selected which are shown as below
  • ENET_SRC_FILTER: filter source address function
  • ENET_SRC_FILTER_INVERSE: inverse source address filtering result function
  • ENET_DEST_FILTER_INVERSE: inverse DA filtering result function
  • ENET_MULTICAST_FILTER_PASS: pass all multicast frames function
  • ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function
  • ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function
  • ENET_FILTER_MODE_EITHER: HASH or perfect filter function
[out] none
Return values
none

Definition at line 1593 of file gd32f10x_enet.c.

1594 {
1595 ENET_MAC_FRMF |= feature;
1596 }
ENET_MAC_FRMF
#define ENET_MAC_FRMF
Definition: gd32f10x_enet.h:96
void enet_flowcontrol_feature_disable ( uint32_t feature )

disable ENET flow control feature

Parameters
[in] feature the feature of ENET flow control mode one or more parameters can be selected which are shown as below
  • ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function
  • ENET_TX_FLOWCONTROL: the flow control operation in the MAC
  • ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it
  • ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode)
[out] none
Return values
none

Definition at line 1734 of file gd32f10x_enet.c.

1735 {
1736 if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
1737 ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE;
1738 }
1739 feature &= ~ENET_ZERO_QUANTA_PAUSE;
1740 ENET_MAC_FCTL &= ~feature;
1741 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_ZERO_QUANTA_PAUSE
#define ENET_ZERO_QUANTA_PAUSE
Definition: gd32f10x_enet.h:989
void enet_flowcontrol_feature_enable ( uint32_t feature )

enable ENET flow control feature

Parameters
[in] feature the feature of ENET flow control mode one or more parameters can be selected which are shown as below
  • ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function
  • ENET_TX_FLOWCONTROL: the flow control operation in the MAC
  • ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it
  • ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode)
[out] none
Return values
none

Definition at line 1714 of file gd32f10x_enet.c.

1715 {
1716 if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
1717 ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE;
1718 }
1719 feature &= ~ENET_ZERO_QUANTA_PAUSE;
1720 ENET_MAC_FCTL |= feature;
1721 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_ZERO_QUANTA_PAUSE
#define ENET_ZERO_QUANTA_PAUSE
Definition: gd32f10x_enet.h:989
void enet_flowcontrol_threshold_config | ( | uint32_t | deactive,
 |  | uint32_t | active
 | ) |  |

configure the threshold of the flow control(deactive and active threshold)

Parameters
[in] deactive the threshold of the deactive flow control, this value should always be less than active flow control value, only one parameter can be selected which is shown as below
  • ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes
  • ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes
  • ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes
  • ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes
  • ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes
  • ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes
  • ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes
[in] active the threshold of the active flow control, only one parameter can be selected which is shown as below
  • ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes
  • ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes
  • ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes
  • ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes
  • ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes
  • ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes
  • ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes
[out] none
Return values
none

Definition at line 1698 of file gd32f10x_enet.c.

1699 {
1700 ENET_MAC_FCTH = ((deactive | active) >> 8);
1701 }
ENET_MAC_FCTH
#define ENET_MAC_FCTH
Definition: gd32f10x_enet.h:102
void enet_forward_feature_disable ( uint32_t feature )

disable ENET forward feature

Parameters
[in] feature the feature of ENET forward mode, one or more parameters can be selected which are shown as below
  • ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function
  • ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it
  • ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode)
[out] none
Return values
none

Definition at line 1568 of file gd32f10x_enet.c.

1569 {
1570 uint32_t mask;
1571
1572 mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
1573 ENET_MAC_CFG &= ~mask;
1574
1575 mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
1576 ENET_DMA_CTL &= ~(mask >> 2);
1577 }
ENET_FORWARD_ERRFRAMES
#define ENET_FORWARD_ERRFRAMES
Definition: gd32f10x_enet.h:1185
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_AUTO_PADCRC_DROP
#define ENET_AUTO_PADCRC_DROP
Definition: gd32f10x_enet.h:922
ENET_FORWARD_UNDERSZ_GOODFRAMES
#define ENET_FORWARD_UNDERSZ_GOODFRAMES
Definition: gd32f10x_enet.h:1189
void enet_forward_feature_enable ( uint32_t feature )

enable ENET forward feature

Parameters
[in] feature the feature of ENET forward mode, one or more parameters can be selected which are shown as below
  • ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames
  • ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory
  • ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames
[out] none
Return values
none

Definition at line 1547 of file gd32f10x_enet.c.

1548 {
1549 uint32_t mask;
1550
1551 mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
1552 ENET_MAC_CFG |= mask;
1553
1554 mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
1555 ENET_DMA_CTL |= (mask >> 2);
1556 }
ENET_FORWARD_ERRFRAMES
#define ENET_FORWARD_ERRFRAMES
Definition: gd32f10x_enet.h:1185
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_AUTO_PADCRC_DROP
#define ENET_AUTO_PADCRC_DROP
Definition: gd32f10x_enet.h:922
ENET_FORWARD_UNDERSZ_GOODFRAMES
#define ENET_FORWARD_UNDERSZ_GOODFRAMES
Definition: gd32f10x_enet.h:1189
ErrStatus enet_frame_receive | ( | uint8_t * | buffer,
 |  | uint32_t | bufsize
 | ) |  |

handle current received frame data to application buffer

Parameters
[in] | bufsize | the size of buffer which is the parameter in function
[out] | buffer | pointer to the received frame data note – if the input is NULL, user should copy data in application by himself
Return values
ErrStatus SUCCESS or ERROR

Definition at line 792 of file gd32f10x_enet.c.

793 {
794 uint32_t offset = 0U, size = 0U;
795
796 /* the descriptor is busy due to own by the DMA */
797 if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
798 return ERROR;
799 }
800
801
802 /* if buffer pointer is null, indicates that users has copied data in application */
803 if(NULL != buffer){
804 /* if no error occurs, and the frame uses only one descriptor */
805 if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
806 (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
807 (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
808 /* get the frame length except CRC */
809 size = GET_RDES0_FRML(dma_current_rxdesc->status);
810 size = size - 4U;
811
812 /* to avoid situation that the frame size exceeds the buffer length */
813 if(size > bufsize){
814 return ERROR;
815 }
816
817 /* copy data from Rx buffer to application buffer */
818 for(offset = 0U; offset<size; offset++){
819 (*(buffer + offset)) = (*(__IO uint8_t *) (uint32_t)((dma_current_rxdesc->buffer1_addr) + offset));
820 }
821
822 }else{
823 /* return ERROR */
824 return ERROR;
825 }
826 }
827 /* enable reception, descriptor is owned by DMA */
828 dma_current_rxdesc->status = ENET_RDES0_DAV;
829
830 /* check Rx buffer unavailable flag status */
831 if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
832 /* clear RBU flag */
833 ENET_DMA_STAT = ENET_DMA_STAT_RBU;
834 /* resume DMA reception by writing to the RPEN register*/
835 ENET_DMA_RPEN = 0U;
836 }
837
838 /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */
839 /* chained mode */
840 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
841 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
842 }else{
843 /* ring mode */
844 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
845 /* if is the last descriptor in table, the next descriptor is the table header */
846 dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
847 }else{
848 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
849 dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
850 }
851 }
852
853 return SUCCESS;
854 }
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
GET_RDES0_FRML
#define GET_RDES0_FRML(regval)
Definition: gd32f10x_enet.h:1217
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ETH_DMARXDESC_SIZE
#define ETH_DMARXDESC_SIZE
Definition: gd32f10x_enet.h:1241
ENET_DMA_STAT_RBU
#define ENET_DMA_STAT_RBU
Definition: gd32f10x_enet.h:384
ENET_RDES0_FDES
#define ENET_RDES0_FDES
Definition: gd32f10x_enet.h:495
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
ENET_DMA_RPEN
#define ENET_DMA_RPEN
Definition: gd32f10x_enet.h:141
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_RDES0_ERRS
#define ENET_RDES0_ERRS
Definition: gd32f10x_enet.h:501
NULL
#define NULL
Definition: usbd_std.h:20
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
ENET_RDES0_LDES
#define ENET_RDES0_LDES
Definition: gd32f10x_enet.h:494
ErrStatus enet_frame_transmit | ( | uint8_t * | buffer,
 |  | uint32_t | length
 | ) |  |

handle application buffer data to transmit it

Parameters
[in] | buffer | pointer to the frame data to be transmitted, note – if the input is NULL, user should handle the data in application by himself
[in] | length | the length of frame data to be transmitted
[out] | none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 864 of file gd32f10x_enet.c.

865 {
866 uint32_t offset = 0U;
867 uint32_t dma_tbu_flag, dma_tu_flag;
868
869 /* the descriptor is busy due to own by the DMA */
870 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
871 return ERROR;
872 }
873
874 /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */
875 if(length > ENET_MAX_FRAME_SIZE){
876 return ERROR;
877 }
878
879 /* if buffer pointer is null, indicates that users has handled data in application */
880 if(NULL != buffer){
881 /* copy frame data from application buffer to Tx buffer */
882 for(offset = 0U; offset < length; offset++){
883 (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
884 }
885 }
886
887 /* set the frame length */
888 dma_current_txdesc->control_buffer_size = length;
889 /* set the segment of frame, frame is transmitted in one descriptor */
890 dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
891 /* enable the DMA transmission */
892 dma_current_txdesc->status |= ENET_TDES0_DAV;
893
894 /* check Tx buffer unavailable flag status */
895 dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
896 dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
897
898 if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
899 /* clear TBU and TU flag */
900 ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
901 /* resume DMA transmission by writing to the TPEN register*/
902 ENET_DMA_TPEN = 0U;
903 }
904
905 /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/
906 /* chained mode */
907 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
908 dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr);
909 }else{
910 /* ring mode */
911 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
912 /* if is the last descriptor in table, the next descriptor is the table header */
913 dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
914 }else{
915 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
916 dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
917 }
918 }
919
920 return SUCCESS;
921 }
ETH_DMATXDESC_SIZE
#define ETH_DMATXDESC_SIZE
Definition: gd32f10x_enet.h:1240
ENET_MAX_FRAME_SIZE
#define ENET_MAX_FRAME_SIZE
Definition: gd32f10x_enet.h:1256
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_DMA_STAT_TU
#define ENET_DMA_STAT_TU
Definition: gd32f10x_enet.h:382
ENET_TDES0_TERM
#define ENET_TDES0_TERM
Definition: gd32f10x_enet.h:465
ENET_DMA_STAT_TBU
#define ENET_DMA_STAT_TBU
Definition: gd32f10x_enet.h:379
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ENET_TDES0_FSG
#define ENET_TDES0_FSG
Definition: gd32f10x_enet.h:470
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
ENET_DMA_TPEN
#define ENET_DMA_TPEN
Definition: gd32f10x_enet.h:140
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_TCHM
#define ENET_TDES0_TCHM
Definition: gd32f10x_enet.h:464
NULL
#define NULL
Definition: usbd_std.h:20
ENET_TDES0_LSG
#define ENET_TDES0_LSG
Definition: gd32f10x_enet.h:471
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
ENET_TDES0_DAV
#define ENET_TDES0_DAV
Definition: gd32f10x_enet.h:473
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
ErrStatus enet_init | ( | enet_mediamode_enum | mediamode,
 |  | enet_chksumconf_enum | checksum,
 |  | enet_frmrecept_enum | recept
 | ) |  |

initialize ENET peripheral with generally concerned parameters and the less cared parameters

Parameters
[in] mediamode PHY mode and mac loopback configurations, only one parameter can be selected which is shown as below, refer to enet_mediamode_enum
  • ENET_AUTO_NEGOTIATION: PHY auto negotiation
  • ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex
  • ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex
  • ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex
  • ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex
  • ENET_LOOPBACKMODE: MAC in loopback mode at the MII
[in] checksum IP frame checksum offload function, only one parameter can be selected which is shown as below, refer to enet_mediamode_enum
  • ENET_NO_AUTOCHECKSUM: disable IP frame checksum function
  • ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function
  • ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame with only payload error but no other errors will not be dropped
[in] recept frame filter function, only one parameter can be selected which is shown as below, refer to enet_frmrecept_enum
  • ENET_PROMISCUOUS_MODE: promiscuous mode enabled
  • ENET_RECEIVEALL: all received frame are forwarded to application
  • ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames
  • ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames
[out] none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 280 of file gd32f10x_enet.c.

281 {
282 uint32_t reg_value=0U, reg_temp = 0U, temp = 0U;
283 uint32_t media_temp = 0U;
284 uint32_t timeout = 0U;
285 uint16_t phy_value = 0U;
286 ErrStatus phy_state= ERROR, enet_state = ERROR;
287
288 /* PHY interface configuration, configure SMI clock and reset PHY chip */
289 if(ERROR == enet_phy_config()){
290 _ENET_DELAY_(PHY_RESETDELAY);
291 if(ERROR == enet_phy_config()){
292 return enet_state;
293 }
294 }
295 /* initialize ENET peripheral with generally concerned parameters */
296 enet_default_init();
297
298 /* 1st, configure mediamode */
299 media_temp = (uint32_t)mediamode;
300 /* if is PHY auto negotiation */
301 if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){
302 /* wait for PHY_LINKED_STATUS bit be set */
303 do{
304 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
305 phy_value &= PHY_LINKED_STATUS;
306 timeout++;
307 }while((RESET == phy_value) && (timeout < PHY_READ_TO));
308 /* return ERROR due to timeout */
309 if(PHY_READ_TO == timeout){
310 return enet_state;
311 }
312 /* reset timeout counter */
313 timeout = 0U;
314
315 /* enable auto-negotiation */
316 phy_value = PHY_AUTONEGOTIATION;
317 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
318 if(!phy_state){
319 /* return ERROR due to write timeout */
320 return enet_state;
321 }
322
323 /* wait for the PHY_AUTONEGO_COMPLETE bit be set */
324 do{
325 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
326 phy_value &= PHY_AUTONEGO_COMPLETE;
327 timeout++;
328 }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO));
329 /* return ERROR due to timeout */
330 if(PHY_READ_TO == timeout){
331 return enet_state;
332 }
333 /* reset timeout counter */
334 timeout = 0U;
335
336 /* read the result of the auto-negotiation */
337 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value);
338 /* configure the duplex mode of MAC following the auto-negotiation result */
339 if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){
340 media_temp = ENET_MODE_FULLDUPLEX;
341 }else{
342 media_temp = ENET_MODE_HALFDUPLEX;
343 }
344 /* configure the communication speed of MAC following the auto-negotiation result */
345 if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){
346 media_temp |= ENET_SPEEDMODE_10M;
347 }else{
348 media_temp |= ENET_SPEEDMODE_100M;
349 }
350 }else{
351 phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3);
352 phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1);
353 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
354 if(!phy_state){
355 /* return ERROR due to write timeout */
356 return enet_state;
357 }
358 /* PHY configuration need some time */
359 _ENET_DELAY_(PHY_CONFIGDELAY);
360 }
361 /* after configuring the PHY, use mediamode to configure registers */
362 reg_value = ENET_MAC_CFG;
363 /* configure ENET_MAC_CFG register */
364 reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM));
365 reg_value |= media_temp;
366 ENET_MAC_CFG = reg_value;
367
368
369 /* 2st, configure checksum */
370 if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){
371 ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE;
372
373 reg_value = ENET_DMA_CTL;
374 /* configure ENET_DMA_CTL register */
375 reg_value &= ~ENET_DMA_CTL_DTCERFD;
376 reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD);
377 ENET_DMA_CTL = reg_value;
378 }
379
380 /* 3rd, configure recept */
381 ENET_MAC_FRMF |= (uint32_t)recept;
382
383 /* 4th, configure different function options */
384 /* configure forward_frame related registers */
385 if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){
386 reg_temp = enet_initpara.forward_frame;
387
388 reg_value = ENET_MAC_CFG;
389 temp = reg_temp;
390 /* configure ENET_MAC_CFG register */
391 reg_value &= (~ENET_MAC_CFG_APCD);
392 temp &= ENET_MAC_CFG_APCD;
393 reg_value |= temp;
394 ENET_MAC_CFG = reg_value;
395
396 reg_value = ENET_DMA_CTL;
397 temp = reg_temp;
398 /* configure ENET_DMA_CTL register */
399 reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF));
400 temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2);
401 reg_value |= (temp >> 2);
402 ENET_DMA_CTL = reg_value;
403 }
404
405 /* configure dmabus_mode related registers */
406 if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){
407 temp = enet_initpara.dmabus_mode;
408
409 reg_value = ENET_DMA_BCTL;
410 /* configure ENET_DMA_BCTL register */
411 reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \
412 |ENET_DMA_BCTL_FPBL);
413 reg_value |= temp;
414 ENET_DMA_BCTL = reg_value;
415 }
416
417 /* configure dma_maxburst related registers */
418 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){
419 temp = enet_initpara.dma_maxburst;
420
421 reg_value = ENET_DMA_BCTL;
422 /* configure ENET_DMA_BCTL register */
423 reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP);
424 reg_value |= temp;
425 ENET_DMA_BCTL = reg_value;
426 }
427
428 /* configure dma_arbitration related registers */
429 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){
430 temp = enet_initpara.dma_arbitration;
431
432 reg_value = ENET_DMA_BCTL;
433 /* configure ENET_DMA_BCTL register */
434 reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB);
435 reg_value |= temp;
436 ENET_DMA_BCTL = reg_value;
437 }
438
439 /* configure store_forward_mode related registers */
440 if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){
441 temp = enet_initpara.store_forward_mode;
442
443 reg_value = ENET_DMA_CTL;
444 /* configure ENET_DMA_CTL register */
445 reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC);
446 reg_value |= temp;
447 ENET_DMA_CTL = reg_value;
448 }
449
450 /* configure dma_function related registers */
451 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){
452 reg_temp = enet_initpara.dma_function;
453
454 reg_value = ENET_DMA_CTL;
455 /* configure ENET_DMA_CTL register */
456 reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF));
457 reg_value |= reg_temp;
458 ENET_DMA_CTL = reg_value;
459 }
460
461 /* configure vlan_config related registers */
462 if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){
463 reg_temp = enet_initpara.vlan_config;
464
465 reg_value = ENET_MAC_VLT;
466 /* configure ENET_MAC_VLT register */
467 reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC);
468 reg_value |= reg_temp;
469 ENET_MAC_VLT = reg_value;
470 }
471
472 /* configure flow_control related registers */
473 if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){
474 reg_temp = enet_initpara.flow_control;
475
476 reg_value = ENET_MAC_FCTL;
477 temp = reg_temp;
478 /* configure ENET_MAC_FCTL register */
479 reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
480 | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
481 temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
482 | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
483 reg_value |= temp;
484 ENET_MAC_FCTL = reg_value;
485
486 reg_value = ENET_MAC_FCTH;
487 temp = reg_temp;
488 /* configure ENET_MAC_FCTH register */
489 reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD);
490 temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8);
491 reg_value |= (temp >> 8);
492 ENET_MAC_FCTH = reg_value;
493 }
494
495 /* configure hashtable_high related registers */
496 if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){
497 ENET_MAC_HLH = enet_initpara.hashtable_high;
498 }
499
500 /* configure hashtable_low related registers */
501 if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){
502 ENET_MAC_HLL = enet_initpara.hashtable_low;
503 }
504
505 /* configure framesfilter_mode related registers */
506 if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){
507 reg_temp = enet_initpara.framesfilter_mode;
508
509 reg_value = ENET_MAC_FRMF;
510 /* configure ENET_MAC_FRMF register */
511 reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \
512 | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \
513 | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM);
514 reg_value |= reg_temp;
515 ENET_MAC_FRMF = reg_value;
516 }
517
518 /* configure halfduplex_param related registers */
519 if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){
520 reg_temp = enet_initpara.halfduplex_param;
521
522 reg_value = ENET_MAC_CFG;
523 /* configure ENET_MAC_CFG register */
524 reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \
525 | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC);
526 reg_value |= reg_temp;
527 ENET_MAC_CFG = reg_value;
528 }
529
530 /* configure timer_config related registers */
531 if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){
532 reg_temp = enet_initpara.timer_config;
533
534 reg_value = ENET_MAC_CFG;
535 /* configure ENET_MAC_CFG register */
536 reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD);
537 reg_value |= reg_temp;
538 ENET_MAC_CFG = reg_value;
539 }
540
541 /* configure interframegap related registers */
542 if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){
543 reg_temp = enet_initpara.interframegap;
544
545 reg_value = ENET_MAC_CFG;
546 /* configure ENET_MAC_CFG register */
547 reg_value &= ~ENET_MAC_CFG_IGBS;
548 reg_value |= reg_temp;
549 ENET_MAC_CFG = reg_value;
550 }
551
552 enet_state = SUCCESS;
553 return enet_state;
554 }
HALFDUPLEX_OPTION
Definition: gd32f10x_enet.h:755
ENET_MAC_CFG_DPM
#define ENET_MAC_CFG_DPM
Definition: gd32f10x_enet.h:162
ENET_DMA_CTL_DAFRF
#define ENET_DMA_CTL_DAFRF
Definition: gd32f10x_enet.h:409
ENET_DMA_BCTL_RTPR
#define ENET_DMA_BCTL_RTPR
Definition: gd32f10x_enet.h:357
ENET_MAC_FRMF_SAFLT
#define ENET_MAC_FRMF_SAFLT
Definition: gd32f10x_enet.h:180
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
PHY_AUTONEGOTIATION
#define PHY_AUTONEGOTIATION
Definition: gd32f10x_enet.h:68
DMABUS_OPTION
Definition: gd32f10x_enet.h:745
ENET_MAC_FRMF_SAIFLT
#define ENET_MAC_FRMF_SAIFLT
Definition: gd32f10x_enet.h:179
HASHL_OPTION
Definition: gd32f10x_enet.h:753
PHY_RESETDELAY
#define PHY_RESETDELAY
Definition: gd32f10x_enet.h:54
ENET_MAC_FCTH
#define ENET_MAC_FCTH
Definition: gd32f10x_enet.h:102
enet_initpara_struct::dmabus_mode
uint32_t dmabus_mode
Definition: gd32f10x_enet.h:844
PHY_DUPLEX_STATUS
#define PHY_DUPLEX_STATUS
Definition: gd32f10x_enet.h:85
ENET_MAC_FRMF_HMF
#define ENET_MAC_FRMF_HMF
Definition: gd32f10x_enet.h:174
ENET_MAC_FRMF_DAIFLT
#define ENET_MAC_FRMF_DAIFLT
Definition: gd32f10x_enet.h:175
ENET_DMA_CTL_FERF
#define ENET_DMA_CTL_FERF
Definition: gd32f10x_enet.h:404
FLOWCTL_OPTION
Definition: gd32f10x_enet.h:751
ENET_DMA_CTL_RTHC
#define ENET_DMA_CTL_RTHC
Definition: gd32f10x_enet.h:402
ENET_MAC_VLT_VLTC
#define ENET_MAC_VLT_VLTC
Definition: gd32f10x_enet.h:215
PHY_SR
#define PHY_SR
Definition: gd32f10x_enet.h:83
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
PHY_REG_BCR
#define PHY_REG_BCR
Definition: gd32f10x_enet.h:58
ENET_DMA_BCTL_DAB
#define ENET_DMA_BCTL_DAB
Definition: gd32f10x_enet.h:354
ENET_MAC_HLL
#define ENET_MAC_HLL
Definition: gd32f10x_enet.h:98
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
enet_initpara_struct::dma_arbitration
uint32_t dma_arbitration
Definition: gd32f10x_enet.h:846
enet_initpara_struct::interframegap
uint32_t interframegap
Definition: gd32f10x_enet.h:856
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_MODE_FULLDUPLEX
#define ENET_MODE_FULLDUPLEX
Definition: gd32f10x_enet.h:911
ENET_DMA_CTL_TTHC
#define ENET_DMA_CTL_TTHC
Definition: gd32f10x_enet.h:406
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
enet_phy_config
ErrStatus enet_phy_config(void)
PHY interface configuration (configure SMI clock and reset PHY chip)
Definition: gd32f10x_enet.c:1394
enet_initpara_struct::hashtable_high
uint32_t hashtable_high
Definition: gd32f10x_enet.h:851
enet_initpara_struct::halfduplex_param
uint32_t halfduplex_param
Definition: gd32f10x_enet.h:854
ENET_SPEEDMODE_10M
#define ENET_SPEEDMODE_10M
Definition: gd32f10x_enet.h:902
ENET_MAC_CFG_ROD
#define ENET_MAC_CFG_ROD
Definition: gd32f10x_enet.h:164
ENET_MAC_FCTL_DZQP
#define ENET_MAC_FCTL_DZQP
Definition: gd32f10x_enet.h:206
ENET_MAC_FRMF_PCFRM
#define ENET_MAC_FRMF_PCFRM
Definition: gd32f10x_enet.h:178
HASHH_OPTION
Definition: gd32f10x_enet.h:752
ENET_DMA_CTL_RSFD
#define ENET_DMA_CTL_RSFD
Definition: gd32f10x_enet.h:410
PHY_LINKED_STATUS
#define PHY_LINKED_STATUS
Definition: gd32f10x_enet.h:75
ENET_DMA_CTL_FUF
#define ENET_DMA_CTL_FUF
Definition: gd32f10x_enet.h:403
ENET_DMA_BCTL_FPBL
#define ENET_DMA_BCTL_FPBL
Definition: gd32f10x_enet.h:361
DMA_MAXBURST_OPTION
Definition: gd32f10x_enet.h:746
enet_initpara_struct::flow_control
uint32_t flow_control
Definition: gd32f10x_enet.h:850
ENET_DMA_CTL_TSFD
#define ENET_DMA_CTL_TSFD
Definition: gd32f10x_enet.h:408
enet_initpara_struct::store_forward_mode
uint32_t store_forward_mode
Definition: gd32f10x_enet.h:847
DMA_ARBITRATION_OPTION
Definition: gd32f10x_enet.h:747
enet_initpara_struct::dma_function
uint32_t dma_function
Definition: gd32f10x_enet.h:848
ENET_MAC_FCTL_PTM
#define ENET_MAC_FCTL_PTM
Definition: gd32f10x_enet.h:207
ENET_MAC_FRMF
#define ENET_MAC_FRMF
Definition: gd32f10x_enet.h:96
ENET_DMA_CTL_OSF
#define ENET_DMA_CTL_OSF
Definition: gd32f10x_enet.h:401
_ENET_DELAY_
#define _ENET_DELAY_
Definition: gd32f10x_enet.h:1473
ENET_MODE_HALFDUPLEX
#define ENET_MODE_HALFDUPLEX
Definition: gd32f10x_enet.h:912
PHY_READ_TO
#define PHY_READ_TO
Definition: gd32f10x_enet.h:50
ENET_MAC_HLH
#define ENET_MAC_HLH
Definition: gd32f10x_enet.h:97
ENET_MAC_FCTL_PLTS
#define ENET_MAC_FCTL_PLTS
Definition: gd32f10x_enet.h:205
ENET_MAC_FCTL_TFCEN
#define ENET_MAC_FCTL_TFCEN
Definition: gd32f10x_enet.h:202
enet_initpara_struct::hashtable_low
uint32_t hashtable_low
Definition: gd32f10x_enet.h:852
PHY_CONFIGDELAY
#define PHY_CONFIGDELAY
Definition: gd32f10x_enet.h:55
STORE_OPTION
Definition: gd32f10x_enet.h:748
TIMER_OPTION
Definition: gd32f10x_enet.h:756
INTERFRAMEGAP_OPTION
Definition: gd32f10x_enet.h:757
PHY_SPEED_STATUS
#define PHY_SPEED_STATUS
Definition: gd32f10x_enet.h:84
ENET_AUTO_NEGOTIATION
Definition: gd32f10x_enet.h:763
ENET_DMA_BCTL_FB
#define ENET_DMA_BCTL_FB
Definition: gd32f10x_enet.h:358
ENET_MAC_FRMF_HPFLT
#define ENET_MAC_FRMF_HPFLT
Definition: gd32f10x_enet.h:181
ENET_DMA_BCTL_PGBL
#define ENET_DMA_BCTL_PGBL
Definition: gd32f10x_enet.h:356
VLAN_OPTION
Definition: gd32f10x_enet.h:750
enet_initpara_struct::forward_frame
uint32_t forward_frame
Definition: gd32f10x_enet.h:843
ENET_MAC_CFG_BOL
#define ENET_MAC_CFG_BOL
Definition: gd32f10x_enet.h:158
ENET_MAC_CFG_APCD
#define ENET_MAC_CFG_APCD
Definition: gd32f10x_enet.h:159
ENET_DMA_BCTL_RXDP
#define ENET_DMA_BCTL_RXDP
Definition: gd32f10x_enet.h:359
enet_initpara_struct::timer_config
uint32_t timer_config
Definition: gd32f10x_enet.h:855
ENET_MAC_FCTL_RFCEN
#define ENET_MAC_FCTL_RFCEN
Definition: gd32f10x_enet.h:203
ENET_MAC_CFG_SPD
#define ENET_MAC_CFG_SPD
Definition: gd32f10x_enet.h:165
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
DMA_OPTION
Definition: gd32f10x_enet.h:749
enet_initpara_struct::option_enable
uint32_t option_enable
Definition: gd32f10x_enet.h:842
ENET_CHECKSUMOFFLOAD_ENABLE
#define ENET_CHECKSUMOFFLOAD_ENABLE
Definition: gd32f10x_enet.h:914
ENET_MAC_CFG_WDD
#define ENET_MAC_CFG_WDD
Definition: gd32f10x_enet.h:169
ENET_DMA_BCTL_UIP
#define ENET_DMA_BCTL_UIP
Definition: gd32f10x_enet.h:360
ENET_MAC_FCTL_UPFDT
#define ENET_MAC_FCTL_UPFDT
Definition: gd32f10x_enet.h:204
PHY_REG_BSR
#define PHY_REG_BSR
Definition: gd32f10x_enet.h:59
ENET_MAC_FCTH_RFD
#define ENET_MAC_FCTH_RFD
Definition: gd32f10x_enet.h:211
ENET_DMA_CTL_DTCERFD
#define ENET_DMA_CTL_DTCERFD
Definition: gd32f10x_enet.h:411
ENET_DMA_BCTL_AA
#define ENET_DMA_BCTL_AA
Definition: gd32f10x_enet.h:362
PHY_AUTONEGO_COMPLETE
#define PHY_AUTONEGO_COMPLETE
Definition: gd32f10x_enet.h:74
enet_initpara_struct::vlan_config
uint32_t vlan_config
Definition: gd32f10x_enet.h:849
PHY_ADDRESS
#define PHY_ADDRESS
Definition: gd32f10x_enet.h:47
ENET_MAC_CFG_IGBS
#define ENET_MAC_CFG_IGBS
Definition: gd32f10x_enet.h:167
ENET_MAC_CFG_RTD
#define ENET_MAC_CFG_RTD
Definition: gd32f10x_enet.h:160
enet_initpara_struct::dma_maxburst
uint32_t dma_maxburst
Definition: gd32f10x_enet.h:845
ENET_MAC_CFG_CSD
#define ENET_MAC_CFG_CSD
Definition: gd32f10x_enet.h:166
FORWARD_OPTION
Definition: gd32f10x_enet.h:744
ENET_MAC_FRMF_MFD
#define ENET_MAC_FRMF_MFD
Definition: gd32f10x_enet.h:176
ENET_SPEEDMODE_100M
#define ENET_SPEEDMODE_100M
Definition: gd32f10x_enet.h:903
ENET_MAC_VLT
#define ENET_MAC_VLT
Definition: gd32f10x_enet.h:103
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
ENET_MAC_FCTH_RFA
#define ENET_MAC_FCTH_RFA
Definition: gd32f10x_enet.h:210
ENET_MAC_CFG_DFC
#define ENET_MAC_CFG_DFC
Definition: gd32f10x_enet.h:157
enet_initpara_struct::framesfilter_mode
uint32_t framesfilter_mode
Definition: gd32f10x_enet.h:853
FILTER_OPTION
Definition: gd32f10x_enet.h:754
ENET_MAC_CFG_JBD
#define ENET_MAC_CFG_JBD
Definition: gd32f10x_enet.h:168
ENET_MAC_VLT_VLTI
#define ENET_MAC_VLT_VLTI
Definition: gd32f10x_enet.h:214
ENET_MAC_CFG_LBM
#define ENET_MAC_CFG_LBM
Definition: gd32f10x_enet.h:163
ENET_MAC_FRMF_HUF
#define ENET_MAC_FRMF_HUF
Definition: gd32f10x_enet.h:173
void enet_initpara_config | ( | enet_option_enum | option,
 |  | uint32_t | para
 | ) |  |

configure the parameters which are usually less cared for initialization note – this function must be called before enet_init(), otherwise configuration will be no effect

Parameters
[in] option different function option, which is related to several parameters, only one parameter can be selected which is shown as below, refer to enet_option_enum
  • FORWARD_OPTION: choose to configure the frame forward related parameters
  • DMABUS_OPTION: choose to configure the DMA bus mode related parameters
  • DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters
  • DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters
  • STORE_OPTION: choose to configure the store forward mode related parameters
  • DMA_OPTION: choose to configure the DMA descriptor related parameters
  • VLAN_OPTION: choose to configure vlan related parameters
  • FLOWCTL_OPTION: choose to configure flow control related parameters
  • HASHH_OPTION: choose to configure hash high
  • HASHL_OPTION: choose to configure hash low
  • FILTER_OPTION: choose to configure frame filter related parameters
  • HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters
  • TIMER_OPTION: choose to configure time counter related parameters
  • INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters
[in] para the related parameters according to the option all the related parameters should be configured which are shown as below FORWARD_OPTION related parameters:
  • ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ;
  • ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ;
  • ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . DMABUS_OPTION related parameters:
  • ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ;
  • ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; DMA_MAXBURST_OPTION related parameters:
  • ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ;
  • ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ;
  • ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; DMA_ARBITRATION_OPTION related parameters:
  • ENET_ARBITRATION_RXPRIORTX
  • ENET_ARBITRATION_RXTX_1_1/ ENET_ARBITRATION_RXTX_2_1/ ENET_ARBITRATION_RXTX_3_1/ ENET_ARBITRATION_RXTX_4_1/. STORE_OPTION related parameters:
  • ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ;
  • ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ;
  • ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ;
  • ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . DMA_OPTION related parameters:
  • ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ;
  • ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE . VLAN_OPTION related parameters:
  • ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ;
  • MAC_VLT_VLTI(regval) . FLOWCTL_OPTION related parameters:
  • MAC_FCTL_PTM(regval) ;
  • ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ;
  • ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ;
  • ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ;
  • ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ;
  • ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . HASHH_OPTION related parameters:
  • 0x0~0xFFFF FFFFU HASHL_OPTION related parameters:
  • 0x0~0xFFFF FFFFU FILTER_OPTION related parameters:
  • ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ ENET_SRC_FILTER_DISABLE ;
  • ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ;
  • ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ;
  • ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ ENET_UNICAST_FILTER_PERFECT ;
  • ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . HALFDUPLEX_OPTION related parameters:
  • ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ;
  • ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ;
  • ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ;
  • ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ;
  • ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . TIMER_OPTION related parameters:
  • ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ;
  • ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; INTERFRAMEGAP_OPTION related parameters:
  • ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT .
[out] none
Return values
none

Definition at line 176 of file gd32f10x_enet.c.

177 {
178 switch(option){
179 case FORWARD_OPTION:
180 /* choose to configure forward_frame, and save the configuration parameters */
181 enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION;
182 enet_initpara.forward_frame = para;
183 break;
184 case DMABUS_OPTION:
185 /* choose to configure dmabus_mode, and save the configuration parameters */
186 enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION;
187 enet_initpara.dmabus_mode = para;
188 break;
189 case DMA_MAXBURST_OPTION:
190 /* choose to configure dma_maxburst, and save the configuration parameters */
191 enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION;
192 enet_initpara.dma_maxburst = para;
193 break;
194 case DMA_ARBITRATION_OPTION:
195 /* choose to configure dma_arbitration, and save the configuration parameters */
196 enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION;
197 enet_initpara.dma_arbitration = para;
198 break;
199 case STORE_OPTION:
200 /* choose to configure store_forward_mode, and save the configuration parameters */
201 enet_initpara.option_enable |= (uint32_t)STORE_OPTION;
202 enet_initpara.store_forward_mode = para;
203 break;
204 case DMA_OPTION:
205 /* choose to configure dma_function, and save the configuration parameters */
206 enet_initpara.option_enable |= (uint32_t)DMA_OPTION;
207 enet_initpara.dma_function = para;
208 break;
209 case VLAN_OPTION:
210 /* choose to configure vlan_config, and save the configuration parameters */
211 enet_initpara.option_enable |= (uint32_t)VLAN_OPTION;
212 enet_initpara.vlan_config = para;
213 break;
214 case FLOWCTL_OPTION:
215 /* choose to configure flow_control, and save the configuration parameters */
216 enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION;
217 enet_initpara.flow_control = para;
218 break;
219 case HASHH_OPTION:
220 /* choose to configure hashtable_high, and save the configuration parameters */
221 enet_initpara.option_enable |= (uint32_t)HASHH_OPTION;
222 enet_initpara.hashtable_high = para;
223 break;
224 case HASHL_OPTION:
225 /* choose to configure hashtable_low, and save the configuration parameters */
226 enet_initpara.option_enable |= (uint32_t)HASHL_OPTION;
227 enet_initpara.hashtable_low = para;
228 break;
229 case FILTER_OPTION:
230 /* choose to configure framesfilter_mode, and save the configuration parameters */
231 enet_initpara.option_enable |= (uint32_t)FILTER_OPTION;
232 enet_initpara.framesfilter_mode = para;
233 break;
234 case HALFDUPLEX_OPTION:
235 /* choose to configure halfduplex_param, and save the configuration parameters */
236 enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION;
237 enet_initpara.halfduplex_param = para;
238 break;
239 case TIMER_OPTION:
240 /* choose to configure timer_config, and save the configuration parameters */
241 enet_initpara.option_enable |= (uint32_t)TIMER_OPTION;
242 enet_initpara.timer_config = para;
243 break;
244 case INTERFRAMEGAP_OPTION:
245 /* choose to configure interframegap, and save the configuration parameters */
246 enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION;
247 enet_initpara.interframegap = para;
248 break;
249 default:
250 break;
251 }
252 }
HALFDUPLEX_OPTION
Definition: gd32f10x_enet.h:755
DMABUS_OPTION
Definition: gd32f10x_enet.h:745
HASHL_OPTION
Definition: gd32f10x_enet.h:753
enet_initpara_struct::dmabus_mode
uint32_t dmabus_mode
Definition: gd32f10x_enet.h:844
FLOWCTL_OPTION
Definition: gd32f10x_enet.h:751
enet_initpara_struct::dma_arbitration
uint32_t dma_arbitration
Definition: gd32f10x_enet.h:846
enet_initpara_struct::interframegap
uint32_t interframegap
Definition: gd32f10x_enet.h:856
enet_initpara_struct::hashtable_high
uint32_t hashtable_high
Definition: gd32f10x_enet.h:851
enet_initpara_struct::halfduplex_param
uint32_t halfduplex_param
Definition: gd32f10x_enet.h:854
HASHH_OPTION
Definition: gd32f10x_enet.h:752
DMA_MAXBURST_OPTION
Definition: gd32f10x_enet.h:746
enet_initpara_struct::flow_control
uint32_t flow_control
Definition: gd32f10x_enet.h:850
enet_initpara_struct::store_forward_mode
uint32_t store_forward_mode
Definition: gd32f10x_enet.h:847
DMA_ARBITRATION_OPTION
Definition: gd32f10x_enet.h:747
enet_initpara_struct::dma_function
uint32_t dma_function
Definition: gd32f10x_enet.h:848
enet_initpara_struct::hashtable_low
uint32_t hashtable_low
Definition: gd32f10x_enet.h:852
STORE_OPTION
Definition: gd32f10x_enet.h:748
TIMER_OPTION
Definition: gd32f10x_enet.h:756
INTERFRAMEGAP_OPTION
Definition: gd32f10x_enet.h:757
VLAN_OPTION
Definition: gd32f10x_enet.h:750
enet_initpara_struct::forward_frame
uint32_t forward_frame
Definition: gd32f10x_enet.h:843
enet_initpara_struct::timer_config
uint32_t timer_config
Definition: gd32f10x_enet.h:855
DMA_OPTION
Definition: gd32f10x_enet.h:749
enet_initpara_struct::option_enable
uint32_t option_enable
Definition: gd32f10x_enet.h:842
enet_initpara_struct::vlan_config
uint32_t vlan_config
Definition: gd32f10x_enet.h:849
enet_initpara_struct::dma_maxburst
uint32_t dma_maxburst
Definition: gd32f10x_enet.h:845
FORWARD_OPTION
Definition: gd32f10x_enet.h:744
enet_initpara_struct::framesfilter_mode
uint32_t framesfilter_mode
Definition: gd32f10x_enet.h:853
FILTER_OPTION
Definition: gd32f10x_enet.h:754
void enet_initpara_reset ( void )

reset the ENET initpara struct, call it before using enet_initpara_config()

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 2925 of file gd32f10x_enet.c.

2926 {
2927 enet_initpara.option_enable = 0U;
2928 enet_initpara.forward_frame = 0U;
2929 enet_initpara.dmabus_mode = 0U;
2930 enet_initpara.dma_maxburst = 0U;
2931 enet_initpara.dma_arbitration = 0U;
2932 enet_initpara.store_forward_mode = 0U;
2933 enet_initpara.dma_function = 0U;
2934 enet_initpara.vlan_config = 0U;
2935 enet_initpara.flow_control = 0U;
2936 enet_initpara.hashtable_high = 0U;
2937 enet_initpara.hashtable_low = 0U;
2938 enet_initpara.framesfilter_mode = 0U;
2939 enet_initpara.halfduplex_param = 0U;
2940 enet_initpara.timer_config = 0U;
2941 enet_initpara.interframegap = 0U;
2942 }
enet_initpara_struct::dmabus_mode
uint32_t dmabus_mode
Definition: gd32f10x_enet.h:844
enet_initpara_struct::dma_arbitration
uint32_t dma_arbitration
Definition: gd32f10x_enet.h:846
enet_initpara_struct::interframegap
uint32_t interframegap
Definition: gd32f10x_enet.h:856
enet_initpara_struct::hashtable_high
uint32_t hashtable_high
Definition: gd32f10x_enet.h:851
enet_initpara_struct::halfduplex_param
uint32_t halfduplex_param
Definition: gd32f10x_enet.h:854
enet_initpara_struct::flow_control
uint32_t flow_control
Definition: gd32f10x_enet.h:850
enet_initpara_struct::store_forward_mode
uint32_t store_forward_mode
Definition: gd32f10x_enet.h:847
enet_initpara_struct::dma_function
uint32_t dma_function
Definition: gd32f10x_enet.h:848
enet_initpara_struct::hashtable_low
uint32_t hashtable_low
Definition: gd32f10x_enet.h:852
enet_initpara_struct::forward_frame
uint32_t forward_frame
Definition: gd32f10x_enet.h:843
enet_initpara_struct::timer_config
uint32_t timer_config
Definition: gd32f10x_enet.h:855
enet_initpara_struct::option_enable
uint32_t option_enable
Definition: gd32f10x_enet.h:842
enet_initpara_struct::vlan_config
uint32_t vlan_config
Definition: gd32f10x_enet.h:849
enet_initpara_struct::dma_maxburst
uint32_t dma_maxburst
Definition: gd32f10x_enet.h:845
enet_initpara_struct::framesfilter_mode
uint32_t framesfilter_mode
Definition: gd32f10x_enet.h:853
void enet_interrupt_disable ( enet_int_enum enet_int )

disable ENET MAC/MSC/DMA interrupt

Parameters
[in] enet_int ENET interrupt, only one parameter can be selected which is shown as below
  • ENET_MAC_INT_WUMIM: WUM interrupt mask
  • ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask
  • ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask
  • ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask
  • ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask
  • ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask
  • ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask
  • ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask
  • ENET_DMA_INT_TIE: transmit interrupt enable
  • ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable
  • ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable
  • ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable
  • ENET_DMA_INT_ROIE: receive overflow interrupt enable
  • ENET_DMA_INT_TUIE: transmit underflow interrupt enable
  • ENET_DMA_INT_RIE: receive interrupt enable
  • ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable
  • ENET_DMA_INT_RPSIE: receive process stopped interrupt enable
  • ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable
  • ENET_DMA_INT_ETIE: early transmit interrupt enable
  • ENET_DMA_INT_FBEIE: fatal bus error interrupt enable
  • ENET_DMA_INT_ERIE: early receive interrupt enable
  • ENET_DMA_INT_AIE: abnormal interrupt summary enable
  • ENET_DMA_INT_NIE: normal interrupt summary enable
[out] none
Return values
none

Definition at line 1158 of file gd32f10x_enet.c.

1159 {
1160 if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
1161 /* ENET_DMA_INTEN register interrupt */
1162 ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
1163 }else{
1164 /* other INTMSK register interrupt */
1165 ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
1166 }
1167 }
DMA_INTEN_REG_OFFSET
#define DMA_INTEN_REG_OFFSET
Definition: gd32f10x_enet.h:553
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
void enet_interrupt_enable ( enet_int_enum enet_int )

enable ENET MAC/MSC/DMA interrupt

Parameters
[in] enet_int ENET interrupt, only one parameter can be selected which is shown as below
  • ENET_MAC_INT_WUMIM: WUM interrupt mask
  • ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask
  • ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask
  • ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask
  • ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask
  • ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask
  • ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask
  • ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask
  • ENET_DMA_INT_TIE: transmit interrupt enable
  • ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable
  • ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable
  • ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable
  • ENET_DMA_INT_ROIE: receive overflow interrupt enable
  • ENET_DMA_INT_TUIE: transmit underflow interrupt enable
  • ENET_DMA_INT_RIE: receive interrupt enable
  • ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable
  • ENET_DMA_INT_RPSIE: receive process stopped interrupt enable
  • ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable
  • ENET_DMA_INT_ETIE: early transmit interrupt enable
  • ENET_DMA_INT_FBEIE: fatal bus error interrupt enable
  • ENET_DMA_INT_ERIE: early receive interrupt enable
  • ENET_DMA_INT_AIE: abnormal interrupt summary enable
  • ENET_DMA_INT_NIE: normal interrupt summary enable
[out] none
Return values
none

Definition at line 1117 of file gd32f10x_enet.c.

1118 {
1119 if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
1120 /* ENET_DMA_INTEN register interrupt */
1121 ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
1122 }else{
1123 /* other INTMSK register interrupt */
1124 ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
1125 }
1126 }
DMA_INTEN_REG_OFFSET
#define DMA_INTEN_REG_OFFSET
Definition: gd32f10x_enet.h:553
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
void enet_interrupt_flag_clear ( enet_int_flag_clear_enum int_flag_clear )

clear ENET DMA interrupt flag

Parameters
[in] int_flag_clear clear ENET interrupt flag, only one parameter can be selected which is shown as below
  • ENET_DMA_INT_FLAG_TS_CLR: transmit status flag
  • ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag
  • ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag
  • ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag
  • ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag
  • ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag
  • ENET_DMA_INT_FLAG_RS_CLR: receive status flag
  • ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag
  • ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag
  • ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag
  • ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag
  • ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag
  • ENET_DMA_INT_FLAG_ER_CLR: early receive status flag
  • ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag
  • ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag
[out] none
Return values
none

Definition at line 1236 of file gd32f10x_enet.c.

1237 {
1238 /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */
1239 ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear));
1240 }
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
FlagStatus enet_interrupt_flag_get ( enet_int_flag_enum int_flag )

get ENET MAC/MSC/DMA interrupt flag

Parameters
[in] int_flag ENET interrupt flag, only one parameter can be selected which is shown as below
  • ENET_MAC_INT_FLAG_WUM: WUM status flag
  • ENET_MAC_INT_FLAG_MSC: MSC status flag
  • ENET_MAC_INT_FLAG_MSCR: MSC receive status flag
  • ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag
  • ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag
  • ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag
  • ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag
  • ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag
  • ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag
  • ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag
  • ENET_MSC_INT_FLAG_TGF: transmitted good frames flag
  • ENET_DMA_INT_FLAG_TS: transmit status flag
  • ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag
  • ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag
  • ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag
  • ENET_DMA_INT_FLAG_RO: receive overflow status flag
  • ENET_DMA_INT_FLAG_TU: transmit underflow status flag
  • ENET_DMA_INT_FLAG_RS: receive status flag
  • ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag
  • ENET_DMA_INT_FLAG_RPS: receive process stopped status flag
  • ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag
  • ENET_DMA_INT_FLAG_ET: early transmit status flag
  • ENET_DMA_INT_FLAG_FBE: fatal bus error status flag
  • ENET_DMA_INT_FLAG_ER: early receive status flag
  • ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag
  • ENET_DMA_INT_FLAG_NI: normal interrupt summary flag
  • ENET_DMA_INT_FLAG_MSC: MSC status flag
  • ENET_DMA_INT_FLAG_WUM: WUM status flag
  • ENET_DMA_INT_FLAG_TST: timestamp trigger status flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 1205 of file gd32f10x_enet.c.

1206 {
1207 if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){
1208 return SET;
1209 }else{
1210 return RESET;
1211 }
1212 }
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
void enet_mac_address_get | ( | enet_macaddress_enum | mac_addr,
 |  | uint8_t | paddr[]
 | ) |  |

get MAC address

Parameters
[in] mac_addr select which MAC address will be get, only one parameter can be selected which is shown as below
  • ENET_MAC_ADDRESS0: get MAC address 0 filter
  • ENET_MAC_ADDRESS1: get MAC address 1 filter
  • ENET_MAC_ADDRESS2: get MAC address 2 filter
  • ENET_MAC_ADDRESS3: get MAC address 3 filter
[out] paddr the buffer pointer which is stored the MAC address (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa})
Return values
none

Definition at line 996 of file gd32f10x_enet.c.

997 {
998 paddr[0] = ENET_GET_MACADDR(mac_addr, 0U);
999 paddr[1] = ENET_GET_MACADDR(mac_addr, 1U);
1000 paddr[2] = ENET_GET_MACADDR(mac_addr, 2U);
1001 paddr[3] = ENET_GET_MACADDR(mac_addr, 3U);
1002 paddr[4] = ENET_GET_MACADDR(mac_addr, 4U);
1003 paddr[5] = ENET_GET_MACADDR(mac_addr, 5U);
1004 }
ENET_GET_MACADDR
#define ENET_GET_MACADDR(offset, n)
Definition: gd32f10x_enet.h:533
void enet_mac_address_set | ( | enet_macaddress_enum | mac_addr,
 |  | uint8_t | paddr[]
 | ) |  |

configure MAC address

Parameters
[in] mac_addr select which MAC address will be set, only one parameter can be selected which is shown as below
  • ENET_MAC_ADDRESS0: set MAC address 0 filter
  • ENET_MAC_ADDRESS1: set MAC address 1 filter
  • ENET_MAC_ADDRESS2: set MAC address 2 filter
  • ENET_MAC_ADDRESS3: set MAC address 3 filter
[in] | paddr | the buffer pointer which stores the MAC address (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa})
[out] | none
Return values
none

Definition at line 978 of file gd32f10x_enet.c.

979 {
980 REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr);
981 REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr);
982 }
ENET_ADDRH_BASE
#define ENET_ADDRH_BASE
Definition: gd32f10x_enet.h:531
ENET_SET_MACADDRL
#define ENET_SET_MACADDRL(p)
Definition: gd32f10x_enet.h:530
ENET_SET_MACADDRH
#define ENET_SET_MACADDRH(p)
Definition: gd32f10x_enet.h:529
ENET_ADDRL_BASE
#define ENET_ADDRL_BASE
Definition: gd32f10x_enet.h:532
void enet_missed_frame_counter_get | ( | uint32_t * | rxfifo_drop,
 |  | uint32_t * | rxdma_drop
 | ) |  |

get the number of missed frames during receiving

Parameters
[in] | none
[out] | rxfifo_drop | pointer to the number of frames dropped by RxFIFO
[out] | rxdma_drop | pointer to the number of frames missed by the RxDMA controller
Return values
none

Definition at line 1906 of file gd32f10x_enet.c.

1907 {
1908 uint32_t temp_counter = 0U;
1909
1910 temp_counter = ENET_DMA_MFBOCNT;
1911 *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter);
1912 *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter);
1913 }
ENET_DMA_MFBOCNT
#define ENET_DMA_MFBOCNT
Definition: gd32f10x_enet.h:147
GET_DMA_MFBOCNT_MSFC
#define GET_DMA_MFBOCNT_MSFC(regval)
Definition: gd32f10x_enet.h:1196
GET_DMA_MFBOCNT_MSFA
#define GET_DMA_MFBOCNT_MSFA(regval)
Definition: gd32f10x_enet.h:1198
uint32_t enet_msc_counters_get ( enet_msc_counter_enum counter )

get MAC statistics counter

Parameters
[in] counter MSC counters which is selected, refer to enet_msc_counter_enum, only one parameter can be selected which is shown as below
  • ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter
  • ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter
  • ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter
  • ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter
  • ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter
  • ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter
[out] none
Return values
the MSC counter value

Definition at line 2572 of file gd32f10x_enet.c.

2573 {
2574 uint32_t reval;
2575
2576 reval = REG32((ENET + (uint32_t)counter));
2577
2578 return reval;
2579 }
ENET
#define ENET
Definition: gd32f10x_enet.h:92
void enet_msc_counters_reset ( void )

reset the MAC statistics counters

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 2525 of file gd32f10x_enet.c.

2526 {
2527 /* reset all counters */
2528 ENET_MSC_CTL |= ENET_MSC_CTL_CTR;
2529 }
ENET_MSC_CTL
#define ENET_MSC_CTL
Definition: gd32f10x_enet.h:117
ENET_MSC_CTL_CTR
#define ENET_MSC_CTL_CTR
Definition: gd32f10x_enet.h:275
void enet_msc_feature_disable ( uint32_t feature )

disable the MAC statistics counter features

Parameters
[in] feature one or more parameters can be selected which are shown as below
  • ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover
  • ENET_MSC_RESET_ON_READ: reset on read
  • ENET_MSC_COUNTERS_FREEZE: MSC counter freeze
[out] none
Return values
none

Definition at line 2554 of file gd32f10x_enet.c.

2555 {
2556 ENET_MSC_CTL &= (~feature);
2557 }
ENET_MSC_CTL
#define ENET_MSC_CTL
Definition: gd32f10x_enet.h:117
void enet_msc_feature_enable ( uint32_t feature )

enable the MAC statistics counter features

Parameters
[in] feature one or more parameters can be selected which are shown as below
  • ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover
  • ENET_MSC_RESET_ON_READ: reset on read
  • ENET_MSC_COUNTERS_FREEZE: MSC counter freeze
[out] none
Return values
none

Definition at line 2540 of file gd32f10x_enet.c.

2541 {
2542 ENET_MSC_CTL |= feature;
2543 }
ENET_MSC_CTL
#define ENET_MSC_CTL
Definition: gd32f10x_enet.h:117
void enet_pauseframe_config | ( | uint32_t | pausetime,
 |  | uint32_t | pause_threshold
 | ) |  |

configure the pause frame parameters

Parameters
[in] | pausetime | pause time in transmit pause control frame
[in] pause_threshold the threshold of the pause timer for retransmitting frames automatically, this value must make sure to be less than configured pause time, only one parameter can be selected which is shown as below
  • ENET_PAUSETIME_MINUS4: pause time minus 4 slot times
  • ENET_PAUSETIME_MINUS28: pause time minus 28 slot times
  • ENET_PAUSETIME_MINUS144: pause time minus 144 slot times
  • ENET_PAUSETIME_MINUS256: pause time minus 256 slot times
[out] | none
Return values
none

Definition at line 1668 of file gd32f10x_enet.c.

1669 {
1670 ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS);
1671 ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold);
1672 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_MAC_FCTL_PTM
#define ENET_MAC_FCTL_PTM
Definition: gd32f10x_enet.h:207
ENET_MAC_FCTL_PLTS
#define ENET_MAC_FCTL_PLTS
Definition: gd32f10x_enet.h:205
MAC_FCTL_PTM
#define MAC_FCTL_PTM(regval)
Definition: gd32f10x_enet.h:1006
void enet_pauseframe_detect_config ( uint32_t detect )

configure the pause frame detect type

Parameters
[in] detect pause frame detect type, only one parameter can be selected which is shown as below
  • ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also use the MAC0 address to detecting pause frame
  • ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected
[out] none
Return values
none

Definition at line 1649 of file gd32f10x_enet.c.

1650 {
1651 ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT;
1652 ENET_MAC_FCTL |= detect;
1653 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_MAC_FCTL_UPFDT
#define ENET_MAC_FCTL_UPFDT
Definition: gd32f10x_enet.h:204
ErrStatus enet_pauseframe_generate ( void )

generate the pause frame, ENET will send pause frame after enable transmit flow control this function only use in full-dulex mode

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 1624 of file gd32f10x_enet.c.

1625 {
1626 ErrStatus enet_state =ERROR;
1627 uint32_t temp = 0U;
1628
1629 /* in full-duplex mode, must make sure this bit is 0 before writing register */
1630 temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA;
1631 if(RESET == temp){
1632 ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA;
1633 enet_state = SUCCESS;
1634 }
1635 return enet_state;
1636 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_MAC_FCTL_FLCBBKPA
#define ENET_MAC_FCTL_FLCBBKPA
Definition: gd32f10x_enet.h:201
ErrStatus enet_phy_config ( void )

PHY interface configuration (configure SMI clock and reset PHY chip)

Parameters
[in] | none
[out] | none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 1394 of file gd32f10x_enet.c.

1395 {
1396 uint32_t ahbclk;
1397 uint32_t reg;
1398 uint16_t phy_value;
1399 ErrStatus enet_state = ERROR;
1400
1401 /* clear the previous MDC clock */
1402 reg = ENET_MAC_PHY_CTL;
1403 reg &= ~ENET_MAC_PHY_CTL_CLR;
1404
1405 /* get the HCLK frequency */
1406 ahbclk = rcu_clock_freq_get(CK_AHB);
1407
1408 /* configure MDC clock according to HCLK frequency range */
1409 if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){
1410 reg |= ENET_MDC_HCLK_DIV16;
1411 }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){
1412 reg |= ENET_MDC_HCLK_DIV26;
1413 }else if(ENET_RANGE(ahbclk, 60000000U, 90000000U)){
1414 reg |= ENET_MDC_HCLK_DIV42;
1415 }else if((ENET_RANGE(ahbclk, 90000000U, 108000000U))||(108000000U == ahbclk)){
1416 reg |= ENET_MDC_HCLK_DIV62;
1417 }else{
1418 return enet_state;
1419 }
1420 ENET_MAC_PHY_CTL = reg;
1421
1422 /* reset PHY */
1423 phy_value = PHY_RESET;
1424 if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
1425 return enet_state;
1426 }
1427 /* PHY reset need some time */
1428 _ENET_DELAY_(ENET_DELAY_TO);
1429
1430 /* check whether PHY reset is complete */
1431 if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
1432 return enet_state;
1433 }
1434
1435 /* PHY reset complete */
1436 if(RESET == (phy_value & PHY_RESET)){
1437 enet_state = SUCCESS;
1438 }
1439
1440 return enet_state;
1441 }
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_RANGE
#define ENET_RANGE(hclk, n, m)
Definition: gd32f10x_enet.h:526
PHY_REG_BCR
#define PHY_REG_BCR
Definition: gd32f10x_enet.h:58
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
ENET_MAC_PHY_CTL
#define ENET_MAC_PHY_CTL
Definition: gd32f10x_enet.h:99
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
PHY_RESET
#define PHY_RESET
Definition: gd32f10x_enet.h:62
ENET_MDC_HCLK_DIV16
#define ENET_MDC_HCLK_DIV16
Definition: gd32f10x_enet.h:970
ENET_MDC_HCLK_DIV42
#define ENET_MDC_HCLK_DIV42
Definition: gd32f10x_enet.h:968
ENET_MDC_HCLK_DIV62
#define ENET_MDC_HCLK_DIV62
Definition: gd32f10x_enet.h:969
ENET_MDC_HCLK_DIV26
#define ENET_MDC_HCLK_DIV26
Definition: gd32f10x_enet.h:971
_ENET_DELAY_
#define _ENET_DELAY_
Definition: gd32f10x_enet.h:1473
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
CK_AHB
Definition: gd32f10x_rcu.h:585
PHY_ADDRESS
#define PHY_ADDRESS
Definition: gd32f10x_enet.h:47
ENET_MAC_PHY_CTL_CLR
#define ENET_MAC_PHY_CTL_CLR
Definition: gd32f10x_enet.h:193
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
ErrStatus enet_phy_write_read | ( | enet_phydirection_enum | direction,
 |  | uint16_t | phy_address,
 |  | uint16_t | phy_reg,
 |  | uint16_t * | pvalue
 | ) |  |

write to / read from a PHY register

Parameters
[in] direction only one parameter can be selected which is shown as below
  • ENET_PHY_WRITE: write data to phy register
  • ENET_PHY_READ: read data from phy register
[in] | phy_address | 0x0 - 0x1F
[in] | phy_reg | 0x0 - 0x1F
[in] | pvalue | the value will be written to the PHY register in ENET_PHY_WRITE direction
[out] | pvalue | the value will be read from the PHY register in ENET_PHY_READ direction
Return values
ErrStatus SUCCESS or ERROR

Definition at line 1454 of file gd32f10x_enet.c.

1455 {
1456 uint32_t reg, phy_flag;
1457 uint32_t timeout = 0U;
1458 ErrStatus enet_state = ERROR;
1459
1460 /* configure ENET_MAC_PHY_CTL with write/read operation */
1461 reg = ENET_MAC_PHY_CTL;
1462 reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA);
1463 reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB);
1464
1465 /* if do the write operation, write value to the register */
1466 if(ENET_PHY_WRITE == direction){
1467 ENET_MAC_PHY_DATA = *pvalue;
1468 }
1469
1470 /* do PHY write/read operation, and wait the operation complete */
1471 ENET_MAC_PHY_CTL = reg;
1472 do{
1473 phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB);
1474 timeout++;
1475 }
1476 while((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
1477
1478 /* write/read operation complete */
1479 if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){
1480 enet_state = SUCCESS;
1481 }
1482
1483 /* if do the read operation, get value from the register */
1484 if(ENET_PHY_READ == direction){
1485 *pvalue = (uint16_t)ENET_MAC_PHY_DATA;
1486 }
1487
1488 return enet_state;
1489 }
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
ENET_MAC_PHY_CTL_PA
#define ENET_MAC_PHY_CTL_PA
Definition: gd32f10x_enet.h:195
ENET_MAC_PHY_CTL
#define ENET_MAC_PHY_CTL
Definition: gd32f10x_enet.h:99
MAC_PHY_CTL_PR
#define MAC_PHY_CTL_PR(regval)
Definition: gd32f10x_enet.h:973
ENET_MAC_PHY_CTL_PW
#define ENET_MAC_PHY_CTL_PW
Definition: gd32f10x_enet.h:192
ENET_MAC_PHY_CTL_PR
#define ENET_MAC_PHY_CTL_PR
Definition: gd32f10x_enet.h:194
MAC_PHY_CTL_PA
#define MAC_PHY_CTL_PA(regval)
Definition: gd32f10x_enet.h:975
ENET_MAC_PHY_CTL_PB
#define ENET_MAC_PHY_CTL_PB
Definition: gd32f10x_enet.h:191
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
ENET_MAC_PHY_DATA
#define ENET_MAC_PHY_DATA
Definition: gd32f10x_enet.h:100
ErrStatus enet_phyloopback_disable ( void )

disable the loopback function of PHY chip

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 1520 of file gd32f10x_enet.c.

1521 {
1522 uint16_t temp_phy = 0U;
1523 ErrStatus phy_state = ERROR;
1524
1525 /* get the PHY configuration to update it */
1526 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1527
1528 /* disable the PHY loopback mode */
1529 temp_phy &= (uint16_t)~PHY_LOOPBACK;
1530
1531 /* update the PHY control register with the new configuration */
1532 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1533
1534 return phy_state;
1535 }
PHY_REG_BCR
#define PHY_REG_BCR
Definition: gd32f10x_enet.h:58
PHY_LOOPBACK
#define PHY_LOOPBACK
Definition: gd32f10x_enet.h:63
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
PHY_ADDRESS
#define PHY_ADDRESS
Definition: gd32f10x_enet.h:47
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
ErrStatus enet_phyloopback_enable ( void )

enable the loopback function of PHY chip

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 1497 of file gd32f10x_enet.c.

1498 {
1499 uint16_t temp_phy = 0U;
1500 ErrStatus phy_state = ERROR;
1501
1502 /* get the PHY configuration to update it */
1503 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1504
1505 /* enable the PHY loopback mode */
1506 temp_phy |= PHY_LOOPBACK;
1507
1508 /* update the PHY control register with the new configuration */
1509 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1510
1511 return phy_state;
1512 }
PHY_REG_BCR
#define PHY_REG_BCR
Definition: gd32f10x_enet.h:58
PHY_LOOPBACK
#define PHY_LOOPBACK
Definition: gd32f10x_enet.h:63
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
PHY_ADDRESS
#define PHY_ADDRESS
Definition: gd32f10x_enet.h:47
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
void enet_ptp_coarsecorrection_systime_update ( enet_ptp_systime_struct * systime_struct )

update system time in coarse method

Parameters
[in] | systime_struct | pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE
[out] | none
Return values
none

Definition at line 2850 of file gd32f10x_enet.c.

2851 {
2852 uint32_t subsecond_val;
2853 uint32_t carry_cfg;
2854
2855 subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
2856
2857 /* save the carry_cfg value */
2858 carry_cfg = ENET_PTP_TSADDEND_TMSA;
2859
2860 /* update the system time */
2861 enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
2862 enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE);
2863
2864 /* wait until the update is completed */
2865 while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){
2866 }
2867
2868 /* write back the carry_cfg value, then update */
2869 enet_ptp_timestamp_addend_config(carry_cfg);
2870 enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
2871 }
enet_ptp_timestamp_addend_config
void enet_ptp_timestamp_addend_config(uint32_t add)
adjusting the clock frequency only in fine update mode
Definition: gd32f10x_enet.c:2724
enet_ptp_flag_get
FlagStatus enet_ptp_flag_get(uint32_t flag)
get the ptp flag status
Definition: gd32f10x_enet.c:2908
enet_ptp_systime_struct::sign
uint32_t sign
Definition: gd32f10x_enet.h:873
enet_ptp_systime_struct::nanosecond
uint32_t nanosecond
Definition: gd32f10x_enet.h:872
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
enet_ptp_nanosecond_2_subsecond
uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
change nanosecond to subsecond
Definition: gd32f10x_enet.c:2600
enet_ptp_systime_struct::second
uint32_t second
Definition: gd32f10x_enet.h:871
enet_ptp_timestamp_update_config
void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time
Definition: gd32f10x_enet.c:2741
ENET_PTP_TSADDEND_TMSA
#define ENET_PTP_TSADDEND_TMSA
Definition: gd32f10x_enet.h:344
ENET_PTP_SYSTIME_UPDATE
Definition: gd32f10x_enet.h:1245
void enet_ptp_expected_time_config | ( | uint32_t | second,
 |  | uint32_t | nanosecond
 | ) |  |

configure the expected target time

Parameters
[in] | second | the expected target second time
[in] | nanosecond | the expected target nanosecond time (signed)
[out] | none
Return values
none

Definition at line 2754 of file gd32f10x_enet.c.

2755 {
2756 ENET_PTP_ETH = second;
2757 ENET_PTP_ETL = nanosecond;
2758 }
ENET_PTP_ETH
#define ENET_PTP_ETH
Definition: gd32f10x_enet.h:136
ENET_PTP_ETL
#define ENET_PTP_ETL
Definition: gd32f10x_enet.h:137
void enet_ptp_feature_disable ( uint32_t feature )

disable the PTP features

Parameters
[in] feature the feature of ENET PTP mode one or more parameters can be selected which are shown as below
  • ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames
  • ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger
[out] none
Return values
none

Definition at line 2630 of file gd32f10x_enet.c.

2631 {
2632 ENET_PTP_TSCTL &= ~feature;
2633 }
ENET_PTP_TSCTL
#define ENET_PTP_TSCTL
Definition: gd32f10x_enet.h:129
void enet_ptp_feature_enable ( uint32_t feature )

enable the PTP features

Parameters
[in] feature the feature of ENET PTP mode one or more parameters can be selected which are shown as below
  • ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames
  • ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger
[out] none
Return values
none

Definition at line 2616 of file gd32f10x_enet.c.

2617 {
2618 ENET_PTP_TSCTL |= feature;
2619 }
ENET_PTP_TSCTL
#define ENET_PTP_TSCTL
Definition: gd32f10x_enet.h:129
void enet_ptp_finecorrection_adjfreq ( int32_t carry_cfg )

adjust frequency in fine method by configure addend register

Parameters
[in] | carry_cfg | the value to be added to the accumulator register
[out] | none
Return values
none

Definition at line 2832 of file gd32f10x_enet.c.

2833 {
2834 /* re-configure the timestamp addend, then update */
2835 enet_ptp_timestamp_addend_config((uint32_t)carry_cfg);
2836 enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
2837 }
enet_ptp_timestamp_addend_config
void enet_ptp_timestamp_addend_config(uint32_t add)
adjusting the clock frequency only in fine update mode
Definition: gd32f10x_enet.c:2724
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
void enet_ptp_finecorrection_settime ( enet_ptp_systime_struct * systime_struct )

set system time in fine method

Parameters
[in] | systime_struct | pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE
[out] | none
Return values
none

Definition at line 2884 of file gd32f10x_enet.c.

2885 {
2886 uint32_t subsecond_val;
2887
2888 subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
2889
2890 /* initialize the system time */
2891 enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
2892 enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
2893
2894 /* wait until the system time initialzation finished */
2895 while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){
2896 }
2897 }
ENET_PTP_SYSTIME_INIT
Definition: gd32f10x_enet.h:1244
enet_ptp_flag_get
FlagStatus enet_ptp_flag_get(uint32_t flag)
get the ptp flag status
Definition: gd32f10x_enet.c:2908
enet_ptp_systime_struct::sign
uint32_t sign
Definition: gd32f10x_enet.h:873
enet_ptp_systime_struct::nanosecond
uint32_t nanosecond
Definition: gd32f10x_enet.h:872
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
enet_ptp_nanosecond_2_subsecond
uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
change nanosecond to subsecond
Definition: gd32f10x_enet.c:2600
enet_ptp_systime_struct::second
uint32_t second
Definition: gd32f10x_enet.h:871
enet_ptp_timestamp_update_config
void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time
Definition: gd32f10x_enet.c:2741
FlagStatus enet_ptp_flag_get ( uint32_t flag )

get the ptp flag status

Parameters
[in] flag ptp flag status to be checked
  • ENET_PTP_ADDEND_UPDATE: addend register update
  • ENET_PTP_SYSTIME_UPDATE: timestamp update
  • ENET_PTP_SYSTIME_INIT: timestamp initialize
[out] none
Return values
FlagStatus SET or RESET

Definition at line 2908 of file gd32f10x_enet.c.

2909 {
2910 FlagStatus bitstatus = RESET;
2911
2912 if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){
2913 bitstatus = SET;
2914 }
2915
2916 return bitstatus;
2917 }
ENET_PTP_TSCTL
#define ENET_PTP_TSCTL
Definition: gd32f10x_enet.h:129
uint32_t enet_ptp_nanosecond_2_subsecond ( uint32_t nanosecond )

change nanosecond to subsecond

Parameters
[in] | nanosecond | nanosecond value
[out] | none
Return values
the subsecond value

Definition at line 2600 of file gd32f10x_enet.c.

2601 {
2602 uint64_t val = nanosecond * 0x80000000Ull;
2603 val /= 1000000000U;
2604 return (uint32_t)val;
2605 }
void enet_ptp_normal_descriptors_chain_init | ( | enet_dmadirection_enum | direction,
 |  | enet_descriptors_struct * | desc_ptptab
 | ) |  |

initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function

Parameters
[in] direction the descriptors which users want to init, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA Tx descriptors
  • ENET_DMA_RX: DMA Rx descriptors
[in] | desc_ptptab | pointer to the first descriptor address of PTP Rx descriptor table
[out] | none
Return values
none

Definition at line 2120 of file gd32f10x_enet.c.

2121 {
2122 uint32_t num = 0U, count = 0U, maxsize = 0U;
2123 uint32_t desc_status = 0U, desc_bufsize = 0U;
2124 enet_descriptors_struct *desc, *desc_tab;
2125 uint8_t *buf;
2126
2127 /* if want to initialize DMA Tx descriptors */
2128 if (ENET_DMA_TX == direction){
2129 /* save a copy of the DMA Tx descriptors */
2130 desc_tab = txdesc_tab;
2131 buf = &tx_buff[0][0];
2132 count = ENET_TXBUF_NUM;
2133 maxsize = ENET_TXBUF_SIZE;
2134
2135 /* select chain mode, and enable transmit timestamp function */
2136 desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN;
2137
2138 /* configure DMA Tx descriptor table address register */
2139 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
2140 dma_current_txdesc = desc_tab;
2141 dma_current_ptp_txdesc = desc_ptptab;
2142 }else{
2143 /* if want to initialize DMA Rx descriptors */
2144 /* save a copy of the DMA Rx descriptors */
2145 desc_tab = rxdesc_tab;
2146 buf = &rx_buff[0][0];
2147 count = ENET_RXBUF_NUM;
2148 maxsize = ENET_RXBUF_SIZE;
2149
2150 /* enable receiving */
2151 desc_status = ENET_RDES0_DAV;
2152 /* select receive chained mode and set buffer1 size */
2153 desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
2154
2155 /* configure DMA Rx descriptor table address register */
2156 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
2157 dma_current_rxdesc = desc_tab;
2158 dma_current_ptp_rxdesc = desc_ptptab;
2159 }
2160
2161 /* configure each descriptor */
2162 for(num = 0U; num < count; num++){
2163 /* get the pointer to the next descriptor of the descriptor table */
2164 desc = desc_tab + num;
2165
2166 /* configure descriptors */
2167 desc->status = desc_status;
2168 desc->control_buffer_size = desc_bufsize;
2169 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
2170
2171 /* if is not the last descriptor */
2172 if(num < (count - 1U)){
2173 /* configure the next descriptor address */
2174 desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
2175 }else{
2176 /* when it is the last descriptor, the next descriptor address
2177 equals to first descriptor address in descriptor table */
2178 desc->buffer2_next_desc_addr = (uint32_t)desc_tab;
2179 }
2180 /* set desc_ptptab equal to desc_tab */
2181 (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
2182 (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
2183 }
2184 /* when it is the last ptp descriptor, preserve the first descriptor
2185 address of desc_ptptab in ptp descriptor status */
2186 (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
2187 }
ENET_RXBUF_NUM
#define ENET_RXBUF_NUM
Definition: gd32f10x_enet.h:25
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_TXBUF_SIZE
#define ENET_TXBUF_SIZE
Definition: gd32f10x_enet.h:37
ENET_TXBUF_NUM
#define ENET_TXBUF_NUM
Definition: gd32f10x_enet.h:29
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
ENET_TDES0_TTSEN
#define ENET_TDES0_TTSEN
Definition: gd32f10x_enet.h:467
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_TCHM
#define ENET_TDES0_TCHM
Definition: gd32f10x_enet.h:464
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_RXBUF_SIZE
#define ENET_RXBUF_SIZE
Definition: gd32f10x_enet.h:33
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_ptp_normal_descriptors_ring_init | ( | enet_dmadirection_enum | direction,
 |  | enet_descriptors_struct * | desc_ptptab
 | ) |  |

initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function

Parameters
[in] direction the descriptors which users want to init, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA Tx descriptors
  • ENET_DMA_RX: DMA Rx descriptors
[in] | desc_ptptab | pointer to the first descriptor address of PTP Rx descriptor table
[out] | none
Return values
none

Definition at line 2199 of file gd32f10x_enet.c.

2200 {
2201 uint32_t num = 0U, count = 0U, maxsize = 0U;
2202 uint32_t desc_status = 0U, desc_bufsize = 0U;
2203 enet_descriptors_struct *desc, *desc_tab;
2204 uint8_t *buf;
2205
2206 /* configure descriptor skip length */
2207 ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
2208 ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
2209
2210 /* if want to initialize DMA Tx descriptors */
2211 if (ENET_DMA_TX == direction){
2212 /* save a copy of the DMA Tx descriptors */
2213 desc_tab = txdesc_tab;
2214 buf = &tx_buff[0][0];
2215 count = ENET_TXBUF_NUM;
2216 maxsize = ENET_TXBUF_SIZE;
2217
2218 /* select ring mode, and enable transmit timestamp function */
2219 desc_status = ENET_TDES0_TTSEN;
2220
2221 /* configure DMA Tx descriptor table address register */
2222 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
2223 dma_current_txdesc = desc_tab;
2224 dma_current_ptp_txdesc = desc_ptptab;
2225 }else{
2226 /* if want to initialize DMA Rx descriptors */
2227 /* save a copy of the DMA Rx descriptors */
2228 desc_tab = rxdesc_tab;
2229 buf = &rx_buff[0][0];
2230 count = ENET_RXBUF_NUM;
2231 maxsize = ENET_RXBUF_SIZE;
2232
2233 /* enable receiving */
2234 desc_status = ENET_RDES0_DAV;
2235 /* select receive ring mode and set buffer1 size */
2236 desc_bufsize = (uint32_t)ENET_RXBUF_SIZE;
2237
2238 /* configure DMA Rx descriptor table address register */
2239 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
2240 dma_current_rxdesc = desc_tab;
2241 dma_current_ptp_rxdesc = desc_ptptab;
2242 }
2243
2244 /* configure each descriptor */
2245 for(num = 0U; num < count; num++){
2246 /* get the pointer to the next descriptor of the descriptor table */
2247 desc = desc_tab + num;
2248
2249 /* configure descriptors */
2250 desc->status = desc_status;
2251 desc->control_buffer_size = desc_bufsize;
2252 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
2253
2254 /* when it is the last descriptor */
2255 if(num == (count - 1U)){
2256 if (ENET_DMA_TX == direction){
2257 /* configure transmit end of ring mode */
2258 desc->status |= ENET_TDES0_TERM;
2259 }else{
2260 /* configure receive end of ring mode */
2261 desc->control_buffer_size |= ENET_RDES1_RERM;
2262 }
2263 }
2264 /* set desc_ptptab equal to desc_tab */
2265 (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
2266 (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
2267 }
2268 /* when it is the last ptp descriptor, preserve the first descriptor
2269 address of desc_ptptab in ptp descriptor status */
2270 (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
2271 }
ENET_RXBUF_NUM
#define ENET_RXBUF_NUM
Definition: gd32f10x_enet.h:25
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
ENET_DMA_BCTL_DPSL
#define ENET_DMA_BCTL_DPSL
Definition: gd32f10x_enet.h:355
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_TDES0_TERM
#define ENET_TDES0_TERM
Definition: gd32f10x_enet.h:465
ENET_TXBUF_SIZE
#define ENET_TXBUF_SIZE
Definition: gd32f10x_enet.h:37
ENET_TXBUF_NUM
#define ENET_TXBUF_NUM
Definition: gd32f10x_enet.h:29
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
ENET_TDES0_TTSEN
#define ENET_TDES0_TTSEN
Definition: gd32f10x_enet.h:467
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
DMA_BCTL_DPSL
#define DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1084
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_RXBUF_SIZE
#define ENET_RXBUF_SIZE
Definition: gd32f10x_enet.h:33
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_ptp_pps_output_frequency_config ( uint32_t freq )
void enet_ptp_start | ( | int32_t | updatemethod,
 |  | uint32_t | init_sec,
 |  | uint32_t | init_subsec,
 |  | uint32_t | carry_cfg,
 |  | uint32_t | accuracy_cfg
 | ) |  |

configure and start PTP timestamp counter

Parameters
[in] updatemethod method for updating
  • ENET_PTP_FINEMODE: fine correction method
  • ENET_PTP_COARSEMODE: coarse correction method
[in] | init_sec | second value for initializing system time
[in] | init_subsec | subsecond value for initializing system time
[in] | carry_cfg | the value to be added to the accumulator register (in fine method is used)
[in] | accuracy_cfg | the value to be added to the subsecond value of system time
[out] | none
Return values
none

Definition at line 2798 of file gd32f10x_enet.c.

2799 {
2800 /* mask the timestamp trigger interrupt */
2801 enet_interrupt_disable(ENET_MAC_INT_TMSTIM);
2802
2803 /* enable timestamp */
2804 enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP);
2805
2806 /* configure system time subsecond increment based on the PTP clock frequency */
2807 enet_ptp_subsecond_increment_config(accuracy_cfg);
2808
2809 if(ENET_PTP_FINEMODE == updatemethod){
2810 /* fine correction method: configure the timestamp addend, then update */
2811 enet_ptp_timestamp_addend_config(carry_cfg);
2812 enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
2813 /* wait until update is completed */
2814 while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){
2815 }
2816 }
2817
2818 /* choose the fine correction method */
2819 enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod);
2820
2821 /* initialize the system time */
2822 enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec);
2823 enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
2824 }
ENET_PTP_SYSTIME_INIT
Definition: gd32f10x_enet.h:1244
ENET_RXTX_TIMESTAMP
#define ENET_RXTX_TIMESTAMP
Definition: gd32f10x_enet.h:1063
enet_ptp_timestamp_addend_config
void enet_ptp_timestamp_addend_config(uint32_t add)
adjusting the clock frequency only in fine update mode
Definition: gd32f10x_enet.c:2724
ENET_PTP_ADD_TO_TIME
#define ENET_PTP_ADD_TO_TIME
Definition: gd32f10x_enet.h:1080
enet_ptp_flag_get
FlagStatus enet_ptp_flag_get(uint32_t flag)
get the ptp flag status
Definition: gd32f10x_enet.c:2908
enet_ptp_feature_enable
void enet_ptp_feature_enable(uint32_t feature)
enable the PTP features
Definition: gd32f10x_enet.c:2616
enet_interrupt_disable
void enet_interrupt_disable(enet_int_enum enet_int)
disable ENET MAC/MSC/DMA interrupt
Definition: gd32f10x_enet.c:1158
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
ENET_PTP_FINEMODE
Definition: gd32f10x_enet.h:1247
ENET_MAC_INT_TMSTIM
Definition: gd32f10x_enet.h:633
enet_ptp_timestamp_update_config
void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time
Definition: gd32f10x_enet.c:2741
enet_ptp_function_enum
enet_ptp_function_enum
Definition: gd32f10x_enet.h:1243
enet_ptp_subsecond_increment_config
void enet_ptp_subsecond_increment_config(uint32_t subsecond)
configure system time subsecond increment value
Definition: gd32f10x_enet.c:2713
uint32_t enet_ptp_subsecond_2_nanosecond ( uint32_t subsecond )

change subsecond to nanosecond

Parameters
[in] | subsecond | subsecond value
[out] | none
Return values
the nanosecond value

Definition at line 2587 of file gd32f10x_enet.c.

2588 {
2589 uint64_t val = subsecond * 1000000000Ull;
2590 val >>= 31;
2591 return (uint32_t)val;
2592 }
void enet_ptp_subsecond_increment_config ( uint32_t subsecond )

configure system time subsecond increment value

Parameters
[in] | subsecond | the value will be added to the subsecond value of system time, this value must be between 0 and 0xFF
[out] | none
Return values
none

Definition at line 2713 of file gd32f10x_enet.c.

2714 {
2715 ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond);
2716 }
PTP_SSINC_STMSSI
#define PTP_SSINC_STMSSI(regval)
Definition: gd32f10x_enet.h:1067
ENET_PTP_SSINC
#define ENET_PTP_SSINC
Definition: gd32f10x_enet.h:130
void enet_ptp_system_time_get ( enet_ptp_systime_struct * systime_struct )

get the current system time

Parameters
[in] | none
[out] | systime_struct | pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE
Return values
none

Definition at line 2771 of file gd32f10x_enet.c.

2772 {
2773 uint32_t temp_sec = 0U, temp_subs = 0U;
2774
2775 /* get the value of sysytem time registers */
2776 temp_sec = (uint32_t)ENET_PTP_TSH;
2777 temp_subs = (uint32_t)ENET_PTP_TSL;
2778
2779 /* get sysytem time and construct the enet_ptp_systime_struct structure */
2780 systime_struct->second = temp_sec;
2781 systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs);
2782 systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond);
2783 systime_struct->sign = GET_PTP_TSL_STS(temp_subs);
2784 }
enet_ptp_systime_struct::sign
uint32_t sign
Definition: gd32f10x_enet.h:873
enet_ptp_subsecond_2_nanosecond
uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond)
change subsecond to nanosecond
Definition: gd32f10x_enet.c:2587
enet_ptp_systime_struct::nanosecond
uint32_t nanosecond
Definition: gd32f10x_enet.h:872
enet_ptp_systime_struct::second
uint32_t second
Definition: gd32f10x_enet.h:871
ENET_PTP_TSL
#define ENET_PTP_TSL
Definition: gd32f10x_enet.h:132
ENET_PTP_TSH
#define ENET_PTP_TSH
Definition: gd32f10x_enet.h:131
GET_PTP_TSL_STMSS
#define GET_PTP_TSL_STMSS(regval)
Definition: gd32f10x_enet.h:1070
GET_PTP_TSL_STS
#define GET_PTP_TSL_STS(regval)
Definition: gd32f10x_enet.h:1075
void enet_ptp_timestamp_addend_config ( uint32_t add )

adjusting the clock frequency only in fine update mode

Parameters
[in] | add | the value will be added to the accumulator register to achieve time synchronization
[out] | none
Return values
none

Definition at line 2724 of file gd32f10x_enet.c.

2725 {
2726 ENET_PTP_TSADDEND = add;
2727 }
ENET_PTP_TSADDEND
#define ENET_PTP_TSADDEND
Definition: gd32f10x_enet.h:135
ErrStatus enet_ptp_timestamp_function_config ( enet_ptp_function_enum func )

configure the PTP timestamp function

Parameters
[in] func only one parameter can be selected which is shown as below
  • ENET_PTP_ADDEND_UPDATE: addend register update
  • ENET_PTP_SYSTIME_UPDATE: timestamp update
  • ENET_PTP_SYSTIME_INIT: timestamp initialize
  • ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating
  • ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 2647 of file gd32f10x_enet.c.

2648 {
2649 uint32_t temp_config = 0U, temp_state = 0U;
2650 uint32_t timeout = 0U;
2651 ErrStatus enet_state = SUCCESS;
2652
2653 switch(func){
2654 case ENET_PTP_ADDEND_UPDATE:
2655 /* this bit must be read as zero before application set it */
2656 do{
2657 temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU;
2658 timeout++;
2659 }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
2660 /* return ERROR due to timeout */
2661 if(ENET_DELAY_TO == timeout){
2662 enet_state = ERROR;
2663 }else{
2664 ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU;
2665 }
2666 break;
2667 case ENET_PTP_SYSTIME_UPDATE:
2668 /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */
2669 do{
2670 temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI);
2671 timeout++;
2672 }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
2673 /* return ERROR due to timeout */
2674 if(ENET_DELAY_TO == timeout){
2675 enet_state = ERROR;
2676 }else{
2677 ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU;
2678 }
2679 break;
2680 case ENET_PTP_SYSTIME_INIT:
2681 /* this bit must be read as zero before application set it */
2682 do{
2683 temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI;
2684 timeout++;
2685 }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
2686 /* return ERROR due to timeout */
2687 if(ENET_DELAY_TO == timeout){
2688 enet_state = ERROR;
2689 }else{
2690 ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI;
2691 }
2692 break;
2693 default:
2694 temp_config = (uint32_t)func & (~BIT(31));
2695 if(RESET != ((uint32_t)func & BIT(31))){
2696 ENET_PTP_TSCTL |= temp_config;
2697 }else{
2698 ENET_PTP_TSCTL &= ~temp_config;
2699 }
2700 break;
2701 }
2702
2703 return enet_state;
2704 }
ENET_PTP_SYSTIME_INIT
Definition: gd32f10x_enet.h:1244
ENET_PTP_TSCTL_TMSSTU
#define ENET_PTP_TSCTL_TMSSTU
Definition: gd32f10x_enet.h:322
ENET_PTP_TSCTL_TMSARU
#define ENET_PTP_TSCTL_TMSARU
Definition: gd32f10x_enet.h:324
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
ENET_PTP_TSCTL
#define ENET_PTP_TSCTL
Definition: gd32f10x_enet.h:129
ENET_PTP_TSCTL_TMSSTI
#define ENET_PTP_TSCTL_TMSSTI
Definition: gd32f10x_enet.h:321
ENET_PTP_SYSTIME_UPDATE
Definition: gd32f10x_enet.h:1245
void enet_ptp_timestamp_update_config | ( | uint32_t | sign,
 |  | uint32_t | second,
 |  | uint32_t | subsecond
 | ) |  |

initialize or add/subtract to second of the system time

Parameters
[in] sign timestamp update positive or negative sign, only one parameter can be selected which is shown as below
  • ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time
  • ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time
[in] | second | initializing or adding/subtracting to second of the system time
[in] | subsecond | the current subsecond of the system time with 0.46 ns accuracy if required accuracy is 20 ns
[out] | none
Return values
none

Definition at line 2741 of file gd32f10x_enet.c.

2742 {
2743 ENET_PTP_TSUH = second;
2744 ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond);
2745 }
ENET_PTP_TSUL
#define ENET_PTP_TSUL
Definition: gd32f10x_enet.h:134
ENET_PTP_TSUH
#define ENET_PTP_TSUH
Definition: gd32f10x_enet.h:133
PTP_TSUL_TMSUSS
#define PTP_TSUL_TMSUSS(regval)
Definition: gd32f10x_enet.h:1078
ErrStatus enet_ptpframe_receive_normal_mode | ( | uint8_t * | buffer,
 |  | uint32_t | bufsize,
 |  | uint32_t | timestamp[]
 | ) |  |

receive a packet data with timestamp values to application buffer, when the DMA is in normal mode

Parameters
[in] | bufsize | the size of buffer which is the parameter in function
[out] | timestamp | pointer to the table which stores the timestamp high and low
[out] | buffer | pointer to the application buffer note – if the input is NULL, user should copy data in application by himself
Return values
ErrStatus SUCCESS or ERROR

Definition at line 2281 of file gd32f10x_enet.c.

2282 {
2283 uint32_t offset = 0U, size = 0U;
2284
2285 /* the descriptor is busy due to own by the DMA */
2286 if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
2287 return ERROR;
2288 }
2289
2290 /* if buffer pointer is null, indicates that users has copied data in application */
2291 if(NULL != buffer){
2292 /* if no error occurs, and the frame uses only one descriptor */
2293 if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
2294 ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
2295 ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
2296
2297 /* get the frame length except CRC */
2298 size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U;
2299
2300 /* to avoid situation that the frame size exceeds the buffer length */
2301 if(size > bufsize){
2302 return ERROR;
2303 }
2304
2305 /* copy data from Rx buffer to application buffer */
2306 for(offset = 0U; offset < size; offset++){
2307 (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset));
2308 }
2309
2310 }else{
2311 return ERROR;
2312 }
2313 }
2314 /* copy timestamp value from Rx descriptor to application array */
2315 timestamp[0] = dma_current_rxdesc->buffer1_addr;
2316 timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr;
2317
2318 dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ;
2319 dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr;
2320
2321 /* enable reception, descriptor is owned by DMA */
2322 dma_current_rxdesc->status = ENET_RDES0_DAV;
2323
2324 /* check Rx buffer unavailable flag status */
2325 if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
2326 /* clear RBU flag */
2327 ENET_DMA_STAT = ENET_DMA_STAT_RBU;
2328 /* resume DMA reception by writing to the RPEN register*/
2329 ENET_DMA_RPEN = 0U;
2330 }
2331
2332
2333 /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */
2334 /* chained mode */
2335 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
2336 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
2337 /* if it is the last ptp descriptor */
2338 if(0U != dma_current_ptp_rxdesc->status){
2339 /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
2340 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2341 }else{
2342 /* ponter to the next ptp descriptor */
2343 dma_current_ptp_rxdesc++;
2344 }
2345 }else{
2346 /* ring mode */
2347 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
2348 /* if is the last descriptor in table, the next descriptor is the table header */
2349 dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
2350 /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table,
2351 use the same table with RxDMA descriptor */
2352 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2353 }else{
2354 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
2355 dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
2356 dma_current_ptp_rxdesc ++;
2357 }
2358 }
2359
2360 return SUCCESS;
2361 }
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
GET_RDES0_FRML
#define GET_RDES0_FRML(regval)
Definition: gd32f10x_enet.h:1217
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ETH_DMARXDESC_SIZE
#define ETH_DMARXDESC_SIZE
Definition: gd32f10x_enet.h:1241
ENET_DMA_STAT_RBU
#define ENET_DMA_STAT_RBU
Definition: gd32f10x_enet.h:384
ENET_RDES0_FDES
#define ENET_RDES0_FDES
Definition: gd32f10x_enet.h:495
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
ENET_DMA_RPEN
#define ENET_DMA_RPEN
Definition: gd32f10x_enet.h:141
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_RDES0_ERRS
#define ENET_RDES0_ERRS
Definition: gd32f10x_enet.h:501
NULL
#define NULL
Definition: usbd_std.h:20
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
ENET_RDES0_LDES
#define ENET_RDES0_LDES
Definition: gd32f10x_enet.h:494
ErrStatus enet_ptpframe_transmit_normal_mode | ( | uint8_t * | buffer,
 |  | uint32_t | length,
 |  | uint32_t | timestamp[]
 | ) |  |

send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode

Parameters
[in] | buffer | pointer on the application buffer note – if the input is NULL, user should copy data in application by himself
[in] | length | the length of frame data to be transmitted
[out] | timestamp | pointer to the table which stores the timestamp high and low note – if the input is NULL, timestamp is ignored
Return values
ErrStatus SUCCESS or ERROR

Definition at line 2372 of file gd32f10x_enet.c.

2373 {
2374 uint32_t offset = 0U, timeout = 0U;
2375 uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag;
2376
2377 /* the descriptor is busy due to own by the DMA */
2378 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
2379 return ERROR;
2380 }
2381
2382 /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */
2383 if(length > ENET_MAX_FRAME_SIZE){
2384 return ERROR;
2385 }
2386
2387 /* if buffer pointer is null, indicates that users has handled data in application */
2388 if(NULL != buffer){
2389 /* copy frame data from application buffer to Tx buffer */
2390 for(offset = 0U; offset < length; offset++){
2391 (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
2392 }
2393 }
2394 /* set the frame length */
2395 dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF);
2396 /* set the segment of frame, frame is transmitted in one descriptor */
2397 dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
2398 /* enable the DMA transmission */
2399 dma_current_txdesc->status |= ENET_TDES0_DAV;
2400
2401 /* check Tx buffer unavailable flag status */
2402 dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
2403 dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
2404
2405 if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
2406 /* clear TBU and TU flag */
2407 ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
2408 /* resume DMA transmission by writing to the TPEN register*/
2409 ENET_DMA_TPEN = 0U;
2410 }
2411
2412 /* if timestamp pointer is null, indicates that users don't care timestamp in application */
2413 if(NULL != timestamp){
2414 /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */
2415 do{
2416 tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS);
2417 timeout++;
2418 }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO));
2419
2420 /* return ERROR due to timeout */
2421 if(ENET_DELAY_TO == timeout){
2422 return ERROR;
2423 }
2424
2425 /* clear the ENET_TDES0_TTMSS flag */
2426 dma_current_txdesc->status &= ~ENET_TDES0_TTMSS;
2427 /* get the timestamp value of the transmit frame */
2428 timestamp[0] = dma_current_txdesc->buffer1_addr;
2429 timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr;
2430 }
2431 dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ;
2432 dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr;
2433
2434 /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */
2435 /* chained mode */
2436 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
2437 dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr);
2438 /* if it is the last ptp descriptor */
2439 if(0U != dma_current_ptp_txdesc->status){
2440 /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
2441 dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
2442 }else{
2443 /* ponter to the next ptp descriptor */
2444 dma_current_ptp_txdesc++;
2445 }
2446 }else{
2447 /* ring mode */
2448 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
2449 /* if is the last descriptor in table, the next descriptor is the table header */
2450 dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
2451 /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table,
2452 use the same table with TxDMA descriptor */
2453 dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
2454 }else{
2455 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
2456 dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
2457 dma_current_ptp_txdesc ++;
2458 }
2459 }
2460 return SUCCESS;
2461 }
ETH_DMATXDESC_SIZE
#define ETH_DMATXDESC_SIZE
Definition: gd32f10x_enet.h:1240
ENET_MAX_FRAME_SIZE
#define ENET_MAX_FRAME_SIZE
Definition: gd32f10x_enet.h:1256
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_DMA_STAT_TU
#define ENET_DMA_STAT_TU
Definition: gd32f10x_enet.h:382
ENET_TDES0_TERM
#define ENET_TDES0_TERM
Definition: gd32f10x_enet.h:465
ENET_DMA_STAT_TBU
#define ENET_DMA_STAT_TBU
Definition: gd32f10x_enet.h:379
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ENET_TDES0_FSG
#define ENET_TDES0_FSG
Definition: gd32f10x_enet.h:470
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
ENET_DMA_TPEN
#define ENET_DMA_TPEN
Definition: gd32f10x_enet.h:140
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_TCHM
#define ENET_TDES0_TCHM
Definition: gd32f10x_enet.h:464
NULL
#define NULL
Definition: usbd_std.h:20
ENET_TDES0_TTMSS
#define ENET_TDES0_TTMSS
Definition: gd32f10x_enet.h:463
ENET_TDES0_LSG
#define ENET_TDES0_LSG
Definition: gd32f10x_enet.h:471
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
ENET_TDES0_DAV
#define ENET_TDES0_DAV
Definition: gd32f10x_enet.h:473
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_registers_get | ( | enet_registers_type_enum | type,
 |  | uint32_t * | preg,
 |  | uint32_t | num
 | ) |  |

put registers value into the application buffer

Parameters
[in] type register type which will be get, refer to enet_registers_type_enum, only one parameter can be selected which is shown as below
  • ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH
  • ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT
  • ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL
  • ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR
[in] | num | the number of registers that the user want to get
[out] | preg | the application buffer pointer for storing the register value
Return values
none

Definition at line 1304 of file gd32f10x_enet.c.

1305 {
1306 uint32_t offset = 0U, max = 0U, limit = 0U;
1307
1308 offset = (uint32_t)type;
1309 max = (uint32_t)type + num;
1310 limit = sizeof(enet_reg_tab)/sizeof(uint16_t);
1311
1312 /* prevent element in this array is out of range */
1313 if(max > limit){
1314 max = limit;
1315 }
1316
1317 for(; offset < max; offset++){
1318 /* get value of the corresponding register */
1319 *preg = REG32((ENET) + enet_reg_tab[offset]);
1320 preg++;
1321 }
1322 }
ENET
#define ENET
Definition: gd32f10x_enet.h:92
void enet_rx_desc_delay_receive_complete_interrupt | ( | enet_descriptors_struct * | desc,
 |  | uint32_t | delay_time
 | ) |  |
void enet_rx_desc_immediate_receive_complete_interrupt ( enet_descriptors_struct * desc )

when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set

Parameters
[in] | desc | the descriptor pointer which users want to configure
[out] | none
Return values
none

Definition at line 2032 of file gd32f10x_enet.c.

2033 {
2034 desc->control_buffer_size &= ~ENET_RDES1_DINTC;
2035 }
ENET_RDES1_DINTC
#define ENET_RDES1_DINTC
Definition: gd32f10x_enet.h:511
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
void enet_rx_disable ( void )

ENET Rx function disable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1286 of file gd32f10x_enet.c.

1287 {
1288 ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE;
1289 ENET_MAC_CFG &= ~ENET_MAC_CFG_REN;
1290 }
ENET_DMA_CTL_SRE
#define ENET_DMA_CTL_SRE
Definition: gd32f10x_enet.h:400
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_MAC_CFG_REN
#define ENET_MAC_CFG_REN
Definition: gd32f10x_enet.h:155
void enet_rx_enable ( void )

ENET Rx function enable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1274 of file gd32f10x_enet.c.

1275 {
1276 ENET_MAC_CFG |= ENET_MAC_CFG_REN;
1277 ENET_DMA_CTL |= ENET_DMA_CTL_SRE;
1278 }
ENET_DMA_CTL_SRE
#define ENET_DMA_CTL_SRE
Definition: gd32f10x_enet.h:400
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_MAC_CFG_REN
#define ENET_MAC_CFG_REN
Definition: gd32f10x_enet.h:155
void enet_rxframe_drop ( void )

drop current receive frame

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 2043 of file gd32f10x_enet.c.

2044 {
2045 /* enable reception, descriptor is owned by DMA */
2046 dma_current_rxdesc->status = ENET_RDES0_DAV;
2047
2048 /* chained mode */
2049 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
2050 if(NULL != dma_current_ptp_rxdesc){
2051 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
2052 /* if it is the last ptp descriptor */
2053 if(0U != dma_current_ptp_rxdesc->status){
2054 /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
2055 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2056 }else{
2057 /* ponter to the next ptp descriptor */
2058 dma_current_ptp_rxdesc++;
2059 }
2060 }else{
2061 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
2062 }
2063
2064 }else{
2065 /* ring mode */
2066 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
2067 /* if is the last descriptor in table, the next descriptor is the table header */
2068 dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
2069 if(NULL != dma_current_ptp_rxdesc){
2070 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2071 }
2072 }else{
2073 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
2074 dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
2075 if(NULL != dma_current_ptp_rxdesc){
2076 dma_current_ptp_rxdesc++;
2077 }
2078 }
2079 }
2080 }
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ETH_DMARXDESC_SIZE
#define ETH_DMARXDESC_SIZE
Definition: gd32f10x_enet.h:1241
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
NULL
#define NULL
Definition: usbd_std.h:20
uint32_t enet_rxframe_size_get ( void )

check receive frame valid and return frame size

Parameters
[in] | none
[out] | none
Return values
size of received frame: 0x0 - 0x3FFF

Definition at line 591 of file gd32f10x_enet.c.

592 {
593 uint32_t size = 0U;
594 uint32_t status;
595
596 /* get rdes0 information of current RxDMA descriptor */
597 status = dma_current_rxdesc->status;
598
599 /* if the desciptor is owned by DMA */
600 if((uint32_t)RESET != (status & ENET_RDES0_DAV)){
601 return 0U;
602 }
603
604 /* if has any error, or the frame uses two or more descriptors */
605 if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) ||
606 (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) ||
607 (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){
608 /* drop current receive frame */
609 enet_rxframe_drop();
610
611 return 0U;
612 }
613
614 /* if is an ethernet-type frame, and IP frame payload error occurred */
615 if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) &&
616 (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){
617 /* drop current receive frame */
618 enet_rxframe_drop();
619
620 return 0U;
621 }
622
623 /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */
624 if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) &&
625 (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) &&
626 (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) &&
627 (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){
628 /* get the size of the received data including CRC */
629 size = GET_RDES0_FRML(status);
630 /* substract the CRC size */
631 size = size - 4U;
632 }
633
634 /* return packet size */
635 return size;
636 }
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
ENET_RDES0_PCERR
#define ENET_RDES0_PCERR
Definition: gd32f10x_enet.h:486
enet_rxframe_drop
void enet_rxframe_drop(void)
drop current receive frame
Definition: gd32f10x_enet.c:2043
GET_RDES0_FRML
#define GET_RDES0_FRML(regval)
Definition: gd32f10x_enet.h:1217
ENET_RDES0_FRMT
#define ENET_RDES0_FRMT
Definition: gd32f10x_enet.h:491
ENET_RDES0_FDES
#define ENET_RDES0_FDES
Definition: gd32f10x_enet.h:495
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_RDES0_ERRS
#define ENET_RDES0_ERRS
Definition: gd32f10x_enet.h:501
ENET_RDES0_LDES
#define ENET_RDES0_LDES
Definition: gd32f10x_enet.h:494
void enet_rxprocess_check_recovery ( void )

check and recover the Rx process

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1788 of file gd32f10x_enet.c.

1789 {
1790 uint32_t status;
1791
1792 /* get DAV information of current RxDMA descriptor */
1793 status = dma_current_rxdesc->status;
1794 status &= ENET_RDES0_DAV;
1795
1796 /* if current descriptor is owned by DMA, but the descriptor address mismatches with
1797 receive descriptor address pointer updated by RxDMA controller */
1798 if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) &&
1799 (ENET_RDES0_DAV == status)){
1800 dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR;
1801 }
1802 }
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_DMA_CRDADDR
#define ENET_DMA_CRDADDR
Definition: gd32f10x_enet.h:149
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ErrStatus enet_software_reset ( void )

reset all core internal registers located in CLK_TX and CLK_RX

Parameters
[in] | none
[out] | none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 562 of file gd32f10x_enet.c.

563 {
564 uint32_t timeout = 0U;
565 ErrStatus enet_state = ERROR;
566 uint32_t dma_flag;
567
568 /* reset all core internal registers located in CLK_TX and CLK_RX */
569 ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR;
570
571 /* wait for reset operation complete */
572 do{
573 dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR);
574 timeout++;
575 }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout));
576
577 /* reset operation complete */
578 if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){
579 enet_state = SUCCESS;
580 }
581
582 return enet_state;
583 }
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_DMA_BCTL_SWR
#define ENET_DMA_BCTL_SWR
Definition: gd32f10x_enet.h:353
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
void enet_transmit_checksum_config | ( | enet_descriptors_struct * | desc,
 |  | uint32_t | checksum
 | ) |  |

configure the transmit IP frame checksum offload calculation and insertion

Parameters
[in] | desc | the descriptor pointer which users want to configure
[in] checksum IP frame checksum configuration only one parameter can be selected which is shown as below
  • ENET_CHECKSUM_DISABLE: checksum insertion disabled
  • ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled
  • ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header
  • ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated
[out] | none
Return values
none

Definition at line 935 of file gd32f10x_enet.c.

936 {
937 desc->status &= ~ENET_TDES0_CM;
938 desc->status |= checksum;
939 }
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_CM
#define ENET_TDES0_CM
Definition: gd32f10x_enet.h:466
void enet_tx_disable ( void )

ENET Tx function disable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1261 of file gd32f10x_enet.c.

1262 {
1263 ENET_DMA_CTL &= ~ENET_DMA_CTL_STE;
1264 enet_txfifo_flush();
1265 ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN;
1266 }
ENET_DMA_CTL_STE
#define ENET_DMA_CTL_STE
Definition: gd32f10x_enet.h:405
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
enet_txfifo_flush
ErrStatus enet_txfifo_flush(void)
flush the ENET transmit FIFO, and wait until the flush operation completes
Definition: gd32f10x_enet.c:1810
ENET_MAC_CFG_TEN
#define ENET_MAC_CFG_TEN
Definition: gd32f10x_enet.h:156
void enet_tx_enable ( void )

ENET Tx function enable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1248 of file gd32f10x_enet.c.

1249 {
1250 ENET_MAC_CFG |= ENET_MAC_CFG_TEN;
1251 enet_txfifo_flush();
1252 ENET_DMA_CTL |= ENET_DMA_CTL_STE;
1253 }
ENET_DMA_CTL_STE
#define ENET_DMA_CTL_STE
Definition: gd32f10x_enet.h:405
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
enet_txfifo_flush
ErrStatus enet_txfifo_flush(void)
flush the ENET transmit FIFO, and wait until the flush operation completes
Definition: gd32f10x_enet.c:1810
ENET_MAC_CFG_TEN
#define ENET_MAC_CFG_TEN
Definition: gd32f10x_enet.h:156
ErrStatus enet_txfifo_flush ( void )

flush the ENET transmit FIFO, and wait until the flush operation completes

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 1810 of file gd32f10x_enet.c.

1811 {
1812 uint32_t flush_state;
1813 uint32_t timeout = 0U;
1814 ErrStatus enet_state = ERROR;
1815
1816 /* set the FTF bit for flushing transmit FIFO */
1817 ENET_DMA_CTL |= ENET_DMA_CTL_FTF;
1818 /* wait until the flush operation completes */
1819 do{
1820 flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF;
1821 timeout++;
1822 }while((RESET != flush_state) && (timeout < ENET_DELAY_TO));
1823 /* return ERROR due to timeout */
1824 if(RESET == flush_state){
1825 enet_state = SUCCESS;
1826 }
1827
1828 return enet_state;
1829 }
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_DMA_CTL_FTF
#define ENET_DMA_CTL_FTF
Definition: gd32f10x_enet.h:407
void enet_wum_feature_disable ( uint32_t feature )

disable wakeup management features

Parameters
[in] feature one or more parameters can be selected which are shown as below
  • ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception
  • ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception
  • ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame
[out] none
Return values
none

Definition at line 2514 of file gd32f10x_enet.c.

2515 {
2516 ENET_MAC_WUM &= (~feature);
2517 }
ENET_MAC_WUM
#define ENET_MAC_WUM
Definition: gd32f10x_enet.h:105
void enet_wum_feature_enable ( uint32_t feature )

enable wakeup management features

Parameters
[in] feature one or more parameters can be selected which are shown as below
  • ENET_WUM_POWER_DOWN: power down mode
  • ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception
  • ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception
  • ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame
[out] none
Return values
none

Definition at line 2500 of file gd32f10x_enet.c.

2501 {
2502 ENET_MAC_WUM |= feature;
2503 }
ENET_MAC_WUM
#define ENET_MAC_WUM
Definition: gd32f10x_enet.h:105
void enet_wum_filter_config ( uint32_t pdata[] )

set the remote wakeup frame registers

Parameters
[in] | pdata | pointer to buffer data which is written to remote wakeup frame registers (8 words total)
[out] | none
Return values
none

Definition at line 2480 of file gd32f10x_enet.c.

2481 {
2482 uint32_t num = 0U;
2483
2484 /* configure ENET_MAC_RWFF register */
2485 for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){
2486 ENET_MAC_RWFF = pdata[num];
2487 }
2488 }
ETH_WAKEUP_REGISTER_LENGTH
#define ETH_WAKEUP_REGISTER_LENGTH
Definition: gd32f10x_enet.h:1253
ENET_MAC_RWFF
#define ENET_MAC_RWFF
Definition: gd32f10x_enet.h:104
void enet_wum_filter_register_pointer_reset ( void )

wakeup frame filter register pointer reset

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 2469 of file gd32f10x_enet.c.

2470 {
2471 ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR;
2472 }
ENET_MAC_WUM_WUFFRPR
#define ENET_MAC_WUM_WUFFRPR
Definition: gd32f10x_enet.h:227
ENET_MAC_WUM
#define ENET_MAC_WUM
Definition: gd32f10x_enet.h:105
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Data Structures | Macros | Functions
gd32f10x_exmc.h File Reference

definitions for the EXMC More...

#include "gd32f10x.h"

Go to the source code of this file.

Data Structures

struct | exmc_norsram_timing_parameter_struct
struct | exmc_norsram_parameter_struct
struct | exmc_nand_pccard_timing_parameter_struct
struct | exmc_nand_parameter_struct
struct | exmc_pccard_parameter_struct

Macros

#define | EXMC (EXMC_BASE)
#define | EXMC_SNCTL0 REG32(EXMC + 0x00U)
#define | EXMC_SNTCFG0 REG32(EXMC + 0x04U)
#define | EXMC_SNWTCFG0 REG32(EXMC + 0x104U)
#define | EXMC_SNCTL1 REG32(EXMC + 0x08U)
#define | EXMC_SNTCFG1 REG32(EXMC + 0x0CU)
#define | EXMC_SNWTCFG1 REG32(EXMC + 0x10CU)
#define | EXMC_SNCTL2 REG32(EXMC + 0x10U)
#define | EXMC_SNTCFG2 REG32(EXMC + 0x14U)
#define | EXMC_SNWTCFG2 REG32(EXMC + 0x114U)
#define | EXMC_SNCTL3 REG32(EXMC + 0x18U)
#define | EXMC_SNTCFG3 REG32(EXMC + 0x1CU)
#define | EXMC_SNWTCFG3 REG32(EXMC + 0x11CU)
#define | EXMC_NPCTL1 REG32(EXMC + 0x60U)
#define | EXMC_NPINTEN1 REG32(EXMC + 0x64U)
#define | EXMC_NPCTCFG1 REG32(EXMC + 0x68U)
#define | EXMC_NPATCFG1 REG32(EXMC + 0x6CU)
#define | EXMC_NECC1 REG32(EXMC + 0x74U)
#define | EXMC_NPCTL2 REG32(EXMC + 0x80U)
#define | EXMC_NPINTEN2 REG32(EXMC + 0x84U)
#define | EXMC_NPCTCFG2 REG32(EXMC + 0x88U)
#define | EXMC_NPATCFG2 REG32(EXMC + 0x8CU)
#define | EXMC_NECC2 REG32(EXMC + 0x94U)
#define | EXMC_NPCTL3 REG32(EXMC + 0xA0U)
#define | EXMC_NPINTEN3 REG32(EXMC + 0xA4U)
#define | EXMC_NPCTCFG3 REG32(EXMC + 0xA8U)
#define | EXMC_NPATCFG3 REG32(EXMC + 0xACU)
#define | EXMC_PIOTCFG3 REG32(EXMC + 0xB0U)
#define | EXMC_SNCTL_NRBKEN BIT(0)
#define | EXMC_SNCTL_NRMUX BIT(1)
#define | EXMC_SNCTL_NRTP BITS(2,3)
#define | EXMC_SNCTL_NRW BITS(4,5)
#define | EXMC_SNCTL_NREN BIT(6)
#define | EXMC_SNCTL_SBRSTEN BIT(8)
#define | EXMC_SNCTL_NRWTPOL BIT(9)
#define | EXMC_SNCTL_WRAPEN BIT(10)
#define | EXMC_SNCTL_NRWTCFG BIT(11)
#define | EXMC_SNCTL_WREN BIT(12)
#define | EXMC_SNCTL_NRWTEN BIT(13)
#define | EXMC_SNCTL_EXMODEN BIT(14)
#define | EXMC_SNCTL_ASYNCWAIT BIT(15)
#define | EXMC_SNCTL_SYNCWR BIT(19)
#define | EXMC_SNTCFG_ASET BITS(0,3)
#define | EXMC_SNTCFG_AHLD BITS(4,7)
#define | EXMC_SNTCFG_DSET BITS(8,15)
#define | EXMC_SNTCFG_BUSLAT BITS(16,19)
#define | EXMC_SNTCFG_CKDIV BITS(20,23)
#define | EXMC_SNTCFG_DLAT BITS(24,27)
#define | EXMC_SNTCFG_ASYNCMOD BITS(28,29)
#define | EXMC_SNWTCFG_WASET BITS(0,3)
#define | EXMC_SNWTCFG_WAHLD BITS(4,7)
#define | EXMC_SNWTCFG_WDSET BITS(8,15)
#define | EXMC_SNWTCFG_CKDIV BITS(20,23)
#define | EXMC_SNWTCFG_DLAT BITS(24,27)
#define | EXMC_SNWTCFG_WASYNCMOD BITS(28,29)
#define | EXMC_NPCTL_NDWTEN BIT(1)
#define | EXMC_NPCTL_NDBKEN BIT(2)
#define | EXMC_NPCTL_NDTP BIT(3)
#define | EXMC_NPCTL_NDW BITS(4,5)
#define | EXMC_NPCTL_ECCEN BIT(6)
#define | EXMC_NPCTL_CTR BITS(9,12)
#define | EXMC_NPCTL_ATR BITS(13,16)
#define | EXMC_NPCTL_ECCSZ BITS(17,19)
#define | EXMC_NPINTEN_INTRS BIT(0)
#define | EXMC_NPINTEN_INTHS BIT(1)
#define | EXMC_NPINTEN_INTFS BIT(2)
#define | EXMC_NPINTEN_INTREN BIT(3)
#define | EXMC_NPINTEN_INTHEN BIT(4)
#define | EXMC_NPINTEN_INTFEN BIT(5)
#define | EXMC_NPINTEN_FFEPT BIT(6)
#define | EXMC_NPCTCFG_COMSET BITS(0,7)
#define | EXMC_NPCTCFG_COMWAIT BITS(8,15)
#define | EXMC_NPCTCFG_COMHLD BITS(16,23)
#define | EXMC_NPCTCFG_COMHIZ BITS(24,31)
#define | EXMC_NPATCFG_ATTSET BITS(0,7)
#define | EXMC_NPATCFG_ATTWAIT BITS(8,15)
#define | EXMC_NPATCFG_ATTHLD BITS(16,23)
#define | EXMC_NPATCFG_ATTHIZ BITS(24,31)
#define | EXMC_PIOTCFG3_IOSET BITS(0,7)
#define | EXMC_PIOTCFG3_IOWAIT BITS(8,15)
#define | EXMC_PIOTCFG3_IOHLD BITS(16,23)
#define | EXMC_PIOTCFG3_IOHIZ BITS(24,31)
#define | EXMC_NECC_ECC BITS(0,31)
#define | EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region))
#define | EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region))
#define | EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region))
#define | EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank))
#define | EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank))
#define | EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank))
#define | EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank))
#define | EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank))
#define | SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define | EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0)
#define | EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1)
#define | SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define | EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0)
#define | EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1)
#define | EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2)
#define | SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define | EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0)
#define | EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1)
#define | EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2)
#define | EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3)
#define | SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
#define | EXMC_DATALAT_2_CLK SNTCFG_DLAT(0)
#define | EXMC_DATALAT_3_CLK SNTCFG_DLAT(1)
#define | EXMC_DATALAT_4_CLK SNTCFG_DLAT(2)
#define | EXMC_DATALAT_5_CLK SNTCFG_DLAT(3)
#define | EXMC_DATALAT_6_CLK SNTCFG_DLAT(4)
#define | EXMC_DATALAT_7_CLK SNTCFG_DLAT(5)
#define | EXMC_DATALAT_8_CLK SNTCFG_DLAT(6)
#define | EXMC_DATALAT_9_CLK SNTCFG_DLAT(7)
#define | EXMC_DATALAT_10_CLK SNTCFG_DLAT(8)
#define | EXMC_DATALAT_11_CLK SNTCFG_DLAT(9)
#define | EXMC_DATALAT_12_CLK SNTCFG_DLAT(10)
#define | EXMC_DATALAT_13_CLK SNTCFG_DLAT(11)
#define | EXMC_DATALAT_14_CLK SNTCFG_DLAT(12)
#define | EXMC_DATALAT_15_CLK SNTCFG_DLAT(13)
#define | EXMC_DATALAT_16_CLK SNTCFG_DLAT(14)
#define | EXMC_DATALAT_17_CLK SNTCFG_DLAT(15)
#define | SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
#define | EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0)
#define | EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1)
#define | EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2)
#define | EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3)
#define | EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4)
#define | EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5)
#define | EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6)
#define | EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7)
#define | EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8)
#define | EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9)
#define | EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10)
#define | EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11)
#define | EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12)
#define | EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13)
#define | EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14)
#define | EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15)
#define | NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
#define | EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */
#define | EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */
#define | EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */
#define | EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */
#define | EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */
#define | EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */
#define | NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
#define | EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
#define | EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
#define | EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
#define | EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
#define | EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
#define | EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
#define | EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
#define | EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
#define | EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
#define | EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
#define | EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
#define | EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
#define | EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
#define | EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
#define | EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
#define | EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
#define | NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
#define | EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
#define | EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
#define | EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
#define | EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
#define | EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
#define | EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
#define | EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
#define | EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
#define | EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
#define | EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
#define | EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
#define | EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
#define | EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
#define | EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
#define | EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
#define | EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
#define | NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define | EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0)
#define | EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1)
#define | EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U)
#define | EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U)
#define | EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U)
#define | EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U)
#define | EXMC_ASYN_WRITE ((uint32_t)0x00000000U)
#define | EXMC_SYN_WRITE ((uint32_t)0x00080000U)
#define | EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U)
#define | EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U)
#define | EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U)
#define | EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U)
#define | EXMC_BANK1_NAND ((uint32_t)0x00000001U)
#define | EXMC_BANK2_NAND ((uint32_t)0x00000002U)
#define | EXMC_BANK3_PCCARD ((uint32_t)0x00000003U)
#define | EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS
#define | EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS
#define | EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS
#define | EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT
#define | EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN
#define | EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN
#define | EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN

Functions

void | exmc_norsram_deinit (uint32_t norsram_region)
deinitialize EXMC NOR/SRAM region More...
void | exmc_norsram_init (exmc_norsram_parameter_struct *norsram_init_struct)
initialize EXMC NOR/SRAM region More...
void | exmc_norsram_parameter_init (exmc_norsram_parameter_struct *norsram_init_struct)
initialize the struct exmc_norsram_parameter_struct More...
void | exmc_norsram_enable (uint32_t norsram_region)
enable EXMC NOR/PSRAM bank region More...
void | exmc_norsram_disable (uint32_t norsram_region)
disable EXMC NOR/PSRAM bank region More...
void | exmc_nand_deinit (uint32_t nand_bank)
deinitialize EXMC NAND bank More...
void | exmc_nand_init (exmc_nand_parameter_struct *nand_init_struct)
initialize EXMC NAND bank More...
void | exmc_nand_parameter_init (exmc_nand_parameter_struct *nand_init_struct)
initialize the struct exmc_norsram_parameter_struct More...
void | exmc_nand_enable (uint32_t nand_bank)
enable NAND bank More...
void | exmc_nand_disable (uint32_t nand_bank)
disable NAND bank More...
void | exmc_nand_ecc_config (uint32_t nand_bank, ControlStatus newvalue)
enable or disable the EXMC NAND ECC function More...
uint32_t | exmc_ecc_get (uint32_t nand_bank)
get the EXMC ECC value More...
void | exmc_pccard_deinit (void)
deinitialize EXMC PC card bank More...
void | exmc_pccard_init (exmc_pccard_parameter_struct *exmc_pccard_init_struct)
initialize EXMC PC card bank More...
void | exmc_pccard_parameter_init (exmc_pccard_parameter_struct *exmc_pccard_init_struct)
initialize the struct exmc_pccard_parameter_struct More...
void | exmc_pccard_enable (void)
enable PC Card Bank More...
void | exmc_pccard_disable (void)
disable PC Card Bank More...
FlagStatus | exmc_flag_get (uint32_t bank, uint32_t flag)
check EXMC flag is set or not More...
void | exmc_flag_clear (uint32_t bank, uint32_t flag)
clear EXMC flag More...
FlagStatus | exmc_interrupt_flag_get (uint32_t bank, uint32_t interrupt_source)
check EXMC interrupt flag is set or not More...
void | exmc_interrupt_flag_clear (uint32_t bank, uint32_t interrupt_source)
clear EXMC interrupt flag More...
void | exmc_interrupt_enable (uint32_t bank, uint32_t interrupt_source)
enable EXMC interrupt More...
void | exmc_interrupt_disable (uint32_t bank, uint32_t interrupt_source)
disable EXMC interrupt More...

Detailed Description

definitions for the EXMC

Definition in file gd32f10x_exmc.h.

Macro Definition Documentation

#define EXMC (EXMC_BASE)

EXMC register base address

Definition at line 19 of file gd32f10x_exmc.h.

#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0)

mode A access

Definition at line 234 of file gd32f10x_exmc.h.

#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1)

mode B access

Definition at line 235 of file gd32f10x_exmc.h.

#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2)

mode C access

Definition at line 236 of file gd32f10x_exmc.h.

#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3)

mode D access

Definition at line 237 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */

Definition at line 297 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */

Definition at line 298 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */

Definition at line 299 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */

Definition at line 300 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */

Definition at line 301 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */

Definition at line 302 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */

Definition at line 303 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */

Definition at line 288 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */

Definition at line 289 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */

Definition at line 290 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */

Definition at line 291 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */

Definition at line 292 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */

Definition at line 293 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */

Definition at line 294 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */

Definition at line 295 of file gd32f10x_exmc.h.

#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */

Definition at line 296 of file gd32f10x_exmc.h.

#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U)

asynchronous write mode

Definition at line 336 of file gd32f10x_exmc.h.

#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U)

bank0 NOR/SRAM region0

Definition at line 330 of file gd32f10x_exmc.h.

#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U)

bank0 NOR/SRAM region1

Definition at line 331 of file gd32f10x_exmc.h.

#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U)

bank0 NOR/SRAM region2

Definition at line 332 of file gd32f10x_exmc.h.

#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U)

bank0 NOR/SRAM region3

Definition at line 333 of file gd32f10x_exmc.h.

#define EXMC_BANK1_NAND ((uint32_t)0x00000001U)

bank1 NAND flash

Definition at line 348 of file gd32f10x_exmc.h.

#define EXMC_BANK2_NAND ((uint32_t)0x00000002U)

bank2 NAND flash

Definition at line 349 of file gd32f10x_exmc.h.

#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U)

bank3 PC card

Definition at line 350 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */

Definition at line 316 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */

Definition at line 317 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */

Definition at line 318 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */

Definition at line 319 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */

Definition at line 320 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */

Definition at line 321 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */

Definition at line 322 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */

Definition at line 307 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */

Definition at line 308 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */

Definition at line 309 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */

Definition at line 310 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */

Definition at line 311 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */

Definition at line 312 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */

Definition at line 313 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */

Definition at line 314 of file gd32f10x_exmc.h.

#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */

Definition at line 315 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8)

data latency 10 EXMC_CLK

Definition at line 249 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9)

data latency 11 EXMC_CLK

Definition at line 250 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10)

data latency 12 EXMC_CLK

Definition at line 251 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11)

data latency 13 EXMC_CLK

Definition at line 252 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12)

data latency 14 EXMC_CLK

Definition at line 253 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13)

data latency 15 EXMC_CLK

Definition at line 254 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14)

data latency 16 EXMC_CLK

Definition at line 255 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15)

data latency 17 EXMC_CLK

Definition at line 256 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0)

data latency 2 EXMC_CLK

Definition at line 241 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1)

data latency 3 EXMC_CLK

Definition at line 242 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2)

data latency 4 EXMC_CLK

Definition at line 243 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3)

data latency 5 EXMC_CLK

Definition at line 244 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4)

data latency 6 EXMC_CLK

Definition at line 245 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5)

data latency 7 EXMC_CLK

Definition at line 246 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6)

data latency 8 EXMC_CLK

Definition at line 247 of file gd32f10x_exmc.h.

#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7)

data latency 9 EXMC_CLK

Definition at line 248 of file gd32f10x_exmc.h.

#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */

Definition at line 281 of file gd32f10x_exmc.h.

#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */

Definition at line 282 of file gd32f10x_exmc.h.

#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */

Definition at line 279 of file gd32f10x_exmc.h.

#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */

Definition at line 283 of file gd32f10x_exmc.h.

#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */

Definition at line 280 of file gd32f10x_exmc.h.

#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */

Definition at line 284 of file gd32f10x_exmc.h.

#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2)

NOR flash

Definition at line 230 of file gd32f10x_exmc.h.

#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1)

PSRAM,CRAM

Definition at line 229 of file gd32f10x_exmc.h.

#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0)

SRAM,ROM

Definition at line 228 of file gd32f10x_exmc.h.

#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1)

NAND data width 16 bits

Definition at line 327 of file gd32f10x_exmc.h.

#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0)

NAND data width 8 bits

Definition at line 326 of file gd32f10x_exmc.h.

#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS

interrupt falling edge status

Definition at line 355 of file gd32f10x_exmc.h.

#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT

FIFO empty flag

Definition at line 356 of file gd32f10x_exmc.h.

#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS

interrupt high-level status

Definition at line 354 of file gd32f10x_exmc.h.

#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS

interrupt rising edge status

Definition at line 353 of file gd32f10x_exmc.h.

#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN

interrupt falling edge detection enable

Definition at line 361 of file gd32f10x_exmc.h.

#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN

interrupt high-level detection enable

Definition at line 360 of file gd32f10x_exmc.h.

#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN

interrupt rising edge detection enable

Definition at line 359 of file gd32f10x_exmc.h.

#define EXMC_NECC ( bank ) REG32(EXMC + 0x54U + 0x20U * (bank))

EXMC NAND ECC register

Definition at line 211 of file gd32f10x_exmc.h.

#define EXMC_NECC1 REG32(EXMC + 0x74U)

EXMC NAND ECC register 1

Definition at line 44 of file gd32f10x_exmc.h.

#define EXMC_NECC2 REG32(EXMC + 0x94U)

EXMC NAND ECC register 2

Definition at line 50 of file gd32f10x_exmc.h.

#define EXMC_NECC_ECC BITS(0,31)

ECC result

Definition at line 132 of file gd32f10x_exmc.h.

#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1)

NOR data width 16 bits

Definition at line 224 of file gd32f10x_exmc.h.

#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0)

NOR data width 8 bits

Definition at line 223 of file gd32f10x_exmc.h.

#define EXMC_NPATCFG ( bank ) REG32(EXMC + 0x4CU + 0x20U * (bank))

EXMC NAND/PC card attribute space timing configuration register

Definition at line 210 of file gd32f10x_exmc.h.

#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU)

EXMC NAND/PC card attribute space timing configuration register 1

Definition at line 43 of file gd32f10x_exmc.h.

#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU)

EXMC NAND/PC card attribute space timing configuration register 2

Definition at line 49 of file gd32f10x_exmc.h.

#define EXMC_NPATCFG3 REG32(EXMC + 0xACU)

EXMC NAND/PC card attribute space timing configuration register 3

Definition at line 55 of file gd32f10x_exmc.h.

#define EXMC_NPATCFG_ATTHIZ BITS(24,31)

attribute memory data bus HiZ time

Definition at line 123 of file gd32f10x_exmc.h.

#define EXMC_NPATCFG_ATTHLD BITS(16,23)

attribute memory hold time

Definition at line 122 of file gd32f10x_exmc.h.

#define EXMC_NPATCFG_ATTSET BITS(0,7)

attribute memory setup time

Definition at line 120 of file gd32f10x_exmc.h.

#define EXMC_NPATCFG_ATTWAIT BITS(8,15)

attribute memory wait time

Definition at line 121 of file gd32f10x_exmc.h.

#define EXMC_NPCTCFG ( bank ) REG32(EXMC + 0x48U + 0x20U * (bank))

EXMC NAND/PC card common space timing configuration register

Definition at line 209 of file gd32f10x_exmc.h.

#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U)

EXMC NAND/PC card common space timing configuration register 1

Definition at line 42 of file gd32f10x_exmc.h.

#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U)

EXMC NAND/PC card common space timing configuration register 2

Definition at line 48 of file gd32f10x_exmc.h.

#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U)

EXMC NAND/PC card common space timing configuration register 3

Definition at line 54 of file gd32f10x_exmc.h.

#define EXMC_NPCTCFG_COMHIZ BITS(24,31)

common memory data bus HiZ time

Definition at line 117 of file gd32f10x_exmc.h.

#define EXMC_NPCTCFG_COMHLD BITS(16,23)

common memory hold time

Definition at line 116 of file gd32f10x_exmc.h.

#define EXMC_NPCTCFG_COMSET BITS(0,7)

common memory setup time

Definition at line 114 of file gd32f10x_exmc.h.

#define EXMC_NPCTCFG_COMWAIT BITS(8,15)

common memory wait time

Definition at line 115 of file gd32f10x_exmc.h.

#define EXMC_NPCTL ( bank ) REG32(EXMC + 0x40U + 0x20U * (bank))

EXMC NAND/PC card control register

Definition at line 207 of file gd32f10x_exmc.h.

#define EXMC_NPCTL1 REG32(EXMC + 0x60U)

EXMC NAND/PC card control register 1

Definition at line 40 of file gd32f10x_exmc.h.

#define EXMC_NPCTL2 REG32(EXMC + 0x80U)

EXMC NAND/PC card control register 2

Definition at line 46 of file gd32f10x_exmc.h.

#define EXMC_NPCTL3 REG32(EXMC + 0xA0U)

EXMC NAND/PC card control register 3

Definition at line 52 of file gd32f10x_exmc.h.

#define EXMC_NPCTL_ATR BITS(13,16)

ALE to RE delay

Definition at line 101 of file gd32f10x_exmc.h.

#define EXMC_NPCTL_CTR BITS(9,12)

CLE to RE delay

Definition at line 100 of file gd32f10x_exmc.h.

#define EXMC_NPCTL_ECCEN BIT(6)

ECC enable

Definition at line 99 of file gd32f10x_exmc.h.

#define EXMC_NPCTL_ECCSZ BITS(17,19)

ECC size

Definition at line 102 of file gd32f10x_exmc.h.

#define EXMC_NPCTL_NDBKEN BIT(2)

NAND bank enable

Definition at line 96 of file gd32f10x_exmc.h.

#define EXMC_NPCTL_NDTP BIT(3)

NAND bank memory type

Definition at line 97 of file gd32f10x_exmc.h.

#define EXMC_NPCTL_NDW BITS(4,5)

NAND bank memory data bus width

Definition at line 98 of file gd32f10x_exmc.h.

#define EXMC_NPCTL_NDWTEN BIT(1)

wait feature enable

Definition at line 95 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN ( bank ) REG32(EXMC + 0x44U + 0x20U * (bank))

EXMC NAND/PC card interrupt enable register

Definition at line 208 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN1 REG32(EXMC + 0x64U)

EXMC NAND/PC card interrupt enable register 1

Definition at line 41 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN2 REG32(EXMC + 0x84U)

EXMC NAND/PC card interrupt enable register 2

Definition at line 47 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U)

EXMC NAND/PC card interrupt enable register 3

Definition at line 53 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN_FFEPT BIT(6)

FIFO empty flag

Definition at line 111 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN_INTFEN BIT(5)

interrupt falling edge detection enable

Definition at line 110 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN_INTFS BIT(2)

interrupt falling edge status

Definition at line 107 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN_INTHEN BIT(4)

interrupt high-level detection enable

Definition at line 109 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN_INTHS BIT(1)

interrupt high-level status

Definition at line 106 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN_INTREN BIT(3)

interrupt rising edge detection enable

Definition at line 108 of file gd32f10x_exmc.h.

#define EXMC_NPINTEN_INTRS BIT(0)

interrupt rising edge status

Definition at line 105 of file gd32f10x_exmc.h.

#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U)

NWAIT signal is active one data cycle before wait state

Definition at line 340 of file gd32f10x_exmc.h.

#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U)

NWAIT signal is active during wait state

Definition at line 341 of file gd32f10x_exmc.h.

#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U)

high level is active of NWAIT

Definition at line 345 of file gd32f10x_exmc.h.

#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U)

low level is active of NWAIT

Definition at line 344 of file gd32f10x_exmc.h.

#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U)

EXMC PC card I/O space timing configuration register

Definition at line 56 of file gd32f10x_exmc.h.

#define EXMC_PIOTCFG3_IOHIZ BITS(24,31)

IO space data bus HiZ time

Definition at line 129 of file gd32f10x_exmc.h.

#define EXMC_PIOTCFG3_IOHLD BITS(16,23)

IO space hold time

Definition at line 128 of file gd32f10x_exmc.h.

#define EXMC_PIOTCFG3_IOSET BITS(0,7)

IO space setup time

Definition at line 126 of file gd32f10x_exmc.h.

#define EXMC_PIOTCFG3_IOWAIT BITS(8,15)

IO space wait time

Definition at line 127 of file gd32f10x_exmc.h.

#define EXMC_SNCTL ( region ) REG32(EXMC + 0x08U * (region))

EXMC SRAM/NOR flash control register

Definition at line 203 of file gd32f10x_exmc.h.

#define EXMC_SNCTL0 REG32(EXMC + 0x00U)

EXMC SRAM/NOR flash control register 0

Definition at line 23 of file gd32f10x_exmc.h.

#define EXMC_SNCTL1 REG32(EXMC + 0x08U)

EXMC SRAM/NOR flash control register 1

Definition at line 27 of file gd32f10x_exmc.h.

#define EXMC_SNCTL2 REG32(EXMC + 0x10U)

EXMC SRAM/NOR flash control register 2

Definition at line 31 of file gd32f10x_exmc.h.

#define EXMC_SNCTL3 REG32(EXMC + 0x18U)

EXMC SRAM/NOR flash control register 3

Definition at line 35 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_ASYNCWAIT BIT(15)

asynchronous wait

Definition at line 73 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_EXMODEN BIT(14)

extended mode enable

Definition at line 72 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_NRBKEN BIT(0)

NOR bank enable

Definition at line 61 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_NREN BIT(6)

NOR flash access enable

Definition at line 65 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_NRMUX BIT(1)

NOR bank memory address/data multiplexing

Definition at line 62 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_NRTP BITS(2,3)

NOR bank memory type

Definition at line 63 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_NRW BITS(4,5)

NOR bank memory data bus width

Definition at line 64 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_NRWTCFG BIT(11)

NWAIT signal configuration, only work in synchronous mode

Definition at line 69 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_NRWTEN BIT(13)

NWAIT signal enable

Definition at line 71 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_NRWTPOL BIT(9)

NWAIT signal polarity

Definition at line 67 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_SBRSTEN BIT(8)

synchronous burst enable

Definition at line 66 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_SYNCWR BIT(19)

synchronous write

Definition at line 74 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_WRAPEN BIT(10)

wrapped burst mode enable

Definition at line 68 of file gd32f10x_exmc.h.

#define EXMC_SNCTL_WREN BIT(12)

write enable

Definition at line 70 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG ( region ) REG32(EXMC + 0x04U + 0x08U * (region))

EXMC SRAM/NOR flash timing configuration register

Definition at line 204 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG0 REG32(EXMC + 0x04U)

EXMC SRAM/NOR flash timing configuration register 0

Definition at line 24 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU)

EXMC SRAM/NOR flash timing configuration register 1

Definition at line 28 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG2 REG32(EXMC + 0x14U)

EXMC SRAM/NOR flash timing configuration register 2

Definition at line 32 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU)

EXMC SRAM/NOR flash timing configuration register 3

Definition at line 36 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG_AHLD BITS(4,7)

address hold time

Definition at line 78 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG_ASET BITS(0,3)

address setup time

Definition at line 77 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG_ASYNCMOD BITS(28,29)

asynchronous access mode

Definition at line 83 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG_BUSLAT BITS(16,19)

bus latency

Definition at line 80 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG_CKDIV BITS(20,23)

synchronous clock divide ratio

Definition at line 81 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG_DLAT BITS(24,27)

data latency for NOR flash

Definition at line 82 of file gd32f10x_exmc.h.

#define EXMC_SNTCFG_DSET BITS(8,15)

data setup time

Definition at line 79 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG ( region ) REG32(EXMC + 0x104U + 0x08U * (region))

EXMC SRAM/NOR flash write timing configuration register

Definition at line 205 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U)

EXMC SRAM/NOR flash write timing configuration register 0

Definition at line 25 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU)

EXMC SRAM/NOR flash write timing configuration register 1

Definition at line 29 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U)

EXMC SRAM/NOR flash write timing configuration register 2

Definition at line 33 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU)

EXMC SRAM/NOR flash write timing configuration register 3

Definition at line 37 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG_CKDIV BITS(20,23)

synchronous clock divide ratio

Definition at line 89 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG_DLAT BITS(24,27)

data latency for NOR flash

Definition at line 90 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG_WAHLD BITS(4,7)

address hold time

Definition at line 87 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG_WASET BITS(0,3)

address setup time

Definition at line 86 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29)

asynchronous access mode

Definition at line 91 of file gd32f10x_exmc.h.

#define EXMC_SNWTCFG_WDSET BITS(8,15)

data setup time

Definition at line 88 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9)

EXMC_CLK = 10*HCLK

Definition at line 269 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10)

EXMC_CLK = 11*HCLK

Definition at line 270 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11)

EXMC_CLK = 12*HCLK

Definition at line 271 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12)

EXMC_CLK = 13*HCLK

Definition at line 272 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13)

EXMC_CLK = 14*HCLK

Definition at line 273 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14)

EXMC_CLK = 15*HCLK

Definition at line 274 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15)

EXMC_CLK = 16*HCLK

Definition at line 275 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1)

EXMC_CLK = 2*HCLK

Definition at line 261 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2)

EXMC_CLK = 3*HCLK

Definition at line 262 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3)

EXMC_CLK = 4*HCLK

Definition at line 263 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4)

EXMC_CLK = 5*HCLK

Definition at line 264 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5)

EXMC_CLK = 6*HCLK

Definition at line 265 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6)

EXMC_CLK = 7*HCLK

Definition at line 266 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7)

EXMC_CLK = 8*HCLK

Definition at line 267 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8)

EXMC_CLK = 9*HCLK

Definition at line 268 of file gd32f10x_exmc.h.

#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0)

EXMC_CLK disable

Definition at line 260 of file gd32f10x_exmc.h.

#define EXMC_SYN_WRITE ((uint32_t)0x00080000U)

synchronous write mode

Definition at line 337 of file gd32f10x_exmc.h.

#define NPCTL_ATR ( regval ) (BITS(13,16) & ((uint32_t)(regval) << 13))

Definition at line 287 of file gd32f10x_exmc.h.

#define NPCTL_CTR ( regval ) (BITS(9,12) & ((uint32_t)(regval) << 9))

Definition at line 306 of file gd32f10x_exmc.h.

#define NPCTL_ECCSZ ( regval ) (BITS(17,19) & ((uint32_t)(regval) << 17))

Definition at line 278 of file gd32f10x_exmc.h.

#define NPCTL_NDW ( regval ) (BITS(4,5) & ((uint32_t)(regval) << 4))

Definition at line 325 of file gd32f10x_exmc.h.

#define SNCTL_NRTP ( regval ) (BITS(2,3) & ((uint32_t)(regval) << 2))

Definition at line 227 of file gd32f10x_exmc.h.

#define SNCTL_NRW ( regval ) (BITS(4,5) & ((uint32_t)(regval) << 4))
  • CRAM page size */

Definition at line 222 of file gd32f10x_exmc.h.

#define SNTCFG_ASYNCMOD ( regval ) (BITS(28,29) & ((uint32_t)(regval) << 28))

Definition at line 233 of file gd32f10x_exmc.h.

#define SNTCFG_CKDIV ( regval ) (BITS(20,23) & ((uint32_t)(regval) << 20))

Definition at line 259 of file gd32f10x_exmc.h.

#define SNTCFG_DLAT ( regval ) (BITS(24,27) & ((uint32_t)(regval) << 24))

Definition at line 240 of file gd32f10x_exmc.h.

Function Documentation

uint32_t exmc_ecc_get ( uint32_t nand_bank )

get the EXMC ECC value

Parameters
[in] nand_bank specifie the NAND bank
  • EXMC_BANKx_NAND(x=1,2)
[out] none
Return values
the error correction code(ECC) value

Definition at line 363 of file gd32f10x_exmc.c.

364 {
365 return (EXMC_NECC(nand_bank));
366 }
EXMC_NECC
#define EXMC_NECC(bank)
Definition: gd32f10x_exmc.h:211
void exmc_flag_clear | ( | uint32_t | bank,
 |  | uint32_t | flag
 | ) |  |

clear EXMC flag

Parameters
[in] bank specifie the NAND bank , PCCARD bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] flag specify get which flag
  • EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status
  • EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status
  • EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status
  • EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag
[out] none
Return values
none

Definition at line 515 of file gd32f10x_exmc.c.

516 {
517 /* NAND bank1,bank2 or PC card bank3 */
518 EXMC_NPINTEN(bank) &= ~flag;
519 }
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
FlagStatus exmc_flag_get | ( | uint32_t | bank,
 |  | uint32_t | flag
 | ) |  |

check EXMC flag is set or not

Parameters
[in] bank specifies the NAND bank , PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC Card bank
[in] flag specify get which flag
  • EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status
  • EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status
  • EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status
  • EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 485 of file gd32f10x_exmc.c.

486 {
487 uint32_t status = 0x00000000U;
488
489 /* NAND bank1,bank2 or PC card bank3 */
490 status = EXMC_NPINTEN(bank);
491
492 if ((status & flag) != (uint32_t)flag ){
493 /* flag is reset */
494 return RESET;
495 }else{
496 /* flag is set */
497 return SET;
498 }
499 }
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_interrupt_disable | ( | uint32_t | bank,
 |  | uint32_t | interrupt_source
 | ) |  |

disable EXMC interrupt

Parameters
[in] bank specifies the NAND bank , PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] interrupt_source specify get which interrupt flag
  • EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
  • EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
  • EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
[out] none
Return values
none

Definition at line 604 of file gd32f10x_exmc.c.

605 {
606 /* NAND bank1,bank2 or PC card bank3 */
607 EXMC_NPINTEN(bank) &= ~interrupt_source;
608 }
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_interrupt_enable | ( | uint32_t | bank,
 |  | uint32_t | interrupt_source
 | ) |  |

enable EXMC interrupt

Parameters
[in] bank specifies the NAND bank,PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] interrupt_source specify get which interrupt flag
  • EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
  • EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
  • EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
[out] none
Return values
none

Definition at line 585 of file gd32f10x_exmc.c.

586 {
587 /* NAND bank1,bank2 or PC card bank3 */
588 EXMC_NPINTEN(bank) |= interrupt_source;
589 }
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_interrupt_flag_clear | ( | uint32_t | bank,
 |  | uint32_t | interrupt_source
 | ) |  |

clear EXMC interrupt flag

Parameters
[in] bank specifies the NAND bank , PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] interrupt_source specify get which interrupt flag
  • EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
  • EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
  • EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
[out] none
Return values
none

Definition at line 566 of file gd32f10x_exmc.c.

567 {
568 /* NAND bank1,bank2 or PC card bank3 */
569 EXMC_NPINTEN(bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET);
570 }
INTEN_INTS_OFFSET
#define INTEN_INTS_OFFSET
Definition: gd32f10x_exmc.c:66
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
FlagStatus exmc_interrupt_flag_get | ( | uint32_t | bank,
 |  | uint32_t | interrupt_source
 | ) |  |

check EXMC interrupt flag is set or not

Parameters
[in] bank specifies the NAND bank , PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] interrupt_source specify get which interrupt flag
  • EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
  • EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
  • EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
[out] none
Return values
FlagStatus SET or RESET

Definition at line 534 of file gd32f10x_exmc.c.

535 {
536 uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U;
537
538 /* NAND bank1,bank2 or PC card bank3 */
539 status = EXMC_NPINTEN(bank);
540 interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET));
541
542 interrupt_enable = (status & interrupt_source);
543
544 if ((interrupt_enable) && (interrupt_state)){
545 /* interrupt flag is set */
546 return SET;
547 }else{
548 /* interrupt flag is reset */
549 return RESET;
550 }
551 }
INTEN_INTS_OFFSET
#define INTEN_INTS_OFFSET
Definition: gd32f10x_exmc.c:66
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_nand_deinit ( uint32_t nand_bank )

deinitialize EXMC NAND bank

Parameters
[in] nand_bank select the bank of NAND
  • EXMC_BANKx_NAND(x=1..2)
[out] none
Return values
none

Definition at line 235 of file gd32f10x_exmc.c.

236 {
237 /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */
238 EXMC_NPCTL(nand_bank) = BANK1_2_NPCTL_RESET;
239 EXMC_NPINTEN(nand_bank) = BANK1_2_NPINTEN_RESET;
240 EXMC_NPCTCFG(nand_bank) = BANK1_2_NPCTCFG_RESET;
241 EXMC_NPATCFG(nand_bank) = BANK1_2_NPATCFG_RESET;
242 }
BANK1_2_NPCTCFG_RESET
#define BANK1_2_NPCTCFG_RESET
Definition: gd32f10x_exmc.c:24
EXMC_NPATCFG
#define EXMC_NPATCFG(bank)
Definition: gd32f10x_exmc.h:210
BANK1_2_NPATCFG_RESET
#define BANK1_2_NPATCFG_RESET
Definition: gd32f10x_exmc.c:25
BANK1_2_NPINTEN_RESET
#define BANK1_2_NPINTEN_RESET
Definition: gd32f10x_exmc.c:23
BANK1_2_NPCTL_RESET
#define BANK1_2_NPCTL_RESET
Definition: gd32f10x_exmc.c:22
EXMC_NPCTCFG
#define EXMC_NPCTCFG(bank)
Definition: gd32f10x_exmc.h:209
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_nand_disable ( uint32_t nand_bank )

disable NAND bank

Parameters
[in] nand_bank specifie the NAND bank
  • EXMC_BANKx_NAND(x=1,2)
[out] none
Return values
none

Definition at line 332 of file gd32f10x_exmc.c.

333 {
334 EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_NDBKEN;
335 }
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
EXMC_NPCTL_NDBKEN
#define EXMC_NPCTL_NDBKEN
Definition: gd32f10x_exmc.h:96
void exmc_nand_ecc_config | ( | uint32_t | nand_bank,
 |  | ControlStatus | newvalue
 | ) |  |

enable or disable the EXMC NAND ECC function

Parameters
[in] nand_bank specifie the NAND bank
  • EXMC_BANKx_NAND(x=1,2)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 345 of file gd32f10x_exmc.c.

346 {
347 if (ENABLE == newvalue){
348 /* enable the selected NAND bank ECC function */
349 EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_ECCEN;
350 }else{
351 /* disable the selected NAND bank ECC function */
352 EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_ECCEN;
353 }
354 }
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
EXMC_NPCTL_ECCEN
#define EXMC_NPCTL_ECCEN
Definition: gd32f10x_exmc.h:99
void exmc_nand_enable ( uint32_t nand_bank )

enable NAND bank

Parameters
[in] nand_bank specifie the NAND bank
  • EXMC_BANKx_NAND(x=1,2)
[out] none
Return values
none

Definition at line 320 of file gd32f10x_exmc.c.

321 {
322 EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_NDBKEN;
323 }
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
EXMC_NPCTL_NDBKEN
#define EXMC_NPCTL_NDBKEN
Definition: gd32f10x_exmc.h:96
void exmc_nand_init ( exmc_nand_parameter_struct * exmc_nand_init_struct )

initialize EXMC NAND bank

Parameters
[in] | exmc_nand_parameter_struct | configure the EXMC NAND parameter nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 ecc_logic: ENABLE or DISABLE databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B wait_feature: ENABLE or DISABLE common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
[out] | none
Return values
none

Definition at line 259 of file gd32f10x_exmc.c.

260 {
261 uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U;
262
263 npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)|
264 EXMC_NPCTL_NDTP |
265 exmc_nand_init_struct->databus_width |
266 (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)|
267 exmc_nand_init_struct->ecc_size |
268 exmc_nand_init_struct->ctr_latency |
269 exmc_nand_init_struct->atr_latency;
270
271 npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) |
272 (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
273 ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
274 (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
275
276 npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
277 (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
278 ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) |
279 (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
280
281 /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */
282 EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl;
283 EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg;
284 EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg;
285 }
EXMC_NPATCFG_ATTHLD
#define EXMC_NPATCFG_ATTHLD
Definition: gd32f10x_exmc.h:122
EXMC_NPCTL_NDTP
#define EXMC_NPCTL_NDTP
Definition: gd32f10x_exmc.h:97
NPATCFG_ATTHLD_OFFSET
#define NPATCFG_ATTHLD_OFFSET
Definition: gd32f10x_exmc.c:59
exmc_nand_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:185
exmc_nand_pccard_timing_parameter_struct::waittime
uint32_t waittime
Definition: gd32f10x_exmc.h:173
EXMC_NPATCFG
#define EXMC_NPATCFG(bank)
Definition: gd32f10x_exmc.h:210
EXMC_NPCTCFG_COMSET
#define EXMC_NPCTCFG_COMSET
Definition: gd32f10x_exmc.h:114
exmc_nand_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:183
EXMC_NPATCFG_ATTWAIT
#define EXMC_NPATCFG_ATTWAIT
Definition: gd32f10x_exmc.h:121
NPCTCFG_COMWAIT_OFFSET
#define NPCTCFG_COMWAIT_OFFSET
Definition: gd32f10x_exmc.c:54
exmc_nand_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:187
EXMC_NPATCFG_ATTHIZ
#define EXMC_NPATCFG_ATTHIZ
Definition: gd32f10x_exmc.h:123
exmc_nand_pccard_timing_parameter_struct::databus_hiztime
uint32_t databus_hiztime
Definition: gd32f10x_exmc.h:171
NPATCFG_ATTWAIT_OFFSET
#define NPATCFG_ATTWAIT_OFFSET
Definition: gd32f10x_exmc.c:58
EXMC_NPCTCFG_COMWAIT
#define EXMC_NPCTCFG_COMWAIT
Definition: gd32f10x_exmc.h:115
EXMC_NPCTCFG_COMHLD
#define EXMC_NPCTCFG_COMHLD
Definition: gd32f10x_exmc.h:116
exmc_nand_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:188
exmc_nand_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:186
exmc_nand_parameter_struct::ecc_logic
uint32_t ecc_logic
Definition: gd32f10x_exmc.h:184
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
EXMC_NPCTCFG
#define EXMC_NPCTCFG(bank)
Definition: gd32f10x_exmc.h:209
NPCTCFG_COMHLD_OFFSET
#define NPCTCFG_COMHLD_OFFSET
Definition: gd32f10x_exmc.c:55
exmc_nand_parameter_struct::ecc_size
uint32_t ecc_size
Definition: gd32f10x_exmc.h:181
NPATCFG_ATTHIZ_OFFSET
#define NPATCFG_ATTHIZ_OFFSET
Definition: gd32f10x_exmc.c:60
EXMC_NPATCFG_ATTSET
#define EXMC_NPATCFG_ATTSET
Definition: gd32f10x_exmc.h:120
exmc_nand_parameter_struct::nand_bank
uint32_t nand_bank
Definition: gd32f10x_exmc.h:180
NPCTCFG_COMHIZ_OFFSET
#define NPCTCFG_COMHIZ_OFFSET
Definition: gd32f10x_exmc.c:56
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
EXMC_NPCTCFG_COMHIZ
#define EXMC_NPCTCFG_COMHIZ
Definition: gd32f10x_exmc.h:117
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
exmc_nand_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:182
NPCTL_ECCEN_OFFSET
#define NPCTL_ECCEN_OFFSET
Definition: gd32f10x_exmc.c:52
NPCTL_NDWTEN_OFFSET
#define NPCTL_NDWTEN_OFFSET
Definition: gd32f10x_exmc.c:51
void exmc_nand_parameter_init ( exmc_nand_parameter_struct * exmc_nand_init_struct )

initialize the struct exmc_norsram_parameter_struct

Parameters
[in] | none
[out] | the | initialized struct exmc_norsram_parameter_struct pointer
Return values
none

Definition at line 293 of file gd32f10x_exmc.c.

294 {
295 /* configure the structure with default value */
296 exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND;
297 exmc_nand_init_struct->wait_feature = DISABLE;
298 exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B;
299 exmc_nand_init_struct->ecc_logic = DISABLE;
300 exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES;
301 exmc_nand_init_struct->ctr_latency = 0x0U;
302 exmc_nand_init_struct->atr_latency = 0x0U;
303 exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU;
304 exmc_nand_init_struct->common_space_timing->waittime = 0xFCU;
305 exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU;
306 exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU;
307 exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU;
308 exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU;
309 exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU;
310 exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
311 }
exmc_nand_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:185
exmc_nand_pccard_timing_parameter_struct::waittime
uint32_t waittime
Definition: gd32f10x_exmc.h:173
exmc_nand_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:183
exmc_nand_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:187
exmc_nand_pccard_timing_parameter_struct::databus_hiztime
uint32_t databus_hiztime
Definition: gd32f10x_exmc.h:171
EXMC_BANK1_NAND
#define EXMC_BANK1_NAND
Definition: gd32f10x_exmc.h:348
exmc_nand_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:188
EXMC_NAND_DATABUS_WIDTH_8B
#define EXMC_NAND_DATABUS_WIDTH_8B
Definition: gd32f10x_exmc.h:326
exmc_nand_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:186
exmc_nand_parameter_struct::ecc_logic
uint32_t ecc_logic
Definition: gd32f10x_exmc.h:184
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
exmc_nand_parameter_struct::ecc_size
uint32_t ecc_size
Definition: gd32f10x_exmc.h:181
exmc_nand_parameter_struct::nand_bank
uint32_t nand_bank
Definition: gd32f10x_exmc.h:180
EXMC_ECC_SIZE_256BYTES
#define EXMC_ECC_SIZE_256BYTES
Definition: gd32f10x_exmc.h:279
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
exmc_nand_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:182
void exmc_norsram_deinit ( uint32_t norsram_region )

deinitialize EXMC NOR/SRAM region

Parameters
[in] norsram_region select the region of bank0
  • EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
[out] none
Return values
none

Definition at line 75 of file gd32f10x_exmc.c.

76 {
77 /* reset the registers */
78 if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
79 EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
80 }else{
81 EXMC_SNCTL(norsram_region) = BANK0_SNCTL1_2_3_REGION_RESET;
82 }
83
84 EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET;
85 EXMC_SNWTCFG(norsram_region) = BANK0_SNWTCFG_RESET;
86 }
EXMC_SNWTCFG
#define EXMC_SNWTCFG(region)
Definition: gd32f10x_exmc.h:205
BANK0_SNCTL0_REGION_RESET
#define BANK0_SNCTL0_REGION_RESET
Definition: gd32f10x_exmc.c:16
EXMC_SNCTL
#define EXMC_SNCTL(region)
Definition: gd32f10x_exmc.h:203
BANK0_SNCTL1_2_3_REGION_RESET
#define BANK0_SNCTL1_2_3_REGION_RESET
Definition: gd32f10x_exmc.c:17
EXMC_SNTCFG
#define EXMC_SNTCFG(region)
Definition: gd32f10x_exmc.h:204
BANK0_SNWTCFG_RESET
#define BANK0_SNWTCFG_RESET
Definition: gd32f10x_exmc.c:19
BANK0_SNTCFG_RESET
#define BANK0_SNTCFG_RESET
Definition: gd32f10x_exmc.c:18
EXMC_BANK0_NORSRAM_REGION0
#define EXMC_BANK0_NORSRAM_REGION0
Definition: gd32f10x_exmc.h:330
void exmc_norsram_disable ( uint32_t norsram_region )

disable EXMC NOR/PSRAM bank region

Parameters
[in] norsram_region specifie the region of NOR/PSRAM Bank
  • EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
[out] none
Return values
none

Definition at line 223 of file gd32f10x_exmc.c.

224 {
225 EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
226 }
EXMC_SNCTL_NRBKEN
#define EXMC_SNCTL_NRBKEN
Definition: gd32f10x_exmc.h:61
EXMC_SNCTL
#define EXMC_SNCTL(region)
Definition: gd32f10x_exmc.h:203
void exmc_norsram_enable ( uint32_t norsram_region )

enable EXMC NOR/PSRAM bank region

Parameters
[in] norsram_region specifie the region of NOR/PSRAM bank
  • EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
[out] none
Return values
none

Definition at line 211 of file gd32f10x_exmc.c.

212 {
213 EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
214 }
EXMC_SNCTL_NRBKEN
#define EXMC_SNCTL_NRBKEN
Definition: gd32f10x_exmc.h:61
EXMC_SNCTL
#define EXMC_SNCTL(region)
Definition: gd32f10x_exmc.h:203
void exmc_norsram_init ( exmc_norsram_parameter_struct * exmc_norsram_init_struct )

initialize EXMC NOR/SRAM region

Parameters
[in] | exmc_norsram_parameter_struct | configure the EXMC NOR/SRAM parameter norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE extended_mode: ENABLE or DISABLE asyn_wait: ENABLE or DISABLE nwait_signal: ENABLE or DISABLE memory_write: ENABLE or DISABLE nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING wrap_burst_mode: ENABLE or DISABLE nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH burst_mode: ENABLE or DISABLE databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR address_data_mux: ENABLE or DISABLE read_write_timing: struct exmc_norsram_timing_parameter_struct set the time write_timing: struct exmc_norsram_timing_parameter_struct set the time
[out] | none
Return values
none

Definition at line 109 of file gd32f10x_exmc.c.

110 {
111 uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U;
112
113 /* get the register value */
114 snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
115
116 /* clear relative bits */
117 snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN |
118 EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN |
119 EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR |
120 EXMC_SNCTL_NRMUX ));
121
122 snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
123 exmc_norsram_init_struct->memory_type |
124 exmc_norsram_init_struct->databus_width |
125 (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) |
126 exmc_norsram_init_struct->nwait_polarity |
127 (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) |
128 exmc_norsram_init_struct->nwait_config |
129 (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
130 (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
131 (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) |
132 (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) |
133 exmc_norsram_init_struct->write_mode;
134
135 sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
136 (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
137 (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
138 (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )|
139 exmc_norsram_init_struct->read_write_timing->syn_clk_division |
140 exmc_norsram_init_struct->read_write_timing->syn_data_latency |
141 exmc_norsram_init_struct->read_write_timing->asyn_access_mode;
142
143 /* nor flash access enable */
144 if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
145 snctl |= (uint32_t)EXMC_SNCTL_NREN;
146 }
147
148 /* extended mode configure */
149 if(ENABLE == exmc_norsram_init_struct->extended_mode){
150 snwtcfg = (uint32_t)(((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) |
151 (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD)|
152 (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNWTCFG_WDSET) |
153 exmc_norsram_init_struct->write_timing->asyn_access_mode);
154 }else{
155 snwtcfg = BANK0_SNWTCFG_RESET;
156 }
157
158 /* configure the registers */
159 EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
160 EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
161 EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg;
162 }
exmc_norsram_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:160
exmc_norsram_parameter_struct::extended_mode
uint32_t extended_mode
Definition: gd32f10x_exmc.h:152
exmc_norsram_timing_parameter_struct::asyn_data_setuptime
uint32_t asyn_data_setuptime
Definition: gd32f10x_exmc.h:142
EXMC_SNCTL_ASYNCWAIT
#define EXMC_SNCTL_ASYNCWAIT
Definition: gd32f10x_exmc.h:73
EXMC_SNWTCFG
#define EXMC_SNWTCFG(region)
Definition: gd32f10x_exmc.h:205
EXMC_SNWTCFG_WAHLD
#define EXMC_SNWTCFG_WAHLD
Definition: gd32f10x_exmc.h:87
EXMC_SNCTL_NRWTEN
#define EXMC_SNCTL_NRWTEN
Definition: gd32f10x_exmc.h:71
exmc_norsram_parameter_struct::write_mode
uint32_t write_mode
Definition: gd32f10x_exmc.h:151
EXMC_SNCTL_SYNCWR
#define EXMC_SNCTL_SYNCWR
Definition: gd32f10x_exmc.h:74
SNCTL_EXMODEN_OFFSET
#define SNCTL_EXMODEN_OFFSET
Definition: gd32f10x_exmc.c:40
exmc_norsram_timing_parameter_struct::asyn_address_setuptime
uint32_t asyn_address_setuptime
Definition: gd32f10x_exmc.h:144
exmc_norsram_parameter_struct::norsram_region
uint32_t norsram_region
Definition: gd32f10x_exmc.h:150
EXMC_SNTCFG_AHLD
#define EXMC_SNTCFG_AHLD
Definition: gd32f10x_exmc.h:78
exmc_norsram_timing_parameter_struct::syn_clk_division
uint32_t syn_clk_division
Definition: gd32f10x_exmc.h:140
EXMC_SNCTL
#define EXMC_SNCTL(region)
Definition: gd32f10x_exmc.h:203
EXMC_SNCTL_NRW
#define EXMC_SNCTL_NRW
Definition: gd32f10x_exmc.h:64
SNCTL_NRWTEN_OFFSET
#define SNCTL_NRWTEN_OFFSET
Definition: gd32f10x_exmc.c:39
exmc_norsram_parameter_struct::nwait_config
uint32_t nwait_config
Definition: gd32f10x_exmc.h:156
exmc_norsram_parameter_struct::write_timing
exmc_norsram_timing_parameter_struct * write_timing
Definition: gd32f10x_exmc.h:165
exmc_norsram_timing_parameter_struct::asyn_access_mode
uint32_t asyn_access_mode
Definition: gd32f10x_exmc.h:138
EXMC_MEMORY_TYPE_NOR
#define EXMC_MEMORY_TYPE_NOR
Definition: gd32f10x_exmc.h:230
exmc_norsram_parameter_struct::read_write_timing
exmc_norsram_timing_parameter_struct * read_write_timing
Definition: gd32f10x_exmc.h:163
EXMC_SNTCFG
#define EXMC_SNTCFG(region)
Definition: gd32f10x_exmc.h:204
exmc_norsram_parameter_struct::burst_mode
uint32_t burst_mode
Definition: gd32f10x_exmc.h:159
EXMC_SNWTCFG_WDSET
#define EXMC_SNWTCFG_WDSET
Definition: gd32f10x_exmc.h:88
exmc_norsram_parameter_struct::memory_type
uint32_t memory_type
Definition: gd32f10x_exmc.h:161
SNCTL_WREN_OFFSET
#define SNCTL_WREN_OFFSET
Definition: gd32f10x_exmc.c:38
EXMC_SNCTL_SBRSTEN
#define EXMC_SNCTL_SBRSTEN
Definition: gd32f10x_exmc.h:66
exmc_norsram_parameter_struct::asyn_wait
uint32_t asyn_wait
Definition: gd32f10x_exmc.h:153
SNCTL_NRMUX_OFFSET
#define SNCTL_NRMUX_OFFSET
Definition: gd32f10x_exmc.c:35
BANK0_SNWTCFG_RESET
#define BANK0_SNWTCFG_RESET
Definition: gd32f10x_exmc.c:19
exmc_norsram_parameter_struct::nwait_polarity
uint32_t nwait_polarity
Definition: gd32f10x_exmc.h:158
EXMC_SNCTL_WRAPEN
#define EXMC_SNCTL_WRAPEN
Definition: gd32f10x_exmc.h:68
exmc_norsram_parameter_struct::nwait_signal
uint32_t nwait_signal
Definition: gd32f10x_exmc.h:154
SNCTL_SBRSTEN_OFFSET
#define SNCTL_SBRSTEN_OFFSET
Definition: gd32f10x_exmc.c:36
EXMC_SNCTL_EXMODEN
#define EXMC_SNCTL_EXMODEN
Definition: gd32f10x_exmc.h:72
EXMC_SNTCFG_BUSLAT
#define EXMC_SNTCFG_BUSLAT
Definition: gd32f10x_exmc.h:80
EXMC_SNWTCFG_WASET
#define EXMC_SNWTCFG_WASET
Definition: gd32f10x_exmc.h:86
SNTCFG_DSET_OFFSET
#define SNTCFG_DSET_OFFSET
Definition: gd32f10x_exmc.c:44
SNCTL_ASYNCWAIT_OFFSET
#define SNCTL_ASYNCWAIT_OFFSET
Definition: gd32f10x_exmc.c:41
SNCTL_WRAPEN_OFFSET
#define SNCTL_WRAPEN_OFFSET
Definition: gd32f10x_exmc.c:37
EXMC_SNCTL_WREN
#define EXMC_SNCTL_WREN
Definition: gd32f10x_exmc.h:70
EXMC_SNCTL_NRWTPOL
#define EXMC_SNCTL_NRWTPOL
Definition: gd32f10x_exmc.h:67
EXMC_SNCTL_NREN
#define EXMC_SNCTL_NREN
Definition: gd32f10x_exmc.h:65
EXMC_SNCTL_NRTP
#define EXMC_SNCTL_NRTP
Definition: gd32f10x_exmc.h:63
exmc_norsram_parameter_struct::wrap_burst_mode
uint32_t wrap_burst_mode
Definition: gd32f10x_exmc.h:157
exmc_norsram_parameter_struct::address_data_mux
uint32_t address_data_mux
Definition: gd32f10x_exmc.h:162
SNTCFG_AHLD_OFFSET
#define SNTCFG_AHLD_OFFSET
Definition: gd32f10x_exmc.c:43
SNTCFG_BUSLAT_OFFSET
#define SNTCFG_BUSLAT_OFFSET
Definition: gd32f10x_exmc.c:45
exmc_norsram_parameter_struct::memory_write
uint32_t memory_write
Definition: gd32f10x_exmc.h:155
exmc_norsram_timing_parameter_struct::asyn_address_holdtime
uint32_t asyn_address_holdtime
Definition: gd32f10x_exmc.h:143
EXMC_SNTCFG_DSET
#define EXMC_SNTCFG_DSET
Definition: gd32f10x_exmc.h:79
exmc_norsram_timing_parameter_struct::bus_latency
uint32_t bus_latency
Definition: gd32f10x_exmc.h:141
EXMC_SNTCFG_ASET
#define EXMC_SNTCFG_ASET
Definition: gd32f10x_exmc.h:77
EXMC_SNCTL_NRMUX
#define EXMC_SNCTL_NRMUX
Definition: gd32f10x_exmc.h:62
EXMC_SNCTL_NRWTCFG
#define EXMC_SNCTL_NRWTCFG
Definition: gd32f10x_exmc.h:69
exmc_norsram_timing_parameter_struct::syn_data_latency
uint32_t syn_data_latency
Definition: gd32f10x_exmc.h:139
void exmc_norsram_parameter_init ( exmc_norsram_parameter_struct * exmc_norsram_init_struct )

initialize the struct exmc_norsram_parameter_struct

Parameters
[in] | none
[out] | exmc_norsram_init_struct | the initialized struct exmc_norsram_parameter_struct pointer
Return values
none

Definition at line 170 of file gd32f10x_exmc.c.

171 {
172 /* configure the structure with default value */
173 exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
174 exmc_norsram_init_struct->address_data_mux = ENABLE;
175 exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
176 exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B;
177 exmc_norsram_init_struct->burst_mode = DISABLE;
178 exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
179 exmc_norsram_init_struct->wrap_burst_mode = DISABLE;
180 exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE;
181 exmc_norsram_init_struct->memory_write = ENABLE;
182 exmc_norsram_init_struct->nwait_signal = ENABLE;
183 exmc_norsram_init_struct->extended_mode = DISABLE;
184 exmc_norsram_init_struct->asyn_wait = DISABLE;
185 exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE;
186
187 /* read/write timing configure */
188 exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
189 exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
190 exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
191 exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
192 exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK;
193 exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK;
194 exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
195
196 /* write timing configure, when extended mode is used */
197 exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU;
198 exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU;
199 exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU;
200 exmc_norsram_init_struct->write_timing->bus_latency = 0xFU;
201 exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
202 }
EXMC_MEMORY_TYPE_SRAM
#define EXMC_MEMORY_TYPE_SRAM
Definition: gd32f10x_exmc.h:228
exmc_norsram_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:160
exmc_norsram_parameter_struct::extended_mode
uint32_t extended_mode
Definition: gd32f10x_exmc.h:152
exmc_norsram_timing_parameter_struct::asyn_data_setuptime
uint32_t asyn_data_setuptime
Definition: gd32f10x_exmc.h:142
exmc_norsram_parameter_struct::write_mode
uint32_t write_mode
Definition: gd32f10x_exmc.h:151
exmc_norsram_timing_parameter_struct::asyn_address_setuptime
uint32_t asyn_address_setuptime
Definition: gd32f10x_exmc.h:144
EXMC_ASYN_WRITE
#define EXMC_ASYN_WRITE
Definition: gd32f10x_exmc.h:336
exmc_norsram_parameter_struct::norsram_region
uint32_t norsram_region
Definition: gd32f10x_exmc.h:150
exmc_norsram_timing_parameter_struct::syn_clk_division
uint32_t syn_clk_division
Definition: gd32f10x_exmc.h:140
exmc_norsram_parameter_struct::nwait_config
uint32_t nwait_config
Definition: gd32f10x_exmc.h:156
exmc_norsram_parameter_struct::write_timing
exmc_norsram_timing_parameter_struct * write_timing
Definition: gd32f10x_exmc.h:165
exmc_norsram_timing_parameter_struct::asyn_access_mode
uint32_t asyn_access_mode
Definition: gd32f10x_exmc.h:138
exmc_norsram_parameter_struct::read_write_timing
exmc_norsram_timing_parameter_struct * read_write_timing
Definition: gd32f10x_exmc.h:163
exmc_norsram_parameter_struct::burst_mode
uint32_t burst_mode
Definition: gd32f10x_exmc.h:159
exmc_norsram_parameter_struct::memory_type
uint32_t memory_type
Definition: gd32f10x_exmc.h:161
exmc_norsram_parameter_struct::asyn_wait
uint32_t asyn_wait
Definition: gd32f10x_exmc.h:153
exmc_norsram_parameter_struct::nwait_polarity
uint32_t nwait_polarity
Definition: gd32f10x_exmc.h:158
EXMC_NWAIT_POLARITY_LOW
#define EXMC_NWAIT_POLARITY_LOW
Definition: gd32f10x_exmc.h:344
exmc_norsram_parameter_struct::nwait_signal
uint32_t nwait_signal
Definition: gd32f10x_exmc.h:154
EXMC_SYN_CLOCK_RATIO_16_CLK
#define EXMC_SYN_CLOCK_RATIO_16_CLK
Definition: gd32f10x_exmc.h:275
EXMC_ACCESS_MODE_A
#define EXMC_ACCESS_MODE_A
Definition: gd32f10x_exmc.h:234
EXMC_BANK0_NORSRAM_REGION0
#define EXMC_BANK0_NORSRAM_REGION0
Definition: gd32f10x_exmc.h:330
exmc_norsram_parameter_struct::wrap_burst_mode
uint32_t wrap_burst_mode
Definition: gd32f10x_exmc.h:157
exmc_norsram_parameter_struct::address_data_mux
uint32_t address_data_mux
Definition: gd32f10x_exmc.h:162
exmc_norsram_parameter_struct::memory_write
uint32_t memory_write
Definition: gd32f10x_exmc.h:155
EXMC_DATALAT_17_CLK
#define EXMC_DATALAT_17_CLK
Definition: gd32f10x_exmc.h:256
exmc_norsram_timing_parameter_struct::asyn_address_holdtime
uint32_t asyn_address_holdtime
Definition: gd32f10x_exmc.h:143
EXMC_NWAIT_CONFIG_BEFORE
#define EXMC_NWAIT_CONFIG_BEFORE
Definition: gd32f10x_exmc.h:340
exmc_norsram_timing_parameter_struct::bus_latency
uint32_t bus_latency
Definition: gd32f10x_exmc.h:141
EXMC_NOR_DATABUS_WIDTH_8B
#define EXMC_NOR_DATABUS_WIDTH_8B
Definition: gd32f10x_exmc.h:223
exmc_norsram_timing_parameter_struct::syn_data_latency
uint32_t syn_data_latency
Definition: gd32f10x_exmc.h:139
void exmc_pccard_deinit ( void )

deinitialize EXMC PC card bank

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 374 of file gd32f10x_exmc.c.

375 {
376 /* EXMC_BANK3_PCCARD */
377 EXMC_NPCTL3 = BANK3_NPCTL_RESET;
378 EXMC_NPINTEN3 = BANK3_NPINTEN_RESET;
379 EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET;
380 EXMC_NPATCFG3 = BANK3_NPATCFG_RESET;
381 EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET;
382 }
EXMC_NPATCFG3
#define EXMC_NPATCFG3
Definition: gd32f10x_exmc.h:55
EXMC_NPINTEN3
#define EXMC_NPINTEN3
Definition: gd32f10x_exmc.h:53
BANK3_PIOTCFG3_RESET
#define BANK3_PIOTCFG3_RESET
Definition: gd32f10x_exmc.c:32
BANK3_NPATCFG_RESET
#define BANK3_NPATCFG_RESET
Definition: gd32f10x_exmc.c:31
BANK3_NPINTEN_RESET
#define BANK3_NPINTEN_RESET
Definition: gd32f10x_exmc.c:29
EXMC_PIOTCFG3
#define EXMC_PIOTCFG3
Definition: gd32f10x_exmc.h:56
BANK3_NPCTCFG_RESET
#define BANK3_NPCTCFG_RESET
Definition: gd32f10x_exmc.c:30
EXMC_NPCTL3
#define EXMC_NPCTL3
Definition: gd32f10x_exmc.h:52
BANK3_NPCTL_RESET
#define BANK3_NPCTL_RESET
Definition: gd32f10x_exmc.c:28
EXMC_NPCTCFG3
#define EXMC_NPCTCFG3
Definition: gd32f10x_exmc.h:54
void exmc_pccard_disable ( void )

disable PC Card Bank

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 466 of file gd32f10x_exmc.c.

467 {
468 EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN;
469 }
EXMC_NPCTL3
#define EXMC_NPCTL3
Definition: gd32f10x_exmc.h:52
EXMC_NPCTL_NDBKEN
#define EXMC_NPCTL_NDBKEN
Definition: gd32f10x_exmc.h:96
void exmc_pccard_enable ( void )

enable PC Card Bank

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 455 of file gd32f10x_exmc.c.

456 {
457 EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN;
458 }
EXMC_NPCTL3
#define EXMC_NPCTL3
Definition: gd32f10x_exmc.h:52
EXMC_NPCTL_NDBKEN
#define EXMC_NPCTL_NDBKEN
Definition: gd32f10x_exmc.h:96
void exmc_pccard_init ( exmc_pccard_parameter_struct * exmc_pccard_init_struct )

initialize EXMC PC card bank

Parameters
[in] | exmc_pccard_parameter_struct | configure the EXMC NAND parameter atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 wait_feature: ENABLE or DISABLE common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time
[out] | none
Return values
none

Definition at line 396 of file gd32f10x_exmc.c.

397 {
398 /* configure the EXMC bank3 PC card control register */
399 EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) |
400 EXMC_NAND_DATABUS_WIDTH_16B |
401 exmc_pccard_init_struct->ctr_latency |
402 exmc_pccard_init_struct->atr_latency ;
403
404 /* configure the EXMC bank3 PC card common space timing configuration register */
405 EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) |
406 (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
407 ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
408 (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
409
410 /* configure the EXMC bank3 PC card attribute space timing configuration register */
411 EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
412 (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
413 ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )|
414 (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
415
416 /* configure the EXMC bank3 PC card io space timing configuration register */
417 EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) |
418 (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) |
419 ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )|
420 ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ );
421 }
EXMC_NPATCFG_ATTHLD
#define EXMC_NPATCFG_ATTHLD
Definition: gd32f10x_exmc.h:122
EXMC_NPATCFG3
#define EXMC_NPATCFG3
Definition: gd32f10x_exmc.h:55
exmc_pccard_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:195
NPATCFG_ATTHLD_OFFSET
#define NPATCFG_ATTHLD_OFFSET
Definition: gd32f10x_exmc.c:59
exmc_nand_pccard_timing_parameter_struct::waittime
uint32_t waittime
Definition: gd32f10x_exmc.h:173
EXMC_PIOTCFG3_IOSET
#define EXMC_PIOTCFG3_IOSET
Definition: gd32f10x_exmc.h:126
EXMC_NPCTCFG_COMSET
#define EXMC_NPCTCFG_COMSET
Definition: gd32f10x_exmc.h:114
EXMC_NPATCFG_ATTWAIT
#define EXMC_NPATCFG_ATTWAIT
Definition: gd32f10x_exmc.h:121
NPCTCFG_COMWAIT_OFFSET
#define NPCTCFG_COMWAIT_OFFSET
Definition: gd32f10x_exmc.c:54
EXMC_PIOTCFG3_IOHIZ
#define EXMC_PIOTCFG3_IOHIZ
Definition: gd32f10x_exmc.h:129
EXMC_NPATCFG_ATTHIZ
#define EXMC_NPATCFG_ATTHIZ
Definition: gd32f10x_exmc.h:123
EXMC_PIOTCFG3
#define EXMC_PIOTCFG3
Definition: gd32f10x_exmc.h:56
PIOTCFG_IOHIZ_OFFSET
#define PIOTCFG_IOHIZ_OFFSET
Definition: gd32f10x_exmc.c:64
exmc_nand_pccard_timing_parameter_struct::databus_hiztime
uint32_t databus_hiztime
Definition: gd32f10x_exmc.h:171
NPATCFG_ATTWAIT_OFFSET
#define NPATCFG_ATTWAIT_OFFSET
Definition: gd32f10x_exmc.c:58
EXMC_NPCTL3
#define EXMC_NPCTL3
Definition: gd32f10x_exmc.h:52
EXMC_NPCTCFG_COMWAIT
#define EXMC_NPCTCFG_COMWAIT
Definition: gd32f10x_exmc.h:115
EXMC_NPCTCFG_COMHLD
#define EXMC_NPCTCFG_COMHLD
Definition: gd32f10x_exmc.h:116
exmc_pccard_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:196
exmc_pccard_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:194
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
EXMC_PIOTCFG3_IOHLD
#define EXMC_PIOTCFG3_IOHLD
Definition: gd32f10x_exmc.h:128
exmc_pccard_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:197
EXMC_NPCTCFG3
#define EXMC_NPCTCFG3
Definition: gd32f10x_exmc.h:54
NPCTCFG_COMHLD_OFFSET
#define NPCTCFG_COMHLD_OFFSET
Definition: gd32f10x_exmc.c:55
exmc_pccard_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:198
NPATCFG_ATTHIZ_OFFSET
#define NPATCFG_ATTHIZ_OFFSET
Definition: gd32f10x_exmc.c:60
EXMC_NPATCFG_ATTSET
#define EXMC_NPATCFG_ATTSET
Definition: gd32f10x_exmc.h:120
PIOTCFG_IOWAIT_OFFSET
#define PIOTCFG_IOWAIT_OFFSET
Definition: gd32f10x_exmc.c:62
exmc_pccard_parameter_struct::io_space_timing
exmc_nand_pccard_timing_parameter_struct * io_space_timing
Definition: gd32f10x_exmc.h:199
PIOTCFG_IOHLD_OFFSET
#define PIOTCFG_IOHLD_OFFSET
Definition: gd32f10x_exmc.c:63
NPCTCFG_COMHIZ_OFFSET
#define NPCTCFG_COMHIZ_OFFSET
Definition: gd32f10x_exmc.c:56
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
EXMC_NPCTCFG_COMHIZ
#define EXMC_NPCTCFG_COMHIZ
Definition: gd32f10x_exmc.h:117
EXMC_PIOTCFG3_IOWAIT
#define EXMC_PIOTCFG3_IOWAIT
Definition: gd32f10x_exmc.h:127
EXMC_NAND_DATABUS_WIDTH_16B
#define EXMC_NAND_DATABUS_WIDTH_16B
Definition: gd32f10x_exmc.h:327
NPCTL_NDWTEN_OFFSET
#define NPCTL_NDWTEN_OFFSET
Definition: gd32f10x_exmc.c:51
void exmc_pccard_parameter_init ( exmc_pccard_parameter_struct * exmc_pccard_init_struct )

initialize the struct exmc_pccard_parameter_struct

Parameters
[in] | none
[out] | the | initialized struct exmc_pccard_parameter_struct pointer
Return values
none

Definition at line 429 of file gd32f10x_exmc.c.

430 {
431 /* configure the structure with default value */
432 exmc_pccard_init_struct->wait_feature = DISABLE;
433 exmc_pccard_init_struct->ctr_latency = 0x0U;
434 exmc_pccard_init_struct->atr_latency = 0x0U;
435 exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU;
436 exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU;
437 exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU;
438 exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU;
439 exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU;
440 exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU;
441 exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU;
442 exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
443 exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU;
444 exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU;
445 exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU;
446 exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU;
447 }
exmc_pccard_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:195
exmc_nand_pccard_timing_parameter_struct::waittime
uint32_t waittime
Definition: gd32f10x_exmc.h:173
exmc_nand_pccard_timing_parameter_struct::databus_hiztime
uint32_t databus_hiztime
Definition: gd32f10x_exmc.h:171
exmc_pccard_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:196
exmc_pccard_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:194
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
exmc_pccard_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:197
exmc_pccard_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:198
exmc_pccard_parameter_struct::io_space_timing
exmc_nand_pccard_timing_parameter_struct * io_space_timing
Definition: gd32f10x_exmc.h:199
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f10x_exti.h File Reference

definitions for the EXTI More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | EXTI EXTI_BASE
#define | EXTI_INTEN REG32(EXTI + 0x00U)
#define | EXTI_EVEN REG32(EXTI + 0x04U)
#define | EXTI_RTEN REG32(EXTI + 0x08U)
#define | EXTI_FTEN REG32(EXTI + 0x0CU)
#define | EXTI_SWIEV REG32(EXTI + 0x10U)
#define | EXTI_PD REG32(EXTI + 0x14U)
#define | EXTI_INTEN_INTEN0 BIT(0)
#define | EXTI_INTEN_INTEN1 BIT(1)
#define | EXTI_INTEN_INTEN2 BIT(2)
#define | EXTI_INTEN_INTEN3 BIT(3)
#define | EXTI_INTEN_INTEN4 BIT(4)
#define | EXTI_INTEN_INTEN5 BIT(5)
#define | EXTI_INTEN_INTEN6 BIT(6)
#define | EXTI_INTEN_INTEN7 BIT(7)
#define | EXTI_INTEN_INTEN8 BIT(8)
#define | EXTI_INTEN_INTEN9 BIT(9)
#define | EXTI_INTEN_INTEN10 BIT(10)
#define | EXTI_INTEN_INTEN11 BIT(11)
#define | EXTI_INTEN_INTEN12 BIT(12)
#define | EXTI_INTEN_INTEN13 BIT(13)
#define | EXTI_INTEN_INTEN14 BIT(14)
#define | EXTI_INTEN_INTEN15 BIT(15)
#define | EXTI_INTEN_INTEN16 BIT(16)
#define | EXTI_INTEN_INTEN17 BIT(17)
#define | EXTI_INTEN_INTEN18 BIT(18)
#define | EXTI_INTEN_INTEN19 BIT(19)
#define | EXTI_EVEN_EVEN0 BIT(0)
#define | EXTI_EVEN_EVEN1 BIT(1)
#define | EXTI_EVEN_EVEN2 BIT(2)
#define | EXTI_EVEN_EVEN3 BIT(3)
#define | EXTI_EVEN_EVEN4 BIT(4)
#define | EXTI_EVEN_EVEN5 BIT(5)
#define | EXTI_EVEN_EVEN6 BIT(6)
#define | EXTI_EVEN_EVEN7 BIT(7)
#define | EXTI_EVEN_EVEN8 BIT(8)
#define | EXTI_EVEN_EVEN9 BIT(9)
#define | EXTI_EVEN_EVEN10 BIT(10)
#define | EXTI_EVEN_EVEN11 BIT(11)
#define | EXTI_EVEN_EVEN12 BIT(12)
#define | EXTI_EVEN_EVEN13 BIT(13)
#define | EXTI_EVEN_EVEN14 BIT(14)
#define | EXTI_EVEN_EVEN15 BIT(15)
#define | EXTI_EVEN_EVEN16 BIT(16)
#define | EXTI_EVEN_EVEN17 BIT(17)
#define | EXTI_EVEN_EVEN18 BIT(18)
#define | EXTI_EVEN_EVEN19 BIT(19)
#define | EXTI_RTEN_RTEN0 BIT(0)
#define | EXTI_RTEN_RTEN1 BIT(1)
#define | EXTI_RTEN_RTEN2 BIT(2)
#define | EXTI_RTEN_RTEN3 BIT(3)
#define | EXTI_RTEN_RTEN4 BIT(4)
#define | EXTI_RTEN_RTEN5 BIT(5)
#define | EXTI_RTEN_RTEN6 BIT(6)
#define | EXTI_RTEN_RTEN7 BIT(7)
#define | EXTI_RTEN_RTEN8 BIT(8)
#define | EXTI_RTEN_RTEN9 BIT(9)
#define | EXTI_RTEN_RTEN10 BIT(10)
#define | EXTI_RTEN_RTEN11 BIT(11)
#define | EXTI_RTEN_RTEN12 BIT(12)
#define | EXTI_RTEN_RTEN13 BIT(13)
#define | EXTI_RTEN_RTEN14 BIT(14)
#define | EXTI_RTEN_RTEN15 BIT(15)
#define | EXTI_RTEN_RTEN16 BIT(16)
#define | EXTI_RTEN_RTEN17 BIT(17)
#define | EXTI_RTEN_RTEN18 BIT(18)
#define | EXTI_RTEN_RTEN19 BIT(19)
#define | EXTI_FTEN_FTEN0 BIT(0)
#define | EXTI_FTEN_FTEN1 BIT(1)
#define | EXTI_FTEN_FTEN2 BIT(2)
#define | EXTI_FTEN_FTEN3 BIT(3)
#define | EXTI_FTEN_FTEN4 BIT(4)
#define | EXTI_FTEN_FTEN5 BIT(5)
#define | EXTI_FTEN_FTEN6 BIT(6)
#define | EXTI_FTEN_FTEN7 BIT(7)
#define | EXTI_FTEN_FTEN8 BIT(8)
#define | EXTI_FTEN_FTEN9 BIT(9)
#define | EXTI_FTEN_FTEN10 BIT(10)
#define | EXTI_FTEN_FTEN11 BIT(11)
#define | EXTI_FTEN_FTEN12 BIT(12)
#define | EXTI_FTEN_FTEN13 BIT(13)
#define | EXTI_FTEN_FTEN14 BIT(14)
#define | EXTI_FTEN_FTEN15 BIT(15)
#define | EXTI_FTEN_FTEN16 BIT(16)
#define | EXTI_FTEN_FTEN17 BIT(17)
#define | EXTI_FTEN_FTEN18 BIT(18)
#define | EXTI_FTEN_FTEN19 BIT(19)
#define | EXTI_SWIEV_SWIEV0 BIT(0)
#define | EXTI_SWIEV_SWIEV1 BIT(1)
#define | EXTI_SWIEV_SWIEV2 BIT(2)
#define | EXTI_SWIEV_SWIEV3 BIT(3)
#define | EXTI_SWIEV_SWIEV4 BIT(4)
#define | EXTI_SWIEV_SWIEV5 BIT(5)
#define | EXTI_SWIEV_SWIEV6 BIT(6)
#define | EXTI_SWIEV_SWIEV7 BIT(7)
#define | EXTI_SWIEV_SWIEV8 BIT(8)
#define | EXTI_SWIEV_SWIEV9 BIT(9)
#define | EXTI_SWIEV_SWIEV10 BIT(10)
#define | EXTI_SWIEV_SWIEV11 BIT(11)
#define | EXTI_SWIEV_SWIEV12 BIT(12)
#define | EXTI_SWIEV_SWIEV13 BIT(13)
#define | EXTI_SWIEV_SWIEV14 BIT(14)
#define | EXTI_SWIEV_SWIEV15 BIT(15)
#define | EXTI_SWIEV_SWIEV16 BIT(16)
#define | EXTI_SWIEV_SWIEV17 BIT(17)
#define | EXTI_SWIEV_SWIEV18 BIT(18)
#define | EXTI_SWIEV_SWIEV19 BIT(19)
#define | EXTI_PD_PD0 BIT(0)
#define | EXTI_PD_PD1 BIT(1)
#define | EXTI_PD_PD2 BIT(2)
#define | EXTI_PD_PD3 BIT(3)
#define | EXTI_PD_PD4 BIT(4)
#define | EXTI_PD_PD5 BIT(5)
#define | EXTI_PD_PD6 BIT(6)
#define | EXTI_PD_PD7 BIT(7)
#define | EXTI_PD_PD8 BIT(8)
#define | EXTI_PD_PD9 BIT(9)
#define | EXTI_PD_PD10 BIT(10)
#define | EXTI_PD_PD11 BIT(11)
#define | EXTI_PD_PD12 BIT(12)
#define | EXTI_PD_PD13 BIT(13)
#define | EXTI_PD_PD14 BIT(14)
#define | EXTI_PD_PD15 BIT(15)
#define | EXTI_PD_PD16 BIT(16)
#define | EXTI_PD_PD17 BIT(17)
#define | EXTI_PD_PD18 BIT(18)
#define | EXTI_PD_PD19 BIT(19)

Enumerations

enum exti_line_enum {
EXTI_0 = BIT(0), EXTI_1 = BIT(1), EXTI_2 = BIT(2), EXTI_3 = BIT(3),
EXTI_4 = BIT(4), EXTI_5 = BIT(5), EXTI_6 = BIT(6), EXTI_7 = BIT(7),
EXTI_8 = BIT(8), EXTI_9 = BIT(9), EXTI_10 = BIT(10), EXTI_11 = BIT(11),
EXTI_12 = BIT(12), EXTI_13 = BIT(13), EXTI_14 = BIT(14), EXTI_15 = BIT(15),
EXTI_16 = BIT(16), EXTI_17 = BIT(17), EXTI_18 = BIT(18), EXTI_19 = BIT(19)
}
enum | exti_mode_enum { EXTI_INTERRUPT = 0, EXTI_EVENT }
enum | exti_trig_type_enum { EXTI_TRIG_RISING = 0, EXTI_TRIG_FALLING, EXTI_TRIG_BOTH }

Functions

void | exti_deinit (void)
deinitialize the EXTI More...
void | exti_init (exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
initialize the EXTI More...
void | exti_interrupt_enable (exti_line_enum linex)
enable the interrupts from EXTI line x More...
void | exti_event_enable (exti_line_enum linex)
enable the events from EXTI line x More...
void | exti_interrupt_disable (exti_line_enum linex)
disable the interrupt from EXTI line x More...
void | exti_event_disable (exti_line_enum linex)
disable the events from EXTI line x More...
FlagStatus | exti_flag_get (exti_line_enum linex)
get EXTI lines flag More...
void | exti_flag_clear (exti_line_enum linex)
clear EXTI lines pending flag More...
FlagStatus | exti_interrupt_flag_get (exti_line_enum linex)
get EXTI lines flag when the interrupt flag is set More...
void | exti_interrupt_flag_clear (exti_line_enum linex)
clear EXTI lines pending flag More...
void | exti_software_interrupt_enable (exti_line_enum linex)
enable EXTI software interrupt event More...
void | exti_software_interrupt_disable (exti_line_enum linex)
disable EXTI software interrupt event More...

Detailed Description

definitions for the EXTI

Definition in file gd32f10x_exti.h.

Macro Definition Documentation

#define EXTI EXTI_BASE

Definition at line 19 of file gd32f10x_exti.h.

#define EXTI_EVEN REG32(EXTI + 0x04U)

event enable register

Definition at line 23 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN0 BIT(0)

event from line 0

Definition at line 53 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN1 BIT(1)

event from line 1

Definition at line 54 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN10 BIT(10)

event from line 10

Definition at line 63 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN11 BIT(11)

event from line 11

Definition at line 64 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN12 BIT(12)

event from line 12

Definition at line 65 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN13 BIT(13)

event from line 13

Definition at line 66 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN14 BIT(14)

event from line 14

Definition at line 67 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN15 BIT(15)

event from line 15

Definition at line 68 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN16 BIT(16)

event from line 16

Definition at line 69 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN17 BIT(17)

event from line 17

Definition at line 70 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN18 BIT(18)

event from line 18

Definition at line 71 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN19 BIT(19)

event from line 19

Definition at line 72 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN2 BIT(2)

event from line 2

Definition at line 55 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN3 BIT(3)

event from line 3

Definition at line 56 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN4 BIT(4)

event from line 4

Definition at line 57 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN5 BIT(5)

event from line 5

Definition at line 58 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN6 BIT(6)

event from line 6

Definition at line 59 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN7 BIT(7)

event from line 7

Definition at line 60 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN8 BIT(8)

event from line 8

Definition at line 61 of file gd32f10x_exti.h.

#define EXTI_EVEN_EVEN9 BIT(9)

event from line 9

Definition at line 62 of file gd32f10x_exti.h.

#define EXTI_FTEN REG32(EXTI + 0x0CU)

falling trigger enable register

Definition at line 25 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN0 BIT(0)

falling edge from line 0

Definition at line 97 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN1 BIT(1)

falling edge from line 1

Definition at line 98 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN10 BIT(10)

falling edge from line 10

Definition at line 107 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN11 BIT(11)

falling edge from line 11

Definition at line 108 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN12 BIT(12)

falling edge from line 12

Definition at line 109 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN13 BIT(13)

falling edge from line 13

Definition at line 110 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN14 BIT(14)

falling edge from line 14

Definition at line 111 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN15 BIT(15)

falling edge from line 15

Definition at line 112 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN16 BIT(16)

falling edge from line 16

Definition at line 113 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN17 BIT(17)

falling edge from line 17

Definition at line 114 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN18 BIT(18)

falling edge from line 18

Definition at line 115 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN19 BIT(19)

falling edge from line 19

Definition at line 116 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN2 BIT(2)

falling edge from line 2

Definition at line 99 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN3 BIT(3)

falling edge from line 3

Definition at line 100 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN4 BIT(4)

falling edge from line 4

Definition at line 101 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN5 BIT(5)

falling edge from line 5

Definition at line 102 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN6 BIT(6)

falling edge from line 6

Definition at line 103 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN7 BIT(7)

falling edge from line 7

Definition at line 104 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN8 BIT(8)

falling edge from line 8

Definition at line 105 of file gd32f10x_exti.h.

#define EXTI_FTEN_FTEN9 BIT(9)

falling edge from line 9

Definition at line 106 of file gd32f10x_exti.h.

#define EXTI_INTEN REG32(EXTI + 0x00U)

interrupt enable register

Definition at line 22 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN0 BIT(0)

interrupt from line 0

Definition at line 31 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN1 BIT(1)

interrupt from line 1

Definition at line 32 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN10 BIT(10)

interrupt from line 10

Definition at line 41 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN11 BIT(11)

interrupt from line 11

Definition at line 42 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN12 BIT(12)

interrupt from line 12

Definition at line 43 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN13 BIT(13)

interrupt from line 13

Definition at line 44 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN14 BIT(14)

interrupt from line 14

Definition at line 45 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN15 BIT(15)

interrupt from line 15

Definition at line 46 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN16 BIT(16)

interrupt from line 16

Definition at line 47 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN17 BIT(17)

interrupt from line 17

Definition at line 48 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN18 BIT(18)

interrupt from line 18

Definition at line 49 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN19 BIT(19)

interrupt from line 19

Definition at line 50 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN2 BIT(2)

interrupt from line 2

Definition at line 33 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN3 BIT(3)

interrupt from line 3

Definition at line 34 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN4 BIT(4)

interrupt from line 4

Definition at line 35 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN5 BIT(5)

interrupt from line 5

Definition at line 36 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN6 BIT(6)

interrupt from line 6

Definition at line 37 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN7 BIT(7)

interrupt from line 7

Definition at line 38 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN8 BIT(8)

interrupt from line 8

Definition at line 39 of file gd32f10x_exti.h.

#define EXTI_INTEN_INTEN9 BIT(9)

interrupt from line 9

Definition at line 40 of file gd32f10x_exti.h.

#define EXTI_PD REG32(EXTI + 0x14U)

pending register

Definition at line 27 of file gd32f10x_exti.h.

#define EXTI_PD_PD0 BIT(0)

interrupt/event pending status from line 0

Definition at line 141 of file gd32f10x_exti.h.

#define EXTI_PD_PD1 BIT(1)

interrupt/event pending status from line 1

Definition at line 142 of file gd32f10x_exti.h.

#define EXTI_PD_PD10 BIT(10)

interrupt/event pending status from line 10

Definition at line 151 of file gd32f10x_exti.h.

#define EXTI_PD_PD11 BIT(11)

interrupt/event pending status from line 11

Definition at line 152 of file gd32f10x_exti.h.

#define EXTI_PD_PD12 BIT(12)

interrupt/event pending status from line 12

Definition at line 153 of file gd32f10x_exti.h.

#define EXTI_PD_PD13 BIT(13)

interrupt/event pending status from line 13

Definition at line 154 of file gd32f10x_exti.h.

#define EXTI_PD_PD14 BIT(14)

interrupt/event pending status from line 14

Definition at line 155 of file gd32f10x_exti.h.

#define EXTI_PD_PD15 BIT(15)

interrupt/event pending status from line 15

Definition at line 156 of file gd32f10x_exti.h.

#define EXTI_PD_PD16 BIT(16)

interrupt/event pending status from line 16

Definition at line 157 of file gd32f10x_exti.h.

#define EXTI_PD_PD17 BIT(17)

interrupt/event pending status from line 17

Definition at line 158 of file gd32f10x_exti.h.

#define EXTI_PD_PD18 BIT(18)

interrupt/event pending status from line 18

Definition at line 159 of file gd32f10x_exti.h.

#define EXTI_PD_PD19 BIT(19)

interrupt/event pending status from line 19

Definition at line 160 of file gd32f10x_exti.h.

#define EXTI_PD_PD2 BIT(2)

interrupt/event pending status from line 2

Definition at line 143 of file gd32f10x_exti.h.

#define EXTI_PD_PD3 BIT(3)

interrupt/event pending status from line 3

Definition at line 144 of file gd32f10x_exti.h.

#define EXTI_PD_PD4 BIT(4)

interrupt/event pending status from line 4

Definition at line 145 of file gd32f10x_exti.h.

#define EXTI_PD_PD5 BIT(5)

interrupt/event pending status from line 5

Definition at line 146 of file gd32f10x_exti.h.

#define EXTI_PD_PD6 BIT(6)

interrupt/event pending status from line 6

Definition at line 147 of file gd32f10x_exti.h.

#define EXTI_PD_PD7 BIT(7)

interrupt/event pending status from line 7

Definition at line 148 of file gd32f10x_exti.h.

#define EXTI_PD_PD8 BIT(8)

interrupt/event pending status from line 8

Definition at line 149 of file gd32f10x_exti.h.

#define EXTI_PD_PD9 BIT(9)

interrupt/event pending status from line 9

Definition at line 150 of file gd32f10x_exti.h.

#define EXTI_RTEN REG32(EXTI + 0x08U)

rising edge trigger enable register

Definition at line 24 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN0 BIT(0)

rising edge from line 0

Definition at line 75 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN1 BIT(1)

rising edge from line 1

Definition at line 76 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN10 BIT(10)

rising edge from line 10

Definition at line 85 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN11 BIT(11)

rising edge from line 11

Definition at line 86 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN12 BIT(12)

rising edge from line 12

Definition at line 87 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN13 BIT(13)

rising edge from line 13

Definition at line 88 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN14 BIT(14)

rising edge from line 14

Definition at line 89 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN15 BIT(15)

rising edge from line 15

Definition at line 90 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN16 BIT(16)

rising edge from line 16

Definition at line 91 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN17 BIT(17)

rising edge from line 17

Definition at line 92 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN18 BIT(18)

rising edge from line 18

Definition at line 93 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN19 BIT(19)

rising edge from line 19

Definition at line 94 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN2 BIT(2)

rising edge from line 2

Definition at line 77 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN3 BIT(3)

rising edge from line 3

Definition at line 78 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN4 BIT(4)

rising edge from line 4

Definition at line 79 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN5 BIT(5)

rising edge from line 5

Definition at line 80 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN6 BIT(6)

rising edge from line 6

Definition at line 81 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN7 BIT(7)

rising edge from line 7

Definition at line 82 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN8 BIT(8)

rising edge from line 8

Definition at line 83 of file gd32f10x_exti.h.

#define EXTI_RTEN_RTEN9 BIT(9)

rising edge from line 9

Definition at line 84 of file gd32f10x_exti.h.

#define EXTI_SWIEV REG32(EXTI + 0x10U)

software interrupt event register

Definition at line 26 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV0 BIT(0)

software interrupt/event request from line 0

Definition at line 119 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV1 BIT(1)

software interrupt/event request from line 1

Definition at line 120 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV10 BIT(10)

software interrupt/event request from line 10

Definition at line 129 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV11 BIT(11)

software interrupt/event request from line 11

Definition at line 130 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV12 BIT(12)

software interrupt/event request from line 12

Definition at line 131 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV13 BIT(13)

software interrupt/event request from line 13

Definition at line 132 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV14 BIT(14)

software interrupt/event request from line 14

Definition at line 133 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV15 BIT(15)

software interrupt/event request from line 15

Definition at line 134 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV16 BIT(16)

software interrupt/event request from line 16

Definition at line 135 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV17 BIT(17)

software interrupt/event request from line 17

Definition at line 136 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV18 BIT(18)

software interrupt/event request from line 18

Definition at line 137 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV19 BIT(19)

software interrupt/event request from line 19

Definition at line 138 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV2 BIT(2)

software interrupt/event request from line 2

Definition at line 121 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV3 BIT(3)

software interrupt/event request from line 3

Definition at line 122 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV4 BIT(4)

software interrupt/event request from line 4

Definition at line 123 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV5 BIT(5)

software interrupt/event request from line 5

Definition at line 124 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV6 BIT(6)

software interrupt/event request from line 6

Definition at line 125 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV7 BIT(7)

software interrupt/event request from line 7

Definition at line 126 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV8 BIT(8)

software interrupt/event request from line 8

Definition at line 127 of file gd32f10x_exti.h.

#define EXTI_SWIEV_SWIEV9 BIT(9)

software interrupt/event request from line 9

Definition at line 128 of file gd32f10x_exti.h.

Enumeration Type Documentation

enum exti_line_enum
Enumerator
EXTI_0 | EXTI line 0
EXTI_1 | EXTI line 1
EXTI_2 | EXTI line 2
EXTI_3 | EXTI line 3
EXTI_4 | EXTI line 4
EXTI_5 | EXTI line 5
EXTI_6 | EXTI line 6
EXTI_7 | EXTI line 7
EXTI_8 | EXTI line 8
EXTI_9 | EXTI line 9
EXTI_10 | EXTI line 10
EXTI_11 | EXTI line 11
EXTI_12 | EXTI line 12
EXTI_13 | EXTI line 13
EXTI_14 | EXTI line 14
EXTI_15 | EXTI line 15
EXTI_16 | EXTI line 16
EXTI_17 | EXTI line 17
EXTI_18 | EXTI line 18
EXTI_19 | EXTI line 19

Definition at line 164 of file gd32f10x_exti.h.

165 {
166 EXTI_0 = BIT(0),
167 EXTI_1 = BIT(1),
168 EXTI_2 = BIT(2),
169 EXTI_3 = BIT(3),
170 EXTI_4 = BIT(4),
171 EXTI_5 = BIT(5),
172 EXTI_6 = BIT(6),
173 EXTI_7 = BIT(7),
174 EXTI_8 = BIT(8),
175 EXTI_9 = BIT(9),
176 EXTI_10 = BIT(10),
177 EXTI_11 = BIT(11),
178 EXTI_12 = BIT(12),
179 EXTI_13 = BIT(13),
180 EXTI_14 = BIT(14),
181 EXTI_15 = BIT(15),
182 EXTI_16 = BIT(16),
183 EXTI_17 = BIT(17),
184 EXTI_18 = BIT(18),
185 EXTI_19 = BIT(19),
186 }exti_line_enum;
EXTI_2
Definition: gd32f10x_exti.h:168
EXTI_10
Definition: gd32f10x_exti.h:176
EXTI_19
Definition: gd32f10x_exti.h:185
EXTI_16
Definition: gd32f10x_exti.h:182
EXTI_6
Definition: gd32f10x_exti.h:172
EXTI_5
Definition: gd32f10x_exti.h:171
EXTI_15
Definition: gd32f10x_exti.h:181
EXTI_4
Definition: gd32f10x_exti.h:170
exti_line_enum
exti_line_enum
Definition: gd32f10x_exti.h:164
EXTI_11
Definition: gd32f10x_exti.h:177
EXTI_9
Definition: gd32f10x_exti.h:175
EXTI_18
Definition: gd32f10x_exti.h:184
EXTI_8
Definition: gd32f10x_exti.h:174
EXTI_3
Definition: gd32f10x_exti.h:169
EXTI_0
Definition: gd32f10x_exti.h:166
EXTI_14
Definition: gd32f10x_exti.h:180
EXTI_7
Definition: gd32f10x_exti.h:173
EXTI_13
Definition: gd32f10x_exti.h:179
EXTI_17
Definition: gd32f10x_exti.h:183
EXTI_12
Definition: gd32f10x_exti.h:178
EXTI_1
Definition: gd32f10x_exti.h:167
enum exti_mode_enum
Enumerator
EXTI_INTERRUPT | EXTI interrupt mode
EXTI_EVENT | EXTI event mode

Definition at line 189 of file gd32f10x_exti.h.

190 {
191 EXTI_INTERRUPT = 0,
192 EXTI_EVENT
193 }exti_mode_enum;
EXTI_INTERRUPT
Definition: gd32f10x_exti.h:191
exti_mode_enum
exti_mode_enum
Definition: gd32f10x_exti.h:189
EXTI_EVENT
Definition: gd32f10x_exti.h:192
enum exti_trig_type_enum
Enumerator
EXTI_TRIG_RISING | EXTI rising edge trigger
EXTI_TRIG_FALLING | EXTI falling edge trigger
EXTI_TRIG_BOTH | EXTI rising and falling edge trigger

Definition at line 196 of file gd32f10x_exti.h.

197 {
198 EXTI_TRIG_RISING = 0,
199 EXTI_TRIG_FALLING,
200 EXTI_TRIG_BOTH
201 }exti_trig_type_enum;
EXTI_TRIG_FALLING
Definition: gd32f10x_exti.h:199
EXTI_TRIG_BOTH
Definition: gd32f10x_exti.h:200
EXTI_TRIG_RISING
Definition: gd32f10x_exti.h:198
exti_trig_type_enum
exti_trig_type_enum
Definition: gd32f10x_exti.h:196

Function Documentation

void exti_deinit ( void )

deinitialize the EXTI

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_exti.c.

22 {
23 /* reset the value of all the EXTI registers */
24 EXTI_INTEN = (uint32_t)0x00000000U;
25 EXTI_EVEN = (uint32_t)0x00000000U;
26 EXTI_RTEN = (uint32_t)0x00000000U;
27 EXTI_FTEN = (uint32_t)0x00000000U;
28 EXTI_SWIEV = (uint32_t)0x00000000U;
29 }
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f10x_exti.h:25
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f10x_exti.h:23
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f10x_exti.h:26
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f10x_exti.h:24
void exti_event_disable ( exti_line_enum linex )

disable the events from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 134 of file gd32f10x_exti.c.

135 {
136 EXTI_EVEN &= ~(uint32_t)linex;
137 }
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f10x_exti.h:23
void exti_event_enable ( exti_line_enum linex )

enable the events from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 108 of file gd32f10x_exti.c.

109 {
110 EXTI_EVEN |= (uint32_t)linex;
111 }
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f10x_exti.h:23
void exti_flag_clear ( exti_line_enum linex )

clear EXTI lines pending flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 164 of file gd32f10x_exti.c.

165 {
166 EXTI_PD = (uint32_t)linex;
167 }
EXTI_PD
#define EXTI_PD
Definition: gd32f10x_exti.h:27
FlagStatus exti_flag_get ( exti_line_enum linex )

get EXTI lines flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
FlagStatus status of flag (RESET or SET)

Definition at line 147 of file gd32f10x_exti.c.

148 {
149 if(RESET != (EXTI_PD & (uint32_t)linex)){
150 return SET;
151 }else{
152 return RESET;
153 }
154 }
EXTI_PD
#define EXTI_PD
Definition: gd32f10x_exti.h:27
void exti_init | ( | exti_line_enum | linex,
 |  | exti_mode_enum | mode,
 |  | exti_trig_type_enum | trig_type
 | ) |  |

initialize the EXTI

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[in] mode interrupt or event mode, refer to exti_mode_enum only one parameter can be selected which is shown as below:
  • EXTI_INTERRUPT: interrupt mode
  • EXTI_EVENT: event mode
[in] trig_type interrupt trigger type, refer to exti_trig_type_enum only one parameter can be selected which is shown as below:
  • EXTI_TRIG_RISING: rising edge trigger
  • EXTI_TRIG_FALLING: falling trigger
  • EXTI_TRIG_BOTH: rising and falling trigger
[out] none
Return values
none

Definition at line 48 of file gd32f10x_exti.c.

49 {
50 /* reset the EXTI line x */
51 EXTI_INTEN &= ~(uint32_t)linex;
52 EXTI_EVEN &= ~(uint32_t)linex;
53 EXTI_RTEN &= ~(uint32_t)linex;
54 EXTI_FTEN &= ~(uint32_t)linex;
55
56 /* set the EXTI mode and enable the interrupts or events from EXTI line x */
57 switch(mode){
58 case EXTI_INTERRUPT:
59 EXTI_INTEN |= (uint32_t)linex;
60 break;
61 case EXTI_EVENT:
62 EXTI_EVEN |= (uint32_t)linex;
63 break;
64 default:
65 break;
66 }
67
68 /* set the EXTI trigger type */
69 switch(trig_type){
70 case EXTI_TRIG_RISING:
71 EXTI_RTEN |= (uint32_t)linex;
72 EXTI_FTEN &= ~(uint32_t)linex;
73 break;
74 case EXTI_TRIG_FALLING:
75 EXTI_RTEN &= ~(uint32_t)linex;
76 EXTI_FTEN |= (uint32_t)linex;
77 break;
78 case EXTI_TRIG_BOTH:
79 EXTI_RTEN |= (uint32_t)linex;
80 EXTI_FTEN |= (uint32_t)linex;
81 break;
82 default:
83 break;
84 }
85 }
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f10x_exti.h:25
EXTI_INTERRUPT
Definition: gd32f10x_exti.h:191
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
EXTI_TRIG_FALLING
Definition: gd32f10x_exti.h:199
EXTI_TRIG_BOTH
Definition: gd32f10x_exti.h:200
EXTI_TRIG_RISING
Definition: gd32f10x_exti.h:198
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f10x_exti.h:23
EXTI_EVENT
Definition: gd32f10x_exti.h:192
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f10x_exti.h:24
void exti_interrupt_disable ( exti_line_enum linex )

disable the interrupt from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 121 of file gd32f10x_exti.c.

122 {
123 EXTI_INTEN &= ~(uint32_t)linex;
124 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
void exti_interrupt_enable ( exti_line_enum linex )

enable the interrupts from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 95 of file gd32f10x_exti.c.

96 {
97 EXTI_INTEN |= (uint32_t)linex;
98 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
void exti_interrupt_flag_clear ( exti_line_enum linex )

clear EXTI lines pending flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 199 of file gd32f10x_exti.c.

200 {
201 EXTI_PD = (uint32_t)linex;
202 }
EXTI_PD
#define EXTI_PD
Definition: gd32f10x_exti.h:27
FlagStatus exti_interrupt_flag_get ( exti_line_enum linex )

get EXTI lines flag when the interrupt flag is set

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
FlagStatus status of flag (RESET or SET)

Definition at line 177 of file gd32f10x_exti.c.

178 {
179 uint32_t flag_left, flag_right;
180
181 flag_left = EXTI_PD & (uint32_t)linex;
182 flag_right = EXTI_INTEN & (uint32_t)linex;
183
184 if((RESET != flag_left) && (RESET != flag_right)){
185 return SET;
186 }else{
187 return RESET;
188 }
189 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
EXTI_PD
#define EXTI_PD
Definition: gd32f10x_exti.h:27
void exti_software_interrupt_disable ( exti_line_enum linex )

disable EXTI software interrupt event

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 225 of file gd32f10x_exti.c.

226 {
227 EXTI_SWIEV &= ~(uint32_t)linex;
228 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f10x_exti.h:26
void exti_software_interrupt_enable ( exti_line_enum linex )

enable EXTI software interrupt event

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 212 of file gd32f10x_exti.c.

213 {
214 EXTI_SWIEV |= (uint32_t)linex;
215 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f10x_exti.h:26
Generated on Tue Jul 18 2017 09:24:15 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f10x_fmc.h File Reference

definitions for the FMC More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | FMC FMC_BASE
#define | OB OB_BASE
#define | FMC_WS REG32((FMC) + 0x00U)
#define | FMC_KEY0 REG32((FMC) + 0x04U)
#define | FMC_OBKEY REG32((FMC) + 0x08U)
#define | FMC_STAT0 REG32((FMC) + 0x0CU)
#define | FMC_CTL0 REG32((FMC) + 0x10U)
#define | FMC_ADDR0 REG32((FMC) + 0x14U)
#define | FMC_OBSTAT REG32((FMC) + 0x1CU)
#define | FMC_WP REG32((FMC) + 0x20U)
#define | FMC_KEY1 REG32((FMC) + 0x44U)
#define | FMC_STAT1 REG32((FMC) + 0x4CU)
#define | FMC_CTL1 REG32((FMC) + 0x50U)
#define | FMC_ADDR1 REG32((FMC) + 0x54U)
#define | FMC_WSEN REG32((FMC) + 0xFCU)
#define | FMC_PID REG32((FMC) + 0x100U)
#define | OB_SPC REG16((OB) + 0x00U)
#define | OB_USER REG16((OB) + 0x02U)
#define | OB_WP0 REG16((OB) + 0x08U)
#define | OB_WP1 REG16((OB) + 0x0AU)
#define | OB_WP2 REG16((OB) + 0x0CU)
#define | OB_WP3 REG16((OB) + 0x0EU)
#define | FMC_WS_WSCNT BITS(0,2)
#define | FMC_KEY0_KEY BITS(0,31)
#define | FMC_OBKEY_OBKEY BITS(0,31)
#define | FMC_STAT0_BUSY BIT(0)
#define | FMC_STAT0_PGERR BIT(2)
#define | FMC_STAT0_WPERR BIT(4)
#define | FMC_STAT0_ENDF BIT(5)
#define | FMC_CTL0_PG BIT(0)
#define | FMC_CTL0_PER BIT(1)
#define | FMC_CTL0_MER BIT(2)
#define | FMC_CTL0_OBPG BIT(4)
#define | FMC_CTL0_OBER BIT(5)
#define | FMC_CTL0_START BIT(6)
#define | FMC_CTL0_LK BIT(7)
#define | FMC_CTL0_OBWEN BIT(9)
#define | FMC_CTL0_ERRIE BIT(10)
#define | FMC_CTL0_ENDIE BIT(12)
#define | FMC_ADDR0_ADDR BITS(0,31)
#define | FMC_OBSTAT_OBERR BIT(0)
#define | FMC_OBSTAT_SPC BIT(1)
#define | FMC_OBSTAT_USER BITS(2,9)
#define | FMC_OBSTAT_DATA BITS(10,25)
#define | FMC_WP_WP BITS(0,31)
#define | FMC_KEY1_KEY BITS(0,31)
#define | FMC_STAT1_BUSY BIT(0)
#define | FMC_STAT1_PGERR BIT(2)
#define | FMC_STAT1_WPERR BIT(4)
#define | FMC_STAT1_ENDF BIT(5)
#define | FMC_CTL1_PG BIT(0)
#define | FMC_CTL1_PER BIT(1)
#define | FMC_CTL1_MER BIT(2)
#define | FMC_CTL1_START BIT(6)
#define | FMC_CTL1_LK BIT(7)
#define | FMC_CTL1_ERRIE BIT(10)
#define | FMC_CTL1_ENDIE BIT(12)
#define | FMC_ADDR1_ADDR BITS(0,31)
#define | FMC_WSEN_WSEN BIT(0)
#define | FMC_PID_PID BITS(0,31)
#define | FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define | FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6)))
#define | FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define | FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
#define | FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12)))
#define | FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
#define | FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
#define | FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
#define | FMC_STAT0_REG_OFFSET 0x0CU
#define | FMC_CTL0_REG_OFFSET 0x10U
#define | FMC_STAT1_REG_OFFSET 0x4CU
#define | FMC_CTL1_REG_OFFSET 0x50U
#define | FMC_OBSTAT_REG_OFFSET 0x1CU
#define | UNLOCK_KEY0 ((uint32_t)0x45670123U)
#define | UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU)
#define | WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval)))
#define | WS_WSCNT_0 WS_WSCNT(0)
#define | WS_WSCNT_1 WS_WSCNT(1)
#define | WS_WSCNT_2 WS_WSCNT(2)
#define | OB_FWDGT_SW ((uint8_t)0x01U)
#define | OB_FWDGT_HW ((uint8_t)0x00U)
#define | OB_DEEPSLEEP_NRST ((uint8_t)0x02U)
#define | OB_DEEPSLEEP_RST ((uint8_t)0x00U)
#define | OB_STDBY_NRST ((uint8_t)0x04U)
#define | OB_STDBY_RST ((uint8_t)0x00U)
#define | OB_BOOT_B0 ((uint8_t)0x08U)
#define | OB_BOOT_B1 ((uint8_t)0x00U)
#define | OB_USER_MASK ((uint8_t)0xF0U)
#define | FMC_NSPC ((uint8_t)0xA5U)
#define | FMC_USPC ((uint8_t)0xBBU)
#define | OB_SPC_SPC ((uint32_t)0x000000FFU)
#define | OB_SPC_SPC_N ((uint32_t)0x0000FF00U)
#define | OB_USER_USER ((uint32_t)0x00FF0000U)
#define | OB_USER_USER_N ((uint32_t)0xFF000000U)
#define | OB_WP0_WP0 ((uint32_t)0x000000FFU)
#define | OB_WP1_WP1 ((uint32_t)0x0000FF00U)
#define | OB_WP2_WP2 ((uint32_t)0x00FF0000U)
#define | OB_WP3_WP3 ((uint32_t)0xFF000000U)
#define | OB_WP_0 ((uint32_t)0x00000001U)
#define | OB_WP_1 ((uint32_t)0x00000002U)
#define | OB_WP_2 ((uint32_t)0x00000004U)
#define | OB_WP_3 ((uint32_t)0x00000008U)
#define | OB_WP_4 ((uint32_t)0x00000010U)
#define | OB_WP_5 ((uint32_t)0x00000020U)
#define | OB_WP_6 ((uint32_t)0x00000040U)
#define | OB_WP_7 ((uint32_t)0x00000080U)
#define | OB_WP_8 ((uint32_t)0x00000100U)
#define | OB_WP_9 ((uint32_t)0x00000200U)
#define | OB_WP_10 ((uint32_t)0x00000400U)
#define | OB_WP_11 ((uint32_t)0x00000800U)
#define | OB_WP_12 ((uint32_t)0x00001000U)
#define | OB_WP_13 ((uint32_t)0x00002000U)
#define | OB_WP_14 ((uint32_t)0x00004000U)
#define | OB_WP_15 ((uint32_t)0x00008000U)
#define | OB_WP_16 ((uint32_t)0x00010000U)
#define | OB_WP_17 ((uint32_t)0x00020000U)
#define | OB_WP_18 ((uint32_t)0x00040000U)
#define | OB_WP_19 ((uint32_t)0x00080000U)
#define | OB_WP_20 ((uint32_t)0x00100000U)
#define | OB_WP_21 ((uint32_t)0x00200000U)
#define | OB_WP_22 ((uint32_t)0x00400000U)
#define | OB_WP_23 ((uint32_t)0x00800000U)
#define | OB_WP_24 ((uint32_t)0x01000000U)
#define | OB_WP_25 ((uint32_t)0x02000000U)
#define | OB_WP_26 ((uint32_t)0x04000000U)
#define | OB_WP_27 ((uint32_t)0x08000000U)
#define | OB_WP_28 ((uint32_t)0x10000000U)
#define | OB_WP_29 ((uint32_t)0x20000000U)
#define | OB_WP_30 ((uint32_t)0x40000000U)
#define | OB_WP_31 ((uint32_t)0x80000000U)
#define | OB_WP_ALL ((uint32_t)0xFFFFFFFFU)
#define | FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U)
#define | FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU)
#define | FMC_BANK0_SIZE ((uint32_t)0x00000200U)
#define | FMC_SIZE (*(uint16_t *)0x1FFFF7E0U)

Enumerations

enum fmc_state_enum {
FMC_READY, FMC_BUSY, FMC_PGERR, FMC_WPERR,
FMC_TOERR
}
enum fmc_int_enum { FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U) }
enum fmc_flag_enum {
FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U),
FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U),
FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U)
}
enum fmc_interrupt_flag_enum {
FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U),
FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U)
}

Functions

void | fmc_wscnt_set (uint32_t wscnt)
set the wait state counter value More...
void | fmc_unlock (void)
unlock the main FMC operation More...
void | fmc_bank0_unlock (void)
unlock the FMC bank0 operation this function can be used for all GD32F10x devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. More...
void | fmc_bank1_unlock (void)
unlock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. More...
void | fmc_lock (void)
lock the main FMC operation More...
void | fmc_bank0_lock (void)
lock the FMC bank0 operation this function can be used for all GD32F10X devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. More...
void | fmc_bank1_lock (void)
lock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. More...
fmc_state_enum | fmc_page_erase (uint32_t page_address)
erase page More...
fmc_state_enum | fmc_mass_erase (void)
erase whole chip More...
fmc_state_enum | fmc_bank0_erase (void)
erase bank0 More...
fmc_state_enum | fmc_bank1_erase (void)
erase bank1 More...
fmc_state_enum | fmc_word_program (uint32_t address, uint32_t data)
program a word at the corresponding address More...
fmc_state_enum | fmc_halfword_program (uint32_t address, uint16_t data)
program a half word at the corresponding address More...
void | ob_unlock (void)
unlock the option byte operation More...
void | ob_lock (void)
lock the option byte operation More...
fmc_state_enum | ob_erase (void)
erase the FMC option byte unlock the FMC_CTL0 and option byte before calling this function More...
fmc_state_enum | ob_write_protection_enable (uint32_t ob_wp)
enable write protection More...
fmc_state_enum | ob_security_protection_config (uint8_t ob_spc)
configure security protection More...
fmc_state_enum | ob_user_write (uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot)
program the FMC user option byte More...
fmc_state_enum | ob_data_program (uint32_t address, uint8_t data)
program option bytes data More...
uint8_t | ob_user_get (void)
get the FMC user option byte More...
uint16_t | ob_data_get (void)
get OB_DATA in register FMC_OBSTAT More...
uint32_t | ob_write_protection_get (void)
get the FMC option byte write protection More...
FlagStatus | ob_spc_get (void)
get the FMC option byte security protection More...
void | fmc_interrupt_enable (uint32_t interrupt)
enable FMC interrupt More...
void | fmc_interrupt_disable (uint32_t interrupt)
disable FMC interrupt More...
FlagStatus | fmc_flag_get (uint32_t flag)
check flag is set or not More...
void | fmc_flag_clear (uint32_t flag)
clear the FMC flag More...
FlagStatus | fmc_interrupt_flag_get (fmc_interrupt_flag_enum flag)
get FMC interrupt flag state More...
void | fmc_interrupt_flag_clear (fmc_interrupt_flag_enum flag)
clear FMC interrupt flag state More...
fmc_state_enum | fmc_bank0_state_get (void)
get the FMC bank0 state More...
fmc_state_enum | fmc_bank1_state_get (void)
get the FMC bank1 state More...
fmc_state_enum | fmc_bank0_ready_wait (uint32_t timeout)
check whether FMC bank0 is ready or not More...
fmc_state_enum | fmc_bank1_ready_wait (uint32_t timeout)
check whether FMC bank1 is ready or not More...

Detailed Description

definitions for the FMC

Definition in file gd32f10x_fmc.h.

Macro Definition Documentation

#define FMC FMC_BASE

FMC register base address

Definition at line 19 of file gd32f10x_fmc.h.

#define FMC_ADDR0 REG32((FMC) + 0x14U)

FMC address register 0

Definition at line 28 of file gd32f10x_fmc.h.

#define FMC_ADDR0_ADDR BITS(0,31)

Flash erase/program command address bits

Definition at line 74 of file gd32f10x_fmc.h.

#define FMC_ADDR1 REG32((FMC) + 0x54U)

FMC address register 1

Definition at line 34 of file gd32f10x_fmc.h.

#define FMC_ADDR1_ADDR BITS(0,31)

Flash erase/program command address bits

Definition at line 104 of file gd32f10x_fmc.h.

#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU)

FMC bank0 end address

Definition at line 265 of file gd32f10x_fmc.h.

#define FMC_BANK0_SIZE ((uint32_t)0x00000200U)

FMC bank0 size

Definition at line 266 of file gd32f10x_fmc.h.

#define FMC_BIT_POS ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 116 of file gd32f10x_fmc.h.

#define FMC_BIT_POS0 ( val ) (((uint32_t)(val) >> 6) & 0x1FU)

Definition at line 119 of file gd32f10x_fmc.h.

#define FMC_BIT_POS1 ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 120 of file gd32f10x_fmc.h.

#define FMC_CTL0 REG32((FMC) + 0x10U)

FMC control register 0

Definition at line 27 of file gd32f10x_fmc.h.

#define FMC_CTL0_ENDIE BIT(12)

end of operation interrupt enable bit

Definition at line 71 of file gd32f10x_fmc.h.

#define FMC_CTL0_ERRIE BIT(10)

error interrupt enable bit

Definition at line 70 of file gd32f10x_fmc.h.

#define FMC_CTL0_LK BIT(7)

FMC_CTL0 lock bit

Definition at line 68 of file gd32f10x_fmc.h.

#define FMC_CTL0_MER BIT(2)

main flash mass erase for bank0 command bit

Definition at line 64 of file gd32f10x_fmc.h.

#define FMC_CTL0_OBER BIT(5)

option bytes erase command bit

Definition at line 66 of file gd32f10x_fmc.h.

#define FMC_CTL0_OBPG BIT(4)

option bytes program command bit

Definition at line 65 of file gd32f10x_fmc.h.

#define FMC_CTL0_OBWEN BIT(9)

option bytes erase/program enable bit

Definition at line 69 of file gd32f10x_fmc.h.

#define FMC_CTL0_PER BIT(1)

main flash page erase for bank0 command bit

Definition at line 63 of file gd32f10x_fmc.h.

#define FMC_CTL0_PG BIT(0)

main flash program for bank0 command bit

Definition at line 62 of file gd32f10x_fmc.h.

#define FMC_CTL0_REG_OFFSET 0x10U

control register 0 offset

Definition at line 125 of file gd32f10x_fmc.h.

#define FMC_CTL0_START BIT(6)

send erase command to FMC bit

Definition at line 67 of file gd32f10x_fmc.h.

#define FMC_CTL1 REG32((FMC) + 0x50U)

FMC control register 1

Definition at line 33 of file gd32f10x_fmc.h.

#define FMC_CTL1_ENDIE BIT(12)

end of operation interrupt enable bit

Definition at line 101 of file gd32f10x_fmc.h.

#define FMC_CTL1_ERRIE BIT(10)

error interrupt enable bit

Definition at line 100 of file gd32f10x_fmc.h.

#define FMC_CTL1_LK BIT(7)

FMC_CTL1 lock bit

Definition at line 99 of file gd32f10x_fmc.h.

#define FMC_CTL1_MER BIT(2)

main flash mass erase for bank1 command bit

Definition at line 97 of file gd32f10x_fmc.h.

#define FMC_CTL1_PER BIT(1)

main flash page erase for bank1 command bit

Definition at line 96 of file gd32f10x_fmc.h.

#define FMC_CTL1_PG BIT(0)

main flash program for bank1 command bit

Definition at line 95 of file gd32f10x_fmc.h.

#define FMC_CTL1_REG_OFFSET 0x50U

control register 1 offset

Definition at line 127 of file gd32f10x_fmc.h.

#define FMC_CTL1_START BIT(6)

send erase command to FMC bit

Definition at line 98 of file gd32f10x_fmc.h.

#define FMC_KEY0 REG32((FMC) + 0x04U)

FMC unlock key register 0

Definition at line 24 of file gd32f10x_fmc.h.

#define FMC_KEY0_KEY BITS(0,31)

FMC_CTL0 unlock key bits

Definition at line 50 of file gd32f10x_fmc.h.

#define FMC_KEY1 REG32((FMC) + 0x44U)

FMC unlock key register 1

Definition at line 31 of file gd32f10x_fmc.h.

#define FMC_KEY1_KEY BITS(0,31)

FMC_CTL1 unlock key bits

Definition at line 86 of file gd32f10x_fmc.h.

#define FMC_NSPC ((uint8_t)0xA5U)

no security protection

Definition at line 203 of file gd32f10x_fmc.h.

#define FMC_OBKEY REG32((FMC) + 0x08U)

FMC option bytes unlock key register

Definition at line 25 of file gd32f10x_fmc.h.

#define FMC_OBKEY_OBKEY BITS(0,31)

option bytes unlock key bits

Definition at line 53 of file gd32f10x_fmc.h.

#define FMC_OBSTAT REG32((FMC) + 0x1CU)

FMC option bytes status register

Definition at line 29 of file gd32f10x_fmc.h.

#define FMC_OBSTAT_DATA BITS(10,25)

store DATA of option bytes block after system reset.

Definition at line 80 of file gd32f10x_fmc.h.

#define FMC_OBSTAT_OBERR BIT(0)

option bytes read error bit.

Definition at line 77 of file gd32f10x_fmc.h.

#define FMC_OBSTAT_REG_OFFSET 0x1CU

option byte status register offset

Definition at line 128 of file gd32f10x_fmc.h.

#define FMC_OBSTAT_SPC BIT(1)

option bytes security protection code

Definition at line 78 of file gd32f10x_fmc.h.

#define FMC_OBSTAT_USER BITS(2,9)

store USER of option bytes block after system reset

Definition at line 79 of file gd32f10x_fmc.h.

#define FMC_PID REG32((FMC) + 0x100U)

FMC product ID register

Definition at line 36 of file gd32f10x_fmc.h.

#define FMC_PID_PID BITS(0,31)

product ID bits

Definition at line 110 of file gd32f10x_fmc.h.

#define FMC_REG_OFFSET_GET ( flag ) ((uint32_t)(flag) >> 12)

Definition at line 121 of file gd32f10x_fmc.h.

#define FMC_REG_VAL ( offset ) (REG32(FMC + ((uint32_t)(offset) >> 6)))

Definition at line 115 of file gd32f10x_fmc.h.

#define FMC_REG_VALS ( offset ) (REG32(FMC + ((uint32_t)(offset) >> 12)))

Definition at line 118 of file gd32f10x_fmc.h.

#define FMC_REGIDX_BIT | ( | regidx,
 |  | bitpos
 | ) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))

Definition at line 114 of file gd32f10x_fmc.h.

#define FMC_REGIDX_BITS | ( | regidx,
 |  | bitpos0,
 |  | bitpos1
 | ) | (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))

Definition at line 117 of file gd32f10x_fmc.h.

#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U)

FMC size

Definition at line 267 of file gd32f10x_fmc.h.

#define FMC_STAT0 REG32((FMC) + 0x0CU)

FMC status register 0

Definition at line 26 of file gd32f10x_fmc.h.

#define FMC_STAT0_BUSY BIT(0)

flash busy flag bit

Definition at line 56 of file gd32f10x_fmc.h.

#define FMC_STAT0_ENDF BIT(5)

end of operation flag bit

Definition at line 59 of file gd32f10x_fmc.h.

#define FMC_STAT0_PGERR BIT(2)

flash program error flag bit

Definition at line 57 of file gd32f10x_fmc.h.

#define FMC_STAT0_REG_OFFSET 0x0CU

status register 0 offset

Definition at line 124 of file gd32f10x_fmc.h.

#define FMC_STAT0_WPERR BIT(4)

erase/program protection error flag bit

Definition at line 58 of file gd32f10x_fmc.h.

#define FMC_STAT1 REG32((FMC) + 0x4CU)

FMC status register 1

Definition at line 32 of file gd32f10x_fmc.h.

#define FMC_STAT1_BUSY BIT(0)

flash busy flag bit

Definition at line 89 of file gd32f10x_fmc.h.

#define FMC_STAT1_ENDF BIT(5)

end of operation flag bit

Definition at line 92 of file gd32f10x_fmc.h.

#define FMC_STAT1_PGERR BIT(2)

flash program error flag bit

Definition at line 90 of file gd32f10x_fmc.h.

#define FMC_STAT1_REG_OFFSET 0x4CU

status register 1 offset

Definition at line 126 of file gd32f10x_fmc.h.

#define FMC_STAT1_WPERR BIT(4)

erase/program protection error flag bit

Definition at line 91 of file gd32f10x_fmc.h.

#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U)

FMC timeout count value

Definition at line 262 of file gd32f10x_fmc.h.

#define FMC_USPC ((uint8_t)0xBBU)

under security protection

Definition at line 204 of file gd32f10x_fmc.h.

#define FMC_WP REG32((FMC) + 0x20U)

FMC erase/program protection register

Definition at line 30 of file gd32f10x_fmc.h.

#define FMC_WP_WP BITS(0,31)

store WP of option bytes block after system reset

Definition at line 83 of file gd32f10x_fmc.h.

#define FMC_WS REG32((FMC) + 0x00U)

FMC wait state register

Definition at line 23 of file gd32f10x_fmc.h.

#define FMC_WS_WSCNT BITS(0,2)

wait state counter

Definition at line 47 of file gd32f10x_fmc.h.

#define FMC_WSEN REG32((FMC) + 0xFCU)

FMC wait state enable register

Definition at line 35 of file gd32f10x_fmc.h.

#define FMC_WSEN_WSEN BIT(0)

FMC wait state enable bit

Definition at line 107 of file gd32f10x_fmc.h.

#define OB OB_BASE

option bytes base address

Definition at line 20 of file gd32f10x_fmc.h.

#define OB_BOOT_B0 ((uint8_t)0x08U)

boot from bank0

Definition at line 197 of file gd32f10x_fmc.h.

#define OB_BOOT_B1 ((uint8_t)0x00U)

boot from bank1

Definition at line 198 of file gd32f10x_fmc.h.

#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U)

no reset when entering deepsleep mode

Definition at line 189 of file gd32f10x_fmc.h.

#define OB_DEEPSLEEP_RST ((uint8_t)0x00U)

generate a reset instead of entering deepsleep mode

Definition at line 190 of file gd32f10x_fmc.h.

#define OB_FWDGT_HW ((uint8_t)0x00U)

hardware free watchdog

Definition at line 186 of file gd32f10x_fmc.h.

#define OB_FWDGT_SW ((uint8_t)0x01U)

software free watchdog

Definition at line 185 of file gd32f10x_fmc.h.

#define OB_SPC REG16((OB) + 0x00U)

option byte security protection value

Definition at line 38 of file gd32f10x_fmc.h.

#define OB_SPC_SPC ((uint32_t)0x000000FFU)

option byte security protection value

Definition at line 207 of file gd32f10x_fmc.h.

#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U)

option byte security protection complement value

Definition at line 208 of file gd32f10x_fmc.h.

#define OB_STDBY_NRST ((uint8_t)0x04U)

no reset when entering deepsleep mode

Definition at line 193 of file gd32f10x_fmc.h.

#define OB_STDBY_RST ((uint8_t)0x00U)

generate a reset instead of entering standby mode

Definition at line 194 of file gd32f10x_fmc.h.

#define OB_USER REG16((OB) + 0x02U)

option byte user value

Definition at line 39 of file gd32f10x_fmc.h.

#define OB_USER_MASK ((uint8_t)0xF0U)

MASK value

Definition at line 200 of file gd32f10x_fmc.h.

#define OB_USER_USER ((uint32_t)0x00FF0000U)

user option value

Definition at line 211 of file gd32f10x_fmc.h.

#define OB_USER_USER_N ((uint32_t)0xFF000000U)

user option complement value

Definition at line 212 of file gd32f10x_fmc.h.

#define OB_WP0 REG16((OB) + 0x08U)

option byte write protection 0

Definition at line 40 of file gd32f10x_fmc.h.

#define OB_WP0_WP0 ((uint32_t)0x000000FFU)

FMC write protection option value

Definition at line 215 of file gd32f10x_fmc.h.

#define OB_WP1 REG16((OB) + 0x0AU)

option byte write protection 1

Definition at line 41 of file gd32f10x_fmc.h.

#define OB_WP1_WP1 ((uint32_t)0x0000FF00U)

FMC write protection option complement value

Definition at line 218 of file gd32f10x_fmc.h.

#define OB_WP2 REG16((OB) + 0x0CU)

option byte write protection 2

Definition at line 42 of file gd32f10x_fmc.h.

#define OB_WP2_WP2 ((uint32_t)0x00FF0000U)

FMC write protection option value

Definition at line 221 of file gd32f10x_fmc.h.

#define OB_WP3 REG16((OB) + 0x0EU)

option byte write protection 3

Definition at line 43 of file gd32f10x_fmc.h.

#define OB_WP3_WP3 ((uint32_t)0xFF000000U)

FMC write protection option complement value

Definition at line 224 of file gd32f10x_fmc.h.

#define OB_WP_0 ((uint32_t)0x00000001U)

erase/program protection of sector 0

Definition at line 227 of file gd32f10x_fmc.h.

#define OB_WP_1 ((uint32_t)0x00000002U)

erase/program protection of sector 1

Definition at line 228 of file gd32f10x_fmc.h.

#define OB_WP_10 ((uint32_t)0x00000400U)

erase/program protection of sector 10

Definition at line 237 of file gd32f10x_fmc.h.

#define OB_WP_11 ((uint32_t)0x00000800U)

erase/program protection of sector 11

Definition at line 238 of file gd32f10x_fmc.h.

#define OB_WP_12 ((uint32_t)0x00001000U)

erase/program protection of sector 12

Definition at line 239 of file gd32f10x_fmc.h.

#define OB_WP_13 ((uint32_t)0x00002000U)

erase/program protection of sector 13

Definition at line 240 of file gd32f10x_fmc.h.

#define OB_WP_14 ((uint32_t)0x00004000U)

erase/program protection of sector 14

Definition at line 241 of file gd32f10x_fmc.h.

#define OB_WP_15 ((uint32_t)0x00008000U)

erase/program protection of sector 15

Definition at line 242 of file gd32f10x_fmc.h.

#define OB_WP_16 ((uint32_t)0x00010000U)

erase/program protection of sector 16

Definition at line 243 of file gd32f10x_fmc.h.

#define OB_WP_17 ((uint32_t)0x00020000U)

erase/program protection of sector 17

Definition at line 244 of file gd32f10x_fmc.h.

#define OB_WP_18 ((uint32_t)0x00040000U)

erase/program protection of sector 18

Definition at line 245 of file gd32f10x_fmc.h.

#define OB_WP_19 ((uint32_t)0x00080000U)

erase/program protection of sector 19

Definition at line 246 of file gd32f10x_fmc.h.

#define OB_WP_2 ((uint32_t)0x00000004U)

erase/program protection of sector 2

Definition at line 229 of file gd32f10x_fmc.h.

#define OB_WP_20 ((uint32_t)0x00100000U)

erase/program protection of sector 20

Definition at line 247 of file gd32f10x_fmc.h.

#define OB_WP_21 ((uint32_t)0x00200000U)

erase/program protection of sector 21

Definition at line 248 of file gd32f10x_fmc.h.

#define OB_WP_22 ((uint32_t)0x00400000U)

erase/program protection of sector 22

Definition at line 249 of file gd32f10x_fmc.h.

#define OB_WP_23 ((uint32_t)0x00800000U)

erase/program protection of sector 23

Definition at line 250 of file gd32f10x_fmc.h.

#define OB_WP_24 ((uint32_t)0x01000000U)

erase/program protection of sector 24

Definition at line 251 of file gd32f10x_fmc.h.

#define OB_WP_25 ((uint32_t)0x02000000U)

erase/program protection of sector 25

Definition at line 252 of file gd32f10x_fmc.h.

#define OB_WP_26 ((uint32_t)0x04000000U)

erase/program protection of sector 26

Definition at line 253 of file gd32f10x_fmc.h.

#define OB_WP_27 ((uint32_t)0x08000000U)

erase/program protection of sector 27

Definition at line 254 of file gd32f10x_fmc.h.

#define OB_WP_28 ((uint32_t)0x10000000U)

erase/program protection of sector 28

Definition at line 255 of file gd32f10x_fmc.h.

#define OB_WP_29 ((uint32_t)0x20000000U)

erase/program protection of sector 29

Definition at line 256 of file gd32f10x_fmc.h.

#define OB_WP_3 ((uint32_t)0x00000008U)

erase/program protection of sector 3

Definition at line 230 of file gd32f10x_fmc.h.

#define OB_WP_30 ((uint32_t)0x40000000U)

erase/program protection of sector 30

Definition at line 257 of file gd32f10x_fmc.h.

#define OB_WP_31 ((uint32_t)0x80000000U)

erase/program protection of sector 31

Definition at line 258 of file gd32f10x_fmc.h.

#define OB_WP_4 ((uint32_t)0x00000010U)

erase/program protection of sector 4

Definition at line 231 of file gd32f10x_fmc.h.

#define OB_WP_5 ((uint32_t)0x00000020U)

erase/program protection of sector 5

Definition at line 232 of file gd32f10x_fmc.h.

#define OB_WP_6 ((uint32_t)0x00000040U)

erase/program protection of sector 6

Definition at line 233 of file gd32f10x_fmc.h.

#define OB_WP_7 ((uint32_t)0x00000080U)

erase/program protection of sector 7

Definition at line 234 of file gd32f10x_fmc.h.

#define OB_WP_8 ((uint32_t)0x00000100U)

erase/program protection of sector 8

Definition at line 235 of file gd32f10x_fmc.h.

#define OB_WP_9 ((uint32_t)0x00000200U)

erase/program protection of sector 9

Definition at line 236 of file gd32f10x_fmc.h.

#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU)

erase/program protection of all sectors

Definition at line 259 of file gd32f10x_fmc.h.

#define UNLOCK_KEY0 ((uint32_t)0x45670123U)

unlock key 0

Definition at line 175 of file gd32f10x_fmc.h.

#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU)

unlock key 1

Definition at line 176 of file gd32f10x_fmc.h.

#define WS_WSCNT ( regval ) (BITS(0,2) & ((uint32_t)(regval)))

Definition at line 179 of file gd32f10x_fmc.h.

#define WS_WSCNT_0 WS_WSCNT(0)

FMC 0 wait

Definition at line 180 of file gd32f10x_fmc.h.

#define WS_WSCNT_1 WS_WSCNT(1)

FMC 1 wait

Definition at line 181 of file gd32f10x_fmc.h.

#define WS_WSCNT_2 WS_WSCNT(2)

FMC 2 wait

Definition at line 182 of file gd32f10x_fmc.h.

Enumeration Type Documentation

enum fmc_flag_enum
Enumerator
FMC_FLAG_BANK0_BUSY | FMC bank0 busy flag
FMC_FLAG_BANK0_PGERR | FMC bank0 operation error flag bit
FMC_FLAG_BANK0_WPERR | FMC bank0 erase/program protection error flag bit
FMC_FLAG_BANK0_END | FMC bank0 end of operation flag bit
FMC_FLAG_OBERR | FMC option bytes read error flag
FMC_FLAG_BANK1_BUSY | FMC bank1 busy flag
FMC_FLAG_BANK1_PGERR | FMC bank1 operation error flag bit
FMC_FLAG_BANK1_WPERR | FMC bank1 erase/program protection error flag bit
FMC_FLAG_BANK1_END | FMC bank1 end of operation flag bit

Definition at line 150 of file gd32f10x_fmc.h.

151 {
152 FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U),
153 FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U),
154 FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U),
155 FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U),
156 FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U),
157 FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U),
158 FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U),
159 FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U),
160 FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U),
161 }fmc_flag_enum;
FMC_STAT1_REG_OFFSET
#define FMC_STAT1_REG_OFFSET
Definition: gd32f10x_fmc.h:126
FMC_FLAG_BANK1_WPERR
Definition: gd32f10x_fmc.h:159
FMC_FLAG_BANK0_PGERR
Definition: gd32f10x_fmc.h:153
FMC_OBSTAT_REG_OFFSET
#define FMC_OBSTAT_REG_OFFSET
Definition: gd32f10x_fmc.h:128
fmc_flag_enum
fmc_flag_enum
Definition: gd32f10x_fmc.h:150
FMC_FLAG_BANK1_PGERR
Definition: gd32f10x_fmc.h:158
FMC_FLAG_BANK1_END
Definition: gd32f10x_fmc.h:160
FMC_FLAG_BANK0_END
Definition: gd32f10x_fmc.h:155
FMC_REGIDX_BIT
#define FMC_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_fmc.h:114
FMC_STAT0_REG_OFFSET
#define FMC_STAT0_REG_OFFSET
Definition: gd32f10x_fmc.h:124
FMC_FLAG_BANK0_WPERR
Definition: gd32f10x_fmc.h:154
FMC_FLAG_BANK0_BUSY
Definition: gd32f10x_fmc.h:152
FMC_FLAG_BANK1_BUSY
Definition: gd32f10x_fmc.h:157
FMC_FLAG_OBERR
Definition: gd32f10x_fmc.h:156
enum fmc_int_enum
Enumerator
FMC_INT_BANK0_END | enable FMC end of program interrupt
FMC_INT_BANK0_ERR | enable FMC error interrupt
FMC_INT_BANK1_END | enable FMC bank1 end of program interrupt
FMC_INT_BANK1_ERR | enable FMC bank1 error interrupt

Definition at line 141 of file gd32f10x_fmc.h.

142 {
143 FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U),
144 FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U),
145 FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U),
146 FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U),
147 }fmc_int_enum;
FMC_INT_BANK0_END
Definition: gd32f10x_fmc.h:143
FMC_INT_BANK0_ERR
Definition: gd32f10x_fmc.h:144
fmc_int_enum
fmc_int_enum
Definition: gd32f10x_fmc.h:141
FMC_INT_BANK1_END
Definition: gd32f10x_fmc.h:145
FMC_CTL0_REG_OFFSET
#define FMC_CTL0_REG_OFFSET
Definition: gd32f10x_fmc.h:125
FMC_REGIDX_BIT
#define FMC_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_fmc.h:114
FMC_INT_BANK1_ERR
Definition: gd32f10x_fmc.h:146
FMC_CTL1_REG_OFFSET
#define FMC_CTL1_REG_OFFSET
Definition: gd32f10x_fmc.h:127
enum fmc_interrupt_flag_enum
Enumerator
FMC_INT_FLAG_BANK0_PGERR | FMC bank0 operation error interrupt flag bit
FMC_INT_FLAG_BANK0_WPERR | FMC bank0 erase/program protection error interrupt flag bit
FMC_INT_FLAG_BANK0_END | FMC bank0 end of operation interrupt flag bit
FMC_INT_FLAG_BANK1_PGERR | FMC bank1 operation error interrupt flag bit
FMC_INT_FLAG_BANK1_WPERR | FMC bank1 erase/program protection error interrupt flag bit
FMC_INT_FLAG_BANK1_END | FMC bank1 end of operation interrupt flag bit

Definition at line 164 of file gd32f10x_fmc.h.

165 {
166 FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U),
167 FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U),
168 FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U),
169 FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U),
170 FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U),
171 FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U),
172 }fmc_interrupt_flag_enum;
FMC_STAT1_REG_OFFSET
#define FMC_STAT1_REG_OFFSET
Definition: gd32f10x_fmc.h:126
FMC_INT_FLAG_BANK0_END
Definition: gd32f10x_fmc.h:168
FMC_INT_FLAG_BANK1_PGERR
Definition: gd32f10x_fmc.h:169
FMC_INT_FLAG_BANK1_WPERR
Definition: gd32f10x_fmc.h:170
FMC_INT_FLAG_BANK0_PGERR
Definition: gd32f10x_fmc.h:166
fmc_interrupt_flag_enum
fmc_interrupt_flag_enum
Definition: gd32f10x_fmc.h:164
FMC_STAT0_REG_OFFSET
#define FMC_STAT0_REG_OFFSET
Definition: gd32f10x_fmc.h:124
FMC_REGIDX_BITS
#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1)
Definition: gd32f10x_fmc.h:117
FMC_INT_FLAG_BANK1_END
Definition: gd32f10x_fmc.h:171
FMC_INT_FLAG_BANK0_WPERR
Definition: gd32f10x_fmc.h:167
enum fmc_state_enum
Enumerator
FMC_READY | the operation has been completed
FMC_BUSY | the operation is in progress
FMC_PGERR | program error
FMC_WPERR | erase/program protection error
FMC_TOERR | timeout error

Definition at line 131 of file gd32f10x_fmc.h.

132 {
133 FMC_READY,
134 FMC_BUSY,
135 FMC_PGERR,
136 FMC_WPERR,
137 FMC_TOERR,
138 }fmc_state_enum;
FMC_BUSY
Definition: gd32f10x_fmc.h:134
FMC_WPERR
Definition: gd32f10x_fmc.h:136
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_TOERR
Definition: gd32f10x_fmc.h:137
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_PGERR
Definition: gd32f10x_fmc.h:135

Function Documentation

fmc_state_enum fmc_bank0_erase ( void )

erase bank0

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 246 of file gd32f10x_fmc.c.

247 {
248 fmc_state_enum fmc_state = FMC_READY;
249 /* wait for the FMC ready */
250 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
251
252 if(FMC_READY == fmc_state){
253 /* start FMC bank0 erase */
254 FMC_CTL0 |= FMC_CTL0_MER;
255 FMC_CTL0 |= FMC_CTL0_START;
256 /* wait for the FMC ready */
257 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
258 /* reset the MER bit */
259 FMC_CTL0 &= ~FMC_CTL0_MER;
260 }
261 /* return the fmc state */
262 return fmc_state;
263 }
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_CTL0_MER
#define FMC_CTL0_MER
Definition: gd32f10x_fmc.h:64
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_bank0_lock ( void )

lock the FMC bank0 operation this function can be used for all GD32F10X devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 116 of file gd32f10x_fmc.c.

117 {
118 /* set the LK bit*/
119 FMC_CTL0 |= FMC_CTL0_LK;
120 }
FMC_CTL0_LK
#define FMC_CTL0_LK
Definition: gd32f10x_fmc.h:68
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum fmc_bank0_ready_wait ( uint32_t timeout )

check whether FMC bank0 is ready or not

Parameters
[in] | timeout | count of loop
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 892 of file gd32f10x_fmc.c.

893 {
894 fmc_state_enum fmc_state = FMC_BUSY;
895
896 /* wait for FMC ready */
897 do{
898 /* get FMC state */
899 fmc_state = fmc_bank0_state_get();
900 timeout--;
901 }while((FMC_BUSY == fmc_state) && (0x00U != timeout));
902
903 if(FMC_BUSY == fmc_state){
904 fmc_state = FMC_TOERR;
905 }
906 /* return the FMC state */
907 return fmc_state;
908 }
FMC_BUSY
Definition: gd32f10x_fmc.h:134
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_bank0_state_get
fmc_state_enum fmc_bank0_state_get(void)
get the FMC bank0 state
Definition: gd32f10x_fmc.c:841
fmc_state_enum fmc_bank0_state_get ( void )

get the FMC bank0 state

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 841 of file gd32f10x_fmc.c.

842 {
843 fmc_state_enum fmc_state = FMC_READY;
844
845 if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){
846 fmc_state = FMC_BUSY;
847 }else{
848 if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){
849 fmc_state = FMC_WPERR;
850 }else{
851 if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){
852 fmc_state = FMC_PGERR;
853 }
854 }
855 }
856 /* return the FMC state */
857 return fmc_state;
858 }
FMC_BUSY
Definition: gd32f10x_fmc.h:134
FMC_WPERR
Definition: gd32f10x_fmc.h:136
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_STAT0_WPERR
#define FMC_STAT0_WPERR
Definition: gd32f10x_fmc.h:58
FMC_STAT0
#define FMC_STAT0
Definition: gd32f10x_fmc.h:26
FMC_STAT0_PGERR
#define FMC_STAT0_PGERR
Definition: gd32f10x_fmc.h:57
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_STAT0_BUSY
#define FMC_STAT0_BUSY
Definition: gd32f10x_fmc.h:56
FMC_PGERR
Definition: gd32f10x_fmc.h:135
void fmc_bank0_unlock ( void )

unlock the FMC bank0 operation this function can be used for all GD32F10x devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 65 of file gd32f10x_fmc.c.

66 {
67 if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
68 /* write the FMC unlock key */
69 FMC_KEY0 = UNLOCK_KEY0;
70 FMC_KEY0 = UNLOCK_KEY1;
71 }
72 }
FMC_CTL0_LK
#define FMC_CTL0_LK
Definition: gd32f10x_fmc.h:68
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f10x_fmc.h:175
FMC_KEY0
#define FMC_KEY0
Definition: gd32f10x_fmc.h:24
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f10x_fmc.h:176
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum fmc_bank1_erase ( void )

erase bank1

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 271 of file gd32f10x_fmc.c.

272 {
273 fmc_state_enum fmc_state = FMC_READY;
274 /* wait for the FMC ready */
275 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
276
277 if(FMC_READY == fmc_state){
278 /* start FMC bank1 erase */
279 FMC_CTL1 |= FMC_CTL1_MER;
280 FMC_CTL1 |= FMC_CTL1_START;
281 /* wait for the FMC ready */
282 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
283 /* reset the MER bit */
284 FMC_CTL1 &= ~FMC_CTL1_MER;
285 }
286 /* return the fmc state */
287 return fmc_state;
288 }
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_CTL1_START
#define FMC_CTL1_START
Definition: gd32f10x_fmc.h:98
FMC_CTL1_MER
#define FMC_CTL1_MER
Definition: gd32f10x_fmc.h:97
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_READY
Definition: gd32f10x_fmc.h:133
void fmc_bank1_lock ( void )

lock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 129 of file gd32f10x_fmc.c.

130 {
131 /* set the LK bit*/
132 FMC_CTL1 |= FMC_CTL1_LK;
133 }
FMC_CTL1_LK
#define FMC_CTL1_LK
Definition: gd32f10x_fmc.h:99
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
fmc_state_enum fmc_bank1_ready_wait ( uint32_t timeout )

check whether FMC bank1 is ready or not

Parameters
[in] | timeout | count of loop
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 916 of file gd32f10x_fmc.c.

917 {
918 fmc_state_enum fmc_state = FMC_BUSY;
919
920 /* wait for FMC ready */
921 do{
922 /* get FMC state */
923 fmc_state = fmc_bank1_state_get();
924 timeout--;
925 }while((FMC_BUSY == fmc_state) && (0x00U != timeout));
926
927 if(FMC_BUSY == fmc_state){
928 fmc_state = FMC_TOERR;
929 }
930 /* return the FMC state */
931 return fmc_state;
932 }
fmc_bank1_state_get
fmc_state_enum fmc_bank1_state_get(void)
get the FMC bank1 state
Definition: gd32f10x_fmc.c:866
FMC_BUSY
Definition: gd32f10x_fmc.h:134
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_state_enum fmc_bank1_state_get ( void )

get the FMC bank1 state

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 866 of file gd32f10x_fmc.c.

867 {
868 fmc_state_enum fmc_state = FMC_READY;
869
870 if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){
871 fmc_state = FMC_BUSY;
872 }else{
873 if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){
874 fmc_state = FMC_WPERR;
875 }else{
876 if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){
877 fmc_state = FMC_PGERR;
878 }
879 }
880 }
881
882 /* return the FMC state */
883 return fmc_state;
884 }
FMC_BUSY
Definition: gd32f10x_fmc.h:134
FMC_WPERR
Definition: gd32f10x_fmc.h:136
FMC_STAT1
#define FMC_STAT1
Definition: gd32f10x_fmc.h:32
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_STAT1_WPERR
#define FMC_STAT1_WPERR
Definition: gd32f10x_fmc.h:91
FMC_STAT1_BUSY
#define FMC_STAT1_BUSY
Definition: gd32f10x_fmc.h:89
FMC_STAT1_PGERR
#define FMC_STAT1_PGERR
Definition: gd32f10x_fmc.h:90
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_PGERR
Definition: gd32f10x_fmc.h:135
void fmc_bank1_unlock ( void )

unlock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 81 of file gd32f10x_fmc.c.

82 {
83 if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){
84 /* write the FMC unlock key */
85 FMC_KEY1 = UNLOCK_KEY0;
86 FMC_KEY1 = UNLOCK_KEY1;
87 }
88 }
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f10x_fmc.h:175
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f10x_fmc.h:176
FMC_CTL1_LK
#define FMC_CTL1_LK
Definition: gd32f10x_fmc.h:99
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_KEY1
#define FMC_KEY1
Definition: gd32f10x_fmc.h:31
void fmc_flag_clear ( uint32_t flag )

clear the FMC flag

Parameters
[in] flag clear FMC flag only one parameter can be selected which is shown as below:
  • FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit
  • FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit
  • FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit
  • FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit
  • FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit
  • FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit
[out] none
Return values
none

Definition at line 775 of file gd32f10x_fmc.c.

776 {
777 FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag));
778 }
FMC_REG_VAL
#define FMC_REG_VAL(offset)
Definition: gd32f10x_fmc.h:115
FMC_BIT_POS
#define FMC_BIT_POS(val)
Definition: gd32f10x_fmc.h:116
FlagStatus fmc_flag_get ( uint32_t flag )

check flag is set or not

Parameters
[in] flag check FMC flag only one parameter can be selected which is shown as below:
  • FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit
  • FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit
  • FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit
  • FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit
  • FMC_FLAG_OBERR: FMC option bytes read error flag bit
  • FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit
  • FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit
  • FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit
  • FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit
[out] none
Return values
FlagStatus SET or RESET

Definition at line 753 of file gd32f10x_fmc.c.

754 {
755 if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){
756 return SET;
757 }else{
758 return RESET;
759 }
760 }
FMC_REG_VAL
#define FMC_REG_VAL(offset)
Definition: gd32f10x_fmc.h:115
FMC_BIT_POS
#define FMC_BIT_POS(val)
Definition: gd32f10x_fmc.h:116
fmc_state_enum fmc_halfword_program | ( | uint32_t | address,
 |  | uint16_t | data
 | ) |  |

program a half word at the corresponding address

Parameters
[in] | address | address to program
[in] | data | halfword to program
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 350 of file gd32f10x_fmc.c.

351 {
352 fmc_state_enum fmc_state = FMC_READY;
353 if(FMC_BANK0_SIZE > FMC_SIZE){
354 if(FMC_BANK0_END_ADDRESS > address){
355 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
356
357 if(FMC_READY == fmc_state){
358 /* set the PG bit to start program */
359 FMC_CTL0 |= FMC_CTL0_PG;
360 REG16(address) = data;
361 /* wait for the FMC ready */
362 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
363 /* reset the PG bit */
364 FMC_CTL0 &= ~FMC_CTL0_PG;
365 }
366 }else{
367 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
368
369 if(FMC_READY == fmc_state){
370 /* set the PG bit to start program */
371 FMC_CTL1 |= FMC_CTL1_PG;
372 REG16(address) = data;
373 /* wait for the FMC ready */
374 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
375 /* reset the PG bit */
376 FMC_CTL1 &= ~FMC_CTL1_PG;
377 }
378 }
379 }else{
380 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
381
382 if(FMC_READY == fmc_state){
383 /* set the PG bit to start program */
384 FMC_CTL0 |= FMC_CTL0_PG;
385 REG16(address) = data;
386 /* wait for the FMC ready */
387 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
388 /* reset the PG bit */
389 FMC_CTL0 &= ~FMC_CTL0_PG;
390 }
391 }
392 /* return the FMC state */
393 return fmc_state;
394 }
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_BANK0_END_ADDRESS
#define FMC_BANK0_END_ADDRESS
Definition: gd32f10x_fmc.h:265
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_CTL0_PG
#define FMC_CTL0_PG
Definition: gd32f10x_fmc.h:62
FMC_CTL1_PG
#define FMC_CTL1_PG
Definition: gd32f10x_fmc.h:95
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_interrupt_disable ( uint32_t interrupt )

disable FMC interrupt

Parameters
[in] interrupt the FMC interrupt source
  • FMC_INT_BANK0_END: enable FMC end of program interrupt
  • FMC_INT_BANK0_ERR: enable FMC error interrupt
  • FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt
  • FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt
[out] none
Return values
none

Definition at line 732 of file gd32f10x_fmc.c.

733 {
734 FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt));
735 }
FMC_REG_VAL
#define FMC_REG_VAL(offset)
Definition: gd32f10x_fmc.h:115
FMC_BIT_POS
#define FMC_BIT_POS(val)
Definition: gd32f10x_fmc.h:116
void fmc_interrupt_enable ( uint32_t interrupt )

enable FMC interrupt

Parameters
[in] interrupt the FMC interrupt source
  • FMC_INT_BANK0_END: enable FMC end of program interrupt
  • FMC_INT_BANK0_ERR: enable FMC error interrupt
  • FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt
  • FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt
[out] none
Return values
none

Definition at line 717 of file gd32f10x_fmc.c.

718 {
719 FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt));
720 }
FMC_REG_VAL
#define FMC_REG_VAL(offset)
Definition: gd32f10x_fmc.h:115
FMC_BIT_POS
#define FMC_BIT_POS(val)
Definition: gd32f10x_fmc.h:116
void fmc_interrupt_flag_clear ( fmc_interrupt_flag_enum flag )

clear FMC interrupt flag state

Parameters
[in] flag FMC interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below:
  • FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit
  • FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit
  • FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit
  • FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit
  • FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit
  • FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit
[out] none
Return values
none

Definition at line 830 of file gd32f10x_fmc.c.

831 {
832 FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag));
833 }
FMC_BIT_POS0
#define FMC_BIT_POS0(val)
Definition: gd32f10x_fmc.h:119
FMC_REG_VALS
#define FMC_REG_VALS(offset)
Definition: gd32f10x_fmc.h:118
FlagStatus fmc_interrupt_flag_get ( fmc_interrupt_flag_enum flag )

get FMC interrupt flag state

Parameters
[in] flag FMC interrupt flags, refer to fmc_interrupt_flag_enum only one parameter can be selected which is shown as below:
  • FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit
  • FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit
  • FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit
  • FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit
  • FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit
  • FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit
[out] none
Return values
FlagStatus SET or RESET

Definition at line 793 of file gd32f10x_fmc.c.

794 {
795 FlagStatus ret1 = RESET;
796 FlagStatus ret2 = RESET;
797
798 if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){
799 /* get the staus of interrupt flag */
800 ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
801 /* get the staus of interrupt enale bit */
802 ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
803 }else{
804 /* get the staus of interrupt flag */
805 ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
806 /* get the staus of interrupt enale bit */
807 ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag)));
808 }
809
810 if(ret1 && ret2){
811 return SET;
812 }else{
813 return RESET;
814 }
815 }
FMC_BIT_POS0
#define FMC_BIT_POS0(val)
Definition: gd32f10x_fmc.h:119
FMC_REG_VALS
#define FMC_REG_VALS(offset)
Definition: gd32f10x_fmc.h:118
FMC_REG_OFFSET_GET
#define FMC_REG_OFFSET_GET(flag)
Definition: gd32f10x_fmc.h:121
FMC_BIT_POS1
#define FMC_BIT_POS1(val)
Definition: gd32f10x_fmc.h:120
FMC_STAT0_REG_OFFSET
#define FMC_STAT0_REG_OFFSET
Definition: gd32f10x_fmc.h:124
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_lock ( void )

lock the main FMC operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 96 of file gd32f10x_fmc.c.

97 {
98 /* set the LK bit */
99 FMC_CTL0 |= FMC_CTL0_LK;
100
101 if(FMC_BANK0_SIZE < FMC_SIZE){
102 /* set the LK bit */
103 FMC_CTL1 |= FMC_CTL1_LK;
104 }
105 }
FMC_CTL0_LK
#define FMC_CTL0_LK
Definition: gd32f10x_fmc.h:68
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
FMC_CTL1_LK
#define FMC_CTL1_LK
Definition: gd32f10x_fmc.h:99
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum fmc_mass_erase ( void )

erase whole chip

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 198 of file gd32f10x_fmc.c.

199 {
200 fmc_state_enum fmc_state;
201 if(FMC_BANK0_SIZE < FMC_SIZE){
202 /* wait for the FMC ready */
203 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
204 if(FMC_READY == fmc_state){
205 /* start whole chip erase */
206 FMC_CTL0 |= FMC_CTL0_MER;
207 FMC_CTL0 |= FMC_CTL0_START;
208 /* wait for the FMC ready */
209 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
210 /* reset the MER bit */
211 FMC_CTL0 &= ~FMC_CTL0_MER;
212 }
213 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
214 if(FMC_READY == fmc_state){
215 /* start whole chip erase */
216 FMC_CTL1 |= FMC_CTL1_MER;
217 FMC_CTL1 |= FMC_CTL1_START;
218 /* wait for the FMC ready */
219 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
220 /* reset the MER bit */
221 FMC_CTL1 &= ~FMC_CTL1_MER;
222 }
223 }else{
224 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
225
226 if(FMC_READY == fmc_state){
227 /* start whole chip erase */
228 FMC_CTL0 |= FMC_CTL0_MER;
229 FMC_CTL0 |= FMC_CTL0_START;
230 /* wait for the FMC ready */
231 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
232 /* reset the MER bit */
233 FMC_CTL0 &= ~FMC_CTL0_MER;
234 }
235 }
236 /* return the FMC state */
237 return fmc_state;
238 }
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_CTL0_MER
#define FMC_CTL0_MER
Definition: gd32f10x_fmc.h:64
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_CTL1_START
#define FMC_CTL1_START
Definition: gd32f10x_fmc.h:98
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
FMC_CTL1_MER
#define FMC_CTL1_MER
Definition: gd32f10x_fmc.h:97
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum fmc_page_erase ( uint32_t page_address )

erase page

Parameters
[in] | page_address | the page address to be erased.
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 141 of file gd32f10x_fmc.c.

142 {
143 fmc_state_enum fmc_state;
144
145 if(FMC_BANK0_SIZE < FMC_SIZE){
146 if(FMC_BANK0_END_ADDRESS > page_address){
147 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
148 /* if the last operation is completed, start page erase */
149 if(FMC_READY == fmc_state){
150 FMC_CTL0 |= FMC_CTL0_PER;
151 FMC_ADDR0 = page_address;
152 FMC_CTL0 |= FMC_CTL0_START;
153 /* wait for the FMC ready */
154 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
155 /* reset the PER bit */
156 FMC_CTL0 &= ~FMC_CTL0_PER;
157 }
158 }else{
159 /* wait for the FMC ready */
160 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
161 /* if the last operation is completed, start page erase */
162 if(FMC_READY == fmc_state){
163 FMC_CTL1 |= FMC_CTL1_PER;
164 FMC_ADDR1 = page_address;
165 if(FMC_OBSTAT & FMC_OBSTAT_SPC){
166 FMC_ADDR0 = page_address;
167 }
168 FMC_CTL1 |= FMC_CTL1_START;
169 /* wait for the FMC ready */
170 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
171 /* reset the PER bit */
172 FMC_CTL1 &= ~FMC_CTL1_PER;
173 }
174 }
175 }else{
176 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
177 /* if the last operation is completed, start page erase */
178 if(FMC_READY == fmc_state){
179 FMC_CTL0 |= FMC_CTL0_PER;
180 FMC_ADDR0 = page_address;
181 FMC_CTL0 |= FMC_CTL0_START;
182 /* wait for the FMC ready */
183 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
184 /* reset the PER bit */
185 FMC_CTL0 &= ~FMC_CTL0_PER;
186 }
187 }
188 /* return the FMC state */
189 return fmc_state;
190 }
FMC_ADDR0
#define FMC_ADDR0
Definition: gd32f10x_fmc.h:28
FMC_CTL0_PER
#define FMC_CTL0_PER
Definition: gd32f10x_fmc.h:63
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_CTL1_START
#define FMC_CTL1_START
Definition: gd32f10x_fmc.h:98
FMC_BANK0_END_ADDRESS
#define FMC_BANK0_END_ADDRESS
Definition: gd32f10x_fmc.h:265
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
FMC_ADDR1
#define FMC_ADDR1
Definition: gd32f10x_fmc.h:34
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f10x_fmc.h:29
FMC_OBSTAT_SPC
#define FMC_OBSTAT_SPC
Definition: gd32f10x_fmc.h:78
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL1_PER
#define FMC_CTL1_PER
Definition: gd32f10x_fmc.h:96
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_unlock ( void )

unlock the main FMC operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 40 of file gd32f10x_fmc.c.

41 {
42 if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
43 /* write the FMC unlock key */
44 FMC_KEY0 = UNLOCK_KEY0;
45 FMC_KEY0 = UNLOCK_KEY1;
46 }
47 if(FMC_BANK0_SIZE < FMC_SIZE){
48 /* write the FMC unlock key */
49 if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){
50 FMC_KEY1 = UNLOCK_KEY0;
51 FMC_KEY1 = UNLOCK_KEY1;
52 }
53 }
54 }
FMC_CTL0_LK
#define FMC_CTL0_LK
Definition: gd32f10x_fmc.h:68
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f10x_fmc.h:175
FMC_KEY0
#define FMC_KEY0
Definition: gd32f10x_fmc.h:24
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f10x_fmc.h:176
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
FMC_CTL1_LK
#define FMC_CTL1_LK
Definition: gd32f10x_fmc.h:99
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
FMC_KEY1
#define FMC_KEY1
Definition: gd32f10x_fmc.h:31
fmc_state_enum fmc_word_program | ( | uint32_t | address,
 |  | uint32_t | data
 | ) |  |

program a word at the corresponding address

Parameters
[in] | address | address to program
[in] | data | word to program
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 297 of file gd32f10x_fmc.c.

298 {
299 fmc_state_enum fmc_state = FMC_READY;
300 if(FMC_BANK0_SIZE < FMC_SIZE){
301 if(FMC_BANK0_END_ADDRESS > address){
302 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
303
304 if(FMC_READY == fmc_state){
305 /* set the PG bit to start program */
306 FMC_CTL0 |= FMC_CTL0_PG;
307 REG32(address) = data;
308 /* wait for the FMC ready */
309 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
310 /* reset the PG bit */
311 FMC_CTL0 &= ~FMC_CTL0_PG;
312 }
313 }else{
314 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
315
316 if(FMC_READY == fmc_state){
317 /* set the PG bit to start program */
318 FMC_CTL1 |= FMC_CTL1_PG;
319 REG32(address) = data;
320 /* wait for the FMC ready */
321 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
322 /* reset the PG bit */
323 FMC_CTL1 &= ~FMC_CTL1_PG;
324 }
325 }
326 }else{
327 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
328
329 if(FMC_READY == fmc_state){
330 /* set the PG bit to start program */
331 FMC_CTL0 |= FMC_CTL0_PG;
332 REG32(address) = data;
333 /* wait for the FMC ready */
334 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
335 /* reset the PG bit */
336 FMC_CTL0 &= ~FMC_CTL0_PG;
337 }
338 }
339 /* return the FMC state */
340 return fmc_state;
341 }
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_BANK0_END_ADDRESS
#define FMC_BANK0_END_ADDRESS
Definition: gd32f10x_fmc.h:265
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_CTL0_PG
#define FMC_CTL0_PG
Definition: gd32f10x_fmc.h:62
FMC_CTL1_PG
#define FMC_CTL1_PG
Definition: gd32f10x_fmc.h:95
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_wscnt_set ( uint32_t wscnt )

set the wait state counter value

Parameters
[in] wscnt£ºwait state counter value
  • WS_WSCNT_0: FMC 0 wait
  • WS_WSCNT_1: FMC 1 wait
  • WS_WSCNT_2: FMC 2 wait
[out] none
Return values
none

Definition at line 24 of file gd32f10x_fmc.c.

25 {
26 uint32_t reg;
27
28 reg = FMC_WS;
29 /* set the wait state counter value */
30 reg &= ~FMC_WS_WSCNT;
31 FMC_WS = (reg | wscnt);
32 }
FMC_WS_WSCNT
#define FMC_WS_WSCNT
Definition: gd32f10x_fmc.h:47
FMC_WS
#define FMC_WS
Definition: gd32f10x_fmc.h:23
uint16_t ob_data_get ( void )

get OB_DATA in register FMC_OBSTAT

Parameters
[in] | none
[out] | none
Return values
ob_data

Definition at line 672 of file gd32f10x_fmc.c.

673 {
674 return (uint16_t)(FMC_OBSTAT >> 10U);
675 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f10x_fmc.h:29
fmc_state_enum ob_data_program | ( | uint32_t | address,
 |  | uint8_t | data
 | ) |  |

program option bytes data

Parameters
[in] | address | the option bytes address to be programmed
[in] | data | the byte to be programmed
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 633 of file gd32f10x_fmc.c.

634 {
635 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
636
637 if(FMC_READY == fmc_state){
638 /* set the OBPG bit */
639 FMC_CTL0 |= FMC_CTL0_OBPG;
640 REG16(address) = data;
641
642 /* wait for the FMC ready */
643 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
644
645 if(FMC_TOERR != fmc_state){
646 /* reset the OBPG bit */
647 FMC_CTL0 &= ~FMC_CTL0_OBPG;
648 }
649 }
650 /* return the FMC state */
651 return fmc_state;
652 }
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum ob_erase ( void )

erase the FMC option byte unlock the FMC_CTL0 and option byte before calling this function

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 434 of file gd32f10x_fmc.c.

435 {
436 uint16_t temp_spc = FMC_NSPC;
437
438 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
439
440 /* check the option byte security protection value */
441 if(RESET != ob_spc_get()){
442 temp_spc = FMC_USPC;
443 }
444
445 if(FMC_READY == fmc_state){
446
447 /* start erase the option byte */
448 FMC_CTL0 |= FMC_CTL0_OBER;
449 FMC_CTL0 |= FMC_CTL0_START;
450
451 /* wait for the FMC ready */
452 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
453
454 if(FMC_READY == fmc_state){
455 /* reset the OBER bit */
456 FMC_CTL0 &= ~FMC_CTL0_OBER;
457 /* set the OBPG bit */
458 FMC_CTL0 |= FMC_CTL0_OBPG;
459 /* no security protection */
460 OB_SPC = (uint16_t)temp_spc;
461 /* wait for the FMC ready */
462 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
463 if(FMC_TOERR != fmc_state){
464 /* reset the OBPG bit */
465 FMC_CTL0 &= ~FMC_CTL0_OBPG;
466 }
467 }else{
468 if(FMC_TOERR != fmc_state){
469 /* reset the OBPG bit */
470 FMC_CTL0 &= ~FMC_CTL0_OBPG;
471 }
472 }
473 }
474 /* return the FMC state */
475 return fmc_state;
476 }
FMC_CTL0_OBER
#define FMC_CTL0_OBER
Definition: gd32f10x_fmc.h:66
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
OB_SPC
#define OB_SPC
Definition: gd32f10x_fmc.h:38
FMC_TOERR
Definition: gd32f10x_fmc.h:137
FMC_NSPC
#define FMC_NSPC
Definition: gd32f10x_fmc.h:203
FMC_USPC
#define FMC_USPC
Definition: gd32f10x_fmc.h:204
ob_spc_get
FlagStatus ob_spc_get(void)
get the FMC option byte security protection
Definition: gd32f10x_fmc.c:695
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void ob_lock ( void )

lock the option byte operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 421 of file gd32f10x_fmc.c.

422 {
423 /* reset the OBWEN bit */
424 FMC_CTL0 &= ~FMC_CTL0_OBWEN;
425 }
FMC_CTL0_OBWEN
#define FMC_CTL0_OBWEN
Definition: gd32f10x_fmc.h:69
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum ob_security_protection_config ( uint8_t ob_spc )

configure security protection

Parameters
[in] ob_spc specify security protection
  • FMC_NSPC: no security protection
  • FMC_USPC: under security protection
[out] none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 544 of file gd32f10x_fmc.c.

545 {
546 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
547
548 if(FMC_READY == fmc_state){
549 FMC_CTL0 |= FMC_CTL0_OBER;
550 FMC_CTL0 |= FMC_CTL0_START;
551
552 /* wait for the FMC ready */
553 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
554
555 if(FMC_READY == fmc_state){
556 /* reset the OBER bit */
557 FMC_CTL0 &= ~FMC_CTL0_OBER;
558
559 /* start the option byte program */
560 FMC_CTL0 |= FMC_CTL0_OBPG;
561
562 OB_SPC = (uint16_t)ob_spc;
563
564 /* wait for the FMC ready */
565 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
566
567 if(FMC_TOERR != fmc_state){
568 /* reset the OBPG bit */
569 FMC_CTL0 &= ~FMC_CTL0_OBPG;
570 }
571 }else{
572 if(FMC_TOERR != fmc_state){
573 /* reset the OBER bit */
574 FMC_CTL0 &= ~FMC_CTL0_OBER;
575 }
576 }
577 }
578 /* return the FMC state */
579 return fmc_state;
580 }
FMC_CTL0_OBER
#define FMC_CTL0_OBER
Definition: gd32f10x_fmc.h:66
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
OB_SPC
#define OB_SPC
Definition: gd32f10x_fmc.h:38
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
FlagStatus ob_spc_get ( void )

get the FMC option byte security protection

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 695 of file gd32f10x_fmc.c.

696 {
697 FlagStatus spc_state = RESET;
698
699 if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){
700 spc_state = SET;
701 }else{
702 spc_state = RESET;
703 }
704 return spc_state;
705 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f10x_fmc.h:29
FMC_OBSTAT_SPC
#define FMC_OBSTAT_SPC
Definition: gd32f10x_fmc.h:78
void ob_unlock ( void )

unlock the option byte operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 402 of file gd32f10x_fmc.c.

403 {
404 if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
405 /* write the FMC key */
406 FMC_OBKEY = UNLOCK_KEY0;
407 FMC_OBKEY = UNLOCK_KEY1;
408 }
409
410 /* wait until OBWEN bit is set by hardware */
411 while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
412 }
413 }
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f10x_fmc.h:175
FMC_OBKEY
#define FMC_OBKEY
Definition: gd32f10x_fmc.h:25
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f10x_fmc.h:176
FMC_CTL0_OBWEN
#define FMC_CTL0_OBWEN
Definition: gd32f10x_fmc.h:69
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
uint8_t ob_user_get ( void )

get the FMC user option byte

Parameters
[in] | none
[out] | none
Return values
the FMC user option byte values

Definition at line 660 of file gd32f10x_fmc.c.

661 {
662 /* return the FMC user option byte value */
663 return (uint8_t)(FMC_OBSTAT >> 2U);
664 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f10x_fmc.h:29
fmc_state_enum ob_user_write | ( | uint8_t | ob_fwdgt,
 |  | uint8_t | ob_deepsleep,
 |  | uint8_t | ob_stdby,
 |  | uint8_t | ob_boot
 | ) |  |

program the FMC user option byte

Parameters
[in] ob_fwdgt option byte watchdog value
  • OB_FWDGT_SW: software free watchdog
  • OB_FWDGT_HW: hardware free watchdog
[in] ob_deepsleep option byte deepsleep reset value
  • OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode
  • OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode
[in] ob_stdby:option byte standby reset value
  • OB_STDBY_NRST: no reset when entering standby mode
  • OB_STDBY_RST: generate a reset instead of entering standby mode
[in] ob_boot specifies the option byte boot bank value
  • OB_BOOT_B0: boot from bank0
  • OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void
[out] none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 599 of file gd32f10x_fmc.c.

600 {
601 fmc_state_enum fmc_state = FMC_READY;
602 uint8_t temp;
603
604 /* wait for the FMC ready */
605 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
606
607 if(FMC_READY == fmc_state){
608 /* set the OBPG bit*/
609 FMC_CTL0 |= FMC_CTL0_OBPG;
610
611 temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK);
612 OB_USER = (uint16_t)temp;
613
614 /* wait for the FMC ready */
615 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
616
617 if(FMC_TOERR != fmc_state){
618 /* reset the OBPG bit */
619 FMC_CTL0 &= ~FMC_CTL0_OBPG;
620 }
621 }
622 /* return the FMC state */
623 return fmc_state;
624 }
OB_USER_MASK
#define OB_USER_MASK
Definition: gd32f10x_fmc.h:200
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
OB_USER
#define OB_USER
Definition: gd32f10x_fmc.h:39
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum ob_write_protection_enable ( uint32_t ob_wp )

enable write protection

Parameters
[in] ob_wp specify sector to be write protected
  • OB_WPx(x=0..31): write protect specify sector
  • OB_WP_ALL: write protect all sector
[out] none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 486 of file gd32f10x_fmc.c.

487 {
488 uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3;
489
490 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
491
492 ob_wp = (uint32_t)(~ob_wp);
493 temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0);
494 temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U);
495 temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U);
496 temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U);
497
498 if(FMC_READY == fmc_state){
499
500 /* set the OBPG bit*/
501 FMC_CTL0 |= FMC_CTL0_OBPG;
502
503 if(0xFFU != temp_wp0){
504 OB_WP0 = temp_wp0;
505
506 /* wait for the FMC ready */
507 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
508 }
509 if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){
510 OB_WP1 = temp_wp1;
511
512 /* wait for the FMC ready */
513 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
514 }
515 if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){
516 OB_WP2 = temp_wp2;
517
518 /* wait for the FMC ready */
519 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
520 }
521 if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){
522 OB_WP3 = temp_wp3;
523
524 /* wait for the FMC ready */
525 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
526 }
527 if(FMC_TOERR != fmc_state){
528 /* reset the OBPG bit */
529 FMC_CTL0 &= ~FMC_CTL0_OBPG;
530 }
531 }
532 /* return the FMC state */
533 return fmc_state;
534 }
OB_WP1_WP1
#define OB_WP1_WP1
Definition: gd32f10x_fmc.h:218
OB_WP0
#define OB_WP0
Definition: gd32f10x_fmc.h:40
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
OB_WP0_WP0
#define OB_WP0_WP0
Definition: gd32f10x_fmc.h:215
OB_WP3
#define OB_WP3
Definition: gd32f10x_fmc.h:43
FMC_TOERR
Definition: gd32f10x_fmc.h:137
OB_WP3_WP3
#define OB_WP3_WP3
Definition: gd32f10x_fmc.h:224
OB_WP2_WP2
#define OB_WP2_WP2
Definition: gd32f10x_fmc.h:221
OB_WP1
#define OB_WP1
Definition: gd32f10x_fmc.h:41
OB_WP2
#define OB_WP2
Definition: gd32f10x_fmc.h:42
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
uint32_t ob_write_protection_get ( void )

get the FMC option byte write protection

Parameters
[in] | none
[out] | none
Return values
the FMC write protection option byte value

Definition at line 683 of file gd32f10x_fmc.c.

684 {
685 /* return the FMC write protection option byte value */
686 return FMC_WP;
687 }
FMC_WP
#define FMC_WP
Definition: gd32f10x_fmc.h:30
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_fwdgt.h File Reference

definitions for the FWDGT More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | FWDGT FWDGT_BASE
#define | FWDGT_CTL REG32((FWDGT) + 0x00U)
#define | FWDGT_PSC REG32((FWDGT) + 0x04U)
#define | FWDGT_RLD REG32((FWDGT) + 0x08U)
#define | FWDGT_STAT REG32((FWDGT) + 0x0CU)
#define | FWDGT_CTL_CMD BITS(0,15)
#define | FWDGT_PSC_PSC BITS(0,2)
#define | FWDGT_RLD_RLD BITS(0,11)
#define | FWDGT_STAT_PUD BIT(0)
#define | FWDGT_STAT_RUD BIT(1)
#define | PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define | FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0))
#define | FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1))
#define | FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2))
#define | FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3))
#define | FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4))
#define | FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5))
#define | FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6))
#define | FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U)
#define | FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U)
#define | FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU)
#define | FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU)
#define | FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU)
#define | FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU)
#define | FWDGT_FLAG_PUD FWDGT_STAT_PUD
#define | FWDGT_FLAG_RUD FWDGT_STAT_RUD

Functions

void | fwdgt_write_disable (void)
disable write access to FWDGT_PSC and FWDGT_RLD More...
void | fwdgt_enable (void)
start the free watchdog timer counter More...
void | fwdgt_counter_reload (void)
reload the counter of FWDGT More...
ErrStatus | fwdgt_config (uint16_t reload_value, uint8_t prescaler_div)
configure counter reload value, and prescaler divider value More...
FlagStatus | fwdgt_flag_get (uint16_t flag)
get flag state of FWDGT More...

Detailed Description

definitions for the FWDGT

Definition in file gd32f10x_fwdgt.h.

Macro Definition Documentation

#define FWDGT FWDGT_BASE

FWDGT base address

Definition at line 19 of file gd32f10x_fwdgt.h.

#define FWDGT_CTL REG32((FWDGT) + 0x00U)

FWDGT control register

Definition at line 22 of file gd32f10x_fwdgt.h.

#define FWDGT_CTL_CMD BITS(0,15)

FWDGT command value

Definition at line 29 of file gd32f10x_fwdgt.h.

#define FWDGT_FLAG_PUD FWDGT_STAT_PUD

FWDGT prescaler divider value update flag

Definition at line 63 of file gd32f10x_fwdgt.h.

#define FWDGT_FLAG_RUD FWDGT_STAT_RUD

FWDGT counter reload value update flag

Definition at line 64 of file gd32f10x_fwdgt.h.

#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU)

FWDGT_CTL bits fwdgt counter enable value

Definition at line 56 of file gd32f10x_fwdgt.h.

#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU)

FWDGT_CTL bits fwdgt counter reload value

Definition at line 55 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC REG32((FWDGT) + 0x04U)

FWDGT prescaler register

Definition at line 23 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5))

FWDGT prescaler set to 128

Definition at line 49 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2))

FWDGT prescaler set to 16

Definition at line 46 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6))

FWDGT prescaler set to 256

Definition at line 50 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3))

FWDGT prescaler set to 32

Definition at line 47 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0))

FWDGT prescaler set to 4

Definition at line 44 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4))

FWDGT prescaler set to 64

Definition at line 48 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1))

FWDGT prescaler set to 8

Definition at line 45 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC_PSC BITS(0,2)

FWDGT prescaler divider value

Definition at line 32 of file gd32f10x_fwdgt.h.

#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU)

FWDGT_PSC register write operation state flag timeout

Definition at line 59 of file gd32f10x_fwdgt.h.

#define FWDGT_RLD REG32((FWDGT) + 0x08U)

FWDGT reload register

Definition at line 24 of file gd32f10x_fwdgt.h.

#define FWDGT_RLD_RLD BITS(0,11)

FWDGT counter reload value

Definition at line 35 of file gd32f10x_fwdgt.h.

#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU)

FWDGT_RLD register write operation state flag timeout

Definition at line 60 of file gd32f10x_fwdgt.h.

#define FWDGT_STAT REG32((FWDGT) + 0x0CU)

FWDGT status register

Definition at line 25 of file gd32f10x_fwdgt.h.

#define FWDGT_STAT_PUD BIT(0)

FWDGT prescaler divider value update

Definition at line 38 of file gd32f10x_fwdgt.h.

#define FWDGT_STAT_RUD BIT(1)

FWDGT counter reload value update

Definition at line 39 of file gd32f10x_fwdgt.h.

#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U)

FWDGT_CTL bits write access disable value

Definition at line 54 of file gd32f10x_fwdgt.h.

#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U)

FWDGT_CTL bits write access enable value

Definition at line 53 of file gd32f10x_fwdgt.h.

#define PSC_PSC ( regval ) (BITS(0,2) & ((uint32_t)(regval) << 0))

Definition at line 43 of file gd32f10x_fwdgt.h.

Function Documentation

ErrStatus fwdgt_config | ( | uint16_t | reload_value,
 |  | uint8_t | prescaler_div
 | ) |  |

configure counter reload value, and prescaler divider value

Parameters
[in] | reload_value | specify reload value(0x0000 - 0x0FFF)
[in] prescaler_div FWDGT prescaler value
  • FWDGT_PSC_DIV4: FWDGT prescaler set to 4
  • FWDGT_PSC_DIV8: FWDGT prescaler set to 8
  • FWDGT_PSC_DIV16: FWDGT prescaler set to 16
  • FWDGT_PSC_DIV32: FWDGT prescaler set to 32
  • FWDGT_PSC_DIV64: FWDGT prescaler set to 64
  • FWDGT_PSC_DIV128: FWDGT prescaler set to 128
  • FWDGT_PSC_DIV256: FWDGT prescaler set to 256
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 68 of file gd32f10x_fwdgt.c.

69 {
70 uint32_t timeout = FWDGT_PSC_TIMEOUT;
71 uint32_t flag_status = RESET;
72
73 /* enable write access to FWDGT_PSC,and FWDGT_RLD */
74 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
75 /* wait until the PUD flag to be reset */
76 do{
77 flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
78 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
79
80 if((uint32_t)RESET != flag_status){
81 return ERROR;
82 }
83 /* configure FWDGT */
84 FWDGT_PSC = (uint32_t)prescaler_div;
85
86 timeout = FWDGT_RLD_TIMEOUT;
87 /* wait until the RUD flag to be reset */
88 do{
89 flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
90 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
91
92 if((uint32_t)RESET != flag_status){
93 return ERROR;
94 }
95 FWDGT_RLD = RLD_RLD(reload_value);
96 /* reload the counter */
97 FWDGT_CTL = FWDGT_KEY_RELOAD;
98
99 return SUCCESS;
100 }
FWDGT_STAT_PUD
#define FWDGT_STAT_PUD
Definition: gd32f10x_fwdgt.h:38
FWDGT_RLD_TIMEOUT
#define FWDGT_RLD_TIMEOUT
Definition: gd32f10x_fwdgt.h:60
RLD_RLD
#define RLD_RLD(regval)
Definition: gd32f10x_fwdgt.c:18
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f10x_fwdgt.h:25
FWDGT_WRITEACCESS_ENABLE
#define FWDGT_WRITEACCESS_ENABLE
Definition: gd32f10x_fwdgt.h:53
FWDGT_RLD
#define FWDGT_RLD
Definition: gd32f10x_fwdgt.h:24
FWDGT_PSC_TIMEOUT
#define FWDGT_PSC_TIMEOUT
Definition: gd32f10x_fwdgt.h:59
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f10x_fwdgt.h:55
FWDGT_STAT_RUD
#define FWDGT_STAT_RUD
Definition: gd32f10x_fwdgt.h:39
FWDGT_PSC
#define FWDGT_PSC
Definition: gd32f10x_fwdgt.h:23
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f10x_fwdgt.h:22
void fwdgt_counter_reload ( void )

reload the counter of FWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 37 of file gd32f10x_fwdgt.c.

38 {
39 FWDGT_CTL = FWDGT_KEY_RELOAD;
40 }
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f10x_fwdgt.h:55
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f10x_fwdgt.h:22
void fwdgt_enable ( void )

start the free watchdog timer counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 48 of file gd32f10x_fwdgt.c.

49 {
50 FWDGT_CTL = FWDGT_KEY_ENABLE;
51 }
FWDGT_KEY_ENABLE
#define FWDGT_KEY_ENABLE
Definition: gd32f10x_fwdgt.h:56
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f10x_fwdgt.h:22
FlagStatus fwdgt_flag_get ( uint16_t flag )

get flag state of FWDGT

Parameters
[in] flag flag to get
  • FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
  • FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
[out] none
Return values
FlagStatus SET or RESET

Definition at line 110 of file gd32f10x_fwdgt.c.

111 {
112 if(FWDGT_STAT & flag){
113 return SET;
114 }
115 return RESET;
116 }
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f10x_fwdgt.h:25
void fwdgt_write_disable ( void )

disable write access to FWDGT_PSC and FWDGT_RLD

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 26 of file gd32f10x_fwdgt.c.

27 {
28 FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
29 }
FWDGT_WRITEACCESS_DISABLE
#define FWDGT_WRITEACCESS_DISABLE
Definition: gd32f10x_fwdgt.h:54
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f10x_fwdgt.h:22
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Typedefs | Functions
gd32f10x_gpio.h File Reference

definitions for the GPIO More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | GPIOA (GPIO_BASE + 0x00000000U)
#define | GPIOB (GPIO_BASE + 0x00000400U)
#define | GPIOC (GPIO_BASE + 0x00000800U)
#define | GPIOD (GPIO_BASE + 0x00000C00U)
#define | GPIOE (GPIO_BASE + 0x00001000U)
#define | GPIOF (GPIO_BASE + 0x00001400U)
#define | GPIOG (GPIO_BASE + 0x00001800U)
#define | AFIO AFIO_BASE
#define | GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U)
#define | GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U)
#define | GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U)
#define | GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU)
#define | GPIO_BOP(gpiox) REG32((gpiox) + 0x10U)
#define | GPIO_BC(gpiox) REG32((gpiox) + 0x14U)
#define | GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U)
#define | AFIO_EC REG32(AFIO + 0x00U)
#define | AFIO_PCF0 REG32(AFIO + 0x04U)
#define | AFIO_EXTISS0 REG32(AFIO + 0x08U)
#define | AFIO_EXTISS1 REG32(AFIO + 0x0CU)
#define | AFIO_EXTISS2 REG32(AFIO + 0x10U)
#define | AFIO_EXTISS3 REG32(AFIO + 0x14U)
#define | AFIO_PCF1 REG32(AFIO + 0x1CU)
#define | GPIO_CTL0_MD0 BITS(0,1)
#define | GPIO_CTL0_CTL0 BITS(2,3)
#define | GPIO_CTL0_MD1 BITS(4,5)
#define | GPIO_CTL0_CTL1 BITS(6,7)
#define | GPIO_CTL0_MD2 BITS(8,9)
#define | GPIO_CTL0_CTL2 BITS(10,11)
#define | GPIO_CTL0_MD3 BITS(12,13)
#define | GPIO_CTL0_CTL3 BITS(14,15)
#define | GPIO_CTL0_MD4 BITS(16,17)
#define | GPIO_CTL0_CTL4 BITS(18,19)
#define | GPIO_CTL0_MD5 BITS(20,21)
#define | GPIO_CTL0_CTL5 BITS(22,23)
#define | GPIO_CTL0_MD6 BITS(24,25)
#define | GPIO_CTL0_CTL6 BITS(26,27)
#define | GPIO_CTL0_MD7 BITS(28,29)
#define | GPIO_CTL0_CTL7 BITS(30,31)
#define | GPIO_CTL1_MD8 BITS(0,1)
#define | GPIO_CTL1_CTL8 BITS(2,3)
#define | GPIO_CTL1_MD9 BITS(4,5)
#define | GPIO_CTL1_CTL9 BITS(6,7)
#define | GPIO_CTL1_MD10 BITS(8,9)
#define | GPIO_CTL1_CTL10 BITS(10,11)
#define | GPIO_CTL1_MD11 BITS(12,13)
#define | GPIO_CTL1_CTL11 BITS(14,15)
#define | GPIO_CTL1_MD12 BITS(16,17)
#define | GPIO_CTL1_CTL12 BITS(18,19)
#define | GPIO_CTL1_MD13 BITS(20,21)
#define | GPIO_CTL1_CTL13 BITS(22,23)
#define | GPIO_CTL1_MD14 BITS(24,25)
#define | GPIO_CTL1_CTL14 BITS(26,27)
#define | GPIO_CTL1_MD15 BITS(28,29)
#define | GPIO_CTL1_CTL15 BITS(30,31)
#define | GPIO_ISTAT_ISTAT0 BIT(0)
#define | GPIO_ISTAT_ISTAT1 BIT(1)
#define | GPIO_ISTAT_ISTAT2 BIT(2)
#define | GPIO_ISTAT_ISTAT3 BIT(3)
#define | GPIO_ISTAT_ISTAT4 BIT(4)
#define | GPIO_ISTAT_ISTAT5 BIT(5)
#define | GPIO_ISTAT_ISTAT6 BIT(6)
#define | GPIO_ISTAT_ISTAT7 BIT(7)
#define | GPIO_ISTAT_ISTAT8 BIT(8)
#define | GPIO_ISTAT_ISTAT9 BIT(9)
#define | GPIO_ISTAT_ISTAT10 BIT(10)
#define | GPIO_ISTAT_ISTAT11 BIT(11)
#define | GPIO_ISTAT_ISTAT12 BIT(12)
#define | GPIO_ISTAT_ISTAT13 BIT(13)
#define | GPIO_ISTAT_ISTAT14 BIT(14)
#define | GPIO_ISTAT_ISTAT15 BIT(15)
#define | GPIO_OCTL_OCTL0 BIT(0)
#define | GPIO_OCTL_OCTL1 BIT(1)
#define | GPIO_OCTL_OCTL2 BIT(2)
#define | GPIO_OCTL_OCTL3 BIT(3)
#define | GPIO_OCTL_OCTL4 BIT(4)
#define | GPIO_OCTL_OCTL5 BIT(5)
#define | GPIO_OCTL_OCTL6 BIT(6)
#define | GPIO_OCTL_OCTL7 BIT(7)
#define | GPIO_OCTL_OCTL8 BIT(8)
#define | GPIO_OCTL_OCTL9 BIT(9)
#define | GPIO_OCTL_OCTL10 BIT(10)
#define | GPIO_OCTL_OCTL11 BIT(11)
#define | GPIO_OCTL_OCTL12 BIT(12)
#define | GPIO_OCTL_OCTL13 BIT(13)
#define | GPIO_OCTL_OCTL14 BIT(14)
#define | GPIO_OCTL_OCTL15 BIT(15)
#define | GPIO_BOP_BOP0 BIT(0)
#define | GPIO_BOP_BOP1 BIT(1)
#define | GPIO_BOP_BOP2 BIT(2)
#define | GPIO_BOP_BOP3 BIT(3)
#define | GPIO_BOP_BOP4 BIT(4)
#define | GPIO_BOP_BOP5 BIT(5)
#define | GPIO_BOP_BOP6 BIT(6)
#define | GPIO_BOP_BOP7 BIT(7)
#define | GPIO_BOP_BOP8 BIT(8)
#define | GPIO_BOP_BOP9 BIT(9)
#define | GPIO_BOP_BOP10 BIT(10)
#define | GPIO_BOP_BOP11 BIT(11)
#define | GPIO_BOP_BOP12 BIT(12)
#define | GPIO_BOP_BOP13 BIT(13)
#define | GPIO_BOP_BOP14 BIT(14)
#define | GPIO_BOP_BOP15 BIT(15)
#define | GPIO_BOP_CR0 BIT(16)
#define | GPIO_BOP_CR1 BIT(17)
#define | GPIO_BOP_CR2 BIT(18)
#define | GPIO_BOP_CR3 BIT(19)
#define | GPIO_BOP_CR4 BIT(20)
#define | GPIO_BOP_CR5 BIT(21)
#define | GPIO_BOP_CR6 BIT(22)
#define | GPIO_BOP_CR7 BIT(23)
#define | GPIO_BOP_CR8 BIT(24)
#define | GPIO_BOP_CR9 BIT(25)
#define | GPIO_BOP_CR10 BIT(26)
#define | GPIO_BOP_CR11 BIT(27)
#define | GPIO_BOP_CR12 BIT(28)
#define | GPIO_BOP_CR13 BIT(29)
#define | GPIO_BOP_CR14 BIT(30)
#define | GPIO_BOP_CR15 BIT(31)
#define | GPIO_BC_CR0 BIT(0)
#define | GPIO_BC_CR1 BIT(1)
#define | GPIO_BC_CR2 BIT(2)
#define | GPIO_BC_CR3 BIT(3)
#define | GPIO_BC_CR4 BIT(4)
#define | GPIO_BC_CR5 BIT(5)
#define | GPIO_BC_CR6 BIT(6)
#define | GPIO_BC_CR7 BIT(7)
#define | GPIO_BC_CR8 BIT(8)
#define | GPIO_BC_CR9 BIT(9)
#define | GPIO_BC_CR10 BIT(10)
#define | GPIO_BC_CR11 BIT(11)
#define | GPIO_BC_CR12 BIT(12)
#define | GPIO_BC_CR13 BIT(13)
#define | GPIO_BC_CR14 BIT(14)
#define | GPIO_BC_CR15 BIT(15)
#define | GPIO_LOCK_LK0 BIT(0)
#define | GPIO_LOCK_LK1 BIT(1)
#define | GPIO_LOCK_LK2 BIT(2)
#define | GPIO_LOCK_LK3 BIT(3)
#define | GPIO_LOCK_LK4 BIT(4)
#define | GPIO_LOCK_LK5 BIT(5)
#define | GPIO_LOCK_LK6 BIT(6)
#define | GPIO_LOCK_LK7 BIT(7)
#define | GPIO_LOCK_LK8 BIT(8)
#define | GPIO_LOCK_LK9 BIT(9)
#define | GPIO_LOCK_LK10 BIT(10)
#define | GPIO_LOCK_LK11 BIT(11)
#define | GPIO_LOCK_LK12 BIT(12)
#define | GPIO_LOCK_LK13 BIT(13)
#define | GPIO_LOCK_LK14 BIT(14)
#define | GPIO_LOCK_LK15 BIT(15)
#define | GPIO_LOCK_LKK BIT(16)
#define | AFIO_EC_PIN BITS(0,3)
#define | AFIO_EC_PORT BITS(4,6)
#define | AFIO_EC_EOE BIT(7)
#define | AFIO_PCF0_SPI0_REMAP BIT(0)
#define | AFIO_PCF0_I2C0_REMAP BIT(1)
#define | AFIO_PCF0_USART0_REMAP BIT(2)
#define | AFIO_PCF0_USART1_REMAP BIT(3)
#define | AFIO_PCF0_USART2_REMAP BITS(4,5)
#define | AFIO_PCF0_TIMER0_REMAP BITS(6,7)
#define | AFIO_PCF0_TIMER1_REMAP BITS(8,9)
#define | AFIO_PCF0_TIMER2_REMAP BITS(10,11)
#define | AFIO_PCF0_TIMER3_REMAP BIT(12)
#define | AFIO_PCF0_CAN0_REMAP BITS(13,14)
#define | AFIO_PCF0_PD01_REMAP BIT(15)
#define | AFIO_PCF0_TIMER4CH3_IREMAP BIT(16)
#define | AFIO_PCF0_ENET_REMAP BIT(21)
#define | AFIO_PCF0_CAN1_REMAP BIT(22)
#define | AFIO_PCF0_ENET_PHY_SEL BIT(23)
#define | AFIO_PCF0_SWJ_CFG BITS(24,26)
#define | AFIO_PCF0_SPI2_REMAP BIT(28)
#define | AFIO_PCF0_TIMER1ITR0_REMAP BIT(29)
#define | AFIO_PCF0_PTP_PPS_REMAP BIT(30)
#define | AFIO_EXTI0_SS BITS(0,3)
#define | AFIO_EXTI1_SS BITS(4,7)
#define | AFIO_EXTI2_SS BITS(8,11)
#define | AFIO_EXTI3_SS BITS(12,15)
#define | AFIO_EXTI4_SS BITS(0,3)
#define | AFIO_EXTI5_SS BITS(4,7)
#define | AFIO_EXTI6_SS BITS(8,11)
#define | AFIO_EXTI7_SS BITS(12,15)
#define | AFIO_EXTI8_SS BITS(0,3)
#define | AFIO_EXTI9_SS BITS(4,7)
#define | AFIO_EXTI10_SS BITS(8,11)
#define | AFIO_EXTI11_SS BITS(12,15)
#define | AFIO_EXTI12_SS BITS(0,3)
#define | AFIO_EXTI13_SS BITS(4,7)
#define | AFIO_EXTI14_SS BITS(8,11)
#define | AFIO_EXTI15_SS BITS(12,15)
#define | AFIO_PCF1_TIMER8_REMAP BIT(5)
#define | AFIO_PCF1_TIMER9_REMAP BIT(6)
#define | AFIO_PCF1_TIMER10_REMAP BIT(7)
#define | AFIO_PCF1_TIMER12_REMAP BIT(8)
#define | AFIO_PCF1_TIMER13_REMAP BIT(9)
#define | AFIO_PCF1_FSMC_NADV BIT(10)
#define | GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n))))
#define | GPIO_MODE_MASK(n) (0xFU << (4U * (n)))
#define | GPIO_MODE_AIN ((uint8_t)0x00U)
#define | GPIO_MODE_IN_FLOATING ((uint8_t)0x04U)
#define | GPIO_MODE_IPD ((uint8_t)0x28U)
#define | GPIO_MODE_IPU ((uint8_t)0x48U)
#define | GPIO_MODE_OUT_OD ((uint8_t)0x14U)
#define | GPIO_MODE_OUT_PP ((uint8_t)0x10U)
#define | GPIO_MODE_AF_OD ((uint8_t)0x1CU)
#define | GPIO_MODE_AF_PP ((uint8_t)0x18U)
#define | GPIO_OSPEED_10MHZ ((uint8_t)0x01U)
#define | GPIO_OSPEED_2MHZ ((uint8_t)0x02U)
#define | GPIO_OSPEED_50MHZ ((uint8_t)0x03U)
#define | GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U)
#define | GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U)
#define | GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U)
#define | GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U)
#define | GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U)
#define | GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U)
#define | GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U)
#define | GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U)
#define | GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U)
#define | GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U)
#define | GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U)
#define | GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U)
#define | GPIO_EVENT_PIN_0 ((uint8_t)0x00U)
#define | GPIO_EVENT_PIN_1 ((uint8_t)0x01U)
#define | GPIO_EVENT_PIN_2 ((uint8_t)0x02U)
#define | GPIO_EVENT_PIN_3 ((uint8_t)0x03U)
#define | GPIO_EVENT_PIN_4 ((uint8_t)0x04U)
#define | GPIO_EVENT_PIN_5 ((uint8_t)0x05U)
#define | GPIO_EVENT_PIN_6 ((uint8_t)0x06U)
#define | GPIO_EVENT_PIN_7 ((uint8_t)0x07U)
#define | GPIO_EVENT_PIN_8 ((uint8_t)0x08U)
#define | GPIO_EVENT_PIN_9 ((uint8_t)0x09U)
#define | GPIO_EVENT_PIN_10 ((uint8_t)0x0AU)
#define | GPIO_EVENT_PIN_11 ((uint8_t)0x0BU)
#define | GPIO_EVENT_PIN_12 ((uint8_t)0x0CU)
#define | GPIO_EVENT_PIN_13 ((uint8_t)0x0DU)
#define | GPIO_EVENT_PIN_14 ((uint8_t)0x0EU)
#define | GPIO_EVENT_PIN_15 ((uint8_t)0x0FU)
#define | GPIO_PIN_SOURCE_0 ((uint8_t)0x00U)
#define | GPIO_PIN_SOURCE_1 ((uint8_t)0x01U)
#define | GPIO_PIN_SOURCE_2 ((uint8_t)0x02U)
#define | GPIO_PIN_SOURCE_3 ((uint8_t)0x03U)
#define | GPIO_PIN_SOURCE_4 ((uint8_t)0x04U)
#define | GPIO_PIN_SOURCE_5 ((uint8_t)0x05U)
#define | GPIO_PIN_SOURCE_6 ((uint8_t)0x06U)
#define | GPIO_PIN_SOURCE_7 ((uint8_t)0x07U)
#define | GPIO_PIN_SOURCE_8 ((uint8_t)0x08U)
#define | GPIO_PIN_SOURCE_9 ((uint8_t)0x09U)
#define | GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU)
#define | GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU)
#define | GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU)
#define | GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU)
#define | GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU)
#define | GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU)
#define | GPIO_PIN_0 BIT(0)
#define | GPIO_PIN_1 BIT(1)
#define | GPIO_PIN_2 BIT(2)
#define | GPIO_PIN_3 BIT(3)
#define | GPIO_PIN_4 BIT(4)
#define | GPIO_PIN_5 BIT(5)
#define | GPIO_PIN_6 BIT(6)
#define | GPIO_PIN_7 BIT(7)
#define | GPIO_PIN_8 BIT(8)
#define | GPIO_PIN_9 BIT(9)
#define | GPIO_PIN_10 BIT(10)
#define | GPIO_PIN_11 BIT(11)
#define | GPIO_PIN_12 BIT(12)
#define | GPIO_PIN_13 BIT(13)
#define | GPIO_PIN_14 BIT(14)
#define | GPIO_PIN_15 BIT(15)
#define | GPIO_PIN_ALL BITS(0,15)
#define | GPIO_SPI0_REMAP ((uint32_t)0x00000001U)
#define | GPIO_I2C0_REMAP ((uint32_t)0x00000002U)
#define | GPIO_USART0_REMAP ((uint32_t)0x00000004U)
#define | GPIO_USART1_REMAP ((uint32_t)0x00000008U)
#define | GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U)
#define | GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U)
#define | GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U)
#define | GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U)
#define | GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U)
#define | GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U)
#define | GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U)
#define | GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U)
#define | GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U)
#define | GPIO_TIMER3_REMAP ((uint32_t)0x00001000U)
#define | GPIO_PD01_REMAP ((uint32_t)0x00008000U)
#define | GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U)
#define | GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U)
#define | GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U)
#define | GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U)
#define | GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U)
#define | GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U)
#define | GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U)
#define | GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U)
#define | GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U)
#define | GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U)
#define | GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U)
#define | GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U)
#define | GPIO_ENET_REMAP ((uint32_t)0x00200020U)
#define | GPIO_CAN1_REMAP ((uint32_t)0x00200040U)
#define | GPIO_SPI2_REMAP ((uint32_t)0x00201100U)
#define | GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00202000U)
#define | GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U)
#define | GPIO_TIMER8_REMAP ((uint32_t)0x80000020U)
#define | GPIO_TIMER9_REMAP ((uint32_t)0x80000040U)
#define | GPIO_TIMER10_REMAP ((uint32_t)0x80000080U)
#define | GPIO_TIMER12_REMAP ((uint32_t)0x80000100U)
#define | GPIO_TIMER13_REMAP ((uint32_t)0x80000200U)
#define | GPIO_FSMC_NADV_REMAP ((uint32_t)0x80000400U)
#define | GPIO_ENET_PHY_MII ((uint32_t)0x00000000U)
#define | GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL

Typedefs

typedef FlagStatus bit_status

Functions

void | gpio_deinit (uint32_t gpio_periph)
reset GPIO port More...
void | gpio_afio_deinit (void)
reset alternate function I/O(AFIO) More...
void | gpio_init (uint32_t gpio_periph, uint32_t gpio_mode, uint32_t gpio_speed, uint32_t pin)
GPIO parameter initialization. More...
void | gpio_bit_set (uint32_t gpio_periph, uint32_t pin)
set GPIO pin More...
void | gpio_bit_reset (uint32_t gpio_periph, uint32_t pin)
reset GPIO pin More...
void | gpio_bit_write (uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
write data to the specified GPIO pin More...
void | gpio_port_write (uint32_t gpio_periph, uint16_t data)
write data to the specified GPIO port More...
FlagStatus | gpio_input_bit_get (uint32_t gpio_periph, uint32_t pin)
get GPIO pin input status More...
uint16_t | gpio_input_port_get (uint32_t gpio_periph)
get GPIO port input status More...
FlagStatus | gpio_output_bit_get (uint32_t gpio_periph, uint32_t pin)
get GPIO pin output status More...
uint16_t | gpio_output_port_get (uint32_t gpio_periph)
get GPIO port output status More...
void | gpio_pin_lock (uint32_t gpio_periph, uint32_t pin)
lock GPIO pin More...
void | gpio_event_output_config (uint8_t gpio_outputport, uint8_t gpio_outputpin)
configure GPIO pin event output More...
void | gpio_event_output_enable (void)
enable GPIO pin event output More...
void | gpio_event_output_disable (void)
disable GPIO pin event output More...
void | gpio_exti_source_select (uint8_t gpio_outputport, uint8_t gpio_outputpin)
select GPIO pin exti sources More...
void | gpio_ethernet_phy_select (uint32_t gpio_enetsel)
select ethernet MII or RMII PHY More...
void | gpio_pin_remap_config (uint32_t gpio_remap, ControlStatus newvalue)
configure GPIO pin remap More...

Detailed Description

definitions for the GPIO

Definition in file gd32f10x_gpio.h.

Macro Definition Documentation

#define AFIO AFIO_BASE

Definition at line 28 of file gd32f10x_gpio.h.

#define AFIO_EC REG32(AFIO + 0x00U)

AFIO event control register

Definition at line 42 of file gd32f10x_gpio.h.

#define AFIO_EC_EOE BIT(7)

event output enable

Definition at line 197 of file gd32f10x_gpio.h.

#define AFIO_EC_PIN BITS(0,3)

event output pin selection

Definition at line 195 of file gd32f10x_gpio.h.

#define AFIO_EC_PORT BITS(4,6)

event output port selection

Definition at line 196 of file gd32f10x_gpio.h.

#define AFIO_EXTI0_SS BITS(0,3)

EXTI 0 sources selection

Definition at line 244 of file gd32f10x_gpio.h.

#define AFIO_EXTI10_SS BITS(8,11)

EXTI 10 sources selection

Definition at line 258 of file gd32f10x_gpio.h.

#define AFIO_EXTI11_SS BITS(12,15)

EXTI 11 sources selection

Definition at line 259 of file gd32f10x_gpio.h.

#define AFIO_EXTI12_SS BITS(0,3)

EXTI 12 sources selection

Definition at line 262 of file gd32f10x_gpio.h.

#define AFIO_EXTI13_SS BITS(4,7)

EXTI 13 sources selection

Definition at line 263 of file gd32f10x_gpio.h.

#define AFIO_EXTI14_SS BITS(8,11)

EXTI 14 sources selection

Definition at line 264 of file gd32f10x_gpio.h.

#define AFIO_EXTI15_SS BITS(12,15)

EXTI 15 sources selection

Definition at line 265 of file gd32f10x_gpio.h.

#define AFIO_EXTI1_SS BITS(4,7)

EXTI 1 sources selection

Definition at line 245 of file gd32f10x_gpio.h.

#define AFIO_EXTI2_SS BITS(8,11)

EXTI 2 sources selection

Definition at line 246 of file gd32f10x_gpio.h.

#define AFIO_EXTI3_SS BITS(12,15)

EXTI 3 sources selection

Definition at line 247 of file gd32f10x_gpio.h.

#define AFIO_EXTI4_SS BITS(0,3)

EXTI 4 sources selection

Definition at line 250 of file gd32f10x_gpio.h.

#define AFIO_EXTI5_SS BITS(4,7)

EXTI 5 sources selection

Definition at line 251 of file gd32f10x_gpio.h.

#define AFIO_EXTI6_SS BITS(8,11)

EXTI 6 sources selection

Definition at line 252 of file gd32f10x_gpio.h.

#define AFIO_EXTI7_SS BITS(12,15)

EXTI 7 sources selection

Definition at line 253 of file gd32f10x_gpio.h.

#define AFIO_EXTI8_SS BITS(0,3)

EXTI 8 sources selection

Definition at line 256 of file gd32f10x_gpio.h.

#define AFIO_EXTI9_SS BITS(4,7)

EXTI 9 sources selection

Definition at line 257 of file gd32f10x_gpio.h.

#define AFIO_EXTISS0 REG32(AFIO + 0x08U)

AFIO port EXTI sources selection register 0

Definition at line 44 of file gd32f10x_gpio.h.

#define AFIO_EXTISS1 REG32(AFIO + 0x0CU)

AFIO port EXTI sources selection register 1

Definition at line 45 of file gd32f10x_gpio.h.

#define AFIO_EXTISS2 REG32(AFIO + 0x10U)

AFIO port EXTI sources selection register 2

Definition at line 46 of file gd32f10x_gpio.h.

#define AFIO_EXTISS3 REG32(AFIO + 0x14U)

AFIO port EXTI sources selection register 3

Definition at line 47 of file gd32f10x_gpio.h.

#define AFIO_PCF0 REG32(AFIO + 0x04U)

AFIO port configuration register 0

Definition at line 43 of file gd32f10x_gpio.h.

#define AFIO_PCF0_CAN0_REMAP BITS(13,14)

CAN0 remapping

Definition at line 211 of file gd32f10x_gpio.h.

#define AFIO_PCF0_CAN1_REMAP BIT(22)

CAN1 remapping

Definition at line 215 of file gd32f10x_gpio.h.

#define AFIO_PCF0_ENET_PHY_SEL BIT(23)

ethernet MII or RMII PHY selection

Definition at line 216 of file gd32f10x_gpio.h.

#define AFIO_PCF0_ENET_REMAP BIT(21)

ethernet MAC I/O remapping

Definition at line 214 of file gd32f10x_gpio.h.

#define AFIO_PCF0_I2C0_REMAP BIT(1)

I2C0 remapping

Definition at line 203 of file gd32f10x_gpio.h.

#define AFIO_PCF0_PD01_REMAP BIT(15)

port D0/port D1 mapping on OSC_IN/OSC_OUT

Definition at line 212 of file gd32f10x_gpio.h.

#define AFIO_PCF0_PTP_PPS_REMAP BIT(30)

ethernet PTP PPS remapping

Definition at line 220 of file gd32f10x_gpio.h.

#define AFIO_PCF0_SPI0_REMAP BIT(0)

SPI0 remapping

Definition at line 202 of file gd32f10x_gpio.h.

#define AFIO_PCF0_SPI2_REMAP BIT(28)

SPI2/I2S2 remapping

Definition at line 218 of file gd32f10x_gpio.h.

#define AFIO_PCF0_SWJ_CFG BITS(24,26)

serial wire JTAG configuration

Definition at line 217 of file gd32f10x_gpio.h.

#define AFIO_PCF0_TIMER0_REMAP BITS(6,7)

TIMER0 remapping

Definition at line 207 of file gd32f10x_gpio.h.

#define AFIO_PCF0_TIMER1_REMAP BITS(8,9)

TIMER1 remapping

Definition at line 208 of file gd32f10x_gpio.h.

#define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29)

TIMER1 internal trigger 0 remapping

Definition at line 219 of file gd32f10x_gpio.h.

#define AFIO_PCF0_TIMER2_REMAP BITS(10,11)

TIMER2 remapping

Definition at line 209 of file gd32f10x_gpio.h.

#define AFIO_PCF0_TIMER3_REMAP BIT(12)

TIMER3 remapping

Definition at line 210 of file gd32f10x_gpio.h.

#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16)

TIMER3 channel3 internal remapping

Definition at line 213 of file gd32f10x_gpio.h.

#define AFIO_PCF0_USART0_REMAP BIT(2)

USART0 remapping

Definition at line 204 of file gd32f10x_gpio.h.

#define AFIO_PCF0_USART1_REMAP BIT(3)

USART1 remapping

Definition at line 205 of file gd32f10x_gpio.h.

#define AFIO_PCF0_USART2_REMAP BITS(4,5)

USART2 remapping

Definition at line 206 of file gd32f10x_gpio.h.

#define AFIO_PCF1 REG32(AFIO + 0x1CU)

AFIO port configuration register 1

Definition at line 48 of file gd32f10x_gpio.h.

#define AFIO_PCF1_FSMC_NADV BIT(10)

FSMC_NADV connect/disconnect

Definition at line 273 of file gd32f10x_gpio.h.

#define AFIO_PCF1_TIMER10_REMAP BIT(7)

TIMER10 remapping

Definition at line 270 of file gd32f10x_gpio.h.

#define AFIO_PCF1_TIMER12_REMAP BIT(8)

TIMER12 remapping

Definition at line 271 of file gd32f10x_gpio.h.

#define AFIO_PCF1_TIMER13_REMAP BIT(9)

TIMER13 remapping

Definition at line 272 of file gd32f10x_gpio.h.

#define AFIO_PCF1_TIMER8_REMAP BIT(5)

TIMER8 remapping

Definition at line 268 of file gd32f10x_gpio.h.

#define AFIO_PCF1_TIMER9_REMAP BIT(6)

TIMER9 remapping

Definition at line 269 of file gd32f10x_gpio.h.

#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U)

ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices)

Definition at line 392 of file gd32f10x_gpio.h.

#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U)

ADC0 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices)

Definition at line 393 of file gd32f10x_gpio.h.

#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U)

ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices)

Definition at line 394 of file gd32f10x_gpio.h.

#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U)

ADC1 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices)

Definition at line 395 of file gd32f10x_gpio.h.

#define GPIO_BC ( gpiox ) REG32((gpiox) + 0x14U)

GPIO bit clear register

Definition at line 38 of file gd32f10x_gpio.h.

#define GPIO_BC_CR0 BIT(0)

pin 0 clear bit

Definition at line 158 of file gd32f10x_gpio.h.

#define GPIO_BC_CR1 BIT(1)

pin 1 clear bit

Definition at line 159 of file gd32f10x_gpio.h.

#define GPIO_BC_CR10 BIT(10)

pin 10 clear bit

Definition at line 168 of file gd32f10x_gpio.h.

#define GPIO_BC_CR11 BIT(11)

pin 11 clear bit

Definition at line 169 of file gd32f10x_gpio.h.

#define GPIO_BC_CR12 BIT(12)

pin 12 clear bit

Definition at line 170 of file gd32f10x_gpio.h.

#define GPIO_BC_CR13 BIT(13)

pin 13 clear bit

Definition at line 171 of file gd32f10x_gpio.h.

#define GPIO_BC_CR14 BIT(14)

pin 14 clear bit

Definition at line 172 of file gd32f10x_gpio.h.

#define GPIO_BC_CR15 BIT(15)

pin 15 clear bit

Definition at line 173 of file gd32f10x_gpio.h.

#define GPIO_BC_CR2 BIT(2)

pin 2 clear bit

Definition at line 160 of file gd32f10x_gpio.h.

#define GPIO_BC_CR3 BIT(3)

pin 3 clear bit

Definition at line 161 of file gd32f10x_gpio.h.

#define GPIO_BC_CR4 BIT(4)

pin 4 clear bit

Definition at line 162 of file gd32f10x_gpio.h.

#define GPIO_BC_CR5 BIT(5)

pin 5 clear bit

Definition at line 163 of file gd32f10x_gpio.h.

#define GPIO_BC_CR6 BIT(6)

pin 6 clear bit

Definition at line 164 of file gd32f10x_gpio.h.

#define GPIO_BC_CR7 BIT(7)

pin 7 clear bit

Definition at line 165 of file gd32f10x_gpio.h.

#define GPIO_BC_CR8 BIT(8)

pin 8 clear bit

Definition at line 166 of file gd32f10x_gpio.h.

#define GPIO_BC_CR9 BIT(9)

pin 9 clear bit

Definition at line 167 of file gd32f10x_gpio.h.

#define GPIO_BOP ( gpiox ) REG32((gpiox) + 0x10U)

GPIO port bit operation register

Definition at line 37 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP0 BIT(0)

pin 0 set bit

Definition at line 124 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP1 BIT(1)

pin 1 set bit

Definition at line 125 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP10 BIT(10)

pin 10 set bit

Definition at line 134 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP11 BIT(11)

pin 11 set bit

Definition at line 135 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP12 BIT(12)

pin 12 set bit

Definition at line 136 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP13 BIT(13)

pin 13 set bit

Definition at line 137 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP14 BIT(14)

pin 14 set bit

Definition at line 138 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP15 BIT(15)

pin 15 set bit

Definition at line 139 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP2 BIT(2)

pin 2 set bit

Definition at line 126 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP3 BIT(3)

pin 3 set bit

Definition at line 127 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP4 BIT(4)

pin 4 set bit

Definition at line 128 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP5 BIT(5)

pin 5 set bit

Definition at line 129 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP6 BIT(6)

pin 6 set bit

Definition at line 130 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP7 BIT(7)

pin 7 set bit

Definition at line 131 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP8 BIT(8)

pin 8 set bit

Definition at line 132 of file gd32f10x_gpio.h.

#define GPIO_BOP_BOP9 BIT(9)

pin 9 set bit

Definition at line 133 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR0 BIT(16)

pin 0 clear bit

Definition at line 140 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR1 BIT(17)

pin 1 clear bit

Definition at line 141 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR10 BIT(26)

pin 10 clear bit

Definition at line 150 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR11 BIT(27)

pin 11 clear bit

Definition at line 151 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR12 BIT(28)

pin 12 clear bit

Definition at line 152 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR13 BIT(29)

pin 13 clear bit

Definition at line 153 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR14 BIT(30)

pin 14 clear bit

Definition at line 154 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR15 BIT(31)

pin 15 clear bit

Definition at line 155 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR2 BIT(18)

pin 2 clear bit

Definition at line 142 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR3 BIT(19)

pin 3 clear bit

Definition at line 143 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR4 BIT(20)

pin 4 clear bit

Definition at line 144 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR5 BIT(21)

pin 5 clear bit

Definition at line 145 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR6 BIT(22)

pin 6 clear bit

Definition at line 146 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR7 BIT(23)

pin 7 clear bit

Definition at line 147 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR8 BIT(24)

pin 8 clear bit

Definition at line 148 of file gd32f10x_gpio.h.

#define GPIO_BOP_CR9 BIT(25)

pin 9 clear bit

Definition at line 149 of file gd32f10x_gpio.h.

#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U)

CAN0 full remapping(only for GD32F10X_CL devices)

Definition at line 402 of file gd32f10x_gpio.h.

#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U)

CAN0 partial remapping(only for GD32F10X_CL devices)

Definition at line 401 of file gd32f10x_gpio.h.

#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U)

CAN1 remapping(only for GD32F10X_CL devices)

Definition at line 404 of file gd32f10x_gpio.h.

#define GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U)

CAN full remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices)

Definition at line 386 of file gd32f10x_gpio.h.

#define GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U)

CAN partial remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices)

Definition at line 385 of file gd32f10x_gpio.h.

#define GPIO_CTL0 ( gpiox ) REG32((gpiox) + 0x00U)

GPIO port control register 0

Definition at line 33 of file gd32f10x_gpio.h.

#define GPIO_CTL0_CTL0 BITS(2,3)

pin 0 configuration bits

Definition at line 53 of file gd32f10x_gpio.h.

#define GPIO_CTL0_CTL1 BITS(6,7)

pin 1 configuration bits

Definition at line 55 of file gd32f10x_gpio.h.

#define GPIO_CTL0_CTL2 BITS(10,11)

pin 2 configuration bits

Definition at line 57 of file gd32f10x_gpio.h.

#define GPIO_CTL0_CTL3 BITS(14,15)

pin 3 configuration bits

Definition at line 59 of file gd32f10x_gpio.h.

#define GPIO_CTL0_CTL4 BITS(18,19)

pin 4 configuration bits

Definition at line 61 of file gd32f10x_gpio.h.

#define GPIO_CTL0_CTL5 BITS(22,23)

pin 5 configuration bits

Definition at line 63 of file gd32f10x_gpio.h.

#define GPIO_CTL0_CTL6 BITS(26,27)

pin 6 configuration bits

Definition at line 65 of file gd32f10x_gpio.h.

#define GPIO_CTL0_CTL7 BITS(30,31)

pin 7 configuration bits

Definition at line 67 of file gd32f10x_gpio.h.

#define GPIO_CTL0_MD0 BITS(0,1)

port 0 mode bits

Definition at line 52 of file gd32f10x_gpio.h.

#define GPIO_CTL0_MD1 BITS(4,5)

port 1 mode bits

Definition at line 54 of file gd32f10x_gpio.h.

#define GPIO_CTL0_MD2 BITS(8,9)

port 2 mode bits

Definition at line 56 of file gd32f10x_gpio.h.

#define GPIO_CTL0_MD3 BITS(12,13)

port 3 mode bits

Definition at line 58 of file gd32f10x_gpio.h.

#define GPIO_CTL0_MD4 BITS(16,17)

port 4 mode bits

Definition at line 60 of file gd32f10x_gpio.h.

#define GPIO_CTL0_MD5 BITS(20,21)

port 5 mode bits

Definition at line 62 of file gd32f10x_gpio.h.

#define GPIO_CTL0_MD6 BITS(24,25)

port 6 mode bits

Definition at line 64 of file gd32f10x_gpio.h.

#define GPIO_CTL0_MD7 BITS(28,29)

port 7 mode bits

Definition at line 66 of file gd32f10x_gpio.h.

#define GPIO_CTL1 ( gpiox ) REG32((gpiox) + 0x04U)

GPIO port control register 1

Definition at line 34 of file gd32f10x_gpio.h.

#define GPIO_CTL1_CTL10 BITS(10,11)

pin 10 configuration bits

Definition at line 75 of file gd32f10x_gpio.h.

#define GPIO_CTL1_CTL11 BITS(14,15)

pin 11 configuration bits

Definition at line 77 of file gd32f10x_gpio.h.

#define GPIO_CTL1_CTL12 BITS(18,19)

pin 12 configuration bits

Definition at line 79 of file gd32f10x_gpio.h.

#define GPIO_CTL1_CTL13 BITS(22,23)

pin 13 configuration bits

Definition at line 81 of file gd32f10x_gpio.h.

#define GPIO_CTL1_CTL14 BITS(26,27)

pin 14 configuration bits

Definition at line 83 of file gd32f10x_gpio.h.

#define GPIO_CTL1_CTL15 BITS(30,31)

pin 15 configuration bits

Definition at line 85 of file gd32f10x_gpio.h.

#define GPIO_CTL1_CTL8 BITS(2,3)

pin 8 configuration bits

Definition at line 71 of file gd32f10x_gpio.h.

#define GPIO_CTL1_CTL9 BITS(6,7)

pin 9 configuration bits

Definition at line 73 of file gd32f10x_gpio.h.

#define GPIO_CTL1_MD10 BITS(8,9)

port 10 mode bits

Definition at line 74 of file gd32f10x_gpio.h.

#define GPIO_CTL1_MD11 BITS(12,13)

port 11 mode bits

Definition at line 76 of file gd32f10x_gpio.h.

#define GPIO_CTL1_MD12 BITS(16,17)

port 12 mode bits

Definition at line 78 of file gd32f10x_gpio.h.

#define GPIO_CTL1_MD13 BITS(20,21)

port 13 mode bits

Definition at line 80 of file gd32f10x_gpio.h.

#define GPIO_CTL1_MD14 BITS(24,25)

port 14 mode bits

Definition at line 82 of file gd32f10x_gpio.h.

#define GPIO_CTL1_MD15 BITS(28,29)

port 15 mode bits

Definition at line 84 of file gd32f10x_gpio.h.

#define GPIO_CTL1_MD8 BITS(0,1)

port 8 mode bits

Definition at line 70 of file gd32f10x_gpio.h.

#define GPIO_CTL1_MD9 BITS(4,5)

port 9 mode bits

Definition at line 72 of file gd32f10x_gpio.h.

#define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U)

configure ethernet MAC for connection with an MII PHY

Definition at line 420 of file gd32f10x_gpio.h.

#define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL

configure ethernet MAC for connection with an RMII PHY

Definition at line 421 of file gd32f10x_gpio.h.

#define GPIO_ENET_REMAP ((uint32_t)0x00200020U)

ENET remapping(only for GD32F10X_CL devices)

Definition at line 403 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U)

GPIO event pin 0

Definition at line 314 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U)

GPIO event pin 1

Definition at line 315 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU)

GPIO event pin 10

Definition at line 324 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU)

GPIO event pin 11

Definition at line 325 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU)

GPIO event pin 12

Definition at line 326 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU)

GPIO event pin 13

Definition at line 327 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU)

GPIO event pin 14

Definition at line 328 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU)

GPIO event pin 15

Definition at line 329 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U)

GPIO event pin 2

Definition at line 316 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U)

GPIO event pin 3

Definition at line 317 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U)

GPIO event pin 4

Definition at line 318 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U)

GPIO event pin 5

Definition at line 319 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U)

GPIO event pin 6

Definition at line 320 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U)

GPIO event pin 7

Definition at line 321 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U)

GPIO event pin 8

Definition at line 322 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U)

GPIO event pin 9

Definition at line 323 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U)

event output port A

Definition at line 298 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U)

event output port B

Definition at line 299 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U)

event output port C

Definition at line 300 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U)

event output port D

Definition at line 301 of file gd32f10x_gpio.h.

#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U)

event output port E

Definition at line 302 of file gd32f10x_gpio.h.

#define GPIO_FSMC_NADV_REMAP ((uint32_t)0x80000400U)

FSMC_NADV connect/disconnect

Definition at line 415 of file gd32f10x_gpio.h.

#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U)

I2C0 remapping

Definition at line 370 of file gd32f10x_gpio.h.

#define GPIO_ISTAT ( gpiox ) REG32((gpiox) + 0x08U)

GPIO port input status register

Definition at line 35 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT0 BIT(0)

pin 0 input status

Definition at line 88 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT1 BIT(1)

pin 1 input status

Definition at line 89 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT10 BIT(10)

pin 10 input status

Definition at line 98 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT11 BIT(11)

pin 11 input status

Definition at line 99 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT12 BIT(12)

pin 12 input status

Definition at line 100 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT13 BIT(13)

pin 13 input status

Definition at line 101 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT14 BIT(14)

pin 14 input status

Definition at line 102 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT15 BIT(15)

pin 15 input status

Definition at line 103 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT2 BIT(2)

pin 2 input status

Definition at line 90 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT3 BIT(3)

pin 3 input status

Definition at line 91 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT4 BIT(4)

pin 4 input status

Definition at line 92 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT5 BIT(5)

pin 5 input status

Definition at line 93 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT6 BIT(6)

pin 6 input status

Definition at line 94 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT7 BIT(7)

pin 7 input status

Definition at line 95 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT8 BIT(8)

pin 8 input status

Definition at line 96 of file gd32f10x_gpio.h.

#define GPIO_ISTAT_ISTAT9 BIT(9)

pin 9 input status

Definition at line 97 of file gd32f10x_gpio.h.

#define GPIO_LOCK ( gpiox ) REG32((gpiox) + 0x18U)

GPIO port configuration lock register

Definition at line 39 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK0 BIT(0)

pin 0 lock bit

Definition at line 176 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK1 BIT(1)

pin 1 lock bit

Definition at line 177 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK10 BIT(10)

pin 10 lock bit

Definition at line 186 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK11 BIT(11)

pin 11 lock bit

Definition at line 187 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK12 BIT(12)

pin 12 lock bit

Definition at line 188 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK13 BIT(13)

pin 13 lock bit

Definition at line 189 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK14 BIT(14)

pin 14 lock bit

Definition at line 190 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK15 BIT(15)

pin 15 lock bit

Definition at line 191 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK2 BIT(2)

pin 2 lock bit

Definition at line 178 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK3 BIT(3)

pin 3 lock bit

Definition at line 179 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK4 BIT(4)

pin 4 lock bit

Definition at line 180 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK5 BIT(5)

pin 5 lock bit

Definition at line 181 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK6 BIT(6)

pin 6 lock bit

Definition at line 182 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK7 BIT(7)

pin 7 lock bit

Definition at line 183 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK8 BIT(8)

pin 8 lock bit

Definition at line 184 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LK9 BIT(9)

pin 9 lock bit

Definition at line 185 of file gd32f10x_gpio.h.

#define GPIO_LOCK_LKK BIT(16)

pin sequence lock key

Definition at line 192 of file gd32f10x_gpio.h.

#define GPIO_MODE_AF_OD ((uint8_t)0x1CU)

AFIO output with open-drain

Definition at line 289 of file gd32f10x_gpio.h.

#define GPIO_MODE_AF_PP ((uint8_t)0x18U)

AFIO output with push-pull

Definition at line 290 of file gd32f10x_gpio.h.

#define GPIO_MODE_AIN ((uint8_t)0x00U)

analog input mode

Definition at line 283 of file gd32f10x_gpio.h.

#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U)

floating input mode

Definition at line 284 of file gd32f10x_gpio.h.

#define GPIO_MODE_IPD ((uint8_t)0x28U)

pull-down input mode

Definition at line 285 of file gd32f10x_gpio.h.

#define GPIO_MODE_IPU ((uint8_t)0x48U)

pull-up input mode

Definition at line 286 of file gd32f10x_gpio.h.

#define GPIO_MODE_MASK ( n ) (0xFU << (4U * (n)))

Definition at line 280 of file gd32f10x_gpio.h.

#define GPIO_MODE_OUT_OD ((uint8_t)0x14U)

GPIO output with open-drain

Definition at line 287 of file gd32f10x_gpio.h.

#define GPIO_MODE_OUT_PP ((uint8_t)0x10U)

GPIO output with push-pull

Definition at line 288 of file gd32f10x_gpio.h.

#define GPIO_MODE_SET | ( | n,
 |  | mode
 | ) | ((uint32_t)((uint32_t)(mode) << (4U * (n))))

Definition at line 279 of file gd32f10x_gpio.h.

#define GPIO_OCTL ( gpiox ) REG32((gpiox) + 0x0CU)

GPIO port output control register

Definition at line 36 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL0 BIT(0)

pin 0 output bit

Definition at line 106 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL1 BIT(1)

pin 1 output bit

Definition at line 107 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL10 BIT(10)

pin 10 output bit

Definition at line 116 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL11 BIT(11)

pin 11 output bit

Definition at line 117 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL12 BIT(12)

pin 12 output bit

Definition at line 118 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL13 BIT(13)

pin 13 output bit

Definition at line 119 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL14 BIT(14)

pin 14 output bit

Definition at line 120 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL15 BIT(15)

pin 15 output bit

Definition at line 121 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL2 BIT(2)

pin 2 output bit

Definition at line 108 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL3 BIT(3)

pin 3 output bit

Definition at line 109 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL4 BIT(4)

pin 4 output bit

Definition at line 110 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL5 BIT(5)

pin 5 output bit

Definition at line 111 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL6 BIT(6)

pin 6 output bit

Definition at line 112 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL7 BIT(7)

pin 7 output bit

Definition at line 113 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL8 BIT(8)

pin 8 output bit

Definition at line 114 of file gd32f10x_gpio.h.

#define GPIO_OCTL_OCTL9 BIT(9)

pin 9 output bit

Definition at line 115 of file gd32f10x_gpio.h.

#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U)

output max speed 10M

Definition at line 293 of file gd32f10x_gpio.h.

#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U)

output max speed 2M

Definition at line 294 of file gd32f10x_gpio.h.

#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U)

output max speed 50M

Definition at line 295 of file gd32f10x_gpio.h.

#define GPIO_PD01_REMAP ((uint32_t)0x00008000U)

PD01 remapping

Definition at line 383 of file gd32f10x_gpio.h.

#define GPIO_PIN_0 BIT(0)

GPIO pin 0

Definition at line 350 of file gd32f10x_gpio.h.

#define GPIO_PIN_1 BIT(1)

GPIO pin 1

Definition at line 351 of file gd32f10x_gpio.h.

#define GPIO_PIN_10 BIT(10)

GPIO pin 10

Definition at line 360 of file gd32f10x_gpio.h.

#define GPIO_PIN_11 BIT(11)

GPIO pin 11

Definition at line 361 of file gd32f10x_gpio.h.

#define GPIO_PIN_12 BIT(12)

GPIO pin 12

Definition at line 362 of file gd32f10x_gpio.h.

#define GPIO_PIN_13 BIT(13)

GPIO pin 13

Definition at line 363 of file gd32f10x_gpio.h.

#define GPIO_PIN_14 BIT(14)

GPIO pin 14

Definition at line 364 of file gd32f10x_gpio.h.

#define GPIO_PIN_15 BIT(15)

GPIO pin 15

Definition at line 365 of file gd32f10x_gpio.h.

#define GPIO_PIN_2 BIT(2)

GPIO pin 2

Definition at line 352 of file gd32f10x_gpio.h.

#define GPIO_PIN_3 BIT(3)

GPIO pin 3

Definition at line 353 of file gd32f10x_gpio.h.

#define GPIO_PIN_4 BIT(4)

GPIO pin 4

Definition at line 354 of file gd32f10x_gpio.h.

#define GPIO_PIN_5 BIT(5)

GPIO pin 5

Definition at line 355 of file gd32f10x_gpio.h.

#define GPIO_PIN_6 BIT(6)

GPIO pin 6

Definition at line 356 of file gd32f10x_gpio.h.

#define GPIO_PIN_7 BIT(7)

GPIO pin 7

Definition at line 357 of file gd32f10x_gpio.h.

#define GPIO_PIN_8 BIT(8)

GPIO pin 8

Definition at line 358 of file gd32f10x_gpio.h.

#define GPIO_PIN_9 BIT(9)

GPIO pin 9

Definition at line 359 of file gd32f10x_gpio.h.

#define GPIO_PIN_ALL BITS(0,15)

GPIO pin all

Definition at line 366 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U)

GPIO pin source 0

Definition at line 332 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U)

GPIO pin source 1

Definition at line 333 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU)

GPIO pin source 10

Definition at line 342 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU)

GPIO pin source 11

Definition at line 343 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU)

GPIO pin source 12

Definition at line 344 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU)

GPIO pin source 13

Definition at line 345 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU)

GPIO pin source 14

Definition at line 346 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU)

GPIO pin source 15

Definition at line 347 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U)

GPIO pin source 2

Definition at line 334 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U)

GPIO pin source 3

Definition at line 335 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U)

GPIO pin source 4

Definition at line 336 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U)

GPIO pin source 5

Definition at line 337 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U)

GPIO pin source 6

Definition at line 338 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U)

GPIO pin source 7

Definition at line 339 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U)

GPIO pin source 8

Definition at line 340 of file gd32f10x_gpio.h.

#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U)

GPIO pin source 9

Definition at line 341 of file gd32f10x_gpio.h.

#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U)

output port source A

Definition at line 305 of file gd32f10x_gpio.h.

#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U)

output port source B

Definition at line 306 of file gd32f10x_gpio.h.

#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U)

output port source C

Definition at line 307 of file gd32f10x_gpio.h.

#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U)

output port source D

Definition at line 308 of file gd32f10x_gpio.h.

#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U)

output port source E

Definition at line 309 of file gd32f10x_gpio.h.

#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U)

output port source F

Definition at line 310 of file gd32f10x_gpio.h.

#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U)

output port source G

Definition at line 311 of file gd32f10x_gpio.h.

#define GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U)

ethernet PTP PPS remapping(only for GD32F10X_CL devices)

Definition at line 407 of file gd32f10x_gpio.h.

#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U)

SPI0 remapping

Definition at line 369 of file gd32f10x_gpio.h.

#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U)

SPI2 remapping(only for GD32F10X_CL devices)

Definition at line 405 of file gd32f10x_gpio.h.

#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U)

JTAG-DP disabled and SW-DP disabled

Definition at line 399 of file gd32f10x_gpio.h.

#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U)

full SWJ(JTAG-DP + SW-DP),but without NJTRST

Definition at line 397 of file gd32f10x_gpio.h.

#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U)

JTAG-DP disabled and SW-DP enabled

Definition at line 398 of file gd32f10x_gpio.h.

#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U)

TIMER0 full remapping

Definition at line 376 of file gd32f10x_gpio.h.

#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U)

TIMER0 partial remapping

Definition at line 375 of file gd32f10x_gpio.h.

#define GPIO_TIMER10_REMAP ((uint32_t)0x80000080U)

TIMER10 remapping

Definition at line 412 of file gd32f10x_gpio.h.

#define GPIO_TIMER12_REMAP ((uint32_t)0x80000100U)

TIMER12 remapping

Definition at line 413 of file gd32f10x_gpio.h.

#define GPIO_TIMER13_REMAP ((uint32_t)0x80000200U)

TIMER13 remapping

Definition at line 414 of file gd32f10x_gpio.h.

#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U)

TIMER1 full remapping

Definition at line 379 of file gd32f10x_gpio.h.

#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U)

TIMER1 partial remapping

Definition at line 377 of file gd32f10x_gpio.h.

#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U)

TIMER1 partial remapping

Definition at line 378 of file gd32f10x_gpio.h.

#define GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00202000U)

TIMER1 internal trigger 0 remapping(only for GD32F10X_CL devices)

Definition at line 406 of file gd32f10x_gpio.h.

#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U)

TIMER2 full remapping

Definition at line 381 of file gd32f10x_gpio.h.

#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U)

TIMER2 partial remapping

Definition at line 380 of file gd32f10x_gpio.h.

#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U)

TIMER3 remapping

Definition at line 382 of file gd32f10x_gpio.h.

#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U)

TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices)

Definition at line 389 of file gd32f10x_gpio.h.

#define GPIO_TIMER8_REMAP ((uint32_t)0x80000020U)

TIMER8 remapping

Definition at line 410 of file gd32f10x_gpio.h.

#define GPIO_TIMER9_REMAP ((uint32_t)0x80000040U)

TIMER9 remapping

Definition at line 411 of file gd32f10x_gpio.h.

#define GPIO_USART0_REMAP ((uint32_t)0x00000004U)

USART0 remapping

Definition at line 371 of file gd32f10x_gpio.h.

#define GPIO_USART1_REMAP ((uint32_t)0x00000008U)

USART1 remapping

Definition at line 372 of file gd32f10x_gpio.h.

#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U)

USART2 full remapping

Definition at line 374 of file gd32f10x_gpio.h.

#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U)

USART2 partial remapping

Definition at line 373 of file gd32f10x_gpio.h.

#define GPIOA (GPIO_BASE + 0x00000000U)

Definition at line 19 of file gd32f10x_gpio.h.

#define GPIOB (GPIO_BASE + 0x00000400U)

Definition at line 20 of file gd32f10x_gpio.h.

#define GPIOC (GPIO_BASE + 0x00000800U)

Definition at line 21 of file gd32f10x_gpio.h.

#define GPIOD (GPIO_BASE + 0x00000C00U)

Definition at line 22 of file gd32f10x_gpio.h.

#define GPIOE (GPIO_BASE + 0x00001000U)

Definition at line 23 of file gd32f10x_gpio.h.

#define GPIOF (GPIO_BASE + 0x00001400U)

Definition at line 24 of file gd32f10x_gpio.h.

#define GPIOG (GPIO_BASE + 0x00001800U)

Definition at line 25 of file gd32f10x_gpio.h.

Typedef Documentation

typedef FlagStatus bit_status

Definition at line 276 of file gd32f10x_gpio.h.

Function Documentation

void gpio_afio_deinit ( void )

reset alternate function I/O(AFIO)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 78 of file gd32f10x_gpio.c.

79 {
80 rcu_periph_reset_enable(RCU_AFRST);
81 rcu_periph_reset_disable(RCU_AFRST);
82 }
RCU_AFRST
Definition: gd32f10x_rcu.h:477
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void gpio_bit_reset | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

reset GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 188 of file gd32f10x_gpio.c.

189 {
190 GPIO_BC(gpio_periph) = (uint32_t)pin;
191 }
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f10x_gpio.h:38
void gpio_bit_set | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

set GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 176 of file gd32f10x_gpio.c.

177 {
178 GPIO_BOP(gpio_periph) = (uint32_t)pin;
179 }
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f10x_gpio.h:37
void gpio_bit_write | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin,
 |  | bit_status | bit_value
 | ) |  |

write data to the specified GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[in] bit_value SET or RESET
  • RESET: clear the port pin
  • SET: set the port pin
[out] | none
Return values
none

Definition at line 203 of file gd32f10x_gpio.c.

204 {
205 if(RESET != bit_value){
206 GPIO_BOP(gpio_periph) = (uint32_t)pin;
207 }else{
208 GPIO_BC(gpio_periph) = (uint32_t)pin;
209 }
210 }
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f10x_gpio.h:37
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f10x_gpio.h:38
void gpio_deinit ( uint32_t gpio_periph )

reset GPIO port

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[out] | none
Return values
none

Definition at line 29 of file gd32f10x_gpio.c.

30 {
31 switch(gpio_periph){
32 case GPIOA:
33 /* reset GPIOA */
34 rcu_periph_reset_enable(RCU_GPIOARST);
35 rcu_periph_reset_disable(RCU_GPIOARST);
36 break;
37 case GPIOB:
38 /* reset GPIOB */
39 rcu_periph_reset_enable(RCU_GPIOBRST);
40 rcu_periph_reset_disable(RCU_GPIOBRST);
41 break;
42 case GPIOC:
43 /* reset GPIOC */
44 rcu_periph_reset_enable(RCU_GPIOCRST);
45 rcu_periph_reset_disable(RCU_GPIOCRST);
46 break;
47 case GPIOD:
48 /* reset GPIOD */
49 rcu_periph_reset_enable(RCU_GPIODRST);
50 rcu_periph_reset_disable(RCU_GPIODRST);
51 break;
52 case GPIOE:
53 /* reset GPIOE */
54 rcu_periph_reset_enable(RCU_GPIOERST);
55 rcu_periph_reset_disable(RCU_GPIOERST);
56 break;
57 case GPIOF:
58 /* reset GPIOF */
59 rcu_periph_reset_enable(RCU_GPIOFRST);
60 rcu_periph_reset_disable(RCU_GPIOFRST);
61 break;
62 case GPIOG:
63 /* reset GPIOG */
64 rcu_periph_reset_enable(RCU_GPIOGRST);
65 rcu_periph_reset_disable(RCU_GPIOGRST);
66 break;
67 default:
68 break;
69 }
70 }
RCU_GPIOGRST
Definition: gd32f10x_rcu.h:484
RCU_GPIOBRST
Definition: gd32f10x_rcu.h:479
GPIOD
#define GPIOD
Definition: gd32f10x_gpio.h:22
RCU_GPIOFRST
Definition: gd32f10x_rcu.h:483
GPIOA
#define GPIOA
Definition: gd32f10x_gpio.h:19
RCU_GPIODRST
Definition: gd32f10x_rcu.h:481
GPIOF
#define GPIOF
Definition: gd32f10x_gpio.h:24
RCU_GPIOARST
Definition: gd32f10x_rcu.h:478
GPIOB
#define GPIOB
Definition: gd32f10x_gpio.h:20
GPIOG
#define GPIOG
Definition: gd32f10x_gpio.h:25
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
RCU_GPIOCRST
Definition: gd32f10x_rcu.h:480
GPIOE
#define GPIOE
Definition: gd32f10x_gpio.h:23
RCU_GPIOERST
Definition: gd32f10x_rcu.h:482
GPIOC
#define GPIOC
Definition: gd32f10x_gpio.h:21
void gpio_ethernet_phy_select ( uint32_t gpio_enetsel )

select ethernet MII or RMII PHY

Parameters
[in] gpio_enetsel ethernet MII or RMII PHY selection
  • GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY
  • GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY
[out] none
Return values
none

Definition at line 394 of file gd32f10x_gpio.c.

395 {
396 /* clear AFIO_PCF0_ENET_PHY_SEL bit */
397 AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL);
398
399 /* select MII or RMII PHY */
400 AFIO_PCF0 |= (uint32_t)gpio_enetsel;
401 }
AFIO_PCF0_ENET_PHY_SEL
#define AFIO_PCF0_ENET_PHY_SEL
Definition: gd32f10x_gpio.h:216
AFIO_PCF0
#define AFIO_PCF0
Definition: gd32f10x_gpio.h:43
void gpio_event_output_config | ( | uint8_t | gpio_outputport,
 |  | uint8_t | gpio_outputpin
 | ) |  |

configure GPIO pin event output

Parameters
[in] gpio_outputport gpio event output port
  • GPIO_EVENT_PORT_GPIOA: event output port A
  • GPIO_EVENT_PORT_GPIOB: event output port B
  • GPIO_EVENT_PORT_GPIOC: event output port C
  • GPIO_EVENT_PORT_GPIOD: event output port D
  • GPIO_EVENT_PORT_GPIOE: event output port E
[in] | gpio_outputpin | GPIO_EVENT_PIN_x(x=0..15)
[out] | none
Return values
none

Definition at line 310 of file gd32f10x_gpio.c.

311 {
312 uint32_t reg = 0U;
313 reg = AFIO_EC;
314
315 /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */
316 reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN));
317
318 reg |= (uint32_t)((uint32_t)gpio_outputport << 0x04U);
319 reg |= (uint32_t)gpio_outputpin;
320
321 AFIO_EC = reg;
322 }
AFIO_EC_PIN
#define AFIO_EC_PIN
Definition: gd32f10x_gpio.h:195
AFIO_EC
#define AFIO_EC
Definition: gd32f10x_gpio.h:42
AFIO_EC_PORT
#define AFIO_EC_PORT
Definition: gd32f10x_gpio.h:196
void gpio_event_output_disable ( void )

disable GPIO pin event output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 341 of file gd32f10x_gpio.c.

342 {
343 AFIO_EC &= (uint32_t)(~AFIO_EC_EOE);
344 }
AFIO_EC_EOE
#define AFIO_EC_EOE
Definition: gd32f10x_gpio.h:197
AFIO_EC
#define AFIO_EC
Definition: gd32f10x_gpio.h:42
void gpio_event_output_enable ( void )

enable GPIO pin event output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 330 of file gd32f10x_gpio.c.

331 {
332 AFIO_EC |= AFIO_EC_EOE;
333 }
AFIO_EC_EOE
#define AFIO_EC_EOE
Definition: gd32f10x_gpio.h:197
AFIO_EC
#define AFIO_EC
Definition: gd32f10x_gpio.h:42
void gpio_exti_source_select | ( | uint8_t | gpio_outputport,
 |  | uint8_t | gpio_outputpin
 | ) |  |

select GPIO pin exti sources

Parameters
[in] gpio_outputport gpio event output port
  • GPIO_PORT_SOURCE_GPIOA: output port source A
  • GPIO_PORT_SOURCE_GPIOB: output port source B
  • GPIO_PORT_SOURCE_GPIOC: output port source C
  • GPIO_PORT_SOURCE_GPIOD: output port source D
  • GPIO_PORT_SOURCE_GPIOE: output port source E
  • GPIO_PORT_SOURCE_GPIOF: output port source F
  • GPIO_PORT_SOURCE_GPIOG: output port source G
[in] | gpio_outputpin | GPIO_PIN_SOURCE_x(x=0..15)
[out] | none
Return values
none

Definition at line 360 of file gd32f10x_gpio.c.

361 {
362 uint32_t source = 0U;
363 source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U));
364
365 /* select EXTI sources */
366 if(GPIO_PIN_SOURCE_4 > gpio_outputpin){
367 /* select EXTI0/EXTI1/EXTI2/EXTI3 */
368 AFIO_EXTISS0 &= ~source;
369 AFIO_EXTISS0 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
370 }else if(GPIO_PIN_SOURCE_8 > gpio_outputpin){
371 /* select EXTI4/EXTI5/EXTI6/EXTI7 */
372 AFIO_EXTISS1 &= ~source;
373 AFIO_EXTISS1 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
374 }else if(GPIO_PIN_SOURCE_12 > gpio_outputpin){
375 /* select EXTI8/EXTI9/EXTI10/EXTI11 */
376 AFIO_EXTISS2 &= ~source;
377 AFIO_EXTISS2 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
378 }else{
379 /* select EXTI12/EXTI13/EXTI14/EXTI15 */
380 AFIO_EXTISS3 &= ~source;
381 AFIO_EXTISS3 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
382 }
383 }
AFIO_EXTISS1
#define AFIO_EXTISS1
Definition: gd32f10x_gpio.h:45
GPIO_PIN_SOURCE_8
#define GPIO_PIN_SOURCE_8
Definition: gd32f10x_gpio.h:340
GPIO_PIN_SOURCE_4
#define GPIO_PIN_SOURCE_4
Definition: gd32f10x_gpio.h:336
AFIO_EXTISS3
#define AFIO_EXTISS3
Definition: gd32f10x_gpio.h:47
GPIO_PIN_SOURCE_12
#define GPIO_PIN_SOURCE_12
Definition: gd32f10x_gpio.h:344
AFIO_EXTISS0
#define AFIO_EXTISS0
Definition: gd32f10x_gpio.h:44
AFIO_EXTISS2
#define AFIO_EXTISS2
Definition: gd32f10x_gpio.h:46
AFIO_EXTI_SOURCE_FIELDS
#define AFIO_EXTI_SOURCE_FIELDS
Definition: gd32f10x_gpio.c:15
void gpio_init | ( | uint32_t | gpio_periph,
 |  | uint32_t | gpio_mode,
 |  | uint32_t | gpio_speed,
 |  | uint32_t | pin
 | ) |  |

GPIO parameter initialization.

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] gpio_mode gpio pin mode
  • GPIO_MODE_AIN: analog input mode
  • GPIO_MODE_IN_FLOATING: floating input mode
  • GPIO_MODE_IPD: pull-down input mode
  • GPIO_MODE_IPU: pull-up input mode
  • GPIO_MODE_OUT_OD: GPIO output with open-drain
  • GPIO_MODE_OUT_PP: GPIO output with push-pull
  • GPIO_MODE_AF_OD: AFIO output with open-drain
  • GPIO_MODE_AF_PP: AFIO output with push-pull
[in] gpio_speed gpio output max speed value
  • GPIO_OSPEED_10MHZ: output max speed 10MHz
  • GPIO_OSPEED_2MHZ: output max speed 2MHz
  • GPIO_OSPEED_50MHZ: output max speed 50MHz
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 104 of file gd32f10x_gpio.c.

105 {
106 uint16_t i;
107 uint32_t temp_mode = 0U;
108 uint32_t reg = 0U;
109
110 /* GPIO mode configuration */
111 temp_mode = (uint32_t)(gpio_mode & ((uint32_t)0x0FU));
112
113 /* GPIO speed configuration */
114 if(((uint32_t)0x00U) != ((uint32_t)gpio_mode & ((uint32_t)0x10U))){
115 /* output mode max speed:10MHz,2MHz,50MHz */
116 temp_mode |= (uint32_t)gpio_speed;
117 }
118
119 /* configure the eight low port pins with GPIO_CTL0 */
120 for(i = 0U;i < 8U;i++){
121 if((1U << i) & pin){
122 reg = GPIO_CTL0(gpio_periph);
123
124 /* clear the specified pin mode bits */
125 reg &= ~GPIO_MODE_MASK(i);
126 /* set the specified pin mode bits */
127 reg |= GPIO_MODE_SET(i, temp_mode);
128
129 /* set IPD or IPU */
130 if(GPIO_MODE_IPD == gpio_mode){
131 /* reset the corresponding OCTL bit */
132 GPIO_BC(gpio_periph) = (uint32_t)pin;
133 }else{
134 /* set the corresponding OCTL bit */
135 if(GPIO_MODE_IPU == gpio_mode){
136 GPIO_BOP(gpio_periph) = (uint32_t)pin;
137 }
138 }
139 /* set GPIO_CTL0 register */
140 GPIO_CTL0(gpio_periph) = reg;
141 }
142 }
143 /* configure the eight high port pins with GPIO_CTL1 */
144 for(i = 8U;i < 16U;i++){
145 if((1U << i) & pin){
146 reg = GPIO_CTL1(gpio_periph);
147
148 /* clear the specified pin mode bits */
149 reg &= ~GPIO_MODE_MASK(i - 8U);
150 /* set the specified pin mode bits */
151 reg |= GPIO_MODE_SET(i - 8U, temp_mode);
152
153 /* set IPD or IPU */
154 if(GPIO_MODE_IPD == gpio_mode){
155 /* reset the corresponding OCTL bit */
156 GPIO_BC(gpio_periph) = (uint32_t)pin;
157 }else{
158 /* set the corresponding OCTL bit */
159 if(GPIO_MODE_IPU == gpio_mode){
160 GPIO_BOP(gpio_periph) = (uint32_t)pin;
161 }
162 }
163 /* set GPIO_CTL1 register */
164 GPIO_CTL1(gpio_periph) = reg;
165 }
166 }
167 }
GPIO_MODE_IPU
#define GPIO_MODE_IPU
Definition: gd32f10x_gpio.h:286
GPIO_MODE_IPD
#define GPIO_MODE_IPD
Definition: gd32f10x_gpio.h:285
GPIO_CTL1
#define GPIO_CTL1(gpiox)
Definition: gd32f10x_gpio.h:34
GPIO_MODE_SET
#define GPIO_MODE_SET(n, mode)
Definition: gd32f10x_gpio.h:279
GPIO_MODE_MASK
#define GPIO_MODE_MASK(n)
Definition: gd32f10x_gpio.h:280
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f10x_gpio.h:37
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f10x_gpio.h:38
GPIO_CTL0
#define GPIO_CTL0(gpiox)
Definition: gd32f10x_gpio.h:33
FlagStatus gpio_input_bit_get | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

get GPIO pin input status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
input status of gpio pin: SET or RESET

Definition at line 231 of file gd32f10x_gpio.c.

232 {
233 if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
234 return SET;
235 }else{
236 return RESET;
237 }
238 }
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f10x_gpio.h:35
uint16_t gpio_input_port_get ( uint32_t gpio_periph )

get GPIO port input status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[out] | none
Return values
input status of gpio all pins

Definition at line 246 of file gd32f10x_gpio.c.

247 {
248 return (uint16_t)(GPIO_ISTAT(gpio_periph));
249 }
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f10x_gpio.h:35
FlagStatus gpio_output_bit_get | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

get GPIO pin output status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
output status of gpio pin: SET or RESET

Definition at line 258 of file gd32f10x_gpio.c.

259 {
260 if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){
261 return SET;
262 }else{
263 return RESET;
264 }
265 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f10x_gpio.h:36
uint16_t gpio_output_port_get ( uint32_t gpio_periph )

get GPIO port output status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[out] | none
Return values
output status of gpio all pins

Definition at line 273 of file gd32f10x_gpio.c.

274 {
275 return ((uint16_t)GPIO_OCTL(gpio_periph));
276 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f10x_gpio.h:36
void gpio_pin_lock | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

lock GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 285 of file gd32f10x_gpio.c.

286 {
287 uint32_t lock = 0x00010000U;
288 lock |= pin;
289
290 /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */
291 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
292 GPIO_LOCK(gpio_periph) = (uint32_t)pin;
293 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
294 lock = GPIO_LOCK(gpio_periph);
295 lock = GPIO_LOCK(gpio_periph);
296 }
GPIO_LOCK
#define GPIO_LOCK(gpiox)
Definition: gd32f10x_gpio.h:39
void gpio_pin_remap_config | ( | uint32_t | gpio_remap,
 |  | ControlStatus | newvalue
 | ) |  |

configure GPIO pin remap

Parameters
[in] gpio_remap select the pin to remap
  • GPIO_SPI0_REMAP: SPI0 remapping
  • GPIO_I2C0_REMAP: I2C0 remapping
  • GPIO_USART0_REMAP: USART0 remapping
  • GPIO_USART1_REMAP: USART1 remapping
  • GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping
  • GPIO_USART2_FULL_REMAP: USART2 full remapping
  • GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping
  • GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping
  • GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping
  • GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping
  • GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping
  • GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping
  • GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping
  • GPIO_TIMER3_REMAP: TIMER3 remapping
  • GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F10X_CL devices)
  • GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F10X_CL devices)
  • GPIO_PD01_REMAP: PD01 remapping
  • GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices)
  • GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_ENET_REMAP: ENET remapping(only for GD32F10X_CL devices)
  • GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F10X_CL devices)
  • GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST
  • GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled
  • GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled
  • GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F10X_CL devices)
  • GPIO_TIMER1ITR0_REMAP: TIMER1 internal trigger 0 remapping(only for GD32F10X_CL devices)
  • GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F10X_CL devices)
  • GPIO_TIMER8_REMAP: TIMER8 remapping
  • GPIO_TIMER9_REMAP: TIMER9 remapping
  • GPIO_TIMER10_REMAP: TIMER10 remapping
  • GPIO_TIMER12_REMAP: TIMER12 remapping
  • GPIO_TIMER13_REMAP: TIMER13 remapping
  • GPIO_FSMC_NADV_REMAP: FSMC_NADV connect/disconnect
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 449 of file gd32f10x_gpio.c.

450 {
451 uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;
452
453 if(((uint32_t)0x80000000U) == (gpio_remap & 0x80000000U)){
454 /* get AFIO_PCF1 regiter value */
455 temp_reg = AFIO_PCF1;
456 }else{
457 /* get AFIO_PCF0 regiter value */
458 temp_reg = AFIO_PCF0;
459 }
460
461 temp_mask = (gpio_remap & PCF_POSITION_MASK) >> 0x10U;
462 remap1 = gpio_remap & LSB_16BIT_MASK;
463
464 /* judge pin remap type */
465 if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){
466 temp_reg &= PCF_SWJCFG_MASK;
467 AFIO_PCF0 &= PCF_SWJCFG_MASK;
468 }else if(PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)){
469 remap2 = ((uint32_t)0x03U) << temp_mask;
470 temp_reg &= ~remap2;
471 temp_reg |= ~PCF_SWJCFG_MASK;
472 }else{
473 temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U)*0x10U));
474 temp_reg |= ~PCF_SWJCFG_MASK;
475 }
476
477 /* set pin remap value */
478 if(DISABLE != newvalue){
479 temp_reg |= (remap1 << ((gpio_remap >> 0x15U)*0x10U));
480 }
481
482 if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){
483 /* set AFIO_PCF1 regiter value */
484 AFIO_PCF1 = temp_reg;
485 }else{
486 /* set AFIO_PCF0 regiter value */
487 AFIO_PCF0 = temp_reg;
488 }
489 }
AFIO_PCF1_FIELDS
#define AFIO_PCF1_FIELDS
Definition: gd32f10x_gpio.c:21
AFIO_PCF1
#define AFIO_PCF1
Definition: gd32f10x_gpio.h:48
LSB_16BIT_MASK
#define LSB_16BIT_MASK
Definition: gd32f10x_gpio.c:16
PCF_SWJCFG_MASK
#define PCF_SWJCFG_MASK
Definition: gd32f10x_gpio.c:18
PCF_LOCATION1_MASK
#define PCF_LOCATION1_MASK
Definition: gd32f10x_gpio.c:19
PCF_LOCATION2_MASK
#define PCF_LOCATION2_MASK
Definition: gd32f10x_gpio.c:20
AFIO_PCF0
#define AFIO_PCF0
Definition: gd32f10x_gpio.h:43
PCF_POSITION_MASK
#define PCF_POSITION_MASK
Definition: gd32f10x_gpio.c:17
void gpio_port_write | ( | uint32_t | gpio_periph,
 |  | uint16_t | data
 | ) |  |

write data to the specified GPIO port

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | data | specify the value to be written to the port output data register
[out] | none
Return values
none

Definition at line 219 of file gd32f10x_gpio.c.

220 {
221 GPIO_OCTL(gpio_periph) = (uint32_t)data;
222 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f10x_gpio.h:36
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_i2c.h File Reference

definitions for the I2C More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | I2C0 I2C_BASE
#define | I2C1 (I2C_BASE+0x400U)
#define | I2C_CTL0(i2cx) REG32((i2cx) + 0x00U)
#define | I2C_CTL1(i2cx) REG32((i2cx) + 0x04U)
#define | I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U)
#define | I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU)
#define | I2C_DATA(i2cx) REG32((i2cx) + 0x10U)
#define | I2C_STAT0(i2cx) REG32((i2cx) + 0x14U)
#define | I2C_STAT1(i2cx) REG32((i2cx) + 0x18U)
#define | I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU)
#define | I2C_RT(i2cx) REG32((i2cx) + 0x20U)
#define | I2C_CTL0_I2CEN BIT(0)
#define | I2C_CTL0_SMBEN BIT(1)
#define | I2C_CTL0_SMBSEL BIT(3)
#define | I2C_CTL0_ARPEN BIT(4)
#define | I2C_CTL0_PECEN BIT(5)
#define | I2C_CTL0_GCEN BIT(6)
#define | I2C_CTL0_DISSTRC BIT(7)
#define | I2C_CTL0_START BIT(8)
#define | I2C_CTL0_STOP BIT(9)
#define | I2C_CTL0_ACKEN BIT(10)
#define | I2C_CTL0_POAP BIT(11)
#define | I2C_CTL0_PECTRANS BIT(12)
#define | I2C_CTL0_SALT BIT(13)
#define | I2C_CTL0_SRESET BIT(15)
#define | I2C_CTL1_I2CCLK BITS(0,5)
#define | I2C_CTL1_ERRIE BIT(8)
#define | I2C_CTL1_EVIE BIT(9)
#define | I2C_CTL1_BUFIE BIT(10)
#define | I2C_CTL1_DMAON BIT(11)
#define | I2C_CTL1_DMALST BIT(12)
#define | I2C_SADDR0_ADDRESS0 BIT(0)
#define | I2C_SADDR0_ADDRESS BITS(1,7)
#define | I2C_SADDR0_ADDRESS_H BITS(8,9)
#define | I2C_SADDR0_ADDFORMAT BIT(15)
#define | I2C_SADDR1_DUADEN BIT(0)
#define | I2C_SADDR1_ADDRESS2 BITS(1,7)
#define | I2C_DATA_TRB BITS(0,7)
#define | I2C_STAT0_SBSEND BIT(0)
#define | I2C_STAT0_ADDSEND BIT(1)
#define | I2C_STAT0_BTC BIT(2)
#define | I2C_STAT0_ADD10SEND BIT(3)
#define | I2C_STAT0_STPDET BIT(4)
#define | I2C_STAT0_RBNE BIT(6)
#define | I2C_STAT0_TBE BIT(7)
#define | I2C_STAT0_BERR BIT(8)
#define | I2C_STAT0_LOSTARB BIT(9)
#define | I2C_STAT0_AERR BIT(10)
#define | I2C_STAT0_OUERR BIT(11)
#define | I2C_STAT0_PECERR BIT(12)
#define | I2C_STAT0_SMBTO BIT(14)
#define | I2C_STAT0_SMBALT BIT(15)
#define | I2C_STAT1_MASTER BIT(0)
#define | I2C_STAT1_I2CBSY BIT(1)
#define | I2C_STAT1_TRS BIT(2)
#define | I2C_STAT1_RXGC BIT(4)
#define | I2C_STAT1_DEFSMB BIT(5)
#define | I2C_STAT1_HSTSMB BIT(6)
#define | I2C_STAT1_DUMODF BIT(7)
#define | I2C_STAT1_ECV BITS(8,15)
#define | I2C_CKCFG_CLKC BITS(0,11)
#define | I2C_CKCFG_DTCY BIT(14)
#define | I2C_CKCFG_FAST BIT(15)
#define | I2C_RT_RISETIME BITS(0,5)
#define | I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U)
#define | I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN
#define | I2C_SMBUS_DEVICE ((uint32_t)0x00000000U)
#define | I2C_SMBUS_HOST I2C_CTL0_SMBSEL
#define | I2C_RECEIVER ((uint32_t)0x00000001U)
#define | I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU)
#define | I2C_ACK_DISABLE ((uint32_t)0x00000000U)
#define | I2C_ACK_ENABLE ((uint32_t)0x00000001U)
#define | I2C_ACKPOS_NEXT ((uint32_t)0x00000000U)
#define | I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U)
#define | I2C_DUADEN_DISABLE ((uint32_t)0x00000000U)
#define | I2C_DUADEN_ENABLE ((uint32_t)0x00000001U)
#define | I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U)
#define | I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC
#define | I2C_GCEN_ENABLE I2C_CTL0_GCEN
#define | I2C_GCEN_DISABLE ((uint32_t)0x00000000U)
#define | I2C_SRESET_SET I2C_CTL0_SRESET
#define | I2C_SRESET_RESET ((uint32_t)0x00000000U)
#define | I2C_DMA_ON I2C_CTL1_DMAON
#define | I2C_DMA_OFF ((uint32_t)0x00000000U)
#define | I2C_DMALST_ON I2C_CTL1_DMALST
#define | I2C_DMALST_OFF ((uint32_t)0x00000000U)
#define | I2C_PEC_ENABLE I2C_CTL0_PECEN
#define | I2C_PEC_DISABLE ((uint32_t)0x00000000U)
#define | I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS
#define | I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U)
#define | I2C_SALTSEND_ENABLE I2C_CTL0_SALT
#define | I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U)
#define | I2C_ARP_ENABLE I2C_CTL0_ARPEN
#define | I2C_ARP_DISABLE ((uint32_t)0x00000000U)
#define | DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
#define | DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
#define | I2C_FLAG_SBSEND BIT(0)
#define | I2C_FLAG_ADDSEND BIT(1)
#define | I2C_FLAG_BTC BIT(2)
#define | I2C_FLAG_ADD10SEND BIT(3)
#define | I2C_FLAG_STPDET BIT(4)
#define | I2C_FLAG_RBNE BIT(6)
#define | I2C_FLAG_TBE BIT(7)
#define | I2C_FLAG_BERR BIT(8)
#define | I2C_FLAG_LOSTARB BIT(9)
#define | I2C_FLAG_AERR BIT(10)
#define | I2C_FLAG_OUERR BIT(11)
#define | I2C_FLAG_PECERR BIT(12)
#define | I2C_FLAG_SMBTO BIT(14)
#define | I2C_FLAG_SMBALT BIT(15)
#define | I2C_FLAG_MASTER (BIT(0)|BIT(31))
#define | I2C_FLAG_I2CBSY (BIT(1)|BIT(31))
#define | I2C_FLAG_TRS (BIT(2)|BIT(31))
#define | I2C_FLAG_RXGC (BIT(4)|BIT(31))
#define | I2C_FLAG_DEFSMB (BIT(5)|BIT(31))
#define | I2C_FLAG_HSTSMB (BIT(6)|BIT(31))
#define | I2C_FLAG_DUMOD (BIT(7)|BIT(31))
#define | I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND
#define | I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND
#define | I2C_INT_FLAG_BTC I2C_FLAG_BTC
#define | I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND
#define | I2C_INT_FLAG_STPDET I2C_FLAG_STPDET
#define | I2C_INT_FLAG_RBNE I2C_FLAG_RBNE
#define | I2C_INT_FLAG_TBE I2C_FLAG_TBE
#define | I2C_INT_FLAG_BERR I2C_FLAG_BERR
#define | I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB
#define | I2C_INT_FLAG_AERR I2C_FLAG_AERR
#define | I2C_INT_FLAG_OUERR I2C_FLAG_OUERR
#define | I2C_INT_FLAG_PECERR I2C_FLAG_PECERR
#define | I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO
#define | I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT
#define | I2C_INT_ERR I2C_CTL1_ERRIE
#define | I2C_INT_EV I2C_CTL1_EVIE
#define | I2C_INT_BUF I2C_CTL1_BUFIE
#define | CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14))
#define | I2C_DTCY_2 CKCFG_DTCY(0)
#define | I2C_DTCY_16_9 CKCFG_DTCY(1)
#define | SADDR0_ADDFORMAT(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define | I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0)
#define | I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1)

Functions

void | i2c_deinit (uint32_t i2c_periph)
reset I2C More...
void | i2c_clock_config (uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
I2C clock configure. More...
void | i2c_mode_addr_config (uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
configure I2C address More...
void | i2c_smbus_type_config (uint32_t i2c_periph, uint32_t type)
SMBus type selection. More...
void | i2c_ack_config (uint32_t i2c_periph, uint32_t ack)
whether or not to send an ACK More...
void | i2c_ackpos_config (uint32_t i2c_periph, uint32_t pos)
I2C POAP position configure. More...
void | i2c_master_addressing (uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
master send slave address More...
void | i2c_dualaddr_enable (uint32_t i2c_periph, uint32_t dualaddr)
dual-address mode switch More...
void | i2c_enable (uint32_t i2c_periph)
enable I2C More...
void | i2c_disable (uint32_t i2c_periph)
disable I2C More...
void | i2c_start_on_bus (uint32_t i2c_periph)
generate a START condition on I2C bus More...
void | i2c_stop_on_bus (uint32_t i2c_periph)
generate a STOP condition on I2C bus More...
void | i2c_data_transmit (uint32_t i2c_periph, uint8_t data)
I2C transmit data function. More...
uint8_t | i2c_data_receive (uint32_t i2c_periph)
I2C receive data function. More...
void | i2c_dma_enable (uint32_t i2c_periph, uint32_t dmastate)
enable I2C DMA mode More...
void | i2c_dma_last_transfer_enable (uint32_t i2c_periph, uint32_t dmalast)
flag indicating DMA last transfer More...
void | i2c_stretch_scl_low_config (uint32_t i2c_periph, uint32_t stretchpara)
whether to stretch SCL low when data is not ready in slave mode More...
void | i2c_slave_response_to_gcall_config (uint32_t i2c_periph, uint32_t gcallpara)
whether or not to response to a general call More...
void | i2c_software_reset_config (uint32_t i2c_periph, uint32_t sreset)
software reset I2C More...
FlagStatus | i2c_flag_get (uint32_t i2c_periph, uint32_t flag)
check I2C flag is set or not More...
void | i2c_flag_clear (uint32_t i2c_periph, uint32_t flag)
clear I2C flag More...
void | i2c_interrupt_enable (uint32_t i2c_periph, uint32_t inttype)
enable I2C interrupt More...
void | i2c_interrupt_disable (uint32_t i2c_periph, uint32_t inttype)
disable I2C interrupt More...
FlagStatus | i2c_interrupt_flag_get (uint32_t i2c_periph, uint32_t intflag)
check I2C interrupt flag More...
void | i2c_interrupt_flag_clear (uint32_t i2c_periph, uint32_t intflag)
clear I2C interrupt flag More...
void | i2c_pec_enable (uint32_t i2c_periph, uint32_t pecstate)
I2C PEC calculation on or off. More...
void | i2c_pec_transfer_enable (uint32_t i2c_periph, uint32_t pecpara)
I2C whether to transfer PEC value. More...
uint8_t | i2c_pec_value_get (uint32_t i2c_periph)
get packet error checking value More...
void | i2c_smbus_issue_alert (uint32_t i2c_periph, uint32_t smbuspara)
I2C issue alert through SMBA pin. More...
void | i2c_smbus_arp_enable (uint32_t i2c_periph, uint32_t arpstate)
enable or disable I2C ARP protocol in SMBus switch More...

Detailed Description

definitions for the I2C

Definition in file gd32f10x_i2c.h.

Macro Definition Documentation

#define CKCFG_DTCY ( regval ) (BIT(14) & ((uint32_t)(regval) << 14))

Definition at line 218 of file gd32f10x_i2c.h.

#define DATA_RECV ( regval ) GET_BITS((uint32_t)(regval), 0, 7)

Definition at line 171 of file gd32f10x_i2c.h.

#define DATA_TRANS ( regval ) (BITS(0,7) & ((uint32_t)(regval) << 0))

Definition at line 168 of file gd32f10x_i2c.h.

#define I2C0 I2C_BASE

Definition at line 19 of file gd32f10x_i2c.h.

#define I2C1 (I2C_BASE+0x400U)

Definition at line 20 of file gd32f10x_i2c.h.

#define I2C_ACK_DISABLE ((uint32_t)0x00000000U)

ACK will be not sent

Definition at line 118 of file gd32f10x_i2c.h.

#define I2C_ACK_ENABLE ((uint32_t)0x00000001U)

ACK will be sent

Definition at line 119 of file gd32f10x_i2c.h.

#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U)

ACKEN bit decides whether or not to send ACK or not for the current byte

Definition at line 123 of file gd32f10x_i2c.h.

#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U)

ACKEN bit decides whether or not to send ACK for the next byte

Definition at line 122 of file gd32f10x_i2c.h.

#define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1)

address:10 bits

Definition at line 225 of file gd32f10x_i2c.h.

#define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0)

address:7 bits

Definition at line 224 of file gd32f10x_i2c.h.

#define I2C_ARP_DISABLE ((uint32_t)0x00000000U)

ARP is disabled

Definition at line 165 of file gd32f10x_i2c.h.

#define I2C_ARP_ENABLE I2C_CTL0_ARPEN

ARP is enabled

Definition at line 164 of file gd32f10x_i2c.h.

#define I2C_CKCFG ( i2cx ) REG32((i2cx) + 0x1CU)

I2C clock configure register

Definition at line 30 of file gd32f10x_i2c.h.

#define I2C_CKCFG_CLKC BITS(0,11)

clock control register in fast/standard mode (master mode)

Definition at line 98 of file gd32f10x_i2c.h.

#define I2C_CKCFG_DTCY BIT(14)

fast mode duty cycle

Definition at line 99 of file gd32f10x_i2c.h.

#define I2C_CKCFG_FAST BIT(15)

I2C speed selection in master mode

Definition at line 100 of file gd32f10x_i2c.h.

#define I2C_CTL0 ( i2cx ) REG32((i2cx) + 0x00U)

I2C control register 0

Definition at line 23 of file gd32f10x_i2c.h.

#define I2C_CTL0_ACKEN BIT(10)

acknowledge enable

Definition at line 44 of file gd32f10x_i2c.h.

#define I2C_CTL0_ARPEN BIT(4)

ARP enable

Definition at line 38 of file gd32f10x_i2c.h.

#define I2C_CTL0_DISSTRC BIT(7)

clock stretching disable (slave mode)

Definition at line 41 of file gd32f10x_i2c.h.

#define I2C_CTL0_GCEN BIT(6)

general call enable

Definition at line 40 of file gd32f10x_i2c.h.

#define I2C_CTL0_I2CEN BIT(0)

peripheral enable

Definition at line 35 of file gd32f10x_i2c.h.

#define I2C_CTL0_PECEN BIT(5)

PEC enable

Definition at line 39 of file gd32f10x_i2c.h.

#define I2C_CTL0_PECTRANS BIT(12)

packet error checking

Definition at line 46 of file gd32f10x_i2c.h.

#define I2C_CTL0_POAP BIT(11)

acknowledge/PEC position (for data reception)

Definition at line 45 of file gd32f10x_i2c.h.

#define I2C_CTL0_SALT BIT(13)

SMBus alert

Definition at line 47 of file gd32f10x_i2c.h.

#define I2C_CTL0_SMBEN BIT(1)

SMBus mode

Definition at line 36 of file gd32f10x_i2c.h.

#define I2C_CTL0_SMBSEL BIT(3)

SMBus type

Definition at line 37 of file gd32f10x_i2c.h.

#define I2C_CTL0_SRESET BIT(15)

software reset

Definition at line 48 of file gd32f10x_i2c.h.

#define I2C_CTL0_START BIT(8)

start generation

Definition at line 42 of file gd32f10x_i2c.h.

#define I2C_CTL0_STOP BIT(9)

stop generation

Definition at line 43 of file gd32f10x_i2c.h.

#define I2C_CTL1 ( i2cx ) REG32((i2cx) + 0x04U)

I2C control register 1

Definition at line 24 of file gd32f10x_i2c.h.

#define I2C_CTL1_BUFIE BIT(10)

buffer interrupt enable

Definition at line 54 of file gd32f10x_i2c.h.

#define I2C_CTL1_DMALST BIT(12)

DMA last transfer

Definition at line 56 of file gd32f10x_i2c.h.

#define I2C_CTL1_DMAON BIT(11)

DMA requests enable

Definition at line 55 of file gd32f10x_i2c.h.

#define I2C_CTL1_ERRIE BIT(8)

error interrupt enable

Definition at line 52 of file gd32f10x_i2c.h.

#define I2C_CTL1_EVIE BIT(9)

event interrupt enable

Definition at line 53 of file gd32f10x_i2c.h.

#define I2C_CTL1_I2CCLK BITS(0,5)

I2CCLK[5:0] bits (peripheral clock frequency)

Definition at line 51 of file gd32f10x_i2c.h.

#define I2C_DATA ( i2cx ) REG32((i2cx) + 0x10U)

I2C transfer buffer register

Definition at line 27 of file gd32f10x_i2c.h.

#define I2C_DATA_TRB BITS(0,7)

8-bit data register

Definition at line 69 of file gd32f10x_i2c.h.

#define I2C_DMA_OFF ((uint32_t)0x00000000U)

DMA mode disabled

Definition at line 145 of file gd32f10x_i2c.h.

#define I2C_DMA_ON I2C_CTL1_DMAON

DMA mode enabled

Definition at line 144 of file gd32f10x_i2c.h.

#define I2C_DMALST_OFF ((uint32_t)0x00000000U)

next DMA EOT is not the last transfer

Definition at line 148 of file gd32f10x_i2c.h.

#define I2C_DMALST_ON I2C_CTL1_DMALST

next DMA EOT is the last transfer

Definition at line 147 of file gd32f10x_i2c.h.

#define I2C_DTCY_16_9 CKCFG_DTCY(1)

I2C fast mode Tlow/Thigh = 16/9

Definition at line 220 of file gd32f10x_i2c.h.

#define I2C_DTCY_2 CKCFG_DTCY(0)

I2C fast mode Tlow/Thigh = 2

Definition at line 219 of file gd32f10x_i2c.h.

#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U)

dual-address mode disabled

Definition at line 126 of file gd32f10x_i2c.h.

#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U)

dual-address mode enabled

Definition at line 127 of file gd32f10x_i2c.h.

#define I2C_FLAG_ADD10SEND BIT(3)

header of 10-bit address is sent in master mode

Definition at line 177 of file gd32f10x_i2c.h.

#define I2C_FLAG_ADDSEND BIT(1)

address is sent in master mode or received and matches in slave mode

Definition at line 175 of file gd32f10x_i2c.h.

#define I2C_FLAG_AERR BIT(10)

acknowledge error

Definition at line 183 of file gd32f10x_i2c.h.

#define I2C_FLAG_BERR BIT(8)

a bus error occurs indication a unexpected start or stop condition on I2C bus

Definition at line 181 of file gd32f10x_i2c.h.

#define I2C_FLAG_BTC BIT(2)

byte transmission finishes

Definition at line 176 of file gd32f10x_i2c.h.

#define I2C_FLAG_DEFSMB (BIT(5)|BIT(31))

default address of SMBus device

Definition at line 192 of file gd32f10x_i2c.h.

#define I2C_FLAG_DUMOD (BIT(7)|BIT(31))

dual flag in slave mode indicating which address is matched in dual-address mode

Definition at line 194 of file gd32f10x_i2c.h.

#define I2C_FLAG_HSTSMB (BIT(6)|BIT(31))

SMBus host header detected in slave mode

Definition at line 193 of file gd32f10x_i2c.h.

#define I2C_FLAG_I2CBSY (BIT(1)|BIT(31))

busy flag

Definition at line 189 of file gd32f10x_i2c.h.

#define I2C_FLAG_LOSTARB BIT(9)

arbitration lost in master mode

Definition at line 182 of file gd32f10x_i2c.h.

#define I2C_FLAG_MASTER (BIT(0)|BIT(31))

a flag indicating whether I2C block is in master or slave mode

Definition at line 188 of file gd32f10x_i2c.h.

#define I2C_FLAG_OUERR BIT(11)

over-run or under-run situation occurs in slave mode

Definition at line 184 of file gd32f10x_i2c.h.

#define I2C_FLAG_PECERR BIT(12)

PEC error when receiving data

Definition at line 185 of file gd32f10x_i2c.h.

#define I2C_FLAG_RBNE BIT(6)

I2C_DATA is not Empty during receiving

Definition at line 179 of file gd32f10x_i2c.h.

#define I2C_FLAG_RXGC (BIT(4)|BIT(31))

general call address (00h) received

Definition at line 191 of file gd32f10x_i2c.h.

#define I2C_FLAG_SBSEND BIT(0)

start condition sent out in master mode

Definition at line 174 of file gd32f10x_i2c.h.

#define I2C_FLAG_SMBALT BIT(15)

SMBus alert status

Definition at line 187 of file gd32f10x_i2c.h.

#define I2C_FLAG_SMBTO BIT(14)

timeout signal in SMBus mode

Definition at line 186 of file gd32f10x_i2c.h.

#define I2C_FLAG_STPDET BIT(4)

stop condition detected in slave mode

Definition at line 178 of file gd32f10x_i2c.h.

#define I2C_FLAG_TBE BIT(7)

I2C_DATA is empty during transmitting

Definition at line 180 of file gd32f10x_i2c.h.

#define I2C_FLAG_TRS (BIT(2)|BIT(31))

whether the I2C is a transmitter or a receiver

Definition at line 190 of file gd32f10x_i2c.h.

#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U)

slave will not response to a general call

Definition at line 136 of file gd32f10x_i2c.h.

#define I2C_GCEN_ENABLE I2C_CTL0_GCEN

slave will response to a general call

Definition at line 135 of file gd32f10x_i2c.h.

#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U)

I2C mode

Definition at line 107 of file gd32f10x_i2c.h.

#define I2C_INT_BUF I2C_CTL1_BUFIE

buffer interrupt enable

Definition at line 215 of file gd32f10x_i2c.h.

#define I2C_INT_ERR I2C_CTL1_ERRIE

error interrupt enable

Definition at line 213 of file gd32f10x_i2c.h.

#define I2C_INT_EV I2C_CTL1_EVIE

event interrupt enable

Definition at line 214 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND

header of 10-bit address is sent in master mode interrupt flag

Definition at line 200 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND

address is sent in master mode or received and matches in slave mode interrupt flag

Definition at line 198 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_AERR I2C_FLAG_AERR

acknowledge error interrupt flag

Definition at line 206 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_BERR I2C_FLAG_BERR

a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag

Definition at line 204 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_BTC I2C_FLAG_BTC

byte transmission finishes

Definition at line 199 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB

arbitration lost in master mode interrupt flag

Definition at line 205 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_OUERR I2C_FLAG_OUERR

over-run or under-run situation occurs in slave mode interrupt flag

Definition at line 207 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_PECERR I2C_FLAG_PECERR

PEC error when receiving data interrupt flag

Definition at line 208 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_RBNE I2C_FLAG_RBNE

I2C_DATA is not Empty during receiving interrupt flag

Definition at line 202 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND

start condition sent out in master mode interrupt flag

Definition at line 197 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT

SMBus Alert status interrupt flag

Definition at line 210 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO

timeout signal in SMBus mode interrupt flag

Definition at line 209 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_STPDET I2C_FLAG_STPDET

stop condition detected in slave mode interrupt flag

Definition at line 201 of file gd32f10x_i2c.h.

#define I2C_INT_FLAG_TBE I2C_FLAG_TBE

I2C_DATA is empty during transmitting interrupt flag

Definition at line 203 of file gd32f10x_i2c.h.

#define I2C_PEC_DISABLE ((uint32_t)0x00000000U)

PEC calculation off

Definition at line 153 of file gd32f10x_i2c.h.

#define I2C_PEC_ENABLE I2C_CTL0_PECEN

PEC calculation on

Definition at line 152 of file gd32f10x_i2c.h.

#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U)

not transfer PEC value

Definition at line 157 of file gd32f10x_i2c.h.

#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS

transfer PEC

Definition at line 156 of file gd32f10x_i2c.h.

#define I2C_RECEIVER ((uint32_t)0x00000001U)

receiver

Definition at line 114 of file gd32f10x_i2c.h.

#define I2C_RT ( i2cx ) REG32((i2cx) + 0x20U)

I2C rise time register

Definition at line 31 of file gd32f10x_i2c.h.

#define I2C_RT_RISETIME BITS(0,5)

maximum rise time in fast/standard mode (Master mode)

Definition at line 103 of file gd32f10x_i2c.h.

#define I2C_SADDR0 ( i2cx ) REG32((i2cx) + 0x08U)

I2C slave address register 0

Definition at line 25 of file gd32f10x_i2c.h.

#define I2C_SADDR0_ADDFORMAT BIT(15)

address mode for the I2C slave

Definition at line 62 of file gd32f10x_i2c.h.

#define I2C_SADDR0_ADDRESS BITS(1,7)

7-bit address or bits 7:1 of a 10-bit address

Definition at line 60 of file gd32f10x_i2c.h.

#define I2C_SADDR0_ADDRESS0 BIT(0)

bit 0 of a 10-bit address

Definition at line 59 of file gd32f10x_i2c.h.

#define I2C_SADDR0_ADDRESS_H BITS(8,9)

highest two bits of a 10-bit address

Definition at line 61 of file gd32f10x_i2c.h.

#define I2C_SADDR1 ( i2cx ) REG32((i2cx) + 0x0CU)

I2C slave address register

Definition at line 26 of file gd32f10x_i2c.h.

#define I2C_SADDR1_ADDRESS2 BITS(1,7)

second I2C address for the slave in dual-address mode

Definition at line 66 of file gd32f10x_i2c.h.

#define I2C_SADDR1_DUADEN BIT(0)

aual-address mode switch

Definition at line 65 of file gd32f10x_i2c.h.

#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U)

not issue alert through SMBA

Definition at line 162 of file gd32f10x_i2c.h.

#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT

issue alert through SMBA pin

Definition at line 161 of file gd32f10x_i2c.h.

#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC

SCL stretching is disabled

Definition at line 132 of file gd32f10x_i2c.h.

#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U)

SCL stretching is enabled

Definition at line 131 of file gd32f10x_i2c.h.

#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U)

SMBus mode device type

Definition at line 111 of file gd32f10x_i2c.h.

#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL

SMBus mode host type

Definition at line 112 of file gd32f10x_i2c.h.

#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN

SMBus mode

Definition at line 108 of file gd32f10x_i2c.h.

#define I2C_SRESET_RESET ((uint32_t)0x00000000U)

I2C is not under reset

Definition at line 140 of file gd32f10x_i2c.h.

#define I2C_SRESET_SET I2C_CTL0_SRESET

I2C is under reset

Definition at line 139 of file gd32f10x_i2c.h.

#define I2C_STAT0 ( i2cx ) REG32((i2cx) + 0x14U)

I2C transfer status register 0

Definition at line 28 of file gd32f10x_i2c.h.

#define I2C_STAT0_ADD10SEND BIT(3)

10-bit header sent (master mode)

Definition at line 75 of file gd32f10x_i2c.h.

#define I2C_STAT0_ADDSEND BIT(1)

address sent (master mode)/matched (slave mode)

Definition at line 73 of file gd32f10x_i2c.h.

#define I2C_STAT0_AERR BIT(10)

acknowledge failure

Definition at line 81 of file gd32f10x_i2c.h.

#define I2C_STAT0_BERR BIT(8)

bus error

Definition at line 79 of file gd32f10x_i2c.h.

#define I2C_STAT0_BTC BIT(2)

byte transfer finished

Definition at line 74 of file gd32f10x_i2c.h.

#define I2C_STAT0_LOSTARB BIT(9)

arbitration lost (master mode)

Definition at line 80 of file gd32f10x_i2c.h.

#define I2C_STAT0_OUERR BIT(11)

overrun/underrun

Definition at line 82 of file gd32f10x_i2c.h.

#define I2C_STAT0_PECERR BIT(12)

PEC error in reception

Definition at line 83 of file gd32f10x_i2c.h.

#define I2C_STAT0_RBNE BIT(6)

data register not empty (receivers)

Definition at line 77 of file gd32f10x_i2c.h.

#define I2C_STAT0_SBSEND BIT(0)

start bit (master mode)

Definition at line 72 of file gd32f10x_i2c.h.

#define I2C_STAT0_SMBALT BIT(15)

SMBus alert status

Definition at line 85 of file gd32f10x_i2c.h.

#define I2C_STAT0_SMBTO BIT(14)

timeout signal in SMBus mode

Definition at line 84 of file gd32f10x_i2c.h.

#define I2C_STAT0_STPDET BIT(4)

stop detection (slave mode)

Definition at line 76 of file gd32f10x_i2c.h.

#define I2C_STAT0_TBE BIT(7)

data register empty (transmitters)

Definition at line 78 of file gd32f10x_i2c.h.

#define I2C_STAT1 ( i2cx ) REG32((i2cx) + 0x18U)

I2C transfer status register

Definition at line 29 of file gd32f10x_i2c.h.

#define I2C_STAT1_DEFSMB BIT(5)

SMBus device default address (slave mode)

Definition at line 92 of file gd32f10x_i2c.h.

#define I2C_STAT1_DUMODF BIT(7)

dual flag (slave mode)

Definition at line 94 of file gd32f10x_i2c.h.

#define I2C_STAT1_ECV BITS(8,15)

packet error checking register

Definition at line 95 of file gd32f10x_i2c.h.

#define I2C_STAT1_HSTSMB BIT(6)

SMBus host header (slave mode)

Definition at line 93 of file gd32f10x_i2c.h.

#define I2C_STAT1_I2CBSY BIT(1)

bus busy

Definition at line 89 of file gd32f10x_i2c.h.

#define I2C_STAT1_MASTER BIT(0)

master/slave

Definition at line 88 of file gd32f10x_i2c.h.

#define I2C_STAT1_RXGC BIT(4)

general call address (slave mode)

Definition at line 91 of file gd32f10x_i2c.h.

#define I2C_STAT1_TRS BIT(2)

transmitter/receiver

Definition at line 90 of file gd32f10x_i2c.h.

#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU)

transmitter

Definition at line 115 of file gd32f10x_i2c.h.

#define SADDR0_ADDFORMAT ( regval ) (BIT(15) & ((uint32_t)(regval) << 15))

Definition at line 223 of file gd32f10x_i2c.h.

Function Documentation

void i2c_ack_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | ack
 | ) |  |

whether or not to send an ACK

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] ack
  • I2C_ACK_ENABLE: ACK will be sent
  • I2C_ACK_DISABLE: ACK will not be sent
[out] | none
Return values
none

Definition at line 157 of file gd32f10x_i2c.c.

158 {
159 if(I2C_ACK_ENABLE == ack){
160 I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
161 }else{
162 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
163 }
164 }
I2C_CTL0_ACKEN
#define I2C_CTL0_ACKEN
Definition: gd32f10x_i2c.h:44
I2C_ACK_ENABLE
#define I2C_ACK_ENABLE
Definition: gd32f10x_i2c.h:119
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_ackpos_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | pos
 | ) |  |

I2C POAP position configure.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] pos
  • I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
  • I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
[out] | none
Return values
none

Definition at line 175 of file gd32f10x_i2c.c.

176 {
177 /* configure I2C POAP position */
178 if(I2C_ACKPOS_NEXT == pos){
179 I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
180 }else{
181 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
182 }
183 }
I2C_ACKPOS_NEXT
#define I2C_ACKPOS_NEXT
Definition: gd32f10x_i2c.h:122
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
I2C_CTL0_POAP
#define I2C_CTL0_POAP
Definition: gd32f10x_i2c.h:45
void i2c_clock_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | clkspeed,
 |  | uint32_t | dutycyc
 | ) |  |

I2C clock configure.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] | clkspeed | i2c clock speed
[in] dutycyc duty cycle in fast mode
  • I2C_DTCY_2: T_low/T_high=2
  • I2C_DTCY_16_9: T_low/T_high=16/9
[out] | none
Return values
none

Definition at line 51 of file gd32f10x_i2c.c.

52 {
53 uint32_t pclk1,clkc,freq,risetime;
54 uint32_t temp;
55
56 pclk1 = rcu_clock_freq_get(CK_APB1);
57 /* I2C peripheral clock frequency */
58 freq = (uint32_t)(pclk1/1000000U);
59 if(freq >= I2CCLK_MAX){
60 freq = I2CCLK_MAX;
61 }
62 temp = I2C_CTL1(i2c_periph);
63 temp &= ~I2C_CTL1_I2CCLK;
64 temp |= freq;
65
66 I2C_CTL1(i2c_periph) = temp;
67
68 if(100000U >= clkspeed){
69 /* the maximum SCL rise time is 1000ns in standard mode */
70 risetime = (uint32_t)((pclk1/1000000U)+1U);
71 if(risetime >= I2CCLK_MAX){
72 I2C_RT(i2c_periph) = I2CCLK_MAX;
73 }else{
74 I2C_RT(i2c_periph) = risetime;
75 }
76 clkc = (uint32_t)(pclk1/(clkspeed*2U));
77 if(clkc < 0x04U){
78 /* the CLKC in standard mode minmum value is 4 */
79 clkc = 0x04U;
80 }
81 I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
82
83 }else if(400000U >= clkspeed){
84 /* the maximum SCL rise time is 300ns in fast mode */
85 I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
86 if(I2C_DTCY_2 == dutycyc){
87 /* I2C duty cycle is 2 */
88 clkc = (uint32_t)(pclk1/(clkspeed*3U));
89 I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
90 }else{
91 /* I2C duty cycle is 16/9 */
92 clkc = (uint32_t)(pclk1/(clkspeed*25U));
93 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
94 }
95 if(0U == (clkc & I2C_CKCFG_CLKC)){
96 /* the CLKC in fast mode minmum value is 1 */
97 clkc |= 0x0001U;
98 }
99 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
100 I2C_CKCFG(i2c_periph) |= clkc;
101 }else{
102 }
103 }
I2C_DTCY_2
#define I2C_DTCY_2
Definition: gd32f10x_i2c.h:219
I2C_CKCFG_DTCY
#define I2C_CKCFG_DTCY
Definition: gd32f10x_i2c.h:99
I2C_CKCFG_FAST
#define I2C_CKCFG_FAST
Definition: gd32f10x_i2c.h:100
I2C_CKCFG_CLKC
#define I2C_CKCFG_CLKC
Definition: gd32f10x_i2c.h:98
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
I2C_RT
#define I2C_RT(i2cx)
Definition: gd32f10x_i2c.h:31
I2C_CTL1_I2CCLK
#define I2C_CTL1_I2CCLK
Definition: gd32f10x_i2c.h:51
I2C_CKCFG
#define I2C_CKCFG(i2cx)
Definition: gd32f10x_i2c.h:30
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
I2CCLK_MAX
#define I2CCLK_MAX
Definition: gd32f10x_i2c.c:16
CK_APB1
Definition: gd32f10x_rcu.h:586
uint8_t i2c_data_receive ( uint32_t i2c_periph )

I2C receive data function.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
data of received

Definition at line 285 of file gd32f10x_i2c.c.

286 {
287 return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
288 }
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f10x_i2c.h:27
DATA_RECV
#define DATA_RECV(regval)
Definition: gd32f10x_i2c.h:171
void i2c_data_transmit | ( | uint32_t | i2c_periph,
 |  | uint8_t | data
 | ) |  |

I2C transmit data function.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] | data | data of transmission
[out] | none
Return values
none

Definition at line 274 of file gd32f10x_i2c.c.

275 {
276 I2C_DATA(i2c_periph) = DATA_TRANS(data);
277 }
DATA_TRANS
#define DATA_TRANS(regval)
Definition: gd32f10x_i2c.h:168
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f10x_i2c.h:27
void i2c_deinit ( uint32_t i2c_periph )

reset I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 25 of file gd32f10x_i2c.c.

26 {
27 switch(i2c_periph){
28 case I2C0:
29 rcu_periph_reset_enable(RCU_I2C0RST);
30 rcu_periph_reset_disable(RCU_I2C0RST);
31 break;
32 case I2C1:
33 rcu_periph_reset_enable(RCU_I2C1RST);
34 rcu_periph_reset_disable(RCU_I2C1RST);
35 break;
36 default:
37 break;
38 }
39 }
RCU_I2C0RST
Definition: gd32f10x_rcu.h:463
RCU_I2C1RST
Definition: gd32f10x_rcu.h:464
I2C1
#define I2C1
Definition: gd32f10x_i2c.h:20
I2C0
#define I2C0
Definition: gd32f10x_i2c.h:19
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void i2c_disable ( uint32_t i2c_periph )

disable I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 240 of file gd32f10x_i2c.c.

241 {
242 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
243 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f10x_i2c.h:35
void i2c_dma_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dmastate
 | ) |  |

enable I2C DMA mode

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] dmastate
  • I2C_DMA_ON: DMA mode enable
  • I2C_DMA_OFF: DMA mode disable
[out] | none
Return values
none

Definition at line 299 of file gd32f10x_i2c.c.

300 {
301 /* configure I2C DMA function */
302 uint32_t ctl = 0U;
303 ctl = I2C_CTL1(i2c_periph);
304 ctl &= ~(I2C_CTL1_DMAON);
305 ctl |= dmastate;
306 I2C_CTL1(i2c_periph) = ctl;
307 }
I2C_CTL1_DMAON
#define I2C_CTL1_DMAON
Definition: gd32f10x_i2c.h:55
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
void i2c_dma_last_transfer_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dmalast
 | ) |  |

flag indicating DMA last transfer

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] dmalast
  • I2C_DMALST_ON: next DMA EOT is the last transfer
  • I2C_DMALST_OFF: next DMA EOT is not the last transfer
[out] | none
Return values
none

Definition at line 318 of file gd32f10x_i2c.c.

319 {
320 /* configure DMA last transfer */
321 uint32_t ctl = 0U;
322 ctl = I2C_CTL1(i2c_periph);
323 ctl &= ~(I2C_CTL1_DMALST);
324 ctl |= dmalast;
325 I2C_CTL1(i2c_periph) = ctl;
326 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
I2C_CTL1_DMALST
#define I2C_CTL1_DMALST
Definition: gd32f10x_i2c.h:56
void i2c_dualaddr_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dualaddr
 | ) |  |

dual-address mode switch

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] dualaddr
  • I2C_DUADEN_DISABLE: disable dual-address mode
  • I2C_DUADEN_ENABLE: enable dual-address mode
[out] | none
Return values
none

Definition at line 214 of file gd32f10x_i2c.c.

215 {
216 if(I2C_DUADEN_ENABLE == dualaddr){
217 I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
218 }else{
219 I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
220 }
221 }
I2C_SADDR1_DUADEN
#define I2C_SADDR1_DUADEN
Definition: gd32f10x_i2c.h:65
I2C_SADDR1
#define I2C_SADDR1(i2cx)
Definition: gd32f10x_i2c.h:26
I2C_DUADEN_ENABLE
#define I2C_DUADEN_ENABLE
Definition: gd32f10x_i2c.h:127
void i2c_enable ( uint32_t i2c_periph )

enable I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 229 of file gd32f10x_i2c.c.

230 {
231 I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
232 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f10x_i2c.h:35
void i2c_flag_clear | ( | uint32_t | i2c_periph,
 |  | uint32_t | flag
 | ) |  |

clear I2C flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] flag flag type
  • I2C_FLAG_SMBALT: SMBus Alert status
  • I2C_FLAG_SMBTO: timeout signal in SMBus mode
  • I2C_FLAG_PECERR: PEC error when receiving data
  • I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
  • I2C_FLAG_AERR: acknowledge error
  • I2C_FLAG_LOSTARB: arbitration lost in master mode
  • I2C_FLAG_BERR: a bus error
  • I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
[out] | none
Return values
none

Definition at line 451 of file gd32f10x_i2c.c.

452 {
453 if(I2C_FLAG_ADDSEND == flag){
454 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
455 I2C_STAT0(i2c_periph);
456 I2C_STAT1(i2c_periph);
457 }else{
458 I2C_STAT0(i2c_periph) &= ~(flag);
459 }
460 }
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f10x_i2c.h:29
I2C_FLAG_ADDSEND
#define I2C_FLAG_ADDSEND
Definition: gd32f10x_i2c.h:175
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f10x_i2c.h:28
FlagStatus i2c_flag_get | ( | uint32_t | i2c_periph,
 |  | uint32_t | flag
 | ) |  |

check I2C flag is set or not

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] flag
  • I2C_FLAG_SBSEND: start condition send out
  • I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
  • I2C_FLAG_BTC: byte transmission finishes
  • I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
  • I2C_FLAG_STPDET: stop condition detected in slave mode
  • I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
  • I2C_FLAG_TBE: I2C_DATA is empty during transmitting
  • I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
  • I2C_FLAG_LOSTARB: arbitration lost in master mode
  • I2C_FLAG_AERR: acknowledge error
  • I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
  • I2C_FLAG_PECERR: PEC error when receiving data
  • I2C_FLAG_SMBTO: timeout signal in SMBus mode
  • I2C_FLAG_SMBALT: SMBus alert status
  • I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
  • I2C_FLAG_I2CBSY: busy flag
  • I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver
  • I2C_FLAG_RXGC: general call address (00h) received
  • I2C_FLAG_DEFSMB: default address of SMBus device
  • I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
  • I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 413 of file gd32f10x_i2c.c.

414 {
415 uint32_t reg = 0U;
416 FlagStatus reval = RESET;
417 /* get the flag in which register */
418 reg = (BIT(31) & flag);
419 if((BIT(31) == reg)){
420 if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){
421 reval = SET;
422 }else{
423 reval = RESET;
424 }
425 }else{
426 if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){
427 reval = SET;
428 }else{
429 reval = RESET;
430 }
431 }
432 /* return the flag status */
433 return reval;
434 }
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f10x_i2c.h:29
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: gd32f10x_i2c.c:17
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f10x_i2c.h:28
void i2c_interrupt_disable | ( | uint32_t | i2c_periph,
 |  | uint32_t | inttype
 | ) |  |

disable I2C interrupt

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] inttype interrupt type
  • I2C_INT_ERR: error interrupt enable
  • I2C_INT_EV: event interrupt enable
  • I2C_INT_BUF: buffer interrupt enable
[out] | none
Return values
none

Definition at line 487 of file gd32f10x_i2c.c.

488 {
489 I2C_CTL1(i2c_periph) &= ~(inttype);
490 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
void i2c_interrupt_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | inttype
 | ) |  |

enable I2C interrupt

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] inttype interrupt type
  • I2C_INT_ERR: error interrupt enable
  • I2C_INT_EV: event interrupt enable
  • I2C_INT_BUF: buffer interrupt enable
[out] | none
Return values
none

Definition at line 472 of file gd32f10x_i2c.c.

473 {
474 I2C_CTL1(i2c_periph) |= (inttype);
475 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
void i2c_interrupt_flag_clear | ( | uint32_t | i2c_periph,
 |  | uint32_t | intflag
 | ) |  |

clear I2C interrupt flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] intflag interrupt flag
  • I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
  • I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
  • I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
  • I2C_INT_FLAG_AERR: acknowledge error interrupt flag
  • I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
  • I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
  • I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
  • I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
[out] | none
Return values
none

Definition at line 569 of file gd32f10x_i2c.c.

570 {
571 if(I2C_INT_FLAG_ADDSEND == intflag){
572 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
573 I2C_STAT0(i2c_periph);
574 I2C_STAT1(i2c_periph);
575 }else{
576 I2C_STAT0(i2c_periph) &= ~(intflag);
577 }
578 }
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f10x_i2c.h:29
I2C_INT_FLAG_ADDSEND
#define I2C_INT_FLAG_ADDSEND
Definition: gd32f10x_i2c.h:198
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f10x_i2c.h:28
FlagStatus i2c_interrupt_flag_get | ( | uint32_t | i2c_periph,
 |  | uint32_t | intflag
 | ) |  |

check I2C interrupt flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] int_flag interrupt flag
  • I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
  • I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
  • I2C_INT_FLAG_BTC: byte transmission finishes
  • I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
  • I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
  • I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
  • I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
  • I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
  • I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
  • I2C_INT_FLAG_AERR: acknowledge error interrupt flag
  • I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
  • I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
  • I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
  • I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
[out] | none
Return values
none

Definition at line 513 of file gd32f10x_i2c.c.

514 {
515 uint32_t evie, errie, bufie;
516
517 evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE;
518 errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE;
519 /* check I2C event interrupt enable bit */
520 if((intflag&0x00ffU) && evie){
521 if(intflag&0x001fU){
522 /* check I2C event flags except TBE and RBNE */
523 if(intflag & I2C_STAT0(i2c_periph)){
524 return SET;
525 }else{
526 return RESET;
527 }
528 }else{
529 /* check I2C event flags TBE and RBNE */
530 bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
531 if(bufie){
532 if(intflag & I2C_STAT0(i2c_periph)){
533 return SET;
534 }else{
535 return RESET;
536 }
537 }else{
538 return RESET;
539 }
540 }
541 /* check I2C error interrupt enable bit */
542 }else if((intflag&0xff00U) && errie){
543 /* check I2C error flags */
544 if(intflag & I2C_STAT0(i2c_periph)){
545 return SET;
546 }else{
547 return RESET;
548 }
549 }else{
550 return RESET;
551 }
552 }
I2C_CTL1_ERRIE
#define I2C_CTL1_ERRIE
Definition: gd32f10x_i2c.h:52
I2C_CTL1_BUFIE
#define I2C_CTL1_BUFIE
Definition: gd32f10x_i2c.h:54
I2C_CTL1_EVIE
#define I2C_CTL1_EVIE
Definition: gd32f10x_i2c.h:53
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f10x_i2c.h:28
void i2c_master_addressing | ( | uint32_t | i2c_periph,
 |  | uint32_t | addr,
 |  | uint32_t | trandirection
 | ) |  |

master send slave address

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] | addr | slave address
[in] trandirection transmitter or receiver
  • I2C_TRANSMITTER: transmitter
  • I2C_RECEIVER: receiver
[out] | none
Return values
none

Definition at line 195 of file gd32f10x_i2c.c.

196 {
197 if(I2C_TRANSMITTER == trandirection){
198 addr = addr & I2C_TRANSMITTER;
199 }else{
200 addr = addr | I2C_RECEIVER;
201 }
202 I2C_DATA(i2c_periph) = addr;
203 }
I2C_RECEIVER
#define I2C_RECEIVER
Definition: gd32f10x_i2c.h:114
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f10x_i2c.h:27
I2C_TRANSMITTER
#define I2C_TRANSMITTER
Definition: gd32f10x_i2c.h:115
void i2c_mode_addr_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | mode,
 |  | uint32_t | addformat,
 |  | uint32_t | addr
 | ) |  |

configure I2C address

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] i2cmod
  • I2C_I2CMODE_ENABLE: I2C mode
  • I2C_SMBUSMODE_ENABLE: SMBus mode
[in] addformat 7bits or 10bits
  • I2C_ADDFORMAT_7BITS: 7bits
  • I2C_ADDFORMAT_10BITS: 10bits
[in] | addr | I2C address
[out] | none
Return values
none

Definition at line 118 of file gd32f10x_i2c.c.

119 {
120 /* SMBus/I2C mode selected */
121 uint32_t ctl = 0U;
122 ctl = I2C_CTL0(i2c_periph);
123 ctl &= ~(I2C_CTL0_SMBEN);
124 ctl |= mode;
125 I2C_CTL0(i2c_periph) = ctl;
126 /* configure address */
127 I2C_SADDR0(i2c_periph) = (addformat | addr);
128 }
I2C_CTL0_SMBEN
#define I2C_CTL0_SMBEN
Definition: gd32f10x_i2c.h:36
I2C_SADDR0
#define I2C_SADDR0(i2cx)
Definition: gd32f10x_i2c.h:25
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_pec_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | pecstate
 | ) |  |

I2C PEC calculation on or off.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] pecpara
  • I2C_PEC_ENABLE: PEC calculation on
  • I2C_PEC_DISABLE: PEC calculation off
[out] | none
Return values
none

Definition at line 589 of file gd32f10x_i2c.c.

590 {
591 /* on/off PEC calculation */
592 uint32_t ctl = 0U;
593 ctl = I2C_CTL0(i2c_periph);
594 ctl &= ~(I2C_CTL0_PECEN);
595 ctl |= pecstate;
596 I2C_CTL0(i2c_periph) = ctl;
597 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
I2C_CTL0_PECEN
#define I2C_CTL0_PECEN
Definition: gd32f10x_i2c.h:39
void i2c_pec_transfer_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | pecpara
 | ) |  |

I2C whether to transfer PEC value.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] pecpara
  • I2C_PECTRANS_ENABLE: transfer PEC
  • I2C_PECTRANS_DISABLE: not transfer PEC
[out] | none
Return values
none

Definition at line 608 of file gd32f10x_i2c.c.

609 {
610 /* whether to transfer PEC */
611 uint32_t ctl = 0U;
612 ctl = I2C_CTL0(i2c_periph);
613 ctl &= ~(I2C_CTL0_PECTRANS);
614 ctl |= pecpara;
615 I2C_CTL0(i2c_periph) = ctl;
616 }
I2C_CTL0_PECTRANS
#define I2C_CTL0_PECTRANS
Definition: gd32f10x_i2c.h:46
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
uint8_t i2c_pec_value_get ( uint32_t i2c_periph )

get packet error checking value

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
PEC value

Definition at line 624 of file gd32f10x_i2c.c.

625 {
626 return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>8);
627 }
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f10x_i2c.h:29
I2C_STAT1_ECV
#define I2C_STAT1_ECV
Definition: gd32f10x_i2c.h:95
void i2c_slave_response_to_gcall_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | gcallpara
 | ) |  |

whether or not to response to a general call

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] gcallpara
  • I2C_GCEN_ENABLE: slave will response to a general call
  • I2C_GCEN_DISABLE: slave will not response to a general call
[out] | none
Return values
none

Definition at line 356 of file gd32f10x_i2c.c.

357 {
358 /* configure slave response to a general call enable or disable */
359 uint32_t ctl = 0U;
360 ctl = I2C_CTL0(i2c_periph);
361 ctl &= ~(I2C_CTL0_GCEN);
362 ctl |= gcallpara;
363 I2C_CTL0(i2c_periph) = ctl;
364 }
I2C_CTL0_GCEN
#define I2C_CTL0_GCEN
Definition: gd32f10x_i2c.h:40
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_smbus_arp_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | arpstate
 | ) |  |

enable or disable I2C ARP protocol in SMBus switch

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] smbuspara
  • I2C_ARP_ENABLE: enable ARP
  • I2C_ARP_DISABLE: disable ARP
[out] | none
Return values
none

Definition at line 657 of file gd32f10x_i2c.c.

658 {
659 /* enable or disable I2C ARP protocol*/
660 uint32_t ctl = 0U;
661 ctl = I2C_CTL0(i2c_periph);
662 ctl &= ~(I2C_CTL0_ARPEN);
663 ctl |= arpstate;
664 I2C_CTL0(i2c_periph) = ctl;
665 }
I2C_CTL0_ARPEN
#define I2C_CTL0_ARPEN
Definition: gd32f10x_i2c.h:38
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_smbus_issue_alert | ( | uint32_t | i2c_periph,
 |  | uint32_t | smbuspara
 | ) |  |

I2C issue alert through SMBA pin.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] smbuspara
  • I2C_SALTSEND_ENABLE: issue alert through SMBA pin
  • I2C_SALTSEND_DISABLE: not issue alert through SMBA pin
[out] | none
Return values
none

Definition at line 638 of file gd32f10x_i2c.c.

639 {
640 /* issue alert through SMBA pin configure*/
641 uint32_t ctl = 0U;
642 ctl = I2C_CTL0(i2c_periph);
643 ctl &= ~(I2C_CTL0_SALT);
644 ctl |= smbuspara;
645 I2C_CTL0(i2c_periph) = ctl;
646 }
I2C_CTL0_SALT
#define I2C_CTL0_SALT
Definition: gd32f10x_i2c.h:47
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_smbus_type_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | type
 | ) |  |

SMBus type selection.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] ack
  • I2C_SMBUS_DEVICE: device
  • I2C_SMBUS_HOST: host
[out] | none
Return values
none

Definition at line 139 of file gd32f10x_i2c.c.

140 {
141 if(I2C_SMBUS_HOST == type){
142 I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
143 }else{
144 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
145 }
146 }
I2C_SMBUS_HOST
#define I2C_SMBUS_HOST
Definition: gd32f10x_i2c.h:112
I2C_CTL0_SMBSEL
#define I2C_CTL0_SMBSEL
Definition: gd32f10x_i2c.h:37
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_software_reset_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | sreset
 | ) |  |

software reset I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] sreset
  • I2C_SRESET_SET: I2C is under reset
  • I2C_SRESET_RESET: I2C is not under reset
[out] | none
Return values
none

Definition at line 375 of file gd32f10x_i2c.c.

376 {
377 /* modify CTL0 and configure software reset I2C state */
378 uint32_t ctl = 0U;
379 ctl = I2C_CTL0(i2c_periph);
380 ctl &= ~(I2C_CTL0_SRESET);
381 ctl |= sreset;
382 I2C_CTL0(i2c_periph) = ctl;
383 }
I2C_CTL0_SRESET
#define I2C_CTL0_SRESET
Definition: gd32f10x_i2c.h:48
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_start_on_bus ( uint32_t i2c_periph )

generate a START condition on I2C bus

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 251 of file gd32f10x_i2c.c.

252 {
253 I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
254 }
I2C_CTL0_START
#define I2C_CTL0_START
Definition: gd32f10x_i2c.h:42
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_stop_on_bus ( uint32_t i2c_periph )

generate a STOP condition on I2C bus

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 262 of file gd32f10x_i2c.c.

263 {
264 I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
265 }
I2C_CTL0_STOP
#define I2C_CTL0_STOP
Definition: gd32f10x_i2c.h:43
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_stretch_scl_low_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | stretchpara
 | ) |  |

whether to stretch SCL low when data is not ready in slave mode

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] stretchpara
  • I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
  • I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
[out] | none
Return values
none

Definition at line 337 of file gd32f10x_i2c.c.

338 {
339 /* configure I2C SCL strerching enable or disable */
340 uint32_t ctl = 0U;
341 ctl = I2C_CTL0(i2c_periph);
342 ctl &= ~(I2C_CTL0_DISSTRC);
343 ctl |= stretchpara;
344 I2C_CTL0(i2c_periph) = ctl;
345 }
I2C_CTL0_DISSTRC
#define I2C_CTL0_DISSTRC
Definition: gd32f10x_i2c.h:41
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_misc.h File Reference

definitions for the MISC More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | NVIC_VECTTAB_RAM ((uint32_t)0x20000000)
#define | NVIC_VECTTAB_FLASH ((uint32_t)0x08000000)
#define | NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)
#define | NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
#define | NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700)
#define | NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600)
#define | NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500)
#define | NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400)
#define | NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300)
#define | SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)
#define | SCB_SCR_SLEEPDEEP ((uint8_t)0x04)
#define | SCB_SCR_SEVONPEND ((uint8_t)0x10)
#define | SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
#define | SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
#define | SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)

Functions

void | nvic_priority_group_set (uint32_t nvic_prigroup)
set the priority group More...
void | nvic_irq_enable (uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority)
enable NVIC request More...
void | nvic_irq_disable (uint8_t nvic_irq)
disable NVIC request More...
void | nvic_vector_table_set (uint32_t nvic_vict_tab, uint32_t offset)
set the NVIC vector table base address More...
void | system_lowpower_set (uint8_t lowpower_mode)
set the state of the low power mode More...
void | system_lowpower_reset (uint8_t lowpower_mode)
reset the state of the low power mode More...
void | systick_clksource_set (uint32_t systick_clksource)
set the systick clock source More...

Detailed Description

definitions for the MISC

Definition in file gd32f10x_misc.h.

Macro Definition Documentation

#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)

Definition at line 27 of file gd32f10x_misc.h.

#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700)

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 30 of file gd32f10x_misc.h.

#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600)

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 31 of file gd32f10x_misc.h.

#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500)

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 32 of file gd32f10x_misc.h.

#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400)

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 33 of file gd32f10x_misc.h.

#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300)

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 34 of file gd32f10x_misc.h.

#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000)

Flash base address

Definition at line 21 of file gd32f10x_misc.h.

#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)

Definition at line 24 of file gd32f10x_misc.h.

#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000)

RAM base address

Definition at line 20 of file gd32f10x_misc.h.

#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP

Definition at line 42 of file gd32f10x_misc.h.

#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT

Definition at line 41 of file gd32f10x_misc.h.

#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND

Definition at line 43 of file gd32f10x_misc.h.

#define SCB_SCR_SEVONPEND ((uint8_t)0x10)

choose the interrupt source that can wake up the lowpower mode

Definition at line 39 of file gd32f10x_misc.h.

#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04)

choose the the system enter the DEEPSLEEP mode or SLEEP mode

Definition at line 38 of file gd32f10x_misc.h.

#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)

choose the the system whether enter low power mode by exiting from ISR

Definition at line 37 of file gd32f10x_misc.h.

#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)

systick clock source is from HCLK

Definition at line 47 of file gd32f10x_misc.h.

#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU)

systick clock source is from HCLK/8

Definition at line 46 of file gd32f10x_misc.h.

Function Documentation

void nvic_irq_disable ( uint8_t nvic_irq )

disable NVIC request

Parameters
[in] | nvic_irq | the NVIC interrupt request, detailed in IRQn_Type
[out] | none
Return values
none

Definition at line 77 of file gd32f10x_misc.c.

78 {
79 /* disable the selected IRQ.*/
80 NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
81 }
void nvic_irq_enable | ( | uint8_t | nvic_irq,
 |  | uint8_t | nvic_irq_pre_priority,
 |  | uint8_t | nvic_irq_sub_priority
 | ) |  |

enable NVIC request

Parameters
[in] | nvic_irq | the NVIC interrupt request, detailed in IRQn_Type
[in] | nvic_irq_pre_priority | the pre-emption priority needed to set
[in] | nvic_irq_sub_priority | the subpriority needed to set
[out] | none
Return values
none

Definition at line 40 of file gd32f10x_misc.c.

42 {
43 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
44 /* use the priority group value to get the temp_pre and the temp_sub */
45 if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
46 temp_pre=0U;
47 temp_sub=0x4U;
48 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
49 temp_pre=1U;
50 temp_sub=0x3U;
51 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
52 temp_pre=2U;
53 temp_sub=0x2U;
54 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
55 temp_pre=3U;
56 temp_sub=0x1U;
57 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
58 temp_pre=4U;
59 temp_sub=0x0U;
60 }else{
61 }
62 /* get the temp_priority to fill the NVIC->IP register */
63 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
64 temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
65 temp_priority = temp_priority << 0x04U;
66 NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
67 /* enable the selected IRQ */
68 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
69 }
NVIC_PRIGROUP_PRE2_SUB2
#define NVIC_PRIGROUP_PRE2_SUB2
Definition: gd32f10x_misc.h:32
NVIC_PRIGROUP_PRE3_SUB1
#define NVIC_PRIGROUP_PRE3_SUB1
Definition: gd32f10x_misc.h:33
NVIC_PRIGROUP_PRE0_SUB4
#define NVIC_PRIGROUP_PRE0_SUB4
Definition: gd32f10x_misc.h:30
NVIC_PRIGROUP_PRE1_SUB3
#define NVIC_PRIGROUP_PRE1_SUB3
Definition: gd32f10x_misc.h:31
NVIC_PRIGROUP_PRE4_SUB0
#define NVIC_PRIGROUP_PRE4_SUB0
Definition: gd32f10x_misc.h:34
void nvic_priority_group_set ( uint32_t nvic_prigroup )

set the priority group

Parameters
[in] nvic_prigroup the NVIC priority group
  • NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
  • NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
  • NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
  • NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
  • NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
[out] none
Return values
none

Definition at line 26 of file gd32f10x_misc.c.

27 {
28 /* set the priority group value */
29 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
30 }
NVIC_AIRCR_VECTKEY_MASK
#define NVIC_AIRCR_VECTKEY_MASK
Definition: gd32f10x_misc.h:27
void nvic_vector_table_set | ( | uint32_t | nvic_vict_tab,
 |  | uint32_t | offset
 | ) |  |

set the NVIC vector table base address

Parameters
[in] nvic_vict_tab the RAM or FLASH base address
  • NVIC_VECTTAB_RAM: RAM base address NVIC_VECTTAB_FLASH: Flash base address
[in] | offset | Vector Table offset
[out] | none
Return values
none

Definition at line 92 of file gd32f10x_misc.c.

93 {
94 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
95 }
NVIC_VECTTAB_OFFSET_MASK
#define NVIC_VECTTAB_OFFSET_MASK
Definition: gd32f10x_misc.h:24
void system_lowpower_reset ( uint8_t lowpower_mode )

reset the state of the low power mode

Parameters
[in] lowpower_mode the low power mode state
  • SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power mode by exiting from ISR
  • SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
  • SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be woke up by the enable interrupts
[out] none
Return values
none

Definition at line 124 of file gd32f10x_misc.c.

125 {
126 SCB->SCR &= (~(uint32_t)lowpower_mode);
127 }
void system_lowpower_set ( uint8_t lowpower_mode )

set the state of the low power mode

Parameters
[in] lowpower_mode the low power mode state
  • SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power mode by exiting from ISR
  • SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
  • SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up by all the enable and disable interrupts
[out] none
Return values
none

Definition at line 108 of file gd32f10x_misc.c.

109 {
110 SCB->SCR |= (uint32_t)lowpower_mode;
111 }
void systick_clksource_set ( uint32_t systick_clksource )

set the systick clock source

Parameters
[in] systick_clksource the systick clock source needed to choose
  • SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
  • SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
[out] none
Return values
none

Definition at line 138 of file gd32f10x_misc.c.

139 {
140 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
141 /* set the systick clock source from HCLK */
142 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
143 }else{
144 /* set the systick clock source from HCLK/8 */
145 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
146 }
147 }
SYSTICK_CLKSOURCE_HCLK_DIV8
#define SYSTICK_CLKSOURCE_HCLK_DIV8
Definition: gd32f10x_misc.h:46
SYSTICK_CLKSOURCE_HCLK
#define SYSTICK_CLKSOURCE_HCLK
Definition: gd32f10x_misc.h:47
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_pmu.h File Reference

definitions for the PMU More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | PMU PMU_BASE
#define | PMU_CTL REG32((PMU) + 0x00U)
#define | PMU_CS REG32((PMU) + 0x04U)
#define | PMU_CTL_LDOLP BIT(0)
#define | PMU_CTL_STBMOD BIT(1)
#define | PMU_CTL_WURST BIT(2)
#define | PMU_CTL_STBRST BIT(3)
#define | PMU_CTL_LVDEN BIT(4)
#define | PMU_CTL_LVDT BITS(5,7)
#define | PMU_CTL_BKPWEN BIT(8)
#define | PMU_CS_WUF BIT(0)
#define | PMU_CS_STBF BIT(1)
#define | PMU_CS_LVDF BIT(2)
#define | PMU_CS_WUPEN BIT(8)
#define | CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5))
#define | PMU_LVDT_0 CTL_LVDT(0)
#define | PMU_LVDT_1 CTL_LVDT(1)
#define | PMU_LVDT_2 CTL_LVDT(2)
#define | PMU_LVDT_3 CTL_LVDT(3)
#define | PMU_LVDT_4 CTL_LVDT(4)
#define | PMU_LVDT_5 CTL_LVDT(5)
#define | PMU_LVDT_6 CTL_LVDT(6)
#define | PMU_LVDT_7 CTL_LVDT(7)
#define | PMU_FLAG_WAKEUP PMU_CS_WUF
#define | PMU_FLAG_STANDBY PMU_CS_STBF
#define | PMU_FLAG_LVD PMU_CS_LVDF
#define | PMU_LDO_NORMAL ((uint32_t)0x00000000U)
#define | PMU_LDO_LOWPOWER PMU_CTL_LDOLP
#define | PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U)
#define | PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U)
#define | WFI_CMD ((uint8_t)0x00U)
#define | WFE_CMD ((uint8_t)0x01U)

Functions

void | pmu_deinit (void)
reset PMU register More...
void | pmu_lvd_select (uint32_t lvdt_n)
select low voltage detector threshold More...
void | pmu_lvd_disable (void)
disable PMU lvd More...
void | pmu_to_sleepmode (uint8_t sleepmodecmd)
PMU work at sleep mode. More...
void | pmu_to_deepsleepmode (uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode. More...
void | pmu_to_standbymode (uint8_t standbymodecmd)
pmu work at standby mode More...
void | pmu_wakeup_pin_enable (void)
enable wakeup pin More...
void | pmu_wakeup_pin_disable (void)
disable wakeup pin More...
void | pmu_backup_write_enable (void)
enable backup domain write More...
void | pmu_backup_write_disable (void)
disable backup domain write More...
void | pmu_flag_clear (uint32_t flag_reset)
clear flag bit More...
FlagStatus | pmu_flag_get (uint32_t flag)
get flag state More...

Detailed Description

definitions for the PMU

Definition in file gd32f10x_pmu.h.

Macro Definition Documentation

#define CTL_LVDT ( regval ) (BITS(5,7)&((uint32_t)(regval) << 5))

Definition at line 43 of file gd32f10x_pmu.h.

#define PMU PMU_BASE

PMU base address

Definition at line 19 of file gd32f10x_pmu.h.

#define PMU_CS REG32((PMU) + 0x04U)

PMU control and status register

Definition at line 23 of file gd32f10x_pmu.h.

#define PMU_CS_LVDF BIT(2)

low voltage detector status flag

Definition at line 38 of file gd32f10x_pmu.h.

#define PMU_CS_STBF BIT(1)

standby flag

Definition at line 37 of file gd32f10x_pmu.h.

#define PMU_CS_WUF BIT(0)

wakeup flag

Definition at line 36 of file gd32f10x_pmu.h.

#define PMU_CS_WUPEN BIT(8)

wakeup pin enable

Definition at line 39 of file gd32f10x_pmu.h.

#define PMU_CTL REG32((PMU) + 0x00U)

PMU control register

Definition at line 22 of file gd32f10x_pmu.h.

#define PMU_CTL_BKPWEN BIT(8)

backup domain write enable

Definition at line 33 of file gd32f10x_pmu.h.

#define PMU_CTL_LDOLP BIT(0)

LDO low power mode

Definition at line 27 of file gd32f10x_pmu.h.

#define PMU_CTL_LVDEN BIT(4)

low voltage detector enable

Definition at line 31 of file gd32f10x_pmu.h.

#define PMU_CTL_LVDT BITS(5,7)

low voltage detector threshold

Definition at line 32 of file gd32f10x_pmu.h.

#define PMU_CTL_STBMOD BIT(1)

standby mode

Definition at line 28 of file gd32f10x_pmu.h.

#define PMU_CTL_STBRST BIT(3)

standby flag reset

Definition at line 30 of file gd32f10x_pmu.h.

#define PMU_CTL_WURST BIT(2)

wakeup flag reset

Definition at line 29 of file gd32f10x_pmu.h.

#define PMU_FLAG_LVD PMU_CS_LVDF

lvd flag status

Definition at line 56 of file gd32f10x_pmu.h.

#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U)

standby flag reset

Definition at line 64 of file gd32f10x_pmu.h.

#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U)

wakeup flag reset

Definition at line 63 of file gd32f10x_pmu.h.

#define PMU_FLAG_STANDBY PMU_CS_STBF

standby flag status

Definition at line 55 of file gd32f10x_pmu.h.

#define PMU_FLAG_WAKEUP PMU_CS_WUF

wakeup flag status

Definition at line 54 of file gd32f10x_pmu.h.

#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP

LDO work at low power status when PMU enter deepsleep mode

Definition at line 60 of file gd32f10x_pmu.h.

#define PMU_LDO_NORMAL ((uint32_t)0x00000000U)

LDO normal work when PMU enter deepsleep mode

Definition at line 59 of file gd32f10x_pmu.h.

#define PMU_LVDT_0 CTL_LVDT(0)

voltage threshold is 2.2V

Definition at line 44 of file gd32f10x_pmu.h.

#define PMU_LVDT_1 CTL_LVDT(1)

voltage threshold is 2.3V

Definition at line 45 of file gd32f10x_pmu.h.

#define PMU_LVDT_2 CTL_LVDT(2)

voltage threshold is 2.4V

Definition at line 46 of file gd32f10x_pmu.h.

#define PMU_LVDT_3 CTL_LVDT(3)

voltage threshold is 2.5V

Definition at line 47 of file gd32f10x_pmu.h.

#define PMU_LVDT_4 CTL_LVDT(4)

voltage threshold is 2.6V

Definition at line 48 of file gd32f10x_pmu.h.

#define PMU_LVDT_5 CTL_LVDT(5)

voltage threshold is 2.7V

Definition at line 49 of file gd32f10x_pmu.h.

#define PMU_LVDT_6 CTL_LVDT(6)

voltage threshold is 2.8V

Definition at line 50 of file gd32f10x_pmu.h.

#define PMU_LVDT_7 CTL_LVDT(7)

voltage threshold is 2.9V

Definition at line 51 of file gd32f10x_pmu.h.

#define WFE_CMD ((uint8_t)0x01U)

use WFE command

Definition at line 68 of file gd32f10x_pmu.h.

#define WFI_CMD ((uint8_t)0x00U)

use WFI command

Definition at line 67 of file gd32f10x_pmu.h.

Function Documentation

void pmu_backup_write_disable ( void )

disable backup domain write

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 207 of file gd32f10x_pmu.c.

208 {
209 PMU_CTL &= ~PMU_CTL_BKPWEN;
210 }
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f10x_pmu.h:33
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_backup_write_enable ( void )

enable backup domain write

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 196 of file gd32f10x_pmu.c.

197 {
198 PMU_CTL |= PMU_CTL_BKPWEN;
199 }
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f10x_pmu.h:33
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_deinit ( void )

reset PMU register

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_pmu.c.

22 {
23 /* reset PMU */
24 rcu_periph_reset_enable(RCU_PMURST);
25 rcu_periph_reset_disable(RCU_PMURST);
26 }
RCU_PMURST
Definition: gd32f10x_rcu.h:473
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void pmu_flag_clear ( uint32_t flag_reset )

clear flag bit

Parameters
[in] flag_reset
  • PMU_FLAG_RESET_WAKEUP: reset wakeup flag
  • PMU_FLAG_RESET_STANDBY: reset standby flag
[out] none
Return values
none

Definition at line 156 of file gd32f10x_pmu.c.

157 {
158 switch(flag_reset){
159 case PMU_FLAG_RESET_WAKEUP:
160 /* reset wakeup flag */
161 PMU_CTL |= PMU_CTL_WURST;
162 break;
163 case PMU_FLAG_RESET_STANDBY:
164 /* reset standby flag */
165 PMU_CTL |= PMU_CTL_STBRST;
166 break;
167 default :
168 break;
169 }
170 }
PMU_FLAG_RESET_STANDBY
#define PMU_FLAG_RESET_STANDBY
Definition: gd32f10x_pmu.h:64
PMU_FLAG_RESET_WAKEUP
#define PMU_FLAG_RESET_WAKEUP
Definition: gd32f10x_pmu.h:63
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f10x_pmu.h:29
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
PMU_CTL_STBRST
#define PMU_CTL_STBRST
Definition: gd32f10x_pmu.h:30
FlagStatus pmu_flag_get ( uint32_t flag )

get flag state

Parameters
[in] flag
  • PMU_FLAG_WAKEUP: wakeup flag
  • PMU_FLAG_STANDBY: standby flag
  • PMU_FLAG_LVD: lvd flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 181 of file gd32f10x_pmu.c.

182 {
183 if(PMU_CS & flag){
184 return SET;
185 }else{
186 return RESET;
187 }
188 }
PMU_CS
#define PMU_CS
Definition: gd32f10x_pmu.h:23
void pmu_lvd_disable ( void )

disable PMU lvd

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 60 of file gd32f10x_pmu.c.

61 {
62 /* disable LVD */
63 PMU_CTL &= ~PMU_CTL_LVDEN;
64 }
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f10x_pmu.h:31
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_lvd_select ( uint32_t lvdt_n )

select low voltage detector threshold

Parameters
[in] lvdt_n
  • PMU_LVDT_0: voltage threshold is 2.2V
  • PMU_LVDT_1: voltage threshold is 2.3V
  • PMU_LVDT_2: voltage threshold is 2.4V
  • PMU_LVDT_3: voltage threshold is 2.5V
  • PMU_LVDT_4: voltage threshold is 2.6V
  • PMU_LVDT_5: voltage threshold is 2.7V
  • PMU_LVDT_6: voltage threshold is 2.8V
  • PMU_LVDT_7: voltage threshold is 2.9V
[out] none
Return values
none

Definition at line 42 of file gd32f10x_pmu.c.

43 {
44 /* disable LVD */
45 PMU_CTL &= ~PMU_CTL_LVDEN;
46 /* clear LVDT bits */
47 PMU_CTL &= ~PMU_CTL_LVDT;
48 /* set LVDT bits according to lvdt_n */
49 PMU_CTL |= lvdt_n;
50 /* enable LVD */
51 PMU_CTL |= PMU_CTL_LVDEN;
52 }
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f10x_pmu.h:31
PMU_CTL_LVDT
#define PMU_CTL_LVDT
Definition: gd32f10x_pmu.h:32
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_to_deepsleepmode | ( | uint32_t | ldo,
 |  | uint8_t | deepsleepmodecmd
 | ) |  |

PMU work at deepsleep mode.

Parameters
[in] ldo
  • PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode
  • PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
[in] deepsleepmodecmd
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 98 of file gd32f10x_pmu.c.

99 {
100 /* clear stbmod and ldolp bits */
101 PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
102
103 /* set ldolp bit according to pmu_ldo */
104 PMU_CTL |= ldo;
105
106 /* set sleepdeep bit of Cortex-M3 system control register */
107 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
108
109 /* select WFI or WFE command to enter deepsleep mode */
110 if(WFI_CMD == deepsleepmodecmd){
111 __WFI();
112 }else{
113 __SEV();
114 __WFE();
115 __WFE();
116 }
117 /* reset sleepdeep bit of Cortex-M3 system control register */
118 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
119 }
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f10x_pmu.h:28
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
PMU_CTL_LDOLP
#define PMU_CTL_LDOLP
Definition: gd32f10x_pmu.h:27
void pmu_to_sleepmode ( uint8_t sleepmodecmd )

PMU work at sleep mode.

Parameters
[in] sleepmodecmd
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 74 of file gd32f10x_pmu.c.

75 {
76 /* clear sleepdeep bit of Cortex-M3 system control register */
77 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
78
79 /* select WFI or WFE command to enter sleep mode */
80 if(WFI_CMD == sleepmodecmd){
81 __WFI();
82 }else{
83 __WFE();
84 }
85 }
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
void pmu_to_standbymode ( uint8_t standbymodecmd )

pmu work at standby mode

Parameters
[in] standbymodecmd
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 129 of file gd32f10x_pmu.c.

130 {
131 /* set sleepdeep bit of Cortex-M3 system control register */
132 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
133
134 /* set stbmod bit */
135 PMU_CTL |= PMU_CTL_STBMOD;
136
137 /* reset wakeup flag */
138 PMU_CTL |= PMU_CTL_WURST;
139
140 /* select WFI or WFE command to enter standby mode */
141 if(WFI_CMD == standbymodecmd){
142 __WFI();
143 }else{
144 __WFE();
145 }
146 }
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f10x_pmu.h:28
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f10x_pmu.h:29
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_wakeup_pin_disable ( void )

disable wakeup pin

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 229 of file gd32f10x_pmu.c.

230 {
231 PMU_CS &= ~PMU_CS_WUPEN;
232 }
PMU_CS_WUPEN
#define PMU_CS_WUPEN
Definition: gd32f10x_pmu.h:39
PMU_CS
#define PMU_CS
Definition: gd32f10x_pmu.h:23
void pmu_wakeup_pin_enable ( void )

enable wakeup pin

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 218 of file gd32f10x_pmu.c.

219 {
220 PMU_CS |= PMU_CS_WUPEN;
221 }
PMU_CS_WUPEN
#define PMU_CS_WUPEN
Definition: gd32f10x_pmu.h:39
PMU_CS
#define PMU_CS
Definition: gd32f10x_pmu.h:23
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f10x_rcu.h File Reference

definitions for the RCU More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | RCU RCU_BASE
#define | RCU_CTL REG32(RCU + 0x00U)
#define | RCU_CFG0 REG32(RCU + 0x04U)
#define | RCU_INT REG32(RCU + 0x08U)
#define | RCU_APB2RST REG32(RCU + 0x0CU)
#define | RCU_APB1RST REG32(RCU + 0x10U)
#define | RCU_AHBEN REG32(RCU + 0x14U)
#define | RCU_APB2EN REG32(RCU + 0x18U)
#define | RCU_APB1EN REG32(RCU + 0x1CU)
#define | RCU_BDCTL REG32(RCU + 0x20U)
#define | RCU_RSTSCK REG32(RCU + 0x24U)
#define | RCU_DSV REG32(RCU + 0x34U)
#define | RCU_CTL_IRC8MEN BIT(0)
#define | RCU_CTL_IRC8MSTB BIT(1)
#define | RCU_CTL_IRC8MADJ BITS(3,7)
#define | RCU_CTL_IRC8MCALIB BITS(8,15)
#define | RCU_CTL_HXTALEN BIT(16)
#define | RCU_CTL_HXTALSTB BIT(17)
#define | RCU_CTL_HXTALBPS BIT(18)
#define | RCU_CTL_CKMEN BIT(19)
#define | RCU_CTL_PLLEN BIT(24)
#define | RCU_CTL_PLLSTB BIT(25)
#define | RCU_CFG0_SCS BITS(0,1)
#define | RCU_CFG0_SCSS BITS(2,3)
#define | RCU_CFG0_AHBPSC BITS(4,7)
#define | RCU_CFG0_APB1PSC BITS(8,10)
#define | RCU_CFG0_APB2PSC BITS(11,13)
#define | RCU_CFG0_ADCPSC BITS(14,15)
#define | RCU_CFG0_PLLSEL BIT(16)
#define | RCU_CFG0_PREDV0 BIT(17)
#define | RCU_CFG0_PLLMF BITS(18,21)
#define | RCU_CFG0_USBDPSC BITS(22,23)
#define | RCU_CFG0_CKOUT0SEL BITS(24,26)
#define | RCU_CFG0_PLLMF_4 BIT(27)
#define | RCU_CFG0_ADCPSC_2 BIT(28)
#define | RCU_INT_IRC40KSTBIF BIT(0)
#define | RCU_INT_LXTALSTBIF BIT(1)
#define | RCU_INT_IRC8MSTBIF BIT(2)
#define | RCU_INT_HXTALSTBIF BIT(3)
#define | RCU_INT_PLLSTBIF BIT(4)
#define | RCU_INT_CKMIF BIT(7)
#define | RCU_INT_IRC40KSTBIE BIT(8)
#define | RCU_INT_LXTALSTBIE BIT(9)
#define | RCU_INT_IRC8MSTBIE BIT(10)
#define | RCU_INT_HXTALSTBIE BIT(11)
#define | RCU_INT_PLLSTBIE BIT(12)
#define | RCU_INT_IRC40KSTBIC BIT(16)
#define | RCU_INT_LXTALSTBIC BIT(17)
#define | RCU_INT_IRC8MSTBIC BIT(18)
#define | RCU_INT_HXTALSTBIC BIT(19)
#define | RCU_INT_PLLSTBIC BIT(20)
#define | RCU_INT_CKMIC BIT(23)
#define | RCU_APB2RST_AFRST BIT(0)
#define | RCU_APB2RST_PARST BIT(2)
#define | RCU_APB2RST_PBRST BIT(3)
#define | RCU_APB2RST_PCRST BIT(4)
#define | RCU_APB2RST_PDRST BIT(5)
#define | RCU_APB2RST_PERST BIT(6)
#define | RCU_APB2RST_PFRST BIT(7)
#define | RCU_APB2RST_PGRST BIT(8)
#define | RCU_APB2RST_ADC0RST BIT(9)
#define | RCU_APB2RST_ADC1RST BIT(10)
#define | RCU_APB2RST_TIMER0RST BIT(11)
#define | RCU_APB2RST_SPI0RST BIT(12)
#define | RCU_APB2RST_TIMER7RST BIT(13)
#define | RCU_APB2RST_USART0RST BIT(14)
#define | RCU_APB2RST_TIMER8RST BIT(19)
#define | RCU_APB2RST_TIMER9RST BIT(20)
#define | RCU_APB2RST_TIMER10RST BIT(21)
#define | RCU_APB1RST_TIMER1RST BIT(0)
#define | RCU_APB1RST_TIMER2RST BIT(1)
#define | RCU_APB1RST_TIMER3RST BIT(2)
#define | RCU_APB1RST_TIMER4RST BIT(3)
#define | RCU_APB1RST_TIMER5RST BIT(4)
#define | RCU_APB1RST_TIMER6RST BIT(5)
#define | RCU_APB1RST_TIMER11RST BIT(6)
#define | RCU_APB1RST_TIMER12RST BIT(7)
#define | RCU_APB1RST_TIMER13RST BIT(8)
#define | RCU_APB1RST_WWDGTRST BIT(11)
#define | RCU_APB1RST_SPI1RST BIT(14)
#define | RCU_APB1RST_SPI2RST BIT(15)
#define | RCU_APB1RST_USART1RST BIT(17)
#define | RCU_APB1RST_USART2RST BIT(18)
#define | RCU_APB1RST_UART3RST BIT(19)
#define | RCU_APB1RST_UART4RST BIT(20)
#define | RCU_APB1RST_I2C0RST BIT(21)
#define | RCU_APB1RST_I2C1RST BIT(22)
#define | RCU_APB1RST_USBDRST BIT(23)
#define | RCU_APB1RST_CAN0RST BIT(25)
#define | RCU_APB1RST_CAN1RST BIT(26)
#define | RCU_APB1RST_BKPIRST BIT(27)
#define | RCU_APB1RST_PMURST BIT(28)
#define | RCU_APB1RST_DACRST BIT(29)
#define | RCU_AHBEN_DMA0EN BIT(0)
#define | RCU_AHBEN_DMA1EN BIT(1)
#define | RCU_AHBEN_SRAMSPEN BIT(2)
#define | RCU_AHBEN_FMCSPEN BIT(4)
#define | RCU_AHBEN_CRCEN BIT(6)
#define | RCU_AHBEN_EXMCEN BIT(8)
#define | RCU_AHBEN_SDIOEN BIT(10)
#define | RCU_APB2EN_AFEN BIT(0)
#define | RCU_APB2EN_PAEN BIT(2)
#define | RCU_APB2EN_PBEN BIT(3)
#define | RCU_APB2EN_PCEN BIT(4)
#define | RCU_APB2EN_PDEN BIT(5)
#define | RCU_APB2EN_PEEN BIT(6)
#define | RCU_APB2EN_PFEN BIT(7)
#define | RCU_APB2EN_PGEN BIT(8)
#define | RCU_APB2EN_ADC0EN BIT(9)
#define | RCU_APB2EN_ADC1EN BIT(10)
#define | RCU_APB2EN_TIMER0EN BIT(11)
#define | RCU_APB2EN_SPI0EN BIT(12)
#define | RCU_APB2EN_TIMER7EN BIT(13)
#define | RCU_APB2EN_USART0EN BIT(14)
#define | RCU_APB2EN_TIMER8EN BIT(19)
#define | RCU_APB2EN_TIMER9EN BIT(20)
#define | RCU_APB2EN_TIMER10EN BIT(21)
#define | RCU_APB1EN_TIMER1EN BIT(0)
#define | RCU_APB1EN_TIMER2EN BIT(1)
#define | RCU_APB1EN_TIMER3EN BIT(2)
#define | RCU_APB1EN_TIMER4EN BIT(3)
#define | RCU_APB1EN_TIMER5EN BIT(4)
#define | RCU_APB1EN_TIMER6EN BIT(5)
#define | RCU_APB1EN_TIMER11EN BIT(6)
#define | RCU_APB1EN_TIMER12EN BIT(7)
#define | RCU_APB1EN_TIMER13EN BIT(8)
#define | RCU_APB1EN_WWDGTEN BIT(11)
#define | RCU_APB1EN_SPI1EN BIT(14)
#define | RCU_APB1EN_SPI2EN BIT(15)
#define | RCU_APB1EN_USART1EN BIT(17)
#define | RCU_APB1EN_USART2EN BIT(18)
#define | RCU_APB1EN_UART3EN BIT(19)
#define | RCU_APB1EN_UART4EN BIT(20)
#define | RCU_APB1EN_I2C0EN BIT(21)
#define | RCU_APB1EN_I2C1EN BIT(22)
#define | RCU_APB1EN_USBDEN BIT(23)
#define | RCU_APB1EN_CAN0EN BIT(25)
#define | RCU_APB1EN_CAN1EN BIT(26)
#define | RCU_APB1EN_BKPIEN BIT(27)
#define | RCU_APB1EN_PMUEN BIT(28)
#define | RCU_APB1EN_DACEN BIT(29)
#define | RCU_BDCTL_LXTALEN BIT(0)
#define | RCU_BDCTL_LXTALSTB BIT(1)
#define | RCU_BDCTL_LXTALBPS BIT(2)
#define | RCU_BDCTL_RTCSRC BITS(8,9)
#define | RCU_BDCTL_RTCEN BIT(15)
#define | RCU_BDCTL_BKPRST BIT(16)
#define | RCU_RSTSCK_IRC40KEN BIT(0)
#define | RCU_RSTSCK_IRC40KSTB BIT(1)
#define | RCU_RSTSCK_RSTFC BIT(24)
#define | RCU_RSTSCK_EPRSTF BIT(26)
#define | RCU_RSTSCK_PORRSTF BIT(27)
#define | RCU_RSTSCK_SWRSTF BIT(28)
#define | RCU_RSTSCK_FWDGTRSTF BIT(29)
#define | RCU_RSTSCK_WWDGTRSTF BIT(30)
#define | RCU_RSTSCK_LPRSTF BIT(31)
#define | RCU_AHBRST_USBFSRST BIT(12)
#define | RCU_AHBRST_ENETRST BIT(14)
#define | RCU_CFG1_PREDV0 BITS(0,3)
#define | RCU_CFG1_PREDV1 BITS(4,7)
#define | RCU_CFG1_PLL1MF BITS(8,11)
#define | RCU_CFG1_PLL2MF BITS(12,15)
#define | RCU_CFG1_PREDV0SEL BIT(16)
#define | RCU_CFG1_I2S1SEL BIT(17)
#define | RCU_CFG1_I2S2SEL BIT(18)
#define | RCU_DSV_DSLPVS BITS(0,2)
#define | RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define | RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))
#define | RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define | AHBEN_REG_OFFSET 0x14U
#define | APB1EN_REG_OFFSET 0x1CU
#define | APB2EN_REG_OFFSET 0x18U
#define | AHBRST_REG_OFFSET 0x28U
#define | APB1RST_REG_OFFSET 0x10U
#define | APB2RST_REG_OFFSET 0x0CU
#define | RSTSCK_REG_OFFSET 0x24U
#define | CTL_REG_OFFSET 0x00U
#define | BDCTL_REG_OFFSET 0x20U
#define | INT_REG_OFFSET 0x08U
#define | CFG0_REG_OFFSET 0x04U
#define | CFG1_REG_OFFSET 0x2CU
#define | CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define | RCU_CKSYSSRC_IRC8M CFG0_SCS(0)
#define | RCU_CKSYSSRC_HXTAL CFG0_SCS(1)
#define | RCU_CKSYSSRC_PLL CFG0_SCS(2)
#define | CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define | RCU_SCSS_IRC8M CFG0_SCSS(0)
#define | RCU_SCSS_HXTAL CFG0_SCSS(1)
#define | RCU_SCSS_PLL CFG0_SCSS(2)
#define | CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
#define | RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0)
#define | RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8)
#define | RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9)
#define | RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10)
#define | RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11)
#define | RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12)
#define | RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13)
#define | RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14)
#define | RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15)
#define | CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
#define | RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0)
#define | RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4)
#define | RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5)
#define | RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6)
#define | RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7)
#define | CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
#define | RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0)
#define | RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4)
#define | RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5)
#define | RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6)
#define | RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7)
#define | RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U)
#define | RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U)
#define | RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U)
#define | RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U)
#define | RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U)
#define | RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U)
#define | RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U)
#define | RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL
#define | PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */
#define | CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
#define | RCU_PLL_MUL2 CFG0_PLLMF(0)
#define | RCU_PLL_MUL3 CFG0_PLLMF(1)
#define | RCU_PLL_MUL4 CFG0_PLLMF(2)
#define | RCU_PLL_MUL5 CFG0_PLLMF(3)
#define | RCU_PLL_MUL6 CFG0_PLLMF(4)
#define | RCU_PLL_MUL7 CFG0_PLLMF(5)
#define | RCU_PLL_MUL8 CFG0_PLLMF(6)
#define | RCU_PLL_MUL9 CFG0_PLLMF(7)
#define | RCU_PLL_MUL10 CFG0_PLLMF(8)
#define | RCU_PLL_MUL11 CFG0_PLLMF(9)
#define | RCU_PLL_MUL12 CFG0_PLLMF(10)
#define | RCU_PLL_MUL13 CFG0_PLLMF(11)
#define | RCU_PLL_MUL14 CFG0_PLLMF(12)
#define | RCU_PLL_MUL15 CFG0_PLLMF(13)
#define | RCU_PLL_MUL16 CFG0_PLLMF(14)
#define | RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0))
#define | RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1))
#define | RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2))
#define | RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3))
#define | RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4))
#define | RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5))
#define | RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6))
#define | RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7))
#define | RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8))
#define | RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9))
#define | RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10))
#define | RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11))
#define | RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12))
#define | RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13))
#define | RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14))
#define | RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15))
#define | CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
#define | RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0)
#define | RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1)
#define | RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2)
#define | RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3)
#define | CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
#define | RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0)
#define | RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4)
#define | RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5)
#define | RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6)
#define | RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7)
#define | RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8)
#define | RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9)
#define | RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10)
#define | RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11)
#define | BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
#define | RCU_RTCSRC_NONE BDCTL_RTCSRC(0)
#define | RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1)
#define | RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2)
#define | RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3)
#define | CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define | RCU_PREDV0_DIV1 CFG1_PREDV0(0)
#define | RCU_PREDV0_DIV2 CFG1_PREDV0(1)
#define | RCU_PREDV0_DIV3 CFG1_PREDV0(2)
#define | RCU_PREDV0_DIV4 CFG1_PREDV0(3)
#define | RCU_PREDV0_DIV5 CFG1_PREDV0(4)
#define | RCU_PREDV0_DIV6 CFG1_PREDV0(5)
#define | RCU_PREDV0_DIV7 CFG1_PREDV0(6)
#define | RCU_PREDV0_DIV8 CFG1_PREDV0(7)
#define | RCU_PREDV0_DIV9 CFG1_PREDV0(8)
#define | RCU_PREDV0_DIV10 CFG1_PREDV0(9)
#define | RCU_PREDV0_DIV11 CFG1_PREDV0(10)
#define | RCU_PREDV0_DIV12 CFG1_PREDV0(11)
#define | RCU_PREDV0_DIV13 CFG1_PREDV0(12)
#define | RCU_PREDV0_DIV14 CFG1_PREDV0(13)
#define | RCU_PREDV0_DIV15 CFG1_PREDV0(14)
#define | RCU_PREDV0_DIV16 CFG1_PREDV0(15)
#define | CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
#define | RCU_PREDV1_DIV1 CFG1_PREDV1(0)
#define | RCU_PREDV1_DIV2 CFG1_PREDV1(1)
#define | RCU_PREDV1_DIV3 CFG1_PREDV1(2)
#define | RCU_PREDV1_DIV4 CFG1_PREDV1(3)
#define | RCU_PREDV1_DIV5 CFG1_PREDV1(4)
#define | RCU_PREDV1_DIV6 CFG1_PREDV1(5)
#define | RCU_PREDV1_DIV7 CFG1_PREDV1(6)
#define | RCU_PREDV1_DIV8 CFG1_PREDV1(7)
#define | RCU_PREDV1_DIV9 CFG1_PREDV1(8)
#define | RCU_PREDV1_DIV10 CFG1_PREDV1(9)
#define | RCU_PREDV1_DIV11 CFG1_PREDV1(10)
#define | RCU_PREDV1_DIV12 CFG1_PREDV1(11)
#define | RCU_PREDV1_DIV13 CFG1_PREDV1(12)
#define | RCU_PREDV1_DIV14 CFG1_PREDV1(13)
#define | RCU_PREDV1_DIV15 CFG1_PREDV1(14)
#define | RCU_PREDV1_DIV16 CFG1_PREDV1(15)
#define | CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
#define | RCU_PLL1_MUL8 CFG1_PLL1MF(6)
#define | RCU_PLL1_MUL9 CFG1_PLL1MF(7)
#define | RCU_PLL1_MUL10 CFG1_PLL1MF(8)
#define | RCU_PLL1_MUL11 CFG1_PLL1MF(9)
#define | RCU_PLL1_MUL12 CFG1_PLL1MF(10)
#define | RCU_PLL1_MUL13 CFG1_PLL1MF(11)
#define | RCU_PLL1_MUL14 CFG1_PLL1MF(12)
#define | RCU_PLL1_MUL15 CFG1_PLL1MF(13)
#define | RCU_PLL1_MUL16 CFG1_PLL1MF(14)
#define | RCU_PLL1_MUL20 CFG1_PLL1MF(15)
#define | CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12))
#define | RCU_PLL2_MUL8 CFG1_PLL2MF(6)
#define | RCU_PLL2_MUL9 CFG1_PLL2MF(7)
#define | RCU_PLL2_MUL10 CFG1_PLL2MF(8)
#define | RCU_PLL2_MUL11 CFG1_PLL2MF(9)
#define | RCU_PLL2_MUL12 CFG1_PLL2MF(10)
#define | RCU_PLL2_MUL13 CFG1_PLL2MF(11)
#define | RCU_PLL2_MUL14 CFG1_PLL2MF(12)
#define | RCU_PLL2_MUL15 CFG1_PLL2MF(13)
#define | RCU_PLL2_MUL16 CFG1_PLL2MF(14)
#define | RCU_PLL2_MUL20 CFG1_PLL2MF(15)
#define | RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U)
#define | RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL
#define | RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U)
#define | RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL
#define | RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U)
#define | RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL
#define | DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define | RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0)
#define | RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1)
#define | RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2)
#define | RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3)

Enumerations

enum rcu_periph_enum {
RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U),
RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U),
RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U),
RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U),
RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U),
RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U),
RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U),
RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U),
RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U),
RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U),
RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U),
RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U)
}
enum | rcu_periph_sleep_enum { RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U) }
enum rcu_periph_reset_enum {
RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U),
RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U),
RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U),
RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U),
RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U),
RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U),
RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U),
RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U),
RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U),
RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U),
RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U)
}
enum rcu_flag_enum {
RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U),
RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U),
RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U),
RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U)
}
enum rcu_int_flag_enum {
RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U),
RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U)
}
enum rcu_int_flag_clear_enum {
RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U),
RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U)
}
enum rcu_int_enum {
RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U),
RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U)
}
enum rcu_osci_type_enum {
RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U),
RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U)
}
enum | rcu_clock_freq_enum { CK_SYS = 0, CK_AHB, CK_APB1, CK_APB2 }

Functions

void | rcu_deinit (void)
deinitialize the RCU More...
void | rcu_periph_clock_enable (rcu_periph_enum periph)
enable the peripherals clock More...
void | rcu_periph_clock_disable (rcu_periph_enum periph)
disable the peripherals clock More...
void | rcu_periph_clock_sleep_enable (rcu_periph_sleep_enum periph)
enable the peripherals clock when sleep mode More...
void | rcu_periph_clock_sleep_disable (rcu_periph_sleep_enum periph)
disable the peripherals clock when sleep mode More...
void | rcu_periph_reset_enable (rcu_periph_reset_enum periph_reset)
reset the peripherals More...
void | rcu_periph_reset_disable (rcu_periph_reset_enum periph_reset)
disable reset the peripheral More...
void | rcu_bkp_reset_enable (void)
reset the BKP domain More...
void | rcu_bkp_reset_disable (void)
disable the BKP domain reset More...
void | rcu_system_clock_source_config (uint32_t ck_sys)
configure the system clock source More...
uint32_t | rcu_system_clock_source_get (void)
get the system clock source More...
void | rcu_ahb_clock_config (uint32_t ck_ahb)
configure the AHB clock prescaler selection More...
void | rcu_apb1_clock_config (uint32_t ck_apb1)
configure the APB1 clock prescaler selection More...
void | rcu_apb2_clock_config (uint32_t ck_apb2)
configure the APB2 clock prescaler selection More...
void | rcu_ckout0_config (uint32_t ckout0_src)
configure the CK_OUT0 clock source More...
void | rcu_pll_config (uint32_t pll_src, uint32_t pll_mul)
configure the main PLL clock More...
void | rcu_predv0_config (uint32_t predv0_div)
configure the PREDV0 division factor More...
void | rcu_adc_clock_config (uint32_t adc_psc)
configure the ADC prescaler factor More...
void | rcu_usb_clock_config (uint32_t usb_psc)
configure the USBD/USBFS prescaler factor More...
void | rcu_rtc_clock_config (uint32_t rtc_clock_source)
configure the RTC clock source selection More...
void | rcu_i2s1_clock_config (uint32_t i2s_clock_source)
configure the I2S1 clock source selection More...
void | rcu_i2s2_clock_config (uint32_t i2s_clock_source)
configure the I2S2 clock source selection More...
FlagStatus | rcu_flag_get (rcu_flag_enum flag)
get the clock stabilization and periphral reset flags More...
void | rcu_all_reset_flag_clear (void)
clear all the reset flag More...
FlagStatus | rcu_interrupt_flag_get (rcu_int_flag_enum int_flag)
get the clock stabilization interrupt and ckm flags More...
void | rcu_interrupt_flag_clear (rcu_int_flag_clear_enum int_flag_clear)
clear the interrupt flags More...
void | rcu_interrupt_enable (rcu_int_enum stab_int)
enable the stabilization interrupt More...
void | rcu_interrupt_disable (rcu_int_enum stab_int)
disable the stabilization interrupt More...
ErrStatus | rcu_osci_stab_wait (rcu_osci_type_enum osci)
wait for oscillator stabilization flags is SET or oscillator startup is timeout More...
void | rcu_osci_on (rcu_osci_type_enum osci)
turn on the oscillator More...
void | rcu_osci_off (rcu_osci_type_enum osci)
turn off the oscillator More...
void | rcu_osci_bypass_mode_enable (rcu_osci_type_enum osci)
enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it More...
void | rcu_osci_bypass_mode_disable (rcu_osci_type_enum osci)
disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it More...
void | rcu_hxtal_clock_monitor_enable (void)
enable the HXTAL clock monitor More...
void | rcu_hxtal_clock_monitor_disable (void)
disable the HXTAL clock monitor More...
void | rcu_irc8m_adjust_value_set (uint32_t irc8m_adjval)
set the IRC8M adjust value More...
void | rcu_deepsleep_voltage_set (uint32_t dsvol)
deep-sleep mode voltage select More...
uint32_t | rcu_clock_freq_get (rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency More...

Detailed Description

definitions for the RCU

Definition in file gd32f10x_rcu.h.

Macro Definition Documentation

#define AHBEN_REG_OFFSET 0x14U

AHB enable register offset

Definition at line 331 of file gd32f10x_rcu.h.

#define AHBRST_REG_OFFSET 0x28U

AHB reset register offset

Definition at line 336 of file gd32f10x_rcu.h.

#define APB1EN_REG_OFFSET 0x1CU

APB1 enable register offset

Definition at line 332 of file gd32f10x_rcu.h.

#define APB1RST_REG_OFFSET 0x10U

APB1 reset register offset

Definition at line 337 of file gd32f10x_rcu.h.

#define APB2EN_REG_OFFSET 0x18U

APB2 enable register offset

Definition at line 333 of file gd32f10x_rcu.h.

#define APB2RST_REG_OFFSET 0x0CU

APB2 reset register offset

Definition at line 338 of file gd32f10x_rcu.h.

#define BDCTL_REG_OFFSET 0x20U

backup domain control register offset

Definition at line 343 of file gd32f10x_rcu.h.

#define BDCTL_RTCSRC ( regval ) (BITS(8,9) & ((uint32_t)(regval) << 8))

Definition at line 705 of file gd32f10x_rcu.h.

#define CFG0_AHBPSC ( regval ) (BITS(4,7) & ((uint32_t)(regval) << 4))

Definition at line 604 of file gd32f10x_rcu.h.

#define CFG0_APB1PSC ( regval ) (BITS(8,10) & ((uint32_t)(regval) << 8))

Definition at line 616 of file gd32f10x_rcu.h.

#define CFG0_APB2PSC ( regval ) (BITS(11,13) & ((uint32_t)(regval) << 11))

Definition at line 624 of file gd32f10x_rcu.h.

#define CFG0_CKOUT0SEL ( regval ) (BITS(24,27) & ((uint32_t)(regval) << 24))

Definition at line 691 of file gd32f10x_rcu.h.

#define CFG0_PLLMF ( regval ) (BITS(18,21) & ((uint32_t)(regval) << 18))

Definition at line 646 of file gd32f10x_rcu.h.

#define CFG0_REG_OFFSET 0x04U

clock configuration register 0 offset

Definition at line 349 of file gd32f10x_rcu.h.

#define CFG0_SCS ( regval ) (BITS(0,1) & ((uint32_t)(regval) << 0))

Definition at line 592 of file gd32f10x_rcu.h.

#define CFG0_SCSS ( regval ) (BITS(2,3) & ((uint32_t)(regval) << 2))

Definition at line 598 of file gd32f10x_rcu.h.

#define CFG0_USBPSC ( regval ) (BITS(22,23) & ((uint32_t)(regval) << 22))

Definition at line 684 of file gd32f10x_rcu.h.

#define CFG1_PLL1MF ( regval ) (BITS(8,11) & ((uint32_t)(regval) << 8))

Definition at line 750 of file gd32f10x_rcu.h.

#define CFG1_PLL2MF ( regval ) (BITS(12,15) & ((uint32_t)(regval) << 12))

Definition at line 763 of file gd32f10x_rcu.h.

#define CFG1_PREDV0 ( regval ) (BITS(0,3) & ((uint32_t)(regval) << 0))

Definition at line 712 of file gd32f10x_rcu.h.

#define CFG1_PREDV1 ( regval ) (BITS(4,7) & ((uint32_t)(regval) << 4))

Definition at line 731 of file gd32f10x_rcu.h.

#define CFG1_REG_OFFSET 0x2CU

clock configuration register 1 offset

Definition at line 350 of file gd32f10x_rcu.h.

#define CTL_REG_OFFSET 0x00U

control register offset

Definition at line 342 of file gd32f10x_rcu.h.

#define DSV_DSLPVS ( regval ) (BITS(0,2) & ((uint32_t)(regval) << 0))

Definition at line 790 of file gd32f10x_rcu.h.

#define INT_REG_OFFSET 0x08U

clock interrupt register offset

Definition at line 346 of file gd32f10x_rcu.h.

#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */

Definition at line 644 of file gd32f10x_rcu.h.

#define RCU RCU_BASE

Definition at line 19 of file gd32f10x_rcu.h.

#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0)

AHB prescaler select CK_SYS

Definition at line 605 of file gd32f10x_rcu.h.

#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13)

AHB prescaler select CK_SYS/128

Definition at line 611 of file gd32f10x_rcu.h.

#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11)

AHB prescaler select CK_SYS/16

Definition at line 609 of file gd32f10x_rcu.h.

#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8)

AHB prescaler select CK_SYS/2

Definition at line 606 of file gd32f10x_rcu.h.

#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14)

AHB prescaler select CK_SYS/256

Definition at line 612 of file gd32f10x_rcu.h.

#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9)

AHB prescaler select CK_SYS/4

Definition at line 607 of file gd32f10x_rcu.h.

#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15)

AHB prescaler select CK_SYS/512

Definition at line 613 of file gd32f10x_rcu.h.

#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12)

AHB prescaler select CK_SYS/64

Definition at line 610 of file gd32f10x_rcu.h.

#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10)

AHB prescaler select CK_SYS/8

Definition at line 608 of file gd32f10x_rcu.h.

#define RCU_AHBEN REG32(RCU + 0x14U)

AHB enable register

Definition at line 28 of file gd32f10x_rcu.h.

#define RCU_AHBEN_CRCEN BIT(6)

CRC clock enable

Definition at line 217 of file gd32f10x_rcu.h.

#define RCU_AHBEN_DMA0EN BIT(0)

DMA0 clock enable

Definition at line 213 of file gd32f10x_rcu.h.

#define RCU_AHBEN_DMA1EN BIT(1)

DMA1 clock enable

Definition at line 214 of file gd32f10x_rcu.h.

#define RCU_AHBEN_EXMCEN BIT(8)

EXMC clock enable

Definition at line 218 of file gd32f10x_rcu.h.

#define RCU_AHBEN_FMCSPEN BIT(4)

FMC clock enable when sleep mode

Definition at line 216 of file gd32f10x_rcu.h.

#define RCU_AHBEN_SDIOEN BIT(10)

SDIO clock enable

Definition at line 220 of file gd32f10x_rcu.h.

#define RCU_AHBEN_SRAMSPEN BIT(2)

SRAM clock enable when sleep mode

Definition at line 215 of file gd32f10x_rcu.h.

#define RCU_AHBRST_ENETRST BIT(14)

ENET reset

Definition at line 306 of file gd32f10x_rcu.h.

#define RCU_AHBRST_USBFSRST BIT(12)

USBFS reset

Definition at line 305 of file gd32f10x_rcu.h.

#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0)

APB1 prescaler select CK_AHB

Definition at line 617 of file gd32f10x_rcu.h.

#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7)

APB1 prescaler select CK_AHB/16

Definition at line 621 of file gd32f10x_rcu.h.

#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4)

APB1 prescaler select CK_AHB/2

Definition at line 618 of file gd32f10x_rcu.h.

#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5)

APB1 prescaler select CK_AHB/4

Definition at line 619 of file gd32f10x_rcu.h.

#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6)

APB1 prescaler select CK_AHB/8

Definition at line 620 of file gd32f10x_rcu.h.

#define RCU_APB1EN REG32(RCU + 0x1CU)

APB1 enable register

Definition at line 30 of file gd32f10x_rcu.h.

#define RCU_APB1EN_BKPIEN BIT(27)

backup interface clock enable

Definition at line 280 of file gd32f10x_rcu.h.

#define RCU_APB1EN_CAN0EN BIT(25)

CAN0 clock enable

Definition at line 276 of file gd32f10x_rcu.h.

#define RCU_APB1EN_CAN1EN BIT(26)

CAN1 clock enable

Definition at line 278 of file gd32f10x_rcu.h.

#define RCU_APB1EN_DACEN BIT(29)

DAC clock enable

Definition at line 282 of file gd32f10x_rcu.h.

#define RCU_APB1EN_I2C0EN BIT(21)

I2C0 clock enable

Definition at line 271 of file gd32f10x_rcu.h.

#define RCU_APB1EN_I2C1EN BIT(22)

I2C1 clock enable

Definition at line 272 of file gd32f10x_rcu.h.

#define RCU_APB1EN_PMUEN BIT(28)

PMU clock enable

Definition at line 281 of file gd32f10x_rcu.h.

#define RCU_APB1EN_SPI1EN BIT(14)

SPI1 clock enable

Definition at line 265 of file gd32f10x_rcu.h.

#define RCU_APB1EN_SPI2EN BIT(15)

SPI2 clock enable

Definition at line 266 of file gd32f10x_rcu.h.

#define RCU_APB1EN_TIMER11EN BIT(6)

TIMER11 clock enable

Definition at line 260 of file gd32f10x_rcu.h.

#define RCU_APB1EN_TIMER12EN BIT(7)

TIMER12 clock enable

Definition at line 261 of file gd32f10x_rcu.h.

#define RCU_APB1EN_TIMER13EN BIT(8)

TIMER13 clock enable

Definition at line 262 of file gd32f10x_rcu.h.

#define RCU_APB1EN_TIMER1EN BIT(0)

TIMER1 clock enable

Definition at line 253 of file gd32f10x_rcu.h.

#define RCU_APB1EN_TIMER2EN BIT(1)

TIMER2 clock enable

Definition at line 254 of file gd32f10x_rcu.h.

#define RCU_APB1EN_TIMER3EN BIT(2)

TIMER3 clock enable

Definition at line 255 of file gd32f10x_rcu.h.

#define RCU_APB1EN_TIMER4EN BIT(3)

TIMER4 clock enable

Definition at line 256 of file gd32f10x_rcu.h.

#define RCU_APB1EN_TIMER5EN BIT(4)

TIMER5 clock enable

Definition at line 257 of file gd32f10x_rcu.h.

#define RCU_APB1EN_TIMER6EN BIT(5)

TIMER6 clock enable

Definition at line 258 of file gd32f10x_rcu.h.

#define RCU_APB1EN_UART3EN BIT(19)

UART3 clock enable

Definition at line 269 of file gd32f10x_rcu.h.

#define RCU_APB1EN_UART4EN BIT(20)

UART4 clock enable

Definition at line 270 of file gd32f10x_rcu.h.

#define RCU_APB1EN_USART1EN BIT(17)

USART1 clock enable

Definition at line 267 of file gd32f10x_rcu.h.

#define RCU_APB1EN_USART2EN BIT(18)

USART2 clock enable

Definition at line 268 of file gd32f10x_rcu.h.

#define RCU_APB1EN_USBDEN BIT(23)

USBD clock enable

Definition at line 274 of file gd32f10x_rcu.h.

#define RCU_APB1EN_WWDGTEN BIT(11)

WWDGT clock enable

Definition at line 264 of file gd32f10x_rcu.h.

#define RCU_APB1RST REG32(RCU + 0x10U)

APB1 reset register

Definition at line 27 of file gd32f10x_rcu.h.

#define RCU_APB1RST_BKPIRST BIT(27)

backup interface reset

Definition at line 208 of file gd32f10x_rcu.h.

#define RCU_APB1RST_CAN0RST BIT(25)

CAN0 reset

Definition at line 204 of file gd32f10x_rcu.h.

#define RCU_APB1RST_CAN1RST BIT(26)

CAN1 reset

Definition at line 206 of file gd32f10x_rcu.h.

#define RCU_APB1RST_DACRST BIT(29)

DAC reset

Definition at line 210 of file gd32f10x_rcu.h.

#define RCU_APB1RST_I2C0RST BIT(21)

I2C0 reset

Definition at line 199 of file gd32f10x_rcu.h.

#define RCU_APB1RST_I2C1RST BIT(22)

I2C1 reset

Definition at line 200 of file gd32f10x_rcu.h.

#define RCU_APB1RST_PMURST BIT(28)

PMU reset

Definition at line 209 of file gd32f10x_rcu.h.

#define RCU_APB1RST_SPI1RST BIT(14)

SPI1 reset

Definition at line 193 of file gd32f10x_rcu.h.

#define RCU_APB1RST_SPI2RST BIT(15)

SPI2 reset

Definition at line 194 of file gd32f10x_rcu.h.

#define RCU_APB1RST_TIMER11RST BIT(6)

TIMER11 reset

Definition at line 188 of file gd32f10x_rcu.h.

#define RCU_APB1RST_TIMER12RST BIT(7)

TIMER12 reset

Definition at line 189 of file gd32f10x_rcu.h.

#define RCU_APB1RST_TIMER13RST BIT(8)

TIMER13 reset

Definition at line 190 of file gd32f10x_rcu.h.

#define RCU_APB1RST_TIMER1RST BIT(0)

TIMER1 reset

Definition at line 181 of file gd32f10x_rcu.h.

#define RCU_APB1RST_TIMER2RST BIT(1)

TIMER2 reset

Definition at line 182 of file gd32f10x_rcu.h.

#define RCU_APB1RST_TIMER3RST BIT(2)

TIMER3 reset

Definition at line 183 of file gd32f10x_rcu.h.

#define RCU_APB1RST_TIMER4RST BIT(3)

TIMER4 reset

Definition at line 184 of file gd32f10x_rcu.h.

#define RCU_APB1RST_TIMER5RST BIT(4)

TIMER5 reset

Definition at line 185 of file gd32f10x_rcu.h.

#define RCU_APB1RST_TIMER6RST BIT(5)

TIMER6 reset

Definition at line 186 of file gd32f10x_rcu.h.

#define RCU_APB1RST_UART3RST BIT(19)

UART3 reset

Definition at line 197 of file gd32f10x_rcu.h.

#define RCU_APB1RST_UART4RST BIT(20)

UART4 reset

Definition at line 198 of file gd32f10x_rcu.h.

#define RCU_APB1RST_USART1RST BIT(17)

USART1 reset

Definition at line 195 of file gd32f10x_rcu.h.

#define RCU_APB1RST_USART2RST BIT(18)

USART2 reset

Definition at line 196 of file gd32f10x_rcu.h.

#define RCU_APB1RST_USBDRST BIT(23)

USBD reset

Definition at line 202 of file gd32f10x_rcu.h.

#define RCU_APB1RST_WWDGTRST BIT(11)

WWDGT reset

Definition at line 192 of file gd32f10x_rcu.h.

#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0)

APB2 prescaler select CK_AHB

Definition at line 625 of file gd32f10x_rcu.h.

#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7)

APB2 prescaler select CK_AHB/16

Definition at line 629 of file gd32f10x_rcu.h.

#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4)

APB2 prescaler select CK_AHB/2

Definition at line 626 of file gd32f10x_rcu.h.

#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5)

APB2 prescaler select CK_AHB/4

Definition at line 627 of file gd32f10x_rcu.h.

#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6)

APB2 prescaler select CK_AHB/8

Definition at line 628 of file gd32f10x_rcu.h.

#define RCU_APB2EN REG32(RCU + 0x18U)

APB2 enable register

Definition at line 29 of file gd32f10x_rcu.h.

#define RCU_APB2EN_ADC0EN BIT(9)

ADC0 clock enable

Definition at line 237 of file gd32f10x_rcu.h.

#define RCU_APB2EN_ADC1EN BIT(10)

ADC1 clock enable

Definition at line 238 of file gd32f10x_rcu.h.

#define RCU_APB2EN_AFEN BIT(0)

alternate function IO clock enable

Definition at line 229 of file gd32f10x_rcu.h.

#define RCU_APB2EN_PAEN BIT(2)

GPIO port A clock enable

Definition at line 230 of file gd32f10x_rcu.h.

#define RCU_APB2EN_PBEN BIT(3)

GPIO port B clock enable

Definition at line 231 of file gd32f10x_rcu.h.

#define RCU_APB2EN_PCEN BIT(4)

GPIO port C clock enable

Definition at line 232 of file gd32f10x_rcu.h.

#define RCU_APB2EN_PDEN BIT(5)

GPIO port D clock enable

Definition at line 233 of file gd32f10x_rcu.h.

#define RCU_APB2EN_PEEN BIT(6)

GPIO port E clock enable

Definition at line 234 of file gd32f10x_rcu.h.

#define RCU_APB2EN_PFEN BIT(7)

GPIO port F clock enable

Definition at line 235 of file gd32f10x_rcu.h.

#define RCU_APB2EN_PGEN BIT(8)

GPIO port G clock enable

Definition at line 236 of file gd32f10x_rcu.h.

#define RCU_APB2EN_SPI0EN BIT(12)

SPI0 clock enable

Definition at line 240 of file gd32f10x_rcu.h.

#define RCU_APB2EN_TIMER0EN BIT(11)

TIMER0 clock enable

Definition at line 239 of file gd32f10x_rcu.h.

#define RCU_APB2EN_TIMER10EN BIT(21)

TIMER10 clock enable

Definition at line 249 of file gd32f10x_rcu.h.

#define RCU_APB2EN_TIMER7EN BIT(13)

TIMER7 clock enable

Definition at line 241 of file gd32f10x_rcu.h.

#define RCU_APB2EN_TIMER8EN BIT(19)

TIMER8 clock enable

Definition at line 247 of file gd32f10x_rcu.h.

#define RCU_APB2EN_TIMER9EN BIT(20)

TIMER9 clock enable

Definition at line 248 of file gd32f10x_rcu.h.

#define RCU_APB2EN_USART0EN BIT(14)

USART0 clock enable

Definition at line 242 of file gd32f10x_rcu.h.

#define RCU_APB2RST REG32(RCU + 0x0CU)

APB2 reset register

Definition at line 26 of file gd32f10x_rcu.h.

#define RCU_APB2RST_ADC0RST BIT(9)

ADC0 reset

Definition at line 165 of file gd32f10x_rcu.h.

#define RCU_APB2RST_ADC1RST BIT(10)

ADC1 reset

Definition at line 166 of file gd32f10x_rcu.h.

#define RCU_APB2RST_AFRST BIT(0)

alternate function I/O reset

Definition at line 157 of file gd32f10x_rcu.h.

#define RCU_APB2RST_PARST BIT(2)

GPIO port A reset

Definition at line 158 of file gd32f10x_rcu.h.

#define RCU_APB2RST_PBRST BIT(3)

GPIO port B reset

Definition at line 159 of file gd32f10x_rcu.h.

#define RCU_APB2RST_PCRST BIT(4)

GPIO port C reset

Definition at line 160 of file gd32f10x_rcu.h.

#define RCU_APB2RST_PDRST BIT(5)

GPIO port D reset

Definition at line 161 of file gd32f10x_rcu.h.

#define RCU_APB2RST_PERST BIT(6)

GPIO port E reset

Definition at line 162 of file gd32f10x_rcu.h.

#define RCU_APB2RST_PFRST BIT(7)

GPIO port F reset

Definition at line 163 of file gd32f10x_rcu.h.

#define RCU_APB2RST_PGRST BIT(8)

GPIO port G reset

Definition at line 164 of file gd32f10x_rcu.h.

#define RCU_APB2RST_SPI0RST BIT(12)

SPI0 reset

Definition at line 168 of file gd32f10x_rcu.h.

#define RCU_APB2RST_TIMER0RST BIT(11)

TIMER0 reset

Definition at line 167 of file gd32f10x_rcu.h.

#define RCU_APB2RST_TIMER10RST BIT(21)

TIMER10 reset

Definition at line 177 of file gd32f10x_rcu.h.

#define RCU_APB2RST_TIMER7RST BIT(13)

TIMER7 reset

Definition at line 169 of file gd32f10x_rcu.h.

#define RCU_APB2RST_TIMER8RST BIT(19)

TIMER8 reset

Definition at line 175 of file gd32f10x_rcu.h.

#define RCU_APB2RST_TIMER9RST BIT(20)

TIMER9 reset

Definition at line 176 of file gd32f10x_rcu.h.

#define RCU_APB2RST_USART0RST BIT(14)

USART0 reset

Definition at line 170 of file gd32f10x_rcu.h.

#define RCU_BDCTL REG32(RCU + 0x20U)

backup domain control register

Definition at line 31 of file gd32f10x_rcu.h.

#define RCU_BDCTL_BKPRST BIT(16)

backup domain reset

Definition at line 290 of file gd32f10x_rcu.h.

#define RCU_BDCTL_LXTALBPS BIT(2)

LXTAL bypass mode enable

Definition at line 287 of file gd32f10x_rcu.h.

#define RCU_BDCTL_LXTALEN BIT(0)

LXTAL enable

Definition at line 285 of file gd32f10x_rcu.h.

#define RCU_BDCTL_LXTALSTB BIT(1)

low speed crystal oscillator stabilization flag

Definition at line 286 of file gd32f10x_rcu.h.

#define RCU_BDCTL_RTCEN BIT(15)

RTC clock enable

Definition at line 289 of file gd32f10x_rcu.h.

#define RCU_BDCTL_RTCSRC BITS(8,9)

RTC clock entry selection

Definition at line 288 of file gd32f10x_rcu.h.

#define RCU_BIT_POS ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 327 of file gd32f10x_rcu.h.

#define RCU_CFG0 REG32(RCU + 0x04U)

clock configuration register 0

Definition at line 24 of file gd32f10x_rcu.h.

#define RCU_CFG0_ADCPSC BITS(14,15)

ADC prescaler selection

Definition at line 87 of file gd32f10x_rcu.h.

#define RCU_CFG0_ADCPSC_2 BIT(28)

bit 2 of ADCPSC

Definition at line 94 of file gd32f10x_rcu.h.

#define RCU_CFG0_AHBPSC BITS(4,7)

AHB prescaler selection

Definition at line 84 of file gd32f10x_rcu.h.

#define RCU_CFG0_APB1PSC BITS(8,10)

APB1 prescaler selection

Definition at line 85 of file gd32f10x_rcu.h.

#define RCU_CFG0_APB2PSC BITS(11,13)

APB2 prescaler selection

Definition at line 86 of file gd32f10x_rcu.h.

#define RCU_CFG0_CKOUT0SEL BITS(24,26)

CKOUT0 clock source selection

Definition at line 92 of file gd32f10x_rcu.h.

#define RCU_CFG0_PLLMF BITS(18,21)

PLL clock multiplication factor

Definition at line 90 of file gd32f10x_rcu.h.

#define RCU_CFG0_PLLMF_4 BIT(27)

bit 4 of PLLMF

Definition at line 93 of file gd32f10x_rcu.h.

#define RCU_CFG0_PLLSEL BIT(16)

PLL clock source selection

Definition at line 88 of file gd32f10x_rcu.h.

#define RCU_CFG0_PREDV0 BIT(17)

PREDV0 division factor

Definition at line 89 of file gd32f10x_rcu.h.

#define RCU_CFG0_SCS BITS(0,1)

system clock switch

Definition at line 82 of file gd32f10x_rcu.h.

#define RCU_CFG0_SCSS BITS(2,3)

system clock switch status

Definition at line 83 of file gd32f10x_rcu.h.

#define RCU_CFG0_USBDPSC BITS(22,23)

USBD clock prescaler selection

Definition at line 91 of file gd32f10x_rcu.h.

#define RCU_CFG1_I2S1SEL BIT(17)

I2S1 clock source selection

Definition at line 316 of file gd32f10x_rcu.h.

#define RCU_CFG1_I2S2SEL BIT(18)

I2S2 clock source selection

Definition at line 317 of file gd32f10x_rcu.h.

#define RCU_CFG1_PLL1MF BITS(8,11)

PLL1 clock multiplication factor

Definition at line 313 of file gd32f10x_rcu.h.

#define RCU_CFG1_PLL2MF BITS(12,15)

PLL2 clock multiplication factor

Definition at line 314 of file gd32f10x_rcu.h.

#define RCU_CFG1_PREDV0 BITS(0,3)

PREDV0 division factor

Definition at line 311 of file gd32f10x_rcu.h.

#define RCU_CFG1_PREDV0SEL BIT(16)

PREDV0 input clock source selection

Definition at line 315 of file gd32f10x_rcu.h.

#define RCU_CFG1_PREDV1 BITS(4,7)

PREDV1 division factor

Definition at line 312 of file gd32f10x_rcu.h.

#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U)

ADC prescaler select CK_APB2/12

Definition at line 636 of file gd32f10x_rcu.h.

#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U)

ADC prescaler select CK_APB2/16

Definition at line 637 of file gd32f10x_rcu.h.

#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U)

ADC prescaler select CK_APB2/2

Definition at line 632 of file gd32f10x_rcu.h.

#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U)

ADC prescaler select CK_APB2/4

Definition at line 633 of file gd32f10x_rcu.h.

#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U)

ADC prescaler select CK_APB2/6

Definition at line 634 of file gd32f10x_rcu.h.

#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U)

ADC prescaler select CK_APB2/8

Definition at line 635 of file gd32f10x_rcu.h.

#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8)

CK_PLL1 clock selected

Definition at line 698 of file gd32f10x_rcu.h.

#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11)

CK_PLL2 clock selected

Definition at line 701 of file gd32f10x_rcu.h.

#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9)

CK_PLL2/2 clock selected

Definition at line 699 of file gd32f10x_rcu.h.

#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7)

CK_PLL/2 clock selected

Definition at line 696 of file gd32f10x_rcu.h.

#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4)

system clock selected

Definition at line 693 of file gd32f10x_rcu.h.

#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10)

EXT1 selected, to provide the external clock for ENET

Definition at line 700 of file gd32f10x_rcu.h.

#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6)

high speed crystal oscillator clock (HXTAL) selected

Definition at line 695 of file gd32f10x_rcu.h.

#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5)

internal 8M RC oscillator clock selected

Definition at line 694 of file gd32f10x_rcu.h.

#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0)

no clock selected

Definition at line 692 of file gd32f10x_rcu.h.

#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1)

system clock source select HXTAL

Definition at line 594 of file gd32f10x_rcu.h.

#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0)

system clock source select IRC8M

Definition at line 593 of file gd32f10x_rcu.h.

#define RCU_CKSYSSRC_PLL CFG0_SCS(2)

system clock source select PLL

Definition at line 595 of file gd32f10x_rcu.h.

#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1)

USBD/USBFS prescaler select CK_PLL/1

Definition at line 686 of file gd32f10x_rcu.h.

#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0)

USBD/USBFS prescaler select CK_PLL/1.5

Definition at line 685 of file gd32f10x_rcu.h.

#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3)

USBD/USBFS prescaler select CK_PLL/2

Definition at line 688 of file gd32f10x_rcu.h.

#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2)

USBD/USBFS prescaler select CK_PLL/2.5

Definition at line 687 of file gd32f10x_rcu.h.

#define RCU_CTL REG32(RCU + 0x00U)

control register

Definition at line 23 of file gd32f10x_rcu.h.

#define RCU_CTL_CKMEN BIT(19)

HXTAL clock monitor enable

Definition at line 60 of file gd32f10x_rcu.h.

#define RCU_CTL_HXTALBPS BIT(18)

external crystal oscillator clock bypass mode enable

Definition at line 59 of file gd32f10x_rcu.h.

#define RCU_CTL_HXTALEN BIT(16)

external high speed oscillator enable

Definition at line 57 of file gd32f10x_rcu.h.

#define RCU_CTL_HXTALSTB BIT(17)

external crystal oscillator clock stabilization flag

Definition at line 58 of file gd32f10x_rcu.h.

#define RCU_CTL_IRC8MADJ BITS(3,7)

high speed internal oscillator clock trim adjust value

Definition at line 55 of file gd32f10x_rcu.h.

#define RCU_CTL_IRC8MCALIB BITS(8,15)

high speed internal oscillator calibration value register

Definition at line 56 of file gd32f10x_rcu.h.

#define RCU_CTL_IRC8MEN BIT(0)

internal high speed oscillator enable

Definition at line 53 of file gd32f10x_rcu.h.

#define RCU_CTL_IRC8MSTB BIT(1)

IRC8M high speed internal oscillator stabilization flag

Definition at line 54 of file gd32f10x_rcu.h.

#define RCU_CTL_PLLEN BIT(24)

PLL enable

Definition at line 61 of file gd32f10x_rcu.h.

#define RCU_CTL_PLLSTB BIT(25)

PLL clock stabilization flag

Definition at line 62 of file gd32f10x_rcu.h.

#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3)

core voltage is 0.9V in deep-sleep mode

Definition at line 794 of file gd32f10x_rcu.h.

#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2)

core voltage is 1.0V in deep-sleep mode

Definition at line 793 of file gd32f10x_rcu.h.

#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1)

core voltage is 1.1V in deep-sleep mode

Definition at line 792 of file gd32f10x_rcu.h.

#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0)

core voltage is 1.2V in deep-sleep mode

Definition at line 791 of file gd32f10x_rcu.h.

#define RCU_DSV REG32(RCU + 0x34U)

deep-sleep mode voltage register

Definition at line 33 of file gd32f10x_rcu.h.

#define RCU_DSV_DSLPVS BITS(0,2)

deep-sleep mode voltage select

Definition at line 321 of file gd32f10x_rcu.h.

#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL

(CK_PLL2 x 2) selected as I2S1 source clock

Definition at line 782 of file gd32f10x_rcu.h.

#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U)

system clock selected as I2S1 source clock

Definition at line 781 of file gd32f10x_rcu.h.

#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL

(CK_PLL2 x 2) selected as I2S2 source clock

Definition at line 786 of file gd32f10x_rcu.h.

#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U)

system clock selected as I2S2 source clock

Definition at line 785 of file gd32f10x_rcu.h.

#define RCU_INT REG32(RCU + 0x08U)

clock interrupt register

Definition at line 25 of file gd32f10x_rcu.h.

#define RCU_INT_CKMIC BIT(23)

HXTAL clock stuck interrupt clear

Definition at line 129 of file gd32f10x_rcu.h.

#define RCU_INT_CKMIF BIT(7)

HXTAL clock stuck interrupt flag

Definition at line 118 of file gd32f10x_rcu.h.

#define RCU_INT_HXTALSTBIC BIT(19)

HXTAL Stabilization interrupt clear

Definition at line 127 of file gd32f10x_rcu.h.

#define RCU_INT_HXTALSTBIE BIT(11)

HXTAL stabilization interrupt enable

Definition at line 122 of file gd32f10x_rcu.h.

#define RCU_INT_HXTALSTBIF BIT(3)

HXTAL stabilization interrupt flag

Definition at line 116 of file gd32f10x_rcu.h.

#define RCU_INT_IRC40KSTBIC BIT(16)

IRC40K Stabilization interrupt clear

Definition at line 124 of file gd32f10x_rcu.h.

#define RCU_INT_IRC40KSTBIE BIT(8)

IRC40K stabilization interrupt enable

Definition at line 119 of file gd32f10x_rcu.h.

#define RCU_INT_IRC40KSTBIF BIT(0)

IRC40K stabilization interrupt flag

Definition at line 113 of file gd32f10x_rcu.h.

#define RCU_INT_IRC8MSTBIC BIT(18)

IRC8M Stabilization interrupt clear

Definition at line 126 of file gd32f10x_rcu.h.

#define RCU_INT_IRC8MSTBIE BIT(10)

IRC8M stabilization interrupt enable

Definition at line 121 of file gd32f10x_rcu.h.

#define RCU_INT_IRC8MSTBIF BIT(2)

IRC8M stabilization interrupt flag

Definition at line 115 of file gd32f10x_rcu.h.

#define RCU_INT_LXTALSTBIC BIT(17)

LXTAL Stabilization interrupt clear

Definition at line 125 of file gd32f10x_rcu.h.

#define RCU_INT_LXTALSTBIE BIT(9)

LXTAL stabilization interrupt enable

Definition at line 120 of file gd32f10x_rcu.h.

#define RCU_INT_LXTALSTBIF BIT(1)

LXTAL stabilization interrupt flag

Definition at line 114 of file gd32f10x_rcu.h.

#define RCU_INT_PLLSTBIC BIT(20)

PLL stabilization interrupt clear

Definition at line 128 of file gd32f10x_rcu.h.

#define RCU_INT_PLLSTBIE BIT(12)

PLL stabilization interrupt enable

Definition at line 123 of file gd32f10x_rcu.h.

#define RCU_INT_PLLSTBIF BIT(4)

PLL stabilization interrupt flag

Definition at line 117 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL10 CFG1_PLL1MF(8)

PLL1 source clock multiply by 10

Definition at line 753 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL11 CFG1_PLL1MF(9)

PLL1 source clock multiply by 11

Definition at line 754 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL12 CFG1_PLL1MF(10)

PLL1 source clock multiply by 12

Definition at line 755 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL13 CFG1_PLL1MF(11)

PLL1 source clock multiply by 13

Definition at line 756 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL14 CFG1_PLL1MF(12)

PLL1 source clock multiply by 14

Definition at line 757 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL15 CFG1_PLL1MF(13)

PLL1 source clock multiply by 15

Definition at line 758 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL16 CFG1_PLL1MF(14)

PLL1 source clock multiply by 16

Definition at line 759 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL20 CFG1_PLL1MF(15)

PLL1 source clock multiply by 20

Definition at line 760 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL8 CFG1_PLL1MF(6)

PLL1 source clock multiply by 8

Definition at line 751 of file gd32f10x_rcu.h.

#define RCU_PLL1_MUL9 CFG1_PLL1MF(7)

PLL1 source clock multiply by 9

Definition at line 752 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL10 CFG1_PLL2MF(8)

PLL2 source clock multiply by 10

Definition at line 766 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL11 CFG1_PLL2MF(9)

PLL2 source clock multiply by 11

Definition at line 767 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL12 CFG1_PLL2MF(10)

PLL2 source clock multiply by 12

Definition at line 768 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL13 CFG1_PLL2MF(11)

PLL2 source clock multiply by 13

Definition at line 769 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL14 CFG1_PLL2MF(12)

PLL2 source clock multiply by 14

Definition at line 770 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL15 CFG1_PLL2MF(13)

PLL2 source clock multiply by 15

Definition at line 771 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL16 CFG1_PLL2MF(14)

PLL2 source clock multiply by 16

Definition at line 772 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL20 CFG1_PLL2MF(15)

PLL2 source clock multiply by 20

Definition at line 773 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL8 CFG1_PLL2MF(6)

PLL2 source clock multiply by 8

Definition at line 764 of file gd32f10x_rcu.h.

#define RCU_PLL2_MUL9 CFG1_PLL2MF(7)

PLL2 source clock multiply by 9

Definition at line 765 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL10 CFG0_PLLMF(8)

PLL source clock multiply by 10

Definition at line 655 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL11 CFG0_PLLMF(9)

PLL source clock multiply by 11

Definition at line 656 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL12 CFG0_PLLMF(10)

PLL source clock multiply by 12

Definition at line 657 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL13 CFG0_PLLMF(11)

PLL source clock multiply by 13

Definition at line 658 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL14 CFG0_PLLMF(12)

PLL source clock multiply by 14

Definition at line 659 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL15 CFG0_PLLMF(13)

PLL source clock multiply by 15

Definition at line 661 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL16 CFG0_PLLMF(14)

PLL source clock multiply by 16

Definition at line 665 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0))

PLL source clock multiply by 17

Definition at line 666 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1))

PLL source clock multiply by 18

Definition at line 667 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2))

PLL source clock multiply by 19

Definition at line 668 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL2 CFG0_PLLMF(0)

PLL source clock multiply by 2

Definition at line 647 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3))

PLL source clock multiply by 20

Definition at line 669 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4))

PLL source clock multiply by 21

Definition at line 670 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5))

PLL source clock multiply by 22

Definition at line 671 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6))

PLL source clock multiply by 23

Definition at line 672 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7))

PLL source clock multiply by 24

Definition at line 673 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8))

PLL source clock multiply by 25

Definition at line 674 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9))

PLL source clock multiply by 26

Definition at line 675 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10))

PLL source clock multiply by 27

Definition at line 676 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11))

PLL source clock multiply by 28

Definition at line 677 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12))

PLL source clock multiply by 29

Definition at line 678 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL3 CFG0_PLLMF(1)

PLL source clock multiply by 3

Definition at line 648 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13))

PLL source clock multiply by 30

Definition at line 679 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14))

PLL source clock multiply by 31

Definition at line 680 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15))

PLL source clock multiply by 32

Definition at line 681 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL4 CFG0_PLLMF(2)

PLL source clock multiply by 4

Definition at line 649 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL5 CFG0_PLLMF(3)

PLL source clock multiply by 5

Definition at line 650 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL6 CFG0_PLLMF(4)

PLL source clock multiply by 6

Definition at line 651 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL7 CFG0_PLLMF(5)

PLL source clock multiply by 7

Definition at line 652 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL8 CFG0_PLLMF(6)

PLL source clock multiply by 8

Definition at line 653 of file gd32f10x_rcu.h.

#define RCU_PLL_MUL9 CFG0_PLLMF(7)

PLL source clock multiply by 9

Definition at line 654 of file gd32f10x_rcu.h.

#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL

HXTAL clock selected as source clock of PLL

Definition at line 641 of file gd32f10x_rcu.h.

#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U)

IRC8M/2 clock selected as source clock of PLL

Definition at line 640 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV1 CFG1_PREDV0(0)

PREDV0 input source clock not divided

Definition at line 713 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV10 CFG1_PREDV0(9)

PREDV0 input source clock divided by 10

Definition at line 722 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV11 CFG1_PREDV0(10)

PREDV0 input source clock divided by 11

Definition at line 723 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV12 CFG1_PREDV0(11)

PREDV0 input source clock divided by 12

Definition at line 724 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV13 CFG1_PREDV0(12)

PREDV0 input source clock divided by 13

Definition at line 725 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV14 CFG1_PREDV0(13)

PREDV0 input source clock divided by 14

Definition at line 726 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV15 CFG1_PREDV0(14)

PREDV0 input source clock divided by 15

Definition at line 727 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV16 CFG1_PREDV0(15)

PREDV0 input source clock divided by 16

Definition at line 728 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV2 CFG1_PREDV0(1)

PREDV0 input source clock divided by 2

Definition at line 714 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV3 CFG1_PREDV0(2)

PREDV0 input source clock divided by 3

Definition at line 715 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV4 CFG1_PREDV0(3)

PREDV0 input source clock divided by 4

Definition at line 716 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV5 CFG1_PREDV0(4)

PREDV0 input source clock divided by 5

Definition at line 717 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV6 CFG1_PREDV0(5)

PREDV0 input source clock divided by 6

Definition at line 718 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV7 CFG1_PREDV0(6)

PREDV0 input source clock divided by 7

Definition at line 719 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV8 CFG1_PREDV0(7)

PREDV0 input source clock divided by 8

Definition at line 720 of file gd32f10x_rcu.h.

#define RCU_PREDV0_DIV9 CFG1_PREDV0(8)

PREDV0 input source clock divided by 9

Definition at line 721 of file gd32f10x_rcu.h.

#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL

CK_PLL1 selected as PREDV0 input source clock

Definition at line 778 of file gd32f10x_rcu.h.

#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U)

HXTAL selected as PREDV0 input source clock

Definition at line 777 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV1 CFG1_PREDV1(0)

PREDV1 input source clock not divided

Definition at line 732 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV10 CFG1_PREDV1(9)

PREDV1 input source clock divided by 10

Definition at line 741 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV11 CFG1_PREDV1(10)

PREDV1 input source clock divided by 11

Definition at line 742 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV12 CFG1_PREDV1(11)

PREDV1 input source clock divided by 12

Definition at line 743 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV13 CFG1_PREDV1(12)

PREDV1 input source clock divided by 13

Definition at line 744 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV14 CFG1_PREDV1(13)

PREDV1 input source clock divided by 14

Definition at line 745 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV15 CFG1_PREDV1(14)

PREDV1 input source clock divided by 15

Definition at line 746 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV16 CFG1_PREDV1(15)

PREDV1 input source clock divided by 16

Definition at line 747 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV2 CFG1_PREDV1(1)

PREDV1 input source clock divided by 2

Definition at line 733 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV3 CFG1_PREDV1(2)

PREDV1 input source clock divided by 3

Definition at line 734 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV4 CFG1_PREDV1(3)

PREDV1 input source clock divided by 4

Definition at line 735 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV5 CFG1_PREDV1(4)

PREDV1 input source clock divided by 5

Definition at line 736 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV6 CFG1_PREDV1(5)

PREDV1 input source clock divided by 6

Definition at line 737 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV7 CFG1_PREDV1(6)

PREDV1 input source clock divided by 7

Definition at line 738 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV8 CFG1_PREDV1(7)

PREDV1 input source clock divided by 8

Definition at line 739 of file gd32f10x_rcu.h.

#define RCU_PREDV1_DIV9 CFG1_PREDV1(8)

PREDV1 input source clock divided by 9

Definition at line 740 of file gd32f10x_rcu.h.

#define RCU_REG_VAL ( periph ) (REG32(RCU + ((uint32_t)(periph) >> 6)))

Definition at line 326 of file gd32f10x_rcu.h.

#define RCU_REGIDX_BIT | ( | regidx,
 |  | bitpos
 | ) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))

Definition at line 325 of file gd32f10x_rcu.h.

#define RCU_RSTSCK REG32(RCU + 0x24U)

reset source / clock register

Definition at line 32 of file gd32f10x_rcu.h.

#define RCU_RSTSCK_EPRSTF BIT(26)

external pin reset flag

Definition at line 296 of file gd32f10x_rcu.h.

#define RCU_RSTSCK_FWDGTRSTF BIT(29)

free watchdog timer reset flag

Definition at line 299 of file gd32f10x_rcu.h.

#define RCU_RSTSCK_IRC40KEN BIT(0)

IRC40K enable

Definition at line 293 of file gd32f10x_rcu.h.

#define RCU_RSTSCK_IRC40KSTB BIT(1)

IRC40K stabilization flag

Definition at line 294 of file gd32f10x_rcu.h.

#define RCU_RSTSCK_LPRSTF BIT(31)

low-power reset flag

Definition at line 301 of file gd32f10x_rcu.h.

#define RCU_RSTSCK_PORRSTF BIT(27)

power reset flag

Definition at line 297 of file gd32f10x_rcu.h.

#define RCU_RSTSCK_RSTFC BIT(24)

reset flag clear

Definition at line 295 of file gd32f10x_rcu.h.

#define RCU_RSTSCK_SWRSTF BIT(28)

software reset flag

Definition at line 298 of file gd32f10x_rcu.h.

#define RCU_RSTSCK_WWDGTRSTF BIT(30)

window watchdog timer reset flag

Definition at line 300 of file gd32f10x_rcu.h.

#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3)

RTC source clock select HXTAL/128

Definition at line 709 of file gd32f10x_rcu.h.

#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2)

RTC source clock select IRC40K

Definition at line 708 of file gd32f10x_rcu.h.

#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1)

RTC source clock select LXTAL

Definition at line 707 of file gd32f10x_rcu.h.

#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0)

no clock selected

Definition at line 706 of file gd32f10x_rcu.h.

#define RCU_SCSS_HXTAL CFG0_SCSS(1)

system clock source select HXTAL

Definition at line 600 of file gd32f10x_rcu.h.

#define RCU_SCSS_IRC8M CFG0_SCSS(0)

system clock source select IRC8M

Definition at line 599 of file gd32f10x_rcu.h.

#define RCU_SCSS_PLL CFG0_SCSS(2)

system clock source select PLLP

Definition at line 601 of file gd32f10x_rcu.h.

#define RSTSCK_REG_OFFSET 0x24U

reset source/clock register offset

Definition at line 339 of file gd32f10x_rcu.h.

Enumeration Type Documentation

enum rcu_clock_freq_enum
Enumerator
CK_SYS | system clock
CK_AHB | AHB clock
CK_APB1 | APB1 clock
CK_APB2 | APB2 clock

Definition at line 582 of file gd32f10x_rcu.h.

583 {
584 CK_SYS = 0,
585 CK_AHB,
586 CK_APB1,
587 CK_APB2,
588 }rcu_clock_freq_enum;
CK_SYS
Definition: gd32f10x_rcu.h:584
rcu_clock_freq_enum
rcu_clock_freq_enum
Definition: gd32f10x_rcu.h:582
CK_APB2
Definition: gd32f10x_rcu.h:587
CK_AHB
Definition: gd32f10x_rcu.h:585
CK_APB1
Definition: gd32f10x_rcu.h:586
enum rcu_flag_enum
Enumerator
RCU_FLAG_IRC8MSTB | IRC8M stabilization flags
RCU_FLAG_HXTALSTB | HXTAL stabilization flags
RCU_FLAG_PLLSTB | PLL stabilization flags
RCU_FLAG_PLL1STB | PLL1 stabilization flags
RCU_FLAG_PLL2STB | PLL2 stabilization flags
RCU_FLAG_LXTALSTB | LXTAL stabilization flags
RCU_FLAG_IRC40KSTB | IRC40K stabilization flags
RCU_FLAG_EPRST | external PIN reset flags
RCU_FLAG_PORRST | power reset flags
RCU_FLAG_SWRST | software reset flags
RCU_FLAG_FWDGTRST | FWDGT reset flags
RCU_FLAG_WWDGTRST | WWDGT reset flags
RCU_FLAG_LPRST | low-power reset flags

Definition at line 502 of file gd32f10x_rcu.h.

503 {
504 /* clock stabilization flags */
505 RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U),
506 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U),
507 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U),
508 #ifdef GD32F10X_CL
509 RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U),
510 RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U),
511 #endif /* GD32F10X_CL */
512 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U),
513 RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U),
514 /* reset source flags */
515 RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U),
516 RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U),
517 RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U),
518 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U),
519 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U),
520 RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U),
521 }rcu_flag_enum;
RCU_FLAG_PLL1STB
Definition: gd32f10x_rcu.h:509
RCU_FLAG_PORRST
Definition: gd32f10x_rcu.h:516
RCU_FLAG_LPRST
Definition: gd32f10x_rcu.h:520
RSTSCK_REG_OFFSET
#define RSTSCK_REG_OFFSET
Definition: gd32f10x_rcu.h:339
RCU_FLAG_HXTALSTB
Definition: gd32f10x_rcu.h:506
BDCTL_REG_OFFSET
#define BDCTL_REG_OFFSET
Definition: gd32f10x_rcu.h:343
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_rcu.h:325
CTL_REG_OFFSET
#define CTL_REG_OFFSET
Definition: gd32f10x_rcu.h:342
rcu_flag_enum
rcu_flag_enum
Definition: gd32f10x_rcu.h:502
RCU_FLAG_PLL2STB
Definition: gd32f10x_rcu.h:510
RCU_FLAG_LXTALSTB
Definition: gd32f10x_rcu.h:512
RCU_FLAG_PLLSTB
Definition: gd32f10x_rcu.h:507
RCU_FLAG_SWRST
Definition: gd32f10x_rcu.h:517
RCU_FLAG_IRC8MSTB
Definition: gd32f10x_rcu.h:505
RCU_FLAG_IRC40KSTB
Definition: gd32f10x_rcu.h:513
RCU_FLAG_FWDGTRST
Definition: gd32f10x_rcu.h:518
RCU_FLAG_WWDGTRST
Definition: gd32f10x_rcu.h:519
RCU_FLAG_EPRST
Definition: gd32f10x_rcu.h:515
enum rcu_int_enum
Enumerator
RCU_INT_IRC40KSTB | IRC40K stabilization interrupt
RCU_INT_LXTALSTB | LXTAL stabilization interrupt
RCU_INT_IRC8MSTB | IRC8M stabilization interrupt
RCU_INT_HXTALSTB | HXTAL stabilization interrupt
RCU_INT_PLLSTB | PLL stabilization interrupt
RCU_INT_PLL1STB | PLL1 stabilization interrupt
RCU_INT_PLL2STB | PLL2 stabilization interrupt

Definition at line 554 of file gd32f10x_rcu.h.

555 {
556 RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U),
557 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U),
558 RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U),
559 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U),
560 RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U),
561 #ifdef GD32F10X_CL
562 RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U),
563 RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U),
564 #endif /* GD32F10X_CL */
565 }rcu_int_enum;
RCU_INT_PLL2STB
Definition: gd32f10x_rcu.h:563
INT_REG_OFFSET
#define INT_REG_OFFSET
Definition: gd32f10x_rcu.h:346
rcu_int_enum
rcu_int_enum
Definition: gd32f10x_rcu.h:554
RCU_INT_PLL1STB
Definition: gd32f10x_rcu.h:562
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_rcu.h:325
RCU_INT_LXTALSTB
Definition: gd32f10x_rcu.h:557
RCU_INT_IRC8MSTB
Definition: gd32f10x_rcu.h:558
RCU_INT_IRC40KSTB
Definition: gd32f10x_rcu.h:556
RCU_INT_HXTALSTB
Definition: gd32f10x_rcu.h:559
RCU_INT_PLLSTB
Definition: gd32f10x_rcu.h:560
enum rcu_int_flag_clear_enum
Enumerator
RCU_INT_FLAG_IRC40KSTB_CLR | IRC40K stabilization interrupt flags clear
RCU_INT_FLAG_LXTALSTB_CLR | LXTAL stabilization interrupt flags clear
RCU_INT_FLAG_IRC8MSTB_CLR | IRC8M stabilization interrupt flags clear
RCU_INT_FLAG_HXTALSTB_CLR | HXTAL stabilization interrupt flags clear
RCU_INT_FLAG_PLLSTB_CLR | PLL stabilization interrupt flags clear
RCU_INT_FLAG_PLL1STB_CLR | PLL1 stabilization interrupt flags clear
RCU_INT_FLAG_PLL2STB_CLR | PLL2 stabilization interrupt flags clear
RCU_INT_FLAG_CKM_CLR | CKM interrupt flags clear

Definition at line 539 of file gd32f10x_rcu.h.

540 {
541 RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U),
542 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U),
543 RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U),
544 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U),
545 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U),
546 #ifdef GD32F10X_CL
547 RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U),
548 RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U),
549 #endif /* GD32F10X_CL */
550 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U),
551 }rcu_int_flag_clear_enum;
RCU_INT_FLAG_HXTALSTB_CLR
Definition: gd32f10x_rcu.h:544
INT_REG_OFFSET
#define INT_REG_OFFSET
Definition: gd32f10x_rcu.h:346
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_rcu.h:325
RCU_INT_FLAG_CKM_CLR
Definition: gd32f10x_rcu.h:550
RCU_INT_FLAG_PLLSTB_CLR
Definition: gd32f10x_rcu.h:545
RCU_INT_FLAG_LXTALSTB_CLR
Definition: gd32f10x_rcu.h:542
RCU_INT_FLAG_PLL2STB_CLR
Definition: gd32f10x_rcu.h:548
RCU_INT_FLAG_PLL1STB_CLR
Definition: gd32f10x_rcu.h:547
RCU_INT_FLAG_IRC8MSTB_CLR
Definition: gd32f10x_rcu.h:543
RCU_INT_FLAG_IRC40KSTB_CLR
Definition: gd32f10x_rcu.h:541
rcu_int_flag_clear_enum
rcu_int_flag_clear_enum
Definition: gd32f10x_rcu.h:539
enum rcu_int_flag_enum
Enumerator
RCU_INT_FLAG_IRC40KSTB | IRC40K stabilization interrupt flag
RCU_INT_FLAG_LXTALSTB | LXTAL stabilization interrupt flag
RCU_INT_FLAG_IRC8MSTB | IRC8M stabilization interrupt flag
RCU_INT_FLAG_HXTALSTB | HXTAL stabilization interrupt flag
RCU_INT_FLAG_PLLSTB | PLL stabilization interrupt flag
RCU_INT_FLAG_PLL1STB | PLL1 stabilization interrupt flag
RCU_INT_FLAG_PLL2STB | PLL2 stabilization interrupt flag
RCU_INT_FLAG_CKM | HXTAL clock stuck interrupt flag

Definition at line 524 of file gd32f10x_rcu.h.

525 {
526 RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U),
527 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U),
528 RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U),
529 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U),
530 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U),
531 #ifdef GD32F10X_CL
532 RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U),
533 RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U),
534 #endif /* GD32F10X_CL */
535 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U),
536 }rcu_int_flag_enum;
RCU_INT_FLAG_HXTALSTB
Definition: gd32f10x_rcu.h:529
RCU_INT_FLAG_LXTALSTB
Definition: gd32f10x_rcu.h:527
RCU_INT_FLAG_PLLSTB
Definition: gd32f10x_rcu.h:530
INT_REG_OFFSET
#define INT_REG_OFFSET
Definition: gd32f10x_rcu.h:346
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_rcu.h:325
RCU_INT_FLAG_CKM
Definition: gd32f10x_rcu.h:535
rcu_int_flag_enum
rcu_int_flag_enum
Definition: gd32f10x_rcu.h:524
RCU_INT_FLAG_PLL2STB
Definition: gd32f10x_rcu.h:533
RCU_INT_FLAG_PLL1STB
Definition: gd32f10x_rcu.h:532
RCU_INT_FLAG_IRC8MSTB
Definition: gd32f10x_rcu.h:528
RCU_INT_FLAG_IRC40KSTB
Definition: gd32f10x_rcu.h:526
enum rcu_osci_type_enum
Enumerator
RCU_HXTAL | HXTAL
RCU_LXTAL | LXTAL
RCU_IRC8M | IRC8M
RCU_IRC40K | IRC40K
RCU_PLL_CK | PLL
RCU_PLL1_CK | PLL1
RCU_PLL2_CK | PLL2

Definition at line 568 of file gd32f10x_rcu.h.

569 {
570 RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U),
571 RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U),
572 RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U),
573 RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U),
574 RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U),
575 #ifdef GD32F10X_CL
576 RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U),
577 RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U),
578 #endif /* GD32F10X_CL */
579 }rcu_osci_type_enum;
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
RSTSCK_REG_OFFSET
#define RSTSCK_REG_OFFSET
Definition: gd32f10x_rcu.h:339
BDCTL_REG_OFFSET
#define BDCTL_REG_OFFSET
Definition: gd32f10x_rcu.h:343
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_rcu.h:325
CTL_REG_OFFSET
#define CTL_REG_OFFSET
Definition: gd32f10x_rcu.h:342
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
rcu_osci_type_enum
rcu_osci_type_enum
Definition: gd32f10x_rcu.h:568
RCU_PLL1_CK
Definition: gd32f10x_rcu.h:576
RCU_IRC40K
Definition: gd32f10x_rcu.h:573
RCU_PLL2_CK
Definition: gd32f10x_rcu.h:577
RCU_LXTAL
Definition: gd32f10x_rcu.h:571
enum rcu_periph_enum
Enumerator
RCU_DMA0 | DMA0 clock
RCU_DMA1 | DMA1 clock
RCU_CRC | CRC clock
RCU_EXMC | EXMC clock
RCU_SDIO | SDIO clock
RCU_TIMER1 | TIMER1 clock
RCU_TIMER2 | TIMER2 clock
RCU_TIMER3 | TIMER3 clock
RCU_TIMER4 | TIMER4 clock
RCU_TIMER5 | TIMER5 clock
RCU_TIMER6 | TIMER6 clock
RCU_TIMER11 | TIMER11 clock
RCU_TIMER12 | TIMER12 clock
RCU_TIMER13 | TIMER13 clock
RCU_WWDGT | WWDGT clock
RCU_SPI1 | SPI1 clock
RCU_SPI2 | SPI2 clock
RCU_USART1 | USART1 clock
RCU_USART2 | USART2 clock
RCU_UART3 | UART3 clock
RCU_UART4 | UART4 clock
RCU_I2C0 | I2C0 clock
RCU_I2C1 | I2C1 clock
RCU_USBD | USBD clock
RCU_CAN0 | CAN0 clock
RCU_CAN1 | CAN1 clock
RCU_BKPI | BKPI clock
RCU_PMU | PMU clock
RCU_DAC | DAC clock
RCU_RTC | RTC clock
RCU_AF | alternate function clock
RCU_GPIOA | GPIOA clock
RCU_GPIOB | GPIOB clock
RCU_GPIOC | GPIOC clock
RCU_GPIOD | GPIOD clock
RCU_GPIOE | GPIOE clock
RCU_GPIOF | GPIOF clock
RCU_GPIOG | GPIOG clock
RCU_ADC0 | ADC0 clock
RCU_ADC1 | ADC1 clock
RCU_TIMER0 | TIMER0 clock
RCU_SPI0 | SPI0 clock
RCU_TIMER7 | TIMER7 clock
RCU_USART0 | USART0 clock
RCU_TIMER8 | TIMER8 clock
RCU_TIMER9 | TIMER9 clock
RCU_TIMER10 | TIMER10 clock

Definition at line 353 of file gd32f10x_rcu.h.

354 {
355 /* AHB peripherals */
356 RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U),
357 RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U),
358 RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U),
359 RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U),
360 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
361 RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U),
362 #elif defined(GD32F10X_CL)
363 RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U),
364 RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U),
365 RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U),
366 RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U),
367 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
368
369 /* APB1 peripherals */
370 RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U),
371 RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U),
372 RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U),
373 RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U),
374 RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U),
375 RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U),
376 #if defined(GD32F10X_XD)
377 RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U),
378 RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U),
379 RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U),
380 #endif /* GD32F10X_XD */
381 RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U),
382 RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U),
383 RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U),
384 RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U),
385 RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U),
386 RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U),
387 RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U),
388 RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U),
389 RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U),
390 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
391 RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U),
392 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
393 RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U),
394 #ifdef GD32F10X_CL
395 RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U),
396 #endif /* GD32F10X_CL */
397 RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U),
398 RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U),
399 RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U),
400 RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U),
402 /* APB2 peripherals */
403 RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U),
404 RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U),
405 RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U),
406 RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U),
407 RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U),
408 RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U),
409 RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U),
410 RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U),
411 RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U),
412 RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U),
413 RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U),
414 RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U),
415 RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U),
416 RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U),
417 #ifndef GD32F10X_CL
418 RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U),
419 #endif /* GD32F10X_CL */
420 #ifdef GD32F10X_XD
421 RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U),
422 RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U),
423 RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U),
424 #endif /* GD32F10X_XD */
425 }rcu_periph_enum;
RCU_USART1
Definition: gd32f10x_rcu.h:384
RCU_TIMER11
Definition: gd32f10x_rcu.h:377
RCU_SPI0
Definition: gd32f10x_rcu.h:414
RCU_TIMER10
Definition: gd32f10x_rcu.h:423
RCU_AF
Definition: gd32f10x_rcu.h:403
BDCTL_REG_OFFSET
#define BDCTL_REG_OFFSET
Definition: gd32f10x_rcu.h:343
RCU_TIMER5
Definition: gd32f10x_rcu.h:374
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_rcu.h:325
RCU_WWDGT
Definition: gd32f10x_rcu.h:381
RCU_RTC
Definition: gd32f10x_rcu.h:400
RCU_GPIOG
Definition: gd32f10x_rcu.h:410
RCU_TIMER8
Definition: gd32f10x_rcu.h:421
RCU_GPIOE
Definition: gd32f10x_rcu.h:408
RCU_ADC0
Definition: gd32f10x_rcu.h:411
RCU_BKPI
Definition: gd32f10x_rcu.h:397
RCU_SPI2
Definition: gd32f10x_rcu.h:383
RCU_DAC
Definition: gd32f10x_rcu.h:399
RCU_DMA1
Definition: gd32f10x_rcu.h:357
RCU_TIMER6
Definition: gd32f10x_rcu.h:375
APB2EN_REG_OFFSET
#define APB2EN_REG_OFFSET
Definition: gd32f10x_rcu.h:333
RCU_DMA0
Definition: gd32f10x_rcu.h:356
RCU_UART4
Definition: gd32f10x_rcu.h:387
RCU_USBD
Definition: gd32f10x_rcu.h:391
AHBEN_REG_OFFSET
#define AHBEN_REG_OFFSET
Definition: gd32f10x_rcu.h:331
RCU_TIMER2
Definition: gd32f10x_rcu.h:371
RCU_TIMER4
Definition: gd32f10x_rcu.h:373
RCU_CRC
Definition: gd32f10x_rcu.h:358
RCU_TIMER12
Definition: gd32f10x_rcu.h:378
RCU_GPIOC
Definition: gd32f10x_rcu.h:406
RCU_TIMER13
Definition: gd32f10x_rcu.h:379
RCU_SPI1
Definition: gd32f10x_rcu.h:382
RCU_USART0
Definition: gd32f10x_rcu.h:416
RCU_I2C1
Definition: gd32f10x_rcu.h:389
RCU_GPIOA
Definition: gd32f10x_rcu.h:404
RCU_UART3
Definition: gd32f10x_rcu.h:386
RCU_EXMC
Definition: gd32f10x_rcu.h:359
RCU_GPIOD
Definition: gd32f10x_rcu.h:407
RCU_TIMER1
Definition: gd32f10x_rcu.h:370
RCU_CAN1
Definition: gd32f10x_rcu.h:395
RCU_SDIO
Definition: gd32f10x_rcu.h:361
RCU_TIMER3
Definition: gd32f10x_rcu.h:372
RCU_TIMER0
Definition: gd32f10x_rcu.h:413
RCU_USART2
Definition: gd32f10x_rcu.h:385
APB1EN_REG_OFFSET
#define APB1EN_REG_OFFSET
Definition: gd32f10x_rcu.h:332
RCU_TIMER7
Definition: gd32f10x_rcu.h:415
RCU_I2C0
Definition: gd32f10x_rcu.h:388
RCU_CAN0
Definition: gd32f10x_rcu.h:393
RCU_TIMER9
Definition: gd32f10x_rcu.h:422
RCU_ADC1
Definition: gd32f10x_rcu.h:412
RCU_GPIOF
Definition: gd32f10x_rcu.h:409
rcu_periph_enum
rcu_periph_enum
Definition: gd32f10x_rcu.h:353
RCU_GPIOB
Definition: gd32f10x_rcu.h:405
RCU_PMU
Definition: gd32f10x_rcu.h:398
enum rcu_periph_reset_enum
Enumerator
RCU_USBFSRST | USBFS clock reset
RCU_ENETRST | ENET clock reset
RCU_TIMER1RST | TIMER1 clock reset
RCU_TIMER2RST | TIMER2 clock reset
RCU_TIMER3RST | TIMER3 clock reset
RCU_TIMER4RST | TIMER4 clock reset
RCU_TIMER5RST | TIMER5 clock reset
RCU_TIMER6RST | TIMER6 clock reset
RCU_TIMER11RST | TIMER11 clock reset
RCU_TIMER12RST | TIMER12 clock reset
RCU_TIMER13RST | TIMER13 clock reset
RCU_WWDGTRST | WWDGT clock reset
RCU_SPI1RST | SPI1 clock reset
RCU_SPI2RST | SPI2 clock reset
RCU_USART1RST | USART1 clock reset
RCU_USART2RST | USART2 clock reset
RCU_UART3RST | UART3 clock reset
RCU_UART4RST | UART4 clock reset
RCU_I2C0RST | I2C0 clock reset
RCU_I2C1RST | I2C1 clock reset
RCU_USBDRST | USBD clock reset
RCU_CAN0RST | CAN0 clock reset
RCU_CAN1RST | CAN1 clock reset
RCU_BKPIRST | BKPI clock reset
RCU_PMURST | PMU clock reset
RCU_DACRST | DAC clock reset
RCU_AFRST | alternate function clock reset
RCU_GPIOARST | GPIOA clock reset
RCU_GPIOBRST | GPIOB clock reset
RCU_GPIOCRST | GPIOC clock reset
RCU_GPIODRST | GPIOD clock reset
RCU_GPIOERST | GPIOE clock reset
RCU_GPIOFRST | GPIOF clock reset
RCU_GPIOGRST | GPIOG clock reset
RCU_ADC0RST | ADC0 clock reset
RCU_ADC1RST | ADC1 clock reset
RCU_TIMER0RST | TIMER0 clock reset
RCU_SPI0RST | SPI0 clock reset
RCU_TIMER7RST | TIMER7 clock reset
RCU_USART0RST | USART0 clock reset
RCU_TIMER8RST | TIMER8 clock reset
RCU_TIMER9RST | TIMER9 clock reset
RCU_TIMER10RST | TIMER10 clock reset

Definition at line 436 of file gd32f10x_rcu.h.

437 {
438 /* AHB peripherals */
439 #ifdef GD32F10X_CL
440 RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U),
441 RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U),
442 #endif /* GD32F10X_CL */
443
444 /* APB1 peripherals */
445 RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U),
446 RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U),
447 RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U),
448 RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U),
449 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U),
450 RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U),
451 #ifdef GD32F10X_XD
452 RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U),
453 RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U),
454 RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U),
455 #endif /* GD32F10X_XD */
456 RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U),
457 RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U),
458 RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U),
459 RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U),
460 RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U),
461 RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U),
462 RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U),
463 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U),
464 RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U),
465 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
466 RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U),
467 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
468 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U),
469 #ifdef GD32F10X_CL
470 RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U),
471 #endif /* GD32F10X_CL */
472 RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U),
473 RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U),
474 RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U),
476 /* APB2 peripherals */
477 RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U),
478 RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U),
479 RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U),
480 RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U),
481 RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U),
482 RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U),
483 RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U),
484 RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U),
485 RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U),
486 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U),
487 RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U),
488 RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U),
489 RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U),
490 RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U),
491 #ifndef GD32F10X_CL
492 RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U),
493 #endif /* GD32F10X_CL */
494 #ifdef GD32F10X_XD
495 RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U),
496 RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U),
497 RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U),
498 #endif /* GD32F10X_XD */
499 }rcu_periph_reset_enum;
RCU_ENETRST
Definition: gd32f10x_rcu.h:441
RCU_TIMER11RST
Definition: gd32f10x_rcu.h:452
RCU_USART1RST
Definition: gd32f10x_rcu.h:459
RCU_I2C0RST
Definition: gd32f10x_rcu.h:463
RCU_GPIOGRST
Definition: gd32f10x_rcu.h:484
RCU_BKPIRST
Definition: gd32f10x_rcu.h:472
RCU_TIMER2RST
Definition: gd32f10x_rcu.h:446
RCU_I2C1RST
Definition: gd32f10x_rcu.h:464
RCU_CAN0RST
Definition: gd32f10x_rcu.h:468
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_rcu.h:325
RCU_GPIOBRST
Definition: gd32f10x_rcu.h:479
RCU_SPI1RST
Definition: gd32f10x_rcu.h:457
RCU_TIMER8RST
Definition: gd32f10x_rcu.h:495
RCU_TIMER7RST
Definition: gd32f10x_rcu.h:489
RCU_TIMER5RST
Definition: gd32f10x_rcu.h:449
RCU_ADC0RST
Definition: gd32f10x_rcu.h:485
AHBRST_REG_OFFSET
#define AHBRST_REG_OFFSET
Definition: gd32f10x_rcu.h:336
RCU_TIMER4RST
Definition: gd32f10x_rcu.h:448
RCU_TIMER6RST
Definition: gd32f10x_rcu.h:450
RCU_GPIOFRST
Definition: gd32f10x_rcu.h:483
RCU_AFRST
Definition: gd32f10x_rcu.h:477
RCU_GPIODRST
Definition: gd32f10x_rcu.h:481
RCU_WWDGTRST
Definition: gd32f10x_rcu.h:456
APB1RST_REG_OFFSET
#define APB1RST_REG_OFFSET
Definition: gd32f10x_rcu.h:337
RCU_DACRST
Definition: gd32f10x_rcu.h:474
RCU_GPIOARST
Definition: gd32f10x_rcu.h:478
RCU_USBDRST
Definition: gd32f10x_rcu.h:466
RCU_TIMER1RST
Definition: gd32f10x_rcu.h:445
RCU_TIMER9RST
Definition: gd32f10x_rcu.h:496
RCU_TIMER12RST
Definition: gd32f10x_rcu.h:453
RCU_SPI2RST
Definition: gd32f10x_rcu.h:458
RCU_PMURST
Definition: gd32f10x_rcu.h:473
RCU_TIMER10RST
Definition: gd32f10x_rcu.h:497
RCU_USBFSRST
Definition: gd32f10x_rcu.h:440
RCU_SPI0RST
Definition: gd32f10x_rcu.h:488
APB2RST_REG_OFFSET
#define APB2RST_REG_OFFSET
Definition: gd32f10x_rcu.h:338
RCU_GPIOCRST
Definition: gd32f10x_rcu.h:480
RCU_USART0RST
Definition: gd32f10x_rcu.h:490
RCU_USART2RST
Definition: gd32f10x_rcu.h:460
RCU_TIMER3RST
Definition: gd32f10x_rcu.h:447
RCU_UART4RST
Definition: gd32f10x_rcu.h:462
RCU_ADC1RST
Definition: gd32f10x_rcu.h:486
RCU_CAN1RST
Definition: gd32f10x_rcu.h:470
RCU_UART3RST
Definition: gd32f10x_rcu.h:461
RCU_GPIOERST
Definition: gd32f10x_rcu.h:482
RCU_TIMER0RST
Definition: gd32f10x_rcu.h:487
RCU_TIMER13RST
Definition: gd32f10x_rcu.h:454
rcu_periph_reset_enum
rcu_periph_reset_enum
Definition: gd32f10x_rcu.h:436
enum rcu_periph_sleep_enum
Enumerator
RCU_SRAM_SLP | SRAM clock
RCU_FMC_SLP | FMC clock

Definition at line 428 of file gd32f10x_rcu.h.

429 {
430 /* AHB peripherals */
431 RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U),
432 RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U),
433 }rcu_periph_sleep_enum;
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_rcu.h:325
rcu_periph_sleep_enum
rcu_periph_sleep_enum
Definition: gd32f10x_rcu.h:428
AHBEN_REG_OFFSET
#define AHBEN_REG_OFFSET
Definition: gd32f10x_rcu.h:331
RCU_SRAM_SLP
Definition: gd32f10x_rcu.h:431
RCU_FMC_SLP
Definition: gd32f10x_rcu.h:432

Function Documentation

void rcu_adc_clock_config ( uint32_t adc_psc )

configure the ADC prescaler factor

Parameters
[in] adc_psc ADC prescaler factor
  • RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2
  • RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4
  • RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6
  • RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8
  • RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12
  • RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16
[out] none
Return values
none

Definition at line 493 of file gd32f10x_rcu.c.

494 {
495 uint32_t reg0;
496
497 /* reset the ADCPSC bits */
498 reg0 = RCU_CFG0;
499 reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC);
500
501 /* set the ADC prescaler factor */
502 switch(adc_psc){
503 case RCU_CKADC_CKAPB2_DIV2:
504 case RCU_CKADC_CKAPB2_DIV4:
505 case RCU_CKADC_CKAPB2_DIV6:
506 case RCU_CKADC_CKAPB2_DIV8:
507 reg0 |= (adc_psc << 14);
508 break;
509
510 case RCU_CKADC_CKAPB2_DIV12:
511 case RCU_CKADC_CKAPB2_DIV16:
512 adc_psc &= ~BIT(2);
513 reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2);
514 break;
515
516 default:
517 break;
518 }
519
520 /* set the register */
521 RCU_CFG0 = reg0;
522 }
RCU_CKADC_CKAPB2_DIV8
#define RCU_CKADC_CKAPB2_DIV8
Definition: gd32f10x_rcu.h:635
RCU_CKADC_CKAPB2_DIV2
#define RCU_CKADC_CKAPB2_DIV2
Definition: gd32f10x_rcu.h:632
RCU_CFG0_ADCPSC_2
#define RCU_CFG0_ADCPSC_2
Definition: gd32f10x_rcu.h:94
RCU_CKADC_CKAPB2_DIV4
#define RCU_CKADC_CKAPB2_DIV4
Definition: gd32f10x_rcu.h:633
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f10x_rcu.h:87
RCU_CKADC_CKAPB2_DIV16
#define RCU_CKADC_CKAPB2_DIV16
Definition: gd32f10x_rcu.h:637
RCU_CKADC_CKAPB2_DIV12
#define RCU_CKADC_CKAPB2_DIV12
Definition: gd32f10x_rcu.h:636
RCU_CKADC_CKAPB2_DIV6
#define RCU_CKADC_CKAPB2_DIV6
Definition: gd32f10x_rcu.h:634
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_ahb_clock_config ( uint32_t ck_ahb )

configure the AHB clock prescaler selection

Parameters
[in] ck_ahb AHB clock prescaler selection only one parameter can be selected which is shown as below:
  • RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
[out] none
Return values
none

Definition at line 281 of file gd32f10x_rcu.c.

282 {
283 uint32_t reg;
284
285 reg = RCU_CFG0;
286
287 /* reset the AHBPSC bits and set according to ck_ahb */
288 reg &= ~RCU_CFG0_AHBPSC;
289 RCU_CFG0 = (reg | ck_ahb);
290 }
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f10x_rcu.h:84
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_all_reset_flag_clear ( void )

clear all the reset flag

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 647 of file gd32f10x_rcu.c.

648 {
649 RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
650 }
RCU_RSTSCK_RSTFC
#define RCU_RSTSCK_RSTFC
Definition: gd32f10x_rcu.h:295
RCU_RSTSCK
#define RCU_RSTSCK
Definition: gd32f10x_rcu.h:32
void rcu_apb1_clock_config ( uint32_t ck_apb1 )

configure the APB1 clock prescaler selection

Parameters
[in] ck_apb1 APB1 clock prescaler selection only one parameter can be selected which is shown as below:
  • RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
  • RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
  • RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
  • RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
  • RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
[out] none
Return values
none

Definition at line 304 of file gd32f10x_rcu.c.

305 {
306 uint32_t reg;
307
308 reg = RCU_CFG0;
309
310 /* reset the APB1PSC and set according to ck_apb1 */
311 reg &= ~RCU_CFG0_APB1PSC;
312 RCU_CFG0 = (reg | ck_apb1);
313 }
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f10x_rcu.h:85
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_apb2_clock_config ( uint32_t ck_apb2 )

configure the APB2 clock prescaler selection

Parameters
[in] ck_apb2 APB2 clock prescaler selection only one parameter can be selected which is shown as below:
  • RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
  • RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
  • RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
  • RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
  • RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
[out] none
Return values
none

Definition at line 327 of file gd32f10x_rcu.c.

328 {
329 uint32_t reg;
330
331 reg = RCU_CFG0;
332
333 /* reset the APB2PSC and set according to ck_apb2 */
334 reg &= ~RCU_CFG0_APB2PSC;
335 RCU_CFG0 = (reg | ck_apb2);
336 }
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f10x_rcu.h:86
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_bkp_reset_disable ( void )

disable the BKP domain reset

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 234 of file gd32f10x_rcu.c.

235 {
236 RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
237 }
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f10x_rcu.h:290
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
void rcu_bkp_reset_enable ( void )

reset the BKP domain

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 223 of file gd32f10x_rcu.c.

224 {
225 RCU_BDCTL |= RCU_BDCTL_BKPRST;
226 }
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f10x_rcu.h:290
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
void rcu_ckout0_config ( uint32_t ckout0_src )

configure the CK_OUT0 clock source

Parameters
[in] ckout0_src CK_OUT0 clock source selection only one parameter can be selected which is shown as below:
  • RCU_CKOUT0SRC_NONE: no clock selected
  • RCU_CKOUT0SRC_CKSYS: system clock selected
  • RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected
  • RCU_CKOUT0SRC_HXTAL: HXTAL selected
  • RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected
  • RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected
  • RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected
  • RCU_CKOUT0SRC_EXT1: EXT1 selected
  • RCU_CKOUT0SRC_CKPLL2: PLL selected
[out] none
Return values
none

Definition at line 354 of file gd32f10x_rcu.c.

355 {
356 uint32_t reg;
357
358 reg = RCU_CFG0;
359
360 /* reset the CKOUT0SRC, set according to ckout0_src */
361 reg &= ~RCU_CFG0_CKOUT0SEL;
362 RCU_CFG0 = (reg | ckout0_src);
363 }
RCU_CFG0_CKOUT0SEL
#define RCU_CFG0_CKOUT0SEL
Definition: gd32f10x_rcu.h:92
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
uint32_t rcu_clock_freq_get ( rcu_clock_freq_enum clock )

get the system clock, bus and peripheral clock frequency

Parameters
[in] clock the clock frequency which to get only one parameter can be selected which is shown as below:
  • CK_SYS: system clock frequency
  • CK_AHB: AHB clock frequency
  • CK_APB1: APB1 clock frequency
  • CK_APB2: APB2 clock frequency
[out] none
Return values
clock frequency of system, AHB, APB1, APB2

Definition at line 1039 of file gd32f10x_rcu.c.

1040 {
1041 uint32_t sws, ck_freq = 0U;
1042 uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq;
1043 uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp;
1044 #ifdef GD32F10X_CL
1045 uint32_t predv0, predv1, pll1mf;
1046 #endif /* GD32F10X_CL */
1047
1048 /* exponent of AHB, APB1 and APB2 clock divider */
1049 uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
1050 uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
1051 uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
1052
1053 sws = GET_BITS(RCU_CFG0, 2, 3);
1054 switch(sws){
1055 /* IRC8M is selected as CK_SYS */
1056 case SEL_IRC8M:
1057 cksys_freq = IRC8M_VALUE;
1058 break;
1059 /* HXTAL is selected as CK_SYS */
1060 case SEL_HXTAL:
1061 cksys_freq = HXTAL_VALUE;
1062 break;
1063 /* PLL is selected as CK_SYS */
1064 case SEL_PLL:
1065 /* PLL clock source selection, HXTAL or IRC8M/2 */
1066 pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
1067
1068 if(RCU_PLLSRC_HXTAL == pllsel) {
1069 /* PLL clock source is HXTAL */
1070 ck_src = HXTAL_VALUE;
1071
1072 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
1073 predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0);
1074 /* PREDV0 input source clock divided by 2 */
1075 if(RCU_CFG0_PREDV0 == predv0sel){
1076 ck_src = HXTAL_VALUE/2U;
1077 }
1078 #elif defined(GD32F10X_CL)
1079 predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
1080 /* source clock use PLL1 */
1081 if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
1082 predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
1083 pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
1084 if(17U == pll1mf){
1085 pll1mf = 20U;
1086 }
1087 ck_src = (ck_src / predv1) * pll1mf;
1088 }
1089 predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
1090 ck_src /= predv0;
1091 #endif /* GD32F10X_HD and GD32F10X_XD */
1092 }else{
1093 /* PLL clock source is IRC8M/2 */
1094 ck_src = IRC8M_VALUE/2U;
1095 }
1096
1097 /* PLL multiplication factor */
1098 pllmf = GET_BITS(RCU_CFG0, 18, 21);
1099 if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
1100 pllmf |= 0x10U;
1101 }
1102 if(pllmf < 15U){
1103 pllmf += 2U;
1104 }else{
1105 pllmf += 1U;
1106 }
1107
1108 cksys_freq = ck_src * pllmf;
1109
1110 #ifdef GD32F10X_CL
1111 if(15U == pllmf){
1112 /* PLL source clock multiply by 6.5 */
1113 cksys_freq = ck_src * 6U + ck_src / 2U;
1114 }
1115 #endif /* GD32F10X_CL */
1116
1117 break;
1118 /* IRC8M is selected as CK_SYS */
1119 default:
1120 cksys_freq = IRC8M_VALUE;
1121 break;
1122 }
1123
1124 /* calculate AHB clock frequency */
1125 idx = GET_BITS(RCU_CFG0, 4, 7);
1126 clk_exp = ahb_exp[idx];
1127 ahb_freq = cksys_freq >> clk_exp;
1128
1129 /* calculate APB1 clock frequency */
1130 idx = GET_BITS(RCU_CFG0, 8, 10);
1131 clk_exp = apb1_exp[idx];
1132 apb1_freq = ahb_freq >> clk_exp;
1133
1134 /* calculate APB2 clock frequency */
1135 idx = GET_BITS(RCU_CFG0, 11, 13);
1136 clk_exp = apb2_exp[idx];
1137 apb2_freq = ahb_freq >> clk_exp;
1138
1139 /* return the clocks frequency */
1140 switch(clock){
1141 case CK_SYS:
1142 ck_freq = cksys_freq;
1143 break;
1144 case CK_AHB:
1145 ck_freq = ahb_freq;
1146 break;
1147 case CK_APB1:
1148 ck_freq = apb1_freq;
1149 break;
1150 case CK_APB2:
1151 ck_freq = apb2_freq;
1152 break;
1153 default:
1154 break;
1155 }
1156 return ck_freq;
1157 }
SEL_HXTAL
#define SEL_HXTAL
Definition: gd32f10x_rcu.c:17
RCU_CFG0_PREDV0
#define RCU_CFG0_PREDV0
Definition: gd32f10x_rcu.h:89
SEL_IRC8M
#define SEL_IRC8M
Definition: gd32f10x_rcu.c:16
RCU_PLLSRC_HXTAL
#define RCU_PLLSRC_HXTAL
Definition: gd32f10x_rcu.h:641
CK_SYS
Definition: gd32f10x_rcu.h:584
RCU_PREDV0SRC_CKPLL1
#define RCU_PREDV0SRC_CKPLL1
Definition: gd32f10x_rcu.h:778
RCU_CFG1_PREDV0
#define RCU_CFG1_PREDV0
Definition: gd32f10x_rcu.h:311
RCU_CFG1_PREDV1
#define RCU_CFG1_PREDV1
Definition: gd32f10x_rcu.h:312
RCU_CFG1_PLL1MF
#define RCU_CFG1_PLL1MF
Definition: gd32f10x_rcu.h:313
CK_APB2
Definition: gd32f10x_rcu.h:587
CK_AHB
Definition: gd32f10x_rcu.h:585
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f10x_rcu.h:88
SEL_PLL
#define SEL_PLL
Definition: gd32f10x_rcu.c:18
RCU_CFG0_PLLMF_4
#define RCU_CFG0_PLLMF_4
Definition: gd32f10x_rcu.h:93
CK_APB1
Definition: gd32f10x_rcu.h:586
RCU_CFG1_PREDV0SEL
#define RCU_CFG1_PREDV0SEL
Definition: gd32f10x_rcu.h:315
void rcu_deepsleep_voltage_set ( uint32_t dsvol )

deep-sleep mode voltage select

Parameters
[in] dsvol deep sleep mode voltage only one parameter can be selected which is shown as below:
  • RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V
  • RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V
  • RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
  • RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
[out] none
Return values
none

Definition at line 1022 of file gd32f10x_rcu.c.

1023 {
1024 dsvol &= RCU_DSV_DSLPVS;
1025 RCU_DSV = dsvol;
1026 }
RCU_DSV
#define RCU_DSV
Definition: gd32f10x_rcu.h:33
RCU_DSV_DSLPVS
#define RCU_DSV_DSLPVS
Definition: gd32f10x_rcu.h:321
void rcu_deinit ( void )

deinitialize the RCU

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 30 of file gd32f10x_rcu.c.

31 {
32 /* enable IRC8M */
33 RCU_CTL |= RCU_CTL_IRC8MEN;
34 rcu_osci_stab_wait(RCU_IRC8M);
35
36 /* reset CFG0 register */
37 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
38 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
39 RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF |
40 RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2);
41 #elif defined(GD32F10X_CL)
42 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
43 RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
44 RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4);
45 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
46 /* reset CTL register */
47 RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
48 RCU_CTL &= ~RCU_CTL_HXTALBPS;
49 #ifdef GD32F10X_CL
50 RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN);
51 #endif /* GD32F10X_CL */
52
53 /* reset INT and CFG1 register */
54 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
55 RCU_INT = 0x009f0000U;
56 #elif defined(GD32F10X_CL)
57 RCU_INT = 0x00ff0000U;
58 RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF |
59 RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL);
60 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
61 }
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f10x_rcu.h:90
RCU_INT
#define RCU_INT
Definition: gd32f10x_rcu.h:25
RCU_CFG0_PREDV0
#define RCU_CFG0_PREDV0
Definition: gd32f10x_rcu.h:89
RCU_CTL_PLLEN
#define RCU_CTL_PLLEN
Definition: gd32f10x_rcu.h:61
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_CFG0_CKOUT0SEL
#define RCU_CFG0_CKOUT0SEL
Definition: gd32f10x_rcu.h:92
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f10x_rcu.h:86
RCU_CFG0_ADCPSC_2
#define RCU_CFG0_ADCPSC_2
Definition: gd32f10x_rcu.h:94
RCU_CFG1_I2S1SEL
#define RCU_CFG1_I2S1SEL
Definition: gd32f10x_rcu.h:316
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
RCU_CFG1_PLL2MF
#define RCU_CFG1_PLL2MF
Definition: gd32f10x_rcu.h:314
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f10x_rcu.h:84
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f10x_rcu.h:87
rcu_osci_stab_wait
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
wait for oscillator stabilization flags is SET or oscillator startup is timeout
Definition: gd32f10x_rcu.c:749
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f10x_rcu.h:85
RCU_CTL_CKMEN
#define RCU_CTL_CKMEN
Definition: gd32f10x_rcu.h:60
RCU_CFG1_I2S2SEL
#define RCU_CFG1_I2S2SEL
Definition: gd32f10x_rcu.h:317
RCU_CFG1_PREDV0
#define RCU_CFG1_PREDV0
Definition: gd32f10x_rcu.h:311
RCU_CFG1_PREDV1
#define RCU_CFG1_PREDV1
Definition: gd32f10x_rcu.h:312
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f10x_rcu.h:82
RCU_CFG0_USBDPSC
#define RCU_CFG0_USBDPSC
Definition: gd32f10x_rcu.h:91
RCU_CFG1_PLL1MF
#define RCU_CFG1_PLL1MF
Definition: gd32f10x_rcu.h:313
RCU_CTL_HXTALBPS
#define RCU_CTL_HXTALBPS
Definition: gd32f10x_rcu.h:59
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
RCU_CTL_IRC8MEN
#define RCU_CTL_IRC8MEN
Definition: gd32f10x_rcu.h:53
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f10x_rcu.h:88
RCU_CFG0_PLLMF_4
#define RCU_CFG0_PLLMF_4
Definition: gd32f10x_rcu.h:93
RCU_CFG1_PREDV0SEL
#define RCU_CFG1_PREDV0SEL
Definition: gd32f10x_rcu.h:315
RCU_CTL_HXTALEN
#define RCU_CTL_HXTALEN
Definition: gd32f10x_rcu.h:57
FlagStatus rcu_flag_get ( rcu_flag_enum flag )

get the clock stabilization and periphral reset flags

Parameters
[in] flag the clock stabilization and periphral reset flags, refer to rcu_flag_enum only one parameter can be selected which is shown as below:
  • RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
  • RCU_FLAG_HXTALSTB: HXTAL stabilization flag
  • RCU_FLAG_PLLSTB: PLL stabilization flag
  • RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only)
  • RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only)
  • RCU_FLAG_LXTALSTB: LXTAL stabilization flag
  • RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
  • RCU_FLAG_EPRST: external PIN reset flag
  • RCU_FLAG_PORRST: power reset flag
  • RCU_FLAG_SWRST: software reset flag
  • RCU_FLAG_FWDGTRST: free watchdog timer reset flag
  • RCU_FLAG_WWDGTRST: window watchdog timer reset flag
  • RCU_FLAG_LPRST: low-power reset flag
[out] none
Return values
none

Definition at line 631 of file gd32f10x_rcu.c.

632 {
633 /* get the rcu flag */
634 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
635 return SET;
636 }else{
637 return RESET;
638 }
639 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_hxtal_clock_monitor_disable ( void )

disable the HXTAL clock monitor

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 990 of file gd32f10x_rcu.c.

991 {
992 RCU_CTL &= ~RCU_CTL_CKMEN;
993 }
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_CTL_CKMEN
#define RCU_CTL_CKMEN
Definition: gd32f10x_rcu.h:60
void rcu_hxtal_clock_monitor_enable ( void )

enable the HXTAL clock monitor

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 979 of file gd32f10x_rcu.c.

980 {
981 RCU_CTL |= RCU_CTL_CKMEN;
982 }
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_CTL_CKMEN
#define RCU_CTL_CKMEN
Definition: gd32f10x_rcu.h:60
void rcu_i2s1_clock_config ( uint32_t i2s_clock_source )

configure the I2S1 clock source selection

Parameters
[in] i2s_clock_source I2S1 clock source selection only one parameter can be selected which is shown as below:
  • RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock
  • RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock
[out] none
Return values
none

Definition at line 581 of file gd32f10x_rcu.c.

582 {
583 uint32_t reg;
584
585 reg = RCU_CFG1;
586 /* reset the I2S1SEL bit and set according to i2s_clock_source */
587 reg &= ~RCU_CFG1_I2S1SEL;
588 RCU_CFG1 = (reg | i2s_clock_source);
589 }
RCU_CFG1_I2S1SEL
#define RCU_CFG1_I2S1SEL
Definition: gd32f10x_rcu.h:316
void rcu_i2s2_clock_config ( uint32_t i2s_clock_source )

configure the I2S2 clock source selection

Parameters
[in] i2s_clock_source I2S2 clock source selection only one parameter can be selected which is shown as below:
  • RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock
  • RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock
[out] none
Return values
none

Definition at line 600 of file gd32f10x_rcu.c.

601 {
602 uint32_t reg;
603
604 reg = RCU_CFG1;
605 /* reset the I2S2SEL bit and set according to i2s_clock_source */
606 reg &= ~RCU_CFG1_I2S2SEL;
607 RCU_CFG1 = (reg | i2s_clock_source);
608 }
RCU_CFG1_I2S2SEL
#define RCU_CFG1_I2S2SEL
Definition: gd32f10x_rcu.h:317
void rcu_interrupt_disable ( rcu_int_enum stab_int )

disable the stabilization interrupt

Parameters
[in] stab_int clock stabilization interrupt, refer to rcu_int_enum only one parameter can be selected which is shown as below:
  • RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
  • RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
  • RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
  • RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
  • RCU_INT_PLLSTB: PLL stabilization interrupt enable
  • RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only)
  • RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only)
[out] none
Return values
none

Definition at line 730 of file gd32f10x_rcu.c.

731 {
732 RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
733 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_interrupt_enable ( rcu_int_enum stab_int )

enable the stabilization interrupt

Parameters
[in] stab_int clock stabilization interrupt, refer to rcu_int_enum Only one parameter can be selected which is shown as below:
  • RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
  • RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
  • RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
  • RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
  • RCU_INT_PLLSTB: PLL stabilization interrupt enable
  • RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only)
  • RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only)
[out] none
Return values
none

Definition at line 711 of file gd32f10x_rcu.c.

712 {
713 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
714 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_interrupt_flag_clear ( rcu_int_flag_clear_enum int_flag_clear )

clear the interrupt flags

Parameters
[in] int_flag_clear clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum only one parameter can be selected which is shown as below:
  • RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
  • RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
  • RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
  • RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
  • RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
  • RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only)
  • RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only)
  • RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
[out] none
Return values
none

Definition at line 692 of file gd32f10x_rcu.c.

693 {
694 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
695 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
FlagStatus rcu_interrupt_flag_get ( rcu_int_flag_enum int_flag )

get the clock stabilization interrupt and ckm flags

Parameters
[in] int_flag interrupt and ckm flags, refer to rcu_int_flag_enum only one parameter can be selected which is shown as below:
  • RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
  • RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
  • RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
  • RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
  • RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
  • RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only)
  • RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only)
  • RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 667 of file gd32f10x_rcu.c.

668 {
669 /* get the rcu interrupt flag */
670 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
671 return SET;
672 }else{
673 return RESET;
674 }
675 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_irc8m_adjust_value_set ( uint32_t irc8m_adjval )

set the IRC8M adjust value

Parameters
[in] | irc8m_adjval | IRC8M adjust value, must be between 0 and 0x1F
[out] | none
Return values
none

Definition at line 1001 of file gd32f10x_rcu.c.

1002 {
1003 uint32_t reg;
1004
1005 reg = RCU_CTL;
1006 /* reset the IRC8MADJ bits and set according to irc8m_adjval */
1007 reg &= ~RCU_CTL_IRC8MADJ;
1008 RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3));
1009 }
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_CTL_IRC8MADJ
#define RCU_CTL_IRC8MADJ
Definition: gd32f10x_rcu.h:55
void rcu_osci_bypass_mode_disable ( rcu_osci_type_enum osci )

disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
[out] none
Return values
none

Definition at line 942 of file gd32f10x_rcu.c.

943 {
944 uint32_t reg;
945
946 switch(osci){
947 /* disable HXTAL to bypass mode */
948 case RCU_HXTAL:
949 reg = RCU_CTL;
950 RCU_CTL &= ~RCU_CTL_HXTALEN;
951 RCU_CTL = (reg & ~RCU_CTL_HXTALBPS);
952 break;
953 /* disable LXTAL to bypass mode */
954 case RCU_LXTAL:
955 reg = RCU_BDCTL;
956 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
957 RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS);
958 break;
959 case RCU_IRC8M:
960 case RCU_IRC40K:
961 case RCU_PLL_CK:
962 #ifdef GD32F10X_CL
963 case RCU_PLL1_CK:
964 case RCU_PLL2_CK:
965 #endif /* GD32F10X_CL */
966 break;
967 default:
968 break;
969 }
970 }
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
RCU_PLL1_CK
Definition: gd32f10x_rcu.h:576
RCU_IRC40K
Definition: gd32f10x_rcu.h:573
RCU_CTL_HXTALBPS
#define RCU_CTL_HXTALBPS
Definition: gd32f10x_rcu.h:59
RCU_PLL2_CK
Definition: gd32f10x_rcu.h:577
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f10x_rcu.h:285
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f10x_rcu.h:287
RCU_LXTAL
Definition: gd32f10x_rcu.h:571
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
RCU_CTL_HXTALEN
#define RCU_CTL_HXTALEN
Definition: gd32f10x_rcu.h:57
void rcu_osci_bypass_mode_enable ( rcu_osci_type_enum osci )

enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
[out] none
Return values
none

Definition at line 903 of file gd32f10x_rcu.c.

904 {
905 uint32_t reg;
906
907 switch(osci){
908 /* enable HXTAL to bypass mode */
909 case RCU_HXTAL:
910 reg = RCU_CTL;
911 RCU_CTL &= ~RCU_CTL_HXTALEN;
912 RCU_CTL = (reg | RCU_CTL_HXTALBPS);
913 break;
914 /* enable LXTAL to bypass mode */
915 case RCU_LXTAL:
916 reg = RCU_BDCTL;
917 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
918 RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
919 break;
920 case RCU_IRC8M:
921 case RCU_IRC40K:
922 case RCU_PLL_CK:
923 #ifdef GD32F10X_CL
924 case RCU_PLL1_CK:
925 case RCU_PLL2_CK:
926 #endif /* GD32F10X_CL */
927 break;
928 default:
929 break;
930 }
931 }
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
RCU_PLL1_CK
Definition: gd32f10x_rcu.h:576
RCU_IRC40K
Definition: gd32f10x_rcu.h:573
RCU_CTL_HXTALBPS
#define RCU_CTL_HXTALBPS
Definition: gd32f10x_rcu.h:59
RCU_PLL2_CK
Definition: gd32f10x_rcu.h:577
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f10x_rcu.h:285
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f10x_rcu.h:287
RCU_LXTAL
Definition: gd32f10x_rcu.h:571
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
RCU_CTL_HXTALEN
#define RCU_CTL_HXTALEN
Definition: gd32f10x_rcu.h:57
void rcu_osci_off ( rcu_osci_type_enum osci )

turn off the oscillator

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
  • RCU_IRC8M: internal 8M RC oscillators(IRC8M)
  • RCU_IRC40K: internal 40K RC oscillator(IRC40K)
  • RCU_PLL_CK: phase locked loop(PLL)
  • RCU_PLL1_CK: phase locked loop 1(CL series only)
  • RCU_PLL2_CK: phase locked loop 2(CL series only)
[out] none
Return values
none

Definition at line 889 of file gd32f10x_rcu.c.

890 {
891 RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
892 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_osci_on ( rcu_osci_type_enum osci )

turn on the oscillator

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
  • RCU_IRC8M: internal 8M RC oscillators(IRC8M)
  • RCU_IRC40K: internal 40K RC oscillator(IRC40K)
  • RCU_PLL_CK: phase locked loop(PLL)
  • RCU_PLL1_CK: phase locked loop 1(CL series only)
  • RCU_PLL2_CK: phase locked loop 2(CL series only)
[out] none
Return values
none

Definition at line 870 of file gd32f10x_rcu.c.

871 {
872 RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
873 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
ErrStatus rcu_osci_stab_wait ( rcu_osci_type_enum osci )

wait for oscillator stabilization flags is SET or oscillator startup is timeout

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
  • RCU_IRC8M: internal 8M RC oscillators(IRC8M)
  • RCU_IRC40K: internal 40K RC oscillator(IRC40K)
  • RCU_PLL_CK: phase locked loop(PLL)
  • RCU_PLL1_CK: phase locked loop 1(CL series only)
  • RCU_PLL2_CK: phase locked loop 2(CL series only)
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 749 of file gd32f10x_rcu.c.

750 {
751 uint32_t stb_cnt = 0U;
752 ErrStatus reval = ERROR;
753 FlagStatus osci_stat = RESET;
754
755 switch(osci){
756 /* wait HXTAL stable */
757 case RCU_HXTAL:
758 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
759 osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
760 stb_cnt++;
761 }
762
763 /* check whether flag is set or not */
764 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
765 reval = SUCCESS;
766 }
767 break;
768
769 /* wait LXTAL stable */
770 case RCU_LXTAL:
771 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
772 osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
773 stb_cnt++;
774 }
775
776 /* check whether flag is set or not */
777 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
778 reval = SUCCESS;
779 }
780 break;
781
782 /* wait IRC8M stable */
783 case RCU_IRC8M:
784 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
785 osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
786 stb_cnt++;
787 }
788
789 /* check whether flag is set or not */
790 if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
791 reval = SUCCESS;
792 }
793 break;
794
795 /* wait IRC40K stable */
796 case RCU_IRC40K:
797 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
798 osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
799 stb_cnt++;
800 }
801
802 /* check whether flag is set or not */
803 if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
804 reval = SUCCESS;
805 }
806 break;
807
808 /* wait PLL stable */
809 case RCU_PLL_CK:
810 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
811 osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
812 stb_cnt++;
813 }
814
815 /* check whether flag is set or not */
816 if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
817 reval = SUCCESS;
818 }
819 break;
820
821 #ifdef GD32F10X_CL
822 /* wait PLL1 stable */
823 case RCU_PLL1_CK:
824 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
825 osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
826 stb_cnt++;
827 }
828
829 /* check whether flag is set or not */
830 if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){
831 reval = SUCCESS;
832 }
833 break;
834 /* wait PLL2 stable */
835 case RCU_PLL2_CK:
836 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
837 osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
838 stb_cnt++;
839 }
840
841 /* check whether flag is set or not */
842 if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){
843 reval = SUCCESS;
844 }
845 break;
846 #endif /* GD32F10X_CL */
847
848 default:
849 break;
850 }
851
852 /* return value */
853 return reval;
854 }
RCU_FLAG_PLL1STB
Definition: gd32f10x_rcu.h:509
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
RCU_FLAG_HXTALSTB
Definition: gd32f10x_rcu.h:506
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
RCU_FLAG_PLL2STB
Definition: gd32f10x_rcu.h:510
OSC_STARTUP_TIMEOUT
#define OSC_STARTUP_TIMEOUT
Definition: gd32f10x_rcu.c:21
LXTAL_STARTUP_TIMEOUT
#define LXTAL_STARTUP_TIMEOUT
Definition: gd32f10x_rcu.c:22
RCU_FLAG_LXTALSTB
Definition: gd32f10x_rcu.h:512
RCU_FLAG_PLLSTB
Definition: gd32f10x_rcu.h:507
RCU_PLL1_CK
Definition: gd32f10x_rcu.h:576
RCU_IRC40K
Definition: gd32f10x_rcu.h:573
rcu_flag_get
FlagStatus rcu_flag_get(rcu_flag_enum flag)
get the clock stabilization and periphral reset flags
Definition: gd32f10x_rcu.c:631
RCU_FLAG_IRC8MSTB
Definition: gd32f10x_rcu.h:505
RCU_FLAG_IRC40KSTB
Definition: gd32f10x_rcu.h:513
RCU_PLL2_CK
Definition: gd32f10x_rcu.h:577
RCU_LXTAL
Definition: gd32f10x_rcu.h:571
void rcu_periph_clock_disable ( rcu_periph_enum periph )

disable the peripherals clock

Parameters
[in] periph RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock
  • RCU_AF: alternate function clock
  • RCU_CRC: CRC clock
  • RCU_DMAx (x=0,1): DMA clock
  • RCU_ENET: ENET clock(CL series available)
  • RCU_ENETTX: ENETTX clock(CL series available)
  • RCU_ENETRX: ENETRX clock(CL series available)
  • RCU_USBD: USBD clock(HD,XD series available)
  • RCU_USBFS: USBFS clock(CL series available)
  • RCU_EXMC: EXMC clock
  • RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock
  • RCU_WWDGT: WWDGT clock
  • RCU_SPIx (x=0,1,2): SPI clock
  • RCU_USARTx (x=0,1,2): USART clock
  • RCU_UARTx (x=3,4): UART clock
  • RCU_I2Cx (x=0,1): I2C clock
  • RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock
  • RCU_PMU: PMU clock
  • RCU_DAC: DAC clock
  • RCU_RTC: RTC clock
  • RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock
  • RCU_SDIO: SDIO clock(not available for CL series)
  • RCU_BKPI: BKP interface clock
[out] none
Return values
none

Definition at line 128 of file gd32f10x_rcu.c.

129 {
130 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
131 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_clock_enable ( rcu_periph_enum periph )

enable the peripherals clock

Parameters
[in] periph RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock
  • RCU_AF : alternate function clock
  • RCU_CRC: CRC clock
  • RCU_DMAx (x=0,1): DMA clock
  • RCU_ENET: ENET clock(CL series available)
  • RCU_ENETTX: ENETTX clock(CL series available)
  • RCU_ENETRX: ENETRX clock(CL series available)
  • RCU_USBD: USBD clock(HD,XD series available)
  • RCU_USBFS: USBFS clock(CL series available)
  • RCU_EXMC: EXMC clock
  • RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock
  • RCU_WWDGT: WWDGT clock
  • RCU_SPIx (x=0,1,2): SPI clock
  • RCU_USARTx (x=0,1,2): USART clock
  • RCU_UARTx (x=3,4): UART clock
  • RCU_I2Cx (x=0,1): I2C clock
  • RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock
  • RCU_PMU: PMU clock
  • RCU_DAC: DAC clock
  • RCU_RTC: RTC clock
  • RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock
  • RCU_SDIO: SDIO clock(not available for CL series)
  • RCU_BKPI: BKP interface clock
[out] none
Return values
none

Definition at line 93 of file gd32f10x_rcu.c.

94 {
95 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
96 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_clock_sleep_disable ( rcu_periph_sleep_enum periph )

disable the peripherals clock when sleep mode

Parameters
[in] periph RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below:
  • RCU_FMC_SLP: FMC clock
  • RCU_SRAM_SLP: SRAM clock
[out] none
Return values
none

Definition at line 156 of file gd32f10x_rcu.c.

157 {
158 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
159 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_clock_sleep_enable ( rcu_periph_sleep_enum periph )

enable the peripherals clock when sleep mode

Parameters
[in] periph RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below:
  • RCU_FMC_SLP: FMC clock
  • RCU_SRAM_SLP: SRAM clock
[out] none
Return values
none

Definition at line 142 of file gd32f10x_rcu.c.

143 {
144 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
145 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_reset_disable ( rcu_periph_reset_enum periph_reset )

disable reset the peripheral

Parameters
[in] periph_reset RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports
  • RCU_AFRST : reset alternate function clock
  • RCU_ENETRST: reset ENET(CL series available)
  • RCU_USBDRST: reset USBD(HD,XD series available)
  • RCU_USBFSRST: reset USBFS(CL series available)
  • RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER
  • RCU_WWDGTRST: reset WWDGT
  • RCU_SPIxRST (x=0,1,2): reset SPI
  • RCU_USARTxRST (x=0,1,2): reset USART
  • RCU_UARTxRST (x=3,4): reset UART
  • RCU_I2CxRST (x=0,1): reset I2C
  • RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN
  • RCU_PMURST: reset PMU
  • RCU_DACRST: reset DAC
  • RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC
  • RCU_BKPIRST: reset BKPI
[out] none
Return values
none

Definition at line 212 of file gd32f10x_rcu.c.

213 {
214 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
215 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_reset_enable ( rcu_periph_reset_enum periph_reset )

reset the peripherals

Parameters
[in] periph_reset RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports
  • RCU_AFRST : reset alternate function clock
  • RCU_ENETRST: reset ENET(CL series available)
  • RCU_USBDRST: reset USBD(HD,XD series available)
  • RCU_USBFSRST: reset USBFS(CL series available)
  • RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER
  • RCU_WWDGTRST: reset WWDGT
  • RCU_SPIxRST (x=0,1,2): reset SPI
  • RCU_USARTxRST (x=0,1,2): reset USART
  • RCU_UARTxRST (x=3,4): reset UART
  • RCU_I2CxRST (x=0,1): reset I2C
  • RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN
  • RCU_PMURST: reset PMU
  • RCU_DACRST: reset DAC
  • RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC
  • RCU_BKPIRST: reset BKPI
[out] none
Return values
none

Definition at line 184 of file gd32f10x_rcu.c.

185 {
186 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
187 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_pll_config | ( | uint32_t | pll_src,
 |  | uint32_t | pll_mul
 | ) |  |

configure the main PLL clock

Parameters
[in] pll_src PLL clock source selection
  • RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL
  • RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL
[in] pll_mul PLL clock multiplication factor
  • RCU_PLL_MULx (XD series x = 2..32, CL series x = 2..14, 6.5, 16..32)
[out] none
Return values
none

Definition at line 375 of file gd32f10x_rcu.c.

376 {
377 uint32_t reg = 0U;
378
379 reg = RCU_CFG0;
380
381 /* PLL clock source and multiplication factor configuration */
382 reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
383 reg |= (pll_src | pll_mul);
384
385 RCU_CFG0 = reg;
386 }
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f10x_rcu.h:90
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f10x_rcu.h:88
RCU_CFG0_PLLMF_4
#define RCU_CFG0_PLLMF_4
Definition: gd32f10x_rcu.h:93
void rcu_predv0_config ( uint32_t predv0_div )

configure the PREDV0 division factor

Parameters
[in] predv0_div PREDV0 division factor
  • RCU_PREDV0_DIVx, x = 1,2
[out] none
Return values
none

Definition at line 396 of file gd32f10x_rcu.c.

397 {
398 uint32_t reg = 0U;
399
400 reg = RCU_CFG0;
401 /* reset PREDV0 bit */
402 reg &= ~RCU_CFG0_PREDV0;
403 if(RCU_PREDV0_DIV2 == predv0_div){
404 /* set the PREDV0 bit */
405 reg |= RCU_CFG0_PREDV0;
406 }
407
408 RCU_CFG0 = reg;
409 }
RCU_CFG0_PREDV0
#define RCU_CFG0_PREDV0
Definition: gd32f10x_rcu.h:89
RCU_PREDV0_DIV2
#define RCU_PREDV0_DIV2
Definition: gd32f10x_rcu.h:714
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_rtc_clock_config ( uint32_t rtc_clock_source )

configure the RTC clock source selection

Parameters
[in] rtc_clock_source RTC clock source selection only one parameter can be selected which is shown as below:
  • RCU_RTCSRC_NONE: no clock selected
  • RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
  • RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
  • RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock
[out] none
Return values
none

Definition at line 561 of file gd32f10x_rcu.c.

562 {
563 uint32_t reg;
564
565 reg = RCU_BDCTL;
566 /* reset the RTCSRC bits and set according to rtc_clock_source */
567 reg &= ~RCU_BDCTL_RTCSRC;
568 RCU_BDCTL = (reg | rtc_clock_source);
569 }
RCU_BDCTL_RTCSRC
#define RCU_BDCTL_RTCSRC
Definition: gd32f10x_rcu.h:288
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
void rcu_system_clock_source_config ( uint32_t ck_sys )

configure the system clock source

Parameters
[in] ck_sys system clock source select only one parameter can be selected which is shown as below:
  • RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
  • RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
  • RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
[out] none
Return values
none

Definition at line 249 of file gd32f10x_rcu.c.

250 {
251 uint32_t reg;
252
253 reg = RCU_CFG0;
254 /* reset the SCS bits and set according to ck_sys */
255 reg &= ~RCU_CFG0_SCS;
256 RCU_CFG0 = (reg | ck_sys);
257 }
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f10x_rcu.h:82
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
uint32_t rcu_system_clock_source_get ( void )

get the system clock source

Parameters
[in] | none
[out] | none
Return values
which clock is selected as CK_SYS source
  • RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source
  • RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source
  • RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source

Definition at line 268 of file gd32f10x_rcu.c.

269 {
270 return (RCU_CFG0 & RCU_CFG0_SCSS);
271 }
RCU_CFG0_SCSS
#define RCU_CFG0_SCSS
Definition: gd32f10x_rcu.h:83
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_usb_clock_config ( uint32_t usb_psc )

configure the USBD/USBFS prescaler factor

Parameters
[in] adc_div USB prescaler factor
  • RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5
  • RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1
  • RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5
  • RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2
[out] none
Return values
none

Definition at line 534 of file gd32f10x_rcu.c.

535 {
536 uint32_t reg;
537
538 reg = RCU_CFG0;
539
540 /* configure the USBD/USBFS prescaler factor */
541 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
542 reg &= ~RCU_CFG0_USBDPSC;
543 #elif defined(GD32F10X_CL)
544 reg &= ~RCU_CFG0_USBFSPSC;
545 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
546
547 RCU_CFG0 = (reg | usb_psc);
548 }
RCU_CFG0_USBDPSC
#define RCU_CFG0_USBDPSC
Definition: gd32f10x_rcu.h:91
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_rtc.h File Reference

definitions for the RTC More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | RTC RTC_BASE
#define | RTC_INTEN REG32(RTC + 0x00U)
#define | RTC_CTL REG32(RTC + 0x04U)
#define | RTC_PSCH REG32(RTC + 0x08U)
#define | RTC_PSCL REG32(RTC + 0x0CU)
#define | RTC_DIVH REG32(RTC + 0x10U)
#define | RTC_DIVL REG32(RTC + 0x14U)
#define | RTC_CNTH REG32(RTC + 0x18U)
#define | RTC_CNTL REG32(RTC + 0x1CU)
#define | RTC_ALRMH REG32(RTC + 0x20U)
#define | RTC_ALRML REG32(RTC + 0x24U)
#define | RTC_INTEN_SCIE BIT(0)
#define | RTC_INTEN_ALRMIE BIT(1)
#define | RTC_INTEN_OVIE BIT(2)
#define | RTC_CTL_SCIF BIT(0)
#define | RTC_CTL_ALRMIF BIT(1)
#define | RTC_CTL_OVIF BIT(2)
#define | RTC_CTL_RSYNF BIT(3)
#define | RTC_CTL_CMF BIT(4)
#define | RTC_CTL_LWOFF BIT(5)
#define | RTC_PSCH_PSC BITS(0, 3)
#define | RTC_PSCL_PSC BITS(0, 15)
#define | RTC_DIVH_DIV BITS(0, 3)
#define | RTC_DIVL_DIV BITS(0, 15)
#define | RTC_CNTH_CNT BITS(0, 15)
#define | RTC_CNTL_CNT BITS(0, 15)
#define | RTC_ALRMH_ALRM BITS(0, 15)
#define | RTC_ALRML_ALRM BITS(0, 15)
#define | RTC_HIGH_VALUE 0x000F0000U
#define | RTC_LOW_VALUE 0x0000FFFFU
#define | RTC_INT_SECOND RTC_INTEN_SCIE
#define | RTC_INT_ALARM RTC_INTEN_ALRMIE
#define | RTC_INT_OVERFLOW RTC_INTEN_OVIE
#define | RTC_FLAG_SECOND RTC_CTL_SCIF
#define | RTC_FLAG_ALARM RTC_CTL_ALRMIF
#define | RTC_FLAG_OVERFLOW RTC_CTL_OVIF
#define | RTC_FLAG_RSYN RTC_CTL_RSYNF
#define | RTC_FLAG_LWOF RTC_CTL_LWOFF

Functions

void | rtc_interrupt_enable (uint32_t interrupt)
enable RTC interrupt More...
void | rtc_interrupt_disable (uint32_t interrupt)
disable RTC interrupt More...
void | rtc_configuration_mode_enter (void)
enter RTC configuration mode More...
void | rtc_configuration_mode_exit (void)
exit RTC configuration mode More...
void | rtc_lwoff_wait (void)
wait RTC last write operation finished flag set More...
void | rtc_register_sync_wait (void)
wait RTC registers synchronized flag set More...
uint32_t | rtc_counter_get (void)
get RTC counter value More...
void | rtc_counter_set (uint32_t cnt)
set RTC counter value More...
void | rtc_prescaler_set (uint32_t psc)
set RTC prescaler value More...
void | rtc_alarm_config (uint32_t alarm)
set RTC alarm value More...
uint32_t | rtc_divider_get (void)
get RTC divider value More...
FlagStatus | rtc_flag_get (uint32_t flag)
get RTC flag status More...
void | rtc_flag_clear (uint32_t flag)
clear RTC flag status More...

Detailed Description

definitions for the RTC

Definition in file gd32f10x_rtc.h.

Macro Definition Documentation

#define RTC RTC_BASE

Definition at line 19 of file gd32f10x_rtc.h.

#define RTC_ALRMH REG32(RTC + 0x20U)

alarm high register

Definition at line 30 of file gd32f10x_rtc.h.

#define RTC_ALRMH_ALRM BITS(0, 15)

alarm high value

Definition at line 53 of file gd32f10x_rtc.h.

#define RTC_ALRML REG32(RTC + 0x24U)

alarm low register

Definition at line 31 of file gd32f10x_rtc.h.

#define RTC_ALRML_ALRM BITS(0, 15)

alarm low value

Definition at line 54 of file gd32f10x_rtc.h.

#define RTC_CNTH REG32(RTC + 0x18U)

counter high register

Definition at line 28 of file gd32f10x_rtc.h.

#define RTC_CNTH_CNT BITS(0, 15)

counter high value

Definition at line 51 of file gd32f10x_rtc.h.

#define RTC_CNTL REG32(RTC + 0x1CU)

counter low register

Definition at line 29 of file gd32f10x_rtc.h.

#define RTC_CNTL_CNT BITS(0, 15)

counter low value

Definition at line 52 of file gd32f10x_rtc.h.

#define RTC_CTL REG32(RTC + 0x04U)

control register

Definition at line 23 of file gd32f10x_rtc.h.

#define RTC_CTL_ALRMIF BIT(1)

alarm interrupt flag

Definition at line 41 of file gd32f10x_rtc.h.

#define RTC_CTL_CMF BIT(4)

configuration mode flag

Definition at line 44 of file gd32f10x_rtc.h.

#define RTC_CTL_LWOFF BIT(5)

last write operation finished flag

Definition at line 45 of file gd32f10x_rtc.h.

#define RTC_CTL_OVIF BIT(2)

overflow interrupt flag

Definition at line 42 of file gd32f10x_rtc.h.

#define RTC_CTL_RSYNF BIT(3)

registers synchronized flag

Definition at line 43 of file gd32f10x_rtc.h.

#define RTC_CTL_SCIF BIT(0)

second interrupt flag

Definition at line 40 of file gd32f10x_rtc.h.

#define RTC_DIVH REG32(RTC + 0x10U)

divider high register

Definition at line 26 of file gd32f10x_rtc.h.

#define RTC_DIVH_DIV BITS(0, 3)

divider high value

Definition at line 49 of file gd32f10x_rtc.h.

#define RTC_DIVL REG32(RTC + 0x14U)

divider low register

Definition at line 27 of file gd32f10x_rtc.h.

#define RTC_DIVL_DIV BITS(0, 15)

divider low value

Definition at line 50 of file gd32f10x_rtc.h.

#define RTC_FLAG_ALARM RTC_CTL_ALRMIF

alarm interrupt flag

Definition at line 65 of file gd32f10x_rtc.h.

#define RTC_FLAG_LWOF RTC_CTL_LWOFF

last write operation finished flag

Definition at line 68 of file gd32f10x_rtc.h.

#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF

overflow interrupt flag

Definition at line 66 of file gd32f10x_rtc.h.

#define RTC_FLAG_RSYN RTC_CTL_RSYNF

registers synchronized flag

Definition at line 67 of file gd32f10x_rtc.h.

#define RTC_FLAG_SECOND RTC_CTL_SCIF

second interrupt flag

Definition at line 64 of file gd32f10x_rtc.h.

#define RTC_HIGH_VALUE 0x000F0000U

RTC high value

Definition at line 57 of file gd32f10x_rtc.h.

#define RTC_INT_ALARM RTC_INTEN_ALRMIE

alarm interrupt enable

Definition at line 61 of file gd32f10x_rtc.h.

#define RTC_INT_OVERFLOW RTC_INTEN_OVIE

overflow interrupt enable

Definition at line 62 of file gd32f10x_rtc.h.

#define RTC_INT_SECOND RTC_INTEN_SCIE

second interrupt enable

Definition at line 60 of file gd32f10x_rtc.h.

#define RTC_INTEN REG32(RTC + 0x00U)

interrupt enable register

Definition at line 22 of file gd32f10x_rtc.h.

#define RTC_INTEN_ALRMIE BIT(1)

alarm interrupt enable

Definition at line 36 of file gd32f10x_rtc.h.

#define RTC_INTEN_OVIE BIT(2)

overflow interrupt enable

Definition at line 37 of file gd32f10x_rtc.h.

#define RTC_INTEN_SCIE BIT(0)

second interrupt enable

Definition at line 35 of file gd32f10x_rtc.h.

#define RTC_LOW_VALUE 0x0000FFFFU

RTC low value

Definition at line 58 of file gd32f10x_rtc.h.

#define RTC_PSCH REG32(RTC + 0x08U)

prescaler high register

Definition at line 24 of file gd32f10x_rtc.h.

#define RTC_PSCH_PSC BITS(0, 3)

prescaler high value

Definition at line 47 of file gd32f10x_rtc.h.

#define RTC_PSCL REG32(RTC + 0x0CU)

prescaler low register

Definition at line 25 of file gd32f10x_rtc.h.

#define RTC_PSCL_PSC BITS(0, 15)

prescaler low value

Definition at line 48 of file gd32f10x_rtc.h.

Function Documentation

void rtc_alarm_config ( uint32_t alarm )

set RTC alarm value

Parameters
[in] | alarm | RTC alarm value
[out] | none
Return values
none

Definition at line 145 of file gd32f10x_rtc.c.

146 {
147 rtc_configuration_mode_enter();
148 /* set the alarm high bits */
149 RTC_ALRMH = alarm >> 16;
150 /* set the alarm low bits */
151 RTC_ALRML = (alarm & RTC_LOW_VALUE);
152 rtc_configuration_mode_exit();
153 }
rtc_configuration_mode_enter
void rtc_configuration_mode_enter(void)
enter RTC configuration mode
Definition: gd32f10x_rtc.c:49
RTC_LOW_VALUE
#define RTC_LOW_VALUE
Definition: gd32f10x_rtc.h:58
rtc_configuration_mode_exit
void rtc_configuration_mode_exit(void)
exit RTC configuration mode
Definition: gd32f10x_rtc.c:60
RTC_ALRML
#define RTC_ALRML
Definition: gd32f10x_rtc.h:31
RTC_ALRMH
#define RTC_ALRMH
Definition: gd32f10x_rtc.h:30
void rtc_configuration_mode_enter ( void )

enter RTC configuration mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 49 of file gd32f10x_rtc.c.

50 {
51 RTC_CTL |= RTC_CTL_CMF;
52 }
RTC_CTL_CMF
#define RTC_CTL_CMF
Definition: gd32f10x_rtc.h:44
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
void rtc_configuration_mode_exit ( void )

exit RTC configuration mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 60 of file gd32f10x_rtc.c.

61 {
62 RTC_CTL &= ~RTC_CTL_CMF;
63 }
RTC_CTL_CMF
#define RTC_CTL_CMF
Definition: gd32f10x_rtc.h:44
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
uint32_t rtc_counter_get ( void )

get RTC counter value

Parameters
[in] | none
[out] | none
Return values
RTC counter value

Definition at line 99 of file gd32f10x_rtc.c.

100 {
101 uint32_t temp = 0x0U;
102 temp = RTC_CNTL;
103 temp |= (RTC_CNTH << 16);
104 return temp;
105 }
RTC_CNTL
#define RTC_CNTL
Definition: gd32f10x_rtc.h:29
RTC_CNTH
#define RTC_CNTH
Definition: gd32f10x_rtc.h:28
void rtc_counter_set ( uint32_t cnt )

set RTC counter value

Parameters
[in] | cnt | RTC counter value
[out] | none
Return values
none

Definition at line 113 of file gd32f10x_rtc.c.

114 {
115 rtc_configuration_mode_enter();
116 /* set the RTC counter high bits */
117 RTC_CNTH = cnt >> 16;
118 /* set the RTC counter low bits */
119 RTC_CNTL = (cnt & RTC_LOW_VALUE);
120 rtc_configuration_mode_exit();
121 }
RTC_CNTL
#define RTC_CNTL
Definition: gd32f10x_rtc.h:29
rtc_configuration_mode_enter
void rtc_configuration_mode_enter(void)
enter RTC configuration mode
Definition: gd32f10x_rtc.c:49
RTC_LOW_VALUE
#define RTC_LOW_VALUE
Definition: gd32f10x_rtc.h:58
rtc_configuration_mode_exit
void rtc_configuration_mode_exit(void)
exit RTC configuration mode
Definition: gd32f10x_rtc.c:60
RTC_CNTH
#define RTC_CNTH
Definition: gd32f10x_rtc.h:28
uint32_t rtc_divider_get ( void )

get RTC divider value

Parameters
[in] | none
[out] | none
Return values
RTC divider value

Definition at line 161 of file gd32f10x_rtc.c.

162 {
163 uint32_t temp = 0x00U;
164 temp = (RTC_DIVH & RTC_DIVH_DIV) << 16;
165 temp |= RTC_DIVL;
166 return temp;
167 }
RTC_DIVL
#define RTC_DIVL
Definition: gd32f10x_rtc.h:27
RTC_DIVH_DIV
#define RTC_DIVH_DIV
Definition: gd32f10x_rtc.h:49
RTC_DIVH
#define RTC_DIVH
Definition: gd32f10x_rtc.h:26
void rtc_flag_clear ( uint32_t flag )

clear RTC flag status

Parameters
[in] flag specify which flag status to clear
  • RTC_FLAG_SECOND: second interrupt flag
  • RTC_FLAG_ALARM: alarm interrupt flag
  • RTC_FLAG_OVERFLOW: overflow interrupt flag
  • RTC_FLAG_RSYN: registers synchronized flag
[out] none
Return values
none

Definition at line 199 of file gd32f10x_rtc.c.

200 {
201 /* clear RTC flag */
202 RTC_CTL &= ~flag;
203 }
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
FlagStatus rtc_flag_get ( uint32_t flag )

get RTC flag status

Parameters
[in] flag specify which flag status to get
  • RTC_FLAG_SECOND: second interrupt flag
  • RTC_FLAG_ALARM: alarm interrupt flag
  • RTC_FLAG_OVERFLOW: overflow interrupt flag
  • RTC_FLAG_RSYN: registers synchronized flag
  • RTC_FLAG_LWOF: last write operation finished flag
[out] none
Return values
SET or RESET

Definition at line 180 of file gd32f10x_rtc.c.

181 {
182 if(RESET != (RTC_CTL & flag)){
183 return SET;
184 }else{
185 return RESET;
186 }
187 }
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
void rtc_interrupt_disable ( uint32_t interrupt )

disable RTC interrupt

Parameters
[in] interrupt specify which interrupt to disbale
  • RTC_INT_SECOND: second interrupt
  • RTC_INT_ALARM: alarm interrupt
  • RTC_INT_OVERFLOW: overflow interrupt
[out] none
Return values
none

Definition at line 38 of file gd32f10x_rtc.c.

39 {
40 RTC_INTEN &= ~interrupt;
41 }
RTC_INTEN
#define RTC_INTEN
Definition: gd32f10x_rtc.h:22
void rtc_interrupt_enable ( uint32_t interrupt )

enable RTC interrupt

Parameters
[in] interrupt specify which interrupt to enbale
  • RTC_INT_SECOND: second interrupt
  • RTC_INT_ALARM: alarm interrupt
  • RTC_INT_OVERFLOW: overflow interrupt
[out] none
Return values
none

Definition at line 24 of file gd32f10x_rtc.c.

25 {
26 RTC_INTEN |= interrupt;
27 }
RTC_INTEN
#define RTC_INTEN
Definition: gd32f10x_rtc.h:22
void rtc_lwoff_wait ( void )

wait RTC last write operation finished flag set

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 71 of file gd32f10x_rtc.c.

72 {
73 /* loop until LWOFF flag is set */
74 while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){
75 }
76 }
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
RTC_CTL_LWOFF
#define RTC_CTL_LWOFF
Definition: gd32f10x_rtc.h:45
void rtc_prescaler_set ( uint32_t psc )

set RTC prescaler value

Parameters
[in] | psc | RTC prescaler value
[out] | none
Return values
none

Definition at line 129 of file gd32f10x_rtc.c.

130 {
131 rtc_configuration_mode_enter();
132 /* set the RTC prescaler high bits */
133 RTC_PSCH = (psc & RTC_HIGH_VALUE) >> 16;
134 /* set the RTC prescaler low bits */
135 RTC_PSCL = (psc & RTC_LOW_VALUE);
136 rtc_configuration_mode_exit();
137 }
RTC_HIGH_VALUE
#define RTC_HIGH_VALUE
Definition: gd32f10x_rtc.h:57
RTC_PSCL
#define RTC_PSCL
Definition: gd32f10x_rtc.h:25
RTC_PSCH
#define RTC_PSCH
Definition: gd32f10x_rtc.h:24
rtc_configuration_mode_enter
void rtc_configuration_mode_enter(void)
enter RTC configuration mode
Definition: gd32f10x_rtc.c:49
RTC_LOW_VALUE
#define RTC_LOW_VALUE
Definition: gd32f10x_rtc.h:58
rtc_configuration_mode_exit
void rtc_configuration_mode_exit(void)
exit RTC configuration mode
Definition: gd32f10x_rtc.c:60
void rtc_register_sync_wait ( void )

wait RTC registers synchronized flag set

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 84 of file gd32f10x_rtc.c.

85 {
86 /* clear RSYNF flag */
87 RTC_CTL &= ~RTC_CTL_RSYNF;
88 /* loop until RSYNF flag is set */
89 while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){
90 }
91 }
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
RTC_CTL_RSYNF
#define RTC_CTL_RSYNF
Definition: gd32f10x_rtc.h:43
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_sdio.h File Reference

definitions for the SDIO More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | SDIO SDIO_BASE
#define | SDIO_PWRCTL REG32(SDIO + 0x00U)
#define | SDIO_CLKCTL REG32(SDIO + 0x04U)
#define | SDIO_CMDAGMT REG32(SDIO + 0x08U)
#define | SDIO_CMDCTL REG32(SDIO + 0x0CU)
#define | SDIO_RSPCMDIDX REG32(SDIO + 0x10U)
#define | SDIO_RESP0 REG32(SDIO + 0x14U)
#define | SDIO_RESP1 REG32(SDIO + 0x18U)
#define | SDIO_RESP2 REG32(SDIO + 0x1CU)
#define | SDIO_RESP3 REG32(SDIO + 0x20U)
#define | SDIO_DATATO REG32(SDIO + 0x24U)
#define | SDIO_DATALEN REG32(SDIO + 0x28U)
#define | SDIO_DATACTL REG32(SDIO + 0x2CU)
#define | SDIO_DATACNT REG32(SDIO + 0x30U)
#define | SDIO_STAT REG32(SDIO + 0x34U)
#define | SDIO_INTC REG32(SDIO + 0x38U)
#define | SDIO_INTEN REG32(SDIO + 0x3CU)
#define | SDIO_FIFOCNT REG32(SDIO + 0x48U)
#define | SDIO_FIFO REG32(SDIO + 0x80U)
#define | SDIO_PWRCTL_PWRCTL BITS(0,1)
#define | SDIO_CLKCTL_DIV BITS(0,7)
#define | SDIO_CLKCTL_CLKEN BIT(8)
#define | SDIO_CLKCTL_CLKPWRSAV BIT(9)
#define | SDIO_CLKCTL_CLKBYP BIT(10)
#define | SDIO_CLKCTL_BUSMODE BITS(11,12)
#define | SDIO_CLKCTL_CLKEDGE BIT(13)
#define | SDIO_CLKCTL_HWCLKEN BIT(14)
#define | SDIO_CMDAGMT_CMDAGMT BITS(0,31)
#define | SDIO_CMDCTL_CMDIDX BITS(0,5)
#define | SDIO_CMDCTL_CMDRESP BITS(6,7)
#define | SDIO_CMDCTL_INTWAIT BIT(8)
#define | SDIO_CMDCTL_WAITDEND BIT(9)
#define | SDIO_CMDCTL_CSMEN BIT(10)
#define | SDIO_CMDCTL_SUSPEND BIT(11)
#define | SDIO_CMDCTL_ENCMDC BIT(12)
#define | SDIO_CMDCTL_NINTEN BIT(13)
#define | SDIO_CMDCTL_ATAEN BIT(14)
#define | SDIO_DATATO_DATATO BITS(0,31)
#define | SDIO_DATALEN_DATALEN BITS(0,24)
#define | SDIO_DATACTL_DATAEN BIT(0)
#define | SDIO_DATACTL_DATADIR BIT(1)
#define | SDIO_DATACTL_TRANSMOD BIT(2)
#define | SDIO_DATACTL_DMAEN BIT(3)
#define | SDIO_DATACTL_BLKSZ BITS(4,7)
#define | SDIO_DATACTL_RWEN BIT(8)
#define | SDIO_DATACTL_RWSTOP BIT(9)
#define | SDIO_DATACTL_RWTYPE BIT(10)
#define | SDIO_DATACTL_IOEN BIT(11)
#define | SDIO_STAT_CCRCERR BIT(0)
#define | SDIO_STAT_DTCRCERR BIT(1)
#define | SDIO_STAT_CMDTMOUT BIT(2)
#define | SDIO_STAT_DTTMOUT BIT(3)
#define | SDIO_STAT_TXURE BIT(4)
#define | SDIO_STAT_RXORE BIT(5)
#define | SDIO_STAT_CMDRECV BIT(6)
#define | SDIO_STAT_CMDSEND BIT(7)
#define | SDIO_STAT_DTEND BIT(8)
#define | SDIO_STAT_STBITE BIT(9)
#define | SDIO_STAT_DTBLKEND BIT(10)
#define | SDIO_STAT_CMDRUN BIT(11)
#define | SDIO_STAT_TXRUN BIT(12)
#define | SDIO_STAT_RXRUN BIT(13)
#define | SDIO_STAT_TFH BIT(14)
#define | SDIO_STAT_RFH BIT(15)
#define | SDIO_STAT_TFF BIT(16)
#define | SDIO_STAT_RFF BIT(17)
#define | SDIO_STAT_TFE BIT(18)
#define | SDIO_STAT_RFE BIT(19)
#define | SDIO_STAT_TXDTVAL BIT(20)
#define | SDIO_STAT_RXDTVAL BIT(21)
#define | SDIO_STAT_SDIOINT BIT(22)
#define | SDIO_STAT_ATAEND BIT(23)
#define | SDIO_INTC_CCRCERRC BIT(0)
#define | SDIO_INTC_DTCRCERRC BIT(1)
#define | SDIO_INTC_CMDTMOUTC BIT(2)
#define | SDIO_INTC_DTTMOUTC BIT(3)
#define | SDIO_INTC_TXUREC BIT(4)
#define | SDIO_INTC_RXOREC BIT(5)
#define | SDIO_INTC_CMDRECVC BIT(6)
#define | SDIO_INTC_CMDSENDC BIT(7)
#define | SDIO_INTC_DTENDC BIT(8)
#define | SDIO_INTC_STBITEC BIT(9)
#define | SDIO_INTC_DTBLKENDC BIT(10)
#define | SDIO_INTC_SDIOINTC BIT(22)
#define | SDIO_INTC_ATAENDC BIT(23)
#define | SDIO_INTEN_CCRCERRIE BIT(0)
#define | SDIO_INTEN_DTCRCERRIE BIT(1)
#define | SDIO_INTEN_CMDTMOUTIE BIT(2)
#define | SDIO_INTEN_DTTMOUTIE BIT(3)
#define | SDIO_INTEN_TXUREIE BIT(4)
#define | SDIO_INTEN_RXOREIE BIT(5)
#define | SDIO_INTEN_CMDRECVIE BIT(6)
#define | SDIO_INTEN_CMDSENDIE BIT(7)
#define | SDIO_INTEN_DTENDIE BIT(8)
#define | SDIO_INTEN_STBITEIE BIT(9)
#define | SDIO_INTEN_DTBLKENDIE BIT(10)
#define | SDIO_INTEN_CMDRUNIE BIT(11)
#define | SDIO_INTEN_TXRUNIE BIT(12)
#define | SDIO_INTEN_RXRUNIE BIT(13)
#define | SDIO_INTEN_TFHIE BIT(14)
#define | SDIO_INTEN_RFHIE BIT(15)
#define | SDIO_INTEN_TFFIE BIT(16)
#define | SDIO_INTEN_RFFIE BIT(17)
#define | SDIO_INTEN_TFEIE BIT(18)
#define | SDIO_INTEN_RFEIE BIT(19)
#define | SDIO_INTEN_TXDTVALIE BIT(20)
#define | SDIO_INTEN_RXDTVALIE BIT(21)
#define | SDIO_INTEN_SDIOINTIE BIT(22)
#define | SDIO_INTEN_ATAENDIE BIT(23)
#define | SDIO_FIFO_FIFODT BITS(0,31)
#define | SDIO_FLAG_CCRCERR BIT(0)
#define | SDIO_FLAG_DTCRCERR BIT(1)
#define | SDIO_FLAG_CMDTMOUT BIT(2)
#define | SDIO_FLAG_DTTMOUT BIT(3)
#define | SDIO_FLAG_TXURE BIT(4)
#define | SDIO_FLAG_RXORE BIT(5)
#define | SDIO_FLAG_CMDRECV BIT(6)
#define | SDIO_FLAG_CMDSEND BIT(7)
#define | SDIO_FLAG_DTEND BIT(8)
#define | SDIO_FLAG_STBITE BIT(9)
#define | SDIO_FLAG_DTBLKEND BIT(10)
#define | SDIO_FLAG_CMDRUN BIT(11)
#define | SDIO_FLAG_TXRUN BIT(12)
#define | SDIO_FLAG_RXRUN BIT(13)
#define | SDIO_FLAG_TFH BIT(14)
#define | SDIO_FLAG_RFH BIT(15)
#define | SDIO_FLAG_TFF BIT(16)
#define | SDIO_FLAG_RFF BIT(17)
#define | SDIO_FLAG_TFE BIT(18)
#define | SDIO_FLAG_RFE BIT(19)
#define | SDIO_FLAG_TXDTVAL BIT(20)
#define | SDIO_FLAG_RXDTVAL BIT(21)
#define | SDIO_FLAG_SDIOINT BIT(22)
#define | SDIO_FLAG_ATAEND BIT(23)
#define | SDIO_INT_CCRCERR BIT(0)
#define | SDIO_INT_DTCRCERR BIT(1)
#define | SDIO_INT_CMDTMOUT BIT(2)
#define | SDIO_INT_DTTMOUT BIT(3)
#define | SDIO_INT_TXURE BIT(4)
#define | SDIO_INT_RXORE BIT(5)
#define | SDIO_INT_CMDRECV BIT(6)
#define | SDIO_INT_CMDSEND BIT(7)
#define | SDIO_INT_DTEND BIT(8)
#define | SDIO_INT_STBITE BIT(9)
#define | SDIO_INT_DTBLKEND BIT(10)
#define | SDIO_INT_CMDRUN BIT(11)
#define | SDIO_INT_TXRUN BIT(12)
#define | SDIO_INT_RXRUN BIT(13)
#define | SDIO_INT_TFH BIT(14)
#define | SDIO_INT_RFH BIT(15)
#define | SDIO_INT_TFF BIT(16)
#define | SDIO_INT_RFF BIT(17)
#define | SDIO_INT_TFE BIT(18)
#define | SDIO_INT_RFE BIT(19)
#define | SDIO_INT_TXDTVAL BIT(20)
#define | SDIO_INT_RXDTVAL BIT(21)
#define | SDIO_INT_SDIOINT BIT(22)
#define | SDIO_INT_ATAEND BIT(23)
#define | SDIO_INT_FLAG_CCRCERR BIT(0)
#define | SDIO_INT_FLAG_DTCRCERR BIT(1)
#define | SDIO_INT_FLAG_CMDTMOUT BIT(2)
#define | SDIO_INT_FLAG_DTTMOUT BIT(3)
#define | SDIO_INT_FLAG_TXURE BIT(4)
#define | SDIO_INT_FLAG_RXORE BIT(5)
#define | SDIO_INT_FLAG_CMDRECV BIT(6)
#define | SDIO_INT_FLAG_CMDSEND BIT(7)
#define | SDIO_INT_FLAG_DTEND BIT(8)
#define | SDIO_INT_FLAG_STBITE BIT(9)
#define | SDIO_INT_FLAG_DTBLKEND BIT(10)
#define | SDIO_INT_FLAG_CMDRUN BIT(11)
#define | SDIO_INT_FLAG_TXRUN BIT(12)
#define | SDIO_INT_FLAG_RXRUN BIT(13)
#define | SDIO_INT_FLAG_TFH BIT(14)
#define | SDIO_INT_FLAG_RFH BIT(15)
#define | SDIO_INT_FLAG_TFF BIT(16)
#define | SDIO_INT_FLAG_RFF BIT(17)
#define | SDIO_INT_FLAG_TFE BIT(18)
#define | SDIO_INT_FLAG_RFE BIT(19)
#define | SDIO_INT_FLAG_TXDTVAL BIT(20)
#define | SDIO_INT_FLAG_RXDTVAL BIT(21)
#define | SDIO_INT_FLAG_SDIOINT BIT(22)
#define | SDIO_INT_FLAG_ATAEND BIT(23)
#define | PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define | SDIO_POWER_OFF PWRCTL_PWRCTL(0)
#define | SDIO_POWER_ON PWRCTL_PWRCTL(3)
#define | CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
#define | SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0)
#define | SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1)
#define | SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2)
#define | SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U
#define | SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE
#define | SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U
#define | SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP
#define | SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U
#define | SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV
#define | CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
#define | SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0)
#define | SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1)
#define | SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3)
#define | SDIO_WAITTYPE_NO (uint32_t)0x00000000U
#define | SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT
#define | SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND
#define | SDIO_RESPONSE0 (uint32_t)0x00000000U
#define | SDIO_RESPONSE1 (uint32_t)0x00000001U
#define | SDIO_RESPONSE2 (uint32_t)0x00000002U
#define | SDIO_RESPONSE3 (uint32_t)0x00000003U
#define | DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
#define | SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0)
#define | SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1)
#define | SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2)
#define | SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3)
#define | SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4)
#define | SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5)
#define | SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6)
#define | SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7)
#define | SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8)
#define | SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9)
#define | SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10)
#define | SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11)
#define | SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12)
#define | SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13)
#define | SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14)
#define | SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U
#define | SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD
#define | SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U
#define | SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR
#define | SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U
#define | SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE

Functions

void | sdio_deinit (void)
deinitialize the SDIO More...
void | sdio_clock_config (uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division)
configure the SDIO clock More...
void | sdio_hardware_clock_enable (void)
enable hardware clock control More...
void | sdio_hardware_clock_disable (void)
disable hardware clock control More...
void | sdio_bus_mode_set (uint32_t bus_mode)
set different SDIO card bus mode More...
void | sdio_power_state_set (uint32_t power_state)
set the SDIO power state More...
uint32_t | sdio_power_state_get (void)
get the SDIO power state More...
void | sdio_clock_enable (void)
enable SDIO_CLK clock output More...
void | sdio_clock_disable (void)
disable SDIO_CLK clock output More...
void | sdio_command_response_config (uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type)
configure the command and response More...
void | sdio_wait_type_set (uint32_t wait_type)
set the command state machine wait type More...
void | sdio_csm_enable (void)
enable the CSM(command state machine) More...
void | sdio_csm_disable (void)
disable the CSM(command state machine) More...
uint8_t | sdio_command_index_get (void)
get the last response command index More...
uint32_t | sdio_response_get (uint32_t responsex)
get the response for the last received command More...
void | sdio_data_config (uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize)
configure the data timeout, data length and data block size More...
void | sdio_data_transfer_config (uint32_t transfer_mode, uint32_t transfer_direction)
configure the data transfer mode and direction More...
void | sdio_dsm_enable (void)
enable the DSM(data state machine) for data transfer More...
void | sdio_dsm_disable (void)
disable the DSM(data state machine) More...
void | sdio_data_write (uint32_t data)
write data(one word) to the transmit FIFO More...
uint32_t | sdio_data_read (void)
read data(one word) from the receive FIFO More...
uint32_t | sdio_data_counter_get (void)
get the number of remaining data bytes to be transferred to card More...
uint32_t | sdio_fifo_counter_get (void)
get the number of words remaining to be written or read from FIFO More...
void | sdio_dma_enable (void)
enable the DMA request for SDIO More...
void | sdio_dma_disable (void)
disable the DMA request for SDIO More...
FlagStatus | sdio_flag_get (uint32_t flag)
get the flags state of SDIO More...
void | sdio_flag_clear (uint32_t flag)
clear the pending flags of SDIO More...
void | sdio_interrupt_enable (uint32_t int_flag)
enable the SDIO interrupt More...
void | sdio_interrupt_disable (uint32_t int_flag)
disable the SDIO interrupt More...
FlagStatus | sdio_interrupt_flag_get (uint32_t int_flag)
get the interrupt flags state of SDIO More...
void | sdio_interrupt_flag_clear (uint32_t int_flag)
clear the interrupt pending flags of SDIO More...
void | sdio_readwait_enable (void)
enable the read wait mode(SD I/O only) More...
void | sdio_readwait_disable (void)
disable the read wait mode(SD I/O only) More...
void | sdio_stop_readwait_enable (void)
enable the function that stop the read wait process(SD I/O only) More...
void | sdio_stop_readwait_disable (void)
disable the function that stop the read wait process(SD I/O only) More...
void | sdio_readwait_type_set (uint32_t readwait_type)
set the read wait type(SD I/O only) More...
void | sdio_operation_enable (void)
enable the SD I/O mode specific operation(SD I/O only) More...
void | sdio_operation_disable (void)
disable the SD I/O mode specific operation(SD I/O only) More...
void | sdio_suspend_enable (void)
enable the SD I/O suspend operation(SD I/O only) More...
void | sdio_suspend_disable (void)
disable the SD I/O suspend operation(SD I/O only) More...
void | sdio_ceata_command_enable (void)
enable the CE-ATA command(CE-ATA only) More...
void | sdio_ceata_command_disable (void)
disable the CE-ATA command(CE-ATA only) More...
void | sdio_ceata_interrupt_enable (void)
enable the CE-ATA interrupt(CE-ATA only) More...
void | sdio_ceata_interrupt_disable (void)
disable the CE-ATA interrupt(CE-ATA only) More...
void | sdio_ceata_command_completion_enable (void)
enable the CE-ATA command completion signal(CE-ATA only) More...
void | sdio_ceata_command_completion_disable (void)
disable the CE-ATA command completion signal(CE-ATA only) More...

Detailed Description

definitions for the SDIO

Definition in file gd32f10x_sdio.h.

Macro Definition Documentation

#define CLKCTL_BUSMODE ( regval ) (BITS(11,12) & ((uint32_t)(regval) << 11))

Definition at line 240 of file gd32f10x_sdio.h.

#define CMDCTL_CMDRESP ( regval ) (BITS(6,7) & ((uint32_t)(regval) << 6))

Definition at line 258 of file gd32f10x_sdio.h.

#define DATACTL_BLKSZ ( regval ) (BITS(4,7) & ((uint32_t)(regval) << 4))

Definition at line 274 of file gd32f10x_sdio.h.

#define PWRCTL_PWRCTL ( regval ) (BITS(0,1) & ((uint32_t)(regval) << 0))

Definition at line 235 of file gd32f10x_sdio.h.

#define SDIO SDIO_BASE

Definition at line 19 of file gd32f10x_sdio.h.

#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0)

1-bit SDIO card bus mode

Definition at line 241 of file gd32f10x_sdio.h.

#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1)

4-bit SDIO card bus mode

Definition at line 242 of file gd32f10x_sdio.h.

#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2)

8-bit SDIO card bus mode

Definition at line 243 of file gd32f10x_sdio.h.

#define SDIO_CLKCTL REG32(SDIO + 0x04U)

SDIO clock control register

Definition at line 23 of file gd32f10x_sdio.h.

#define SDIO_CLKCTL_BUSMODE BITS(11,12)

SDIO card bus mode control bit

Definition at line 50 of file gd32f10x_sdio.h.

#define SDIO_CLKCTL_CLKBYP BIT(10)

clock bypass enable bit

Definition at line 49 of file gd32f10x_sdio.h.

#define SDIO_CLKCTL_CLKEDGE BIT(13)

SDIO_CLK clock edge selection bit

Definition at line 51 of file gd32f10x_sdio.h.

#define SDIO_CLKCTL_CLKEN BIT(8)

SDIO_CLK clock output enable bit

Definition at line 47 of file gd32f10x_sdio.h.

#define SDIO_CLKCTL_CLKPWRSAV BIT(9)

SDIO_CLK clock dynamic switch on/off for power saving

Definition at line 48 of file gd32f10x_sdio.h.

#define SDIO_CLKCTL_DIV BITS(0,7)

clock division

Definition at line 46 of file gd32f10x_sdio.h.

#define SDIO_CLKCTL_HWCLKEN BIT(14)

hardware clock control enable bit

Definition at line 52 of file gd32f10x_sdio.h.

#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U

no bypass

Definition at line 250 of file gd32f10x_sdio.h.

#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP

clock bypass

Definition at line 251 of file gd32f10x_sdio.h.

#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U

SDIO_CLK clock is always on

Definition at line 254 of file gd32f10x_sdio.h.

#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV

SDIO_CLK closed when bus is idle

Definition at line 255 of file gd32f10x_sdio.h.

#define SDIO_CMDAGMT REG32(SDIO + 0x08U)

SDIO command argument register

Definition at line 24 of file gd32f10x_sdio.h.

#define SDIO_CMDAGMT_CMDAGMT BITS(0,31)

SDIO card command argument

Definition at line 55 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL REG32(SDIO + 0x0CU)

SDIO command control register

Definition at line 25 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL_ATAEN BIT(14)

CE-ATA command enable(CE-ATA only)

Definition at line 66 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL_CMDIDX BITS(0,5)

command index

Definition at line 58 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL_CMDRESP BITS(6,7)

command response type bits

Definition at line 59 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL_CSMEN BIT(10)

command state machine(CSM) enable bit

Definition at line 62 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL_ENCMDC BIT(12)

CMD completion signal enabled (CE-ATA only)

Definition at line 64 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL_INTWAIT BIT(8)

interrupt wait instead of timeout

Definition at line 60 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL_NINTEN BIT(13)

no CE-ATA interrupt (CE-ATA only)

Definition at line 65 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL_SUSPEND BIT(11)

SD I/O suspend command(SD I/O only)

Definition at line 63 of file gd32f10x_sdio.h.

#define SDIO_CMDCTL_WAITDEND BIT(9)

wait for ends of data transfer

Definition at line 61 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10)

block size = 1024 bytes

Definition at line 285 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7)

block size = 128 bytes

Definition at line 282 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14)

block size = 16384 bytes

Definition at line 289 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4)

block size = 16 bytes

Definition at line 279 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0)

block size = 1 byte

Definition at line 275 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11)

block size = 2048 bytes

Definition at line 286 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8)

block size = 256 bytes

Definition at line 283 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1)

block size = 2 bytes

Definition at line 276 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5)

block size = 32 bytes

Definition at line 280 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12)

block size = 4096 bytes

Definition at line 287 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2)

block size = 4 bytes

Definition at line 277 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9)

block size = 512 bytes

Definition at line 284 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6)

block size = 64 bytes

Definition at line 281 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13)

block size = 8192 bytes

Definition at line 288 of file gd32f10x_sdio.h.

#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3)

block size = 8 bytes

Definition at line 278 of file gd32f10x_sdio.h.

#define SDIO_DATACNT REG32(SDIO + 0x30U)

SDIO data counter register

Definition at line 34 of file gd32f10x_sdio.h.

#define SDIO_DATACTL REG32(SDIO + 0x2CU)

SDIO data control register

Definition at line 33 of file gd32f10x_sdio.h.

#define SDIO_DATACTL_BLKSZ BITS(4,7)

data block size

Definition at line 79 of file gd32f10x_sdio.h.

#define SDIO_DATACTL_DATADIR BIT(1)

data transfer direction

Definition at line 76 of file gd32f10x_sdio.h.

#define SDIO_DATACTL_DATAEN BIT(0)

data transfer enabled bit

Definition at line 75 of file gd32f10x_sdio.h.

#define SDIO_DATACTL_DMAEN BIT(3)

DMA enable bit

Definition at line 78 of file gd32f10x_sdio.h.

#define SDIO_DATACTL_IOEN BIT(11)

SD I/O specific function enable(SD I/O only)

Definition at line 83 of file gd32f10x_sdio.h.

#define SDIO_DATACTL_RWEN BIT(8)

read wait mode enabled(SD I/O only)

Definition at line 80 of file gd32f10x_sdio.h.

#define SDIO_DATACTL_RWSTOP BIT(9)

read wait stop(SD I/O only)

Definition at line 81 of file gd32f10x_sdio.h.

#define SDIO_DATACTL_RWTYPE BIT(10)

read wait type(SD I/O only)

Definition at line 82 of file gd32f10x_sdio.h.

#define SDIO_DATACTL_TRANSMOD BIT(2)

data transfer mode

Definition at line 77 of file gd32f10x_sdio.h.

#define SDIO_DATALEN REG32(SDIO + 0x28U)

SDIO data length register

Definition at line 32 of file gd32f10x_sdio.h.

#define SDIO_DATALEN_DATALEN BITS(0,24)

data transfer length

Definition at line 72 of file gd32f10x_sdio.h.

#define SDIO_DATATO REG32(SDIO + 0x24U)

SDIO data timeout register

Definition at line 31 of file gd32f10x_sdio.h.

#define SDIO_DATATO_DATATO BITS(0,31)

data timeout period

Definition at line 69 of file gd32f10x_sdio.h.

#define SDIO_FIFO REG32(SDIO + 0x80U)

SDIO FIFO data register

Definition at line 39 of file gd32f10x_sdio.h.

#define SDIO_FIFO_FIFODT BITS(0,31)

receive FIFO data or transmit FIFO data

Definition at line 153 of file gd32f10x_sdio.h.

#define SDIO_FIFOCNT REG32(SDIO + 0x48U)

SDIO FIFO counter register

Definition at line 38 of file gd32f10x_sdio.h.

#define SDIO_FLAG_ATAEND BIT(23)

CE-ATA command completion signal received (only for CMD61) flag

Definition at line 180 of file gd32f10x_sdio.h.

#define SDIO_FLAG_CCRCERR BIT(0)

command response received (CRC check failed) flag

Definition at line 157 of file gd32f10x_sdio.h.

#define SDIO_FLAG_CMDRECV BIT(6)

command response received (CRC check passed) flag

Definition at line 163 of file gd32f10x_sdio.h.

#define SDIO_FLAG_CMDRUN BIT(11)

command transmission in progress flag

Definition at line 168 of file gd32f10x_sdio.h.

#define SDIO_FLAG_CMDSEND BIT(7)

command sent (no response required) flag

Definition at line 164 of file gd32f10x_sdio.h.

#define SDIO_FLAG_CMDTMOUT BIT(2)

command response timeout flag

Definition at line 159 of file gd32f10x_sdio.h.

#define SDIO_FLAG_DTBLKEND BIT(10)

data block sent/received (CRC check passed) flag

Definition at line 167 of file gd32f10x_sdio.h.

#define SDIO_FLAG_DTCRCERR BIT(1)

data block sent/received (CRC check failed) flag

Definition at line 158 of file gd32f10x_sdio.h.

#define SDIO_FLAG_DTEND BIT(8)

data end (data counter, SDIO_DATACNT, is zero) flag

Definition at line 165 of file gd32f10x_sdio.h.

#define SDIO_FLAG_DTTMOUT BIT(3)

data timeout flag

Definition at line 160 of file gd32f10x_sdio.h.

#define SDIO_FLAG_RFE BIT(19)

receive FIFO is empty flag

Definition at line 176 of file gd32f10x_sdio.h.

#define SDIO_FLAG_RFF BIT(17)

receive FIFO is full flag

Definition at line 174 of file gd32f10x_sdio.h.

#define SDIO_FLAG_RFH BIT(15)

receive FIFO is half full flag: at least 8 words can be read in the FIFO

Definition at line 172 of file gd32f10x_sdio.h.

#define SDIO_FLAG_RXDTVAL BIT(21)

data is valid in receive FIFO flag

Definition at line 178 of file gd32f10x_sdio.h.

#define SDIO_FLAG_RXORE BIT(5)

received FIFO overrun error occurs flag

Definition at line 162 of file gd32f10x_sdio.h.

#define SDIO_FLAG_RXRUN BIT(13)

data reception in progress flag

Definition at line 170 of file gd32f10x_sdio.h.

#define SDIO_FLAG_SDIOINT BIT(22)

SD I/O interrupt received flag

Definition at line 179 of file gd32f10x_sdio.h.

#define SDIO_FLAG_STBITE BIT(9)

start bit error in the bus flag

Definition at line 166 of file gd32f10x_sdio.h.

#define SDIO_FLAG_TFE BIT(18)

transmit FIFO is empty flag

Definition at line 175 of file gd32f10x_sdio.h.

#define SDIO_FLAG_TFF BIT(16)

transmit FIFO is full flag

Definition at line 173 of file gd32f10x_sdio.h.

#define SDIO_FLAG_TFH BIT(14)

transmit FIFO is half empty flag: at least 8 words can be written into the FIFO

Definition at line 171 of file gd32f10x_sdio.h.

#define SDIO_FLAG_TXDTVAL BIT(20)

data is valid in transmit FIFO flag

Definition at line 177 of file gd32f10x_sdio.h.

#define SDIO_FLAG_TXRUN BIT(12)

data transmission in progress flag

Definition at line 169 of file gd32f10x_sdio.h.

#define SDIO_FLAG_TXURE BIT(4)

transmit FIFO underrun error occurs flag

Definition at line 161 of file gd32f10x_sdio.h.

#define SDIO_INT_ATAEND BIT(23)

SDIO ATAEND interrupt

Definition at line 206 of file gd32f10x_sdio.h.

#define SDIO_INT_CCRCERR BIT(0)

SDIO CCRCERR interrupt

Definition at line 183 of file gd32f10x_sdio.h.

#define SDIO_INT_CMDRECV BIT(6)

SDIO CMDRECV interrupt

Definition at line 189 of file gd32f10x_sdio.h.

#define SDIO_INT_CMDRUN BIT(11)

SDIO CMDRUN interrupt

Definition at line 194 of file gd32f10x_sdio.h.

#define SDIO_INT_CMDSEND BIT(7)

SDIO CMDSEND interrupt

Definition at line 190 of file gd32f10x_sdio.h.

#define SDIO_INT_CMDTMOUT BIT(2)

SDIO CMDTMOUT interrupt

Definition at line 185 of file gd32f10x_sdio.h.

#define SDIO_INT_DTBLKEND BIT(10)

SDIO DTBLKEND interrupt

Definition at line 193 of file gd32f10x_sdio.h.

#define SDIO_INT_DTCRCERR BIT(1)

SDIO DTCRCERR interrupt

Definition at line 184 of file gd32f10x_sdio.h.

#define SDIO_INT_DTEND BIT(8)

SDIO DTEND interrupt

Definition at line 191 of file gd32f10x_sdio.h.

#define SDIO_INT_DTTMOUT BIT(3)

SDIO DTTMOUT interrupt

Definition at line 186 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_ATAEND BIT(23)

SDIO ATAEND interrupt

Definition at line 232 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_CCRCERR BIT(0)

SDIO CCRCERR interrupt

Definition at line 209 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_CMDRECV BIT(6)

SDIO CMDRECV interrupt

Definition at line 215 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_CMDRUN BIT(11)

SDIO CMDRUN interrupt

Definition at line 220 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_CMDSEND BIT(7)

SDIO CMDSEND interrupt

Definition at line 216 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_CMDTMOUT BIT(2)

SDIO CMDTMOUT interrupt

Definition at line 211 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_DTBLKEND BIT(10)

SDIO DTBLKEND interrupt

Definition at line 219 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_DTCRCERR BIT(1)

SDIO DTCRCERR interrupt

Definition at line 210 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_DTEND BIT(8)

SDIO DTEND interrupt

Definition at line 217 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_DTTMOUT BIT(3)

SDIO DTTMOUT interrupt

Definition at line 212 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_RFE BIT(19)

SDIO RFE interrupt

Definition at line 228 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_RFF BIT(17)

SDIO RFF interrupt

Definition at line 226 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_RFH BIT(15)

SDIO RFH interrupt

Definition at line 224 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_RXDTVAL BIT(21)

SDIO RXDTVAL interrupt

Definition at line 230 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_RXORE BIT(5)

SDIO RXORE interrupt

Definition at line 214 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_RXRUN BIT(13)

SDIO RXRUN interrupt

Definition at line 222 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_SDIOINT BIT(22)

SDIO SDIOINT interrupt

Definition at line 231 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_STBITE BIT(9)

SDIO STBITE interrupt

Definition at line 218 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_TFE BIT(18)

SDIO TFE interrupt

Definition at line 227 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_TFF BIT(16)

SDIO TFF interrupt

Definition at line 225 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_TFH BIT(14)

SDIO TFH interrupt

Definition at line 223 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_TXDTVAL BIT(20)

SDIO TXDTVAL interrupt

Definition at line 229 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_TXRUN BIT(12)

SDIO TXRUN interrupt

Definition at line 221 of file gd32f10x_sdio.h.

#define SDIO_INT_FLAG_TXURE BIT(4)

SDIO TXURE interrupt

Definition at line 213 of file gd32f10x_sdio.h.

#define SDIO_INT_RFE BIT(19)

SDIO RFE interrupt

Definition at line 202 of file gd32f10x_sdio.h.

#define SDIO_INT_RFF BIT(17)

SDIO RFF interrupt

Definition at line 200 of file gd32f10x_sdio.h.

#define SDIO_INT_RFH BIT(15)

SDIO RFH interrupt

Definition at line 198 of file gd32f10x_sdio.h.

#define SDIO_INT_RXDTVAL BIT(21)

SDIO RXDTVAL interrupt

Definition at line 204 of file gd32f10x_sdio.h.

#define SDIO_INT_RXORE BIT(5)

SDIO RXORE interrupt

Definition at line 188 of file gd32f10x_sdio.h.

#define SDIO_INT_RXRUN BIT(13)

SDIO RXRUN interrupt

Definition at line 196 of file gd32f10x_sdio.h.

#define SDIO_INT_SDIOINT BIT(22)

SDIO SDIOINT interrupt

Definition at line 205 of file gd32f10x_sdio.h.

#define SDIO_INT_STBITE BIT(9)

SDIO STBITE interrupt

Definition at line 192 of file gd32f10x_sdio.h.

#define SDIO_INT_TFE BIT(18)

SDIO TFE interrupt

Definition at line 201 of file gd32f10x_sdio.h.

#define SDIO_INT_TFF BIT(16)

SDIO TFF interrupt

Definition at line 199 of file gd32f10x_sdio.h.

#define SDIO_INT_TFH BIT(14)

SDIO TFH interrupt

Definition at line 197 of file gd32f10x_sdio.h.

#define SDIO_INT_TXDTVAL BIT(20)

SDIO TXDTVAL interrupt

Definition at line 203 of file gd32f10x_sdio.h.

#define SDIO_INT_TXRUN BIT(12)

SDIO TXRUN interrupt

Definition at line 195 of file gd32f10x_sdio.h.

#define SDIO_INT_TXURE BIT(4)

SDIO TXURE interrupt

Definition at line 187 of file gd32f10x_sdio.h.

#define SDIO_INTC REG32(SDIO + 0x38U)

SDIO interrupt clear register

Definition at line 36 of file gd32f10x_sdio.h.

#define SDIO_INTC_ATAENDC BIT(23)

ATAEND flag clear bit

Definition at line 124 of file gd32f10x_sdio.h.

#define SDIO_INTC_CCRCERRC BIT(0)

CCRCERR flag clear bit

Definition at line 112 of file gd32f10x_sdio.h.

#define SDIO_INTC_CMDRECVC BIT(6)

CMDRECV flag clear bit

Definition at line 118 of file gd32f10x_sdio.h.

#define SDIO_INTC_CMDSENDC BIT(7)

CMDSEND flag clear bit

Definition at line 119 of file gd32f10x_sdio.h.

#define SDIO_INTC_CMDTMOUTC BIT(2)

CMDTMOUT flag clear bit

Definition at line 114 of file gd32f10x_sdio.h.

#define SDIO_INTC_DTBLKENDC BIT(10)

DTBLKEND flag clear bit

Definition at line 122 of file gd32f10x_sdio.h.

#define SDIO_INTC_DTCRCERRC BIT(1)

DTCRCERR flag clear bit

Definition at line 113 of file gd32f10x_sdio.h.

#define SDIO_INTC_DTENDC BIT(8)

DTEND flag clear bit

Definition at line 120 of file gd32f10x_sdio.h.

#define SDIO_INTC_DTTMOUTC BIT(3)

DTTMOUT flag clear bit

Definition at line 115 of file gd32f10x_sdio.h.

#define SDIO_INTC_RXOREC BIT(5)

RXORE flag clear bit

Definition at line 117 of file gd32f10x_sdio.h.

#define SDIO_INTC_SDIOINTC BIT(22)

SDIOINT flag clear bit

Definition at line 123 of file gd32f10x_sdio.h.

#define SDIO_INTC_STBITEC BIT(9)

STBITE flag clear bit

Definition at line 121 of file gd32f10x_sdio.h.

#define SDIO_INTC_TXUREC BIT(4)

TXURE flag clear bit

Definition at line 116 of file gd32f10x_sdio.h.

#define SDIO_INTEN REG32(SDIO + 0x3CU)

SDIO interrupt enable register

Definition at line 37 of file gd32f10x_sdio.h.

#define SDIO_INTEN_ATAENDIE BIT(23)

CE-ATA command completion signal received interrupt enable

Definition at line 150 of file gd32f10x_sdio.h.

#define SDIO_INTEN_CCRCERRIE BIT(0)

command response CRC fail interrupt enable

Definition at line 127 of file gd32f10x_sdio.h.

#define SDIO_INTEN_CMDRECVIE BIT(6)

command response received interrupt enable

Definition at line 133 of file gd32f10x_sdio.h.

#define SDIO_INTEN_CMDRUNIE BIT(11)

command transmission interrupt enable

Definition at line 138 of file gd32f10x_sdio.h.

#define SDIO_INTEN_CMDSENDIE BIT(7)

command sent interrupt enable

Definition at line 134 of file gd32f10x_sdio.h.

#define SDIO_INTEN_CMDTMOUTIE BIT(2)

command response timeout interrupt enable

Definition at line 129 of file gd32f10x_sdio.h.

#define SDIO_INTEN_DTBLKENDIE BIT(10)

data block end interrupt enable

Definition at line 137 of file gd32f10x_sdio.h.

#define SDIO_INTEN_DTCRCERRIE BIT(1)

data CRC fail interrupt enable

Definition at line 128 of file gd32f10x_sdio.h.

#define SDIO_INTEN_DTENDIE BIT(8)

data end interrupt enable

Definition at line 135 of file gd32f10x_sdio.h.

#define SDIO_INTEN_DTTMOUTIE BIT(3)

data timeout interrupt enable

Definition at line 130 of file gd32f10x_sdio.h.

#define SDIO_INTEN_RFEIE BIT(19)

receive FIFO empty interrupt enable

Definition at line 146 of file gd32f10x_sdio.h.

#define SDIO_INTEN_RFFIE BIT(17)

receive FIFO full interrupt enable

Definition at line 144 of file gd32f10x_sdio.h.

#define SDIO_INTEN_RFHIE BIT(15)

receive FIFO half full interrupt enable

Definition at line 142 of file gd32f10x_sdio.h.

#define SDIO_INTEN_RXDTVALIE BIT(21)

data valid in receive FIFO interrupt enable

Definition at line 148 of file gd32f10x_sdio.h.

#define SDIO_INTEN_RXOREIE BIT(5)

received FIFO overrun error interrupt enable

Definition at line 132 of file gd32f10x_sdio.h.

#define SDIO_INTEN_RXRUNIE BIT(13)

data reception interrupt enable

Definition at line 140 of file gd32f10x_sdio.h.

#define SDIO_INTEN_SDIOINTIE BIT(22)

SD I/O interrupt received interrupt enable

Definition at line 149 of file gd32f10x_sdio.h.

#define SDIO_INTEN_STBITEIE BIT(9)

start bit error interrupt enable

Definition at line 136 of file gd32f10x_sdio.h.

#define SDIO_INTEN_TFEIE BIT(18)

transmit FIFO empty interrupt enable

Definition at line 145 of file gd32f10x_sdio.h.

#define SDIO_INTEN_TFFIE BIT(16)

transmit FIFO full interrupt enable

Definition at line 143 of file gd32f10x_sdio.h.

#define SDIO_INTEN_TFHIE BIT(14)

transmit FIFO half empty interrupt enable

Definition at line 141 of file gd32f10x_sdio.h.

#define SDIO_INTEN_TXDTVALIE BIT(20)

data valid in transmit FIFO interrupt enable

Definition at line 147 of file gd32f10x_sdio.h.

#define SDIO_INTEN_TXRUNIE BIT(12)

data transmission interrupt enable

Definition at line 139 of file gd32f10x_sdio.h.

#define SDIO_INTEN_TXUREIE BIT(4)

transmit FIFO underrun error interrupt enable

Definition at line 131 of file gd32f10x_sdio.h.

#define SDIO_POWER_OFF PWRCTL_PWRCTL(0)

SDIO power off

Definition at line 236 of file gd32f10x_sdio.h.

#define SDIO_POWER_ON PWRCTL_PWRCTL(3)

SDIO power on

Definition at line 237 of file gd32f10x_sdio.h.

#define SDIO_PWRCTL REG32(SDIO + 0x00U)

SDIO power control register

Definition at line 22 of file gd32f10x_sdio.h.

#define SDIO_PWRCTL_PWRCTL BITS(0,1)

SDIO power control bits

Definition at line 43 of file gd32f10x_sdio.h.

#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE

read wait control by stopping SDIO_CLK

Definition at line 301 of file gd32f10x_sdio.h.

#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U

read wait control using SDIO_DAT[2]

Definition at line 300 of file gd32f10x_sdio.h.

#define SDIO_RESP0 REG32(SDIO + 0x14U)

SDIO response register 0

Definition at line 27 of file gd32f10x_sdio.h.

#define SDIO_RESP1 REG32(SDIO + 0x18U)

SDIO response register 1

Definition at line 28 of file gd32f10x_sdio.h.

#define SDIO_RESP2 REG32(SDIO + 0x1CU)

SDIO response register 2

Definition at line 29 of file gd32f10x_sdio.h.

#define SDIO_RESP3 REG32(SDIO + 0x20U)

SDIO response register 3

Definition at line 30 of file gd32f10x_sdio.h.

#define SDIO_RESPONSE0 (uint32_t)0x00000000U

card response[31:0]/card response[127:96]

Definition at line 268 of file gd32f10x_sdio.h.

#define SDIO_RESPONSE1 (uint32_t)0x00000001U

card response[95:64]

Definition at line 269 of file gd32f10x_sdio.h.

#define SDIO_RESPONSE2 (uint32_t)0x00000002U

card response[63:32]

Definition at line 270 of file gd32f10x_sdio.h.

#define SDIO_RESPONSE3 (uint32_t)0x00000003U

card response[31:1], plus bit 0

Definition at line 271 of file gd32f10x_sdio.h.

#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3)

long response

Definition at line 261 of file gd32f10x_sdio.h.

#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0)

no response

Definition at line 259 of file gd32f10x_sdio.h.

#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1)

short response

Definition at line 260 of file gd32f10x_sdio.h.

#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U)

SDIO command index response register

Definition at line 26 of file gd32f10x_sdio.h.

#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE

select the falling edge of the SDIOCLK to generate SDIO_CLK

Definition at line 247 of file gd32f10x_sdio.h.

#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U

select the rising edge of the SDIOCLK to generate SDIO_CLK

Definition at line 246 of file gd32f10x_sdio.h.

#define SDIO_STAT REG32(SDIO + 0x34U)

SDIO status register

Definition at line 35 of file gd32f10x_sdio.h.

#define SDIO_STAT_ATAEND BIT(23)

CE-ATA command completion signal received (only for CMD61)

Definition at line 109 of file gd32f10x_sdio.h.

#define SDIO_STAT_CCRCERR BIT(0)

command response received (CRC check failed)

Definition at line 86 of file gd32f10x_sdio.h.

#define SDIO_STAT_CMDRECV BIT(6)

command response received (CRC check passed)

Definition at line 92 of file gd32f10x_sdio.h.

#define SDIO_STAT_CMDRUN BIT(11)

command transmission in progress

Definition at line 97 of file gd32f10x_sdio.h.

#define SDIO_STAT_CMDSEND BIT(7)

command sent (no response required)

Definition at line 93 of file gd32f10x_sdio.h.

#define SDIO_STAT_CMDTMOUT BIT(2)

command response timeout

Definition at line 88 of file gd32f10x_sdio.h.

#define SDIO_STAT_DTBLKEND BIT(10)

data block sent/received (CRC check passed)

Definition at line 96 of file gd32f10x_sdio.h.

#define SDIO_STAT_DTCRCERR BIT(1)

data block sent/received (CRC check failed)

Definition at line 87 of file gd32f10x_sdio.h.

#define SDIO_STAT_DTEND BIT(8)

data end (data counter, SDIO_DATACNT, is zero)

Definition at line 94 of file gd32f10x_sdio.h.

#define SDIO_STAT_DTTMOUT BIT(3)

data timeout

Definition at line 89 of file gd32f10x_sdio.h.

#define SDIO_STAT_RFE BIT(19)

receive FIFO is empty

Definition at line 105 of file gd32f10x_sdio.h.

#define SDIO_STAT_RFF BIT(17)

receive FIFO is full

Definition at line 103 of file gd32f10x_sdio.h.

#define SDIO_STAT_RFH BIT(15)

receive FIFO is half full: at least 8 words can be read in the FIFO

Definition at line 101 of file gd32f10x_sdio.h.

#define SDIO_STAT_RXDTVAL BIT(21)

data is valid in receive FIFO

Definition at line 107 of file gd32f10x_sdio.h.

#define SDIO_STAT_RXORE BIT(5)

received FIFO overrun error occurs

Definition at line 91 of file gd32f10x_sdio.h.

#define SDIO_STAT_RXRUN BIT(13)

data reception in progress

Definition at line 99 of file gd32f10x_sdio.h.

#define SDIO_STAT_SDIOINT BIT(22)

SD I/O interrupt received

Definition at line 108 of file gd32f10x_sdio.h.

#define SDIO_STAT_STBITE BIT(9)

start bit error in the bus

Definition at line 95 of file gd32f10x_sdio.h.

#define SDIO_STAT_TFE BIT(18)

transmit FIFO is empty

Definition at line 104 of file gd32f10x_sdio.h.

#define SDIO_STAT_TFF BIT(16)

transmit FIFO is full

Definition at line 102 of file gd32f10x_sdio.h.

#define SDIO_STAT_TFH BIT(14)

transmit FIFO is half empty: at least 8 words can be written into the FIFO

Definition at line 100 of file gd32f10x_sdio.h.

#define SDIO_STAT_TXDTVAL BIT(20)

data is valid in transmit FIFO

Definition at line 106 of file gd32f10x_sdio.h.

#define SDIO_STAT_TXRUN BIT(12)

data transmission in progress

Definition at line 98 of file gd32f10x_sdio.h.

#define SDIO_STAT_TXURE BIT(4)

transmit FIFO underrun error occurs

Definition at line 90 of file gd32f10x_sdio.h.

#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U

write data to card

Definition at line 296 of file gd32f10x_sdio.h.

#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR

read data from card

Definition at line 297 of file gd32f10x_sdio.h.

#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U

block transfer

Definition at line 292 of file gd32f10x_sdio.h.

#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD

stream transfer or SDIO multibyte transfer

Definition at line 293 of file gd32f10x_sdio.h.

#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND

wait the end of data transfer

Definition at line 266 of file gd32f10x_sdio.h.

#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT

wait interrupt

Definition at line 265 of file gd32f10x_sdio.h.

#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U

not wait interrupt

Definition at line 264 of file gd32f10x_sdio.h.

Function Documentation

void sdio_bus_mode_set ( uint32_t bus_mode )

set different SDIO card bus mode

Parameters
[in] bus_mode SDIO card bus mode
  • SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode
  • SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode
  • SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode
[out] none
Return values
none

Definition at line 94 of file gd32f10x_sdio.c.

95 {
96 /* reset the SDIO card bus mode bits and set according to bus_mode */
97 SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE;
98 SDIO_CLKCTL |= bus_mode;
99 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_BUSMODE
#define SDIO_CLKCTL_BUSMODE
Definition: gd32f10x_sdio.h:50
void sdio_ceata_command_completion_disable ( void )

disable the CE-ATA command completion signal(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 766 of file gd32f10x_sdio.c.

767 {
768 SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC;
769 }
SDIO_CMDCTL_ENCMDC
#define SDIO_CMDCTL_ENCMDC
Definition: gd32f10x_sdio.h:64
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_command_completion_enable ( void )

enable the CE-ATA command completion signal(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 755 of file gd32f10x_sdio.c.

756 {
757 SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC;
758 }
SDIO_CMDCTL_ENCMDC
#define SDIO_CMDCTL_ENCMDC
Definition: gd32f10x_sdio.h:64
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_command_disable ( void )

disable the CE-ATA command(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 722 of file gd32f10x_sdio.c.

723 {
724 SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN;
725 }
SDIO_CMDCTL_ATAEN
#define SDIO_CMDCTL_ATAEN
Definition: gd32f10x_sdio.h:66
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_command_enable ( void )

enable the CE-ATA command(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 711 of file gd32f10x_sdio.c.

712 {
713 SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN;
714 }
SDIO_CMDCTL_ATAEN
#define SDIO_CMDCTL_ATAEN
Definition: gd32f10x_sdio.h:66
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_interrupt_disable ( void )

disable the CE-ATA interrupt(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 744 of file gd32f10x_sdio.c.

745 {
746 SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN;
747 }
SDIO_CMDCTL_NINTEN
#define SDIO_CMDCTL_NINTEN
Definition: gd32f10x_sdio.h:65
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_interrupt_enable ( void )

enable the CE-ATA interrupt(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 733 of file gd32f10x_sdio.c.

734 {
735 SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN;
736 }
SDIO_CMDCTL_NINTEN
#define SDIO_CMDCTL_NINTEN
Definition: gd32f10x_sdio.h:65
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_clock_config | ( | uint32_t | clock_edge,
 |  | uint32_t | clock_bypass,
 |  | uint32_t | clock_powersave,
 |  | uint16_t | clock_division
 | ) |  |

configure the SDIO clock

Parameters
[in] clock_edge SDIO_CLK clock edge
  • SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK
  • SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK
[in] clock_bypass clock bypass
  • SDIO_CLOCKBYPASS_ENABLE: clock bypass
  • SDIO_CLOCKBYPASS_DISABLE: no bypass
[in] clock_powersave SDIO_CLK clock dynamic switch on/off for power saving
  • SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle
  • SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on
[in] | clock_division | clock division, less than 256
[out] | none
Return values
none

Definition at line 51 of file gd32f10x_sdio.c.

52 {
53 uint32_t clock_config = 0U;
54 clock_config = SDIO_CLKCTL;
55 /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */
56 clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV);
57
58 /* configure the SDIO_CLKCTL according to the parameters */
59 clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division);
60 SDIO_CLKCTL = clock_config;
61 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_CLKEDGE
#define SDIO_CLKCTL_CLKEDGE
Definition: gd32f10x_sdio.h:51
SDIO_CLKCTL_CLKBYP
#define SDIO_CLKCTL_CLKBYP
Definition: gd32f10x_sdio.h:49
SDIO_CLKCTL_CLKPWRSAV
#define SDIO_CLKCTL_CLKPWRSAV
Definition: gd32f10x_sdio.h:48
SDIO_CLKCTL_DIV
#define SDIO_CLKCTL_DIV
Definition: gd32f10x_sdio.h:46
void sdio_clock_disable ( void )

disable SDIO_CLK clock output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 144 of file gd32f10x_sdio.c.

145 {
146 SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN;
147 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_CLKEN
#define SDIO_CLKCTL_CLKEN
Definition: gd32f10x_sdio.h:47
void sdio_clock_enable ( void )

enable SDIO_CLK clock output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 133 of file gd32f10x_sdio.c.

134 {
135 SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN;
136 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_CLKEN
#define SDIO_CLKCTL_CLKEN
Definition: gd32f10x_sdio.h:47
uint8_t sdio_command_index_get ( void )

get the last response command index

Parameters
[in] | none
[out] | none
Return values
last response command index

Definition at line 218 of file gd32f10x_sdio.c.

219 {
220 return (uint8_t)SDIO_RSPCMDIDX;
221 }
SDIO_RSPCMDIDX
#define SDIO_RSPCMDIDX
Definition: gd32f10x_sdio.h:26
void sdio_command_response_config | ( | uint32_t | cmd_index,
 |  | uint32_t | cmd_argument,
 |  | uint32_t | response_type
 | ) |  |

configure the command and response

Parameters
[in] | cmd_index | command index, refer to the related specifications
[in] | cmd_argument | command argument, refer to the related specifications
[in] response_type response type
  • SDIO_RESPONSETYPE_NO: no response
  • SDIO_RESPONSETYPE_SHORT: short response
  • SDIO_RESPONSETYPE_LONG: long response
[out] | none
Return values
none

Definition at line 160 of file gd32f10x_sdio.c.

161 {
162 uint32_t cmd_config = 0U;
163 /* reset the command index, command argument and response type */
164 SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT;
165 SDIO_CMDAGMT = cmd_argument;
166 cmd_config = SDIO_CMDCTL;
167 cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP);
168 /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */
169 cmd_config |= (cmd_index | response_type);
170 SDIO_CMDCTL = cmd_config;
171 }
SDIO_CMDAGMT
#define SDIO_CMDAGMT
Definition: gd32f10x_sdio.h:24
SDIO_CMDCTL_CMDIDX
#define SDIO_CMDCTL_CMDIDX
Definition: gd32f10x_sdio.h:58
SDIO_CMDCTL_CMDRESP
#define SDIO_CMDCTL_CMDRESP
Definition: gd32f10x_sdio.h:59
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
SDIO_CMDAGMT_CMDAGMT
#define SDIO_CMDAGMT_CMDAGMT
Definition: gd32f10x_sdio.h:55
void sdio_csm_disable ( void )

disable the CSM(command state machine)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 207 of file gd32f10x_sdio.c.

208 {
209 SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN;
210 }
SDIO_CMDCTL_CSMEN
#define SDIO_CMDCTL_CSMEN
Definition: gd32f10x_sdio.h:62
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_csm_enable ( void )

enable the CSM(command state machine)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 196 of file gd32f10x_sdio.c.

197 {
198 SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN;
199 }
SDIO_CMDCTL_CSMEN
#define SDIO_CMDCTL_CSMEN
Definition: gd32f10x_sdio.h:62
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_data_config | ( | uint32_t | data_timeout,
 |  | uint32_t | data_length,
 |  | uint32_t | data_blocksize
 | ) |  |

configure the data timeout, data length and data block size

Parameters
[in] | data_timeout | data timeout period in card bus clock periods
[in] | data_length | number of data bytes to be transferred
[in] data_blocksize size of data block for block transfer
  • SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte
  • SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes
  • SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes
  • SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes
  • SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes
  • SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes
  • SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes
  • SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes
  • SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes
  • SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes
  • SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes
  • SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes
  • SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes
  • SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes
  • SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes
[out] | none
Return values
none

Definition at line 278 of file gd32f10x_sdio.c.

279 {
280 /* reset data timeout, data length and data block size */
281 SDIO_DATATO &= ~SDIO_DATATO_DATATO;
282 SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN;
283 SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ;
284 /* configure the related parameters of data */
285 SDIO_DATATO = data_timeout;
286 SDIO_DATALEN = data_length;
287 SDIO_DATACTL |= data_blocksize;
288 }
SDIO_DATATO
#define SDIO_DATATO
Definition: gd32f10x_sdio.h:31
SDIO_DATALEN_DATALEN
#define SDIO_DATALEN_DATALEN
Definition: gd32f10x_sdio.h:72
SDIO_DATALEN
#define SDIO_DATALEN
Definition: gd32f10x_sdio.h:32
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_BLKSZ
#define SDIO_DATACTL_BLKSZ
Definition: gd32f10x_sdio.h:79
SDIO_DATATO_DATATO
#define SDIO_DATATO_DATATO
Definition: gd32f10x_sdio.h:69
uint32_t sdio_data_counter_get ( void )

get the number of remaining data bytes to be transferred to card

Parameters
[in] | none
[out] | none
Return values
number of remaining data bytes to be transferred

Definition at line 361 of file gd32f10x_sdio.c.

362 {
363 return SDIO_DATACNT;
364 }
SDIO_DATACNT
#define SDIO_DATACNT
Definition: gd32f10x_sdio.h:34
uint32_t sdio_data_read ( void )

read data(one word) from the receive FIFO

Parameters
[in] | none
[out] | none
Return values
received data

Definition at line 350 of file gd32f10x_sdio.c.

351 {
352 return SDIO_FIFO;
353 }
SDIO_FIFO
#define SDIO_FIFO
Definition: gd32f10x_sdio.h:39
void sdio_data_transfer_config | ( | uint32_t | transfer_mode,
 |  | uint32_t | transfer_direction
 | ) |  |

configure the data transfer mode and direction

Parameters
[in] transfer_mode mode of data transfer
  • SDIO_TRANSMODE_BLOCK: block transfer
  • SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer
[in] transfer_direction data transfer direction, read or write
  • SDIO_TRANSDIRECTION_TOCARD: write data to card
  • SDIO_TRANSDIRECTION_TOSDIO: read data from card
[out] none
Return values
none

Definition at line 301 of file gd32f10x_sdio.c.

302 {
303 uint32_t data_trans = 0U;
304 /* reset the data transfer mode, transfer direction and set according to the parameters */
305 data_trans = SDIO_DATACTL;
306 data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR);
307 data_trans |= (transfer_mode | transfer_direction);
308 SDIO_DATACTL = data_trans;
309 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_TRANSMOD
#define SDIO_DATACTL_TRANSMOD
Definition: gd32f10x_sdio.h:77
SDIO_DATACTL_DATADIR
#define SDIO_DATACTL_DATADIR
Definition: gd32f10x_sdio.h:76
void sdio_data_write ( uint32_t data )

write data(one word) to the transmit FIFO

Parameters
[in] | data | 32-bit data write to card
[out] | none
Return values
none

Definition at line 339 of file gd32f10x_sdio.c.

340 {
341 SDIO_FIFO = data;
342 }
SDIO_FIFO
#define SDIO_FIFO
Definition: gd32f10x_sdio.h:39
void sdio_deinit ( void )

deinitialize the SDIO

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 23 of file gd32f10x_sdio.c.

24 {
25 SDIO_PWRCTL = DEFAULT_RESET_VALUE;
26 SDIO_CLKCTL = DEFAULT_RESET_VALUE;
27 SDIO_CMDAGMT = DEFAULT_RESET_VALUE;
28 SDIO_CMDCTL = DEFAULT_RESET_VALUE;
29 SDIO_DATATO = DEFAULT_RESET_VALUE;
30 SDIO_DATALEN = DEFAULT_RESET_VALUE;
31 SDIO_DATACTL = DEFAULT_RESET_VALUE;
32 SDIO_INTC = DEFAULT_RESET_VALUE;
33 SDIO_INTEN = DEFAULT_RESET_VALUE;
34 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_DATATO
#define SDIO_DATATO
Definition: gd32f10x_sdio.h:31
SDIO_CMDAGMT
#define SDIO_CMDAGMT
Definition: gd32f10x_sdio.h:24
SDIO_PWRCTL
#define SDIO_PWRCTL
Definition: gd32f10x_sdio.h:22
SDIO_DATALEN
#define SDIO_DATALEN
Definition: gd32f10x_sdio.h:32
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
SDIO_INTEN
#define SDIO_INTEN
Definition: gd32f10x_sdio.h:37
SDIO_INTC
#define SDIO_INTC
Definition: gd32f10x_sdio.h:36
DEFAULT_RESET_VALUE
#define DEFAULT_RESET_VALUE
Definition: gd32f10x_sdio.c:15
void sdio_dma_disable ( void )

disable the DMA request for SDIO

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 394 of file gd32f10x_sdio.c.

395 {
396 SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN;
397 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_DMAEN
#define SDIO_DATACTL_DMAEN
Definition: gd32f10x_sdio.h:78
void sdio_dma_enable ( void )

enable the DMA request for SDIO

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 383 of file gd32f10x_sdio.c.

384 {
385 SDIO_DATACTL |= SDIO_DATACTL_DMAEN;
386 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_DMAEN
#define SDIO_DATACTL_DMAEN
Definition: gd32f10x_sdio.h:78
void sdio_dsm_disable ( void )

disable the DSM(data state machine)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 328 of file gd32f10x_sdio.c.

329 {
330 SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN;
331 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_DATAEN
#define SDIO_DATACTL_DATAEN
Definition: gd32f10x_sdio.h:75
void sdio_dsm_enable ( void )

enable the DSM(data state machine) for data transfer

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 317 of file gd32f10x_sdio.c.

318 {
319 SDIO_DATACTL |= SDIO_DATACTL_DATAEN;
320 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_DATAEN
#define SDIO_DATACTL_DATAEN
Definition: gd32f10x_sdio.h:75
uint32_t sdio_fifo_counter_get ( void )

get the number of words remaining to be written or read from FIFO

Parameters
[in] | none
[out] | none
Return values
remaining number of words

Definition at line 372 of file gd32f10x_sdio.c.

373 {
374 return SDIO_FIFOCNT;
375 }
SDIO_FIFOCNT
#define SDIO_FIFOCNT
Definition: gd32f10x_sdio.h:38
void sdio_flag_clear ( uint32_t flag )

clear the pending flags of SDIO

Parameters
[in] flag flags state of SDIO
  • SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag
  • SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
  • SDIO_FLAG_CMDTMOUT: command response timeout flag
  • SDIO_FLAG_DTTMOUT: data timeout flag
  • SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag
  • SDIO_FLAG_RXORE: received FIFO overrun error occurs flag
  • SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag
  • SDIO_FLAG_CMDSEND: command sent (no response required) flag
  • SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
  • SDIO_FLAG_STBITE: start bit error in the bus flag
  • SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
  • SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
  • SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
[out] none
Return values
none

Definition at line 457 of file gd32f10x_sdio.c.

458 {
459 SDIO_INTC = flag;
460 }
SDIO_INTC
#define SDIO_INTC
Definition: gd32f10x_sdio.h:36
FlagStatus sdio_flag_get ( uint32_t flag )

get the flags state of SDIO

Parameters
[in] flag flags state of SDIO
  • SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag
  • SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
  • SDIO_FLAG_CMDTMOUT: command response timeout flag
  • SDIO_FLAG_DTTMOUT: data timeout flag
  • SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag
  • SDIO_FLAG_RXORE: received FIFO overrun error occurs flag
  • SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag
  • SDIO_FLAG_CMDSEND: command sent (no response required) flag
  • SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
  • SDIO_FLAG_STBITE: start bit error in the bus flag
  • SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
  • SDIO_FLAG_CMDRUN: command transmission in progress flag
  • SDIO_FLAG_TXRUN: data transmission in progress flag
  • SDIO_FLAG_RXRUN: data reception in progress flag
  • SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO
  • SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO
  • SDIO_FLAG_TFF: transmit FIFO is full flag
  • SDIO_FLAG_RFF: receive FIFO is full flag
  • SDIO_FLAG_TFE: transmit FIFO is empty flag
  • SDIO_FLAG_RFE: receive FIFO is empty flag
  • SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag
  • SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag
  • SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
  • SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 429 of file gd32f10x_sdio.c.

430 {
431 FlagStatus temp_flag = RESET;
432 if(RESET != (SDIO_STAT & flag)){
433 temp_flag = SET;
434 }
435 return temp_flag;
436 }
SDIO_STAT
#define SDIO_STAT
Definition: gd32f10x_sdio.h:35
void sdio_hardware_clock_disable ( void )

disable hardware clock control

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 80 of file gd32f10x_sdio.c.

81 {
82 SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN;
83 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_HWCLKEN
#define SDIO_CLKCTL_HWCLKEN
Definition: gd32f10x_sdio.h:52
void sdio_hardware_clock_enable ( void )

enable hardware clock control

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 69 of file gd32f10x_sdio.c.

70 {
71 SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN;
72 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_HWCLKEN
#define SDIO_CLKCTL_HWCLKEN
Definition: gd32f10x_sdio.h:52
void sdio_interrupt_disable ( uint32_t int_flag )

disable the SDIO interrupt

Parameters
[in] int_flag interrupt flags state of SDIO
  • SDIO_INT_CCRCERR: SDIO CCRCERR interrupt
  • SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt
  • SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt
  • SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt
  • SDIO_INT_TXURE: SDIO TXURE interrupt
  • SDIO_INT_RXORE: SDIO RXORE interrupt
  • SDIO_INT_CMDRECV: SDIO CMDRECV interrupt
  • SDIO_INT_CMDSEND: SDIO CMDSEND interrupt
  • SDIO_INT_DTEND: SDIO DTEND interrupt
  • SDIO_INT_STBITE: SDIO STBITE interrupt
  • SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt
  • SDIO_INT_CMDRUN: SDIO CMDRUN interrupt
  • SDIO_INT_TXRUN: SDIO TXRUN interrupt
  • SDIO_INT_RXRUN: SDIO RXRUN interrupt
  • SDIO_INT_TFH: SDIO TFH interrupt
  • SDIO_INT_RFH: SDIO RFH interrupt
  • SDIO_INT_TFF: SDIO TFF interrupt
  • SDIO_INT_RFF: SDIO RFF interrupt
  • SDIO_INT_TFE: SDIO TFE interrupt
  • SDIO_INT_RFE: SDIO RFE interrupt
  • SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt
  • SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt
  • SDIO_INT_SDIOINT: SDIO SDIOINT interrupt
  • SDIO_INT_ATAEND: SDIO ATAEND interrupt
[out] none
Return values
none

Definition at line 527 of file gd32f10x_sdio.c.

528 {
529 SDIO_INTEN &= ~int_flag;
530 }
SDIO_INTEN
#define SDIO_INTEN
Definition: gd32f10x_sdio.h:37
void sdio_interrupt_enable ( uint32_t int_flag )

enable the SDIO interrupt

Parameters
[in] int_flag interrupt flags state of SDIO
  • SDIO_INT_CCRCERR: SDIO CCRCERR interrupt
  • SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt
  • SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt
  • SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt
  • SDIO_INT_TXURE: SDIO TXURE interrupt
  • SDIO_INT_RXORE: SDIO RXORE interrupt
  • SDIO_INT_CMDRECV: SDIO CMDRECV interrupt
  • SDIO_INT_CMDSEND: SDIO CMDSEND interrupt
  • SDIO_INT_DTEND: SDIO DTEND interrupt
  • SDIO_INT_STBITE: SDIO STBITE interrupt
  • SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt
  • SDIO_INT_CMDRUN: SDIO CMDRUN interrupt
  • SDIO_INT_TXRUN: SDIO TXRUN interrupt
  • SDIO_INT_RXRUN: SDIO RXRUN interrupt
  • SDIO_INT_TFH: SDIO TFH interrupt
  • SDIO_INT_RFH: SDIO RFH interrupt
  • SDIO_INT_TFF: SDIO TFF interrupt
  • SDIO_INT_RFF: SDIO RFF interrupt
  • SDIO_INT_TFE: SDIO TFE interrupt
  • SDIO_INT_RFE: SDIO RFE interrupt
  • SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt
  • SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt
  • SDIO_INT_SDIOINT: SDIO SDIOINT interrupt
  • SDIO_INT_ATAEND: SDIO ATAEND interrupt
[out] none
Return values
none

Definition at line 492 of file gd32f10x_sdio.c.

493 {
494 SDIO_INTEN |= int_flag;
495 }
SDIO_INTEN
#define SDIO_INTEN
Definition: gd32f10x_sdio.h:37
void sdio_interrupt_flag_clear ( uint32_t int_flag )

clear the interrupt pending flags of SDIO

Parameters
[in] int_flag interrupt flags state of SDIO
  • SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag
  • SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
  • SDIO_INT_FLAG_CMDTMOUT: command response timeout flag
  • SDIO_INT_FLAG_DTTMOUT: data timeout flag
  • SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag
  • SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag
  • SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag
  • SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag
  • SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
  • SDIO_INT_FLAG_STBITE: start bit error in the bus flag
  • SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
  • SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag
  • SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
[out] none
Return values
none

Definition at line 595 of file gd32f10x_sdio.c.

596 {
597 SDIO_INTC = int_flag;
598 }
SDIO_INTC
#define SDIO_INTC
Definition: gd32f10x_sdio.h:36
FlagStatus sdio_interrupt_flag_get ( uint32_t int_flag )

get the interrupt flags state of SDIO

Parameters
[in] int_flag interrupt flags state of SDIO
  • SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt
  • SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt
  • SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt
  • SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt
  • SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt
  • SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt
  • SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt
  • SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt
  • SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt
  • SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt
  • SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt
  • SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt
  • SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt
  • SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt
  • SDIO_INT_FLAG_TFH: SDIO TFH interrupt
  • SDIO_INT_FLAG_RFH: SDIO RFH interrupt
  • SDIO_INT_FLAG_TFF: SDIO TFF interrupt
  • SDIO_INT_FLAG_RFF: SDIO RFF interrupt
  • SDIO_INT_FLAG_TFE: SDIO TFE interrupt
  • SDIO_INT_FLAG_RFE: SDIO RFE interrupt
  • SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt
  • SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt
  • SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt
  • SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt
[out] none
Return values
FlagStatus SET or RESET

Definition at line 562 of file gd32f10x_sdio.c.

563 {
564 uint32_t state = 0U;
565 state = SDIO_STAT;
566 if(state & int_flag){
567 state = SDIO_INTEN;
568 /* check whether the corresponding bit in SDIO_INTEN is set or not */
569 if(state & int_flag){
570 return SET;
571 }
572 }
573 return RESET;
574 }
SDIO_STAT
#define SDIO_STAT
Definition: gd32f10x_sdio.h:35
SDIO_INTEN
#define SDIO_INTEN
Definition: gd32f10x_sdio.h:37
void sdio_operation_disable ( void )

disable the SD I/O mode specific operation(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 678 of file gd32f10x_sdio.c.

679 {
680 SDIO_DATACTL &= ~SDIO_DATACTL_IOEN;
681 }
SDIO_DATACTL_IOEN
#define SDIO_DATACTL_IOEN
Definition: gd32f10x_sdio.h:83
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
void sdio_operation_enable ( void )

enable the SD I/O mode specific operation(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 667 of file gd32f10x_sdio.c.

668 {
669 SDIO_DATACTL |= SDIO_DATACTL_IOEN;
670 }
SDIO_DATACTL_IOEN
#define SDIO_DATACTL_IOEN
Definition: gd32f10x_sdio.h:83
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
uint32_t sdio_power_state_get ( void )

get the SDIO power state

Parameters
[in] | none
[out] | none
Return values
SDIO power state
  • SDIO_POWER_ON: SDIO power on
  • SDIO_POWER_OFF: SDIO power off

Definition at line 122 of file gd32f10x_sdio.c.

123 {
124 return SDIO_PWRCTL;
125 }
SDIO_PWRCTL
#define SDIO_PWRCTL
Definition: gd32f10x_sdio.h:22
void sdio_power_state_set ( uint32_t power_state )

set the SDIO power state

Parameters
[in] power_state SDIO power state
  • SDIO_POWER_ON: SDIO power on
  • SDIO_POWER_OFF: SDIO power off
[out] none
Return values
none

Definition at line 109 of file gd32f10x_sdio.c.

110 {
111 SDIO_PWRCTL = power_state;
112 }
SDIO_PWRCTL
#define SDIO_PWRCTL
Definition: gd32f10x_sdio.h:22
void sdio_readwait_disable ( void )

disable the read wait mode(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 617 of file gd32f10x_sdio.c.

618 {
619 SDIO_DATACTL &= ~SDIO_DATACTL_RWEN;
620 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_RWEN
#define SDIO_DATACTL_RWEN
Definition: gd32f10x_sdio.h:80
void sdio_readwait_enable ( void )

enable the read wait mode(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 606 of file gd32f10x_sdio.c.

607 {
608 SDIO_DATACTL |= SDIO_DATACTL_RWEN;
609 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_RWEN
#define SDIO_DATACTL_RWEN
Definition: gd32f10x_sdio.h:80
void sdio_readwait_type_set ( uint32_t readwait_type )

set the read wait type(SD I/O only)

Parameters
[in] readwait_type SD I/O read wait type
  • SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK
  • SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2]
[out] none
Return values
none

Definition at line 652 of file gd32f10x_sdio.c.

653 {
654 if(SDIO_READWAITTYPE_CLK == readwait_type){
655 SDIO_DATACTL |= SDIO_DATACTL_RWTYPE;
656 }else{
657 SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE;
658 }
659 }
SDIO_READWAITTYPE_CLK
#define SDIO_READWAITTYPE_CLK
Definition: gd32f10x_sdio.h:301
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_RWTYPE
#define SDIO_DATACTL_RWTYPE
Definition: gd32f10x_sdio.h:82
uint32_t sdio_response_get ( uint32_t responsex )

get the response for the last received command

Parameters
[in] responsex SDIO response
  • SDIO_RESPONSE0: card response[31:0]/card response[127:96]
  • SDIO_RESPONSE1: card response[95:64]
  • SDIO_RESPONSE2: card response[63:32]
  • SDIO_RESPONSE3: card response[31:1], plus bit 0
[out] none
Return values
response for the last received command

Definition at line 233 of file gd32f10x_sdio.c.

234 {
235 uint32_t resp_content = 0U;
236 switch(responsex){
237 case SDIO_RESPONSE0:
238 resp_content = SDIO_RESP0;
239 break;
240 case SDIO_RESPONSE1:
241 resp_content = SDIO_RESP1;
242 break;
243 case SDIO_RESPONSE2:
244 resp_content = SDIO_RESP2;
245 break;
246 case SDIO_RESPONSE3:
247 resp_content = SDIO_RESP3;
248 break;
249 default:
250 break;
251 }
252 return resp_content;
253 }
SDIO_RESP0
#define SDIO_RESP0
Definition: gd32f10x_sdio.h:27
SDIO_RESPONSE1
#define SDIO_RESPONSE1
Definition: gd32f10x_sdio.h:269
SDIO_RESP1
#define SDIO_RESP1
Definition: gd32f10x_sdio.h:28
SDIO_RESPONSE2
#define SDIO_RESPONSE2
Definition: gd32f10x_sdio.h:270
SDIO_RESPONSE3
#define SDIO_RESPONSE3
Definition: gd32f10x_sdio.h:271
SDIO_RESP2
#define SDIO_RESP2
Definition: gd32f10x_sdio.h:29
SDIO_RESP3
#define SDIO_RESP3
Definition: gd32f10x_sdio.h:30
SDIO_RESPONSE0
#define SDIO_RESPONSE0
Definition: gd32f10x_sdio.h:268
void sdio_stop_readwait_disable ( void )

disable the function that stop the read wait process(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 639 of file gd32f10x_sdio.c.

640 {
641 SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP;
642 }
SDIO_DATACTL_RWSTOP
#define SDIO_DATACTL_RWSTOP
Definition: gd32f10x_sdio.h:81
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
void sdio_stop_readwait_enable ( void )

enable the function that stop the read wait process(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 628 of file gd32f10x_sdio.c.

629 {
630 SDIO_DATACTL |= SDIO_DATACTL_RWSTOP;
631 }
SDIO_DATACTL_RWSTOP
#define SDIO_DATACTL_RWSTOP
Definition: gd32f10x_sdio.h:81
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
void sdio_suspend_disable ( void )

disable the SD I/O suspend operation(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 700 of file gd32f10x_sdio.c.

701 {
702 SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND;
703 }
SDIO_CMDCTL_SUSPEND
#define SDIO_CMDCTL_SUSPEND
Definition: gd32f10x_sdio.h:63
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_suspend_enable ( void )

enable the SD I/O suspend operation(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 689 of file gd32f10x_sdio.c.

690 {
691 SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND;
692 }
SDIO_CMDCTL_SUSPEND
#define SDIO_CMDCTL_SUSPEND
Definition: gd32f10x_sdio.h:63
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_wait_type_set ( uint32_t wait_type )

set the command state machine wait type

Parameters
[in] wait_type wait type
  • SDIO_WAITTYPE_NO: not wait interrupt
  • SDIO_WAITTYPE_INTERRUPT: wait interrupt
  • SDIO_WAITTYPE_DATAEND: wait the end of data transfer
[out] none
Return values
none

Definition at line 182 of file gd32f10x_sdio.c.

183 {
184 /* reset INTWAIT and WAITDEND */
185 SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND);
186 /* set the wait type according to wait_type */
187 SDIO_CMDCTL |= wait_type;
188 }
SDIO_CMDCTL_INTWAIT
#define SDIO_CMDCTL_INTWAIT
Definition: gd32f10x_sdio.h:60
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
SDIO_CMDCTL_WAITDEND
#define SDIO_CMDCTL_WAITDEND
Definition: gd32f10x_sdio.h:61
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Data Structures | Macros | Functions
gd32f10x_spi.h File Reference

definitions for the SPI More...

#include "gd32f10x.h"

Go to the source code of this file.

Data Structures

struct spi_parameter_struct

Macros

#define | SPI0 (SPI_BASE + 0x0000F800U)
#define | SPI1 SPI_BASE
#define | SPI2 (SPI_BASE + 0x00000400U)
#define | SPI_CTL0(spix) REG32((spix) + 0x00U)
#define | SPI_CTL1(spix) REG32((spix) + 0x04U)
#define | SPI_STAT(spix) REG32((spix) + 0x08U)
#define | SPI_DATA(spix) REG32((spix) + 0x0CU)
#define | SPI_CRCPOLY(spix) REG32((spix) + 0x10U)
#define | SPI_RCRC(spix) REG32((spix) + 0x14U)
#define | SPI_TCRC(spix) REG32((spix) + 0x18U)
#define | SPI_I2SCTL(spix) REG32((spix) + 0x1CU)
#define | SPI_I2SPSC(spix) REG32((spix) + 0x20U)
#define | SPI_CTL0_CKPH BIT(0)
#define | SPI_CTL0_CKPL BIT(1)
#define | SPI_CTL0_MSTMOD BIT(2)
#define | SPI_CTL0_PSC BITS(3,5)
#define | SPI_CTL0_SPIEN BIT(6)
#define | SPI_CTL0_LF BIT(7)
#define | SPI_CTL0_SWNSS BIT(8)
#define | SPI_CTL0_SWNSSEN BIT(9)
#define | SPI_CTL0_RO BIT(10)
#define | SPI_CTL0_FF16 BIT(11)
#define | SPI_CTL0_CRCNT BIT(12)
#define | SPI_CTL0_CRCEN BIT(13)
#define | SPI_CTL0_BDOEN BIT(14)
#define | SPI_CTL0_BDEN BIT(15)
#define | SPI_CTL1_DMAREN BIT(0)
#define | SPI_CTL1_DMATEN BIT(1)
#define | SPI_CTL1_NSSDRV BIT(2)
#define | SPI_CTL1_ERRIE BIT(5)
#define | SPI_CTL1_RBNEIE BIT(6)
#define | SPI_CTL1_TBEIE BIT(7)
#define | SPI_STAT_RBNE BIT(0)
#define | SPI_STAT_TBE BIT(1)
#define | SPI_STAT_I2SCH BIT(2)
#define | SPI_STAT_TXURERR BIT(3)
#define | SPI_STAT_CRCERR BIT(4)
#define | SPI_STAT_CONFERR BIT(5)
#define | SPI_STAT_RXORERR BIT(6)
#define | SPI_STAT_TRANS BIT(7)
#define | SPI_DATA_DATA BITS(0,15)
#define | SPI_CRCPOLY_CPR BITS(0,15)
#define | SPI_RCRC_RCR BITS(0,15)
#define | SPI_TCRC_TCR BITS(0,15)
#define | SPI_I2SCTL_CHLEN BIT(0)
#define | SPI_I2SCTL_DTLEN BITS(1,2)
#define | SPI_I2SCTL_CKPL BIT(3)
#define | SPI_I2SCTL_I2SSTD BITS(4,5)
#define | SPI_I2SCTL_PCMSMOD BIT(7)
#define | SPI_I2SCTL_I2SOPMOD BITS(8,9)
#define | SPI_I2SCTL_I2SEN BIT(10)
#define | SPI_I2SCTL_I2SSEL BIT(11)
#define | SPI_I2SPSC_DIV BITS(0,7)
#define | SPI_I2SPSC_OF BIT(8)
#define | SPI_I2SPSC_MCKOEN BIT(9)
#define | SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)
#define | SPI_SLAVE ((uint32_t)0x00000000U)
#define | SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN
#define | SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN
#define | SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U)
#define | SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO
#define | SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN
#define | SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)
#define | SPI_FRAMESIZE_16BIT SPI_CTL0_FF16
#define | SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U)
#define | SPI_NSS_SOFT SPI_CTL0_SWNSSEN
#define | SPI_NSS_HARD ((uint32_t)0x00000000U)
#define | SPI_ENDIAN_MSB ((uint32_t)0x00000000U)
#define | SPI_ENDIAN_LSB SPI_CTL0_LF
#define | SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U)
#define | SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL
#define | SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH
#define | SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH)
#define | CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
#define | SPI_PSC_2 CTL0_PSC(0)
#define | SPI_PSC_4 CTL0_PSC(1)
#define | SPI_PSC_8 CTL0_PSC(2)
#define | SPI_PSC_16 CTL0_PSC(3)
#define | SPI_PSC_32 CTL0_PSC(4)
#define | SPI_PSC_64 CTL0_PSC(5)
#define | SPI_PSC_128 CTL0_PSC(6)
#define | SPI_PSC_256 CTL0_PSC(7)
#define | I2S_AUDIOSAMPLE_8K ((uint32_t)8000U)
#define | I2S_AUDIOSAMPLE_11K ((uint32_t)11025U)
#define | I2S_AUDIOSAMPLE_16K ((uint32_t)16000U)
#define | I2S_AUDIOSAMPLE_22K ((uint32_t)22050U)
#define | I2S_AUDIOSAMPLE_32K ((uint32_t)32000U)
#define | I2S_AUDIOSAMPLE_44K ((uint32_t)44100U)
#define | I2S_AUDIOSAMPLE_48K ((uint32_t)48000U)
#define | I2S_AUDIOSAMPLE_96K ((uint32_t)96000U)
#define | I2S_AUDIOSAMPLE_192K ((uint32_t)192000U)
#define | I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
#define | I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0)
#define | I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN)
#define | I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN)
#define | I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN)
#define | I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U)
#define | I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN
#define | I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
#define | I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0)
#define | I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1)
#define | I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2)
#define | I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3)
#define | I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define | I2S_STD_PHILLIPS I2SCTL_I2SSTD(0)
#define | I2S_STD_MSB I2SCTL_I2SSTD(1)
#define | I2S_STD_LSB I2SCTL_I2SSTD(2)
#define | I2S_STD_PCMSHORT I2SCTL_I2SSTD(3)
#define | I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD)
#define | I2S_CKPL_LOW ((uint32_t)0x00000000U)
#define | I2S_CKPL_HIGH SPI_I2SCTL_CKPL
#define | SPI_DMA_TRANSMIT ((uint8_t)0x00U)
#define | SPI_DMA_RECEIVE ((uint8_t)0x01U)
#define | SPI_CRC_TX ((uint8_t)0x00U)
#define | SPI_CRC_RX ((uint8_t)0x01U)
#define | SPI_I2S_INT_TBE ((uint8_t)0x00U)
#define | SPI_I2S_INT_RBNE ((uint8_t)0x01U)
#define | SPI_I2S_INT_ERR ((uint8_t)0x02U)
#define | SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U)
#define | SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U)
#define | SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U)
#define | SPI_INT_FLAG_CONFERR ((uint8_t)0x03U)
#define | SPI_INT_FLAG_CRCERR ((uint8_t)0x04U)
#define | I2S_INT_FLAG_TXURERR ((uint8_t)0x05U)
#define | SPI_FLAG_RBNE SPI_STAT_RBNE
#define | SPI_FLAG_TBE SPI_STAT_TBE
#define | SPI_FLAG_CRCERR SPI_STAT_CRCERR
#define | SPI_FLAG_CONFERR SPI_STAT_CONFERR
#define | SPI_FLAG_RXORERR SPI_STAT_RXORERR
#define | SPI_FLAG_TRANS SPI_STAT_TRANS
#define | I2S_FLAG_RBNE SPI_STAT_RBNE
#define | I2S_FLAG_TBE SPI_STAT_TBE
#define | I2S_FLAG_CH SPI_STAT_I2SCH
#define | I2S_FLAG_TXURERR SPI_STAT_TXURERR
#define | I2S_FLAG_RXORERR SPI_STAT_RXORERR
#define | I2S_FLAG_TRANS SPI_STAT_TRANS

Functions

void | spi_i2s_deinit (uint32_t spi_periph)
reset SPI and I2S More...
void | spi_init (uint32_t spi_periph, spi_parameter_struct *spi_struct)
initialize SPI parameter More...
void | spi_enable (uint32_t spi_periph)
enable SPI More...
void | spi_disable (uint32_t spi_periph)
disable SPI More...
void | i2s_init (uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
initialize I2S parameter More...
void | i2s_psc_config (uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
configure I2S prescaler More...
void | i2s_enable (uint32_t spi_periph)
enable I2S More...
void | i2s_disable (uint32_t spi_periph)
disable I2S More...
void | spi_nss_output_enable (uint32_t spi_periph)
enable SPI NSS output More...
void | spi_nss_output_disable (uint32_t spi_periph)
disable SPI NSS output More...
void | spi_nss_internal_high (uint32_t spi_periph)
SPI NSS pin high level in software mode. More...
void | spi_nss_internal_low (uint32_t spi_periph)
SPI NSS pin low level in software mode. More...
void | spi_dma_enable (uint32_t spi_periph, uint8_t dma)
enable SPI DMA send or receive More...
void | spi_dma_disable (uint32_t spi_periph, uint8_t dma)
disable SPI DMA send or receive More...
void | spi_i2s_data_frame_format_config (uint32_t spi_periph, uint16_t frame_format)
configure SPI/I2S data frame format More...
void | spi_i2s_data_transmit (uint32_t spi_periph, uint16_t data)
SPI transmit data. More...
uint16_t | spi_i2s_data_receive (uint32_t spi_periph)
SPI receive data. More...
void | spi_bidirectional_transfer_config (uint32_t spi_periph, uint32_t transfer_direction)
configure SPI bidirectional transfer direction More...
void | spi_i2s_interrupt_enable (uint32_t spi_periph, uint8_t interrupt)
enable SPI and I2S interrupt More...
void | spi_i2s_interrupt_disable (uint32_t spi_periph, uint8_t interrupt)
disable SPI and I2S interrupt More...
FlagStatus | spi_i2s_interrupt_flag_get (uint32_t spi_periph, uint8_t interrupt)
get SPI and I2S interrupt flag status More...
FlagStatus | spi_i2s_flag_get (uint32_t spi_periph, uint32_t flag)
get SPI and I2S flag status More...
void | spi_crc_error_clear (uint32_t spi_periph)
clear SPI CRC error flag status More...
void | spi_crc_on (uint32_t spi_periph)
turn on CRC function More...
void | spi_crc_off (uint32_t spi_periph)
turn off CRC function More...
void | spi_crc_polynomial_set (uint32_t spi_periph, uint16_t crc_poly)
set CRC polynomial More...
uint16_t | spi_crc_polynomial_get (uint32_t spi_periph)
get SPI CRC polynomial More...
void | spi_crc_next (uint32_t spi_periph)
SPI next data is CRC value. More...
uint16_t | spi_crc_get (uint32_t spi_periph, uint8_t crc)
get SPI CRC send value or receive value More...

Detailed Description

definitions for the SPI

Definition in file gd32f10x_spi.h.

Macro Definition Documentation

#define CTL0_PSC ( regval ) (BITS(3,5) & ((uint32_t)(regval) << 3))

Definition at line 142 of file gd32f10x_spi.h.

#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U)

I2S audio sample rate is 11KHz

Definition at line 154 of file gd32f10x_spi.h.

#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U)

I2S audio sample rate is 16KHz

Definition at line 155 of file gd32f10x_spi.h.

#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U)

I2S audio sample rate is 192KHz

Definition at line 161 of file gd32f10x_spi.h.

#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U)

I2S audio sample rate is 22KHz

Definition at line 156 of file gd32f10x_spi.h.

#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U)

I2S audio sample rate is 32KHz

Definition at line 157 of file gd32f10x_spi.h.

#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U)

I2S audio sample rate is 44KHz

Definition at line 158 of file gd32f10x_spi.h.

#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U)

I2S audio sample rate is 48KHz

Definition at line 159 of file gd32f10x_spi.h.

#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U)

I2S audio sample rate is 8KHz

Definition at line 153 of file gd32f10x_spi.h.

#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U)

I2S audio sample rate is 96KHz

Definition at line 160 of file gd32f10x_spi.h.

#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL

I2S clock polarity high level

Definition at line 191 of file gd32f10x_spi.h.

#define I2S_CKPL_LOW ((uint32_t)0x00000000U)

I2S clock polarity low level

Definition at line 190 of file gd32f10x_spi.h.

#define I2S_FLAG_CH SPI_STAT_I2SCH

channel side flag

Definition at line 223 of file gd32f10x_spi.h.

#define I2S_FLAG_RBNE SPI_STAT_RBNE

receive buffer not empty flag

Definition at line 221 of file gd32f10x_spi.h.

#define I2S_FLAG_RXORERR SPI_STAT_RXORERR

overrun error flag

Definition at line 225 of file gd32f10x_spi.h.

#define I2S_FLAG_TBE SPI_STAT_TBE

transmit buffer empty flag

Definition at line 222 of file gd32f10x_spi.h.

#define I2S_FLAG_TRANS SPI_STAT_TRANS

transmit on-going flag

Definition at line 226 of file gd32f10x_spi.h.

#define I2S_FLAG_TXURERR SPI_STAT_TXURERR

underrun error flag

Definition at line 224 of file gd32f10x_spi.h.

#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0)

I2S data length is 16 bit and channel length is 16 bit

Definition at line 165 of file gd32f10x_spi.h.

#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN)

I2S data length is 16 bit and channel length is 32 bit

Definition at line 166 of file gd32f10x_spi.h.

#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN)

I2S data length is 24 bit and channel length is 32 bit

Definition at line 167 of file gd32f10x_spi.h.

#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN)

I2S data length is 32 bit and channel length is 32 bit

Definition at line 168 of file gd32f10x_spi.h.

#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U)

underrun error interrupt

Definition at line 212 of file gd32f10x_spi.h.

#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U)

I2S master clock output disable

Definition at line 171 of file gd32f10x_spi.h.

#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN

I2S master clock output enable

Definition at line 172 of file gd32f10x_spi.h.

#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3)

I2S master receive mode

Definition at line 179 of file gd32f10x_spi.h.

#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2)

I2S master transmit mode

Definition at line 178 of file gd32f10x_spi.h.

#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1)

I2S slave receive mode

Definition at line 177 of file gd32f10x_spi.h.

#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0)

I2S slave transmit mode

Definition at line 176 of file gd32f10x_spi.h.

#define I2S_STD_LSB I2SCTL_I2SSTD(2)

I2S LSB standard

Definition at line 185 of file gd32f10x_spi.h.

#define I2S_STD_MSB I2SCTL_I2SSTD(1)

I2S MSB standard

Definition at line 184 of file gd32f10x_spi.h.

#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD)

I2S PCM long standard

Definition at line 187 of file gd32f10x_spi.h.

#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3)

I2S PCM short standard

Definition at line 186 of file gd32f10x_spi.h.

#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0)

I2S phillips standard

Definition at line 183 of file gd32f10x_spi.h.

#define I2SCTL_DTLEN ( regval ) (BITS(1,2) & ((uint32_t)(regval) << 1))

Definition at line 164 of file gd32f10x_spi.h.

#define I2SCTL_I2SOPMOD ( regval ) (BITS(8,9) & ((uint32_t)(regval) << 8))

Definition at line 175 of file gd32f10x_spi.h.

#define I2SCTL_I2SSTD ( regval ) (BITS(4,5) & ((uint32_t)(regval) << 4))

Definition at line 182 of file gd32f10x_spi.h.

#define SPI0 (SPI_BASE + 0x0000F800U)

Definition at line 19 of file gd32f10x_spi.h.

#define SPI1 SPI_BASE

Definition at line 20 of file gd32f10x_spi.h.

#define SPI2 (SPI_BASE + 0x00000400U)

Definition at line 21 of file gd32f10x_spi.h.

#define SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN

SPI work in receive-only mode

Definition at line 115 of file gd32f10x_spi.h.

#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN

SPI work in transmit-only mode

Definition at line 114 of file gd32f10x_spi.h.

#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL

SPI clock polarity is high level and phase is first edge

Definition at line 137 of file gd32f10x_spi.h.

#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH)

SPI clock polarity is high level and phase is second edge

Definition at line 139 of file gd32f10x_spi.h.

#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U)

SPI clock polarity is low level and phase is first edge

Definition at line 136 of file gd32f10x_spi.h.

#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH

SPI clock polarity is low level and phase is second edge

Definition at line 138 of file gd32f10x_spi.h.

#define SPI_CRC_RX ((uint8_t)0x01U)

SPI receive CRC value

Definition at line 199 of file gd32f10x_spi.h.

#define SPI_CRC_TX ((uint8_t)0x00U)

SPI transmit CRC value

Definition at line 198 of file gd32f10x_spi.h.

#define SPI_CRCPOLY ( spix ) REG32((spix) + 0x10U)

SPI CRC polynomial register

Definition at line 28 of file gd32f10x_spi.h.

#define SPI_CRCPOLY_CPR BITS(0,15)

CRC polynomial register

Definition at line 73 of file gd32f10x_spi.h.

#define SPI_CTL0 ( spix ) REG32((spix) + 0x00U)

SPI control register 0

Definition at line 24 of file gd32f10x_spi.h.

#define SPI_CTL0_BDEN BIT(15)

bidirectional enable

Definition at line 49 of file gd32f10x_spi.h.

#define SPI_CTL0_BDOEN BIT(14)

bidirectional transmit output enable

Definition at line 48 of file gd32f10x_spi.h.

#define SPI_CTL0_CKPH BIT(0)

clock phase selection

Definition at line 36 of file gd32f10x_spi.h.

#define SPI_CTL0_CKPL BIT(1)

clock polarity selection

Definition at line 37 of file gd32f10x_spi.h.

#define SPI_CTL0_CRCEN BIT(13)

CRC calculation enable

Definition at line 47 of file gd32f10x_spi.h.

#define SPI_CTL0_CRCNT BIT(12)

CRC next transfer

Definition at line 46 of file gd32f10x_spi.h.

#define SPI_CTL0_FF16 BIT(11)

data frame size

Definition at line 45 of file gd32f10x_spi.h.

#define SPI_CTL0_LF BIT(7)

LSB first mode

Definition at line 41 of file gd32f10x_spi.h.

#define SPI_CTL0_MSTMOD BIT(2)

master mode enable

Definition at line 38 of file gd32f10x_spi.h.

#define SPI_CTL0_PSC BITS(3,5)

master clock prescaler selection

Definition at line 39 of file gd32f10x_spi.h.

#define SPI_CTL0_RO BIT(10)

receive only

Definition at line 44 of file gd32f10x_spi.h.

#define SPI_CTL0_SPIEN BIT(6)

SPI enable

Definition at line 40 of file gd32f10x_spi.h.

#define SPI_CTL0_SWNSS BIT(8)

NSS pin selection in NSS software mode

Definition at line 42 of file gd32f10x_spi.h.

#define SPI_CTL0_SWNSSEN BIT(9)

NSS software mode selection

Definition at line 43 of file gd32f10x_spi.h.

#define SPI_CTL1 ( spix ) REG32((spix) + 0x04U)

SPI control register 1

Definition at line 25 of file gd32f10x_spi.h.

#define SPI_CTL1_DMAREN BIT(0)

receive buffer dma enable

Definition at line 52 of file gd32f10x_spi.h.

#define SPI_CTL1_DMATEN BIT(1)

transmit buffer dma enable

Definition at line 53 of file gd32f10x_spi.h.

#define SPI_CTL1_ERRIE BIT(5)

errors interrupt enable

Definition at line 55 of file gd32f10x_spi.h.

#define SPI_CTL1_NSSDRV BIT(2)

drive NSS output

Definition at line 54 of file gd32f10x_spi.h.

#define SPI_CTL1_RBNEIE BIT(6)

receive buffer not empty interrupt enable

Definition at line 56 of file gd32f10x_spi.h.

#define SPI_CTL1_TBEIE BIT(7)

transmit buffer empty interrupt enable

Definition at line 57 of file gd32f10x_spi.h.

#define SPI_DATA ( spix ) REG32((spix) + 0x0CU)

SPI data register

Definition at line 27 of file gd32f10x_spi.h.

#define SPI_DATA_DATA BITS(0,15)

data transfer register

Definition at line 70 of file gd32f10x_spi.h.

#define SPI_DMA_RECEIVE ((uint8_t)0x01U)

SPI receive data use DMA

Definition at line 195 of file gd32f10x_spi.h.

#define SPI_DMA_TRANSMIT ((uint8_t)0x00U)

SPI transmit data use DMA

Definition at line 194 of file gd32f10x_spi.h.

#define SPI_ENDIAN_LSB SPI_CTL0_LF

SPI transmit way is little endian: transmit LSB first

Definition at line 133 of file gd32f10x_spi.h.

#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U)

SPI transmit way is big endian: transmit MSB first

Definition at line 132 of file gd32f10x_spi.h.

#define SPI_FLAG_CONFERR SPI_STAT_CONFERR

mode config error flag

Definition at line 218 of file gd32f10x_spi.h.

#define SPI_FLAG_CRCERR SPI_STAT_CRCERR

CRC error flag

Definition at line 217 of file gd32f10x_spi.h.

#define SPI_FLAG_RBNE SPI_STAT_RBNE

receive buffer not empty flag

Definition at line 215 of file gd32f10x_spi.h.

#define SPI_FLAG_RXORERR SPI_STAT_RXORERR

receive overrun error flag

Definition at line 219 of file gd32f10x_spi.h.

#define SPI_FLAG_TBE SPI_STAT_TBE

transmit buffer empty flag

Definition at line 216 of file gd32f10x_spi.h.

#define SPI_FLAG_TRANS SPI_STAT_TRANS

transmit on-going flag

Definition at line 220 of file gd32f10x_spi.h.

#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16

SPI frame size is 16 bits

Definition at line 124 of file gd32f10x_spi.h.

#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U)

SPI frame size is 8 bits

Definition at line 125 of file gd32f10x_spi.h.

#define SPI_I2S_INT_ERR ((uint8_t)0x02U)

error interrupt

Definition at line 204 of file gd32f10x_spi.h.

#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U)

receive buffer not empty interrupt

Definition at line 208 of file gd32f10x_spi.h.

#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U)

overrun interrupt

Definition at line 209 of file gd32f10x_spi.h.

#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U)

transmit buffer empty interrupt

Definition at line 207 of file gd32f10x_spi.h.

#define SPI_I2S_INT_RBNE ((uint8_t)0x01U)

receive buffer not empty interrupt

Definition at line 203 of file gd32f10x_spi.h.

#define SPI_I2S_INT_TBE ((uint8_t)0x00U)

transmit buffer empty interrupt

Definition at line 202 of file gd32f10x_spi.h.

#define SPI_I2SCTL ( spix ) REG32((spix) + 0x1CU)

SPI I2S control register

Definition at line 31 of file gd32f10x_spi.h.

#define SPI_I2SCTL_CHLEN BIT(0)

channel length

Definition at line 82 of file gd32f10x_spi.h.

#define SPI_I2SCTL_CKPL BIT(3)

idle state clock polarity

Definition at line 84 of file gd32f10x_spi.h.

#define SPI_I2SCTL_DTLEN BITS(1,2)

data length

Definition at line 83 of file gd32f10x_spi.h.

#define SPI_I2SCTL_I2SEN BIT(10)

I2S enable

Definition at line 88 of file gd32f10x_spi.h.

#define SPI_I2SCTL_I2SOPMOD BITS(8,9)

I2S operation mode

Definition at line 87 of file gd32f10x_spi.h.

#define SPI_I2SCTL_I2SSEL BIT(11)

I2S mode selection

Definition at line 89 of file gd32f10x_spi.h.

#define SPI_I2SCTL_I2SSTD BITS(4,5)

I2S standard selection

Definition at line 85 of file gd32f10x_spi.h.

#define SPI_I2SCTL_PCMSMOD BIT(7)

PCM frame synchronization mode

Definition at line 86 of file gd32f10x_spi.h.

#define SPI_I2SPSC ( spix ) REG32((spix) + 0x20U)

SPI I2S clock prescaler register

Definition at line 32 of file gd32f10x_spi.h.

#define SPI_I2SPSC_DIV BITS(0,7)

dividing factor for the prescaler

Definition at line 92 of file gd32f10x_spi.h.

#define SPI_I2SPSC_MCKOEN BIT(9)

I2S MCK output enable

Definition at line 94 of file gd32f10x_spi.h.

#define SPI_I2SPSC_OF BIT(8)

odd factor for the prescaler

Definition at line 93 of file gd32f10x_spi.h.

#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U)

config error interrupt

Definition at line 210 of file gd32f10x_spi.h.

#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U)

CRC error interrupt

Definition at line 211 of file gd32f10x_spi.h.

#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)

SPI as master

Definition at line 110 of file gd32f10x_spi.h.

#define SPI_NSS_HARD ((uint32_t)0x00000000U)

SPI NSS control by hardware

Definition at line 129 of file gd32f10x_spi.h.

#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN

SPI NSS control by software

Definition at line 128 of file gd32f10x_spi.h.

#define SPI_PSC_128 CTL0_PSC(6)

SPI clock prescale factor is 128

Definition at line 149 of file gd32f10x_spi.h.

#define SPI_PSC_16 CTL0_PSC(3)

SPI clock prescale factor is 16

Definition at line 146 of file gd32f10x_spi.h.

#define SPI_PSC_2 CTL0_PSC(0)

SPI clock prescale factor is 2

Definition at line 143 of file gd32f10x_spi.h.

#define SPI_PSC_256 CTL0_PSC(7)

SPI clock prescale factor is 256

Definition at line 150 of file gd32f10x_spi.h.

#define SPI_PSC_32 CTL0_PSC(4)

SPI clock prescale factor is 32

Definition at line 147 of file gd32f10x_spi.h.

#define SPI_PSC_4 CTL0_PSC(1)

SPI clock prescale factor is 4

Definition at line 144 of file gd32f10x_spi.h.

#define SPI_PSC_64 CTL0_PSC(5)

SPI clock prescale factor is 64

Definition at line 148 of file gd32f10x_spi.h.

#define SPI_PSC_8 CTL0_PSC(2)

SPI clock prescale factor is 8

Definition at line 145 of file gd32f10x_spi.h.

#define SPI_RCRC ( spix ) REG32((spix) + 0x14U)

SPI receive CRC register

Definition at line 29 of file gd32f10x_spi.h.

#define SPI_RCRC_RCR BITS(0,15)

RX CRC register

Definition at line 76 of file gd32f10x_spi.h.

#define SPI_SLAVE ((uint32_t)0x00000000U)

SPI as slave

Definition at line 111 of file gd32f10x_spi.h.

#define SPI_STAT ( spix ) REG32((spix) + 0x08U)

SPI status register

Definition at line 26 of file gd32f10x_spi.h.

#define SPI_STAT_CONFERR BIT(5)

SPI configuration error bit

Definition at line 65 of file gd32f10x_spi.h.

#define SPI_STAT_CRCERR BIT(4)

SPI CRC error bit

Definition at line 64 of file gd32f10x_spi.h.

#define SPI_STAT_I2SCH BIT(2)

I2S channel side

Definition at line 62 of file gd32f10x_spi.h.

#define SPI_STAT_RBNE BIT(0)

receive buffer not empty

Definition at line 60 of file gd32f10x_spi.h.

#define SPI_STAT_RXORERR BIT(6)

SPI reception overrun error bit

Definition at line 66 of file gd32f10x_spi.h.

#define SPI_STAT_TBE BIT(1)

transmit buffer empty

Definition at line 61 of file gd32f10x_spi.h.

#define SPI_STAT_TRANS BIT(7)

transmitting on-going bit

Definition at line 67 of file gd32f10x_spi.h.

#define SPI_STAT_TXURERR BIT(3)

I2S transmission underrun error bit

Definition at line 63 of file gd32f10x_spi.h.

#define SPI_TCRC ( spix ) REG32((spix) + 0x18U)

SPI transmit CRC register

Definition at line 30 of file gd32f10x_spi.h.

#define SPI_TCRC_TCR BITS(0,15)

RX CRC register

Definition at line 79 of file gd32f10x_spi.h.

#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN

bidirectional receive data

Definition at line 120 of file gd32f10x_spi.h.

#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)

bidirectional transmit data

Definition at line 121 of file gd32f10x_spi.h.

#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U)

SPI receive and send data at fullduplex communication

Definition at line 118 of file gd32f10x_spi.h.

#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO

SPI only receive data

Definition at line 119 of file gd32f10x_spi.h.

Function Documentation

void i2s_disable ( uint32_t spi_periph )

disable I2S

Parameters
[in] | spi_periph | SPIx(x=1,2)
[out] | none
Return values
none

Definition at line 276 of file gd32f10x_spi.c.

277 {
278 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
279 }
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
SPI_I2SCTL_I2SEN
#define SPI_I2SCTL_I2SEN
Definition: gd32f10x_spi.h:88
void i2s_enable ( uint32_t spi_periph )

enable I2S

Parameters
[in] | spi_periph | SPIx(x=1,2)
[out] | none
Return values
none

Definition at line 265 of file gd32f10x_spi.c.

266 {
267 SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
268 }
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
SPI_I2SCTL_I2SEN
#define SPI_I2SCTL_I2SEN
Definition: gd32f10x_spi.h:88
void i2s_init | ( | uint32_t | spi_periph,
 |  | uint32_t | mode,
 |  | uint32_t | standard,
 |  | uint32_t | ckpl
 | ) |  |

initialize I2S parameter

Parameters
[in] | spi_periph | SPIx(x=1,2)
[in] mode I2S operation mode
  • I2S_MODE_SLAVETX: I2S slave transmit mode
  • I2S_MODE_SLAVERX: I2S slave receive mode
  • I2S_MODE_MASTERTX: I2S master transmit mode
  • I2S_MODE_MASTERRX: I2S master receive mode
[in] standard I2S standard
  • I2S_STD_PHILLIPS: I2S phillips standard
  • I2S_STD_MSB: I2S MSB standard
  • I2S_STD_LSB: I2S LSB standard
  • I2S_STD_PCMSHORT: I2S PCM short standard
  • I2S_STD_PCMLONG: I2S PCM long standard
[in] ckpl I2S idle state clock polarity
  • I2S_CKPL_LOW: I2S clock polarity low level
  • I2S_CKPL_HIGH: I2S clock polarity high level
[out] | none
Return values
none

Definition at line 138 of file gd32f10x_spi.c.

139 {
140 uint32_t reg = 0U;
141 reg = SPI_I2SCTL(spi_periph);
142 reg &= I2S_INIT_MASK;
143
144 /* enable I2S mode */
145 reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
146 /* select I2S mode */
147 reg |= (uint32_t)mode;
148 /* select I2S standard */
149 reg |= (uint32_t)standard;
150 /* select I2S polarity */
151 reg |= (uint32_t)ckpl;
152
153 /* write to SPI_I2SCTL register */
154 SPI_I2SCTL(spi_periph) = (uint32_t)reg;
155 }
SPI_I2SCTL_I2SSEL
#define SPI_I2SCTL_I2SSEL
Definition: gd32f10x_spi.h:89
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
I2S_INIT_MASK
#define I2S_INIT_MASK
Definition: gd32f10x_spi.c:16
void i2s_psc_config | ( | uint32_t | spi_periph,
 |  | uint32_t | audiosample,
 |  | uint32_t | frameformat,
 |  | uint32_t | mckout
 | ) |  |

configure I2S prescaler

Parameters
[in] | spi_periph | SPIx(x=1,2)
[in] audiosample I2S audio sample rate
  • I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
  • I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
  • I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
  • I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
  • I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
  • I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
  • I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
  • I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
  • I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
[in] frameformat I2S data length and channel length
  • I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
  • I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
  • I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
  • I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
[in] mckout I2S master clock output
  • I2S_MCKOUT_ENABLE: I2S master clock output enable
  • I2S_MCKOUT_DISABLE: I2S master clock output disable
[out] | none
Return values
none

Definition at line 181 of file gd32f10x_spi.c.

182 {
183 uint32_t i2sdiv = 2U, i2sof = 0U;
184 uint32_t clks = 0U;
185 uint32_t i2sclock = 0U;
186
187 /* deinit SPI_I2SPSC register */
188 SPI_I2SPSC(spi_periph) = 0x0002U;
189
190 #ifdef GD32F10X_CL
191 /* get the I2S clock source */
192 if(((uint32_t)spi_periph) == SPI1){
193 /* I2S1 clock source selection */
194 clks = I2S1_CLOCK_SEL;
195 }else{
196 /* I2S2 clock source selection */
197 clks = I2S2_CLOCK_SEL;
198 }
199
200 if(0U != (RCU_CFG1 & clks)){
201 /* get RCU PLL2 clock multiplication factor */
202 clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U);
203
204 if((clks > 5U) && (clks < 15U)){
205 /* multiplier is between 8 and 14 */
206 clks += 2U;
207 }else{
208 if(15U == clks){
209 /* multiplier is 20 */
210 clks = 20U;
211 }
212 }
213
214 /* get the PREDV1 value */
215 i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U);
216 /* calculate i2sclock based on PLL2 and PREDV1 */
217 i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U);
218 }else{
219 /* get system clock */
220 i2sclock = rcu_clock_freq_get(CK_SYS);
221 }
222 #else
223 /* get system clock */
224 i2sclock = rcu_clock_freq_get(CK_SYS);
225 #endif /* GD32F10X_CL */
226
227 /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
228 if(I2S_MCKOUT_ENABLE == mckout){
229 clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
230 }else{
231 if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){
232 clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample);
233 }else{
234 clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample);
235 }
236 }
237
238 /* remove the floating point */
239 clks = (clks + 5U) / 10U;
240 i2sof = (clks & 0x00000001U);
241 i2sdiv = ((clks - i2sof) / 2U);
242 i2sof = (i2sof << 8U);
243
244 /* set the default values */
245 if((i2sdiv < 2U) || (i2sdiv > 255U)){
246 i2sdiv = 2U;
247 i2sof = 0U;
248 }
249
250 /* configure SPI_I2SPSC */
251 SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout);
252
253 /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
254 SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
255 /* configure data frame format */
256 SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat;
257 }
SPI1
#define SPI1
Definition: gd32f10x_spi.h:20
I2S_CLOCK_DIV_MASK
#define I2S_CLOCK_DIV_MASK
Definition: gd32f10x_spi.c:21
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
CK_SYS
Definition: gd32f10x_rcu.h:584
I2S2_CLOCK_SEL
#define I2S2_CLOCK_SEL
Definition: gd32f10x_spi.c:19
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
SPI_I2SCTL_DTLEN
#define SPI_I2SCTL_DTLEN
Definition: gd32f10x_spi.h:83
I2S_CLOCK_MUL_MASK
#define I2S_CLOCK_MUL_MASK
Definition: gd32f10x_spi.c:20
I2S_MCKOUT_ENABLE
#define I2S_MCKOUT_ENABLE
Definition: gd32f10x_spi.h:172
I2S_FRAMEFORMAT_DT16B_CH16B
#define I2S_FRAMEFORMAT_DT16B_CH16B
Definition: gd32f10x_spi.h:165
SPI_I2SPSC
#define SPI_I2SPSC(spix)
Definition: gd32f10x_spi.h:32
SPI_I2SCTL_CHLEN
#define SPI_I2SCTL_CHLEN
Definition: gd32f10x_spi.h:82
I2S1_CLOCK_SEL
#define I2S1_CLOCK_SEL
Definition: gd32f10x_spi.c:18
void spi_bidirectional_transfer_config | ( | uint32_t | spi_periph,
 |  | uint32_t | transfer_direction
 | ) |  |

configure SPI bidirectional transfer direction

Parameters
[in] spi_periph SPIx(x=0,1,2)
[in] transfer_direction SPI transfer direction
  • SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
  • SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
Return values
none

Definition at line 409 of file gd32f10x_spi.c.

410 {
411 if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
412 /* set the transmit only mode */
413 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
414 }else{
415 /* set the receive only mode */
416 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
417 }
418 }
SPI_BIDIRECTIONAL_RECEIVE
#define SPI_BIDIRECTIONAL_RECEIVE
Definition: gd32f10x_spi.h:115
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
SPI_BIDIRECTIONAL_TRANSMIT
#define SPI_BIDIRECTIONAL_TRANSMIT
Definition: gd32f10x_spi.h:114
void spi_crc_error_clear ( uint32_t spi_periph )

clear SPI CRC error flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 576 of file gd32f10x_spi.c.

577 {
578 SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
579 }
SPI_FLAG_CRCERR
#define SPI_FLAG_CRCERR
Definition: gd32f10x_spi.h:217
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f10x_spi.h:26
uint16_t spi_crc_get | ( | uint32_t | spi_periph,
 |  | uint8_t | crc
 | ) |  |

get SPI CRC send value or receive value

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] crc SPI crc value
  • SPI_CRC_TX: get transmit crc value
  • SPI_CRC_RX: get receive crc value
[out] | none
Return values
16-bit CRC value

Definition at line 647 of file gd32f10x_spi.c.

648 {
649 if(SPI_CRC_TX == crc){
650 return ((uint16_t)(SPI_TCRC(spi_periph)));
651 }else{
652 return ((uint16_t)(SPI_RCRC(spi_periph)));
653 }
654 }
SPI_CRC_TX
#define SPI_CRC_TX
Definition: gd32f10x_spi.h:198
SPI_RCRC
#define SPI_RCRC(spix)
Definition: gd32f10x_spi.h:29
SPI_TCRC
#define SPI_TCRC(spix)
Definition: gd32f10x_spi.h:30
void spi_crc_next ( uint32_t spi_periph )

SPI next data is CRC value.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 633 of file gd32f10x_spi.c.

634 {
635 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
636 }
SPI_CTL0_CRCNT
#define SPI_CTL0_CRCNT
Definition: gd32f10x_spi.h:46
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_crc_off ( uint32_t spi_periph )

turn off CRC function

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 598 of file gd32f10x_spi.c.

599 {
600 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
601 }
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f10x_spi.h:47
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_crc_on ( uint32_t spi_periph )

turn on CRC function

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 587 of file gd32f10x_spi.c.

588 {
589 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
590 }
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f10x_spi.h:47
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
uint16_t spi_crc_polynomial_get ( uint32_t spi_periph )

get SPI CRC polynomial

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
16-bit CRC polynomial

Definition at line 622 of file gd32f10x_spi.c.

623 {
624 return ((uint16_t)SPI_CRCPOLY(spi_periph));
625 }
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f10x_spi.h:28
void spi_crc_polynomial_set | ( | uint32_t | spi_periph,
 |  | uint16_t | crc_poly
 | ) |  |

set CRC polynomial

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | crc_poly | CRC polynomial value
[out] | none
Return values
none

Definition at line 610 of file gd32f10x_spi.c.

611 {
612 /* set SPI CRC polynomial */
613 SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
614 }
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f10x_spi.h:28
void spi_disable ( uint32_t spi_periph )

disable SPI

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 113 of file gd32f10x_spi.c.

114 {
115 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
116 }
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f10x_spi.h:40
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_dma_disable | ( | uint32_t | spi_periph,
 |  | uint8_t | dma
 | ) |  |

disable SPI DMA send or receive

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] dma SPI DMA mode
  • SPI_DMA_TRANSMIT: SPI transmit data use DMA
  • SPI_DMA_RECEIVE: SPI receive data use DMA
[out] | none
Return values
none

Definition at line 352 of file gd32f10x_spi.c.

353 {
354 if(SPI_DMA_TRANSMIT == dma){
355 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
356 }else{
357 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
358 }
359 }
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f10x_spi.h:53
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f10x_spi.h:194
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f10x_spi.h:52
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
void spi_dma_enable | ( | uint32_t | spi_periph,
 |  | uint8_t | dma
 | ) |  |

enable SPI DMA send or receive

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] dma SPI DMA mode
  • SPI_DMA_TRANSMIT: SPI transmit data use DMA
  • SPI_DMA_RECEIVE: SPI receive data use DMA
[out] | none
Return values
none

Definition at line 334 of file gd32f10x_spi.c.

335 {
336 if(SPI_DMA_TRANSMIT == dma){
337 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
338 }else{
339 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
340 }
341 }
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f10x_spi.h:53
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f10x_spi.h:194
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f10x_spi.h:52
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
void spi_enable ( uint32_t spi_periph )

enable SPI

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 102 of file gd32f10x_spi.c.

103 {
104 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
105 }
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f10x_spi.h:40
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_i2s_data_frame_format_config | ( | uint32_t | spi_periph,
 |  | uint16_t | frame_format
 | ) |  |

configure SPI/I2S data frame format

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] frame_format SPI frame size
  • SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
  • SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
[out] | none
Return values
none

Definition at line 370 of file gd32f10x_spi.c.

371 {
372 /* clear SPI_CTL0_FF16 bit */
373 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
374 /* confige SPI_CTL0_FF16 bit */
375 SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
376 }
SPI_CTL0_FF16
#define SPI_CTL0_FF16
Definition: gd32f10x_spi.h:45
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
uint16_t spi_i2s_data_receive ( uint32_t spi_periph )

SPI receive data.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
16-bit data

Definition at line 396 of file gd32f10x_spi.c.

397 {
398 return ((uint16_t)SPI_DATA(spi_periph));
399 }
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f10x_spi.h:27
void spi_i2s_data_transmit | ( | uint32_t | spi_periph,
 |  | uint16_t | data
 | ) |  |

SPI transmit data.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | data | 16-bit data
[out] | none
Return values
none

Definition at line 385 of file gd32f10x_spi.c.

386 {
387 SPI_DATA(spi_periph) = (uint32_t)data;
388 }
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f10x_spi.h:27
void spi_i2s_deinit ( uint32_t spi_periph )

reset SPI and I2S

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 29 of file gd32f10x_spi.c.

30 {
31 switch(spi_periph){
32 case SPI0:
33 /* reset SPI0 */
34 rcu_periph_reset_enable(RCU_SPI0RST);
35 rcu_periph_reset_disable(RCU_SPI0RST);
36 break;
37 case SPI1:
38 /* reset SPI1 and I2S1 */
39 rcu_periph_reset_enable(RCU_SPI1RST);
40 rcu_periph_reset_disable(RCU_SPI1RST);
41 break;
42 case SPI2:
43 /* reset SPI2 and I2S2 */
44 rcu_periph_reset_enable(RCU_SPI2RST);
45 rcu_periph_reset_disable(RCU_SPI2RST);
46 break;
47 default :
48 break;
49 }
50 }
SPI1
#define SPI1
Definition: gd32f10x_spi.h:20
RCU_SPI1RST
Definition: gd32f10x_rcu.h:457
SPI0
#define SPI0
Definition: gd32f10x_spi.h:19
SPI2
#define SPI2
Definition: gd32f10x_spi.h:21
RCU_SPI2RST
Definition: gd32f10x_rcu.h:458
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
RCU_SPI0RST
Definition: gd32f10x_rcu.h:488
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
FlagStatus spi_i2s_flag_get | ( | uint32_t | spi_periph,
 |  | uint32_t | flag
 | ) |  |

get SPI and I2S flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] flag SPI/I2S flag status
  • SPI_FLAG_TBE: transmit buffer empty flag
  • SPI_FLAG_RBNE: receive buffer not empty flag
  • SPI_FLAG_TRANS: transmit on-going flag
  • SPI_FLAG_RXORERR: receive overrun error flag
  • SPI_FLAG_CONFERR: mode config error flag
  • SPI_FLAG_CRCERR: CRC error flag
  • I2S_FLAG_TBE: transmit buffer empty flag
  • I2S_FLAG_RBNE: receive buffer not empty flag
  • I2S_FLAG_TRANS: transmit on-going flag
  • I2S_FLAG_RXORERR: overrun error flag
  • I2S_FLAG_TXURERR: underrun error flag
  • I2S_FLAG_CH: channel side flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 561 of file gd32f10x_spi.c.

562 {
563 if(SPI_STAT(spi_periph) & flag){
564 return SET;
565 }else{
566 return RESET;
567 }
568 }
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f10x_spi.h:26
void spi_i2s_interrupt_disable | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

disable SPI and I2S interrupt

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt
  • SPI_I2S_INT_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt
[out] | none
Return values
none

Definition at line 462 of file gd32f10x_spi.c.

463 {
464 switch(interrupt){
465 /* SPI/I2S transmit buffer empty interrupt */
466 case SPI_I2S_INT_TBE:
467 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
468 break;
469 /* SPI/I2S receive buffer not empty interrupt */
470 case SPI_I2S_INT_RBNE:
471 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
472 break;
473 /* SPI/I2S error */
474 case SPI_I2S_INT_ERR:
475 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
476 break;
477 default :
478 break;
479 }
480 }
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f10x_spi.h:204
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f10x_spi.h:55
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f10x_spi.h:203
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f10x_spi.h:202
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f10x_spi.h:56
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f10x_spi.h:57
void spi_i2s_interrupt_enable | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

enable SPI and I2S interrupt

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt
  • SPI_I2S_INT_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt
[out] | none
Return values
none

Definition at line 431 of file gd32f10x_spi.c.

432 {
433 switch(interrupt){
434 /* SPI/I2S transmit buffer empty interrupt */
435 case SPI_I2S_INT_TBE:
436 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
437 break;
438 /* SPI/I2S receive buffer not empty interrupt */
439 case SPI_I2S_INT_RBNE:
440 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
441 break;
442 /* SPI/I2S error */
443 case SPI_I2S_INT_ERR:
444 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
445 break;
446 default:
447 break;
448 }
449 }
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f10x_spi.h:204
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f10x_spi.h:55
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f10x_spi.h:203
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f10x_spi.h:202
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f10x_spi.h:56
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f10x_spi.h:57
FlagStatus spi_i2s_interrupt_flag_get | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

get SPI and I2S interrupt flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt flag status
  • SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_FLAG_RXORERR: overrun interrupt
  • SPI_INT_FLAG_CONFERR: config error interrupt
  • SPI_INT_FLAG_CRCERR: CRC error interrupt
  • I2S_INT_FLAG_TXURERR: underrun error interrupt
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 495 of file gd32f10x_spi.c.

496 {
497 uint32_t reg1 = SPI_STAT(spi_periph);
498 uint32_t reg2 = SPI_CTL1(spi_periph);
499
500 switch(interrupt){
501 /* SPI/I2S transmit buffer empty interrupt */
502 case SPI_I2S_INT_FLAG_TBE:
503 reg1 = reg1 & SPI_STAT_TBE;
504 reg2 = reg2 & SPI_CTL1_TBEIE;
505 break;
506 /* SPI/I2S receive buffer not empty interrupt */
507 case SPI_I2S_INT_FLAG_RBNE:
508 reg1 = reg1 & SPI_STAT_RBNE;
509 reg2 = reg2 & SPI_CTL1_RBNEIE;
510 break;
511 /* SPI/I2S overrun interrupt */
512 case SPI_I2S_INT_FLAG_RXORERR:
513 reg1 = reg1 & SPI_STAT_RXORERR;
514 reg2 = reg2 & SPI_CTL1_ERRIE;
515 break;
516 /* SPI config error interrupt */
517 case SPI_INT_FLAG_CONFERR:
518 reg1 = reg1 & SPI_STAT_CONFERR;
519 reg2 = reg2 & SPI_CTL1_ERRIE;
520 break;
521 /* SPI CRC error interrupt */
522 case SPI_INT_FLAG_CRCERR:
523 reg1 = reg1 & SPI_STAT_CRCERR;
524 reg2 = reg2 & SPI_CTL1_ERRIE;
525 break;
526 /* I2S underrun error interrupt */
527 case I2S_INT_FLAG_TXURERR:
528 reg1 = reg1 & SPI_STAT_TXURERR;
529 reg2 = reg2 & SPI_CTL1_ERRIE;
530 break;
531 default :
532 break;
533 }
534 /*get SPI/I2S interrupt flag status */
535 if(reg1 && reg2){
536 return SET;
537 }else{
538 return RESET;
539 }
540 }
SPI_STAT_CONFERR
#define SPI_STAT_CONFERR
Definition: gd32f10x_spi.h:65
SPI_STAT_TBE
#define SPI_STAT_TBE
Definition: gd32f10x_spi.h:61
SPI_INT_FLAG_CRCERR
#define SPI_INT_FLAG_CRCERR
Definition: gd32f10x_spi.h:211
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f10x_spi.h:55
SPI_I2S_INT_FLAG_TBE
#define SPI_I2S_INT_FLAG_TBE
Definition: gd32f10x_spi.h:207
SPI_STAT_CRCERR
#define SPI_STAT_CRCERR
Definition: gd32f10x_spi.h:64
SPI_STAT_TXURERR
#define SPI_STAT_TXURERR
Definition: gd32f10x_spi.h:63
SPI_I2S_INT_FLAG_RBNE
#define SPI_I2S_INT_FLAG_RBNE
Definition: gd32f10x_spi.h:208
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_I2S_INT_FLAG_RXORERR
#define SPI_I2S_INT_FLAG_RXORERR
Definition: gd32f10x_spi.h:209
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f10x_spi.h:26
I2S_INT_FLAG_TXURERR
#define I2S_INT_FLAG_TXURERR
Definition: gd32f10x_spi.h:212
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f10x_spi.h:56
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f10x_spi.h:57
SPI_INT_FLAG_CONFERR
#define SPI_INT_FLAG_CONFERR
Definition: gd32f10x_spi.h:210
SPI_STAT_RXORERR
#define SPI_STAT_RXORERR
Definition: gd32f10x_spi.h:66
SPI_STAT_RBNE
#define SPI_STAT_RBNE
Definition: gd32f10x_spi.h:60
void spi_init | ( | uint32_t | spi_periph,
 |  | spi_parameter_struct * | spi_struct
 | ) |  |

initialize SPI parameter

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | spi_struct | SPI parameter initialization stuct members of the structure and the member values are shown as below: device_mode: SPI_MASTER, SPI_SLAVE trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT nss: SPI_NSS_SOFT, SPI_NSS_HARD endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
[out] | none
Return values
none

Definition at line 69 of file gd32f10x_spi.c.

70 {
71 uint32_t reg = 0U;
72 reg = SPI_CTL0(spi_periph);
73 reg &= SPI_INIT_MASK;
74
75 /* select SPI as master or slave */
76 reg |= spi_struct->device_mode;
77 /* select SPI transfer mode */
78 reg |= spi_struct->trans_mode;
79 /* select SPI frame size */
80 reg |= spi_struct->frame_size;
81 /* select SPI NSS use hardware or software */
82 reg |= spi_struct->nss;
83 /* select SPI LSB or MSB */
84 reg |= spi_struct->endian;
85 /* select SPI polarity and phase */
86 reg |= spi_struct->clock_polarity_phase;
87 /* select SPI prescale to adjust transmit speed */
88 reg |= spi_struct->prescale;
89
90 /* write to SPI_CTL0 register */
91 SPI_CTL0(spi_periph) = (uint32_t)reg;
92
93 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
94 }
SPI_I2SCTL_I2SSEL
#define SPI_I2SCTL_I2SSEL
Definition: gd32f10x_spi.h:89
spi_parameter_struct::nss
uint32_t nss
Definition: gd32f10x_spi.h:103
spi_parameter_struct::device_mode
uint32_t device_mode
Definition: gd32f10x_spi.h:100
spi_parameter_struct::frame_size
uint32_t frame_size
Definition: gd32f10x_spi.h:102
spi_parameter_struct::trans_mode
uint32_t trans_mode
Definition: gd32f10x_spi.h:101
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
spi_parameter_struct::endian
uint32_t endian
Definition: gd32f10x_spi.h:104
SPI_INIT_MASK
#define SPI_INIT_MASK
Definition: gd32f10x_spi.c:15
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
spi_parameter_struct::clock_polarity_phase
uint32_t clock_polarity_phase
Definition: gd32f10x_spi.h:105
spi_parameter_struct::prescale
uint32_t prescale
Definition: gd32f10x_spi.h:106
void spi_nss_internal_high ( uint32_t spi_periph )

SPI NSS pin high level in software mode.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 309 of file gd32f10x_spi.c.

310 {
311 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
312 }
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f10x_spi.h:42
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_nss_internal_low ( uint32_t spi_periph )

SPI NSS pin low level in software mode.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 320 of file gd32f10x_spi.c.

321 {
322 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
323 }
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f10x_spi.h:42
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_nss_output_disable ( uint32_t spi_periph )

disable SPI NSS output

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 298 of file gd32f10x_spi.c.

299 {
300 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
301 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f10x_spi.h:54
void spi_nss_output_enable ( uint32_t spi_periph )

enable SPI NSS output

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 287 of file gd32f10x_spi.c.

288 {
289 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
290 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f10x_spi.h:54
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Data Structures | Macros | Functions
gd32f10x_timer.h File Reference

definitions for the TIMER More...

#include "gd32f10x.h"

Go to the source code of this file.

Data Structures

struct | timer_parameter_struct
struct | timer_break_parameter_struct
struct | timer_oc_parameter_struct
struct | timer_ic_parameter_struct

Macros

#define | TIMER0 (TIMER_BASE + 0x00012C00U)
#define | TIMER1 (TIMER_BASE + 0x00000000U)
#define | TIMER2 (TIMER_BASE + 0x00000400U)
#define | TIMER3 (TIMER_BASE + 0x00000800U)
#define | TIMER4 (TIMER_BASE + 0x00000C00U)
#define | TIMER5 (TIMER_BASE + 0x00001000U)
#define | TIMER6 (TIMER_BASE + 0x00001400U)
#define | TIMER7 (TIMER_BASE + 0x00013400U)
#define | TIMER8 (TIMER_BASE + 0x00014C00U)
#define | TIMER9 (TIMER_BASE + 0x00015000U)
#define | TIMER10 (TIMER_BASE + 0x00015400U)
#define | TIMER11 (TIMER_BASE + 0x00001800U)
#define | TIMER12 (TIMER_BASE + 0x00001C00U)
#define | TIMER13 (TIMER_BASE + 0x00002000U)
#define | TIMER_CTL0(timerx) REG32((timerx) + 0x00U)
#define | TIMER_CTL1(timerx) REG32((timerx) + 0x04U)
#define | TIMER_SMCFG(timerx) REG32((timerx) + 0x08U)
#define | TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU)
#define | TIMER_INTF(timerx) REG32((timerx) + 0x10U)
#define | TIMER_SWEVG(timerx) REG32((timerx) + 0x14U)
#define | TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U)
#define | TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU)
#define | TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U)
#define | TIMER_CNT(timerx) REG32((timerx) + 0x24U)
#define | TIMER_PSC(timerx) REG32((timerx) + 0x28U)
#define | TIMER_CAR(timerx) REG32((timerx) + 0x2CU)
#define | TIMER_CREP(timerx) REG32((timerx) + 0x30U)
#define | TIMER_CH0CV(timerx) REG32((timerx) + 0x34U)
#define | TIMER_CH1CV(timerx) REG32((timerx) + 0x38U)
#define | TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU)
#define | TIMER_CH3CV(timerx) REG32((timerx) + 0x40U)
#define | TIMER_CCHP(timerx) REG32((timerx) + 0x44U)
#define | TIMER_DMACFG(timerx) REG32((timerx) + 0x48U)
#define | TIMER_DMATB(timerx) REG32((timerx) + 0x4CU)
#define | TIMER_CTL0_CEN BIT(0)
#define | TIMER_CTL0_UPDIS BIT(1)
#define | TIMER_CTL0_UPS BIT(2)
#define | TIMER_CTL0_SPM BIT(3)
#define | TIMER_CTL0_DIR BIT(4)
#define | TIMER_CTL0_CAM BITS(5,6)
#define | TIMER_CTL0_ARSE BIT(7)
#define | TIMER_CTL0_CKDIV BITS(8,9)
#define | TIMER_CTL1_CCSE BIT(0)
#define | TIMER_CTL1_CCUC BIT(2)
#define | TIMER_CTL1_DMAS BIT(3)
#define | TIMER_CTL1_MMC BITS(4,6)
#define | TIMER_CTL1_TI0S BIT(7)
#define | TIMER_CTL1_ISO0 BIT(8)
#define | TIMER_CTL1_ISO0N BIT(9)
#define | TIMER_CTL1_ISO1 BIT(10)
#define | TIMER_CTL1_ISO1N BIT(11)
#define | TIMER_CTL1_ISO2 BIT(12)
#define | TIMER_CTL1_ISO2N BIT(13)
#define | TIMER_CTL1_ISO3 BIT(14)
#define | TIMER_SMCFG_SMC BITS(0,2)
#define | TIMER_SMCFG_TRGS BITS(4,6)
#define | TIMER_SMCFG_MSM BIT(7)
#define | TIMER_SMCFG_ETFC BITS(8,11)
#define | TIMER_SMCFG_ETPSC BITS(12,13)
#define | TIMER_SMCFG_SMC1 BIT(14)
#define | TIMER_SMCFG_ETP BIT(15)
#define | TIMER_DMAINTEN_UPIE BIT(0)
#define | TIMER_DMAINTEN_CH0IE BIT(1)
#define | TIMER_DMAINTEN_CH1IE BIT(2)
#define | TIMER_DMAINTEN_CH2IE BIT(3)
#define | TIMER_DMAINTEN_CH3IE BIT(4)
#define | TIMER_DMAINTEN_CMTIE BIT(5)
#define | TIMER_DMAINTEN_TRGIE BIT(6)
#define | TIMER_DMAINTEN_BRKIE BIT(7)
#define | TIMER_DMAINTEN_UPDEN BIT(8)
#define | TIMER_DMAINTEN_CH0DEN BIT(9)
#define | TIMER_DMAINTEN_CH1DEN BIT(10)
#define | TIMER_DMAINTEN_CH2DEN BIT(11)
#define | TIMER_DMAINTEN_CH3DEN BIT(12)
#define | TIMER_DMAINTEN_CMTDEN BIT(13)
#define | TIMER_DMAINTEN_TRGDEN BIT(14)
#define | TIMER_INTF_UPIF BIT(0)
#define | TIMER_INTF_CH0IF BIT(1)
#define | TIMER_INTF_CH1IF BIT(2)
#define | TIMER_INTF_CH2IF BIT(3)
#define | TIMER_INTF_CH3IF BIT(4)
#define | TIMER_INTF_CMTIF BIT(5)
#define | TIMER_INTF_TRGIF BIT(6)
#define | TIMER_INTF_BRKIF BIT(7)
#define | TIMER_INTF_CH0OF BIT(9)
#define | TIMER_INTF_CH1OF BIT(10)
#define | TIMER_INTF_CH2OF BIT(11)
#define | TIMER_INTF_CH3OF BIT(12)
#define | TIMER_SWEVG_UPG BIT(0)
#define | TIMER_SWEVG_CH0G BIT(1)
#define | TIMER_SWEVG_CH1G BIT(2)
#define | TIMER_SWEVG_CH2G BIT(3)
#define | TIMER_SWEVG_CH3G BIT(4)
#define | TIMER_SWEVG_CMTG BIT(5)
#define | TIMER_SWEVG_TRGG BIT(6)
#define | TIMER_SWEVG_BRKG BIT(7)
#define | TIMER_CHCTL0_CH0MS BITS(0,1)
#define | TIMER_CHCTL0_CH0COMFEN BIT(2)
#define | TIMER_CHCTL0_CH0COMSEN BIT(3)
#define | TIMER_CHCTL0_CH0COMCTL BITS(4,6)
#define | TIMER_CHCTL0_CH0COMCEN BIT(7)
#define | TIMER_CHCTL0_CH1MS BITS(8,9)
#define | TIMER_CHCTL0_CH1COMFEN BIT(10)
#define | TIMER_CHCTL0_CH1COMSEN BIT(11)
#define | TIMER_CHCTL0_CH1COMCTL BITS(12,14)
#define | TIMER_CHCTL0_CH1COMCEN BIT(15)
#define | TIMER_CHCTL0_CH0CAPPSC BITS(2,3)
#define | TIMER_CHCTL0_CH0CAPFLT BITS(4,7)
#define | TIMER_CHCTL0_CH1CAPPSC BITS(10,11)
#define | TIMER_CHCTL0_CH1CAPFLT BITS(12,15)
#define | TIMER_CHCTL1_CH2MS BITS(0,1)
#define | TIMER_CHCTL1_CH2COMFEN BIT(2)
#define | TIMER_CHCTL1_CH2COMSEN BIT(3)
#define | TIMER_CHCTL1_CH2COMCTL BITS(4,6)
#define | TIMER_CHCTL1_CH2COMCEN BIT(7)
#define | TIMER_CHCTL1_CH3MS BITS(8,9)
#define | TIMER_CHCTL1_CH3COMFEN BIT(10)
#define | TIMER_CHCTL1_CH3COMSEN BIT(11)
#define | TIMER_CHCTL1_CH3COMCTL BITS(12,14)
#define | TIMER_CHCTL1_CH3COMCEN BIT(15)
#define | TIMER_CHCTL1_CH2CAPPSC BITS(2,3)
#define | TIMER_CHCTL1_CH2CAPFLT BITS(4,7)
#define | TIMER_CHCTL1_CH3CAPPSC BITS(10,11)
#define | TIMER_CHCTL1_CH3CAPFLT BITS(12,15)
#define | TIMER_CHCTL2_CH0EN BIT(0)
#define | TIMER_CHCTL2_CH0P BIT(1)
#define | TIMER_CHCTL2_CH0NEN BIT(2)
#define | TIMER_CHCTL2_CH0NP BIT(3)
#define | TIMER_CHCTL2_CH1EN BIT(4)
#define | TIMER_CHCTL2_CH1P BIT(5)
#define | TIMER_CHCTL2_CH1NEN BIT(6)
#define | TIMER_CHCTL2_CH1NP BIT(7)
#define | TIMER_CHCTL2_CH2EN BIT(8)
#define | TIMER_CHCTL2_CH2P BIT(9)
#define | TIMER_CHCTL2_CH2NEN BIT(10)
#define | TIMER_CHCTL2_CH2NP BIT(11)
#define | TIMER_CHCTL2_CH3EN BIT(12)
#define | TIMER_CHCTL2_CH3P BIT(13)
#define | TIMER_CNT_CNT BITS(0,15)
#define | TIMER_PSC_PSC BITS(0,15)
#define | TIMER_CAR_CARL BITS(0,15)
#define | TIMER_CREP_CREP BITS(0,7)
#define | TIMER_CH0CV_CH0VAL BITS(0,15)
#define | TIMER_CH1CV_CH1VAL BITS(0,15)
#define | TIMER_CH2CV_CH2VAL BITS(0,15)
#define | TIMER_CH3CV_CH3VAL BITS(0,15)
#define | TIMER_CCHP_DTCFG BITS(0,7)
#define | TIMER_CCHP_PROT BITS(8,9)
#define | TIMER_CCHP_IOS BIT(10)
#define | TIMER_CCHP_ROS BIT(11)
#define | TIMER_CCHP_BRKEN BIT(12)
#define | TIMER_CCHP_BRKP BIT(13)
#define | TIMER_CCHP_OAEN BIT(14)
#define | TIMER_CCHP_POEN BIT(15)
#define | TIMER_DMACFG_DMATA BITS(0,4)
#define | TIMER_DMACFG_DMATC BITS(8,12)
#define | TIMER_DMATB_DMATB BITS(0,15)
#define | TIMER_INT_UP TIMER_DMAINTEN_UPIE
#define | TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE
#define | TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE
#define | TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE
#define | TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE
#define | TIMER_INT_CMT TIMER_DMAINTEN_CMTIE
#define | TIMER_INT_TRG TIMER_DMAINTEN_TRGIE
#define | TIMER_INT_BRK TIMER_DMAINTEN_BRKIE
#define | TIMER_FLAG_UP TIMER_INTF_UPIF
#define | TIMER_FLAG_CH0 TIMER_INTF_CH0IF
#define | TIMER_FLAG_CH1 TIMER_INTF_CH1IF
#define | TIMER_FLAG_CH2 TIMER_INTF_CH2IF
#define | TIMER_FLAG_CH3 TIMER_INTF_CH3IF
#define | TIMER_FLAG_CMT TIMER_INTF_CMTIF
#define | TIMER_FLAG_TRG TIMER_INTF_TRGIF
#define | TIMER_FLAG_BRK TIMER_INTF_BRKIF
#define | TIMER_FLAG_CH0O TIMER_INTF_CH0OF
#define | TIMER_FLAG_CH1O TIMER_INTF_CH1OF
#define | TIMER_FLAG_CH2O TIMER_INTF_CH2OF
#define | TIMER_FLAG_CH3O TIMER_INTF_CH3OF
#define | TIMER_INT_FLAG_UP TIMER_INTF_UPIF
#define | TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF
#define | TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF
#define | TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF
#define | TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF
#define | TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF
#define | TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF
#define | TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF
#define | TIMER_DMA_UPD ((uint16_t)0x0100U)
#define | TIMER_DMA_CH0D ((uint16_t)0x0200U)
#define | TIMER_DMA_CH1D ((uint16_t)0x0400U)
#define | TIMER_DMA_CH2D ((uint16_t)0x0800U)
#define | TIMER_DMA_CH3D ((uint16_t)0x1000U)
#define | TIMER_DMA_CMTD ((uint16_t)0x2000U)
#define | TIMER_DMA_TRGD ((uint16_t)0x4000U)
#define | TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U)
#define | TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U)
#define | DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
#define | TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0)
#define | TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1)
#define | TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2)
#define | TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3)
#define | TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4)
#define | TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5)
#define | TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6)
#define | TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7)
#define | TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8)
#define | TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9)
#define | TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10)
#define | TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11)
#define | TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12)
#define | TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13)
#define | TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14)
#define | TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15)
#define | TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16)
#define | TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17)
#define | TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18)
#define | TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19)
#define | DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
#define | TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0)
#define | TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1)
#define | TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2)
#define | TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3)
#define | TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4)
#define | TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5)
#define | TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6)
#define | TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7)
#define | TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8)
#define | TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9)
#define | TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10)
#define | TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11)
#define | TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12)
#define | TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13)
#define | TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14)
#define | TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15)
#define | TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16)
#define | TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17)
#define | TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U)
#define | TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U)
#define | TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U)
#define | TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U)
#define | TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U)
#define | TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U)
#define | TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U)
#define | TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U)
#define | CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
#define | TIMER_COUNTER_EDGE CTL0_CAM(0)
#define | TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1)
#define | TIMER_COUNTER_CENTER_UP CTL0_CAM(2)
#define | TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3)
#define | TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U)
#define | TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U)
#define | TIMER_COUNTER_UP ((uint16_t)0x0000U)
#define | TIMER_COUNTER_DOWN ((uint16_t)0x0010U)
#define | CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
#define | TIMER_CKDIV_DIV1 CTL0_CKDIV(0)
#define | TIMER_CKDIV_DIV2 CTL0_CKDIV(1)
#define | TIMER_CKDIV_DIV4 CTL0_CKDIV(2)
#define | TIMER_SP_MODE_SINGLE ((uint8_t)0x00U)
#define | TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U)
#define | TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U)
#define | TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U)
#define | TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U)
#define | TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U)
#define | TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U)
#define | TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U)
#define | TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U)
#define | TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U)
#define | TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U)
#define | TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U)
#define | CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
#define | TIMER_CCHP_PROT_OFF CCHP_PROT(0)
#define | TIMER_CCHP_PROT_0 CCHP_PROT(1)
#define | TIMER_CCHP_PROT_1 CCHP_PROT(2)
#define | TIMER_CCHP_PROT_2 CCHP_PROT(3)
#define | TIMER_BREAK_ENABLE ((uint16_t)0x1000U)
#define | TIMER_BREAK_DISABLE ((uint16_t)0x0000U)
#define | TIMER_CH_0 ((uint16_t)0x0000U)
#define | TIMER_CH_1 ((uint16_t)0x0001U)
#define | TIMER_CH_2 ((uint16_t)0x0002U)
#define | TIMER_CH_3 ((uint16_t)0x0003U)
#define | TIMER_CCX_ENABLE ((uint32_t)0x00000001U)
#define | TIMER_CCX_DISABLE ((uint32_t)0x00000000U)
#define | TIMER_CCXN_ENABLE ((uint16_t)0x0004U)
#define | TIMER_CCXN_DISABLE ((uint16_t)0x0000U)
#define | TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U)
#define | TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U)
#define | TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U)
#define | TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U)
#define | TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100)
#define | TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000)
#define | TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U)
#define | TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U)
#define | TIMER_OC_MODE_TIMING ((uint16_t)0x0000U)
#define | TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U)
#define | TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U)
#define | TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U)
#define | TIMER_OC_MODE_LOW ((uint16_t)0x0040U)
#define | TIMER_OC_MODE_HIGH ((uint16_t)0x0050U)
#define | TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U)
#define | TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U)
#define | TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U)
#define | TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U)
#define | TIMER_OC_FAST_ENABLE ((uint16_t)0x0004)
#define | TIMER_OC_FAST_DISABLE ((uint16_t)0x0000)
#define | TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U)
#define | TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U)
#define | TIMER_UPDATECTL_CCU ((uint8_t)0x00U)
#define | TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U)
#define | TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U)
#define | TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U)
#define | TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU)
#define | TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U)
#define | TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U)
#define | TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U)
#define | TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U)
#define | TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U)
#define | TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U)
#define | TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU)
#define | SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
#define | TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0)
#define | TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1)
#define | TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2)
#define | TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3)
#define | TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4)
#define | TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5)
#define | TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6)
#define | TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7)
#define | CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
#define | TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0)
#define | TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1)
#define | TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2)
#define | TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3)
#define | TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4)
#define | TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5)
#define | TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6)
#define | TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7)
#define | SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
#define | TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0)
#define | TIMER_ENCODER_MODE0 SMCFG_SMC(1)
#define | TIMER_ENCODER_MODE1 SMCFG_SMC(2)
#define | TIMER_ENCODER_MODE2 SMCFG_SMC(3)
#define | TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4)
#define | TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5)
#define | TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6)
#define | TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7)
#define | TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U)
#define | TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U)
#define | SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
#define | TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0)
#define | TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1)
#define | TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2)
#define | TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3)
#define | TIMER_ETP_FALLING TIMER_SMCFG_ETP
#define | TIMER_ETP_RISING ((uint32_t)0x00000000U)
#define | TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U)
#define | TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U)

Functions

void | timer_deinit (uint32_t timer_periph)
deinit a TIMER More...
void | timer_init (uint32_t timer_periph, timer_parameter_struct *initpara)
initialize TIMER counter More...
void | timer_enable (uint32_t timer_periph)
enable a TIMER More...
void | timer_disable (uint32_t timer_periph)
disable a TIMER More...
void | timer_auto_reload_shadow_enable (uint32_t timer_periph)
enable the auto reload shadow function More...
void | timer_auto_reload_shadow_disable (uint32_t timer_periph)
disable the auto reload shadow function More...
void | timer_update_event_enable (uint32_t timer_periph)
enable the update event More...
void | timer_update_event_disable (uint32_t timer_periph)
disable the update event More...
void | timer_counter_alignment (uint32_t timer_periph, uint16_t aligned)
set TIMER counter alignment mode More...
void | timer_counter_up_direction (uint32_t timer_periph)
set TIMER counter up direction More...
void | timer_counter_down_direction (uint32_t timer_periph)
set TIMER counter down direction More...
void | timer_prescaler_config (uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
configure TIMER prescaler More...
void | timer_repetition_value_config (uint32_t timer_periph, uint16_t repetition)
configure TIMER repetition register value More...
void | timer_autoreload_value_config (uint32_t timer_periph, uint32_t autoreload)
configure TIMER autoreload register value More...
void | timer_counter_value_config (uint32_t timer_periph, uint32_t counter)
configure TIMER counter register value More...
uint32_t | timer_counter_read (uint32_t timer_periph)
read TIMER counter value More...
uint16_t | timer_prescaler_read (uint32_t timer_periph)
read TIMER prescaler value More...
void | timer_single_pulse_mode_config (uint32_t timer_periph, uint8_t spmode)
configure TIMER single pulse mode More...
void | timer_update_source_config (uint32_t timer_periph, uint8_t update)
configure TIMER update source More...
void | timer_interrupt_enable (uint32_t timer_periph, uint32_t interrupt)
enable the TIMER interrupt More...
void | timer_interrupt_disable (uint32_t timer_periph, uint32_t interrupt)
disable the TIMER interrupt More...
FlagStatus | timer_interrupt_flag_get (uint32_t timer_periph, uint32_t interrupt)
get timer interrupt flag More...
void | timer_interrupt_flag_clear (uint32_t timer_periph, uint32_t interrupt)
clear TIMER interrupt flag More...
FlagStatus | timer_flag_get (uint32_t timer_periph, uint32_t flag)
get TIMER flags More...
void | timer_flag_clear (uint32_t timer_periph, uint32_t flag)
clear TIMER flags More...
void | timer_dma_enable (uint32_t timer_periph, uint16_t dma)
enable the TIMER DMA More...
void | timer_dma_disable (uint32_t timer_periph, uint16_t dma)
disable the TIMER DMA More...
void | timer_channel_dma_request_source_select (uint32_t timer_periph, uint8_t dma_request)
channel DMA request source selection More...
void | timer_dma_transfer_config (uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
configure the TIMER DMA transfer More...
void | timer_event_software_generate (uint32_t timer_periph, uint16_t event)
software generate events More...
void | timer_break_config (uint32_t timer_periph, timer_break_parameter_struct *breakpara)
configure TIMER break function More...
void | timer_break_enable (uint32_t timer_periph)
enable TIMER break function More...
void | timer_break_disable (uint32_t timer_periph)
disable TIMER break function More...
void | timer_automatic_output_enable (uint32_t timer_periph)
enable TIMER output automatic function More...
void | timer_automatic_output_disable (uint32_t timer_periph)
disable TIMER output automatic function More...
void | timer_primary_output_config (uint32_t timer_periph, ControlStatus newvalue)
configure TIMER primary output function More...
void | timer_channel_control_shadow_config (uint32_t timer_periph, ControlStatus newvalue)
channel capture/compare control shadow register enable More...
void | timer_channel_control_shadow_update_config (uint32_t timer_periph, uint8_t ccuctl)
configure TIMER channel control shadow register update control More...
void | timer_channel_output_config (uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
configure TIMER channel output function More...
void | timer_channel_output_mode_config (uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
configure TIMER channel output compare mode More...
void | timer_channel_output_pulse_value_config (uint32_t timer_periph, uint16_t channel, uint32_t pulse)
configure TIMER channel output pulse value More...
void | timer_channel_output_shadow_config (uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
configure TIMER channel output shadow function More...
void | timer_channel_output_fast_config (uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
configure TIMER channel output fast function More...
void | timer_channel_output_clear_config (uint32_t timer_periph, uint16_t channel, uint16_t occlear)
configure TIMER channel output clear function More...
void | timer_channel_output_polarity_config (uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
configure TIMER channel output polarity More...
void | timer_channel_complementary_output_polarity_config (uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
configure TIMER channel complementary output polarity More...
void | timer_channel_output_state_config (uint32_t timer_periph, uint16_t channel, uint32_t state)
configure TIMER channel enable state More...
void | timer_channel_complementary_output_state_config (uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
configure TIMER channel complementary output enable state More...
void | timer_input_capture_config (uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
configure TIMER input capture parameter More...
void | timer_channel_input_capture_prescaler_config (uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value More...
uint32_t | timer_channel_capture_value_register_read (uint32_t timer_periph, uint16_t channel)
read TIMER channel capture compare register value More...
void | timer_input_pwm_capture_config (uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
configure TIMER input pwm capture function More...
void | timer_hall_mode_config (uint32_t timer_periph, uint8_t hallmode)
configure TIMER hall sensor mode More...
void | timer_input_trigger_source_select (uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source More...
void | timer_master_output_trigger_source_select (uint32_t timer_periph, uint32_t outrigger)
select TIMER master mode output trigger source More...
void | timer_slave_mode_select (uint32_t timer_periph, uint32_t slavemode)
select TIMER slave mode More...
void | timer_master_slave_mode_config (uint32_t timer_periph, uint8_t masterslave)
configure TIMER master slave mode More...
void | timer_external_trigger_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input More...
void | timer_quadrature_decoder_mode_config (uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
configure TIMER quadrature decoder mode More...
void | timer_internal_clock_config (uint32_t timer_periph)
configure TIMER internal clock mode More...
void | timer_internal_trigger_as_external_clock_config (uint32_t timer_periph, uint32_t intrigger)
configure TIMER the internal trigger as external clock input More...
void | timer_external_trigger_as_external_clock_config (uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
configure TIMER the external trigger as external clock input More...
void | timer_external_clock_mode0_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode0 More...
void | timer_external_clock_mode1_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode1 More...
void | timer_external_clock_mode1_disable (uint32_t timer_periph)
disable TIMER the external clock mode1 More...

Detailed Description

definitions for the TIMER

Definition in file gd32f10x_timer.h.

Macro Definition Documentation

#define CCHP_PROT ( regval ) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))

Definition at line 415 of file gd32f10x_timer.h.

#define CTL0_CAM ( regval ) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))

Definition at line 370 of file gd32f10x_timer.h.

#define CTL0_CKDIV ( regval ) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))

Definition at line 385 of file gd32f10x_timer.h.

#define CTL1_MMC ( regval ) (BITS(4, 6) & ((uint32_t)(regval) << 4U))

Definition at line 509 of file gd32f10x_timer.h.

#define DMACFG_DMATA ( regval ) (BITS(0, 4) & ((uint32_t)(regval) << 0U))

Definition at line 316 of file gd32f10x_timer.h.

#define DMACFG_DMATC ( regval ) (BITS(8, 12) & ((uint32_t)(regval) << 8U))

Definition at line 339 of file gd32f10x_timer.h.

#define SMCFG_ETPSC ( regval ) (BITS(12, 13) & ((uint32_t)(regval) << 12U))

Definition at line 535 of file gd32f10x_timer.h.

#define SMCFG_SMC ( regval ) (BITS(0, 2) & ((uint32_t)(regval) << 0U))

Definition at line 520 of file gd32f10x_timer.h.

#define SMCFG_TRGSEL ( regval ) (BITS(4, 6) & ((uint32_t)(regval) << 4U))

Definition at line 498 of file gd32f10x_timer.h.

#define TIMER0 (TIMER_BASE + 0x00012C00U)

Definition at line 19 of file gd32f10x_timer.h.

#define TIMER1 (TIMER_BASE + 0x00000000U)

Definition at line 20 of file gd32f10x_timer.h.

#define TIMER10 (TIMER_BASE + 0x00015400U)

Definition at line 29 of file gd32f10x_timer.h.

#define TIMER11 (TIMER_BASE + 0x00001800U)

Definition at line 30 of file gd32f10x_timer.h.

#define TIMER12 (TIMER_BASE + 0x00001C00U)

Definition at line 31 of file gd32f10x_timer.h.

#define TIMER13 (TIMER_BASE + 0x00002000U)

Definition at line 32 of file gd32f10x_timer.h.

#define TIMER2 (TIMER_BASE + 0x00000400U)

Definition at line 21 of file gd32f10x_timer.h.

#define TIMER3 (TIMER_BASE + 0x00000800U)

Definition at line 22 of file gd32f10x_timer.h.

#define TIMER4 (TIMER_BASE + 0x00000C00U)

Definition at line 23 of file gd32f10x_timer.h.

#define TIMER5 (TIMER_BASE + 0x00001000U)

Definition at line 24 of file gd32f10x_timer.h.

#define TIMER6 (TIMER_BASE + 0x00001400U)

Definition at line 25 of file gd32f10x_timer.h.

#define TIMER7 (TIMER_BASE + 0x00013400U)

Definition at line 26 of file gd32f10x_timer.h.

#define TIMER8 (TIMER_BASE + 0x00014C00U)

Definition at line 27 of file gd32f10x_timer.h.

#define TIMER9 (TIMER_BASE + 0x00015000U)

Definition at line 28 of file gd32f10x_timer.h.

#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U)

break input disable

Definition at line 423 of file gd32f10x_timer.h.

#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U)

break input enable

Definition at line 422 of file gd32f10x_timer.h.

#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U)

break input polarity is high

Definition at line 408 of file gd32f10x_timer.h.

#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U)

break input polarity is low

Definition at line 407 of file gd32f10x_timer.h.

#define TIMER_CAR ( timerx ) REG32((timerx) + 0x2CU)

TIMER counter auto reload register

Definition at line 46 of file gd32f10x_timer.h.

#define TIMER_CAR_CARL BITS(0,15)

16 bit counter auto reload value

Definition at line 190 of file gd32f10x_timer.h.

#define TIMER_CCHP ( timerx ) REG32((timerx) + 0x44U)

TIMER complementary channel protection register

Definition at line 52 of file gd32f10x_timer.h.

#define TIMER_CCHP_BRKEN BIT(12)

break enable

Definition at line 212 of file gd32f10x_timer.h.

#define TIMER_CCHP_BRKP BIT(13)

break polarity

Definition at line 213 of file gd32f10x_timer.h.

#define TIMER_CCHP_DTCFG BITS(0,7)

dead time configure

Definition at line 208 of file gd32f10x_timer.h.

#define TIMER_CCHP_IOS BIT(10)

idle mode off-state configure

Definition at line 210 of file gd32f10x_timer.h.

#define TIMER_CCHP_OAEN BIT(14)

output automatic enable

Definition at line 214 of file gd32f10x_timer.h.

#define TIMER_CCHP_POEN BIT(15)

primary output enable

Definition at line 215 of file gd32f10x_timer.h.

#define TIMER_CCHP_PROT BITS(8,9)

complementary register protect control

Definition at line 209 of file gd32f10x_timer.h.

#define TIMER_CCHP_PROT_0 CCHP_PROT(1)

PROT mode 0

Definition at line 417 of file gd32f10x_timer.h.

#define TIMER_CCHP_PROT_1 CCHP_PROT(2)

PROT mode 1

Definition at line 418 of file gd32f10x_timer.h.

#define TIMER_CCHP_PROT_2 CCHP_PROT(3)

PROT mode 2

Definition at line 419 of file gd32f10x_timer.h.

#define TIMER_CCHP_PROT_OFF CCHP_PROT(0)

protect disable

Definition at line 416 of file gd32f10x_timer.h.

#define TIMER_CCHP_ROS BIT(11)

run mode off-state configure

Definition at line 211 of file gd32f10x_timer.h.

#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U)

channel disable

Definition at line 433 of file gd32f10x_timer.h.

#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U)

channel enable

Definition at line 432 of file gd32f10x_timer.h.

#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U)

channel complementary disable

Definition at line 437 of file gd32f10x_timer.h.

#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U)

channel complementary enable

Definition at line 436 of file gd32f10x_timer.h.

#define TIMER_CH0CV ( timerx ) REG32((timerx) + 0x34U)

TIMER channel 0 capture/compare value register

Definition at line 48 of file gd32f10x_timer.h.

#define TIMER_CH0CV_CH0VAL BITS(0,15)

capture/compare value of channel 0

Definition at line 196 of file gd32f10x_timer.h.

#define TIMER_CH1CV ( timerx ) REG32((timerx) + 0x38U)

TIMER channel 1 capture/compare value register

Definition at line 49 of file gd32f10x_timer.h.

#define TIMER_CH1CV_CH1VAL BITS(0,15)

capture/compare value of channel 1

Definition at line 199 of file gd32f10x_timer.h.

#define TIMER_CH2CV ( timerx ) REG32((timerx) + 0x3CU)

TIMER channel 2 capture/compare value register

Definition at line 50 of file gd32f10x_timer.h.

#define TIMER_CH2CV_CH2VAL BITS(0,15)

capture/compare value of channel 2

Definition at line 202 of file gd32f10x_timer.h.

#define TIMER_CH3CV ( timerx ) REG32((timerx) + 0x40U)

TIMER channel 3 capture/compare value register

Definition at line 51 of file gd32f10x_timer.h.

#define TIMER_CH3CV_CH3VAL BITS(0,15)

capture/compare value of channel 3

Definition at line 205 of file gd32f10x_timer.h.

#define TIMER_CH_0 ((uint16_t)0x0000U)

TIMER channel 0(TIMERx(x=0..4,7..13))

Definition at line 426 of file gd32f10x_timer.h.

#define TIMER_CH_1 ((uint16_t)0x0001U)

TIMER channel 1(TIMERx(x=0..4,7,8,11))

Definition at line 427 of file gd32f10x_timer.h.

#define TIMER_CH_2 ((uint16_t)0x0002U)

TIMER channel 2(TIMERx(x=0..4,7))

Definition at line 428 of file gd32f10x_timer.h.

#define TIMER_CH_3 ((uint16_t)0x0003U)

TIMER channel 3(TIMERx(x=0..4,7))

Definition at line 429 of file gd32f10x_timer.h.

#define TIMER_CHCTL0 ( timerx ) REG32((timerx) + 0x18U)

TIMER channel control register 0

Definition at line 41 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7)

channel 0 input capture filter control

Definition at line 145 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3)

channel 0 input capture prescaler

Definition at line 144 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH0COMCEN BIT(7)

channel 0 output compare clear enable

Definition at line 137 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH0COMCTL BITS(4,6)

channel 0 output compare mode

Definition at line 136 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH0COMFEN BIT(2)

channel 0 output compare fast enable

Definition at line 134 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH0COMSEN BIT(3)

channel 0 output compare shadow enable

Definition at line 135 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH0MS BITS(0,1)

channel 0 mode selection

Definition at line 133 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15)

channel 1 input capture filter control

Definition at line 147 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11)

channel 1 input capture prescaler

Definition at line 146 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH1COMCEN BIT(15)

channel 1 output compare clear enable

Definition at line 142 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH1COMCTL BITS(12,14)

channel 1 output compare mode

Definition at line 141 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH1COMFEN BIT(10)

channel 1 output compare fast enable

Definition at line 139 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH1COMSEN BIT(11)

channel 1 output compare shadow enable

Definition at line 140 of file gd32f10x_timer.h.

#define TIMER_CHCTL0_CH1MS BITS(8,9)

channel 1 mode selection

Definition at line 138 of file gd32f10x_timer.h.

#define TIMER_CHCTL1 ( timerx ) REG32((timerx) + 0x1CU)

TIMER channel control register 1

Definition at line 42 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7)

channel 2 input capture filter control

Definition at line 163 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3)

channel 2 input capture prescaler

Definition at line 162 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH2COMCEN BIT(7)

channel 2 output compare clear enable

Definition at line 155 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH2COMCTL BITS(4,6)

channel 2 output compare mode

Definition at line 154 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH2COMFEN BIT(2)

channel 2 output compare fast enable

Definition at line 152 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH2COMSEN BIT(3)

channel 2 output compare shadow enable

Definition at line 153 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH2MS BITS(0,1)

channel 2 mode selection

Definition at line 151 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15)

channel 3 input capture filter control

Definition at line 165 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11)

channel 3 input capture prescaler

Definition at line 164 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH3COMCEN BIT(15)

channel 3 output compare clear enable

Definition at line 160 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH3COMCTL BITS(12,14)

channel 3 output compare mode

Definition at line 159 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH3COMFEN BIT(10)

channel 3 output compare fast enable

Definition at line 157 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH3COMSEN BIT(11)

channel 3 output compare shadow enable

Definition at line 158 of file gd32f10x_timer.h.

#define TIMER_CHCTL1_CH3MS BITS(8,9)

channel 3 mode selection

Definition at line 156 of file gd32f10x_timer.h.

#define TIMER_CHCTL2 ( timerx ) REG32((timerx) + 0x20U)

TIMER channel control register 2

Definition at line 43 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH0EN BIT(0)

channel 0 enable

Definition at line 168 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH0NEN BIT(2)

channel 0 complementary output enable

Definition at line 170 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH0NP BIT(3)

channel 0 complementary output polarity

Definition at line 171 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH0P BIT(1)

channel 0 polarity

Definition at line 169 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH1EN BIT(4)

channel 1 enable

Definition at line 172 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH1NEN BIT(6)

channel 1 complementary output enable

Definition at line 174 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH1NP BIT(7)

channel 1 complementary output polarity

Definition at line 175 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH1P BIT(5)

channel 1 polarity

Definition at line 173 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH2EN BIT(8)

channel 2 enable

Definition at line 176 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH2NEN BIT(10)

channel 2 complementary output enable

Definition at line 178 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH2NP BIT(11)

channel 2 complementary output polarity

Definition at line 179 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH2P BIT(9)

channel 2 polarity

Definition at line 177 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH3EN BIT(12)

channel 3 enable

Definition at line 180 of file gd32f10x_timer.h.

#define TIMER_CHCTL2_CH3P BIT(13)

channel 3 polarity

Definition at line 181 of file gd32f10x_timer.h.

#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0)

clock division value is 1,fDTS=fTIMER_CK

Definition at line 386 of file gd32f10x_timer.h.

#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1)

clock division value is 2,fDTS= fTIMER_CK/2

Definition at line 387 of file gd32f10x_timer.h.

#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2)

clock division value is 4, fDTS= fTIMER_CK/4

Definition at line 388 of file gd32f10x_timer.h.

#define TIMER_CNT ( timerx ) REG32((timerx) + 0x24U)

TIMER counter register

Definition at line 44 of file gd32f10x_timer.h.

#define TIMER_CNT_CNT BITS(0,15)

16 bit timer counter

Definition at line 184 of file gd32f10x_timer.h.

#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3)

center-aligned and counting up/down assert mode

Definition at line 374 of file gd32f10x_timer.h.

#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1)

center-aligned and counting down assert mode

Definition at line 372 of file gd32f10x_timer.h.

#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2)

center-aligned and counting up assert mode

Definition at line 373 of file gd32f10x_timer.h.

#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U)

counter down direction

Definition at line 382 of file gd32f10x_timer.h.

#define TIMER_COUNTER_EDGE CTL0_CAM(0)

edge-aligned mode

Definition at line 371 of file gd32f10x_timer.h.

#define TIMER_COUNTER_UP ((uint16_t)0x0000U)

counter up direction

Definition at line 381 of file gd32f10x_timer.h.

#define TIMER_CREP ( timerx ) REG32((timerx) + 0x30U)

TIMER counter repetition register

Definition at line 47 of file gd32f10x_timer.h.

#define TIMER_CREP_CREP BITS(0,7)

counter repetition value

Definition at line 193 of file gd32f10x_timer.h.

#define TIMER_CTL0 ( timerx ) REG32((timerx) + 0x00U)

TIMER control register 0

Definition at line 35 of file gd32f10x_timer.h.

#define TIMER_CTL0_ARSE BIT(7)

auto-reload shadow enable

Definition at line 64 of file gd32f10x_timer.h.

#define TIMER_CTL0_CAM BITS(5,6)

center-aligned mode selection

Definition at line 63 of file gd32f10x_timer.h.

#define TIMER_CTL0_CEN BIT(0)

TIMER counter enable

Definition at line 58 of file gd32f10x_timer.h.

#define TIMER_CTL0_CKDIV BITS(8,9)

clock division

Definition at line 65 of file gd32f10x_timer.h.

#define TIMER_CTL0_DIR BIT(4)

timer counter direction

Definition at line 62 of file gd32f10x_timer.h.

#define TIMER_CTL0_SPM BIT(3)

single pulse mode

Definition at line 61 of file gd32f10x_timer.h.

#define TIMER_CTL0_UPDIS BIT(1)

update disable

Definition at line 59 of file gd32f10x_timer.h.

#define TIMER_CTL0_UPS BIT(2)

update source

Definition at line 60 of file gd32f10x_timer.h.

#define TIMER_CTL1 ( timerx ) REG32((timerx) + 0x04U)

TIMER control register 1

Definition at line 36 of file gd32f10x_timer.h.

#define TIMER_CTL1_CCSE BIT(0)

commutation control shadow enable

Definition at line 68 of file gd32f10x_timer.h.

#define TIMER_CTL1_CCUC BIT(2)

commutation control shadow register update control

Definition at line 69 of file gd32f10x_timer.h.

#define TIMER_CTL1_DMAS BIT(3)

DMA request source selection

Definition at line 70 of file gd32f10x_timer.h.

#define TIMER_CTL1_ISO0 BIT(8)

idle state of channel 0 output

Definition at line 73 of file gd32f10x_timer.h.

#define TIMER_CTL1_ISO0N BIT(9)

idle state of channel 0 complementary output

Definition at line 74 of file gd32f10x_timer.h.

#define TIMER_CTL1_ISO1 BIT(10)

idle state of channel 1 output

Definition at line 75 of file gd32f10x_timer.h.

#define TIMER_CTL1_ISO1N BIT(11)

idle state of channel 1 complementary output

Definition at line 76 of file gd32f10x_timer.h.

#define TIMER_CTL1_ISO2 BIT(12)

idle state of channel 2 output

Definition at line 77 of file gd32f10x_timer.h.

#define TIMER_CTL1_ISO2N BIT(13)

idle state of channel 2 complementary output

Definition at line 78 of file gd32f10x_timer.h.

#define TIMER_CTL1_ISO3 BIT(14)

idle state of channel 3 output

Definition at line 79 of file gd32f10x_timer.h.

#define TIMER_CTL1_MMC BITS(4,6)

master mode control

Definition at line 71 of file gd32f10x_timer.h.

#define TIMER_CTL1_TI0S BIT(7)

channel 0 trigger input selection(hall mode selection)

Definition at line 72 of file gd32f10x_timer.h.

#define TIMER_DMA_CH0D ((uint16_t)0x0200U)

channel 0 DMA enable

Definition at line 304 of file gd32f10x_timer.h.

#define TIMER_DMA_CH1D ((uint16_t)0x0400U)

channel 1 DMA enable

Definition at line 305 of file gd32f10x_timer.h.

#define TIMER_DMA_CH2D ((uint16_t)0x0800U)

channel 2 DMA enable

Definition at line 306 of file gd32f10x_timer.h.

#define TIMER_DMA_CH3D ((uint16_t)0x1000U)

channel 3 DMA enable

Definition at line 307 of file gd32f10x_timer.h.

#define TIMER_DMA_CMTD ((uint16_t)0x2000U)

commutation DMA request enable

Definition at line 308 of file gd32f10x_timer.h.

#define TIMER_DMA_TRGD ((uint16_t)0x4000U)

trigger DMA enable

Definition at line 309 of file gd32f10x_timer.h.

#define TIMER_DMA_UPD ((uint16_t)0x0100U)

update DMA enable

Definition at line 303 of file gd32f10x_timer.h.

#define TIMER_DMACFG ( timerx ) REG32((timerx) + 0x48U)

TIMER DMA configuration register

Definition at line 53 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA BITS(0,4)

DMA transfer access start address

Definition at line 218 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11)

DMA transfer address is TIMER_CAR

Definition at line 328 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17)

DMA transfer address is TIMER_CCHP

Definition at line 334 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13)

DMA transfer address is TIMER_CH0CV

Definition at line 330 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14)

DMA transfer address is TIMER_CH1CV

Definition at line 331 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15)

DMA transfer address is TIMER_CH2CV

Definition at line 332 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16)

DMA transfer address is TIMER_CH3CV

Definition at line 333 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6)

DMA transfer address is TIMER_CHCTL0

Definition at line 323 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7)

DMA transfer address is TIMER_CHCTL1

Definition at line 324 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8)

DMA transfer address is TIMER_CHCTL2

Definition at line 325 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9)

DMA transfer address is TIMER_CNT

Definition at line 326 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12)

DMA transfer address is TIMER_CREP

Definition at line 329 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0)

DMA transfer address is TIMER_CTL0

Definition at line 317 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1)

DMA transfer address is TIMER_CTL1

Definition at line 318 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18)

DMA transfer address is TIMER_DMACFG

Definition at line 335 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3)

DMA transfer address is TIMER_DMAINTEN

Definition at line 320 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19)

DMA transfer address is TIMER_DMATB

Definition at line 336 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4)

DMA transfer address is TIMER_INTF

Definition at line 321 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10)

DMA transfer address is TIMER_PSC

Definition at line 327 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2)

DMA transfer address is TIMER_SMCFG

Definition at line 319 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5)

DMA transfer address is TIMER_SWEVG

Definition at line 322 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC BITS(8,12)

DMA transfer count

Definition at line 219 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9)

DMA transfer 10 times

Definition at line 349 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10)

DMA transfer 11 times

Definition at line 350 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11)

DMA transfer 12 times

Definition at line 351 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12)

DMA transfer 13 times

Definition at line 352 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13)

DMA transfer 14 times

Definition at line 353 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14)

DMA transfer 15 times

Definition at line 354 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15)

DMA transfer 16 times

Definition at line 355 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16)

DMA transfer 17 times

Definition at line 356 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17)

DMA transfer 18 times

Definition at line 357 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0)

DMA transfer 1 time

Definition at line 340 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1)

DMA transfer 2 times

Definition at line 341 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2)

DMA transfer 3 times

Definition at line 342 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3)

DMA transfer 4 times

Definition at line 343 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4)

DMA transfer 5 times

Definition at line 344 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5)

DMA transfer 6 times

Definition at line 345 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6)

DMA transfer 7 times

Definition at line 346 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7)

DMA transfer 8 times

Definition at line 347 of file gd32f10x_timer.h.

#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8)

DMA transfer 9 times

Definition at line 348 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN ( timerx ) REG32((timerx) + 0x0CU)

TIMER DMA and interrupt enable register

Definition at line 38 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_BRKIE BIT(7)

break interrupt enable

Definition at line 98 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CH0DEN BIT(9)

channel 0 DMA request enable

Definition at line 100 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CH0IE BIT(1)

channel 0 interrupt enable

Definition at line 92 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CH1DEN BIT(10)

channel 1 DMA request enable

Definition at line 101 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CH1IE BIT(2)

channel 1 interrupt enable

Definition at line 93 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CH2DEN BIT(11)

channel 2 DMA request enable

Definition at line 102 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CH2IE BIT(3)

channel 2 interrupt enable

Definition at line 94 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CH3DEN BIT(12)

channel 3 DMA request enable

Definition at line 103 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CH3IE BIT(4)

channel 3 interrupt enable

Definition at line 95 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CMTDEN BIT(13)

channel control update DMA request enable

Definition at line 104 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_CMTIE BIT(5)

commutation DMA request enable

Definition at line 96 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_TRGDEN BIT(14)

trigger DMA request enable

Definition at line 105 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_TRGIE BIT(6)

trigger interrupt enable

Definition at line 97 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_UPDEN BIT(8)

update DMA request enable

Definition at line 99 of file gd32f10x_timer.h.

#define TIMER_DMAINTEN_UPIE BIT(0)

update interrupt enable

Definition at line 91 of file gd32f10x_timer.h.

#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U)

DMA request of channel y is sent when channel y event occurs

Definition at line 313 of file gd32f10x_timer.h.

#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U)

DMA request of channel y is sent when update event occurs

Definition at line 312 of file gd32f10x_timer.h.

#define TIMER_DMATB ( timerx ) REG32((timerx) + 0x4CU)

TIMER DMA transfer buffer register

Definition at line 54 of file gd32f10x_timer.h.

#define TIMER_DMATB_DMATB BITS(0,15)

DMA transfer buffer address

Definition at line 222 of file gd32f10x_timer.h.

#define TIMER_ENCODER_MODE0 SMCFG_SMC(1)

encoder mode 0

Definition at line 522 of file gd32f10x_timer.h.

#define TIMER_ENCODER_MODE1 SMCFG_SMC(2)

encoder mode 1

Definition at line 523 of file gd32f10x_timer.h.

#define TIMER_ENCODER_MODE2 SMCFG_SMC(3)

encoder mode 2

Definition at line 524 of file gd32f10x_timer.h.

#define TIMER_ETP_FALLING TIMER_SMCFG_ETP

active low or falling edge active

Definition at line 542 of file gd32f10x_timer.h.

#define TIMER_ETP_RISING ((uint32_t)0x00000000U)

active high or rising edge active

Definition at line 543 of file gd32f10x_timer.h.

#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U)

break event generation

Definition at line 367 of file gd32f10x_timer.h.

#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U)

channel 0 capture or compare event generation

Definition at line 361 of file gd32f10x_timer.h.

#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U)

channel 1 capture or compare event generation

Definition at line 362 of file gd32f10x_timer.h.

#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U)

channel 2 capture or compare event generation

Definition at line 363 of file gd32f10x_timer.h.

#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U)

channel 3 capture or compare event generation

Definition at line 364 of file gd32f10x_timer.h.

#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U)

channel commutation event generation

Definition at line 365 of file gd32f10x_timer.h.

#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U)

trigger event generation

Definition at line 366 of file gd32f10x_timer.h.

#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U)

update event generation

Definition at line 360 of file gd32f10x_timer.h.

#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1)

divided by 2

Definition at line 537 of file gd32f10x_timer.h.

#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2)

divided by 4

Definition at line 538 of file gd32f10x_timer.h.

#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3)

divided by 8

Definition at line 539 of file gd32f10x_timer.h.

#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0)

no divided

Definition at line 536 of file gd32f10x_timer.h.

#define TIMER_FLAG_BRK TIMER_INTF_BRKIF

break flag

Definition at line 286 of file gd32f10x_timer.h.

#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF

channel 0 flag

Definition at line 280 of file gd32f10x_timer.h.

#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF

channel 0 overcapture flag

Definition at line 287 of file gd32f10x_timer.h.

#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF

channel 1 flag

Definition at line 281 of file gd32f10x_timer.h.

#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF

channel 1 overcapture flag

Definition at line 288 of file gd32f10x_timer.h.

#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF

channel 2 flag

Definition at line 282 of file gd32f10x_timer.h.

#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF

channel 2 overcapture flag

Definition at line 289 of file gd32f10x_timer.h.

#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF

channel 3 flag

Definition at line 283 of file gd32f10x_timer.h.

#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF

channel 3 overcapture flag

Definition at line 290 of file gd32f10x_timer.h.

#define TIMER_FLAG_CMT TIMER_INTF_CMTIF

channel commutation flag

Definition at line 284 of file gd32f10x_timer.h.

#define TIMER_FLAG_TRG TIMER_INTF_TRGIF

trigger flag

Definition at line 285 of file gd32f10x_timer.h.

#define TIMER_FLAG_UP TIMER_INTF_UPIF

update flag

Definition at line 279 of file gd32f10x_timer.h.

#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U)

TIMER hall sensor mode disable

Definition at line 547 of file gd32f10x_timer.h.

#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U)

TIMER hall sensor mode enable

Definition at line 546 of file gd32f10x_timer.h.

#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU)

input capture both edge

Definition at line 484 of file gd32f10x_timer.h.

#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U)

input capture falling edge

Definition at line 483 of file gd32f10x_timer.h.

#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U)

input capture rising edge

Definition at line 482 of file gd32f10x_timer.h.

#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U)

no prescaler

Definition at line 492 of file gd32f10x_timer.h.

#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U)

divided by 2

Definition at line 493 of file gd32f10x_timer.h.

#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U)

divided by 4

Definition at line 494 of file gd32f10x_timer.h.

#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU)

divided by 8

Definition at line 495 of file gd32f10x_timer.h.

#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U)

channel y is configured as input and icy is mapped on CIy

Definition at line 487 of file gd32f10x_timer.h.

#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U)

channel y is configured as input and icy is mapped on opposite input

Definition at line 488 of file gd32f10x_timer.h.

#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U)

channel y is configured as input and icy is mapped on ITS

Definition at line 489 of file gd32f10x_timer.h.

#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE

break interrupt

Definition at line 276 of file gd32f10x_timer.h.

#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE

channel 0 interrupt

Definition at line 270 of file gd32f10x_timer.h.

#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE

channel 1 interrupt

Definition at line 271 of file gd32f10x_timer.h.

#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE

channel 2 interrupt

Definition at line 272 of file gd32f10x_timer.h.

#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE

channel 3 interrupt

Definition at line 273 of file gd32f10x_timer.h.

#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE

channel commutation interrupt flag

Definition at line 274 of file gd32f10x_timer.h.

#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF

break interrupt flag

Definition at line 300 of file gd32f10x_timer.h.

#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF

channel 0 interrupt flag

Definition at line 294 of file gd32f10x_timer.h.

#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF

channel 1 interrupt flag

Definition at line 295 of file gd32f10x_timer.h.

#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF

channel 2 interrupt flag

Definition at line 296 of file gd32f10x_timer.h.

#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF

channel 3 interrupt flag

Definition at line 297 of file gd32f10x_timer.h.

#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF

channel commutation interrupt flag

Definition at line 298 of file gd32f10x_timer.h.

#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF

trigger interrupt flag

Definition at line 299 of file gd32f10x_timer.h.

#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF

update interrupt flag

Definition at line 293 of file gd32f10x_timer.h.

#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE

trigger interrupt

Definition at line 275 of file gd32f10x_timer.h.

#define TIMER_INT_UP TIMER_DMAINTEN_UPIE

update interrupt

Definition at line 269 of file gd32f10x_timer.h.

#define TIMER_INTF ( timerx ) REG32((timerx) + 0x10U)

TIMER interrupt flag register

Definition at line 39 of file gd32f10x_timer.h.

#define TIMER_INTF_BRKIF BIT(7)

break interrupt flag

Definition at line 115 of file gd32f10x_timer.h.

#define TIMER_INTF_CH0IF BIT(1)

channel 0 interrupt flag

Definition at line 109 of file gd32f10x_timer.h.

#define TIMER_INTF_CH0OF BIT(9)

channel 0 overcapture flag

Definition at line 116 of file gd32f10x_timer.h.

#define TIMER_INTF_CH1IF BIT(2)

channel 1 interrupt flag

Definition at line 110 of file gd32f10x_timer.h.

#define TIMER_INTF_CH1OF BIT(10)

channel 1 overcapture flag

Definition at line 117 of file gd32f10x_timer.h.

#define TIMER_INTF_CH2IF BIT(3)

channel 2 interrupt flag

Definition at line 111 of file gd32f10x_timer.h.

#define TIMER_INTF_CH2OF BIT(11)

channel 2 overcapture flag

Definition at line 118 of file gd32f10x_timer.h.

#define TIMER_INTF_CH3IF BIT(4)

channel 3 interrupt flag

Definition at line 112 of file gd32f10x_timer.h.

#define TIMER_INTF_CH3OF BIT(12)

channel 3 overcapture flag

Definition at line 119 of file gd32f10x_timer.h.

#define TIMER_INTF_CMTIF BIT(5)

channel commutation interrupt flag

Definition at line 113 of file gd32f10x_timer.h.

#define TIMER_INTF_TRGIF BIT(6)

trigger interrupt flag

Definition at line 114 of file gd32f10x_timer.h.

#define TIMER_INTF_UPIF BIT(0)

update interrupt flag

Definition at line 108 of file gd32f10x_timer.h.

#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U)

when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled

Definition at line 404 of file gd32f10x_timer.h.

#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U)

when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits

Definition at line 403 of file gd32f10x_timer.h.

#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U)

master slave mode disable

Definition at line 532 of file gd32f10x_timer.h.

#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U)

master slave mode enable

Definition at line 531 of file gd32f10x_timer.h.

#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U)

channel output clear function disable

Definition at line 475 of file gd32f10x_timer.h.

#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U)

channel output clear function enable

Definition at line 474 of file gd32f10x_timer.h.

#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000)

channel output fast function disable

Definition at line 471 of file gd32f10x_timer.h.

#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004)

channel output fast function enable

Definition at line 470 of file gd32f10x_timer.h.

#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100)

idle state of channel output is high

Definition at line 448 of file gd32f10x_timer.h.

#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000)

idle state of channel output is low

Definition at line 449 of file gd32f10x_timer.h.

#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U)

active mode

Definition at line 457 of file gd32f10x_timer.h.

#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U)

force high mode

Definition at line 461 of file gd32f10x_timer.h.

#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U)

inactive mode

Definition at line 458 of file gd32f10x_timer.h.

#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U)

force low mode

Definition at line 460 of file gd32f10x_timer.h.

#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U)

PWM0 mode

Definition at line 462 of file gd32f10x_timer.h.

#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U)

PWM1 mode

Definition at line 463 of file gd32f10x_timer.h.

#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U)

timing mode

Definition at line 456 of file gd32f10x_timer.h.

#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U)

toggle mode

Definition at line 459 of file gd32f10x_timer.h.

#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U)

channel output polarity is high

Definition at line 440 of file gd32f10x_timer.h.

#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U)

channel output polarity is low

Definition at line 441 of file gd32f10x_timer.h.

#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U)

channel output shadow state disable

Definition at line 467 of file gd32f10x_timer.h.

#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U)

channel output shadow state enable

Definition at line 466 of file gd32f10x_timer.h.

#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U)

idle state of channel complementary output is high

Definition at line 452 of file gd32f10x_timer.h.

#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U)

idle state of channel complementary output is low

Definition at line 453 of file gd32f10x_timer.h.

#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U)

channel complementary output polarity is high

Definition at line 444 of file gd32f10x_timer.h.

#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U)

channel complementary output polarity is low

Definition at line 445 of file gd32f10x_timer.h.

#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U)

output automatic disable

Definition at line 412 of file gd32f10x_timer.h.

#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U)

output automatic enable

Definition at line 411 of file gd32f10x_timer.h.

#define TIMER_PSC ( timerx ) REG32((timerx) + 0x28U)

TIMER prescaler register

Definition at line 45 of file gd32f10x_timer.h.

#define TIMER_PSC_PSC BITS(0,15)

prescaler value of the counter clock

Definition at line 187 of file gd32f10x_timer.h.

#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U)

the prescaler is loaded right now

Definition at line 377 of file gd32f10x_timer.h.

#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U)

the prescaler is loaded at the next update event

Definition at line 378 of file gd32f10x_timer.h.

#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U)

when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled

Definition at line 400 of file gd32f10x_timer.h.

#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U)

when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits

Definition at line 399 of file gd32f10x_timer.h.

#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0)

slave mode disable

Definition at line 521 of file gd32f10x_timer.h.

#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6)

event mode

Definition at line 527 of file gd32f10x_timer.h.

#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7)

external clock mode 0

Definition at line 528 of file gd32f10x_timer.h.

#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5)

pause mode

Definition at line 526 of file gd32f10x_timer.h.

#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4)

restart mode

Definition at line 525 of file gd32f10x_timer.h.

#define TIMER_SMCFG ( timerx ) REG32((timerx) + 0x08U)

TIMER slave mode configuration register

Definition at line 37 of file gd32f10x_timer.h.

#define TIMER_SMCFG_ETFC BITS(8,11)

external trigger filter control

Definition at line 85 of file gd32f10x_timer.h.

#define TIMER_SMCFG_ETP BIT(15)

external trigger polarity

Definition at line 88 of file gd32f10x_timer.h.

#define TIMER_SMCFG_ETPSC BITS(12,13)

external trigger prescaler

Definition at line 86 of file gd32f10x_timer.h.

#define TIMER_SMCFG_MSM BIT(7)

master-slave mode

Definition at line 84 of file gd32f10x_timer.h.

#define TIMER_SMCFG_SMC BITS(0,2)

slave mode control

Definition at line 82 of file gd32f10x_timer.h.

#define TIMER_SMCFG_SMC1 BIT(14)

part of SMC for enable external clock mode 1

Definition at line 87 of file gd32f10x_timer.h.

#define TIMER_SMCFG_TRGS BITS(4,6)

trigger selection

Definition at line 83 of file gd32f10x_timer.h.

#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4)

TI0 Edge Detector

Definition at line 503 of file gd32f10x_timer.h.

#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5)

filtered TIMER input 0

Definition at line 504 of file gd32f10x_timer.h.

#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6)

filtered TIMER input 1

Definition at line 505 of file gd32f10x_timer.h.

#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7)

external trigger

Definition at line 506 of file gd32f10x_timer.h.

#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0)

internal trigger 0

Definition at line 499 of file gd32f10x_timer.h.

#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1)

internal trigger 1

Definition at line 500 of file gd32f10x_timer.h.

#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2)

internal trigger 2

Definition at line 501 of file gd32f10x_timer.h.

#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3)

internal trigger 3

Definition at line 502 of file gd32f10x_timer.h.

#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U)

repetitive pulse mode

Definition at line 392 of file gd32f10x_timer.h.

#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U)

single pulse mode

Definition at line 391 of file gd32f10x_timer.h.

#define TIMER_SWEVG ( timerx ) REG32((timerx) + 0x14U)

TIMER software event generation register

Definition at line 40 of file gd32f10x_timer.h.

#define TIMER_SWEVG_BRKG BIT(7)

break event generation

Definition at line 129 of file gd32f10x_timer.h.

#define TIMER_SWEVG_CH0G BIT(1)

channel 0 capture or compare event generation

Definition at line 123 of file gd32f10x_timer.h.

#define TIMER_SWEVG_CH1G BIT(2)

channel 1 capture or compare event generation

Definition at line 124 of file gd32f10x_timer.h.

#define TIMER_SWEVG_CH2G BIT(3)

channel 2 capture or compare event generation

Definition at line 125 of file gd32f10x_timer.h.

#define TIMER_SWEVG_CH3G BIT(4)

channel 3 capture or compare event generation

Definition at line 126 of file gd32f10x_timer.h.

#define TIMER_SWEVG_CMTG BIT(5)

channel commutation event generation

Definition at line 127 of file gd32f10x_timer.h.

#define TIMER_SWEVG_TRGG BIT(6)

trigger event generation

Definition at line 128 of file gd32f10x_timer.h.

#define TIMER_SWEVG_UPG BIT(0)

update event generate

Definition at line 122 of file gd32f10x_timer.h.

#define TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3)

a capture or a compare match occurred in channal0 as trigger output TRGO

Definition at line 513 of file gd32f10x_timer.h.

#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1)

the counter enable signal TIMER_CTL0_CEN as trigger output

Definition at line 511 of file gd32f10x_timer.h.

#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4)

O0CPRE as trigger output

Definition at line 514 of file gd32f10x_timer.h.

#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5)

O1CPRE as trigger output

Definition at line 515 of file gd32f10x_timer.h.

#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6)

O2CPRE as trigger output

Definition at line 516 of file gd32f10x_timer.h.

#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7)

O3CPRE as trigger output

Definition at line 517 of file gd32f10x_timer.h.

#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0)

the UPG bit as trigger output

Definition at line 510 of file gd32f10x_timer.h.

#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2)

update event as trigger output

Definition at line 512 of file gd32f10x_timer.h.

#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U)

update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger

Definition at line 396 of file gd32f10x_timer.h.

#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U)

update generate only by counter overflow/underflow

Definition at line 395 of file gd32f10x_timer.h.

#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U)

the shadow registers update by when CMTG bit is set

Definition at line 478 of file gd32f10x_timer.h.

#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U)

the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs

Definition at line 479 of file gd32f10x_timer.h.

Function Documentation

void timer_auto_reload_shadow_disable ( uint32_t timer_periph )

disable the auto reload shadow function

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 185 of file gd32f10x_timer.c.

186 {
187 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
188 }
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f10x_timer.h:64
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_auto_reload_shadow_enable ( uint32_t timer_periph )

enable the auto reload shadow function

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 174 of file gd32f10x_timer.c.

175 {
176 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
177 }
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f10x_timer.h:64
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_automatic_output_disable ( uint32_t timer_periph )

disable TIMER output automatic function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 684 of file gd32f10x_timer.c.

685 {
686 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
687 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f10x_timer.h:214
void timer_automatic_output_enable ( uint32_t timer_periph )

enable TIMER output automatic function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 673 of file gd32f10x_timer.c.

674 {
675 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
676 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f10x_timer.h:214
void timer_autoreload_value_config | ( | uint32_t | timer_periph,
 |  | uint32_t | autoreload
 | ) |  |

configure TIMER autoreload register value

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] | autoreload | the counter auto-reload value
[out] | none
Return values
none

Definition at line 289 of file gd32f10x_timer.c.

290 {
291 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
292 }
TIMER_CAR
#define TIMER_CAR(timerx)
Definition: gd32f10x_timer.h:46
void timer_break_config | ( | uint32_t | timer_periph,
 |  | timer_break_parameter_struct * | breakpara
 | ) |  |

configure TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] | breakpara | TIMER break parameter struct runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE deadtime: 0~255 breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
[out] | none
Return values
none

Definition at line 634 of file gd32f10x_timer.c.

635 {
636 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
637 ((uint32_t)(breakpara->ideloffstate)) |
638 ((uint32_t)(breakpara->deadtime)) |
639 ((uint32_t)(breakpara->breakpolarity)) |
640 ((uint32_t)(breakpara->outputautostate)) |
641 ((uint32_t)(breakpara->protectmode)) |
642 ((uint32_t)(breakpara->breakstate))) ;
643 }
timer_break_parameter_struct::deadtime
uint16_t deadtime
Definition: gd32f10x_timer.h:241
timer_break_parameter_struct::ideloffstate
uint32_t ideloffstate
Definition: gd32f10x_timer.h:240
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
timer_break_parameter_struct::outputautostate
uint16_t outputautostate
Definition: gd32f10x_timer.h:243
timer_break_parameter_struct::runoffstate
uint16_t runoffstate
Definition: gd32f10x_timer.h:239
timer_break_parameter_struct::breakpolarity
uint16_t breakpolarity
Definition: gd32f10x_timer.h:242
timer_break_parameter_struct::breakstate
uint16_t breakstate
Definition: gd32f10x_timer.h:245
timer_break_parameter_struct::protectmode
uint16_t protectmode
Definition: gd32f10x_timer.h:244
void timer_break_disable ( uint32_t timer_periph )

disable TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 662 of file gd32f10x_timer.c.

663 {
664 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
665 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_BRKEN
#define TIMER_CCHP_BRKEN
Definition: gd32f10x_timer.h:212
void timer_break_enable ( uint32_t timer_periph )

enable TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 651 of file gd32f10x_timer.c.

652 {
653 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
654 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_BRKEN
#define TIMER_CCHP_BRKEN
Definition: gd32f10x_timer.h:212
uint32_t timer_channel_capture_value_register_read | ( | uint32_t | timer_periph,
 |  | uint16_t | channel
 | ) |  |

read TIMER channel capture compare register value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[out] | none
Return values
channel capture compare register value

Definition at line 1398 of file gd32f10x_timer.c.

1399 {
1400 uint32_t count_value = 0U;
1401
1402 switch(channel){
1403 case TIMER_CH_0:
1404 count_value = TIMER_CH0CV(timer_periph);
1405 break;
1406 case TIMER_CH_1:
1407 count_value = TIMER_CH1CV(timer_periph);
1408 break;
1409 case TIMER_CH_2:
1410 count_value = TIMER_CH2CV(timer_periph);
1411 break;
1412 case TIMER_CH_3:
1413 count_value = TIMER_CH3CV(timer_periph);
1414 break;
1415 default:
1416 break;
1417 }
1418 return (count_value);
1419 }
TIMER_CH1CV
#define TIMER_CH1CV(timerx)
Definition: gd32f10x_timer.h:49
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CH2CV
#define TIMER_CH2CV(timerx)
Definition: gd32f10x_timer.h:50
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f10x_timer.h:51
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f10x_timer.h:48
void timer_channel_complementary_output_polarity_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocnpolarity
 | ) |  |

configure TIMER channel complementary output polarity

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
[in] ocnpolarity channel complementary output polarity
  • TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
  • TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
[out] | none
Return values
none

Definition at line 1139 of file gd32f10x_timer.c.

1140 {
1141 switch(channel){
1142 /* configure TIMER_CH_0 */
1143 case TIMER_CH_0:
1144 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1145 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1146 break;
1147 /* configure TIMER_CH_1 */
1148 case TIMER_CH_1:
1149 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1150 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1151 break;
1152 /* configure TIMER_CH_2 */
1153 case TIMER_CH_2:
1154 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1155 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1156 break;
1157 default:
1158 break;
1159 }
1160 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f10x_timer.h:179
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_complementary_output_state_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocnstate
 | ) |  |

configure TIMER channel complementary output enable state

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] channel
  • TIMER_CH_0: TIMER channel0
  • TIMER_CH_1: TIMER channel1
  • TIMER_CH_2: TIMER channel2
[in] ocnstate TIMER channel complementary output enable state
  • TIMER_CCXN_ENABLE: channel complementary enable
  • TIMER_CCXN_DISABLE: channel complementary disable
[out] | none
Return values
none

Definition at line 1217 of file gd32f10x_timer.c.

1218 {
1219 switch(channel){
1220 /* configure TIMER_CH_0 */
1221 case TIMER_CH_0:
1222 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1223 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1224 break;
1225 /* configure TIMER_CH_1 */
1226 case TIMER_CH_1:
1227 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1228 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1229 break;
1230 /* configure TIMER_CH_2 */
1231 case TIMER_CH_2:
1232 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1233 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1234 break;
1235 default:
1236 break;
1237 }
1238 }
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f10x_timer.h:170
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f10x_timer.h:178
TIMER_CHCTL2_CH1NEN
#define TIMER_CHCTL2_CH1NEN
Definition: gd32f10x_timer.h:174
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_control_shadow_config | ( | uint32_t | timer_periph,
 |  | ControlStatus | newvalue
 | ) |  |

channel capture/compare control shadow register enable

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 712 of file gd32f10x_timer.c.

713 {
714 if(ENABLE == newvalue){
715 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
716 }else{
717 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
718 }
719 }
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_CTL1_CCSE
#define TIMER_CTL1_CCSE
Definition: gd32f10x_timer.h:68
void timer_channel_control_shadow_update_config | ( | uint32_t | timer_periph,
 |  | uint8_t | ccuctl
 | ) |  |

configure TIMER channel control shadow register update control

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] ccuctl channel control shadow register update control
  • TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
  • TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
[out] | none
Return values
none

Definition at line 730 of file gd32f10x_timer.c.

731 {
732 if(TIMER_UPDATECTL_CCU == ccuctl){
733 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
734 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
735 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
736 }else{
737 }
738 }
TIMER_UPDATECTL_CCU
#define TIMER_UPDATECTL_CCU
Definition: gd32f10x_timer.h:478
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_CTL1_CCUC
#define TIMER_CTL1_CCUC
Definition: gd32f10x_timer.h:69
TIMER_UPDATECTL_CCUTRI
#define TIMER_UPDATECTL_CCUTRI
Definition: gd32f10x_timer.h:479
void timer_channel_dma_request_source_select | ( | uint32_t | timer_periph,
 |  | uint8_t | dma_request
 | ) |  |

channel DMA request source selection

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] dma_request channel DMA request source selection
  • TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
  • TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
[out] | none
Return values
none

Definition at line 555 of file gd32f10x_timer.c.

556 {
557 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
558 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
559 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
560 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
561 }else{
562 }
563 }
TIMER_CTL1_DMAS
#define TIMER_CTL1_DMAS
Definition: gd32f10x_timer.h:70
TIMER_DMAREQUEST_CHANNELEVENT
#define TIMER_DMAREQUEST_CHANNELEVENT
Definition: gd32f10x_timer.h:313
TIMER_DMAREQUEST_UPDATEEVENT
#define TIMER_DMAREQUEST_UPDATEEVENT
Definition: gd32f10x_timer.h:312
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
void timer_channel_input_capture_prescaler_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | prescaler
 | ) |  |

configure TIMER channel input capture prescaler value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] prescaler channel input capture prescaler value
  • TIMER_IC_PSC_DIV1: no prescaler
  • TIMER_IC_PSC_DIV2: divided by 2
  • TIMER_IC_PSC_DIV4: divided by 4
  • TIMER_IC_PSC_DIV8: divided by 8
[out] | none
Return values
none

Definition at line 1359 of file gd32f10x_timer.c.

1360 {
1361 switch(channel){
1362 /* configure TIMER_CH_0 */
1363 case TIMER_CH_0:
1364 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1365 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1366 break;
1367 /* configure TIMER_CH_1 */
1368 case TIMER_CH_1:
1369 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1370 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1371 break;
1372 /* configure TIMER_CH_2 */
1373 case TIMER_CH_2:
1374 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1375 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1376 break;
1377 /* configure TIMER_CH_3 */
1378 case TIMER_CH_3:
1379 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1380 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1381 break;
1382 default:
1383 break;
1384 }
1385 }
TIMER_CHCTL0_CH0CAPPSC
#define TIMER_CHCTL0_CH0CAPPSC
Definition: gd32f10x_timer.h:144
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL1_CH3CAPPSC
#define TIMER_CHCTL1_CH3CAPPSC
Definition: gd32f10x_timer.h:164
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL0_CH1CAPPSC
#define TIMER_CHCTL0_CH1CAPPSC
Definition: gd32f10x_timer.h:146
TIMER_CHCTL1_CH2CAPPSC
#define TIMER_CHCTL1_CH2CAPPSC
Definition: gd32f10x_timer.h:162
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_output_clear_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | occlear
 | ) |  |

configure TIMER channel output clear function

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] channel
  • TIMER_CH_0: TIMER channel0
  • TIMER_CH_1: TIMER channel1
  • TIMER_CH_2: TIMER channel2
  • TIMER_CH_3: TIMER channel3
[in] occlear channel output clear function
  • TIMER_OC_CLEAR_ENABLE: channel output clear function enable
  • TIMER_OC_CLEAR_DISABLE: channel output clear function disable
[out] | none
Return values
none

Definition at line 1056 of file gd32f10x_timer.c.

1057 {
1058 switch(channel){
1059 /* configure TIMER_CH_0 */
1060 case TIMER_CH_0:
1061 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1062 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1063 break;
1064 /* configure TIMER_CH_1 */
1065 case TIMER_CH_1:
1066 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1067 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1068 break;
1069 /* configure TIMER_CH_2 */
1070 case TIMER_CH_2:
1071 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1072 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1073 break;
1074 /* configure TIMER_CH_3 */
1075 case TIMER_CH_3:
1076 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1077 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1078 break;
1079 default:
1080 break;
1081 }
1082 }
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL0_CH1COMCEN
#define TIMER_CHCTL0_CH1COMCEN
Definition: gd32f10x_timer.h:142
TIMER_CHCTL1_CH2COMCEN
#define TIMER_CHCTL1_CH2COMCEN
Definition: gd32f10x_timer.h:155
TIMER_CHCTL1_CH3COMCEN
#define TIMER_CHCTL1_CH3COMCEN
Definition: gd32f10x_timer.h:160
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL0_CH0COMCEN
#define TIMER_CHCTL0_CH0COMCEN
Definition: gd32f10x_timer.h:137
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_output_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_oc_parameter_struct * | ocpara
 | ) |  |

configure TIMER channel output function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7))
[in] | ocpara | TIMER channeln output parameter struct outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
[out] | none
Return values
none

Definition at line 758 of file gd32f10x_timer.c.

759 {
760 switch(channel){
761 /* configure TIMER_CH_0 */
762 case TIMER_CH_0:
763 /* reset the CH0EN bit */
764 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
765 /* set the CH0EN bit */
766 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
767 /* reset the CH0P bit */
768 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
769 /* set the CH0P bit */
770 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
771
772 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
773 /* reset the CH0NEN bit */
774 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
775 /* set the CH0NEN bit */
776 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
777 /* reset the CH0NP bit */
778 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
779 /* set the CH0NP bit */
780 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
781 /* reset the ISO0 bit */
782 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
783 /* set the ISO0 bit */
784 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
785 /* reset the ISO0N bit */
786 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
787 /* set the ISO0N bit */
788 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
789 }
790 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
791 break;
792 /* configure TIMER_CH_1 */
793 case TIMER_CH_1:
794 /* reset the CH1EN bit */
795 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
796 /* set the CH1EN bit */
797 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 4U);
798 /* reset the CH1P bit */
799 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
800 /* set the CH1P bit */
801 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U);
802
803 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
804 /* reset the CH1NEN bit */
805 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
806 /* set the CH1NEN bit */
807 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U);
808 /* reset the CH1NP bit */
809 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
810 /* set the CH1NP bit */
811 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U);
812 /* reset the ISO1 bit */
813 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
814 /* set the ISO1 bit */
815 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U);
816 /* reset the ISO1N bit */
817 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
818 /* set the ISO1N bit */
819 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U);
820 }
821 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
822 break;
823 /* configure TIMER_CH_2 */
824 case TIMER_CH_2:
825 /* reset the CH2EN bit */
826 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
827 /* set the CH2EN bit */
828 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 8U);
829 /* reset the CH2P bit */
830 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
831 /* set the CH2P bit */
832 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U);
833
834 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
835 /* reset the CH2NEN bit */
836 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
837 /* set the CH2NEN bit */
838 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U);
839 /* reset the CH2NP bit */
840 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
841 /* set the CH2NP bit */
842 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U);
843 /* reset the ISO2 bit */
844 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
845 /* set the ISO2 bit */
846 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U);
847 /* reset the ISO2N bit */
848 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
849 /* set the ISO2N bit */
850 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U);
851 }
852 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
853 break;
854 /* configure TIMER_CH_3 */
855 case TIMER_CH_3:
856 /* reset the CH3EN bit */
857 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
858 /* set the CH3EN bit */
859 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 12U);
860 /* reset the CH3P bit */
861 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
862 /* set the CH3P bit */
863 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U);
864
865 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
866 /* reset the ISO3 bit */
867 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
868 /* set the ISO3 bit */
869 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U);
870 }
871 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
872 break;
873 default:
874 break;
875 }
876 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CTL1_ISO2
#define TIMER_CTL1_ISO2
Definition: gd32f10x_timer.h:77
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f10x_timer.h:170
TIMER_CTL1_ISO3
#define TIMER_CTL1_ISO3
Definition: gd32f10x_timer.h:79
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
TIMER7
#define TIMER7
Definition: gd32f10x_timer.h:26
timer_oc_parameter_struct::ocnidlestate
uint16_t ocnidlestate
Definition: gd32f10x_timer.h:256
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f10x_timer.h:179
TIMER_CHCTL1_CH2MS
#define TIMER_CHCTL1_CH2MS
Definition: gd32f10x_timer.h:151
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CTL1_ISO0
#define TIMER_CTL1_ISO0
Definition: gd32f10x_timer.h:73
timer_oc_parameter_struct::ocpolarity
uint16_t ocpolarity
Definition: gd32f10x_timer.h:253
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f10x_timer.h:180
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f10x_timer.h:178
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_CTL1_ISO2N
#define TIMER_CTL1_ISO2N
Definition: gd32f10x_timer.h:78
TIMER_CHCTL2_CH1NEN
#define TIMER_CHCTL2_CH1NEN
Definition: gd32f10x_timer.h:174
TIMER0
#define TIMER0
Definition: gd32f10x_timer.h:19
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f10x_timer.h:176
TIMER_CTL1_ISO0N
#define TIMER_CTL1_ISO0N
Definition: gd32f10x_timer.h:74
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CTL1_ISO1N
#define TIMER_CTL1_ISO1N
Definition: gd32f10x_timer.h:76
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f10x_timer.h:177
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
timer_oc_parameter_struct::outputstate
uint32_t outputstate
Definition: gd32f10x_timer.h:251
timer_oc_parameter_struct::ocidlestate
uint16_t ocidlestate
Definition: gd32f10x_timer.h:255
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
TIMER_CTL1_ISO1
#define TIMER_CTL1_ISO1
Definition: gd32f10x_timer.h:75
timer_oc_parameter_struct::ocnpolarity
uint16_t ocnpolarity
Definition: gd32f10x_timer.h:254
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f10x_timer.h:181
timer_oc_parameter_struct::outputnstate
uint16_t outputnstate
Definition: gd32f10x_timer.h:252
TIMER_CHCTL1_CH3MS
#define TIMER_CHCTL1_CH3MS
Definition: gd32f10x_timer.h:156
void timer_channel_output_fast_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocfast
 | ) |  |

configure TIMER channel output fast function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] ocfast channel output fast function
  • TIMER_OC_FAST_ENABLE: channel output fast function enable
  • TIMER_OC_FAST_DISABLE: channel output fast function disable
[out] | none
Return values
none

Definition at line 1014 of file gd32f10x_timer.c.

1015 {
1016 switch(channel){
1017 /* configure TIMER_CH_0 */
1018 case TIMER_CH_0:
1019 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
1020 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
1021 break;
1022 /* configure TIMER_CH_1 */
1023 case TIMER_CH_1:
1024 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
1025 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1026 break;
1027 /* configure TIMER_CH_2 */
1028 case TIMER_CH_2:
1029 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
1030 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
1031 break;
1032 /* configure TIMER_CH_3 */
1033 case TIMER_CH_3:
1034 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
1035 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1036 break;
1037 default:
1038 break;
1039 }
1040 }
TIMER_CHCTL0_CH1COMFEN
#define TIMER_CHCTL0_CH1COMFEN
Definition: gd32f10x_timer.h:139
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL1_CH3COMFEN
#define TIMER_CHCTL1_CH3COMFEN
Definition: gd32f10x_timer.h:157
TIMER_CHCTL0_CH0COMFEN
#define TIMER_CHCTL0_CH0COMFEN
Definition: gd32f10x_timer.h:134
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL1_CH2COMFEN
#define TIMER_CHCTL1_CH2COMFEN
Definition: gd32f10x_timer.h:152
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_output_mode_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocmode
 | ) |  |

configure TIMER channel output compare mode

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] ocmode channel output compare mode
  • TIMER_OC_MODE_TIMING: timing mode
  • TIMER_OC_MODE_ACTIVE: active mode
  • TIMER_OC_MODE_INACTIVE: inactive mode
  • TIMER_OC_MODE_TOGGLE: toggle mode
  • TIMER_OC_MODE_LOW: force low mode
  • TIMER_OC_MODE_HIGH: force high mode
  • TIMER_OC_MODE_PWM0: PWM0 mode
  • TIMER_OC_MODE_PWM1: PWM1 mode
[out] | none
Return values
none

Definition at line 898 of file gd32f10x_timer.c.

899 {
900 switch(channel){
901 /* configure TIMER_CH_0 */
902 case TIMER_CH_0:
903 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
904 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
905 break;
906 /* configure TIMER_CH_1 */
907 case TIMER_CH_1:
908 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
909 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U);
910 break;
911 /* configure TIMER_CH_2 */
912 case TIMER_CH_2:
913 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
914 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
915 break;
916 /* configure TIMER_CH_3 */
917 case TIMER_CH_3:
918 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
919 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U);
920 break;
921 default:
922 break;
923 }
924 }
TIMER_CHCTL0_CH0COMCTL
#define TIMER_CHCTL0_CH0COMCTL
Definition: gd32f10x_timer.h:136
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL1_CH2COMCTL
#define TIMER_CHCTL1_CH2COMCTL
Definition: gd32f10x_timer.h:154
TIMER_CHCTL0_CH1COMCTL
#define TIMER_CHCTL0_CH1COMCTL
Definition: gd32f10x_timer.h:141
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CHCTL1_CH3COMCTL
#define TIMER_CHCTL1_CH3COMCTL
Definition: gd32f10x_timer.h:159
void timer_channel_output_polarity_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocpolarity
 | ) |  |

configure TIMER channel output polarity

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] ocpolarity channel output polarity
  • TIMER_OC_POLARITY_HIGH: channel output polarity is high
  • TIMER_OC_POLARITY_LOW: channel output polarity is low
[out] | none
Return values
none

Definition at line 1098 of file gd32f10x_timer.c.

1099 {
1100 switch(channel){
1101 /* configure TIMER_CH_0 */
1102 case TIMER_CH_0:
1103 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1104 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1105 break;
1106 /* configure TIMER_CH_1 */
1107 case TIMER_CH_1:
1108 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1109 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1110 break;
1111 /* configure TIMER_CH_2 */
1112 case TIMER_CH_2:
1113 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1114 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1115 break;
1116 /* configure TIMER_CH_3 */
1117 case TIMER_CH_3:
1118 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1119 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1120 break;
1121 default:
1122 break;
1123 }
1124 }
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f10x_timer.h:177
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f10x_timer.h:181
void timer_channel_output_pulse_value_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint32_t | pulse
 | ) |  |

configure TIMER channel output pulse value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] | pulse | channel output pulse value
[out] | none
Return values
none

Definition at line 938 of file gd32f10x_timer.c.

939 {
940 switch(channel){
941 case TIMER_CH_0:
942 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
943 break;
944 case TIMER_CH_1:
945 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
946 break;
947 case TIMER_CH_2:
948 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
949 break;
950 case TIMER_CH_3:
951 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
952 break;
953 default:
954 break;
955 }
956 }
TIMER_CH1CV
#define TIMER_CH1CV(timerx)
Definition: gd32f10x_timer.h:49
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CH2CV
#define TIMER_CH2CV(timerx)
Definition: gd32f10x_timer.h:50
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f10x_timer.h:51
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f10x_timer.h:48
void timer_channel_output_shadow_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocshadow
 | ) |  |

configure TIMER channel output shadow function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] ocshadow channel output shadow state
  • TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
  • TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
[out] | none
Return values
none

Definition at line 972 of file gd32f10x_timer.c.

973 {
974 switch(channel){
975 /* configure TIMER_CH_0 */
976 case TIMER_CH_0:
977 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
978 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
979 break;
980 /* configure TIMER_CH_1 */
981 case TIMER_CH_1:
982 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
983 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
984 break;
985 /* configure TIMER_CH_2 */
986 case TIMER_CH_2:
987 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
988 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
989 break;
990 /* configure TIMER_CH_3 */
991 case TIMER_CH_3:
992 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
993 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
994 break;
995 default:
996 break;
997 }
998 }
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL1_CH2COMSEN
#define TIMER_CHCTL1_CH2COMSEN
Definition: gd32f10x_timer.h:153
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL0_CH0COMSEN
#define TIMER_CHCTL0_CH0COMSEN
Definition: gd32f10x_timer.h:135
TIMER_CHCTL1_CH3COMSEN
#define TIMER_CHCTL1_CH3COMSEN
Definition: gd32f10x_timer.h:158
TIMER_CHCTL0_CH1COMSEN
#define TIMER_CHCTL0_CH1COMSEN
Definition: gd32f10x_timer.h:140
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_output_state_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint32_t | state
 | ) |  |

configure TIMER channel enable state

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] state TIMER channel enable state
  • TIMER_CCX_ENABLE: channel enable
  • TIMER_CCX_DISABLE: channel disable
[out] | none
Return values
none

Definition at line 1176 of file gd32f10x_timer.c.

1177 {
1178 switch(channel){
1179 /* configure TIMER_CH_0 */
1180 case TIMER_CH_0:
1181 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1182 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1183 break;
1184 /* configure TIMER_CH_1 */
1185 case TIMER_CH_1:
1186 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1187 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1188 break;
1189 /* configure TIMER_CH_2 */
1190 case TIMER_CH_2:
1191 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1192 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1193 break;
1194 /* configure TIMER_CH_3 */
1195 case TIMER_CH_3:
1196 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1197 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1198 break;
1199 default:
1200 break;
1201 }
1202 }
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f10x_timer.h:180
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f10x_timer.h:176
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_counter_alignment | ( | uint32_t | timer_periph,
 |  | uint16_t | aligned
 | ) |  |

set TIMER counter alignment mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7..13)
[in] aligned
  • TIMER_COUNTER_EDGE: edge-aligned mode
  • TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
  • TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
  • TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
[out] | none
Return values
none

Definition at line 223 of file gd32f10x_timer.c.

224 {
225 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
226 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
227 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f10x_timer.h:63
void timer_counter_down_direction ( uint32_t timer_periph )

set TIMER counter down direction

Parameters
[in] | timer_periph | TIMERx(x=0..4,7..13)
[out] | none
Return values
none

Definition at line 246 of file gd32f10x_timer.c.

247 {
248 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
249 }
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f10x_timer.h:62
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
uint32_t timer_counter_read ( uint32_t timer_periph )

read TIMER counter value

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
counter value

Definition at line 312 of file gd32f10x_timer.c.

313 {
314 uint32_t count_value = 0U;
315 count_value = TIMER_CNT(timer_periph);
316 return (count_value);
317 }
TIMER_CNT
#define TIMER_CNT(timerx)
Definition: gd32f10x_timer.h:44
void timer_counter_up_direction ( uint32_t timer_periph )

set TIMER counter up direction

Parameters
[in] | timer_periph | TIMERx(x=0..4,7..13)
[out] | none
Return values
none

Definition at line 235 of file gd32f10x_timer.c.

236 {
237 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
238 }
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f10x_timer.h:62
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_counter_value_config | ( | uint32_t | timer_periph,
 |  | uint32_t | counter
 | ) |  |

configure TIMER counter register value

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] | counter | the counter value
[out] | none
Return values
none

Definition at line 301 of file gd32f10x_timer.c.

302 {
303 TIMER_CNT(timer_periph) = (uint32_t)counter;
304 }
TIMER_CNT
#define TIMER_CNT(timerx)
Definition: gd32f10x_timer.h:44
void timer_deinit ( uint32_t timer_periph )

deinit a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_timer.c.

22 {
23 switch(timer_periph){
24 case TIMER0:
25 /* reset TIMER0 */
26 rcu_periph_reset_enable(RCU_TIMER0RST);
27 rcu_periph_reset_disable(RCU_TIMER0RST);
28 break;
29 case TIMER1:
30 /* reset TIMER1 */
31 rcu_periph_reset_enable(RCU_TIMER1RST);
32 rcu_periph_reset_disable(RCU_TIMER1RST);
33 break;
34 case TIMER2:
35 /* reset TIMER2 */
36 rcu_periph_reset_enable(RCU_TIMER2RST);
37 rcu_periph_reset_disable(RCU_TIMER2RST);
38 break;
39 case TIMER3:
40 /* reset TIMER3 */
41 rcu_periph_reset_enable(RCU_TIMER3RST);
42 rcu_periph_reset_disable(RCU_TIMER3RST);
43 break;
44 case TIMER4:
45 /* reset TIMER4 */
46 rcu_periph_reset_enable(RCU_TIMER4RST);
47 rcu_periph_reset_disable(RCU_TIMER4RST);
48 break;
49 case TIMER5:
50 /* reset TIMER5 */
51 rcu_periph_reset_enable(RCU_TIMER5RST);
52 rcu_periph_reset_disable(RCU_TIMER5RST);
53 break;
54 case TIMER6:
55 /* reset TIMER6 */
56 rcu_periph_reset_enable(RCU_TIMER6RST);
57 rcu_periph_reset_disable(RCU_TIMER6RST);
58 break;
59 case TIMER7:
60 /* reset TIMER7 */
61 rcu_periph_reset_enable(RCU_TIMER7RST);
62 rcu_periph_reset_disable(RCU_TIMER7RST);
63 break;
64 #ifdef GD32F10X_XD
65 case TIMER8:
66 /* reset TIMER8 */
67 rcu_periph_reset_enable(RCU_TIMER8RST);
68 rcu_periph_reset_disable(RCU_TIMER8RST);
69 break;
70 case TIMER9:
71 /* reset TIMER9 */
72 rcu_periph_reset_enable(RCU_TIMER9RST);
73 rcu_periph_reset_disable(RCU_TIMER9RST);
74 break;
75 case TIMER10:
76 /* reset TIMER10 */
77 rcu_periph_reset_enable(RCU_TIMER10RST);
78 rcu_periph_reset_disable(RCU_TIMER10RST);
79 break;
80 case TIMER11:
81 /* reset TIMER11 */
82 rcu_periph_reset_enable(RCU_TIMER11RST);
83 rcu_periph_reset_disable(RCU_TIMER11RST);
84 break;
85 case TIMER12:
86 /* reset TIMER12 */
87 rcu_periph_reset_enable(RCU_TIMER12RST);
88 rcu_periph_reset_disable(RCU_TIMER12RST);
89 break;
90 case TIMER13:
91 /* reset TIMER13 */
92 rcu_periph_reset_enable(RCU_TIMER13RST);
93 rcu_periph_reset_disable(RCU_TIMER13RST);
94 break;
95 #endif /* GD32F10X_XD */
96 default:
97 break;
98 }
99 }
RCU_TIMER11RST
Definition: gd32f10x_rcu.h:452
TIMER7
#define TIMER7
Definition: gd32f10x_timer.h:26
RCU_TIMER2RST
Definition: gd32f10x_rcu.h:446
RCU_TIMER8RST
Definition: gd32f10x_rcu.h:495
TIMER13
#define TIMER13
Definition: gd32f10x_timer.h:32
RCU_TIMER7RST
Definition: gd32f10x_rcu.h:489
RCU_TIMER5RST
Definition: gd32f10x_rcu.h:449
RCU_TIMER4RST
Definition: gd32f10x_rcu.h:448
RCU_TIMER6RST
Definition: gd32f10x_rcu.h:450
TIMER9
#define TIMER9
Definition: gd32f10x_timer.h:28
TIMER5
#define TIMER5
Definition: gd32f10x_timer.h:24
TIMER11
#define TIMER11
Definition: gd32f10x_timer.h:30
TIMER8
#define TIMER8
Definition: gd32f10x_timer.h:27
TIMER12
#define TIMER12
Definition: gd32f10x_timer.h:31
TIMER0
#define TIMER0
Definition: gd32f10x_timer.h:19
RCU_TIMER1RST
Definition: gd32f10x_rcu.h:445
RCU_TIMER9RST
Definition: gd32f10x_rcu.h:496
RCU_TIMER12RST
Definition: gd32f10x_rcu.h:453
TIMER1
#define TIMER1
Definition: gd32f10x_timer.h:20
RCU_TIMER10RST
Definition: gd32f10x_rcu.h:497
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
TIMER2
#define TIMER2
Definition: gd32f10x_timer.h:21
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
TIMER6
#define TIMER6
Definition: gd32f10x_timer.h:25
RCU_TIMER3RST
Definition: gd32f10x_rcu.h:447
TIMER3
#define TIMER3
Definition: gd32f10x_timer.h:22
TIMER10
#define TIMER10
Definition: gd32f10x_timer.h:29
RCU_TIMER0RST
Definition: gd32f10x_rcu.h:487
RCU_TIMER13RST
Definition: gd32f10x_rcu.h:454
TIMER4
#define TIMER4
Definition: gd32f10x_timer.h:23
void timer_disable ( uint32_t timer_periph )

disable a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 163 of file gd32f10x_timer.c.

164 {
165 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
166 }
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f10x_timer.h:58
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_dma_disable | ( | uint32_t | timer_periph,
 |  | uint16_t | dma
 | ) |  |

disable the TIMER DMA

Parameters
[in] | timer_periph | please refer to the following parameters
[in] dma timer DMA source enable
  • TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7)
  • TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7)
  • TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7)
[out] | none
Return values
none

Definition at line 541 of file gd32f10x_timer.c.

542 {
543 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
544 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_dma_enable | ( | uint32_t | timer_periph,
 |  | uint16_t | dma
 | ) |  |

enable the TIMER DMA

Parameters
[in] | timer_periph | TIMERx(x=0,1,2,5,14,15,16)
[in] dma timer DMA source enable
  • TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7)
  • TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7)
  • TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7)
[out] | none
Return values
none

Definition at line 522 of file gd32f10x_timer.c.

523 {
524 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
525 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_dma_transfer_config | ( | uint32_t | timer_periph,
 |  | uint32_t | dma_baseaddr,
 |  | uint32_t | dma_lenth
 | ) |  |

configure the TIMER DMA transfer

Parameters
[in] | timer_periph | please refer to the following parameters
[in] dma_baseaddr
  • TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7)
  • TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7)
  • TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7)
[in] dma_lenth
  • TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
[out] | none
Return values
none

Definition at line 594 of file gd32f10x_timer.c.

595 {
596 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
597 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
598 }
TIMER_DMACFG
#define TIMER_DMACFG(timerx)
Definition: gd32f10x_timer.h:53
TIMER_DMACFG_DMATA
#define TIMER_DMACFG_DMATA
Definition: gd32f10x_timer.h:218
TIMER_DMACFG_DMATC
#define TIMER_DMACFG_DMATC
Definition: gd32f10x_timer.h:219
void timer_enable ( uint32_t timer_periph )

enable a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 152 of file gd32f10x_timer.c.

153 {
154 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
155 }
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f10x_timer.h:58
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_event_software_generate | ( | uint32_t | timer_periph,
 |  | uint16_t | event
 | ) |  |

software generate events

Parameters
[in] | timer_periph | please refer to the following parameters
[in] event the timer software event generation sources
  • TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13)
  • TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13)
  • TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11)
  • TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7)
  • TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7)
  • TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7)
  • TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11)
  • TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 615 of file gd32f10x_timer.c.

616 {
617 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
618 }
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f10x_timer.h:40
void timer_external_clock_mode0_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external clock mode0

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1791 of file gd32f10x_timer.c.

1793 {
1794 /* configure TIMER external trigger input */
1795 timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter);
1796
1797 /* reset the SMC bit,TRGS bit */
1798 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1799 /* set the SMC bit,TRGS bit */
1800 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1801 }
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f10x_timer.c:1649
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f10x_timer.h:528
TIMER_SMCFG_TRGSEL_ETIFP
#define TIMER_SMCFG_TRGSEL_ETIFP
Definition: gd32f10x_timer.h:506
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f10x_timer.h:83
void timer_external_clock_mode1_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external clock mode1

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1818 of file gd32f10x_timer.c.

1820 {
1821 /* configure TIMER external trigger input */
1822 timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter);
1823
1824 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1825 }
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f10x_timer.c:1649
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f10x_timer.h:87
void timer_external_clock_mode1_disable ( uint32_t timer_periph )

disable TIMER the external clock mode1

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[out] | none
Return values
none

Definition at line 1833 of file gd32f10x_timer.c.

1834 {
1835 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1836 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f10x_timer.h:87
void timer_external_trigger_as_external_clock_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extrigger,
 |  | uint16_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external trigger as external clock input

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] extrigger
  • TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
  • TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
  • TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
[in] expolarity
  • TIMER_IC_POLARITY_RISING: active low or falling edge active
  • TIMER_IC_POLARITY_FALLING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1730 of file gd32f10x_timer.c.

1732 {
1733 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1734 /* reset the CH1EN bit */
1735 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1736 /* reset the CH1NP bit */
1737 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1738 /* set the CH1NP bit */
1739 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U);
1740 /* reset the CH1MS bit */
1741 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1742 /* set the CH1MS bit */
1743 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U);
1744 /* reset the CH1CAPFLT bit */
1745 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1746 /* set the CH1CAPFLT bit */
1747 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U);
1748 /* set the CH1EN bit */
1749 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1750 }else{
1751 /* reset the CH0EN bit */
1752 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1753 /* reset the CH0P and CH0NP bits */
1754 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1755 /* set the CH0P and CH0NP bits */
1756 TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity;
1757 /* reset the CH0MS bit */
1758 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1759 /* set the CH0MS bit */
1760 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1761 /* reset the CH0CAPFLT bit */
1762 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1763 /* reset the CH0CAPFLT bit */
1764 TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter;
1765 /* set the CH0EN bit */
1766 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1767 }
1768 /* select TIMER input trigger source */
1769 timer_input_trigger_source_select(timer_periph,extrigger);
1770 /* reset the SMC bit */
1771 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1772 /* set the SMC bit */
1773 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1774 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f10x_timer.h:147
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_TRGSEL_CI1FE1
#define TIMER_SMCFG_TRGSEL_CI1FE1
Definition: gd32f10x_timer.h:505
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f10x_timer.h:487
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f10x_timer.h:528
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f10x_timer.c:1565
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f10x_timer.h:145
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
void timer_external_trigger_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER external trigger input

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1649 of file gd32f10x_timer.c.

1651 {
1652 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP|TIMER_SMCFG_ETPSC|TIMER_SMCFG_ETFC));
1653 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler|expolarity);
1654 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter<< 8U);
1655 }
TIMER_SMCFG_ETPSC
#define TIMER_SMCFG_ETPSC
Definition: gd32f10x_timer.h:86
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_ETP
#define TIMER_SMCFG_ETP
Definition: gd32f10x_timer.h:88
TIMER_SMCFG_ETFC
#define TIMER_SMCFG_ETFC
Definition: gd32f10x_timer.h:85
void timer_flag_clear | ( | uint32_t | timer_periph,
 |  | uint32_t | flag
 | ) |  |

clear TIMER flags

Parameters
[in] | timer_periph | please refer to the following parameters
[in] flag the timer interrupt flags
  • TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
  • TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
  • TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
  • TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
  • TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
  • TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
  • TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
  • TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
  • TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
[out] | none
Return values
none

Definition at line 503 of file gd32f10x_timer.c.

504 {
505 TIMER_INTF(timer_periph) &= (~(uint32_t)flag);
506 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f10x_timer.h:39
FlagStatus timer_flag_get | ( | uint32_t | timer_periph,
 |  | uint32_t | flag
 | ) |  |

get TIMER flags

Parameters
[in] | timer_periph | please refer to the following parameters
[in] flag the timer interrupt flags
  • TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
  • TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
  • TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
  • TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
  • TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
  • TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
  • TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
  • TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
  • TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 475 of file gd32f10x_timer.c.

476 {
477 if(RESET != (TIMER_INTF(timer_periph) & flag)){
478 return SET;
479 }else{
480 return RESET;
481 }
482 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f10x_timer.h:39
void timer_hall_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | hallmode
 | ) |  |

configure TIMER hall sensor mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] hallmode
  • TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
  • TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
[out] | none
Return values
none

Definition at line 1540 of file gd32f10x_timer.c.

1541 {
1542 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1543 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1544 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1545 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1546 }else{
1547 }
1548 }
TIMER_CTL1_TI0S
#define TIMER_CTL1_TI0S
Definition: gd32f10x_timer.h:72
TIMER_HALLINTERFACE_ENABLE
#define TIMER_HALLINTERFACE_ENABLE
Definition: gd32f10x_timer.h:546
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_HALLINTERFACE_DISABLE
#define TIMER_HALLINTERFACE_DISABLE
Definition: gd32f10x_timer.h:547
void timer_init | ( | uint32_t | timer_periph,
 |  | timer_parameter_struct * | initpara
 | ) |  |

initialize TIMER counter

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] | initpara | init parameter struct prescaler: prescaler value of the counter clock,0~65535 alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN period: counter auto reload value clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 repetitioncounter: counter repetition value,0~255
[out] | none
Return values
none

Definition at line 114 of file gd32f10x_timer.c.

115 {
116 /* configure the counter prescaler value */
117 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
118
119 /* configure the counter direction and aligned mode */
120 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) ||
121 (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) ||
122 (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)){
123 TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM);
124 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
125 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
126 }
127
128 /* configure the autoreload value */
129 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
130
131 if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
132 /* reset the CKDIV bit */
133 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV;
134 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
135 }
136
137 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
138 /* configure the repetition counter value */
139 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
140 }
141
142 /* generate an update event */
143 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
144 }
TIMER7
#define TIMER7
Definition: gd32f10x_timer.h:26
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f10x_timer.h:62
TIMER_SWEVG_UPG
#define TIMER_SWEVG_UPG
Definition: gd32f10x_timer.h:122
TIMER13
#define TIMER13
Definition: gd32f10x_timer.h:32
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f10x_timer.h:40
TIMER_CAR
#define TIMER_CAR(timerx)
Definition: gd32f10x_timer.h:46
TIMER9
#define TIMER9
Definition: gd32f10x_timer.h:28
TIMER5
#define TIMER5
Definition: gd32f10x_timer.h:24
TIMER11
#define TIMER11
Definition: gd32f10x_timer.h:30
TIMER8
#define TIMER8
Definition: gd32f10x_timer.h:27
TIMER_CTL0_CKDIV
#define TIMER_CTL0_CKDIV
Definition: gd32f10x_timer.h:65
TIMER12
#define TIMER12
Definition: gd32f10x_timer.h:31
TIMER0
#define TIMER0
Definition: gd32f10x_timer.h:19
timer_parameter_struct::clockdivision
uint16_t clockdivision
Definition: gd32f10x_timer.h:232
TIMER1
#define TIMER1
Definition: gd32f10x_timer.h:20
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f10x_timer.h:45
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f10x_timer.h:47
TIMER2
#define TIMER2
Definition: gd32f10x_timer.h:21
TIMER6
#define TIMER6
Definition: gd32f10x_timer.h:25
timer_parameter_struct::repetitioncounter
uint8_t repetitioncounter
Definition: gd32f10x_timer.h:233
TIMER3
#define TIMER3
Definition: gd32f10x_timer.h:22
timer_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f10x_timer.h:228
timer_parameter_struct::period
uint32_t period
Definition: gd32f10x_timer.h:231
TIMER10
#define TIMER10
Definition: gd32f10x_timer.h:29
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f10x_timer.h:63
timer_parameter_struct::alignedmode
uint16_t alignedmode
Definition: gd32f10x_timer.h:229
timer_parameter_struct::counterdirection
uint16_t counterdirection
Definition: gd32f10x_timer.h:230
TIMER4
#define TIMER4
Definition: gd32f10x_timer.h:23
void timer_input_capture_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_ic_parameter_struct * | icpara
 | ) |  |

configure TIMER input capture parameter

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] | icpara | TIMER channel intput parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 icfilter: 0~15
[out] | none
Return values
none

Definition at line 1256 of file gd32f10x_timer.c.

1257 {
1258 switch(channel){
1259 /* configure TIMER_CH_0 */
1260 case TIMER_CH_0:
1261 /* reset the CH0EN bit */
1262 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1263
1264 /* reset the CH0P and CH0NP bits */
1265 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1266 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1267 /* reset the CH0MS bit */
1268 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1269 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1270 /* reset the CH0CAPFLT bit */
1271 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1272 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1273
1274 /* set the CH0EN bit */
1275 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1276 break;
1277
1278 /* configure TIMER_CH_1 */
1279 case TIMER_CH_1:
1280 /* reset the CH1EN bit */
1281 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1282
1283 /* reset the CH1P and CH1NP bits */
1284 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1285 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 4U);
1286 /* reset the CH1MS bit */
1287 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1288 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U);
1289 /* reset the CH1CAPFLT bit */
1290 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1291 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U);
1292
1293 /* set the CH1EN bit */
1294 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1295 break;
1296 /* configure TIMER_CH_2 */
1297 case TIMER_CH_2:
1298 /* reset the CH2EN bit */
1299 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1300
1301 /* reset the CH2P and CH2NP bits */
1302 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
1303 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 8U);
1304
1305 /* reset the CH2MS bit */
1306 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1307 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1308
1309 /* reset the CH2CAPFLT bit */
1310 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1311 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 4U);
1312
1313 /* set the CH2EN bit */
1314 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1315 break;
1316 /* configure TIMER_CH_3 */
1317 case TIMER_CH_3:
1318 /* reset the CH3EN bit */
1319 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1320
1321 /* reset the CH3P bits */
1322 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P));
1323 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 12U);
1324
1325 /* reset the CH3MS bit */
1326 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1327 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U);
1328
1329 /* reset the CH3CAPFLT bit */
1330 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1331 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U);
1332
1333 /* set the CH3EN bit */
1334 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1335 break;
1336 default:
1337 break;
1338 }
1339 /* configure TIMER channel input capture prescaler value */
1340 timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler));
1341 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f10x_timer.h:263
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f10x_timer.h:179
TIMER_CHCTL1_CH2MS
#define TIMER_CHCTL1_CH2MS
Definition: gd32f10x_timer.h:151
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f10x_timer.c:1359
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f10x_timer.h:147
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f10x_timer.h:180
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f10x_timer.h:264
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f10x_timer.h:176
TIMER_CHCTL1_CH3CAPFLT
#define TIMER_CHCTL1_CH3CAPFLT
Definition: gd32f10x_timer.h:165
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f10x_timer.h:177
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f10x_timer.h:262
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f10x_timer.h:145
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
TIMER_CHCTL1_CH2CAPFLT
#define TIMER_CHCTL1_CH2CAPFLT
Definition: gd32f10x_timer.h:163
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f10x_timer.h:181
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f10x_timer.h:265
TIMER_CHCTL1_CH3MS
#define TIMER_CHCTL1_CH3MS
Definition: gd32f10x_timer.h:156
void timer_input_pwm_capture_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_ic_parameter_struct * | icpwm
 | ) |  |

configure TIMER input pwm capture function

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] channel
  • TIMER_CH_0: TIMER channel0
  • TIMER_CH_1: TIMER channel1
[in] | icpwm:TIMER | channel intput pwm parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 icfilter: 0~15
[out] | none
Return values
none

Definition at line 1435 of file gd32f10x_timer.c.

1436 {
1437 uint16_t icpolarity = 0x0U;
1438 uint16_t icselection = 0x0U;
1439
1440 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1441 icpolarity = TIMER_IC_POLARITY_FALLING;
1442 }else{
1443 icpolarity = TIMER_IC_POLARITY_RISING;
1444 }
1445
1446 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1447 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1448 }else{
1449 icselection = TIMER_IC_SELECTION_DIRECTTI;
1450 }
1451
1452 if(TIMER_CH_0 == channel){
1453 /* reset the CH0EN bit */
1454 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1455 /* reset the CH0P and CH0NP bits */
1456 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1457 /* set the CH0P and CH0NP bits */
1458 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1459 /* reset the CH0MS bit */
1460 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1461 /* set the CH0MS bit */
1462 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1463 /* reset the CH0CAPFLT bit */
1464 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1465 /* set the CH0CAPFLT bit */
1466 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1467 /* set the CH0EN bit */
1468 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1469 /* configure TIMER channel input capture prescaler value */
1470 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1471
1472 /* reset the CH1EN bit */
1473 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1474 /* reset the CH1P and CH1NP bits */
1475 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1476 /* set the CH1P and CH1NP bits */
1477 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U);
1478 /* reset the CH1MS bit */
1479 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1480 /* set the CH1MS bit */
1481 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U);
1482 /* reset the CH1CAPFLT bit */
1483 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1484 /* set the CH1CAPFLT bit */
1485 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U);
1486 /* set the CH1EN bit */
1487 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1488 /* configure TIMER channel input capture prescaler value */
1489 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1490 }else{
1491 /* reset the CH1EN bit */
1492 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1493 /* reset the CH1P and CH1NP bits */
1494 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1495 /* set the CH1P and CH1NP bits */
1496 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U);
1497 /* reset the CH1MS bit */
1498 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1499 /* set the CH1MS bit */
1500 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U);
1501 /* reset the CH1CAPFLT bit */
1502 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1503 /* set the CH1CAPFLT bit */
1504 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U);
1505 /* set the CH1EN bit */
1506 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1507 /* configure TIMER channel input capture prescaler value */
1508 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1509
1510 /* reset the CH0EN bit */
1511 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1512 /* reset the CH0P and CH0NP bits */
1513 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1514 /* set the CH0P and CH0NP bits */
1515 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1516 /* reset the CH0MS bit */
1517 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1518 /* set the CH0MS bit */
1519 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1520 /* reset the CH0CAPFLT bit */
1521 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1522 /* set the CH0CAPFLT bit */
1523 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1524 /* set the CH0EN bit */
1525 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1526 /* configure TIMER channel input capture prescaler value */
1527 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1528 }
1529 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f10x_timer.h:263
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f10x_timer.c:1359
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f10x_timer.h:147
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f10x_timer.h:264
TIMER_IC_SELECTION_INDIRECTTI
#define TIMER_IC_SELECTION_INDIRECTTI
Definition: gd32f10x_timer.h:488
TIMER_IC_POLARITY_RISING
#define TIMER_IC_POLARITY_RISING
Definition: gd32f10x_timer.h:482
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f10x_timer.h:487
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f10x_timer.h:262
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f10x_timer.h:145
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_IC_POLARITY_FALLING
#define TIMER_IC_POLARITY_FALLING
Definition: gd32f10x_timer.h:483
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f10x_timer.h:265
void timer_input_trigger_source_select | ( | uint32_t | timer_periph,
 |  | uint32_t | intrigger
 | ) |  |

select TIMER input trigger source

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] intrigger
  • TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
  • TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
  • TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
  • TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
  • TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector
  • TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
  • TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
  • TIMER_SMCFG_TRGSEL_ETIFP: external trigger
[out] | none
Return values
none

Definition at line 1565 of file gd32f10x_timer.c.

1566 {
1567 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1568 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1569 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f10x_timer.h:83
void timer_internal_clock_config ( uint32_t timer_periph )

configure TIMER internal clock mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[out] | none
Return values
none

Definition at line 1693 of file gd32f10x_timer.c.

1694 {
1695 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1696 }
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
void timer_internal_trigger_as_external_clock_config | ( | uint32_t | timer_periph,
 |  | uint32_t | intrigger
 | ) |  |

configure TIMER the internal trigger as external clock input

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] intrigger
  • TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
  • TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
  • TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
  • TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
[out] | none
Return values
none

Definition at line 1709 of file gd32f10x_timer.c.

1710 {
1711 timer_input_trigger_source_select(timer_periph,intrigger);
1712 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1713 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1714 }
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f10x_timer.h:528
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f10x_timer.c:1565
void timer_interrupt_disable | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

disable the TIMER interrupt

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt timer interrupt source enable
  • TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
  • TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
  • TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
  • TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
  • TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
  • TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
  • TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
  • TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 405 of file gd32f10x_timer.c.

406 {
407 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
408 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_interrupt_enable | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

enable the TIMER interrupt

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt timer interrupt enable source
  • TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
  • TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
  • TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
  • TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
  • TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
  • TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
  • TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
  • TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 385 of file gd32f10x_timer.c.

386 {
387 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
388 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_interrupt_flag_clear | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

clear TIMER interrupt flag

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt the timer interrupt bits
  • TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
  • TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
  • TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
  • TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
  • TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
  • TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
  • TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
  • TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 451 of file gd32f10x_timer.c.

452 {
453 TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt);
454 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f10x_timer.h:39
FlagStatus timer_interrupt_flag_get | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

get timer interrupt flag

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt the timer interrupt bits
  • TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
  • TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
  • TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
  • TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
  • TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
  • TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
  • TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
  • TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 425 of file gd32f10x_timer.c.

426 {
427 uint32_t val;
428 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
429 if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
430 return SET;
431 }else{
432 return RESET;
433 }
434 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f10x_timer.h:39
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_master_output_trigger_source_select | ( | uint32_t | timer_periph,
 |  | uint32_t | outrigger
 | ) |  |

select TIMER master mode output trigger source

Parameters
[in] | timer_periph | TIMERx(x=0..7)
[in] outrigger
  • TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output
  • TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output
  • TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output
  • TIMER_TRI_OUT_SRC_CC0: a capture or a compare match occurred in channal0 as trigger output TRGO
  • TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output
  • TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output
  • TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output
  • TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output
[out] | none
Return values
none

Definition at line 1586 of file gd32f10x_timer.c.

1587 {
1588 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1589 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1590 }
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_CTL1_MMC
#define TIMER_CTL1_MMC
Definition: gd32f10x_timer.h:71
void timer_master_slave_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | masterslave
 | ) |  |

configure TIMER master slave mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] masterslave
  • TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
  • TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
[out] | none
Return values
none

Definition at line 1624 of file gd32f10x_timer.c.

1625 {
1626 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1627 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1628 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1629 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1630 }else{
1631 }
1632 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_MSM
#define TIMER_SMCFG_MSM
Definition: gd32f10x_timer.h:84
TIMER_MASTER_SLAVE_MODE_DISABLE
#define TIMER_MASTER_SLAVE_MODE_DISABLE
Definition: gd32f10x_timer.h:532
TIMER_MASTER_SLAVE_MODE_ENABLE
#define TIMER_MASTER_SLAVE_MODE_ENABLE
Definition: gd32f10x_timer.h:531
void timer_prescaler_config | ( | uint32_t | timer_periph,
 |  | uint16_t | prescaler,
 |  | uint8_t | pscreload
 | ) |  |

configure TIMER prescaler

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] | prescaler | prescaler value
[in] pscreload prescaler reload mode
  • TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
  • TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
[out] | none
Return values
none

Definition at line 261 of file gd32f10x_timer.c.

262 {
263 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
264
265 if(TIMER_PSC_RELOAD_NOW == pscreload){
266 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
267 }
268 }
TIMER_SWEVG_UPG
#define TIMER_SWEVG_UPG
Definition: gd32f10x_timer.h:122
TIMER_PSC_RELOAD_NOW
#define TIMER_PSC_RELOAD_NOW
Definition: gd32f10x_timer.h:377
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f10x_timer.h:40
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f10x_timer.h:45
uint16_t timer_prescaler_read ( uint32_t timer_periph )

read TIMER prescaler value

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
prescaler register value

Definition at line 325 of file gd32f10x_timer.c.

326 {
327 uint16_t prescaler_value = 0U;
328 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
329 return (prescaler_value);
330 }
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f10x_timer.h:45
void timer_primary_output_config | ( | uint32_t | timer_periph,
 |  | ControlStatus | newvalue
 | ) |  |

configure TIMER primary output function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 696 of file gd32f10x_timer.c.

697 {
698 if(ENABLE == newvalue){
699 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
700 }else{
701 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
702 }
703 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_POEN
#define TIMER_CCHP_POEN
Definition: gd32f10x_timer.h:215
void timer_quadrature_decoder_mode_config | ( | uint32_t | timer_periph,
 |  | uint32_t | decomode,
 |  | uint16_t | ic0polarity,
 |  | uint16_t | ic1polarity
 | ) |  |

configure TIMER quadrature decoder mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] decomode
  • TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
  • TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
  • TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
[in] ic0polarity
  • TIMER_IC_POLARITY_RISING: capture rising edge
  • TIMER_IC_POLARITY_FALLING: capture falling edge
[in] ic1polarity
  • TIMER_IC_POLARITY_RISING: capture rising edge
  • TIMER_IC_POLARITY_FALLING: capture falling edge
[out] | none
Return values
none

Definition at line 1673 of file gd32f10x_timer.c.

1675 {
1676 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1677 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1678
1679 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1680 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U));
1681
1682 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1683 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1684 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity<< 4U));
1685 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f10x_timer.h:487
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
void timer_repetition_value_config | ( | uint32_t | timer_periph,
 |  | uint16_t | repetition
 | ) |  |

configure TIMER repetition register value

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] | repetition | the counter repetition value,0~255
[out] | none
Return values
none

Definition at line 277 of file gd32f10x_timer.c.

278 {
279 TIMER_CREP(timer_periph) = (uint32_t)repetition;
280 }
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f10x_timer.h:47
void timer_single_pulse_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | spmode
 | ) |  |

configure TIMER single pulse mode

Parameters
[in] | timer_periph | TIMERx(x=0..8,11)
[in] spmode
  • TIMER_SP_MODE_SINGLE: single pulse mode
  • TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
[out] | none
Return values
none

Definition at line 341 of file gd32f10x_timer.c.

342 {
343 if(TIMER_SP_MODE_SINGLE == spmode){
344 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
345 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
346 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
347 }else{
348 }
349 }
TIMER_CTL0_SPM
#define TIMER_CTL0_SPM
Definition: gd32f10x_timer.h:61
TIMER_SP_MODE_REPETITIVE
#define TIMER_SP_MODE_REPETITIVE
Definition: gd32f10x_timer.h:392
TIMER_SP_MODE_SINGLE
#define TIMER_SP_MODE_SINGLE
Definition: gd32f10x_timer.h:391
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_slave_mode_select | ( | uint32_t | timer_periph,
 |  | uint32_t | slavemode
 | ) |  |

select TIMER slave mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] slavemode
  • TIMER_SLAVE_MODE_DISABLE: slave mode disable
  • TIMER_ENCODER_MODE0: encoder mode 0
  • TIMER_ENCODER_MODE1: encoder mode 1
  • TIMER_ENCODER_MODE2: encoder mode 2
  • TIMER_SLAVE_MODE_RESTART: restart mode
  • TIMER_SLAVE_MODE_PAUSE: pause mode
  • TIMER_SLAVE_MODE_EVENT: event mode
  • TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.
[out] | none
Return values
none

Definition at line 1608 of file gd32f10x_timer.c.

1609 {
1610 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1611
1612 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1613 }
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
void timer_update_event_disable ( uint32_t timer_periph )

disable the update event

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 207 of file gd32f10x_timer.c.

208 {
209 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
210 }
TIMER_CTL0_UPDIS
#define TIMER_CTL0_UPDIS
Definition: gd32f10x_timer.h:59
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_update_event_enable ( uint32_t timer_periph )

enable the update event

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 196 of file gd32f10x_timer.c.

197 {
198 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
199 }
TIMER_CTL0_UPDIS
#define TIMER_CTL0_UPDIS
Definition: gd32f10x_timer.h:59
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_update_source_config | ( | uint32_t | timer_periph,
 |  | uint8_t | update
 | ) |  |

configure TIMER update source

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] update
  • TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
  • TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
[out] | none
Return values
none

Definition at line 360 of file gd32f10x_timer.c.

361 {
362 if(TIMER_UPDATE_SRC_REGULAR == update){
363 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
364 }else if(update == TIMER_UPDATE_SRC_GLOBAL){
365 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
366 }else{
367 }
368 }
TIMER_UPDATE_SRC_GLOBAL
#define TIMER_UPDATE_SRC_GLOBAL
Definition: gd32f10x_timer.h:396
TIMER_UPDATE_SRC_REGULAR
#define TIMER_UPDATE_SRC_REGULAR
Definition: gd32f10x_timer.h:395
TIMER_CTL0_UPS
#define TIMER_CTL0_UPS
Definition: gd32f10x_timer.h:60
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f10x_usart.h File Reference

definitions for the USART More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | USART1 USART_BASE
#define | USART2 (USART_BASE+0x00000400U)
#define | UART3 (USART_BASE+0x00000800U)
#define | UART4 (USART_BASE+0x00000C00U)
#define | USART0 (USART_BASE+0x0000F400U)
#define | USART_STAT(usartx) REG32((usartx) + 0x00U)
#define | USART_DATA(usartx) REG32((usartx) + 0x04U)
#define | USART_BAUD(usartx) REG32((usartx) + 0x08U)
#define | USART_CTL0(usartx) REG32((usartx) + 0x0CU)
#define | USART_CTL1(usartx) REG32((usartx) + 0x10U)
#define | USART_CTL2(usartx) REG32((usartx) + 0x14U)
#define | USART_GP(usartx) REG32((usartx) + 0x18U)
#define | USART_STAT_PERR BIT(0)
#define | USART_STAT_FERR BIT(1)
#define | USART_STAT_NERR BIT(2)
#define | USART_STAT_ORERR BIT(3)
#define | USART_STAT_IDLEF BIT(4)
#define | USART_STAT_RBNE BIT(5)
#define | USART_STAT_TC BIT(6)
#define | USART_STAT_TBE BIT(7)
#define | USART_STAT_LBDF BIT(8)
#define | USART_STAT_CTSF BIT(9)
#define | USART_DATA_DATA BITS(0,8)
#define | USART_BAUD_FRADIV BITS(0,3)
#define | USART_BAUD_INTDIV BITS(4,15)
#define | USART_CTL0_SBKCMD BIT(0)
#define | USART_CTL0_RWU BIT(1)
#define | USART_CTL0_REN BIT(2)
#define | USART_CTL0_TEN BIT(3)
#define | USART_CTL0_IDLEIE BIT(4)
#define | USART_CTL0_RBNEIE BIT(5)
#define | USART_CTL0_TCIE BIT(6)
#define | USART_CTL0_TBEIE BIT(7)
#define | USART_CTL0_PERRIE BIT(8)
#define | USART_CTL0_PM BIT(9)
#define | USART_CTL0_PCEN BIT(10)
#define | USART_CTL0_WM BIT(11)
#define | USART_CTL0_WL BIT(12)
#define | USART_CTL0_UEN BIT(13)
#define | USART_CTL1_ADDR BITS(0,3)
#define | USART_CTL1_LBLEN BIT(5)
#define | USART_CTL1_LBDIE BIT(6)
#define | USART_CTL1_CLEN BIT(8)
#define | USART_CTL1_CPH BIT(9)
#define | USART_CTL1_CPL BIT(10)
#define | USART_CTL1_CKEN BIT(11)
#define | USART_CTL1_STB BITS(12,13)
#define | USART_CTL1_LMEN BIT(14)
#define | USART_CTL2_ERRIE BIT(0)
#define | USART_CTL2_IREN BIT(1)
#define | USART_CTL2_IRLP BIT(2)
#define | USART_CTL2_HDEN BIT(3)
#define | USART_CTL2_NKEN BIT(4)
#define | USART_CTL2_SCEN BIT(5)
#define | USART_CTL2_DENR BIT(6)
#define | USART_CTL2_DENT BIT(7)
#define | USART_CTL2_RTSEN BIT(8)
#define | USART_CTL2_CTSEN BIT(9)
#define | USART_CTL2_CTSIE BIT(10)
#define | USART_GP_PSC BITS(0,7)
#define | USART_GP_GUAT BITS(8,15)
#define | USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define | USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
#define | USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define | USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)
#define | USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
#define | USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
#define | USART_STAT_REG_OFFSET 0x00U
#define | USART_CTL0_REG_OFFSET 0x0CU
#define | USART_CTL1_REG_OFFSET 0x10U
#define | USART_CTL2_REG_OFFSET 0x14U
#define | CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define | USART_RECEIVE_ENABLE CTL0_REN(1)
#define | USART_RECEIVE_DISABLE CTL0_REN(0)
#define | CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
#define | USART_TRANSMIT_ENABLE CTL0_TEN(1)
#define | USART_TRANSMIT_DISABLE CTL0_TEN(0)
#define | CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
#define | USART_PM_NONE CTL0_PM(0)
#define | USART_PM_EVEN CTL0_PM(2)
#define | USART_PM_ODD CTL0_PM(3)
#define | CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define | USART_WM_IDLE CTL0_WM(0)
#define | USART_WM_ADDR CTL0_WM(1)
#define | CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
#define | USART_WL_8BIT CTL0_WL(0)
#define | USART_WL_9BIT CTL0_WL(1)
#define | CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
#define | USART_STB_1BIT CTL1_STB(0)
#define | USART_STB_0_5BIT CTL1_STB(1)
#define | USART_STB_2BIT CTL1_STB(2)
#define | USART_STB_1_5BIT CTL1_STB(3)
#define | CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
#define | USART_LBLEN_10B CTL1_LBLEN(0)
#define | USART_LBLEN_11B CTL1_LBLEN(1)
#define | CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define | USART_CLEN_NONE CTL1_CLEN(0)
#define | USART_CLEN_EN CTL1_CLEN(1)
#define | CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define | USART_CPH_1CK CTL1_CPH(0)
#define | USART_CPH_2CK CTL1_CPH(1)
#define | CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
#define | USART_CPL_LOW CTL1_CPL(0)
#define | USART_CPL_HIGH CTL1_CPL(1)
#define | CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
#define | USART_DENR_ENABLE CLT2_DENR(1)
#define | USART_DENR_DISABLE CLT2_DENR(0)
#define | CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
#define | USART_DENT_ENABLE CLT2_DENT(1)
#define | USART_DENT_DISABLE CLT2_DENT(0)
#define | CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define | USART_RTS_ENABLE CLT2_RTSEN(1)
#define | USART_RTS_DISABLE CLT2_RTSEN(0)
#define | CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define | USART_CTS_ENABLE CLT2_CTSEN(1)
#define | USART_CTS_DISABLE CLT2_CTSEN(0)
#define | CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define | USART_IRLP_LOW CTL2_IRLP(1)
#define | USART_IRLP_NORMAL CTL2_IRLP(0)

Enumerations

enum usart_flag_enum {
USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U),
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U),
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U)
}
enum usart_interrupt_flag_enum {
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U),
USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),
USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U)
}
enum usart_interrupt_enum {
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),
USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U)
}

Functions

void | usart_deinit (uint32_t usart_periph)
reset USART/UART More...
void | usart_baudrate_set (uint32_t usart_periph, uint32_t baudval)
configure USART baud rate value More...
void | usart_parity_config (uint32_t usart_periph, uint32_t paritycfg)
configure USART parity More...
void | usart_word_length_set (uint32_t usart_periph, uint32_t wlen)
configure USART word length More...
void | usart_stop_bit_set (uint32_t usart_periph, uint32_t stblen)
configure USART stop bit length More...
void | usart_enable (uint32_t usart_periph)
enable USART More...
void | usart_disable (uint32_t usart_periph)
disable USART More...
void | usart_transmit_config (uint32_t usart_periph, uint32_t txconfig)
configure USART transmitter More...
void | usart_receive_config (uint32_t usart_periph, uint32_t rxconfig)
configure USART receiver More...
void | usart_data_transmit (uint32_t usart_periph, uint32_t data)
USART transmit data function. More...
uint16_t | usart_data_receive (uint32_t usart_periph)
USART receive data function. More...
void | usart_address_config (uint32_t usart_periph, uint8_t addr)
configure the address of the USART in wake up by address match mode More...
void | usart_mute_mode_enable (uint32_t usart_periph)
receiver in mute mode More...
void | usart_mute_mode_disable (uint32_t usart_periph)
receiver in active mode More...
void | usart_mute_mode_wakeup_config (uint32_t usart_periph, uint32_t wmethod)
configure wakeup method in mute mode More...
void | usart_lin_mode_enable (uint32_t usart_periph)
enable LIN mode More...
void | usart_lin_mode_disable (uint32_t usart_periph)
disable LIN mode More...
void | usart_lin_break_dection_length_config (uint32_t usart_periph, uint32_t lblen)
configure lin break frame length More...
void | usart_send_break (uint32_t usart_periph)
send break frame More...
void | usart_halfduplex_enable (uint32_t usart_periph)
enable half duplex mode More...
void | usart_halfduplex_disable (uint32_t usart_periph)
disable half duplex mode More...
void | usart_synchronous_clock_enable (uint32_t usart_periph)
enable CK pin in synchronous mode More...
void | usart_synchronous_clock_disable (uint32_t usart_periph)
disable CK pin in synchronous mode More...
void | usart_synchronous_clock_config (uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
configure USART synchronous mode parameters More...
void | usart_guard_time_config (uint32_t usart_periph, uint32_t gaut)
configure guard time value in smartcard mode More...
void | usart_smartcard_mode_enable (uint32_t usart_periph)
enable smartcard mode More...
void | usart_smartcard_mode_disable (uint32_t usart_periph)
disable smartcard mode More...
void | usart_smartcard_mode_nack_enable (uint32_t usart_periph)
enable NACK in smartcard mode More...
void | usart_smartcard_mode_nack_disable (uint32_t usart_periph)
disable NACK in smartcard mode More...
void | usart_irda_mode_enable (uint32_t usart_periph)
enable IrDA mode More...
void | usart_irda_mode_disable (uint32_t usart_periph)
disable IrDA mode More...
void | usart_prescaler_config (uint32_t usart_periph, uint8_t psc)
configure the peripheral clock prescaler in USART IrDA low-power mode More...
void | usart_irda_lowpower_config (uint32_t usart_periph, uint32_t irlp)
configure IrDA low-power More...
void | usart_hardware_flow_rts_config (uint32_t usart_periph, uint32_t rtsconfig)
configure hardware flow control RTS More...
void | usart_hardware_flow_cts_config (uint32_t usart_periph, uint32_t ctsconfig)
configure hardware flow control CTS More...
void | usart_dma_receive_config (uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA reception More...
void | usart_dma_transmit_config (uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA transmission More...
FlagStatus | usart_flag_get (uint32_t usart_periph, usart_flag_enum flag)
get flag in STAT register More...
void | usart_flag_clear (uint32_t usart_periph, usart_flag_enum flag)
clear flag in STAT register More...
void | usart_interrupt_enable (uint32_t usart_periph, uint32_t int_flag)
enable USART interrupt More...
void | usart_interrupt_disable (uint32_t usart_periph, uint32_t int_flag)
disable USART interrupt More...
FlagStatus | usart_interrupt_flag_get (uint32_t usart_periph, uint32_t int_flag)
get USART interrupt and flag status More...
void | usart_interrupt_flag_clear (uint32_t usart_periph, uint32_t flag)
clear USART interrupt flag in STAT register More...

Detailed Description

definitions for the USART

Definition in file gd32f10x_usart.h.

Macro Definition Documentation

#define CLT2_CTSEN ( regval ) (BIT(9) & ((uint32_t)(regval) << 9))

Definition at line 234 of file gd32f10x_usart.h.

#define CLT2_DENR ( regval ) (BIT(6) & ((uint32_t)(regval) << 6))

Definition at line 219 of file gd32f10x_usart.h.

#define CLT2_DENT ( regval ) (BIT(7) & ((uint32_t)(regval) << 7))

Definition at line 224 of file gd32f10x_usart.h.

#define CLT2_RTSEN ( regval ) (BIT(8) & ((uint32_t)(regval) << 8))

Definition at line 229 of file gd32f10x_usart.h.

#define CTL0_PM ( regval ) (BITS(9,10) & ((uint32_t)(regval) << 9))

Definition at line 176 of file gd32f10x_usart.h.

#define CTL0_REN ( regval ) (BIT(2) & ((uint32_t)(regval) << 2))

Definition at line 166 of file gd32f10x_usart.h.

#define CTL0_TEN ( regval ) (BIT(3) & ((uint32_t)(regval) << 3))

Definition at line 171 of file gd32f10x_usart.h.

#define CTL0_WL ( regval ) (BIT(12) & ((uint32_t)(regval) << 12))

Definition at line 187 of file gd32f10x_usart.h.

#define CTL0_WM ( regval ) (BIT(11) & ((uint32_t)(regval) << 11))

Definition at line 182 of file gd32f10x_usart.h.

#define CTL1_CLEN ( regval ) (BIT(8) & ((uint32_t)(regval) << 8))

Definition at line 204 of file gd32f10x_usart.h.

#define CTL1_CPH ( regval ) (BIT(9) & ((uint32_t)(regval) << 9))

Definition at line 209 of file gd32f10x_usart.h.

#define CTL1_CPL ( regval ) (BIT(10) & ((uint32_t)(regval) << 10))

Definition at line 214 of file gd32f10x_usart.h.

#define CTL1_LBLEN ( regval ) (BIT(5) & ((uint32_t)(regval) << 5))

Definition at line 199 of file gd32f10x_usart.h.

#define CTL1_STB ( regval ) (BITS(12,13) & ((uint32_t)(regval) << 12))

Definition at line 192 of file gd32f10x_usart.h.

#define CTL2_IRLP ( regval ) (BIT(2) & ((uint32_t)(regval) << 2))

Definition at line 239 of file gd32f10x_usart.h.

#define UART3 (USART_BASE+0x00000800U)

UART3 base address

Definition at line 21 of file gd32f10x_usart.h.

#define UART4 (USART_BASE+0x00000C00U)

UART4 base address

Definition at line 22 of file gd32f10x_usart.h.

#define USART0 (USART_BASE+0x0000F400U)

USART0 base address

Definition at line 23 of file gd32f10x_usart.h.

#define USART1 USART_BASE

USART1 base address

Definition at line 19 of file gd32f10x_usart.h.

#define USART2 (USART_BASE+0x00000400U)

USART2 base address

Definition at line 20 of file gd32f10x_usart.h.

#define USART_BAUD ( usartx ) REG32((usartx) + 0x08U)

USART baud rate register

Definition at line 28 of file gd32f10x_usart.h.

#define USART_BAUD_FRADIV BITS(0,3)

fraction part of baud-rate divider

Definition at line 51 of file gd32f10x_usart.h.

#define USART_BAUD_INTDIV BITS(4,15)

integer part of baud-rate divider

Definition at line 52 of file gd32f10x_usart.h.

#define USART_BIT_POS ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 102 of file gd32f10x_usart.h.

#define USART_BIT_POS2 ( val ) (((uint32_t)(val) & 0x1F0000U) >> 16)

Definition at line 106 of file gd32f10x_usart.h.

#define USART_CLEN_EN CTL1_CLEN(1)

there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame

Definition at line 206 of file gd32f10x_usart.h.

#define USART_CLEN_NONE CTL1_CLEN(0)

there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame

Definition at line 205 of file gd32f10x_usart.h.

#define USART_CPH_1CK CTL1_CPH(0)

first clock transition is the first data capture edge

Definition at line 210 of file gd32f10x_usart.h.

#define USART_CPH_2CK CTL1_CPH(1)

second clock transition is the first data capture edge

Definition at line 211 of file gd32f10x_usart.h.

#define USART_CPL_HIGH CTL1_CPL(1)

steady high value on CK pin

Definition at line 216 of file gd32f10x_usart.h.

#define USART_CPL_LOW CTL1_CPL(0)

steady low value on CK pin

Definition at line 215 of file gd32f10x_usart.h.

#define USART_CTL0 ( usartx ) REG32((usartx) + 0x0CU)

USART control register 0

Definition at line 29 of file gd32f10x_usart.h.

#define USART_CTL0_IDLEIE BIT(4)

idle line detected interrupt enable

Definition at line 59 of file gd32f10x_usart.h.

#define USART_CTL0_PCEN BIT(10)

parity check function enable

Definition at line 65 of file gd32f10x_usart.h.

#define USART_CTL0_PERRIE BIT(8)

parity error interrupt enable

Definition at line 63 of file gd32f10x_usart.h.

#define USART_CTL0_PM BIT(9)

parity mode

Definition at line 64 of file gd32f10x_usart.h.

#define USART_CTL0_RBNEIE BIT(5)

read data buffer not empty interrupt and overrun error interrupt enable

Definition at line 60 of file gd32f10x_usart.h.

#define USART_CTL0_REG_OFFSET 0x0CU

CTL0 register offset

Definition at line 110 of file gd32f10x_usart.h.

#define USART_CTL0_REN BIT(2)

receiver enable

Definition at line 57 of file gd32f10x_usart.h.

#define USART_CTL0_RWU BIT(1)

receiver wakeup from mute mode

Definition at line 56 of file gd32f10x_usart.h.

#define USART_CTL0_SBKCMD BIT(0)

send break command

Definition at line 55 of file gd32f10x_usart.h.

#define USART_CTL0_TBEIE BIT(7)

transmitter buffer empty interrupt enable

Definition at line 62 of file gd32f10x_usart.h.

#define USART_CTL0_TCIE BIT(6)

transmission complete interrupt enable

Definition at line 61 of file gd32f10x_usart.h.

#define USART_CTL0_TEN BIT(3)

transmitter enable

Definition at line 58 of file gd32f10x_usart.h.

#define USART_CTL0_UEN BIT(13)

USART enable

Definition at line 68 of file gd32f10x_usart.h.

#define USART_CTL0_WL BIT(12)

word length

Definition at line 67 of file gd32f10x_usart.h.

#define USART_CTL0_WM BIT(11)

wakeup method in mute mode

Definition at line 66 of file gd32f10x_usart.h.

#define USART_CTL1 ( usartx ) REG32((usartx) + 0x10U)

USART control register 1

Definition at line 30 of file gd32f10x_usart.h.

#define USART_CTL1_ADDR BITS(0,3)

address of USART

Definition at line 71 of file gd32f10x_usart.h.

#define USART_CTL1_CKEN BIT(11)

CK pin enable

Definition at line 77 of file gd32f10x_usart.h.

#define USART_CTL1_CLEN BIT(8)

CK length

Definition at line 74 of file gd32f10x_usart.h.

#define USART_CTL1_CPH BIT(9)

CK phase

Definition at line 75 of file gd32f10x_usart.h.

#define USART_CTL1_CPL BIT(10)

CK polarity

Definition at line 76 of file gd32f10x_usart.h.

#define USART_CTL1_LBDIE BIT(6)

LIN break detected interrupt eanble

Definition at line 73 of file gd32f10x_usart.h.

#define USART_CTL1_LBLEN BIT(5)

LIN break frame length

Definition at line 72 of file gd32f10x_usart.h.

#define USART_CTL1_LMEN BIT(14)

LIN mode enable

Definition at line 79 of file gd32f10x_usart.h.

#define USART_CTL1_REG_OFFSET 0x10U

CTL1 register offset

Definition at line 111 of file gd32f10x_usart.h.

#define USART_CTL1_STB BITS(12,13)

STOP bits length

Definition at line 78 of file gd32f10x_usart.h.

#define USART_CTL2 ( usartx ) REG32((usartx) + 0x14U)

USART control register 2

Definition at line 31 of file gd32f10x_usart.h.

#define USART_CTL2_CTSEN BIT(9)

CTS enable

Definition at line 91 of file gd32f10x_usart.h.

#define USART_CTL2_CTSIE BIT(10)

CTS interrupt enable

Definition at line 92 of file gd32f10x_usart.h.

#define USART_CTL2_DENR BIT(6)

DMA request enable for reception

Definition at line 88 of file gd32f10x_usart.h.

#define USART_CTL2_DENT BIT(7)

DMA request enable for transmission

Definition at line 89 of file gd32f10x_usart.h.

#define USART_CTL2_ERRIE BIT(0)

error interrupt enable

Definition at line 82 of file gd32f10x_usart.h.

#define USART_CTL2_HDEN BIT(3)

half-duplex enable

Definition at line 85 of file gd32f10x_usart.h.

#define USART_CTL2_IREN BIT(1)

IrDA mode enable

Definition at line 83 of file gd32f10x_usart.h.

#define USART_CTL2_IRLP BIT(2)

IrDA low-power

Definition at line 84 of file gd32f10x_usart.h.

#define USART_CTL2_NKEN BIT(4)

NACK enable in smartcard mode

Definition at line 86 of file gd32f10x_usart.h.

#define USART_CTL2_REG_OFFSET 0x14U

CTL2 register offset

Definition at line 112 of file gd32f10x_usart.h.

#define USART_CTL2_RTSEN BIT(8)

RTS enable

Definition at line 90 of file gd32f10x_usart.h.

#define USART_CTL2_SCEN BIT(5)

smartcard mode enable

Definition at line 87 of file gd32f10x_usart.h.

#define USART_CTS_DISABLE CLT2_CTSEN(0)

CTS disable

Definition at line 236 of file gd32f10x_usart.h.

#define USART_CTS_ENABLE CLT2_CTSEN(1)

CTS enable

Definition at line 235 of file gd32f10x_usart.h.

#define USART_DATA ( usartx ) REG32((usartx) + 0x04U)

USART data register

Definition at line 27 of file gd32f10x_usart.h.

#define USART_DATA_DATA BITS(0,8)

transmit or read data value

Definition at line 48 of file gd32f10x_usart.h.

#define USART_DENR_DISABLE CLT2_DENR(0)

DMA request disable for reception

Definition at line 221 of file gd32f10x_usart.h.

#define USART_DENR_ENABLE CLT2_DENR(1)

DMA request enable for reception

Definition at line 220 of file gd32f10x_usart.h.

#define USART_DENT_DISABLE CLT2_DENT(0)

DMA request disable for transmission

Definition at line 226 of file gd32f10x_usart.h.

#define USART_DENT_ENABLE CLT2_DENT(1)

DMA request enable for transmission

Definition at line 225 of file gd32f10x_usart.h.

#define USART_GP ( usartx ) REG32((usartx) + 0x18U)

USART guard time and prescaler register

Definition at line 32 of file gd32f10x_usart.h.

#define USART_GP_GUAT BITS(8,15)

guard time value in smartcard mode

Definition at line 96 of file gd32f10x_usart.h.

#define USART_GP_PSC BITS(0,7)

prescaler value for dividing the system clock

Definition at line 95 of file gd32f10x_usart.h.

#define USART_IRLP_LOW CTL2_IRLP(1)

low-power

Definition at line 240 of file gd32f10x_usart.h.

#define USART_IRLP_NORMAL CTL2_IRLP(0)

normal

Definition at line 241 of file gd32f10x_usart.h.

#define USART_LBLEN_10B CTL1_LBLEN(0)

10 bits

Definition at line 200 of file gd32f10x_usart.h.

#define USART_LBLEN_11B CTL1_LBLEN(1)

11 bits

Definition at line 201 of file gd32f10x_usart.h.

#define USART_PM_EVEN CTL0_PM(2)

even parity

Definition at line 178 of file gd32f10x_usart.h.

#define USART_PM_NONE CTL0_PM(0)

no parity

Definition at line 177 of file gd32f10x_usart.h.

#define USART_PM_ODD CTL0_PM(3)

odd parity

Definition at line 179 of file gd32f10x_usart.h.

#define USART_RECEIVE_DISABLE CTL0_REN(0)

disable receiver

Definition at line 168 of file gd32f10x_usart.h.

#define USART_RECEIVE_ENABLE CTL0_REN(1)

enable receiver

Definition at line 167 of file gd32f10x_usart.h.

#define USART_REG_VAL | ( | usartx,
 |  | offset
 | ) | (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))

Definition at line 101 of file gd32f10x_usart.h.

#define USART_REG_VAL2 | ( | usartx,
 |  | offset
 | ) | (REG32((usartx) + ((uint32_t)(offset) >> 22)))

Definition at line 105 of file gd32f10x_usart.h.

#define USART_REGIDX_BIT | ( | regidx,
 |  | bitpos
 | ) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))

Definition at line 100 of file gd32f10x_usart.h.

#define USART_REGIDX_BIT2 | ( | regidx,
 |  | bitpos,
 |  | regidx2,
 |  | bitpos2
 | ) |
Value:
(((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))

Definition at line 103 of file gd32f10x_usart.h.

#define USART_RTS_DISABLE CLT2_RTSEN(0)

RTS disable

Definition at line 231 of file gd32f10x_usart.h.

#define USART_RTS_ENABLE CLT2_RTSEN(1)

RTS enable

Definition at line 230 of file gd32f10x_usart.h.

#define USART_STAT ( usartx ) REG32((usartx) + 0x00U)

USART status register

Definition at line 26 of file gd32f10x_usart.h.

#define USART_STAT_CTSF BIT(9)

CTS change flag

Definition at line 45 of file gd32f10x_usart.h.

#define USART_STAT_FERR BIT(1)

frame error flag

Definition at line 37 of file gd32f10x_usart.h.

#define USART_STAT_IDLEF BIT(4)

IDLE frame detected flag

Definition at line 40 of file gd32f10x_usart.h.

#define USART_STAT_LBDF BIT(8)

LIN break detected flag

Definition at line 44 of file gd32f10x_usart.h.

#define USART_STAT_NERR BIT(2)

noise error flag

Definition at line 38 of file gd32f10x_usart.h.

#define USART_STAT_ORERR BIT(3)

overrun error

Definition at line 39 of file gd32f10x_usart.h.

#define USART_STAT_PERR BIT(0)

parity error flag

Definition at line 36 of file gd32f10x_usart.h.

#define USART_STAT_RBNE BIT(5)

read data buffer not empty

Definition at line 41 of file gd32f10x_usart.h.

#define USART_STAT_REG_OFFSET 0x00U

STAT register offset

Definition at line 109 of file gd32f10x_usart.h.

#define USART_STAT_TBE BIT(7)

transmit data buffer empty

Definition at line 43 of file gd32f10x_usart.h.

#define USART_STAT_TC BIT(6)

transmission complete

Definition at line 42 of file gd32f10x_usart.h.

#define USART_STB_0_5BIT CTL1_STB(1)

0.5 bit

Definition at line 194 of file gd32f10x_usart.h.

#define USART_STB_1_5BIT CTL1_STB(3)

1.5 bits

Definition at line 196 of file gd32f10x_usart.h.

#define USART_STB_1BIT CTL1_STB(0)

1 bit

Definition at line 193 of file gd32f10x_usart.h.

#define USART_STB_2BIT CTL1_STB(2)

2 bits

Definition at line 195 of file gd32f10x_usart.h.

#define USART_TRANSMIT_DISABLE CTL0_TEN(0)

disable transmitter

Definition at line 173 of file gd32f10x_usart.h.

#define USART_TRANSMIT_ENABLE CTL0_TEN(1)

enable transmitter

Definition at line 172 of file gd32f10x_usart.h.

#define USART_WL_8BIT CTL0_WL(0)

8 bits

Definition at line 188 of file gd32f10x_usart.h.

#define USART_WL_9BIT CTL0_WL(1)

9 bits

Definition at line 189 of file gd32f10x_usart.h.

#define USART_WM_ADDR CTL0_WM(1)

address match

Definition at line 184 of file gd32f10x_usart.h.

#define USART_WM_IDLE CTL0_WM(0)

idle line

Definition at line 183 of file gd32f10x_usart.h.

Enumeration Type Documentation

enum usart_flag_enum
Enumerator
USART_FLAG_CTSF | CTS change flag
USART_FLAG_LBDF | LIN break detected flag
USART_FLAG_TBE | transmit data buffer empty
USART_FLAG_TC | transmission complete
USART_FLAG_RBNE | read data buffer not empty
USART_FLAG_IDLEF | IDLE frame detected flag
USART_FLAG_ORERR | overrun error
USART_FLAG_NERR | noise error flag
USART_FLAG_FERR | frame error flag
USART_FLAG_PERR | parity error flag

Definition at line 115 of file gd32f10x_usart.h.

116 {
117 /* flags in STAT register */
118 USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U),
119 USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U),
120 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U),
121 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U),
122 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U),
123 USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U),
124 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U),
125 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U),
126 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U),
127 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U),
128 }usart_flag_enum;
USART_FLAG_CTSF
Definition: gd32f10x_usart.h:118
USART_FLAG_IDLEF
Definition: gd32f10x_usart.h:123
USART_FLAG_TBE
Definition: gd32f10x_usart.h:120
USART_REGIDX_BIT
#define USART_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_usart.h:100
USART_FLAG_TC
Definition: gd32f10x_usart.h:121
USART_FLAG_LBDF
Definition: gd32f10x_usart.h:119
USART_STAT_REG_OFFSET
#define USART_STAT_REG_OFFSET
Definition: gd32f10x_usart.h:109
USART_FLAG_RBNE
Definition: gd32f10x_usart.h:122
USART_FLAG_ORERR
Definition: gd32f10x_usart.h:124
USART_FLAG_PERR
Definition: gd32f10x_usart.h:127
USART_FLAG_NERR
Definition: gd32f10x_usart.h:125
usart_flag_enum
usart_flag_enum
Definition: gd32f10x_usart.h:115
USART_FLAG_FERR
Definition: gd32f10x_usart.h:126
enum usart_interrupt_enum
Enumerator
USART_INT_PERR | parity error interrupt
USART_INT_TBE | transmitter buffer empty interrupt
USART_INT_TC | transmission complete interrupt
USART_INT_RBNE | read data buffer not empty interrupt and overrun error interrupt
USART_INT_IDLE | IDLE line detected interrupt
USART_INT_LBD | LIN break detected interrupt
USART_INT_CTS | CTS interrupt
USART_INT_ERR | error interrupt

Definition at line 150 of file gd32f10x_usart.h.

151 {
152 /* interrupt in CTL0 register */
153 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),
154 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U),
155 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U),
156 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),
157 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),
158 /* interrupt in CTL1 register */
159 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U),
160 /* interrupt in CTL2 register */
161 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U),
162 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),
163 }usart_interrupt_enum;
USART_CTL0_REG_OFFSET
#define USART_CTL0_REG_OFFSET
Definition: gd32f10x_usart.h:110
USART_INT_TC
Definition: gd32f10x_usart.h:155
USART_INT_PERR
Definition: gd32f10x_usart.h:153
USART_INT_LBD
Definition: gd32f10x_usart.h:159
USART_REGIDX_BIT
#define USART_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_usart.h:100
USART_INT_TBE
Definition: gd32f10x_usart.h:154
USART_INT_ERR
Definition: gd32f10x_usart.h:162
USART_INT_CTS
Definition: gd32f10x_usart.h:161
USART_INT_RBNE
Definition: gd32f10x_usart.h:156
USART_CTL1_REG_OFFSET
#define USART_CTL1_REG_OFFSET
Definition: gd32f10x_usart.h:111
USART_CTL2_REG_OFFSET
#define USART_CTL2_REG_OFFSET
Definition: gd32f10x_usart.h:112
USART_INT_IDLE
Definition: gd32f10x_usart.h:157
usart_interrupt_enum
usart_interrupt_enum
Definition: gd32f10x_usart.h:150
enum usart_interrupt_flag_enum
Enumerator
USART_INT_FLAG_PERR | parity error interrupt and flag
USART_INT_FLAG_TBE | transmitter buffer empty interrupt and flag
USART_INT_FLAG_TC | transmission complete interrupt and flag
USART_INT_FLAG_RBNE | read data buffer not empty interrupt and flag
USART_INT_FLAG_RBNE_ORERR | read data buffer not empty interrupt and overrun error flag
USART_INT_FLAG_IDLE | IDLE line detected interrupt and flag
USART_INT_FLAG_LBD | LIN break detected interrupt and flag
USART_INT_FLAG_CTS | CTS interrupt and flag
USART_INT_FLAG_ERR_ORERR | error interrupt and overrun error
USART_INT_FLAG_ERR_NERR | error interrupt and noise error flag
USART_INT_FLAG_ERR_FERR | error interrupt and frame error flag

Definition at line 131 of file gd32f10x_usart.h.

132 {
133 /* interrupt flags in CTL0 register */
134 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U),
135 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U),
136 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U),
137 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U),
138 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U),
139 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U),
140 /* interrupt flags in CTL1 register */
141 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U),
142 /* interrupt flags in CTL2 register */
143 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),
144 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U),
145 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U),
146 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U),
147 }usart_interrupt_flag_enum;
USART_INT_FLAG_LBD
Definition: gd32f10x_usart.h:141
USART_CTL0_REG_OFFSET
#define USART_CTL0_REG_OFFSET
Definition: gd32f10x_usart.h:110
usart_interrupt_flag_enum
usart_interrupt_flag_enum
Definition: gd32f10x_usart.h:131
USART_INT_FLAG_ERR_ORERR
Definition: gd32f10x_usart.h:144
USART_INT_FLAG_ERR_NERR
Definition: gd32f10x_usart.h:145
USART_INT_FLAG_PERR
Definition: gd32f10x_usart.h:134
USART_INT_FLAG_TBE
Definition: gd32f10x_usart.h:135
USART_STAT_REG_OFFSET
#define USART_STAT_REG_OFFSET
Definition: gd32f10x_usart.h:109
USART_INT_FLAG_IDLE
Definition: gd32f10x_usart.h:139
USART_INT_FLAG_RBNE_ORERR
Definition: gd32f10x_usart.h:138
USART_CTL1_REG_OFFSET
#define USART_CTL1_REG_OFFSET
Definition: gd32f10x_usart.h:111
USART_CTL2_REG_OFFSET
#define USART_CTL2_REG_OFFSET
Definition: gd32f10x_usart.h:112
USART_REGIDX_BIT2
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)
Definition: gd32f10x_usart.h:103
USART_INT_FLAG_ERR_FERR
Definition: gd32f10x_usart.h:146
USART_INT_FLAG_CTS
Definition: gd32f10x_usart.h:143
USART_INT_FLAG_RBNE
Definition: gd32f10x_usart.h:137
USART_INT_FLAG_TC
Definition: gd32f10x_usart.h:136

Function Documentation

void usart_address_config | ( | uint32_t | usart_periph,
 |  | uint8_t | addr
 | ) |  |

configure the address of the USART in wake up by address match mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] | addr | address of USART/UART
[out] | none
Return values
none

Definition at line 231 of file gd32f10x_usart.c.

232 {
233 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
234 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr);
235 }
USART_CTL1_ADDR
#define USART_CTL1_ADDR
Definition: gd32f10x_usart.h:71
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
void usart_baudrate_set | ( | uint32_t | usart_periph,
 |  | uint32_t | baudval
 | ) |  |

configure USART baud rate value

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] | baudval | baud rate value
[out] | none
Return values
none

Definition at line 56 of file gd32f10x_usart.c.

57 {
58 uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U;
59 switch(usart_periph){
60 case USART0:
61 /* get clock frequency */
62 uclk=rcu_clock_freq_get(CK_APB2);
63 break;
64 case USART1:
65 uclk=rcu_clock_freq_get(CK_APB1);
66 break;
67 case USART2:
68 uclk=rcu_clock_freq_get(CK_APB1);
69 break;
70 case UART3:
71 uclk=rcu_clock_freq_get(CK_APB1);
72 break;
73 case UART4:
74 uclk=rcu_clock_freq_get(CK_APB1);
75 break;
76 default:
77 break;
78 }
79 /* oversampling by 16, configure the value of USART_BAUD */
80 udiv = (uclk+baudval/2U)/baudval;
81 intdiv = udiv & 0xfff0U;
82 fradiv = udiv & 0xfU;
83 USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
84 }
USART0
#define USART0
Definition: gd32f10x_usart.h:23
UART3
#define UART3
Definition: gd32f10x_usart.h:21
USART_BAUD
#define USART_BAUD(usartx)
Definition: gd32f10x_usart.h:28
USART_BAUD_FRADIV
#define USART_BAUD_FRADIV
Definition: gd32f10x_usart.h:51
USART_BAUD_INTDIV
#define USART_BAUD_INTDIV
Definition: gd32f10x_usart.h:52
USART1
#define USART1
Definition: gd32f10x_usart.h:19
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
CK_APB2
Definition: gd32f10x_rcu.h:587
CK_APB1
Definition: gd32f10x_rcu.h:586
USART2
#define USART2
Definition: gd32f10x_usart.h:20
UART4
#define UART4
Definition: gd32f10x_usart.h:22
uint16_t usart_data_receive ( uint32_t usart_periph )

USART receive data function.

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
data of received

Definition at line 219 of file gd32f10x_usart.c.

220 {
221 return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U));
222 }
USART_DATA
#define USART_DATA(usartx)
Definition: gd32f10x_usart.h:27
void usart_data_transmit | ( | uint32_t | usart_periph,
 |  | uint32_t | data
 | ) |  |

USART transmit data function.

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] | data | data of transmission
[out] | none
Return values
none

Definition at line 208 of file gd32f10x_usart.c.

209 {
210 USART_DATA(usart_periph) = USART_DATA_DATA & data;
211 }
USART_DATA
#define USART_DATA(usartx)
Definition: gd32f10x_usart.h:27
USART_DATA_DATA
#define USART_DATA_DATA
Definition: gd32f10x_usart.h:48
void usart_deinit ( uint32_t usart_periph )

reset USART/UART

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_usart.c.

22 {
23 switch(usart_periph){
24 case USART0:
25 rcu_periph_reset_enable(RCU_USART0RST);
26 rcu_periph_reset_disable(RCU_USART0RST);
27 break;
28 case USART1:
29 rcu_periph_reset_enable(RCU_USART1RST);
30 rcu_periph_reset_disable(RCU_USART1RST);
31 break;
32 case USART2:
33 rcu_periph_reset_enable(RCU_USART2RST);
34 rcu_periph_reset_disable(RCU_USART2RST);
35 break;
36 case UART3:
37 rcu_periph_reset_enable(RCU_UART3RST);
38 rcu_periph_reset_disable(RCU_UART3RST);
39 break;
40 case UART4:
41 rcu_periph_reset_enable(RCU_UART4RST);
42 rcu_periph_reset_disable(RCU_UART4RST);
43 break;
44 default:
45 break;
46 }
47 }
RCU_USART1RST
Definition: gd32f10x_rcu.h:459
USART0
#define USART0
Definition: gd32f10x_usart.h:23
UART3
#define UART3
Definition: gd32f10x_usart.h:21
USART1
#define USART1
Definition: gd32f10x_usart.h:19
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
RCU_USART0RST
Definition: gd32f10x_rcu.h:490
RCU_USART2RST
Definition: gd32f10x_rcu.h:460
RCU_UART4RST
Definition: gd32f10x_rcu.h:462
USART2
#define USART2
Definition: gd32f10x_usart.h:20
UART4
#define UART4
Definition: gd32f10x_usart.h:22
RCU_UART3RST
Definition: gd32f10x_rcu.h:461
void usart_disable ( uint32_t usart_periph )

disable USART

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 156 of file gd32f10x_usart.c.

157 {
158 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
159 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f10x_usart.h:68
void usart_dma_receive_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dmacmd
 | ) |  |

configure USART DMA reception

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3)
[in] dmacmd enable or disable DMA for reception
  • USART_DENR_ENABLE: DMA enable for reception
  • USART_DENR_DISABLE: DMA disable for reception
[out] | none
Return values
none

Definition at line 549 of file gd32f10x_usart.c.

550 {
551 uint32_t ctl = 0U;
552
553 ctl = USART_CTL2(usart_periph);
554 ctl &= ~USART_CTL2_DENR;
555 ctl |= dmacmd;
556 /* configure DMA reception */
557 USART_CTL2(usart_periph) = ctl;
558 }
USART_CTL2_DENR
#define USART_CTL2_DENR
Definition: gd32f10x_usart.h:88
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_dma_transmit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dmacmd
 | ) |  |

configure USART DMA transmission

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3)
[in] dmacmd enable or disable DMA for transmission
  • USART_DENT_ENABLE: DMA enable for transmission
  • USART_DENT_DISABLE: DMA disable for transmission
[out] | none
Return values
none

Definition at line 569 of file gd32f10x_usart.c.

570 {
571 uint32_t ctl = 0U;
572
573 ctl = USART_CTL2(usart_periph);
574 ctl &= ~USART_CTL2_DENT;
575 ctl |= dmacmd;
576 /* configure DMA transmission */
577 USART_CTL2(usart_periph) = ctl;
578 }
USART_CTL2_DENT
#define USART_CTL2_DENT
Definition: gd32f10x_usart.h:89
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_enable ( uint32_t usart_periph )

enable USART

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 145 of file gd32f10x_usart.c.

146 {
147 USART_CTL0(usart_periph) |= USART_CTL0_UEN;
148 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f10x_usart.h:68
void usart_flag_clear | ( | uint32_t | usart_periph,
 |  | usart_flag_enum | flag
 | ) |  |

clear flag in STAT register

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] flag USART flags, refer to usart_flag_enum only one among these parameters can be selected
  • USART_FLAG_CTSF: CTS change flag
  • USART_FLAG_LBDF: LIN break detected flag
  • USART_FLAG_TC: transmission complete
  • USART_FLAG_RBNE: read data buffer not empty
[out] | none
Return values
none

Definition at line 619 of file gd32f10x_usart.c.

620 {
621 USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag));
622 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
FlagStatus usart_flag_get | ( | uint32_t | usart_periph,
 |  | usart_flag_enum | flag
 | ) |  |

get flag in STAT register

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] flag USART flags, refer to usart_flag_enum only one among these parameters can be selected
  • USART_FLAG_CTSF: CTS change flag
  • USART_FLAG_LBDF: LIN break detected flag
  • USART_FLAG_TBE: transmit data buffer empty
  • USART_FLAG_TC: transmission complete
  • USART_FLAG_RBNE: read data buffer not empty
  • USART_FLAG_IDLEF: IDLE frame detected flag
  • USART_FLAG_ORERR: overrun error
  • USART_FLAG_NERR: noise error flag
  • USART_FLAG_FERR: frame error flag
  • USART_FLAG_PERR: parity error flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 598 of file gd32f10x_usart.c.

599 {
600 if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
601 return SET;
602 }else{
603 return RESET;
604 }
605 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
void usart_guard_time_config | ( | uint32_t | usart_periph,
 |  | uint32_t | gaut
 | ) |  |

configure guard time value in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[in] | gaut | guard time value
[out] | none
Return values
none

Definition at line 400 of file gd32f10x_usart.c.

401 {
402 USART_GP(usart_periph) &= ~(USART_GP_GUAT);
403 USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8));
404 }
USART_GP_GUAT
#define USART_GP_GUAT
Definition: gd32f10x_usart.h:96
USART_GP
#define USART_GP(usartx)
Definition: gd32f10x_usart.h:32
void usart_halfduplex_disable ( uint32_t usart_periph )

disable half duplex mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 339 of file gd32f10x_usart.c.

340 {
341 USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
342 }
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f10x_usart.h:85
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_halfduplex_enable ( uint32_t usart_periph )

enable half duplex mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 328 of file gd32f10x_usart.c.

329 {
330 USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
331 }
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f10x_usart.h:85
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_hardware_flow_cts_config | ( | uint32_t | usart_periph,
 |  | uint32_t | ctsconfig
 | ) |  |

configure hardware flow control CTS

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[in] hardwareflow enable or disable CTS
  • USART_CTS_ENABLE: enable CTS
  • USART_CTS_DISABLE: disable CTS
[out] | none
Return values
none

Definition at line 529 of file gd32f10x_usart.c.

530 {
531 uint32_t ctl = 0U;
532
533 ctl = USART_CTL2(usart_periph);
534 ctl &= ~USART_CTL2_CTSEN;
535 ctl |= ctsconfig;
536 /* configure CTS */
537 USART_CTL2(usart_periph) = ctl;
538 }
USART_CTL2_CTSEN
#define USART_CTL2_CTSEN
Definition: gd32f10x_usart.h:91
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_hardware_flow_rts_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rtsconfig
 | ) |  |

configure hardware flow control RTS

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[in] hardwareflow enable or disable RTS
  • USART_RTS_ENABLE: enable RTS
  • USART_RTS_DISABLE: disable RTS
[out] | none
Return values
none

Definition at line 509 of file gd32f10x_usart.c.

510 {
511 uint32_t ctl = 0U;
512
513 ctl = USART_CTL2(usart_periph);
514 ctl &= ~USART_CTL2_RTSEN;
515 ctl |= rtsconfig;
516 /* configure RTS */
517 USART_CTL2(usart_periph) = ctl;
518 }
USART_CTL2_RTSEN
#define USART_CTL2_RTSEN
Definition: gd32f10x_usart.h:90
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_interrupt_disable | ( | uint32_t | usart_periph,
 |  | uint32_t | int_flag
 | ) |  |

disable USART interrupt

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] int_flag
  • USART_INT_PERR: parity error interrupt
  • USART_INT_TBE: transmitter buffer empty interrupt
  • USART_INT_TC: transmission complete interrupt
  • USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
  • USART_INT_IDLE: IDLE line detected interrupt
  • USART_INT_LBD: LIN break detected interrupt
  • USART_INT_ERR: error interrupt
  • USART_INT_CTS: CTS interrupt
[out] | none
Return values
none

Definition at line 659 of file gd32f10x_usart.c.

660 {
661 USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag));
662 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
void usart_interrupt_enable | ( | uint32_t | usart_periph,
 |  | uint32_t | int_flag
 | ) |  |

enable USART interrupt

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] int_flag
  • USART_INT_PERR: parity error interrupt
  • USART_INT_TBE: transmitter buffer empty interrupt
  • USART_INT_TC: transmission complete interrupt
  • USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
  • USART_INT_IDLE: IDLE line detected interrupt
  • USART_INT_LBD: LIN break detected interrupt
  • USART_INT_ERR: error interrupt
  • USART_INT_CTS: CTS interrupt
[out] | none
Return values
none

Definition at line 639 of file gd32f10x_usart.c.

640 {
641 USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag));
642 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
void usart_interrupt_flag_clear | ( | uint32_t | usart_periph,
 |  | uint32_t | flag
 | ) |  |

clear USART interrupt flag in STAT register

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] flag USART interrupt flag
  • USART_INT_FLAG_CTS: CTS change flag
  • USART_INT_FLAG_LBD: LIN break detected flag
  • USART_INT_FLAG_TC: transmission complete
  • USART_INT_FLAG_RBNE: read data buffer not empty
[out] | none
Return values
none

Definition at line 708 of file gd32f10x_usart.c.

709 {
710 USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag));
711 }
USART_REG_VAL2
#define USART_REG_VAL2(usartx, offset)
Definition: gd32f10x_usart.h:105
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f10x_usart.h:106
FlagStatus usart_interrupt_flag_get | ( | uint32_t | usart_periph,
 |  | uint32_t | int_flag
 | ) |  |

get USART interrupt and flag status

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] int_flag
  • USART_INT_FLAG_PERR: parity error interrupt and flag
  • USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag
  • USART_INT_FLAG_TC: transmission complete interrupt and flag
  • USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
  • USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
  • USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
  • USART_INT_FLAG_LBD: LIN break detected interrupt and flag
  • USART_INT_FLAG_CTS: CTS interrupt and flag
  • USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
  • USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
  • USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
[out] | none
Return values
FlagStatus

Definition at line 682 of file gd32f10x_usart.c.

683 {
684 uint32_t intenable = 0U, flagstatus = 0U;
685 /* get the interrupt enable bit status */
686 intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
687 /* get the corresponding flag bit status */
688 flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
689
690 if(flagstatus && intenable){
691 return SET;
692 }else{
693 return RESET;
694 }
695 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL2
#define USART_REG_VAL2(usartx, offset)
Definition: gd32f10x_usart.h:105
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f10x_usart.h:106
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
void usart_irda_lowpower_config | ( | uint32_t | usart_periph,
 |  | uint32_t | irlp
 | ) |  |

configure IrDA low-power

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] irlp IrDA low-power or normal
  • USART_IRLP_LOW: low-power
  • USART_IRLP_NORMAL: normal
[out] | none
Return values
none

Definition at line 494 of file gd32f10x_usart.c.

495 {
496 USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP);
497 USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
498 }
USART_CTL2_IRLP
#define USART_CTL2_IRLP
Definition: gd32f10x_usart.h:84
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_irda_mode_disable ( uint32_t usart_periph )

disable IrDA mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 467 of file gd32f10x_usart.c.

468 {
469 USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
470 }
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f10x_usart.h:83
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_irda_mode_enable ( uint32_t usart_periph )

enable IrDA mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 456 of file gd32f10x_usart.c.

457 {
458 USART_CTL2(usart_periph) |= USART_CTL2_IREN;
459 }
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f10x_usart.h:83
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_lin_break_dection_length_config | ( | uint32_t | usart_periph,
 |  | uint32_t | lblen
 | ) |  |

configure lin break frame length

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] lblen lin break frame length
  • USART_LBLEN_10B: 10 bits
  • USART_LBLEN_11B: 11 bits
[out] | none
Return values
none

Definition at line 305 of file gd32f10x_usart.c.

306 {
307 USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN);
308 USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen);
309 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_LBLEN
#define USART_CTL1_LBLEN
Definition: gd32f10x_usart.h:72
void usart_lin_mode_disable ( uint32_t usart_periph )

disable LIN mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 291 of file gd32f10x_usart.c.

292 {
293 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
294 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f10x_usart.h:79
void usart_lin_mode_enable ( uint32_t usart_periph )

enable LIN mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 280 of file gd32f10x_usart.c.

281 {
282 USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
283 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f10x_usart.h:79
void usart_mute_mode_disable ( uint32_t usart_periph )

receiver in active mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 254 of file gd32f10x_usart.c.

255 {
256 USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU);
257 }
USART_CTL0_RWU
#define USART_CTL0_RWU
Definition: gd32f10x_usart.h:56
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
void usart_mute_mode_enable ( uint32_t usart_periph )

receiver in mute mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 243 of file gd32f10x_usart.c.

244 {
245 USART_CTL0(usart_periph) |= USART_CTL0_RWU;
246 }
USART_CTL0_RWU
#define USART_CTL0_RWU
Definition: gd32f10x_usart.h:56
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
void usart_mute_mode_wakeup_config | ( | uint32_t | usart_periph,
 |  | uint32_t | wmethod
 | ) |  |

configure wakeup method in mute mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] wmethod two methods be used to enter or exit the mute mode
  • USART_WM_IDLE: idle line
  • USART_WM_ADDR: address mask
[out] | none
Return values
none

Definition at line 268 of file gd32f10x_usart.c.

269 {
270 USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
271 USART_CTL0(usart_periph) |= wmethod;
272 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_WM
#define USART_CTL0_WM
Definition: gd32f10x_usart.h:66
void usart_parity_config | ( | uint32_t | usart_periph,
 |  | uint32_t | paritycfg
 | ) |  |

configure USART parity

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] paritycfg configure USART parity
  • USART_PM_NONE: no parity
  • USART_PM_ODD: odd parity
  • USART_PM_EVEN: even parity
[out] | none
Return values
none

Definition at line 96 of file gd32f10x_usart.c.

97 {
98 /* clear USART_CTL0 PM,PCEN bits */
99 USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
100 /* configure USART parity mode */
101 USART_CTL0(usart_periph) |= paritycfg ;
102 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_PM
#define USART_CTL0_PM
Definition: gd32f10x_usart.h:64
USART_CTL0_PCEN
#define USART_CTL0_PCEN
Definition: gd32f10x_usart.h:65
void usart_prescaler_config | ( | uint32_t | usart_periph,
 |  | uint8_t | psc
 | ) |  |

configure the peripheral clock prescaler in USART IrDA low-power mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] | psc | 0x00-0xFF
[out] | none
Return values
none

Definition at line 479 of file gd32f10x_usart.c.

480 {
481 USART_GP(usart_periph) &= ~(USART_GP_PSC);
482 USART_GP(usart_periph) |= psc;
483 }
USART_GP_PSC
#define USART_GP_PSC
Definition: gd32f10x_usart.h:95
USART_GP
#define USART_GP(usartx)
Definition: gd32f10x_usart.h:32
void usart_receive_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rxconfig
 | ) |  |

configure USART receiver

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] rxconfig enable or disable USART receiver
  • USART_RECEIVE_ENABLE: enable USART reception
  • USART_RECEIVE_DISABLE: disable USART reception
[out] | none
Return values
none

Definition at line 190 of file gd32f10x_usart.c.

191 {
192 uint32_t ctl = 0U;
193
194 ctl = USART_CTL0(usart_periph);
195 ctl &= ~USART_CTL0_REN;
196 ctl |= rxconfig;
197 /* configure transfer mode */
198 USART_CTL0(usart_periph) = ctl;
199 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_REN
#define USART_CTL0_REN
Definition: gd32f10x_usart.h:57
void usart_send_break ( uint32_t usart_periph )

send break frame

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 317 of file gd32f10x_usart.c.

318 {
319 USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD;
320 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_SBKCMD
#define USART_CTL0_SBKCMD
Definition: gd32f10x_usart.h:55
void usart_smartcard_mode_disable ( uint32_t usart_periph )

disable smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 423 of file gd32f10x_usart.c.

424 {
425 USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
426 }
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f10x_usart.h:87
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_smartcard_mode_enable ( uint32_t usart_periph )

enable smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 412 of file gd32f10x_usart.c.

413 {
414 USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
415 }
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f10x_usart.h:87
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_smartcard_mode_nack_disable ( uint32_t usart_periph )

disable NACK in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 445 of file gd32f10x_usart.c.

446 {
447 USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
448 }
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f10x_usart.h:86
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_smartcard_mode_nack_enable ( uint32_t usart_periph )

enable NACK in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 434 of file gd32f10x_usart.c.

435 {
436 USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
437 }
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f10x_usart.h:86
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_stop_bit_set | ( | uint32_t | usart_periph,
 |  | uint32_t | stblen
 | ) |  |

configure USART stop bit length

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] stblen USART stop bit configure
  • USART_STB_1BIT: 1 bit
  • USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4)
  • USART_STB_2BIT: 2 bits
  • USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 132 of file gd32f10x_usart.c.

133 {
134 /* clear USART_CTL1 STB bits */
135 USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
136 /* configure USART stop bits */
137 USART_CTL1(usart_periph) |= stblen;
138 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_STB
#define USART_CTL1_STB
Definition: gd32f10x_usart.h:78
void usart_synchronous_clock_config | ( | uint32_t | usart_periph,
 |  | uint32_t | clen,
 |  | uint32_t | cph,
 |  | uint32_t | cpl
 | ) |  |

configure USART synchronous mode parameters

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[in] clen CK length
  • USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame
  • USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame
[in] cph clock phase
  • USART_CPH_1CK: first clock transition is the first data capture edge
  • USART_CPH_2CK: second clock transition is the first data capture edge
[in] cpl clock polarity
  • USART_CPL_LOW: steady low value on CK pin
  • USART_CPL_HIGH: steady high value on CK pin
[out] | none
Return values
none

Definition at line 381 of file gd32f10x_usart.c.

382 {
383 uint32_t ctl = 0U;
384
385 /* read USART_CTL1 register */
386 ctl = USART_CTL1(usart_periph);
387 /* set CK length, CK phase, CK polarity */
388 ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl);
389
390 USART_CTL1(usart_periph) |= ctl;
391 }
USART_CTL1_CPH
#define USART_CTL1_CPH
Definition: gd32f10x_usart.h:75
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_CLEN
#define USART_CTL1_CLEN
Definition: gd32f10x_usart.h:74
USART_CTL1_CPL
#define USART_CTL1_CPL
Definition: gd32f10x_usart.h:76
void usart_synchronous_clock_disable ( uint32_t usart_periph )

disable CK pin in synchronous mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 361 of file gd32f10x_usart.c.

362 {
363 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
364 }
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f10x_usart.h:77
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
void usart_synchronous_clock_enable ( uint32_t usart_periph )

enable CK pin in synchronous mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 350 of file gd32f10x_usart.c.

351 {
352 USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
353 }
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f10x_usart.h:77
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
void usart_transmit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | txconfig
 | ) |  |

configure USART transmitter

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] txconfig enable or disable USART transmitter
  • USART_TRANSMIT_ENABLE: enable USART transmission
  • USART_TRANSMIT_DISABLE: enable USART transmission
[out] | none
Return values
none

Definition at line 170 of file gd32f10x_usart.c.

171 {
172 uint32_t ctl = 0U;
173
174 ctl = USART_CTL0(usart_periph);
175 ctl &= ~USART_CTL0_TEN;
176 ctl |= txconfig;
177 /* configure transfer mode */
178 USART_CTL0(usart_periph) = ctl;
179 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_TEN
#define USART_CTL0_TEN
Definition: gd32f10x_usart.h:58
void usart_word_length_set | ( | uint32_t | usart_periph,
 |  | uint32_t | wlen
 | ) |  |

configure USART word length

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] wlen USART word length configure
  • USART_WL_8BIT: 8 bits
  • USART_WL_9BIT: 9 bits
[out] | none
Return values
none

Definition at line 113 of file gd32f10x_usart.c.

114 {
115 /* clear USART_CTL0 WL bit */
116 USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
117 /* configure USART word length */
118 USART_CTL0(usart_periph) |= wlen;
119 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_WL
#define USART_CTL0_WL
Definition: gd32f10x_usart.h:67
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
Macros | Functions
gd32f10x_wwdgt.h File Reference

definitions for the WWDGT More...

#include "gd32f10x.h"

Go to the source code of this file.

Macros

#define | WWDGT WWDGT_BASE
#define | WWDGT_CTL REG32((WWDGT) + 0x00U)
#define | WWDGT_CFG REG32((WWDGT) + 0x04U)
#define | WWDGT_STAT REG32((WWDGT) + 0x08U)
#define | WWDGT_CTL_CNT BITS(0,6)
#define | WWDGT_CTL_WDGTEN BIT(7)
#define | WWDGT_CFG_WIN BITS(0,6)
#define | WWDGT_CFG_PSC BITS(7,8)
#define | WWDGT_CFG_EWIE BIT(9)
#define | WWDGT_STAT_EWIF BIT(0)
#define | CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7))
#define | WWDGT_CFG_PSC_DIV1 CFG_PSC(0)
#define | WWDGT_CFG_PSC_DIV2 CFG_PSC(1)
#define | WWDGT_CFG_PSC_DIV4 CFG_PSC(2)
#define | WWDGT_CFG_PSC_DIV8 CFG_PSC(3)

Functions

void | wwdgt_deinit (void)
reset the window watchdog timer configuration More...
void | wwdgt_enable (void)
start the window watchdog timer counter More...
void | wwdgt_counter_update (uint16_t counter_value)
configure the window watchdog timer counter value More...
void | wwdgt_config (uint16_t counter, uint16_t window, uint32_t prescaler)
configure counter value, window value, and prescaler divider value More...
void | wwdgt_interrupt_enable (void)
enable early wakeup interrupt of WWDGT More...
FlagStatus | wwdgt_flag_get (void)
check early wakeup interrupt state of WWDGT More...
void | wwdgt_flag_clear (void)
clear early wakeup interrupt state of WWDGT More...

Detailed Description

definitions for the WWDGT

Definition in file gd32f10x_wwdgt.h.

Macro Definition Documentation

#define CFG_PSC ( regval ) (BITS(7,8) & ((uint32_t)(regval) << 7))

write value to WWDGT_CFG_PSC bit field

Definition at line 40 of file gd32f10x_wwdgt.h.

#define WWDGT WWDGT_BASE

WWDGT base address

Definition at line 19 of file gd32f10x_wwdgt.h.

#define WWDGT_CFG REG32((WWDGT) + 0x04U)

WWDGT configuration register

Definition at line 23 of file gd32f10x_wwdgt.h.

#define WWDGT_CFG_EWIE BIT(9)

early wakeup interrupt enable

Definition at line 34 of file gd32f10x_wwdgt.h.

#define WWDGT_CFG_PSC BITS(7,8)

WWDGT prescaler divider value

Definition at line 33 of file gd32f10x_wwdgt.h.

#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0)

the time base of WWDGT = (PCLK1/4096)/1

Definition at line 41 of file gd32f10x_wwdgt.h.

#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1)

the time base of WWDGT = (PCLK1/4096)/2

Definition at line 42 of file gd32f10x_wwdgt.h.

#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2)

the time base of WWDGT = (PCLK1/4096)/4

Definition at line 43 of file gd32f10x_wwdgt.h.

#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3)

the time base of WWDGT = (PCLK1/4096)/8

Definition at line 44 of file gd32f10x_wwdgt.h.

#define WWDGT_CFG_WIN BITS(0,6)

WWDGT counter window value

Definition at line 32 of file gd32f10x_wwdgt.h.

#define WWDGT_CTL REG32((WWDGT) + 0x00U)

WWDGT control register

Definition at line 22 of file gd32f10x_wwdgt.h.

#define WWDGT_CTL_CNT BITS(0,6)

WWDGT counter value

Definition at line 28 of file gd32f10x_wwdgt.h.

#define WWDGT_CTL_WDGTEN BIT(7)

WWDGT counter enable

Definition at line 29 of file gd32f10x_wwdgt.h.

#define WWDGT_STAT REG32((WWDGT) + 0x08U)

WWDGT status register

Definition at line 24 of file gd32f10x_wwdgt.h.

#define WWDGT_STAT_EWIF BIT(0)

early wakeup interrupt flag

Definition at line 37 of file gd32f10x_wwdgt.h.

Function Documentation

void wwdgt_config | ( | uint16_t | counter,
 |  | uint16_t | window,
 |  | uint32_t | prescaler
 | ) |  |

configure counter value, window value, and prescaler divider value

Parameters
[in] | counter | 0x00 - 0x7F
[in] | window | 0x00 - 0x7F
[in] prescaler wwdgt prescaler value
  • WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
  • WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
  • WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
  • WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
[out] | none
Return values
none

Definition at line 71 of file gd32f10x_wwdgt.c.

72 {
73 uint32_t reg_cfg = 0U, reg_ctl = 0U;
74
75 /* clear WIN and PSC bits, clear CNT bit */
76 reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
77 reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
78
79 /* configure WIN and PSC bits, configure CNT bit */
80 reg_cfg |= CFG_WIN(window);
81 reg_cfg |= prescaler;
82 reg_ctl |= CTL_CNT(counter);
83
84 WWDGT_CTL = reg_ctl;
85 WWDGT_CFG = reg_cfg;
86 }
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f10x_wwdgt.h:28
CFG_WIN
#define CFG_WIN(regval)
Definition: gd32f10x_wwdgt.c:18
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f10x_wwdgt.h:23
WWDGT_CFG_PSC
#define WWDGT_CFG_PSC
Definition: gd32f10x_wwdgt.h:33
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f10x_wwdgt.c:16
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f10x_wwdgt.h:22
WWDGT_CFG_WIN
#define WWDGT_CFG_WIN
Definition: gd32f10x_wwdgt.h:32
void wwdgt_counter_update ( uint16_t counter_value )

configure the window watchdog timer counter value

Parameters
[in] | counter_value | 0x00 - 0x7F
[out] | none
Return values
none

Definition at line 38 of file gd32f10x_wwdgt.c.

39 {
40 uint32_t reg = 0U;
41
42 reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
43 reg |= CTL_CNT(counter_value);
44
45 WWDGT_CTL = reg;
46 }
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f10x_wwdgt.h:28
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f10x_wwdgt.c:16
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f10x_wwdgt.h:22
void wwdgt_deinit ( void )

reset the window watchdog timer configuration

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 26 of file gd32f10x_wwdgt.c.

27 {
28 rcu_periph_reset_enable(RCU_WWDGTRST);
29 rcu_periph_reset_disable(RCU_WWDGTRST);
30 }
RCU_WWDGTRST
Definition: gd32f10x_rcu.h:456
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void wwdgt_enable ( void )

start the window watchdog timer counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 54 of file gd32f10x_wwdgt.c.

55 {
56 WWDGT_CTL |= WWDGT_CTL_WDGTEN;
57 }
WWDGT_CTL_WDGTEN
#define WWDGT_CTL_WDGTEN
Definition: gd32f10x_wwdgt.h:29
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f10x_wwdgt.h:22
void wwdgt_flag_clear ( void )

clear early wakeup interrupt state of WWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 120 of file gd32f10x_wwdgt.c.

121 {
122 WWDGT_STAT &= (~WWDGT_STAT_EWIF);
123 }
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f10x_wwdgt.h:37
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f10x_wwdgt.h:24
FlagStatus wwdgt_flag_get ( void )

check early wakeup interrupt state of WWDGT

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 105 of file gd32f10x_wwdgt.c.

106 {
107 if(WWDGT_STAT & WWDGT_STAT_EWIF){
108 return SET;
109 }
110
111 return RESET;
112 }
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f10x_wwdgt.h:37
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f10x_wwdgt.h:24
void wwdgt_interrupt_enable ( void )

enable early wakeup interrupt of WWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 94 of file gd32f10x_wwdgt.c.

95 {
96 WWDGT_CFG |= WWDGT_CFG_EWIE;
97 }
WWDGT_CFG_EWIE
#define WWDGT_CFG_EWIE
Definition: gd32f10x_wwdgt.h:34
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f10x_wwdgt.h:23
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Source Directory Reference

Files

file | gd32f10x_adc.c [code]
ADC driver.
file | gd32f10x_bkp.c [code]
BKP driver.
file | gd32f10x_can.c [code]
CAN driver.
file | gd32f10x_crc.c [code]
CRC driver.
file | gd32f10x_dac.c [code]
DAC driver.
file | gd32f10x_dbg.c [code]
DBG driver.
file | gd32f10x_dma.c [code]
DMA driver.
file | gd32f10x_enet.c [code]
ENET driver.
file | gd32f10x_exmc.c [code]
EXMC driver.
file | gd32f10x_exti.c [code]
EXTI driver.
file | gd32f10x_fmc.c [code]
FMC driver.
file | gd32f10x_fwdgt.c [code]
FWDGT driver.
file | gd32f10x_gpio.c [code]
GPIO driver.
file | gd32f10x_i2c.c [code]
I2C driver.
file | gd32f10x_misc.c [code]
MISC driver.
file | gd32f10x_pmu.c [code]
PMU driver.
file | gd32f10x_rcu.c [code]
RCU driver.
file | gd32f10x_rtc.c [code]
RTC driver.
file | gd32f10x_sdio.c [code]
SDIO driver.
file | gd32f10x_spi.c [code]
SPI driver.
file | gd32f10x_timer.c [code]
TIMER driver.
file | gd32f10x_usart.c [code]
USART driver.
file | gd32f10x_wwdgt.c [code]
WWDGT driver.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_adc.c File Reference

ADC driver. More...

#include "gd32f10x_adc.h"

Go to the source code of this file.

Functions

void | adc_deinit (uint32_t adc_periph)
reset ADC More...
void | adc_enable (uint32_t adc_periph)
enable ADC interface More...
void | adc_disable (uint32_t adc_periph)
disable ADC interface More...
void | adc_calibration_enable (uint32_t adc_periph)
ADC calibration and reset calibration. More...
void | adc_dma_mode_enable (uint32_t adc_periph)
enable DMA request More...
void | adc_dma_mode_disable (uint32_t adc_periph)
disable DMA request More...
void | adc_tempsensor_vrefint_enable (void)
enable the temperature sensor and Vrefint channel More...
void | adc_tempsensor_vrefint_disable (void)
disable the temperature sensor and Vrefint channel More...
void | adc_discontinuous_mode_config (uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
configure ADC discontinuous mode More...
void | adc_mode_config (uint32_t mode)
configure the ADC sync mode More...
void | adc_special_function_config (uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
enable or disable ADC special function More...
void | adc_data_alignment_config (uint32_t adc_periph, uint32_t data_alignment)
configure ADC data alignment More...
void | adc_channel_length_config (uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
configure the length of regular channel group or inserted channel group More...
void | adc_regular_channel_config (uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
configure ADC regular channel More...
void | adc_inserted_channel_config (uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
configure ADC inserted channel More...
void | adc_inserted_channel_offset_config (uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
configure ADC inserted channel offset More...
void | adc_external_trigger_config (uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
enable ADC external trigger More...
void | adc_external_trigger_source_config (uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
configure ADC external trigger source More...
void | adc_software_trigger_enable (uint32_t adc_periph, uint8_t adc_channel_group)
enable ADC software trigger More...
FlagStatus | adc_regular_software_startconv_flag_get (uint32_t adc_periph)
get the bit state of ADCx software start conversion More...
FlagStatus | adc_inserted_software_startconv_flag_get (uint32_t adc_periph)
get the bit state of ADCx software inserted channel start conversion More...
uint16_t | adc_regular_data_read (uint32_t adc_periph)
read ADC regular group data register More...
uint16_t | adc_inserted_data_read (uint32_t adc_periph, uint8_t inserted_channel)
read ADC inserted group data register More...
uint32_t | adc_sync_mode_convert_value_read (void)
read the last ADC0 and ADC1 conversion result data in sync mode More...
FlagStatus | adc_flag_get (uint32_t adc_periph, uint32_t adc_flag)
get the ADC flag bits More...
void | adc_flag_clear (uint32_t adc_periph, uint32_t adc_flag)
clear the ADC flag bits More...
FlagStatus | adc_interrupt_flag_get (uint32_t adc_periph, uint32_t adc_interrupt)
get the ADC interrupt bits More...
void | adc_interrupt_flag_clear (uint32_t adc_periph, uint32_t adc_interrupt)
clear the ADC flag More...
void | adc_interrupt_enable (uint32_t adc_periph, uint32_t adc_interrupt)
enable ADC interrupt More...
void | adc_interrupt_disable (uint32_t adc_periph, uint32_t adc_interrupt)
disable ADC interrupt More...
void | adc_watchdog_single_channel_enable (uint32_t adc_periph, uint8_t adc_channel)
configure ADC analog watchdog single channel More...
void | adc_watchdog_group_channel_enable (uint32_t adc_periph, uint8_t adc_channel_group)
configure ADC analog watchdog group channel More...
void | adc_watchdog_disable (uint32_t adc_periph)
disable ADC analog watchdog More...
void | adc_watchdog_threshold_config (uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
configure ADC analog watchdog threshold More...

Detailed Description

ADC driver.

Definition in file gd32f10x_adc.c.

Function Documentation

void adc_calibration_enable ( uint32_t adc_periph )

ADC calibration and reset calibration.

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 77 of file gd32f10x_adc.c.

78 {
79 /* reset the selected ADC1 calibration registers */
80 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
81 /* check the RSTCLB bit state */
82 while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
83 }
84 /* enable ADC calibration process */
85 ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
86 /* check the CLB bit state */
87 while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
88 }
89 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_RSTCLB
#define ADC_CTL1_RSTCLB
Definition: gd32f10x_adc.h:73
ADC_CTL1_CLB
#define ADC_CTL1_CLB
Definition: gd32f10x_adc.h:72
void adc_channel_length_config | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group,
 |  | uint32_t | length
 | ) |  |

configure the length of regular channel group or inserted channel group

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] | length | the length of the channel regular channel 1-16 inserted channel 1-4
[out] | none
Return values
none

Definition at line 268 of file gd32f10x_adc.c.

269 {
270 switch(adc_channel_group){
271 case ADC_REGULAR_CHANNEL:
272 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
273 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U));
274
275 break;
276 case ADC_INSERTED_CHANNEL:
277 ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
278 ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-1U));
279
280 break;
281 default:
282 break;
283 }
284 }
RSQ0_RL
#define RSQ0_RL(regval)
Definition: gd32f10x_adc.h:204
ADC_RSQ0_RL
#define ADC_RSQ0_RL
Definition: gd32f10x_adc.h:98
ADC_ISQ_IL
#define ADC_ISQ_IL
Definition: gd32f10x_adc.h:102
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_ISQ
#define ADC_ISQ(adcx)
Definition: gd32f10x_adc.h:38
ISQ_IL
#define ISQ_IL(regval)
Definition: gd32f10x_adc.h:207
ADC_RSQ0
#define ADC_RSQ0(adcx)
Definition: gd32f10x_adc.h:35
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_data_alignment_config | ( | uint32_t | adc_periph,
 |  | uint32_t | data_alignment
 | ) |  |

configure ADC data alignment

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] data_alignment data alignment select only one parameter can be selected
  • ADC_DATAALIGN_RIGHT: LSB alignment
  • ADC_DATAALIGN_LEFT: MSB alignment
[out] | none
Return values
none

Definition at line 245 of file gd32f10x_adc.c.

246 {
247 if(ADC_DATAALIGN_RIGHT != data_alignment){
248 ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
249 }else{
250 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
251 }
252 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_DAL
#define ADC_CTL1_DAL
Definition: gd32f10x_adc.h:75
ADC_DATAALIGN_RIGHT
#define ADC_DATAALIGN_RIGHT
Definition: gd32f10x_adc.h:140
void adc_deinit ( uint32_t adc_periph )

reset ADC

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 22 of file gd32f10x_adc.c.

23 {
24 switch(adc_periph){
25 case ADC0:
26 rcu_periph_reset_enable(RCU_ADC0RST);
27 rcu_periph_reset_disable(RCU_ADC0RST);
28 break;
29 case ADC1:
30 rcu_periph_reset_enable(RCU_ADC1RST);
31 rcu_periph_reset_disable(RCU_ADC1RST);
32 break;
33 #ifndef GD32F10X_CL
34 case ADC2:
35 rcu_periph_reset_enable(RCU_ADC2RST);
36 rcu_periph_reset_disable(RCU_ADC2RST);
37 break;
38 #endif /* GD32F10X_CL */
39 default:
40 break;
41 }
42 }
ADC1
#define ADC1
Definition: gd32f10x_adc.h:20
RCU_ADC0RST
Definition: gd32f10x_rcu.h:485
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
RCU_ADC1RST
Definition: gd32f10x_rcu.h:486
ADC2
#define ADC2
Definition: gd32f10x_adc.h:21
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_disable ( uint32_t adc_periph )

disable ADC interface

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 65 of file gd32f10x_adc.c.

66 {
67 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
68 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f10x_adc.h:70
void adc_discontinuous_mode_config | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group,
 |  | uint8_t | length
 | ) |  |

configure ADC discontinuous mode

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group only one among these parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
  • ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
[in] | length | number of conversions in discontinuous mode,the number can be 1..8 for regular channel ,the number has no effect for inserted channel
[out] | none
Return values
none

Definition at line 153 of file gd32f10x_adc.c.

154 {
155 ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC ));
156 switch(adc_channel_group){
157 case ADC_REGULAR_CHANNEL:
158 /* config the number of conversions in discontinuous mode */
159 ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
160 ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U));
161
162 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
163 break;
164 case ADC_INSERTED_CHANNEL:
165 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
166 break;
167 case ADC_CHANNEL_DISCON_DISABLE:
168 default:
169 break;
170 }
171 }
ADC_CTL0_DISIC
#define ADC_CTL0_DISIC
Definition: gd32f10x_adc.h:62
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL0_DISRC
#define ADC_CTL0_DISRC
Definition: gd32f10x_adc.h:61
ADC_CTL0_DISNUM
#define ADC_CTL0_DISNUM
Definition: gd32f10x_adc.h:63
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_CHANNEL_DISCON_DISABLE
#define ADC_CHANNEL_DISCON_DISABLE
Definition: gd32f10x_adc.h:214
CTL0_DISNUM
#define CTL0_DISNUM(regval)
Definition: gd32f10x_adc.h:121
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_dma_mode_disable ( uint32_t adc_periph )

disable DMA request

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 110 of file gd32f10x_adc.c.

111 {
112 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
113 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f10x_adc.h:74
void adc_dma_mode_enable ( uint32_t adc_periph )

enable DMA request

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 98 of file gd32f10x_adc.c.

99 {
100 ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
101 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f10x_adc.h:74
void adc_enable ( uint32_t adc_periph )

enable ADC interface

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 51 of file gd32f10x_adc.c.

52 {
53 if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
54 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
55 }
56 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f10x_adc.h:70
void adc_external_trigger_config | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group,
 |  | ControlStatus | newvalue
 | ) |  |

enable ADC external trigger

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group one or more parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 435 of file gd32f10x_adc.c.

436 {
437 if(newvalue){
438 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
439 ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
440 }
441 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
442 ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
443 }
444 }else{
445 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
446 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
447 }
448 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
449 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
450 }
451 }
452 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL1_ETEIC
#define ADC_CTL1_ETEIC
Definition: gd32f10x_adc.h:77
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
ADC_CTL1_ETERC
#define ADC_CTL1_ETERC
Definition: gd32f10x_adc.h:79
void adc_external_trigger_source_config | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group,
 |  | uint32_t | external_trigger_source
 | ) |  |

configure ADC external trigger source

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] external_trigger_source regular or inserted group trigger source only one parameter can be selected for regular channel:
  • ADC0_1_EXTTRIG_REGULAR_T0_CH0: timer 0 CC0 event select
  • ADC0_1_EXTTRIG_REGULAR_T0_CH1: timer 0 CC1 event select
  • ADC0_1_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select
  • ADC0_1_EXTTRIG_REGULAR_T1_CH1: timer 1 CC1 event select
  • ADC0_1_EXTTRIG_REGULAR_T2_TRGO: timer 2 TRGO event select
  • ADC0_1_EXTTRIG_REGULAR_T3_CH3: timer 3 CC3 event select
  • ADC0_1_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select
  • ADC0_1_EXTTRIG_REGULAR_EXTI_11 : external interrupt line 11
  • ADC2_EXTTRIG_REGULAR_T2_CH0: timer 2 CC0 event select
  • ADC2_EXTTRIG_REGULAR_T1_CH2: timer 1 CC2 event select
  • ADC2_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select
  • ADC2_EXTTRIG_REGULAR_T7_CH0: timer 7 CC0 event select
  • ADC2_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select
  • ADC2_EXTTRIG_REGULAR_T4_CH0: timer 4 CC0 event select
  • ADC2_EXTTRIG_REGULAR_T4_CH2: timer 4 CC2 event select
  • ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger for inserted channel:
  • ADC0_1_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select
  • ADC0_1_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select
  • ADC0_1_EXTTRIG_INSERTED_T1_TRGO: timer 1 TRGO event select
  • ADC0_1_EXTTRIG_INSERTED_T1_CH0: timer 1 CC0 event select
  • ADC0_1_EXTTRIG_INSERTED_T2_CH3: timer 2 CC3 event select
  • ADC0_1_EXTTRIG_INSERTED_T3_TRGO: timer 3 TRGO event select
  • ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
  • ADC0_1_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select
  • ADC2_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select
  • ADC2_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select
  • ADC2_EXTTRIG_INSERTED_T3_CH2: timer 3 CC2 event select
  • ADC2_EXTTRIG_INSERTED_T7_CH1: timer 7 CC1 event select
  • ADC2_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select
  • ADC2_EXTTRIG_INSERTED_T4_TRGO: timer 4 TRGO event select
  • ADC2_EXTTRIG_INSERTED_T4_CH3: timer 4 CC3 event select
  • ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger
[out] | none
Return values
none

Definition at line 501 of file gd32f10x_adc.c.

502 {
503 switch(adc_channel_group){
504 case ADC_REGULAR_CHANNEL:
505 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
506 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
507 break;
508 case ADC_INSERTED_CHANNEL:
509 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
510 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
511 break;
512 default:
513 break;
514 }
515 }
ADC_CTL1_ETSIC
#define ADC_CTL1_ETSIC
Definition: gd32f10x_adc.h:76
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL1_ETSRC
#define ADC_CTL1_ETSRC
Definition: gd32f10x_adc.h:78
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_flag_clear | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_flag
 | ) |  |

clear the ADC flag bits

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_flag the adc flag bits one or more parameters can be selected
  • ADC_FLAG_WDE: analog watchdog event flag
  • ADC_FLAG_EOC: end of group conversion flag
  • ADC_FLAG_EOIC: end of inserted group conversion flag
  • ADC_FLAG_STIC: start flag of inserted channel group
  • ADC_FLAG_STRC: start flag of regular channel group
[out] | none
Return values
none

Definition at line 669 of file gd32f10x_adc.c.

670 {
671 ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
672 }
ADC_STAT
#define ADC_STAT(adcx)
Definition: gd32f10x_adc.h:24
FlagStatus adc_flag_get | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_flag
 | ) |  |

get the ADC flag bits

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_flag the adc flag bits only one parameter can be selected
  • ADC_FLAG_WDE: analog watchdog event flag
  • ADC_FLAG_EOC: end of group conversion flag
  • ADC_FLAG_EOIC: end of inserted group conversion flag
  • ADC_FLAG_STIC: start flag of inserted channel group
  • ADC_FLAG_STRC: start flag of regular channel group
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 646 of file gd32f10x_adc.c.

647 {
648 FlagStatus reval = RESET;
649 if(ADC_STAT(adc_periph) & adc_flag){
650 reval = SET;
651 }
652 return reval;
653 }
ADC_STAT
#define ADC_STAT(adcx)
Definition: gd32f10x_adc.h:24
void adc_inserted_channel_config | ( | uint32_t | adc_periph,
 |  | uint8_t | rank,
 |  | uint8_t | adc_channel,
 |  | uint32_t | sample_time
 | ) |  |

configure ADC inserted channel

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] | rank | the inserted group sequencer rank,this parameter must be between 0 to 3
[in] adc_channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
[in] sample_time The sample time value only one parameter can be selected
  • ADC_SAMPLETIME_1POINT5: 1.5 cycles
  • ADC_SAMPLETIME_7POINT5: 7.5 cycles
  • ADC_SAMPLETIME_13POINT5: 13.5 cycles
  • ADC_SAMPLETIME_28POINT5: 28.5 cycles
  • ADC_SAMPLETIME_41POINT5: 41.5 cycles
  • ADC_SAMPLETIME_55POINT5: 55.5 cycles
  • ADC_SAMPLETIME_71POINT5: 71.5 cycles
  • ADC_SAMPLETIME_239POINT5: 239.5 cycles
[out] | none
Return values
none

Definition at line 366 of file gd32f10x_adc.c.

367 {
368 uint8_t inserted_length;
369 uint32_t isq,sampt;
370
371 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
372
373 isq = ADC_ISQ(adc_periph);
374 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U-(inserted_length-rank)*5U)));
375 isq |= ((uint32_t)adc_channel << (15U-(inserted_length-rank)*5U));
376 ADC_ISQ(adc_periph) = isq;
377
378 /* ADC sampling time config */
379 if(adc_channel < 10U){
380 sampt = ADC_SAMPT1(adc_periph);
381 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
382 sampt |= (uint32_t) sample_time << (3U*adc_channel);
383 ADC_SAMPT1(adc_periph) = sampt;
384 }else if(adc_channel < 18U){
385 sampt = ADC_SAMPT0(adc_periph);
386 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
387 sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U)));
388 ADC_SAMPT0(adc_periph) = sampt;
389 }else{
390 }
391 }
ADC_SAMPT0
#define ADC_SAMPT0(adcx)
Definition: gd32f10x_adc.h:27
ADC_ISQ
#define ADC_ISQ(adcx)
Definition: gd32f10x_adc.h:38
ADC_SAMPT1
#define ADC_SAMPT1(adcx)
Definition: gd32f10x_adc.h:28
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f10x_adc.h:85
ADC_ISQ_ISQN
#define ADC_ISQ_ISQN
Definition: gd32f10x_adc.h:101
void adc_inserted_channel_offset_config | ( | uint32_t | adc_periph,
 |  | uint8_t | inserted_channel,
 |  | uint16_t | offset
 | ) |  |

configure ADC inserted channel offset

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] inserted_channel : insert channel select only one parameter can be selected
  • ADC_INSERTED_CHANNEL_0: inserted channel0
  • ADC_INSERTED_CHANNEL_1: inserted channel1
  • ADC_INSERTED_CHANNEL_2: inserted channel2
  • ADC_INSERTED_CHANNEL_3: inserted channel3
[in] | offset | : the offset data
[out] | none
Return values
none

Definition at line 407 of file gd32f10x_adc.c.

408 {
409 uint8_t inserted_length;
410 uint32_t num = 0U;
411
412 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
413 num = 3U - (inserted_length - inserted_channel);
414
415 if(num <= 3U){
416 /* calculate the offset of the register */
417 num = num * 4U;
418 /* config the offset of the selected channels */
419 REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
420 }
421 }
ADC_ISQ
#define ADC_ISQ(adcx)
Definition: gd32f10x_adc.h:38
IOFFX_IOFF
#define IOFFX_IOFF(regval)
Definition: gd32f10x_adc.h:195
uint16_t adc_inserted_data_read | ( | uint32_t | adc_periph,
 |  | uint8_t | inserted_channel
 | ) |  |

read ADC inserted group data register

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] inserted_channel : insert channel select only one parameter can be selected
  • ADC_INSERTED_CHANNEL_0: inserted Channel0
  • ADC_INSERTED_CHANNEL_1: inserted channel1
  • ADC_INSERTED_CHANNEL_2: inserted Channel2
  • ADC_INSERTED_CHANNEL_3: inserted Channel3
[out] | none
Return values
the conversion value

Definition at line 596 of file gd32f10x_adc.c.

597 {
598 uint32_t idata;
599 /* read the data of the selected channel */
600 switch(inserted_channel){
601 case ADC_INSERTED_CHANNEL_0:
602 idata = ADC_IDATA0(adc_periph);
603 break;
604 case ADC_INSERTED_CHANNEL_1:
605 idata = ADC_IDATA1(adc_periph);
606 break;
607 case ADC_INSERTED_CHANNEL_2:
608 idata = ADC_IDATA2(adc_periph);
609 break;
610 case ADC_INSERTED_CHANNEL_3:
611 idata = ADC_IDATA3(adc_periph);
612 break;
613 default:
614 idata = 0U;
615 break;
616 }
617 return (uint16_t)idata;
618 }
ADC_INSERTED_CHANNEL_1
#define ADC_INSERTED_CHANNEL_1
Definition: gd32f10x_adc.h:218
ADC_IDATA0
#define ADC_IDATA0(adcx)
Definition: gd32f10x_adc.h:39
ADC_IDATA1
#define ADC_IDATA1(adcx)
Definition: gd32f10x_adc.h:40
ADC_INSERTED_CHANNEL_2
#define ADC_INSERTED_CHANNEL_2
Definition: gd32f10x_adc.h:219
ADC_IDATA2
#define ADC_IDATA2(adcx)
Definition: gd32f10x_adc.h:41
ADC_INSERTED_CHANNEL_3
#define ADC_INSERTED_CHANNEL_3
Definition: gd32f10x_adc.h:220
ADC_IDATA3
#define ADC_IDATA3(adcx)
Definition: gd32f10x_adc.h:42
ADC_INSERTED_CHANNEL_0
#define ADC_INSERTED_CHANNEL_0
Definition: gd32f10x_adc.h:217
FlagStatus adc_inserted_software_startconv_flag_get ( uint32_t adc_periph )

get the bit state of ADCx software inserted channel start conversion

Parameters
[in] | adc_periph | ADCx,x=0,1,2, only one among these parameters can be selected
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 561 of file gd32f10x_adc.c.

562 {
563 FlagStatus reval = RESET;
564 if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){
565 reval = SET;
566 }
567 return reval;
568 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_SWICST
#define ADC_CTL1_SWICST
Definition: gd32f10x_adc.h:80
void adc_interrupt_disable | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_interrupt
 | ) |  |

disable ADC interrupt

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_interrupt the adc interrupt flag one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt flag
  • ADC_INT_EOC: end of group conversion interrupt flag
  • ADC_INT_EOIC: end of inserted group conversion interrupt flag
[out] | none
Return values
none

Definition at line 772 of file gd32f10x_adc.c.

773 {
774 if(0U != (adc_interrupt & ADC_INT_WDE)){
775 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
776 }
777
778 if(0U != (adc_interrupt & ADC_INT_EOC)){
779 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
780 }
781
782 if(0U != (adc_interrupt & ADC_INT_EOIC)){
783 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
784 }
785 }
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f10x_adc.h:57
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f10x_adc.h:245
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f10x_adc.h:244
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f10x_adc.h:243
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f10x_adc.h:55
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f10x_adc.h:56
void adc_interrupt_enable | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_interrupt
 | ) |  |

enable ADC interrupt

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_interrupt the adc interrupt one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt flag
  • ADC_INT_EOC: end of group conversion interrupt flag
  • ADC_INT_EOIC: end of inserted group conversion interrupt flag
[out] | none
Return values
none

Definition at line 745 of file gd32f10x_adc.c.

746 {
747 if(0U != (adc_interrupt & ADC_INT_WDE)){
748 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
749 }
750
751 if(0U != (adc_interrupt & ADC_INT_EOC)){
752 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
753 }
754
755 if(0U != (adc_interrupt & ADC_INT_EOIC)){
756 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
757 }
758 }
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f10x_adc.h:57
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f10x_adc.h:245
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f10x_adc.h:244
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f10x_adc.h:243
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f10x_adc.h:55
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f10x_adc.h:56
void adc_interrupt_flag_clear | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_interrupt
 | ) |  |

clear the ADC flag

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_interrupt the adc status flag one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt
  • ADC_INT_EOC: end of group conversion interrupt
  • ADC_INT_EOIC: end of inserted group conversion interrupt
[out] | none
Return values
none

Definition at line 728 of file gd32f10x_adc.c.

729 {
730 ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
731 }
ADC_STAT
#define ADC_STAT(adcx)
Definition: gd32f10x_adc.h:24
FlagStatus adc_interrupt_flag_get | ( | uint32_t | adc_periph,
 |  | uint32_t | adc_interrupt
 | ) |  |

get the ADC interrupt bits

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_interrupt the adc interrupt bits only oneparameter can be selected
  • ADC_INT_WDE: analog watchdog interrupt
  • ADC_INT_EOC: end of group conversion interrupt
  • ADC_INT_EOIC: end of inserted group conversion interrupt
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 686 of file gd32f10x_adc.c.

687 {
688 FlagStatus interrupt_flag = RESET;
689 uint32_t state;
690 /* check the interrupt bits */
691 switch(adc_interrupt){
692 case ADC_INT_WDE:
693 state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
694 if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
695 interrupt_flag = SET;
696 }
697 break;
698 case ADC_INT_EOC:
699 state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
700 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
701 interrupt_flag = SET;
702 }
703 break;
704 case ADC_INT_EOIC:
705 state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
706 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
707 interrupt_flag = SET;
708 }
709 break;
710 default:
711 break;
712 }
713 return interrupt_flag;
714 }
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f10x_adc.h:57
ADC_STAT_EOC
#define ADC_STAT_EOC
Definition: gd32f10x_adc.h:48
ADC_STAT_EOIC
#define ADC_STAT_EOIC
Definition: gd32f10x_adc.h:49
ADC_STAT
#define ADC_STAT(adcx)
Definition: gd32f10x_adc.h:24
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f10x_adc.h:245
ADC_STAT_WDE
#define ADC_STAT_WDE
Definition: gd32f10x_adc.h:47
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f10x_adc.h:244
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f10x_adc.h:243
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f10x_adc.h:55
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f10x_adc.h:56
void adc_mode_config ( uint32_t mode )

configure the ADC sync mode

Parameters
[in] mode ADC mode only one among these parameters can be selected
  • ADC_MODE_FREE: all the ADCs work independently
  • ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
  • ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
  • ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
  • ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
  • ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
  • ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
  • ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
  • ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
  • ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
[out] none
Return values
none

Definition at line 190 of file gd32f10x_adc.c.

191 {
192 ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
193 ADC_CTL0(ADC0) |= mode;
194 }
ADC_CTL0_SYNCM
#define ADC_CTL0_SYNCM
Definition: gd32f10x_adc.h:64
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_regular_channel_config | ( | uint32_t | adc_periph,
 |  | uint8_t | rank,
 |  | uint8_t | adc_channel,
 |  | uint32_t | sample_time
 | ) |  |

configure ADC regular channel

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] | rank | the regular group sequence rank,this parameter must be between 0 to 15
[in] adc_channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
[in] sample_time the sample time value only one parameter can be selected
  • ADC_SAMPLETIME_1POINT5: 1.5 cycles
  • ADC_SAMPLETIME_7POINT5: 7.5 cycles
  • ADC_SAMPLETIME_13POINT5: 13.5 cycles
  • ADC_SAMPLETIME_28POINT5: 28.5 cycles
  • ADC_SAMPLETIME_41POINT5: 41.5 cycles
  • ADC_SAMPLETIME_55POINT5: 55.5 cycles
  • ADC_SAMPLETIME_71POINT5: 71.5 cycles
  • ADC_SAMPLETIME_239POINT5: 239.5 cycles
[out] | none
Return values
none

Definition at line 307 of file gd32f10x_adc.c.

308 {
309 uint32_t rsq,sampt;
310
311 /* ADC regular sequence config */
312 if(rank < 6U){
313 rsq = ADC_RSQ2(adc_periph);
314 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
315 rsq |= ((uint32_t)adc_channel << (5U*rank));
316 ADC_RSQ2(adc_periph) = rsq;
317 }else if(rank < 12U){
318 rsq = ADC_RSQ1(adc_periph);
319 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
320 rsq |= ((uint32_t)adc_channel << (5U*(rank-6U)));
321 ADC_RSQ1(adc_periph) = rsq;
322 }else if(rank < 16U){
323 rsq = ADC_RSQ0(adc_periph);
324 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
325 rsq |= ((uint32_t)adc_channel << (5U*(rank-12U)));
326 ADC_RSQ0(adc_periph) = rsq;
327 }else{
328 }
329
330 /* ADC sampling time config */
331 if(adc_channel < 10U){
332 sampt = ADC_SAMPT1(adc_periph);
333 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
334 sampt |= (uint32_t)(sample_time << (3U*adc_channel));
335 ADC_SAMPT1(adc_periph) = sampt;
336 }else if(adc_channel < 18U){
337 sampt = ADC_SAMPT0(adc_periph);
338 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
339 sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U)));
340 ADC_SAMPT0(adc_periph) = sampt;
341 }else{
342 }
343 }
ADC_SAMPT0
#define ADC_SAMPT0(adcx)
Definition: gd32f10x_adc.h:27
ADC_SAMPT1
#define ADC_SAMPT1(adcx)
Definition: gd32f10x_adc.h:28
ADC_RSQ2
#define ADC_RSQ2(adcx)
Definition: gd32f10x_adc.h:37
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f10x_adc.h:85
ADC_RSQ0
#define ADC_RSQ0(adcx)
Definition: gd32f10x_adc.h:35
ADC_RSQ1
#define ADC_RSQ1(adcx)
Definition: gd32f10x_adc.h:36
ADC_RSQX_RSQN
#define ADC_RSQX_RSQN
Definition: gd32f10x_adc.h:97
uint16_t adc_regular_data_read ( uint32_t adc_periph )

read ADC regular group data register

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] | none
[out] | none
Return values
the conversion value

Definition at line 578 of file gd32f10x_adc.c.

579 {
580 return (uint16_t)(ADC_RDATA(adc_periph));
581 }
ADC_RDATA
#define ADC_RDATA(adcx)
Definition: gd32f10x_adc.h:43
FlagStatus adc_regular_software_startconv_flag_get ( uint32_t adc_periph )

get the bit state of ADCx software start conversion

Parameters
[in] | adc_periph | ADCx,x=0,1,2, only one among these parameters can be selected
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 545 of file gd32f10x_adc.c.

546 {
547 FlagStatus reval = RESET;
548 if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){
549 reval = SET;
550 }
551 return reval;
552 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_CTL1_SWRCST
#define ADC_CTL1_SWRCST
Definition: gd32f10x_adc.h:81
void adc_software_trigger_enable | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group
 | ) |  |

enable ADC software trigger

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group select the channel group one or more parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[out] | none
Return values
none

Definition at line 528 of file gd32f10x_adc.c.

529 {
530 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
531 ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
532 }
533 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
534 ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
535 }
536 }
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL1_SWRCST
#define ADC_CTL1_SWRCST
Definition: gd32f10x_adc.h:81
ADC_CTL1_SWICST
#define ADC_CTL1_SWICST
Definition: gd32f10x_adc.h:80
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_special_function_config | ( | uint32_t | adc_periph,
 |  | uint32_t | function,
 |  | ControlStatus | newvalue
 | ) |  |

enable or disable ADC special function

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] function the function to config one or more parameters can be selected below
  • ADC_SCAN_MODE: scan mode select
  • ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
  • ADC_CONTINUOUS_MODE: continuous mode select
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 209 of file gd32f10x_adc.c.

210 {
211 if(newvalue){
212 if(0U != (function & ADC_SCAN_MODE)){
213 ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
214 }
215 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
216 ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
217 }
218 if(0U != (function & ADC_CONTINUOUS_MODE)){
219 ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
220 }
221 }else{
222 if(0U != (function & ADC_SCAN_MODE)){
223 ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
224 }
225 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
226 ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
227 }
228 if(0U != (function & ADC_CONTINUOUS_MODE)){
229 ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
230 }
231 }
232 }
ADC_CONTINUOUS_MODE
#define ADC_CONTINUOUS_MODE
Definition: gd32f10x_adc.h:143
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_INSERTED_CHANNEL_AUTO
#define ADC_INSERTED_CHANNEL_AUTO
Definition: gd32f10x_adc.h:125
ADC_SCAN_MODE
#define ADC_SCAN_MODE
Definition: gd32f10x_adc.h:123
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
uint32_t adc_sync_mode_convert_value_read ( void )

read the last ADC0 and ADC1 conversion result data in sync mode

Parameters
[in] | none
[out] | none
Return values
the conversion value

Definition at line 626 of file gd32f10x_adc.c.

627 {
628 /* return conversion value */
629 return ADC_RDATA(ADC0);
630 }
ADC_RDATA
#define ADC_RDATA(adcx)
Definition: gd32f10x_adc.h:43
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_tempsensor_vrefint_disable ( void )

disable the temperature sensor and Vrefint channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 133 of file gd32f10x_adc.c.

134 {
135 /* disable the temperature sensor and Vrefint channel */
136 ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
137 }
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f10x_adc.h:82
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_tempsensor_vrefint_enable ( void )

enable the temperature sensor and Vrefint channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 121 of file gd32f10x_adc.c.

122 {
123 /* enable the temperature sensor and Vrefint channel */
124 ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
125 }
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f10x_adc.h:82
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
void adc_watchdog_disable ( uint32_t adc_periph )

disable ADC analog watchdog

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[out] | none
Return values
none

Definition at line 843 of file gd32f10x_adc.c.

844 {
845 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
846 }
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f10x_adc.h:59
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f10x_adc.h:65
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f10x_adc.h:54
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f10x_adc.h:66
void adc_watchdog_group_channel_enable | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel_group
 | ) |  |

configure ADC analog watchdog group channel

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel_group the channel group use analog watchdog only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
  • ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
[out] | none
Return values
none

Definition at line 817 of file gd32f10x_adc.c.

818 {
819 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
820 /* select the group */
821 switch(adc_channel_group){
822 case ADC_REGULAR_CHANNEL:
823 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
824 break;
825 case ADC_INSERTED_CHANNEL:
826 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
827 break;
828 case ADC_REGULAR_INSERTED_CHANNEL:
829 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
830 break;
831 default:
832 break;
833 }
834 }
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f10x_adc.h:59
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f10x_adc.h:65
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_REGULAR_INSERTED_CHANNEL
#define ADC_REGULAR_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:212
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f10x_adc.h:66
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
void adc_watchdog_single_channel_enable | ( | uint32_t | adc_periph,
 |  | uint8_t | adc_channel
 | ) |  |

configure ADC analog watchdog single channel

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] adc_channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
[out] | none
Return values
none

Definition at line 797 of file gd32f10x_adc.c.

798 {
799 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
800
801 ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
802 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
803 }
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f10x_adc.h:59
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f10x_adc.h:65
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f10x_adc.h:54
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f10x_adc.h:66
void adc_watchdog_threshold_config | ( | uint32_t | adc_periph,
 |  | uint16_t | low_threshold,
 |  | uint16_t | high_threshold
 | ) |  |

configure ADC analog watchdog threshold

Parameters
[in] | adc_periph | ADCx,x=0,1,2 only one among these parameters can be selected
[in] | low_threshold | analog watchdog low threshold,0..4095
[in] | high_threshold | analog watchdog high threshold,0..4095
[out] | none
Return values
none

Definition at line 857 of file gd32f10x_adc.c.

858 {
859 ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
860 ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
861 }
ADC_WDLT
#define ADC_WDLT(adcx)
Definition: gd32f10x_adc.h:34
WDLT_WDLT
#define WDLT_WDLT(regval)
Definition: gd32f10x_adc.h:201
ADC_WDHT
#define ADC_WDHT(adcx)
Definition: gd32f10x_adc.h:33
WDHT_WDHT
#define WDHT_WDHT(regval)
Definition: gd32f10x_adc.h:198
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_bkp.c File Reference

BKP driver. More...

#include "gd32f10x_bkp.h"

Go to the source code of this file.

Macros

#define TAMPER_FLAG_SHIFT ((uint8_t)8U)

Functions

void | bkp_deinit (void)
reset BKP registers More...
void | bkp_write_data (bkp_data_register_enum register_number, uint16_t data)
write BKP data register More...
uint16_t | bkp_read_data (bkp_data_register_enum register_number)
read BKP data register More...
void | bkp_rtc_calibration_output_enable (void)
enable RTC clock calibration output More...
void | bkp_rtc_calibration_output_disable (void)
disable RTC clock calibration output More...
void | bkp_rtc_signal_output_enable (void)
enable RTC alarm or second signal output More...
void | bkp_rtc_signal_output_disable (void)
disable RTC alarm or second signal output More...
void | bkp_rtc_output_select (uint16_t outputsel)
select RTC output More...
void | bkp_rtc_calibration_value_set (uint8_t value)
set RTC clock calibration value More...
void | bkp_tamper_detection_enable (void)
enable tamper detection More...
void | bkp_tamper_detection_disable (void)
disable tamper detection More...
void | bkp_tamper_active_level_set (uint16_t level)
set tamper pin active level More...
void | bkp_tamper_interrupt_enable (void)
enable tamper interrupt More...
void | bkp_tamper_interrupt_disable (void)
disable tamper interrupt More...
FlagStatus | bkp_flag_get (uint16_t flag)
get bkp flag state More...
void | bkp_flag_clear (uint16_t flag)
clear bkp flag state More...
FlagStatus | bkp_interrupt_flag_get (uint16_t flag)
get bkp interrupt flag state More...
void | bkp_interrupt_flag_clear (uint16_t flag)
clear bkp interrupt flag state More...

Detailed Description

BKP driver.

Definition in file gd32f10x_bkp.c.

Macro Definition Documentation

#define TAMPER_FLAG_SHIFT ((uint8_t)8U)

Definition at line 15 of file gd32f10x_bkp.c.

Function Documentation

void bkp_deinit ( void )

reset BKP registers

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 23 of file gd32f10x_bkp.c.

24 {
25 /* reset BKP domain register*/
26 rcu_bkp_reset_enable();
27 rcu_bkp_reset_disable();
28 }
rcu_bkp_reset_enable
void rcu_bkp_reset_enable(void)
reset the BKP domain
Definition: gd32f10x_rcu.c:223
rcu_bkp_reset_disable
void rcu_bkp_reset_disable(void)
disable the BKP domain reset
Definition: gd32f10x_rcu.c:234
void bkp_flag_clear ( uint16_t flag )

clear bkp flag state

Parameters
[in] flag
  • BKP_FLAG_TAMPER: tamper event flag
[out] none
Return values
none

Definition at line 235 of file gd32f10x_bkp.c.

236 {
237 BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT);
238 }
TAMPER_FLAG_SHIFT
#define TAMPER_FLAG_SHIFT
Definition: gd32f10x_bkp.c:15
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
FlagStatus bkp_flag_get ( uint16_t flag )

get bkp flag state

Parameters
[in] flag
  • BKP_FLAG_TAMPER: tamper event flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 219 of file gd32f10x_bkp.c.

220 {
221 if(RESET != (BKP_TPCS & flag)){
222 return SET;
223 }else{
224 return RESET;
225 }
226 }
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
void bkp_interrupt_flag_clear ( uint16_t flag )

clear bkp interrupt flag state

Parameters
[in] flag
  • BKP_INT_FLAG_TAMPER: tamper interrupt flag
[out] none
Return values
none

Definition at line 263 of file gd32f10x_bkp.c.

264 {
265 BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT);
266 }
TAMPER_FLAG_SHIFT
#define TAMPER_FLAG_SHIFT
Definition: gd32f10x_bkp.c:15
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
FlagStatus bkp_interrupt_flag_get ( uint16_t flag )

get bkp interrupt flag state

Parameters
[in] flag
  • BKP_INT_FLAG_TAMPER: tamper interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 247 of file gd32f10x_bkp.c.

248 {
249 if(RESET != (BKP_TPCS & flag)){
250 return SET;
251 }else{
252 return RESET;
253 }
254 }
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
uint16_t bkp_read_data ( bkp_data_register_enum register_number )

read BKP data register

Parameters
[in] register_number refer to bkp_data_register_enum, only one parameter can be selected
  • BKP_DATA_x(x = 0..41): bkp data register number x
[out] none
Return values
data of BKP data register

Definition at line 56 of file gd32f10x_bkp.c.

57 {
58 uint16_t data = 0U;
59
60 /* get the data from the BKP data register */
61 if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
62 data = BKP_DATA10_41(register_number - 1U);
63 }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
64 data = BKP_DATA0_9(register_number - 1U);
65 }else{
66 /* illegal parameters */
67 }
68 return data;
69 }
BKP_DATA10_41
#define BKP_DATA10_41(number)
Definition: gd32f10x_bkp.h:92
BKP_DATA0_9
#define BKP_DATA0_9(number)
Definition: gd32f10x_bkp.h:91
BKP_DATA_9
Definition: gd32f10x_bkp.h:126
BKP_DATA_41
Definition: gd32f10x_bkp.h:158
BKP_DATA_10
Definition: gd32f10x_bkp.h:127
BKP_DATA_0
Definition: gd32f10x_bkp.h:117
void bkp_rtc_calibration_output_disable ( void )

disable RTC clock calibration output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 88 of file gd32f10x_bkp.c.

89 {
90 BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
91 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_COEN
#define BKP_OCTL_COEN
Definition: gd32f10x_bkp.h:74
void bkp_rtc_calibration_output_enable ( void )

enable RTC clock calibration output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 77 of file gd32f10x_bkp.c.

78 {
79 BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
80 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_COEN
#define BKP_OCTL_COEN
Definition: gd32f10x_bkp.h:74
void bkp_rtc_calibration_value_set ( uint8_t value )

set RTC clock calibration value

Parameters
[in] value RTC clock calibration value
  • 0x00 - 0x7F
[out] none
Return values
none

Definition at line 140 of file gd32f10x_bkp.c.

141 {
142 uint16_t ctl;
143
144 ctl = BKP_OCTL;
145 ctl &= (uint16_t)OCTL_RCCV(0);
146 ctl |= (uint16_t)OCTL_RCCV(value);
147 BKP_OCTL = ctl;
148 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
OCTL_RCCV
#define OCTL_RCCV(regval)
Definition: gd32f10x_bkp.h:98
void bkp_rtc_output_select ( uint16_t outputsel )

select RTC output

Parameters
[in] outputsel RTC output selection
  • RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output
  • RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output
[out] none
Return values
none

Definition at line 123 of file gd32f10x_bkp.c.

124 {
125 uint16_t ctl = 0U;
126
127 ctl = BKP_OCTL;
128 ctl &= (uint16_t)~BKP_OCTL_ROSEL;
129 ctl |= outputsel;
130 BKP_OCTL = ctl;
131 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_ROSEL
#define BKP_OCTL_ROSEL
Definition: gd32f10x_bkp.h:76
void bkp_rtc_signal_output_disable ( void )

disable RTC alarm or second signal output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 110 of file gd32f10x_bkp.c.

111 {
112 BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
113 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_ASOEN
#define BKP_OCTL_ASOEN
Definition: gd32f10x_bkp.h:75
void bkp_rtc_signal_output_enable ( void )

enable RTC alarm or second signal output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 99 of file gd32f10x_bkp.c.

100 {
101 BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
102 }
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_OCTL_ASOEN
#define BKP_OCTL_ASOEN
Definition: gd32f10x_bkp.h:75
void bkp_tamper_active_level_set ( uint16_t level )

set tamper pin active level

Parameters
[in] level tamper active level
  • TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high
  • TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low
[out] none
Return values
none

Definition at line 180 of file gd32f10x_bkp.c.

181 {
182 uint16_t ctl = 0U;
183
184 ctl = BKP_TPCTL;
185 ctl &= (uint16_t)~BKP_TPCTL_TPAL;
186 ctl |= level;
187 BKP_TPCTL = ctl;
188 }
BKP_TPCTL
#define BKP_TPCTL
Definition: gd32f10x_bkp.h:65
BKP_TPCTL_TPAL
#define BKP_TPCTL_TPAL
Definition: gd32f10x_bkp.h:80
void bkp_tamper_detection_disable ( void )

disable tamper detection

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 167 of file gd32f10x_bkp.c.

168 {
169 BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN;
170 }
BKP_TPCTL
#define BKP_TPCTL
Definition: gd32f10x_bkp.h:65
BKP_TPCTL_TPEN
#define BKP_TPCTL_TPEN
Definition: gd32f10x_bkp.h:79
void bkp_tamper_detection_enable ( void )

enable tamper detection

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 156 of file gd32f10x_bkp.c.

157 {
158 BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN;
159 }
BKP_TPCTL
#define BKP_TPCTL
Definition: gd32f10x_bkp.h:65
BKP_TPCTL_TPEN
#define BKP_TPCTL_TPEN
Definition: gd32f10x_bkp.h:79
void bkp_tamper_interrupt_disable ( void )

disable tamper interrupt

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 207 of file gd32f10x_bkp.c.

208 {
209 BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE;
210 }
BKP_TPCS_TPIE
#define BKP_TPCS_TPIE
Definition: gd32f10x_bkp.h:85
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
void bkp_tamper_interrupt_enable ( void )

enable tamper interrupt

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 196 of file gd32f10x_bkp.c.

197 {
198 BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE;
199 }
BKP_TPCS_TPIE
#define BKP_TPCS_TPIE
Definition: gd32f10x_bkp.h:85
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
void bkp_write_data | ( | bkp_data_register_enum | register_number,
 |  | uint16_t | data
 | ) |  |

write BKP data register

Parameters
[in] register_number refer to bkp_data_register_enum, only one parameter can be selected
  • BKP_DATA_x(x = 0..41): bkp data register number x
[in] | data | the data to be write in BKP data register
[out] | none
Return values
none

Definition at line 38 of file gd32f10x_bkp.c.

39 {
40 if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
41 BKP_DATA10_41(register_number - 1U) = data;
42 }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
43 BKP_DATA0_9(register_number - 1U) = data;
44 }else{
45 /* illegal parameters */
46 }
47 }
BKP_DATA10_41
#define BKP_DATA10_41(number)
Definition: gd32f10x_bkp.h:92
BKP_DATA0_9
#define BKP_DATA0_9(number)
Definition: gd32f10x_bkp.h:91
BKP_DATA_9
Definition: gd32f10x_bkp.h:126
BKP_DATA_41
Definition: gd32f10x_bkp.h:158
BKP_DATA_10
Definition: gd32f10x_bkp.h:127
BKP_DATA_0
Definition: gd32f10x_bkp.h:117
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_can.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_can.c File Reference

CAN driver. More...

#include "gd32f10x_can.h"

Go to the source code of this file.

Functions

void | can_deinit (uint32_t can_periph)
deinitialize CAN More...
ErrStatus | can_init (uint32_t can_periph, can_parameter_struct *can_parameter_init)
initialize CAN More...
void | can_filter_init (can_filter_parameter_struct *can_filter_parameter_init)
initialize CAN filter More...
void | can1_filter_start_bank (uint8_t start_bank)
set CAN1 fliter start bank number More...
void | can_debug_freeze_enable (uint32_t can_periph)
enable CAN debug freeze More...
void | can_debug_freeze_disable (uint32_t can_periph)
disable CAN debug freeze More...
void | can_time_trigger_mode_enable (uint32_t can_periph)
enable CAN time trigger mode More...
void | can_time_trigger_mode_disable (uint32_t can_periph)
disable CAN time trigger mode More...
uint8_t | can_message_transmit (uint32_t can_periph, can_trasnmit_message_struct *transmit_message)
transmit CAN message More...
can_transmit_state_enum | can_transmit_states (uint32_t can_periph, uint8_t mailbox_number)
get CAN transmit state More...
void | can_transmission_stop (uint32_t can_periph, uint8_t mailbox_number)
stop CAN transmission More...
void | can_message_receive (uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message)
CAN receive message. More...
void | can_fifo_release (uint32_t can_periph, uint8_t fifo_number)
release FIFO0 More...
uint8_t | can_receive_message_length_get (uint32_t can_periph, uint8_t fifo_number)
CAN receive message length. More...
ErrStatus | can_working_mode_set (uint32_t can_periph, uint8_t working_mode)
set CAN working mode More...
ErrStatus | can_wakeup (uint32_t can_periph)
wake up CAN More...
can_error_enum | can_error_get (uint32_t can_periph)
get CAN error type More...
uint8_t | can_receive_error_number_get (uint32_t can_periph)
get CAN receive error number More...
uint8_t | can_transmit_error_number_get (uint32_t can_periph)
get CAN transmit error number More...
void | can_interrupt_enable (uint32_t can_periph, uint32_t interrupt)
enable CAN interrupt More...
void | can_interrupt_disable (uint32_t can_periph, uint32_t interrupt)
disable CAN interrupt More...
FlagStatus | can_flag_get (uint32_t can_periph, can_flag_enum flag)
get CAN flag state More...
void | can_flag_clear (uint32_t can_periph, can_flag_enum flag)
clear CAN flag state More...
FlagStatus | can_interrupt_flag_get (uint32_t can_periph, can_interrupt_flag_enum flag)
get CAN interrupt flag state More...
void | can_interrupt_flag_clear (uint32_t can_periph, can_interrupt_flag_enum flag)
clear CAN interrupt flag state More...

Detailed Description

CAN driver.

Definition in file gd32f10x_can.c.

Function Documentation

void can1_filter_start_bank ( uint8_t start_bank )

set CAN1 fliter start bank number

Parameters
[in] can1_start_bank_number
  • (1..27)
[out] none
Return values
none

Definition at line 220 of file gd32f10x_can.c.

221 {
222 /* filter lock disable */
223 CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
224 /* set CAN1 filter start number */
225 CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F;
226 CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank);
227 /* filter lock enaable */
228 CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
229 }
FCTL_HBC1F
#define FCTL_HBC1F(regval)
Definition: gd32f10x_can.h:443
CAN_FCTL_HBC1F
#define CAN_FCTL_HBC1F
Definition: gd32f10x_can.h:270
CAN_FCTL
#define CAN_FCTL(canx)
Definition: gd32f10x_can.h:51
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
CAN_FCTL_FLD
#define CAN_FCTL_FLD
Definition: gd32f10x_can.h:269
void can_debug_freeze_disable ( uint32_t can_periph )

disable CAN debug freeze

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 261 of file gd32f10x_can.c.

262 {
263 CAN_CTL(can_periph) |= CAN_CTL_DFZ;
264 #ifdef GD32F10x_CL
265 if(CAN0 == can_periph){
266 dbg_periph_disable(DBG_CAN0_HOLD);
267 }else{
268 dbg_periph_disable(DBG_CAN1_HOLD);
269 }
270 #else
271 if(CAN0 == can_periph){
272 dbg_periph_enable(DBG_CAN0_HOLD);
273 }
274 #endif
275 }
DBG_CAN0_HOLD
Definition: gd32f10x_dbg.h:73
dbg_periph_enable
void dbg_periph_enable(dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:68
dbg_periph_disable
void dbg_periph_disable(dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:85
CAN_CTL_DFZ
#define CAN_CTL_DFZ
Definition: gd32f10x_can.h:140
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
void can_debug_freeze_enable ( uint32_t can_periph )

enable CAN debug freeze

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 238 of file gd32f10x_can.c.

239 {
240 CAN_CTL(can_periph) |= CAN_CTL_DFZ;
241 #ifdef GD32F10x_CL
242 if(CAN0 == can_periph){
243 dbg_periph_enable(DBG_CAN0_HOLD);
244 }else{
245 dbg_periph_enable(DBG_CAN1_HOLD);
246 }
247 #else
248 if(CAN0 == can_periph){
249 dbg_periph_enable(DBG_CAN0_HOLD);
250 }
251 #endif
252 }
DBG_CAN0_HOLD
Definition: gd32f10x_dbg.h:73
dbg_periph_enable
void dbg_periph_enable(dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:68
CAN_CTL_DFZ
#define CAN_CTL_DFZ
Definition: gd32f10x_can.h:140
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
void can_deinit ( uint32_t can_periph )

deinitialize CAN

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 22 of file gd32f10x_can.c.

23 {
24 #ifdef GD32F10x_CL
25 if(CAN0 == can_periph){
26 rcu_periph_reset_enable(RCU_CAN0RST);
27 rcu_periph_reset_disable(RCU_CAN0RST);
28 }else{
29 rcu_periph_reset_enable(RCU_CAN1RST);
30 rcu_periph_reset_disable(RCU_CAN1RST);
31 }
32 #else
33 if(CAN0 == can_periph){
34 rcu_periph_reset_enable(RCU_CAN0RST);
35 rcu_periph_reset_disable(RCU_CAN0RST);
36 }
37 #endif
38 }
RCU_CAN0RST
Definition: gd32f10x_rcu.h:468
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
RCU_CAN1RST
Definition: gd32f10x_rcu.h:470
can_error_enum can_error_get ( uint32_t can_periph )

get CAN error type

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
can_error_enum

Definition at line 640 of file gd32f10x_can.c.

641 {
642 can_error_enum error;
643 error = CAN_ERROR_NONE;
644
645 /* get error type */
646 error = (can_error_enum)((CAN_ERR(can_periph) & CAN_ERR_ERRN) >> 4U);
647 return error;
648 }
can_error_enum
can_error_enum
Definition: gd32f10x_can.h:400
CAN_ERR
#define CAN_ERR(canx)
Definition: gd32f10x_can.h:29
CAN_ERROR_NONE
Definition: gd32f10x_can.h:402
CAN_ERR_ERRN
#define CAN_ERR_ERRN
Definition: gd32f10x_can.h:209
void can_fifo_release | ( | uint32_t | can_periph,
 |  | uint8_t | fifo_number
 | ) |  |

release FIFO0

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
  • CAN_FIFOx(x=0,1)
[out] none
Return values
none

Definition at line 510 of file gd32f10x_can.c.

511 {
512 if(CAN_FIFO0 == fifo_number){
513 CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
514 }else if(CAN_FIFO1 == fifo_number){
515 CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
516 }else{
517 /* illegal parameter */
518 }
519 }
CAN_RFIFO1_RFD1
#define CAN_RFIFO1_RFD1
Definition: gd32f10x_can.h:187
CAN_RFIFO1
#define CAN_RFIFO1(canx)
Definition: gd32f10x_can.h:27
CAN_RFIFO0
#define CAN_RFIFO0(canx)
Definition: gd32f10x_can.h:26
CAN_FIFO1
#define CAN_FIFO1
Definition: gd32f10x_can.h:576
CAN_RFIFO0_RFD0
#define CAN_RFIFO0_RFD0
Definition: gd32f10x_can.h:181
CAN_FIFO0
#define CAN_FIFO0
Definition: gd32f10x_can.h:575
void can_filter_init ( can_filter_parameter_struct * can_filter_parameter_init )

initialize CAN filter

Parameters
[in] can_filter_parameter_init struct for CAN filter initialization
  • filter_list_high: 0x0000 - 0xFFFF
  • filter_list_low: 0x0000 - 0xFFFF
  • filter_mask_high: 0x0000 - 0xFFFF
  • filter_mask_low: 0x0000 - 0xFFFF
  • filter_fifo_number: CAN_FIFO0, CAN_FIFO1
  • filter_number: 0 - 27
  • filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST
  • filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT
  • filter_enable: ENABLE or DISABLE
[out] none
Return values
none

Definition at line 148 of file gd32f10x_can.c.

149 {
150 uint32_t val = 0U;
151
152 val = ((uint32_t)1) << (can_filter_parameter_init->filter_number);
153 /* filter lock disable */
154 CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
155 /* disable filter */
156 CAN_FW(CAN0) &= ~(uint32_t)val;
157
158 /* filter 16 bits */
159 if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){
160 /* set filter 16 bits */
161 CAN_FSCFG(CAN0) &= ~(uint32_t)val;
162 /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */
163 CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
164 FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \
165 FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
166 /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */
167 CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
168 FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \
169 FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS);
170 }
171 /* filter 32 bits */
172 if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){
173 /* set filter 32 bits */
174 CAN_FSCFG(CAN0) |= (uint32_t)val;
175 /* 32 bits list or first 32 bits list */
176 CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
177 FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) |
178 FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
179 /* 32 bits mask or second 32 bits list */
180 CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
181 FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) |
182 FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS);
183 }
184
185 /* filter mode */
186 if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){
187 /* mask mode */
188 CAN_FMCFG(CAN0) &= ~(uint32_t)val;
189 }else{
190 /* list mode */
191 CAN_FMCFG(CAN0) |= (uint32_t)val;
192 }
193
194 /* filter FIFO */
195 if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){
196 /* FIFO0 */
197 CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
198 }else{
199 /* FIFO1 */
200 CAN_FAFIFO(CAN0) |= (uint32_t)val;
201 }
202
203 /* filter working */
204 if(ENABLE == can_filter_parameter_init->filter_enable){
205
206 CAN_FW(CAN0) |= (uint32_t)val;
207 }
208
209 /* filter lock enable */
210 CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
211 }
can_filter_parameter_struct::filter_list_high
uint16_t filter_list_high
Definition: gd32f10x_can.h:388
can_filter_parameter_struct::filter_list_low
uint16_t filter_list_low
Definition: gd32f10x_can.h:389
can_filter_parameter_struct::filter_mode
uint16_t filter_mode
Definition: gd32f10x_can.h:394
FDATA_MASK_HIGH
#define FDATA_MASK_HIGH(regval)
Definition: gd32f10x_can.h:437
CAN_FILTERBITS_32BIT
#define CAN_FILTERBITS_32BIT
Definition: gd32f10x_can.h:591
CAN_FSCFG
#define CAN_FSCFG(canx)
Definition: gd32f10x_can.h:53
CAN_FILTER_MASK_16BITS
#define CAN_FILTER_MASK_16BITS
Definition: gd32f10x_can.h:598
CAN_FCTL
#define CAN_FCTL(canx)
Definition: gd32f10x_can.h:51
CAN_FW
#define CAN_FW(canx)
Definition: gd32f10x_can.h:55
can_filter_parameter_struct::filter_mask_low
uint16_t filter_mask_low
Definition: gd32f10x_can.h:391
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
can_filter_parameter_struct::filter_number
uint16_t filter_number
Definition: gd32f10x_can.h:393
CAN_FCTL_FLD
#define CAN_FCTL_FLD
Definition: gd32f10x_can.h:269
CAN_FMCFG
#define CAN_FMCFG(canx)
Definition: gd32f10x_can.h:52
can_filter_parameter_struct::filter_mask_high
uint16_t filter_mask_high
Definition: gd32f10x_can.h:390
CAN_FAFIFO
#define CAN_FAFIFO(canx)
Definition: gd32f10x_can.h:54
CAN_FDATA0
#define CAN_FDATA0(canx, bank)
Definition: gd32f10x_can.h:120
FDATA_MASK_LOW
#define FDATA_MASK_LOW(regval)
Definition: gd32f10x_can.h:440
can_filter_parameter_struct::filter_bits
uint16_t filter_bits
Definition: gd32f10x_can.h:395
can_filter_parameter_struct::filter_enable
ControlStatus filter_enable
Definition: gd32f10x_can.h:396
CAN_FDATA1
#define CAN_FDATA1(canx, bank)
Definition: gd32f10x_can.h:121
CAN_FILTERMODE_MASK
#define CAN_FILTERMODE_MASK
Definition: gd32f10x_can.h:594
CAN_FILTERBITS_16BIT
#define CAN_FILTERBITS_16BIT
Definition: gd32f10x_can.h:590
can_filter_parameter_struct::filter_fifo_number
uint16_t filter_fifo_number
Definition: gd32f10x_can.h:392
CAN_FIFO0
#define CAN_FIFO0
Definition: gd32f10x_can.h:575
void can_flag_clear | ( | uint32_t | can_periph,
 |  | can_flag_enum | flag
 | ) |  |

clear CAN flag state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] flag CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below:
  • CAN_FLAG_MTE2: mailbox 2 transmit error
  • CAN_FLAG_MTE1: mailbox 1 transmit error
  • CAN_FLAG_MTE0: mailbox 0 transmit error
  • CAN_FLAG_MTF2: mailbox 2 transmit finished
  • CAN_FLAG_MTF1: mailbox 1 transmit finished
  • CAN_FLAG_MTF0: mailbox 0 transmit finished
  • CAN_FLAG_RFO0: receive FIFO0 overfull
  • CAN_FLAG_RFF0: receive FIFO0 full
  • CAN_FLAG_RFO1: receive FIFO1 overfull
  • CAN_FLAG_RFF1: receive FIFO1 full
[out] none
Return values
none

Definition at line 784 of file gd32f10x_can.c.

785 {
786 CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag));
787 }
CAN_BIT_POS
#define CAN_BIT_POS(val)
Definition: gd32f10x_can.h:291
CAN_REG_VAL
#define CAN_REG_VAL(canx, offset)
Definition: gd32f10x_can.h:290
FlagStatus can_flag_get | ( | uint32_t | can_periph,
 |  | can_flag_enum | flag
 | ) |  |

get CAN flag state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] flag CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below:
  • CAN_FLAG_MTE2: mailbox 2 transmit error
  • CAN_FLAG_MTE1: mailbox 1 transmit error
  • CAN_FLAG_MTE0: mailbox 0 transmit error
  • CAN_FLAG_MTF2: mailbox 2 transmit finished
  • CAN_FLAG_MTF1: mailbox 1 transmit finished
  • CAN_FLAG_MTF0: mailbox 0 transmit finished
  • CAN_FLAG_RFO0: receive FIFO0 overfull
  • CAN_FLAG_RFF0: receive FIFO0 full
  • CAN_FLAG_RFO1: receive FIFO1 overfull
  • CAN_FLAG_RFF1: receive FIFO1 full
  • CAN_FLAG_BOERR: bus-off error
  • CAN_FLAG_PERR: passive error
  • CAN_FLAG_WERR: warning error
[out] none
Return values
FlagStatus SET or RESET

Definition at line 756 of file gd32f10x_can.c.

757 {
758 if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){
759 return SET;
760 }else{
761 return RESET;
762 }
763 }
CAN_BIT_POS
#define CAN_BIT_POS(val)
Definition: gd32f10x_can.h:291
CAN_REG_VAL
#define CAN_REG_VAL(canx, offset)
Definition: gd32f10x_can.h:290
ErrStatus can_init | ( | uint32_t | can_periph,
 |  | can_parameter_struct * | can_parameter_init
 | ) |  |

initialize CAN

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] can_parameter_init parameters for CAN initializtion
  • working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE
  • resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4)
  • time_segment_1: CAN_BT_BS1_xTQ(1..16)
  • time_segment_2: CAN_BT_BS2_xTQ(1..8)
  • time_triggered: ENABLE or DISABLE
  • auto_bus_off_recovery: ENABLE or DISABLE
  • auto_wake_up: ENABLE or DISABLE
  • auto_retrans: ENABLE or DISABLE
  • rec_fifo_overwrite: ENABLE or DISABLE
  • trans_fifo_order: ENABLE or DISABLE
  • prescaler: 0x0001 - 0x03FF
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 59 of file gd32f10x_can.c.

60 {
61 uint32_t timeout = CAN_TIMEOUT;
62 ErrStatus flag = ERROR;
63
64 /* disable sleep mode */
65 CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
66 /* enable initialize mode */
67 CAN_CTL(can_periph) |= CAN_CTL_IWMOD;
68 /* wait ACK */
69 while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){
70 timeout--;
71 }
72 /* check initialize working success */
73 if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
74 flag = ERROR;
75 }else{
76 /* set the bit timing register */
77 CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \
78 BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \
79 BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
80 BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
81 BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
82 /* time trigger communication mode */
83 if(ENABLE == can_parameter_init->time_triggered){
84 CAN_CTL(can_periph) |= CAN_CTL_TTC;
85 }else{
86 CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
87 }
88 /* automatic bus-off managment */
89 if(ENABLE == can_parameter_init->auto_bus_off_recovery){
90 CAN_CTL(can_periph) |= CAN_CTL_ABOR;
91 }else{
92 CAN_CTL(can_periph) &= ~CAN_CTL_ABOR;
93 }
94 /* automatic wakeup mode */
95 if(ENABLE == can_parameter_init->auto_wake_up){
96 CAN_CTL(can_periph) |= CAN_CTL_AWU;
97 }else{
98 CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
99 }
100 /* automatic retransmission mode */
101 if(ENABLE == can_parameter_init->auto_retrans){
102 CAN_CTL(can_periph) |= CAN_CTL_ARD;
103 }else{
104 CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
105 }
106 /* receive fifo overwrite mode */
107 if(ENABLE == can_parameter_init->rec_fifo_overwrite){
108 CAN_CTL(can_periph) |= CAN_CTL_RFOD;
109 }else{
110 CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
111 }
112 /* transmit fifo order */
113 if(ENABLE == can_parameter_init->trans_fifo_order){
114 CAN_CTL(can_periph) |= CAN_CTL_TFO;
115 }else{
116 CAN_CTL(can_periph) &= ~CAN_CTL_TFO;
117 }
118 /* disable initialize mode */
119 CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD;
120 timeout = CAN_TIMEOUT;
121 /* wait the ACK */
122 while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){
123 timeout--;
124 }
125 /* check exit initialize mode */
126 if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){
127 flag = SUCCESS;
128 }
129 }
130 return flag;
131 }
BT_BS2
#define BT_BS2(regval)
Definition: gd32f10x_can.h:428
can_parameter_struct::auto_wake_up
ControlStatus auto_wake_up
Definition: gd32f10x_can.h:355
can_parameter_struct::time_segment_1
uint8_t time_segment_1
Definition: gd32f10x_can.h:351
BT_BAUDPSC
#define BT_BAUDPSC(regval)
Definition: gd32f10x_can.h:422
CAN_CTL_IWMOD
#define CAN_CTL_IWMOD
Definition: gd32f10x_can.h:131
BT_MODE
#define BT_MODE(regval)
Definition: gd32f10x_can.h:434
CAN_STAT
#define CAN_STAT(canx)
Definition: gd32f10x_can.h:24
CAN_CTL_ABOR
#define CAN_CTL_ABOR
Definition: gd32f10x_can.h:137
BT_BS1
#define BT_BS1(regval)
Definition: gd32f10x_can.h:425
CAN_CTL_RFOD
#define CAN_CTL_RFOD
Definition: gd32f10x_can.h:134
can_parameter_struct::auto_bus_off_recovery
ControlStatus auto_bus_off_recovery
Definition: gd32f10x_can.h:354
can_parameter_struct::resync_jump_width
uint8_t resync_jump_width
Definition: gd32f10x_can.h:350
can_parameter_struct::rec_fifo_overwrite
ControlStatus rec_fifo_overwrite
Definition: gd32f10x_can.h:357
can_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f10x_can.h:359
CAN_CTL_ARD
#define CAN_CTL_ARD
Definition: gd32f10x_can.h:135
CAN_CTL_SLPWMOD
#define CAN_CTL_SLPWMOD
Definition: gd32f10x_can.h:132
CAN_TIMEOUT
#define CAN_TIMEOUT
Definition: gd32f10x_can.h:605
can_parameter_struct::time_triggered
ControlStatus time_triggered
Definition: gd32f10x_can.h:353
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_CTL_AWU
#define CAN_CTL_AWU
Definition: gd32f10x_can.h:136
CAN_STAT_IWS
#define CAN_STAT_IWS
Definition: gd32f10x_can.h:143
BT_SJW
#define BT_SJW(regval)
Definition: gd32f10x_can.h:431
CAN_CTL_TFO
#define CAN_CTL_TFO
Definition: gd32f10x_can.h:133
can_parameter_struct::trans_fifo_order
ControlStatus trans_fifo_order
Definition: gd32f10x_can.h:358
CAN_CTL_TTC
#define CAN_CTL_TTC
Definition: gd32f10x_can.h:138
can_parameter_struct::time_segment_2
uint8_t time_segment_2
Definition: gd32f10x_can.h:352
can_parameter_struct::auto_retrans
ControlStatus auto_retrans
Definition: gd32f10x_can.h:356
CAN_BT
#define CAN_BT(canx)
Definition: gd32f10x_can.h:30
can_parameter_struct::working_mode
uint8_t working_mode
Definition: gd32f10x_can.h:349
void can_interrupt_disable | ( | uint32_t | can_periph,
 |  | uint32_t | interrupt
 | ) |  |

disable CAN interrupt

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] interrupt
  • CAN_INT_TME: transmit mailbox empty interrupt enable
  • CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
  • CAN_INT_RFF0: receive FIFO0 full interrupt enable
  • CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
  • CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
  • CAN_INT_RFF1: receive FIFO1 full interrupt enable
  • CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
  • CAN_INT_WERR: warning error interrupt enable
  • CAN_INT_PERR: passive error interrupt enable
  • CAN_INT_BO: bus-off interrupt enable
  • CAN_INT_ERRN: error number interrupt enable
  • CAN_INT_ERR: error interrupt enable
  • CAN_INT_WU: wakeup interrupt enable
  • CAN_INT_SLPW: sleep working interrupt enable
[out] none
Return values
none

Definition at line 729 of file gd32f10x_can.c.

730 {
731 CAN_INTEN(can_periph) &= ~interrupt;
732 }
CAN_INTEN
#define CAN_INTEN(canx)
Definition: gd32f10x_can.h:28
void can_interrupt_enable | ( | uint32_t | can_periph,
 |  | uint32_t | interrupt
 | ) |  |

enable CAN interrupt

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] interrupt
  • CAN_INT_TME: transmit mailbox empty interrupt enable
  • CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
  • CAN_INT_RFF0: receive FIFO0 full interrupt enable
  • CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
  • CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
  • CAN_INT_RFF1: receive FIFO1 full interrupt enable
  • CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
  • CAN_INT_WERR: warning error interrupt enable
  • CAN_INT_PERR: passive error interrupt enable
  • CAN_INT_BO: bus-off interrupt enable
  • CAN_INT_ERRN: error number interrupt enable
  • CAN_INT_ERR: error interrupt enable
  • CAN_INT_WU: wakeup interrupt enable
  • CAN_INT_SLPW: sleep working interrupt enable
[out] none
Return values
none

Definition at line 702 of file gd32f10x_can.c.

703 {
704 CAN_INTEN(can_periph) |= interrupt;
705 }
CAN_INTEN
#define CAN_INTEN(canx)
Definition: gd32f10x_can.h:28
void can_interrupt_flag_clear | ( | uint32_t | can_periph,
 |  | can_interrupt_flag_enum | flag
 | ) |  |

clear CAN interrupt flag state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] flag CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below:
  • CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
  • CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
  • CAN_INT_FLAG_ERRIF: error interrupt flag
  • CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
  • CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
  • CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
  • CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
  • CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
  • CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
  • CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
[out] none
Return values
none

Definition at line 843 of file gd32f10x_can.c.

844 {
845 CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag));
846 }
CAN_REG_VALS
#define CAN_REG_VALS(canx, offset)
Definition: gd32f10x_can.h:294
CAN_BIT_POS0
#define CAN_BIT_POS0(val)
Definition: gd32f10x_can.h:295
FlagStatus can_interrupt_flag_get | ( | uint32_t | can_periph,
 |  | can_interrupt_flag_enum | flag
 | ) |  |

get CAN interrupt flag state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] flag CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below:
  • CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
  • CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
  • CAN_INT_FLAG_ERRIF: error interrupt flag
  • CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
  • CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
  • CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
  • CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
  • CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
  • CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
  • CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 808 of file gd32f10x_can.c.

809 {
810 FlagStatus ret1 = RESET;
811 FlagStatus ret2 = RESET;
812
813 /* get the staus of interrupt flag */
814 ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)));
815 /* get the staus of interrupt enale bit */
816 ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)));
817 if(ret1 && ret2){
818 return SET;
819 }else{
820 return RESET;
821 }
822 }
CAN_REG_VALS
#define CAN_REG_VALS(canx, offset)
Definition: gd32f10x_can.h:294
CAN_BIT_POS1
#define CAN_BIT_POS1(val)
Definition: gd32f10x_can.h:296
CAN_INTEN
#define CAN_INTEN(canx)
Definition: gd32f10x_can.h:28
CAN_BIT_POS0
#define CAN_BIT_POS0(val)
Definition: gd32f10x_can.h:295
void can_message_receive | ( | uint32_t | can_periph,
 |  | uint8_t | fifo_number,
 |  | can_receive_message_struct * | receive_message
 | ) |  |

CAN receive message.

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] fifo_number
  • CAN_FIFOx(x=0,1)
[out] receive_message struct for CAN receive message
  • rx_sfid: 0x00000000 - 0x000007FF
  • rx_efid: 0x00000000 - 0x1FFFFFFF
  • rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
  • rx_ft: CAN_FT_DATA, CAN_FT_REMOTE
  • rx_dlenc: 1 - 7
  • rx_data[]: 0x00 - 0xFF
  • rx_fi: 0 - 27
Return values
none

Definition at line 465 of file gd32f10x_can.c.

466 {
467 /* get the frame format */
468 receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number));
469 if(CAN_FF_STANDARD == receive_message->rx_ff){
470 /* get standard identifier */
471 receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number)));
472 }else{
473 /* get extended identifier */
474 receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number)));
475 }
476
477 /* get frame type */
478 receive_message -> rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number));
479 /* get recevie data length */
480 receive_message -> rx_dlen = (uint8_t)(RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number)));
481 /* filtering index */
482 receive_message -> rx_fi = (uint8_t)(RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number)));
483
484 /* receive data */
485 receive_message -> rx_data[0] = (uint8_t)(RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number)));
486 receive_message -> rx_data[1] = (uint8_t)(RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number)));
487 receive_message -> rx_data[2] = (uint8_t)(RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number)));
488 receive_message -> rx_data[3] = (uint8_t)(RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number)));
489 receive_message -> rx_data[4] = (uint8_t)(RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number)));
490 receive_message -> rx_data[5] = (uint8_t)(RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number)));
491 receive_message -> rx_data[6] = (uint8_t)(RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number)));
492 receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number)));
493
494 /* release FIFO */
495 if(CAN_FIFO0 == fifo_number){
496 CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
497 }else{
498 CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
499 }
500 }
RFIFOMDATA0_DB0
#define RFIFOMDATA0_DB0(regval)
Definition: gd32f10x_can.h:488
CAN_RFIFOMDATA0
#define CAN_RFIFOMDATA0(canx, bank)
Definition: gd32f10x_can.h:126
CAN_RFIFO1_RFD1
#define CAN_RFIFO1_RFD1
Definition: gd32f10x_can.h:187
RFIFOMDATA1_DB6
#define RFIFOMDATA1_DB6(regval)
Definition: gd32f10x_can.h:506
can_receive_message_struct::rx_ff
uint8_t rx_ff
Definition: gd32f10x_can.h:378
RFIFOMI_SFID
#define RFIFOMI_SFID(regval)
Definition: gd32f10x_can.h:479
CAN_RFIFOMDATA1
#define CAN_RFIFOMDATA1(canx, bank)
Definition: gd32f10x_can.h:127
RFIFOMP_FI
#define RFIFOMP_FI(regval)
Definition: gd32f10x_can.h:485
CAN_RFIFO1
#define CAN_RFIFO1(canx)
Definition: gd32f10x_can.h:27
RFIFOMI_EFID
#define RFIFOMI_EFID(regval)
Definition: gd32f10x_can.h:476
CAN_RFIFO0
#define CAN_RFIFO0(canx)
Definition: gd32f10x_can.h:26
RFIFOMDATA0_DB1
#define RFIFOMDATA0_DB1(regval)
Definition: gd32f10x_can.h:491
RFIFOMDATA1_DB4
#define RFIFOMDATA1_DB4(regval)
Definition: gd32f10x_can.h:500
RFIFOMDATA1_DB5
#define RFIFOMDATA1_DB5(regval)
Definition: gd32f10x_can.h:503
CAN_RFIFOMI
#define CAN_RFIFOMI(canx, bank)
Definition: gd32f10x_can.h:124
CAN_RFIFO0_RFD0
#define CAN_RFIFO0_RFD0
Definition: gd32f10x_can.h:181
CAN_RFIFOMI_FF
#define CAN_RFIFOMI_FF
Definition: gd32f10x_can.h:247
RFIFOMDATA1_DB7
#define RFIFOMDATA1_DB7(regval)
Definition: gd32f10x_can.h:509
CAN_FF_STANDARD
#define CAN_FF_STANDARD
Definition: gd32f10x_can.h:571
RFIFOMDATA0_DB2
#define RFIFOMDATA0_DB2(regval)
Definition: gd32f10x_can.h:494
CAN_RFIFOMI_FT
#define CAN_RFIFOMI_FT
Definition: gd32f10x_can.h:246
RFIFOMP_DLENC
#define RFIFOMP_DLENC(regval)
Definition: gd32f10x_can.h:482
CAN_RFIFOMP
#define CAN_RFIFOMP(canx, bank)
Definition: gd32f10x_can.h:125
RFIFOMDATA0_DB3
#define RFIFOMDATA0_DB3(regval)
Definition: gd32f10x_can.h:497
CAN_FIFO0
#define CAN_FIFO0
Definition: gd32f10x_can.h:575
uint8_t can_message_transmit | ( | uint32_t | can_periph,
 |  | can_trasnmit_message_struct * | transmit_message
 | ) |  |

transmit CAN message

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] transmit_message struct for CAN transmit message
  • tx_sfid: 0x00000000 - 0x000007FF
  • tx_efid: 0x00000000 - 0x1FFFFFFF
  • tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
  • tx_ft: CAN_FT_DATA, CAN_FT_REMOTE
  • tx_dlenc: 1 - 7
  • tx_data[]: 0x00 - 0xFF
[out] none
Return values
mailbox_number

Definition at line 329 of file gd32f10x_can.c.

330 {
331 uint8_t mailbox_number = CAN_MAILBOX0;
332
333 /* select one empty mailbox */
334 if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){
335 mailbox_number = CAN_MAILBOX0;
336 }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){
337 mailbox_number = CAN_MAILBOX1;
338 }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){
339 mailbox_number = CAN_MAILBOX2;
340 }else{
341 mailbox_number = CAN_NOMAILBOX;
342 }
343 if(CAN_NOMAILBOX == mailbox_number){
344 return CAN_NOMAILBOX;
345 }
346
347 CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN;
348 if(CAN_FF_STANDARD == transmit_message->tx_ff){
349 /* set transmit mailbox standard identifier */
350 CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \
351 transmit_message->tx_ft);
352 }else{
353 /* set transmit mailbox extended identifier */
354 CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \
355 transmit_message->tx_ff | \
356 transmit_message->tx_ft);
357 }
358 /* set the data length */
359 CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC);
360 CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
361 /* set the data */
362 CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \
363 TMDATA0_DB2(transmit_message->tx_data[2]) | \
364 TMDATA0_DB1(transmit_message->tx_data[1]) | \
365 TMDATA0_DB0(transmit_message->tx_data[0]);
366 CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \
367 TMDATA1_DB6(transmit_message->tx_data[6]) | \
368 TMDATA1_DB5(transmit_message->tx_data[5]) | \
369 TMDATA1_DB4(transmit_message->tx_data[4]);
370 /* enable transmission */
371 CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN;
372
373 return mailbox_number;
374 }
CAN_TMDATA0
#define CAN_TMDATA0(canx, bank)
Definition: gd32f10x_can.h:116
CAN_TSTAT
#define CAN_TSTAT(canx)
Definition: gd32f10x_can.h:25
TMDATA0_DB3
#define TMDATA0_DB3(regval)
Definition: gd32f10x_can.h:461
CAN_TMI
#define CAN_TMI(canx, bank)
Definition: gd32f10x_can.h:114
can_trasnmit_message_struct::tx_dlen
uint8_t tx_dlen
Definition: gd32f10x_can.h:369
TMDATA1_DB5
#define TMDATA1_DB5(regval)
Definition: gd32f10x_can.h:467
TMDATA0_DB0
#define TMDATA0_DB0(regval)
Definition: gd32f10x_can.h:452
can_trasnmit_message_struct::tx_sfid
uint32_t tx_sfid
Definition: gd32f10x_can.h:365
CAN_TSTAT_TME2
#define CAN_TSTAT_TME2
Definition: gd32f10x_can.h:172
can_trasnmit_message_struct::tx_ff
uint8_t tx_ff
Definition: gd32f10x_can.h:367
CAN_TSTAT_TME1
#define CAN_TSTAT_TME1
Definition: gd32f10x_can.h:171
can_trasnmit_message_struct::tx_efid
uint32_t tx_efid
Definition: gd32f10x_can.h:366
CAN_TMP_DLENC
#define CAN_TMP_DLENC
Definition: gd32f10x_can.h:229
TMDATA0_DB1
#define TMDATA0_DB1(regval)
Definition: gd32f10x_can.h:455
TMDATA1_DB6
#define TMDATA1_DB6(regval)
Definition: gd32f10x_can.h:470
can_trasnmit_message_struct::tx_data
uint8_t tx_data[8]
Definition: gd32f10x_can.h:370
CAN_NOMAILBOX
#define CAN_NOMAILBOX
Definition: gd32f10x_can.h:568
CAN_TMDATA1
#define CAN_TMDATA1(canx, bank)
Definition: gd32f10x_can.h:117
CAN_TSTAT_TME0
#define CAN_TSTAT_TME0
Definition: gd32f10x_can.h:170
CAN_FF_STANDARD
#define CAN_FF_STANDARD
Definition: gd32f10x_can.h:571
CAN_TMP
#define CAN_TMP(canx, bank)
Definition: gd32f10x_can.h:115
CAN_MAILBOX0
#define CAN_MAILBOX0
Definition: gd32f10x_can.h:565
CAN_MAILBOX2
#define CAN_MAILBOX2
Definition: gd32f10x_can.h:567
CAN_MAILBOX1
#define CAN_MAILBOX1
Definition: gd32f10x_can.h:566
TMDATA1_DB7
#define TMDATA1_DB7(regval)
Definition: gd32f10x_can.h:473
TMDATA0_DB2
#define TMDATA0_DB2(regval)
Definition: gd32f10x_can.h:458
TMDATA1_DB4
#define TMDATA1_DB4(regval)
Definition: gd32f10x_can.h:464
TMI_SFID
#define TMI_SFID(regval)
Definition: gd32f10x_can.h:449
TMI_EFID
#define TMI_EFID(regval)
Definition: gd32f10x_can.h:446
CAN_TMI_TEN
#define CAN_TMI_TEN
Definition: gd32f10x_can.h:222
uint8_t can_receive_error_number_get ( uint32_t can_periph )

get CAN receive error number

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
error number

Definition at line 657 of file gd32f10x_can.c.

658 {
659 uint8_t val;
660
661 val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_RECNT) >> 24U);
662 return val;
663 }
CAN_ERR
#define CAN_ERR(canx)
Definition: gd32f10x_can.h:29
CAN_ERR_RECNT
#define CAN_ERR_RECNT
Definition: gd32f10x_can.h:211
uint8_t can_receive_message_length_get | ( | uint32_t | can_periph,
 |  | uint8_t | fifo_number
 | ) |  |

CAN receive message length.

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL \
  • CAN_FIFOx(x=0,1)
[out] none
Return values
message length

Definition at line 530 of file gd32f10x_can.c.

531 {
532 uint8_t val = 0U;
533
534 if(CAN_FIFO0 == fifo_number){
535 val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK);
536 }else if(CAN_FIFO1 == fifo_number){
537 val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK);
538 }else{
539 /* illegal parameter */
540 }
541 return val;
542 }
CAN_RFIF_RFL_MASK
#define CAN_RFIF_RFL_MASK
Definition: gd32f10x_can.h:579
CAN_RFIFO1
#define CAN_RFIFO1(canx)
Definition: gd32f10x_can.h:27
CAN_RFIFO0
#define CAN_RFIFO0(canx)
Definition: gd32f10x_can.h:26
CAN_FIFO1
#define CAN_FIFO1
Definition: gd32f10x_can.h:576
CAN_FIFO0
#define CAN_FIFO0
Definition: gd32f10x_can.h:575
void can_time_trigger_mode_disable ( uint32_t can_periph )

disable CAN time trigger mode

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 303 of file gd32f10x_can.c.

304 {
305 uint8_t mailbox_number;
306
307 /* disable the TCC mode */
308 CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
309 /* reset TSEN bits */
310 for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){
311 CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN;
312 }
313 }
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_TMP
#define CAN_TMP(canx, bank)
Definition: gd32f10x_can.h:115
CAN_CTL_TTC
#define CAN_CTL_TTC
Definition: gd32f10x_can.h:138
CAN_TMP_TSEN
#define CAN_TMP_TSEN
Definition: gd32f10x_can.h:230
void can_time_trigger_mode_enable ( uint32_t can_periph )

enable CAN time trigger mode

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
none

Definition at line 284 of file gd32f10x_can.c.

285 {
286 uint8_t mailbox_number;
287
288 /* enable the tcc mode */
289 CAN_CTL(can_periph) |= CAN_CTL_TTC;
290 /* enable time stamp */
291 for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){
292 CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN;
293 }
294 }
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_TMP
#define CAN_TMP(canx, bank)
Definition: gd32f10x_can.h:115
CAN_CTL_TTC
#define CAN_CTL_TTC
Definition: gd32f10x_can.h:138
CAN_TMP_TSEN
#define CAN_TMP_TSEN
Definition: gd32f10x_can.h:230
void can_transmission_stop | ( | uint32_t | can_periph,
 |  | uint8_t | mailbox_number
 | ) |  |

stop CAN transmission

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] mailbox_number only one parameter can be selected which is shown as below:
  • CAN_MAILBOXx(x=0,1,2)
[out] none
Return values
none

Definition at line 436 of file gd32f10x_can.c.

437 {
438 if(CAN_MAILBOX0 == mailbox_number){
439 CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
440 }else if(CAN_MAILBOX1 == mailbox_number){
441 CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
442 }else if(CAN_MAILBOX2 == mailbox_number){
443 CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
444 }else{
445 /* illegal parameter*/
446 }
447 }
CAN_TSTAT
#define CAN_TSTAT(canx)
Definition: gd32f10x_can.h:25
CAN_TSTAT_MST1
#define CAN_TSTAT_MST1
Definition: gd32f10x_can.h:163
CAN_TSTAT_MST0
#define CAN_TSTAT_MST0
Definition: gd32f10x_can.h:158
CAN_MAILBOX0
#define CAN_MAILBOX0
Definition: gd32f10x_can.h:565
CAN_MAILBOX2
#define CAN_MAILBOX2
Definition: gd32f10x_can.h:567
CAN_MAILBOX1
#define CAN_MAILBOX1
Definition: gd32f10x_can.h:566
CAN_TSTAT_MST2
#define CAN_TSTAT_MST2
Definition: gd32f10x_can.h:168
uint8_t can_transmit_error_number_get ( uint32_t can_periph )

get CAN transmit error number

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
error number

Definition at line 672 of file gd32f10x_can.c.

673 {
674 uint8_t val;
675
676 val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_TECNT) >> 16U);
677 return val;
678 }
CAN_ERR
#define CAN_ERR(canx)
Definition: gd32f10x_can.h:29
CAN_ERR_TECNT
#define CAN_ERR_TECNT
Definition: gd32f10x_can.h:210
can_transmit_state_enum can_transmit_states | ( | uint32_t | can_periph,
 |  | uint8_t | mailbox_number
 | ) |  |

get CAN transmit state

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] mailbox_number
  • CAN_MAILBOX(x=0,1,2)
[out] none
Return values
can_transmit_state_enum

Definition at line 385 of file gd32f10x_can.c.

386 {
387 can_transmit_state_enum state = CAN_TRANSMIT_FAILED;
388 uint32_t val = 0U;
389
390 switch(mailbox_number){
391 case CAN_MAILBOX0:
392 val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0);
393 break;
394 case CAN_MAILBOX1:
395 val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1);
396 break;
397 case CAN_MAILBOX2:
398 val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2);
399 break;
400 default:
401 val = CAN_TRANSMIT_FAILED;
402 break;
403 }
404 switch(val){
405 /* transmit pending */
406 case (CAN_STATE_PENDING):
407 state = CAN_TRANSMIT_PENDING;
408 break;
409 /* transmit succeeded */
410 case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0):
411 state = CAN_TRANSMIT_OK;
412 break;
413 case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1):
414 state = CAN_TRANSMIT_OK;
415 break;
416 case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2):
417 state = CAN_TRANSMIT_OK;
418 break;
419 default:
420 state = CAN_TRANSMIT_FAILED;
421 break;
422 }
423 return state;
424 }
CAN_TSTAT_MTFNERR1
#define CAN_TSTAT_MTFNERR1
Definition: gd32f10x_can.h:160
can_transmit_state_enum
can_transmit_state_enum
Definition: gd32f10x_can.h:413
CAN_TSTAT
#define CAN_TSTAT(canx)
Definition: gd32f10x_can.h:25
CAN_TSTAT_MTF1
#define CAN_TSTAT_MTF1
Definition: gd32f10x_can.h:159
CAN_TRANSMIT_FAILED
Definition: gd32f10x_can.h:415
CAN_TSTAT_TME2
#define CAN_TSTAT_TME2
Definition: gd32f10x_can.h:172
CAN_TSTAT_TME1
#define CAN_TSTAT_TME1
Definition: gd32f10x_can.h:171
CAN_TSTAT_MTF0
#define CAN_TSTAT_MTF0
Definition: gd32f10x_can.h:154
CAN_TRANSMIT_PENDING
Definition: gd32f10x_can.h:417
CAN_TSTAT_TME0
#define CAN_TSTAT_TME0
Definition: gd32f10x_can.h:170
CAN_TSTAT_MTF2
#define CAN_TSTAT_MTF2
Definition: gd32f10x_can.h:164
CAN_MAILBOX0
#define CAN_MAILBOX0
Definition: gd32f10x_can.h:565
CAN_TRANSMIT_OK
Definition: gd32f10x_can.h:416
CAN_MAILBOX2
#define CAN_MAILBOX2
Definition: gd32f10x_can.h:567
CAN_MAILBOX1
#define CAN_MAILBOX1
Definition: gd32f10x_can.h:566
CAN_TSTAT_MTFNERR0
#define CAN_TSTAT_MTFNERR0
Definition: gd32f10x_can.h:155
CAN_STATE_PENDING
#define CAN_STATE_PENDING
Definition: gd32f10x_can.h:522
CAN_TSTAT_MTFNERR2
#define CAN_TSTAT_MTFNERR2
Definition: gd32f10x_can.h:165
ErrStatus can_wakeup ( uint32_t can_periph )

wake up CAN

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 614 of file gd32f10x_can.c.

615 {
616 ErrStatus flag = ERROR;
617 uint32_t timeout = CAN_TIMEOUT;
618
619 /* wakeup */
620 CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
621
622 while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){
623 timeout--;
624 }
625 if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
626 flag = ERROR;
627 }else{
628 flag = SUCCESS;
629 }
630 return flag;
631 }
CAN_STAT
#define CAN_STAT(canx)
Definition: gd32f10x_can.h:24
CAN_CTL_SLPWMOD
#define CAN_CTL_SLPWMOD
Definition: gd32f10x_can.h:132
CAN_TIMEOUT
#define CAN_TIMEOUT
Definition: gd32f10x_can.h:605
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_STAT_SLPWS
#define CAN_STAT_SLPWS
Definition: gd32f10x_can.h:144
ErrStatus can_working_mode_set | ( | uint32_t | can_periph,
 |  | uint8_t | working_mode
 | ) |  |

set CAN working mode

Parameters
[in] can_periph
  • CANx(x=0,1),the CAN1 only for GD32F10x_CL
[in] can_working_mode
  • CAN_MODE_INITIALIZE
  • CAN_MODE_NORMAL
  • CAN_MODE_SLEEP
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 555 of file gd32f10x_can.c.

556 {
557 ErrStatus flag = ERROR;
558 /* timeout for IWS or also for SLPWS bits */
559 uint32_t timeout = CAN_TIMEOUT;
560
561 if(CAN_MODE_INITIALIZE == working_mode){
562 /* disable sleep mode */
563 CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD);
564 /* set initialize mode */
565 CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD;
566 /* wait the acknowledge */
567 while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
568 timeout--;
569 }
570 if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
571 flag = ERROR;
572 }else{
573 flag = SUCCESS;
574 }
575 }else if(CAN_MODE_NORMAL == working_mode){
576 /* enter normal mode */
577 CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD);
578 /* wait the acknowledge */
579 while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){
580 timeout--;
581 }
582 if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){
583 flag = ERROR;
584 }else{
585 flag = SUCCESS;
586 }
587 }else if(CAN_MODE_SLEEP == working_mode){
588 /* disable initialize mode */
589 CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD);
590 /* set sleep mode */
591 CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD;
592 /* wait the acknowledge */
593 while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){
594 timeout--;
595 }
596 if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
597 flag = ERROR;
598 }else{
599 flag = SUCCESS;
600 }
601 }else{
602 flag = ERROR;
603 }
604 return flag;
605 }
CAN_MODE_NORMAL
#define CAN_MODE_NORMAL
Definition: gd32f10x_can.h:586
CAN_CTL_IWMOD
#define CAN_CTL_IWMOD
Definition: gd32f10x_can.h:131
CAN_STAT
#define CAN_STAT(canx)
Definition: gd32f10x_can.h:24
CAN_MODE_SLEEP
#define CAN_MODE_SLEEP
Definition: gd32f10x_can.h:587
CAN_MODE_INITIALIZE
#define CAN_MODE_INITIALIZE
Definition: gd32f10x_can.h:585
CAN_CTL_SLPWMOD
#define CAN_CTL_SLPWMOD
Definition: gd32f10x_can.h:132
CAN_TIMEOUT
#define CAN_TIMEOUT
Definition: gd32f10x_can.h:605
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_STAT_IWS
#define CAN_STAT_IWS
Definition: gd32f10x_can.h:143
CAN_STAT_SLPWS
#define CAN_STAT_SLPWS
Definition: gd32f10x_can.h:144
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_crc.c File Reference

CRC driver. More...

#include "gd32f10x_crc.h"

Go to the source code of this file.

Functions

void | crc_deinit (void)
deinit CRC calculation unit More...
void | crc_data_register_reset (void)
reset data register to the value of initializaiton data register More...
uint32_t | crc_data_register_read (void)
read the data register More...
uint8_t | crc_free_data_register_read (void)
read the free data register More...
void | crc_free_data_register_write (uint8_t free_data)
write the free data register More...
uint32_t | crc_single_data_calculate (uint32_t sdata)
CRC calculate a 32-bit data. More...
uint32_t | crc_block_data_calculate (uint32_t array[], uint32_t size)
CRC calculate a 32-bit data array. More...

Detailed Description

CRC driver.

Definition in file gd32f10x_crc.c.

Function Documentation

uint32_t crc_block_data_calculate | ( | uint32_t | array[],
 |  | uint32_t | size
 | ) |  |

CRC calculate a 32-bit data array.

Parameters
[in] | array | pointer to an array of 32 bit data words
[in] | size | size of the array
[out] | none
Return values
32-bit CRC calculate value

Definition at line 95 of file gd32f10x_crc.c.

96 {
97 uint32_t index;
98 for(index = 0U; index < size; index++){
99 CRC_DATA = array[index];
100 }
101 return (CRC_DATA);
102 }
CRC_DATA
#define CRC_DATA
Definition: gd32f10x_crc.h:22
uint32_t crc_data_register_read ( void )

read the data register

Parameters
[in] | none
[out] | none
Return values
32-bit value of the data register

Definition at line 45 of file gd32f10x_crc.c.

46 {
47 uint32_t data;
48 data = CRC_DATA;
49 return (data);
50 }
CRC_DATA
#define CRC_DATA
Definition: gd32f10x_crc.h:22
void crc_data_register_reset ( void )

reset data register to the value of initializaiton data register

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 34 of file gd32f10x_crc.c.

35 {
36 CRC_CTL |= (uint32_t)CRC_CTL_RST;
37 }
CRC_CTL
#define CRC_CTL
Definition: gd32f10x_crc.h:24
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f10x_crc.h:34
void crc_deinit ( void )

deinit CRC calculation unit

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_crc.c.

22 {
23 CRC_DATA = (uint32_t)0xFFFFFFFFU;
24 CRC_FDATA = (uint32_t)0x00000000U;
25 CRC_CTL = (uint32_t)CRC_CTL_RST;
26 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f10x_crc.h:23
CRC_CTL
#define CRC_CTL
Definition: gd32f10x_crc.h:24
CRC_DATA
#define CRC_DATA
Definition: gd32f10x_crc.h:22
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f10x_crc.h:34
uint8_t crc_free_data_register_read ( void )

read the free data register

Parameters
[in] | none
[out] | none
Return values
8-bit value of the free data register

Definition at line 58 of file gd32f10x_crc.c.

59 {
60 uint8_t fdata;
61 fdata = (uint8_t)CRC_FDATA;
62 return (fdata);
63 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f10x_crc.h:23
void crc_free_data_register_write ( uint8_t free_data )

write the free data register

Parameters
[in] | free_data | specify 8-bit data
[out] | none
Return values
none

Definition at line 71 of file gd32f10x_crc.c.

72 {
73 CRC_FDATA = (uint32_t)free_data;
74 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f10x_crc.h:23
uint32_t crc_single_data_calculate ( uint32_t sdata )

CRC calculate a 32-bit data.

Parameters
[in] | sdata | specify 32-bit data
[out] | none
Return values
32-bit CRC calculate value

Definition at line 82 of file gd32f10x_crc.c.

83 {
84 CRC_DATA = sdata;
85 return (CRC_DATA);
86 }
CRC_DATA
#define CRC_DATA
Definition: gd32f10x_crc.h:22
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_dac.c File Reference

DAC driver. More...

#include "gd32f10x_dac.h"

Go to the source code of this file.

Functions

void | dac_deinit (void)
deinitialize DAC More...
void | dac_enable (uint32_t dac_periph)
enable DAC More...
void | dac_disable (uint32_t dac_periph)
disable DAC More...
void | dac_dma_enable (uint32_t dac_periph)
enable DAC DMA function More...
void | dac_dma_disable (uint32_t dac_periph)
disable DAC DMA function More...
void | dac_output_buffer_enable (uint32_t dac_periph)
enable DAC output buffer More...
void | dac_output_buffer_disable (uint32_t dac_periph)
disable DAC output buffer More...
void | dac_trigger_enable (uint32_t dac_periph)
enable DAC trigger More...
void | dac_trigger_disable (uint32_t dac_periph)
disable DAC trigger More...
void | dac_software_trigger_enable (uint32_t dac_periph)
enable DAC software trigger More...
void | dac_software_trigger_disable (uint32_t dac_periph)
disable DAC software trigger More...
void | dac_trigger_source_config (uint32_t dac_periph, uint32_t triggersource)
set DAC trigger source More...
void | dac_wave_mode_config (uint32_t dac_periph, uint32_t wave_mode)
configure DAC wave mode More...
void | dac_wave_bit_width_config (uint32_t dac_periph, uint32_t bit_width)
configure DAC wave bit width More...
void | dac_lfsr_noise_config (uint32_t dac_periph, uint32_t unmask_bits)
configure DAC LFSR noise mode More...
void | dac_triangle_noise_config (uint32_t dac_periph, uint32_t amplitude)
configure DAC triangle noise mode More...
uint16_t | dac_output_value_get (uint32_t dac_periph)
get DAC output value More...
void | dac_concurrent_enable (void)
enable DAC concurrent mode More...
void | dac_concurrent_disable (void)
disable DAC concurrent mode More...
void | dac_concurrent_software_trigger_enable (void)
enable DAC concurrent software trigger function More...
void | dac_concurrent_software_trigger_disable (void)
disable DAC concurrent software trigger function More...
void | dac_concurrent_output_buffer_enable (void)
enable DAC concurrent buffer function More...
void | dac_concurrent_output_buffer_disable (void)
disable DAC concurrent buffer function More...
void | dac_data_set (uint32_t dac_periph, uint32_t dac_align, uint16_t data)
set the DAC specified data holding register value More...
void | dac_concurrent_data_set (uint32_t dac_align, uint16_t data0, uint16_t data1)
set DAC concurrent mode data holding register value More...

Detailed Description

DAC driver.

Definition in file gd32f10x_dac.c.

Function Documentation

void dac_concurrent_data_set | ( | uint32_t | dac_align,
 |  | uint16_t | data0,
 |  | uint16_t | data1
 | ) |  |

set DAC concurrent mode data holding register value

Parameters
[in] dac_align
  • DAC_ALIGN_8B_R: data right 8b alignment
  • DAC_ALIGN_12B_R: data right 12b alignment
  • DAC_ALIGN_12B_L: data left 12b alignment
[in] | data0 | data to be loaded
[in] | data1 | data to be loaded
[out] | none
Return values
none

Definition at line 487 of file gd32f10x_dac.c.

488 {
489 uint32_t data = 0U;
490 switch(dac_align){
491 /* data right 12b alignment */
492 case DAC_ALIGN_12B_R:
493 data = ((uint32_t)data1 << 16) | data0;
494 DACC_R12DH = data;
495 break;
496 /* data left 12b alignment */
497 case DAC_ALIGN_12B_L:
498 data = ((uint32_t)data1 << 16) | data0;
499 DACC_L12DH = data;
500 break;
501 /* data right 8b alignment */
502 case DAC_ALIGN_8B_R:
503 data = ((uint32_t)data1 << 8) | data0;
504 DACC_R8DH = data;
505 break;
506 default:
507 break;
508 }
509 }
DACC_L12DH
#define DACC_L12DH
Definition: gd32f10x_dac.h:33
DACC_R12DH
#define DACC_R12DH
Definition: gd32f10x_dac.h:32
DACC_R8DH
#define DACC_R8DH
Definition: gd32f10x_dac.h:34
DAC_ALIGN_12B_R
#define DAC_ALIGN_12B_R
Definition: gd32f10x_dac.h:162
DAC_ALIGN_12B_L
#define DAC_ALIGN_12B_L
Definition: gd32f10x_dac.h:163
DAC_ALIGN_8B_R
#define DAC_ALIGN_8B_R
Definition: gd32f10x_dac.h:164
void dac_concurrent_disable ( void )

disable DAC concurrent mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 366 of file gd32f10x_dac.c.

367 {
368 uint32_t ctl = 0U;
369 ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
370 DAC_CTL &= (~ctl);
371 }
DAC_CTL_DEN1
#define DAC_CTL_DEN1
Definition: gd32f10x_dac.h:47
DAC_CTL_DEN0
#define DAC_CTL_DEN0
Definition: gd32f10x_dac.h:40
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
void dac_concurrent_enable ( void )

enable DAC concurrent mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 353 of file gd32f10x_dac.c.

354 {
355 uint32_t ctl = 0U;
356 ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
357 DAC_CTL |= (ctl);
358 }
DAC_CTL_DEN1
#define DAC_CTL_DEN1
Definition: gd32f10x_dac.h:47
DAC_CTL_DEN0
#define DAC_CTL_DEN0
Definition: gd32f10x_dac.h:40
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
void dac_concurrent_output_buffer_disable ( void )

disable DAC concurrent buffer function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 418 of file gd32f10x_dac.c.

419 {
420 uint32_t ctl = 0U;
421 ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
422 DAC_CTL |= (ctl);
423 }
DAC_CTL_DBOFF1
#define DAC_CTL_DBOFF1
Definition: gd32f10x_dac.h:48
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DBOFF0
#define DAC_CTL_DBOFF0
Definition: gd32f10x_dac.h:41
void dac_concurrent_output_buffer_enable ( void )

enable DAC concurrent buffer function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 405 of file gd32f10x_dac.c.

406 {
407 uint32_t ctl = 0U;
408 ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
409 DAC_CTL &= (~ctl);
410 }
DAC_CTL_DBOFF1
#define DAC_CTL_DBOFF1
Definition: gd32f10x_dac.h:48
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DBOFF0
#define DAC_CTL_DBOFF0
Definition: gd32f10x_dac.h:41
void dac_concurrent_software_trigger_disable ( void )

disable DAC concurrent software trigger function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 392 of file gd32f10x_dac.c.

393 {
394 uint32_t swt = 0U;
395 swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
396 DAC_SWT &= (~swt);
397 }
DAC_SWT
#define DAC_SWT
Definition: gd32f10x_dac.h:25
DAC_SWT_SWTR0
#define DAC_SWT_SWTR0
Definition: gd32f10x_dac.h:56
DAC_SWT_SWTR1
#define DAC_SWT_SWTR1
Definition: gd32f10x_dac.h:57
void dac_concurrent_software_trigger_enable ( void )

enable DAC concurrent software trigger function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 379 of file gd32f10x_dac.c.

380 {
381 uint32_t swt = 0U;
382 swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
383 DAC_SWT |= (swt);
384 }
DAC_SWT
#define DAC_SWT
Definition: gd32f10x_dac.h:25
DAC_SWT_SWTR0
#define DAC_SWT_SWTR0
Definition: gd32f10x_dac.h:56
DAC_SWT_SWTR1
#define DAC_SWT_SWTR1
Definition: gd32f10x_dac.h:57
void dac_data_set | ( | uint32_t | dac_periph,
 |  | uint32_t | dac_align,
 |  | uint16_t | data
 | ) |  |

set the DAC specified data holding register value

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] dac_align
  • DAC_ALIGN_8B_R: data right 8b alignment
  • DAC_ALIGN_12B_R: data right 12b alignment
  • DAC_ALIGN_12B_L: data left 12b alignment
[in] | data | data to be loaded
[out] | none
Return values
none

Definition at line 437 of file gd32f10x_dac.c.

438 {
439 if(DAC0 == dac_periph){
440 switch(dac_align){
441 /* data right 12b alignment */
442 case DAC_ALIGN_12B_R:
443 DAC0_R12DH = data;
444 break;
445 /* data left 12b alignment */
446 case DAC_ALIGN_12B_L:
447 DAC0_L12DH = data;
448 break;
449 /* data right 8b alignment */
450 case DAC_ALIGN_8B_R:
451 DAC0_R8DH = data;
452 break;
453 default:
454 break;
455 }
456 }else{
457 switch(dac_align){
458 /* data right 12b alignment */
459 case DAC_ALIGN_12B_R:
460 DAC1_R12DH = data;
461 break;
462 /* data left 12b alignment */
463 case DAC_ALIGN_12B_L:
464 DAC1_L12DH = data;
465 break;
466 /* data right 8b alignment */
467 case DAC_ALIGN_8B_R:
468 DAC1_R8DH = data;
469 break;
470 default:
471 break;
472 }
473 }
474 }
DAC_ALIGN_12B_R
#define DAC_ALIGN_12B_R
Definition: gd32f10x_dac.h:162
DAC1_R8DH
#define DAC1_R8DH
Definition: gd32f10x_dac.h:31
DAC_ALIGN_12B_L
#define DAC_ALIGN_12B_L
Definition: gd32f10x_dac.h:163
DAC_ALIGN_8B_R
#define DAC_ALIGN_8B_R
Definition: gd32f10x_dac.h:164
DAC0_R8DH
#define DAC0_R8DH
Definition: gd32f10x_dac.h:28
DAC0_L12DH
#define DAC0_L12DH
Definition: gd32f10x_dac.h:27
DAC1_R12DH
#define DAC1_R12DH
Definition: gd32f10x_dac.h:29
DAC0_R12DH
#define DAC0_R12DH
Definition: gd32f10x_dac.h:26
DAC1_L12DH
#define DAC1_L12DH
Definition: gd32f10x_dac.h:30
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_deinit ( void )

deinitialize DAC

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_dac.c.

22 {
23 rcu_periph_reset_enable(RCU_DACRST);
24 rcu_periph_reset_disable(RCU_DACRST);
25 }
RCU_DACRST
Definition: gd32f10x_rcu.h:474
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void dac_disable ( uint32_t dac_periph )

disable DAC

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 50 of file gd32f10x_dac.c.

51 {
52 if(DAC0 == dac_periph){
53 DAC_CTL &= ~DAC_CTL_DEN0;
54 }else{
55 DAC_CTL &= ~DAC_CTL_DEN1;
56 }
57 }
DAC_CTL_DEN1
#define DAC_CTL_DEN1
Definition: gd32f10x_dac.h:47
DAC_CTL_DEN0
#define DAC_CTL_DEN0
Definition: gd32f10x_dac.h:40
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_dma_disable ( uint32_t dac_periph )

disable DAC DMA function

Parameters
[in] dac_periph
  • DACx(x=0,1)
[out] none
Return values
none

Definition at line 82 of file gd32f10x_dac.c.

83 {
84 if(DAC0 == dac_periph){
85 DAC_CTL &= ~DAC_CTL_DDMAEN0;
86 }else{
87 DAC_CTL &= ~DAC_CTL_DDMAEN1;
88 }
89 }
DAC_CTL_DDMAEN0
#define DAC_CTL_DDMAEN0
Definition: gd32f10x_dac.h:46
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DDMAEN1
#define DAC_CTL_DDMAEN1
Definition: gd32f10x_dac.h:53
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_dma_enable ( uint32_t dac_periph )

enable DAC DMA function

Parameters
[in] dac_periph
  • DACx(x=0,1)
[out] none
Return values
none

Definition at line 66 of file gd32f10x_dac.c.

67 {
68 if(DAC0 == dac_periph){
69 DAC_CTL |= DAC_CTL_DDMAEN0;
70 }else{
71 DAC_CTL |= DAC_CTL_DDMAEN1;
72 }
73 }
DAC_CTL_DDMAEN0
#define DAC_CTL_DDMAEN0
Definition: gd32f10x_dac.h:46
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DDMAEN1
#define DAC_CTL_DDMAEN1
Definition: gd32f10x_dac.h:53
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_enable ( uint32_t dac_periph )

enable DAC

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 34 of file gd32f10x_dac.c.

35 {
36 if(DAC0 == dac_periph){
37 DAC_CTL |= DAC_CTL_DEN0;
38 }else{
39 DAC_CTL |= DAC_CTL_DEN1;
40 }
41 }
DAC_CTL_DEN1
#define DAC_CTL_DEN1
Definition: gd32f10x_dac.h:47
DAC_CTL_DEN0
#define DAC_CTL_DEN0
Definition: gd32f10x_dac.h:40
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_lfsr_noise_config | ( | uint32_t | dac_periph,
 |  | uint32_t | unmask_bits
 | ) |  |

configure DAC LFSR noise mode

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] unmask_bits
  • DAC_LFSR_BIT0: unmask the LFSR bit0
  • DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
  • DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
  • DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
  • DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
  • DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
  • DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
  • DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
  • DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
  • DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
  • DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
  • DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
[out] none
Return values
none

Definition at line 287 of file gd32f10x_dac.c.

288 {
289 if(DAC0 == dac_periph){
290 DAC_CTL &= ~DAC_CTL_DWBW0;
291 DAC_CTL |= unmask_bits;
292 }else{
293 DAC_CTL &= ~DAC_CTL_DWBW1;
294 DAC_CTL |= unmask_bits << 16;
295 }
296 }
DAC_CTL_DWBW1
#define DAC_CTL_DWBW1
Definition: gd32f10x_dac.h:52
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DWBW0
#define DAC_CTL_DWBW0
Definition: gd32f10x_dac.h:45
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_output_buffer_disable ( uint32_t dac_periph )

disable DAC output buffer

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 114 of file gd32f10x_dac.c.

115 {
116 if(DAC0 == dac_periph){
117 DAC_CTL |= DAC_CTL_DBOFF0;
118 }else{
119 DAC_CTL |= DAC_CTL_DBOFF1;
120 }
121 }
DAC_CTL_DBOFF1
#define DAC_CTL_DBOFF1
Definition: gd32f10x_dac.h:48
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DBOFF0
#define DAC_CTL_DBOFF0
Definition: gd32f10x_dac.h:41
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_output_buffer_enable ( uint32_t dac_periph )

enable DAC output buffer

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 98 of file gd32f10x_dac.c.

99 {
100 if(DAC0 == dac_periph){
101 DAC_CTL &= ~DAC_CTL_DBOFF0;
102 }else{
103 DAC_CTL &= ~DAC_CTL_DBOFF1;
104 }
105 }
DAC_CTL_DBOFF1
#define DAC_CTL_DBOFF1
Definition: gd32f10x_dac.h:48
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DBOFF0
#define DAC_CTL_DBOFF0
Definition: gd32f10x_dac.h:41
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
uint16_t dac_output_value_get ( uint32_t dac_periph )

get DAC output value

Parameters
[in] dac_periph
  • DACx(x=0,1)
[out] none
Return values
DAC output data

Definition at line 336 of file gd32f10x_dac.c.

337 {
338 uint16_t data = 0U;
339 if(DAC0 == dac_periph){
340 data = (uint16_t)DAC0_DO;
341 }else{
342 data = (uint16_t)DAC1_DO;
343 }
344 return data;
345 }
DAC0_DO
#define DAC0_DO
Definition: gd32f10x_dac.h:35
DAC1_DO
#define DAC1_DO
Definition: gd32f10x_dac.h:36
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_software_trigger_disable ( uint32_t dac_periph )

disable DAC software trigger

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 177 of file gd32f10x_dac.c.

178 {
179 if(DAC0 == dac_periph){
180 DAC_SWT &= ~DAC_SWT_SWTR0;
181 }else{
182 DAC_SWT &= ~DAC_SWT_SWTR1;
183 }
184 }
DAC_SWT
#define DAC_SWT
Definition: gd32f10x_dac.h:25
DAC_SWT_SWTR0
#define DAC_SWT_SWTR0
Definition: gd32f10x_dac.h:56
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
DAC_SWT_SWTR1
#define DAC_SWT_SWTR1
Definition: gd32f10x_dac.h:57
void dac_software_trigger_enable ( uint32_t dac_periph )

enable DAC software trigger

Parameters
[in] dac_periph
  • DACx(x =0,1)
Return values
none

Definition at line 161 of file gd32f10x_dac.c.

162 {
163 if(DAC0 == dac_periph){
164 DAC_SWT |= DAC_SWT_SWTR0;
165 }else{
166 DAC_SWT |= DAC_SWT_SWTR1;
167 }
168 }
DAC_SWT
#define DAC_SWT
Definition: gd32f10x_dac.h:25
DAC_SWT_SWTR0
#define DAC_SWT_SWTR0
Definition: gd32f10x_dac.h:56
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
DAC_SWT_SWTR1
#define DAC_SWT_SWTR1
Definition: gd32f10x_dac.h:57
void dac_triangle_noise_config | ( | uint32_t | dac_periph,
 |  | uint32_t | amplitude
 | ) |  |

configure DAC triangle noise mode

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] amplitude
  • DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
  • DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
  • DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
  • DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
  • DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
  • DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
  • DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
  • DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
  • DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
  • DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
  • DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
  • DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
[out] none
Return values
none

Definition at line 318 of file gd32f10x_dac.c.

319 {
320 if(DAC0 == dac_periph){
321 DAC_CTL &= ~DAC_CTL_DWBW0;
322 DAC_CTL |= amplitude;
323 }else{
324 DAC_CTL &= ~DAC_CTL_DWBW1;
325 DAC_CTL |= amplitude << 16;
326 }
327 }
DAC_CTL_DWBW1
#define DAC_CTL_DWBW1
Definition: gd32f10x_dac.h:52
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DWBW0
#define DAC_CTL_DWBW0
Definition: gd32f10x_dac.h:45
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_trigger_disable ( uint32_t dac_periph )

disable DAC trigger

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 146 of file gd32f10x_dac.c.

147 {
148 if(DAC0 == dac_periph){
149 DAC_CTL &= ~DAC_CTL_DTEN0;
150 }else{
151 DAC_CTL &= ~DAC_CTL_DTEN1;
152 }
153 }
DAC_CTL_DTEN0
#define DAC_CTL_DTEN0
Definition: gd32f10x_dac.h:42
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
DAC_CTL_DTEN1
#define DAC_CTL_DTEN1
Definition: gd32f10x_dac.h:49
void dac_trigger_enable ( uint32_t dac_periph )

enable DAC trigger

Parameters
[in] dac_periph
  • DACx(x =0,1)
[out] none
Return values
none

Definition at line 130 of file gd32f10x_dac.c.

131 {
132 if(DAC0 == dac_periph){
133 DAC_CTL |= DAC_CTL_DTEN0;
134 }else{
135 DAC_CTL |= DAC_CTL_DTEN1;
136 }
137 }
DAC_CTL_DTEN0
#define DAC_CTL_DTEN0
Definition: gd32f10x_dac.h:42
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
DAC_CTL_DTEN1
#define DAC_CTL_DTEN1
Definition: gd32f10x_dac.h:49
void dac_trigger_source_config | ( | uint32_t | dac_periph,
 |  | uint32_t | triggersource
 | ) |  |

set DAC trigger source

Parameters
[in] dac_periph
  • DACx(x =0,1)
[in] triggersource external triggers of DAC
  • DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
  • DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F10X_CL)
  • DAC_TRIGGER_T3_TRGO: TIMER3 TRGO
  • DAC_TRIGGER_T4_TRGO: TIMER4 TRGO
  • DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
  • DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
  • DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F10X_MD and GD32F10X_HD and GD32F10X_XD)
  • DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
  • DAC_TRIGGER_SOFTWARE: software trigger
[out] none
Return values
none

Definition at line 203 of file gd32f10x_dac.c.

204 {
205 if(DAC0 == dac_periph){
206 DAC_CTL &= ~DAC_CTL_DTSEL0;
207 DAC_CTL |= triggersource;
208 }else{
209 DAC_CTL &= ~DAC_CTL_DTSEL1;
210 DAC_CTL |= (triggersource << 16);
211 }
212 }
DAC_CTL_DTSEL1
#define DAC_CTL_DTSEL1
Definition: gd32f10x_dac.h:50
DAC_CTL_DTSEL0
#define DAC_CTL_DTSEL0
Definition: gd32f10x_dac.h:43
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_wave_bit_width_config | ( | uint32_t | dac_periph,
 |  | uint32_t | bit_width
 | ) |  |

configure DAC wave bit width

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] bit_width
  • DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
  • DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
  • DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
  • DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
  • DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
  • DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
  • DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
  • DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
  • DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
  • DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
  • DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
  • DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
[out] none
Return values
none

Definition at line 256 of file gd32f10x_dac.c.

257 {
258 if(DAC0 == dac_periph){
259 DAC_CTL &= ~DAC_CTL_DWBW0;
260 DAC_CTL |= bit_width;
261 }else{
262 DAC_CTL &= ~DAC_CTL_DWBW1;
263 DAC_CTL |= bit_width << 16;
264 }
265 }
DAC_CTL_DWBW1
#define DAC_CTL_DWBW1
Definition: gd32f10x_dac.h:52
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DWBW0
#define DAC_CTL_DWBW0
Definition: gd32f10x_dac.h:45
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
void dac_wave_mode_config | ( | uint32_t | dac_periph,
 |  | uint32_t | wave_mode
 | ) |  |

configure DAC wave mode

Parameters
[in] dac_periph
  • DACx(x=0,1)
[in] wave_mode
  • DAC_WAVE_DISABLE: wave disable
  • DAC_WAVE_MODE_LFSR: LFSR noise mode
  • DAC_WAVE_MODE_TRIANGLE: triangle noise mode
[out] none
Return values
none

Definition at line 225 of file gd32f10x_dac.c.

226 {
227 if(DAC0 == dac_periph){
228 DAC_CTL &= ~DAC_CTL_DWM0;
229 DAC_CTL |= wave_mode;
230 }else{
231 DAC_CTL &= ~DAC_CTL_DWM1;
232 DAC_CTL |= wave_mode << 16;
233 }
234 }
DAC_CTL_DWM1
#define DAC_CTL_DWM1
Definition: gd32f10x_dac.h:51
DAC_CTL_DWM0
#define DAC_CTL_DWM0
Definition: gd32f10x_dac.h:44
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_dbg.c File Reference

DBG driver. More...

#include "gd32f10x_dbg.h"

Go to the source code of this file.

Functions

uint32_t | dbg_id_get (void)
read DBG_ID code register More...
void | dbg_low_power_enable (uint32_t dbg_low_power)
enable low power behavior when the mcu is in debug mode More...
void | dbg_low_power_disable (uint32_t dbg_low_power)
disable low power behavior when the mcu is in debug mode More...
void | dbg_periph_enable (dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode More...
void | dbg_periph_disable (dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode More...
void | dbg_trace_pin_enable (void)
enable trace pin assignment More...
void | dbg_trace_pin_disable (void)
disable trace pin assignment More...
void | dbg_trace_pin_mode_set (uint32_t trace_mode)
trace pin mode selection More...

Detailed Description

DBG driver.

Definition in file gd32f10x_dbg.c.

Function Documentation

uint32_t dbg_id_get ( void )

read DBG_ID code register

Parameters
[in] | none
[out] | none
Return values
DBG_ID code

Definition at line 21 of file gd32f10x_dbg.c.

22 {
23 return DBG_ID;
24 }
DBG_ID
#define DBG_ID
Definition: gd32f10x_dbg.h:22
void dbg_low_power_disable ( uint32_t dbg_low_power )

disable low power behavior when the mcu is in debug mode

Parameters
[in] dbg_low_power this parameter can be any combination of the following values:
  • DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
  • DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
  • DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
[out] none
Return values
none

Definition at line 51 of file gd32f10x_dbg.c.

52 {
53 DBG_CTL0 &= ~dbg_low_power;
54 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
void dbg_low_power_enable ( uint32_t dbg_low_power )

enable low power behavior when the mcu is in debug mode

Parameters
[in] dbg_low_power this parameter can be any combination of the following values:
  • DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
  • DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
  • DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
[out] none
Return values
none

Definition at line 36 of file gd32f10x_dbg.c.

37 {
38 DBG_CTL0 |= dbg_low_power;
39 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
void dbg_periph_disable ( dbg_periph_enum dbg_periph )

disable peripheral behavior when the mcu is in debug mode

Parameters
[in] dbg_periph refer to dbg_periph_enum only one parameter can be selected which is shown as below:
  • DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
  • DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
  • DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted
  • DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
  • DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD and CL series): hold TIMERx counter when core is halted
[out] none
Return values
none

Definition at line 85 of file gd32f10x_dbg.c.

86 {
87 DBG_CTL0 &= ~(uint32_t)dbg_periph;
88 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
void dbg_periph_enable ( dbg_periph_enum dbg_periph )

enable peripheral behavior when the mcu is in debug mode

Parameters
[in] dbg_periph refer to dbg_periph_enum only one parameter can be selected which is shown as below:
  • DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
  • DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
  • DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted
  • DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
  • DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted
[out] none
Return values
none

Definition at line 68 of file gd32f10x_dbg.c.

69 {
70 DBG_CTL0 |= (uint32_t)dbg_periph;
71 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
void dbg_trace_pin_disable ( void )

disable trace pin assignment

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 107 of file gd32f10x_dbg.c.

108 {
109 DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
110 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
DBG_CTL0_TRACE_IOEN
#define DBG_CTL0_TRACE_IOEN
Definition: gd32f10x_dbg.h:33
void dbg_trace_pin_enable ( void )

enable trace pin assignment

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 96 of file gd32f10x_dbg.c.

97 {
98 DBG_CTL0 |= DBG_CTL0_TRACE_IOEN;
99 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
DBG_CTL0_TRACE_IOEN
#define DBG_CTL0_TRACE_IOEN
Definition: gd32f10x_dbg.h:33
void dbg_trace_pin_mode_set ( uint32_t trace_mode )

trace pin mode selection

Parameters
[in] trace_mode
  • TRACE_MODE_ASYNC: trace pin used for async mode
  • TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
  • TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
  • TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
[out] none
Return values
none

Definition at line 122 of file gd32f10x_dbg.c.

123 {
124 DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE;
125 DBG_CTL0 |= trace_mode;
126 }
DBG_CTL0_TRACE_MODE
#define DBG_CTL0_TRACE_MODE
Definition: gd32f10x_dbg.h:34
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_dma.c File Reference

DMA driver. More...

#include "gd32f10x_dma.h"

Go to the source code of this file.

Macros

#define DMA_WRONG_HANDLE while(1){}

Functions

void | dma_deinit (uint32_t dma_periph, dma_channel_enum channelx)
deinitialize DMA a channel registers More...
void | dma_init (uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct)
initialize DMA channel More...
void | dma_circulation_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable DMA circulation mode More...
void | dma_circulation_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable DMA circulation mode More...
void | dma_memory_to_memory_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable memory to memory mode More...
void | dma_memory_to_memory_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable memory to memory mode More...
void | dma_channel_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable DMA channel More...
void | dma_channel_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable DMA channel More...
void | dma_periph_address_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
set DMA peripheral base address More...
void | dma_memory_address_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
set DMA memory base address More...
void | dma_transfer_number_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
set the number of remaining data to be transferred by the DMA More...
uint32_t | dma_transfer_number_get (uint32_t dma_periph, dma_channel_enum channelx)
get the number of remaining data to be transferred by the DMA More...
void | dma_priority_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
configure priority level of DMA channel More...
void | dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
configure transfer data size of memory More...
void | dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
configure transfer data size of peripheral More...
void | dma_memory_increase_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable next address increasement algorithm of memory More...
void | dma_memory_increase_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable next address increasement algorithm of memory More...
void | dma_periph_increase_enable (uint32_t dma_periph, dma_channel_enum channelx)
enable next address increasement algorithm of peripheral More...
void | dma_periph_increase_disable (uint32_t dma_periph, dma_channel_enum channelx)
disable next address increasement algorithm of peripheral More...
void | dma_transfer_direction_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
configure the direction of data transfer on the channel More...
FlagStatus | dma_flag_get (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
check DMA flag is set or not More...
void | dma_flag_clear (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag More...
FlagStatus | dma_interrupt_flag_get (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
check DMA flag and interrupt enable bit is set or not More...
void | dma_interrupt_flag_clear (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag More...
void | dma_interrupt_enable (uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
enable DMA interrupt More...
void | dma_interrupt_disable (uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
disable DMA interrupt More...

Detailed Description

DMA driver.

Definition in file gd32f10x_dma.c.

Macro Definition Documentation

#define DMA_WRONG_HANDLE while(1){}

Definition at line 15 of file gd32f10x_dma.c.

Function Documentation

void dma_channel_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable DMA channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 207 of file gd32f10x_dma.c.

208 {
209 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
210 DMA_WRONG_HANDLE
211 }
212
213 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
214 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f10x_dma.h:75
void dma_channel_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable DMA channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 189 of file gd32f10x_dma.c.

190 {
191 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
192 DMA_WRONG_HANDLE
193 }
194
195 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
196 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f10x_dma.h:75
void dma_circulation_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable DMA circulation mode

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 135 of file gd32f10x_dma.c.

136 {
137 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
138 DMA_WRONG_HANDLE
139 }
140
141 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
142 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f10x_dma.h:80
void dma_circulation_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable DMA circulation mode

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 117 of file gd32f10x_dma.c.

118 {
119 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
120 DMA_WRONG_HANDLE
121 }
122
123 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
124 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f10x_dma.h:80
void dma_deinit | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

deinitialize DMA a channel registers

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel is deinitialized
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 28 of file gd32f10x_dma.c.

29 {
30 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
31 DMA_WRONG_HANDLE
32 }
33
34 /* disable DMA a channel */
35 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
36 /* reset DMA channel registers */
37 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
38 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
39 DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
40 DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
41 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
42 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHMADDR
#define DMA_CHMADDR(dma, channel)
Definition: gd32f10x_dma.h:131
DMA_CHCNT
#define DMA_CHCNT(dma, channel)
Definition: gd32f10x_dma.h:129
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_CHCTL_RESET_VALUE
#define DMA_CHCTL_RESET_VALUE
Definition: gd32f10x_dma.h:134
DMA_CHPADDR
#define DMA_CHPADDR(dma, channel)
Definition: gd32f10x_dma.h:130
DMA_CHMADDR_RESET_VALUE
#define DMA_CHMADDR_RESET_VALUE
Definition: gd32f10x_dma.h:137
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f10x_dma.h:75
DMA_INTC
#define DMA_INTC(dmax)
Definition: gd32f10x_dma.h:24
DMA_CHCNT_RESET_VALUE
#define DMA_CHCNT_RESET_VALUE
Definition: gd32f10x_dma.h:135
DMA_CHINTF_RESET_VALUE
#define DMA_CHINTF_RESET_VALUE
Definition: gd32f10x_dma.h:138
DMA_CHPADDR_RESET_VALUE
#define DMA_CHPADDR_RESET_VALUE
Definition: gd32f10x_dma.h:136
void dma_flag_clear | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

clear DMA a channel flag

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to clear flag
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_FLAG_G: global interrupt flag of channel
  • DMA_FLAG_FTF: full transfer finish flag of channel
  • DMA_FLAG_HTF: half transfer finish flag of channel
  • DMA_FLAG_ERR: error flag of channel
[out] none
Return values
none

Definition at line 519 of file gd32f10x_dma.c.

520 {
521 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
522 }
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_INTC
#define DMA_INTC(dmax)
Definition: gd32f10x_dma.h:24
FlagStatus dma_flag_get | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

check DMA flag is set or not

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to get flag
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_FLAG_G: global interrupt flag of channel
  • DMA_FLAG_FTF: full transfer finish flag of channel
  • DMA_FLAG_HTF: half transfer finish flag of channel
  • DMA_FLAG_ERR: error flag of channel
[out] none
Return values
FlagStatus SET or RESET

Definition at line 491 of file gd32f10x_dma.c.

492 {
493 FlagStatus reval;
494
495 if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
496 reval = SET;
497 }else{
498 reval = RESET;
499 }
500
501 return reval;
502 }
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_INTF
#define DMA_INTF(dmax)
Definition: gd32f10x_dma.h:23
void dma_init | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | dma_parameter_struct | init_struct
 | ) |  |

initialize DMA channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel is initialized
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] | init_struct | the data needed to initialize DMA channel periph_addr: peripheral base address periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE memory_addr: memory base address memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL number: the number of remaining data to be transferred by the DMA priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
[out] | none
Return values
none

Definition at line 63 of file gd32f10x_dma.c.

64 {
65 uint32_t ctl;
66
67 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
68 DMA_WRONG_HANDLE
69 }
70
71 /* configure peripheral base address */
72 DMA_CHPADDR(dma_periph, channelx) = init_struct.periph_addr;
73
74 /* configure memory base address */
75 DMA_CHMADDR(dma_periph, channelx) = init_struct.memory_addr;
76
77 /* configure the number of remaining data to be transferred */
78 DMA_CHCNT(dma_periph, channelx) = (init_struct.number & DMA_CHANNEL_CNT_MASK);
79
80 /* configure peripheral transfer width,memory transfer width, */
81 ctl = DMA_CHCTL(dma_periph, channelx);
82 ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
83 ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
84 DMA_CHCTL(dma_periph, channelx) = ctl;
85
86 /* configure peripheral increasing mode */
87 if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
88 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
89 }else{
90 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
91 }
92
93 /* configure memory increasing mode */
94 if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
95 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
96 }else{
97 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
98 }
99
100 /* configure the direction of data transfer */
101 if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
102 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
103 }else{
104 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
105 }
106 }
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f10x_dma.h:84
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHMADDR
#define DMA_CHMADDR(dma, channel)
Definition: gd32f10x_dma.h:131
dma_parameter_struct::priority
uint32_t priority
Definition: gd32f10x_dma.h:118
dma_parameter_struct::memory_width
uint32_t memory_width
Definition: gd32f10x_dma.h:116
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f10x_dma.h:79
dma_parameter_struct::periph_inc
uint8_t periph_inc
Definition: gd32f10x_dma.h:119
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f10x_dma.h:81
DMA_CHCNT
#define DMA_CHCNT(dma, channel)
Definition: gd32f10x_dma.h:129
DMA_PERIPH_INCREASE_ENABLE
#define DMA_PERIPH_INCREASE_ENABLE
Definition: gd32f10x_dma.h:169
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f10x_dma.h:83
DMA_CHANNEL_CNT_MASK
#define DMA_CHANNEL_CNT_MASK
Definition: gd32f10x_dma.h:200
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f10x_dma.h:82
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
dma_parameter_struct::number
uint32_t number
Definition: gd32f10x_dma.h:117
DMA_MEMORY_INCREASE_ENABLE
#define DMA_MEMORY_INCREASE_ENABLE
Definition: gd32f10x_dma.h:173
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f10x_dma.h:85
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f10x_dma.h:161
DMA_CHPADDR
#define DMA_CHPADDR(dma, channel)
Definition: gd32f10x_dma.h:130
dma_parameter_struct::periph_width
uint32_t periph_width
Definition: gd32f10x_dma.h:114
dma_parameter_struct::memory_inc
uint8_t memory_inc
Definition: gd32f10x_dma.h:120
dma_parameter_struct::direction
uint8_t direction
Definition: gd32f10x_dma.h:121
dma_parameter_struct::periph_addr
uint32_t periph_addr
Definition: gd32f10x_dma.h:113
dma_parameter_struct::memory_addr
uint32_t memory_addr
Definition: gd32f10x_dma.h:115
void dma_interrupt_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | source
 | ) |  |

disable DMA interrupt

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] source specify which interrupt to disbale one or more parameters can be selected which are shown as below
  • DMA_INT_FTF: channel full transfer finish interrupt
  • DMA_INT_HTF: channel half transfer finish interrupt
  • DMA_INT_ERR: channel error interrupt
[out] none
Return values
none

Definition at line 623 of file gd32f10x_dma.c.

624 {
625 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
626 DMA_WRONG_HANDLE
627 }
628
629 DMA_CHCTL(dma_periph, channelx) &= ~source;
630 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_interrupt_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | source
 | ) |  |

enable DMA interrupt

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] source specify which interrupt to enbale one or more parameters can be selected which are shown as below
  • DMA_INT_FTF: channel full transfer finish interrupt
  • DMA_INT_HTF: channel half transfer finish interrupt
  • DMA_INT_ERR: channel error interrupt
[out] none
Return values
none

Definition at line 600 of file gd32f10x_dma.c.

601 {
602 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
603 DMA_WRONG_HANDLE
604 }
605
606 DMA_CHCTL(dma_periph, channelx) |= source;
607 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_interrupt_flag_clear | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

clear DMA a channel flag

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to clear flag
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_INT_FLAG_G: global interrupt flag of channel
  • DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
  • DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
  • DMA_INT_FLAG_ERR: error interrupt flag of channel
[out] none
Return values
none

Definition at line 581 of file gd32f10x_dma.c.

582 {
583 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
584 }
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_INTC
#define DMA_INTC(dmax)
Definition: gd32f10x_dma.h:24
FlagStatus dma_interrupt_flag_get | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

check DMA flag and interrupt enable bit is set or not

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to get flag
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
  • DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
  • DMA_INT_FLAG_ERR: error interrupt flag of channel
[out] none
Return values
FlagStatus SET or RESET

Definition at line 538 of file gd32f10x_dma.c.

539 {
540 uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
541
542 switch(flag){
543 case DMA_INT_FLAG_FTF:
544 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
545 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
546 break;
547 case DMA_INT_FLAG_HTF:
548 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
549 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
550 break;
551 case DMA_INT_FLAG_ERR:
552 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
553 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
554 break;
555 default:
556 DMA_WRONG_HANDLE
557 }
558
559 if(interrupt_flag && interrupt_enable){
560 return SET;
561 }else{
562 return RESET;
563 }
564 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_HTFIE
#define DMA_CHXCTL_HTFIE
Definition: gd32f10x_dma.h:77
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
DMA_CHXCTL_FTFIE
#define DMA_CHXCTL_FTFIE
Definition: gd32f10x_dma.h:76
DMA_INTF
#define DMA_INTF(dmax)
Definition: gd32f10x_dma.h:23
DMA_INT_FLAG_ERR
#define DMA_INT_FLAG_ERR
Definition: gd32f10x_dma.h:146
DMA_INT_FLAG_FTF
#define DMA_INT_FLAG_FTF
Definition: gd32f10x_dma.h:144
DMA_CHXCTL_ERRIE
#define DMA_CHXCTL_ERRIE
Definition: gd32f10x_dma.h:78
DMA_INT_FLAG_HTF
#define DMA_INT_FLAG_HTF
Definition: gd32f10x_dma.h:145
void dma_memory_address_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | address
 | ) |  |

set DMA memory base address

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to set memory base address
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] | address | memory base address
[out] | none
Return values
none

Definition at line 245 of file gd32f10x_dma.c.

246 {
247 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
248 DMA_WRONG_HANDLE
249 }
250
251 DMA_CHMADDR(dma_periph, channelx) = address;
252 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHMADDR
#define DMA_CHMADDR(dma, channel)
Definition: gd32f10x_dma.h:131
void dma_memory_increase_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable next address increasement algorithm of memory

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 406 of file gd32f10x_dma.c.

407 {
408 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
409 DMA_WRONG_HANDLE
410 }
411
412 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
413 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f10x_dma.h:82
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_memory_increase_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable next address increasement algorithm of memory

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 388 of file gd32f10x_dma.c.

389 {
390 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
391 DMA_WRONG_HANDLE
392 }
393
394 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
395 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f10x_dma.h:82
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_memory_to_memory_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable memory to memory mode

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 171 of file gd32f10x_dma.c.

172 {
173 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
174 DMA_WRONG_HANDLE
175 }
176
177 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
178 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f10x_dma.h:86
void dma_memory_to_memory_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable memory to memory mode

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 153 of file gd32f10x_dma.c.

154 {
155 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
156 DMA_WRONG_HANDLE
157 }
158
159 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
160 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f10x_dma.h:86
void dma_memory_width_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | mwidth
 | ) |  |

configure transfer data size of memory

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] mwidth transfer data width of memory
  • DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
  • DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
  • DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
[out] none
Return values
none

Definition at line 334 of file gd32f10x_dma.c.

335 {
336 uint32_t ctl;
337
338 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
339 DMA_WRONG_HANDLE
340 }
341
342 /* acquire DMA_CHxCTL register */
343 ctl = DMA_CHCTL(dma_periph, channelx);
344 /* assign regiser */
345 ctl &= ~DMA_CHXCTL_MWIDTH;
346 ctl |= mwidth;
347 DMA_CHCTL(dma_periph, channelx) = ctl;
348 }
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f10x_dma.h:84
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_periph_address_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | address
 | ) |  |

set DMA peripheral base address

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to set peripheral base address
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] | address | peripheral base address
[out] | none
Return values
none

Definition at line 226 of file gd32f10x_dma.c.

227 {
228 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
229 DMA_WRONG_HANDLE
230 }
231
232 DMA_CHPADDR(dma_periph, channelx) = address;
233 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHPADDR
#define DMA_CHPADDR(dma, channel)
Definition: gd32f10x_dma.h:130
void dma_periph_increase_disable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

disable next address increasement algorithm of peripheral

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 442 of file gd32f10x_dma.c.

443 {
444 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
445 DMA_WRONG_HANDLE
446 }
447
448 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
449 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f10x_dma.h:81
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_periph_increase_enable | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

enable next address increasement algorithm of peripheral

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
none

Definition at line 424 of file gd32f10x_dma.c.

425 {
426 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
427 DMA_WRONG_HANDLE
428 }
429
430 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
431 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f10x_dma.h:81
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_periph_width_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | pwidth
 | ) |  |

configure transfer data size of peripheral

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] pwidth transfer data width of peripheral
  • DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
  • DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
  • DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
[out] none
Return values
none

Definition at line 363 of file gd32f10x_dma.c.

364 {
365 uint32_t ctl;
366
367 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
368 DMA_WRONG_HANDLE
369 }
370
371 /* acquire DMA_CHxCTL register */
372 ctl = DMA_CHCTL(dma_periph, channelx);
373 /* assign regiser */
374 ctl &= ~DMA_CHXCTL_PWIDTH;
375 ctl |= pwidth;
376 DMA_CHCTL(dma_periph, channelx) = ctl;
377 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f10x_dma.h:83
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
void dma_priority_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | priority
 | ) |  |

configure priority level of DMA channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] priority priority Level of this channel
  • DMA_PRIORITY_LOW: low priority
  • DMA_PRIORITY_MEDIUM: medium priority
  • DMA_PRIORITY_HIGH: high priority
  • DMA_PRIORITY_ULTRA_HIGH: ultra high priority
[out] none
Return values
none

Definition at line 305 of file gd32f10x_dma.c.

306 {
307 uint32_t ctl;
308
309 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
310 DMA_WRONG_HANDLE
311 }
312
313 /* acquire DMA_CHxCTL register */
314 ctl = DMA_CHCTL(dma_periph, channelx);
315 /* assign regiser */
316 ctl &= ~DMA_CHXCTL_PRIO;
317 ctl |= priority;
318 DMA_CHCTL(dma_periph, channelx) = ctl;
319 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f10x_dma.h:85
void dma_transfer_direction_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | direction
 | ) |  |

configure the direction of data transfer on the channel

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] direction specify the direction of data transfer
  • DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
  • DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
[out] none
Return values
none

Definition at line 463 of file gd32f10x_dma.c.

464 {
465 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
466 DMA_WRONG_HANDLE
467 }
468
469 if(DMA_PERIPHERAL_TO_MEMORY == direction){
470 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
471 } else {
472 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
473 }
474 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f10x_dma.h:79
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f10x_dma.h:161
void dma_transfer_number_config | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | number
 | ) |  |

set the number of remaining data to be transferred by the DMA

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to set number
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[in] | number | the number of remaining data to be transferred by the DMA
[out] | none
Return values
none

Definition at line 264 of file gd32f10x_dma.c.

265 {
266 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
267 DMA_WRONG_HANDLE
268 }
269
270 DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
271 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCNT
#define DMA_CHCNT(dma, channel)
Definition: gd32f10x_dma.h:129
DMA_CHANNEL_CNT_MASK
#define DMA_CHANNEL_CNT_MASK
Definition: gd32f10x_dma.h:200
uint32_t dma_transfer_number_get | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx
 | ) |  |

get the number of remaining data to be transferred by the DMA

Parameters
[in] dma_periph DMAx(x=0,1)
  • DMAx(x=0,1)
[in] channelx specify which DMA channel to set number
  • DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
[out] none
Return values
uint32_t the number of remaining data to be transferred by the DMA

Definition at line 282 of file gd32f10x_dma.c.

283 {
284 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
285 DMA_WRONG_HANDLE
286 }
287
288 return (uint32_t)DMA_CHCNT(dma_periph, channelx);
289 }
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHCNT
#define DMA_CHCNT(dma, channel)
Definition: gd32f10x_dma.h:129
Generated on Tue Jul 18 2017 09:24:16 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions | Variables
gd32f10x_enet.c File Reference

ENET driver. More...

#include "gd32f10x_enet.h"

Go to the source code of this file.

Functions

void | enet_deinit (void)
deinitialize the ENET, and reset structure parameters for ENET initialization More...
void | enet_initpara_config (enet_option_enum option, uint32_t para)
configure the parameters which are usually less cared for initialization note – this function must be called before enet_init(), otherwise configuration will be no effect More...
ErrStatus | enet_init (enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept)
initialize ENET peripheral with generally concerned parameters and the less cared parameters More...
ErrStatus | enet_software_reset (void)
reset all core internal registers located in CLK_TX and CLK_RX More...
uint32_t | enet_rxframe_size_get (void)
check receive frame valid and return frame size More...
void | enet_descriptors_chain_init (enet_dmadirection_enum direction)
initialize the DMA Tx/Rx descriptors's parameters in chain mode More...
void | enet_descriptors_ring_init (enet_dmadirection_enum direction)
initialize the DMA Tx/Rx descriptors's parameters in ring mode More...
ErrStatus | enet_frame_receive (uint8_t *buffer, uint32_t bufsize)
handle current received frame data to application buffer More...
ErrStatus | enet_frame_transmit (uint8_t *buffer, uint32_t length)
handle application buffer data to transmit it More...
void | enet_transmit_checksum_config (enet_descriptors_struct *desc, uint32_t checksum)
configure the transmit IP frame checksum offload calculation and insertion More...
void | enet_enable (void)
ENET Tx and Rx function enable (include MAC and DMA module) More...
void | enet_disable (void)
ENET Tx and Rx function disable (include MAC and DMA module) More...
void | enet_mac_address_set (enet_macaddress_enum mac_addr, uint8_t paddr[])
configure MAC address More...
void | enet_mac_address_get (enet_macaddress_enum mac_addr, uint8_t paddr[])
get MAC address More...
FlagStatus | enet_flag_get (enet_flag_enum enet_flag)
get the ENET MAC/MSC/PTP/DMA status flag More...
void | enet_flag_clear (enet_flag_clear_enum enet_flag)
clear the ENET DMA status flag More...
void | enet_interrupt_enable (enet_int_enum enet_int)
enable ENET MAC/MSC/DMA interrupt More...
void | enet_interrupt_disable (enet_int_enum enet_int)
disable ENET MAC/MSC/DMA interrupt More...
FlagStatus | enet_interrupt_flag_get (enet_int_flag_enum int_flag)
get ENET MAC/MSC/DMA interrupt flag More...
void | enet_interrupt_flag_clear (enet_int_flag_clear_enum int_flag_clear)
clear ENET DMA interrupt flag More...
void | enet_tx_enable (void)
ENET Tx function enable (include MAC and DMA module) More...
void | enet_tx_disable (void)
ENET Tx function disable (include MAC and DMA module) More...
void | enet_rx_enable (void)
ENET Rx function enable (include MAC and DMA module) More...
void | enet_rx_disable (void)
ENET Rx function disable (include MAC and DMA module) More...
void | enet_registers_get (enet_registers_type_enum type, uint32_t *preg, uint32_t num)
put registers value into the application buffer More...
void | enet_address_filter_enable (enet_macaddress_enum mac_addr)
enable the MAC address filter More...
void | enet_address_filter_disable (enet_macaddress_enum mac_addr)
disable the MAC address filter More...
void | enet_address_filter_config (enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type)
configure the MAC address filter More...
ErrStatus | enet_phy_config (void)
PHY interface configuration (configure SMI clock and reset PHY chip) More...
ErrStatus | enet_phy_write_read (enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register More...
ErrStatus | enet_phyloopback_enable (void)
enable the loopback function of PHY chip More...
ErrStatus | enet_phyloopback_disable (void)
disable the loopback function of PHY chip More...
void | enet_forward_feature_enable (uint32_t feature)
enable ENET forward feature More...
void | enet_forward_feature_disable (uint32_t feature)
disable ENET forward feature More...
void | enet_fliter_feature_enable (uint32_t feature)
enable ENET fliter feature More...
void | enet_fliter_feature_disable (uint32_t feature)
disable ENET fliter feature More...
ErrStatus | enet_pauseframe_generate (void)
generate the pause frame, ENET will send pause frame after enable transmit flow control this function only use in full-dulex mode More...
void | enet_pauseframe_detect_config (uint32_t detect)
configure the pause frame detect type More...
void | enet_pauseframe_config (uint32_t pausetime, uint32_t pause_threshold)
configure the pause frame parameters More...
void | enet_flowcontrol_threshold_config (uint32_t deactive, uint32_t active)
configure the threshold of the flow control(deactive and active threshold) More...
void | enet_flowcontrol_feature_enable (uint32_t feature)
enable ENET flow control feature More...
void | enet_flowcontrol_feature_disable (uint32_t feature)
disable ENET flow control feature More...
uint32_t | enet_dmaprocess_state_get (enet_dmadirection_enum direction)
get the dma transmit/receive process state More...
void | enet_dmaprocess_resume (enet_dmadirection_enum direction)
poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception More...
void | enet_rxprocess_check_recovery (void)
check and recover the Rx process More...
ErrStatus | enet_txfifo_flush (void)
flush the ENET transmit FIFO, and wait until the flush operation completes More...
uint32_t | enet_current_desc_address_get (enet_desc_reg_enum addr_get)
get the transmit/receive address of current descriptor, or current buffer, or descriptor table More...
uint32_t | enet_desc_information_get (enet_descriptors_struct *desc, enet_descstate_enum info_get)
get the Tx or Rx descriptor information More...
void | enet_missed_frame_counter_get (uint32_t *rxfifo_drop, uint32_t *rxdma_drop)
get the number of missed frames during receiving More...
FlagStatus | enet_desc_flag_get (enet_descriptors_struct *desc, uint32_t desc_flag)
get the bit flag of ENET DMA descriptor More...
void | enet_desc_flag_set (enet_descriptors_struct *desc, uint32_t desc_flag)
set the bit flag of ENET DMA descriptor More...
void | enet_desc_flag_clear (enet_descriptors_struct *desc, uint32_t desc_flag)
clear the bit flag of ENET DMA descriptor More...
void | enet_rx_desc_immediate_receive_complete_interrupt (enet_descriptors_struct *desc)
when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set More...
void | enet_rxframe_drop (void)
drop current receive frame More...
void | enet_dma_feature_enable (uint32_t feature)
enable DMA feature More...
void | enet_dma_feature_disable (uint32_t feature)
disable DMA feature More...
void | enet_ptp_normal_descriptors_chain_init (enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function More...
void | enet_ptp_normal_descriptors_ring_init (enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function More...
ErrStatus | enet_ptpframe_receive_normal_mode (uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[])
receive a packet data with timestamp values to application buffer, when the DMA is in normal mode More...
ErrStatus | enet_ptpframe_transmit_normal_mode (uint8_t *buffer, uint32_t length, uint32_t timestamp[])
send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode More...
void | enet_wum_filter_register_pointer_reset (void)
wakeup frame filter register pointer reset More...
void | enet_wum_filter_config (uint32_t pdata[])
set the remote wakeup frame registers More...
void | enet_wum_feature_enable (uint32_t feature)
enable wakeup management features More...
void | enet_wum_feature_disable (uint32_t feature)
disable wakeup management features More...
void | enet_msc_counters_reset (void)
reset the MAC statistics counters More...
void | enet_msc_feature_enable (uint32_t feature)
enable the MAC statistics counter features More...
void | enet_msc_feature_disable (uint32_t feature)
disable the MAC statistics counter features More...
uint32_t | enet_msc_counters_get (enet_msc_counter_enum counter)
get MAC statistics counter More...
uint32_t | enet_ptp_subsecond_2_nanosecond (uint32_t subsecond)
change subsecond to nanosecond More...
uint32_t | enet_ptp_nanosecond_2_subsecond (uint32_t nanosecond)
change nanosecond to subsecond More...
void | enet_ptp_feature_enable (uint32_t feature)
enable the PTP features More...
void | enet_ptp_feature_disable (uint32_t feature)
disable the PTP features More...
ErrStatus | enet_ptp_timestamp_function_config (enet_ptp_function_enum func)
configure the PTP timestamp function More...
void | enet_ptp_subsecond_increment_config (uint32_t subsecond)
configure system time subsecond increment value More...
void | enet_ptp_timestamp_addend_config (uint32_t add)
adjusting the clock frequency only in fine update mode More...
void | enet_ptp_timestamp_update_config (uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time More...
void | enet_ptp_expected_time_config (uint32_t second, uint32_t nanosecond)
configure the expected target time More...
void | enet_ptp_system_time_get (enet_ptp_systime_struct *systime_struct)
get the current system time More...
void | enet_ptp_start (int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg)
configure and start PTP timestamp counter More...
void | enet_ptp_finecorrection_adjfreq (int32_t carry_cfg)
adjust frequency in fine method by configure addend register More...
void | enet_ptp_coarsecorrection_systime_update (enet_ptp_systime_struct *systime_struct)
update system time in coarse method More...
void | enet_ptp_finecorrection_settime (enet_ptp_systime_struct *systime_struct)
set system time in fine method More...
FlagStatus | enet_ptp_flag_get (uint32_t flag)
get the ptp flag status More...
void | enet_initpara_reset (void)
reset the ENET initpara struct, call it before using enet_initpara_config() More...

Variables

enet_descriptors_struct * dma_current_txdesc
enet_descriptors_struct * dma_current_rxdesc
enet_descriptors_struct * dma_current_ptp_txdesc = NULL
enet_descriptors_struct * dma_current_ptp_rxdesc = NULL

Detailed Description

ENET driver.

Definition in file gd32f10x_enet.c.

Function Documentation

void enet_address_filter_config | ( | enet_macaddress_enum | mac_addr,
 |  | uint32_t | addr_mask,
 |  | uint32_t | filter_type
 | ) |  |

configure the MAC address filter

Parameters
[in] mac_addr select which MAC address will be configured, only one parameter can be selected which is shown as below
  • ENET_MAC_ADDRESS1: configure MAC address 1 filter
  • ENET_MAC_ADDRESS2: configure MAC address 2 filter
  • ENET_MAC_ADDRESS3: configure MAC address 3 filter
[in] addr_mask select which MAC address bytes will be mask, one or more parameters can be selected which are shown as below
  • ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits
  • ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits
  • ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits
  • ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits
  • ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits
  • ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits
[in] filter_type select which MAC address filter type will be selected, only one parameter can be selected which is shown as below
  • ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame
  • ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame
[out] none
Return values
none

Definition at line 1375 of file gd32f10x_enet.c.

1376 {
1377 uint32_t reg;
1378
1379 /* get the address filter register value which is to be configured */
1380 reg = REG32(ENET_ADDRH_BASE + mac_addr);
1381
1382 /* clear and configure the address filter register */
1383 reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF);
1384 reg |= (addr_mask | filter_type);
1385 REG32(ENET_ADDRH_BASE + mac_addr) = reg;
1386 }
ENET_MAC_ADDR1H_SAF
#define ENET_MAC_ADDR1H_SAF
Definition: gd32f10x_enet.h:250
ENET_ADDRH_BASE
#define ENET_ADDRH_BASE
Definition: gd32f10x_enet.h:531
ENET_MAC_ADDR1H_MB
#define ENET_MAC_ADDR1H_MB
Definition: gd32f10x_enet.h:249
void enet_address_filter_disable ( enet_macaddress_enum mac_addr )

disable the MAC address filter

Parameters
[in] mac_addr select which MAC address will be disable, only one parameter can be selected which is shown as below
  • ENET_MAC_ADDRESS1: disable MAC address 1 filter
  • ENET_MAC_ADDRESS2: disable MAC address 2 filter
  • ENET_MAC_ADDRESS3: disable MAC address 3 filter
[out] none
Return values
none

Definition at line 1348 of file gd32f10x_enet.c.

1349 {
1350 REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE;
1351 }
ENET_ADDRH_BASE
#define ENET_ADDRH_BASE
Definition: gd32f10x_enet.h:531
ENET_MAC_ADDR1H_AFE
#define ENET_MAC_ADDR1H_AFE
Definition: gd32f10x_enet.h:251
void enet_address_filter_enable ( enet_macaddress_enum mac_addr )

enable the MAC address filter

Parameters
[in] mac_addr select which MAC address will be enable
  • ENET_MAC_ADDRESS1: enable MAC address 1 filter
  • ENET_MAC_ADDRESS2: enable MAC address 2 filter
  • ENET_MAC_ADDRESS3: enable MAC address 3 filter
[out] none
Return values
none

Definition at line 1333 of file gd32f10x_enet.c.

1334 {
1335 REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE;
1336 }
ENET_ADDRH_BASE
#define ENET_ADDRH_BASE
Definition: gd32f10x_enet.h:531
ENET_MAC_ADDR1H_AFE
#define ENET_MAC_ADDR1H_AFE
Definition: gd32f10x_enet.h:251
uint32_t enet_current_desc_address_get ( enet_desc_reg_enum addr_get )

get the transmit/receive address of current descriptor, or current buffer, or descriptor table

Parameters
[in] addr_get choose the address which users want to get, refer to enet_desc_reg_enum, only one parameter can be selected which is shown as below
  • ENET_RX_DESC_TABLE: the start address of the receive descriptor table
  • ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by the RxDMA controller
  • ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller
  • ENET_TX_DESC_TABLE: the start address of the transmit descriptor table
  • ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by the TxDMA controller
  • ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller
[out] none
Return values
address value

Definition at line 1846 of file gd32f10x_enet.c.

1847 {
1848 uint32_t reval = 0U;
1849
1850 reval = REG32((ENET) +(uint32_t)addr_get);
1851 return reval;
1852 }
ENET
#define ENET
Definition: gd32f10x_enet.h:92
void enet_deinit ( void )

deinitialize the ENET, and reset structure parameters for ENET initialization

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 69 of file gd32f10x_enet.c.

70 {
71 rcu_periph_reset_enable(RCU_ENETRST);
72 rcu_periph_reset_disable(RCU_ENETRST);
73 enet_initpara_reset();
74 }
RCU_ENETRST
Definition: gd32f10x_rcu.h:441
enet_initpara_reset
void enet_initpara_reset(void)
reset the ENET initpara struct, call it before using enet_initpara_config()
Definition: gd32f10x_enet.c:2925
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void enet_desc_flag_clear | ( | enet_descriptors_struct * | desc,
 |  | uint32_t | desc_flag
 | ) |  |

clear the bit flag of ENET DMA descriptor

Parameters
[in] | desc | the descriptor pointer which users want to clear flag
[in] desc_flag the bit flag of ENET DMA descriptor, only one parameter can be selected which is shown as below
  • ENET_TDES0_VFRM: VLAN frame
  • ENET_TDES0_FRMF: frame flushed
  • ENET_TDES0_TCHM: the second address chained mode
  • ENET_TDES0_TERM: transmit end of ring mode
  • ENET_TDES0_TTSEN: transmit timestamp function enable
  • ENET_TDES0_DPAD: disable adding pad
  • ENET_TDES0_DCRC: disable CRC
  • ENET_TDES0_FSG: first segment
  • ENET_TDES0_LSG: last segment
  • ENET_TDES0_INTC: interrupt on completion
  • ENET_TDES0_DAV: DAV bit
  • ENET_RDES0_DAV: descriptor available
[out] | none
Return values
none

Definition at line 2021 of file gd32f10x_enet.c.

2022 {
2023 desc->status &= ~desc_flag;
2024 }
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
FlagStatus enet_desc_flag_get | ( | enet_descriptors_struct * | desc,
 |  | uint32_t | desc_flag
 | ) |  |

get the bit flag of ENET DMA descriptor

Parameters
[in] | desc | the descriptor pointer which users want to get flag
[in] desc_flag the bit flag of ENET DMA descriptor, only one parameter can be selected which is shown as below
  • ENET_TDES0_DB: deferred
  • ENET_TDES0_UFE: underflow error
  • ENET_TDES0_EXD: excessive deferral
  • ENET_TDES0_VFRM: VLAN frame
  • ENET_TDES0_ECO: excessive collision
  • ENET_TDES0_LCO: late collision
  • ENET_TDES0_NCA: no carrier
  • ENET_TDES0_LCA: loss of carrier
  • ENET_TDES0_IPPE: IP payload error
  • ENET_TDES0_FRMF: frame flushed
  • ENET_TDES0_JT: jabber timeout
  • ENET_TDES0_ES: error summary
  • ENET_TDES0_IPHE: IP header error
  • ENET_TDES0_TTMSS: transmit timestamp status
  • ENET_TDES0_TCHM: the second address chained mode
  • ENET_TDES0_TERM: transmit end of ring mode
  • ENET_TDES0_TTSEN: transmit timestamp function enable
  • ENET_TDES0_DPAD: disable adding pad
  • ENET_TDES0_DCRC: disable CRC
  • ENET_TDES0_FSG: first segment
  • ENET_TDES0_LSG: last segment
  • ENET_TDES0_INTC: interrupt on completion
  • ENET_TDES0_DAV: DAV bit
  • ENET_RDES0_PCERR: payload checksum error
  • ENET_RDES0_CERR: CRC error
  • ENET_RDES0_DBERR: dribble bit error
  • ENET_RDES0_RERR: receive error
  • ENET_RDES0_RWDT: receive watchdog timeout
  • ENET_RDES0_FRMT: frame type
  • ENET_RDES0_LCO: late collision
  • ENET_RDES0_IPHERR: IP frame header error
  • ENET_RDES0_LDES: last descriptor
  • ENET_RDES0_FDES: first descriptor
  • ENET_RDES0_VTAG: VLAN tag
  • ENET_RDES0_OERR: overflow error
  • ENET_RDES0_LERR: length error
  • ENET_RDES0_SAFF: SA filter fail
  • ENET_RDES0_DERR: descriptor error
  • ENET_RDES0_ERRS: error summary
  • ENET_RDES0_DAFF: destination address filter fail
  • ENET_RDES0_DAV: descriptor available
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 1965 of file gd32f10x_enet.c.

1966 {
1967 FlagStatus enet_flag = RESET;
1968
1969 if ((uint32_t)RESET != (desc->status & desc_flag)){
1970 enet_flag = SET;
1971 }
1972
1973 return enet_flag;
1974 }
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
void enet_desc_flag_set | ( | enet_descriptors_struct * | desc,
 |  | uint32_t | desc_flag
 | ) |  |

set the bit flag of ENET DMA descriptor

Parameters
[in] | desc | the descriptor pointer which users want to set flag
[in] desc_flag the bit flag of ENET DMA descriptor, only one parameter can be selected which is shown as below
  • ENET_TDES0_VFRM: VLAN frame
  • ENET_TDES0_FRMF: frame flushed
  • ENET_TDES0_TCHM: the second address chained mode
  • ENET_TDES0_TERM: transmit end of ring mode
  • ENET_TDES0_TTSEN: transmit timestamp function enable
  • ENET_TDES0_DPAD: disable adding pad
  • ENET_TDES0_DCRC: disable CRC
  • ENET_TDES0_FSG: first segment
  • ENET_TDES0_LSG: last segment
  • ENET_TDES0_INTC: interrupt on completion
  • ENET_TDES0_DAV: DAV bit
  • ENET_RDES0_DAV: descriptor available
[out] | none
Return values
none

Definition at line 1996 of file gd32f10x_enet.c.

1997 {
1998 desc->status |= desc_flag;
1999 }
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
uint32_t enet_desc_information_get | ( | enet_descriptors_struct * | desc,
 |  | enet_descstate_enum | info_get
 | ) |  |

get the Tx or Rx descriptor information

Parameters
[in] | desc | the descriptor pointer which users want to get information
[in] info_get the descriptor information type which is selected, only one parameter can be selected which is shown as below
  • RXDESC_BUFFER_1_SIZE: receive buffer 1 size
  • RXDESC_BUFFER_2_SIZE: receive buffer 2 size
  • RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer
  • TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted
  • RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame
  • TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame
[out] | none
Return values
descriptor information, if value is 0xFFFFFFFFU, means the false input parameter

Definition at line 1868 of file gd32f10x_enet.c.

1869 {
1870 uint32_t reval = 0xFFFFFFFFU;
1871
1872 switch(info_get){
1873 case RXDESC_BUFFER_1_SIZE:
1874 reval = GET_RDES1_RB1S(desc->control_buffer_size);
1875 break;
1876 case RXDESC_BUFFER_2_SIZE:
1877 reval = GET_RDES1_RB2S(desc->control_buffer_size);
1878 break;
1879 case RXDESC_FRAME_LENGTH:
1880 reval = GET_RDES0_FRML(desc->status);
1881 reval = reval - 4U;
1882
1883 break;
1884 case RXDESC_BUFFER_1_ADDR:
1885 reval = desc->buffer1_addr;
1886 break;
1887 case TXDESC_BUFFER_1_ADDR:
1888 reval = desc->buffer1_addr;
1889 break;
1890 case TXDESC_COLLISION_COUNT:
1891 reval = GET_TDES0_COCNT(desc->status);
1892 break;
1893 default:
1894 break;
1895 }
1896 return reval;
1897 }
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
GET_TDES0_COCNT
#define GET_TDES0_COCNT(regval)
Definition: gd32f10x_enet.h:1202
GET_RDES0_FRML
#define GET_RDES0_FRML(regval)
Definition: gd32f10x_enet.h:1217
RXDESC_FRAME_LENGTH
Definition: gd32f10x_enet.h:833
TXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:832
TXDESC_COLLISION_COUNT
Definition: gd32f10x_enet.h:831
GET_RDES1_RB1S
#define GET_RDES1_RB1S(regval)
Definition: gd32f10x_enet.h:1223
GET_RDES1_RB2S
#define GET_RDES1_RB2S(regval)
Definition: gd32f10x_enet.h:1225
RXDESC_BUFFER_1_SIZE
Definition: gd32f10x_enet.h:834
RXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:836
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
RXDESC_BUFFER_2_SIZE
Definition: gd32f10x_enet.h:835
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
void enet_descriptors_chain_init ( enet_dmadirection_enum direction )

initialize the DMA Tx/Rx descriptors's parameters in chain mode

Parameters
[in] direction the descriptors which users want to init, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA Tx descriptors
  • ENET_DMA_RX: DMA Rx descriptors
[out] none
Return values
none

Definition at line 647 of file gd32f10x_enet.c.

648 {
649 uint32_t num = 0U, count = 0U, maxsize = 0U;
650 uint32_t desc_status = 0U, desc_bufsize = 0U;
651 enet_descriptors_struct *desc, *desc_tab;
652 uint8_t *buf;
653
654 /* if want to initialize DMA Tx descriptors */
655 if (ENET_DMA_TX == direction){
656 /* save a copy of the DMA Tx descriptors */
657 desc_tab = txdesc_tab;
658 buf = &tx_buff[0][0];
659 count = ENET_TXBUF_NUM;
660 maxsize = ENET_TXBUF_SIZE;
661
662 /* select chain mode */
663 desc_status = ENET_TDES0_TCHM;
664
665 /* configure DMA Tx descriptor table address register */
666 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
667 dma_current_txdesc = desc_tab;
668 }else{
669 /* if want to initialize DMA Rx descriptors */
670 /* save a copy of the DMA Rx descriptors */
671 desc_tab = rxdesc_tab;
672 buf = &rx_buff[0][0];
673 count = ENET_RXBUF_NUM;
674 maxsize = ENET_RXBUF_SIZE;
675
676 /* enable receiving */
677 desc_status = ENET_RDES0_DAV;
678 /* select receive chained mode and set buffer1 size */
679 desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
680
681 /* configure DMA Rx descriptor table address register */
682 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
683 dma_current_rxdesc = desc_tab;
684 }
685 dma_current_ptp_rxdesc = NULL;
686 dma_current_ptp_txdesc = NULL;
687
688 /* configure each descriptor */
689 for(num=0U; num < count; num++){
690 /* get the pointer to the next descriptor of the descriptor table */
691 desc = desc_tab + num;
692
693 /* configure descriptors */
694 desc->status = desc_status;
695 desc->control_buffer_size = desc_bufsize;
696 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
697
698 /* if is not the last descriptor */
699 if(num < (count - 1U)){
700 /* configure the next descriptor address */
701 desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
702 }else{
703 /* when it is the last descriptor, the next descriptor address
704 equals to first descriptor address in descriptor table */
705 desc->buffer2_next_desc_addr = (uint32_t) desc_tab;
706 }
707 }
708 }
ENET_RXBUF_NUM
#define ENET_RXBUF_NUM
Definition: gd32f10x_enet.h:25
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_TXBUF_SIZE
#define ENET_TXBUF_SIZE
Definition: gd32f10x_enet.h:37
ENET_TXBUF_NUM
#define ENET_TXBUF_NUM
Definition: gd32f10x_enet.h:29
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_TCHM
#define ENET_TDES0_TCHM
Definition: gd32f10x_enet.h:464
NULL
#define NULL
Definition: usbd_std.h:20
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_RXBUF_SIZE
#define ENET_RXBUF_SIZE
Definition: gd32f10x_enet.h:33
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_descriptors_ring_init ( enet_dmadirection_enum direction )

initialize the DMA Tx/Rx descriptors's parameters in ring mode

Parameters
[in] direction the descriptors which users want to init, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA Tx descriptors
  • ENET_DMA_RX: DMA Rx descriptors
[out] none
Return values
none

Definition at line 719 of file gd32f10x_enet.c.

720 {
721 uint32_t num = 0U, count = 0U, maxsize = 0U;
722 uint32_t desc_status = 0U, desc_bufsize = 0U;
723 enet_descriptors_struct *desc;
724 enet_descriptors_struct *desc_tab;
725 uint8_t *buf;
726
727 /* configure descriptor skip length */
728 ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
729 ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
730
731 /* if want to initialize DMA Tx descriptors */
732 if (ENET_DMA_TX == direction){
733 /* save a copy of the DMA Tx descriptors */
734 desc_tab = txdesc_tab;
735 buf = &tx_buff[0][0];
736 count = ENET_TXBUF_NUM;
737 maxsize = ENET_TXBUF_SIZE;
738
739 /* configure DMA Tx descriptor table address register */
740 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
741 dma_current_txdesc = desc_tab;
742 }else{
743 /* if want to initialize DMA Rx descriptors */
744 /* save a copy of the DMA Rx descriptors */
745 desc_tab = rxdesc_tab;
746 buf = &rx_buff[0][0];
747 count = ENET_RXBUF_NUM;
748 maxsize = ENET_RXBUF_SIZE;
749
750 /* enable receiving */
751 desc_status = ENET_RDES0_DAV;
752 /* set buffer1 size */
753 desc_bufsize = ENET_RXBUF_SIZE;
754
755 /* configure DMA Rx descriptor table address register */
756 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
757 dma_current_rxdesc = desc_tab;
758 }
759 dma_current_ptp_rxdesc = NULL;
760 dma_current_ptp_txdesc = NULL;
761
762 /* configure each descriptor */
763 for(num=0U; num < count; num++){
764 /* get the pointer to the next descriptor of the descriptor table */
765 desc = desc_tab + num;
766
767 /* configure descriptors */
768 desc->status = desc_status;
769 desc->control_buffer_size = desc_bufsize;
770 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
771
772 /* when it is the last descriptor */
773 if(num == (count - 1U)){
774 if (ENET_DMA_TX == direction){
775 /* configure transmit end of ring mode */
776 desc->status |= ENET_TDES0_TERM;
777 }else{
778 /* configure receive end of ring mode */
779 desc->control_buffer_size |= ENET_RDES1_RERM;
780 }
781 }
782 }
783 }
ENET_RXBUF_NUM
#define ENET_RXBUF_NUM
Definition: gd32f10x_enet.h:25
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
ENET_DMA_BCTL_DPSL
#define ENET_DMA_BCTL_DPSL
Definition: gd32f10x_enet.h:355
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_TDES0_TERM
#define ENET_TDES0_TERM
Definition: gd32f10x_enet.h:465
ENET_TXBUF_SIZE
#define ENET_TXBUF_SIZE
Definition: gd32f10x_enet.h:37
ENET_TXBUF_NUM
#define ENET_TXBUF_NUM
Definition: gd32f10x_enet.h:29
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
DMA_BCTL_DPSL
#define DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1084
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
NULL
#define NULL
Definition: usbd_std.h:20
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_RXBUF_SIZE
#define ENET_RXBUF_SIZE
Definition: gd32f10x_enet.h:33
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_disable ( void )

ENET Tx and Rx function disable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 959 of file gd32f10x_enet.c.

960 {
961 enet_tx_disable();
962 enet_rx_disable();
963 }
enet_rx_disable
void enet_rx_disable(void)
ENET Rx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1286
enet_tx_disable
void enet_tx_disable(void)
ENET Tx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1261
void enet_dma_feature_disable ( uint32_t feature )

disable DMA feature

Parameters
[in] feature the feature of DMA mode, one or more parameters can be selected which are shown as below
  • ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function
  • ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function
[out] none
Return values
none

Definition at line 2105 of file gd32f10x_enet.c.

2106 {
2107 ENET_DMA_CTL &= ~feature;
2108 }
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
void enet_dma_feature_enable ( uint32_t feature )

enable DMA feature

Parameters
[in] feature the feature of DMA mode, one or more parameters can be selected which are shown as below
  • ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function
  • ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function
[out] none
Return values
none

Definition at line 2091 of file gd32f10x_enet.c.

2092 {
2093 ENET_DMA_CTL |= feature;
2094 }
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
void enet_dmaprocess_resume ( enet_dmadirection_enum direction )

poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception

Parameters
[in] direction choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA transmit process
  • ENET_DMA_RX: DMA receive process
[out] none
Return values
none

Definition at line 1773 of file gd32f10x_enet.c.

1774 {
1775 if(ENET_DMA_TX == direction){
1776 ENET_DMA_TPEN = 0U;
1777 }else{
1778 ENET_DMA_RPEN = 0U;
1779 }
1780 }
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
ENET_DMA_TPEN
#define ENET_DMA_TPEN
Definition: gd32f10x_enet.h:140
ENET_DMA_RPEN
#define ENET_DMA_RPEN
Definition: gd32f10x_enet.h:141
uint32_t enet_dmaprocess_state_get ( enet_dmadirection_enum direction )

get the dma transmit/receive process state

Parameters
[in] direction choose the direction of dma process which users want to check, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: dma transmit process
  • ENET_DMA_RX: dma receive process
[out] none
Return values
state of dma process, the value range shows below: ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING

Definition at line 1756 of file gd32f10x_enet.c.

1757 {
1758 uint32_t reval;
1759 reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction);
1760 return reval;
1761 }
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
void enet_enable ( void )

ENET Tx and Rx function enable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 947 of file gd32f10x_enet.c.

948 {
949 enet_tx_enable();
950 enet_rx_enable();
951 }
enet_rx_enable
void enet_rx_enable(void)
ENET Rx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1274
enet_tx_enable
void enet_tx_enable(void)
ENET Tx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1248
void enet_flag_clear ( enet_flag_clear_enum enet_flag )

clear the ENET DMA status flag

Parameters
[in] enet_flag ENET DMA flag clear, refer to enet_flag_clear_enum only one parameter can be selected which is shown as below
  • ENET_DMA_FLAG_TS_CLR: transmit status flag clear
  • ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear
  • ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear
  • ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear
  • ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear
  • ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear
  • ENET_DMA_FLAG_RS_CLR: receive status flag clear
  • ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear
  • ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear
  • ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear
  • ENET_DMA_FLAG_ET_CLR: early transmit status flag clear
  • ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear
  • ENET_DMA_FLAG_ER_CLR: early receive status flag clear
  • ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear
  • ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear
[out] none
Return values
none

Definition at line 1081 of file gd32f10x_enet.c.

1082 {
1083 /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */
1084 ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag));
1085 }
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
FlagStatus enet_flag_get ( enet_flag_enum enet_flag )

get the ENET MAC/MSC/PTP/DMA status flag

Parameters
[in] enet_flag ENET status flag, refer to enet_flag_enum, only one parameter can be selected which is shown as below
  • ENET_MAC_FLAG_MPKR: magic packet received flag
  • ENET_MAC_FLAG_WUFR: wakeup frame received flag
  • ENET_MAC_FLAG_FLOWCONTROL: flow control status flag
  • ENET_MAC_FLAG_WUM: WUM status flag
  • ENET_MAC_FLAG_MSC: MSC status flag
  • ENET_MAC_FLAG_MSCR: MSC receive status flag
  • ENET_MAC_FLAG_MSCT: MSC transmit status flag
  • ENET_MAC_FLAG_TMST: time stamp trigger status flag
  • ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag
  • ENET_PTP_FLAG_TTM: target time match flag
  • ENET_MSC_FLAG_RFCE: received frames CRC error flag
  • ENET_MSC_FLAG_RFAE: received frames alignment error flag
  • ENET_MSC_FLAG_RGUF: received good unicast frames flag
  • ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag
  • ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag
  • ENET_MSC_FLAG_TGF: transmitted good frames flag
  • ENET_DMA_FLAG_TS: transmit status flag
  • ENET_DMA_FLAG_TPS: transmit process stopped status flag
  • ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag
  • ENET_DMA_FLAG_TJT: transmit jabber timeout status flag
  • ENET_DMA_FLAG_RO: receive overflow status flag
  • ENET_DMA_FLAG_TU: transmit underflow status flag
  • ENET_DMA_FLAG_RS: receive status flag
  • ENET_DMA_FLAG_RBU: receive buffer unavailable status flag
  • ENET_DMA_FLAG_RPS: receive process stopped status flag
  • ENET_DMA_FLAG_RWT: receive watchdog timeout status flag
  • ENET_DMA_FLAG_ET: early transmit status flag
  • ENET_DMA_FLAG_FBE: fatal bus error status flag
  • ENET_DMA_FLAG_ER: early receive status flag
  • ENET_DMA_FLAG_AI: abnormal interrupt summary flag
  • ENET_DMA_FLAG_NI: normal interrupt summary flag
  • ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag
  • ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag
  • ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag
  • ENET_DMA_FLAG_MSC: MSC status flag
  • ENET_DMA_FLAG_WUM: WUM status flag
  • ENET_DMA_FLAG_TST: timestamp trigger status flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 1050 of file gd32f10x_enet.c.

1051 {
1052 if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){
1053 return SET;
1054 }else{
1055 return RESET;
1056 }
1057 }
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
void enet_fliter_feature_disable ( uint32_t feature )

disable ENET fliter feature

Parameters
[in] feature the feature of ENET fliter mode, one or more parameters can be selected which are shown as below
  • ENET_SRC_FILTER: filter source address function
  • ENET_SRC_FILTER_INVERSE: inverse source address filtering result function
  • ENET_DEST_FILTER_INVERSE: inverse DA filtering result function
  • ENET_MULTICAST_FILTER_PASS: pass all multicast frames function
  • ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function
  • ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function
  • ENET_FILTER_MODE_EITHER: HASH or perfect filter function
[out] none
Return values
none

Definition at line 1612 of file gd32f10x_enet.c.

1613 {
1614 ENET_MAC_FRMF &= ~feature;
1615 }
ENET_MAC_FRMF
#define ENET_MAC_FRMF
Definition: gd32f10x_enet.h:96
void enet_fliter_feature_enable ( uint32_t feature )

enable ENET fliter feature

Parameters
[in] feature the feature of ENET fliter mode, one or more parameters can be selected which are shown as below
  • ENET_SRC_FILTER: filter source address function
  • ENET_SRC_FILTER_INVERSE: inverse source address filtering result function
  • ENET_DEST_FILTER_INVERSE: inverse DA filtering result function
  • ENET_MULTICAST_FILTER_PASS: pass all multicast frames function
  • ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function
  • ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function
  • ENET_FILTER_MODE_EITHER: HASH or perfect filter function
[out] none
Return values
none

Definition at line 1593 of file gd32f10x_enet.c.

1594 {
1595 ENET_MAC_FRMF |= feature;
1596 }
ENET_MAC_FRMF
#define ENET_MAC_FRMF
Definition: gd32f10x_enet.h:96
void enet_flowcontrol_feature_disable ( uint32_t feature )

disable ENET flow control feature

Parameters
[in] feature the feature of ENET flow control mode one or more parameters can be selected which are shown as below
  • ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function
  • ENET_TX_FLOWCONTROL: the flow control operation in the MAC
  • ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it
  • ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode)
[out] none
Return values
none

Definition at line 1734 of file gd32f10x_enet.c.

1735 {
1736 if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
1737 ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE;
1738 }
1739 feature &= ~ENET_ZERO_QUANTA_PAUSE;
1740 ENET_MAC_FCTL &= ~feature;
1741 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_ZERO_QUANTA_PAUSE
#define ENET_ZERO_QUANTA_PAUSE
Definition: gd32f10x_enet.h:989
void enet_flowcontrol_feature_enable ( uint32_t feature )

enable ENET flow control feature

Parameters
[in] feature the feature of ENET flow control mode one or more parameters can be selected which are shown as below
  • ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function
  • ENET_TX_FLOWCONTROL: the flow control operation in the MAC
  • ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it
  • ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode)
[out] none
Return values
none

Definition at line 1714 of file gd32f10x_enet.c.

1715 {
1716 if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
1717 ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE;
1718 }
1719 feature &= ~ENET_ZERO_QUANTA_PAUSE;
1720 ENET_MAC_FCTL |= feature;
1721 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_ZERO_QUANTA_PAUSE
#define ENET_ZERO_QUANTA_PAUSE
Definition: gd32f10x_enet.h:989
void enet_flowcontrol_threshold_config | ( | uint32_t | deactive,
 |  | uint32_t | active
 | ) |  |

configure the threshold of the flow control(deactive and active threshold)

Parameters
[in] deactive the threshold of the deactive flow control, this value should always be less than active flow control value, only one parameter can be selected which is shown as below
  • ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes
  • ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes
  • ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes
  • ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes
  • ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes
  • ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes
  • ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes
[in] active the threshold of the active flow control, only one parameter can be selected which is shown as below
  • ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes
  • ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes
  • ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes
  • ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes
  • ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes
  • ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes
  • ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes
[out] none
Return values
none

Definition at line 1698 of file gd32f10x_enet.c.

1699 {
1700 ENET_MAC_FCTH = ((deactive | active) >> 8);
1701 }
ENET_MAC_FCTH
#define ENET_MAC_FCTH
Definition: gd32f10x_enet.h:102
void enet_forward_feature_disable ( uint32_t feature )

disable ENET forward feature

Parameters
[in] feature the feature of ENET forward mode, one or more parameters can be selected which are shown as below
  • ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function
  • ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it
  • ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode)
[out] none
Return values
none

Definition at line 1568 of file gd32f10x_enet.c.

1569 {
1570 uint32_t mask;
1571
1572 mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
1573 ENET_MAC_CFG &= ~mask;
1574
1575 mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
1576 ENET_DMA_CTL &= ~(mask >> 2);
1577 }
ENET_FORWARD_ERRFRAMES
#define ENET_FORWARD_ERRFRAMES
Definition: gd32f10x_enet.h:1185
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_AUTO_PADCRC_DROP
#define ENET_AUTO_PADCRC_DROP
Definition: gd32f10x_enet.h:922
ENET_FORWARD_UNDERSZ_GOODFRAMES
#define ENET_FORWARD_UNDERSZ_GOODFRAMES
Definition: gd32f10x_enet.h:1189
void enet_forward_feature_enable ( uint32_t feature )

enable ENET forward feature

Parameters
[in] feature the feature of ENET forward mode, one or more parameters can be selected which are shown as below
  • ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames
  • ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory
  • ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames
[out] none
Return values
none

Definition at line 1547 of file gd32f10x_enet.c.

1548 {
1549 uint32_t mask;
1550
1551 mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
1552 ENET_MAC_CFG |= mask;
1553
1554 mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
1555 ENET_DMA_CTL |= (mask >> 2);
1556 }
ENET_FORWARD_ERRFRAMES
#define ENET_FORWARD_ERRFRAMES
Definition: gd32f10x_enet.h:1185
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_AUTO_PADCRC_DROP
#define ENET_AUTO_PADCRC_DROP
Definition: gd32f10x_enet.h:922
ENET_FORWARD_UNDERSZ_GOODFRAMES
#define ENET_FORWARD_UNDERSZ_GOODFRAMES
Definition: gd32f10x_enet.h:1189
ErrStatus enet_frame_receive | ( | uint8_t * | buffer,
 |  | uint32_t | bufsize
 | ) |  |

handle current received frame data to application buffer

Parameters
[in] | bufsize | the size of buffer which is the parameter in function
[out] | buffer | pointer to the received frame data note – if the input is NULL, user should copy data in application by himself
Return values
ErrStatus SUCCESS or ERROR

Definition at line 792 of file gd32f10x_enet.c.

793 {
794 uint32_t offset = 0U, size = 0U;
795
796 /* the descriptor is busy due to own by the DMA */
797 if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
798 return ERROR;
799 }
800
801
802 /* if buffer pointer is null, indicates that users has copied data in application */
803 if(NULL != buffer){
804 /* if no error occurs, and the frame uses only one descriptor */
805 if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
806 (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
807 (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
808 /* get the frame length except CRC */
809 size = GET_RDES0_FRML(dma_current_rxdesc->status);
810 size = size - 4U;
811
812 /* to avoid situation that the frame size exceeds the buffer length */
813 if(size > bufsize){
814 return ERROR;
815 }
816
817 /* copy data from Rx buffer to application buffer */
818 for(offset = 0U; offset<size; offset++){
819 (*(buffer + offset)) = (*(__IO uint8_t *) (uint32_t)((dma_current_rxdesc->buffer1_addr) + offset));
820 }
821
822 }else{
823 /* return ERROR */
824 return ERROR;
825 }
826 }
827 /* enable reception, descriptor is owned by DMA */
828 dma_current_rxdesc->status = ENET_RDES0_DAV;
829
830 /* check Rx buffer unavailable flag status */
831 if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
832 /* clear RBU flag */
833 ENET_DMA_STAT = ENET_DMA_STAT_RBU;
834 /* resume DMA reception by writing to the RPEN register*/
835 ENET_DMA_RPEN = 0U;
836 }
837
838 /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */
839 /* chained mode */
840 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
841 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
842 }else{
843 /* ring mode */
844 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
845 /* if is the last descriptor in table, the next descriptor is the table header */
846 dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
847 }else{
848 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
849 dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
850 }
851 }
852
853 return SUCCESS;
854 }
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
GET_RDES0_FRML
#define GET_RDES0_FRML(regval)
Definition: gd32f10x_enet.h:1217
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ETH_DMARXDESC_SIZE
#define ETH_DMARXDESC_SIZE
Definition: gd32f10x_enet.h:1241
ENET_DMA_STAT_RBU
#define ENET_DMA_STAT_RBU
Definition: gd32f10x_enet.h:384
ENET_RDES0_FDES
#define ENET_RDES0_FDES
Definition: gd32f10x_enet.h:495
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
ENET_DMA_RPEN
#define ENET_DMA_RPEN
Definition: gd32f10x_enet.h:141
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_RDES0_ERRS
#define ENET_RDES0_ERRS
Definition: gd32f10x_enet.h:501
NULL
#define NULL
Definition: usbd_std.h:20
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
ENET_RDES0_LDES
#define ENET_RDES0_LDES
Definition: gd32f10x_enet.h:494
ErrStatus enet_frame_transmit | ( | uint8_t * | buffer,
 |  | uint32_t | length
 | ) |  |

handle application buffer data to transmit it

Parameters
[in] | buffer | pointer to the frame data to be transmitted, note – if the input is NULL, user should handle the data in application by himself
[in] | length | the length of frame data to be transmitted
[out] | none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 864 of file gd32f10x_enet.c.

865 {
866 uint32_t offset = 0U;
867 uint32_t dma_tbu_flag, dma_tu_flag;
868
869 /* the descriptor is busy due to own by the DMA */
870 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
871 return ERROR;
872 }
873
874 /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */
875 if(length > ENET_MAX_FRAME_SIZE){
876 return ERROR;
877 }
878
879 /* if buffer pointer is null, indicates that users has handled data in application */
880 if(NULL != buffer){
881 /* copy frame data from application buffer to Tx buffer */
882 for(offset = 0U; offset < length; offset++){
883 (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
884 }
885 }
886
887 /* set the frame length */
888 dma_current_txdesc->control_buffer_size = length;
889 /* set the segment of frame, frame is transmitted in one descriptor */
890 dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
891 /* enable the DMA transmission */
892 dma_current_txdesc->status |= ENET_TDES0_DAV;
893
894 /* check Tx buffer unavailable flag status */
895 dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
896 dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
897
898 if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
899 /* clear TBU and TU flag */
900 ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
901 /* resume DMA transmission by writing to the TPEN register*/
902 ENET_DMA_TPEN = 0U;
903 }
904
905 /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/
906 /* chained mode */
907 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
908 dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr);
909 }else{
910 /* ring mode */
911 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
912 /* if is the last descriptor in table, the next descriptor is the table header */
913 dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
914 }else{
915 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
916 dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
917 }
918 }
919
920 return SUCCESS;
921 }
ETH_DMATXDESC_SIZE
#define ETH_DMATXDESC_SIZE
Definition: gd32f10x_enet.h:1240
ENET_MAX_FRAME_SIZE
#define ENET_MAX_FRAME_SIZE
Definition: gd32f10x_enet.h:1256
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_DMA_STAT_TU
#define ENET_DMA_STAT_TU
Definition: gd32f10x_enet.h:382
ENET_TDES0_TERM
#define ENET_TDES0_TERM
Definition: gd32f10x_enet.h:465
ENET_DMA_STAT_TBU
#define ENET_DMA_STAT_TBU
Definition: gd32f10x_enet.h:379
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ENET_TDES0_FSG
#define ENET_TDES0_FSG
Definition: gd32f10x_enet.h:470
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
ENET_DMA_TPEN
#define ENET_DMA_TPEN
Definition: gd32f10x_enet.h:140
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_TCHM
#define ENET_TDES0_TCHM
Definition: gd32f10x_enet.h:464
NULL
#define NULL
Definition: usbd_std.h:20
ENET_TDES0_LSG
#define ENET_TDES0_LSG
Definition: gd32f10x_enet.h:471
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
ENET_TDES0_DAV
#define ENET_TDES0_DAV
Definition: gd32f10x_enet.h:473
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
ErrStatus enet_init | ( | enet_mediamode_enum | mediamode,
 |  | enet_chksumconf_enum | checksum,
 |  | enet_frmrecept_enum | recept
 | ) |  |

initialize ENET peripheral with generally concerned parameters and the less cared parameters

Parameters
[in] mediamode PHY mode and mac loopback configurations, only one parameter can be selected which is shown as below, refer to enet_mediamode_enum
  • ENET_AUTO_NEGOTIATION: PHY auto negotiation
  • ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex
  • ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex
  • ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex
  • ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex
  • ENET_LOOPBACKMODE: MAC in loopback mode at the MII
[in] checksum IP frame checksum offload function, only one parameter can be selected which is shown as below, refer to enet_mediamode_enum
  • ENET_NO_AUTOCHECKSUM: disable IP frame checksum function
  • ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function
  • ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame with only payload error but no other errors will not be dropped
[in] recept frame filter function, only one parameter can be selected which is shown as below, refer to enet_frmrecept_enum
  • ENET_PROMISCUOUS_MODE: promiscuous mode enabled
  • ENET_RECEIVEALL: all received frame are forwarded to application
  • ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames
  • ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames
[out] none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 280 of file gd32f10x_enet.c.

281 {
282 uint32_t reg_value=0U, reg_temp = 0U, temp = 0U;
283 uint32_t media_temp = 0U;
284 uint32_t timeout = 0U;
285 uint16_t phy_value = 0U;
286 ErrStatus phy_state= ERROR, enet_state = ERROR;
287
288 /* PHY interface configuration, configure SMI clock and reset PHY chip */
289 if(ERROR == enet_phy_config()){
290 _ENET_DELAY_(PHY_RESETDELAY);
291 if(ERROR == enet_phy_config()){
292 return enet_state;
293 }
294 }
295 /* initialize ENET peripheral with generally concerned parameters */
296 enet_default_init();
297
298 /* 1st, configure mediamode */
299 media_temp = (uint32_t)mediamode;
300 /* if is PHY auto negotiation */
301 if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){
302 /* wait for PHY_LINKED_STATUS bit be set */
303 do{
304 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
305 phy_value &= PHY_LINKED_STATUS;
306 timeout++;
307 }while((RESET == phy_value) && (timeout < PHY_READ_TO));
308 /* return ERROR due to timeout */
309 if(PHY_READ_TO == timeout){
310 return enet_state;
311 }
312 /* reset timeout counter */
313 timeout = 0U;
314
315 /* enable auto-negotiation */
316 phy_value = PHY_AUTONEGOTIATION;
317 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
318 if(!phy_state){
319 /* return ERROR due to write timeout */
320 return enet_state;
321 }
322
323 /* wait for the PHY_AUTONEGO_COMPLETE bit be set */
324 do{
325 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
326 phy_value &= PHY_AUTONEGO_COMPLETE;
327 timeout++;
328 }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO));
329 /* return ERROR due to timeout */
330 if(PHY_READ_TO == timeout){
331 return enet_state;
332 }
333 /* reset timeout counter */
334 timeout = 0U;
335
336 /* read the result of the auto-negotiation */
337 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value);
338 /* configure the duplex mode of MAC following the auto-negotiation result */
339 if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){
340 media_temp = ENET_MODE_FULLDUPLEX;
341 }else{
342 media_temp = ENET_MODE_HALFDUPLEX;
343 }
344 /* configure the communication speed of MAC following the auto-negotiation result */
345 if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){
346 media_temp |= ENET_SPEEDMODE_10M;
347 }else{
348 media_temp |= ENET_SPEEDMODE_100M;
349 }
350 }else{
351 phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3);
352 phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1);
353 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
354 if(!phy_state){
355 /* return ERROR due to write timeout */
356 return enet_state;
357 }
358 /* PHY configuration need some time */
359 _ENET_DELAY_(PHY_CONFIGDELAY);
360 }
361 /* after configuring the PHY, use mediamode to configure registers */
362 reg_value = ENET_MAC_CFG;
363 /* configure ENET_MAC_CFG register */
364 reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM));
365 reg_value |= media_temp;
366 ENET_MAC_CFG = reg_value;
367
368
369 /* 2st, configure checksum */
370 if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){
371 ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE;
372
373 reg_value = ENET_DMA_CTL;
374 /* configure ENET_DMA_CTL register */
375 reg_value &= ~ENET_DMA_CTL_DTCERFD;
376 reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD);
377 ENET_DMA_CTL = reg_value;
378 }
379
380 /* 3rd, configure recept */
381 ENET_MAC_FRMF |= (uint32_t)recept;
382
383 /* 4th, configure different function options */
384 /* configure forward_frame related registers */
385 if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){
386 reg_temp = enet_initpara.forward_frame;
387
388 reg_value = ENET_MAC_CFG;
389 temp = reg_temp;
390 /* configure ENET_MAC_CFG register */
391 reg_value &= (~ENET_MAC_CFG_APCD);
392 temp &= ENET_MAC_CFG_APCD;
393 reg_value |= temp;
394 ENET_MAC_CFG = reg_value;
395
396 reg_value = ENET_DMA_CTL;
397 temp = reg_temp;
398 /* configure ENET_DMA_CTL register */
399 reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF));
400 temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2);
401 reg_value |= (temp >> 2);
402 ENET_DMA_CTL = reg_value;
403 }
404
405 /* configure dmabus_mode related registers */
406 if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){
407 temp = enet_initpara.dmabus_mode;
408
409 reg_value = ENET_DMA_BCTL;
410 /* configure ENET_DMA_BCTL register */
411 reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \
412 |ENET_DMA_BCTL_FPBL);
413 reg_value |= temp;
414 ENET_DMA_BCTL = reg_value;
415 }
416
417 /* configure dma_maxburst related registers */
418 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){
419 temp = enet_initpara.dma_maxburst;
420
421 reg_value = ENET_DMA_BCTL;
422 /* configure ENET_DMA_BCTL register */
423 reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP);
424 reg_value |= temp;
425 ENET_DMA_BCTL = reg_value;
426 }
427
428 /* configure dma_arbitration related registers */
429 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){
430 temp = enet_initpara.dma_arbitration;
431
432 reg_value = ENET_DMA_BCTL;
433 /* configure ENET_DMA_BCTL register */
434 reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB);
435 reg_value |= temp;
436 ENET_DMA_BCTL = reg_value;
437 }
438
439 /* configure store_forward_mode related registers */
440 if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){
441 temp = enet_initpara.store_forward_mode;
442
443 reg_value = ENET_DMA_CTL;
444 /* configure ENET_DMA_CTL register */
445 reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC);
446 reg_value |= temp;
447 ENET_DMA_CTL = reg_value;
448 }
449
450 /* configure dma_function related registers */
451 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){
452 reg_temp = enet_initpara.dma_function;
453
454 reg_value = ENET_DMA_CTL;
455 /* configure ENET_DMA_CTL register */
456 reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF));
457 reg_value |= reg_temp;
458 ENET_DMA_CTL = reg_value;
459 }
460
461 /* configure vlan_config related registers */
462 if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){
463 reg_temp = enet_initpara.vlan_config;
464
465 reg_value = ENET_MAC_VLT;
466 /* configure ENET_MAC_VLT register */
467 reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC);
468 reg_value |= reg_temp;
469 ENET_MAC_VLT = reg_value;
470 }
471
472 /* configure flow_control related registers */
473 if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){
474 reg_temp = enet_initpara.flow_control;
475
476 reg_value = ENET_MAC_FCTL;
477 temp = reg_temp;
478 /* configure ENET_MAC_FCTL register */
479 reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
480 | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
481 temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
482 | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
483 reg_value |= temp;
484 ENET_MAC_FCTL = reg_value;
485
486 reg_value = ENET_MAC_FCTH;
487 temp = reg_temp;
488 /* configure ENET_MAC_FCTH register */
489 reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD);
490 temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8);
491 reg_value |= (temp >> 8);
492 ENET_MAC_FCTH = reg_value;
493 }
494
495 /* configure hashtable_high related registers */
496 if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){
497 ENET_MAC_HLH = enet_initpara.hashtable_high;
498 }
499
500 /* configure hashtable_low related registers */
501 if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){
502 ENET_MAC_HLL = enet_initpara.hashtable_low;
503 }
504
505 /* configure framesfilter_mode related registers */
506 if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){
507 reg_temp = enet_initpara.framesfilter_mode;
508
509 reg_value = ENET_MAC_FRMF;
510 /* configure ENET_MAC_FRMF register */
511 reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \
512 | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \
513 | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM);
514 reg_value |= reg_temp;
515 ENET_MAC_FRMF = reg_value;
516 }
517
518 /* configure halfduplex_param related registers */
519 if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){
520 reg_temp = enet_initpara.halfduplex_param;
521
522 reg_value = ENET_MAC_CFG;
523 /* configure ENET_MAC_CFG register */
524 reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \
525 | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC);
526 reg_value |= reg_temp;
527 ENET_MAC_CFG = reg_value;
528 }
529
530 /* configure timer_config related registers */
531 if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){
532 reg_temp = enet_initpara.timer_config;
533
534 reg_value = ENET_MAC_CFG;
535 /* configure ENET_MAC_CFG register */
536 reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD);
537 reg_value |= reg_temp;
538 ENET_MAC_CFG = reg_value;
539 }
540
541 /* configure interframegap related registers */
542 if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){
543 reg_temp = enet_initpara.interframegap;
544
545 reg_value = ENET_MAC_CFG;
546 /* configure ENET_MAC_CFG register */
547 reg_value &= ~ENET_MAC_CFG_IGBS;
548 reg_value |= reg_temp;
549 ENET_MAC_CFG = reg_value;
550 }
551
552 enet_state = SUCCESS;
553 return enet_state;
554 }
HALFDUPLEX_OPTION
Definition: gd32f10x_enet.h:755
ENET_MAC_CFG_DPM
#define ENET_MAC_CFG_DPM
Definition: gd32f10x_enet.h:162
ENET_DMA_CTL_DAFRF
#define ENET_DMA_CTL_DAFRF
Definition: gd32f10x_enet.h:409
ENET_DMA_BCTL_RTPR
#define ENET_DMA_BCTL_RTPR
Definition: gd32f10x_enet.h:357
ENET_MAC_FRMF_SAFLT
#define ENET_MAC_FRMF_SAFLT
Definition: gd32f10x_enet.h:180
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
PHY_AUTONEGOTIATION
#define PHY_AUTONEGOTIATION
Definition: gd32f10x_enet.h:68
DMABUS_OPTION
Definition: gd32f10x_enet.h:745
ENET_MAC_FRMF_SAIFLT
#define ENET_MAC_FRMF_SAIFLT
Definition: gd32f10x_enet.h:179
HASHL_OPTION
Definition: gd32f10x_enet.h:753
PHY_RESETDELAY
#define PHY_RESETDELAY
Definition: gd32f10x_enet.h:54
ENET_MAC_FCTH
#define ENET_MAC_FCTH
Definition: gd32f10x_enet.h:102
enet_initpara_struct::dmabus_mode
uint32_t dmabus_mode
Definition: gd32f10x_enet.h:844
PHY_DUPLEX_STATUS
#define PHY_DUPLEX_STATUS
Definition: gd32f10x_enet.h:85
ENET_MAC_FRMF_HMF
#define ENET_MAC_FRMF_HMF
Definition: gd32f10x_enet.h:174
ENET_MAC_FRMF_DAIFLT
#define ENET_MAC_FRMF_DAIFLT
Definition: gd32f10x_enet.h:175
ENET_DMA_CTL_FERF
#define ENET_DMA_CTL_FERF
Definition: gd32f10x_enet.h:404
FLOWCTL_OPTION
Definition: gd32f10x_enet.h:751
ENET_DMA_CTL_RTHC
#define ENET_DMA_CTL_RTHC
Definition: gd32f10x_enet.h:402
ENET_MAC_VLT_VLTC
#define ENET_MAC_VLT_VLTC
Definition: gd32f10x_enet.h:215
PHY_SR
#define PHY_SR
Definition: gd32f10x_enet.h:83
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
PHY_REG_BCR
#define PHY_REG_BCR
Definition: gd32f10x_enet.h:58
ENET_DMA_BCTL_DAB
#define ENET_DMA_BCTL_DAB
Definition: gd32f10x_enet.h:354
ENET_MAC_HLL
#define ENET_MAC_HLL
Definition: gd32f10x_enet.h:98
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
enet_initpara_struct::dma_arbitration
uint32_t dma_arbitration
Definition: gd32f10x_enet.h:846
enet_initpara_struct::interframegap
uint32_t interframegap
Definition: gd32f10x_enet.h:856
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_MODE_FULLDUPLEX
#define ENET_MODE_FULLDUPLEX
Definition: gd32f10x_enet.h:911
ENET_DMA_CTL_TTHC
#define ENET_DMA_CTL_TTHC
Definition: gd32f10x_enet.h:406
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
enet_phy_config
ErrStatus enet_phy_config(void)
PHY interface configuration (configure SMI clock and reset PHY chip)
Definition: gd32f10x_enet.c:1394
enet_initpara_struct::hashtable_high
uint32_t hashtable_high
Definition: gd32f10x_enet.h:851
enet_initpara_struct::halfduplex_param
uint32_t halfduplex_param
Definition: gd32f10x_enet.h:854
ENET_SPEEDMODE_10M
#define ENET_SPEEDMODE_10M
Definition: gd32f10x_enet.h:902
ENET_MAC_CFG_ROD
#define ENET_MAC_CFG_ROD
Definition: gd32f10x_enet.h:164
ENET_MAC_FCTL_DZQP
#define ENET_MAC_FCTL_DZQP
Definition: gd32f10x_enet.h:206
ENET_MAC_FRMF_PCFRM
#define ENET_MAC_FRMF_PCFRM
Definition: gd32f10x_enet.h:178
HASHH_OPTION
Definition: gd32f10x_enet.h:752
ENET_DMA_CTL_RSFD
#define ENET_DMA_CTL_RSFD
Definition: gd32f10x_enet.h:410
PHY_LINKED_STATUS
#define PHY_LINKED_STATUS
Definition: gd32f10x_enet.h:75
ENET_DMA_CTL_FUF
#define ENET_DMA_CTL_FUF
Definition: gd32f10x_enet.h:403
ENET_DMA_BCTL_FPBL
#define ENET_DMA_BCTL_FPBL
Definition: gd32f10x_enet.h:361
DMA_MAXBURST_OPTION
Definition: gd32f10x_enet.h:746
enet_initpara_struct::flow_control
uint32_t flow_control
Definition: gd32f10x_enet.h:850
ENET_DMA_CTL_TSFD
#define ENET_DMA_CTL_TSFD
Definition: gd32f10x_enet.h:408
enet_initpara_struct::store_forward_mode
uint32_t store_forward_mode
Definition: gd32f10x_enet.h:847
DMA_ARBITRATION_OPTION
Definition: gd32f10x_enet.h:747
enet_initpara_struct::dma_function
uint32_t dma_function
Definition: gd32f10x_enet.h:848
ENET_MAC_FCTL_PTM
#define ENET_MAC_FCTL_PTM
Definition: gd32f10x_enet.h:207
ENET_MAC_FRMF
#define ENET_MAC_FRMF
Definition: gd32f10x_enet.h:96
ENET_DMA_CTL_OSF
#define ENET_DMA_CTL_OSF
Definition: gd32f10x_enet.h:401
_ENET_DELAY_
#define _ENET_DELAY_
Definition: gd32f10x_enet.h:1473
ENET_MODE_HALFDUPLEX
#define ENET_MODE_HALFDUPLEX
Definition: gd32f10x_enet.h:912
PHY_READ_TO
#define PHY_READ_TO
Definition: gd32f10x_enet.h:50
ENET_MAC_HLH
#define ENET_MAC_HLH
Definition: gd32f10x_enet.h:97
ENET_MAC_FCTL_PLTS
#define ENET_MAC_FCTL_PLTS
Definition: gd32f10x_enet.h:205
ENET_MAC_FCTL_TFCEN
#define ENET_MAC_FCTL_TFCEN
Definition: gd32f10x_enet.h:202
enet_initpara_struct::hashtable_low
uint32_t hashtable_low
Definition: gd32f10x_enet.h:852
PHY_CONFIGDELAY
#define PHY_CONFIGDELAY
Definition: gd32f10x_enet.h:55
STORE_OPTION
Definition: gd32f10x_enet.h:748
TIMER_OPTION
Definition: gd32f10x_enet.h:756
INTERFRAMEGAP_OPTION
Definition: gd32f10x_enet.h:757
PHY_SPEED_STATUS
#define PHY_SPEED_STATUS
Definition: gd32f10x_enet.h:84
ENET_AUTO_NEGOTIATION
Definition: gd32f10x_enet.h:763
ENET_DMA_BCTL_FB
#define ENET_DMA_BCTL_FB
Definition: gd32f10x_enet.h:358
ENET_MAC_FRMF_HPFLT
#define ENET_MAC_FRMF_HPFLT
Definition: gd32f10x_enet.h:181
ENET_DMA_BCTL_PGBL
#define ENET_DMA_BCTL_PGBL
Definition: gd32f10x_enet.h:356
VLAN_OPTION
Definition: gd32f10x_enet.h:750
enet_initpara_struct::forward_frame
uint32_t forward_frame
Definition: gd32f10x_enet.h:843
ENET_MAC_CFG_BOL
#define ENET_MAC_CFG_BOL
Definition: gd32f10x_enet.h:158
ENET_MAC_CFG_APCD
#define ENET_MAC_CFG_APCD
Definition: gd32f10x_enet.h:159
ENET_DMA_BCTL_RXDP
#define ENET_DMA_BCTL_RXDP
Definition: gd32f10x_enet.h:359
enet_initpara_struct::timer_config
uint32_t timer_config
Definition: gd32f10x_enet.h:855
ENET_MAC_FCTL_RFCEN
#define ENET_MAC_FCTL_RFCEN
Definition: gd32f10x_enet.h:203
ENET_MAC_CFG_SPD
#define ENET_MAC_CFG_SPD
Definition: gd32f10x_enet.h:165
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
DMA_OPTION
Definition: gd32f10x_enet.h:749
enet_initpara_struct::option_enable
uint32_t option_enable
Definition: gd32f10x_enet.h:842
ENET_CHECKSUMOFFLOAD_ENABLE
#define ENET_CHECKSUMOFFLOAD_ENABLE
Definition: gd32f10x_enet.h:914
ENET_MAC_CFG_WDD
#define ENET_MAC_CFG_WDD
Definition: gd32f10x_enet.h:169
ENET_DMA_BCTL_UIP
#define ENET_DMA_BCTL_UIP
Definition: gd32f10x_enet.h:360
ENET_MAC_FCTL_UPFDT
#define ENET_MAC_FCTL_UPFDT
Definition: gd32f10x_enet.h:204
PHY_REG_BSR
#define PHY_REG_BSR
Definition: gd32f10x_enet.h:59
ENET_MAC_FCTH_RFD
#define ENET_MAC_FCTH_RFD
Definition: gd32f10x_enet.h:211
ENET_DMA_CTL_DTCERFD
#define ENET_DMA_CTL_DTCERFD
Definition: gd32f10x_enet.h:411
ENET_DMA_BCTL_AA
#define ENET_DMA_BCTL_AA
Definition: gd32f10x_enet.h:362
PHY_AUTONEGO_COMPLETE
#define PHY_AUTONEGO_COMPLETE
Definition: gd32f10x_enet.h:74
enet_initpara_struct::vlan_config
uint32_t vlan_config
Definition: gd32f10x_enet.h:849
PHY_ADDRESS
#define PHY_ADDRESS
Definition: gd32f10x_enet.h:47
ENET_MAC_CFG_IGBS
#define ENET_MAC_CFG_IGBS
Definition: gd32f10x_enet.h:167
ENET_MAC_CFG_RTD
#define ENET_MAC_CFG_RTD
Definition: gd32f10x_enet.h:160
enet_initpara_struct::dma_maxburst
uint32_t dma_maxburst
Definition: gd32f10x_enet.h:845
ENET_MAC_CFG_CSD
#define ENET_MAC_CFG_CSD
Definition: gd32f10x_enet.h:166
FORWARD_OPTION
Definition: gd32f10x_enet.h:744
ENET_MAC_FRMF_MFD
#define ENET_MAC_FRMF_MFD
Definition: gd32f10x_enet.h:176
ENET_SPEEDMODE_100M
#define ENET_SPEEDMODE_100M
Definition: gd32f10x_enet.h:903
ENET_MAC_VLT
#define ENET_MAC_VLT
Definition: gd32f10x_enet.h:103
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
ENET_MAC_FCTH_RFA
#define ENET_MAC_FCTH_RFA
Definition: gd32f10x_enet.h:210
ENET_MAC_CFG_DFC
#define ENET_MAC_CFG_DFC
Definition: gd32f10x_enet.h:157
enet_initpara_struct::framesfilter_mode
uint32_t framesfilter_mode
Definition: gd32f10x_enet.h:853
FILTER_OPTION
Definition: gd32f10x_enet.h:754
ENET_MAC_CFG_JBD
#define ENET_MAC_CFG_JBD
Definition: gd32f10x_enet.h:168
ENET_MAC_VLT_VLTI
#define ENET_MAC_VLT_VLTI
Definition: gd32f10x_enet.h:214
ENET_MAC_CFG_LBM
#define ENET_MAC_CFG_LBM
Definition: gd32f10x_enet.h:163
ENET_MAC_FRMF_HUF
#define ENET_MAC_FRMF_HUF
Definition: gd32f10x_enet.h:173
void enet_initpara_config | ( | enet_option_enum | option,
 |  | uint32_t | para
 | ) |  |

configure the parameters which are usually less cared for initialization note – this function must be called before enet_init(), otherwise configuration will be no effect

Parameters
[in] option different function option, which is related to several parameters, only one parameter can be selected which is shown as below, refer to enet_option_enum
  • FORWARD_OPTION: choose to configure the frame forward related parameters
  • DMABUS_OPTION: choose to configure the DMA bus mode related parameters
  • DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters
  • DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters
  • STORE_OPTION: choose to configure the store forward mode related parameters
  • DMA_OPTION: choose to configure the DMA descriptor related parameters
  • VLAN_OPTION: choose to configure vlan related parameters
  • FLOWCTL_OPTION: choose to configure flow control related parameters
  • HASHH_OPTION: choose to configure hash high
  • HASHL_OPTION: choose to configure hash low
  • FILTER_OPTION: choose to configure frame filter related parameters
  • HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters
  • TIMER_OPTION: choose to configure time counter related parameters
  • INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters
[in] para the related parameters according to the option all the related parameters should be configured which are shown as below FORWARD_OPTION related parameters:
  • ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ;
  • ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ;
  • ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . DMABUS_OPTION related parameters:
  • ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ;
  • ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; DMA_MAXBURST_OPTION related parameters:
  • ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ;
  • ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ;
  • ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; DMA_ARBITRATION_OPTION related parameters:
  • ENET_ARBITRATION_RXPRIORTX
  • ENET_ARBITRATION_RXTX_1_1/ ENET_ARBITRATION_RXTX_2_1/ ENET_ARBITRATION_RXTX_3_1/ ENET_ARBITRATION_RXTX_4_1/. STORE_OPTION related parameters:
  • ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ;
  • ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ;
  • ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ;
  • ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . DMA_OPTION related parameters:
  • ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ;
  • ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE . VLAN_OPTION related parameters:
  • ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ;
  • MAC_VLT_VLTI(regval) . FLOWCTL_OPTION related parameters:
  • MAC_FCTL_PTM(regval) ;
  • ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ;
  • ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ;
  • ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ;
  • ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ;
  • ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . HASHH_OPTION related parameters:
  • 0x0~0xFFFF FFFFU HASHL_OPTION related parameters:
  • 0x0~0xFFFF FFFFU FILTER_OPTION related parameters:
  • ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ ENET_SRC_FILTER_DISABLE ;
  • ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ;
  • ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ;
  • ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ ENET_UNICAST_FILTER_PERFECT ;
  • ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . HALFDUPLEX_OPTION related parameters:
  • ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ;
  • ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ;
  • ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ;
  • ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ;
  • ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . TIMER_OPTION related parameters:
  • ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ;
  • ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; INTERFRAMEGAP_OPTION related parameters:
  • ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT .
[out] none
Return values
none

Definition at line 176 of file gd32f10x_enet.c.

177 {
178 switch(option){
179 case FORWARD_OPTION:
180 /* choose to configure forward_frame, and save the configuration parameters */
181 enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION;
182 enet_initpara.forward_frame = para;
183 break;
184 case DMABUS_OPTION:
185 /* choose to configure dmabus_mode, and save the configuration parameters */
186 enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION;
187 enet_initpara.dmabus_mode = para;
188 break;
189 case DMA_MAXBURST_OPTION:
190 /* choose to configure dma_maxburst, and save the configuration parameters */
191 enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION;
192 enet_initpara.dma_maxburst = para;
193 break;
194 case DMA_ARBITRATION_OPTION:
195 /* choose to configure dma_arbitration, and save the configuration parameters */
196 enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION;
197 enet_initpara.dma_arbitration = para;
198 break;
199 case STORE_OPTION:
200 /* choose to configure store_forward_mode, and save the configuration parameters */
201 enet_initpara.option_enable |= (uint32_t)STORE_OPTION;
202 enet_initpara.store_forward_mode = para;
203 break;
204 case DMA_OPTION:
205 /* choose to configure dma_function, and save the configuration parameters */
206 enet_initpara.option_enable |= (uint32_t)DMA_OPTION;
207 enet_initpara.dma_function = para;
208 break;
209 case VLAN_OPTION:
210 /* choose to configure vlan_config, and save the configuration parameters */
211 enet_initpara.option_enable |= (uint32_t)VLAN_OPTION;
212 enet_initpara.vlan_config = para;
213 break;
214 case FLOWCTL_OPTION:
215 /* choose to configure flow_control, and save the configuration parameters */
216 enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION;
217 enet_initpara.flow_control = para;
218 break;
219 case HASHH_OPTION:
220 /* choose to configure hashtable_high, and save the configuration parameters */
221 enet_initpara.option_enable |= (uint32_t)HASHH_OPTION;
222 enet_initpara.hashtable_high = para;
223 break;
224 case HASHL_OPTION:
225 /* choose to configure hashtable_low, and save the configuration parameters */
226 enet_initpara.option_enable |= (uint32_t)HASHL_OPTION;
227 enet_initpara.hashtable_low = para;
228 break;
229 case FILTER_OPTION:
230 /* choose to configure framesfilter_mode, and save the configuration parameters */
231 enet_initpara.option_enable |= (uint32_t)FILTER_OPTION;
232 enet_initpara.framesfilter_mode = para;
233 break;
234 case HALFDUPLEX_OPTION:
235 /* choose to configure halfduplex_param, and save the configuration parameters */
236 enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION;
237 enet_initpara.halfduplex_param = para;
238 break;
239 case TIMER_OPTION:
240 /* choose to configure timer_config, and save the configuration parameters */
241 enet_initpara.option_enable |= (uint32_t)TIMER_OPTION;
242 enet_initpara.timer_config = para;
243 break;
244 case INTERFRAMEGAP_OPTION:
245 /* choose to configure interframegap, and save the configuration parameters */
246 enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION;
247 enet_initpara.interframegap = para;
248 break;
249 default:
250 break;
251 }
252 }
HALFDUPLEX_OPTION
Definition: gd32f10x_enet.h:755
DMABUS_OPTION
Definition: gd32f10x_enet.h:745
HASHL_OPTION
Definition: gd32f10x_enet.h:753
enet_initpara_struct::dmabus_mode
uint32_t dmabus_mode
Definition: gd32f10x_enet.h:844
FLOWCTL_OPTION
Definition: gd32f10x_enet.h:751
enet_initpara_struct::dma_arbitration
uint32_t dma_arbitration
Definition: gd32f10x_enet.h:846
enet_initpara_struct::interframegap
uint32_t interframegap
Definition: gd32f10x_enet.h:856
enet_initpara_struct::hashtable_high
uint32_t hashtable_high
Definition: gd32f10x_enet.h:851
enet_initpara_struct::halfduplex_param
uint32_t halfduplex_param
Definition: gd32f10x_enet.h:854
HASHH_OPTION
Definition: gd32f10x_enet.h:752
DMA_MAXBURST_OPTION
Definition: gd32f10x_enet.h:746
enet_initpara_struct::flow_control
uint32_t flow_control
Definition: gd32f10x_enet.h:850
enet_initpara_struct::store_forward_mode
uint32_t store_forward_mode
Definition: gd32f10x_enet.h:847
DMA_ARBITRATION_OPTION
Definition: gd32f10x_enet.h:747
enet_initpara_struct::dma_function
uint32_t dma_function
Definition: gd32f10x_enet.h:848
enet_initpara_struct::hashtable_low
uint32_t hashtable_low
Definition: gd32f10x_enet.h:852
STORE_OPTION
Definition: gd32f10x_enet.h:748
TIMER_OPTION
Definition: gd32f10x_enet.h:756
INTERFRAMEGAP_OPTION
Definition: gd32f10x_enet.h:757
VLAN_OPTION
Definition: gd32f10x_enet.h:750
enet_initpara_struct::forward_frame
uint32_t forward_frame
Definition: gd32f10x_enet.h:843
enet_initpara_struct::timer_config
uint32_t timer_config
Definition: gd32f10x_enet.h:855
DMA_OPTION
Definition: gd32f10x_enet.h:749
enet_initpara_struct::option_enable
uint32_t option_enable
Definition: gd32f10x_enet.h:842
enet_initpara_struct::vlan_config
uint32_t vlan_config
Definition: gd32f10x_enet.h:849
enet_initpara_struct::dma_maxburst
uint32_t dma_maxburst
Definition: gd32f10x_enet.h:845
FORWARD_OPTION
Definition: gd32f10x_enet.h:744
enet_initpara_struct::framesfilter_mode
uint32_t framesfilter_mode
Definition: gd32f10x_enet.h:853
FILTER_OPTION
Definition: gd32f10x_enet.h:754
void enet_initpara_reset ( void )

reset the ENET initpara struct, call it before using enet_initpara_config()

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 2925 of file gd32f10x_enet.c.

2926 {
2927 enet_initpara.option_enable = 0U;
2928 enet_initpara.forward_frame = 0U;
2929 enet_initpara.dmabus_mode = 0U;
2930 enet_initpara.dma_maxburst = 0U;
2931 enet_initpara.dma_arbitration = 0U;
2932 enet_initpara.store_forward_mode = 0U;
2933 enet_initpara.dma_function = 0U;
2934 enet_initpara.vlan_config = 0U;
2935 enet_initpara.flow_control = 0U;
2936 enet_initpara.hashtable_high = 0U;
2937 enet_initpara.hashtable_low = 0U;
2938 enet_initpara.framesfilter_mode = 0U;
2939 enet_initpara.halfduplex_param = 0U;
2940 enet_initpara.timer_config = 0U;
2941 enet_initpara.interframegap = 0U;
2942 }
enet_initpara_struct::dmabus_mode
uint32_t dmabus_mode
Definition: gd32f10x_enet.h:844
enet_initpara_struct::dma_arbitration
uint32_t dma_arbitration
Definition: gd32f10x_enet.h:846
enet_initpara_struct::interframegap
uint32_t interframegap
Definition: gd32f10x_enet.h:856
enet_initpara_struct::hashtable_high
uint32_t hashtable_high
Definition: gd32f10x_enet.h:851
enet_initpara_struct::halfduplex_param
uint32_t halfduplex_param
Definition: gd32f10x_enet.h:854
enet_initpara_struct::flow_control
uint32_t flow_control
Definition: gd32f10x_enet.h:850
enet_initpara_struct::store_forward_mode
uint32_t store_forward_mode
Definition: gd32f10x_enet.h:847
enet_initpara_struct::dma_function
uint32_t dma_function
Definition: gd32f10x_enet.h:848
enet_initpara_struct::hashtable_low
uint32_t hashtable_low
Definition: gd32f10x_enet.h:852
enet_initpara_struct::forward_frame
uint32_t forward_frame
Definition: gd32f10x_enet.h:843
enet_initpara_struct::timer_config
uint32_t timer_config
Definition: gd32f10x_enet.h:855
enet_initpara_struct::option_enable
uint32_t option_enable
Definition: gd32f10x_enet.h:842
enet_initpara_struct::vlan_config
uint32_t vlan_config
Definition: gd32f10x_enet.h:849
enet_initpara_struct::dma_maxburst
uint32_t dma_maxburst
Definition: gd32f10x_enet.h:845
enet_initpara_struct::framesfilter_mode
uint32_t framesfilter_mode
Definition: gd32f10x_enet.h:853
void enet_interrupt_disable ( enet_int_enum enet_int )

disable ENET MAC/MSC/DMA interrupt

Parameters
[in] enet_int ENET interrupt, only one parameter can be selected which is shown as below
  • ENET_MAC_INT_WUMIM: WUM interrupt mask
  • ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask
  • ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask
  • ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask
  • ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask
  • ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask
  • ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask
  • ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask
  • ENET_DMA_INT_TIE: transmit interrupt enable
  • ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable
  • ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable
  • ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable
  • ENET_DMA_INT_ROIE: receive overflow interrupt enable
  • ENET_DMA_INT_TUIE: transmit underflow interrupt enable
  • ENET_DMA_INT_RIE: receive interrupt enable
  • ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable
  • ENET_DMA_INT_RPSIE: receive process stopped interrupt enable
  • ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable
  • ENET_DMA_INT_ETIE: early transmit interrupt enable
  • ENET_DMA_INT_FBEIE: fatal bus error interrupt enable
  • ENET_DMA_INT_ERIE: early receive interrupt enable
  • ENET_DMA_INT_AIE: abnormal interrupt summary enable
  • ENET_DMA_INT_NIE: normal interrupt summary enable
[out] none
Return values
none

Definition at line 1158 of file gd32f10x_enet.c.

1159 {
1160 if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
1161 /* ENET_DMA_INTEN register interrupt */
1162 ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
1163 }else{
1164 /* other INTMSK register interrupt */
1165 ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
1166 }
1167 }
DMA_INTEN_REG_OFFSET
#define DMA_INTEN_REG_OFFSET
Definition: gd32f10x_enet.h:553
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
void enet_interrupt_enable ( enet_int_enum enet_int )

enable ENET MAC/MSC/DMA interrupt

Parameters
[in] enet_int ENET interrupt, only one parameter can be selected which is shown as below
  • ENET_MAC_INT_WUMIM: WUM interrupt mask
  • ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask
  • ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask
  • ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask
  • ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask
  • ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask
  • ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask
  • ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask
  • ENET_DMA_INT_TIE: transmit interrupt enable
  • ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable
  • ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable
  • ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable
  • ENET_DMA_INT_ROIE: receive overflow interrupt enable
  • ENET_DMA_INT_TUIE: transmit underflow interrupt enable
  • ENET_DMA_INT_RIE: receive interrupt enable
  • ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable
  • ENET_DMA_INT_RPSIE: receive process stopped interrupt enable
  • ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable
  • ENET_DMA_INT_ETIE: early transmit interrupt enable
  • ENET_DMA_INT_FBEIE: fatal bus error interrupt enable
  • ENET_DMA_INT_ERIE: early receive interrupt enable
  • ENET_DMA_INT_AIE: abnormal interrupt summary enable
  • ENET_DMA_INT_NIE: normal interrupt summary enable
[out] none
Return values
none

Definition at line 1117 of file gd32f10x_enet.c.

1118 {
1119 if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
1120 /* ENET_DMA_INTEN register interrupt */
1121 ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
1122 }else{
1123 /* other INTMSK register interrupt */
1124 ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
1125 }
1126 }
DMA_INTEN_REG_OFFSET
#define DMA_INTEN_REG_OFFSET
Definition: gd32f10x_enet.h:553
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
void enet_interrupt_flag_clear ( enet_int_flag_clear_enum int_flag_clear )

clear ENET DMA interrupt flag

Parameters
[in] int_flag_clear clear ENET interrupt flag, only one parameter can be selected which is shown as below
  • ENET_DMA_INT_FLAG_TS_CLR: transmit status flag
  • ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag
  • ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag
  • ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag
  • ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag
  • ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag
  • ENET_DMA_INT_FLAG_RS_CLR: receive status flag
  • ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag
  • ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag
  • ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag
  • ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag
  • ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag
  • ENET_DMA_INT_FLAG_ER_CLR: early receive status flag
  • ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag
  • ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag
[out] none
Return values
none

Definition at line 1236 of file gd32f10x_enet.c.

1237 {
1238 /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */
1239 ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear));
1240 }
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
FlagStatus enet_interrupt_flag_get ( enet_int_flag_enum int_flag )

get ENET MAC/MSC/DMA interrupt flag

Parameters
[in] int_flag ENET interrupt flag, only one parameter can be selected which is shown as below
  • ENET_MAC_INT_FLAG_WUM: WUM status flag
  • ENET_MAC_INT_FLAG_MSC: MSC status flag
  • ENET_MAC_INT_FLAG_MSCR: MSC receive status flag
  • ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag
  • ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag
  • ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag
  • ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag
  • ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag
  • ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag
  • ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag
  • ENET_MSC_INT_FLAG_TGF: transmitted good frames flag
  • ENET_DMA_INT_FLAG_TS: transmit status flag
  • ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag
  • ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag
  • ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag
  • ENET_DMA_INT_FLAG_RO: receive overflow status flag
  • ENET_DMA_INT_FLAG_TU: transmit underflow status flag
  • ENET_DMA_INT_FLAG_RS: receive status flag
  • ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag
  • ENET_DMA_INT_FLAG_RPS: receive process stopped status flag
  • ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag
  • ENET_DMA_INT_FLAG_ET: early transmit status flag
  • ENET_DMA_INT_FLAG_FBE: fatal bus error status flag
  • ENET_DMA_INT_FLAG_ER: early receive status flag
  • ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag
  • ENET_DMA_INT_FLAG_NI: normal interrupt summary flag
  • ENET_DMA_INT_FLAG_MSC: MSC status flag
  • ENET_DMA_INT_FLAG_WUM: WUM status flag
  • ENET_DMA_INT_FLAG_TST: timestamp trigger status flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 1205 of file gd32f10x_enet.c.

1206 {
1207 if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){
1208 return SET;
1209 }else{
1210 return RESET;
1211 }
1212 }
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
void enet_mac_address_get | ( | enet_macaddress_enum | mac_addr,
 |  | uint8_t | paddr[]
 | ) |  |

get MAC address

Parameters
[in] mac_addr select which MAC address will be get, only one parameter can be selected which is shown as below
  • ENET_MAC_ADDRESS0: get MAC address 0 filter
  • ENET_MAC_ADDRESS1: get MAC address 1 filter
  • ENET_MAC_ADDRESS2: get MAC address 2 filter
  • ENET_MAC_ADDRESS3: get MAC address 3 filter
[out] paddr the buffer pointer which is stored the MAC address (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa})
Return values
none

Definition at line 996 of file gd32f10x_enet.c.

997 {
998 paddr[0] = ENET_GET_MACADDR(mac_addr, 0U);
999 paddr[1] = ENET_GET_MACADDR(mac_addr, 1U);
1000 paddr[2] = ENET_GET_MACADDR(mac_addr, 2U);
1001 paddr[3] = ENET_GET_MACADDR(mac_addr, 3U);
1002 paddr[4] = ENET_GET_MACADDR(mac_addr, 4U);
1003 paddr[5] = ENET_GET_MACADDR(mac_addr, 5U);
1004 }
ENET_GET_MACADDR
#define ENET_GET_MACADDR(offset, n)
Definition: gd32f10x_enet.h:533
void enet_mac_address_set | ( | enet_macaddress_enum | mac_addr,
 |  | uint8_t | paddr[]
 | ) |  |

configure MAC address

Parameters
[in] mac_addr select which MAC address will be set, only one parameter can be selected which is shown as below
  • ENET_MAC_ADDRESS0: set MAC address 0 filter
  • ENET_MAC_ADDRESS1: set MAC address 1 filter
  • ENET_MAC_ADDRESS2: set MAC address 2 filter
  • ENET_MAC_ADDRESS3: set MAC address 3 filter
[in] | paddr | the buffer pointer which stores the MAC address (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa})
[out] | none
Return values
none

Definition at line 978 of file gd32f10x_enet.c.

979 {
980 REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr);
981 REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr);
982 }
ENET_ADDRH_BASE
#define ENET_ADDRH_BASE
Definition: gd32f10x_enet.h:531
ENET_SET_MACADDRL
#define ENET_SET_MACADDRL(p)
Definition: gd32f10x_enet.h:530
ENET_SET_MACADDRH
#define ENET_SET_MACADDRH(p)
Definition: gd32f10x_enet.h:529
ENET_ADDRL_BASE
#define ENET_ADDRL_BASE
Definition: gd32f10x_enet.h:532
void enet_missed_frame_counter_get | ( | uint32_t * | rxfifo_drop,
 |  | uint32_t * | rxdma_drop
 | ) |  |

get the number of missed frames during receiving

Parameters
[in] | none
[out] | rxfifo_drop | pointer to the number of frames dropped by RxFIFO
[out] | rxdma_drop | pointer to the number of frames missed by the RxDMA controller
Return values
none

Definition at line 1906 of file gd32f10x_enet.c.

1907 {
1908 uint32_t temp_counter = 0U;
1909
1910 temp_counter = ENET_DMA_MFBOCNT;
1911 *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter);
1912 *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter);
1913 }
ENET_DMA_MFBOCNT
#define ENET_DMA_MFBOCNT
Definition: gd32f10x_enet.h:147
GET_DMA_MFBOCNT_MSFC
#define GET_DMA_MFBOCNT_MSFC(regval)
Definition: gd32f10x_enet.h:1196
GET_DMA_MFBOCNT_MSFA
#define GET_DMA_MFBOCNT_MSFA(regval)
Definition: gd32f10x_enet.h:1198
uint32_t enet_msc_counters_get ( enet_msc_counter_enum counter )

get MAC statistics counter

Parameters
[in] counter MSC counters which is selected, refer to enet_msc_counter_enum, only one parameter can be selected which is shown as below
  • ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter
  • ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter
  • ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter
  • ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter
  • ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter
  • ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter
[out] none
Return values
the MSC counter value

Definition at line 2572 of file gd32f10x_enet.c.

2573 {
2574 uint32_t reval;
2575
2576 reval = REG32((ENET + (uint32_t)counter));
2577
2578 return reval;
2579 }
ENET
#define ENET
Definition: gd32f10x_enet.h:92
void enet_msc_counters_reset ( void )

reset the MAC statistics counters

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 2525 of file gd32f10x_enet.c.

2526 {
2527 /* reset all counters */
2528 ENET_MSC_CTL |= ENET_MSC_CTL_CTR;
2529 }
ENET_MSC_CTL
#define ENET_MSC_CTL
Definition: gd32f10x_enet.h:117
ENET_MSC_CTL_CTR
#define ENET_MSC_CTL_CTR
Definition: gd32f10x_enet.h:275
void enet_msc_feature_disable ( uint32_t feature )

disable the MAC statistics counter features

Parameters
[in] feature one or more parameters can be selected which are shown as below
  • ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover
  • ENET_MSC_RESET_ON_READ: reset on read
  • ENET_MSC_COUNTERS_FREEZE: MSC counter freeze
[out] none
Return values
none

Definition at line 2554 of file gd32f10x_enet.c.

2555 {
2556 ENET_MSC_CTL &= (~feature);
2557 }
ENET_MSC_CTL
#define ENET_MSC_CTL
Definition: gd32f10x_enet.h:117
void enet_msc_feature_enable ( uint32_t feature )

enable the MAC statistics counter features

Parameters
[in] feature one or more parameters can be selected which are shown as below
  • ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover
  • ENET_MSC_RESET_ON_READ: reset on read
  • ENET_MSC_COUNTERS_FREEZE: MSC counter freeze
[out] none
Return values
none

Definition at line 2540 of file gd32f10x_enet.c.

2541 {
2542 ENET_MSC_CTL |= feature;
2543 }
ENET_MSC_CTL
#define ENET_MSC_CTL
Definition: gd32f10x_enet.h:117
void enet_pauseframe_config | ( | uint32_t | pausetime,
 |  | uint32_t | pause_threshold
 | ) |  |

configure the pause frame parameters

Parameters
[in] | pausetime | pause time in transmit pause control frame
[in] pause_threshold the threshold of the pause timer for retransmitting frames automatically, this value must make sure to be less than configured pause time, only one parameter can be selected which is shown as below
  • ENET_PAUSETIME_MINUS4: pause time minus 4 slot times
  • ENET_PAUSETIME_MINUS28: pause time minus 28 slot times
  • ENET_PAUSETIME_MINUS144: pause time minus 144 slot times
  • ENET_PAUSETIME_MINUS256: pause time minus 256 slot times
[out] | none
Return values
none

Definition at line 1668 of file gd32f10x_enet.c.

1669 {
1670 ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS);
1671 ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold);
1672 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_MAC_FCTL_PTM
#define ENET_MAC_FCTL_PTM
Definition: gd32f10x_enet.h:207
ENET_MAC_FCTL_PLTS
#define ENET_MAC_FCTL_PLTS
Definition: gd32f10x_enet.h:205
MAC_FCTL_PTM
#define MAC_FCTL_PTM(regval)
Definition: gd32f10x_enet.h:1006
void enet_pauseframe_detect_config ( uint32_t detect )

configure the pause frame detect type

Parameters
[in] detect pause frame detect type, only one parameter can be selected which is shown as below
  • ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also use the MAC0 address to detecting pause frame
  • ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected
[out] none
Return values
none

Definition at line 1649 of file gd32f10x_enet.c.

1650 {
1651 ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT;
1652 ENET_MAC_FCTL |= detect;
1653 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_MAC_FCTL_UPFDT
#define ENET_MAC_FCTL_UPFDT
Definition: gd32f10x_enet.h:204
ErrStatus enet_pauseframe_generate ( void )

generate the pause frame, ENET will send pause frame after enable transmit flow control this function only use in full-dulex mode

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 1624 of file gd32f10x_enet.c.

1625 {
1626 ErrStatus enet_state =ERROR;
1627 uint32_t temp = 0U;
1628
1629 /* in full-duplex mode, must make sure this bit is 0 before writing register */
1630 temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA;
1631 if(RESET == temp){
1632 ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA;
1633 enet_state = SUCCESS;
1634 }
1635 return enet_state;
1636 }
ENET_MAC_FCTL
#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
ENET_MAC_FCTL_FLCBBKPA
#define ENET_MAC_FCTL_FLCBBKPA
Definition: gd32f10x_enet.h:201
ErrStatus enet_phy_config ( void )

PHY interface configuration (configure SMI clock and reset PHY chip)

Parameters
[in] | none
[out] | none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 1394 of file gd32f10x_enet.c.

1395 {
1396 uint32_t ahbclk;
1397 uint32_t reg;
1398 uint16_t phy_value;
1399 ErrStatus enet_state = ERROR;
1400
1401 /* clear the previous MDC clock */
1402 reg = ENET_MAC_PHY_CTL;
1403 reg &= ~ENET_MAC_PHY_CTL_CLR;
1404
1405 /* get the HCLK frequency */
1406 ahbclk = rcu_clock_freq_get(CK_AHB);
1407
1408 /* configure MDC clock according to HCLK frequency range */
1409 if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){
1410 reg |= ENET_MDC_HCLK_DIV16;
1411 }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){
1412 reg |= ENET_MDC_HCLK_DIV26;
1413 }else if(ENET_RANGE(ahbclk, 60000000U, 90000000U)){
1414 reg |= ENET_MDC_HCLK_DIV42;
1415 }else if((ENET_RANGE(ahbclk, 90000000U, 108000000U))||(108000000U == ahbclk)){
1416 reg |= ENET_MDC_HCLK_DIV62;
1417 }else{
1418 return enet_state;
1419 }
1420 ENET_MAC_PHY_CTL = reg;
1421
1422 /* reset PHY */
1423 phy_value = PHY_RESET;
1424 if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
1425 return enet_state;
1426 }
1427 /* PHY reset need some time */
1428 _ENET_DELAY_(ENET_DELAY_TO);
1429
1430 /* check whether PHY reset is complete */
1431 if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
1432 return enet_state;
1433 }
1434
1435 /* PHY reset complete */
1436 if(RESET == (phy_value & PHY_RESET)){
1437 enet_state = SUCCESS;
1438 }
1439
1440 return enet_state;
1441 }
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_RANGE
#define ENET_RANGE(hclk, n, m)
Definition: gd32f10x_enet.h:526
PHY_REG_BCR
#define PHY_REG_BCR
Definition: gd32f10x_enet.h:58
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
ENET_MAC_PHY_CTL
#define ENET_MAC_PHY_CTL
Definition: gd32f10x_enet.h:99
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
PHY_RESET
#define PHY_RESET
Definition: gd32f10x_enet.h:62
ENET_MDC_HCLK_DIV16
#define ENET_MDC_HCLK_DIV16
Definition: gd32f10x_enet.h:970
ENET_MDC_HCLK_DIV42
#define ENET_MDC_HCLK_DIV42
Definition: gd32f10x_enet.h:968
ENET_MDC_HCLK_DIV62
#define ENET_MDC_HCLK_DIV62
Definition: gd32f10x_enet.h:969
ENET_MDC_HCLK_DIV26
#define ENET_MDC_HCLK_DIV26
Definition: gd32f10x_enet.h:971
_ENET_DELAY_
#define _ENET_DELAY_
Definition: gd32f10x_enet.h:1473
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
CK_AHB
Definition: gd32f10x_rcu.h:585
PHY_ADDRESS
#define PHY_ADDRESS
Definition: gd32f10x_enet.h:47
ENET_MAC_PHY_CTL_CLR
#define ENET_MAC_PHY_CTL_CLR
Definition: gd32f10x_enet.h:193
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
ErrStatus enet_phy_write_read | ( | enet_phydirection_enum | direction,
 |  | uint16_t | phy_address,
 |  | uint16_t | phy_reg,
 |  | uint16_t * | pvalue
 | ) |  |

write to / read from a PHY register

Parameters
[in] direction only one parameter can be selected which is shown as below
  • ENET_PHY_WRITE: write data to phy register
  • ENET_PHY_READ: read data from phy register
[in] | phy_address | 0x0 - 0x1F
[in] | phy_reg | 0x0 - 0x1F
[in] | pvalue | the value will be written to the PHY register in ENET_PHY_WRITE direction
[out] | pvalue | the value will be read from the PHY register in ENET_PHY_READ direction
Return values
ErrStatus SUCCESS or ERROR

Definition at line 1454 of file gd32f10x_enet.c.

1455 {
1456 uint32_t reg, phy_flag;
1457 uint32_t timeout = 0U;
1458 ErrStatus enet_state = ERROR;
1459
1460 /* configure ENET_MAC_PHY_CTL with write/read operation */
1461 reg = ENET_MAC_PHY_CTL;
1462 reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA);
1463 reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB);
1464
1465 /* if do the write operation, write value to the register */
1466 if(ENET_PHY_WRITE == direction){
1467 ENET_MAC_PHY_DATA = *pvalue;
1468 }
1469
1470 /* do PHY write/read operation, and wait the operation complete */
1471 ENET_MAC_PHY_CTL = reg;
1472 do{
1473 phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB);
1474 timeout++;
1475 }
1476 while((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
1477
1478 /* write/read operation complete */
1479 if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){
1480 enet_state = SUCCESS;
1481 }
1482
1483 /* if do the read operation, get value from the register */
1484 if(ENET_PHY_READ == direction){
1485 *pvalue = (uint16_t)ENET_MAC_PHY_DATA;
1486 }
1487
1488 return enet_state;
1489 }
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
ENET_MAC_PHY_CTL_PA
#define ENET_MAC_PHY_CTL_PA
Definition: gd32f10x_enet.h:195
ENET_MAC_PHY_CTL
#define ENET_MAC_PHY_CTL
Definition: gd32f10x_enet.h:99
MAC_PHY_CTL_PR
#define MAC_PHY_CTL_PR(regval)
Definition: gd32f10x_enet.h:973
ENET_MAC_PHY_CTL_PW
#define ENET_MAC_PHY_CTL_PW
Definition: gd32f10x_enet.h:192
ENET_MAC_PHY_CTL_PR
#define ENET_MAC_PHY_CTL_PR
Definition: gd32f10x_enet.h:194
MAC_PHY_CTL_PA
#define MAC_PHY_CTL_PA(regval)
Definition: gd32f10x_enet.h:975
ENET_MAC_PHY_CTL_PB
#define ENET_MAC_PHY_CTL_PB
Definition: gd32f10x_enet.h:191
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
ENET_MAC_PHY_DATA
#define ENET_MAC_PHY_DATA
Definition: gd32f10x_enet.h:100
ErrStatus enet_phyloopback_disable ( void )

disable the loopback function of PHY chip

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 1520 of file gd32f10x_enet.c.

1521 {
1522 uint16_t temp_phy = 0U;
1523 ErrStatus phy_state = ERROR;
1524
1525 /* get the PHY configuration to update it */
1526 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1527
1528 /* disable the PHY loopback mode */
1529 temp_phy &= (uint16_t)~PHY_LOOPBACK;
1530
1531 /* update the PHY control register with the new configuration */
1532 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1533
1534 return phy_state;
1535 }
PHY_REG_BCR
#define PHY_REG_BCR
Definition: gd32f10x_enet.h:58
PHY_LOOPBACK
#define PHY_LOOPBACK
Definition: gd32f10x_enet.h:63
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
PHY_ADDRESS
#define PHY_ADDRESS
Definition: gd32f10x_enet.h:47
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
ErrStatus enet_phyloopback_enable ( void )

enable the loopback function of PHY chip

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 1497 of file gd32f10x_enet.c.

1498 {
1499 uint16_t temp_phy = 0U;
1500 ErrStatus phy_state = ERROR;
1501
1502 /* get the PHY configuration to update it */
1503 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1504
1505 /* enable the PHY loopback mode */
1506 temp_phy |= PHY_LOOPBACK;
1507
1508 /* update the PHY control register with the new configuration */
1509 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1510
1511 return phy_state;
1512 }
PHY_REG_BCR
#define PHY_REG_BCR
Definition: gd32f10x_enet.h:58
PHY_LOOPBACK
#define PHY_LOOPBACK
Definition: gd32f10x_enet.h:63
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
PHY_ADDRESS
#define PHY_ADDRESS
Definition: gd32f10x_enet.h:47
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
void enet_ptp_coarsecorrection_systime_update ( enet_ptp_systime_struct * systime_struct )

update system time in coarse method

Parameters
[in] | systime_struct | pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE
[out] | none
Return values
none

Definition at line 2850 of file gd32f10x_enet.c.

2851 {
2852 uint32_t subsecond_val;
2853 uint32_t carry_cfg;
2854
2855 subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
2856
2857 /* save the carry_cfg value */
2858 carry_cfg = ENET_PTP_TSADDEND_TMSA;
2859
2860 /* update the system time */
2861 enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
2862 enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE);
2863
2864 /* wait until the update is completed */
2865 while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){
2866 }
2867
2868 /* write back the carry_cfg value, then update */
2869 enet_ptp_timestamp_addend_config(carry_cfg);
2870 enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
2871 }
enet_ptp_timestamp_addend_config
void enet_ptp_timestamp_addend_config(uint32_t add)
adjusting the clock frequency only in fine update mode
Definition: gd32f10x_enet.c:2724
enet_ptp_flag_get
FlagStatus enet_ptp_flag_get(uint32_t flag)
get the ptp flag status
Definition: gd32f10x_enet.c:2908
enet_ptp_systime_struct::sign
uint32_t sign
Definition: gd32f10x_enet.h:873
enet_ptp_systime_struct::nanosecond
uint32_t nanosecond
Definition: gd32f10x_enet.h:872
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
enet_ptp_nanosecond_2_subsecond
uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
change nanosecond to subsecond
Definition: gd32f10x_enet.c:2600
enet_ptp_systime_struct::second
uint32_t second
Definition: gd32f10x_enet.h:871
enet_ptp_timestamp_update_config
void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time
Definition: gd32f10x_enet.c:2741
ENET_PTP_TSADDEND_TMSA
#define ENET_PTP_TSADDEND_TMSA
Definition: gd32f10x_enet.h:344
ENET_PTP_SYSTIME_UPDATE
Definition: gd32f10x_enet.h:1245
void enet_ptp_expected_time_config | ( | uint32_t | second,
 |  | uint32_t | nanosecond
 | ) |  |

configure the expected target time

Parameters
[in] | second | the expected target second time
[in] | nanosecond | the expected target nanosecond time (signed)
[out] | none
Return values
none

Definition at line 2754 of file gd32f10x_enet.c.

2755 {
2756 ENET_PTP_ETH = second;
2757 ENET_PTP_ETL = nanosecond;
2758 }
ENET_PTP_ETH
#define ENET_PTP_ETH
Definition: gd32f10x_enet.h:136
ENET_PTP_ETL
#define ENET_PTP_ETL
Definition: gd32f10x_enet.h:137
void enet_ptp_feature_disable ( uint32_t feature )

disable the PTP features

Parameters
[in] feature the feature of ENET PTP mode one or more parameters can be selected which are shown as below
  • ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames
  • ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger
[out] none
Return values
none

Definition at line 2630 of file gd32f10x_enet.c.

2631 {
2632 ENET_PTP_TSCTL &= ~feature;
2633 }
ENET_PTP_TSCTL
#define ENET_PTP_TSCTL
Definition: gd32f10x_enet.h:129
void enet_ptp_feature_enable ( uint32_t feature )

enable the PTP features

Parameters
[in] feature the feature of ENET PTP mode one or more parameters can be selected which are shown as below
  • ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames
  • ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger
[out] none
Return values
none

Definition at line 2616 of file gd32f10x_enet.c.

2617 {
2618 ENET_PTP_TSCTL |= feature;
2619 }
ENET_PTP_TSCTL
#define ENET_PTP_TSCTL
Definition: gd32f10x_enet.h:129
void enet_ptp_finecorrection_adjfreq ( int32_t carry_cfg )

adjust frequency in fine method by configure addend register

Parameters
[in] | carry_cfg | the value to be added to the accumulator register
[out] | none
Return values
none

Definition at line 2832 of file gd32f10x_enet.c.

2833 {
2834 /* re-configure the timestamp addend, then update */
2835 enet_ptp_timestamp_addend_config((uint32_t)carry_cfg);
2836 enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
2837 }
enet_ptp_timestamp_addend_config
void enet_ptp_timestamp_addend_config(uint32_t add)
adjusting the clock frequency only in fine update mode
Definition: gd32f10x_enet.c:2724
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
void enet_ptp_finecorrection_settime ( enet_ptp_systime_struct * systime_struct )

set system time in fine method

Parameters
[in] | systime_struct | pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE
[out] | none
Return values
none

Definition at line 2884 of file gd32f10x_enet.c.

2885 {
2886 uint32_t subsecond_val;
2887
2888 subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
2889
2890 /* initialize the system time */
2891 enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
2892 enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
2893
2894 /* wait until the system time initialzation finished */
2895 while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){
2896 }
2897 }
ENET_PTP_SYSTIME_INIT
Definition: gd32f10x_enet.h:1244
enet_ptp_flag_get
FlagStatus enet_ptp_flag_get(uint32_t flag)
get the ptp flag status
Definition: gd32f10x_enet.c:2908
enet_ptp_systime_struct::sign
uint32_t sign
Definition: gd32f10x_enet.h:873
enet_ptp_systime_struct::nanosecond
uint32_t nanosecond
Definition: gd32f10x_enet.h:872
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
enet_ptp_nanosecond_2_subsecond
uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
change nanosecond to subsecond
Definition: gd32f10x_enet.c:2600
enet_ptp_systime_struct::second
uint32_t second
Definition: gd32f10x_enet.h:871
enet_ptp_timestamp_update_config
void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time
Definition: gd32f10x_enet.c:2741
FlagStatus enet_ptp_flag_get ( uint32_t flag )

get the ptp flag status

Parameters
[in] flag ptp flag status to be checked
  • ENET_PTP_ADDEND_UPDATE: addend register update
  • ENET_PTP_SYSTIME_UPDATE: timestamp update
  • ENET_PTP_SYSTIME_INIT: timestamp initialize
[out] none
Return values
FlagStatus SET or RESET

Definition at line 2908 of file gd32f10x_enet.c.

2909 {
2910 FlagStatus bitstatus = RESET;
2911
2912 if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){
2913 bitstatus = SET;
2914 }
2915
2916 return bitstatus;
2917 }
ENET_PTP_TSCTL
#define ENET_PTP_TSCTL
Definition: gd32f10x_enet.h:129
uint32_t enet_ptp_nanosecond_2_subsecond ( uint32_t nanosecond )

change nanosecond to subsecond

Parameters
[in] | nanosecond | nanosecond value
[out] | none
Return values
the subsecond value

Definition at line 2600 of file gd32f10x_enet.c.

2601 {
2602 uint64_t val = nanosecond * 0x80000000Ull;
2603 val /= 1000000000U;
2604 return (uint32_t)val;
2605 }
void enet_ptp_normal_descriptors_chain_init | ( | enet_dmadirection_enum | direction,
 |  | enet_descriptors_struct * | desc_ptptab
 | ) |  |

initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function

Parameters
[in] direction the descriptors which users want to init, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA Tx descriptors
  • ENET_DMA_RX: DMA Rx descriptors
[in] | desc_ptptab | pointer to the first descriptor address of PTP Rx descriptor table
[out] | none
Return values
none

Definition at line 2120 of file gd32f10x_enet.c.

2121 {
2122 uint32_t num = 0U, count = 0U, maxsize = 0U;
2123 uint32_t desc_status = 0U, desc_bufsize = 0U;
2124 enet_descriptors_struct *desc, *desc_tab;
2125 uint8_t *buf;
2126
2127 /* if want to initialize DMA Tx descriptors */
2128 if (ENET_DMA_TX == direction){
2129 /* save a copy of the DMA Tx descriptors */
2130 desc_tab = txdesc_tab;
2131 buf = &tx_buff[0][0];
2132 count = ENET_TXBUF_NUM;
2133 maxsize = ENET_TXBUF_SIZE;
2134
2135 /* select chain mode, and enable transmit timestamp function */
2136 desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN;
2137
2138 /* configure DMA Tx descriptor table address register */
2139 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
2140 dma_current_txdesc = desc_tab;
2141 dma_current_ptp_txdesc = desc_ptptab;
2142 }else{
2143 /* if want to initialize DMA Rx descriptors */
2144 /* save a copy of the DMA Rx descriptors */
2145 desc_tab = rxdesc_tab;
2146 buf = &rx_buff[0][0];
2147 count = ENET_RXBUF_NUM;
2148 maxsize = ENET_RXBUF_SIZE;
2149
2150 /* enable receiving */
2151 desc_status = ENET_RDES0_DAV;
2152 /* select receive chained mode and set buffer1 size */
2153 desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
2154
2155 /* configure DMA Rx descriptor table address register */
2156 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
2157 dma_current_rxdesc = desc_tab;
2158 dma_current_ptp_rxdesc = desc_ptptab;
2159 }
2160
2161 /* configure each descriptor */
2162 for(num = 0U; num < count; num++){
2163 /* get the pointer to the next descriptor of the descriptor table */
2164 desc = desc_tab + num;
2165
2166 /* configure descriptors */
2167 desc->status = desc_status;
2168 desc->control_buffer_size = desc_bufsize;
2169 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
2170
2171 /* if is not the last descriptor */
2172 if(num < (count - 1U)){
2173 /* configure the next descriptor address */
2174 desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
2175 }else{
2176 /* when it is the last descriptor, the next descriptor address
2177 equals to first descriptor address in descriptor table */
2178 desc->buffer2_next_desc_addr = (uint32_t)desc_tab;
2179 }
2180 /* set desc_ptptab equal to desc_tab */
2181 (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
2182 (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
2183 }
2184 /* when it is the last ptp descriptor, preserve the first descriptor
2185 address of desc_ptptab in ptp descriptor status */
2186 (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
2187 }
ENET_RXBUF_NUM
#define ENET_RXBUF_NUM
Definition: gd32f10x_enet.h:25
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_TXBUF_SIZE
#define ENET_TXBUF_SIZE
Definition: gd32f10x_enet.h:37
ENET_TXBUF_NUM
#define ENET_TXBUF_NUM
Definition: gd32f10x_enet.h:29
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
ENET_TDES0_TTSEN
#define ENET_TDES0_TTSEN
Definition: gd32f10x_enet.h:467
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_TCHM
#define ENET_TDES0_TCHM
Definition: gd32f10x_enet.h:464
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_RXBUF_SIZE
#define ENET_RXBUF_SIZE
Definition: gd32f10x_enet.h:33
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_ptp_normal_descriptors_ring_init | ( | enet_dmadirection_enum | direction,
 |  | enet_descriptors_struct * | desc_ptptab
 | ) |  |

initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function

Parameters
[in] direction the descriptors which users want to init, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
  • ENET_DMA_TX: DMA Tx descriptors
  • ENET_DMA_RX: DMA Rx descriptors
[in] | desc_ptptab | pointer to the first descriptor address of PTP Rx descriptor table
[out] | none
Return values
none

Definition at line 2199 of file gd32f10x_enet.c.

2200 {
2201 uint32_t num = 0U, count = 0U, maxsize = 0U;
2202 uint32_t desc_status = 0U, desc_bufsize = 0U;
2203 enet_descriptors_struct *desc, *desc_tab;
2204 uint8_t *buf;
2205
2206 /* configure descriptor skip length */
2207 ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
2208 ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
2209
2210 /* if want to initialize DMA Tx descriptors */
2211 if (ENET_DMA_TX == direction){
2212 /* save a copy of the DMA Tx descriptors */
2213 desc_tab = txdesc_tab;
2214 buf = &tx_buff[0][0];
2215 count = ENET_TXBUF_NUM;
2216 maxsize = ENET_TXBUF_SIZE;
2217
2218 /* select ring mode, and enable transmit timestamp function */
2219 desc_status = ENET_TDES0_TTSEN;
2220
2221 /* configure DMA Tx descriptor table address register */
2222 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
2223 dma_current_txdesc = desc_tab;
2224 dma_current_ptp_txdesc = desc_ptptab;
2225 }else{
2226 /* if want to initialize DMA Rx descriptors */
2227 /* save a copy of the DMA Rx descriptors */
2228 desc_tab = rxdesc_tab;
2229 buf = &rx_buff[0][0];
2230 count = ENET_RXBUF_NUM;
2231 maxsize = ENET_RXBUF_SIZE;
2232
2233 /* enable receiving */
2234 desc_status = ENET_RDES0_DAV;
2235 /* select receive ring mode and set buffer1 size */
2236 desc_bufsize = (uint32_t)ENET_RXBUF_SIZE;
2237
2238 /* configure DMA Rx descriptor table address register */
2239 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
2240 dma_current_rxdesc = desc_tab;
2241 dma_current_ptp_rxdesc = desc_ptptab;
2242 }
2243
2244 /* configure each descriptor */
2245 for(num = 0U; num < count; num++){
2246 /* get the pointer to the next descriptor of the descriptor table */
2247 desc = desc_tab + num;
2248
2249 /* configure descriptors */
2250 desc->status = desc_status;
2251 desc->control_buffer_size = desc_bufsize;
2252 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
2253
2254 /* when it is the last descriptor */
2255 if(num == (count - 1U)){
2256 if (ENET_DMA_TX == direction){
2257 /* configure transmit end of ring mode */
2258 desc->status |= ENET_TDES0_TERM;
2259 }else{
2260 /* configure receive end of ring mode */
2261 desc->control_buffer_size |= ENET_RDES1_RERM;
2262 }
2263 }
2264 /* set desc_ptptab equal to desc_tab */
2265 (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
2266 (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
2267 }
2268 /* when it is the last ptp descriptor, preserve the first descriptor
2269 address of desc_ptptab in ptp descriptor status */
2270 (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
2271 }
ENET_RXBUF_NUM
#define ENET_RXBUF_NUM
Definition: gd32f10x_enet.h:25
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
ENET_DMA_BCTL_DPSL
#define ENET_DMA_BCTL_DPSL
Definition: gd32f10x_enet.h:355
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_TDES0_TERM
#define ENET_TDES0_TERM
Definition: gd32f10x_enet.h:465
ENET_TXBUF_SIZE
#define ENET_TXBUF_SIZE
Definition: gd32f10x_enet.h:37
ENET_TXBUF_NUM
#define ENET_TXBUF_NUM
Definition: gd32f10x_enet.h:29
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
ENET_TDES0_TTSEN
#define ENET_TDES0_TTSEN
Definition: gd32f10x_enet.h:467
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
DMA_BCTL_DPSL
#define DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1084
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_RXBUF_SIZE
#define ENET_RXBUF_SIZE
Definition: gd32f10x_enet.h:33
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_ptp_start | ( | int32_t | updatemethod,
 |  | uint32_t | init_sec,
 |  | uint32_t | init_subsec,
 |  | uint32_t | carry_cfg,
 |  | uint32_t | accuracy_cfg
 | ) |  |

configure and start PTP timestamp counter

Parameters
[in] updatemethod method for updating
  • ENET_PTP_FINEMODE: fine correction method
  • ENET_PTP_COARSEMODE: coarse correction method
[in] | init_sec | second value for initializing system time
[in] | init_subsec | subsecond value for initializing system time
[in] | carry_cfg | the value to be added to the accumulator register (in fine method is used)
[in] | accuracy_cfg | the value to be added to the subsecond value of system time
[out] | none
Return values
none

Definition at line 2798 of file gd32f10x_enet.c.

2799 {
2800 /* mask the timestamp trigger interrupt */
2801 enet_interrupt_disable(ENET_MAC_INT_TMSTIM);
2802
2803 /* enable timestamp */
2804 enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP);
2805
2806 /* configure system time subsecond increment based on the PTP clock frequency */
2807 enet_ptp_subsecond_increment_config(accuracy_cfg);
2808
2809 if(ENET_PTP_FINEMODE == updatemethod){
2810 /* fine correction method: configure the timestamp addend, then update */
2811 enet_ptp_timestamp_addend_config(carry_cfg);
2812 enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
2813 /* wait until update is completed */
2814 while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){
2815 }
2816 }
2817
2818 /* choose the fine correction method */
2819 enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod);
2820
2821 /* initialize the system time */
2822 enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec);
2823 enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
2824 }
ENET_PTP_SYSTIME_INIT
Definition: gd32f10x_enet.h:1244
ENET_RXTX_TIMESTAMP
#define ENET_RXTX_TIMESTAMP
Definition: gd32f10x_enet.h:1063
enet_ptp_timestamp_addend_config
void enet_ptp_timestamp_addend_config(uint32_t add)
adjusting the clock frequency only in fine update mode
Definition: gd32f10x_enet.c:2724
ENET_PTP_ADD_TO_TIME
#define ENET_PTP_ADD_TO_TIME
Definition: gd32f10x_enet.h:1080
enet_ptp_flag_get
FlagStatus enet_ptp_flag_get(uint32_t flag)
get the ptp flag status
Definition: gd32f10x_enet.c:2908
enet_ptp_feature_enable
void enet_ptp_feature_enable(uint32_t feature)
enable the PTP features
Definition: gd32f10x_enet.c:2616
enet_interrupt_disable
void enet_interrupt_disable(enet_int_enum enet_int)
disable ENET MAC/MSC/DMA interrupt
Definition: gd32f10x_enet.c:1158
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
ENET_PTP_FINEMODE
Definition: gd32f10x_enet.h:1247
ENET_MAC_INT_TMSTIM
Definition: gd32f10x_enet.h:633
enet_ptp_timestamp_update_config
void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time
Definition: gd32f10x_enet.c:2741
enet_ptp_function_enum
enet_ptp_function_enum
Definition: gd32f10x_enet.h:1243
enet_ptp_subsecond_increment_config
void enet_ptp_subsecond_increment_config(uint32_t subsecond)
configure system time subsecond increment value
Definition: gd32f10x_enet.c:2713
uint32_t enet_ptp_subsecond_2_nanosecond ( uint32_t subsecond )

change subsecond to nanosecond

Parameters
[in] | subsecond | subsecond value
[out] | none
Return values
the nanosecond value

Definition at line 2587 of file gd32f10x_enet.c.

2588 {
2589 uint64_t val = subsecond * 1000000000Ull;
2590 val >>= 31;
2591 return (uint32_t)val;
2592 }
void enet_ptp_subsecond_increment_config ( uint32_t subsecond )

configure system time subsecond increment value

Parameters
[in] | subsecond | the value will be added to the subsecond value of system time, this value must be between 0 and 0xFF
[out] | none
Return values
none

Definition at line 2713 of file gd32f10x_enet.c.

2714 {
2715 ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond);
2716 }
PTP_SSINC_STMSSI
#define PTP_SSINC_STMSSI(regval)
Definition: gd32f10x_enet.h:1067
ENET_PTP_SSINC
#define ENET_PTP_SSINC
Definition: gd32f10x_enet.h:130
void enet_ptp_system_time_get ( enet_ptp_systime_struct * systime_struct )

get the current system time

Parameters
[in] | none
[out] | systime_struct | pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE
Return values
none

Definition at line 2771 of file gd32f10x_enet.c.

2772 {
2773 uint32_t temp_sec = 0U, temp_subs = 0U;
2774
2775 /* get the value of sysytem time registers */
2776 temp_sec = (uint32_t)ENET_PTP_TSH;
2777 temp_subs = (uint32_t)ENET_PTP_TSL;
2778
2779 /* get sysytem time and construct the enet_ptp_systime_struct structure */
2780 systime_struct->second = temp_sec;
2781 systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs);
2782 systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond);
2783 systime_struct->sign = GET_PTP_TSL_STS(temp_subs);
2784 }
enet_ptp_systime_struct::sign
uint32_t sign
Definition: gd32f10x_enet.h:873
enet_ptp_subsecond_2_nanosecond
uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond)
change subsecond to nanosecond
Definition: gd32f10x_enet.c:2587
enet_ptp_systime_struct::nanosecond
uint32_t nanosecond
Definition: gd32f10x_enet.h:872
enet_ptp_systime_struct::second
uint32_t second
Definition: gd32f10x_enet.h:871
ENET_PTP_TSL
#define ENET_PTP_TSL
Definition: gd32f10x_enet.h:132
ENET_PTP_TSH
#define ENET_PTP_TSH
Definition: gd32f10x_enet.h:131
GET_PTP_TSL_STMSS
#define GET_PTP_TSL_STMSS(regval)
Definition: gd32f10x_enet.h:1070
GET_PTP_TSL_STS
#define GET_PTP_TSL_STS(regval)
Definition: gd32f10x_enet.h:1075
void enet_ptp_timestamp_addend_config ( uint32_t add )

adjusting the clock frequency only in fine update mode

Parameters
[in] | add | the value will be added to the accumulator register to achieve time synchronization
[out] | none
Return values
none

Definition at line 2724 of file gd32f10x_enet.c.

2725 {
2726 ENET_PTP_TSADDEND = add;
2727 }
ENET_PTP_TSADDEND
#define ENET_PTP_TSADDEND
Definition: gd32f10x_enet.h:135
ErrStatus enet_ptp_timestamp_function_config ( enet_ptp_function_enum func )

configure the PTP timestamp function

Parameters
[in] func only one parameter can be selected which is shown as below
  • ENET_PTP_ADDEND_UPDATE: addend register update
  • ENET_PTP_SYSTIME_UPDATE: timestamp update
  • ENET_PTP_SYSTIME_INIT: timestamp initialize
  • ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating
  • ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 2647 of file gd32f10x_enet.c.

2648 {
2649 uint32_t temp_config = 0U, temp_state = 0U;
2650 uint32_t timeout = 0U;
2651 ErrStatus enet_state = SUCCESS;
2652
2653 switch(func){
2654 case ENET_PTP_ADDEND_UPDATE:
2655 /* this bit must be read as zero before application set it */
2656 do{
2657 temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU;
2658 timeout++;
2659 }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
2660 /* return ERROR due to timeout */
2661 if(ENET_DELAY_TO == timeout){
2662 enet_state = ERROR;
2663 }else{
2664 ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU;
2665 }
2666 break;
2667 case ENET_PTP_SYSTIME_UPDATE:
2668 /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */
2669 do{
2670 temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI);
2671 timeout++;
2672 }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
2673 /* return ERROR due to timeout */
2674 if(ENET_DELAY_TO == timeout){
2675 enet_state = ERROR;
2676 }else{
2677 ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU;
2678 }
2679 break;
2680 case ENET_PTP_SYSTIME_INIT:
2681 /* this bit must be read as zero before application set it */
2682 do{
2683 temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI;
2684 timeout++;
2685 }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
2686 /* return ERROR due to timeout */
2687 if(ENET_DELAY_TO == timeout){
2688 enet_state = ERROR;
2689 }else{
2690 ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI;
2691 }
2692 break;
2693 default:
2694 temp_config = (uint32_t)func & (~BIT(31));
2695 if(RESET != ((uint32_t)func & BIT(31))){
2696 ENET_PTP_TSCTL |= temp_config;
2697 }else{
2698 ENET_PTP_TSCTL &= ~temp_config;
2699 }
2700 break;
2701 }
2702
2703 return enet_state;
2704 }
ENET_PTP_SYSTIME_INIT
Definition: gd32f10x_enet.h:1244
ENET_PTP_TSCTL_TMSSTU
#define ENET_PTP_TSCTL_TMSSTU
Definition: gd32f10x_enet.h:322
ENET_PTP_TSCTL_TMSARU
#define ENET_PTP_TSCTL_TMSARU
Definition: gd32f10x_enet.h:324
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
ENET_PTP_TSCTL
#define ENET_PTP_TSCTL
Definition: gd32f10x_enet.h:129
ENET_PTP_TSCTL_TMSSTI
#define ENET_PTP_TSCTL_TMSSTI
Definition: gd32f10x_enet.h:321
ENET_PTP_SYSTIME_UPDATE
Definition: gd32f10x_enet.h:1245
void enet_ptp_timestamp_update_config | ( | uint32_t | sign,
 |  | uint32_t | second,
 |  | uint32_t | subsecond
 | ) |  |

initialize or add/subtract to second of the system time

Parameters
[in] sign timestamp update positive or negative sign, only one parameter can be selected which is shown as below
  • ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time
  • ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time
[in] | second | initializing or adding/subtracting to second of the system time
[in] | subsecond | the current subsecond of the system time with 0.46 ns accuracy if required accuracy is 20 ns
[out] | none
Return values
none

Definition at line 2741 of file gd32f10x_enet.c.

2742 {
2743 ENET_PTP_TSUH = second;
2744 ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond);
2745 }
ENET_PTP_TSUL
#define ENET_PTP_TSUL
Definition: gd32f10x_enet.h:134
ENET_PTP_TSUH
#define ENET_PTP_TSUH
Definition: gd32f10x_enet.h:133
PTP_TSUL_TMSUSS
#define PTP_TSUL_TMSUSS(regval)
Definition: gd32f10x_enet.h:1078
ErrStatus enet_ptpframe_receive_normal_mode | ( | uint8_t * | buffer,
 |  | uint32_t | bufsize,
 |  | uint32_t | timestamp[]
 | ) |  |

receive a packet data with timestamp values to application buffer, when the DMA is in normal mode

Parameters
[in] | bufsize | the size of buffer which is the parameter in function
[out] | timestamp | pointer to the table which stores the timestamp high and low
[out] | buffer | pointer to the application buffer note – if the input is NULL, user should copy data in application by himself
Return values
ErrStatus SUCCESS or ERROR

Definition at line 2281 of file gd32f10x_enet.c.

2282 {
2283 uint32_t offset = 0U, size = 0U;
2284
2285 /* the descriptor is busy due to own by the DMA */
2286 if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
2287 return ERROR;
2288 }
2289
2290 /* if buffer pointer is null, indicates that users has copied data in application */
2291 if(NULL != buffer){
2292 /* if no error occurs, and the frame uses only one descriptor */
2293 if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
2294 ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
2295 ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
2296
2297 /* get the frame length except CRC */
2298 size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U;
2299
2300 /* to avoid situation that the frame size exceeds the buffer length */
2301 if(size > bufsize){
2302 return ERROR;
2303 }
2304
2305 /* copy data from Rx buffer to application buffer */
2306 for(offset = 0U; offset < size; offset++){
2307 (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset));
2308 }
2309
2310 }else{
2311 return ERROR;
2312 }
2313 }
2314 /* copy timestamp value from Rx descriptor to application array */
2315 timestamp[0] = dma_current_rxdesc->buffer1_addr;
2316 timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr;
2317
2318 dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ;
2319 dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr;
2320
2321 /* enable reception, descriptor is owned by DMA */
2322 dma_current_rxdesc->status = ENET_RDES0_DAV;
2323
2324 /* check Rx buffer unavailable flag status */
2325 if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
2326 /* clear RBU flag */
2327 ENET_DMA_STAT = ENET_DMA_STAT_RBU;
2328 /* resume DMA reception by writing to the RPEN register*/
2329 ENET_DMA_RPEN = 0U;
2330 }
2331
2332
2333 /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */
2334 /* chained mode */
2335 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
2336 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
2337 /* if it is the last ptp descriptor */
2338 if(0U != dma_current_ptp_rxdesc->status){
2339 /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
2340 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2341 }else{
2342 /* ponter to the next ptp descriptor */
2343 dma_current_ptp_rxdesc++;
2344 }
2345 }else{
2346 /* ring mode */
2347 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
2348 /* if is the last descriptor in table, the next descriptor is the table header */
2349 dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
2350 /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table,
2351 use the same table with RxDMA descriptor */
2352 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2353 }else{
2354 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
2355 dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
2356 dma_current_ptp_rxdesc ++;
2357 }
2358 }
2359
2360 return SUCCESS;
2361 }
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
GET_RDES0_FRML
#define GET_RDES0_FRML(regval)
Definition: gd32f10x_enet.h:1217
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ETH_DMARXDESC_SIZE
#define ETH_DMARXDESC_SIZE
Definition: gd32f10x_enet.h:1241
ENET_DMA_STAT_RBU
#define ENET_DMA_STAT_RBU
Definition: gd32f10x_enet.h:384
ENET_RDES0_FDES
#define ENET_RDES0_FDES
Definition: gd32f10x_enet.h:495
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
ENET_DMA_RPEN
#define ENET_DMA_RPEN
Definition: gd32f10x_enet.h:141
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_RDES0_ERRS
#define ENET_RDES0_ERRS
Definition: gd32f10x_enet.h:501
NULL
#define NULL
Definition: usbd_std.h:20
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
ENET_RDES0_LDES
#define ENET_RDES0_LDES
Definition: gd32f10x_enet.h:494
ErrStatus enet_ptpframe_transmit_normal_mode | ( | uint8_t * | buffer,
 |  | uint32_t | length,
 |  | uint32_t | timestamp[]
 | ) |  |

send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode

Parameters
[in] | buffer | pointer on the application buffer note – if the input is NULL, user should copy data in application by himself
[in] | length | the length of frame data to be transmitted
[out] | timestamp | pointer to the table which stores the timestamp high and low note – if the input is NULL, timestamp is ignored
Return values
ErrStatus SUCCESS or ERROR

Definition at line 2372 of file gd32f10x_enet.c.

2373 {
2374 uint32_t offset = 0U, timeout = 0U;
2375 uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag;
2376
2377 /* the descriptor is busy due to own by the DMA */
2378 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
2379 return ERROR;
2380 }
2381
2382 /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */
2383 if(length > ENET_MAX_FRAME_SIZE){
2384 return ERROR;
2385 }
2386
2387 /* if buffer pointer is null, indicates that users has handled data in application */
2388 if(NULL != buffer){
2389 /* copy frame data from application buffer to Tx buffer */
2390 for(offset = 0U; offset < length; offset++){
2391 (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
2392 }
2393 }
2394 /* set the frame length */
2395 dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF);
2396 /* set the segment of frame, frame is transmitted in one descriptor */
2397 dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
2398 /* enable the DMA transmission */
2399 dma_current_txdesc->status |= ENET_TDES0_DAV;
2400
2401 /* check Tx buffer unavailable flag status */
2402 dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
2403 dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
2404
2405 if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
2406 /* clear TBU and TU flag */
2407 ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
2408 /* resume DMA transmission by writing to the TPEN register*/
2409 ENET_DMA_TPEN = 0U;
2410 }
2411
2412 /* if timestamp pointer is null, indicates that users don't care timestamp in application */
2413 if(NULL != timestamp){
2414 /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */
2415 do{
2416 tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS);
2417 timeout++;
2418 }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO));
2419
2420 /* return ERROR due to timeout */
2421 if(ENET_DELAY_TO == timeout){
2422 return ERROR;
2423 }
2424
2425 /* clear the ENET_TDES0_TTMSS flag */
2426 dma_current_txdesc->status &= ~ENET_TDES0_TTMSS;
2427 /* get the timestamp value of the transmit frame */
2428 timestamp[0] = dma_current_txdesc->buffer1_addr;
2429 timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr;
2430 }
2431 dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ;
2432 dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr;
2433
2434 /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */
2435 /* chained mode */
2436 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
2437 dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr);
2438 /* if it is the last ptp descriptor */
2439 if(0U != dma_current_ptp_txdesc->status){
2440 /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
2441 dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
2442 }else{
2443 /* ponter to the next ptp descriptor */
2444 dma_current_ptp_txdesc++;
2445 }
2446 }else{
2447 /* ring mode */
2448 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
2449 /* if is the last descriptor in table, the next descriptor is the table header */
2450 dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
2451 /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table,
2452 use the same table with TxDMA descriptor */
2453 dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
2454 }else{
2455 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
2456 dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
2457 dma_current_ptp_txdesc ++;
2458 }
2459 }
2460 return SUCCESS;
2461 }
ETH_DMATXDESC_SIZE
#define ETH_DMATXDESC_SIZE
Definition: gd32f10x_enet.h:1240
ENET_MAX_FRAME_SIZE
#define ENET_MAX_FRAME_SIZE
Definition: gd32f10x_enet.h:1256
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_DMA_STAT_TU
#define ENET_DMA_STAT_TU
Definition: gd32f10x_enet.h:382
ENET_TDES0_TERM
#define ENET_TDES0_TERM
Definition: gd32f10x_enet.h:465
ENET_DMA_STAT_TBU
#define ENET_DMA_STAT_TBU
Definition: gd32f10x_enet.h:379
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ENET_TDES0_FSG
#define ENET_TDES0_FSG
Definition: gd32f10x_enet.h:470
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
ENET_DMA_TPEN
#define ENET_DMA_TPEN
Definition: gd32f10x_enet.h:140
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_TCHM
#define ENET_TDES0_TCHM
Definition: gd32f10x_enet.h:464
NULL
#define NULL
Definition: usbd_std.h:20
ENET_TDES0_TTMSS
#define ENET_TDES0_TTMSS
Definition: gd32f10x_enet.h:463
ENET_TDES0_LSG
#define ENET_TDES0_LSG
Definition: gd32f10x_enet.h:471
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
ENET_TDES0_DAV
#define ENET_TDES0_DAV
Definition: gd32f10x_enet.h:473
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
void enet_registers_get | ( | enet_registers_type_enum | type,
 |  | uint32_t * | preg,
 |  | uint32_t | num
 | ) |  |

put registers value into the application buffer

Parameters
[in] type register type which will be get, refer to enet_registers_type_enum, only one parameter can be selected which is shown as below
  • ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH
  • ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT
  • ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL
  • ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR
[in] | num | the number of registers that the user want to get
[out] | preg | the application buffer pointer for storing the register value
Return values
none

Definition at line 1304 of file gd32f10x_enet.c.

1305 {
1306 uint32_t offset = 0U, max = 0U, limit = 0U;
1307
1308 offset = (uint32_t)type;
1309 max = (uint32_t)type + num;
1310 limit = sizeof(enet_reg_tab)/sizeof(uint16_t);
1311
1312 /* prevent element in this array is out of range */
1313 if(max > limit){
1314 max = limit;
1315 }
1316
1317 for(; offset < max; offset++){
1318 /* get value of the corresponding register */
1319 *preg = REG32((ENET) + enet_reg_tab[offset]);
1320 preg++;
1321 }
1322 }
ENET
#define ENET
Definition: gd32f10x_enet.h:92
void enet_rx_desc_immediate_receive_complete_interrupt ( enet_descriptors_struct * desc )

when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set

Parameters
[in] | desc | the descriptor pointer which users want to configure
[out] | none
Return values
none

Definition at line 2032 of file gd32f10x_enet.c.

2033 {
2034 desc->control_buffer_size &= ~ENET_RDES1_DINTC;
2035 }
ENET_RDES1_DINTC
#define ENET_RDES1_DINTC
Definition: gd32f10x_enet.h:511
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
void enet_rx_disable ( void )

ENET Rx function disable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1286 of file gd32f10x_enet.c.

1287 {
1288 ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE;
1289 ENET_MAC_CFG &= ~ENET_MAC_CFG_REN;
1290 }
ENET_DMA_CTL_SRE
#define ENET_DMA_CTL_SRE
Definition: gd32f10x_enet.h:400
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_MAC_CFG_REN
#define ENET_MAC_CFG_REN
Definition: gd32f10x_enet.h:155
void enet_rx_enable ( void )

ENET Rx function enable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1274 of file gd32f10x_enet.c.

1275 {
1276 ENET_MAC_CFG |= ENET_MAC_CFG_REN;
1277 ENET_DMA_CTL |= ENET_DMA_CTL_SRE;
1278 }
ENET_DMA_CTL_SRE
#define ENET_DMA_CTL_SRE
Definition: gd32f10x_enet.h:400
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_MAC_CFG_REN
#define ENET_MAC_CFG_REN
Definition: gd32f10x_enet.h:155
void enet_rxframe_drop ( void )

drop current receive frame

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 2043 of file gd32f10x_enet.c.

2044 {
2045 /* enable reception, descriptor is owned by DMA */
2046 dma_current_rxdesc->status = ENET_RDES0_DAV;
2047
2048 /* chained mode */
2049 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
2050 if(NULL != dma_current_ptp_rxdesc){
2051 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
2052 /* if it is the last ptp descriptor */
2053 if(0U != dma_current_ptp_rxdesc->status){
2054 /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
2055 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2056 }else{
2057 /* ponter to the next ptp descriptor */
2058 dma_current_ptp_rxdesc++;
2059 }
2060 }else{
2061 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
2062 }
2063
2064 }else{
2065 /* ring mode */
2066 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
2067 /* if is the last descriptor in table, the next descriptor is the table header */
2068 dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
2069 if(NULL != dma_current_ptp_rxdesc){
2070 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2071 }
2072 }else{
2073 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
2074 dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
2075 if(NULL != dma_current_ptp_rxdesc){
2076 dma_current_ptp_rxdesc++;
2077 }
2078 }
2079 }
2080 }
ENET_RDES1_RCHM
#define ENET_RDES1_RCHM
Definition: gd32f10x_enet.h:508
ENET_DMA_RDTADDR
#define ENET_DMA_RDTADDR
Definition: gd32f10x_enet.h:142
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
ETH_DMARXDESC_SIZE
#define ETH_DMARXDESC_SIZE
Definition: gd32f10x_enet.h:1241
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
NULL
#define NULL
Definition: usbd_std.h:20
uint32_t enet_rxframe_size_get ( void )

check receive frame valid and return frame size

Parameters
[in] | none
[out] | none
Return values
size of received frame: 0x0 - 0x3FFF

Definition at line 591 of file gd32f10x_enet.c.

592 {
593 uint32_t size = 0U;
594 uint32_t status;
595
596 /* get rdes0 information of current RxDMA descriptor */
597 status = dma_current_rxdesc->status;
598
599 /* if the desciptor is owned by DMA */
600 if((uint32_t)RESET != (status & ENET_RDES0_DAV)){
601 return 0U;
602 }
603
604 /* if has any error, or the frame uses two or more descriptors */
605 if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) ||
606 (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) ||
607 (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){
608 /* drop current receive frame */
609 enet_rxframe_drop();
610
611 return 0U;
612 }
613
614 /* if is an ethernet-type frame, and IP frame payload error occurred */
615 if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) &&
616 (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){
617 /* drop current receive frame */
618 enet_rxframe_drop();
619
620 return 0U;
621 }
622
623 /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */
624 if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) &&
625 (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) &&
626 (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) &&
627 (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){
628 /* get the size of the received data including CRC */
629 size = GET_RDES0_FRML(status);
630 /* substract the CRC size */
631 size = size - 4U;
632 }
633
634 /* return packet size */
635 return size;
636 }
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
ENET_RDES0_PCERR
#define ENET_RDES0_PCERR
Definition: gd32f10x_enet.h:486
enet_rxframe_drop
void enet_rxframe_drop(void)
drop current receive frame
Definition: gd32f10x_enet.c:2043
GET_RDES0_FRML
#define GET_RDES0_FRML(regval)
Definition: gd32f10x_enet.h:1217
ENET_RDES0_FRMT
#define ENET_RDES0_FRMT
Definition: gd32f10x_enet.h:491
ENET_RDES0_FDES
#define ENET_RDES0_FDES
Definition: gd32f10x_enet.h:495
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_RDES0_ERRS
#define ENET_RDES0_ERRS
Definition: gd32f10x_enet.h:501
ENET_RDES0_LDES
#define ENET_RDES0_LDES
Definition: gd32f10x_enet.h:494
void enet_rxprocess_check_recovery ( void )

check and recover the Rx process

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1788 of file gd32f10x_enet.c.

1789 {
1790 uint32_t status;
1791
1792 /* get DAV information of current RxDMA descriptor */
1793 status = dma_current_rxdesc->status;
1794 status &= ENET_RDES0_DAV;
1795
1796 /* if current descriptor is owned by DMA, but the descriptor address mismatches with
1797 receive descriptor address pointer updated by RxDMA controller */
1798 if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) &&
1799 (ENET_RDES0_DAV == status)){
1800 dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR;
1801 }
1802 }
dma_current_rxdesc
enet_descriptors_struct * dma_current_rxdesc
Definition: gd32f10x_enet.c:41
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_DMA_CRDADDR
#define ENET_DMA_CRDADDR
Definition: gd32f10x_enet.h:149
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ErrStatus enet_software_reset ( void )

reset all core internal registers located in CLK_TX and CLK_RX

Parameters
[in] | none
[out] | none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 562 of file gd32f10x_enet.c.

563 {
564 uint32_t timeout = 0U;
565 ErrStatus enet_state = ERROR;
566 uint32_t dma_flag;
567
568 /* reset all core internal registers located in CLK_TX and CLK_RX */
569 ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR;
570
571 /* wait for reset operation complete */
572 do{
573 dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR);
574 timeout++;
575 }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout));
576
577 /* reset operation complete */
578 if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){
579 enet_state = SUCCESS;
580 }
581
582 return enet_state;
583 }
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_DMA_BCTL_SWR
#define ENET_DMA_BCTL_SWR
Definition: gd32f10x_enet.h:353
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
void enet_transmit_checksum_config | ( | enet_descriptors_struct * | desc,
 |  | uint32_t | checksum
 | ) |  |

configure the transmit IP frame checksum offload calculation and insertion

Parameters
[in] | desc | the descriptor pointer which users want to configure
[in] checksum IP frame checksum configuration only one parameter can be selected which is shown as below
  • ENET_CHECKSUM_DISABLE: checksum insertion disabled
  • ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled
  • ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header
  • ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated
[out] | none
Return values
none

Definition at line 935 of file gd32f10x_enet.c.

936 {
937 desc->status &= ~ENET_TDES0_CM;
938 desc->status |= checksum;
939 }
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_TDES0_CM
#define ENET_TDES0_CM
Definition: gd32f10x_enet.h:466
void enet_tx_disable ( void )

ENET Tx function disable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1261 of file gd32f10x_enet.c.

1262 {
1263 ENET_DMA_CTL &= ~ENET_DMA_CTL_STE;
1264 enet_txfifo_flush();
1265 ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN;
1266 }
ENET_DMA_CTL_STE
#define ENET_DMA_CTL_STE
Definition: gd32f10x_enet.h:405
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
enet_txfifo_flush
ErrStatus enet_txfifo_flush(void)
flush the ENET transmit FIFO, and wait until the flush operation completes
Definition: gd32f10x_enet.c:1810
ENET_MAC_CFG_TEN
#define ENET_MAC_CFG_TEN
Definition: gd32f10x_enet.h:156
void enet_tx_enable ( void )

ENET Tx function enable (include MAC and DMA module)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 1248 of file gd32f10x_enet.c.

1249 {
1250 ENET_MAC_CFG |= ENET_MAC_CFG_TEN;
1251 enet_txfifo_flush();
1252 ENET_DMA_CTL |= ENET_DMA_CTL_STE;
1253 }
ENET_DMA_CTL_STE
#define ENET_DMA_CTL_STE
Definition: gd32f10x_enet.h:405
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
enet_txfifo_flush
ErrStatus enet_txfifo_flush(void)
flush the ENET transmit FIFO, and wait until the flush operation completes
Definition: gd32f10x_enet.c:1810
ENET_MAC_CFG_TEN
#define ENET_MAC_CFG_TEN
Definition: gd32f10x_enet.h:156
ErrStatus enet_txfifo_flush ( void )

flush the ENET transmit FIFO, and wait until the flush operation completes

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 1810 of file gd32f10x_enet.c.

1811 {
1812 uint32_t flush_state;
1813 uint32_t timeout = 0U;
1814 ErrStatus enet_state = ERROR;
1815
1816 /* set the FTF bit for flushing transmit FIFO */
1817 ENET_DMA_CTL |= ENET_DMA_CTL_FTF;
1818 /* wait until the flush operation completes */
1819 do{
1820 flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF;
1821 timeout++;
1822 }while((RESET != flush_state) && (timeout < ENET_DELAY_TO));
1823 /* return ERROR due to timeout */
1824 if(RESET == flush_state){
1825 enet_state = SUCCESS;
1826 }
1827
1828 return enet_state;
1829 }
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
ENET_DMA_CTL_FTF
#define ENET_DMA_CTL_FTF
Definition: gd32f10x_enet.h:407
void enet_wum_feature_disable ( uint32_t feature )

disable wakeup management features

Parameters
[in] feature one or more parameters can be selected which are shown as below
  • ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception
  • ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception
  • ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame
[out] none
Return values
none

Definition at line 2514 of file gd32f10x_enet.c.

2515 {
2516 ENET_MAC_WUM &= (~feature);
2517 }
ENET_MAC_WUM
#define ENET_MAC_WUM
Definition: gd32f10x_enet.h:105
void enet_wum_feature_enable ( uint32_t feature )

enable wakeup management features

Parameters
[in] feature one or more parameters can be selected which are shown as below
  • ENET_WUM_POWER_DOWN: power down mode
  • ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception
  • ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception
  • ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame
[out] none
Return values
none

Definition at line 2500 of file gd32f10x_enet.c.

2501 {
2502 ENET_MAC_WUM |= feature;
2503 }
ENET_MAC_WUM
#define ENET_MAC_WUM
Definition: gd32f10x_enet.h:105
void enet_wum_filter_config ( uint32_t pdata[] )

set the remote wakeup frame registers

Parameters
[in] | pdata | pointer to buffer data which is written to remote wakeup frame registers (8 words total)
[out] | none
Return values
none

Definition at line 2480 of file gd32f10x_enet.c.

2481 {
2482 uint32_t num = 0U;
2483
2484 /* configure ENET_MAC_RWFF register */
2485 for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){
2486 ENET_MAC_RWFF = pdata[num];
2487 }
2488 }
ETH_WAKEUP_REGISTER_LENGTH
#define ETH_WAKEUP_REGISTER_LENGTH
Definition: gd32f10x_enet.h:1253
ENET_MAC_RWFF
#define ENET_MAC_RWFF
Definition: gd32f10x_enet.h:104
void enet_wum_filter_register_pointer_reset ( void )

wakeup frame filter register pointer reset

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 2469 of file gd32f10x_enet.c.

2470 {
2471 ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR;
2472 }
ENET_MAC_WUM_WUFFRPR
#define ENET_MAC_WUM_WUFFRPR
Definition: gd32f10x_enet.h:227
ENET_MAC_WUM
#define ENET_MAC_WUM
Definition: gd32f10x_enet.h:105

Variable Documentation

enet_descriptors_struct* dma_current_ptp_rxdesc = NULL

Definition at line 45 of file gd32f10x_enet.c.

enet_descriptors_struct* dma_current_ptp_txdesc = NULL

Definition at line 44 of file gd32f10x_enet.c.

enet_descriptors_struct* dma_current_rxdesc

Definition at line 41 of file gd32f10x_enet.c.

enet_descriptors_struct* dma_current_txdesc

< ARM compiler

< IAR compiler

Definition at line 40 of file gd32f10x_enet.c.

Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_exmc.c File Reference

EXMC driver. More...

#include "gd32f10x_exmc.h"

Go to the source code of this file.

Macros

#define | BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DBU)
#define | BANK0_SNCTL1_2_3_REGION_RESET ((uint32_t)0x000030D2U)
#define | BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)
#define | BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU)
#define | BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U)
#define | BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U)
#define | BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)
#define | BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)
#define | BANK3_NPCTL_RESET ((uint32_t)0x00000018U)
#define | BANK3_NPINTEN_RESET ((uint32_t)0x00000040U)
#define | BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)
#define | BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)
#define | BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU)
#define | SNCTL_NRMUX_OFFSET ((uint32_t)1U)
#define | SNCTL_SBRSTEN_OFFSET ((uint32_t)8U)
#define | SNCTL_WRAPEN_OFFSET ((uint32_t)10U)
#define | SNCTL_WREN_OFFSET ((uint32_t)12U)
#define | SNCTL_NRWTEN_OFFSET ((uint32_t)13U)
#define | SNCTL_EXMODEN_OFFSET ((uint32_t)14U)
#define | SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)
#define | SNTCFG_AHLD_OFFSET ((uint32_t)4U)
#define | SNTCFG_DSET_OFFSET ((uint32_t)8U)
#define | SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)
#define | SNWTCFG_WAHLD_OFFSET ((uint32_t)4U)
#define | SNWTCFG_WDSET_OFFSET ((uint32_t)8U)
#define | SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U)
#define | NPCTL_NDWTEN_OFFSET ((uint32_t)1U)
#define | NPCTL_ECCEN_OFFSET ((uint32_t)6U)
#define | NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U)
#define | NPCTCFG_COMHLD_OFFSET ((uint32_t)16U)
#define | NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U)
#define | NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U)
#define | NPATCFG_ATTHLD_OFFSET ((uint32_t)16U)
#define | NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U)
#define | PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U)
#define | PIOTCFG_IOHLD_OFFSET ((uint32_t)16U)
#define | PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U)
#define | INTEN_INTS_OFFSET ((uint32_t)3U)

Functions

void | exmc_norsram_deinit (uint32_t norsram_region)
deinitialize EXMC NOR/SRAM region More...
void | exmc_norsram_init (exmc_norsram_parameter_struct *exmc_norsram_init_struct)
initialize EXMC NOR/SRAM region More...
void | exmc_norsram_parameter_init (exmc_norsram_parameter_struct *exmc_norsram_init_struct)
initialize the struct exmc_norsram_parameter_struct More...
void | exmc_norsram_enable (uint32_t norsram_region)
enable EXMC NOR/PSRAM bank region More...
void | exmc_norsram_disable (uint32_t norsram_region)
disable EXMC NOR/PSRAM bank region More...
void | exmc_nand_deinit (uint32_t nand_bank)
deinitialize EXMC NAND bank More...
void | exmc_nand_init (exmc_nand_parameter_struct *exmc_nand_init_struct)
initialize EXMC NAND bank More...
void | exmc_nand_parameter_init (exmc_nand_parameter_struct *exmc_nand_init_struct)
initialize the struct exmc_norsram_parameter_struct More...
void | exmc_nand_enable (uint32_t nand_bank)
enable NAND bank More...
void | exmc_nand_disable (uint32_t nand_bank)
disable NAND bank More...
void | exmc_nand_ecc_config (uint32_t nand_bank, ControlStatus newvalue)
enable or disable the EXMC NAND ECC function More...
uint32_t | exmc_ecc_get (uint32_t nand_bank)
get the EXMC ECC value More...
void | exmc_pccard_deinit (void)
deinitialize EXMC PC card bank More...
void | exmc_pccard_init (exmc_pccard_parameter_struct *exmc_pccard_init_struct)
initialize EXMC PC card bank More...
void | exmc_pccard_parameter_init (exmc_pccard_parameter_struct *exmc_pccard_init_struct)
initialize the struct exmc_pccard_parameter_struct More...
void | exmc_pccard_enable (void)
enable PC Card Bank More...
void | exmc_pccard_disable (void)
disable PC Card Bank More...
FlagStatus | exmc_flag_get (uint32_t bank, uint32_t flag)
check EXMC flag is set or not More...
void | exmc_flag_clear (uint32_t bank, uint32_t flag)
clear EXMC flag More...
FlagStatus | exmc_interrupt_flag_get (uint32_t bank, uint32_t interrupt_source)
check EXMC interrupt flag is set or not More...
void | exmc_interrupt_flag_clear (uint32_t bank, uint32_t interrupt_source)
clear EXMC interrupt flag More...
void | exmc_interrupt_enable (uint32_t bank, uint32_t interrupt_source)
enable EXMC interrupt More...
void | exmc_interrupt_disable (uint32_t bank, uint32_t interrupt_source)
disable EXMC interrupt More...

Detailed Description

EXMC driver.

Definition in file gd32f10x_exmc.c.

Macro Definition Documentation

#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DBU)

Definition at line 16 of file gd32f10x_exmc.c.

#define BANK0_SNCTL1_2_3_REGION_RESET ((uint32_t)0x000030D2U)

Definition at line 17 of file gd32f10x_exmc.c.

#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)

Definition at line 18 of file gd32f10x_exmc.c.

#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU)

Definition at line 19 of file gd32f10x_exmc.c.

#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)

Definition at line 25 of file gd32f10x_exmc.c.

#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)

Definition at line 24 of file gd32f10x_exmc.c.

#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U)

Definition at line 22 of file gd32f10x_exmc.c.

#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U)

Definition at line 23 of file gd32f10x_exmc.c.

#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)

Definition at line 31 of file gd32f10x_exmc.c.

#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)

Definition at line 30 of file gd32f10x_exmc.c.

#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U)

Definition at line 28 of file gd32f10x_exmc.c.

#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U)

Definition at line 29 of file gd32f10x_exmc.c.

#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU)

Definition at line 32 of file gd32f10x_exmc.c.

#define INTEN_INTS_OFFSET ((uint32_t)3U)

Definition at line 66 of file gd32f10x_exmc.c.

#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U)

Definition at line 60 of file gd32f10x_exmc.c.

#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U)

Definition at line 59 of file gd32f10x_exmc.c.

#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U)

Definition at line 58 of file gd32f10x_exmc.c.

#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U)

Definition at line 56 of file gd32f10x_exmc.c.

#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U)

Definition at line 55 of file gd32f10x_exmc.c.

#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U)

Definition at line 54 of file gd32f10x_exmc.c.

#define NPCTL_ECCEN_OFFSET ((uint32_t)6U)

Definition at line 52 of file gd32f10x_exmc.c.

#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U)

Definition at line 51 of file gd32f10x_exmc.c.

#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U)

Definition at line 64 of file gd32f10x_exmc.c.

#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U)

Definition at line 63 of file gd32f10x_exmc.c.

#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U)

Definition at line 62 of file gd32f10x_exmc.c.

#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)

Definition at line 41 of file gd32f10x_exmc.c.

#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U)

Definition at line 40 of file gd32f10x_exmc.c.

#define SNCTL_NRMUX_OFFSET ((uint32_t)1U)

Definition at line 35 of file gd32f10x_exmc.c.

#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U)

Definition at line 39 of file gd32f10x_exmc.c.

#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U)

Definition at line 36 of file gd32f10x_exmc.c.

#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U)

Definition at line 37 of file gd32f10x_exmc.c.

#define SNCTL_WREN_OFFSET ((uint32_t)12U)

Definition at line 38 of file gd32f10x_exmc.c.

#define SNTCFG_AHLD_OFFSET ((uint32_t)4U)

Definition at line 43 of file gd32f10x_exmc.c.

#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)

Definition at line 45 of file gd32f10x_exmc.c.

#define SNTCFG_DSET_OFFSET ((uint32_t)8U)

Definition at line 44 of file gd32f10x_exmc.c.

#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U)

Definition at line 47 of file gd32f10x_exmc.c.

#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U)

Definition at line 49 of file gd32f10x_exmc.c.

#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U)

Definition at line 48 of file gd32f10x_exmc.c.

Function Documentation

uint32_t exmc_ecc_get ( uint32_t nand_bank )

get the EXMC ECC value

Parameters
[in] nand_bank specifie the NAND bank
  • EXMC_BANKx_NAND(x=1,2)
[out] none
Return values
the error correction code(ECC) value

Definition at line 363 of file gd32f10x_exmc.c.

364 {
365 return (EXMC_NECC(nand_bank));
366 }
EXMC_NECC
#define EXMC_NECC(bank)
Definition: gd32f10x_exmc.h:211
void exmc_flag_clear | ( | uint32_t | bank,
 |  | uint32_t | flag
 | ) |  |

clear EXMC flag

Parameters
[in] bank specifie the NAND bank , PCCARD bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] flag specify get which flag
  • EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status
  • EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status
  • EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status
  • EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag
[out] none
Return values
none

Definition at line 515 of file gd32f10x_exmc.c.

516 {
517 /* NAND bank1,bank2 or PC card bank3 */
518 EXMC_NPINTEN(bank) &= ~flag;
519 }
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
FlagStatus exmc_flag_get | ( | uint32_t | bank,
 |  | uint32_t | flag
 | ) |  |

check EXMC flag is set or not

Parameters
[in] bank specifies the NAND bank , PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC Card bank
[in] flag specify get which flag
  • EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status
  • EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status
  • EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status
  • EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 485 of file gd32f10x_exmc.c.

486 {
487 uint32_t status = 0x00000000U;
488
489 /* NAND bank1,bank2 or PC card bank3 */
490 status = EXMC_NPINTEN(bank);
491
492 if ((status & flag) != (uint32_t)flag ){
493 /* flag is reset */
494 return RESET;
495 }else{
496 /* flag is set */
497 return SET;
498 }
499 }
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_interrupt_disable | ( | uint32_t | bank,
 |  | uint32_t | interrupt_source
 | ) |  |

disable EXMC interrupt

Parameters
[in] bank specifies the NAND bank , PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] interrupt_source specify get which interrupt flag
  • EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
  • EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
  • EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
[out] none
Return values
none

Definition at line 604 of file gd32f10x_exmc.c.

605 {
606 /* NAND bank1,bank2 or PC card bank3 */
607 EXMC_NPINTEN(bank) &= ~interrupt_source;
608 }
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_interrupt_enable | ( | uint32_t | bank,
 |  | uint32_t | interrupt_source
 | ) |  |

enable EXMC interrupt

Parameters
[in] bank specifies the NAND bank,PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] interrupt_source specify get which interrupt flag
  • EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
  • EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
  • EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
[out] none
Return values
none

Definition at line 585 of file gd32f10x_exmc.c.

586 {
587 /* NAND bank1,bank2 or PC card bank3 */
588 EXMC_NPINTEN(bank) |= interrupt_source;
589 }
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_interrupt_flag_clear | ( | uint32_t | bank,
 |  | uint32_t | interrupt_source
 | ) |  |

clear EXMC interrupt flag

Parameters
[in] bank specifies the NAND bank , PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] interrupt_source specify get which interrupt flag
  • EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
  • EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
  • EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
[out] none
Return values
none

Definition at line 566 of file gd32f10x_exmc.c.

567 {
568 /* NAND bank1,bank2 or PC card bank3 */
569 EXMC_NPINTEN(bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET);
570 }
INTEN_INTS_OFFSET
#define INTEN_INTS_OFFSET
Definition: gd32f10x_exmc.c:66
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
FlagStatus exmc_interrupt_flag_get | ( | uint32_t | bank,
 |  | uint32_t | interrupt_source
 | ) |  |

check EXMC interrupt flag is set or not

Parameters
[in] bank specifies the NAND bank , PC card bank
  • EXMC_BANK1_NAND: the NAND bank1
  • EXMC_BANK2_NAND: the NAND bank2
  • EXMC_BANK3_PCCARD: the PC card bank
[in] interrupt_source specify get which interrupt flag
  • EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
  • EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
  • EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
[out] none
Return values
FlagStatus SET or RESET

Definition at line 534 of file gd32f10x_exmc.c.

535 {
536 uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U;
537
538 /* NAND bank1,bank2 or PC card bank3 */
539 status = EXMC_NPINTEN(bank);
540 interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET));
541
542 interrupt_enable = (status & interrupt_source);
543
544 if ((interrupt_enable) && (interrupt_state)){
545 /* interrupt flag is set */
546 return SET;
547 }else{
548 /* interrupt flag is reset */
549 return RESET;
550 }
551 }
INTEN_INTS_OFFSET
#define INTEN_INTS_OFFSET
Definition: gd32f10x_exmc.c:66
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_nand_deinit ( uint32_t nand_bank )

deinitialize EXMC NAND bank

Parameters
[in] nand_bank select the bank of NAND
  • EXMC_BANKx_NAND(x=1..2)
[out] none
Return values
none

Definition at line 235 of file gd32f10x_exmc.c.

236 {
237 /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */
238 EXMC_NPCTL(nand_bank) = BANK1_2_NPCTL_RESET;
239 EXMC_NPINTEN(nand_bank) = BANK1_2_NPINTEN_RESET;
240 EXMC_NPCTCFG(nand_bank) = BANK1_2_NPCTCFG_RESET;
241 EXMC_NPATCFG(nand_bank) = BANK1_2_NPATCFG_RESET;
242 }
BANK1_2_NPCTCFG_RESET
#define BANK1_2_NPCTCFG_RESET
Definition: gd32f10x_exmc.c:24
EXMC_NPATCFG
#define EXMC_NPATCFG(bank)
Definition: gd32f10x_exmc.h:210
BANK1_2_NPATCFG_RESET
#define BANK1_2_NPATCFG_RESET
Definition: gd32f10x_exmc.c:25
BANK1_2_NPINTEN_RESET
#define BANK1_2_NPINTEN_RESET
Definition: gd32f10x_exmc.c:23
BANK1_2_NPCTL_RESET
#define BANK1_2_NPCTL_RESET
Definition: gd32f10x_exmc.c:22
EXMC_NPCTCFG
#define EXMC_NPCTCFG(bank)
Definition: gd32f10x_exmc.h:209
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
void exmc_nand_disable ( uint32_t nand_bank )

disable NAND bank

Parameters
[in] nand_bank specifie the NAND bank
  • EXMC_BANKx_NAND(x=1,2)
[out] none
Return values
none

Definition at line 332 of file gd32f10x_exmc.c.

333 {
334 EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_NDBKEN;
335 }
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
EXMC_NPCTL_NDBKEN
#define EXMC_NPCTL_NDBKEN
Definition: gd32f10x_exmc.h:96
void exmc_nand_ecc_config | ( | uint32_t | nand_bank,
 |  | ControlStatus | newvalue
 | ) |  |

enable or disable the EXMC NAND ECC function

Parameters
[in] nand_bank specifie the NAND bank
  • EXMC_BANKx_NAND(x=1,2)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 345 of file gd32f10x_exmc.c.

346 {
347 if (ENABLE == newvalue){
348 /* enable the selected NAND bank ECC function */
349 EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_ECCEN;
350 }else{
351 /* disable the selected NAND bank ECC function */
352 EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_ECCEN;
353 }
354 }
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
EXMC_NPCTL_ECCEN
#define EXMC_NPCTL_ECCEN
Definition: gd32f10x_exmc.h:99
void exmc_nand_enable ( uint32_t nand_bank )

enable NAND bank

Parameters
[in] nand_bank specifie the NAND bank
  • EXMC_BANKx_NAND(x=1,2)
[out] none
Return values
none

Definition at line 320 of file gd32f10x_exmc.c.

321 {
322 EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_NDBKEN;
323 }
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
EXMC_NPCTL_NDBKEN
#define EXMC_NPCTL_NDBKEN
Definition: gd32f10x_exmc.h:96
void exmc_nand_init ( exmc_nand_parameter_struct * exmc_nand_init_struct )

initialize EXMC NAND bank

Parameters
[in] | exmc_nand_parameter_struct | configure the EXMC NAND parameter nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 ecc_logic: ENABLE or DISABLE databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B wait_feature: ENABLE or DISABLE common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
[out] | none
Return values
none

Definition at line 259 of file gd32f10x_exmc.c.

260 {
261 uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U;
262
263 npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)|
264 EXMC_NPCTL_NDTP |
265 exmc_nand_init_struct->databus_width |
266 (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)|
267 exmc_nand_init_struct->ecc_size |
268 exmc_nand_init_struct->ctr_latency |
269 exmc_nand_init_struct->atr_latency;
270
271 npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) |
272 (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
273 ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
274 (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
275
276 npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
277 (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
278 ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) |
279 (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
280
281 /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */
282 EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl;
283 EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg;
284 EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg;
285 }
EXMC_NPATCFG_ATTHLD
#define EXMC_NPATCFG_ATTHLD
Definition: gd32f10x_exmc.h:122
EXMC_NPCTL_NDTP
#define EXMC_NPCTL_NDTP
Definition: gd32f10x_exmc.h:97
NPATCFG_ATTHLD_OFFSET
#define NPATCFG_ATTHLD_OFFSET
Definition: gd32f10x_exmc.c:59
exmc_nand_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:185
exmc_nand_pccard_timing_parameter_struct::waittime
uint32_t waittime
Definition: gd32f10x_exmc.h:173
EXMC_NPATCFG
#define EXMC_NPATCFG(bank)
Definition: gd32f10x_exmc.h:210
EXMC_NPCTCFG_COMSET
#define EXMC_NPCTCFG_COMSET
Definition: gd32f10x_exmc.h:114
exmc_nand_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:183
EXMC_NPATCFG_ATTWAIT
#define EXMC_NPATCFG_ATTWAIT
Definition: gd32f10x_exmc.h:121
NPCTCFG_COMWAIT_OFFSET
#define NPCTCFG_COMWAIT_OFFSET
Definition: gd32f10x_exmc.c:54
exmc_nand_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:187
EXMC_NPATCFG_ATTHIZ
#define EXMC_NPATCFG_ATTHIZ
Definition: gd32f10x_exmc.h:123
exmc_nand_pccard_timing_parameter_struct::databus_hiztime
uint32_t databus_hiztime
Definition: gd32f10x_exmc.h:171
NPATCFG_ATTWAIT_OFFSET
#define NPATCFG_ATTWAIT_OFFSET
Definition: gd32f10x_exmc.c:58
EXMC_NPCTCFG_COMWAIT
#define EXMC_NPCTCFG_COMWAIT
Definition: gd32f10x_exmc.h:115
EXMC_NPCTCFG_COMHLD
#define EXMC_NPCTCFG_COMHLD
Definition: gd32f10x_exmc.h:116
exmc_nand_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:188
exmc_nand_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:186
exmc_nand_parameter_struct::ecc_logic
uint32_t ecc_logic
Definition: gd32f10x_exmc.h:184
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
EXMC_NPCTCFG
#define EXMC_NPCTCFG(bank)
Definition: gd32f10x_exmc.h:209
NPCTCFG_COMHLD_OFFSET
#define NPCTCFG_COMHLD_OFFSET
Definition: gd32f10x_exmc.c:55
exmc_nand_parameter_struct::ecc_size
uint32_t ecc_size
Definition: gd32f10x_exmc.h:181
NPATCFG_ATTHIZ_OFFSET
#define NPATCFG_ATTHIZ_OFFSET
Definition: gd32f10x_exmc.c:60
EXMC_NPATCFG_ATTSET
#define EXMC_NPATCFG_ATTSET
Definition: gd32f10x_exmc.h:120
exmc_nand_parameter_struct::nand_bank
uint32_t nand_bank
Definition: gd32f10x_exmc.h:180
NPCTCFG_COMHIZ_OFFSET
#define NPCTCFG_COMHIZ_OFFSET
Definition: gd32f10x_exmc.c:56
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
EXMC_NPCTCFG_COMHIZ
#define EXMC_NPCTCFG_COMHIZ
Definition: gd32f10x_exmc.h:117
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
exmc_nand_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:182
NPCTL_ECCEN_OFFSET
#define NPCTL_ECCEN_OFFSET
Definition: gd32f10x_exmc.c:52
NPCTL_NDWTEN_OFFSET
#define NPCTL_NDWTEN_OFFSET
Definition: gd32f10x_exmc.c:51
void exmc_nand_parameter_init ( exmc_nand_parameter_struct * exmc_nand_init_struct )

initialize the struct exmc_norsram_parameter_struct

Parameters
[in] | none
[out] | the | initialized struct exmc_norsram_parameter_struct pointer
Return values
none

Definition at line 293 of file gd32f10x_exmc.c.

294 {
295 /* configure the structure with default value */
296 exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND;
297 exmc_nand_init_struct->wait_feature = DISABLE;
298 exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B;
299 exmc_nand_init_struct->ecc_logic = DISABLE;
300 exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES;
301 exmc_nand_init_struct->ctr_latency = 0x0U;
302 exmc_nand_init_struct->atr_latency = 0x0U;
303 exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU;
304 exmc_nand_init_struct->common_space_timing->waittime = 0xFCU;
305 exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU;
306 exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU;
307 exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU;
308 exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU;
309 exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU;
310 exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
311 }
exmc_nand_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:185
exmc_nand_pccard_timing_parameter_struct::waittime
uint32_t waittime
Definition: gd32f10x_exmc.h:173
exmc_nand_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:183
exmc_nand_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:187
exmc_nand_pccard_timing_parameter_struct::databus_hiztime
uint32_t databus_hiztime
Definition: gd32f10x_exmc.h:171
EXMC_BANK1_NAND
#define EXMC_BANK1_NAND
Definition: gd32f10x_exmc.h:348
exmc_nand_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:188
EXMC_NAND_DATABUS_WIDTH_8B
#define EXMC_NAND_DATABUS_WIDTH_8B
Definition: gd32f10x_exmc.h:326
exmc_nand_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:186
exmc_nand_parameter_struct::ecc_logic
uint32_t ecc_logic
Definition: gd32f10x_exmc.h:184
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
exmc_nand_parameter_struct::ecc_size
uint32_t ecc_size
Definition: gd32f10x_exmc.h:181
exmc_nand_parameter_struct::nand_bank
uint32_t nand_bank
Definition: gd32f10x_exmc.h:180
EXMC_ECC_SIZE_256BYTES
#define EXMC_ECC_SIZE_256BYTES
Definition: gd32f10x_exmc.h:279
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
exmc_nand_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:182
void exmc_norsram_deinit ( uint32_t norsram_region )

deinitialize EXMC NOR/SRAM region

Parameters
[in] norsram_region select the region of bank0
  • EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
[out] none
Return values
none

Definition at line 75 of file gd32f10x_exmc.c.

76 {
77 /* reset the registers */
78 if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
79 EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
80 }else{
81 EXMC_SNCTL(norsram_region) = BANK0_SNCTL1_2_3_REGION_RESET;
82 }
83
84 EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET;
85 EXMC_SNWTCFG(norsram_region) = BANK0_SNWTCFG_RESET;
86 }
EXMC_SNWTCFG
#define EXMC_SNWTCFG(region)
Definition: gd32f10x_exmc.h:205
BANK0_SNCTL0_REGION_RESET
#define BANK0_SNCTL0_REGION_RESET
Definition: gd32f10x_exmc.c:16
EXMC_SNCTL
#define EXMC_SNCTL(region)
Definition: gd32f10x_exmc.h:203
BANK0_SNCTL1_2_3_REGION_RESET
#define BANK0_SNCTL1_2_3_REGION_RESET
Definition: gd32f10x_exmc.c:17
EXMC_SNTCFG
#define EXMC_SNTCFG(region)
Definition: gd32f10x_exmc.h:204
BANK0_SNWTCFG_RESET
#define BANK0_SNWTCFG_RESET
Definition: gd32f10x_exmc.c:19
BANK0_SNTCFG_RESET
#define BANK0_SNTCFG_RESET
Definition: gd32f10x_exmc.c:18
EXMC_BANK0_NORSRAM_REGION0
#define EXMC_BANK0_NORSRAM_REGION0
Definition: gd32f10x_exmc.h:330
void exmc_norsram_disable ( uint32_t norsram_region )

disable EXMC NOR/PSRAM bank region

Parameters
[in] norsram_region specifie the region of NOR/PSRAM Bank
  • EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
[out] none
Return values
none

Definition at line 223 of file gd32f10x_exmc.c.

224 {
225 EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
226 }
EXMC_SNCTL_NRBKEN
#define EXMC_SNCTL_NRBKEN
Definition: gd32f10x_exmc.h:61
EXMC_SNCTL
#define EXMC_SNCTL(region)
Definition: gd32f10x_exmc.h:203
void exmc_norsram_enable ( uint32_t norsram_region )

enable EXMC NOR/PSRAM bank region

Parameters
[in] norsram_region specifie the region of NOR/PSRAM bank
  • EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
[out] none
Return values
none

Definition at line 211 of file gd32f10x_exmc.c.

212 {
213 EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
214 }
EXMC_SNCTL_NRBKEN
#define EXMC_SNCTL_NRBKEN
Definition: gd32f10x_exmc.h:61
EXMC_SNCTL
#define EXMC_SNCTL(region)
Definition: gd32f10x_exmc.h:203
void exmc_norsram_init ( exmc_norsram_parameter_struct * exmc_norsram_init_struct )

initialize EXMC NOR/SRAM region

Parameters
[in] | exmc_norsram_parameter_struct | configure the EXMC NOR/SRAM parameter norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE extended_mode: ENABLE or DISABLE asyn_wait: ENABLE or DISABLE nwait_signal: ENABLE or DISABLE memory_write: ENABLE or DISABLE nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING wrap_burst_mode: ENABLE or DISABLE nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH burst_mode: ENABLE or DISABLE databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR address_data_mux: ENABLE or DISABLE read_write_timing: struct exmc_norsram_timing_parameter_struct set the time write_timing: struct exmc_norsram_timing_parameter_struct set the time
[out] | none
Return values
none

Definition at line 109 of file gd32f10x_exmc.c.

110 {
111 uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U;
112
113 /* get the register value */
114 snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
115
116 /* clear relative bits */
117 snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN |
118 EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN |
119 EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR |
120 EXMC_SNCTL_NRMUX ));
121
122 snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
123 exmc_norsram_init_struct->memory_type |
124 exmc_norsram_init_struct->databus_width |
125 (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) |
126 exmc_norsram_init_struct->nwait_polarity |
127 (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) |
128 exmc_norsram_init_struct->nwait_config |
129 (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
130 (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
131 (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) |
132 (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) |
133 exmc_norsram_init_struct->write_mode;
134
135 sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
136 (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
137 (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
138 (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )|
139 exmc_norsram_init_struct->read_write_timing->syn_clk_division |
140 exmc_norsram_init_struct->read_write_timing->syn_data_latency |
141 exmc_norsram_init_struct->read_write_timing->asyn_access_mode;
142
143 /* nor flash access enable */
144 if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
145 snctl |= (uint32_t)EXMC_SNCTL_NREN;
146 }
147
148 /* extended mode configure */
149 if(ENABLE == exmc_norsram_init_struct->extended_mode){
150 snwtcfg = (uint32_t)(((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) |
151 (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD)|
152 (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNWTCFG_WDSET) |
153 exmc_norsram_init_struct->write_timing->asyn_access_mode);
154 }else{
155 snwtcfg = BANK0_SNWTCFG_RESET;
156 }
157
158 /* configure the registers */
159 EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
160 EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
161 EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg;
162 }
exmc_norsram_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:160
exmc_norsram_parameter_struct::extended_mode
uint32_t extended_mode
Definition: gd32f10x_exmc.h:152
exmc_norsram_timing_parameter_struct::asyn_data_setuptime
uint32_t asyn_data_setuptime
Definition: gd32f10x_exmc.h:142
EXMC_SNCTL_ASYNCWAIT
#define EXMC_SNCTL_ASYNCWAIT
Definition: gd32f10x_exmc.h:73
EXMC_SNWTCFG
#define EXMC_SNWTCFG(region)
Definition: gd32f10x_exmc.h:205
EXMC_SNWTCFG_WAHLD
#define EXMC_SNWTCFG_WAHLD
Definition: gd32f10x_exmc.h:87
EXMC_SNCTL_NRWTEN
#define EXMC_SNCTL_NRWTEN
Definition: gd32f10x_exmc.h:71
exmc_norsram_parameter_struct::write_mode
uint32_t write_mode
Definition: gd32f10x_exmc.h:151
EXMC_SNCTL_SYNCWR
#define EXMC_SNCTL_SYNCWR
Definition: gd32f10x_exmc.h:74
SNCTL_EXMODEN_OFFSET
#define SNCTL_EXMODEN_OFFSET
Definition: gd32f10x_exmc.c:40
exmc_norsram_timing_parameter_struct::asyn_address_setuptime
uint32_t asyn_address_setuptime
Definition: gd32f10x_exmc.h:144
exmc_norsram_parameter_struct::norsram_region
uint32_t norsram_region
Definition: gd32f10x_exmc.h:150
EXMC_SNTCFG_AHLD
#define EXMC_SNTCFG_AHLD
Definition: gd32f10x_exmc.h:78
exmc_norsram_timing_parameter_struct::syn_clk_division
uint32_t syn_clk_division
Definition: gd32f10x_exmc.h:140
EXMC_SNCTL
#define EXMC_SNCTL(region)
Definition: gd32f10x_exmc.h:203
EXMC_SNCTL_NRW
#define EXMC_SNCTL_NRW
Definition: gd32f10x_exmc.h:64
SNCTL_NRWTEN_OFFSET
#define SNCTL_NRWTEN_OFFSET
Definition: gd32f10x_exmc.c:39
exmc_norsram_parameter_struct::nwait_config
uint32_t nwait_config
Definition: gd32f10x_exmc.h:156
exmc_norsram_parameter_struct::write_timing
exmc_norsram_timing_parameter_struct * write_timing
Definition: gd32f10x_exmc.h:165
exmc_norsram_timing_parameter_struct::asyn_access_mode
uint32_t asyn_access_mode
Definition: gd32f10x_exmc.h:138
EXMC_MEMORY_TYPE_NOR
#define EXMC_MEMORY_TYPE_NOR
Definition: gd32f10x_exmc.h:230
exmc_norsram_parameter_struct::read_write_timing
exmc_norsram_timing_parameter_struct * read_write_timing
Definition: gd32f10x_exmc.h:163
EXMC_SNTCFG
#define EXMC_SNTCFG(region)
Definition: gd32f10x_exmc.h:204
exmc_norsram_parameter_struct::burst_mode
uint32_t burst_mode
Definition: gd32f10x_exmc.h:159
EXMC_SNWTCFG_WDSET
#define EXMC_SNWTCFG_WDSET
Definition: gd32f10x_exmc.h:88
exmc_norsram_parameter_struct::memory_type
uint32_t memory_type
Definition: gd32f10x_exmc.h:161
SNCTL_WREN_OFFSET
#define SNCTL_WREN_OFFSET
Definition: gd32f10x_exmc.c:38
EXMC_SNCTL_SBRSTEN
#define EXMC_SNCTL_SBRSTEN
Definition: gd32f10x_exmc.h:66
exmc_norsram_parameter_struct::asyn_wait
uint32_t asyn_wait
Definition: gd32f10x_exmc.h:153
SNCTL_NRMUX_OFFSET
#define SNCTL_NRMUX_OFFSET
Definition: gd32f10x_exmc.c:35
BANK0_SNWTCFG_RESET
#define BANK0_SNWTCFG_RESET
Definition: gd32f10x_exmc.c:19
exmc_norsram_parameter_struct::nwait_polarity
uint32_t nwait_polarity
Definition: gd32f10x_exmc.h:158
EXMC_SNCTL_WRAPEN
#define EXMC_SNCTL_WRAPEN
Definition: gd32f10x_exmc.h:68
exmc_norsram_parameter_struct::nwait_signal
uint32_t nwait_signal
Definition: gd32f10x_exmc.h:154
SNCTL_SBRSTEN_OFFSET
#define SNCTL_SBRSTEN_OFFSET
Definition: gd32f10x_exmc.c:36
EXMC_SNCTL_EXMODEN
#define EXMC_SNCTL_EXMODEN
Definition: gd32f10x_exmc.h:72
EXMC_SNTCFG_BUSLAT
#define EXMC_SNTCFG_BUSLAT
Definition: gd32f10x_exmc.h:80
EXMC_SNWTCFG_WASET
#define EXMC_SNWTCFG_WASET
Definition: gd32f10x_exmc.h:86
SNTCFG_DSET_OFFSET
#define SNTCFG_DSET_OFFSET
Definition: gd32f10x_exmc.c:44
SNCTL_ASYNCWAIT_OFFSET
#define SNCTL_ASYNCWAIT_OFFSET
Definition: gd32f10x_exmc.c:41
SNCTL_WRAPEN_OFFSET
#define SNCTL_WRAPEN_OFFSET
Definition: gd32f10x_exmc.c:37
EXMC_SNCTL_WREN
#define EXMC_SNCTL_WREN
Definition: gd32f10x_exmc.h:70
EXMC_SNCTL_NRWTPOL
#define EXMC_SNCTL_NRWTPOL
Definition: gd32f10x_exmc.h:67
EXMC_SNCTL_NREN
#define EXMC_SNCTL_NREN
Definition: gd32f10x_exmc.h:65
EXMC_SNCTL_NRTP
#define EXMC_SNCTL_NRTP
Definition: gd32f10x_exmc.h:63
exmc_norsram_parameter_struct::wrap_burst_mode
uint32_t wrap_burst_mode
Definition: gd32f10x_exmc.h:157
exmc_norsram_parameter_struct::address_data_mux
uint32_t address_data_mux
Definition: gd32f10x_exmc.h:162
SNTCFG_AHLD_OFFSET
#define SNTCFG_AHLD_OFFSET
Definition: gd32f10x_exmc.c:43
SNTCFG_BUSLAT_OFFSET
#define SNTCFG_BUSLAT_OFFSET
Definition: gd32f10x_exmc.c:45
exmc_norsram_parameter_struct::memory_write
uint32_t memory_write
Definition: gd32f10x_exmc.h:155
exmc_norsram_timing_parameter_struct::asyn_address_holdtime
uint32_t asyn_address_holdtime
Definition: gd32f10x_exmc.h:143
EXMC_SNTCFG_DSET
#define EXMC_SNTCFG_DSET
Definition: gd32f10x_exmc.h:79
exmc_norsram_timing_parameter_struct::bus_latency
uint32_t bus_latency
Definition: gd32f10x_exmc.h:141
EXMC_SNTCFG_ASET
#define EXMC_SNTCFG_ASET
Definition: gd32f10x_exmc.h:77
EXMC_SNCTL_NRMUX
#define EXMC_SNCTL_NRMUX
Definition: gd32f10x_exmc.h:62
EXMC_SNCTL_NRWTCFG
#define EXMC_SNCTL_NRWTCFG
Definition: gd32f10x_exmc.h:69
exmc_norsram_timing_parameter_struct::syn_data_latency
uint32_t syn_data_latency
Definition: gd32f10x_exmc.h:139
void exmc_norsram_parameter_init ( exmc_norsram_parameter_struct * exmc_norsram_init_struct )

initialize the struct exmc_norsram_parameter_struct

Parameters
[in] | none
[out] | exmc_norsram_init_struct | the initialized struct exmc_norsram_parameter_struct pointer
Return values
none

Definition at line 170 of file gd32f10x_exmc.c.

171 {
172 /* configure the structure with default value */
173 exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
174 exmc_norsram_init_struct->address_data_mux = ENABLE;
175 exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
176 exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B;
177 exmc_norsram_init_struct->burst_mode = DISABLE;
178 exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
179 exmc_norsram_init_struct->wrap_burst_mode = DISABLE;
180 exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE;
181 exmc_norsram_init_struct->memory_write = ENABLE;
182 exmc_norsram_init_struct->nwait_signal = ENABLE;
183 exmc_norsram_init_struct->extended_mode = DISABLE;
184 exmc_norsram_init_struct->asyn_wait = DISABLE;
185 exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE;
186
187 /* read/write timing configure */
188 exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
189 exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
190 exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
191 exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
192 exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK;
193 exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK;
194 exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
195
196 /* write timing configure, when extended mode is used */
197 exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU;
198 exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU;
199 exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU;
200 exmc_norsram_init_struct->write_timing->bus_latency = 0xFU;
201 exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
202 }
EXMC_MEMORY_TYPE_SRAM
#define EXMC_MEMORY_TYPE_SRAM
Definition: gd32f10x_exmc.h:228
exmc_norsram_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:160
exmc_norsram_parameter_struct::extended_mode
uint32_t extended_mode
Definition: gd32f10x_exmc.h:152
exmc_norsram_timing_parameter_struct::asyn_data_setuptime
uint32_t asyn_data_setuptime
Definition: gd32f10x_exmc.h:142
exmc_norsram_parameter_struct::write_mode
uint32_t write_mode
Definition: gd32f10x_exmc.h:151
exmc_norsram_timing_parameter_struct::asyn_address_setuptime
uint32_t asyn_address_setuptime
Definition: gd32f10x_exmc.h:144
EXMC_ASYN_WRITE
#define EXMC_ASYN_WRITE
Definition: gd32f10x_exmc.h:336
exmc_norsram_parameter_struct::norsram_region
uint32_t norsram_region
Definition: gd32f10x_exmc.h:150
exmc_norsram_timing_parameter_struct::syn_clk_division
uint32_t syn_clk_division
Definition: gd32f10x_exmc.h:140
exmc_norsram_parameter_struct::nwait_config
uint32_t nwait_config
Definition: gd32f10x_exmc.h:156
exmc_norsram_parameter_struct::write_timing
exmc_norsram_timing_parameter_struct * write_timing
Definition: gd32f10x_exmc.h:165
exmc_norsram_timing_parameter_struct::asyn_access_mode
uint32_t asyn_access_mode
Definition: gd32f10x_exmc.h:138
exmc_norsram_parameter_struct::read_write_timing
exmc_norsram_timing_parameter_struct * read_write_timing
Definition: gd32f10x_exmc.h:163
exmc_norsram_parameter_struct::burst_mode
uint32_t burst_mode
Definition: gd32f10x_exmc.h:159
exmc_norsram_parameter_struct::memory_type
uint32_t memory_type
Definition: gd32f10x_exmc.h:161
exmc_norsram_parameter_struct::asyn_wait
uint32_t asyn_wait
Definition: gd32f10x_exmc.h:153
exmc_norsram_parameter_struct::nwait_polarity
uint32_t nwait_polarity
Definition: gd32f10x_exmc.h:158
EXMC_NWAIT_POLARITY_LOW
#define EXMC_NWAIT_POLARITY_LOW
Definition: gd32f10x_exmc.h:344
exmc_norsram_parameter_struct::nwait_signal
uint32_t nwait_signal
Definition: gd32f10x_exmc.h:154
EXMC_SYN_CLOCK_RATIO_16_CLK
#define EXMC_SYN_CLOCK_RATIO_16_CLK
Definition: gd32f10x_exmc.h:275
EXMC_ACCESS_MODE_A
#define EXMC_ACCESS_MODE_A
Definition: gd32f10x_exmc.h:234
EXMC_BANK0_NORSRAM_REGION0
#define EXMC_BANK0_NORSRAM_REGION0
Definition: gd32f10x_exmc.h:330
exmc_norsram_parameter_struct::wrap_burst_mode
uint32_t wrap_burst_mode
Definition: gd32f10x_exmc.h:157
exmc_norsram_parameter_struct::address_data_mux
uint32_t address_data_mux
Definition: gd32f10x_exmc.h:162
exmc_norsram_parameter_struct::memory_write
uint32_t memory_write
Definition: gd32f10x_exmc.h:155
EXMC_DATALAT_17_CLK
#define EXMC_DATALAT_17_CLK
Definition: gd32f10x_exmc.h:256
exmc_norsram_timing_parameter_struct::asyn_address_holdtime
uint32_t asyn_address_holdtime
Definition: gd32f10x_exmc.h:143
EXMC_NWAIT_CONFIG_BEFORE
#define EXMC_NWAIT_CONFIG_BEFORE
Definition: gd32f10x_exmc.h:340
exmc_norsram_timing_parameter_struct::bus_latency
uint32_t bus_latency
Definition: gd32f10x_exmc.h:141
EXMC_NOR_DATABUS_WIDTH_8B
#define EXMC_NOR_DATABUS_WIDTH_8B
Definition: gd32f10x_exmc.h:223
exmc_norsram_timing_parameter_struct::syn_data_latency
uint32_t syn_data_latency
Definition: gd32f10x_exmc.h:139
void exmc_pccard_deinit ( void )

deinitialize EXMC PC card bank

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 374 of file gd32f10x_exmc.c.

375 {
376 /* EXMC_BANK3_PCCARD */
377 EXMC_NPCTL3 = BANK3_NPCTL_RESET;
378 EXMC_NPINTEN3 = BANK3_NPINTEN_RESET;
379 EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET;
380 EXMC_NPATCFG3 = BANK3_NPATCFG_RESET;
381 EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET;
382 }
EXMC_NPATCFG3
#define EXMC_NPATCFG3
Definition: gd32f10x_exmc.h:55
EXMC_NPINTEN3
#define EXMC_NPINTEN3
Definition: gd32f10x_exmc.h:53
BANK3_PIOTCFG3_RESET
#define BANK3_PIOTCFG3_RESET
Definition: gd32f10x_exmc.c:32
BANK3_NPATCFG_RESET
#define BANK3_NPATCFG_RESET
Definition: gd32f10x_exmc.c:31
BANK3_NPINTEN_RESET
#define BANK3_NPINTEN_RESET
Definition: gd32f10x_exmc.c:29
EXMC_PIOTCFG3
#define EXMC_PIOTCFG3
Definition: gd32f10x_exmc.h:56
BANK3_NPCTCFG_RESET
#define BANK3_NPCTCFG_RESET
Definition: gd32f10x_exmc.c:30
EXMC_NPCTL3
#define EXMC_NPCTL3
Definition: gd32f10x_exmc.h:52
BANK3_NPCTL_RESET
#define BANK3_NPCTL_RESET
Definition: gd32f10x_exmc.c:28
EXMC_NPCTCFG3
#define EXMC_NPCTCFG3
Definition: gd32f10x_exmc.h:54
void exmc_pccard_disable ( void )

disable PC Card Bank

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 466 of file gd32f10x_exmc.c.

467 {
468 EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN;
469 }
EXMC_NPCTL3
#define EXMC_NPCTL3
Definition: gd32f10x_exmc.h:52
EXMC_NPCTL_NDBKEN
#define EXMC_NPCTL_NDBKEN
Definition: gd32f10x_exmc.h:96
void exmc_pccard_enable ( void )

enable PC Card Bank

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 455 of file gd32f10x_exmc.c.

456 {
457 EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN;
458 }
EXMC_NPCTL3
#define EXMC_NPCTL3
Definition: gd32f10x_exmc.h:52
EXMC_NPCTL_NDBKEN
#define EXMC_NPCTL_NDBKEN
Definition: gd32f10x_exmc.h:96
void exmc_pccard_init ( exmc_pccard_parameter_struct * exmc_pccard_init_struct )

initialize EXMC PC card bank

Parameters
[in] | exmc_pccard_parameter_struct | configure the EXMC NAND parameter atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 wait_feature: ENABLE or DISABLE common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time
[out] | none
Return values
none

Definition at line 396 of file gd32f10x_exmc.c.

397 {
398 /* configure the EXMC bank3 PC card control register */
399 EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) |
400 EXMC_NAND_DATABUS_WIDTH_16B |
401 exmc_pccard_init_struct->ctr_latency |
402 exmc_pccard_init_struct->atr_latency ;
403
404 /* configure the EXMC bank3 PC card common space timing configuration register */
405 EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) |
406 (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
407 ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
408 (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
409
410 /* configure the EXMC bank3 PC card attribute space timing configuration register */
411 EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
412 (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
413 ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )|
414 (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
415
416 /* configure the EXMC bank3 PC card io space timing configuration register */
417 EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) |
418 (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) |
419 ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )|
420 ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ );
421 }
EXMC_NPATCFG_ATTHLD
#define EXMC_NPATCFG_ATTHLD
Definition: gd32f10x_exmc.h:122
EXMC_NPATCFG3
#define EXMC_NPATCFG3
Definition: gd32f10x_exmc.h:55
exmc_pccard_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:195
NPATCFG_ATTHLD_OFFSET
#define NPATCFG_ATTHLD_OFFSET
Definition: gd32f10x_exmc.c:59
exmc_nand_pccard_timing_parameter_struct::waittime
uint32_t waittime
Definition: gd32f10x_exmc.h:173
EXMC_PIOTCFG3_IOSET
#define EXMC_PIOTCFG3_IOSET
Definition: gd32f10x_exmc.h:126
EXMC_NPCTCFG_COMSET
#define EXMC_NPCTCFG_COMSET
Definition: gd32f10x_exmc.h:114
EXMC_NPATCFG_ATTWAIT
#define EXMC_NPATCFG_ATTWAIT
Definition: gd32f10x_exmc.h:121
NPCTCFG_COMWAIT_OFFSET
#define NPCTCFG_COMWAIT_OFFSET
Definition: gd32f10x_exmc.c:54
EXMC_PIOTCFG3_IOHIZ
#define EXMC_PIOTCFG3_IOHIZ
Definition: gd32f10x_exmc.h:129
EXMC_NPATCFG_ATTHIZ
#define EXMC_NPATCFG_ATTHIZ
Definition: gd32f10x_exmc.h:123
EXMC_PIOTCFG3
#define EXMC_PIOTCFG3
Definition: gd32f10x_exmc.h:56
PIOTCFG_IOHIZ_OFFSET
#define PIOTCFG_IOHIZ_OFFSET
Definition: gd32f10x_exmc.c:64
exmc_nand_pccard_timing_parameter_struct::databus_hiztime
uint32_t databus_hiztime
Definition: gd32f10x_exmc.h:171
NPATCFG_ATTWAIT_OFFSET
#define NPATCFG_ATTWAIT_OFFSET
Definition: gd32f10x_exmc.c:58
EXMC_NPCTL3
#define EXMC_NPCTL3
Definition: gd32f10x_exmc.h:52
EXMC_NPCTCFG_COMWAIT
#define EXMC_NPCTCFG_COMWAIT
Definition: gd32f10x_exmc.h:115
EXMC_NPCTCFG_COMHLD
#define EXMC_NPCTCFG_COMHLD
Definition: gd32f10x_exmc.h:116
exmc_pccard_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:196
exmc_pccard_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:194
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
EXMC_PIOTCFG3_IOHLD
#define EXMC_PIOTCFG3_IOHLD
Definition: gd32f10x_exmc.h:128
exmc_pccard_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:197
EXMC_NPCTCFG3
#define EXMC_NPCTCFG3
Definition: gd32f10x_exmc.h:54
NPCTCFG_COMHLD_OFFSET
#define NPCTCFG_COMHLD_OFFSET
Definition: gd32f10x_exmc.c:55
exmc_pccard_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:198
NPATCFG_ATTHIZ_OFFSET
#define NPATCFG_ATTHIZ_OFFSET
Definition: gd32f10x_exmc.c:60
EXMC_NPATCFG_ATTSET
#define EXMC_NPATCFG_ATTSET
Definition: gd32f10x_exmc.h:120
PIOTCFG_IOWAIT_OFFSET
#define PIOTCFG_IOWAIT_OFFSET
Definition: gd32f10x_exmc.c:62
exmc_pccard_parameter_struct::io_space_timing
exmc_nand_pccard_timing_parameter_struct * io_space_timing
Definition: gd32f10x_exmc.h:199
PIOTCFG_IOHLD_OFFSET
#define PIOTCFG_IOHLD_OFFSET
Definition: gd32f10x_exmc.c:63
NPCTCFG_COMHIZ_OFFSET
#define NPCTCFG_COMHIZ_OFFSET
Definition: gd32f10x_exmc.c:56
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
EXMC_NPCTCFG_COMHIZ
#define EXMC_NPCTCFG_COMHIZ
Definition: gd32f10x_exmc.h:117
EXMC_PIOTCFG3_IOWAIT
#define EXMC_PIOTCFG3_IOWAIT
Definition: gd32f10x_exmc.h:127
EXMC_NAND_DATABUS_WIDTH_16B
#define EXMC_NAND_DATABUS_WIDTH_16B
Definition: gd32f10x_exmc.h:327
NPCTL_NDWTEN_OFFSET
#define NPCTL_NDWTEN_OFFSET
Definition: gd32f10x_exmc.c:51
void exmc_pccard_parameter_init ( exmc_pccard_parameter_struct * exmc_pccard_init_struct )

initialize the struct exmc_pccard_parameter_struct

Parameters
[in] | none
[out] | the | initialized struct exmc_pccard_parameter_struct pointer
Return values
none

Definition at line 429 of file gd32f10x_exmc.c.

430 {
431 /* configure the structure with default value */
432 exmc_pccard_init_struct->wait_feature = DISABLE;
433 exmc_pccard_init_struct->ctr_latency = 0x0U;
434 exmc_pccard_init_struct->atr_latency = 0x0U;
435 exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU;
436 exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU;
437 exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU;
438 exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU;
439 exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU;
440 exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU;
441 exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU;
442 exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
443 exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU;
444 exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU;
445 exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU;
446 exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU;
447 }
exmc_pccard_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:195
exmc_nand_pccard_timing_parameter_struct::waittime
uint32_t waittime
Definition: gd32f10x_exmc.h:173
exmc_nand_pccard_timing_parameter_struct::databus_hiztime
uint32_t databus_hiztime
Definition: gd32f10x_exmc.h:171
exmc_pccard_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:196
exmc_pccard_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:194
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
exmc_pccard_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:197
exmc_pccard_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:198
exmc_pccard_parameter_struct::io_space_timing
exmc_nand_pccard_timing_parameter_struct * io_space_timing
Definition: gd32f10x_exmc.h:199
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_exti.c File Reference

EXTI driver. More...

#include "gd32f10x_exti.h"

Go to the source code of this file.

Functions

void | exti_deinit (void)
deinitialize the EXTI More...
void | exti_init (exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
initialize the EXTI More...
void | exti_interrupt_enable (exti_line_enum linex)
enable the interrupts from EXTI line x More...
void | exti_event_enable (exti_line_enum linex)
enable the events from EXTI line x More...
void | exti_interrupt_disable (exti_line_enum linex)
disable the interrupt from EXTI line x More...
void | exti_event_disable (exti_line_enum linex)
disable the events from EXTI line x More...
FlagStatus | exti_flag_get (exti_line_enum linex)
get EXTI lines flag More...
void | exti_flag_clear (exti_line_enum linex)
clear EXTI lines pending flag More...
FlagStatus | exti_interrupt_flag_get (exti_line_enum linex)
get EXTI lines flag when the interrupt flag is set More...
void | exti_interrupt_flag_clear (exti_line_enum linex)
clear EXTI lines pending flag More...
void | exti_software_interrupt_enable (exti_line_enum linex)
enable EXTI software interrupt event More...
void | exti_software_interrupt_disable (exti_line_enum linex)
disable EXTI software interrupt event More...

Detailed Description

EXTI driver.

Definition in file gd32f10x_exti.c.

Function Documentation

void exti_deinit ( void )

deinitialize the EXTI

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_exti.c.

22 {
23 /* reset the value of all the EXTI registers */
24 EXTI_INTEN = (uint32_t)0x00000000U;
25 EXTI_EVEN = (uint32_t)0x00000000U;
26 EXTI_RTEN = (uint32_t)0x00000000U;
27 EXTI_FTEN = (uint32_t)0x00000000U;
28 EXTI_SWIEV = (uint32_t)0x00000000U;
29 }
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f10x_exti.h:25
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f10x_exti.h:23
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f10x_exti.h:26
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f10x_exti.h:24
void exti_event_disable ( exti_line_enum linex )

disable the events from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 134 of file gd32f10x_exti.c.

135 {
136 EXTI_EVEN &= ~(uint32_t)linex;
137 }
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f10x_exti.h:23
void exti_event_enable ( exti_line_enum linex )

enable the events from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 108 of file gd32f10x_exti.c.

109 {
110 EXTI_EVEN |= (uint32_t)linex;
111 }
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f10x_exti.h:23
void exti_flag_clear ( exti_line_enum linex )

clear EXTI lines pending flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 164 of file gd32f10x_exti.c.

165 {
166 EXTI_PD = (uint32_t)linex;
167 }
EXTI_PD
#define EXTI_PD
Definition: gd32f10x_exti.h:27
FlagStatus exti_flag_get ( exti_line_enum linex )

get EXTI lines flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
FlagStatus status of flag (RESET or SET)

Definition at line 147 of file gd32f10x_exti.c.

148 {
149 if(RESET != (EXTI_PD & (uint32_t)linex)){
150 return SET;
151 }else{
152 return RESET;
153 }
154 }
EXTI_PD
#define EXTI_PD
Definition: gd32f10x_exti.h:27
void exti_init | ( | exti_line_enum | linex,
 |  | exti_mode_enum | mode,
 |  | exti_trig_type_enum | trig_type
 | ) |  |

initialize the EXTI

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[in] mode interrupt or event mode, refer to exti_mode_enum only one parameter can be selected which is shown as below:
  • EXTI_INTERRUPT: interrupt mode
  • EXTI_EVENT: event mode
[in] trig_type interrupt trigger type, refer to exti_trig_type_enum only one parameter can be selected which is shown as below:
  • EXTI_TRIG_RISING: rising edge trigger
  • EXTI_TRIG_FALLING: falling trigger
  • EXTI_TRIG_BOTH: rising and falling trigger
[out] none
Return values
none

Definition at line 48 of file gd32f10x_exti.c.

49 {
50 /* reset the EXTI line x */
51 EXTI_INTEN &= ~(uint32_t)linex;
52 EXTI_EVEN &= ~(uint32_t)linex;
53 EXTI_RTEN &= ~(uint32_t)linex;
54 EXTI_FTEN &= ~(uint32_t)linex;
55
56 /* set the EXTI mode and enable the interrupts or events from EXTI line x */
57 switch(mode){
58 case EXTI_INTERRUPT:
59 EXTI_INTEN |= (uint32_t)linex;
60 break;
61 case EXTI_EVENT:
62 EXTI_EVEN |= (uint32_t)linex;
63 break;
64 default:
65 break;
66 }
67
68 /* set the EXTI trigger type */
69 switch(trig_type){
70 case EXTI_TRIG_RISING:
71 EXTI_RTEN |= (uint32_t)linex;
72 EXTI_FTEN &= ~(uint32_t)linex;
73 break;
74 case EXTI_TRIG_FALLING:
75 EXTI_RTEN &= ~(uint32_t)linex;
76 EXTI_FTEN |= (uint32_t)linex;
77 break;
78 case EXTI_TRIG_BOTH:
79 EXTI_RTEN |= (uint32_t)linex;
80 EXTI_FTEN |= (uint32_t)linex;
81 break;
82 default:
83 break;
84 }
85 }
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f10x_exti.h:25
EXTI_INTERRUPT
Definition: gd32f10x_exti.h:191
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
EXTI_TRIG_FALLING
Definition: gd32f10x_exti.h:199
EXTI_TRIG_BOTH
Definition: gd32f10x_exti.h:200
EXTI_TRIG_RISING
Definition: gd32f10x_exti.h:198
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f10x_exti.h:23
EXTI_EVENT
Definition: gd32f10x_exti.h:192
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f10x_exti.h:24
void exti_interrupt_disable ( exti_line_enum linex )

disable the interrupt from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 121 of file gd32f10x_exti.c.

122 {
123 EXTI_INTEN &= ~(uint32_t)linex;
124 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
void exti_interrupt_enable ( exti_line_enum linex )

enable the interrupts from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 95 of file gd32f10x_exti.c.

96 {
97 EXTI_INTEN |= (uint32_t)linex;
98 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
void exti_interrupt_flag_clear ( exti_line_enum linex )

clear EXTI lines pending flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 199 of file gd32f10x_exti.c.

200 {
201 EXTI_PD = (uint32_t)linex;
202 }
EXTI_PD
#define EXTI_PD
Definition: gd32f10x_exti.h:27
FlagStatus exti_interrupt_flag_get ( exti_line_enum linex )

get EXTI lines flag when the interrupt flag is set

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
FlagStatus status of flag (RESET or SET)

Definition at line 177 of file gd32f10x_exti.c.

178 {
179 uint32_t flag_left, flag_right;
180
181 flag_left = EXTI_PD & (uint32_t)linex;
182 flag_right = EXTI_INTEN & (uint32_t)linex;
183
184 if((RESET != flag_left) && (RESET != flag_right)){
185 return SET;
186 }else{
187 return RESET;
188 }
189 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
EXTI_PD
#define EXTI_PD
Definition: gd32f10x_exti.h:27
void exti_software_interrupt_disable ( exti_line_enum linex )

disable EXTI software interrupt event

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 225 of file gd32f10x_exti.c.

226 {
227 EXTI_SWIEV &= ~(uint32_t)linex;
228 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f10x_exti.h:26
void exti_software_interrupt_enable ( exti_line_enum linex )

enable EXTI software interrupt event

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19): EXTI line x
[out] none
Return values
none

Definition at line 212 of file gd32f10x_exti.c.

213 {
214 EXTI_SWIEV |= (uint32_t)linex;
215 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f10x_exti.h:26
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_fmc.c File Reference

FMC driver. More...

#include "gd32f10x_fmc.h"

Go to the source code of this file.

Functions

void | fmc_wscnt_set (uint32_t wscnt)
set the wait state counter value More...
void | fmc_unlock (void)
unlock the main FMC operation More...
void | fmc_bank0_unlock (void)
unlock the FMC bank0 operation this function can be used for all GD32F10x devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. More...
void | fmc_bank1_unlock (void)
unlock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. More...
void | fmc_lock (void)
lock the main FMC operation More...
void | fmc_bank0_lock (void)
lock the FMC bank0 operation this function can be used for all GD32F10X devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. More...
void | fmc_bank1_lock (void)
lock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. More...
fmc_state_enum | fmc_page_erase (uint32_t page_address)
erase page More...
fmc_state_enum | fmc_mass_erase (void)
erase whole chip More...
fmc_state_enum | fmc_bank0_erase (void)
erase bank0 More...
fmc_state_enum | fmc_bank1_erase (void)
erase bank1 More...
fmc_state_enum | fmc_word_program (uint32_t address, uint32_t data)
program a word at the corresponding address More...
fmc_state_enum | fmc_halfword_program (uint32_t address, uint16_t data)
program a half word at the corresponding address More...
void | ob_unlock (void)
unlock the option byte operation More...
void | ob_lock (void)
lock the option byte operation More...
fmc_state_enum | ob_erase (void)
erase the FMC option byte unlock the FMC_CTL0 and option byte before calling this function More...
fmc_state_enum | ob_write_protection_enable (uint32_t ob_wp)
enable write protection More...
fmc_state_enum | ob_security_protection_config (uint8_t ob_spc)
configure security protection More...
fmc_state_enum | ob_user_write (uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot)
program the FMC user option byte More...
fmc_state_enum | ob_data_program (uint32_t address, uint8_t data)
program option bytes data More...
uint8_t | ob_user_get (void)
get the FMC user option byte More...
uint16_t | ob_data_get (void)
get OB_DATA in register FMC_OBSTAT More...
uint32_t | ob_write_protection_get (void)
get the FMC option byte write protection More...
FlagStatus | ob_spc_get (void)
get the FMC option byte security protection More...
void | fmc_interrupt_enable (uint32_t interrupt)
enable FMC interrupt More...
void | fmc_interrupt_disable (uint32_t interrupt)
disable FMC interrupt More...
FlagStatus | fmc_flag_get (uint32_t flag)
check flag is set or not More...
void | fmc_flag_clear (uint32_t flag)
clear the FMC flag More...
FlagStatus | fmc_interrupt_flag_get (fmc_interrupt_flag_enum flag)
get FMC interrupt flag state More...
void | fmc_interrupt_flag_clear (fmc_interrupt_flag_enum flag)
clear FMC interrupt flag state More...
fmc_state_enum | fmc_bank0_state_get (void)
get the FMC bank0 state More...
fmc_state_enum | fmc_bank1_state_get (void)
get the FMC bank1 state More...
fmc_state_enum | fmc_bank0_ready_wait (uint32_t timeout)
check whether FMC bank0 is ready or not More...
fmc_state_enum | fmc_bank1_ready_wait (uint32_t timeout)
check whether FMC bank1 is ready or not More...

Detailed Description

FMC driver.

Definition in file gd32f10x_fmc.c.

Function Documentation

fmc_state_enum fmc_bank0_erase ( void )

erase bank0

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 246 of file gd32f10x_fmc.c.

247 {
248 fmc_state_enum fmc_state = FMC_READY;
249 /* wait for the FMC ready */
250 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
251
252 if(FMC_READY == fmc_state){
253 /* start FMC bank0 erase */
254 FMC_CTL0 |= FMC_CTL0_MER;
255 FMC_CTL0 |= FMC_CTL0_START;
256 /* wait for the FMC ready */
257 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
258 /* reset the MER bit */
259 FMC_CTL0 &= ~FMC_CTL0_MER;
260 }
261 /* return the fmc state */
262 return fmc_state;
263 }
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_CTL0_MER
#define FMC_CTL0_MER
Definition: gd32f10x_fmc.h:64
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_bank0_lock ( void )

lock the FMC bank0 operation this function can be used for all GD32F10X devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 116 of file gd32f10x_fmc.c.

117 {
118 /* set the LK bit*/
119 FMC_CTL0 |= FMC_CTL0_LK;
120 }
FMC_CTL0_LK
#define FMC_CTL0_LK
Definition: gd32f10x_fmc.h:68
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum fmc_bank0_ready_wait ( uint32_t timeout )

check whether FMC bank0 is ready or not

Parameters
[in] | timeout | count of loop
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 892 of file gd32f10x_fmc.c.

893 {
894 fmc_state_enum fmc_state = FMC_BUSY;
895
896 /* wait for FMC ready */
897 do{
898 /* get FMC state */
899 fmc_state = fmc_bank0_state_get();
900 timeout--;
901 }while((FMC_BUSY == fmc_state) && (0x00U != timeout));
902
903 if(FMC_BUSY == fmc_state){
904 fmc_state = FMC_TOERR;
905 }
906 /* return the FMC state */
907 return fmc_state;
908 }
FMC_BUSY
Definition: gd32f10x_fmc.h:134
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_bank0_state_get
fmc_state_enum fmc_bank0_state_get(void)
get the FMC bank0 state
Definition: gd32f10x_fmc.c:841
fmc_state_enum fmc_bank0_state_get ( void )

get the FMC bank0 state

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 841 of file gd32f10x_fmc.c.

842 {
843 fmc_state_enum fmc_state = FMC_READY;
844
845 if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){
846 fmc_state = FMC_BUSY;
847 }else{
848 if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){
849 fmc_state = FMC_WPERR;
850 }else{
851 if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){
852 fmc_state = FMC_PGERR;
853 }
854 }
855 }
856 /* return the FMC state */
857 return fmc_state;
858 }
FMC_BUSY
Definition: gd32f10x_fmc.h:134
FMC_WPERR
Definition: gd32f10x_fmc.h:136
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_STAT0_WPERR
#define FMC_STAT0_WPERR
Definition: gd32f10x_fmc.h:58
FMC_STAT0
#define FMC_STAT0
Definition: gd32f10x_fmc.h:26
FMC_STAT0_PGERR
#define FMC_STAT0_PGERR
Definition: gd32f10x_fmc.h:57
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_STAT0_BUSY
#define FMC_STAT0_BUSY
Definition: gd32f10x_fmc.h:56
FMC_PGERR
Definition: gd32f10x_fmc.h:135
void fmc_bank0_unlock ( void )

unlock the FMC bank0 operation this function can be used for all GD32F10x devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 65 of file gd32f10x_fmc.c.

66 {
67 if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
68 /* write the FMC unlock key */
69 FMC_KEY0 = UNLOCK_KEY0;
70 FMC_KEY0 = UNLOCK_KEY1;
71 }
72 }
FMC_CTL0_LK
#define FMC_CTL0_LK
Definition: gd32f10x_fmc.h:68
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f10x_fmc.h:175
FMC_KEY0
#define FMC_KEY0
Definition: gd32f10x_fmc.h:24
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f10x_fmc.h:176
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum fmc_bank1_erase ( void )

erase bank1

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 271 of file gd32f10x_fmc.c.

272 {
273 fmc_state_enum fmc_state = FMC_READY;
274 /* wait for the FMC ready */
275 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
276
277 if(FMC_READY == fmc_state){
278 /* start FMC bank1 erase */
279 FMC_CTL1 |= FMC_CTL1_MER;
280 FMC_CTL1 |= FMC_CTL1_START;
281 /* wait for the FMC ready */
282 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
283 /* reset the MER bit */
284 FMC_CTL1 &= ~FMC_CTL1_MER;
285 }
286 /* return the fmc state */
287 return fmc_state;
288 }
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_CTL1_START
#define FMC_CTL1_START
Definition: gd32f10x_fmc.h:98
FMC_CTL1_MER
#define FMC_CTL1_MER
Definition: gd32f10x_fmc.h:97
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_READY
Definition: gd32f10x_fmc.h:133
void fmc_bank1_lock ( void )

lock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 129 of file gd32f10x_fmc.c.

130 {
131 /* set the LK bit*/
132 FMC_CTL1 |= FMC_CTL1_LK;
133 }
FMC_CTL1_LK
#define FMC_CTL1_LK
Definition: gd32f10x_fmc.h:99
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
fmc_state_enum fmc_bank1_ready_wait ( uint32_t timeout )

check whether FMC bank1 is ready or not

Parameters
[in] | timeout | count of loop
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 916 of file gd32f10x_fmc.c.

917 {
918 fmc_state_enum fmc_state = FMC_BUSY;
919
920 /* wait for FMC ready */
921 do{
922 /* get FMC state */
923 fmc_state = fmc_bank1_state_get();
924 timeout--;
925 }while((FMC_BUSY == fmc_state) && (0x00U != timeout));
926
927 if(FMC_BUSY == fmc_state){
928 fmc_state = FMC_TOERR;
929 }
930 /* return the FMC state */
931 return fmc_state;
932 }
fmc_bank1_state_get
fmc_state_enum fmc_bank1_state_get(void)
get the FMC bank1 state
Definition: gd32f10x_fmc.c:866
FMC_BUSY
Definition: gd32f10x_fmc.h:134
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_state_enum fmc_bank1_state_get ( void )

get the FMC bank1 state

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 866 of file gd32f10x_fmc.c.

867 {
868 fmc_state_enum fmc_state = FMC_READY;
869
870 if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){
871 fmc_state = FMC_BUSY;
872 }else{
873 if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){
874 fmc_state = FMC_WPERR;
875 }else{
876 if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){
877 fmc_state = FMC_PGERR;
878 }
879 }
880 }
881
882 /* return the FMC state */
883 return fmc_state;
884 }
FMC_BUSY
Definition: gd32f10x_fmc.h:134
FMC_WPERR
Definition: gd32f10x_fmc.h:136
FMC_STAT1
#define FMC_STAT1
Definition: gd32f10x_fmc.h:32
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_STAT1_WPERR
#define FMC_STAT1_WPERR
Definition: gd32f10x_fmc.h:91
FMC_STAT1_BUSY
#define FMC_STAT1_BUSY
Definition: gd32f10x_fmc.h:89
FMC_STAT1_PGERR
#define FMC_STAT1_PGERR
Definition: gd32f10x_fmc.h:90
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_PGERR
Definition: gd32f10x_fmc.h:135
void fmc_bank1_unlock ( void )

unlock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 81 of file gd32f10x_fmc.c.

82 {
83 if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){
84 /* write the FMC unlock key */
85 FMC_KEY1 = UNLOCK_KEY0;
86 FMC_KEY1 = UNLOCK_KEY1;
87 }
88 }
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f10x_fmc.h:175
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f10x_fmc.h:176
FMC_CTL1_LK
#define FMC_CTL1_LK
Definition: gd32f10x_fmc.h:99
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_KEY1
#define FMC_KEY1
Definition: gd32f10x_fmc.h:31
void fmc_flag_clear ( uint32_t flag )

clear the FMC flag

Parameters
[in] flag clear FMC flag only one parameter can be selected which is shown as below:
  • FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit
  • FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit
  • FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit
  • FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit
  • FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit
  • FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit
[out] none
Return values
none

Definition at line 775 of file gd32f10x_fmc.c.

776 {
777 FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag));
778 }
FMC_REG_VAL
#define FMC_REG_VAL(offset)
Definition: gd32f10x_fmc.h:115
FMC_BIT_POS
#define FMC_BIT_POS(val)
Definition: gd32f10x_fmc.h:116
FlagStatus fmc_flag_get ( uint32_t flag )

check flag is set or not

Parameters
[in] flag check FMC flag only one parameter can be selected which is shown as below:
  • FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit
  • FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit
  • FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit
  • FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit
  • FMC_FLAG_OBERR: FMC option bytes read error flag bit
  • FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit
  • FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit
  • FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit
  • FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit
[out] none
Return values
FlagStatus SET or RESET

Definition at line 753 of file gd32f10x_fmc.c.

754 {
755 if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){
756 return SET;
757 }else{
758 return RESET;
759 }
760 }
FMC_REG_VAL
#define FMC_REG_VAL(offset)
Definition: gd32f10x_fmc.h:115
FMC_BIT_POS
#define FMC_BIT_POS(val)
Definition: gd32f10x_fmc.h:116
fmc_state_enum fmc_halfword_program | ( | uint32_t | address,
 |  | uint16_t | data
 | ) |  |

program a half word at the corresponding address

Parameters
[in] | address | address to program
[in] | data | halfword to program
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 350 of file gd32f10x_fmc.c.

351 {
352 fmc_state_enum fmc_state = FMC_READY;
353 if(FMC_BANK0_SIZE > FMC_SIZE){
354 if(FMC_BANK0_END_ADDRESS > address){
355 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
356
357 if(FMC_READY == fmc_state){
358 /* set the PG bit to start program */
359 FMC_CTL0 |= FMC_CTL0_PG;
360 REG16(address) = data;
361 /* wait for the FMC ready */
362 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
363 /* reset the PG bit */
364 FMC_CTL0 &= ~FMC_CTL0_PG;
365 }
366 }else{
367 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
368
369 if(FMC_READY == fmc_state){
370 /* set the PG bit to start program */
371 FMC_CTL1 |= FMC_CTL1_PG;
372 REG16(address) = data;
373 /* wait for the FMC ready */
374 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
375 /* reset the PG bit */
376 FMC_CTL1 &= ~FMC_CTL1_PG;
377 }
378 }
379 }else{
380 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
381
382 if(FMC_READY == fmc_state){
383 /* set the PG bit to start program */
384 FMC_CTL0 |= FMC_CTL0_PG;
385 REG16(address) = data;
386 /* wait for the FMC ready */
387 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
388 /* reset the PG bit */
389 FMC_CTL0 &= ~FMC_CTL0_PG;
390 }
391 }
392 /* return the FMC state */
393 return fmc_state;
394 }
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_BANK0_END_ADDRESS
#define FMC_BANK0_END_ADDRESS
Definition: gd32f10x_fmc.h:265
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_CTL0_PG
#define FMC_CTL0_PG
Definition: gd32f10x_fmc.h:62
FMC_CTL1_PG
#define FMC_CTL1_PG
Definition: gd32f10x_fmc.h:95
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_interrupt_disable ( uint32_t interrupt )

disable FMC interrupt

Parameters
[in] interrupt the FMC interrupt source
  • FMC_INT_BANK0_END: enable FMC end of program interrupt
  • FMC_INT_BANK0_ERR: enable FMC error interrupt
  • FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt
  • FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt
[out] none
Return values
none

Definition at line 732 of file gd32f10x_fmc.c.

733 {
734 FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt));
735 }
FMC_REG_VAL
#define FMC_REG_VAL(offset)
Definition: gd32f10x_fmc.h:115
FMC_BIT_POS
#define FMC_BIT_POS(val)
Definition: gd32f10x_fmc.h:116
void fmc_interrupt_enable ( uint32_t interrupt )

enable FMC interrupt

Parameters
[in] interrupt the FMC interrupt source
  • FMC_INT_BANK0_END: enable FMC end of program interrupt
  • FMC_INT_BANK0_ERR: enable FMC error interrupt
  • FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt
  • FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt
[out] none
Return values
none

Definition at line 717 of file gd32f10x_fmc.c.

718 {
719 FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt));
720 }
FMC_REG_VAL
#define FMC_REG_VAL(offset)
Definition: gd32f10x_fmc.h:115
FMC_BIT_POS
#define FMC_BIT_POS(val)
Definition: gd32f10x_fmc.h:116
void fmc_interrupt_flag_clear ( fmc_interrupt_flag_enum flag )

clear FMC interrupt flag state

Parameters
[in] flag FMC interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below:
  • FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit
  • FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit
  • FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit
  • FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit
  • FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit
  • FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit
[out] none
Return values
none

Definition at line 830 of file gd32f10x_fmc.c.

831 {
832 FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag));
833 }
FMC_BIT_POS0
#define FMC_BIT_POS0(val)
Definition: gd32f10x_fmc.h:119
FMC_REG_VALS
#define FMC_REG_VALS(offset)
Definition: gd32f10x_fmc.h:118
FlagStatus fmc_interrupt_flag_get ( fmc_interrupt_flag_enum flag )

get FMC interrupt flag state

Parameters
[in] flag FMC interrupt flags, refer to fmc_interrupt_flag_enum only one parameter can be selected which is shown as below:
  • FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit
  • FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit
  • FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit
  • FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit
  • FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit
  • FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit
[out] none
Return values
FlagStatus SET or RESET

Definition at line 793 of file gd32f10x_fmc.c.

794 {
795 FlagStatus ret1 = RESET;
796 FlagStatus ret2 = RESET;
797
798 if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){
799 /* get the staus of interrupt flag */
800 ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
801 /* get the staus of interrupt enale bit */
802 ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
803 }else{
804 /* get the staus of interrupt flag */
805 ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
806 /* get the staus of interrupt enale bit */
807 ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag)));
808 }
809
810 if(ret1 && ret2){
811 return SET;
812 }else{
813 return RESET;
814 }
815 }
FMC_BIT_POS0
#define FMC_BIT_POS0(val)
Definition: gd32f10x_fmc.h:119
FMC_REG_VALS
#define FMC_REG_VALS(offset)
Definition: gd32f10x_fmc.h:118
FMC_REG_OFFSET_GET
#define FMC_REG_OFFSET_GET(flag)
Definition: gd32f10x_fmc.h:121
FMC_BIT_POS1
#define FMC_BIT_POS1(val)
Definition: gd32f10x_fmc.h:120
FMC_STAT0_REG_OFFSET
#define FMC_STAT0_REG_OFFSET
Definition: gd32f10x_fmc.h:124
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_lock ( void )

lock the main FMC operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 96 of file gd32f10x_fmc.c.

97 {
98 /* set the LK bit */
99 FMC_CTL0 |= FMC_CTL0_LK;
100
101 if(FMC_BANK0_SIZE < FMC_SIZE){
102 /* set the LK bit */
103 FMC_CTL1 |= FMC_CTL1_LK;
104 }
105 }
FMC_CTL0_LK
#define FMC_CTL0_LK
Definition: gd32f10x_fmc.h:68
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
FMC_CTL1_LK
#define FMC_CTL1_LK
Definition: gd32f10x_fmc.h:99
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum fmc_mass_erase ( void )

erase whole chip

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 198 of file gd32f10x_fmc.c.

199 {
200 fmc_state_enum fmc_state;
201 if(FMC_BANK0_SIZE < FMC_SIZE){
202 /* wait for the FMC ready */
203 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
204 if(FMC_READY == fmc_state){
205 /* start whole chip erase */
206 FMC_CTL0 |= FMC_CTL0_MER;
207 FMC_CTL0 |= FMC_CTL0_START;
208 /* wait for the FMC ready */
209 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
210 /* reset the MER bit */
211 FMC_CTL0 &= ~FMC_CTL0_MER;
212 }
213 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
214 if(FMC_READY == fmc_state){
215 /* start whole chip erase */
216 FMC_CTL1 |= FMC_CTL1_MER;
217 FMC_CTL1 |= FMC_CTL1_START;
218 /* wait for the FMC ready */
219 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
220 /* reset the MER bit */
221 FMC_CTL1 &= ~FMC_CTL1_MER;
222 }
223 }else{
224 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
225
226 if(FMC_READY == fmc_state){
227 /* start whole chip erase */
228 FMC_CTL0 |= FMC_CTL0_MER;
229 FMC_CTL0 |= FMC_CTL0_START;
230 /* wait for the FMC ready */
231 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
232 /* reset the MER bit */
233 FMC_CTL0 &= ~FMC_CTL0_MER;
234 }
235 }
236 /* return the FMC state */
237 return fmc_state;
238 }
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_CTL0_MER
#define FMC_CTL0_MER
Definition: gd32f10x_fmc.h:64
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_CTL1_START
#define FMC_CTL1_START
Definition: gd32f10x_fmc.h:98
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
FMC_CTL1_MER
#define FMC_CTL1_MER
Definition: gd32f10x_fmc.h:97
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum fmc_page_erase ( uint32_t page_address )

erase page

Parameters
[in] | page_address | the page address to be erased.
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 141 of file gd32f10x_fmc.c.

142 {
143 fmc_state_enum fmc_state;
144
145 if(FMC_BANK0_SIZE < FMC_SIZE){
146 if(FMC_BANK0_END_ADDRESS > page_address){
147 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
148 /* if the last operation is completed, start page erase */
149 if(FMC_READY == fmc_state){
150 FMC_CTL0 |= FMC_CTL0_PER;
151 FMC_ADDR0 = page_address;
152 FMC_CTL0 |= FMC_CTL0_START;
153 /* wait for the FMC ready */
154 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
155 /* reset the PER bit */
156 FMC_CTL0 &= ~FMC_CTL0_PER;
157 }
158 }else{
159 /* wait for the FMC ready */
160 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
161 /* if the last operation is completed, start page erase */
162 if(FMC_READY == fmc_state){
163 FMC_CTL1 |= FMC_CTL1_PER;
164 FMC_ADDR1 = page_address;
165 if(FMC_OBSTAT & FMC_OBSTAT_SPC){
166 FMC_ADDR0 = page_address;
167 }
168 FMC_CTL1 |= FMC_CTL1_START;
169 /* wait for the FMC ready */
170 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
171 /* reset the PER bit */
172 FMC_CTL1 &= ~FMC_CTL1_PER;
173 }
174 }
175 }else{
176 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
177 /* if the last operation is completed, start page erase */
178 if(FMC_READY == fmc_state){
179 FMC_CTL0 |= FMC_CTL0_PER;
180 FMC_ADDR0 = page_address;
181 FMC_CTL0 |= FMC_CTL0_START;
182 /* wait for the FMC ready */
183 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
184 /* reset the PER bit */
185 FMC_CTL0 &= ~FMC_CTL0_PER;
186 }
187 }
188 /* return the FMC state */
189 return fmc_state;
190 }
FMC_ADDR0
#define FMC_ADDR0
Definition: gd32f10x_fmc.h:28
FMC_CTL0_PER
#define FMC_CTL0_PER
Definition: gd32f10x_fmc.h:63
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_CTL1_START
#define FMC_CTL1_START
Definition: gd32f10x_fmc.h:98
FMC_BANK0_END_ADDRESS
#define FMC_BANK0_END_ADDRESS
Definition: gd32f10x_fmc.h:265
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
FMC_ADDR1
#define FMC_ADDR1
Definition: gd32f10x_fmc.h:34
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f10x_fmc.h:29
FMC_OBSTAT_SPC
#define FMC_OBSTAT_SPC
Definition: gd32f10x_fmc.h:78
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL1_PER
#define FMC_CTL1_PER
Definition: gd32f10x_fmc.h:96
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_unlock ( void )

unlock the main FMC operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 40 of file gd32f10x_fmc.c.

41 {
42 if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
43 /* write the FMC unlock key */
44 FMC_KEY0 = UNLOCK_KEY0;
45 FMC_KEY0 = UNLOCK_KEY1;
46 }
47 if(FMC_BANK0_SIZE < FMC_SIZE){
48 /* write the FMC unlock key */
49 if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){
50 FMC_KEY1 = UNLOCK_KEY0;
51 FMC_KEY1 = UNLOCK_KEY1;
52 }
53 }
54 }
FMC_CTL0_LK
#define FMC_CTL0_LK
Definition: gd32f10x_fmc.h:68
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f10x_fmc.h:175
FMC_KEY0
#define FMC_KEY0
Definition: gd32f10x_fmc.h:24
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f10x_fmc.h:176
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
FMC_CTL1_LK
#define FMC_CTL1_LK
Definition: gd32f10x_fmc.h:99
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
FMC_KEY1
#define FMC_KEY1
Definition: gd32f10x_fmc.h:31
fmc_state_enum fmc_word_program | ( | uint32_t | address,
 |  | uint32_t | data
 | ) |  |

program a word at the corresponding address

Parameters
[in] | address | address to program
[in] | data | word to program
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 297 of file gd32f10x_fmc.c.

298 {
299 fmc_state_enum fmc_state = FMC_READY;
300 if(FMC_BANK0_SIZE < FMC_SIZE){
301 if(FMC_BANK0_END_ADDRESS > address){
302 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
303
304 if(FMC_READY == fmc_state){
305 /* set the PG bit to start program */
306 FMC_CTL0 |= FMC_CTL0_PG;
307 REG32(address) = data;
308 /* wait for the FMC ready */
309 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
310 /* reset the PG bit */
311 FMC_CTL0 &= ~FMC_CTL0_PG;
312 }
313 }else{
314 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
315
316 if(FMC_READY == fmc_state){
317 /* set the PG bit to start program */
318 FMC_CTL1 |= FMC_CTL1_PG;
319 REG32(address) = data;
320 /* wait for the FMC ready */
321 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
322 /* reset the PG bit */
323 FMC_CTL1 &= ~FMC_CTL1_PG;
324 }
325 }
326 }else{
327 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
328
329 if(FMC_READY == fmc_state){
330 /* set the PG bit to start program */
331 FMC_CTL0 |= FMC_CTL0_PG;
332 REG32(address) = data;
333 /* wait for the FMC ready */
334 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
335 /* reset the PG bit */
336 FMC_CTL0 &= ~FMC_CTL0_PG;
337 }
338 }
339 /* return the FMC state */
340 return fmc_state;
341 }
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_BANK0_END_ADDRESS
#define FMC_BANK0_END_ADDRESS
Definition: gd32f10x_fmc.h:265
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_CTL0_PG
#define FMC_CTL0_PG
Definition: gd32f10x_fmc.h:62
FMC_CTL1_PG
#define FMC_CTL1_PG
Definition: gd32f10x_fmc.h:95
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void fmc_wscnt_set ( uint32_t wscnt )

set the wait state counter value

Parameters
[in] wscnt£ºwait state counter value
  • WS_WSCNT_0: FMC 0 wait
  • WS_WSCNT_1: FMC 1 wait
  • WS_WSCNT_2: FMC 2 wait
[out] none
Return values
none

Definition at line 24 of file gd32f10x_fmc.c.

25 {
26 uint32_t reg;
27
28 reg = FMC_WS;
29 /* set the wait state counter value */
30 reg &= ~FMC_WS_WSCNT;
31 FMC_WS = (reg | wscnt);
32 }
FMC_WS_WSCNT
#define FMC_WS_WSCNT
Definition: gd32f10x_fmc.h:47
FMC_WS
#define FMC_WS
Definition: gd32f10x_fmc.h:23
uint16_t ob_data_get ( void )

get OB_DATA in register FMC_OBSTAT

Parameters
[in] | none
[out] | none
Return values
ob_data

Definition at line 672 of file gd32f10x_fmc.c.

673 {
674 return (uint16_t)(FMC_OBSTAT >> 10U);
675 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f10x_fmc.h:29
fmc_state_enum ob_data_program | ( | uint32_t | address,
 |  | uint8_t | data
 | ) |  |

program option bytes data

Parameters
[in] | address | the option bytes address to be programmed
[in] | data | the byte to be programmed
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 633 of file gd32f10x_fmc.c.

634 {
635 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
636
637 if(FMC_READY == fmc_state){
638 /* set the OBPG bit */
639 FMC_CTL0 |= FMC_CTL0_OBPG;
640 REG16(address) = data;
641
642 /* wait for the FMC ready */
643 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
644
645 if(FMC_TOERR != fmc_state){
646 /* reset the OBPG bit */
647 FMC_CTL0 &= ~FMC_CTL0_OBPG;
648 }
649 }
650 /* return the FMC state */
651 return fmc_state;
652 }
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum ob_erase ( void )

erase the FMC option byte unlock the FMC_CTL0 and option byte before calling this function

Parameters
[in] | none
[out] | none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 434 of file gd32f10x_fmc.c.

435 {
436 uint16_t temp_spc = FMC_NSPC;
437
438 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
439
440 /* check the option byte security protection value */
441 if(RESET != ob_spc_get()){
442 temp_spc = FMC_USPC;
443 }
444
445 if(FMC_READY == fmc_state){
446
447 /* start erase the option byte */
448 FMC_CTL0 |= FMC_CTL0_OBER;
449 FMC_CTL0 |= FMC_CTL0_START;
450
451 /* wait for the FMC ready */
452 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
453
454 if(FMC_READY == fmc_state){
455 /* reset the OBER bit */
456 FMC_CTL0 &= ~FMC_CTL0_OBER;
457 /* set the OBPG bit */
458 FMC_CTL0 |= FMC_CTL0_OBPG;
459 /* no security protection */
460 OB_SPC = (uint16_t)temp_spc;
461 /* wait for the FMC ready */
462 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
463 if(FMC_TOERR != fmc_state){
464 /* reset the OBPG bit */
465 FMC_CTL0 &= ~FMC_CTL0_OBPG;
466 }
467 }else{
468 if(FMC_TOERR != fmc_state){
469 /* reset the OBPG bit */
470 FMC_CTL0 &= ~FMC_CTL0_OBPG;
471 }
472 }
473 }
474 /* return the FMC state */
475 return fmc_state;
476 }
FMC_CTL0_OBER
#define FMC_CTL0_OBER
Definition: gd32f10x_fmc.h:66
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
OB_SPC
#define OB_SPC
Definition: gd32f10x_fmc.h:38
FMC_TOERR
Definition: gd32f10x_fmc.h:137
FMC_NSPC
#define FMC_NSPC
Definition: gd32f10x_fmc.h:203
FMC_USPC
#define FMC_USPC
Definition: gd32f10x_fmc.h:204
ob_spc_get
FlagStatus ob_spc_get(void)
get the FMC option byte security protection
Definition: gd32f10x_fmc.c:695
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
void ob_lock ( void )

lock the option byte operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 421 of file gd32f10x_fmc.c.

422 {
423 /* reset the OBWEN bit */
424 FMC_CTL0 &= ~FMC_CTL0_OBWEN;
425 }
FMC_CTL0_OBWEN
#define FMC_CTL0_OBWEN
Definition: gd32f10x_fmc.h:69
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum ob_security_protection_config ( uint8_t ob_spc )

configure security protection

Parameters
[in] ob_spc specify security protection
  • FMC_NSPC: no security protection
  • FMC_USPC: under security protection
[out] none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 544 of file gd32f10x_fmc.c.

545 {
546 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
547
548 if(FMC_READY == fmc_state){
549 FMC_CTL0 |= FMC_CTL0_OBER;
550 FMC_CTL0 |= FMC_CTL0_START;
551
552 /* wait for the FMC ready */
553 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
554
555 if(FMC_READY == fmc_state){
556 /* reset the OBER bit */
557 FMC_CTL0 &= ~FMC_CTL0_OBER;
558
559 /* start the option byte program */
560 FMC_CTL0 |= FMC_CTL0_OBPG;
561
562 OB_SPC = (uint16_t)ob_spc;
563
564 /* wait for the FMC ready */
565 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
566
567 if(FMC_TOERR != fmc_state){
568 /* reset the OBPG bit */
569 FMC_CTL0 &= ~FMC_CTL0_OBPG;
570 }
571 }else{
572 if(FMC_TOERR != fmc_state){
573 /* reset the OBER bit */
574 FMC_CTL0 &= ~FMC_CTL0_OBER;
575 }
576 }
577 }
578 /* return the FMC state */
579 return fmc_state;
580 }
FMC_CTL0_OBER
#define FMC_CTL0_OBER
Definition: gd32f10x_fmc.h:66
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
OB_SPC
#define OB_SPC
Definition: gd32f10x_fmc.h:38
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
FlagStatus ob_spc_get ( void )

get the FMC option byte security protection

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 695 of file gd32f10x_fmc.c.

696 {
697 FlagStatus spc_state = RESET;
698
699 if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){
700 spc_state = SET;
701 }else{
702 spc_state = RESET;
703 }
704 return spc_state;
705 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f10x_fmc.h:29
FMC_OBSTAT_SPC
#define FMC_OBSTAT_SPC
Definition: gd32f10x_fmc.h:78
void ob_unlock ( void )

unlock the option byte operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 402 of file gd32f10x_fmc.c.

403 {
404 if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
405 /* write the FMC key */
406 FMC_OBKEY = UNLOCK_KEY0;
407 FMC_OBKEY = UNLOCK_KEY1;
408 }
409
410 /* wait until OBWEN bit is set by hardware */
411 while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
412 }
413 }
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f10x_fmc.h:175
FMC_OBKEY
#define FMC_OBKEY
Definition: gd32f10x_fmc.h:25
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f10x_fmc.h:176
FMC_CTL0_OBWEN
#define FMC_CTL0_OBWEN
Definition: gd32f10x_fmc.h:69
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
uint8_t ob_user_get ( void )

get the FMC user option byte

Parameters
[in] | none
[out] | none
Return values
the FMC user option byte values

Definition at line 660 of file gd32f10x_fmc.c.

661 {
662 /* return the FMC user option byte value */
663 return (uint8_t)(FMC_OBSTAT >> 2U);
664 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f10x_fmc.h:29
fmc_state_enum ob_user_write | ( | uint8_t | ob_fwdgt,
 |  | uint8_t | ob_deepsleep,
 |  | uint8_t | ob_stdby,
 |  | uint8_t | ob_boot
 | ) |  |

program the FMC user option byte

Parameters
[in] ob_fwdgt option byte watchdog value
  • OB_FWDGT_SW: software free watchdog
  • OB_FWDGT_HW: hardware free watchdog
[in] ob_deepsleep option byte deepsleep reset value
  • OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode
  • OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode
[in] ob_stdby:option byte standby reset value
  • OB_STDBY_NRST: no reset when entering standby mode
  • OB_STDBY_RST: generate a reset instead of entering standby mode
[in] ob_boot specifies the option byte boot bank value
  • OB_BOOT_B0: boot from bank0
  • OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void
[out] none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 599 of file gd32f10x_fmc.c.

600 {
601 fmc_state_enum fmc_state = FMC_READY;
602 uint8_t temp;
603
604 /* wait for the FMC ready */
605 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
606
607 if(FMC_READY == fmc_state){
608 /* set the OBPG bit*/
609 FMC_CTL0 |= FMC_CTL0_OBPG;
610
611 temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK);
612 OB_USER = (uint16_t)temp;
613
614 /* wait for the FMC ready */
615 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
616
617 if(FMC_TOERR != fmc_state){
618 /* reset the OBPG bit */
619 FMC_CTL0 &= ~FMC_CTL0_OBPG;
620 }
621 }
622 /* return the FMC state */
623 return fmc_state;
624 }
OB_USER_MASK
#define OB_USER_MASK
Definition: gd32f10x_fmc.h:200
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
OB_USER
#define OB_USER
Definition: gd32f10x_fmc.h:39
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
fmc_state_enum ob_write_protection_enable ( uint32_t ob_wp )

enable write protection

Parameters
[in] ob_wp specify sector to be write protected
  • OB_WPx(x=0..31): write protect specify sector
  • OB_WP_ALL: write protect all sector
[out] none
Return values
state of FMC, refer to fmc_state_enum

Definition at line 486 of file gd32f10x_fmc.c.

487 {
488 uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3;
489
490 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
491
492 ob_wp = (uint32_t)(~ob_wp);
493 temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0);
494 temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U);
495 temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U);
496 temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U);
497
498 if(FMC_READY == fmc_state){
499
500 /* set the OBPG bit*/
501 FMC_CTL0 |= FMC_CTL0_OBPG;
502
503 if(0xFFU != temp_wp0){
504 OB_WP0 = temp_wp0;
505
506 /* wait for the FMC ready */
507 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
508 }
509 if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){
510 OB_WP1 = temp_wp1;
511
512 /* wait for the FMC ready */
513 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
514 }
515 if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){
516 OB_WP2 = temp_wp2;
517
518 /* wait for the FMC ready */
519 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
520 }
521 if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){
522 OB_WP3 = temp_wp3;
523
524 /* wait for the FMC ready */
525 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
526 }
527 if(FMC_TOERR != fmc_state){
528 /* reset the OBPG bit */
529 FMC_CTL0 &= ~FMC_CTL0_OBPG;
530 }
531 }
532 /* return the FMC state */
533 return fmc_state;
534 }
OB_WP1_WP1
#define OB_WP1_WP1
Definition: gd32f10x_fmc.h:218
OB_WP0
#define OB_WP0
Definition: gd32f10x_fmc.h:40
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
OB_WP0_WP0
#define OB_WP0_WP0
Definition: gd32f10x_fmc.h:215
OB_WP3
#define OB_WP3
Definition: gd32f10x_fmc.h:43
FMC_TOERR
Definition: gd32f10x_fmc.h:137
OB_WP3_WP3
#define OB_WP3_WP3
Definition: gd32f10x_fmc.h:224
OB_WP2_WP2
#define OB_WP2_WP2
Definition: gd32f10x_fmc.h:221
OB_WP1
#define OB_WP1
Definition: gd32f10x_fmc.h:41
OB_WP2
#define OB_WP2
Definition: gd32f10x_fmc.h:42
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
uint32_t ob_write_protection_get ( void )

get the FMC option byte write protection

Parameters
[in] | none
[out] | none
Return values
the FMC write protection option byte value

Definition at line 683 of file gd32f10x_fmc.c.

684 {
685 /* return the FMC write protection option byte value */
686 return FMC_WP;
687 }
FMC_WP
#define FMC_WP
Definition: gd32f10x_fmc.h:30
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_fwdgt.c File Reference

FWDGT driver. More...

#include "gd32f10x_fwdgt.h"

Go to the source code of this file.

Macros

#define | CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
#define | RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))

Functions

void | fwdgt_write_disable (void)
disable write access to FWDGT_PSC and FWDGT_RLD More...
void | fwdgt_counter_reload (void)
reload the counter of FWDGT More...
void | fwdgt_enable (void)
start the free watchdog timer counter More...
ErrStatus | fwdgt_config (uint16_t reload_value, uint8_t prescaler_div)
configure counter reload value, and prescaler divider value More...
FlagStatus | fwdgt_flag_get (uint16_t flag)
get flag state of FWDGT More...

Detailed Description

FWDGT driver.

Definition in file gd32f10x_fwdgt.c.

Macro Definition Documentation

#define CTL_CMD ( regval ) (BITS(0,15) & ((uint32_t)(regval) << 0))

Definition at line 16 of file gd32f10x_fwdgt.c.

#define RLD_RLD ( regval ) (BITS(0,11) & ((uint32_t)(regval) << 0))

Definition at line 18 of file gd32f10x_fwdgt.c.

Function Documentation

ErrStatus fwdgt_config | ( | uint16_t | reload_value,
 |  | uint8_t | prescaler_div
 | ) |  |

configure counter reload value, and prescaler divider value

Parameters
[in] | reload_value | specify reload value(0x0000 - 0x0FFF)
[in] prescaler_div FWDGT prescaler value
  • FWDGT_PSC_DIV4: FWDGT prescaler set to 4
  • FWDGT_PSC_DIV8: FWDGT prescaler set to 8
  • FWDGT_PSC_DIV16: FWDGT prescaler set to 16
  • FWDGT_PSC_DIV32: FWDGT prescaler set to 32
  • FWDGT_PSC_DIV64: FWDGT prescaler set to 64
  • FWDGT_PSC_DIV128: FWDGT prescaler set to 128
  • FWDGT_PSC_DIV256: FWDGT prescaler set to 256
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 68 of file gd32f10x_fwdgt.c.

69 {
70 uint32_t timeout = FWDGT_PSC_TIMEOUT;
71 uint32_t flag_status = RESET;
72
73 /* enable write access to FWDGT_PSC,and FWDGT_RLD */
74 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
75 /* wait until the PUD flag to be reset */
76 do{
77 flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
78 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
79
80 if((uint32_t)RESET != flag_status){
81 return ERROR;
82 }
83 /* configure FWDGT */
84 FWDGT_PSC = (uint32_t)prescaler_div;
85
86 timeout = FWDGT_RLD_TIMEOUT;
87 /* wait until the RUD flag to be reset */
88 do{
89 flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
90 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
91
92 if((uint32_t)RESET != flag_status){
93 return ERROR;
94 }
95 FWDGT_RLD = RLD_RLD(reload_value);
96 /* reload the counter */
97 FWDGT_CTL = FWDGT_KEY_RELOAD;
98
99 return SUCCESS;
100 }
FWDGT_STAT_PUD
#define FWDGT_STAT_PUD
Definition: gd32f10x_fwdgt.h:38
FWDGT_RLD_TIMEOUT
#define FWDGT_RLD_TIMEOUT
Definition: gd32f10x_fwdgt.h:60
RLD_RLD
#define RLD_RLD(regval)
Definition: gd32f10x_fwdgt.c:18
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f10x_fwdgt.h:25
FWDGT_WRITEACCESS_ENABLE
#define FWDGT_WRITEACCESS_ENABLE
Definition: gd32f10x_fwdgt.h:53
FWDGT_RLD
#define FWDGT_RLD
Definition: gd32f10x_fwdgt.h:24
FWDGT_PSC_TIMEOUT
#define FWDGT_PSC_TIMEOUT
Definition: gd32f10x_fwdgt.h:59
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f10x_fwdgt.h:55
FWDGT_STAT_RUD
#define FWDGT_STAT_RUD
Definition: gd32f10x_fwdgt.h:39
FWDGT_PSC
#define FWDGT_PSC
Definition: gd32f10x_fwdgt.h:23
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f10x_fwdgt.h:22
void fwdgt_counter_reload ( void )

reload the counter of FWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 37 of file gd32f10x_fwdgt.c.

38 {
39 FWDGT_CTL = FWDGT_KEY_RELOAD;
40 }
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f10x_fwdgt.h:55
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f10x_fwdgt.h:22
void fwdgt_enable ( void )

start the free watchdog timer counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 48 of file gd32f10x_fwdgt.c.

49 {
50 FWDGT_CTL = FWDGT_KEY_ENABLE;
51 }
FWDGT_KEY_ENABLE
#define FWDGT_KEY_ENABLE
Definition: gd32f10x_fwdgt.h:56
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f10x_fwdgt.h:22
FlagStatus fwdgt_flag_get ( uint16_t flag )

get flag state of FWDGT

Parameters
[in] flag flag to get
  • FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
  • FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
[out] none
Return values
FlagStatus SET or RESET

Definition at line 110 of file gd32f10x_fwdgt.c.

111 {
112 if(FWDGT_STAT & flag){
113 return SET;
114 }
115 return RESET;
116 }
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f10x_fwdgt.h:25
void fwdgt_write_disable ( void )

disable write access to FWDGT_PSC and FWDGT_RLD

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 26 of file gd32f10x_fwdgt.c.

27 {
28 FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
29 }
FWDGT_WRITEACCESS_DISABLE
#define FWDGT_WRITEACCESS_DISABLE
Definition: gd32f10x_fwdgt.h:54
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f10x_fwdgt.h:22
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_gpio.c File Reference

GPIO driver. More...

#include "gd32f10x_gpio.h"

Go to the source code of this file.

Macros

#define | AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U)
#define | LSB_16BIT_MASK ((uint16_t)0xFFFFU)
#define | PCF_POSITION_MASK ((uint32_t)0x000F0000U)
#define | PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU)
#define | PCF_LOCATION1_MASK ((uint32_t)0x00200000U)
#define | PCF_LOCATION2_MASK ((uint32_t)0x00100000U)
#define | AFIO_PCF1_FIELDS ((uint32_t)0x80000000U)

Functions

void | gpio_deinit (uint32_t gpio_periph)
reset GPIO port More...
void | gpio_afio_deinit (void)
reset alternate function I/O(AFIO) More...
void | gpio_init (uint32_t gpio_periph, uint32_t gpio_mode, uint32_t gpio_speed, uint32_t pin)
GPIO parameter initialization. More...
void | gpio_bit_set (uint32_t gpio_periph, uint32_t pin)
set GPIO pin More...
void | gpio_bit_reset (uint32_t gpio_periph, uint32_t pin)
reset GPIO pin More...
void | gpio_bit_write (uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
write data to the specified GPIO pin More...
void | gpio_port_write (uint32_t gpio_periph, uint16_t data)
write data to the specified GPIO port More...
FlagStatus | gpio_input_bit_get (uint32_t gpio_periph, uint32_t pin)
get GPIO pin input status More...
uint16_t | gpio_input_port_get (uint32_t gpio_periph)
get GPIO port input status More...
FlagStatus | gpio_output_bit_get (uint32_t gpio_periph, uint32_t pin)
get GPIO pin output status More...
uint16_t | gpio_output_port_get (uint32_t gpio_periph)
get GPIO port output status More...
void | gpio_pin_lock (uint32_t gpio_periph, uint32_t pin)
lock GPIO pin More...
void | gpio_event_output_config (uint8_t gpio_outputport, uint8_t gpio_outputpin)
configure GPIO pin event output More...
void | gpio_event_output_enable (void)
enable GPIO pin event output More...
void | gpio_event_output_disable (void)
disable GPIO pin event output More...
void | gpio_exti_source_select (uint8_t gpio_outputport, uint8_t gpio_outputpin)
select GPIO pin exti sources More...
void | gpio_ethernet_phy_select (uint32_t gpio_enetsel)
select ethernet MII or RMII PHY More...
void | gpio_pin_remap_config (uint32_t gpio_remap, ControlStatus newvalue)
configure GPIO pin remap More...

Detailed Description

GPIO driver.

Definition in file gd32f10x_gpio.c.

Macro Definition Documentation

#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U)

select AFIO exti source registers

Definition at line 15 of file gd32f10x_gpio.c.

#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U)

select AFIO_PCF1 register

Definition at line 21 of file gd32f10x_gpio.c.

#define LSB_16BIT_MASK ((uint16_t)0xFFFFU)

LSB 16-bit mask

Definition at line 16 of file gd32f10x_gpio.c.

#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U)

AFIO_PCF register location1 mask

Definition at line 19 of file gd32f10x_gpio.c.

#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U)

AFIO_PCF register location2 mask

Definition at line 20 of file gd32f10x_gpio.c.

#define PCF_POSITION_MASK ((uint32_t)0x000F0000U)

AFIO_PCF register position mask

Definition at line 17 of file gd32f10x_gpio.c.

#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU)

AFIO_PCF register SWJCFG mask

Definition at line 18 of file gd32f10x_gpio.c.

Function Documentation

void gpio_afio_deinit ( void )

reset alternate function I/O(AFIO)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 78 of file gd32f10x_gpio.c.

79 {
80 rcu_periph_reset_enable(RCU_AFRST);
81 rcu_periph_reset_disable(RCU_AFRST);
82 }
RCU_AFRST
Definition: gd32f10x_rcu.h:477
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void gpio_bit_reset | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

reset GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 188 of file gd32f10x_gpio.c.

189 {
190 GPIO_BC(gpio_periph) = (uint32_t)pin;
191 }
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f10x_gpio.h:38
void gpio_bit_set | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

set GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 176 of file gd32f10x_gpio.c.

177 {
178 GPIO_BOP(gpio_periph) = (uint32_t)pin;
179 }
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f10x_gpio.h:37
void gpio_bit_write | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin,
 |  | bit_status | bit_value
 | ) |  |

write data to the specified GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[in] bit_value SET or RESET
  • RESET: clear the port pin
  • SET: set the port pin
[out] | none
Return values
none

Definition at line 203 of file gd32f10x_gpio.c.

204 {
205 if(RESET != bit_value){
206 GPIO_BOP(gpio_periph) = (uint32_t)pin;
207 }else{
208 GPIO_BC(gpio_periph) = (uint32_t)pin;
209 }
210 }
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f10x_gpio.h:37
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f10x_gpio.h:38
void gpio_deinit ( uint32_t gpio_periph )

reset GPIO port

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[out] | none
Return values
none

Definition at line 29 of file gd32f10x_gpio.c.

30 {
31 switch(gpio_periph){
32 case GPIOA:
33 /* reset GPIOA */
34 rcu_periph_reset_enable(RCU_GPIOARST);
35 rcu_periph_reset_disable(RCU_GPIOARST);
36 break;
37 case GPIOB:
38 /* reset GPIOB */
39 rcu_periph_reset_enable(RCU_GPIOBRST);
40 rcu_periph_reset_disable(RCU_GPIOBRST);
41 break;
42 case GPIOC:
43 /* reset GPIOC */
44 rcu_periph_reset_enable(RCU_GPIOCRST);
45 rcu_periph_reset_disable(RCU_GPIOCRST);
46 break;
47 case GPIOD:
48 /* reset GPIOD */
49 rcu_periph_reset_enable(RCU_GPIODRST);
50 rcu_periph_reset_disable(RCU_GPIODRST);
51 break;
52 case GPIOE:
53 /* reset GPIOE */
54 rcu_periph_reset_enable(RCU_GPIOERST);
55 rcu_periph_reset_disable(RCU_GPIOERST);
56 break;
57 case GPIOF:
58 /* reset GPIOF */
59 rcu_periph_reset_enable(RCU_GPIOFRST);
60 rcu_periph_reset_disable(RCU_GPIOFRST);
61 break;
62 case GPIOG:
63 /* reset GPIOG */
64 rcu_periph_reset_enable(RCU_GPIOGRST);
65 rcu_periph_reset_disable(RCU_GPIOGRST);
66 break;
67 default:
68 break;
69 }
70 }
RCU_GPIOGRST
Definition: gd32f10x_rcu.h:484
RCU_GPIOBRST
Definition: gd32f10x_rcu.h:479
GPIOD
#define GPIOD
Definition: gd32f10x_gpio.h:22
RCU_GPIOFRST
Definition: gd32f10x_rcu.h:483
GPIOA
#define GPIOA
Definition: gd32f10x_gpio.h:19
RCU_GPIODRST
Definition: gd32f10x_rcu.h:481
GPIOF
#define GPIOF
Definition: gd32f10x_gpio.h:24
RCU_GPIOARST
Definition: gd32f10x_rcu.h:478
GPIOB
#define GPIOB
Definition: gd32f10x_gpio.h:20
GPIOG
#define GPIOG
Definition: gd32f10x_gpio.h:25
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
RCU_GPIOCRST
Definition: gd32f10x_rcu.h:480
GPIOE
#define GPIOE
Definition: gd32f10x_gpio.h:23
RCU_GPIOERST
Definition: gd32f10x_rcu.h:482
GPIOC
#define GPIOC
Definition: gd32f10x_gpio.h:21
void gpio_ethernet_phy_select ( uint32_t gpio_enetsel )

select ethernet MII or RMII PHY

Parameters
[in] gpio_enetsel ethernet MII or RMII PHY selection
  • GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY
  • GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY
[out] none
Return values
none

Definition at line 394 of file gd32f10x_gpio.c.

395 {
396 /* clear AFIO_PCF0_ENET_PHY_SEL bit */
397 AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL);
398
399 /* select MII or RMII PHY */
400 AFIO_PCF0 |= (uint32_t)gpio_enetsel;
401 }
AFIO_PCF0_ENET_PHY_SEL
#define AFIO_PCF0_ENET_PHY_SEL
Definition: gd32f10x_gpio.h:216
AFIO_PCF0
#define AFIO_PCF0
Definition: gd32f10x_gpio.h:43
void gpio_event_output_config | ( | uint8_t | gpio_outputport,
 |  | uint8_t | gpio_outputpin
 | ) |  |

configure GPIO pin event output

Parameters
[in] gpio_outputport gpio event output port
  • GPIO_EVENT_PORT_GPIOA: event output port A
  • GPIO_EVENT_PORT_GPIOB: event output port B
  • GPIO_EVENT_PORT_GPIOC: event output port C
  • GPIO_EVENT_PORT_GPIOD: event output port D
  • GPIO_EVENT_PORT_GPIOE: event output port E
[in] | gpio_outputpin | GPIO_EVENT_PIN_x(x=0..15)
[out] | none
Return values
none

Definition at line 310 of file gd32f10x_gpio.c.

311 {
312 uint32_t reg = 0U;
313 reg = AFIO_EC;
314
315 /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */
316 reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN));
317
318 reg |= (uint32_t)((uint32_t)gpio_outputport << 0x04U);
319 reg |= (uint32_t)gpio_outputpin;
320
321 AFIO_EC = reg;
322 }
AFIO_EC_PIN
#define AFIO_EC_PIN
Definition: gd32f10x_gpio.h:195
AFIO_EC
#define AFIO_EC
Definition: gd32f10x_gpio.h:42
AFIO_EC_PORT
#define AFIO_EC_PORT
Definition: gd32f10x_gpio.h:196
void gpio_event_output_disable ( void )

disable GPIO pin event output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 341 of file gd32f10x_gpio.c.

342 {
343 AFIO_EC &= (uint32_t)(~AFIO_EC_EOE);
344 }
AFIO_EC_EOE
#define AFIO_EC_EOE
Definition: gd32f10x_gpio.h:197
AFIO_EC
#define AFIO_EC
Definition: gd32f10x_gpio.h:42
void gpio_event_output_enable ( void )

enable GPIO pin event output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 330 of file gd32f10x_gpio.c.

331 {
332 AFIO_EC |= AFIO_EC_EOE;
333 }
AFIO_EC_EOE
#define AFIO_EC_EOE
Definition: gd32f10x_gpio.h:197
AFIO_EC
#define AFIO_EC
Definition: gd32f10x_gpio.h:42
void gpio_exti_source_select | ( | uint8_t | gpio_outputport,
 |  | uint8_t | gpio_outputpin
 | ) |  |

select GPIO pin exti sources

Parameters
[in] gpio_outputport gpio event output port
  • GPIO_PORT_SOURCE_GPIOA: output port source A
  • GPIO_PORT_SOURCE_GPIOB: output port source B
  • GPIO_PORT_SOURCE_GPIOC: output port source C
  • GPIO_PORT_SOURCE_GPIOD: output port source D
  • GPIO_PORT_SOURCE_GPIOE: output port source E
  • GPIO_PORT_SOURCE_GPIOF: output port source F
  • GPIO_PORT_SOURCE_GPIOG: output port source G
[in] | gpio_outputpin | GPIO_PIN_SOURCE_x(x=0..15)
[out] | none
Return values
none

Definition at line 360 of file gd32f10x_gpio.c.

361 {
362 uint32_t source = 0U;
363 source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U));
364
365 /* select EXTI sources */
366 if(GPIO_PIN_SOURCE_4 > gpio_outputpin){
367 /* select EXTI0/EXTI1/EXTI2/EXTI3 */
368 AFIO_EXTISS0 &= ~source;
369 AFIO_EXTISS0 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
370 }else if(GPIO_PIN_SOURCE_8 > gpio_outputpin){
371 /* select EXTI4/EXTI5/EXTI6/EXTI7 */
372 AFIO_EXTISS1 &= ~source;
373 AFIO_EXTISS1 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
374 }else if(GPIO_PIN_SOURCE_12 > gpio_outputpin){
375 /* select EXTI8/EXTI9/EXTI10/EXTI11 */
376 AFIO_EXTISS2 &= ~source;
377 AFIO_EXTISS2 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
378 }else{
379 /* select EXTI12/EXTI13/EXTI14/EXTI15 */
380 AFIO_EXTISS3 &= ~source;
381 AFIO_EXTISS3 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
382 }
383 }
AFIO_EXTISS1
#define AFIO_EXTISS1
Definition: gd32f10x_gpio.h:45
GPIO_PIN_SOURCE_8
#define GPIO_PIN_SOURCE_8
Definition: gd32f10x_gpio.h:340
GPIO_PIN_SOURCE_4
#define GPIO_PIN_SOURCE_4
Definition: gd32f10x_gpio.h:336
AFIO_EXTISS3
#define AFIO_EXTISS3
Definition: gd32f10x_gpio.h:47
GPIO_PIN_SOURCE_12
#define GPIO_PIN_SOURCE_12
Definition: gd32f10x_gpio.h:344
AFIO_EXTISS0
#define AFIO_EXTISS0
Definition: gd32f10x_gpio.h:44
AFIO_EXTISS2
#define AFIO_EXTISS2
Definition: gd32f10x_gpio.h:46
AFIO_EXTI_SOURCE_FIELDS
#define AFIO_EXTI_SOURCE_FIELDS
Definition: gd32f10x_gpio.c:15
void gpio_init | ( | uint32_t | gpio_periph,
 |  | uint32_t | gpio_mode,
 |  | uint32_t | gpio_speed,
 |  | uint32_t | pin
 | ) |  |

GPIO parameter initialization.

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] gpio_mode gpio pin mode
  • GPIO_MODE_AIN: analog input mode
  • GPIO_MODE_IN_FLOATING: floating input mode
  • GPIO_MODE_IPD: pull-down input mode
  • GPIO_MODE_IPU: pull-up input mode
  • GPIO_MODE_OUT_OD: GPIO output with open-drain
  • GPIO_MODE_OUT_PP: GPIO output with push-pull
  • GPIO_MODE_AF_OD: AFIO output with open-drain
  • GPIO_MODE_AF_PP: AFIO output with push-pull
[in] gpio_speed gpio output max speed value
  • GPIO_OSPEED_10MHZ: output max speed 10MHz
  • GPIO_OSPEED_2MHZ: output max speed 2MHz
  • GPIO_OSPEED_50MHZ: output max speed 50MHz
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 104 of file gd32f10x_gpio.c.

105 {
106 uint16_t i;
107 uint32_t temp_mode = 0U;
108 uint32_t reg = 0U;
109
110 /* GPIO mode configuration */
111 temp_mode = (uint32_t)(gpio_mode & ((uint32_t)0x0FU));
112
113 /* GPIO speed configuration */
114 if(((uint32_t)0x00U) != ((uint32_t)gpio_mode & ((uint32_t)0x10U))){
115 /* output mode max speed:10MHz,2MHz,50MHz */
116 temp_mode |= (uint32_t)gpio_speed;
117 }
118
119 /* configure the eight low port pins with GPIO_CTL0 */
120 for(i = 0U;i < 8U;i++){
121 if((1U << i) & pin){
122 reg = GPIO_CTL0(gpio_periph);
123
124 /* clear the specified pin mode bits */
125 reg &= ~GPIO_MODE_MASK(i);
126 /* set the specified pin mode bits */
127 reg |= GPIO_MODE_SET(i, temp_mode);
128
129 /* set IPD or IPU */
130 if(GPIO_MODE_IPD == gpio_mode){
131 /* reset the corresponding OCTL bit */
132 GPIO_BC(gpio_periph) = (uint32_t)pin;
133 }else{
134 /* set the corresponding OCTL bit */
135 if(GPIO_MODE_IPU == gpio_mode){
136 GPIO_BOP(gpio_periph) = (uint32_t)pin;
137 }
138 }
139 /* set GPIO_CTL0 register */
140 GPIO_CTL0(gpio_periph) = reg;
141 }
142 }
143 /* configure the eight high port pins with GPIO_CTL1 */
144 for(i = 8U;i < 16U;i++){
145 if((1U << i) & pin){
146 reg = GPIO_CTL1(gpio_periph);
147
148 /* clear the specified pin mode bits */
149 reg &= ~GPIO_MODE_MASK(i - 8U);
150 /* set the specified pin mode bits */
151 reg |= GPIO_MODE_SET(i - 8U, temp_mode);
152
153 /* set IPD or IPU */
154 if(GPIO_MODE_IPD == gpio_mode){
155 /* reset the corresponding OCTL bit */
156 GPIO_BC(gpio_periph) = (uint32_t)pin;
157 }else{
158 /* set the corresponding OCTL bit */
159 if(GPIO_MODE_IPU == gpio_mode){
160 GPIO_BOP(gpio_periph) = (uint32_t)pin;
161 }
162 }
163 /* set GPIO_CTL1 register */
164 GPIO_CTL1(gpio_periph) = reg;
165 }
166 }
167 }
GPIO_MODE_IPU
#define GPIO_MODE_IPU
Definition: gd32f10x_gpio.h:286
GPIO_MODE_IPD
#define GPIO_MODE_IPD
Definition: gd32f10x_gpio.h:285
GPIO_CTL1
#define GPIO_CTL1(gpiox)
Definition: gd32f10x_gpio.h:34
GPIO_MODE_SET
#define GPIO_MODE_SET(n, mode)
Definition: gd32f10x_gpio.h:279
GPIO_MODE_MASK
#define GPIO_MODE_MASK(n)
Definition: gd32f10x_gpio.h:280
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f10x_gpio.h:37
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f10x_gpio.h:38
GPIO_CTL0
#define GPIO_CTL0(gpiox)
Definition: gd32f10x_gpio.h:33
FlagStatus gpio_input_bit_get | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

get GPIO pin input status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
input status of gpio pin: SET or RESET

Definition at line 231 of file gd32f10x_gpio.c.

232 {
233 if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
234 return SET;
235 }else{
236 return RESET;
237 }
238 }
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f10x_gpio.h:35
uint16_t gpio_input_port_get ( uint32_t gpio_periph )

get GPIO port input status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[out] | none
Return values
input status of gpio all pins

Definition at line 246 of file gd32f10x_gpio.c.

247 {
248 return (uint16_t)(GPIO_ISTAT(gpio_periph));
249 }
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f10x_gpio.h:35
FlagStatus gpio_output_bit_get | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

get GPIO pin output status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
output status of gpio pin: SET or RESET

Definition at line 258 of file gd32f10x_gpio.c.

259 {
260 if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){
261 return SET;
262 }else{
263 return RESET;
264 }
265 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f10x_gpio.h:36
uint16_t gpio_output_port_get ( uint32_t gpio_periph )

get GPIO port output status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[out] | none
Return values
output status of gpio all pins

Definition at line 273 of file gd32f10x_gpio.c.

274 {
275 return ((uint16_t)GPIO_OCTL(gpio_periph));
276 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f10x_gpio.h:36
void gpio_pin_lock | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

lock GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 285 of file gd32f10x_gpio.c.

286 {
287 uint32_t lock = 0x00010000U;
288 lock |= pin;
289
290 /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */
291 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
292 GPIO_LOCK(gpio_periph) = (uint32_t)pin;
293 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
294 lock = GPIO_LOCK(gpio_periph);
295 lock = GPIO_LOCK(gpio_periph);
296 }
GPIO_LOCK
#define GPIO_LOCK(gpiox)
Definition: gd32f10x_gpio.h:39
void gpio_pin_remap_config | ( | uint32_t | gpio_remap,
 |  | ControlStatus | newvalue
 | ) |  |

configure GPIO pin remap

Parameters
[in] gpio_remap select the pin to remap
  • GPIO_SPI0_REMAP: SPI0 remapping
  • GPIO_I2C0_REMAP: I2C0 remapping
  • GPIO_USART0_REMAP: USART0 remapping
  • GPIO_USART1_REMAP: USART1 remapping
  • GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping
  • GPIO_USART2_FULL_REMAP: USART2 full remapping
  • GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping
  • GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping
  • GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping
  • GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping
  • GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping
  • GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping
  • GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping
  • GPIO_TIMER3_REMAP: TIMER3 remapping
  • GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F10X_CL devices)
  • GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F10X_CL devices)
  • GPIO_PD01_REMAP: PD01 remapping
  • GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices)
  • GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
  • GPIO_ENET_REMAP: ENET remapping(only for GD32F10X_CL devices)
  • GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F10X_CL devices)
  • GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST
  • GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled
  • GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled
  • GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F10X_CL devices)
  • GPIO_TIMER1ITR0_REMAP: TIMER1 internal trigger 0 remapping(only for GD32F10X_CL devices)
  • GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F10X_CL devices)
  • GPIO_TIMER8_REMAP: TIMER8 remapping
  • GPIO_TIMER9_REMAP: TIMER9 remapping
  • GPIO_TIMER10_REMAP: TIMER10 remapping
  • GPIO_TIMER12_REMAP: TIMER12 remapping
  • GPIO_TIMER13_REMAP: TIMER13 remapping
  • GPIO_FSMC_NADV_REMAP: FSMC_NADV connect/disconnect
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 449 of file gd32f10x_gpio.c.

450 {
451 uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;
452
453 if(((uint32_t)0x80000000U) == (gpio_remap & 0x80000000U)){
454 /* get AFIO_PCF1 regiter value */
455 temp_reg = AFIO_PCF1;
456 }else{
457 /* get AFIO_PCF0 regiter value */
458 temp_reg = AFIO_PCF0;
459 }
460
461 temp_mask = (gpio_remap & PCF_POSITION_MASK) >> 0x10U;
462 remap1 = gpio_remap & LSB_16BIT_MASK;
463
464 /* judge pin remap type */
465 if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){
466 temp_reg &= PCF_SWJCFG_MASK;
467 AFIO_PCF0 &= PCF_SWJCFG_MASK;
468 }else if(PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)){
469 remap2 = ((uint32_t)0x03U) << temp_mask;
470 temp_reg &= ~remap2;
471 temp_reg |= ~PCF_SWJCFG_MASK;
472 }else{
473 temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U)*0x10U));
474 temp_reg |= ~PCF_SWJCFG_MASK;
475 }
476
477 /* set pin remap value */
478 if(DISABLE != newvalue){
479 temp_reg |= (remap1 << ((gpio_remap >> 0x15U)*0x10U));
480 }
481
482 if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){
483 /* set AFIO_PCF1 regiter value */
484 AFIO_PCF1 = temp_reg;
485 }else{
486 /* set AFIO_PCF0 regiter value */
487 AFIO_PCF0 = temp_reg;
488 }
489 }
AFIO_PCF1_FIELDS
#define AFIO_PCF1_FIELDS
Definition: gd32f10x_gpio.c:21
AFIO_PCF1
#define AFIO_PCF1
Definition: gd32f10x_gpio.h:48
LSB_16BIT_MASK
#define LSB_16BIT_MASK
Definition: gd32f10x_gpio.c:16
PCF_SWJCFG_MASK
#define PCF_SWJCFG_MASK
Definition: gd32f10x_gpio.c:18
PCF_LOCATION1_MASK
#define PCF_LOCATION1_MASK
Definition: gd32f10x_gpio.c:19
PCF_LOCATION2_MASK
#define PCF_LOCATION2_MASK
Definition: gd32f10x_gpio.c:20
AFIO_PCF0
#define AFIO_PCF0
Definition: gd32f10x_gpio.h:43
PCF_POSITION_MASK
#define PCF_POSITION_MASK
Definition: gd32f10x_gpio.c:17
void gpio_port_write | ( | uint32_t | gpio_periph,
 |  | uint16_t | data
 | ) |  |

write data to the specified GPIO port

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,E,F,G)
[in] | data | specify the value to be written to the port output data register
[out] | none
Return values
none

Definition at line 219 of file gd32f10x_gpio.c.

220 {
221 GPIO_OCTL(gpio_periph) = (uint32_t)data;
222 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f10x_gpio.h:36
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_i2c.c File Reference

I2C driver. More...

#include "gd32f10x_i2c.h"

Go to the source code of this file.

Macros

#define | I2CCLK_MAX 0x3FU
#define | I2C_FLAG_MASK 0x0000FFFFU

Functions

void | i2c_deinit (uint32_t i2c_periph)
reset I2C More...
void | i2c_clock_config (uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
I2C clock configure. More...
void | i2c_mode_addr_config (uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
configure I2C address More...
void | i2c_smbus_type_config (uint32_t i2c_periph, uint32_t type)
SMBus type selection. More...
void | i2c_ack_config (uint32_t i2c_periph, uint32_t ack)
whether or not to send an ACK More...
void | i2c_ackpos_config (uint32_t i2c_periph, uint32_t pos)
I2C POAP position configure. More...
void | i2c_master_addressing (uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
master send slave address More...
void | i2c_dualaddr_enable (uint32_t i2c_periph, uint32_t dualaddr)
dual-address mode switch More...
void | i2c_enable (uint32_t i2c_periph)
enable I2C More...
void | i2c_disable (uint32_t i2c_periph)
disable I2C More...
void | i2c_start_on_bus (uint32_t i2c_periph)
generate a START condition on I2C bus More...
void | i2c_stop_on_bus (uint32_t i2c_periph)
generate a STOP condition on I2C bus More...
void | i2c_data_transmit (uint32_t i2c_periph, uint8_t data)
I2C transmit data function. More...
uint8_t | i2c_data_receive (uint32_t i2c_periph)
I2C receive data function. More...
void | i2c_dma_enable (uint32_t i2c_periph, uint32_t dmastate)
enable I2C DMA mode More...
void | i2c_dma_last_transfer_enable (uint32_t i2c_periph, uint32_t dmalast)
flag indicating DMA last transfer More...
void | i2c_stretch_scl_low_config (uint32_t i2c_periph, uint32_t stretchpara)
whether to stretch SCL low when data is not ready in slave mode More...
void | i2c_slave_response_to_gcall_config (uint32_t i2c_periph, uint32_t gcallpara)
whether or not to response to a general call More...
void | i2c_software_reset_config (uint32_t i2c_periph, uint32_t sreset)
software reset I2C More...
FlagStatus | i2c_flag_get (uint32_t i2c_periph, uint32_t flag)
check I2C flag is set or not More...
void | i2c_flag_clear (uint32_t i2c_periph, uint32_t flag)
clear I2C flag More...
void | i2c_interrupt_enable (uint32_t i2c_periph, uint32_t inttype)
enable I2C interrupt More...
void | i2c_interrupt_disable (uint32_t i2c_periph, uint32_t inttype)
disable I2C interrupt More...
FlagStatus | i2c_interrupt_flag_get (uint32_t i2c_periph, uint32_t intflag)
check I2C interrupt flag More...
void | i2c_interrupt_flag_clear (uint32_t i2c_periph, uint32_t intflag)
clear I2C interrupt flag More...
void | i2c_pec_enable (uint32_t i2c_periph, uint32_t pecstate)
I2C PEC calculation on or off. More...
void | i2c_pec_transfer_enable (uint32_t i2c_periph, uint32_t pecpara)
I2C whether to transfer PEC value. More...
uint8_t | i2c_pec_value_get (uint32_t i2c_periph)
get packet error checking value More...
void | i2c_smbus_issue_alert (uint32_t i2c_periph, uint32_t smbuspara)
I2C issue alert through SMBA pin. More...
void | i2c_smbus_arp_enable (uint32_t i2c_periph, uint32_t arpstate)
enable or disable I2C ARP protocol in SMBus switch More...

Detailed Description

I2C driver.

Definition in file gd32f10x_i2c.c.

Macro Definition Documentation

#define I2C_FLAG_MASK 0x0000FFFFU

i2c flag mask

Definition at line 17 of file gd32f10x_i2c.c.

#define I2CCLK_MAX 0x3FU

i2cclk max value

Definition at line 16 of file gd32f10x_i2c.c.

Function Documentation

void i2c_ack_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | ack
 | ) |  |

whether or not to send an ACK

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] ack
  • I2C_ACK_ENABLE: ACK will be sent
  • I2C_ACK_DISABLE: ACK will not be sent
[out] | none
Return values
none

Definition at line 157 of file gd32f10x_i2c.c.

158 {
159 if(I2C_ACK_ENABLE == ack){
160 I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
161 }else{
162 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
163 }
164 }
I2C_CTL0_ACKEN
#define I2C_CTL0_ACKEN
Definition: gd32f10x_i2c.h:44
I2C_ACK_ENABLE
#define I2C_ACK_ENABLE
Definition: gd32f10x_i2c.h:119
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_ackpos_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | pos
 | ) |  |

I2C POAP position configure.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] pos
  • I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
  • I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
[out] | none
Return values
none

Definition at line 175 of file gd32f10x_i2c.c.

176 {
177 /* configure I2C POAP position */
178 if(I2C_ACKPOS_NEXT == pos){
179 I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
180 }else{
181 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
182 }
183 }
I2C_ACKPOS_NEXT
#define I2C_ACKPOS_NEXT
Definition: gd32f10x_i2c.h:122
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
I2C_CTL0_POAP
#define I2C_CTL0_POAP
Definition: gd32f10x_i2c.h:45
void i2c_clock_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | clkspeed,
 |  | uint32_t | dutycyc
 | ) |  |

I2C clock configure.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] | clkspeed | i2c clock speed
[in] dutycyc duty cycle in fast mode
  • I2C_DTCY_2: T_low/T_high=2
  • I2C_DTCY_16_9: T_low/T_high=16/9
[out] | none
Return values
none

Definition at line 51 of file gd32f10x_i2c.c.

52 {
53 uint32_t pclk1,clkc,freq,risetime;
54 uint32_t temp;
55
56 pclk1 = rcu_clock_freq_get(CK_APB1);
57 /* I2C peripheral clock frequency */
58 freq = (uint32_t)(pclk1/1000000U);
59 if(freq >= I2CCLK_MAX){
60 freq = I2CCLK_MAX;
61 }
62 temp = I2C_CTL1(i2c_periph);
63 temp &= ~I2C_CTL1_I2CCLK;
64 temp |= freq;
65
66 I2C_CTL1(i2c_periph) = temp;
67
68 if(100000U >= clkspeed){
69 /* the maximum SCL rise time is 1000ns in standard mode */
70 risetime = (uint32_t)((pclk1/1000000U)+1U);
71 if(risetime >= I2CCLK_MAX){
72 I2C_RT(i2c_periph) = I2CCLK_MAX;
73 }else{
74 I2C_RT(i2c_periph) = risetime;
75 }
76 clkc = (uint32_t)(pclk1/(clkspeed*2U));
77 if(clkc < 0x04U){
78 /* the CLKC in standard mode minmum value is 4 */
79 clkc = 0x04U;
80 }
81 I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
82
83 }else if(400000U >= clkspeed){
84 /* the maximum SCL rise time is 300ns in fast mode */
85 I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
86 if(I2C_DTCY_2 == dutycyc){
87 /* I2C duty cycle is 2 */
88 clkc = (uint32_t)(pclk1/(clkspeed*3U));
89 I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
90 }else{
91 /* I2C duty cycle is 16/9 */
92 clkc = (uint32_t)(pclk1/(clkspeed*25U));
93 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
94 }
95 if(0U == (clkc & I2C_CKCFG_CLKC)){
96 /* the CLKC in fast mode minmum value is 1 */
97 clkc |= 0x0001U;
98 }
99 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
100 I2C_CKCFG(i2c_periph) |= clkc;
101 }else{
102 }
103 }
I2C_DTCY_2
#define I2C_DTCY_2
Definition: gd32f10x_i2c.h:219
I2C_CKCFG_DTCY
#define I2C_CKCFG_DTCY
Definition: gd32f10x_i2c.h:99
I2C_CKCFG_FAST
#define I2C_CKCFG_FAST
Definition: gd32f10x_i2c.h:100
I2C_CKCFG_CLKC
#define I2C_CKCFG_CLKC
Definition: gd32f10x_i2c.h:98
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
I2C_RT
#define I2C_RT(i2cx)
Definition: gd32f10x_i2c.h:31
I2C_CTL1_I2CCLK
#define I2C_CTL1_I2CCLK
Definition: gd32f10x_i2c.h:51
I2C_CKCFG
#define I2C_CKCFG(i2cx)
Definition: gd32f10x_i2c.h:30
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
I2CCLK_MAX
#define I2CCLK_MAX
Definition: gd32f10x_i2c.c:16
CK_APB1
Definition: gd32f10x_rcu.h:586
uint8_t i2c_data_receive ( uint32_t i2c_periph )

I2C receive data function.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
data of received

Definition at line 285 of file gd32f10x_i2c.c.

286 {
287 return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
288 }
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f10x_i2c.h:27
DATA_RECV
#define DATA_RECV(regval)
Definition: gd32f10x_i2c.h:171
void i2c_data_transmit | ( | uint32_t | i2c_periph,
 |  | uint8_t | data
 | ) |  |

I2C transmit data function.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] | data | data of transmission
[out] | none
Return values
none

Definition at line 274 of file gd32f10x_i2c.c.

275 {
276 I2C_DATA(i2c_periph) = DATA_TRANS(data);
277 }
DATA_TRANS
#define DATA_TRANS(regval)
Definition: gd32f10x_i2c.h:168
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f10x_i2c.h:27
void i2c_deinit ( uint32_t i2c_periph )

reset I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 25 of file gd32f10x_i2c.c.

26 {
27 switch(i2c_periph){
28 case I2C0:
29 rcu_periph_reset_enable(RCU_I2C0RST);
30 rcu_periph_reset_disable(RCU_I2C0RST);
31 break;
32 case I2C1:
33 rcu_periph_reset_enable(RCU_I2C1RST);
34 rcu_periph_reset_disable(RCU_I2C1RST);
35 break;
36 default:
37 break;
38 }
39 }
RCU_I2C0RST
Definition: gd32f10x_rcu.h:463
RCU_I2C1RST
Definition: gd32f10x_rcu.h:464
I2C1
#define I2C1
Definition: gd32f10x_i2c.h:20
I2C0
#define I2C0
Definition: gd32f10x_i2c.h:19
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void i2c_disable ( uint32_t i2c_periph )

disable I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 240 of file gd32f10x_i2c.c.

241 {
242 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
243 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f10x_i2c.h:35
void i2c_dma_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dmastate
 | ) |  |

enable I2C DMA mode

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] dmastate
  • I2C_DMA_ON: DMA mode enable
  • I2C_DMA_OFF: DMA mode disable
[out] | none
Return values
none

Definition at line 299 of file gd32f10x_i2c.c.

300 {
301 /* configure I2C DMA function */
302 uint32_t ctl = 0U;
303 ctl = I2C_CTL1(i2c_periph);
304 ctl &= ~(I2C_CTL1_DMAON);
305 ctl |= dmastate;
306 I2C_CTL1(i2c_periph) = ctl;
307 }
I2C_CTL1_DMAON
#define I2C_CTL1_DMAON
Definition: gd32f10x_i2c.h:55
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
void i2c_dma_last_transfer_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dmalast
 | ) |  |

flag indicating DMA last transfer

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] dmalast
  • I2C_DMALST_ON: next DMA EOT is the last transfer
  • I2C_DMALST_OFF: next DMA EOT is not the last transfer
[out] | none
Return values
none

Definition at line 318 of file gd32f10x_i2c.c.

319 {
320 /* configure DMA last transfer */
321 uint32_t ctl = 0U;
322 ctl = I2C_CTL1(i2c_periph);
323 ctl &= ~(I2C_CTL1_DMALST);
324 ctl |= dmalast;
325 I2C_CTL1(i2c_periph) = ctl;
326 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
I2C_CTL1_DMALST
#define I2C_CTL1_DMALST
Definition: gd32f10x_i2c.h:56
void i2c_dualaddr_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dualaddr
 | ) |  |

dual-address mode switch

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] dualaddr
  • I2C_DUADEN_DISABLE: disable dual-address mode
  • I2C_DUADEN_ENABLE: enable dual-address mode
[out] | none
Return values
none

Definition at line 214 of file gd32f10x_i2c.c.

215 {
216 if(I2C_DUADEN_ENABLE == dualaddr){
217 I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
218 }else{
219 I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
220 }
221 }
I2C_SADDR1_DUADEN
#define I2C_SADDR1_DUADEN
Definition: gd32f10x_i2c.h:65
I2C_SADDR1
#define I2C_SADDR1(i2cx)
Definition: gd32f10x_i2c.h:26
I2C_DUADEN_ENABLE
#define I2C_DUADEN_ENABLE
Definition: gd32f10x_i2c.h:127
void i2c_enable ( uint32_t i2c_periph )

enable I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 229 of file gd32f10x_i2c.c.

230 {
231 I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
232 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f10x_i2c.h:35
void i2c_flag_clear | ( | uint32_t | i2c_periph,
 |  | uint32_t | flag
 | ) |  |

clear I2C flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] flag flag type
  • I2C_FLAG_SMBALT: SMBus Alert status
  • I2C_FLAG_SMBTO: timeout signal in SMBus mode
  • I2C_FLAG_PECERR: PEC error when receiving data
  • I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
  • I2C_FLAG_AERR: acknowledge error
  • I2C_FLAG_LOSTARB: arbitration lost in master mode
  • I2C_FLAG_BERR: a bus error
  • I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
[out] | none
Return values
none

Definition at line 451 of file gd32f10x_i2c.c.

452 {
453 if(I2C_FLAG_ADDSEND == flag){
454 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
455 I2C_STAT0(i2c_periph);
456 I2C_STAT1(i2c_periph);
457 }else{
458 I2C_STAT0(i2c_periph) &= ~(flag);
459 }
460 }
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f10x_i2c.h:29
I2C_FLAG_ADDSEND
#define I2C_FLAG_ADDSEND
Definition: gd32f10x_i2c.h:175
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f10x_i2c.h:28
FlagStatus i2c_flag_get | ( | uint32_t | i2c_periph,
 |  | uint32_t | flag
 | ) |  |

check I2C flag is set or not

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] flag
  • I2C_FLAG_SBSEND: start condition send out
  • I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
  • I2C_FLAG_BTC: byte transmission finishes
  • I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
  • I2C_FLAG_STPDET: stop condition detected in slave mode
  • I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
  • I2C_FLAG_TBE: I2C_DATA is empty during transmitting
  • I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
  • I2C_FLAG_LOSTARB: arbitration lost in master mode
  • I2C_FLAG_AERR: acknowledge error
  • I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
  • I2C_FLAG_PECERR: PEC error when receiving data
  • I2C_FLAG_SMBTO: timeout signal in SMBus mode
  • I2C_FLAG_SMBALT: SMBus alert status
  • I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
  • I2C_FLAG_I2CBSY: busy flag
  • I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver
  • I2C_FLAG_RXGC: general call address (00h) received
  • I2C_FLAG_DEFSMB: default address of SMBus device
  • I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
  • I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 413 of file gd32f10x_i2c.c.

414 {
415 uint32_t reg = 0U;
416 FlagStatus reval = RESET;
417 /* get the flag in which register */
418 reg = (BIT(31) & flag);
419 if((BIT(31) == reg)){
420 if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){
421 reval = SET;
422 }else{
423 reval = RESET;
424 }
425 }else{
426 if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){
427 reval = SET;
428 }else{
429 reval = RESET;
430 }
431 }
432 /* return the flag status */
433 return reval;
434 }
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f10x_i2c.h:29
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: gd32f10x_i2c.c:17
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f10x_i2c.h:28
void i2c_interrupt_disable | ( | uint32_t | i2c_periph,
 |  | uint32_t | inttype
 | ) |  |

disable I2C interrupt

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] inttype interrupt type
  • I2C_INT_ERR: error interrupt enable
  • I2C_INT_EV: event interrupt enable
  • I2C_INT_BUF: buffer interrupt enable
[out] | none
Return values
none

Definition at line 487 of file gd32f10x_i2c.c.

488 {
489 I2C_CTL1(i2c_periph) &= ~(inttype);
490 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
void i2c_interrupt_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | inttype
 | ) |  |

enable I2C interrupt

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] inttype interrupt type
  • I2C_INT_ERR: error interrupt enable
  • I2C_INT_EV: event interrupt enable
  • I2C_INT_BUF: buffer interrupt enable
[out] | none
Return values
none

Definition at line 472 of file gd32f10x_i2c.c.

473 {
474 I2C_CTL1(i2c_periph) |= (inttype);
475 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
void i2c_interrupt_flag_clear | ( | uint32_t | i2c_periph,
 |  | uint32_t | intflag
 | ) |  |

clear I2C interrupt flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] intflag interrupt flag
  • I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
  • I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
  • I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
  • I2C_INT_FLAG_AERR: acknowledge error interrupt flag
  • I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
  • I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
  • I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
  • I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
[out] | none
Return values
none

Definition at line 569 of file gd32f10x_i2c.c.

570 {
571 if(I2C_INT_FLAG_ADDSEND == intflag){
572 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
573 I2C_STAT0(i2c_periph);
574 I2C_STAT1(i2c_periph);
575 }else{
576 I2C_STAT0(i2c_periph) &= ~(intflag);
577 }
578 }
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f10x_i2c.h:29
I2C_INT_FLAG_ADDSEND
#define I2C_INT_FLAG_ADDSEND
Definition: gd32f10x_i2c.h:198
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f10x_i2c.h:28
FlagStatus i2c_interrupt_flag_get | ( | uint32_t | i2c_periph,
 |  | uint32_t | intflag
 | ) |  |

check I2C interrupt flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] int_flag interrupt flag
  • I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
  • I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
  • I2C_INT_FLAG_BTC: byte transmission finishes
  • I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
  • I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
  • I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
  • I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
  • I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
  • I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
  • I2C_INT_FLAG_AERR: acknowledge error interrupt flag
  • I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
  • I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
  • I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
  • I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
[out] | none
Return values
none

Definition at line 513 of file gd32f10x_i2c.c.

514 {
515 uint32_t evie, errie, bufie;
516
517 evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE;
518 errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE;
519 /* check I2C event interrupt enable bit */
520 if((intflag&0x00ffU) && evie){
521 if(intflag&0x001fU){
522 /* check I2C event flags except TBE and RBNE */
523 if(intflag & I2C_STAT0(i2c_periph)){
524 return SET;
525 }else{
526 return RESET;
527 }
528 }else{
529 /* check I2C event flags TBE and RBNE */
530 bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
531 if(bufie){
532 if(intflag & I2C_STAT0(i2c_periph)){
533 return SET;
534 }else{
535 return RESET;
536 }
537 }else{
538 return RESET;
539 }
540 }
541 /* check I2C error interrupt enable bit */
542 }else if((intflag&0xff00U) && errie){
543 /* check I2C error flags */
544 if(intflag & I2C_STAT0(i2c_periph)){
545 return SET;
546 }else{
547 return RESET;
548 }
549 }else{
550 return RESET;
551 }
552 }
I2C_CTL1_ERRIE
#define I2C_CTL1_ERRIE
Definition: gd32f10x_i2c.h:52
I2C_CTL1_BUFIE
#define I2C_CTL1_BUFIE
Definition: gd32f10x_i2c.h:54
I2C_CTL1_EVIE
#define I2C_CTL1_EVIE
Definition: gd32f10x_i2c.h:53
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f10x_i2c.h:28
void i2c_master_addressing | ( | uint32_t | i2c_periph,
 |  | uint32_t | addr,
 |  | uint32_t | trandirection
 | ) |  |

master send slave address

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] | addr | slave address
[in] trandirection transmitter or receiver
  • I2C_TRANSMITTER: transmitter
  • I2C_RECEIVER: receiver
[out] | none
Return values
none

Definition at line 195 of file gd32f10x_i2c.c.

196 {
197 if(I2C_TRANSMITTER == trandirection){
198 addr = addr & I2C_TRANSMITTER;
199 }else{
200 addr = addr | I2C_RECEIVER;
201 }
202 I2C_DATA(i2c_periph) = addr;
203 }
I2C_RECEIVER
#define I2C_RECEIVER
Definition: gd32f10x_i2c.h:114
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f10x_i2c.h:27
I2C_TRANSMITTER
#define I2C_TRANSMITTER
Definition: gd32f10x_i2c.h:115
void i2c_mode_addr_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | mode,
 |  | uint32_t | addformat,
 |  | uint32_t | addr
 | ) |  |

configure I2C address

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] i2cmod
  • I2C_I2CMODE_ENABLE: I2C mode
  • I2C_SMBUSMODE_ENABLE: SMBus mode
[in] addformat 7bits or 10bits
  • I2C_ADDFORMAT_7BITS: 7bits
  • I2C_ADDFORMAT_10BITS: 10bits
[in] | addr | I2C address
[out] | none
Return values
none

Definition at line 118 of file gd32f10x_i2c.c.

119 {
120 /* SMBus/I2C mode selected */
121 uint32_t ctl = 0U;
122 ctl = I2C_CTL0(i2c_periph);
123 ctl &= ~(I2C_CTL0_SMBEN);
124 ctl |= mode;
125 I2C_CTL0(i2c_periph) = ctl;
126 /* configure address */
127 I2C_SADDR0(i2c_periph) = (addformat | addr);
128 }
I2C_CTL0_SMBEN
#define I2C_CTL0_SMBEN
Definition: gd32f10x_i2c.h:36
I2C_SADDR0
#define I2C_SADDR0(i2cx)
Definition: gd32f10x_i2c.h:25
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_pec_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | pecstate
 | ) |  |

I2C PEC calculation on or off.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] pecpara
  • I2C_PEC_ENABLE: PEC calculation on
  • I2C_PEC_DISABLE: PEC calculation off
[out] | none
Return values
none

Definition at line 589 of file gd32f10x_i2c.c.

590 {
591 /* on/off PEC calculation */
592 uint32_t ctl = 0U;
593 ctl = I2C_CTL0(i2c_periph);
594 ctl &= ~(I2C_CTL0_PECEN);
595 ctl |= pecstate;
596 I2C_CTL0(i2c_periph) = ctl;
597 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
I2C_CTL0_PECEN
#define I2C_CTL0_PECEN
Definition: gd32f10x_i2c.h:39
void i2c_pec_transfer_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | pecpara
 | ) |  |

I2C whether to transfer PEC value.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] pecpara
  • I2C_PECTRANS_ENABLE: transfer PEC
  • I2C_PECTRANS_DISABLE: not transfer PEC
[out] | none
Return values
none

Definition at line 608 of file gd32f10x_i2c.c.

609 {
610 /* whether to transfer PEC */
611 uint32_t ctl = 0U;
612 ctl = I2C_CTL0(i2c_periph);
613 ctl &= ~(I2C_CTL0_PECTRANS);
614 ctl |= pecpara;
615 I2C_CTL0(i2c_periph) = ctl;
616 }
I2C_CTL0_PECTRANS
#define I2C_CTL0_PECTRANS
Definition: gd32f10x_i2c.h:46
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
uint8_t i2c_pec_value_get ( uint32_t i2c_periph )

get packet error checking value

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
PEC value

Definition at line 624 of file gd32f10x_i2c.c.

625 {
626 return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>8);
627 }
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f10x_i2c.h:29
I2C_STAT1_ECV
#define I2C_STAT1_ECV
Definition: gd32f10x_i2c.h:95
void i2c_slave_response_to_gcall_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | gcallpara
 | ) |  |

whether or not to response to a general call

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] gcallpara
  • I2C_GCEN_ENABLE: slave will response to a general call
  • I2C_GCEN_DISABLE: slave will not response to a general call
[out] | none
Return values
none

Definition at line 356 of file gd32f10x_i2c.c.

357 {
358 /* configure slave response to a general call enable or disable */
359 uint32_t ctl = 0U;
360 ctl = I2C_CTL0(i2c_periph);
361 ctl &= ~(I2C_CTL0_GCEN);
362 ctl |= gcallpara;
363 I2C_CTL0(i2c_periph) = ctl;
364 }
I2C_CTL0_GCEN
#define I2C_CTL0_GCEN
Definition: gd32f10x_i2c.h:40
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_smbus_arp_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | arpstate
 | ) |  |

enable or disable I2C ARP protocol in SMBus switch

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] smbuspara
  • I2C_ARP_ENABLE: enable ARP
  • I2C_ARP_DISABLE: disable ARP
[out] | none
Return values
none

Definition at line 657 of file gd32f10x_i2c.c.

658 {
659 /* enable or disable I2C ARP protocol*/
660 uint32_t ctl = 0U;
661 ctl = I2C_CTL0(i2c_periph);
662 ctl &= ~(I2C_CTL0_ARPEN);
663 ctl |= arpstate;
664 I2C_CTL0(i2c_periph) = ctl;
665 }
I2C_CTL0_ARPEN
#define I2C_CTL0_ARPEN
Definition: gd32f10x_i2c.h:38
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_smbus_issue_alert | ( | uint32_t | i2c_periph,
 |  | uint32_t | smbuspara
 | ) |  |

I2C issue alert through SMBA pin.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] smbuspara
  • I2C_SALTSEND_ENABLE: issue alert through SMBA pin
  • I2C_SALTSEND_DISABLE: not issue alert through SMBA pin
[out] | none
Return values
none

Definition at line 638 of file gd32f10x_i2c.c.

639 {
640 /* issue alert through SMBA pin configure*/
641 uint32_t ctl = 0U;
642 ctl = I2C_CTL0(i2c_periph);
643 ctl &= ~(I2C_CTL0_SALT);
644 ctl |= smbuspara;
645 I2C_CTL0(i2c_periph) = ctl;
646 }
I2C_CTL0_SALT
#define I2C_CTL0_SALT
Definition: gd32f10x_i2c.h:47
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_smbus_type_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | type
 | ) |  |

SMBus type selection.

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] ack
  • I2C_SMBUS_DEVICE: device
  • I2C_SMBUS_HOST: host
[out] | none
Return values
none

Definition at line 139 of file gd32f10x_i2c.c.

140 {
141 if(I2C_SMBUS_HOST == type){
142 I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
143 }else{
144 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
145 }
146 }
I2C_SMBUS_HOST
#define I2C_SMBUS_HOST
Definition: gd32f10x_i2c.h:112
I2C_CTL0_SMBSEL
#define I2C_CTL0_SMBSEL
Definition: gd32f10x_i2c.h:37
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_software_reset_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | sreset
 | ) |  |

software reset I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] sreset
  • I2C_SRESET_SET: I2C is under reset
  • I2C_SRESET_RESET: I2C is not under reset
[out] | none
Return values
none

Definition at line 375 of file gd32f10x_i2c.c.

376 {
377 /* modify CTL0 and configure software reset I2C state */
378 uint32_t ctl = 0U;
379 ctl = I2C_CTL0(i2c_periph);
380 ctl &= ~(I2C_CTL0_SRESET);
381 ctl |= sreset;
382 I2C_CTL0(i2c_periph) = ctl;
383 }
I2C_CTL0_SRESET
#define I2C_CTL0_SRESET
Definition: gd32f10x_i2c.h:48
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_start_on_bus ( uint32_t i2c_periph )

generate a START condition on I2C bus

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 251 of file gd32f10x_i2c.c.

252 {
253 I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
254 }
I2C_CTL0_START
#define I2C_CTL0_START
Definition: gd32f10x_i2c.h:42
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_stop_on_bus ( uint32_t i2c_periph )

generate a STOP condition on I2C bus

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[out] | none
Return values
none

Definition at line 262 of file gd32f10x_i2c.c.

263 {
264 I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
265 }
I2C_CTL0_STOP
#define I2C_CTL0_STOP
Definition: gd32f10x_i2c.h:43
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
void i2c_stretch_scl_low_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | stretchpara
 | ) |  |

whether to stretch SCL low when data is not ready in slave mode

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] stretchpara
  • I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
  • I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
[out] | none
Return values
none

Definition at line 337 of file gd32f10x_i2c.c.

338 {
339 /* configure I2C SCL strerching enable or disable */
340 uint32_t ctl = 0U;
341 ctl = I2C_CTL0(i2c_periph);
342 ctl &= ~(I2C_CTL0_DISSTRC);
343 ctl |= stretchpara;
344 I2C_CTL0(i2c_periph) = ctl;
345 }
I2C_CTL0_DISSTRC
#define I2C_CTL0_DISSTRC
Definition: gd32f10x_i2c.h:41
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_misc.c File Reference

MISC driver. More...

#include "gd32f10x_misc.h"

Go to the source code of this file.

Functions

void | nvic_priority_group_set (uint32_t nvic_prigroup)
set the priority group More...
void | nvic_irq_enable (uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority)
enable NVIC request More...
void | nvic_irq_disable (uint8_t nvic_irq)
disable NVIC request More...
void | nvic_vector_table_set (uint32_t nvic_vict_tab, uint32_t offset)
set the NVIC vector table base address More...
void | system_lowpower_set (uint8_t lowpower_mode)
set the state of the low power mode More...
void | system_lowpower_reset (uint8_t lowpower_mode)
reset the state of the low power mode More...
void | systick_clksource_set (uint32_t systick_clksource)
set the systick clock source More...

Detailed Description

MISC driver.

Definition in file gd32f10x_misc.c.

Function Documentation

void nvic_irq_disable ( uint8_t nvic_irq )

disable NVIC request

Parameters
[in] | nvic_irq | the NVIC interrupt request, detailed in IRQn_Type
[out] | none
Return values
none

Definition at line 77 of file gd32f10x_misc.c.

78 {
79 /* disable the selected IRQ.*/
80 NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
81 }
void nvic_irq_enable | ( | uint8_t | nvic_irq,
 |  | uint8_t | nvic_irq_pre_priority,
 |  | uint8_t | nvic_irq_sub_priority
 | ) |  |

enable NVIC request

Parameters
[in] | nvic_irq | the NVIC interrupt request, detailed in IRQn_Type
[in] | nvic_irq_pre_priority | the pre-emption priority needed to set
[in] | nvic_irq_sub_priority | the subpriority needed to set
[out] | none
Return values
none

Definition at line 40 of file gd32f10x_misc.c.

42 {
43 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
44 /* use the priority group value to get the temp_pre and the temp_sub */
45 if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
46 temp_pre=0U;
47 temp_sub=0x4U;
48 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
49 temp_pre=1U;
50 temp_sub=0x3U;
51 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
52 temp_pre=2U;
53 temp_sub=0x2U;
54 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
55 temp_pre=3U;
56 temp_sub=0x1U;
57 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
58 temp_pre=4U;
59 temp_sub=0x0U;
60 }else{
61 }
62 /* get the temp_priority to fill the NVIC->IP register */
63 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
64 temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
65 temp_priority = temp_priority << 0x04U;
66 NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
67 /* enable the selected IRQ */
68 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
69 }
NVIC_PRIGROUP_PRE2_SUB2
#define NVIC_PRIGROUP_PRE2_SUB2
Definition: gd32f10x_misc.h:32
NVIC_PRIGROUP_PRE3_SUB1
#define NVIC_PRIGROUP_PRE3_SUB1
Definition: gd32f10x_misc.h:33
NVIC_PRIGROUP_PRE0_SUB4
#define NVIC_PRIGROUP_PRE0_SUB4
Definition: gd32f10x_misc.h:30
NVIC_PRIGROUP_PRE1_SUB3
#define NVIC_PRIGROUP_PRE1_SUB3
Definition: gd32f10x_misc.h:31
NVIC_PRIGROUP_PRE4_SUB0
#define NVIC_PRIGROUP_PRE4_SUB0
Definition: gd32f10x_misc.h:34
void nvic_priority_group_set ( uint32_t nvic_prigroup )

set the priority group

Parameters
[in] nvic_prigroup the NVIC priority group
  • NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
  • NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
  • NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
  • NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
  • NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
[out] none
Return values
none

Definition at line 26 of file gd32f10x_misc.c.

27 {
28 /* set the priority group value */
29 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
30 }
NVIC_AIRCR_VECTKEY_MASK
#define NVIC_AIRCR_VECTKEY_MASK
Definition: gd32f10x_misc.h:27
void nvic_vector_table_set | ( | uint32_t | nvic_vict_tab,
 |  | uint32_t | offset
 | ) |  |

set the NVIC vector table base address

Parameters
[in] nvic_vict_tab the RAM or FLASH base address
  • NVIC_VECTTAB_RAM: RAM base address NVIC_VECTTAB_FLASH: Flash base address
[in] | offset | Vector Table offset
[out] | none
Return values
none

Definition at line 92 of file gd32f10x_misc.c.

93 {
94 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
95 }
NVIC_VECTTAB_OFFSET_MASK
#define NVIC_VECTTAB_OFFSET_MASK
Definition: gd32f10x_misc.h:24
void system_lowpower_reset ( uint8_t lowpower_mode )

reset the state of the low power mode

Parameters
[in] lowpower_mode the low power mode state
  • SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power mode by exiting from ISR
  • SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
  • SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be woke up by the enable interrupts
[out] none
Return values
none

Definition at line 124 of file gd32f10x_misc.c.

125 {
126 SCB->SCR &= (~(uint32_t)lowpower_mode);
127 }
void system_lowpower_set ( uint8_t lowpower_mode )

set the state of the low power mode

Parameters
[in] lowpower_mode the low power mode state
  • SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power mode by exiting from ISR
  • SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
  • SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up by all the enable and disable interrupts
[out] none
Return values
none

Definition at line 108 of file gd32f10x_misc.c.

109 {
110 SCB->SCR |= (uint32_t)lowpower_mode;
111 }
void systick_clksource_set ( uint32_t systick_clksource )

set the systick clock source

Parameters
[in] systick_clksource the systick clock source needed to choose
  • SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
  • SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
[out] none
Return values
none

Definition at line 138 of file gd32f10x_misc.c.

139 {
140 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
141 /* set the systick clock source from HCLK */
142 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
143 }else{
144 /* set the systick clock source from HCLK/8 */
145 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
146 }
147 }
SYSTICK_CLKSOURCE_HCLK_DIV8
#define SYSTICK_CLKSOURCE_HCLK_DIV8
Definition: gd32f10x_misc.h:46
SYSTICK_CLKSOURCE_HCLK
#define SYSTICK_CLKSOURCE_HCLK
Definition: gd32f10x_misc.h:47
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_pmu.c File Reference

PMU driver. More...

#include "gd32f10x_pmu.h"

Go to the source code of this file.

Functions

void | pmu_deinit (void)
reset PMU register More...
void | pmu_lvd_select (uint32_t lvdt_n)
select low voltage detector threshold More...
void | pmu_lvd_disable (void)
disable PMU lvd More...
void | pmu_to_sleepmode (uint8_t sleepmodecmd)
PMU work at sleep mode. More...
void | pmu_to_deepsleepmode (uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode. More...
void | pmu_to_standbymode (uint8_t standbymodecmd)
pmu work at standby mode More...
void | pmu_flag_clear (uint32_t flag_reset)
clear flag bit More...
FlagStatus | pmu_flag_get (uint32_t flag)
get flag state More...
void | pmu_backup_write_enable (void)
enable backup domain write More...
void | pmu_backup_write_disable (void)
disable backup domain write More...
void | pmu_wakeup_pin_enable (void)
enable wakeup pin More...
void | pmu_wakeup_pin_disable (void)
disable wakeup pin More...

Detailed Description

PMU driver.

Definition in file gd32f10x_pmu.c.

Function Documentation

void pmu_backup_write_disable ( void )

disable backup domain write

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 207 of file gd32f10x_pmu.c.

208 {
209 PMU_CTL &= ~PMU_CTL_BKPWEN;
210 }
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f10x_pmu.h:33
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_backup_write_enable ( void )

enable backup domain write

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 196 of file gd32f10x_pmu.c.

197 {
198 PMU_CTL |= PMU_CTL_BKPWEN;
199 }
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f10x_pmu.h:33
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_deinit ( void )

reset PMU register

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_pmu.c.

22 {
23 /* reset PMU */
24 rcu_periph_reset_enable(RCU_PMURST);
25 rcu_periph_reset_disable(RCU_PMURST);
26 }
RCU_PMURST
Definition: gd32f10x_rcu.h:473
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void pmu_flag_clear ( uint32_t flag_reset )

clear flag bit

Parameters
[in] flag_reset
  • PMU_FLAG_RESET_WAKEUP: reset wakeup flag
  • PMU_FLAG_RESET_STANDBY: reset standby flag
[out] none
Return values
none

Definition at line 156 of file gd32f10x_pmu.c.

157 {
158 switch(flag_reset){
159 case PMU_FLAG_RESET_WAKEUP:
160 /* reset wakeup flag */
161 PMU_CTL |= PMU_CTL_WURST;
162 break;
163 case PMU_FLAG_RESET_STANDBY:
164 /* reset standby flag */
165 PMU_CTL |= PMU_CTL_STBRST;
166 break;
167 default :
168 break;
169 }
170 }
PMU_FLAG_RESET_STANDBY
#define PMU_FLAG_RESET_STANDBY
Definition: gd32f10x_pmu.h:64
PMU_FLAG_RESET_WAKEUP
#define PMU_FLAG_RESET_WAKEUP
Definition: gd32f10x_pmu.h:63
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f10x_pmu.h:29
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
PMU_CTL_STBRST
#define PMU_CTL_STBRST
Definition: gd32f10x_pmu.h:30
FlagStatus pmu_flag_get ( uint32_t flag )

get flag state

Parameters
[in] flag
  • PMU_FLAG_WAKEUP: wakeup flag
  • PMU_FLAG_STANDBY: standby flag
  • PMU_FLAG_LVD: lvd flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 181 of file gd32f10x_pmu.c.

182 {
183 if(PMU_CS & flag){
184 return SET;
185 }else{
186 return RESET;
187 }
188 }
PMU_CS
#define PMU_CS
Definition: gd32f10x_pmu.h:23
void pmu_lvd_disable ( void )

disable PMU lvd

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 60 of file gd32f10x_pmu.c.

61 {
62 /* disable LVD */
63 PMU_CTL &= ~PMU_CTL_LVDEN;
64 }
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f10x_pmu.h:31
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_lvd_select ( uint32_t lvdt_n )

select low voltage detector threshold

Parameters
[in] lvdt_n
  • PMU_LVDT_0: voltage threshold is 2.2V
  • PMU_LVDT_1: voltage threshold is 2.3V
  • PMU_LVDT_2: voltage threshold is 2.4V
  • PMU_LVDT_3: voltage threshold is 2.5V
  • PMU_LVDT_4: voltage threshold is 2.6V
  • PMU_LVDT_5: voltage threshold is 2.7V
  • PMU_LVDT_6: voltage threshold is 2.8V
  • PMU_LVDT_7: voltage threshold is 2.9V
[out] none
Return values
none

Definition at line 42 of file gd32f10x_pmu.c.

43 {
44 /* disable LVD */
45 PMU_CTL &= ~PMU_CTL_LVDEN;
46 /* clear LVDT bits */
47 PMU_CTL &= ~PMU_CTL_LVDT;
48 /* set LVDT bits according to lvdt_n */
49 PMU_CTL |= lvdt_n;
50 /* enable LVD */
51 PMU_CTL |= PMU_CTL_LVDEN;
52 }
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f10x_pmu.h:31
PMU_CTL_LVDT
#define PMU_CTL_LVDT
Definition: gd32f10x_pmu.h:32
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_to_deepsleepmode | ( | uint32_t | ldo,
 |  | uint8_t | deepsleepmodecmd
 | ) |  |

PMU work at deepsleep mode.

Parameters
[in] ldo
  • PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode
  • PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
[in] deepsleepmodecmd
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 98 of file gd32f10x_pmu.c.

99 {
100 /* clear stbmod and ldolp bits */
101 PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
102
103 /* set ldolp bit according to pmu_ldo */
104 PMU_CTL |= ldo;
105
106 /* set sleepdeep bit of Cortex-M3 system control register */
107 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
108
109 /* select WFI or WFE command to enter deepsleep mode */
110 if(WFI_CMD == deepsleepmodecmd){
111 __WFI();
112 }else{
113 __SEV();
114 __WFE();
115 __WFE();
116 }
117 /* reset sleepdeep bit of Cortex-M3 system control register */
118 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
119 }
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f10x_pmu.h:28
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
PMU_CTL_LDOLP
#define PMU_CTL_LDOLP
Definition: gd32f10x_pmu.h:27
void pmu_to_sleepmode ( uint8_t sleepmodecmd )

PMU work at sleep mode.

Parameters
[in] sleepmodecmd
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 74 of file gd32f10x_pmu.c.

75 {
76 /* clear sleepdeep bit of Cortex-M3 system control register */
77 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
78
79 /* select WFI or WFE command to enter sleep mode */
80 if(WFI_CMD == sleepmodecmd){
81 __WFI();
82 }else{
83 __WFE();
84 }
85 }
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
void pmu_to_standbymode ( uint8_t standbymodecmd )

pmu work at standby mode

Parameters
[in] standbymodecmd
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 129 of file gd32f10x_pmu.c.

130 {
131 /* set sleepdeep bit of Cortex-M3 system control register */
132 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
133
134 /* set stbmod bit */
135 PMU_CTL |= PMU_CTL_STBMOD;
136
137 /* reset wakeup flag */
138 PMU_CTL |= PMU_CTL_WURST;
139
140 /* select WFI or WFE command to enter standby mode */
141 if(WFI_CMD == standbymodecmd){
142 __WFI();
143 }else{
144 __WFE();
145 }
146 }
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f10x_pmu.h:28
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f10x_pmu.h:29
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
void pmu_wakeup_pin_disable ( void )

disable wakeup pin

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 229 of file gd32f10x_pmu.c.

230 {
231 PMU_CS &= ~PMU_CS_WUPEN;
232 }
PMU_CS_WUPEN
#define PMU_CS_WUPEN
Definition: gd32f10x_pmu.h:39
PMU_CS
#define PMU_CS
Definition: gd32f10x_pmu.h:23
void pmu_wakeup_pin_enable ( void )

enable wakeup pin

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 218 of file gd32f10x_pmu.c.

219 {
220 PMU_CS |= PMU_CS_WUPEN;
221 }
PMU_CS_WUPEN
#define PMU_CS_WUPEN
Definition: gd32f10x_pmu.h:39
PMU_CS
#define PMU_CS
Definition: gd32f10x_pmu.h:23
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_rcu.c File Reference

RCU driver. More...

#include "gd32f10x_rcu.h"

Go to the source code of this file.

Macros

#define | SEL_IRC8M ((uint16_t)0U)
#define | SEL_HXTAL ((uint16_t)1U)
#define | SEL_PLL ((uint16_t)2U)
#define | OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)
#define | LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)

Functions

void | rcu_deinit (void)
deinitialize the RCU More...
void | rcu_periph_clock_enable (rcu_periph_enum periph)
enable the peripherals clock More...
void | rcu_periph_clock_disable (rcu_periph_enum periph)
disable the peripherals clock More...
void | rcu_periph_clock_sleep_enable (rcu_periph_sleep_enum periph)
enable the peripherals clock when sleep mode More...
void | rcu_periph_clock_sleep_disable (rcu_periph_sleep_enum periph)
disable the peripherals clock when sleep mode More...
void | rcu_periph_reset_enable (rcu_periph_reset_enum periph_reset)
reset the peripherals More...
void | rcu_periph_reset_disable (rcu_periph_reset_enum periph_reset)
disable reset the peripheral More...
void | rcu_bkp_reset_enable (void)
reset the BKP domain More...
void | rcu_bkp_reset_disable (void)
disable the BKP domain reset More...
void | rcu_system_clock_source_config (uint32_t ck_sys)
configure the system clock source More...
uint32_t | rcu_system_clock_source_get (void)
get the system clock source More...
void | rcu_ahb_clock_config (uint32_t ck_ahb)
configure the AHB clock prescaler selection More...
void | rcu_apb1_clock_config (uint32_t ck_apb1)
configure the APB1 clock prescaler selection More...
void | rcu_apb2_clock_config (uint32_t ck_apb2)
configure the APB2 clock prescaler selection More...
void | rcu_ckout0_config (uint32_t ckout0_src)
configure the CK_OUT0 clock source More...
void | rcu_pll_config (uint32_t pll_src, uint32_t pll_mul)
configure the main PLL clock More...
void | rcu_predv0_config (uint32_t predv0_div)
configure the PREDV0 division factor More...
void | rcu_adc_clock_config (uint32_t adc_psc)
configure the ADC prescaler factor More...
void | rcu_usb_clock_config (uint32_t usb_psc)
configure the USBD/USBFS prescaler factor More...
void | rcu_rtc_clock_config (uint32_t rtc_clock_source)
configure the RTC clock source selection More...
void | rcu_i2s1_clock_config (uint32_t i2s_clock_source)
configure the I2S1 clock source selection More...
void | rcu_i2s2_clock_config (uint32_t i2s_clock_source)
configure the I2S2 clock source selection More...
FlagStatus | rcu_flag_get (rcu_flag_enum flag)
get the clock stabilization and periphral reset flags More...
void | rcu_all_reset_flag_clear (void)
clear all the reset flag More...
FlagStatus | rcu_interrupt_flag_get (rcu_int_flag_enum int_flag)
get the clock stabilization interrupt and ckm flags More...
void | rcu_interrupt_flag_clear (rcu_int_flag_clear_enum int_flag_clear)
clear the interrupt flags More...
void | rcu_interrupt_enable (rcu_int_enum stab_int)
enable the stabilization interrupt More...
void | rcu_interrupt_disable (rcu_int_enum stab_int)
disable the stabilization interrupt More...
ErrStatus | rcu_osci_stab_wait (rcu_osci_type_enum osci)
wait for oscillator stabilization flags is SET or oscillator startup is timeout More...
void | rcu_osci_on (rcu_osci_type_enum osci)
turn on the oscillator More...
void | rcu_osci_off (rcu_osci_type_enum osci)
turn off the oscillator More...
void | rcu_osci_bypass_mode_enable (rcu_osci_type_enum osci)
enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it More...
void | rcu_osci_bypass_mode_disable (rcu_osci_type_enum osci)
disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it More...
void | rcu_hxtal_clock_monitor_enable (void)
enable the HXTAL clock monitor More...
void | rcu_hxtal_clock_monitor_disable (void)
disable the HXTAL clock monitor More...
void | rcu_irc8m_adjust_value_set (uint32_t irc8m_adjval)
set the IRC8M adjust value More...
void | rcu_deepsleep_voltage_set (uint32_t dsvol)
deep-sleep mode voltage select More...
uint32_t | rcu_clock_freq_get (rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency More...

Detailed Description

RCU driver.

Definition in file gd32f10x_rcu.c.

Macro Definition Documentation

#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)

Definition at line 22 of file gd32f10x_rcu.c.

#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)

Definition at line 21 of file gd32f10x_rcu.c.

#define SEL_HXTAL ((uint16_t)1U)

Definition at line 17 of file gd32f10x_rcu.c.

#define SEL_IRC8M ((uint16_t)0U)

Definition at line 16 of file gd32f10x_rcu.c.

#define SEL_PLL ((uint16_t)2U)

Definition at line 18 of file gd32f10x_rcu.c.

Function Documentation

void rcu_adc_clock_config ( uint32_t adc_psc )

configure the ADC prescaler factor

Parameters
[in] adc_psc ADC prescaler factor
  • RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2
  • RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4
  • RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6
  • RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8
  • RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12
  • RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16
[out] none
Return values
none

Definition at line 493 of file gd32f10x_rcu.c.

494 {
495 uint32_t reg0;
496
497 /* reset the ADCPSC bits */
498 reg0 = RCU_CFG0;
499 reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC);
500
501 /* set the ADC prescaler factor */
502 switch(adc_psc){
503 case RCU_CKADC_CKAPB2_DIV2:
504 case RCU_CKADC_CKAPB2_DIV4:
505 case RCU_CKADC_CKAPB2_DIV6:
506 case RCU_CKADC_CKAPB2_DIV8:
507 reg0 |= (adc_psc << 14);
508 break;
509
510 case RCU_CKADC_CKAPB2_DIV12:
511 case RCU_CKADC_CKAPB2_DIV16:
512 adc_psc &= ~BIT(2);
513 reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2);
514 break;
515
516 default:
517 break;
518 }
519
520 /* set the register */
521 RCU_CFG0 = reg0;
522 }
RCU_CKADC_CKAPB2_DIV8
#define RCU_CKADC_CKAPB2_DIV8
Definition: gd32f10x_rcu.h:635
RCU_CKADC_CKAPB2_DIV2
#define RCU_CKADC_CKAPB2_DIV2
Definition: gd32f10x_rcu.h:632
RCU_CFG0_ADCPSC_2
#define RCU_CFG0_ADCPSC_2
Definition: gd32f10x_rcu.h:94
RCU_CKADC_CKAPB2_DIV4
#define RCU_CKADC_CKAPB2_DIV4
Definition: gd32f10x_rcu.h:633
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f10x_rcu.h:87
RCU_CKADC_CKAPB2_DIV16
#define RCU_CKADC_CKAPB2_DIV16
Definition: gd32f10x_rcu.h:637
RCU_CKADC_CKAPB2_DIV12
#define RCU_CKADC_CKAPB2_DIV12
Definition: gd32f10x_rcu.h:636
RCU_CKADC_CKAPB2_DIV6
#define RCU_CKADC_CKAPB2_DIV6
Definition: gd32f10x_rcu.h:634
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_ahb_clock_config ( uint32_t ck_ahb )

configure the AHB clock prescaler selection

Parameters
[in] ck_ahb AHB clock prescaler selection only one parameter can be selected which is shown as below:
  • RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
[out] none
Return values
none

Definition at line 281 of file gd32f10x_rcu.c.

282 {
283 uint32_t reg;
284
285 reg = RCU_CFG0;
286
287 /* reset the AHBPSC bits and set according to ck_ahb */
288 reg &= ~RCU_CFG0_AHBPSC;
289 RCU_CFG0 = (reg | ck_ahb);
290 }
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f10x_rcu.h:84
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_all_reset_flag_clear ( void )

clear all the reset flag

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 647 of file gd32f10x_rcu.c.

648 {
649 RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
650 }
RCU_RSTSCK_RSTFC
#define RCU_RSTSCK_RSTFC
Definition: gd32f10x_rcu.h:295
RCU_RSTSCK
#define RCU_RSTSCK
Definition: gd32f10x_rcu.h:32
void rcu_apb1_clock_config ( uint32_t ck_apb1 )

configure the APB1 clock prescaler selection

Parameters
[in] ck_apb1 APB1 clock prescaler selection only one parameter can be selected which is shown as below:
  • RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
  • RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
  • RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
  • RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
  • RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
[out] none
Return values
none

Definition at line 304 of file gd32f10x_rcu.c.

305 {
306 uint32_t reg;
307
308 reg = RCU_CFG0;
309
310 /* reset the APB1PSC and set according to ck_apb1 */
311 reg &= ~RCU_CFG0_APB1PSC;
312 RCU_CFG0 = (reg | ck_apb1);
313 }
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f10x_rcu.h:85
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_apb2_clock_config ( uint32_t ck_apb2 )

configure the APB2 clock prescaler selection

Parameters
[in] ck_apb2 APB2 clock prescaler selection only one parameter can be selected which is shown as below:
  • RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
  • RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
  • RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
  • RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
  • RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
[out] none
Return values
none

Definition at line 327 of file gd32f10x_rcu.c.

328 {
329 uint32_t reg;
330
331 reg = RCU_CFG0;
332
333 /* reset the APB2PSC and set according to ck_apb2 */
334 reg &= ~RCU_CFG0_APB2PSC;
335 RCU_CFG0 = (reg | ck_apb2);
336 }
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f10x_rcu.h:86
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_bkp_reset_disable ( void )

disable the BKP domain reset

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 234 of file gd32f10x_rcu.c.

235 {
236 RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
237 }
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f10x_rcu.h:290
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
void rcu_bkp_reset_enable ( void )

reset the BKP domain

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 223 of file gd32f10x_rcu.c.

224 {
225 RCU_BDCTL |= RCU_BDCTL_BKPRST;
226 }
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f10x_rcu.h:290
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
void rcu_ckout0_config ( uint32_t ckout0_src )

configure the CK_OUT0 clock source

Parameters
[in] ckout0_src CK_OUT0 clock source selection only one parameter can be selected which is shown as below:
  • RCU_CKOUT0SRC_NONE: no clock selected
  • RCU_CKOUT0SRC_CKSYS: system clock selected
  • RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected
  • RCU_CKOUT0SRC_HXTAL: HXTAL selected
  • RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected
  • RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected
  • RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected
  • RCU_CKOUT0SRC_EXT1: EXT1 selected
  • RCU_CKOUT0SRC_CKPLL2: PLL selected
[out] none
Return values
none

Definition at line 354 of file gd32f10x_rcu.c.

355 {
356 uint32_t reg;
357
358 reg = RCU_CFG0;
359
360 /* reset the CKOUT0SRC, set according to ckout0_src */
361 reg &= ~RCU_CFG0_CKOUT0SEL;
362 RCU_CFG0 = (reg | ckout0_src);
363 }
RCU_CFG0_CKOUT0SEL
#define RCU_CFG0_CKOUT0SEL
Definition: gd32f10x_rcu.h:92
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
uint32_t rcu_clock_freq_get ( rcu_clock_freq_enum clock )

get the system clock, bus and peripheral clock frequency

Parameters
[in] clock the clock frequency which to get only one parameter can be selected which is shown as below:
  • CK_SYS: system clock frequency
  • CK_AHB: AHB clock frequency
  • CK_APB1: APB1 clock frequency
  • CK_APB2: APB2 clock frequency
[out] none
Return values
clock frequency of system, AHB, APB1, APB2

Definition at line 1039 of file gd32f10x_rcu.c.

1040 {
1041 uint32_t sws, ck_freq = 0U;
1042 uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq;
1043 uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp;
1044 #ifdef GD32F10X_CL
1045 uint32_t predv0, predv1, pll1mf;
1046 #endif /* GD32F10X_CL */
1047
1048 /* exponent of AHB, APB1 and APB2 clock divider */
1049 uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
1050 uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
1051 uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
1052
1053 sws = GET_BITS(RCU_CFG0, 2, 3);
1054 switch(sws){
1055 /* IRC8M is selected as CK_SYS */
1056 case SEL_IRC8M:
1057 cksys_freq = IRC8M_VALUE;
1058 break;
1059 /* HXTAL is selected as CK_SYS */
1060 case SEL_HXTAL:
1061 cksys_freq = HXTAL_VALUE;
1062 break;
1063 /* PLL is selected as CK_SYS */
1064 case SEL_PLL:
1065 /* PLL clock source selection, HXTAL or IRC8M/2 */
1066 pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
1067
1068 if(RCU_PLLSRC_HXTAL == pllsel) {
1069 /* PLL clock source is HXTAL */
1070 ck_src = HXTAL_VALUE;
1071
1072 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
1073 predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0);
1074 /* PREDV0 input source clock divided by 2 */
1075 if(RCU_CFG0_PREDV0 == predv0sel){
1076 ck_src = HXTAL_VALUE/2U;
1077 }
1078 #elif defined(GD32F10X_CL)
1079 predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
1080 /* source clock use PLL1 */
1081 if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
1082 predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
1083 pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
1084 if(17U == pll1mf){
1085 pll1mf = 20U;
1086 }
1087 ck_src = (ck_src / predv1) * pll1mf;
1088 }
1089 predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
1090 ck_src /= predv0;
1091 #endif /* GD32F10X_HD and GD32F10X_XD */
1092 }else{
1093 /* PLL clock source is IRC8M/2 */
1094 ck_src = IRC8M_VALUE/2U;
1095 }
1096
1097 /* PLL multiplication factor */
1098 pllmf = GET_BITS(RCU_CFG0, 18, 21);
1099 if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
1100 pllmf |= 0x10U;
1101 }
1102 if(pllmf < 15U){
1103 pllmf += 2U;
1104 }else{
1105 pllmf += 1U;
1106 }
1107
1108 cksys_freq = ck_src * pllmf;
1109
1110 #ifdef GD32F10X_CL
1111 if(15U == pllmf){
1112 /* PLL source clock multiply by 6.5 */
1113 cksys_freq = ck_src * 6U + ck_src / 2U;
1114 }
1115 #endif /* GD32F10X_CL */
1116
1117 break;
1118 /* IRC8M is selected as CK_SYS */
1119 default:
1120 cksys_freq = IRC8M_VALUE;
1121 break;
1122 }
1123
1124 /* calculate AHB clock frequency */
1125 idx = GET_BITS(RCU_CFG0, 4, 7);
1126 clk_exp = ahb_exp[idx];
1127 ahb_freq = cksys_freq >> clk_exp;
1128
1129 /* calculate APB1 clock frequency */
1130 idx = GET_BITS(RCU_CFG0, 8, 10);
1131 clk_exp = apb1_exp[idx];
1132 apb1_freq = ahb_freq >> clk_exp;
1133
1134 /* calculate APB2 clock frequency */
1135 idx = GET_BITS(RCU_CFG0, 11, 13);
1136 clk_exp = apb2_exp[idx];
1137 apb2_freq = ahb_freq >> clk_exp;
1138
1139 /* return the clocks frequency */
1140 switch(clock){
1141 case CK_SYS:
1142 ck_freq = cksys_freq;
1143 break;
1144 case CK_AHB:
1145 ck_freq = ahb_freq;
1146 break;
1147 case CK_APB1:
1148 ck_freq = apb1_freq;
1149 break;
1150 case CK_APB2:
1151 ck_freq = apb2_freq;
1152 break;
1153 default:
1154 break;
1155 }
1156 return ck_freq;
1157 }
SEL_HXTAL
#define SEL_HXTAL
Definition: gd32f10x_rcu.c:17
RCU_CFG0_PREDV0
#define RCU_CFG0_PREDV0
Definition: gd32f10x_rcu.h:89
SEL_IRC8M
#define SEL_IRC8M
Definition: gd32f10x_rcu.c:16
RCU_PLLSRC_HXTAL
#define RCU_PLLSRC_HXTAL
Definition: gd32f10x_rcu.h:641
CK_SYS
Definition: gd32f10x_rcu.h:584
RCU_PREDV0SRC_CKPLL1
#define RCU_PREDV0SRC_CKPLL1
Definition: gd32f10x_rcu.h:778
RCU_CFG1_PREDV0
#define RCU_CFG1_PREDV0
Definition: gd32f10x_rcu.h:311
RCU_CFG1_PREDV1
#define RCU_CFG1_PREDV1
Definition: gd32f10x_rcu.h:312
RCU_CFG1_PLL1MF
#define RCU_CFG1_PLL1MF
Definition: gd32f10x_rcu.h:313
CK_APB2
Definition: gd32f10x_rcu.h:587
CK_AHB
Definition: gd32f10x_rcu.h:585
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f10x_rcu.h:88
SEL_PLL
#define SEL_PLL
Definition: gd32f10x_rcu.c:18
RCU_CFG0_PLLMF_4
#define RCU_CFG0_PLLMF_4
Definition: gd32f10x_rcu.h:93
CK_APB1
Definition: gd32f10x_rcu.h:586
RCU_CFG1_PREDV0SEL
#define RCU_CFG1_PREDV0SEL
Definition: gd32f10x_rcu.h:315
void rcu_deepsleep_voltage_set ( uint32_t dsvol )

deep-sleep mode voltage select

Parameters
[in] dsvol deep sleep mode voltage only one parameter can be selected which is shown as below:
  • RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V
  • RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V
  • RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
  • RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
[out] none
Return values
none

Definition at line 1022 of file gd32f10x_rcu.c.

1023 {
1024 dsvol &= RCU_DSV_DSLPVS;
1025 RCU_DSV = dsvol;
1026 }
RCU_DSV
#define RCU_DSV
Definition: gd32f10x_rcu.h:33
RCU_DSV_DSLPVS
#define RCU_DSV_DSLPVS
Definition: gd32f10x_rcu.h:321
void rcu_deinit ( void )

deinitialize the RCU

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 30 of file gd32f10x_rcu.c.

31 {
32 /* enable IRC8M */
33 RCU_CTL |= RCU_CTL_IRC8MEN;
34 rcu_osci_stab_wait(RCU_IRC8M);
35
36 /* reset CFG0 register */
37 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
38 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
39 RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF |
40 RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2);
41 #elif defined(GD32F10X_CL)
42 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
43 RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
44 RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4);
45 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
46 /* reset CTL register */
47 RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
48 RCU_CTL &= ~RCU_CTL_HXTALBPS;
49 #ifdef GD32F10X_CL
50 RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN);
51 #endif /* GD32F10X_CL */
52
53 /* reset INT and CFG1 register */
54 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
55 RCU_INT = 0x009f0000U;
56 #elif defined(GD32F10X_CL)
57 RCU_INT = 0x00ff0000U;
58 RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF |
59 RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL);
60 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
61 }
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f10x_rcu.h:90
RCU_INT
#define RCU_INT
Definition: gd32f10x_rcu.h:25
RCU_CFG0_PREDV0
#define RCU_CFG0_PREDV0
Definition: gd32f10x_rcu.h:89
RCU_CTL_PLLEN
#define RCU_CTL_PLLEN
Definition: gd32f10x_rcu.h:61
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_CFG0_CKOUT0SEL
#define RCU_CFG0_CKOUT0SEL
Definition: gd32f10x_rcu.h:92
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f10x_rcu.h:86
RCU_CFG0_ADCPSC_2
#define RCU_CFG0_ADCPSC_2
Definition: gd32f10x_rcu.h:94
RCU_CFG1_I2S1SEL
#define RCU_CFG1_I2S1SEL
Definition: gd32f10x_rcu.h:316
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
RCU_CFG1_PLL2MF
#define RCU_CFG1_PLL2MF
Definition: gd32f10x_rcu.h:314
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f10x_rcu.h:84
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f10x_rcu.h:87
rcu_osci_stab_wait
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
wait for oscillator stabilization flags is SET or oscillator startup is timeout
Definition: gd32f10x_rcu.c:749
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f10x_rcu.h:85
RCU_CTL_CKMEN
#define RCU_CTL_CKMEN
Definition: gd32f10x_rcu.h:60
RCU_CFG1_I2S2SEL
#define RCU_CFG1_I2S2SEL
Definition: gd32f10x_rcu.h:317
RCU_CFG1_PREDV0
#define RCU_CFG1_PREDV0
Definition: gd32f10x_rcu.h:311
RCU_CFG1_PREDV1
#define RCU_CFG1_PREDV1
Definition: gd32f10x_rcu.h:312
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f10x_rcu.h:82
RCU_CFG0_USBDPSC
#define RCU_CFG0_USBDPSC
Definition: gd32f10x_rcu.h:91
RCU_CFG1_PLL1MF
#define RCU_CFG1_PLL1MF
Definition: gd32f10x_rcu.h:313
RCU_CTL_HXTALBPS
#define RCU_CTL_HXTALBPS
Definition: gd32f10x_rcu.h:59
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
RCU_CTL_IRC8MEN
#define RCU_CTL_IRC8MEN
Definition: gd32f10x_rcu.h:53
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f10x_rcu.h:88
RCU_CFG0_PLLMF_4
#define RCU_CFG0_PLLMF_4
Definition: gd32f10x_rcu.h:93
RCU_CFG1_PREDV0SEL
#define RCU_CFG1_PREDV0SEL
Definition: gd32f10x_rcu.h:315
RCU_CTL_HXTALEN
#define RCU_CTL_HXTALEN
Definition: gd32f10x_rcu.h:57
FlagStatus rcu_flag_get ( rcu_flag_enum flag )

get the clock stabilization and periphral reset flags

Parameters
[in] flag the clock stabilization and periphral reset flags, refer to rcu_flag_enum only one parameter can be selected which is shown as below:
  • RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
  • RCU_FLAG_HXTALSTB: HXTAL stabilization flag
  • RCU_FLAG_PLLSTB: PLL stabilization flag
  • RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only)
  • RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only)
  • RCU_FLAG_LXTALSTB: LXTAL stabilization flag
  • RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
  • RCU_FLAG_EPRST: external PIN reset flag
  • RCU_FLAG_PORRST: power reset flag
  • RCU_FLAG_SWRST: software reset flag
  • RCU_FLAG_FWDGTRST: free watchdog timer reset flag
  • RCU_FLAG_WWDGTRST: window watchdog timer reset flag
  • RCU_FLAG_LPRST: low-power reset flag
[out] none
Return values
none

Definition at line 631 of file gd32f10x_rcu.c.

632 {
633 /* get the rcu flag */
634 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
635 return SET;
636 }else{
637 return RESET;
638 }
639 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_hxtal_clock_monitor_disable ( void )

disable the HXTAL clock monitor

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 990 of file gd32f10x_rcu.c.

991 {
992 RCU_CTL &= ~RCU_CTL_CKMEN;
993 }
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_CTL_CKMEN
#define RCU_CTL_CKMEN
Definition: gd32f10x_rcu.h:60
void rcu_hxtal_clock_monitor_enable ( void )

enable the HXTAL clock monitor

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 979 of file gd32f10x_rcu.c.

980 {
981 RCU_CTL |= RCU_CTL_CKMEN;
982 }
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_CTL_CKMEN
#define RCU_CTL_CKMEN
Definition: gd32f10x_rcu.h:60
void rcu_i2s1_clock_config ( uint32_t i2s_clock_source )

configure the I2S1 clock source selection

Parameters
[in] i2s_clock_source I2S1 clock source selection only one parameter can be selected which is shown as below:
  • RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock
  • RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock
[out] none
Return values
none

Definition at line 581 of file gd32f10x_rcu.c.

582 {
583 uint32_t reg;
584
585 reg = RCU_CFG1;
586 /* reset the I2S1SEL bit and set according to i2s_clock_source */
587 reg &= ~RCU_CFG1_I2S1SEL;
588 RCU_CFG1 = (reg | i2s_clock_source);
589 }
RCU_CFG1_I2S1SEL
#define RCU_CFG1_I2S1SEL
Definition: gd32f10x_rcu.h:316
void rcu_i2s2_clock_config ( uint32_t i2s_clock_source )

configure the I2S2 clock source selection

Parameters
[in] i2s_clock_source I2S2 clock source selection only one parameter can be selected which is shown as below:
  • RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock
  • RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock
[out] none
Return values
none

Definition at line 600 of file gd32f10x_rcu.c.

601 {
602 uint32_t reg;
603
604 reg = RCU_CFG1;
605 /* reset the I2S2SEL bit and set according to i2s_clock_source */
606 reg &= ~RCU_CFG1_I2S2SEL;
607 RCU_CFG1 = (reg | i2s_clock_source);
608 }
RCU_CFG1_I2S2SEL
#define RCU_CFG1_I2S2SEL
Definition: gd32f10x_rcu.h:317
void rcu_interrupt_disable ( rcu_int_enum stab_int )

disable the stabilization interrupt

Parameters
[in] stab_int clock stabilization interrupt, refer to rcu_int_enum only one parameter can be selected which is shown as below:
  • RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
  • RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
  • RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
  • RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
  • RCU_INT_PLLSTB: PLL stabilization interrupt enable
  • RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only)
  • RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only)
[out] none
Return values
none

Definition at line 730 of file gd32f10x_rcu.c.

731 {
732 RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
733 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_interrupt_enable ( rcu_int_enum stab_int )

enable the stabilization interrupt

Parameters
[in] stab_int clock stabilization interrupt, refer to rcu_int_enum Only one parameter can be selected which is shown as below:
  • RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
  • RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
  • RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
  • RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
  • RCU_INT_PLLSTB: PLL stabilization interrupt enable
  • RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only)
  • RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only)
[out] none
Return values
none

Definition at line 711 of file gd32f10x_rcu.c.

712 {
713 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
714 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_interrupt_flag_clear ( rcu_int_flag_clear_enum int_flag_clear )

clear the interrupt flags

Parameters
[in] int_flag_clear clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum only one parameter can be selected which is shown as below:
  • RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
  • RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
  • RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
  • RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
  • RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
  • RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only)
  • RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only)
  • RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
[out] none
Return values
none

Definition at line 692 of file gd32f10x_rcu.c.

693 {
694 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
695 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
FlagStatus rcu_interrupt_flag_get ( rcu_int_flag_enum int_flag )

get the clock stabilization interrupt and ckm flags

Parameters
[in] int_flag interrupt and ckm flags, refer to rcu_int_flag_enum only one parameter can be selected which is shown as below:
  • RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
  • RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
  • RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
  • RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
  • RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
  • RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only)
  • RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only)
  • RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 667 of file gd32f10x_rcu.c.

668 {
669 /* get the rcu interrupt flag */
670 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
671 return SET;
672 }else{
673 return RESET;
674 }
675 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_irc8m_adjust_value_set ( uint32_t irc8m_adjval )

set the IRC8M adjust value

Parameters
[in] | irc8m_adjval | IRC8M adjust value, must be between 0 and 0x1F
[out] | none
Return values
none

Definition at line 1001 of file gd32f10x_rcu.c.

1002 {
1003 uint32_t reg;
1004
1005 reg = RCU_CTL;
1006 /* reset the IRC8MADJ bits and set according to irc8m_adjval */
1007 reg &= ~RCU_CTL_IRC8MADJ;
1008 RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3));
1009 }
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_CTL_IRC8MADJ
#define RCU_CTL_IRC8MADJ
Definition: gd32f10x_rcu.h:55
void rcu_osci_bypass_mode_disable ( rcu_osci_type_enum osci )

disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
[out] none
Return values
none

Definition at line 942 of file gd32f10x_rcu.c.

943 {
944 uint32_t reg;
945
946 switch(osci){
947 /* disable HXTAL to bypass mode */
948 case RCU_HXTAL:
949 reg = RCU_CTL;
950 RCU_CTL &= ~RCU_CTL_HXTALEN;
951 RCU_CTL = (reg & ~RCU_CTL_HXTALBPS);
952 break;
953 /* disable LXTAL to bypass mode */
954 case RCU_LXTAL:
955 reg = RCU_BDCTL;
956 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
957 RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS);
958 break;
959 case RCU_IRC8M:
960 case RCU_IRC40K:
961 case RCU_PLL_CK:
962 #ifdef GD32F10X_CL
963 case RCU_PLL1_CK:
964 case RCU_PLL2_CK:
965 #endif /* GD32F10X_CL */
966 break;
967 default:
968 break;
969 }
970 }
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
RCU_PLL1_CK
Definition: gd32f10x_rcu.h:576
RCU_IRC40K
Definition: gd32f10x_rcu.h:573
RCU_CTL_HXTALBPS
#define RCU_CTL_HXTALBPS
Definition: gd32f10x_rcu.h:59
RCU_PLL2_CK
Definition: gd32f10x_rcu.h:577
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f10x_rcu.h:285
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f10x_rcu.h:287
RCU_LXTAL
Definition: gd32f10x_rcu.h:571
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
RCU_CTL_HXTALEN
#define RCU_CTL_HXTALEN
Definition: gd32f10x_rcu.h:57
void rcu_osci_bypass_mode_enable ( rcu_osci_type_enum osci )

enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
[out] none
Return values
none

Definition at line 903 of file gd32f10x_rcu.c.

904 {
905 uint32_t reg;
906
907 switch(osci){
908 /* enable HXTAL to bypass mode */
909 case RCU_HXTAL:
910 reg = RCU_CTL;
911 RCU_CTL &= ~RCU_CTL_HXTALEN;
912 RCU_CTL = (reg | RCU_CTL_HXTALBPS);
913 break;
914 /* enable LXTAL to bypass mode */
915 case RCU_LXTAL:
916 reg = RCU_BDCTL;
917 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
918 RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
919 break;
920 case RCU_IRC8M:
921 case RCU_IRC40K:
922 case RCU_PLL_CK:
923 #ifdef GD32F10X_CL
924 case RCU_PLL1_CK:
925 case RCU_PLL2_CK:
926 #endif /* GD32F10X_CL */
927 break;
928 default:
929 break;
930 }
931 }
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
RCU_PLL1_CK
Definition: gd32f10x_rcu.h:576
RCU_IRC40K
Definition: gd32f10x_rcu.h:573
RCU_CTL_HXTALBPS
#define RCU_CTL_HXTALBPS
Definition: gd32f10x_rcu.h:59
RCU_PLL2_CK
Definition: gd32f10x_rcu.h:577
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f10x_rcu.h:285
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f10x_rcu.h:287
RCU_LXTAL
Definition: gd32f10x_rcu.h:571
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
RCU_CTL_HXTALEN
#define RCU_CTL_HXTALEN
Definition: gd32f10x_rcu.h:57
void rcu_osci_off ( rcu_osci_type_enum osci )

turn off the oscillator

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
  • RCU_IRC8M: internal 8M RC oscillators(IRC8M)
  • RCU_IRC40K: internal 40K RC oscillator(IRC40K)
  • RCU_PLL_CK: phase locked loop(PLL)
  • RCU_PLL1_CK: phase locked loop 1(CL series only)
  • RCU_PLL2_CK: phase locked loop 2(CL series only)
[out] none
Return values
none

Definition at line 889 of file gd32f10x_rcu.c.

890 {
891 RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
892 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_osci_on ( rcu_osci_type_enum osci )

turn on the oscillator

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
  • RCU_IRC8M: internal 8M RC oscillators(IRC8M)
  • RCU_IRC40K: internal 40K RC oscillator(IRC40K)
  • RCU_PLL_CK: phase locked loop(PLL)
  • RCU_PLL1_CK: phase locked loop 1(CL series only)
  • RCU_PLL2_CK: phase locked loop 2(CL series only)
[out] none
Return values
none

Definition at line 870 of file gd32f10x_rcu.c.

871 {
872 RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
873 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
ErrStatus rcu_osci_stab_wait ( rcu_osci_type_enum osci )

wait for oscillator stabilization flags is SET or oscillator startup is timeout

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below:
  • RCU_HXTAL: high speed crystal oscillator(HXTAL)
  • RCU_LXTAL: low speed crystal oscillator(LXTAL)
  • RCU_IRC8M: internal 8M RC oscillators(IRC8M)
  • RCU_IRC40K: internal 40K RC oscillator(IRC40K)
  • RCU_PLL_CK: phase locked loop(PLL)
  • RCU_PLL1_CK: phase locked loop 1(CL series only)
  • RCU_PLL2_CK: phase locked loop 2(CL series only)
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 749 of file gd32f10x_rcu.c.

750 {
751 uint32_t stb_cnt = 0U;
752 ErrStatus reval = ERROR;
753 FlagStatus osci_stat = RESET;
754
755 switch(osci){
756 /* wait HXTAL stable */
757 case RCU_HXTAL:
758 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
759 osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
760 stb_cnt++;
761 }
762
763 /* check whether flag is set or not */
764 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
765 reval = SUCCESS;
766 }
767 break;
768
769 /* wait LXTAL stable */
770 case RCU_LXTAL:
771 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
772 osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
773 stb_cnt++;
774 }
775
776 /* check whether flag is set or not */
777 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
778 reval = SUCCESS;
779 }
780 break;
781
782 /* wait IRC8M stable */
783 case RCU_IRC8M:
784 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
785 osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
786 stb_cnt++;
787 }
788
789 /* check whether flag is set or not */
790 if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
791 reval = SUCCESS;
792 }
793 break;
794
795 /* wait IRC40K stable */
796 case RCU_IRC40K:
797 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
798 osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
799 stb_cnt++;
800 }
801
802 /* check whether flag is set or not */
803 if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
804 reval = SUCCESS;
805 }
806 break;
807
808 /* wait PLL stable */
809 case RCU_PLL_CK:
810 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
811 osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
812 stb_cnt++;
813 }
814
815 /* check whether flag is set or not */
816 if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
817 reval = SUCCESS;
818 }
819 break;
820
821 #ifdef GD32F10X_CL
822 /* wait PLL1 stable */
823 case RCU_PLL1_CK:
824 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
825 osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
826 stb_cnt++;
827 }
828
829 /* check whether flag is set or not */
830 if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){
831 reval = SUCCESS;
832 }
833 break;
834 /* wait PLL2 stable */
835 case RCU_PLL2_CK:
836 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
837 osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
838 stb_cnt++;
839 }
840
841 /* check whether flag is set or not */
842 if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){
843 reval = SUCCESS;
844 }
845 break;
846 #endif /* GD32F10X_CL */
847
848 default:
849 break;
850 }
851
852 /* return value */
853 return reval;
854 }
RCU_FLAG_PLL1STB
Definition: gd32f10x_rcu.h:509
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
RCU_FLAG_HXTALSTB
Definition: gd32f10x_rcu.h:506
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
RCU_FLAG_PLL2STB
Definition: gd32f10x_rcu.h:510
OSC_STARTUP_TIMEOUT
#define OSC_STARTUP_TIMEOUT
Definition: gd32f10x_rcu.c:21
LXTAL_STARTUP_TIMEOUT
#define LXTAL_STARTUP_TIMEOUT
Definition: gd32f10x_rcu.c:22
RCU_FLAG_LXTALSTB
Definition: gd32f10x_rcu.h:512
RCU_FLAG_PLLSTB
Definition: gd32f10x_rcu.h:507
RCU_PLL1_CK
Definition: gd32f10x_rcu.h:576
RCU_IRC40K
Definition: gd32f10x_rcu.h:573
rcu_flag_get
FlagStatus rcu_flag_get(rcu_flag_enum flag)
get the clock stabilization and periphral reset flags
Definition: gd32f10x_rcu.c:631
RCU_FLAG_IRC8MSTB
Definition: gd32f10x_rcu.h:505
RCU_FLAG_IRC40KSTB
Definition: gd32f10x_rcu.h:513
RCU_PLL2_CK
Definition: gd32f10x_rcu.h:577
RCU_LXTAL
Definition: gd32f10x_rcu.h:571
void rcu_periph_clock_disable ( rcu_periph_enum periph )

disable the peripherals clock

Parameters
[in] periph RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock
  • RCU_AF: alternate function clock
  • RCU_CRC: CRC clock
  • RCU_DMAx (x=0,1): DMA clock
  • RCU_ENET: ENET clock(CL series available)
  • RCU_ENETTX: ENETTX clock(CL series available)
  • RCU_ENETRX: ENETRX clock(CL series available)
  • RCU_USBD: USBD clock(HD,XD series available)
  • RCU_USBFS: USBFS clock(CL series available)
  • RCU_EXMC: EXMC clock
  • RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock
  • RCU_WWDGT: WWDGT clock
  • RCU_SPIx (x=0,1,2): SPI clock
  • RCU_USARTx (x=0,1,2): USART clock
  • RCU_UARTx (x=3,4): UART clock
  • RCU_I2Cx (x=0,1): I2C clock
  • RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock
  • RCU_PMU: PMU clock
  • RCU_DAC: DAC clock
  • RCU_RTC: RTC clock
  • RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock
  • RCU_SDIO: SDIO clock(not available for CL series)
  • RCU_BKPI: BKP interface clock
[out] none
Return values
none

Definition at line 128 of file gd32f10x_rcu.c.

129 {
130 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
131 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_clock_enable ( rcu_periph_enum periph )

enable the peripherals clock

Parameters
[in] periph RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock
  • RCU_AF : alternate function clock
  • RCU_CRC: CRC clock
  • RCU_DMAx (x=0,1): DMA clock
  • RCU_ENET: ENET clock(CL series available)
  • RCU_ENETTX: ENETTX clock(CL series available)
  • RCU_ENETRX: ENETRX clock(CL series available)
  • RCU_USBD: USBD clock(HD,XD series available)
  • RCU_USBFS: USBFS clock(CL series available)
  • RCU_EXMC: EXMC clock
  • RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock
  • RCU_WWDGT: WWDGT clock
  • RCU_SPIx (x=0,1,2): SPI clock
  • RCU_USARTx (x=0,1,2): USART clock
  • RCU_UARTx (x=3,4): UART clock
  • RCU_I2Cx (x=0,1): I2C clock
  • RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock
  • RCU_PMU: PMU clock
  • RCU_DAC: DAC clock
  • RCU_RTC: RTC clock
  • RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock
  • RCU_SDIO: SDIO clock(not available for CL series)
  • RCU_BKPI: BKP interface clock
[out] none
Return values
none

Definition at line 93 of file gd32f10x_rcu.c.

94 {
95 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
96 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_clock_sleep_disable ( rcu_periph_sleep_enum periph )

disable the peripherals clock when sleep mode

Parameters
[in] periph RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below:
  • RCU_FMC_SLP: FMC clock
  • RCU_SRAM_SLP: SRAM clock
[out] none
Return values
none

Definition at line 156 of file gd32f10x_rcu.c.

157 {
158 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
159 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_clock_sleep_enable ( rcu_periph_sleep_enum periph )

enable the peripherals clock when sleep mode

Parameters
[in] periph RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below:
  • RCU_FMC_SLP: FMC clock
  • RCU_SRAM_SLP: SRAM clock
[out] none
Return values
none

Definition at line 142 of file gd32f10x_rcu.c.

143 {
144 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
145 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_reset_disable ( rcu_periph_reset_enum periph_reset )

disable reset the peripheral

Parameters
[in] periph_reset RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports
  • RCU_AFRST : reset alternate function clock
  • RCU_ENETRST: reset ENET(CL series available)
  • RCU_USBDRST: reset USBD(HD,XD series available)
  • RCU_USBFSRST: reset USBFS(CL series available)
  • RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER
  • RCU_WWDGTRST: reset WWDGT
  • RCU_SPIxRST (x=0,1,2): reset SPI
  • RCU_USARTxRST (x=0,1,2): reset USART
  • RCU_UARTxRST (x=3,4): reset UART
  • RCU_I2CxRST (x=0,1): reset I2C
  • RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN
  • RCU_PMURST: reset PMU
  • RCU_DACRST: reset DAC
  • RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC
  • RCU_BKPIRST: reset BKPI
[out] none
Return values
none

Definition at line 212 of file gd32f10x_rcu.c.

213 {
214 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
215 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_periph_reset_enable ( rcu_periph_reset_enum periph_reset )

reset the peripherals

Parameters
[in] periph_reset RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports
  • RCU_AFRST : reset alternate function clock
  • RCU_ENETRST: reset ENET(CL series available)
  • RCU_USBDRST: reset USBD(HD,XD series available)
  • RCU_USBFSRST: reset USBFS(CL series available)
  • RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER
  • RCU_WWDGTRST: reset WWDGT
  • RCU_SPIxRST (x=0,1,2): reset SPI
  • RCU_USARTxRST (x=0,1,2): reset USART
  • RCU_UARTxRST (x=3,4): reset UART
  • RCU_I2CxRST (x=0,1): reset I2C
  • RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN
  • RCU_PMURST: reset PMU
  • RCU_DACRST: reset DAC
  • RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC
  • RCU_BKPIRST: reset BKPI
[out] none
Return values
none

Definition at line 184 of file gd32f10x_rcu.c.

185 {
186 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
187 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
void rcu_pll_config | ( | uint32_t | pll_src,
 |  | uint32_t | pll_mul
 | ) |  |

configure the main PLL clock

Parameters
[in] pll_src PLL clock source selection
  • RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL
  • RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL
[in] pll_mul PLL clock multiplication factor
  • RCU_PLL_MULx (XD series x = 2..32, CL series x = 2..14, 6.5, 16..32)
[out] none
Return values
none

Definition at line 375 of file gd32f10x_rcu.c.

376 {
377 uint32_t reg = 0U;
378
379 reg = RCU_CFG0;
380
381 /* PLL clock source and multiplication factor configuration */
382 reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
383 reg |= (pll_src | pll_mul);
384
385 RCU_CFG0 = reg;
386 }
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f10x_rcu.h:90
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f10x_rcu.h:88
RCU_CFG0_PLLMF_4
#define RCU_CFG0_PLLMF_4
Definition: gd32f10x_rcu.h:93
void rcu_predv0_config ( uint32_t predv0_div )

configure the PREDV0 division factor

Parameters
[in] predv0_div PREDV0 division factor
  • RCU_PREDV0_DIVx, x = 1,2
[out] none
Return values
none

Definition at line 396 of file gd32f10x_rcu.c.

397 {
398 uint32_t reg = 0U;
399
400 reg = RCU_CFG0;
401 /* reset PREDV0 bit */
402 reg &= ~RCU_CFG0_PREDV0;
403 if(RCU_PREDV0_DIV2 == predv0_div){
404 /* set the PREDV0 bit */
405 reg |= RCU_CFG0_PREDV0;
406 }
407
408 RCU_CFG0 = reg;
409 }
RCU_CFG0_PREDV0
#define RCU_CFG0_PREDV0
Definition: gd32f10x_rcu.h:89
RCU_PREDV0_DIV2
#define RCU_PREDV0_DIV2
Definition: gd32f10x_rcu.h:714
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_rtc_clock_config ( uint32_t rtc_clock_source )

configure the RTC clock source selection

Parameters
[in] rtc_clock_source RTC clock source selection only one parameter can be selected which is shown as below:
  • RCU_RTCSRC_NONE: no clock selected
  • RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
  • RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
  • RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock
[out] none
Return values
none

Definition at line 561 of file gd32f10x_rcu.c.

562 {
563 uint32_t reg;
564
565 reg = RCU_BDCTL;
566 /* reset the RTCSRC bits and set according to rtc_clock_source */
567 reg &= ~RCU_BDCTL_RTCSRC;
568 RCU_BDCTL = (reg | rtc_clock_source);
569 }
RCU_BDCTL_RTCSRC
#define RCU_BDCTL_RTCSRC
Definition: gd32f10x_rcu.h:288
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
void rcu_system_clock_source_config ( uint32_t ck_sys )

configure the system clock source

Parameters
[in] ck_sys system clock source select only one parameter can be selected which is shown as below:
  • RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
  • RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
  • RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
[out] none
Return values
none

Definition at line 249 of file gd32f10x_rcu.c.

250 {
251 uint32_t reg;
252
253 reg = RCU_CFG0;
254 /* reset the SCS bits and set according to ck_sys */
255 reg &= ~RCU_CFG0_SCS;
256 RCU_CFG0 = (reg | ck_sys);
257 }
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f10x_rcu.h:82
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
uint32_t rcu_system_clock_source_get ( void )

get the system clock source

Parameters
[in] | none
[out] | none
Return values
which clock is selected as CK_SYS source
  • RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source
  • RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source
  • RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source

Definition at line 268 of file gd32f10x_rcu.c.

269 {
270 return (RCU_CFG0 & RCU_CFG0_SCSS);
271 }
RCU_CFG0_SCSS
#define RCU_CFG0_SCSS
Definition: gd32f10x_rcu.h:83
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
void rcu_usb_clock_config ( uint32_t usb_psc )

configure the USBD/USBFS prescaler factor

Parameters
[in] adc_div USB prescaler factor
  • RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5
  • RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1
  • RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5
  • RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2
[out] none
Return values
none

Definition at line 534 of file gd32f10x_rcu.c.

535 {
536 uint32_t reg;
537
538 reg = RCU_CFG0;
539
540 /* configure the USBD/USBFS prescaler factor */
541 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
542 reg &= ~RCU_CFG0_USBDPSC;
543 #elif defined(GD32F10X_CL)
544 reg &= ~RCU_CFG0_USBFSPSC;
545 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
546
547 RCU_CFG0 = (reg | usb_psc);
548 }
RCU_CFG0_USBDPSC
#define RCU_CFG0_USBDPSC
Definition: gd32f10x_rcu.h:91
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_rtc.c File Reference

RTC driver. More...

#include "gd32f10x_rtc.h"

Go to the source code of this file.

Functions

void | rtc_interrupt_enable (uint32_t interrupt)
enable RTC interrupt More...
void | rtc_interrupt_disable (uint32_t interrupt)
disable RTC interrupt More...
void | rtc_configuration_mode_enter (void)
enter RTC configuration mode More...
void | rtc_configuration_mode_exit (void)
exit RTC configuration mode More...
void | rtc_lwoff_wait (void)
wait RTC last write operation finished flag set More...
void | rtc_register_sync_wait (void)
wait RTC registers synchronized flag set More...
uint32_t | rtc_counter_get (void)
get RTC counter value More...
void | rtc_counter_set (uint32_t cnt)
set RTC counter value More...
void | rtc_prescaler_set (uint32_t psc)
set RTC prescaler value More...
void | rtc_alarm_config (uint32_t alarm)
set RTC alarm value More...
uint32_t | rtc_divider_get (void)
get RTC divider value More...
FlagStatus | rtc_flag_get (uint32_t flag)
get RTC flag status More...
void | rtc_flag_clear (uint32_t flag)
clear RTC flag status More...

Detailed Description

RTC driver.

Definition in file gd32f10x_rtc.c.

Function Documentation

void rtc_alarm_config ( uint32_t alarm )

set RTC alarm value

Parameters
[in] | alarm | RTC alarm value
[out] | none
Return values
none

Definition at line 145 of file gd32f10x_rtc.c.

146 {
147 rtc_configuration_mode_enter();
148 /* set the alarm high bits */
149 RTC_ALRMH = alarm >> 16;
150 /* set the alarm low bits */
151 RTC_ALRML = (alarm & RTC_LOW_VALUE);
152 rtc_configuration_mode_exit();
153 }
rtc_configuration_mode_enter
void rtc_configuration_mode_enter(void)
enter RTC configuration mode
Definition: gd32f10x_rtc.c:49
RTC_LOW_VALUE
#define RTC_LOW_VALUE
Definition: gd32f10x_rtc.h:58
rtc_configuration_mode_exit
void rtc_configuration_mode_exit(void)
exit RTC configuration mode
Definition: gd32f10x_rtc.c:60
RTC_ALRML
#define RTC_ALRML
Definition: gd32f10x_rtc.h:31
RTC_ALRMH
#define RTC_ALRMH
Definition: gd32f10x_rtc.h:30
void rtc_configuration_mode_enter ( void )

enter RTC configuration mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 49 of file gd32f10x_rtc.c.

50 {
51 RTC_CTL |= RTC_CTL_CMF;
52 }
RTC_CTL_CMF
#define RTC_CTL_CMF
Definition: gd32f10x_rtc.h:44
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
void rtc_configuration_mode_exit ( void )

exit RTC configuration mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 60 of file gd32f10x_rtc.c.

61 {
62 RTC_CTL &= ~RTC_CTL_CMF;
63 }
RTC_CTL_CMF
#define RTC_CTL_CMF
Definition: gd32f10x_rtc.h:44
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
uint32_t rtc_counter_get ( void )

get RTC counter value

Parameters
[in] | none
[out] | none
Return values
RTC counter value

Definition at line 99 of file gd32f10x_rtc.c.

100 {
101 uint32_t temp = 0x0U;
102 temp = RTC_CNTL;
103 temp |= (RTC_CNTH << 16);
104 return temp;
105 }
RTC_CNTL
#define RTC_CNTL
Definition: gd32f10x_rtc.h:29
RTC_CNTH
#define RTC_CNTH
Definition: gd32f10x_rtc.h:28
void rtc_counter_set ( uint32_t cnt )

set RTC counter value

Parameters
[in] | cnt | RTC counter value
[out] | none
Return values
none

Definition at line 113 of file gd32f10x_rtc.c.

114 {
115 rtc_configuration_mode_enter();
116 /* set the RTC counter high bits */
117 RTC_CNTH = cnt >> 16;
118 /* set the RTC counter low bits */
119 RTC_CNTL = (cnt & RTC_LOW_VALUE);
120 rtc_configuration_mode_exit();
121 }
RTC_CNTL
#define RTC_CNTL
Definition: gd32f10x_rtc.h:29
rtc_configuration_mode_enter
void rtc_configuration_mode_enter(void)
enter RTC configuration mode
Definition: gd32f10x_rtc.c:49
RTC_LOW_VALUE
#define RTC_LOW_VALUE
Definition: gd32f10x_rtc.h:58
rtc_configuration_mode_exit
void rtc_configuration_mode_exit(void)
exit RTC configuration mode
Definition: gd32f10x_rtc.c:60
RTC_CNTH
#define RTC_CNTH
Definition: gd32f10x_rtc.h:28
uint32_t rtc_divider_get ( void )

get RTC divider value

Parameters
[in] | none
[out] | none
Return values
RTC divider value

Definition at line 161 of file gd32f10x_rtc.c.

162 {
163 uint32_t temp = 0x00U;
164 temp = (RTC_DIVH & RTC_DIVH_DIV) << 16;
165 temp |= RTC_DIVL;
166 return temp;
167 }
RTC_DIVL
#define RTC_DIVL
Definition: gd32f10x_rtc.h:27
RTC_DIVH_DIV
#define RTC_DIVH_DIV
Definition: gd32f10x_rtc.h:49
RTC_DIVH
#define RTC_DIVH
Definition: gd32f10x_rtc.h:26
void rtc_flag_clear ( uint32_t flag )

clear RTC flag status

Parameters
[in] flag specify which flag status to clear
  • RTC_FLAG_SECOND: second interrupt flag
  • RTC_FLAG_ALARM: alarm interrupt flag
  • RTC_FLAG_OVERFLOW: overflow interrupt flag
  • RTC_FLAG_RSYN: registers synchronized flag
[out] none
Return values
none

Definition at line 199 of file gd32f10x_rtc.c.

200 {
201 /* clear RTC flag */
202 RTC_CTL &= ~flag;
203 }
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
FlagStatus rtc_flag_get ( uint32_t flag )

get RTC flag status

Parameters
[in] flag specify which flag status to get
  • RTC_FLAG_SECOND: second interrupt flag
  • RTC_FLAG_ALARM: alarm interrupt flag
  • RTC_FLAG_OVERFLOW: overflow interrupt flag
  • RTC_FLAG_RSYN: registers synchronized flag
  • RTC_FLAG_LWOF: last write operation finished flag
[out] none
Return values
SET or RESET

Definition at line 180 of file gd32f10x_rtc.c.

181 {
182 if(RESET != (RTC_CTL & flag)){
183 return SET;
184 }else{
185 return RESET;
186 }
187 }
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
void rtc_interrupt_disable ( uint32_t interrupt )

disable RTC interrupt

Parameters
[in] interrupt specify which interrupt to disbale
  • RTC_INT_SECOND: second interrupt
  • RTC_INT_ALARM: alarm interrupt
  • RTC_INT_OVERFLOW: overflow interrupt
[out] none
Return values
none

Definition at line 38 of file gd32f10x_rtc.c.

39 {
40 RTC_INTEN &= ~interrupt;
41 }
RTC_INTEN
#define RTC_INTEN
Definition: gd32f10x_rtc.h:22
void rtc_interrupt_enable ( uint32_t interrupt )

enable RTC interrupt

Parameters
[in] interrupt specify which interrupt to enbale
  • RTC_INT_SECOND: second interrupt
  • RTC_INT_ALARM: alarm interrupt
  • RTC_INT_OVERFLOW: overflow interrupt
[out] none
Return values
none

Definition at line 24 of file gd32f10x_rtc.c.

25 {
26 RTC_INTEN |= interrupt;
27 }
RTC_INTEN
#define RTC_INTEN
Definition: gd32f10x_rtc.h:22
void rtc_lwoff_wait ( void )

wait RTC last write operation finished flag set

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 71 of file gd32f10x_rtc.c.

72 {
73 /* loop until LWOFF flag is set */
74 while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){
75 }
76 }
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
RTC_CTL_LWOFF
#define RTC_CTL_LWOFF
Definition: gd32f10x_rtc.h:45
void rtc_prescaler_set ( uint32_t psc )

set RTC prescaler value

Parameters
[in] | psc | RTC prescaler value
[out] | none
Return values
none

Definition at line 129 of file gd32f10x_rtc.c.

130 {
131 rtc_configuration_mode_enter();
132 /* set the RTC prescaler high bits */
133 RTC_PSCH = (psc & RTC_HIGH_VALUE) >> 16;
134 /* set the RTC prescaler low bits */
135 RTC_PSCL = (psc & RTC_LOW_VALUE);
136 rtc_configuration_mode_exit();
137 }
RTC_HIGH_VALUE
#define RTC_HIGH_VALUE
Definition: gd32f10x_rtc.h:57
RTC_PSCL
#define RTC_PSCL
Definition: gd32f10x_rtc.h:25
RTC_PSCH
#define RTC_PSCH
Definition: gd32f10x_rtc.h:24
rtc_configuration_mode_enter
void rtc_configuration_mode_enter(void)
enter RTC configuration mode
Definition: gd32f10x_rtc.c:49
RTC_LOW_VALUE
#define RTC_LOW_VALUE
Definition: gd32f10x_rtc.h:58
rtc_configuration_mode_exit
void rtc_configuration_mode_exit(void)
exit RTC configuration mode
Definition: gd32f10x_rtc.c:60
void rtc_register_sync_wait ( void )

wait RTC registers synchronized flag set

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 84 of file gd32f10x_rtc.c.

85 {
86 /* clear RSYNF flag */
87 RTC_CTL &= ~RTC_CTL_RSYNF;
88 /* loop until RSYNF flag is set */
89 while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){
90 }
91 }
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
RTC_CTL_RSYNF
#define RTC_CTL_RSYNF
Definition: gd32f10x_rtc.h:43
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_sdio.c File Reference

SDIO driver. More...

#include "gd32f10x_sdio.h"

Go to the source code of this file.

Macros

#define DEFAULT_RESET_VALUE 0x00000000U

Functions

void | sdio_deinit (void)
deinitialize the SDIO More...
void | sdio_clock_config (uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division)
configure the SDIO clock More...
void | sdio_hardware_clock_enable (void)
enable hardware clock control More...
void | sdio_hardware_clock_disable (void)
disable hardware clock control More...
void | sdio_bus_mode_set (uint32_t bus_mode)
set different SDIO card bus mode More...
void | sdio_power_state_set (uint32_t power_state)
set the SDIO power state More...
uint32_t | sdio_power_state_get (void)
get the SDIO power state More...
void | sdio_clock_enable (void)
enable SDIO_CLK clock output More...
void | sdio_clock_disable (void)
disable SDIO_CLK clock output More...
void | sdio_command_response_config (uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type)
configure the command and response More...
void | sdio_wait_type_set (uint32_t wait_type)
set the command state machine wait type More...
void | sdio_csm_enable (void)
enable the CSM(command state machine) More...
void | sdio_csm_disable (void)
disable the CSM(command state machine) More...
uint8_t | sdio_command_index_get (void)
get the last response command index More...
uint32_t | sdio_response_get (uint32_t responsex)
get the response for the last received command More...
void | sdio_data_config (uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize)
configure the data timeout, data length and data block size More...
void | sdio_data_transfer_config (uint32_t transfer_mode, uint32_t transfer_direction)
configure the data transfer mode and direction More...
void | sdio_dsm_enable (void)
enable the DSM(data state machine) for data transfer More...
void | sdio_dsm_disable (void)
disable the DSM(data state machine) More...
void | sdio_data_write (uint32_t data)
write data(one word) to the transmit FIFO More...
uint32_t | sdio_data_read (void)
read data(one word) from the receive FIFO More...
uint32_t | sdio_data_counter_get (void)
get the number of remaining data bytes to be transferred to card More...
uint32_t | sdio_fifo_counter_get (void)
get the number of words remaining to be written or read from FIFO More...
void | sdio_dma_enable (void)
enable the DMA request for SDIO More...
void | sdio_dma_disable (void)
disable the DMA request for SDIO More...
FlagStatus | sdio_flag_get (uint32_t flag)
get the flags state of SDIO More...
void | sdio_flag_clear (uint32_t flag)
clear the pending flags of SDIO More...
void | sdio_interrupt_enable (uint32_t int_flag)
enable the SDIO interrupt More...
void | sdio_interrupt_disable (uint32_t int_flag)
disable the SDIO interrupt More...
FlagStatus | sdio_interrupt_flag_get (uint32_t int_flag)
get the interrupt flags state of SDIO More...
void | sdio_interrupt_flag_clear (uint32_t int_flag)
clear the interrupt pending flags of SDIO More...
void | sdio_readwait_enable (void)
enable the read wait mode(SD I/O only) More...
void | sdio_readwait_disable (void)
disable the read wait mode(SD I/O only) More...
void | sdio_stop_readwait_enable (void)
enable the function that stop the read wait process(SD I/O only) More...
void | sdio_stop_readwait_disable (void)
disable the function that stop the read wait process(SD I/O only) More...
void | sdio_readwait_type_set (uint32_t readwait_type)
set the read wait type(SD I/O only) More...
void | sdio_operation_enable (void)
enable the SD I/O mode specific operation(SD I/O only) More...
void | sdio_operation_disable (void)
disable the SD I/O mode specific operation(SD I/O only) More...
void | sdio_suspend_enable (void)
enable the SD I/O suspend operation(SD I/O only) More...
void | sdio_suspend_disable (void)
disable the SD I/O suspend operation(SD I/O only) More...
void | sdio_ceata_command_enable (void)
enable the CE-ATA command(CE-ATA only) More...
void | sdio_ceata_command_disable (void)
disable the CE-ATA command(CE-ATA only) More...
void | sdio_ceata_interrupt_enable (void)
enable the CE-ATA interrupt(CE-ATA only) More...
void | sdio_ceata_interrupt_disable (void)
disable the CE-ATA interrupt(CE-ATA only) More...
void | sdio_ceata_command_completion_enable (void)
enable the CE-ATA command completion signal(CE-ATA only) More...
void | sdio_ceata_command_completion_disable (void)
disable the CE-ATA command completion signal(CE-ATA only) More...

Detailed Description

SDIO driver.

Definition in file gd32f10x_sdio.c.

Macro Definition Documentation

#define DEFAULT_RESET_VALUE 0x00000000U

Definition at line 15 of file gd32f10x_sdio.c.

Function Documentation

void sdio_bus_mode_set ( uint32_t bus_mode )

set different SDIO card bus mode

Parameters
[in] bus_mode SDIO card bus mode
  • SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode
  • SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode
  • SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode
[out] none
Return values
none

Definition at line 94 of file gd32f10x_sdio.c.

95 {
96 /* reset the SDIO card bus mode bits and set according to bus_mode */
97 SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE;
98 SDIO_CLKCTL |= bus_mode;
99 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_BUSMODE
#define SDIO_CLKCTL_BUSMODE
Definition: gd32f10x_sdio.h:50
void sdio_ceata_command_completion_disable ( void )

disable the CE-ATA command completion signal(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 766 of file gd32f10x_sdio.c.

767 {
768 SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC;
769 }
SDIO_CMDCTL_ENCMDC
#define SDIO_CMDCTL_ENCMDC
Definition: gd32f10x_sdio.h:64
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_command_completion_enable ( void )

enable the CE-ATA command completion signal(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 755 of file gd32f10x_sdio.c.

756 {
757 SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC;
758 }
SDIO_CMDCTL_ENCMDC
#define SDIO_CMDCTL_ENCMDC
Definition: gd32f10x_sdio.h:64
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_command_disable ( void )

disable the CE-ATA command(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 722 of file gd32f10x_sdio.c.

723 {
724 SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN;
725 }
SDIO_CMDCTL_ATAEN
#define SDIO_CMDCTL_ATAEN
Definition: gd32f10x_sdio.h:66
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_command_enable ( void )

enable the CE-ATA command(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 711 of file gd32f10x_sdio.c.

712 {
713 SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN;
714 }
SDIO_CMDCTL_ATAEN
#define SDIO_CMDCTL_ATAEN
Definition: gd32f10x_sdio.h:66
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_interrupt_disable ( void )

disable the CE-ATA interrupt(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 744 of file gd32f10x_sdio.c.

745 {
746 SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN;
747 }
SDIO_CMDCTL_NINTEN
#define SDIO_CMDCTL_NINTEN
Definition: gd32f10x_sdio.h:65
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_ceata_interrupt_enable ( void )

enable the CE-ATA interrupt(CE-ATA only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 733 of file gd32f10x_sdio.c.

734 {
735 SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN;
736 }
SDIO_CMDCTL_NINTEN
#define SDIO_CMDCTL_NINTEN
Definition: gd32f10x_sdio.h:65
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_clock_config | ( | uint32_t | clock_edge,
 |  | uint32_t | clock_bypass,
 |  | uint32_t | clock_powersave,
 |  | uint16_t | clock_division
 | ) |  |

configure the SDIO clock

Parameters
[in] clock_edge SDIO_CLK clock edge
  • SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK
  • SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK
[in] clock_bypass clock bypass
  • SDIO_CLOCKBYPASS_ENABLE: clock bypass
  • SDIO_CLOCKBYPASS_DISABLE: no bypass
[in] clock_powersave SDIO_CLK clock dynamic switch on/off for power saving
  • SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle
  • SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on
[in] | clock_division | clock division, less than 256
[out] | none
Return values
none

Definition at line 51 of file gd32f10x_sdio.c.

52 {
53 uint32_t clock_config = 0U;
54 clock_config = SDIO_CLKCTL;
55 /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */
56 clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV);
57
58 /* configure the SDIO_CLKCTL according to the parameters */
59 clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division);
60 SDIO_CLKCTL = clock_config;
61 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_CLKEDGE
#define SDIO_CLKCTL_CLKEDGE
Definition: gd32f10x_sdio.h:51
SDIO_CLKCTL_CLKBYP
#define SDIO_CLKCTL_CLKBYP
Definition: gd32f10x_sdio.h:49
SDIO_CLKCTL_CLKPWRSAV
#define SDIO_CLKCTL_CLKPWRSAV
Definition: gd32f10x_sdio.h:48
SDIO_CLKCTL_DIV
#define SDIO_CLKCTL_DIV
Definition: gd32f10x_sdio.h:46
void sdio_clock_disable ( void )

disable SDIO_CLK clock output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 144 of file gd32f10x_sdio.c.

145 {
146 SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN;
147 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_CLKEN
#define SDIO_CLKCTL_CLKEN
Definition: gd32f10x_sdio.h:47
void sdio_clock_enable ( void )

enable SDIO_CLK clock output

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 133 of file gd32f10x_sdio.c.

134 {
135 SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN;
136 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_CLKEN
#define SDIO_CLKCTL_CLKEN
Definition: gd32f10x_sdio.h:47
uint8_t sdio_command_index_get ( void )

get the last response command index

Parameters
[in] | none
[out] | none
Return values
last response command index

Definition at line 218 of file gd32f10x_sdio.c.

219 {
220 return (uint8_t)SDIO_RSPCMDIDX;
221 }
SDIO_RSPCMDIDX
#define SDIO_RSPCMDIDX
Definition: gd32f10x_sdio.h:26
void sdio_command_response_config | ( | uint32_t | cmd_index,
 |  | uint32_t | cmd_argument,
 |  | uint32_t | response_type
 | ) |  |

configure the command and response

Parameters
[in] | cmd_index | command index, refer to the related specifications
[in] | cmd_argument | command argument, refer to the related specifications
[in] response_type response type
  • SDIO_RESPONSETYPE_NO: no response
  • SDIO_RESPONSETYPE_SHORT: short response
  • SDIO_RESPONSETYPE_LONG: long response
[out] | none
Return values
none

Definition at line 160 of file gd32f10x_sdio.c.

161 {
162 uint32_t cmd_config = 0U;
163 /* reset the command index, command argument and response type */
164 SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT;
165 SDIO_CMDAGMT = cmd_argument;
166 cmd_config = SDIO_CMDCTL;
167 cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP);
168 /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */
169 cmd_config |= (cmd_index | response_type);
170 SDIO_CMDCTL = cmd_config;
171 }
SDIO_CMDAGMT
#define SDIO_CMDAGMT
Definition: gd32f10x_sdio.h:24
SDIO_CMDCTL_CMDIDX
#define SDIO_CMDCTL_CMDIDX
Definition: gd32f10x_sdio.h:58
SDIO_CMDCTL_CMDRESP
#define SDIO_CMDCTL_CMDRESP
Definition: gd32f10x_sdio.h:59
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
SDIO_CMDAGMT_CMDAGMT
#define SDIO_CMDAGMT_CMDAGMT
Definition: gd32f10x_sdio.h:55
void sdio_csm_disable ( void )

disable the CSM(command state machine)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 207 of file gd32f10x_sdio.c.

208 {
209 SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN;
210 }
SDIO_CMDCTL_CSMEN
#define SDIO_CMDCTL_CSMEN
Definition: gd32f10x_sdio.h:62
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_csm_enable ( void )

enable the CSM(command state machine)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 196 of file gd32f10x_sdio.c.

197 {
198 SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN;
199 }
SDIO_CMDCTL_CSMEN
#define SDIO_CMDCTL_CSMEN
Definition: gd32f10x_sdio.h:62
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_data_config | ( | uint32_t | data_timeout,
 |  | uint32_t | data_length,
 |  | uint32_t | data_blocksize
 | ) |  |

configure the data timeout, data length and data block size

Parameters
[in] | data_timeout | data timeout period in card bus clock periods
[in] | data_length | number of data bytes to be transferred
[in] data_blocksize size of data block for block transfer
  • SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte
  • SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes
  • SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes
  • SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes
  • SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes
  • SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes
  • SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes
  • SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes
  • SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes
  • SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes
  • SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes
  • SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes
  • SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes
  • SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes
  • SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes
[out] | none
Return values
none

Definition at line 278 of file gd32f10x_sdio.c.

279 {
280 /* reset data timeout, data length and data block size */
281 SDIO_DATATO &= ~SDIO_DATATO_DATATO;
282 SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN;
283 SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ;
284 /* configure the related parameters of data */
285 SDIO_DATATO = data_timeout;
286 SDIO_DATALEN = data_length;
287 SDIO_DATACTL |= data_blocksize;
288 }
SDIO_DATATO
#define SDIO_DATATO
Definition: gd32f10x_sdio.h:31
SDIO_DATALEN_DATALEN
#define SDIO_DATALEN_DATALEN
Definition: gd32f10x_sdio.h:72
SDIO_DATALEN
#define SDIO_DATALEN
Definition: gd32f10x_sdio.h:32
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_BLKSZ
#define SDIO_DATACTL_BLKSZ
Definition: gd32f10x_sdio.h:79
SDIO_DATATO_DATATO
#define SDIO_DATATO_DATATO
Definition: gd32f10x_sdio.h:69
uint32_t sdio_data_counter_get ( void )

get the number of remaining data bytes to be transferred to card

Parameters
[in] | none
[out] | none
Return values
number of remaining data bytes to be transferred

Definition at line 361 of file gd32f10x_sdio.c.

362 {
363 return SDIO_DATACNT;
364 }
SDIO_DATACNT
#define SDIO_DATACNT
Definition: gd32f10x_sdio.h:34
uint32_t sdio_data_read ( void )

read data(one word) from the receive FIFO

Parameters
[in] | none
[out] | none
Return values
received data

Definition at line 350 of file gd32f10x_sdio.c.

351 {
352 return SDIO_FIFO;
353 }
SDIO_FIFO
#define SDIO_FIFO
Definition: gd32f10x_sdio.h:39
void sdio_data_transfer_config | ( | uint32_t | transfer_mode,
 |  | uint32_t | transfer_direction
 | ) |  |

configure the data transfer mode and direction

Parameters
[in] transfer_mode mode of data transfer
  • SDIO_TRANSMODE_BLOCK: block transfer
  • SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer
[in] transfer_direction data transfer direction, read or write
  • SDIO_TRANSDIRECTION_TOCARD: write data to card
  • SDIO_TRANSDIRECTION_TOSDIO: read data from card
[out] none
Return values
none

Definition at line 301 of file gd32f10x_sdio.c.

302 {
303 uint32_t data_trans = 0U;
304 /* reset the data transfer mode, transfer direction and set according to the parameters */
305 data_trans = SDIO_DATACTL;
306 data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR);
307 data_trans |= (transfer_mode | transfer_direction);
308 SDIO_DATACTL = data_trans;
309 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_TRANSMOD
#define SDIO_DATACTL_TRANSMOD
Definition: gd32f10x_sdio.h:77
SDIO_DATACTL_DATADIR
#define SDIO_DATACTL_DATADIR
Definition: gd32f10x_sdio.h:76
void sdio_data_write ( uint32_t data )

write data(one word) to the transmit FIFO

Parameters
[in] | data | 32-bit data write to card
[out] | none
Return values
none

Definition at line 339 of file gd32f10x_sdio.c.

340 {
341 SDIO_FIFO = data;
342 }
SDIO_FIFO
#define SDIO_FIFO
Definition: gd32f10x_sdio.h:39
void sdio_deinit ( void )

deinitialize the SDIO

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 23 of file gd32f10x_sdio.c.

24 {
25 SDIO_PWRCTL = DEFAULT_RESET_VALUE;
26 SDIO_CLKCTL = DEFAULT_RESET_VALUE;
27 SDIO_CMDAGMT = DEFAULT_RESET_VALUE;
28 SDIO_CMDCTL = DEFAULT_RESET_VALUE;
29 SDIO_DATATO = DEFAULT_RESET_VALUE;
30 SDIO_DATALEN = DEFAULT_RESET_VALUE;
31 SDIO_DATACTL = DEFAULT_RESET_VALUE;
32 SDIO_INTC = DEFAULT_RESET_VALUE;
33 SDIO_INTEN = DEFAULT_RESET_VALUE;
34 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_DATATO
#define SDIO_DATATO
Definition: gd32f10x_sdio.h:31
SDIO_CMDAGMT
#define SDIO_CMDAGMT
Definition: gd32f10x_sdio.h:24
SDIO_PWRCTL
#define SDIO_PWRCTL
Definition: gd32f10x_sdio.h:22
SDIO_DATALEN
#define SDIO_DATALEN
Definition: gd32f10x_sdio.h:32
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
SDIO_INTEN
#define SDIO_INTEN
Definition: gd32f10x_sdio.h:37
SDIO_INTC
#define SDIO_INTC
Definition: gd32f10x_sdio.h:36
DEFAULT_RESET_VALUE
#define DEFAULT_RESET_VALUE
Definition: gd32f10x_sdio.c:15
void sdio_dma_disable ( void )

disable the DMA request for SDIO

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 394 of file gd32f10x_sdio.c.

395 {
396 SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN;
397 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_DMAEN
#define SDIO_DATACTL_DMAEN
Definition: gd32f10x_sdio.h:78
void sdio_dma_enable ( void )

enable the DMA request for SDIO

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 383 of file gd32f10x_sdio.c.

384 {
385 SDIO_DATACTL |= SDIO_DATACTL_DMAEN;
386 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_DMAEN
#define SDIO_DATACTL_DMAEN
Definition: gd32f10x_sdio.h:78
void sdio_dsm_disable ( void )

disable the DSM(data state machine)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 328 of file gd32f10x_sdio.c.

329 {
330 SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN;
331 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_DATAEN
#define SDIO_DATACTL_DATAEN
Definition: gd32f10x_sdio.h:75
void sdio_dsm_enable ( void )

enable the DSM(data state machine) for data transfer

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 317 of file gd32f10x_sdio.c.

318 {
319 SDIO_DATACTL |= SDIO_DATACTL_DATAEN;
320 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_DATAEN
#define SDIO_DATACTL_DATAEN
Definition: gd32f10x_sdio.h:75
uint32_t sdio_fifo_counter_get ( void )

get the number of words remaining to be written or read from FIFO

Parameters
[in] | none
[out] | none
Return values
remaining number of words

Definition at line 372 of file gd32f10x_sdio.c.

373 {
374 return SDIO_FIFOCNT;
375 }
SDIO_FIFOCNT
#define SDIO_FIFOCNT
Definition: gd32f10x_sdio.h:38
void sdio_flag_clear ( uint32_t flag )

clear the pending flags of SDIO

Parameters
[in] flag flags state of SDIO
  • SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag
  • SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
  • SDIO_FLAG_CMDTMOUT: command response timeout flag
  • SDIO_FLAG_DTTMOUT: data timeout flag
  • SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag
  • SDIO_FLAG_RXORE: received FIFO overrun error occurs flag
  • SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag
  • SDIO_FLAG_CMDSEND: command sent (no response required) flag
  • SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
  • SDIO_FLAG_STBITE: start bit error in the bus flag
  • SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
  • SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
  • SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
[out] none
Return values
none

Definition at line 457 of file gd32f10x_sdio.c.

458 {
459 SDIO_INTC = flag;
460 }
SDIO_INTC
#define SDIO_INTC
Definition: gd32f10x_sdio.h:36
FlagStatus sdio_flag_get ( uint32_t flag )

get the flags state of SDIO

Parameters
[in] flag flags state of SDIO
  • SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag
  • SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
  • SDIO_FLAG_CMDTMOUT: command response timeout flag
  • SDIO_FLAG_DTTMOUT: data timeout flag
  • SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag
  • SDIO_FLAG_RXORE: received FIFO overrun error occurs flag
  • SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag
  • SDIO_FLAG_CMDSEND: command sent (no response required) flag
  • SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
  • SDIO_FLAG_STBITE: start bit error in the bus flag
  • SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
  • SDIO_FLAG_CMDRUN: command transmission in progress flag
  • SDIO_FLAG_TXRUN: data transmission in progress flag
  • SDIO_FLAG_RXRUN: data reception in progress flag
  • SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO
  • SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO
  • SDIO_FLAG_TFF: transmit FIFO is full flag
  • SDIO_FLAG_RFF: receive FIFO is full flag
  • SDIO_FLAG_TFE: transmit FIFO is empty flag
  • SDIO_FLAG_RFE: receive FIFO is empty flag
  • SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag
  • SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag
  • SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
  • SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 429 of file gd32f10x_sdio.c.

430 {
431 FlagStatus temp_flag = RESET;
432 if(RESET != (SDIO_STAT & flag)){
433 temp_flag = SET;
434 }
435 return temp_flag;
436 }
SDIO_STAT
#define SDIO_STAT
Definition: gd32f10x_sdio.h:35
void sdio_hardware_clock_disable ( void )

disable hardware clock control

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 80 of file gd32f10x_sdio.c.

81 {
82 SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN;
83 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_HWCLKEN
#define SDIO_CLKCTL_HWCLKEN
Definition: gd32f10x_sdio.h:52
void sdio_hardware_clock_enable ( void )

enable hardware clock control

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 69 of file gd32f10x_sdio.c.

70 {
71 SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN;
72 }
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
SDIO_CLKCTL_HWCLKEN
#define SDIO_CLKCTL_HWCLKEN
Definition: gd32f10x_sdio.h:52
void sdio_interrupt_disable ( uint32_t int_flag )

disable the SDIO interrupt

Parameters
[in] int_flag interrupt flags state of SDIO
  • SDIO_INT_CCRCERR: SDIO CCRCERR interrupt
  • SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt
  • SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt
  • SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt
  • SDIO_INT_TXURE: SDIO TXURE interrupt
  • SDIO_INT_RXORE: SDIO RXORE interrupt
  • SDIO_INT_CMDRECV: SDIO CMDRECV interrupt
  • SDIO_INT_CMDSEND: SDIO CMDSEND interrupt
  • SDIO_INT_DTEND: SDIO DTEND interrupt
  • SDIO_INT_STBITE: SDIO STBITE interrupt
  • SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt
  • SDIO_INT_CMDRUN: SDIO CMDRUN interrupt
  • SDIO_INT_TXRUN: SDIO TXRUN interrupt
  • SDIO_INT_RXRUN: SDIO RXRUN interrupt
  • SDIO_INT_TFH: SDIO TFH interrupt
  • SDIO_INT_RFH: SDIO RFH interrupt
  • SDIO_INT_TFF: SDIO TFF interrupt
  • SDIO_INT_RFF: SDIO RFF interrupt
  • SDIO_INT_TFE: SDIO TFE interrupt
  • SDIO_INT_RFE: SDIO RFE interrupt
  • SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt
  • SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt
  • SDIO_INT_SDIOINT: SDIO SDIOINT interrupt
  • SDIO_INT_ATAEND: SDIO ATAEND interrupt
[out] none
Return values
none

Definition at line 527 of file gd32f10x_sdio.c.

528 {
529 SDIO_INTEN &= ~int_flag;
530 }
SDIO_INTEN
#define SDIO_INTEN
Definition: gd32f10x_sdio.h:37
void sdio_interrupt_enable ( uint32_t int_flag )

enable the SDIO interrupt

Parameters
[in] int_flag interrupt flags state of SDIO
  • SDIO_INT_CCRCERR: SDIO CCRCERR interrupt
  • SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt
  • SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt
  • SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt
  • SDIO_INT_TXURE: SDIO TXURE interrupt
  • SDIO_INT_RXORE: SDIO RXORE interrupt
  • SDIO_INT_CMDRECV: SDIO CMDRECV interrupt
  • SDIO_INT_CMDSEND: SDIO CMDSEND interrupt
  • SDIO_INT_DTEND: SDIO DTEND interrupt
  • SDIO_INT_STBITE: SDIO STBITE interrupt
  • SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt
  • SDIO_INT_CMDRUN: SDIO CMDRUN interrupt
  • SDIO_INT_TXRUN: SDIO TXRUN interrupt
  • SDIO_INT_RXRUN: SDIO RXRUN interrupt
  • SDIO_INT_TFH: SDIO TFH interrupt
  • SDIO_INT_RFH: SDIO RFH interrupt
  • SDIO_INT_TFF: SDIO TFF interrupt
  • SDIO_INT_RFF: SDIO RFF interrupt
  • SDIO_INT_TFE: SDIO TFE interrupt
  • SDIO_INT_RFE: SDIO RFE interrupt
  • SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt
  • SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt
  • SDIO_INT_SDIOINT: SDIO SDIOINT interrupt
  • SDIO_INT_ATAEND: SDIO ATAEND interrupt
[out] none
Return values
none

Definition at line 492 of file gd32f10x_sdio.c.

493 {
494 SDIO_INTEN |= int_flag;
495 }
SDIO_INTEN
#define SDIO_INTEN
Definition: gd32f10x_sdio.h:37
void sdio_interrupt_flag_clear ( uint32_t int_flag )

clear the interrupt pending flags of SDIO

Parameters
[in] int_flag interrupt flags state of SDIO
  • SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag
  • SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
  • SDIO_INT_FLAG_CMDTMOUT: command response timeout flag
  • SDIO_INT_FLAG_DTTMOUT: data timeout flag
  • SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag
  • SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag
  • SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag
  • SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag
  • SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
  • SDIO_INT_FLAG_STBITE: start bit error in the bus flag
  • SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
  • SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag
  • SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
[out] none
Return values
none

Definition at line 595 of file gd32f10x_sdio.c.

596 {
597 SDIO_INTC = int_flag;
598 }
SDIO_INTC
#define SDIO_INTC
Definition: gd32f10x_sdio.h:36
FlagStatus sdio_interrupt_flag_get ( uint32_t int_flag )

get the interrupt flags state of SDIO

Parameters
[in] int_flag interrupt flags state of SDIO
  • SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt
  • SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt
  • SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt
  • SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt
  • SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt
  • SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt
  • SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt
  • SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt
  • SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt
  • SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt
  • SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt
  • SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt
  • SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt
  • SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt
  • SDIO_INT_FLAG_TFH: SDIO TFH interrupt
  • SDIO_INT_FLAG_RFH: SDIO RFH interrupt
  • SDIO_INT_FLAG_TFF: SDIO TFF interrupt
  • SDIO_INT_FLAG_RFF: SDIO RFF interrupt
  • SDIO_INT_FLAG_TFE: SDIO TFE interrupt
  • SDIO_INT_FLAG_RFE: SDIO RFE interrupt
  • SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt
  • SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt
  • SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt
  • SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt
[out] none
Return values
FlagStatus SET or RESET

Definition at line 562 of file gd32f10x_sdio.c.

563 {
564 uint32_t state = 0U;
565 state = SDIO_STAT;
566 if(state & int_flag){
567 state = SDIO_INTEN;
568 /* check whether the corresponding bit in SDIO_INTEN is set or not */
569 if(state & int_flag){
570 return SET;
571 }
572 }
573 return RESET;
574 }
SDIO_STAT
#define SDIO_STAT
Definition: gd32f10x_sdio.h:35
SDIO_INTEN
#define SDIO_INTEN
Definition: gd32f10x_sdio.h:37
void sdio_operation_disable ( void )

disable the SD I/O mode specific operation(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 678 of file gd32f10x_sdio.c.

679 {
680 SDIO_DATACTL &= ~SDIO_DATACTL_IOEN;
681 }
SDIO_DATACTL_IOEN
#define SDIO_DATACTL_IOEN
Definition: gd32f10x_sdio.h:83
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
void sdio_operation_enable ( void )

enable the SD I/O mode specific operation(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 667 of file gd32f10x_sdio.c.

668 {
669 SDIO_DATACTL |= SDIO_DATACTL_IOEN;
670 }
SDIO_DATACTL_IOEN
#define SDIO_DATACTL_IOEN
Definition: gd32f10x_sdio.h:83
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
uint32_t sdio_power_state_get ( void )

get the SDIO power state

Parameters
[in] | none
[out] | none
Return values
SDIO power state
  • SDIO_POWER_ON: SDIO power on
  • SDIO_POWER_OFF: SDIO power off

Definition at line 122 of file gd32f10x_sdio.c.

123 {
124 return SDIO_PWRCTL;
125 }
SDIO_PWRCTL
#define SDIO_PWRCTL
Definition: gd32f10x_sdio.h:22
void sdio_power_state_set ( uint32_t power_state )

set the SDIO power state

Parameters
[in] power_state SDIO power state
  • SDIO_POWER_ON: SDIO power on
  • SDIO_POWER_OFF: SDIO power off
[out] none
Return values
none

Definition at line 109 of file gd32f10x_sdio.c.

110 {
111 SDIO_PWRCTL = power_state;
112 }
SDIO_PWRCTL
#define SDIO_PWRCTL
Definition: gd32f10x_sdio.h:22
void sdio_readwait_disable ( void )

disable the read wait mode(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 617 of file gd32f10x_sdio.c.

618 {
619 SDIO_DATACTL &= ~SDIO_DATACTL_RWEN;
620 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_RWEN
#define SDIO_DATACTL_RWEN
Definition: gd32f10x_sdio.h:80
void sdio_readwait_enable ( void )

enable the read wait mode(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 606 of file gd32f10x_sdio.c.

607 {
608 SDIO_DATACTL |= SDIO_DATACTL_RWEN;
609 }
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_RWEN
#define SDIO_DATACTL_RWEN
Definition: gd32f10x_sdio.h:80
void sdio_readwait_type_set ( uint32_t readwait_type )

set the read wait type(SD I/O only)

Parameters
[in] readwait_type SD I/O read wait type
  • SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK
  • SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2]
[out] none
Return values
none

Definition at line 652 of file gd32f10x_sdio.c.

653 {
654 if(SDIO_READWAITTYPE_CLK == readwait_type){
655 SDIO_DATACTL |= SDIO_DATACTL_RWTYPE;
656 }else{
657 SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE;
658 }
659 }
SDIO_READWAITTYPE_CLK
#define SDIO_READWAITTYPE_CLK
Definition: gd32f10x_sdio.h:301
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_DATACTL_RWTYPE
#define SDIO_DATACTL_RWTYPE
Definition: gd32f10x_sdio.h:82
uint32_t sdio_response_get ( uint32_t responsex )

get the response for the last received command

Parameters
[in] responsex SDIO response
  • SDIO_RESPONSE0: card response[31:0]/card response[127:96]
  • SDIO_RESPONSE1: card response[95:64]
  • SDIO_RESPONSE2: card response[63:32]
  • SDIO_RESPONSE3: card response[31:1], plus bit 0
[out] none
Return values
response for the last received command

Definition at line 233 of file gd32f10x_sdio.c.

234 {
235 uint32_t resp_content = 0U;
236 switch(responsex){
237 case SDIO_RESPONSE0:
238 resp_content = SDIO_RESP0;
239 break;
240 case SDIO_RESPONSE1:
241 resp_content = SDIO_RESP1;
242 break;
243 case SDIO_RESPONSE2:
244 resp_content = SDIO_RESP2;
245 break;
246 case SDIO_RESPONSE3:
247 resp_content = SDIO_RESP3;
248 break;
249 default:
250 break;
251 }
252 return resp_content;
253 }
SDIO_RESP0
#define SDIO_RESP0
Definition: gd32f10x_sdio.h:27
SDIO_RESPONSE1
#define SDIO_RESPONSE1
Definition: gd32f10x_sdio.h:269
SDIO_RESP1
#define SDIO_RESP1
Definition: gd32f10x_sdio.h:28
SDIO_RESPONSE2
#define SDIO_RESPONSE2
Definition: gd32f10x_sdio.h:270
SDIO_RESPONSE3
#define SDIO_RESPONSE3
Definition: gd32f10x_sdio.h:271
SDIO_RESP2
#define SDIO_RESP2
Definition: gd32f10x_sdio.h:29
SDIO_RESP3
#define SDIO_RESP3
Definition: gd32f10x_sdio.h:30
SDIO_RESPONSE0
#define SDIO_RESPONSE0
Definition: gd32f10x_sdio.h:268
void sdio_stop_readwait_disable ( void )

disable the function that stop the read wait process(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 639 of file gd32f10x_sdio.c.

640 {
641 SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP;
642 }
SDIO_DATACTL_RWSTOP
#define SDIO_DATACTL_RWSTOP
Definition: gd32f10x_sdio.h:81
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
void sdio_stop_readwait_enable ( void )

enable the function that stop the read wait process(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 628 of file gd32f10x_sdio.c.

629 {
630 SDIO_DATACTL |= SDIO_DATACTL_RWSTOP;
631 }
SDIO_DATACTL_RWSTOP
#define SDIO_DATACTL_RWSTOP
Definition: gd32f10x_sdio.h:81
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
void sdio_suspend_disable ( void )

disable the SD I/O suspend operation(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 700 of file gd32f10x_sdio.c.

701 {
702 SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND;
703 }
SDIO_CMDCTL_SUSPEND
#define SDIO_CMDCTL_SUSPEND
Definition: gd32f10x_sdio.h:63
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_suspend_enable ( void )

enable the SD I/O suspend operation(SD I/O only)

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 689 of file gd32f10x_sdio.c.

690 {
691 SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND;
692 }
SDIO_CMDCTL_SUSPEND
#define SDIO_CMDCTL_SUSPEND
Definition: gd32f10x_sdio.h:63
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
void sdio_wait_type_set ( uint32_t wait_type )

set the command state machine wait type

Parameters
[in] wait_type wait type
  • SDIO_WAITTYPE_NO: not wait interrupt
  • SDIO_WAITTYPE_INTERRUPT: wait interrupt
  • SDIO_WAITTYPE_DATAEND: wait the end of data transfer
[out] none
Return values
none

Definition at line 182 of file gd32f10x_sdio.c.

183 {
184 /* reset INTWAIT and WAITDEND */
185 SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND);
186 /* set the wait type according to wait_type */
187 SDIO_CMDCTL |= wait_type;
188 }
SDIO_CMDCTL_INTWAIT
#define SDIO_CMDCTL_INTWAIT
Definition: gd32f10x_sdio.h:60
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
SDIO_CMDCTL_WAITDEND
#define SDIO_CMDCTL_WAITDEND
Definition: gd32f10x_sdio.h:61
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_spi.c File Reference

SPI driver. More...

#include "gd32f10x_spi.h"

Go to the source code of this file.

Macros

#define | SPI_INIT_MASK ((uint32_t)0x00003040U)
#define | I2S_INIT_MASK ((uint32_t)0x0000F047U)
#define | I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */
#define | I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */
#define | I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */
#define | I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */

Functions

void | spi_i2s_deinit (uint32_t spi_periph)
reset SPI and I2S More...
void | spi_init (uint32_t spi_periph, spi_parameter_struct *spi_struct)
initialize SPI parameter More...
void | spi_enable (uint32_t spi_periph)
enable SPI More...
void | spi_disable (uint32_t spi_periph)
disable SPI More...
void | i2s_init (uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
initialize I2S parameter More...
void | i2s_psc_config (uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
configure I2S prescaler More...
void | i2s_enable (uint32_t spi_periph)
enable I2S More...
void | i2s_disable (uint32_t spi_periph)
disable I2S More...
void | spi_nss_output_enable (uint32_t spi_periph)
enable SPI NSS output More...
void | spi_nss_output_disable (uint32_t spi_periph)
disable SPI NSS output More...
void | spi_nss_internal_high (uint32_t spi_periph)
SPI NSS pin high level in software mode. More...
void | spi_nss_internal_low (uint32_t spi_periph)
SPI NSS pin low level in software mode. More...
void | spi_dma_enable (uint32_t spi_periph, uint8_t dma)
enable SPI DMA send or receive More...
void | spi_dma_disable (uint32_t spi_periph, uint8_t dma)
disable SPI DMA send or receive More...
void | spi_i2s_data_frame_format_config (uint32_t spi_periph, uint16_t frame_format)
configure SPI/I2S data frame format More...
void | spi_i2s_data_transmit (uint32_t spi_periph, uint16_t data)
SPI transmit data. More...
uint16_t | spi_i2s_data_receive (uint32_t spi_periph)
SPI receive data. More...
void | spi_bidirectional_transfer_config (uint32_t spi_periph, uint32_t transfer_direction)
configure SPI bidirectional transfer direction More...
void | spi_i2s_interrupt_enable (uint32_t spi_periph, uint8_t interrupt)
enable SPI and I2S interrupt More...
void | spi_i2s_interrupt_disable (uint32_t spi_periph, uint8_t interrupt)
disable SPI and I2S interrupt More...
FlagStatus | spi_i2s_interrupt_flag_get (uint32_t spi_periph, uint8_t interrupt)
get SPI and I2S interrupt flag status More...
FlagStatus | spi_i2s_flag_get (uint32_t spi_periph, uint32_t flag)
get SPI and I2S flag status More...
void | spi_crc_error_clear (uint32_t spi_periph)
clear SPI CRC error flag status More...
void | spi_crc_on (uint32_t spi_periph)
turn on CRC function More...
void | spi_crc_off (uint32_t spi_periph)
turn off CRC function More...
void | spi_crc_polynomial_set (uint32_t spi_periph, uint16_t crc_poly)
set CRC polynomial More...
uint16_t | spi_crc_polynomial_get (uint32_t spi_periph)
get SPI CRC polynomial More...
void | spi_crc_next (uint32_t spi_periph)
SPI next data is CRC value. More...
uint16_t | spi_crc_get (uint32_t spi_periph, uint8_t crc)
get SPI CRC send value or receive value More...

Detailed Description

SPI driver.

Definition in file gd32f10x_spi.c.

Macro Definition Documentation

#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */

Definition at line 18 of file gd32f10x_spi.c.

#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */

Definition at line 19 of file gd32f10x_spi.c.

#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */

Definition at line 21 of file gd32f10x_spi.c.

#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */

Definition at line 20 of file gd32f10x_spi.c.

#define I2S_INIT_MASK ((uint32_t)0x0000F047U)

I2S parameter initialization mask

Definition at line 16 of file gd32f10x_spi.c.

#define SPI_INIT_MASK ((uint32_t)0x00003040U)

SPI parameter initialization mask

Definition at line 15 of file gd32f10x_spi.c.

Function Documentation

void i2s_disable ( uint32_t spi_periph )

disable I2S

Parameters
[in] | spi_periph | SPIx(x=1,2)
[out] | none
Return values
none

Definition at line 276 of file gd32f10x_spi.c.

277 {
278 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
279 }
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
SPI_I2SCTL_I2SEN
#define SPI_I2SCTL_I2SEN
Definition: gd32f10x_spi.h:88
void i2s_enable ( uint32_t spi_periph )

enable I2S

Parameters
[in] | spi_periph | SPIx(x=1,2)
[out] | none
Return values
none

Definition at line 265 of file gd32f10x_spi.c.

266 {
267 SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
268 }
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
SPI_I2SCTL_I2SEN
#define SPI_I2SCTL_I2SEN
Definition: gd32f10x_spi.h:88
void i2s_init | ( | uint32_t | spi_periph,
 |  | uint32_t | mode,
 |  | uint32_t | standard,
 |  | uint32_t | ckpl
 | ) |  |

initialize I2S parameter

Parameters
[in] | spi_periph | SPIx(x=1,2)
[in] mode I2S operation mode
  • I2S_MODE_SLAVETX: I2S slave transmit mode
  • I2S_MODE_SLAVERX: I2S slave receive mode
  • I2S_MODE_MASTERTX: I2S master transmit mode
  • I2S_MODE_MASTERRX: I2S master receive mode
[in] standard I2S standard
  • I2S_STD_PHILLIPS: I2S phillips standard
  • I2S_STD_MSB: I2S MSB standard
  • I2S_STD_LSB: I2S LSB standard
  • I2S_STD_PCMSHORT: I2S PCM short standard
  • I2S_STD_PCMLONG: I2S PCM long standard
[in] ckpl I2S idle state clock polarity
  • I2S_CKPL_LOW: I2S clock polarity low level
  • I2S_CKPL_HIGH: I2S clock polarity high level
[out] | none
Return values
none

Definition at line 138 of file gd32f10x_spi.c.

139 {
140 uint32_t reg = 0U;
141 reg = SPI_I2SCTL(spi_periph);
142 reg &= I2S_INIT_MASK;
143
144 /* enable I2S mode */
145 reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
146 /* select I2S mode */
147 reg |= (uint32_t)mode;
148 /* select I2S standard */
149 reg |= (uint32_t)standard;
150 /* select I2S polarity */
151 reg |= (uint32_t)ckpl;
152
153 /* write to SPI_I2SCTL register */
154 SPI_I2SCTL(spi_periph) = (uint32_t)reg;
155 }
SPI_I2SCTL_I2SSEL
#define SPI_I2SCTL_I2SSEL
Definition: gd32f10x_spi.h:89
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
I2S_INIT_MASK
#define I2S_INIT_MASK
Definition: gd32f10x_spi.c:16
void i2s_psc_config | ( | uint32_t | spi_periph,
 |  | uint32_t | audiosample,
 |  | uint32_t | frameformat,
 |  | uint32_t | mckout
 | ) |  |

configure I2S prescaler

Parameters
[in] | spi_periph | SPIx(x=1,2)
[in] audiosample I2S audio sample rate
  • I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
  • I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
  • I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
  • I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
  • I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
  • I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
  • I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
  • I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
  • I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
[in] frameformat I2S data length and channel length
  • I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
  • I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
  • I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
  • I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
[in] mckout I2S master clock output
  • I2S_MCKOUT_ENABLE: I2S master clock output enable
  • I2S_MCKOUT_DISABLE: I2S master clock output disable
[out] | none
Return values
none

Definition at line 181 of file gd32f10x_spi.c.

182 {
183 uint32_t i2sdiv = 2U, i2sof = 0U;
184 uint32_t clks = 0U;
185 uint32_t i2sclock = 0U;
186
187 /* deinit SPI_I2SPSC register */
188 SPI_I2SPSC(spi_periph) = 0x0002U;
189
190 #ifdef GD32F10X_CL
191 /* get the I2S clock source */
192 if(((uint32_t)spi_periph) == SPI1){
193 /* I2S1 clock source selection */
194 clks = I2S1_CLOCK_SEL;
195 }else{
196 /* I2S2 clock source selection */
197 clks = I2S2_CLOCK_SEL;
198 }
199
200 if(0U != (RCU_CFG1 & clks)){
201 /* get RCU PLL2 clock multiplication factor */
202 clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U);
203
204 if((clks > 5U) && (clks < 15U)){
205 /* multiplier is between 8 and 14 */
206 clks += 2U;
207 }else{
208 if(15U == clks){
209 /* multiplier is 20 */
210 clks = 20U;
211 }
212 }
213
214 /* get the PREDV1 value */
215 i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U);
216 /* calculate i2sclock based on PLL2 and PREDV1 */
217 i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U);
218 }else{
219 /* get system clock */
220 i2sclock = rcu_clock_freq_get(CK_SYS);
221 }
222 #else
223 /* get system clock */
224 i2sclock = rcu_clock_freq_get(CK_SYS);
225 #endif /* GD32F10X_CL */
226
227 /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
228 if(I2S_MCKOUT_ENABLE == mckout){
229 clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
230 }else{
231 if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){
232 clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample);
233 }else{
234 clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample);
235 }
236 }
237
238 /* remove the floating point */
239 clks = (clks + 5U) / 10U;
240 i2sof = (clks & 0x00000001U);
241 i2sdiv = ((clks - i2sof) / 2U);
242 i2sof = (i2sof << 8U);
243
244 /* set the default values */
245 if((i2sdiv < 2U) || (i2sdiv > 255U)){
246 i2sdiv = 2U;
247 i2sof = 0U;
248 }
249
250 /* configure SPI_I2SPSC */
251 SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout);
252
253 /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
254 SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
255 /* configure data frame format */
256 SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat;
257 }
SPI1
#define SPI1
Definition: gd32f10x_spi.h:20
I2S_CLOCK_DIV_MASK
#define I2S_CLOCK_DIV_MASK
Definition: gd32f10x_spi.c:21
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
CK_SYS
Definition: gd32f10x_rcu.h:584
I2S2_CLOCK_SEL
#define I2S2_CLOCK_SEL
Definition: gd32f10x_spi.c:19
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
SPI_I2SCTL_DTLEN
#define SPI_I2SCTL_DTLEN
Definition: gd32f10x_spi.h:83
I2S_CLOCK_MUL_MASK
#define I2S_CLOCK_MUL_MASK
Definition: gd32f10x_spi.c:20
I2S_MCKOUT_ENABLE
#define I2S_MCKOUT_ENABLE
Definition: gd32f10x_spi.h:172
I2S_FRAMEFORMAT_DT16B_CH16B
#define I2S_FRAMEFORMAT_DT16B_CH16B
Definition: gd32f10x_spi.h:165
SPI_I2SPSC
#define SPI_I2SPSC(spix)
Definition: gd32f10x_spi.h:32
SPI_I2SCTL_CHLEN
#define SPI_I2SCTL_CHLEN
Definition: gd32f10x_spi.h:82
I2S1_CLOCK_SEL
#define I2S1_CLOCK_SEL
Definition: gd32f10x_spi.c:18
void spi_bidirectional_transfer_config | ( | uint32_t | spi_periph,
 |  | uint32_t | transfer_direction
 | ) |  |

configure SPI bidirectional transfer direction

Parameters
[in] spi_periph SPIx(x=0,1,2)
[in] transfer_direction SPI transfer direction
  • SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
  • SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
Return values
none

Definition at line 409 of file gd32f10x_spi.c.

410 {
411 if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
412 /* set the transmit only mode */
413 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
414 }else{
415 /* set the receive only mode */
416 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
417 }
418 }
SPI_BIDIRECTIONAL_RECEIVE
#define SPI_BIDIRECTIONAL_RECEIVE
Definition: gd32f10x_spi.h:115
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
SPI_BIDIRECTIONAL_TRANSMIT
#define SPI_BIDIRECTIONAL_TRANSMIT
Definition: gd32f10x_spi.h:114
void spi_crc_error_clear ( uint32_t spi_periph )

clear SPI CRC error flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 576 of file gd32f10x_spi.c.

577 {
578 SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
579 }
SPI_FLAG_CRCERR
#define SPI_FLAG_CRCERR
Definition: gd32f10x_spi.h:217
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f10x_spi.h:26
uint16_t spi_crc_get | ( | uint32_t | spi_periph,
 |  | uint8_t | crc
 | ) |  |

get SPI CRC send value or receive value

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] crc SPI crc value
  • SPI_CRC_TX: get transmit crc value
  • SPI_CRC_RX: get receive crc value
[out] | none
Return values
16-bit CRC value

Definition at line 647 of file gd32f10x_spi.c.

648 {
649 if(SPI_CRC_TX == crc){
650 return ((uint16_t)(SPI_TCRC(spi_periph)));
651 }else{
652 return ((uint16_t)(SPI_RCRC(spi_periph)));
653 }
654 }
SPI_CRC_TX
#define SPI_CRC_TX
Definition: gd32f10x_spi.h:198
SPI_RCRC
#define SPI_RCRC(spix)
Definition: gd32f10x_spi.h:29
SPI_TCRC
#define SPI_TCRC(spix)
Definition: gd32f10x_spi.h:30
void spi_crc_next ( uint32_t spi_periph )

SPI next data is CRC value.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 633 of file gd32f10x_spi.c.

634 {
635 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
636 }
SPI_CTL0_CRCNT
#define SPI_CTL0_CRCNT
Definition: gd32f10x_spi.h:46
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_crc_off ( uint32_t spi_periph )

turn off CRC function

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 598 of file gd32f10x_spi.c.

599 {
600 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
601 }
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f10x_spi.h:47
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_crc_on ( uint32_t spi_periph )

turn on CRC function

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 587 of file gd32f10x_spi.c.

588 {
589 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
590 }
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f10x_spi.h:47
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
uint16_t spi_crc_polynomial_get ( uint32_t spi_periph )

get SPI CRC polynomial

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
16-bit CRC polynomial

Definition at line 622 of file gd32f10x_spi.c.

623 {
624 return ((uint16_t)SPI_CRCPOLY(spi_periph));
625 }
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f10x_spi.h:28
void spi_crc_polynomial_set | ( | uint32_t | spi_periph,
 |  | uint16_t | crc_poly
 | ) |  |

set CRC polynomial

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | crc_poly | CRC polynomial value
[out] | none
Return values
none

Definition at line 610 of file gd32f10x_spi.c.

611 {
612 /* set SPI CRC polynomial */
613 SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
614 }
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f10x_spi.h:28
void spi_disable ( uint32_t spi_periph )

disable SPI

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 113 of file gd32f10x_spi.c.

114 {
115 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
116 }
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f10x_spi.h:40
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_dma_disable | ( | uint32_t | spi_periph,
 |  | uint8_t | dma
 | ) |  |

disable SPI DMA send or receive

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] dma SPI DMA mode
  • SPI_DMA_TRANSMIT: SPI transmit data use DMA
  • SPI_DMA_RECEIVE: SPI receive data use DMA
[out] | none
Return values
none

Definition at line 352 of file gd32f10x_spi.c.

353 {
354 if(SPI_DMA_TRANSMIT == dma){
355 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
356 }else{
357 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
358 }
359 }
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f10x_spi.h:53
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f10x_spi.h:194
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f10x_spi.h:52
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
void spi_dma_enable | ( | uint32_t | spi_periph,
 |  | uint8_t | dma
 | ) |  |

enable SPI DMA send or receive

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] dma SPI DMA mode
  • SPI_DMA_TRANSMIT: SPI transmit data use DMA
  • SPI_DMA_RECEIVE: SPI receive data use DMA
[out] | none
Return values
none

Definition at line 334 of file gd32f10x_spi.c.

335 {
336 if(SPI_DMA_TRANSMIT == dma){
337 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
338 }else{
339 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
340 }
341 }
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f10x_spi.h:53
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f10x_spi.h:194
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f10x_spi.h:52
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
void spi_enable ( uint32_t spi_periph )

enable SPI

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 102 of file gd32f10x_spi.c.

103 {
104 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
105 }
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f10x_spi.h:40
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_i2s_data_frame_format_config | ( | uint32_t | spi_periph,
 |  | uint16_t | frame_format
 | ) |  |

configure SPI/I2S data frame format

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] frame_format SPI frame size
  • SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
  • SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
[out] | none
Return values
none

Definition at line 370 of file gd32f10x_spi.c.

371 {
372 /* clear SPI_CTL0_FF16 bit */
373 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
374 /* confige SPI_CTL0_FF16 bit */
375 SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
376 }
SPI_CTL0_FF16
#define SPI_CTL0_FF16
Definition: gd32f10x_spi.h:45
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
uint16_t spi_i2s_data_receive ( uint32_t spi_periph )

SPI receive data.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
16-bit data

Definition at line 396 of file gd32f10x_spi.c.

397 {
398 return ((uint16_t)SPI_DATA(spi_periph));
399 }
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f10x_spi.h:27
void spi_i2s_data_transmit | ( | uint32_t | spi_periph,
 |  | uint16_t | data
 | ) |  |

SPI transmit data.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | data | 16-bit data
[out] | none
Return values
none

Definition at line 385 of file gd32f10x_spi.c.

386 {
387 SPI_DATA(spi_periph) = (uint32_t)data;
388 }
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f10x_spi.h:27
void spi_i2s_deinit ( uint32_t spi_periph )

reset SPI and I2S

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 29 of file gd32f10x_spi.c.

30 {
31 switch(spi_periph){
32 case SPI0:
33 /* reset SPI0 */
34 rcu_periph_reset_enable(RCU_SPI0RST);
35 rcu_periph_reset_disable(RCU_SPI0RST);
36 break;
37 case SPI1:
38 /* reset SPI1 and I2S1 */
39 rcu_periph_reset_enable(RCU_SPI1RST);
40 rcu_periph_reset_disable(RCU_SPI1RST);
41 break;
42 case SPI2:
43 /* reset SPI2 and I2S2 */
44 rcu_periph_reset_enable(RCU_SPI2RST);
45 rcu_periph_reset_disable(RCU_SPI2RST);
46 break;
47 default :
48 break;
49 }
50 }
SPI1
#define SPI1
Definition: gd32f10x_spi.h:20
RCU_SPI1RST
Definition: gd32f10x_rcu.h:457
SPI0
#define SPI0
Definition: gd32f10x_spi.h:19
SPI2
#define SPI2
Definition: gd32f10x_spi.h:21
RCU_SPI2RST
Definition: gd32f10x_rcu.h:458
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
RCU_SPI0RST
Definition: gd32f10x_rcu.h:488
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
FlagStatus spi_i2s_flag_get | ( | uint32_t | spi_periph,
 |  | uint32_t | flag
 | ) |  |

get SPI and I2S flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] flag SPI/I2S flag status
  • SPI_FLAG_TBE: transmit buffer empty flag
  • SPI_FLAG_RBNE: receive buffer not empty flag
  • SPI_FLAG_TRANS: transmit on-going flag
  • SPI_FLAG_RXORERR: receive overrun error flag
  • SPI_FLAG_CONFERR: mode config error flag
  • SPI_FLAG_CRCERR: CRC error flag
  • I2S_FLAG_TBE: transmit buffer empty flag
  • I2S_FLAG_RBNE: receive buffer not empty flag
  • I2S_FLAG_TRANS: transmit on-going flag
  • I2S_FLAG_RXORERR: overrun error flag
  • I2S_FLAG_TXURERR: underrun error flag
  • I2S_FLAG_CH: channel side flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 561 of file gd32f10x_spi.c.

562 {
563 if(SPI_STAT(spi_periph) & flag){
564 return SET;
565 }else{
566 return RESET;
567 }
568 }
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f10x_spi.h:26
void spi_i2s_interrupt_disable | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

disable SPI and I2S interrupt

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt
  • SPI_I2S_INT_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt
[out] | none
Return values
none

Definition at line 462 of file gd32f10x_spi.c.

463 {
464 switch(interrupt){
465 /* SPI/I2S transmit buffer empty interrupt */
466 case SPI_I2S_INT_TBE:
467 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
468 break;
469 /* SPI/I2S receive buffer not empty interrupt */
470 case SPI_I2S_INT_RBNE:
471 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
472 break;
473 /* SPI/I2S error */
474 case SPI_I2S_INT_ERR:
475 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
476 break;
477 default :
478 break;
479 }
480 }
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f10x_spi.h:204
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f10x_spi.h:55
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f10x_spi.h:203
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f10x_spi.h:202
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f10x_spi.h:56
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f10x_spi.h:57
void spi_i2s_interrupt_enable | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

enable SPI and I2S interrupt

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt
  • SPI_I2S_INT_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt
[out] | none
Return values
none

Definition at line 431 of file gd32f10x_spi.c.

432 {
433 switch(interrupt){
434 /* SPI/I2S transmit buffer empty interrupt */
435 case SPI_I2S_INT_TBE:
436 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
437 break;
438 /* SPI/I2S receive buffer not empty interrupt */
439 case SPI_I2S_INT_RBNE:
440 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
441 break;
442 /* SPI/I2S error */
443 case SPI_I2S_INT_ERR:
444 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
445 break;
446 default:
447 break;
448 }
449 }
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f10x_spi.h:204
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f10x_spi.h:55
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f10x_spi.h:203
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f10x_spi.h:202
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f10x_spi.h:56
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f10x_spi.h:57
FlagStatus spi_i2s_interrupt_flag_get | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

get SPI and I2S interrupt flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt flag status
  • SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_FLAG_RXORERR: overrun interrupt
  • SPI_INT_FLAG_CONFERR: config error interrupt
  • SPI_INT_FLAG_CRCERR: CRC error interrupt
  • I2S_INT_FLAG_TXURERR: underrun error interrupt
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 495 of file gd32f10x_spi.c.

496 {
497 uint32_t reg1 = SPI_STAT(spi_periph);
498 uint32_t reg2 = SPI_CTL1(spi_periph);
499
500 switch(interrupt){
501 /* SPI/I2S transmit buffer empty interrupt */
502 case SPI_I2S_INT_FLAG_TBE:
503 reg1 = reg1 & SPI_STAT_TBE;
504 reg2 = reg2 & SPI_CTL1_TBEIE;
505 break;
506 /* SPI/I2S receive buffer not empty interrupt */
507 case SPI_I2S_INT_FLAG_RBNE:
508 reg1 = reg1 & SPI_STAT_RBNE;
509 reg2 = reg2 & SPI_CTL1_RBNEIE;
510 break;
511 /* SPI/I2S overrun interrupt */
512 case SPI_I2S_INT_FLAG_RXORERR:
513 reg1 = reg1 & SPI_STAT_RXORERR;
514 reg2 = reg2 & SPI_CTL1_ERRIE;
515 break;
516 /* SPI config error interrupt */
517 case SPI_INT_FLAG_CONFERR:
518 reg1 = reg1 & SPI_STAT_CONFERR;
519 reg2 = reg2 & SPI_CTL1_ERRIE;
520 break;
521 /* SPI CRC error interrupt */
522 case SPI_INT_FLAG_CRCERR:
523 reg1 = reg1 & SPI_STAT_CRCERR;
524 reg2 = reg2 & SPI_CTL1_ERRIE;
525 break;
526 /* I2S underrun error interrupt */
527 case I2S_INT_FLAG_TXURERR:
528 reg1 = reg1 & SPI_STAT_TXURERR;
529 reg2 = reg2 & SPI_CTL1_ERRIE;
530 break;
531 default :
532 break;
533 }
534 /*get SPI/I2S interrupt flag status */
535 if(reg1 && reg2){
536 return SET;
537 }else{
538 return RESET;
539 }
540 }
SPI_STAT_CONFERR
#define SPI_STAT_CONFERR
Definition: gd32f10x_spi.h:65
SPI_STAT_TBE
#define SPI_STAT_TBE
Definition: gd32f10x_spi.h:61
SPI_INT_FLAG_CRCERR
#define SPI_INT_FLAG_CRCERR
Definition: gd32f10x_spi.h:211
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f10x_spi.h:55
SPI_I2S_INT_FLAG_TBE
#define SPI_I2S_INT_FLAG_TBE
Definition: gd32f10x_spi.h:207
SPI_STAT_CRCERR
#define SPI_STAT_CRCERR
Definition: gd32f10x_spi.h:64
SPI_STAT_TXURERR
#define SPI_STAT_TXURERR
Definition: gd32f10x_spi.h:63
SPI_I2S_INT_FLAG_RBNE
#define SPI_I2S_INT_FLAG_RBNE
Definition: gd32f10x_spi.h:208
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_I2S_INT_FLAG_RXORERR
#define SPI_I2S_INT_FLAG_RXORERR
Definition: gd32f10x_spi.h:209
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f10x_spi.h:26
I2S_INT_FLAG_TXURERR
#define I2S_INT_FLAG_TXURERR
Definition: gd32f10x_spi.h:212
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f10x_spi.h:56
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f10x_spi.h:57
SPI_INT_FLAG_CONFERR
#define SPI_INT_FLAG_CONFERR
Definition: gd32f10x_spi.h:210
SPI_STAT_RXORERR
#define SPI_STAT_RXORERR
Definition: gd32f10x_spi.h:66
SPI_STAT_RBNE
#define SPI_STAT_RBNE
Definition: gd32f10x_spi.h:60
void spi_init | ( | uint32_t | spi_periph,
 |  | spi_parameter_struct * | spi_struct
 | ) |  |

initialize SPI parameter

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | spi_struct | SPI parameter initialization stuct members of the structure and the member values are shown as below: device_mode: SPI_MASTER, SPI_SLAVE trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT nss: SPI_NSS_SOFT, SPI_NSS_HARD endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
[out] | none
Return values
none

Definition at line 69 of file gd32f10x_spi.c.

70 {
71 uint32_t reg = 0U;
72 reg = SPI_CTL0(spi_periph);
73 reg &= SPI_INIT_MASK;
74
75 /* select SPI as master or slave */
76 reg |= spi_struct->device_mode;
77 /* select SPI transfer mode */
78 reg |= spi_struct->trans_mode;
79 /* select SPI frame size */
80 reg |= spi_struct->frame_size;
81 /* select SPI NSS use hardware or software */
82 reg |= spi_struct->nss;
83 /* select SPI LSB or MSB */
84 reg |= spi_struct->endian;
85 /* select SPI polarity and phase */
86 reg |= spi_struct->clock_polarity_phase;
87 /* select SPI prescale to adjust transmit speed */
88 reg |= spi_struct->prescale;
89
90 /* write to SPI_CTL0 register */
91 SPI_CTL0(spi_periph) = (uint32_t)reg;
92
93 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
94 }
SPI_I2SCTL_I2SSEL
#define SPI_I2SCTL_I2SSEL
Definition: gd32f10x_spi.h:89
spi_parameter_struct::nss
uint32_t nss
Definition: gd32f10x_spi.h:103
spi_parameter_struct::device_mode
uint32_t device_mode
Definition: gd32f10x_spi.h:100
spi_parameter_struct::frame_size
uint32_t frame_size
Definition: gd32f10x_spi.h:102
spi_parameter_struct::trans_mode
uint32_t trans_mode
Definition: gd32f10x_spi.h:101
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
spi_parameter_struct::endian
uint32_t endian
Definition: gd32f10x_spi.h:104
SPI_INIT_MASK
#define SPI_INIT_MASK
Definition: gd32f10x_spi.c:15
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
spi_parameter_struct::clock_polarity_phase
uint32_t clock_polarity_phase
Definition: gd32f10x_spi.h:105
spi_parameter_struct::prescale
uint32_t prescale
Definition: gd32f10x_spi.h:106
void spi_nss_internal_high ( uint32_t spi_periph )

SPI NSS pin high level in software mode.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 309 of file gd32f10x_spi.c.

310 {
311 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
312 }
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f10x_spi.h:42
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_nss_internal_low ( uint32_t spi_periph )

SPI NSS pin low level in software mode.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 320 of file gd32f10x_spi.c.

321 {
322 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
323 }
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f10x_spi.h:42
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
void spi_nss_output_disable ( uint32_t spi_periph )

disable SPI NSS output

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 298 of file gd32f10x_spi.c.

299 {
300 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
301 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f10x_spi.h:54
void spi_nss_output_enable ( uint32_t spi_periph )

enable SPI NSS output

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 287 of file gd32f10x_spi.c.

288 {
289 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
290 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f10x_spi.h:54
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_timer.c File Reference

TIMER driver. More...

#include "gd32f10x_timer.h"

Go to the source code of this file.

Functions

void | timer_deinit (uint32_t timer_periph)
deinit a TIMER More...
void | timer_init (uint32_t timer_periph, timer_parameter_struct *initpara)
initialize TIMER counter More...
void | timer_enable (uint32_t timer_periph)
enable a TIMER More...
void | timer_disable (uint32_t timer_periph)
disable a TIMER More...
void | timer_auto_reload_shadow_enable (uint32_t timer_periph)
enable the auto reload shadow function More...
void | timer_auto_reload_shadow_disable (uint32_t timer_periph)
disable the auto reload shadow function More...
void | timer_update_event_enable (uint32_t timer_periph)
enable the update event More...
void | timer_update_event_disable (uint32_t timer_periph)
disable the update event More...
void | timer_counter_alignment (uint32_t timer_periph, uint16_t aligned)
set TIMER counter alignment mode More...
void | timer_counter_up_direction (uint32_t timer_periph)
set TIMER counter up direction More...
void | timer_counter_down_direction (uint32_t timer_periph)
set TIMER counter down direction More...
void | timer_prescaler_config (uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
configure TIMER prescaler More...
void | timer_repetition_value_config (uint32_t timer_periph, uint16_t repetition)
configure TIMER repetition register value More...
void | timer_autoreload_value_config (uint32_t timer_periph, uint32_t autoreload)
configure TIMER autoreload register value More...
void | timer_counter_value_config (uint32_t timer_periph, uint32_t counter)
configure TIMER counter register value More...
uint32_t | timer_counter_read (uint32_t timer_periph)
read TIMER counter value More...
uint16_t | timer_prescaler_read (uint32_t timer_periph)
read TIMER prescaler value More...
void | timer_single_pulse_mode_config (uint32_t timer_periph, uint8_t spmode)
configure TIMER single pulse mode More...
void | timer_update_source_config (uint32_t timer_periph, uint8_t update)
configure TIMER update source More...
void | timer_interrupt_enable (uint32_t timer_periph, uint32_t interrupt)
enable the TIMER interrupt More...
void | timer_interrupt_disable (uint32_t timer_periph, uint32_t interrupt)
disable the TIMER interrupt More...
FlagStatus | timer_interrupt_flag_get (uint32_t timer_periph, uint32_t interrupt)
get timer interrupt flag More...
void | timer_interrupt_flag_clear (uint32_t timer_periph, uint32_t interrupt)
clear TIMER interrupt flag More...
FlagStatus | timer_flag_get (uint32_t timer_periph, uint32_t flag)
get TIMER flags More...
void | timer_flag_clear (uint32_t timer_periph, uint32_t flag)
clear TIMER flags More...
void | timer_dma_enable (uint32_t timer_periph, uint16_t dma)
enable the TIMER DMA More...
void | timer_dma_disable (uint32_t timer_periph, uint16_t dma)
disable the TIMER DMA More...
void | timer_channel_dma_request_source_select (uint32_t timer_periph, uint8_t dma_request)
channel DMA request source selection More...
void | timer_dma_transfer_config (uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
configure the TIMER DMA transfer More...
void | timer_event_software_generate (uint32_t timer_periph, uint16_t event)
software generate events More...
void | timer_break_config (uint32_t timer_periph, timer_break_parameter_struct *breakpara)
configure TIMER break function More...
void | timer_break_enable (uint32_t timer_periph)
enable TIMER break function More...
void | timer_break_disable (uint32_t timer_periph)
disable TIMER break function More...
void | timer_automatic_output_enable (uint32_t timer_periph)
enable TIMER output automatic function More...
void | timer_automatic_output_disable (uint32_t timer_periph)
disable TIMER output automatic function More...
void | timer_primary_output_config (uint32_t timer_periph, ControlStatus newvalue)
configure TIMER primary output function More...
void | timer_channel_control_shadow_config (uint32_t timer_periph, ControlStatus newvalue)
channel capture/compare control shadow register enable More...
void | timer_channel_control_shadow_update_config (uint32_t timer_periph, uint8_t ccuctl)
configure TIMER channel control shadow register update control More...
void | timer_channel_output_config (uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
configure TIMER channel output function More...
void | timer_channel_output_mode_config (uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
configure TIMER channel output compare mode More...
void | timer_channel_output_pulse_value_config (uint32_t timer_periph, uint16_t channel, uint32_t pulse)
configure TIMER channel output pulse value More...
void | timer_channel_output_shadow_config (uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
configure TIMER channel output shadow function More...
void | timer_channel_output_fast_config (uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
configure TIMER channel output fast function More...
void | timer_channel_output_clear_config (uint32_t timer_periph, uint16_t channel, uint16_t occlear)
configure TIMER channel output clear function More...
void | timer_channel_output_polarity_config (uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
configure TIMER channel output polarity More...
void | timer_channel_complementary_output_polarity_config (uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
configure TIMER channel complementary output polarity More...
void | timer_channel_output_state_config (uint32_t timer_periph, uint16_t channel, uint32_t state)
configure TIMER channel enable state More...
void | timer_channel_complementary_output_state_config (uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
configure TIMER channel complementary output enable state More...
void | timer_input_capture_config (uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
configure TIMER input capture parameter More...
void | timer_channel_input_capture_prescaler_config (uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value More...
uint32_t | timer_channel_capture_value_register_read (uint32_t timer_periph, uint16_t channel)
read TIMER channel capture compare register value More...
void | timer_input_pwm_capture_config (uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
configure TIMER input pwm capture function More...
void | timer_hall_mode_config (uint32_t timer_periph, uint8_t hallmode)
configure TIMER hall sensor mode More...
void | timer_input_trigger_source_select (uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source More...
void | timer_master_output_trigger_source_select (uint32_t timer_periph, uint32_t outrigger)
select TIMER master mode output trigger source More...
void | timer_slave_mode_select (uint32_t timer_periph, uint32_t slavemode)
select TIMER slave mode More...
void | timer_master_slave_mode_config (uint32_t timer_periph, uint8_t masterslave)
configure TIMER master slave mode More...
void | timer_external_trigger_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input More...
void | timer_quadrature_decoder_mode_config (uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
configure TIMER quadrature decoder mode More...
void | timer_internal_clock_config (uint32_t timer_periph)
configure TIMER internal clock mode More...
void | timer_internal_trigger_as_external_clock_config (uint32_t timer_periph, uint32_t intrigger)
configure TIMER the internal trigger as external clock input More...
void | timer_external_trigger_as_external_clock_config (uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
configure TIMER the external trigger as external clock input More...
void | timer_external_clock_mode0_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode0 More...
void | timer_external_clock_mode1_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode1 More...
void | timer_external_clock_mode1_disable (uint32_t timer_periph)
disable TIMER the external clock mode1 More...

Detailed Description

TIMER driver.

Definition in file gd32f10x_timer.c.

Function Documentation

void timer_auto_reload_shadow_disable ( uint32_t timer_periph )

disable the auto reload shadow function

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 185 of file gd32f10x_timer.c.

186 {
187 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
188 }
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f10x_timer.h:64
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_auto_reload_shadow_enable ( uint32_t timer_periph )

enable the auto reload shadow function

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 174 of file gd32f10x_timer.c.

175 {
176 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
177 }
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f10x_timer.h:64
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_automatic_output_disable ( uint32_t timer_periph )

disable TIMER output automatic function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 684 of file gd32f10x_timer.c.

685 {
686 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
687 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f10x_timer.h:214
void timer_automatic_output_enable ( uint32_t timer_periph )

enable TIMER output automatic function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 673 of file gd32f10x_timer.c.

674 {
675 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
676 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f10x_timer.h:214
void timer_autoreload_value_config | ( | uint32_t | timer_periph,
 |  | uint32_t | autoreload
 | ) |  |

configure TIMER autoreload register value

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] | autoreload | the counter auto-reload value
[out] | none
Return values
none

Definition at line 289 of file gd32f10x_timer.c.

290 {
291 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
292 }
TIMER_CAR
#define TIMER_CAR(timerx)
Definition: gd32f10x_timer.h:46
void timer_break_config | ( | uint32_t | timer_periph,
 |  | timer_break_parameter_struct * | breakpara
 | ) |  |

configure TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] | breakpara | TIMER break parameter struct runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE deadtime: 0~255 breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
[out] | none
Return values
none

Definition at line 634 of file gd32f10x_timer.c.

635 {
636 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
637 ((uint32_t)(breakpara->ideloffstate)) |
638 ((uint32_t)(breakpara->deadtime)) |
639 ((uint32_t)(breakpara->breakpolarity)) |
640 ((uint32_t)(breakpara->outputautostate)) |
641 ((uint32_t)(breakpara->protectmode)) |
642 ((uint32_t)(breakpara->breakstate))) ;
643 }
timer_break_parameter_struct::deadtime
uint16_t deadtime
Definition: gd32f10x_timer.h:241
timer_break_parameter_struct::ideloffstate
uint32_t ideloffstate
Definition: gd32f10x_timer.h:240
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
timer_break_parameter_struct::outputautostate
uint16_t outputautostate
Definition: gd32f10x_timer.h:243
timer_break_parameter_struct::runoffstate
uint16_t runoffstate
Definition: gd32f10x_timer.h:239
timer_break_parameter_struct::breakpolarity
uint16_t breakpolarity
Definition: gd32f10x_timer.h:242
timer_break_parameter_struct::breakstate
uint16_t breakstate
Definition: gd32f10x_timer.h:245
timer_break_parameter_struct::protectmode
uint16_t protectmode
Definition: gd32f10x_timer.h:244
void timer_break_disable ( uint32_t timer_periph )

disable TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 662 of file gd32f10x_timer.c.

663 {
664 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
665 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_BRKEN
#define TIMER_CCHP_BRKEN
Definition: gd32f10x_timer.h:212
void timer_break_enable ( uint32_t timer_periph )

enable TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 651 of file gd32f10x_timer.c.

652 {
653 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
654 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_BRKEN
#define TIMER_CCHP_BRKEN
Definition: gd32f10x_timer.h:212
uint32_t timer_channel_capture_value_register_read | ( | uint32_t | timer_periph,
 |  | uint16_t | channel
 | ) |  |

read TIMER channel capture compare register value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[out] | none
Return values
channel capture compare register value

Definition at line 1398 of file gd32f10x_timer.c.

1399 {
1400 uint32_t count_value = 0U;
1401
1402 switch(channel){
1403 case TIMER_CH_0:
1404 count_value = TIMER_CH0CV(timer_periph);
1405 break;
1406 case TIMER_CH_1:
1407 count_value = TIMER_CH1CV(timer_periph);
1408 break;
1409 case TIMER_CH_2:
1410 count_value = TIMER_CH2CV(timer_periph);
1411 break;
1412 case TIMER_CH_3:
1413 count_value = TIMER_CH3CV(timer_periph);
1414 break;
1415 default:
1416 break;
1417 }
1418 return (count_value);
1419 }
TIMER_CH1CV
#define TIMER_CH1CV(timerx)
Definition: gd32f10x_timer.h:49
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CH2CV
#define TIMER_CH2CV(timerx)
Definition: gd32f10x_timer.h:50
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f10x_timer.h:51
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f10x_timer.h:48
void timer_channel_complementary_output_polarity_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocnpolarity
 | ) |  |

configure TIMER channel complementary output polarity

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
[in] ocnpolarity channel complementary output polarity
  • TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
  • TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
[out] | none
Return values
none

Definition at line 1139 of file gd32f10x_timer.c.

1140 {
1141 switch(channel){
1142 /* configure TIMER_CH_0 */
1143 case TIMER_CH_0:
1144 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1145 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1146 break;
1147 /* configure TIMER_CH_1 */
1148 case TIMER_CH_1:
1149 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1150 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1151 break;
1152 /* configure TIMER_CH_2 */
1153 case TIMER_CH_2:
1154 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1155 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1156 break;
1157 default:
1158 break;
1159 }
1160 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f10x_timer.h:179
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_complementary_output_state_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocnstate
 | ) |  |

configure TIMER channel complementary output enable state

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] channel
  • TIMER_CH_0: TIMER channel0
  • TIMER_CH_1: TIMER channel1
  • TIMER_CH_2: TIMER channel2
[in] ocnstate TIMER channel complementary output enable state
  • TIMER_CCXN_ENABLE: channel complementary enable
  • TIMER_CCXN_DISABLE: channel complementary disable
[out] | none
Return values
none

Definition at line 1217 of file gd32f10x_timer.c.

1218 {
1219 switch(channel){
1220 /* configure TIMER_CH_0 */
1221 case TIMER_CH_0:
1222 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1223 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1224 break;
1225 /* configure TIMER_CH_1 */
1226 case TIMER_CH_1:
1227 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1228 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1229 break;
1230 /* configure TIMER_CH_2 */
1231 case TIMER_CH_2:
1232 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1233 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1234 break;
1235 default:
1236 break;
1237 }
1238 }
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f10x_timer.h:170
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f10x_timer.h:178
TIMER_CHCTL2_CH1NEN
#define TIMER_CHCTL2_CH1NEN
Definition: gd32f10x_timer.h:174
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_control_shadow_config | ( | uint32_t | timer_periph,
 |  | ControlStatus | newvalue
 | ) |  |

channel capture/compare control shadow register enable

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 712 of file gd32f10x_timer.c.

713 {
714 if(ENABLE == newvalue){
715 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
716 }else{
717 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
718 }
719 }
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_CTL1_CCSE
#define TIMER_CTL1_CCSE
Definition: gd32f10x_timer.h:68
void timer_channel_control_shadow_update_config | ( | uint32_t | timer_periph,
 |  | uint8_t | ccuctl
 | ) |  |

configure TIMER channel control shadow register update control

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] ccuctl channel control shadow register update control
  • TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
  • TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
[out] | none
Return values
none

Definition at line 730 of file gd32f10x_timer.c.

731 {
732 if(TIMER_UPDATECTL_CCU == ccuctl){
733 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
734 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
735 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
736 }else{
737 }
738 }
TIMER_UPDATECTL_CCU
#define TIMER_UPDATECTL_CCU
Definition: gd32f10x_timer.h:478
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_CTL1_CCUC
#define TIMER_CTL1_CCUC
Definition: gd32f10x_timer.h:69
TIMER_UPDATECTL_CCUTRI
#define TIMER_UPDATECTL_CCUTRI
Definition: gd32f10x_timer.h:479
void timer_channel_dma_request_source_select | ( | uint32_t | timer_periph,
 |  | uint8_t | dma_request
 | ) |  |

channel DMA request source selection

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] dma_request channel DMA request source selection
  • TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
  • TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
[out] | none
Return values
none

Definition at line 555 of file gd32f10x_timer.c.

556 {
557 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
558 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
559 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
560 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
561 }else{
562 }
563 }
TIMER_CTL1_DMAS
#define TIMER_CTL1_DMAS
Definition: gd32f10x_timer.h:70
TIMER_DMAREQUEST_CHANNELEVENT
#define TIMER_DMAREQUEST_CHANNELEVENT
Definition: gd32f10x_timer.h:313
TIMER_DMAREQUEST_UPDATEEVENT
#define TIMER_DMAREQUEST_UPDATEEVENT
Definition: gd32f10x_timer.h:312
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
void timer_channel_input_capture_prescaler_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | prescaler
 | ) |  |

configure TIMER channel input capture prescaler value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] prescaler channel input capture prescaler value
  • TIMER_IC_PSC_DIV1: no prescaler
  • TIMER_IC_PSC_DIV2: divided by 2
  • TIMER_IC_PSC_DIV4: divided by 4
  • TIMER_IC_PSC_DIV8: divided by 8
[out] | none
Return values
none

Definition at line 1359 of file gd32f10x_timer.c.

1360 {
1361 switch(channel){
1362 /* configure TIMER_CH_0 */
1363 case TIMER_CH_0:
1364 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1365 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1366 break;
1367 /* configure TIMER_CH_1 */
1368 case TIMER_CH_1:
1369 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1370 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1371 break;
1372 /* configure TIMER_CH_2 */
1373 case TIMER_CH_2:
1374 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1375 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1376 break;
1377 /* configure TIMER_CH_3 */
1378 case TIMER_CH_3:
1379 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1380 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1381 break;
1382 default:
1383 break;
1384 }
1385 }
TIMER_CHCTL0_CH0CAPPSC
#define TIMER_CHCTL0_CH0CAPPSC
Definition: gd32f10x_timer.h:144
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL1_CH3CAPPSC
#define TIMER_CHCTL1_CH3CAPPSC
Definition: gd32f10x_timer.h:164
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL0_CH1CAPPSC
#define TIMER_CHCTL0_CH1CAPPSC
Definition: gd32f10x_timer.h:146
TIMER_CHCTL1_CH2CAPPSC
#define TIMER_CHCTL1_CH2CAPPSC
Definition: gd32f10x_timer.h:162
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_output_clear_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | occlear
 | ) |  |

configure TIMER channel output clear function

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] channel
  • TIMER_CH_0: TIMER channel0
  • TIMER_CH_1: TIMER channel1
  • TIMER_CH_2: TIMER channel2
  • TIMER_CH_3: TIMER channel3
[in] occlear channel output clear function
  • TIMER_OC_CLEAR_ENABLE: channel output clear function enable
  • TIMER_OC_CLEAR_DISABLE: channel output clear function disable
[out] | none
Return values
none

Definition at line 1056 of file gd32f10x_timer.c.

1057 {
1058 switch(channel){
1059 /* configure TIMER_CH_0 */
1060 case TIMER_CH_0:
1061 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1062 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1063 break;
1064 /* configure TIMER_CH_1 */
1065 case TIMER_CH_1:
1066 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1067 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1068 break;
1069 /* configure TIMER_CH_2 */
1070 case TIMER_CH_2:
1071 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1072 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1073 break;
1074 /* configure TIMER_CH_3 */
1075 case TIMER_CH_3:
1076 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1077 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1078 break;
1079 default:
1080 break;
1081 }
1082 }
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL0_CH1COMCEN
#define TIMER_CHCTL0_CH1COMCEN
Definition: gd32f10x_timer.h:142
TIMER_CHCTL1_CH2COMCEN
#define TIMER_CHCTL1_CH2COMCEN
Definition: gd32f10x_timer.h:155
TIMER_CHCTL1_CH3COMCEN
#define TIMER_CHCTL1_CH3COMCEN
Definition: gd32f10x_timer.h:160
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL0_CH0COMCEN
#define TIMER_CHCTL0_CH0COMCEN
Definition: gd32f10x_timer.h:137
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_output_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_oc_parameter_struct * | ocpara
 | ) |  |

configure TIMER channel output function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7))
[in] | ocpara | TIMER channeln output parameter struct outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
[out] | none
Return values
none

Definition at line 758 of file gd32f10x_timer.c.

759 {
760 switch(channel){
761 /* configure TIMER_CH_0 */
762 case TIMER_CH_0:
763 /* reset the CH0EN bit */
764 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
765 /* set the CH0EN bit */
766 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
767 /* reset the CH0P bit */
768 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
769 /* set the CH0P bit */
770 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
771
772 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
773 /* reset the CH0NEN bit */
774 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
775 /* set the CH0NEN bit */
776 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
777 /* reset the CH0NP bit */
778 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
779 /* set the CH0NP bit */
780 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
781 /* reset the ISO0 bit */
782 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
783 /* set the ISO0 bit */
784 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
785 /* reset the ISO0N bit */
786 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
787 /* set the ISO0N bit */
788 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
789 }
790 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
791 break;
792 /* configure TIMER_CH_1 */
793 case TIMER_CH_1:
794 /* reset the CH1EN bit */
795 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
796 /* set the CH1EN bit */
797 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 4U);
798 /* reset the CH1P bit */
799 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
800 /* set the CH1P bit */
801 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U);
802
803 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
804 /* reset the CH1NEN bit */
805 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
806 /* set the CH1NEN bit */
807 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U);
808 /* reset the CH1NP bit */
809 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
810 /* set the CH1NP bit */
811 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U);
812 /* reset the ISO1 bit */
813 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
814 /* set the ISO1 bit */
815 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U);
816 /* reset the ISO1N bit */
817 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
818 /* set the ISO1N bit */
819 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U);
820 }
821 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
822 break;
823 /* configure TIMER_CH_2 */
824 case TIMER_CH_2:
825 /* reset the CH2EN bit */
826 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
827 /* set the CH2EN bit */
828 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 8U);
829 /* reset the CH2P bit */
830 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
831 /* set the CH2P bit */
832 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U);
833
834 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
835 /* reset the CH2NEN bit */
836 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
837 /* set the CH2NEN bit */
838 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U);
839 /* reset the CH2NP bit */
840 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
841 /* set the CH2NP bit */
842 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U);
843 /* reset the ISO2 bit */
844 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
845 /* set the ISO2 bit */
846 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U);
847 /* reset the ISO2N bit */
848 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
849 /* set the ISO2N bit */
850 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U);
851 }
852 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
853 break;
854 /* configure TIMER_CH_3 */
855 case TIMER_CH_3:
856 /* reset the CH3EN bit */
857 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
858 /* set the CH3EN bit */
859 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 12U);
860 /* reset the CH3P bit */
861 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
862 /* set the CH3P bit */
863 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U);
864
865 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
866 /* reset the ISO3 bit */
867 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
868 /* set the ISO3 bit */
869 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U);
870 }
871 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
872 break;
873 default:
874 break;
875 }
876 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CTL1_ISO2
#define TIMER_CTL1_ISO2
Definition: gd32f10x_timer.h:77
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f10x_timer.h:170
TIMER_CTL1_ISO3
#define TIMER_CTL1_ISO3
Definition: gd32f10x_timer.h:79
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
TIMER7
#define TIMER7
Definition: gd32f10x_timer.h:26
timer_oc_parameter_struct::ocnidlestate
uint16_t ocnidlestate
Definition: gd32f10x_timer.h:256
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f10x_timer.h:179
TIMER_CHCTL1_CH2MS
#define TIMER_CHCTL1_CH2MS
Definition: gd32f10x_timer.h:151
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CTL1_ISO0
#define TIMER_CTL1_ISO0
Definition: gd32f10x_timer.h:73
timer_oc_parameter_struct::ocpolarity
uint16_t ocpolarity
Definition: gd32f10x_timer.h:253
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f10x_timer.h:180
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f10x_timer.h:178
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_CTL1_ISO2N
#define TIMER_CTL1_ISO2N
Definition: gd32f10x_timer.h:78
TIMER_CHCTL2_CH1NEN
#define TIMER_CHCTL2_CH1NEN
Definition: gd32f10x_timer.h:174
TIMER0
#define TIMER0
Definition: gd32f10x_timer.h:19
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f10x_timer.h:176
TIMER_CTL1_ISO0N
#define TIMER_CTL1_ISO0N
Definition: gd32f10x_timer.h:74
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CTL1_ISO1N
#define TIMER_CTL1_ISO1N
Definition: gd32f10x_timer.h:76
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f10x_timer.h:177
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
timer_oc_parameter_struct::outputstate
uint32_t outputstate
Definition: gd32f10x_timer.h:251
timer_oc_parameter_struct::ocidlestate
uint16_t ocidlestate
Definition: gd32f10x_timer.h:255
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
TIMER_CTL1_ISO1
#define TIMER_CTL1_ISO1
Definition: gd32f10x_timer.h:75
timer_oc_parameter_struct::ocnpolarity
uint16_t ocnpolarity
Definition: gd32f10x_timer.h:254
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f10x_timer.h:181
timer_oc_parameter_struct::outputnstate
uint16_t outputnstate
Definition: gd32f10x_timer.h:252
TIMER_CHCTL1_CH3MS
#define TIMER_CHCTL1_CH3MS
Definition: gd32f10x_timer.h:156
void timer_channel_output_fast_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocfast
 | ) |  |

configure TIMER channel output fast function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] ocfast channel output fast function
  • TIMER_OC_FAST_ENABLE: channel output fast function enable
  • TIMER_OC_FAST_DISABLE: channel output fast function disable
[out] | none
Return values
none

Definition at line 1014 of file gd32f10x_timer.c.

1015 {
1016 switch(channel){
1017 /* configure TIMER_CH_0 */
1018 case TIMER_CH_0:
1019 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
1020 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
1021 break;
1022 /* configure TIMER_CH_1 */
1023 case TIMER_CH_1:
1024 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
1025 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1026 break;
1027 /* configure TIMER_CH_2 */
1028 case TIMER_CH_2:
1029 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
1030 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
1031 break;
1032 /* configure TIMER_CH_3 */
1033 case TIMER_CH_3:
1034 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
1035 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1036 break;
1037 default:
1038 break;
1039 }
1040 }
TIMER_CHCTL0_CH1COMFEN
#define TIMER_CHCTL0_CH1COMFEN
Definition: gd32f10x_timer.h:139
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL1_CH3COMFEN
#define TIMER_CHCTL1_CH3COMFEN
Definition: gd32f10x_timer.h:157
TIMER_CHCTL0_CH0COMFEN
#define TIMER_CHCTL0_CH0COMFEN
Definition: gd32f10x_timer.h:134
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL1_CH2COMFEN
#define TIMER_CHCTL1_CH2COMFEN
Definition: gd32f10x_timer.h:152
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_output_mode_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocmode
 | ) |  |

configure TIMER channel output compare mode

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] ocmode channel output compare mode
  • TIMER_OC_MODE_TIMING: timing mode
  • TIMER_OC_MODE_ACTIVE: active mode
  • TIMER_OC_MODE_INACTIVE: inactive mode
  • TIMER_OC_MODE_TOGGLE: toggle mode
  • TIMER_OC_MODE_LOW: force low mode
  • TIMER_OC_MODE_HIGH: force high mode
  • TIMER_OC_MODE_PWM0: PWM0 mode
  • TIMER_OC_MODE_PWM1: PWM1 mode
[out] | none
Return values
none

Definition at line 898 of file gd32f10x_timer.c.

899 {
900 switch(channel){
901 /* configure TIMER_CH_0 */
902 case TIMER_CH_0:
903 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
904 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
905 break;
906 /* configure TIMER_CH_1 */
907 case TIMER_CH_1:
908 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
909 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U);
910 break;
911 /* configure TIMER_CH_2 */
912 case TIMER_CH_2:
913 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
914 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
915 break;
916 /* configure TIMER_CH_3 */
917 case TIMER_CH_3:
918 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
919 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U);
920 break;
921 default:
922 break;
923 }
924 }
TIMER_CHCTL0_CH0COMCTL
#define TIMER_CHCTL0_CH0COMCTL
Definition: gd32f10x_timer.h:136
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL1_CH2COMCTL
#define TIMER_CHCTL1_CH2COMCTL
Definition: gd32f10x_timer.h:154
TIMER_CHCTL0_CH1COMCTL
#define TIMER_CHCTL0_CH1COMCTL
Definition: gd32f10x_timer.h:141
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CHCTL1_CH3COMCTL
#define TIMER_CHCTL1_CH3COMCTL
Definition: gd32f10x_timer.h:159
void timer_channel_output_polarity_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocpolarity
 | ) |  |

configure TIMER channel output polarity

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] ocpolarity channel output polarity
  • TIMER_OC_POLARITY_HIGH: channel output polarity is high
  • TIMER_OC_POLARITY_LOW: channel output polarity is low
[out] | none
Return values
none

Definition at line 1098 of file gd32f10x_timer.c.

1099 {
1100 switch(channel){
1101 /* configure TIMER_CH_0 */
1102 case TIMER_CH_0:
1103 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1104 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1105 break;
1106 /* configure TIMER_CH_1 */
1107 case TIMER_CH_1:
1108 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1109 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1110 break;
1111 /* configure TIMER_CH_2 */
1112 case TIMER_CH_2:
1113 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1114 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1115 break;
1116 /* configure TIMER_CH_3 */
1117 case TIMER_CH_3:
1118 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1119 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1120 break;
1121 default:
1122 break;
1123 }
1124 }
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f10x_timer.h:177
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f10x_timer.h:181
void timer_channel_output_pulse_value_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint32_t | pulse
 | ) |  |

configure TIMER channel output pulse value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] | pulse | channel output pulse value
[out] | none
Return values
none

Definition at line 938 of file gd32f10x_timer.c.

939 {
940 switch(channel){
941 case TIMER_CH_0:
942 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
943 break;
944 case TIMER_CH_1:
945 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
946 break;
947 case TIMER_CH_2:
948 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
949 break;
950 case TIMER_CH_3:
951 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
952 break;
953 default:
954 break;
955 }
956 }
TIMER_CH1CV
#define TIMER_CH1CV(timerx)
Definition: gd32f10x_timer.h:49
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CH2CV
#define TIMER_CH2CV(timerx)
Definition: gd32f10x_timer.h:50
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f10x_timer.h:51
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f10x_timer.h:48
void timer_channel_output_shadow_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocshadow
 | ) |  |

configure TIMER channel output shadow function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] ocshadow channel output shadow state
  • TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
  • TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
[out] | none
Return values
none

Definition at line 972 of file gd32f10x_timer.c.

973 {
974 switch(channel){
975 /* configure TIMER_CH_0 */
976 case TIMER_CH_0:
977 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
978 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
979 break;
980 /* configure TIMER_CH_1 */
981 case TIMER_CH_1:
982 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
983 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
984 break;
985 /* configure TIMER_CH_2 */
986 case TIMER_CH_2:
987 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
988 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
989 break;
990 /* configure TIMER_CH_3 */
991 case TIMER_CH_3:
992 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
993 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
994 break;
995 default:
996 break;
997 }
998 }
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL1_CH2COMSEN
#define TIMER_CHCTL1_CH2COMSEN
Definition: gd32f10x_timer.h:153
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL0_CH0COMSEN
#define TIMER_CHCTL0_CH0COMSEN
Definition: gd32f10x_timer.h:135
TIMER_CHCTL1_CH3COMSEN
#define TIMER_CHCTL1_CH3COMSEN
Definition: gd32f10x_timer.h:158
TIMER_CHCTL0_CH1COMSEN
#define TIMER_CHCTL0_CH1COMSEN
Definition: gd32f10x_timer.h:140
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_channel_output_state_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint32_t | state
 | ) |  |

configure TIMER channel enable state

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] state TIMER channel enable state
  • TIMER_CCX_ENABLE: channel enable
  • TIMER_CCX_DISABLE: channel disable
[out] | none
Return values
none

Definition at line 1176 of file gd32f10x_timer.c.

1177 {
1178 switch(channel){
1179 /* configure TIMER_CH_0 */
1180 case TIMER_CH_0:
1181 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1182 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1183 break;
1184 /* configure TIMER_CH_1 */
1185 case TIMER_CH_1:
1186 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1187 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1188 break;
1189 /* configure TIMER_CH_2 */
1190 case TIMER_CH_2:
1191 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1192 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1193 break;
1194 /* configure TIMER_CH_3 */
1195 case TIMER_CH_3:
1196 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1197 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1198 break;
1199 default:
1200 break;
1201 }
1202 }
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f10x_timer.h:180
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f10x_timer.h:176
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
void timer_counter_alignment | ( | uint32_t | timer_periph,
 |  | uint16_t | aligned
 | ) |  |

set TIMER counter alignment mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7..13)
[in] aligned
  • TIMER_COUNTER_EDGE: edge-aligned mode
  • TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
  • TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
  • TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
[out] | none
Return values
none

Definition at line 223 of file gd32f10x_timer.c.

224 {
225 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
226 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
227 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f10x_timer.h:63
void timer_counter_down_direction ( uint32_t timer_periph )

set TIMER counter down direction

Parameters
[in] | timer_periph | TIMERx(x=0..4,7..13)
[out] | none
Return values
none

Definition at line 246 of file gd32f10x_timer.c.

247 {
248 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
249 }
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f10x_timer.h:62
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
uint32_t timer_counter_read ( uint32_t timer_periph )

read TIMER counter value

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
counter value

Definition at line 312 of file gd32f10x_timer.c.

313 {
314 uint32_t count_value = 0U;
315 count_value = TIMER_CNT(timer_periph);
316 return (count_value);
317 }
TIMER_CNT
#define TIMER_CNT(timerx)
Definition: gd32f10x_timer.h:44
void timer_counter_up_direction ( uint32_t timer_periph )

set TIMER counter up direction

Parameters
[in] | timer_periph | TIMERx(x=0..4,7..13)
[out] | none
Return values
none

Definition at line 235 of file gd32f10x_timer.c.

236 {
237 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
238 }
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f10x_timer.h:62
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_counter_value_config | ( | uint32_t | timer_periph,
 |  | uint32_t | counter
 | ) |  |

configure TIMER counter register value

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] | counter | the counter value
[out] | none
Return values
none

Definition at line 301 of file gd32f10x_timer.c.

302 {
303 TIMER_CNT(timer_periph) = (uint32_t)counter;
304 }
TIMER_CNT
#define TIMER_CNT(timerx)
Definition: gd32f10x_timer.h:44
void timer_deinit ( uint32_t timer_periph )

deinit a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_timer.c.

22 {
23 switch(timer_periph){
24 case TIMER0:
25 /* reset TIMER0 */
26 rcu_periph_reset_enable(RCU_TIMER0RST);
27 rcu_periph_reset_disable(RCU_TIMER0RST);
28 break;
29 case TIMER1:
30 /* reset TIMER1 */
31 rcu_periph_reset_enable(RCU_TIMER1RST);
32 rcu_periph_reset_disable(RCU_TIMER1RST);
33 break;
34 case TIMER2:
35 /* reset TIMER2 */
36 rcu_periph_reset_enable(RCU_TIMER2RST);
37 rcu_periph_reset_disable(RCU_TIMER2RST);
38 break;
39 case TIMER3:
40 /* reset TIMER3 */
41 rcu_periph_reset_enable(RCU_TIMER3RST);
42 rcu_periph_reset_disable(RCU_TIMER3RST);
43 break;
44 case TIMER4:
45 /* reset TIMER4 */
46 rcu_periph_reset_enable(RCU_TIMER4RST);
47 rcu_periph_reset_disable(RCU_TIMER4RST);
48 break;
49 case TIMER5:
50 /* reset TIMER5 */
51 rcu_periph_reset_enable(RCU_TIMER5RST);
52 rcu_periph_reset_disable(RCU_TIMER5RST);
53 break;
54 case TIMER6:
55 /* reset TIMER6 */
56 rcu_periph_reset_enable(RCU_TIMER6RST);
57 rcu_periph_reset_disable(RCU_TIMER6RST);
58 break;
59 case TIMER7:
60 /* reset TIMER7 */
61 rcu_periph_reset_enable(RCU_TIMER7RST);
62 rcu_periph_reset_disable(RCU_TIMER7RST);
63 break;
64 #ifdef GD32F10X_XD
65 case TIMER8:
66 /* reset TIMER8 */
67 rcu_periph_reset_enable(RCU_TIMER8RST);
68 rcu_periph_reset_disable(RCU_TIMER8RST);
69 break;
70 case TIMER9:
71 /* reset TIMER9 */
72 rcu_periph_reset_enable(RCU_TIMER9RST);
73 rcu_periph_reset_disable(RCU_TIMER9RST);
74 break;
75 case TIMER10:
76 /* reset TIMER10 */
77 rcu_periph_reset_enable(RCU_TIMER10RST);
78 rcu_periph_reset_disable(RCU_TIMER10RST);
79 break;
80 case TIMER11:
81 /* reset TIMER11 */
82 rcu_periph_reset_enable(RCU_TIMER11RST);
83 rcu_periph_reset_disable(RCU_TIMER11RST);
84 break;
85 case TIMER12:
86 /* reset TIMER12 */
87 rcu_periph_reset_enable(RCU_TIMER12RST);
88 rcu_periph_reset_disable(RCU_TIMER12RST);
89 break;
90 case TIMER13:
91 /* reset TIMER13 */
92 rcu_periph_reset_enable(RCU_TIMER13RST);
93 rcu_periph_reset_disable(RCU_TIMER13RST);
94 break;
95 #endif /* GD32F10X_XD */
96 default:
97 break;
98 }
99 }
RCU_TIMER11RST
Definition: gd32f10x_rcu.h:452
TIMER7
#define TIMER7
Definition: gd32f10x_timer.h:26
RCU_TIMER2RST
Definition: gd32f10x_rcu.h:446
RCU_TIMER8RST
Definition: gd32f10x_rcu.h:495
TIMER13
#define TIMER13
Definition: gd32f10x_timer.h:32
RCU_TIMER7RST
Definition: gd32f10x_rcu.h:489
RCU_TIMER5RST
Definition: gd32f10x_rcu.h:449
RCU_TIMER4RST
Definition: gd32f10x_rcu.h:448
RCU_TIMER6RST
Definition: gd32f10x_rcu.h:450
TIMER9
#define TIMER9
Definition: gd32f10x_timer.h:28
TIMER5
#define TIMER5
Definition: gd32f10x_timer.h:24
TIMER11
#define TIMER11
Definition: gd32f10x_timer.h:30
TIMER8
#define TIMER8
Definition: gd32f10x_timer.h:27
TIMER12
#define TIMER12
Definition: gd32f10x_timer.h:31
TIMER0
#define TIMER0
Definition: gd32f10x_timer.h:19
RCU_TIMER1RST
Definition: gd32f10x_rcu.h:445
RCU_TIMER9RST
Definition: gd32f10x_rcu.h:496
RCU_TIMER12RST
Definition: gd32f10x_rcu.h:453
TIMER1
#define TIMER1
Definition: gd32f10x_timer.h:20
RCU_TIMER10RST
Definition: gd32f10x_rcu.h:497
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
TIMER2
#define TIMER2
Definition: gd32f10x_timer.h:21
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
TIMER6
#define TIMER6
Definition: gd32f10x_timer.h:25
RCU_TIMER3RST
Definition: gd32f10x_rcu.h:447
TIMER3
#define TIMER3
Definition: gd32f10x_timer.h:22
TIMER10
#define TIMER10
Definition: gd32f10x_timer.h:29
RCU_TIMER0RST
Definition: gd32f10x_rcu.h:487
RCU_TIMER13RST
Definition: gd32f10x_rcu.h:454
TIMER4
#define TIMER4
Definition: gd32f10x_timer.h:23
void timer_disable ( uint32_t timer_periph )

disable a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 163 of file gd32f10x_timer.c.

164 {
165 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
166 }
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f10x_timer.h:58
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_dma_disable | ( | uint32_t | timer_periph,
 |  | uint16_t | dma
 | ) |  |

disable the TIMER DMA

Parameters
[in] | timer_periph | please refer to the following parameters
[in] dma timer DMA source enable
  • TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7)
  • TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7)
  • TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7)
[out] | none
Return values
none

Definition at line 541 of file gd32f10x_timer.c.

542 {
543 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
544 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_dma_enable | ( | uint32_t | timer_periph,
 |  | uint16_t | dma
 | ) |  |

enable the TIMER DMA

Parameters
[in] | timer_periph | TIMERx(x=0,1,2,5,14,15,16)
[in] dma timer DMA source enable
  • TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7)
  • TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7)
  • TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7)
  • TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7)
[out] | none
Return values
none

Definition at line 522 of file gd32f10x_timer.c.

523 {
524 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
525 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_dma_transfer_config | ( | uint32_t | timer_periph,
 |  | uint32_t | dma_baseaddr,
 |  | uint32_t | dma_lenth
 | ) |  |

configure the TIMER DMA transfer

Parameters
[in] | timer_periph | please refer to the following parameters
[in] dma_baseaddr
  • TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7)
  • TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7)
  • TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7)
  • TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7)
[in] dma_lenth
  • TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
[out] | none
Return values
none

Definition at line 594 of file gd32f10x_timer.c.

595 {
596 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
597 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
598 }
TIMER_DMACFG
#define TIMER_DMACFG(timerx)
Definition: gd32f10x_timer.h:53
TIMER_DMACFG_DMATA
#define TIMER_DMACFG_DMATA
Definition: gd32f10x_timer.h:218
TIMER_DMACFG_DMATC
#define TIMER_DMACFG_DMATC
Definition: gd32f10x_timer.h:219
void timer_enable ( uint32_t timer_periph )

enable a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 152 of file gd32f10x_timer.c.

153 {
154 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
155 }
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f10x_timer.h:58
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_event_software_generate | ( | uint32_t | timer_periph,
 |  | uint16_t | event
 | ) |  |

software generate events

Parameters
[in] | timer_periph | please refer to the following parameters
[in] event the timer software event generation sources
  • TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13)
  • TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13)
  • TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11)
  • TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7)
  • TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7)
  • TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7)
  • TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11)
  • TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 615 of file gd32f10x_timer.c.

616 {
617 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
618 }
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f10x_timer.h:40
void timer_external_clock_mode0_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external clock mode0

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1791 of file gd32f10x_timer.c.

1793 {
1794 /* configure TIMER external trigger input */
1795 timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter);
1796
1797 /* reset the SMC bit,TRGS bit */
1798 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1799 /* set the SMC bit,TRGS bit */
1800 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1801 }
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f10x_timer.c:1649
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f10x_timer.h:528
TIMER_SMCFG_TRGSEL_ETIFP
#define TIMER_SMCFG_TRGSEL_ETIFP
Definition: gd32f10x_timer.h:506
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f10x_timer.h:83
void timer_external_clock_mode1_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external clock mode1

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1818 of file gd32f10x_timer.c.

1820 {
1821 /* configure TIMER external trigger input */
1822 timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter);
1823
1824 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1825 }
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f10x_timer.c:1649
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f10x_timer.h:87
void timer_external_clock_mode1_disable ( uint32_t timer_periph )

disable TIMER the external clock mode1

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[out] | none
Return values
none

Definition at line 1833 of file gd32f10x_timer.c.

1834 {
1835 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1836 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f10x_timer.h:87
void timer_external_trigger_as_external_clock_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extrigger,
 |  | uint16_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external trigger as external clock input

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] extrigger
  • TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
  • TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
  • TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
[in] expolarity
  • TIMER_IC_POLARITY_RISING: active low or falling edge active
  • TIMER_IC_POLARITY_FALLING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1730 of file gd32f10x_timer.c.

1732 {
1733 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1734 /* reset the CH1EN bit */
1735 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1736 /* reset the CH1NP bit */
1737 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1738 /* set the CH1NP bit */
1739 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U);
1740 /* reset the CH1MS bit */
1741 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1742 /* set the CH1MS bit */
1743 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U);
1744 /* reset the CH1CAPFLT bit */
1745 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1746 /* set the CH1CAPFLT bit */
1747 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U);
1748 /* set the CH1EN bit */
1749 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1750 }else{
1751 /* reset the CH0EN bit */
1752 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1753 /* reset the CH0P and CH0NP bits */
1754 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1755 /* set the CH0P and CH0NP bits */
1756 TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity;
1757 /* reset the CH0MS bit */
1758 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1759 /* set the CH0MS bit */
1760 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1761 /* reset the CH0CAPFLT bit */
1762 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1763 /* reset the CH0CAPFLT bit */
1764 TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter;
1765 /* set the CH0EN bit */
1766 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1767 }
1768 /* select TIMER input trigger source */
1769 timer_input_trigger_source_select(timer_periph,extrigger);
1770 /* reset the SMC bit */
1771 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1772 /* set the SMC bit */
1773 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1774 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f10x_timer.h:147
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_TRGSEL_CI1FE1
#define TIMER_SMCFG_TRGSEL_CI1FE1
Definition: gd32f10x_timer.h:505
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f10x_timer.h:487
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f10x_timer.h:528
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f10x_timer.c:1565
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f10x_timer.h:145
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
void timer_external_trigger_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER external trigger input

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1649 of file gd32f10x_timer.c.

1651 {
1652 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP|TIMER_SMCFG_ETPSC|TIMER_SMCFG_ETFC));
1653 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler|expolarity);
1654 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter<< 8U);
1655 }
TIMER_SMCFG_ETPSC
#define TIMER_SMCFG_ETPSC
Definition: gd32f10x_timer.h:86
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_ETP
#define TIMER_SMCFG_ETP
Definition: gd32f10x_timer.h:88
TIMER_SMCFG_ETFC
#define TIMER_SMCFG_ETFC
Definition: gd32f10x_timer.h:85
void timer_flag_clear | ( | uint32_t | timer_periph,
 |  | uint32_t | flag
 | ) |  |

clear TIMER flags

Parameters
[in] | timer_periph | please refer to the following parameters
[in] flag the timer interrupt flags
  • TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
  • TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
  • TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
  • TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
  • TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
  • TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
  • TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
  • TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
  • TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
[out] | none
Return values
none

Definition at line 503 of file gd32f10x_timer.c.

504 {
505 TIMER_INTF(timer_periph) &= (~(uint32_t)flag);
506 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f10x_timer.h:39
FlagStatus timer_flag_get | ( | uint32_t | timer_periph,
 |  | uint32_t | flag
 | ) |  |

get TIMER flags

Parameters
[in] | timer_periph | please refer to the following parameters
[in] flag the timer interrupt flags
  • TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
  • TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
  • TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
  • TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
  • TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
  • TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
  • TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
  • TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
  • TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
  • TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 475 of file gd32f10x_timer.c.

476 {
477 if(RESET != (TIMER_INTF(timer_periph) & flag)){
478 return SET;
479 }else{
480 return RESET;
481 }
482 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f10x_timer.h:39
void timer_hall_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | hallmode
 | ) |  |

configure TIMER hall sensor mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7)
[in] hallmode
  • TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
  • TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
[out] | none
Return values
none

Definition at line 1540 of file gd32f10x_timer.c.

1541 {
1542 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1543 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1544 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1545 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1546 }else{
1547 }
1548 }
TIMER_CTL1_TI0S
#define TIMER_CTL1_TI0S
Definition: gd32f10x_timer.h:72
TIMER_HALLINTERFACE_ENABLE
#define TIMER_HALLINTERFACE_ENABLE
Definition: gd32f10x_timer.h:546
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_HALLINTERFACE_DISABLE
#define TIMER_HALLINTERFACE_DISABLE
Definition: gd32f10x_timer.h:547
void timer_init | ( | uint32_t | timer_periph,
 |  | timer_parameter_struct * | initpara
 | ) |  |

initialize TIMER counter

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] | initpara | init parameter struct prescaler: prescaler value of the counter clock,0~65535 alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN period: counter auto reload value clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 repetitioncounter: counter repetition value,0~255
[out] | none
Return values
none

Definition at line 114 of file gd32f10x_timer.c.

115 {
116 /* configure the counter prescaler value */
117 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
118
119 /* configure the counter direction and aligned mode */
120 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) ||
121 (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) ||
122 (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)){
123 TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM);
124 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
125 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
126 }
127
128 /* configure the autoreload value */
129 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
130
131 if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
132 /* reset the CKDIV bit */
133 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV;
134 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
135 }
136
137 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
138 /* configure the repetition counter value */
139 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
140 }
141
142 /* generate an update event */
143 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
144 }
TIMER7
#define TIMER7
Definition: gd32f10x_timer.h:26
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f10x_timer.h:62
TIMER_SWEVG_UPG
#define TIMER_SWEVG_UPG
Definition: gd32f10x_timer.h:122
TIMER13
#define TIMER13
Definition: gd32f10x_timer.h:32
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f10x_timer.h:40
TIMER_CAR
#define TIMER_CAR(timerx)
Definition: gd32f10x_timer.h:46
TIMER9
#define TIMER9
Definition: gd32f10x_timer.h:28
TIMER5
#define TIMER5
Definition: gd32f10x_timer.h:24
TIMER11
#define TIMER11
Definition: gd32f10x_timer.h:30
TIMER8
#define TIMER8
Definition: gd32f10x_timer.h:27
TIMER_CTL0_CKDIV
#define TIMER_CTL0_CKDIV
Definition: gd32f10x_timer.h:65
TIMER12
#define TIMER12
Definition: gd32f10x_timer.h:31
TIMER0
#define TIMER0
Definition: gd32f10x_timer.h:19
timer_parameter_struct::clockdivision
uint16_t clockdivision
Definition: gd32f10x_timer.h:232
TIMER1
#define TIMER1
Definition: gd32f10x_timer.h:20
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f10x_timer.h:45
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f10x_timer.h:47
TIMER2
#define TIMER2
Definition: gd32f10x_timer.h:21
TIMER6
#define TIMER6
Definition: gd32f10x_timer.h:25
timer_parameter_struct::repetitioncounter
uint8_t repetitioncounter
Definition: gd32f10x_timer.h:233
TIMER3
#define TIMER3
Definition: gd32f10x_timer.h:22
timer_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f10x_timer.h:228
timer_parameter_struct::period
uint32_t period
Definition: gd32f10x_timer.h:231
TIMER10
#define TIMER10
Definition: gd32f10x_timer.h:29
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f10x_timer.h:63
timer_parameter_struct::alignedmode
uint16_t alignedmode
Definition: gd32f10x_timer.h:229
timer_parameter_struct::counterdirection
uint16_t counterdirection
Definition: gd32f10x_timer.h:230
TIMER4
#define TIMER4
Definition: gd32f10x_timer.h:23
void timer_input_capture_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_ic_parameter_struct * | icpara
 | ) |  |

configure TIMER input capture parameter

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
[in] | icpara | TIMER channel intput parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 icfilter: 0~15
[out] | none
Return values
none

Definition at line 1256 of file gd32f10x_timer.c.

1257 {
1258 switch(channel){
1259 /* configure TIMER_CH_0 */
1260 case TIMER_CH_0:
1261 /* reset the CH0EN bit */
1262 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1263
1264 /* reset the CH0P and CH0NP bits */
1265 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1266 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1267 /* reset the CH0MS bit */
1268 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1269 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1270 /* reset the CH0CAPFLT bit */
1271 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1272 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1273
1274 /* set the CH0EN bit */
1275 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1276 break;
1277
1278 /* configure TIMER_CH_1 */
1279 case TIMER_CH_1:
1280 /* reset the CH1EN bit */
1281 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1282
1283 /* reset the CH1P and CH1NP bits */
1284 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1285 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 4U);
1286 /* reset the CH1MS bit */
1287 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1288 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U);
1289 /* reset the CH1CAPFLT bit */
1290 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1291 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U);
1292
1293 /* set the CH1EN bit */
1294 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1295 break;
1296 /* configure TIMER_CH_2 */
1297 case TIMER_CH_2:
1298 /* reset the CH2EN bit */
1299 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1300
1301 /* reset the CH2P and CH2NP bits */
1302 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
1303 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 8U);
1304
1305 /* reset the CH2MS bit */
1306 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1307 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1308
1309 /* reset the CH2CAPFLT bit */
1310 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1311 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 4U);
1312
1313 /* set the CH2EN bit */
1314 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1315 break;
1316 /* configure TIMER_CH_3 */
1317 case TIMER_CH_3:
1318 /* reset the CH3EN bit */
1319 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1320
1321 /* reset the CH3P bits */
1322 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P));
1323 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 12U);
1324
1325 /* reset the CH3MS bit */
1326 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1327 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U);
1328
1329 /* reset the CH3CAPFLT bit */
1330 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1331 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U);
1332
1333 /* set the CH3EN bit */
1334 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1335 break;
1336 default:
1337 break;
1338 }
1339 /* configure TIMER channel input capture prescaler value */
1340 timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler));
1341 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f10x_timer.h:263
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f10x_timer.h:179
TIMER_CHCTL1_CH2MS
#define TIMER_CHCTL1_CH2MS
Definition: gd32f10x_timer.h:151
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f10x_timer.h:42
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f10x_timer.h:428
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f10x_timer.c:1359
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f10x_timer.h:147
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f10x_timer.h:180
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f10x_timer.h:264
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f10x_timer.h:176
TIMER_CHCTL1_CH3CAPFLT
#define TIMER_CHCTL1_CH3CAPFLT
Definition: gd32f10x_timer.h:165
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f10x_timer.h:177
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f10x_timer.h:262
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f10x_timer.h:145
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
TIMER_CHCTL1_CH2CAPFLT
#define TIMER_CHCTL1_CH2CAPFLT
Definition: gd32f10x_timer.h:163
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f10x_timer.h:181
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f10x_timer.h:265
TIMER_CHCTL1_CH3MS
#define TIMER_CHCTL1_CH3MS
Definition: gd32f10x_timer.h:156
void timer_input_pwm_capture_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_ic_parameter_struct * | icpwm
 | ) |  |

configure TIMER input pwm capture function

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] channel
  • TIMER_CH_0: TIMER channel0
  • TIMER_CH_1: TIMER channel1
[in] | icpwm:TIMER | channel intput pwm parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 icfilter: 0~15
[out] | none
Return values
none

Definition at line 1435 of file gd32f10x_timer.c.

1436 {
1437 uint16_t icpolarity = 0x0U;
1438 uint16_t icselection = 0x0U;
1439
1440 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1441 icpolarity = TIMER_IC_POLARITY_FALLING;
1442 }else{
1443 icpolarity = TIMER_IC_POLARITY_RISING;
1444 }
1445
1446 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1447 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1448 }else{
1449 icselection = TIMER_IC_SELECTION_DIRECTTI;
1450 }
1451
1452 if(TIMER_CH_0 == channel){
1453 /* reset the CH0EN bit */
1454 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1455 /* reset the CH0P and CH0NP bits */
1456 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1457 /* set the CH0P and CH0NP bits */
1458 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1459 /* reset the CH0MS bit */
1460 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1461 /* set the CH0MS bit */
1462 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1463 /* reset the CH0CAPFLT bit */
1464 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1465 /* set the CH0CAPFLT bit */
1466 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1467 /* set the CH0EN bit */
1468 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1469 /* configure TIMER channel input capture prescaler value */
1470 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1471
1472 /* reset the CH1EN bit */
1473 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1474 /* reset the CH1P and CH1NP bits */
1475 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1476 /* set the CH1P and CH1NP bits */
1477 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U);
1478 /* reset the CH1MS bit */
1479 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1480 /* set the CH1MS bit */
1481 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U);
1482 /* reset the CH1CAPFLT bit */
1483 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1484 /* set the CH1CAPFLT bit */
1485 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U);
1486 /* set the CH1EN bit */
1487 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1488 /* configure TIMER channel input capture prescaler value */
1489 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1490 }else{
1491 /* reset the CH1EN bit */
1492 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1493 /* reset the CH1P and CH1NP bits */
1494 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1495 /* set the CH1P and CH1NP bits */
1496 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U);
1497 /* reset the CH1MS bit */
1498 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1499 /* set the CH1MS bit */
1500 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U);
1501 /* reset the CH1CAPFLT bit */
1502 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1503 /* set the CH1CAPFLT bit */
1504 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U);
1505 /* set the CH1EN bit */
1506 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1507 /* configure TIMER channel input capture prescaler value */
1508 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1509
1510 /* reset the CH0EN bit */
1511 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1512 /* reset the CH0P and CH0NP bits */
1513 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1514 /* set the CH0P and CH0NP bits */
1515 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1516 /* reset the CH0MS bit */
1517 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1518 /* set the CH0MS bit */
1519 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1520 /* reset the CH0CAPFLT bit */
1521 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1522 /* set the CH0CAPFLT bit */
1523 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1524 /* set the CH0EN bit */
1525 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1526 /* configure TIMER channel input capture prescaler value */
1527 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1528 }
1529 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f10x_timer.h:263
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f10x_timer.c:1359
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f10x_timer.h:147
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f10x_timer.h:264
TIMER_IC_SELECTION_INDIRECTTI
#define TIMER_IC_SELECTION_INDIRECTTI
Definition: gd32f10x_timer.h:488
TIMER_IC_POLARITY_RISING
#define TIMER_IC_POLARITY_RISING
Definition: gd32f10x_timer.h:482
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f10x_timer.h:487
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f10x_timer.h:262
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f10x_timer.h:145
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_IC_POLARITY_FALLING
#define TIMER_IC_POLARITY_FALLING
Definition: gd32f10x_timer.h:483
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f10x_timer.h:265
void timer_input_trigger_source_select | ( | uint32_t | timer_periph,
 |  | uint32_t | intrigger
 | ) |  |

select TIMER input trigger source

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] intrigger
  • TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
  • TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
  • TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
  • TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
  • TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector
  • TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
  • TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
  • TIMER_SMCFG_TRGSEL_ETIFP: external trigger
[out] | none
Return values
none

Definition at line 1565 of file gd32f10x_timer.c.

1566 {
1567 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1568 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1569 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f10x_timer.h:83
void timer_internal_clock_config ( uint32_t timer_periph )

configure TIMER internal clock mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[out] | none
Return values
none

Definition at line 1693 of file gd32f10x_timer.c.

1694 {
1695 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1696 }
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
void timer_internal_trigger_as_external_clock_config | ( | uint32_t | timer_periph,
 |  | uint32_t | intrigger
 | ) |  |

configure TIMER the internal trigger as external clock input

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] intrigger
  • TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
  • TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
  • TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
  • TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
[out] | none
Return values
none

Definition at line 1709 of file gd32f10x_timer.c.

1710 {
1711 timer_input_trigger_source_select(timer_periph,intrigger);
1712 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1713 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1714 }
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f10x_timer.h:528
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f10x_timer.c:1565
void timer_interrupt_disable | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

disable the TIMER interrupt

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt timer interrupt source enable
  • TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
  • TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
  • TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
  • TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
  • TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
  • TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
  • TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
  • TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 405 of file gd32f10x_timer.c.

406 {
407 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
408 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_interrupt_enable | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

enable the TIMER interrupt

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt timer interrupt enable source
  • TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
  • TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
  • TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
  • TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
  • TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
  • TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
  • TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
  • TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 385 of file gd32f10x_timer.c.

386 {
387 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
388 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_interrupt_flag_clear | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

clear TIMER interrupt flag

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt the timer interrupt bits
  • TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
  • TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
  • TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
  • TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
  • TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
  • TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
  • TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
  • TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
[out] | none
Return values
none

Definition at line 451 of file gd32f10x_timer.c.

452 {
453 TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt);
454 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f10x_timer.h:39
FlagStatus timer_interrupt_flag_get | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

get timer interrupt flag

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt the timer interrupt bits
  • TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
  • TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
  • TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
  • TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
  • TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
  • TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
  • TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
  • TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 425 of file gd32f10x_timer.c.

426 {
427 uint32_t val;
428 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
429 if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
430 return SET;
431 }else{
432 return RESET;
433 }
434 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f10x_timer.h:39
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
void timer_master_output_trigger_source_select | ( | uint32_t | timer_periph,
 |  | uint32_t | outrigger
 | ) |  |

select TIMER master mode output trigger source

Parameters
[in] | timer_periph | TIMERx(x=0..7)
[in] outrigger
  • TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output
  • TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output
  • TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output
  • TIMER_TRI_OUT_SRC_CC0: a capture or a compare match occurred in channal0 as trigger output TRGO
  • TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output
  • TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output
  • TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output
  • TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output
[out] | none
Return values
none

Definition at line 1586 of file gd32f10x_timer.c.

1587 {
1588 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1589 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1590 }
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_CTL1_MMC
#define TIMER_CTL1_MMC
Definition: gd32f10x_timer.h:71
void timer_master_slave_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | masterslave
 | ) |  |

configure TIMER master slave mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] masterslave
  • TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
  • TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
[out] | none
Return values
none

Definition at line 1624 of file gd32f10x_timer.c.

1625 {
1626 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1627 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1628 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1629 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1630 }else{
1631 }
1632 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_SMCFG_MSM
#define TIMER_SMCFG_MSM
Definition: gd32f10x_timer.h:84
TIMER_MASTER_SLAVE_MODE_DISABLE
#define TIMER_MASTER_SLAVE_MODE_DISABLE
Definition: gd32f10x_timer.h:532
TIMER_MASTER_SLAVE_MODE_ENABLE
#define TIMER_MASTER_SLAVE_MODE_ENABLE
Definition: gd32f10x_timer.h:531
void timer_prescaler_config | ( | uint32_t | timer_periph,
 |  | uint16_t | prescaler,
 |  | uint8_t | pscreload
 | ) |  |

configure TIMER prescaler

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] | prescaler | prescaler value
[in] pscreload prescaler reload mode
  • TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
  • TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
[out] | none
Return values
none

Definition at line 261 of file gd32f10x_timer.c.

262 {
263 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
264
265 if(TIMER_PSC_RELOAD_NOW == pscreload){
266 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
267 }
268 }
TIMER_SWEVG_UPG
#define TIMER_SWEVG_UPG
Definition: gd32f10x_timer.h:122
TIMER_PSC_RELOAD_NOW
#define TIMER_PSC_RELOAD_NOW
Definition: gd32f10x_timer.h:377
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f10x_timer.h:40
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f10x_timer.h:45
uint16_t timer_prescaler_read ( uint32_t timer_periph )

read TIMER prescaler value

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
prescaler register value

Definition at line 325 of file gd32f10x_timer.c.

326 {
327 uint16_t prescaler_value = 0U;
328 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
329 return (prescaler_value);
330 }
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f10x_timer.h:45
void timer_primary_output_config | ( | uint32_t | timer_periph,
 |  | ControlStatus | newvalue
 | ) |  |

configure TIMER primary output function

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 696 of file gd32f10x_timer.c.

697 {
698 if(ENABLE == newvalue){
699 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
700 }else{
701 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
702 }
703 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
TIMER_CCHP_POEN
#define TIMER_CCHP_POEN
Definition: gd32f10x_timer.h:215
void timer_quadrature_decoder_mode_config | ( | uint32_t | timer_periph,
 |  | uint32_t | decomode,
 |  | uint16_t | ic0polarity,
 |  | uint16_t | ic1polarity
 | ) |  |

configure TIMER quadrature decoder mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] decomode
  • TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
  • TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
  • TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
[in] ic0polarity
  • TIMER_IC_POLARITY_RISING: capture rising edge
  • TIMER_IC_POLARITY_FALLING: capture falling edge
[in] ic1polarity
  • TIMER_IC_POLARITY_RISING: capture rising edge
  • TIMER_IC_POLARITY_FALLING: capture falling edge
[out] | none
Return values
none

Definition at line 1673 of file gd32f10x_timer.c.

1675 {
1676 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1677 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1678
1679 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1680 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U));
1681
1682 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1683 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1684 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity<< 4U));
1685 }
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f10x_timer.h:487
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
void timer_repetition_value_config | ( | uint32_t | timer_periph,
 |  | uint16_t | repetition
 | ) |  |

configure TIMER repetition register value

Parameters
[in] | timer_periph | TIMERx(x=0,7)
[in] | repetition | the counter repetition value,0~255
[out] | none
Return values
none

Definition at line 277 of file gd32f10x_timer.c.

278 {
279 TIMER_CREP(timer_periph) = (uint32_t)repetition;
280 }
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f10x_timer.h:47
void timer_single_pulse_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | spmode
 | ) |  |

configure TIMER single pulse mode

Parameters
[in] | timer_periph | TIMERx(x=0..8,11)
[in] spmode
  • TIMER_SP_MODE_SINGLE: single pulse mode
  • TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
[out] | none
Return values
none

Definition at line 341 of file gd32f10x_timer.c.

342 {
343 if(TIMER_SP_MODE_SINGLE == spmode){
344 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
345 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
346 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
347 }else{
348 }
349 }
TIMER_CTL0_SPM
#define TIMER_CTL0_SPM
Definition: gd32f10x_timer.h:61
TIMER_SP_MODE_REPETITIVE
#define TIMER_SP_MODE_REPETITIVE
Definition: gd32f10x_timer.h:392
TIMER_SP_MODE_SINGLE
#define TIMER_SP_MODE_SINGLE
Definition: gd32f10x_timer.h:391
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_slave_mode_select | ( | uint32_t | timer_periph,
 |  | uint32_t | slavemode
 | ) |  |

select TIMER slave mode

Parameters
[in] | timer_periph | TIMERx(x=0..4,7,8,11)
[in] slavemode
  • TIMER_SLAVE_MODE_DISABLE: slave mode disable
  • TIMER_ENCODER_MODE0: encoder mode 0
  • TIMER_ENCODER_MODE1: encoder mode 1
  • TIMER_ENCODER_MODE2: encoder mode 2
  • TIMER_SLAVE_MODE_RESTART: restart mode
  • TIMER_SLAVE_MODE_PAUSE: pause mode
  • TIMER_SLAVE_MODE_EVENT: event mode
  • TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.
[out] | none
Return values
none

Definition at line 1608 of file gd32f10x_timer.c.

1609 {
1610 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1611
1612 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1613 }
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
void timer_update_event_disable ( uint32_t timer_periph )

disable the update event

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 207 of file gd32f10x_timer.c.

208 {
209 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
210 }
TIMER_CTL0_UPDIS
#define TIMER_CTL0_UPDIS
Definition: gd32f10x_timer.h:59
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_update_event_enable ( uint32_t timer_periph )

enable the update event

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[out] | none
Return values
none

Definition at line 196 of file gd32f10x_timer.c.

197 {
198 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
199 }
TIMER_CTL0_UPDIS
#define TIMER_CTL0_UPDIS
Definition: gd32f10x_timer.h:59
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
void timer_update_source_config | ( | uint32_t | timer_periph,
 |  | uint8_t | update
 | ) |  |

configure TIMER update source

Parameters
[in] | timer_periph | TIMERx(x=0..13)
[in] update
  • TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
  • TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
[out] | none
Return values
none

Definition at line 360 of file gd32f10x_timer.c.

361 {
362 if(TIMER_UPDATE_SRC_REGULAR == update){
363 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
364 }else if(update == TIMER_UPDATE_SRC_GLOBAL){
365 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
366 }else{
367 }
368 }
TIMER_UPDATE_SRC_GLOBAL
#define TIMER_UPDATE_SRC_GLOBAL
Definition: gd32f10x_timer.h:396
TIMER_UPDATE_SRC_REGULAR
#define TIMER_UPDATE_SRC_REGULAR
Definition: gd32f10x_timer.h:395
TIMER_CTL0_UPS
#define TIMER_CTL0_UPS
Definition: gd32f10x_timer.h:60
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
Generated on Tue Jul 18 2017 09:24:17 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Functions
gd32f10x_usart.c File Reference

USART driver. More...

#include "gd32f10x_usart.h"

Go to the source code of this file.

Functions

void | usart_deinit (uint32_t usart_periph)
reset USART/UART More...
void | usart_baudrate_set (uint32_t usart_periph, uint32_t baudval)
configure USART baud rate value More...
void | usart_parity_config (uint32_t usart_periph, uint32_t paritycfg)
configure USART parity More...
void | usart_word_length_set (uint32_t usart_periph, uint32_t wlen)
configure USART word length More...
void | usart_stop_bit_set (uint32_t usart_periph, uint32_t stblen)
configure USART stop bit length More...
void | usart_enable (uint32_t usart_periph)
enable USART More...
void | usart_disable (uint32_t usart_periph)
disable USART More...
void | usart_transmit_config (uint32_t usart_periph, uint32_t txconfig)
configure USART transmitter More...
void | usart_receive_config (uint32_t usart_periph, uint32_t rxconfig)
configure USART receiver More...
void | usart_data_transmit (uint32_t usart_periph, uint32_t data)
USART transmit data function. More...
uint16_t | usart_data_receive (uint32_t usart_periph)
USART receive data function. More...
void | usart_address_config (uint32_t usart_periph, uint8_t addr)
configure the address of the USART in wake up by address match mode More...
void | usart_mute_mode_enable (uint32_t usart_periph)
receiver in mute mode More...
void | usart_mute_mode_disable (uint32_t usart_periph)
receiver in active mode More...
void | usart_mute_mode_wakeup_config (uint32_t usart_periph, uint32_t wmethod)
configure wakeup method in mute mode More...
void | usart_lin_mode_enable (uint32_t usart_periph)
enable LIN mode More...
void | usart_lin_mode_disable (uint32_t usart_periph)
disable LIN mode More...
void | usart_lin_break_dection_length_config (uint32_t usart_periph, uint32_t lblen)
configure lin break frame length More...
void | usart_send_break (uint32_t usart_periph)
send break frame More...
void | usart_halfduplex_enable (uint32_t usart_periph)
enable half duplex mode More...
void | usart_halfduplex_disable (uint32_t usart_periph)
disable half duplex mode More...
void | usart_synchronous_clock_enable (uint32_t usart_periph)
enable CK pin in synchronous mode More...
void | usart_synchronous_clock_disable (uint32_t usart_periph)
disable CK pin in synchronous mode More...
void | usart_synchronous_clock_config (uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
configure USART synchronous mode parameters More...
void | usart_guard_time_config (uint32_t usart_periph, uint32_t gaut)
configure guard time value in smartcard mode More...
void | usart_smartcard_mode_enable (uint32_t usart_periph)
enable smartcard mode More...
void | usart_smartcard_mode_disable (uint32_t usart_periph)
disable smartcard mode More...
void | usart_smartcard_mode_nack_enable (uint32_t usart_periph)
enable NACK in smartcard mode More...
void | usart_smartcard_mode_nack_disable (uint32_t usart_periph)
disable NACK in smartcard mode More...
void | usart_irda_mode_enable (uint32_t usart_periph)
enable IrDA mode More...
void | usart_irda_mode_disable (uint32_t usart_periph)
disable IrDA mode More...
void | usart_prescaler_config (uint32_t usart_periph, uint8_t psc)
configure the peripheral clock prescaler in USART IrDA low-power mode More...
void | usart_irda_lowpower_config (uint32_t usart_periph, uint32_t irlp)
configure IrDA low-power More...
void | usart_hardware_flow_rts_config (uint32_t usart_periph, uint32_t rtsconfig)
configure hardware flow control RTS More...
void | usart_hardware_flow_cts_config (uint32_t usart_periph, uint32_t ctsconfig)
configure hardware flow control CTS More...
void | usart_dma_receive_config (uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA reception More...
void | usart_dma_transmit_config (uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA transmission More...
FlagStatus | usart_flag_get (uint32_t usart_periph, usart_flag_enum flag)
get flag in STAT register More...
void | usart_flag_clear (uint32_t usart_periph, usart_flag_enum flag)
clear flag in STAT register More...
void | usart_interrupt_enable (uint32_t usart_periph, uint32_t int_flag)
enable USART interrupt More...
void | usart_interrupt_disable (uint32_t usart_periph, uint32_t int_flag)
disable USART interrupt More...
FlagStatus | usart_interrupt_flag_get (uint32_t usart_periph, uint32_t int_flag)
get USART interrupt and flag status More...
void | usart_interrupt_flag_clear (uint32_t usart_periph, uint32_t flag)
clear USART interrupt flag in STAT register More...

Detailed Description

USART driver.

Definition in file gd32f10x_usart.c.

Function Documentation

void usart_address_config | ( | uint32_t | usart_periph,
 |  | uint8_t | addr
 | ) |  |

configure the address of the USART in wake up by address match mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] | addr | address of USART/UART
[out] | none
Return values
none

Definition at line 231 of file gd32f10x_usart.c.

232 {
233 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
234 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr);
235 }
USART_CTL1_ADDR
#define USART_CTL1_ADDR
Definition: gd32f10x_usart.h:71
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
void usart_baudrate_set | ( | uint32_t | usart_periph,
 |  | uint32_t | baudval
 | ) |  |

configure USART baud rate value

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] | baudval | baud rate value
[out] | none
Return values
none

Definition at line 56 of file gd32f10x_usart.c.

57 {
58 uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U;
59 switch(usart_periph){
60 case USART0:
61 /* get clock frequency */
62 uclk=rcu_clock_freq_get(CK_APB2);
63 break;
64 case USART1:
65 uclk=rcu_clock_freq_get(CK_APB1);
66 break;
67 case USART2:
68 uclk=rcu_clock_freq_get(CK_APB1);
69 break;
70 case UART3:
71 uclk=rcu_clock_freq_get(CK_APB1);
72 break;
73 case UART4:
74 uclk=rcu_clock_freq_get(CK_APB1);
75 break;
76 default:
77 break;
78 }
79 /* oversampling by 16, configure the value of USART_BAUD */
80 udiv = (uclk+baudval/2U)/baudval;
81 intdiv = udiv & 0xfff0U;
82 fradiv = udiv & 0xfU;
83 USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
84 }
USART0
#define USART0
Definition: gd32f10x_usart.h:23
UART3
#define UART3
Definition: gd32f10x_usart.h:21
USART_BAUD
#define USART_BAUD(usartx)
Definition: gd32f10x_usart.h:28
USART_BAUD_FRADIV
#define USART_BAUD_FRADIV
Definition: gd32f10x_usart.h:51
USART_BAUD_INTDIV
#define USART_BAUD_INTDIV
Definition: gd32f10x_usart.h:52
USART1
#define USART1
Definition: gd32f10x_usart.h:19
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
CK_APB2
Definition: gd32f10x_rcu.h:587
CK_APB1
Definition: gd32f10x_rcu.h:586
USART2
#define USART2
Definition: gd32f10x_usart.h:20
UART4
#define UART4
Definition: gd32f10x_usart.h:22
uint16_t usart_data_receive ( uint32_t usart_periph )

USART receive data function.

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
data of received

Definition at line 219 of file gd32f10x_usart.c.

220 {
221 return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U));
222 }
USART_DATA
#define USART_DATA(usartx)
Definition: gd32f10x_usart.h:27
void usart_data_transmit | ( | uint32_t | usart_periph,
 |  | uint32_t | data
 | ) |  |

USART transmit data function.

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] | data | data of transmission
[out] | none
Return values
none

Definition at line 208 of file gd32f10x_usart.c.

209 {
210 USART_DATA(usart_periph) = USART_DATA_DATA & data;
211 }
USART_DATA
#define USART_DATA(usartx)
Definition: gd32f10x_usart.h:27
USART_DATA_DATA
#define USART_DATA_DATA
Definition: gd32f10x_usart.h:48
void usart_deinit ( uint32_t usart_periph )

reset USART/UART

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 21 of file gd32f10x_usart.c.

22 {
23 switch(usart_periph){
24 case USART0:
25 rcu_periph_reset_enable(RCU_USART0RST);
26 rcu_periph_reset_disable(RCU_USART0RST);
27 break;
28 case USART1:
29 rcu_periph_reset_enable(RCU_USART1RST);
30 rcu_periph_reset_disable(RCU_USART1RST);
31 break;
32 case USART2:
33 rcu_periph_reset_enable(RCU_USART2RST);
34 rcu_periph_reset_disable(RCU_USART2RST);
35 break;
36 case UART3:
37 rcu_periph_reset_enable(RCU_UART3RST);
38 rcu_periph_reset_disable(RCU_UART3RST);
39 break;
40 case UART4:
41 rcu_periph_reset_enable(RCU_UART4RST);
42 rcu_periph_reset_disable(RCU_UART4RST);
43 break;
44 default:
45 break;
46 }
47 }
RCU_USART1RST
Definition: gd32f10x_rcu.h:459
USART0
#define USART0
Definition: gd32f10x_usart.h:23
UART3
#define UART3
Definition: gd32f10x_usart.h:21
USART1
#define USART1
Definition: gd32f10x_usart.h:19
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
RCU_USART0RST
Definition: gd32f10x_rcu.h:490
RCU_USART2RST
Definition: gd32f10x_rcu.h:460
RCU_UART4RST
Definition: gd32f10x_rcu.h:462
USART2
#define USART2
Definition: gd32f10x_usart.h:20
UART4
#define UART4
Definition: gd32f10x_usart.h:22
RCU_UART3RST
Definition: gd32f10x_rcu.h:461
void usart_disable ( uint32_t usart_periph )

disable USART

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 156 of file gd32f10x_usart.c.

157 {
158 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
159 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f10x_usart.h:68
void usart_dma_receive_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dmacmd
 | ) |  |

configure USART DMA reception

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3)
[in] dmacmd enable or disable DMA for reception
  • USART_DENR_ENABLE: DMA enable for reception
  • USART_DENR_DISABLE: DMA disable for reception
[out] | none
Return values
none

Definition at line 549 of file gd32f10x_usart.c.

550 {
551 uint32_t ctl = 0U;
552
553 ctl = USART_CTL2(usart_periph);
554 ctl &= ~USART_CTL2_DENR;
555 ctl |= dmacmd;
556 /* configure DMA reception */
557 USART_CTL2(usart_periph) = ctl;
558 }
USART_CTL2_DENR
#define USART_CTL2_DENR
Definition: gd32f10x_usart.h:88
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_dma_transmit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dmacmd
 | ) |  |

configure USART DMA transmission

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3)
[in] dmacmd enable or disable DMA for transmission
  • USART_DENT_ENABLE: DMA enable for transmission
  • USART_DENT_DISABLE: DMA disable for transmission
[out] | none
Return values
none

Definition at line 569 of file gd32f10x_usart.c.

570 {
571 uint32_t ctl = 0U;
572
573 ctl = USART_CTL2(usart_periph);
574 ctl &= ~USART_CTL2_DENT;
575 ctl |= dmacmd;
576 /* configure DMA transmission */
577 USART_CTL2(usart_periph) = ctl;
578 }
USART_CTL2_DENT
#define USART_CTL2_DENT
Definition: gd32f10x_usart.h:89
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_enable ( uint32_t usart_periph )

enable USART

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 145 of file gd32f10x_usart.c.

146 {
147 USART_CTL0(usart_periph) |= USART_CTL0_UEN;
148 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f10x_usart.h:68
void usart_flag_clear | ( | uint32_t | usart_periph,
 |  | usart_flag_enum | flag
 | ) |  |

clear flag in STAT register

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] flag USART flags, refer to usart_flag_enum only one among these parameters can be selected
  • USART_FLAG_CTSF: CTS change flag
  • USART_FLAG_LBDF: LIN break detected flag
  • USART_FLAG_TC: transmission complete
  • USART_FLAG_RBNE: read data buffer not empty
[out] | none
Return values
none

Definition at line 619 of file gd32f10x_usart.c.

620 {
621 USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag));
622 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
FlagStatus usart_flag_get | ( | uint32_t | usart_periph,
 |  | usart_flag_enum | flag
 | ) |  |

get flag in STAT register

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] flag USART flags, refer to usart_flag_enum only one among these parameters can be selected
  • USART_FLAG_CTSF: CTS change flag
  • USART_FLAG_LBDF: LIN break detected flag
  • USART_FLAG_TBE: transmit data buffer empty
  • USART_FLAG_TC: transmission complete
  • USART_FLAG_RBNE: read data buffer not empty
  • USART_FLAG_IDLEF: IDLE frame detected flag
  • USART_FLAG_ORERR: overrun error
  • USART_FLAG_NERR: noise error flag
  • USART_FLAG_FERR: frame error flag
  • USART_FLAG_PERR: parity error flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 598 of file gd32f10x_usart.c.

599 {
600 if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
601 return SET;
602 }else{
603 return RESET;
604 }
605 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
void usart_guard_time_config | ( | uint32_t | usart_periph,
 |  | uint32_t | gaut
 | ) |  |

configure guard time value in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[in] | gaut | guard time value
[out] | none
Return values
none

Definition at line 400 of file gd32f10x_usart.c.

401 {
402 USART_GP(usart_periph) &= ~(USART_GP_GUAT);
403 USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8));
404 }
USART_GP_GUAT
#define USART_GP_GUAT
Definition: gd32f10x_usart.h:96
USART_GP
#define USART_GP(usartx)
Definition: gd32f10x_usart.h:32
void usart_halfduplex_disable ( uint32_t usart_periph )

disable half duplex mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 339 of file gd32f10x_usart.c.

340 {
341 USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
342 }
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f10x_usart.h:85
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_halfduplex_enable ( uint32_t usart_periph )

enable half duplex mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 328 of file gd32f10x_usart.c.

329 {
330 USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
331 }
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f10x_usart.h:85
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_hardware_flow_cts_config | ( | uint32_t | usart_periph,
 |  | uint32_t | ctsconfig
 | ) |  |

configure hardware flow control CTS

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[in] hardwareflow enable or disable CTS
  • USART_CTS_ENABLE: enable CTS
  • USART_CTS_DISABLE: disable CTS
[out] | none
Return values
none

Definition at line 529 of file gd32f10x_usart.c.

530 {
531 uint32_t ctl = 0U;
532
533 ctl = USART_CTL2(usart_periph);
534 ctl &= ~USART_CTL2_CTSEN;
535 ctl |= ctsconfig;
536 /* configure CTS */
537 USART_CTL2(usart_periph) = ctl;
538 }
USART_CTL2_CTSEN
#define USART_CTL2_CTSEN
Definition: gd32f10x_usart.h:91
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_hardware_flow_rts_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rtsconfig
 | ) |  |

configure hardware flow control RTS

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[in] hardwareflow enable or disable RTS
  • USART_RTS_ENABLE: enable RTS
  • USART_RTS_DISABLE: disable RTS
[out] | none
Return values
none

Definition at line 509 of file gd32f10x_usart.c.

510 {
511 uint32_t ctl = 0U;
512
513 ctl = USART_CTL2(usart_periph);
514 ctl &= ~USART_CTL2_RTSEN;
515 ctl |= rtsconfig;
516 /* configure RTS */
517 USART_CTL2(usart_periph) = ctl;
518 }
USART_CTL2_RTSEN
#define USART_CTL2_RTSEN
Definition: gd32f10x_usart.h:90
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_interrupt_disable | ( | uint32_t | usart_periph,
 |  | uint32_t | int_flag
 | ) |  |

disable USART interrupt

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] int_flag
  • USART_INT_PERR: parity error interrupt
  • USART_INT_TBE: transmitter buffer empty interrupt
  • USART_INT_TC: transmission complete interrupt
  • USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
  • USART_INT_IDLE: IDLE line detected interrupt
  • USART_INT_LBD: LIN break detected interrupt
  • USART_INT_ERR: error interrupt
  • USART_INT_CTS: CTS interrupt
[out] | none
Return values
none

Definition at line 659 of file gd32f10x_usart.c.

660 {
661 USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag));
662 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
void usart_interrupt_enable | ( | uint32_t | usart_periph,
 |  | uint32_t | int_flag
 | ) |  |

enable USART interrupt

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] int_flag
  • USART_INT_PERR: parity error interrupt
  • USART_INT_TBE: transmitter buffer empty interrupt
  • USART_INT_TC: transmission complete interrupt
  • USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
  • USART_INT_IDLE: IDLE line detected interrupt
  • USART_INT_LBD: LIN break detected interrupt
  • USART_INT_ERR: error interrupt
  • USART_INT_CTS: CTS interrupt
[out] | none
Return values
none

Definition at line 639 of file gd32f10x_usart.c.

640 {
641 USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag));
642 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
void usart_interrupt_flag_clear | ( | uint32_t | usart_periph,
 |  | uint32_t | flag
 | ) |  |

clear USART interrupt flag in STAT register

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] flag USART interrupt flag
  • USART_INT_FLAG_CTS: CTS change flag
  • USART_INT_FLAG_LBD: LIN break detected flag
  • USART_INT_FLAG_TC: transmission complete
  • USART_INT_FLAG_RBNE: read data buffer not empty
[out] | none
Return values
none

Definition at line 708 of file gd32f10x_usart.c.

709 {
710 USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag));
711 }
USART_REG_VAL2
#define USART_REG_VAL2(usartx, offset)
Definition: gd32f10x_usart.h:105
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f10x_usart.h:106
FlagStatus usart_interrupt_flag_get | ( | uint32_t | usart_periph,
 |  | uint32_t | int_flag
 | ) |  |

get USART interrupt and flag status

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] int_flag
  • USART_INT_FLAG_PERR: parity error interrupt and flag
  • USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag
  • USART_INT_FLAG_TC: transmission complete interrupt and flag
  • USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
  • USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
  • USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
  • USART_INT_FLAG_LBD: LIN break detected interrupt and flag
  • USART_INT_FLAG_CTS: CTS interrupt and flag
  • USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
  • USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
  • USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
[out] | none
Return values
FlagStatus

Definition at line 682 of file gd32f10x_usart.c.

683 {
684 uint32_t intenable = 0U, flagstatus = 0U;
685 /* get the interrupt enable bit status */
686 intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
687 /* get the corresponding flag bit status */
688 flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
689
690 if(flagstatus && intenable){
691 return SET;
692 }else{
693 return RESET;
694 }
695 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_REG_VAL2
#define USART_REG_VAL2(usartx, offset)
Definition: gd32f10x_usart.h:105
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f10x_usart.h:106
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
void usart_irda_lowpower_config | ( | uint32_t | usart_periph,
 |  | uint32_t | irlp
 | ) |  |

configure IrDA low-power

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] irlp IrDA low-power or normal
  • USART_IRLP_LOW: low-power
  • USART_IRLP_NORMAL: normal
[out] | none
Return values
none

Definition at line 494 of file gd32f10x_usart.c.

495 {
496 USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP);
497 USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
498 }
USART_CTL2_IRLP
#define USART_CTL2_IRLP
Definition: gd32f10x_usart.h:84
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_irda_mode_disable ( uint32_t usart_periph )

disable IrDA mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 467 of file gd32f10x_usart.c.

468 {
469 USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
470 }
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f10x_usart.h:83
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_irda_mode_enable ( uint32_t usart_periph )

enable IrDA mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 456 of file gd32f10x_usart.c.

457 {
458 USART_CTL2(usart_periph) |= USART_CTL2_IREN;
459 }
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f10x_usart.h:83
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_lin_break_dection_length_config | ( | uint32_t | usart_periph,
 |  | uint32_t | lblen
 | ) |  |

configure lin break frame length

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] lblen lin break frame length
  • USART_LBLEN_10B: 10 bits
  • USART_LBLEN_11B: 11 bits
[out] | none
Return values
none

Definition at line 305 of file gd32f10x_usart.c.

306 {
307 USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN);
308 USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen);
309 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_LBLEN
#define USART_CTL1_LBLEN
Definition: gd32f10x_usart.h:72
void usart_lin_mode_disable ( uint32_t usart_periph )

disable LIN mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 291 of file gd32f10x_usart.c.

292 {
293 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
294 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f10x_usart.h:79
void usart_lin_mode_enable ( uint32_t usart_periph )

enable LIN mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 280 of file gd32f10x_usart.c.

281 {
282 USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
283 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f10x_usart.h:79
void usart_mute_mode_disable ( uint32_t usart_periph )

receiver in active mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 254 of file gd32f10x_usart.c.

255 {
256 USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU);
257 }
USART_CTL0_RWU
#define USART_CTL0_RWU
Definition: gd32f10x_usart.h:56
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
void usart_mute_mode_enable ( uint32_t usart_periph )

receiver in mute mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 243 of file gd32f10x_usart.c.

244 {
245 USART_CTL0(usart_periph) |= USART_CTL0_RWU;
246 }
USART_CTL0_RWU
#define USART_CTL0_RWU
Definition: gd32f10x_usart.h:56
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
void usart_mute_mode_wakeup_config | ( | uint32_t | usart_periph,
 |  | uint32_t | wmethod
 | ) |  |

configure wakeup method in mute mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] wmethod two methods be used to enter or exit the mute mode
  • USART_WM_IDLE: idle line
  • USART_WM_ADDR: address mask
[out] | none
Return values
none

Definition at line 268 of file gd32f10x_usart.c.

269 {
270 USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
271 USART_CTL0(usart_periph) |= wmethod;
272 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_WM
#define USART_CTL0_WM
Definition: gd32f10x_usart.h:66
void usart_parity_config | ( | uint32_t | usart_periph,
 |  | uint32_t | paritycfg
 | ) |  |

configure USART parity

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] paritycfg configure USART parity
  • USART_PM_NONE: no parity
  • USART_PM_ODD: odd parity
  • USART_PM_EVEN: even parity
[out] | none
Return values
none

Definition at line 96 of file gd32f10x_usart.c.

97 {
98 /* clear USART_CTL0 PM,PCEN bits */
99 USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
100 /* configure USART parity mode */
101 USART_CTL0(usart_periph) |= paritycfg ;
102 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_PM
#define USART_CTL0_PM
Definition: gd32f10x_usart.h:64
USART_CTL0_PCEN
#define USART_CTL0_PCEN
Definition: gd32f10x_usart.h:65
void usart_prescaler_config | ( | uint32_t | usart_periph,
 |  | uint8_t | psc
 | ) |  |

configure the peripheral clock prescaler in USART IrDA low-power mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] | psc | 0x00-0xFF
[out] | none
Return values
none

Definition at line 479 of file gd32f10x_usart.c.

480 {
481 USART_GP(usart_periph) &= ~(USART_GP_PSC);
482 USART_GP(usart_periph) |= psc;
483 }
USART_GP_PSC
#define USART_GP_PSC
Definition: gd32f10x_usart.h:95
USART_GP
#define USART_GP(usartx)
Definition: gd32f10x_usart.h:32
void usart_receive_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rxconfig
 | ) |  |

configure USART receiver

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] rxconfig enable or disable USART receiver
  • USART_RECEIVE_ENABLE: enable USART reception
  • USART_RECEIVE_DISABLE: disable USART reception
[out] | none
Return values
none

Definition at line 190 of file gd32f10x_usart.c.

191 {
192 uint32_t ctl = 0U;
193
194 ctl = USART_CTL0(usart_periph);
195 ctl &= ~USART_CTL0_REN;
196 ctl |= rxconfig;
197 /* configure transfer mode */
198 USART_CTL0(usart_periph) = ctl;
199 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_REN
#define USART_CTL0_REN
Definition: gd32f10x_usart.h:57
void usart_send_break ( uint32_t usart_periph )

send break frame

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 317 of file gd32f10x_usart.c.

318 {
319 USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD;
320 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_SBKCMD
#define USART_CTL0_SBKCMD
Definition: gd32f10x_usart.h:55
void usart_smartcard_mode_disable ( uint32_t usart_periph )

disable smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 423 of file gd32f10x_usart.c.

424 {
425 USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
426 }
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f10x_usart.h:87
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_smartcard_mode_enable ( uint32_t usart_periph )

enable smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 412 of file gd32f10x_usart.c.

413 {
414 USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
415 }
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f10x_usart.h:87
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_smartcard_mode_nack_disable ( uint32_t usart_periph )

disable NACK in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 445 of file gd32f10x_usart.c.

446 {
447 USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
448 }
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f10x_usart.h:86
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_smartcard_mode_nack_enable ( uint32_t usart_periph )

enable NACK in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 434 of file gd32f10x_usart.c.

435 {
436 USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
437 }
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f10x_usart.h:86
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
void usart_stop_bit_set | ( | uint32_t | usart_periph,
 |  | uint32_t | stblen
 | ) |  |

configure USART stop bit length

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] stblen USART stop bit configure
  • USART_STB_1BIT: 1 bit
  • USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4)
  • USART_STB_2BIT: 2 bits
  • USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4)
[out] | none
Return values
none

Definition at line 132 of file gd32f10x_usart.c.

133 {
134 /* clear USART_CTL1 STB bits */
135 USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
136 /* configure USART stop bits */
137 USART_CTL1(usart_periph) |= stblen;
138 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_STB
#define USART_CTL1_STB
Definition: gd32f10x_usart.h:78
void usart_synchronous_clock_config | ( | uint32_t | usart_periph,
 |  | uint32_t | clen,
 |  | uint32_t | cph,
 |  | uint32_t | cpl
 | ) |  |

configure USART synchronous mode parameters

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[in] clen CK length
  • USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame
  • USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame
[in] cph clock phase
  • USART_CPH_1CK: first clock transition is the first data capture edge
  • USART_CPH_2CK: second clock transition is the first data capture edge
[in] cpl clock polarity
  • USART_CPL_LOW: steady low value on CK pin
  • USART_CPL_HIGH: steady high value on CK pin
[out] | none
Return values
none

Definition at line 381 of file gd32f10x_usart.c.

382 {
383 uint32_t ctl = 0U;
384
385 /* read USART_CTL1 register */
386 ctl = USART_CTL1(usart_periph);
387 /* set CK length, CK phase, CK polarity */
388 ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl);
389
390 USART_CTL1(usart_periph) |= ctl;
391 }
USART_CTL1_CPH
#define USART_CTL1_CPH
Definition: gd32f10x_usart.h:75
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
USART_CTL1_CLEN
#define USART_CTL1_CLEN
Definition: gd32f10x_usart.h:74
USART_CTL1_CPL
#define USART_CTL1_CPL
Definition: gd32f10x_usart.h:76
void usart_synchronous_clock_disable ( uint32_t usart_periph )

disable CK pin in synchronous mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 361 of file gd32f10x_usart.c.

362 {
363 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
364 }
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f10x_usart.h:77
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
void usart_synchronous_clock_enable ( uint32_t usart_periph )

enable CK pin in synchronous mode

Parameters
[in] | usart_periph | USARTx(x=0,1,2)
[out] | none
Return values
none

Definition at line 350 of file gd32f10x_usart.c.

351 {
352 USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
353 }
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f10x_usart.h:77
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
void usart_transmit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | txconfig
 | ) |  |

configure USART transmitter

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] txconfig enable or disable USART transmitter
  • USART_TRANSMIT_ENABLE: enable USART transmission
  • USART_TRANSMIT_DISABLE: enable USART transmission
[out] | none
Return values
none

Definition at line 170 of file gd32f10x_usart.c.

171 {
172 uint32_t ctl = 0U;
173
174 ctl = USART_CTL0(usart_periph);
175 ctl &= ~USART_CTL0_TEN;
176 ctl |= txconfig;
177 /* configure transfer mode */
178 USART_CTL0(usart_periph) = ctl;
179 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_TEN
#define USART_CTL0_TEN
Definition: gd32f10x_usart.h:58
void usart_word_length_set | ( | uint32_t | usart_periph,
 |  | uint32_t | wlen
 | ) |  |

configure USART word length

Parameters
[in] | usart_periph | USARTx(x=0,1,2)/UARTx(x=3,4)
[in] wlen USART word length configure
  • USART_WL_8BIT: 8 bits
  • USART_WL_9BIT: 9 bits
[out] | none
Return values
none

Definition at line 113 of file gd32f10x_usart.c.

114 {
115 /* clear USART_CTL0 WL bit */
116 USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
117 /* configure USART word length */
118 USART_CTL0(usart_periph) |= wlen;
119 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_WL
#define USART_CTL0_WL
Definition: gd32f10x_usart.h:67
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
Macros | Functions
gd32f10x_wwdgt.c File Reference

WWDGT driver. More...

#include "gd32f10x_wwdgt.h"

Go to the source code of this file.

Macros

#define | CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
#define | CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))

Functions

void | wwdgt_deinit (void)
reset the window watchdog timer configuration More...
void | wwdgt_counter_update (uint16_t counter_value)
configure the window watchdog timer counter value More...
void | wwdgt_enable (void)
start the window watchdog timer counter More...
void | wwdgt_config (uint16_t counter, uint16_t window, uint32_t prescaler)
configure counter value, window value, and prescaler divider value More...
void | wwdgt_interrupt_enable (void)
enable early wakeup interrupt of WWDGT More...
FlagStatus | wwdgt_flag_get (void)
check early wakeup interrupt state of WWDGT More...
void | wwdgt_flag_clear (void)
clear early wakeup interrupt state of WWDGT More...

Detailed Description

WWDGT driver.

Definition in file gd32f10x_wwdgt.c.

Macro Definition Documentation

#define CFG_WIN ( regval ) (BITS(0,6) & ((uint32_t)(regval) << 0))

Definition at line 18 of file gd32f10x_wwdgt.c.

#define CTL_CNT ( regval ) (BITS(0,6) & ((uint32_t)(regval) << 0))

Definition at line 16 of file gd32f10x_wwdgt.c.

Function Documentation

void wwdgt_config | ( | uint16_t | counter,
 |  | uint16_t | window,
 |  | uint32_t | prescaler
 | ) |  |

configure counter value, window value, and prescaler divider value

Parameters
[in] | counter | 0x00 - 0x7F
[in] | window | 0x00 - 0x7F
[in] prescaler wwdgt prescaler value
  • WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
  • WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
  • WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
  • WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
[out] | none
Return values
none

Definition at line 71 of file gd32f10x_wwdgt.c.

72 {
73 uint32_t reg_cfg = 0U, reg_ctl = 0U;
74
75 /* clear WIN and PSC bits, clear CNT bit */
76 reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
77 reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
78
79 /* configure WIN and PSC bits, configure CNT bit */
80 reg_cfg |= CFG_WIN(window);
81 reg_cfg |= prescaler;
82 reg_ctl |= CTL_CNT(counter);
83
84 WWDGT_CTL = reg_ctl;
85 WWDGT_CFG = reg_cfg;
86 }
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f10x_wwdgt.h:28
CFG_WIN
#define CFG_WIN(regval)
Definition: gd32f10x_wwdgt.c:18
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f10x_wwdgt.h:23
WWDGT_CFG_PSC
#define WWDGT_CFG_PSC
Definition: gd32f10x_wwdgt.h:33
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f10x_wwdgt.c:16
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f10x_wwdgt.h:22
WWDGT_CFG_WIN
#define WWDGT_CFG_WIN
Definition: gd32f10x_wwdgt.h:32
void wwdgt_counter_update ( uint16_t counter_value )

configure the window watchdog timer counter value

Parameters
[in] | counter_value | 0x00 - 0x7F
[out] | none
Return values
none

Definition at line 38 of file gd32f10x_wwdgt.c.

39 {
40 uint32_t reg = 0U;
41
42 reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
43 reg |= CTL_CNT(counter_value);
44
45 WWDGT_CTL = reg;
46 }
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f10x_wwdgt.h:28
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f10x_wwdgt.c:16
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f10x_wwdgt.h:22
void wwdgt_deinit ( void )

reset the window watchdog timer configuration

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 26 of file gd32f10x_wwdgt.c.

27 {
28 rcu_periph_reset_enable(RCU_WWDGTRST);
29 rcu_periph_reset_disable(RCU_WWDGTRST);
30 }
RCU_WWDGTRST
Definition: gd32f10x_rcu.h:456
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
void wwdgt_enable ( void )

start the window watchdog timer counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 54 of file gd32f10x_wwdgt.c.

55 {
56 WWDGT_CTL |= WWDGT_CTL_WDGTEN;
57 }
WWDGT_CTL_WDGTEN
#define WWDGT_CTL_WDGTEN
Definition: gd32f10x_wwdgt.h:29
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f10x_wwdgt.h:22
void wwdgt_flag_clear ( void )

clear early wakeup interrupt state of WWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 120 of file gd32f10x_wwdgt.c.

121 {
122 WWDGT_STAT &= (~WWDGT_STAT_EWIF);
123 }
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f10x_wwdgt.h:37
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f10x_wwdgt.h:24
FlagStatus wwdgt_flag_get ( void )

check early wakeup interrupt state of WWDGT

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 105 of file gd32f10x_wwdgt.c.

106 {
107 if(WWDGT_STAT & WWDGT_STAT_EWIF){
108 return SET;
109 }
110
111 return RESET;
112 }
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f10x_wwdgt.h:37
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f10x_wwdgt.h:24
void wwdgt_interrupt_enable ( void )

enable early wakeup interrupt of WWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 94 of file gd32f10x_wwdgt.c.

95 {
96 WWDGT_CFG |= WWDGT_CFG_EWIE;
97 }
WWDGT_CFG_EWIE
#define WWDGT_CFG_EWIE
Definition: gd32f10x_wwdgt.h:34
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f10x_wwdgt.h:23
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
GD32F10x_usbd_driver Directory Reference

Directories

directory | Include
directory | Source


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
Include Directory Reference

Files

file | usbd_core.h [code]
file | usbd_int.h [code]
file | usbd_pwr.h [code]
USB device power management functions prototype.
file | usbd_regs.h [code]
USB device registers.
file | usbd_std.h [code]


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_core.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
Data Structures | Macros | Enumerations | Functions | Variables
usbd_core.h File Reference
#include "usbd_conf.h"
#include "usbd_regs.h"

Go to the source code of this file.

Data Structures

struct | usbd_ep_buf_struct
struct | usb_ep_struct
struct | usb_device_req_struct
struct | usbd_core_handle_struct

Macros

#define | IER_MASK
#define | USBD_EP0_MAX_SIZE 64U
#define | USBD_CONTRL_STATUS_TX()
#define | USBD_CONTRL_STATUS_RX()
#define | ENDP_BUF_ADDR (sizeof(usbd_ep_buf_struct) * EP_COUNT)

Enumerations

enum | usbd_eptype_enum { ENDP_CONTROL = 0, ENDP_ISOC, ENDP_BULK, ENDP_INT }
enum | usbd_epkind_enum { ENDP_SNG_BUF = 0, ENDP_DBL_BUF }
enum | usbd_dir_enum { USBD_RX = 0, USBD_TX }
enum usbd_run_status_enum {
USBD_UNCONNECTED = 0, USBD_DEFAULT, USBD_ADDRESSED, USBD_CONFIGURED,
USBD_SUSPENDED, USBD_CONNECTED
}
enum usbd_status_enum {
USBD_OK = 0, USBD_BUSY, USBD_FAIL, USBD_OK = 0,
USBD_BUSY, USBD_FAIL
}

Functions

void | usbd_core_init (usbd_core_handle_struct *pudev)
device core register initialization More...
void | usbd_core_deinit (void)
device core register configure when stop device More...
void | user_buffer_free (uint8_t ep_num, uint8_t dir)
free buffer used from application by toggling the SW_BUF byte More...
void | usbd_ep_init (usbd_core_handle_struct *pudev, void *pep_desc)
endpoint initialization More...
void | usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr)
configure the endpoint when it is disabled More...
void | usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data More...
void | usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data More...
void | usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status More...
void | usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status More...
void | usbd_ep_data_write (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
write datas from user fifo to USBRAM More...
void | usbd_ep_data_read (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
read datas from USBRAM to user fifo More...
uint8_t | usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr)
get the endpoint status More...
uint16_t | usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num)
get the received data length More...

Variables

uint32_t g_free_buf_addr
usbd_ep_buf_struct * pbuf_reg

Macro Definition Documentation

#define ENDP_BUF_ADDR (sizeof(usbd_ep_buf_struct) * EP_COUNT)

Definition at line 45 of file usbd_core.h.

#define IER_MASK
Value:
(CTL_STIE | CTL_WKUPIE | CTL_SPSIE \
| CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE)
CTL_STIE
#define CTL_STIE
Definition: usbd_regs.h:38
CTL_WKUPIE
#define CTL_WKUPIE
Definition: usbd_regs.h:41
CTL_SOFIE
#define CTL_SOFIE
Definition: usbd_regs.h:44
CTL_ESOFIE
#define CTL_ESOFIE
Definition: usbd_regs.h:45
CTL_RSTIE
#define CTL_RSTIE
Definition: usbd_regs.h:43
CTL_SPSIE
#define CTL_SPSIE
Definition: usbd_regs.h:42

Definition at line 20 of file usbd_core.h.

#define USBD_CONTRL_STATUS_RX ( )
Value:
do \
{ \
USBD_STATUS_OUT_SET(EP0); \
USBD_ENDP_RX_STATUS_SET(EP0, EPRX_VALID); \
} while(0)
EPRX_VALID
#define EPRX_VALID
Definition: usbd_regs.h:127
EP0
#define EP0
Definition: usbd_regs.h:189
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
USBD_STATUS_OUT_SET
#define USBD_STATUS_OUT_SET(ep_num)
Definition: usbd_regs.h:237

Definition at line 39 of file usbd_core.h.

#define USBD_CONTRL_STATUS_TX ( )
Value:
do \
{ \
pbuf_reg->tx_count = 0U; \
USBD_ENDP_TX_STATUS_SET(EP0, EPTX_VALID); \
} while(0)
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
EP0
#define EP0
Definition: usbd_regs.h:189
pbuf_reg
usbd_ep_buf_struct * pbuf_reg
Definition: usbd_core.c:19
EPTX_VALID
#define EPTX_VALID
Definition: usbd_regs.h:118
usbd_ep_buf_struct::tx_count
uint16_t tx_count
Definition: usbd_core.h:93

Definition at line 33 of file usbd_core.h.

#define USBD_EP0_MAX_SIZE 64U

Definition at line 31 of file usbd_core.h.

Enumeration Type Documentation

enum usbd_dir_enum
Enumerator
USBD_RX | receive direction type value
USBD_TX | transmit direction type value

Definition at line 64 of file usbd_core.h.

65 {
66 USBD_RX = 0,
67 USBD_TX
68 }usbd_dir_enum;
usbd_dir_enum
usbd_dir_enum
Definition: usbd_core.h:64
USBD_RX
Definition: usbd_core.h:66
USBD_TX
Definition: usbd_core.h:67
enum usbd_epkind_enum
Enumerator
ENDP_SNG_BUF | single buffer endpoint type value
ENDP_DBL_BUF | double buffer endpoint type value

Definition at line 57 of file usbd_core.h.

58 {
59 ENDP_SNG_BUF = 0,
60 ENDP_DBL_BUF
61 }usbd_epkind_enum;
ENDP_SNG_BUF
Definition: usbd_core.h:59
ENDP_DBL_BUF
Definition: usbd_core.h:60
usbd_epkind_enum
usbd_epkind_enum
Definition: usbd_core.h:57
enum usbd_eptype_enum
Enumerator
ENDP_CONTROL | control endpoint type value
ENDP_ISOC | isochronous endpoint type value
ENDP_BULK | bulk endpoint type value
ENDP_INT | interupt endpoint type value

Definition at line 48 of file usbd_core.h.

49 {
50 ENDP_CONTROL = 0,
51 ENDP_ISOC,
52 ENDP_BULK,
53 ENDP_INT
54 }usbd_eptype_enum;
ENDP_INT
Definition: usbd_core.h:53
ENDP_ISOC
Definition: usbd_core.h:51
ENDP_BULK
Definition: usbd_core.h:52
ENDP_CONTROL
Definition: usbd_core.h:50
usbd_eptype_enum
usbd_eptype_enum
Definition: usbd_core.h:48
enum usbd_run_status_enum
Enumerator
USBD_UNCONNECTED | USB device unconnected status
USBD_DEFAULT | USB device default status
USBD_ADDRESSED | USB device addressed status
USBD_CONFIGURED | USB device configured status
USBD_SUSPENDED | USB device suspended status
USBD_CONNECTED | USB device connected status

Definition at line 71 of file usbd_core.h.

72 {
73 USBD_UNCONNECTED = 0,
74 USBD_DEFAULT,
75 USBD_ADDRESSED,
76 USBD_CONFIGURED,
77 USBD_SUSPENDED,
78 USBD_CONNECTED
79 }usbd_run_status_enum;
USBD_ADDRESSED
Definition: usbd_core.h:75
USBD_DEFAULT
Definition: usbd_core.h:74
USBD_UNCONNECTED
Definition: usbd_core.h:73
USBD_SUSPENDED
Definition: usbd_core.h:77
usbd_run_status_enum
usbd_run_status_enum
Definition: usbd_core.h:71
USBD_CONNECTED
Definition: usbd_core.h:78
USBD_CONFIGURED
Definition: usbd_core.h:76
enum usbd_status_enum
Enumerator
USBD_OK | USB device ok
USBD_BUSY | USB device busy
USBD_FAIL | USB device fail
USBD_OK |
USBD_BUSY |
USBD_FAIL |

Definition at line 82 of file usbd_core.h.

83 {
84 USBD_OK = 0,
85 USBD_BUSY,
86 USBD_FAIL
87 }usbd_status_enum;
USBD_FAIL
Definition: usbd_core.h:86
USBD_OK
Definition: usbd_core.h:84
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
USBD_BUSY
Definition: usbd_core.h:85

Function Documentation

void usbd_core_deinit ( void )

device core register configure when stop device

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 81 of file usbd_core.c.

82 {
83 /* disable all interrupts and set USB reset */
84 USBD_REG_SET(USBD_CTL, CTL_SETRST);
85
86 /* clear all interrupt flags */
87 USBD_REG_SET(USBD_INTF, 0U);
88
89 /* close device */
90 USBD_REG_SET(USBD_CTL, CTL_SETRST | CTL_CLOSE);
91 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
CTL_SETRST
#define CTL_SETRST
Definition: usbd_regs.h:52
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CTL_CLOSE
#define CTL_CLOSE
Definition: usbd_regs.h:51
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
void usbd_core_init ( usbd_core_handle_struct * pudev )

device core register initialization

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 27 of file usbd_core.c.

28 {
29 /* disable remote wakeup feature */
30 pudev->remote_wakeup = 0U;
31
32 /* just reset the CLOSE bit */
33 USBD_REG_SET(USBD_CTL, CTL_SETRST);
34
35 /* may be need wait some time(tSTARTUP) ... */
36
37 /* clear SETRST bit in USBD_CTL register */
38 USBD_REG_SET(USBD_CTL, 0U);
39
40 /* clear all pending interrupts */
41 USBD_REG_SET(USBD_INTF, 0U);
42
43 /* set allocation buffer address */
44 USBD_REG_SET(USBD_BADDR, BUFFER_ADDRESS & 0xFFF8U);
45
46 g_interrupt_mask = IER_MASK;
47
48 #ifdef LPM_ENABLED
49 /* enable L1REQ interrupt */
50 USBD_REG_SET(USBD_LPMCS, LPMCS_LPMACK | LPMCS_LPMEN);
51 #endif /* LPM_ENABLED */
52
53 /* enable all interrupts mask bits */
54 USBD_REG_SET(USBD_CTL, g_interrupt_mask);
55 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
g_interrupt_mask
uint32_t g_interrupt_mask
Definition: usbd_core.c:16
CTL_SETRST
#define CTL_SETRST
Definition: usbd_regs.h:52
USBD_LPMCS
#define USBD_LPMCS
Definition: usbd_regs.h:34
LPMCS_LPMACK
#define LPMCS_LPMACK
Definition: usbd_regs.h:93
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
usbd_core_handle_struct::remote_wakeup
uint8_t remote_wakeup
Definition: usbd_core.h:131
USBD_BADDR
#define USBD_BADDR
Definition: usbd_regs.h:28
IER_MASK
#define IER_MASK
Definition: usbd_core.h:20
LPMCS_LPMEN
#define LPMCS_LPMEN
Definition: usbd_regs.h:94
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
void usbd_ep_clear_stall | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

clear endpoint stalled status

Parameters
[in] | pudev | pointer to usb core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[out] | none
Return values
none

Definition at line 297 of file usbd_core.c.

298 {
299 uint8_t ep_num = ep_addr & 0x7FU;
300 usb_ep_struct *ep;
301
302 if (ep_addr >> 7U) {
303 ep = &pudev->in_ep[ep_num];
304
305 /* clear endpoint data toggle bit */
306 USBD_DTG_TX_CLEAR(ep_num);
307
308 /* clear endpoint stall status */
309 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID);
310 } else {
311 ep = &pudev->out_ep[ep_num];
312
313 /* clear endpoint data toggle bit */
314 USBD_DTG_RX_CLEAR(ep_num);
315
316 /* clear endpoint stall status */
317 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID);
318 }
319
320 ep->stall = 0U;
321 }
EPRX_VALID
#define EPRX_VALID
Definition: usbd_regs.h:127
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
usb_ep_struct
Definition: usbd_core.h:102
EPTX_VALID
#define EPTX_VALID
Definition: usbd_regs.h:118
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
usb_ep_struct::stall
uint8_t stall
Definition: usbd_core.h:105
USBD_DTG_RX_CLEAR
#define USBD_DTG_RX_CLEAR(ep_num)
Definition: usbd_regs.h:249
USBD_DTG_TX_CLEAR
#define USBD_DTG_TX_CLEAR(ep_num)
Definition: usbd_regs.h:256
void usbd_ep_data_read | ( | uint8_t * | user_fifo,
 |  | uint16_t | usbram_addr,
 |  | uint16_t | bytes
 | ) |  |

read datas from USBRAM to user fifo

Parameters
[in] | user_fifo | pointer to user fifo
[in] | usbram_addr | the allocation buffer address of the endpoint
[in] | bytes | the bytes count of the read datas
[out] | none
Return values
none

Definition at line 369 of file usbd_core.c.

370 {
371 uint32_t n;
372 uint32_t *read_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM));
373
374 for (n = 0U; n < (bytes + 1U) / 2U; n++) {
375 *((__packed uint16_t*)user_fifo) = (uint16_t)*read_addr++;
376 user_fifo += 2U;
377 }
378 }
USBD_RAM
#define USBD_RAM
Definition: usbd_regs.h:20
void usbd_ep_data_write | ( | uint8_t * | user_fifo,
 |  | uint16_t | usbram_addr,
 |  | uint16_t | bytes
 | ) |  |

write datas from user fifo to USBRAM

Parameters
[in] | user_fifo | pointer to user fifo
[in] | usbram_addr | the allocation buffer address of the endpoint
[in] | bytes | the bytes count of the write datas
[out] | none
Return values
none

Definition at line 350 of file usbd_core.c.

351 {
352 uint32_t n;
353 uint32_t *write_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM));
354
355 for (n = 0U; n < (bytes + 1U) / 2U; n++) {
356 *write_addr++ = *((__packed uint16_t*)user_fifo);
357 user_fifo += 2U;
358 }
359 }
USBD_RAM
#define USBD_RAM
Definition: usbd_regs.h:20
void usbd_ep_deinit | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

configure the endpoint when it is disabled

Parameters
[in] | pudev | pointer to USB core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[out] | none
Return values
none

Definition at line 173 of file usbd_core.c.

174 {
175 uint8_t ep_num = ep_addr & 0x7F;
176
177 if (ep_addr >> 7) {
178 USBD_DTG_TX_CLEAR(ep_num);
179
180 /* configure the endpoint status as DISABLED */
181 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_DISABLED);
182 } else {
183 USBD_DTG_RX_CLEAR(ep_num);
184
185 /* configure the endpoint status as DISABLED */
186 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED);
187 }
188 }
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
EPRX_DISABLED
#define EPRX_DISABLED
Definition: usbd_regs.h:124
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
EPTX_DISABLED
#define EPTX_DISABLED
Definition: usbd_regs.h:115
USBD_DTG_RX_CLEAR
#define USBD_DTG_RX_CLEAR(ep_num)
Definition: usbd_regs.h:249
USBD_DTG_TX_CLEAR
#define USBD_DTG_TX_CLEAR(ep_num)
Definition: usbd_regs.h:256
void usbd_ep_init | ( | usbd_core_handle_struct * | pudev,
 |  | void * | ep_desc
 | ) |  |

endpoint initialization

Parameters
[in] | pudev | pointer to USB core instance
[in] | pep_desc | pointer to endpoint descriptor
[out] | none
Return values
none

Definition at line 100 of file usbd_core.c.

101 {
102 usb_ep_struct *ep;
103 uint8_t ep_num = ((usb_descriptor_endpoint_struct *)ep_desc)->bEndpointAddress & 0x0FU;
104 uint32_t reg_value = ((usb_descriptor_endpoint_struct *)ep_desc)->wMaxPacketSize;
105
106 if (((usb_descriptor_endpoint_struct *)ep_desc)->bEndpointAddress >> 7U) {
107 ep = &pudev->in_ep[ep_num];
108
109 ep->maxpacket = reg_value;
110
111 /* set the endpoint transmit buffer address */
112 (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr;
113
114 reg_value = (reg_value + 1U) & ~1U;
115
116 /* configure the endpoint status as NAK status */
117 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK);
118 } else {
119 ep = &pudev->out_ep[ep_num];
120
121 ep->maxpacket = reg_value;
122
123 /* set the endpoint receive buffer address */
124 (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr;
125
126 if (reg_value > 62U) {
127 reg_value = (reg_value + 31U) & ~31U;
128 (pbuf_reg + ep_num)->rx_count = ((reg_value << 5U) - 1U) | 0x8000U;
129 } else {
130 reg_value = (reg_value + 1U) & ~1U;
131 (pbuf_reg + ep_num)->rx_count = reg_value << 9U;
132 }
133
134 /* configure the endpoint status as NAK status */
135 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_NAK);
136 }
137
138 g_free_buf_addr += reg_value;
139
140 /* set the endpoint type */
141 switch (((usb_descriptor_endpoint_struct *)ep_desc)->bmAttributes & USB_EPTYPE_MASK) {
142 case ENDP_CONTROL:
143 reg_value = EP_CONTROL;
144 break;
145 case ENDP_BULK:
146 reg_value = EP_BULK;
147 break;
148 case ENDP_INT:
149 reg_value = EP_INTERRUPT;
150 break;
151 case ENDP_ISOC:
152 reg_value = EP_ISO;
153 break;
154 default:
155 break;
156 }
157
158 USBD_REG_SET(USBD_EPxCS(ep_num), reg_value | ep_num);
159
160 ep->stall = 0;
161 }
EP_ISO
#define EP_ISO
Definition: usbd_regs.h:105
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
ENDP_INT
Definition: usbd_core.h:53
ENDP_ISOC
Definition: usbd_core.h:51
EPRX_NAK
#define EPRX_NAK
Definition: usbd_regs.h:126
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
EP_CONTROL
#define EP_CONTROL
Definition: usbd_regs.h:104
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
usb_ep_struct
Definition: usbd_core.h:102
EP_BULK
#define EP_BULK
Definition: usbd_regs.h:103
ENDP_BULK
Definition: usbd_core.h:52
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
ENDP_CONTROL
Definition: usbd_core.h:50
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
usb_ep_struct::stall
uint8_t stall
Definition: usbd_core.h:105
USBD_EPxCS
#define USBD_EPxCS(ep_id)
Definition: usbd_regs.h:31
pbuf_reg
usbd_ep_buf_struct * pbuf_reg
Definition: usbd_core.c:19
EP_INTERRUPT
#define EP_INTERRUPT
Definition: usbd_regs.h:106
g_free_buf_addr
uint32_t g_free_buf_addr
Definition: usbd_core.c:17
USB_EPTYPE_MASK
#define USB_EPTYPE_MASK
Definition: usbd_std.h:73
EPTX_NAK
#define EPTX_NAK
Definition: usbd_regs.h:117
void usbd_ep_rx | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint16_t | buf_len
 | ) |  |

endpoint prepare to receive data

Parameters
[in] | pudev | pointer to usb core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[in] | pbuf | user buffer address pointer
[in] | buf_len | buffer length
[out] | none
Return values
none

Definition at line 202 of file usbd_core.c.

203 {
204 usb_ep_struct *ep;
205 uint8_t ep_num = ep_addr & 0x7FU;
206
207 ep = &pudev->out_ep[ep_num];
208
209 /* configure the transaction level parameters */
210 ep->trs_buf = pbuf;
211 ep->trs_len = buf_len;
212
213 /* enable endpoint to receive */
214 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID);
215 }
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
EPRX_VALID
#define EPRX_VALID
Definition: usbd_regs.h:127
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
usb_ep_struct
Definition: usbd_core.h:102
void usbd_ep_stall | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

set an endpoint to STALL status

Parameters
[in] | pudev | pointer to usb core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[out] | none
Return values
none

Definition at line 264 of file usbd_core.c.

265 {
266 uint8_t ep_num = ep_addr & 0x7FU;
267 usb_ep_struct *ep;
268
269 if (ep_addr >> 7U) {
270 ep = &pudev->in_ep[ep_num];
271
272 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_STALL);
273 } else {
274 ep = &pudev->out_ep[ep_num];
275
276 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_STALL);
277 }
278
279 ep->stall = 1U;
280
281 if (0U == ep_num) {
282 /* control endpoint need to be stalled in two directions */
283 USBD_ENDP_RX_TX_STATUS_SET(ep_num, EPRX_STALL, EPTX_STALL);
284 }
285 }
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
USBD_ENDP_RX_TX_STATUS_SET
#define USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx)
Definition: usbd_regs.h:226
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
usb_ep_struct
Definition: usbd_core.h:102
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
EPTX_STALL
#define EPTX_STALL
Definition: usbd_regs.h:116
usb_ep_struct::stall
uint8_t stall
Definition: usbd_core.h:105
EPRX_STALL
#define EPRX_STALL
Definition: usbd_regs.h:125
uint8_t usbd_ep_status_get | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

get the endpoint status

Parameters
[in] | pudev | pointer to usb core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[out] | none
Return values
endpoint status

Definition at line 333 of file usbd_core.c.

334 {
335 if (ep_addr >> 7U) {
336 return (uint8_t)USBD_ENDP_TX_STATUS_GET((ep_addr & 0x7FU));
337 } else {
338 return (uint8_t)USBD_ENDP_RX_STATUS_GET(ep_addr);
339 }
340 }
USBD_ENDP_RX_STATUS_GET
#define USBD_ENDP_RX_STATUS_GET(ep_num)
Definition: usbd_regs.h:223
USBD_ENDP_TX_STATUS_GET
#define USBD_ENDP_TX_STATUS_GET(ep_num)
Definition: usbd_regs.h:222
void usbd_ep_tx | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint16_t | buf_len
 | ) |  |

endpoint prepare to transmit data

Parameters
[in] | pudev | pointer to USB core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[in] | pbuf | transmit buffer address pointer
[in] | buf_len | buffer length
[out] | none
Return values
none

Definition at line 229 of file usbd_core.c.

230 {
231 __IO uint32_t len = 0U;
232 uint8_t ep_num = ep_addr & 0x7FU;
233 usb_ep_struct *ep = &pudev->in_ep[ep_num];
234
235 /* configure the transaction level parameters */
236 ep->trs_buf = pbuf;
237 ep->trs_len = buf_len;
238 ep->trs_count = 0U;
239
240 /* transmit length is more than one packet */
241 if (ep->trs_len > ep->maxpacket) {
242 len = ep->maxpacket;
243 } else {
244 len = ep->trs_len;
245 }
246
247 usbd_ep_data_write(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, (uint16_t)len);
248 (pbuf_reg + ep_num)->tx_count = (uint16_t)len;
249
250 /* enable endpoint to transmit */
251 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID);
252 }
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
usb_ep_struct
Definition: usbd_core.h:102
EPTX_VALID
#define EPTX_VALID
Definition: usbd_regs.h:118
usbd_ep_data_write
void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
write datas from user fifo to USBRAM
Definition: usbd_core.c:350
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
pbuf_reg
usbd_ep_buf_struct * pbuf_reg
Definition: usbd_core.c:19
uint16_t usbd_rx_count_get | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

get the received data length

Parameters
[in] | pudev | pointer to USB core instance
[in] | ep_num | endpoint identifier which is in (0..7)
[out] | none
Return values
received data length

Definition at line 387 of file usbd_core.c.

388 {
389 return (uint16_t)pudev->out_ep[ep_num].trs_count;
390 }
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
void user_buffer_free | ( | uint8_t | ep_num,
 |  | uint8_t | dir
 | ) |  |

free buffer used from application by toggling the SW_BUF byte

Parameters
[in] | ep_num | endpoint identifier (0..7)
[in] | dir | endpoint direction which can be OUT(0) or IN(1)
[out] | none
Return values
None

Definition at line 64 of file usbd_core.c.

65 {
66 if (DBUF_EP_OUT == dir) {
67 USBD_SWBUF_RX_TOGGLE(ep_num);
68 } else if (DBUF_EP_IN == dir) {
69 USBD_SWBUF_TX_TOGGLE(ep_num);
70 } else {
71 /* no operation */
72 }
73 }
DBUF_EP_IN
Definition: usbd_regs.h:164
USBD_SWBUF_TX_TOGGLE
#define USBD_SWBUF_TX_TOGGLE(ep_num)
Definition: usbd_regs.h:268
USBD_SWBUF_RX_TOGGLE
#define USBD_SWBUF_RX_TOGGLE(ep_num)
Definition: usbd_regs.h:269
DBUF_EP_OUT
Definition: usbd_regs.h:165

Variable Documentation

uint32_t g_free_buf_addr

Definition at line 17 of file usbd_core.c.

usbd_ep_buf_struct* pbuf_reg

Definition at line 19 of file usbd_core.c.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_core.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Data Structures | Macros | Enumerations | Functions
usb_core.h File Reference

USB core driver header file. More...

#include "usb_conf.h"
#include "usb_regs.h"
#include "usb_defines.h"

Go to the source code of this file.

Data Structures

struct | usb_core_cfgs_struct
struct | usb_ep_struct
struct | usb_device_req_struct
struct | dcd_dev_struct
struct | usb_hostchannel_struct
struct | hcd_dev_struct
struct | usb_core_handle_struct

Macros

#define | USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */
#define | RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */
#define | HC_MAX_PACKET_COUNT 140U /* host channel max packet count */
#define | USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT
#define | USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U)

Enumerations

enum | usb_status_enum { USB_OK = 0, USB_FAIL }
enum hc_status_enum {
HC_IDLE = 0, HC_XF, HC_HALTED, HC_NAK,
HC_NYET, HC_STALL, HC_TRACERR, HC_BBERR,
HC_DTGERR
}
enum urb_state_enum {
URB_IDLE = 0, URB_DONE, URB_NOTREADY, URB_ERROR,
URB_STALL, URB_PING
}
enum usbd_status_enum {
USBD_OK = 0, USBD_BUSY, USBD_FAIL, USBD_OK = 0,
USBD_BUSY, USBD_FAIL
}
enum usbd_control_state_enum {
USB_CTRL_IDLE = 0, USB_CTRL_SETUP, USB_CTRL_DATA_IN, USB_CTRL_DATA_OUT,
USB_CTRL_STATUS_IN, USB_CTRL_STATUS_OUT, USB_CTRL_STALL
}
enum | usb_dir_enum { USB_RX = 0, USB_TX }

Functions

usb_status_enum | usb_core_init (usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation More...
usb_status_enum | usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters More...
void * | usb_fifo_read (uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint More...
usb_status_enum | usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint More...
usb_status_enum | usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs More...
usb_status_enum | usb_rxfifo_flush (usb_core_handle_struct *pudev)
flush the entire Rx FIFO More...
usb_status_enum | usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device) More...

Detailed Description

USB core driver header file.

Definition in file usb_core.h.

Macro Definition Documentation

#define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */

Definition at line 22 of file usb_core.h.

#define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */

Definition at line 21 of file usb_core.h.

#define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT

Definition at line 24 of file usb_core.h.

#define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */

Definition at line 20 of file usb_core.h.

#define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U)

Definition at line 25 of file usb_core.h.

Enumeration Type Documentation

enum hc_status_enum
Enumerator
HC_IDLE
HC_XF
HC_HALTED
HC_NAK
HC_NYET
HC_STALL
HC_TRACERR
HC_BBERR
HC_DTGERR

Definition at line 35 of file usb_core.h.

36 {
37 HC_IDLE = 0, /* USB host channel idle status */
38 HC_XF, /* USB host channel transfer status */
39 HC_HALTED, /* USB host channel halted status */
40 HC_NAK, /* USB host channel nak status */
41 HC_NYET, /* USB host channel nyet status */
42 HC_STALL, /* USB host channel stall status */
43 HC_TRACERR, /* USB host channel tracerr status */
44 HC_BBERR, /* USB host channel bberr status */
45 HC_DTGERR, /* USB host channel dtgerr status */
46 }hc_status_enum;
HC_NYET
Definition: usb_core.h:41
HC_XF
Definition: usb_core.h:38
hc_status_enum
hc_status_enum
Definition: usb_core.h:35
HC_BBERR
Definition: usb_core.h:44
HC_IDLE
Definition: usb_core.h:37
HC_TRACERR
Definition: usb_core.h:43
HC_NAK
Definition: usb_core.h:40
HC_STALL
Definition: usb_core.h:42
HC_HALTED
Definition: usb_core.h:39
HC_DTGERR
Definition: usb_core.h:45
enum urb_state_enum
Enumerator
URB_IDLE
URB_DONE
URB_NOTREADY
URB_ERROR
URB_STALL
URB_PING

Definition at line 49 of file usb_core.h.

50 {
51 URB_IDLE = 0, /* USB URB idle status */
52 URB_DONE, /* USB URB done status */
53 URB_NOTREADY, /* USB URB notready status */
54 URB_ERROR, /* USB URB error status */
55 URB_STALL, /* USB URB stall status */
56 URB_PING /* USB URB ping status */
57 }urb_state_enum;
URB_STALL
Definition: usb_core.h:55
urb_state_enum
urb_state_enum
Definition: usb_core.h:49
URB_PING
Definition: usb_core.h:56
URB_IDLE
Definition: usb_core.h:51
URB_NOTREADY
Definition: usb_core.h:53
URB_ERROR
Definition: usb_core.h:54
URB_DONE
Definition: usb_core.h:52
enum usb_dir_enum
Enumerator
USB_RX
USB_TX

Definition at line 93 of file usb_core.h.

94 {
95 USB_RX = 0, /* receive direction type value */
96 USB_TX /* transmit direction type value */
97 }usb_dir_enum;
USB_TX
Definition: usb_core.h:96
USB_RX
Definition: usb_core.h:95
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:93
enum usb_status_enum
Enumerator
USB_OK
USB_FAIL

Definition at line 28 of file usb_core.h.

29 {
30 USB_OK = 0, /* USB core OK status */
31 USB_FAIL /* USB core fail status */
32 }usb_status_enum;
USB_OK
Definition: usb_core.h:30
usb_status_enum
usb_status_enum
Definition: usb_core.h:28
USB_FAIL
Definition: usb_core.h:31
enum usbd_control_state_enum
Enumerator
USB_CTRL_IDLE
USB_CTRL_SETUP
USB_CTRL_DATA_IN
USB_CTRL_DATA_OUT
USB_CTRL_STATUS_IN
USB_CTRL_STATUS_OUT
USB_CTRL_STALL

Definition at line 81 of file usb_core.h.

82 {
83 USB_CTRL_IDLE = 0, /* USB control transfer idle state */
84 USB_CTRL_SETUP, /* USB control transfer setup state */
85 USB_CTRL_DATA_IN, /* USB control transfer data in state */
86 USB_CTRL_DATA_OUT, /* USB control transfer data out state */
87 USB_CTRL_STATUS_IN, /* USB control transfer status in state*/
88 USB_CTRL_STATUS_OUT, /* USB control transfer status out state */
89 USB_CTRL_STALL /* USB control transfer stall state */
90 }usbd_control_state_enum;
USB_CTRL_STATUS_OUT
Definition: usb_core.h:88
USB_CTRL_STATUS_IN
Definition: usb_core.h:87
USB_CTRL_DATA_IN
Definition: usb_core.h:85
USB_CTRL_STALL
Definition: usb_core.h:89
USB_CTRL_DATA_OUT
Definition: usb_core.h:86
USB_CTRL_SETUP
Definition: usb_core.h:84
USB_CTRL_IDLE
Definition: usb_core.h:83
usbd_control_state_enum
usbd_control_state_enum
Definition: usb_core.h:81
enum usbd_status_enum
Enumerator
USBD_OK | USB device ok
USBD_BUSY | USB device busy
USBD_FAIL | USB device fail
USBD_OK |
USBD_BUSY |
USBD_FAIL |

Definition at line 73 of file usb_core.h.

74 {
75 USBD_OK = 0, /* USB device ok status */
76 USBD_BUSY, /* USB device busy status */
77 USBD_FAIL, /* USB device fail stauts */
78 }usbd_status_enum;
USBD_OK
Definition: usb_core.h:75
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:73
USBD_FAIL
Definition: usb_core.h:77
USBD_BUSY
Definition: usb_core.h:76

Function Documentation

usb_status_enum usb_core_init ( usb_core_handle_struct * pudev )

initializes the USB controller registers and prepares the core device mode or host mode operation

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 170 of file usb_core.c.

171 {
172 /* soft reset the core */
173 usb_core_reset(pudev);
174
175 /* active the transceiver and enable vbus sensing */
176 USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN;
177
178 /* set Tx FIFO empty level to half empty mode */
179 USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF;
180
181 #ifndef VBUS_SENSING_ENABLED
182 USB_GCCFG |= GCCFG_VBUSIG;
183 #endif /* VBUS_SENSING_ENABLED */
184
185 if(pudev->cfg.sof_output){
186 USB_GCCFG |= GCCFG_SOFOEN;
187 }
188
189 if (NULL != pudev->mdelay) {
190 pudev->mdelay(20U);
191 }
192
193
194 #ifdef USE_OTG_MODE
195 /* enable OTG features */
196 USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP;
197 USB_OTG_EnableCommonInt(pudev);
198
199 #endif /* USE_OTG_MODE */
200
201 return USB_OK;
202 }
USB_GCCFG
#define USB_GCCFG
Definition: usb_regs.h:49
GAHBCS_TXFTH
#define GAHBCS_TXFTH
Definition: usb_regs.h:118
GCCFG_VBUSBCEN
#define GCCFG_VBUSBCEN
Definition: usb_regs.h:222
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:39
GCCFG_PWRON
#define GCCFG_PWRON
Definition: usb_regs.h:224
USB_OK
Definition: usb_core.h:30
TXFIFO_EMPTY_HALF
#define TXFIFO_EMPTY_HALF
Definition: usb_regs.h:452
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
GCCFG_SOFOEN
#define GCCFG_SOFOEN
Definition: usb_regs.h:221
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:67
GCCFG_VBUSACEN
#define GCCFG_VBUSACEN
Definition: usb_regs.h:223
GCCFG_VBUSIG
#define GCCFG_VBUSIG
Definition: usb_regs.h:220
NULL
#define NULL
Definition: usbd_std.h:20
USB_GAHBCS
#define USB_GAHBCS
Definition: usb_regs.h:38
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:203
usb_status_enum usb_core_select | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initialize core parameters

Parameters
[in] | pudev | pointer to usb device
[in] | core_id | USB core id
[out] | none
Return values
operation status

Definition at line 128 of file usb_core.c.

129 {
130 /* at startup the core is in FS mode */
131 pudev->cfg.core_speed = USB_CORE_SPEED_FULL;
132 pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE;
133
134 /* initialize the core parameters */
135 if (USB_FS_CORE_ID == core_id) {
136
137 pudev->cfg.core_id = USB_FS_CORE_ID;
138
139 /* set the host channel numbers */
140 pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT;
141
142 /* set the device endpoint numbers */
143 pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT;
144
145 /* fifo size is in terms of DWORD */
146 pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN;
147
148 /* OTG_FS core use embedded physical layer */
149 pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY;
150
151 #ifdef USBFS_SOF_OUTPUT_ENABLED
152 pudev->cfg.sof_output = 1U;
153 #endif /* USBFS_SOF_OUTPUT_ENABLED */
154
155 #ifdef USBFS_LOW_PWR_MGMT_SUPPORT
156 pudev->cfg.low_power = 1U;
157 #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */
158 }
159
160 return USB_OK;
161 }
USBFS_MAX_PACKET_SIZE
#define USBFS_MAX_PACKET_SIZE
Definition: usb_defines.h:25
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:66
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:69
USBFS_MAX_HOST_CHANNELCOUNT
#define USBFS_MAX_HOST_CHANNELCOUNT
Definition: usb_defines.h:26
USB_OK
Definition: usb_core.h:30
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:64
USB_CORE_SPEED_FULL
#define USB_CORE_SPEED_FULL
Definition: usb_defines.h:23
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:67
USB_CORE_EMBEDDED_PHY
#define USB_CORE_EMBEDDED_PHY
Definition: usb_defines.h:36
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:63
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:68
USB_FS_CORE_ID
Definition: usb_defines.h:90
USBFS_MAX_FIFO_WORDLEN
#define USBFS_MAX_FIFO_WORDLEN
Definition: usb_defines.h:28
USBFS_MAX_DEV_EPCOUNT
#define USBFS_MAX_DEV_EPCOUNT
Definition: usb_defines.h:27
usb_core_cfgs_struct::max_fifo_size
uint16_t max_fifo_size
Definition: usb_core.h:70
usb_core_cfgs_struct::core_id
uint8_t core_id
Definition: usb_core.h:62
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:65
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:203
void* usb_fifo_read | ( | uint8_t * | dest,
 |  | uint16_t | len
 | ) |  |

read a packet from the Rx FIFO associated with the endpoint

Parameters
[in] | dest | pointer to destination buffer
[in] | len | packet length
[out] | none
Return values
void type pointer

Definition at line 105 of file usb_core.c.

106 {
107 uint32_t i = 0U;
108 uint32_t count32b = (len + 3U) / 4U;
109
110 __IO uint32_t *fifo = USB_FIFO(0U);
111
112 for (i = 0U; i < count32b; i++) {
113 *(__packed uint32_t *)dest = *fifo;
114
115 dest += 4U;
116 }
117
118 return ((void *)dest);
119 }
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:94
usb_status_enum usb_fifo_write | ( | uint8_t * | src,
 |  | uint8_t | chep_num,
 |  | uint16_t | len
 | ) |  |

write a packet into the Tx FIFO associated with the endpoint

Parameters
[in] | src | pointer to source buffer
[in] | chep_num | channel or endpoint identifier which is in (0..3)
[in] | len | packet length
[out] | none
Return values
operation status

Definition at line 82 of file usb_core.c.

83 {
84 uint32_t count32b = 0U, i = 0U;
85 __IO uint32_t *fifo = USB_FIFO(chep_num);
86
87 count32b = (len + 3U) / 4U;
88
89 for (i = 0U; i < count32b; i++) {
90 *fifo = *((__packed uint32_t *)src);
91
92 src += 4U;
93 }
94
95 return USB_OK;
96 }
USB_OK
Definition: usb_core.h:30
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:94
usb_status_enum usb_mode_set | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | mode
 | ) |  |

set operation mode (host or device)

Parameters
[in] | pudev | pointer to usb device
[in] mode operation mode which need to set
  • HOST_MODE
  • DEVICE_MODE
[out] | none
Return values
operation status

Definition at line 268 of file usb_core.c.

269 {
270 if (HOST_MODE == mode) {
271 USB_GUSBCS &= ~GUSBCS_FDM;
272 USB_GUSBCS |= GUSBCS_FHM;
273 } else if (DEVICE_MODE == mode) {
274 USB_GUSBCS &= ~GUSBCS_FHM;
275 USB_GUSBCS |= GUSBCS_FDM;
276 } else {
277 /* no operation */
278 }
279
280 if (NULL != pudev->mdelay) {
281 pudev->mdelay(50U);
282 }
283
284 return USB_OK;
285 }
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:49
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:39
GUSBCS_FDM
#define GUSBCS_FDM
Definition: usb_regs.h:122
USB_OK
Definition: usb_core.h:30
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
GUSBCS_FHM
#define GUSBCS_FHM
Definition: usb_regs.h:123
NULL
#define NULL
Definition: usbd_std.h:20
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:48
usb_status_enum usb_rxfifo_flush ( usb_core_handle_struct * pudev )

flush the entire Rx FIFO

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 238 of file usb_core.c.

239 {
240 uint32_t count = 0U;
241
242 USB_GRSTCTL = GRSTCTL_RXFF;
243
244 /* wait for Rx FIFO flush bit is set */
245 do {
246 if (++count > 200000U) {
247 break;
248 }
249 } while (USB_GRSTCTL & GRSTCTL_RXFF);
250
251 /* wait for 3 PHY clocks */
252 if (NULL != pudev->udelay) {
253 pudev->udelay(3U);
254 }
255
256 return USB_OK;
257 }
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:217
USB_OK
Definition: usb_core.h:30
GRSTCTL_RXFF
#define GRSTCTL_RXFF
Definition: usb_regs.h:132
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:40
NULL
#define NULL
Definition: usbd_std.h:20
usb_status_enum usb_txfifo_flush | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | fifo_num
 | ) |  |

flush a Tx FIFO or all Tx FIFOs

Parameters
[in] | pudev | pointer to usb device
[in] | fifo_num | FIFO number which is in (0..3)
[out] | none
Return values
operation status

Definition at line 211 of file usb_core.c.

212 {
213 uint32_t count = 0U;
214
215 USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF;
216
217 /* wait for Tx FIFO flush bit is set */
218 do {
219 if (++count > 200000U) {
220 break;
221 }
222 } while (USB_GRSTCTL & GRSTCTL_TXFF);
223
224 /* wait for 3 PHY clocks */
225 if (NULL != pudev->udelay) {
226 pudev->udelay(3U);
227 }
228
229 return USB_OK;
230 }
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:217
USB_OK
Definition: usb_core.h:30
GRSTCTL_TXFF
#define GRSTCTL_TXFF
Definition: usb_regs.h:131
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:40
NULL
#define NULL
Definition: usbd_std.h:20
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_int.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
Data Structures | Functions | Variables
usbd_int.h File Reference
#include "usbd_core.h"
#include "usbd_std.h"
#include "usbd_pwr.h"

Go to the source code of this file.

Data Structures

struct usbd_int_cb_struct

Functions

void usbd_isr (void)
USB interrupt events service routine. More...

Variables

usbd_core_handle_struct usb_device_dev
usbd_int_cb_struct * usbd_int_fops

Function Documentation

void usbd_isr ( void )

USB interrupt events service routine.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 39 of file usbd_int.c.

40 {
41 __IO uint16_t interrupt_flag = 0U;
42 __IO uint16_t ctlr = 0U;
43
44 interrupt_flag = USBD_REG_GET(USBD_INTF);
45
46 if (g_interrupt_mask & INTF_STIF & interrupt_flag) {
47 /* the endpoint successful transfer interrupt service */
48 usbd_intf_lpst(&usb_device_dev);
49 }
50
51 if (g_interrupt_mask & INTF_WKUPIF & interrupt_flag) {
52 /* clear wakeup interrupt flag in INTF */
53 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_WKUPIF);
54
55 /* USB wakeup interrupt handle */
56 usbd_intf_wakeup(&usb_device_dev);
57
58 #ifdef LPM_ENABLED
59 /* clear L1 remote wakeup flag */
60 L1_remote_wakeup = 0;
61 #endif /* LPM_ENABLED */
62 }
63
64 if (g_interrupt_mask & INTF_SPSIF & interrupt_flag) {
65 if(!(USBD_REG_GET(USBD_CTL) & CTL_RSREQ)) {
66 /* process library core layer suspend routine*/
67 usbd_intf_suspend(&usb_device_dev);
68
69 /* clear of suspend interrupt flag bit must be done after setting of CTLR_SETSPS */
70 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SPSIF);
71 }
72 }
73
74 if (g_interrupt_mask & INTF_SOFIF & interrupt_flag) {
75 /* clear SOF interrupt flag in INTF */
76 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SOFIF);
77
78 /* USB SOF interrupt handle */
79 usbd_intf_sof(&usb_device_dev);
80 }
81
82 if (g_interrupt_mask & INTF_ESOFIF & interrupt_flag) {
83 /* clear ESOF interrupt flag in INTF */
84 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_ESOFIF);
85
86 /* USB ESOF interrupt handle */
87 usbd_intf_esof(&usb_device_dev);
88 }
89
90 if (g_interrupt_mask & INTF_RSTIF & interrupt_flag) {
91 /* clear reset interrupt flag in INTF */
92 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_RSTIF);
93
94 /* USB reset interrupt handle */
95 usbd_intf_reset(&usb_device_dev);
96 }
97
98 #ifdef LPM_ENABLED
99 if (g_interrupt_mask & INTF_L1REQ & interrupt_flag) {
100 /* clear L1 ST bit in LPM INTF */
101 USBD_REG_SET(USBD_INTF, CLR_L1REQ);
102
103 /* read BESL field from subendpoint0 register which coressponds to HIRD parameter in LPM spec */
104 besl = (USBD_REG_GET(USBD_LPMCS) & LPMCS_BLSTAT) >> 4;
105
106 /* read BREMOTEWAKE bit from subendpoint0 register which corresponding to bRemoteWake bit in LPM request */
107 L1_remote_wakeup = (USBD_REG_GET(USBD_LPMCS) & LPMCS_REMWK) >> 8;
108
109 /* process USB device core layer suspend routine */
110 /* enter USB model in suspend and system in low power mode (DEEP_SLEEP mode) */
111 usbd_intf_suspend(&usb_device_dev);
112 }
113 #endif /* LPM_ENABLED */
114 }
INTF_STIF
#define INTF_STIF
Definition: usbd_regs.h:55
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
USBD_LPMCS
#define USBD_LPMCS
Definition: usbd_regs.h:34
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
INTF_L1REQ
#define INTF_L1REQ
Definition: usbd_regs.h:63
LPMCS_BLSTAT
#define LPMCS_BLSTAT
Definition: usbd_regs.h:91
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CLR_SPSIF
#define CLR_SPSIF
Definition: usbd_regs.h:142
INTF_SOFIF
#define INTF_SOFIF
Definition: usbd_regs.h:61
CLR_ESOFIF
#define CLR_ESOFIF
Definition: usbd_regs.h:145
g_interrupt_mask
uint32_t g_interrupt_mask
Definition: usbd_core.c:16
CLR_SOFIF
#define CLR_SOFIF
Definition: usbd_regs.h:144
LPMCS_REMWK
#define LPMCS_REMWK
Definition: usbd_regs.h:92
CLR_L1REQ
#define CLR_L1REQ
Definition: usbd_regs.h:146
INTF_RSTIF
#define INTF_RSTIF
Definition: usbd_regs.h:60
INTF_ESOFIF
#define INTF_ESOFIF
Definition: usbd_regs.h:62
INTF_SPSIF
#define INTF_SPSIF
Definition: usbd_regs.h:59
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
CTL_RSREQ
#define CTL_RSREQ
Definition: usbd_regs.h:48
INTF_WKUPIF
#define INTF_WKUPIF
Definition: usbd_regs.h:58
CLR_WKUPIF
#define CLR_WKUPIF
Definition: usbd_regs.h:141
CLR_RSTIF
#define CLR_RSTIF
Definition: usbd_regs.h:143
usb_device_dev
usbd_core_handle_struct usb_device_dev

Variable Documentation

usbd_core_handle_struct usb_device_dev
usbd_int_cb_struct* usbd_int_fops


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_pwr.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
Functions
usbd_pwr.h File Reference

USB device power management functions prototype. More...

#include "usbd_core.h"

Go to the source code of this file.

Functions

void | resume_mcu (void)
USB wakeup first operation is to wakeup mcu. More...
void | usbd_suspend (void)
set USB device to suspend mode More...
void | usbd_remote_wakeup_active (void)
start to remote wakeup More...

Detailed Description

USB device power management functions prototype.

Definition in file usbd_pwr.h.

Function Documentation

void resume_mcu ( void )

USB wakeup first operation is to wakeup mcu.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 33 of file usbd_pwr.c.

34 {
35 /* clear low_power mode bit in USBD_CTL */
36 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM));
37
38 #ifdef USBD_LOWPWR_MODE_ENABLE
39
40 /* restore normal operations */
41 lowpower_mode_exit();
42
43 #endif /* USBD_LOWPWR_MODE_ENABLE */
44
45 /* clear SETSPS bit */
46 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS));
47 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CTL_LOWM
#define CTL_LOWM
Definition: usbd_regs.h:50
CTL_SETSPS
#define CTL_SETSPS
Definition: usbd_regs.h:49
void usbd_remote_wakeup_active ( void )

start to remote wakeup

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 119 of file usbd_pwr.c.

120 {
121 resume_mcu();
122
123 #ifdef LPM_ENABLED
124 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ);
125
126 L1_resume = 1U;
127 #else
128 g_remote_wakeup_on = 1U;
129
130 g_ESOF_count = 15U;
131 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ);
132 #endif /* LPM_ENABLED */
133 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
g_remote_wakeup_on
__IO uint8_t g_remote_wakeup_on
Definition: usbd_pwr.c:21
resume_mcu
void resume_mcu(void)
USB wakeup first operation is to wakeup mcu.
Definition: usbd_pwr.c:33
g_ESOF_count
__IO uint8_t g_ESOF_count
Definition: usbd_pwr.c:19
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CTL_L1RSREQ
#define CTL_L1RSREQ
Definition: usbd_regs.h:47
CTL_RSREQ
#define CTL_RSREQ
Definition: usbd_regs.h:48
void usbd_suspend ( void )

set USB device to suspend mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 91 of file usbd_pwr.c.

92 {
93 /* set usb module to suspend and low-power mode */
94 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM);
95
96 #ifdef USBD_LOWPWR_MODE_ENABLE
97
98 /* check wakeup flag is set */
99 if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) {
100 /* enter DEEP_SLEEP mode with LDO in low power mode */
101 pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
102 } else {
103 /* clear wakeup interrupt flag */
104 USBD_REG_SET(USBD_INTF, CLR_WKUPIF);
105
106 /* clear set_suspend flag */
107 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS);
108 }
109
110 #endif /* USBD_LOWPWR_MODE_ENABLE */
111 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CTL_LOWM
#define CTL_LOWM
Definition: usbd_regs.h:50
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
INTF_WKUPIF
#define INTF_WKUPIF
Definition: usbd_regs.h:58
CTL_SETSPS
#define CTL_SETSPS
Definition: usbd_regs.h:49
CLR_WKUPIF
#define CLR_WKUPIF
Definition: usbd_regs.h:141
pmu_to_deepsleepmode
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode.
Definition: gd32f10x_pmu.c:98
PMU_LDO_LOWPOWER
#define PMU_LDO_LOWPOWER
Definition: gd32f10x_pmu.h:60
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_regs.h File Reference

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  • GD32F10x_Firmware_Library_V2.0.0
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  • GD32F10x_usbd_driver
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Macros | Enumerations
usbd_regs.h File Reference

USB device registers. More...

#include "usbd_conf.h"

Go to the source code of this file.

Macros

#define | USBD USBD_BASE
#define | USBD_RAM (APB1_BUS_BASE + 0x00006000U)
#define | USBD_CTL (REG32(USBD + 0x40U))
#define | USBD_INTF (REG32(USBD + 0x44U))
#define | USBD_STAT (REG32(USBD + 0x48U))
#define | USBD_DADDR (REG32(USBD + 0x4CU))
#define | USBD_BADDR (REG32(USBD + 0x50U))
#define | USBD_EPxCS(ep_id) (REG32(USBD + (ep_id) * 4U))
#define | USBD_LPMCS (REG32(USBD + 0x54U))
#define | CTL_STIE BIT(15)
#define | CTL_PMOUIE BIT(14)
#define | CTL_ERRIE BIT(13)
#define | CTL_WKUPIE BIT(12)
#define | CTL_SPSIE BIT(11)
#define | CTL_RSTIE BIT(10)
#define | CTL_SOFIE BIT(9)
#define | CTL_ESOFIE BIT(8)
#define | CTL_L1REQIE BIT(7)
#define | CTL_L1RSREQ BIT(5)
#define | CTL_RSREQ BIT(4)
#define | CTL_SETSPS BIT(3)
#define | CTL_LOWM BIT(2)
#define | CTL_CLOSE BIT(1)
#define | CTL_SETRST BIT(0)
#define | INTF_STIF BIT(15)
#define | INTF_PMOUIF BIT(14)
#define | INTF_ERRIF BIT(13)
#define | INTF_WKUPIF BIT(12)
#define | INTF_SPSIF BIT(11)
#define | INTF_RSTIF BIT(10)
#define | INTF_SOFIF BIT(9)
#define | INTF_ESOFIF BIT(8)
#define | INTF_L1REQ BIT(7)
#define | INTF_DIR BIT(4)
#define | INTF_EPNUM BITS(0, 3)
#define | STAT_RXDP BIT(15)
#define | STAT_RXDM BIT(14)
#define | STAT_LOCK BIT(13)
#define | STAT_SOFLN BITS(11, 12)
#define | STAT_FCNT BITS(0, 10)
#define | DADDR_USBEN BIT(7)
#define | DADDR_USBDAR BITS(0, 6)
#define | EPxCS_RX_ST BIT(15)
#define | EPxCS_RX_DTG BIT(14)
#define | EPxCS_RX_STA BITS(12, 13)
#define | EPxCS_SETUP BIT(11)
#define | EPxCS_CTL BITS(9, 10)
#define | EPxCS_KCTL BIT(8)
#define | EPxCS_TX_ST BIT(7)
#define | EPxCS_TX_DTG BIT(6)
#define | EPxCS_TX_STA BITS(4, 5)
#define | EPxCS_ADDR BITS(0, 3)
#define | LPMCS_BLSTAT BITS(4, 7)
#define | LPMCS_REMWK BIT(3)
#define | LPMCS_LPMACK BIT(1)
#define | LPMCS_LPMEN BIT(0)
#define | EPCS_MASK (EPxCS_RX_ST|EPxCS_SETUP|EPxCS_CTL|EPxCS_KCTL|EPxCS_TX_ST|EPxCS_ADDR)
#define | ENDP_TYPE(regval) (EPxCS_CTL & ((regval) << 9U))
#define | EP_BULK ENDP_TYPE(0U) /* bulk transfers */
#define | EP_CONTROL ENDP_TYPE(1U) /* control transfers */
#define | EP_ISO ENDP_TYPE(2U) /* isochronous transfers */
#define | EP_INTERRUPT ENDP_TYPE(3U) /* interrupt transfers */
#define | EP_CTL_MASK (~EPxCS_CTL & EPCS_MASK)
#define | EPKCTL_MASK (~EPxCS_KCTL & EPCS_MASK)
#define | ENDP_TXSTAT(regval) (EPxCS_TX_STA & ((regval) << 4U))
#define | EPTX_DISABLED ENDP_TXSTAT(0U) /* transmission state is disabled */
#define | EPTX_STALL ENDP_TXSTAT(1U) /* transmission state is STALL */
#define | EPTX_NAK ENDP_TXSTAT(2U) /* transmission state is NAK */
#define | EPTX_VALID ENDP_TXSTAT(3U) /* transmission state is enabled */
#define | EPTX_DTGMASK (EPxCS_TX_STA | EPCS_MASK)
#define | ENDP_RXSTAT(regval) (EPxCS_RX_STA & ((regval) << 12U))
#define | EPRX_DISABLED ENDP_RXSTAT(0U) /* reception state is disabled */
#define | EPRX_STALL ENDP_RXSTAT(1U) /* reception state is STALL */
#define | EPRX_NAK ENDP_RXSTAT(2U) /* reception state is NAK */
#define | EPRX_VALID ENDP_RXSTAT(3U) /* reception state is enabled */
#define | EPRX_DTGMASK (EPxCS_RX_STA | EPCS_MASK)
#define | EPRCNT_BLKSIZ BIT(15) /* reception data block size */
#define | EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */
#define | EPRCNT_CNT BITS(0, 9) /* reception data count */
#define | EPTCNT_CNT BITS(0, 9) /* transmisson data count */
#define | CLR_STIF (~INTF_STIF)
#define | CLR_PMOUIF (~INTF_PMOUIF)
#define | CLR_ERRIF (~INTF_ERRIF)
#define | CLR_WKUPIF (~INTF_WKUPIF)
#define | CLR_SPSIF (~INTF_SPSIF)
#define | CLR_RSTIF (~INTF_RSTIF)
#define | CLR_SOFIF (~INTF_SOFIF)
#define | CLR_ESOFIF (~INTF_ESOFIF)
#define | CLR_L1REQ (~INTF_L1REQ)
#define | BLKSIZE_OFFSET (0x01U)
#define | BLKNUM_OFFSET (0x05U)
#define | RXCNT_OFFSET (0x0AU)
#define | TXCNT_OFFSET (0x0AU)
#define | BLKSIZE32_MASK (0x1fU)
#define | BLKSIZE2_MASK (0x01U)
#define | BLKSIZE32_OFFSETMASK (0x05U)
#define | BLKSIZE2_OFFSETMASK (0x01U)
#define | EP0_OUT ((uint8_t)0x00) /* OUT endpoint 0 address */
#define | EP0_IN ((uint8_t)0x80) /* IN endpoint 0 address */
#define | EP1_OUT ((uint8_t)0x01) /* OUT endpoint 1 address */
#define | EP1_IN ((uint8_t)0x81) /* IN endpoint 1 address */
#define | EP2_OUT ((uint8_t)0x02) /* OUT endpoint 2 address */
#define | EP2_IN ((uint8_t)0x82) /* IN endpoint 2 address */
#define | EP3_OUT ((uint8_t)0x03) /* OUT endpoint 3 address */
#define | EP3_IN ((uint8_t)0x83) /* IN endpoint 3 address */
#define | EP4_OUT ((uint8_t)0x04) /* OUT endpoint 4 address */
#define | EP4_IN ((uint8_t)0x84) /* IN endpoint 4 address */
#define | EP5_OUT ((uint8_t)0x05) /* OUT endpoint 5 address */
#define | EP5_IN ((uint8_t)0x85) /* IN endpoint 5 address */
#define | EP6_OUT ((uint8_t)0x06) /* OUT endpoint 6 address */
#define | EP6_IN ((uint8_t)0x86) /* IN endpoint 6 address */
#define | EP7_OUT ((uint8_t)0x07) /* OUT endpoint 7 address */
#define | EP7_IN ((uint8_t)0x87) /* IN endpoint 7 address */
#define | EP0 ((uint8_t)0) /* endpoint 0 ID */
#define | EP1 ((uint8_t)1) /* endpoint 1 ID */
#define | EP2 ((uint8_t)2) /* endpoint 2 ID */
#define | EP3 ((uint8_t)3) /* endpoint 3 ID */
#define | EP4 ((uint8_t)4) /* endpoint 4 ID */
#define | EP5 ((uint8_t)5) /* endpoint 5 ID */
#define | EP6 ((uint8_t)6) /* endpoint 6 ID */
#define | EP7 ((uint8_t)7) /* endpoint 7 ID */
#define | USBD_REG_SET(reg, regvalue) ((reg) = (uint16_t)(regvalue))
#define | USBD_REG_GET(reg) ((uint16_t)(reg))
#define | _EP_ADDR_SET(ep_num, addr) USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK) | addr)
#define | USBD_ENDP_TX_STATUS_SET(ep_num, state)
#define | USBD_ENDP_RX_STATUS_SET(ep_num, state)
#define | USBD_ENDP_TX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_STA)
#define | USBD_ENDP_RX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_STA)
#define | USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx)
#define | USBD_ENDP_KIND_SET(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), ((USBD_REG_GET(USBD_EPxCS(ep_num)) | EPxCS_KCTL) & EPCS_MASK)))
#define | USBD_ENDP_KIND_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPKCTL_MASK)))
#define | USBD_STATUS_OUT_SET(ep_num) USBD_ENDP_KIND_SET(ep_num)
#define | USBD_STATUS_OUT_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num)
#define | USBD_ENDP_RX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0x7FFFU & (uint16_t)EPCS_MASK))
#define | USBD_ENDP_TX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0xFF7FU & (uint16_t)EPCS_MASK))
#define | USBD_DTG_RX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_RX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK)))
#define | USBD_DTG_TX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_TX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK)))
#define | USBD_DTG_RX_CLEAR(ep_num)
#define | USBD_DTG_TX_CLEAR(ep_num)
#define | USBD_ENDP_DOUBLE_BUF_SET(ep_num) USBD_ENDP_KIND_SET(ep_num)
#define | USBD_ENDP_DOUBLE_BUF_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num)
#define | USBD_SWBUF_TX_TOGGLE(ep_num) USBD_DTG_RX_TOGGLE(ep_num)
#define | USBD_SWBUF_RX_TOGGLE(ep_num) USBD_DTG_TX_TOGGLE(ep_num)

Enumerations

enum dbuf_ep_dir_enum { DBUF_EP_IN, DBUF_EP_OUT, DBUF_EP_ERR }

Detailed Description

USB device registers.

Definition in file usbd_regs.h.

Macro Definition Documentation

#define _EP_ADDR_SET | ( | ep_num,
 |  | addr
 | ) | USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK) | addr)

Definition at line 206 of file usbd_regs.h.

#define BLKNUM_OFFSET (0x05U)

Definition at line 150 of file usbd_regs.h.

#define BLKSIZE2_MASK (0x01U)

Definition at line 156 of file usbd_regs.h.

#define BLKSIZE2_OFFSETMASK (0x01U)

Definition at line 159 of file usbd_regs.h.

#define BLKSIZE32_MASK (0x1fU)

Definition at line 155 of file usbd_regs.h.

#define BLKSIZE32_OFFSETMASK (0x05U)

Definition at line 158 of file usbd_regs.h.

#define BLKSIZE_OFFSET (0x01U)

Definition at line 149 of file usbd_regs.h.

#define CLR_ERRIF (~INTF_ERRIF)

Definition at line 140 of file usbd_regs.h.

#define CLR_ESOFIF (~INTF_ESOFIF)

Definition at line 145 of file usbd_regs.h.

#define CLR_L1REQ (~INTF_L1REQ)

Definition at line 146 of file usbd_regs.h.

#define CLR_PMOUIF (~INTF_PMOUIF)

Definition at line 139 of file usbd_regs.h.

#define CLR_RSTIF (~INTF_RSTIF)

Definition at line 143 of file usbd_regs.h.

#define CLR_SOFIF (~INTF_SOFIF)

Definition at line 144 of file usbd_regs.h.

#define CLR_SPSIF (~INTF_SPSIF)

Definition at line 142 of file usbd_regs.h.

#define CLR_STIF (~INTF_STIF)

Definition at line 138 of file usbd_regs.h.

#define CLR_WKUPIF (~INTF_WKUPIF)

Definition at line 141 of file usbd_regs.h.

#define CTL_CLOSE BIT(1)

goes to close state

Definition at line 51 of file usbd_regs.h.

#define CTL_ERRIE BIT(13)

error interrupt enable mask

Definition at line 40 of file usbd_regs.h.

#define CTL_ESOFIE BIT(8)

expected start of frame interrupt enable mask

Definition at line 45 of file usbd_regs.h.

#define CTL_L1REQIE BIT(7)

LPM L1 state request interrupt enable

Definition at line 46 of file usbd_regs.h.

#define CTL_L1RSREQ BIT(5)

LPM L1 resume request

Definition at line 47 of file usbd_regs.h.

#define CTL_LOWM BIT(2)

low-power mode at suspend state

Definition at line 50 of file usbd_regs.h.

#define CTL_PMOUIE BIT(14)

packet memory overrun/underrun interrupt enable mask

Definition at line 39 of file usbd_regs.h.

#define CTL_RSREQ BIT(4)

resume request

Definition at line 48 of file usbd_regs.h.

#define CTL_RSTIE BIT(10)

reset interrupt enable mask

Definition at line 43 of file usbd_regs.h.

#define CTL_SETRST BIT(0)

set USB reset

Definition at line 52 of file usbd_regs.h.

#define CTL_SETSPS BIT(3)

set suspend state

Definition at line 49 of file usbd_regs.h.

#define CTL_SOFIE BIT(9)

start of frame interrupt enable mask

Definition at line 44 of file usbd_regs.h.

#define CTL_SPSIE BIT(11)

suspend state interrupt enable mask

Definition at line 42 of file usbd_regs.h.

#define CTL_STIE BIT(15)

successful transfer interrupt enable mask

Definition at line 38 of file usbd_regs.h.

#define CTL_WKUPIE BIT(12)

wakeup interrupt enable mask

Definition at line 41 of file usbd_regs.h.

#define DADDR_USBDAR BITS(0, 6)

USB device address

Definition at line 76 of file usbd_regs.h.

#define DADDR_USBEN BIT(7)

USB module enable

Definition at line 75 of file usbd_regs.h.

#define ENDP_RXSTAT ( regval ) (EPxCS_RX_STA & ((regval) << 12U))

Definition at line 122 of file usbd_regs.h.

#define ENDP_TXSTAT ( regval ) (EPxCS_TX_STA & ((regval) << 4U))

Definition at line 113 of file usbd_regs.h.

#define ENDP_TYPE ( regval ) (EPxCS_CTL & ((regval) << 9U))

Definition at line 101 of file usbd_regs.h.

#define EP0 ((uint8_t)0) /* endpoint 0 ID */

Definition at line 189 of file usbd_regs.h.

#define EP0_IN ((uint8_t)0x80) /* IN endpoint 0 address */

Definition at line 172 of file usbd_regs.h.

#define EP0_OUT ((uint8_t)0x00) /* OUT endpoint 0 address */

Definition at line 171 of file usbd_regs.h.

#define EP1 ((uint8_t)1) /* endpoint 1 ID */

Definition at line 190 of file usbd_regs.h.

#define EP1_IN ((uint8_t)0x81) /* IN endpoint 1 address */

Definition at line 174 of file usbd_regs.h.

#define EP1_OUT ((uint8_t)0x01) /* OUT endpoint 1 address */

Definition at line 173 of file usbd_regs.h.

#define EP2 ((uint8_t)2) /* endpoint 2 ID */

Definition at line 191 of file usbd_regs.h.

#define EP2_IN ((uint8_t)0x82) /* IN endpoint 2 address */

Definition at line 176 of file usbd_regs.h.

#define EP2_OUT ((uint8_t)0x02) /* OUT endpoint 2 address */

Definition at line 175 of file usbd_regs.h.

#define EP3 ((uint8_t)3) /* endpoint 3 ID */

Definition at line 192 of file usbd_regs.h.

#define EP3_IN ((uint8_t)0x83) /* IN endpoint 3 address */

Definition at line 178 of file usbd_regs.h.

#define EP3_OUT ((uint8_t)0x03) /* OUT endpoint 3 address */

Definition at line 177 of file usbd_regs.h.

#define EP4 ((uint8_t)4) /* endpoint 4 ID */

Definition at line 193 of file usbd_regs.h.

#define EP4_IN ((uint8_t)0x84) /* IN endpoint 4 address */

Definition at line 180 of file usbd_regs.h.

#define EP4_OUT ((uint8_t)0x04) /* OUT endpoint 4 address */

Definition at line 179 of file usbd_regs.h.

#define EP5 ((uint8_t)5) /* endpoint 5 ID */

Definition at line 194 of file usbd_regs.h.

#define EP5_IN ((uint8_t)0x85) /* IN endpoint 5 address */

Definition at line 182 of file usbd_regs.h.

#define EP5_OUT ((uint8_t)0x05) /* OUT endpoint 5 address */

Definition at line 181 of file usbd_regs.h.

#define EP6 ((uint8_t)6) /* endpoint 6 ID */

Definition at line 195 of file usbd_regs.h.

#define EP6_IN ((uint8_t)0x86) /* IN endpoint 6 address */

Definition at line 184 of file usbd_regs.h.

#define EP6_OUT ((uint8_t)0x06) /* OUT endpoint 6 address */

Definition at line 183 of file usbd_regs.h.

#define EP7 ((uint8_t)7) /* endpoint 7 ID */

Definition at line 196 of file usbd_regs.h.

#define EP7_IN ((uint8_t)0x87) /* IN endpoint 7 address */

Definition at line 186 of file usbd_regs.h.

#define EP7_OUT ((uint8_t)0x07) /* OUT endpoint 7 address */

Definition at line 185 of file usbd_regs.h.

#define EP_BULK ENDP_TYPE(0U) /* bulk transfers */

Definition at line 103 of file usbd_regs.h.

#define EP_CONTROL ENDP_TYPE(1U) /* control transfers */

Definition at line 104 of file usbd_regs.h.

#define EP_CTL_MASK (~EPxCS_CTL & EPCS_MASK)

Definition at line 107 of file usbd_regs.h.

#define EP_INTERRUPT ENDP_TYPE(3U) /* interrupt transfers */

Definition at line 106 of file usbd_regs.h.

#define EP_ISO ENDP_TYPE(2U) /* isochronous transfers */

Definition at line 105 of file usbd_regs.h.

#define EPCS_MASK (EPxCS_RX_ST|EPxCS_SETUP|EPxCS_CTL|EPxCS_KCTL|EPxCS_TX_ST|EPxCS_ADDR)

Definition at line 98 of file usbd_regs.h.

#define EPKCTL_MASK (~EPxCS_KCTL & EPCS_MASK)

Definition at line 110 of file usbd_regs.h.

#define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */

Definition at line 132 of file usbd_regs.h.

#define EPRCNT_BLKSIZ BIT(15) /* reception data block size */

Definition at line 131 of file usbd_regs.h.

#define EPRCNT_CNT BITS(0, 9) /* reception data count */

Definition at line 133 of file usbd_regs.h.

#define EPRX_DISABLED ENDP_RXSTAT(0U) /* reception state is disabled */

Definition at line 124 of file usbd_regs.h.

#define EPRX_DTGMASK (EPxCS_RX_STA | EPCS_MASK)

Definition at line 128 of file usbd_regs.h.

#define EPRX_NAK ENDP_RXSTAT(2U) /* reception state is NAK */

Definition at line 126 of file usbd_regs.h.

#define EPRX_STALL ENDP_RXSTAT(1U) /* reception state is STALL */

Definition at line 125 of file usbd_regs.h.

#define EPRX_VALID ENDP_RXSTAT(3U) /* reception state is enabled */

Definition at line 127 of file usbd_regs.h.

#define EPTCNT_CNT BITS(0, 9) /* transmisson data count */

Definition at line 135 of file usbd_regs.h.

#define EPTX_DISABLED ENDP_TXSTAT(0U) /* transmission state is disabled */

Definition at line 115 of file usbd_regs.h.

#define EPTX_DTGMASK (EPxCS_TX_STA | EPCS_MASK)

Definition at line 119 of file usbd_regs.h.

#define EPTX_NAK ENDP_TXSTAT(2U) /* transmission state is NAK */

Definition at line 117 of file usbd_regs.h.

#define EPTX_STALL ENDP_TXSTAT(1U) /* transmission state is STALL */

Definition at line 116 of file usbd_regs.h.

#define EPTX_VALID ENDP_TXSTAT(3U) /* transmission state is enabled */

Definition at line 118 of file usbd_regs.h.

#define EPxCS_ADDR BITS(0, 3)

endpoint address

Definition at line 88 of file usbd_regs.h.

#define EPxCS_CTL BITS(9, 10)

endpoint type control

Definition at line 83 of file usbd_regs.h.

#define EPxCS_KCTL BIT(8)

endpoint kind control

Definition at line 84 of file usbd_regs.h.

#define EPxCS_RX_DTG BIT(14)

endpoint reception data PID toggle

Definition at line 80 of file usbd_regs.h.

#define EPxCS_RX_ST BIT(15)

endpoint reception successful transferred

Definition at line 79 of file usbd_regs.h.

#define EPxCS_RX_STA BITS(12, 13)

endpoint reception status bits

Definition at line 81 of file usbd_regs.h.

#define EPxCS_SETUP BIT(11)

endpoint setup transaction completed

Definition at line 82 of file usbd_regs.h.

#define EPxCS_TX_DTG BIT(6)

endpoint transmission data toggle

Definition at line 86 of file usbd_regs.h.

#define EPxCS_TX_ST BIT(7)

endpoint transmission successful transfer

Definition at line 85 of file usbd_regs.h.

#define EPxCS_TX_STA BITS(4, 5)

endpoint transmission transfers status bits

Definition at line 87 of file usbd_regs.h.

#define INTF_DIR BIT(4)

direction of transaction (read-only bit)

Definition at line 64 of file usbd_regs.h.

#define INTF_EPNUM BITS(0, 3)

endpoint number (read-only bit)

Definition at line 65 of file usbd_regs.h.

#define INTF_ERRIF BIT(13)

error interrupt flag (clear-only bit)

Definition at line 57 of file usbd_regs.h.

#define INTF_ESOFIF BIT(8)

expected start of frame interrupt flag(clear-only bit)

Definition at line 62 of file usbd_regs.h.

#define INTF_L1REQ BIT(7)

LPM L1 transaction is successfully received and acknowledged

Definition at line 63 of file usbd_regs.h.

#define INTF_PMOUIF BIT(14)

packet memory overrun/underrun interrupt flag (clear-only bit)

Definition at line 56 of file usbd_regs.h.

#define INTF_RSTIF BIT(10)

reset interrupt flag (clear-only bit)

Definition at line 60 of file usbd_regs.h.

#define INTF_SOFIF BIT(9)

start of frame interrupt flag (clear-only bit)

Definition at line 61 of file usbd_regs.h.

#define INTF_SPSIF BIT(11)

suspend state interrupt flag (clear-only bit)

Definition at line 59 of file usbd_regs.h.

#define INTF_STIF BIT(15)

successful transfer interrupt flag (read only bit)

Definition at line 55 of file usbd_regs.h.

#define INTF_WKUPIF BIT(12)

wakeup interrupt flag (clear-only bit)

Definition at line 58 of file usbd_regs.h.

#define LPMCS_BLSTAT BITS(4, 7)

bLinkState value

Definition at line 91 of file usbd_regs.h.

#define LPMCS_LPMACK BIT(1)

LPM token acknowledge enable

Definition at line 93 of file usbd_regs.h.

#define LPMCS_LPMEN BIT(0)

LPM support enable

Definition at line 94 of file usbd_regs.h.

#define LPMCS_REMWK BIT(3)

bRemoteWake value

Definition at line 92 of file usbd_regs.h.

#define RXCNT_OFFSET (0x0AU)

Definition at line 151 of file usbd_regs.h.

#define STAT_FCNT BITS(0, 10)

frame number count

Definition at line 72 of file usbd_regs.h.

#define STAT_LOCK BIT(13)

locked the USB

Definition at line 70 of file usbd_regs.h.

#define STAT_RXDM BIT(14)

data minus line status

Definition at line 69 of file usbd_regs.h.

#define STAT_RXDP BIT(15)

data plus line status

Definition at line 68 of file usbd_regs.h.

#define STAT_SOFLN BITS(11, 12)

SOF lost number

Definition at line 71 of file usbd_regs.h.

#define TXCNT_OFFSET (0x0AU)

Definition at line 153 of file usbd_regs.h.

#define USBD USBD_BASE

Definition at line 19 of file usbd_regs.h.

#define USBD_BADDR (REG32(USBD + 0x50U))

buffer address register

Definition at line 28 of file usbd_regs.h.

#define USBD_CTL (REG32(USBD + 0x40U))

control register

Definition at line 24 of file usbd_regs.h.

#define USBD_DADDR (REG32(USBD + 0x4CU))

device address register

Definition at line 27 of file usbd_regs.h.

#define USBD_DTG_RX_CLEAR ( ep_num )
Value:
do {\
if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_DTG) != 0U) {\
USBD_DTG_RX_TOGGLE(ep_num);\
} else {\
}\
} while(0)
USBD_DTG_RX_TOGGLE
#define USBD_DTG_RX_TOGGLE(ep_num)
Definition: usbd_regs.h:245
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_EPxCS
#define USBD_EPxCS(ep_id)
Definition: usbd_regs.h:31
EPxCS_RX_DTG
#define EPxCS_RX_DTG
Definition: usbd_regs.h:80

Definition at line 249 of file usbd_regs.h.

#define USBD_DTG_RX_TOGGLE ( ep_num ) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_RX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK)))

Definition at line 245 of file usbd_regs.h.

#define USBD_DTG_TX_CLEAR ( ep_num )
Value:
do {\
if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_DTG) != 0U) {\
USBD_DTG_TX_TOGGLE(ep_num);\
} else {\
}\
} while(0)
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_DTG_TX_TOGGLE
#define USBD_DTG_TX_TOGGLE(ep_num)
Definition: usbd_regs.h:246
EPxCS_TX_DTG
#define EPxCS_TX_DTG
Definition: usbd_regs.h:86
USBD_EPxCS
#define USBD_EPxCS(ep_id)
Definition: usbd_regs.h:31

Definition at line 256 of file usbd_regs.h.

#define USBD_DTG_TX_TOGGLE ( ep_num ) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_TX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK)))

Definition at line 246 of file usbd_regs.h.

#define USBD_ENDP_DOUBLE_BUF_CLEAR ( ep_num ) USBD_ENDP_KIND_CLEAR(ep_num)

Definition at line 265 of file usbd_regs.h.

#define USBD_ENDP_DOUBLE_BUF_SET ( ep_num ) USBD_ENDP_KIND_SET(ep_num)

Definition at line 264 of file usbd_regs.h.

#define USBD_ENDP_KIND_CLEAR ( ep_num ) (USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPKCTL_MASK)))

Definition at line 234 of file usbd_regs.h.

#define USBD_ENDP_KIND_SET ( ep_num ) (USBD_REG_SET(USBD_EPxCS(ep_num), ((USBD_REG_GET(USBD_EPxCS(ep_num)) | EPxCS_KCTL) & EPCS_MASK)))

Definition at line 233 of file usbd_regs.h.

#define USBD_ENDP_RX_STAT_CLEAR ( ep_num ) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0x7FFFU & (uint16_t)EPCS_MASK))

Definition at line 241 of file usbd_regs.h.

#define USBD_ENDP_RX_STATUS_GET ( ep_num ) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_STA)

Definition at line 223 of file usbd_regs.h.

#define USBD_ENDP_RX_STATUS_SET | ( | ep_num,
 |  | state
 | ) |
Value:
do {\
register uint16_t _regval; \
_regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPRX_DTGMASK;\
USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \
} while(0)
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
EPRX_DTGMASK
#define EPRX_DTGMASK
Definition: usbd_regs.h:128
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_EPxCS
#define USBD_EPxCS(ep_id)
Definition: usbd_regs.h:31

Definition at line 215 of file usbd_regs.h.

#define USBD_ENDP_RX_TX_STATUS_SET | ( | ep_num,
 |  | state_rx,
 |  | state_tx
 | ) |
Value:
do {\
register uint16_t _regval; \
_regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)(EPRX_DTGMASK | EPxCS_TX_STA) ;\
USBD_REG_SET(USBD_EPxCS(ep_num), (((_regval) ^ (state_rx)) ^ (state_tx))); \
} while(0)
EPxCS_TX_STA
#define EPxCS_TX_STA
Definition: usbd_regs.h:87
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
EPRX_DTGMASK
#define EPRX_DTGMASK
Definition: usbd_regs.h:128
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_EPxCS
#define USBD_EPxCS(ep_id)
Definition: usbd_regs.h:31

Definition at line 226 of file usbd_regs.h.

#define USBD_ENDP_TX_STAT_CLEAR ( ep_num ) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0xFF7FU & (uint16_t)EPCS_MASK))

Definition at line 242 of file usbd_regs.h.

#define USBD_ENDP_TX_STATUS_GET ( ep_num ) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_STA)

Definition at line 222 of file usbd_regs.h.

#define USBD_ENDP_TX_STATUS_SET | ( | ep_num,
 |  | state
 | ) |
Value:
do {\
register uint16_t _regval; \
_regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPTX_DTGMASK;\
USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \
} while(0)
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
EPTX_DTGMASK
#define EPTX_DTGMASK
Definition: usbd_regs.h:119
USBD_EPxCS
#define USBD_EPxCS(ep_id)
Definition: usbd_regs.h:31

Definition at line 209 of file usbd_regs.h.

#define USBD_EPxCS ( ep_id ) (REG32(USBD + (ep_id) * 4U))

endpoint x control and status register address

Definition at line 31 of file usbd_regs.h.

#define USBD_INTF (REG32(USBD + 0x44U))

interrupt flag register

Definition at line 25 of file usbd_regs.h.

#define USBD_LPMCS (REG32(USBD + 0x54U))

USBD LPM control and status register

Definition at line 34 of file usbd_regs.h.

#define USBD_RAM (APB1_BUS_BASE + 0x00006000U)

Definition at line 20 of file usbd_regs.h.

#define USBD_REG_GET ( reg ) ((uint16_t)(reg))

Definition at line 204 of file usbd_regs.h.

#define USBD_REG_SET | ( | reg,
 |  | regvalue
 | ) | ((reg) = (uint16_t)(regvalue))

Definition at line 201 of file usbd_regs.h.

#define USBD_STAT (REG32(USBD + 0x48U))

status register

Definition at line 26 of file usbd_regs.h.

#define USBD_STATUS_OUT_CLEAR ( ep_num ) USBD_ENDP_KIND_CLEAR(ep_num)

Definition at line 238 of file usbd_regs.h.

#define USBD_STATUS_OUT_SET ( ep_num ) USBD_ENDP_KIND_SET(ep_num)

Definition at line 237 of file usbd_regs.h.

#define USBD_SWBUF_RX_TOGGLE ( ep_num ) USBD_DTG_TX_TOGGLE(ep_num)

Definition at line 269 of file usbd_regs.h.

#define USBD_SWBUF_TX_TOGGLE ( ep_num ) USBD_DTG_RX_TOGGLE(ep_num)

Definition at line 268 of file usbd_regs.h.

Enumeration Type Documentation

enum dbuf_ep_dir_enum
Enumerator
DBUF_EP_IN
DBUF_EP_OUT
DBUF_EP_ERR

Definition at line 162 of file usbd_regs.h.

163 {
164 DBUF_EP_IN, /* double buffer IN direction */
165 DBUF_EP_OUT, /* double buffer OUT direction */
166 DBUF_EP_ERR, /* double buffer errer direction */
167 }dbuf_ep_dir_enum;
DBUF_EP_IN
Definition: usbd_regs.h:164
dbuf_ep_dir_enum
dbuf_ep_dir_enum
Definition: usbd_regs.h:162
DBUF_EP_ERR
Definition: usbd_regs.h:166
DBUF_EP_OUT
Definition: usbd_regs.h:165
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_std.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
Data Structures | Macros | Functions
usbd_std.h File Reference
#include "usbd_core.h"
#include <wchar.h>

Go to the source code of this file.

Data Structures

struct | usb_descriptor_header_struct
struct | usb_descriptor_device_struct
struct | usb_descriptor_configuration_struct
struct | usb_descriptor_interface_struct
struct | usb_descriptor_endpoint_struct
struct | usb_descriptor_language_id_struct

Macros

#define | NULL 0U
#define | USB_DEV_QUALIFIER_DESC_LEN 0x0AU /* device qualifier descriptor length */
#define | USB_CFG_DESC_LEN 0x09U /* configuration descriptor length */
#define | USBD_LANGID_STR_IDX 0x00U /* language ID string index */
#define | USBD_MFC_STR_IDX 0x01U /* manufacturer string index */
#define | USBD_PRODUCT_STR_IDX 0x02U /* product string index */
#define | USBD_SERIAL_STR_IDX 0x03U /* serial string index */
#define | USBD_CONFIG_STR_IDX 0x04U /* configuration string index */
#define | USBD_INTERFACE_STR_IDX 0x05U /* interface string index */
#define | USB_STANDARD_REQ 0x00U /* standard request */
#define | USB_CLASS_REQ 0x20U /* device class request */
#define | USB_VENDOR_REQ 0x40U /* vendor request */
#define | USB_REQ_MASK 0x60U /* request type mask */
#define | USB_REQTYPE_DEVICE 0x00U /* request recipient is device */
#define | USB_REQTYPE_INTERFACE 0x01U /* request recipient is interface */
#define | USB_REQTYPE_ENDPOINT 0x02U /* request recipient is endpoint */
#define | USB_REQ_RECIPIENT_MASK 0x1fU /* request recipient mask */
#define | USBREQ_GET_STATUS 0x00U /* Get_Status standard requeset */
#define | USBREQ_CLEAR_FEATURE 0x01U /* Clear_Feature standard requeset */
#define | USBREQ_SET_FEATURE 0x03U /* Set_Feature standard requeset */
#define | USBREQ_SET_ADDRESS 0x05U /* Set_Address standard requeset */
#define | USBREQ_GET_DESCRIPTOR 0x06U /* Get_Descriptor standard requeset */
#define | USBREQ_GET_CONFIGURATION 0x08U /* Get_Configuration standard requeset */
#define | USBREQ_SET_CONFIGURATION 0x09U /* Set_Configuration standard requeset */
#define | USBREQ_GET_INTERFACE 0x0AU /* Get_Interface standard requeset */
#define | USBREQ_SET_INTERFACE 0x0BU /* Set_Interface standard requeset */
#define | USB_DESCTYPE_DEVICE 0x01U /* device descriptor type */
#define | USB_DESCTYPE_CONFIGURATION 0x02U /* configuration descriptor type */
#define | USB_DESCTYPE_STRING 0x03U /* string descriptor type */
#define | USB_DESCTYPE_INTERFACE 0x04U /* interface descriptor type */
#define | USB_DESCTYPE_ENDPOINT 0x05U /* endpoint descriptor type */
#define | USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /* device qualifier descriptor type */
#define | USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /* other speed configuration descriptor type */
#define | USB_DESCTYPE_BOS 0x0FU /* BOS descriptor type */
#define | USB_STATUS_REMOTE_WAKEUP 2U /* USB is in remote wakeup status */
#define | USB_STATUS_SELF_POWERED 1U /* USB is in self powered status */
#define | USB_FEATURE_ENDP_HALT 0U /* USB has endpoint halt feature */
#define | USB_FEATURE_REMOTE_WAKEUP 1U /* USB has endpoint remote wakeup feature */
#define | USB_FEATURE_TEST_MODE 2U /* USB has endpoint test mode feature */
#define | ENG_LANGID 0x0409U /* english language ID */
#define | CHN_LANGID 0x0804U /* chinese language ID */
#define | USB_EPTYPE_MASK 0x03U
#define | USB_DEVICE_DESC_SIZE 0x12U
#define | SWAPBYTE(addr)
#define | LOWBYTE(x) ((uint8_t)((x) & 0x00FFU))
#define | HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))
#define | MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))
#define | WIDE_STRING(string) _WIDE_STRING(string)
#define | _WIDE_STRING(string) L##string
#define | USBD_STRING_DESC(string)

Functions

uint8_t | usbd_setup_transaction (usbd_core_handle_struct *pudev)
USB setup stage processing. More...
uint8_t | usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num)
data out stage processing More...
uint8_t | usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num)
data in stage processing More...
uint8_t | usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB standard device request More...
uint8_t | usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB device class request More...
uint8_t | usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB vendor request More...
void | usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
decode setup data packet More...
void | usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB enumeration error event More...

Macro Definition Documentation

#define _WIDE_STRING ( string ) L##string

Definition at line 89 of file usbd_std.h.

#define CHN_LANGID 0x0804U /* chinese language ID */

Definition at line 71 of file usbd_std.h.

#define ENG_LANGID 0x0409U /* english language ID */

Definition at line 70 of file usbd_std.h.

#define HIGHBYTE ( x ) ((uint8_t)(((x) & 0xFF00U) >> 8U))

Definition at line 82 of file usbd_std.h.

#define IS_NOT_EP0 ( ep_addr ) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))

Definition at line 86 of file usbd_std.h.

#define LOWBYTE ( x ) ((uint8_t)((x) & 0x00FFU))

Definition at line 81 of file usbd_std.h.

#define MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Definition at line 84 of file usbd_std.h.

#define NULL 0U

Definition at line 20 of file usbd_std.h.

#define SWAPBYTE ( addr )
Value:
(((uint16_t)(*((uint8_t *)(addr)))) + \
(uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))

Definition at line 78 of file usbd_std.h.

#define USB_CFG_DESC_LEN 0x09U /* configuration descriptor length */

Definition at line 25 of file usbd_std.h.

#define USB_CLASS_REQ 0x20U /* device class request */

Definition at line 35 of file usbd_std.h.

#define USB_DESCTYPE_BOS 0x0FU /* BOS descriptor type */

Definition at line 61 of file usbd_std.h.

#define USB_DESCTYPE_CONFIGURATION 0x02U /* configuration descriptor type */

Definition at line 55 of file usbd_std.h.

#define USB_DESCTYPE_DEVICE 0x01U /* device descriptor type */

Definition at line 54 of file usbd_std.h.

#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /* device qualifier descriptor type */

Definition at line 59 of file usbd_std.h.

#define USB_DESCTYPE_ENDPOINT 0x05U /* endpoint descriptor type */

Definition at line 58 of file usbd_std.h.

#define USB_DESCTYPE_INTERFACE 0x04U /* interface descriptor type */

Definition at line 57 of file usbd_std.h.

#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /* other speed configuration descriptor type */

Definition at line 60 of file usbd_std.h.

#define USB_DESCTYPE_STRING 0x03U /* string descriptor type */

Definition at line 56 of file usbd_std.h.

#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /* device qualifier descriptor length */

Definition at line 24 of file usbd_std.h.

#define USB_DEVICE_DESC_SIZE 0x12U

Definition at line 75 of file usbd_std.h.

#define USB_EPTYPE_MASK 0x03U

Definition at line 73 of file usbd_std.h.

#define USB_FEATURE_ENDP_HALT 0U /* USB has endpoint halt feature */

Definition at line 66 of file usbd_std.h.

#define USB_FEATURE_REMOTE_WAKEUP 1U /* USB has endpoint remote wakeup feature */

Definition at line 67 of file usbd_std.h.

#define USB_FEATURE_TEST_MODE 2U /* USB has endpoint test mode feature */

Definition at line 68 of file usbd_std.h.

#define USB_REQ_MASK 0x60U /* request type mask */

Definition at line 37 of file usbd_std.h.

#define USB_REQ_RECIPIENT_MASK 0x1fU /* request recipient mask */

Definition at line 42 of file usbd_std.h.

#define USB_REQTYPE_DEVICE 0x00U /* request recipient is device */

Definition at line 39 of file usbd_std.h.

#define USB_REQTYPE_ENDPOINT 0x02U /* request recipient is endpoint */

Definition at line 41 of file usbd_std.h.

#define USB_REQTYPE_INTERFACE 0x01U /* request recipient is interface */

Definition at line 40 of file usbd_std.h.

#define USB_STANDARD_REQ 0x00U /* standard request */

Definition at line 34 of file usbd_std.h.

#define USB_STATUS_REMOTE_WAKEUP 2U /* USB is in remote wakeup status */

Definition at line 63 of file usbd_std.h.

#define USB_STATUS_SELF_POWERED 1U /* USB is in self powered status */

Definition at line 64 of file usbd_std.h.

#define USB_VENDOR_REQ 0x40U /* vendor request */

Definition at line 36 of file usbd_std.h.

#define USBD_CONFIG_STR_IDX 0x04U /* configuration string index */

Definition at line 31 of file usbd_std.h.

#define USBD_INTERFACE_STR_IDX 0x05U /* interface string index */

Definition at line 32 of file usbd_std.h.

#define USBD_LANGID_STR_IDX 0x00U /* language ID string index */

Definition at line 27 of file usbd_std.h.

#define USBD_MFC_STR_IDX 0x01U /* manufacturer string index */

Definition at line 28 of file usbd_std.h.

#define USBD_PRODUCT_STR_IDX 0x02U /* product string index */

Definition at line 29 of file usbd_std.h.

#define USBD_SERIAL_STR_IDX 0x03U /* serial string index */

Definition at line 30 of file usbd_std.h.

#define USBD_STRING_DESC ( string )
Value:
(void *)&(const struct { \
uint8_t _len; \
uint8_t _type; \
wchar_t _data[sizeof(string)]; \
}) { \
sizeof(WIDE_STRING(string)) + 2U - 2U, \
USB_DESCTYPE_STRING, \
WIDE_STRING(string) \
}
WIDE_STRING
#define WIDE_STRING(string)
Definition: usbd_std.h:88
USB_DESCTYPE_STRING
#define USB_DESCTYPE_STRING
Definition: usbd_std.h:56

Definition at line 91 of file usbd_std.h.

#define USBREQ_CLEAR_FEATURE 0x01U /* Clear_Feature standard requeset */

Definition at line 45 of file usbd_std.h.

#define USBREQ_GET_CONFIGURATION 0x08U /* Get_Configuration standard requeset */

Definition at line 49 of file usbd_std.h.

#define USBREQ_GET_DESCRIPTOR 0x06U /* Get_Descriptor standard requeset */

Definition at line 48 of file usbd_std.h.

#define USBREQ_GET_INTERFACE 0x0AU /* Get_Interface standard requeset */

Definition at line 51 of file usbd_std.h.

#define USBREQ_GET_STATUS 0x00U /* Get_Status standard requeset */

Definition at line 44 of file usbd_std.h.

#define USBREQ_SET_ADDRESS 0x05U /* Set_Address standard requeset */

Definition at line 47 of file usbd_std.h.

#define USBREQ_SET_CONFIGURATION 0x09U /* Set_Configuration standard requeset */

Definition at line 50 of file usbd_std.h.

#define USBREQ_SET_FEATURE 0x03U /* Set_Feature standard requeset */

Definition at line 46 of file usbd_std.h.

#define USBREQ_SET_INTERFACE 0x0BU /* Set_Interface standard requeset */

Definition at line 52 of file usbd_std.h.

#define WIDE_STRING ( string ) _WIDE_STRING(string)

Definition at line 88 of file usbd_std.h.

Function Documentation

uint8_t usbd_device_class_request | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB device class request

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device class request
[out] | none
Return values
USB device operation status

Definition at line 235 of file usbd_std.c.

236 {
237 usbd_status_enum ret;
238
239 switch (pudev->status) {
240 case USBD_CONFIGURED:
241 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
242 /* call device class handle function */
243 ret = (usbd_status_enum)(pudev->class_req_handler(pudev, req));
244
245 if ((0U == req->wLength) && (USBD_OK == ret)) {
246 /* no data stage */
247 USBD_CONTRL_STATUS_TX();
248 }
249 } else {
250 usbd_enum_error(pudev, req);
251 }
252 break;
253 default:
254 usbd_enum_error(pudev, req);
255 break;
256 }
257
258 return USBD_OK;
259 }
usb_device_req_struct::wIndex
uint16_t wIndex
Definition: usbd_core.h:120
usb_device_req_struct::wLength
uint16_t wLength
Definition: usbd_core.h:121
USBD_CONTRL_STATUS_TX
#define USBD_CONTRL_STATUS_TX()
Definition: usbd_core.h:33
LOWBYTE
#define LOWBYTE(x)
Definition: usbd_std.h:81
USBD_OK
Definition: usbd_core.h:84
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
USBD_CONFIGURED
Definition: usbd_core.h:76
usbd_enum_error
void usbd_enum_error(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB enumeration error event
Definition: usbd_std.c:832
usbd_core_handle_struct::class_req_handler
usbd_status_enum(* class_req_handler)(void *pudev, usb_device_req_struct *req)
Definition: usbd_core.h:153
usbd_core_handle_struct::status
uint8_t status
Definition: usbd_core.h:129
void usbd_enum_error | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB enumeration error event

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
none

Definition at line 832 of file usbd_std.c.

833 {
834 usbd_ep_stall(pudev, EP0);
835 }
EP0
#define EP0
Definition: usbd_regs.h:189
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
uint8_t usbd_in_transaction | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

data in stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_num | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 155 of file usbd_std.c.

156 {
157 usb_ep_struct *ep = &pudev->in_ep[ep_num];
158
159 if (0U == ep_num) {
160 if (0U != pudev->ctl_count) {
161 if (ep->trs_len > ep->maxpacket) {
162 /* one data packet has been transmited, update trs_len */
163 ep->trs_len -= ep->maxpacket;
164
165 /* continue to transmit remain data */
166 usbd_ep_tx (pudev, EP0_IN, ep->trs_buf, (uint16_t)ep->trs_len);
167
168 usbd_ep_rx (pudev, 0, NULL, 0);
169 } else {
170 #ifndef USB_DFU
171 /* transmit length is maxpacket multiple, so send zero length packet */
172 if ((0U == (ep->trs_len % ep->maxpacket)) && (ep->trs_len < pudev->ctl_count)) {
173 usbd_ep_tx (pudev, EP0_IN, NULL, 0U);
174
175 pudev->ctl_count = 0U;
176
177 usbd_ep_rx (pudev, 0, NULL, 0);
178 } else
179 #endif /* USB_DFU */
180 {
181 ep->trs_len = 0U;
182
183 if (USBD_CONFIGURED == pudev->status) {
184 pudev->class_data_handler(pudev, USBD_TX, EP0);
185 }
186
187 USBD_CONTRL_STATUS_RX();
188
189 pudev->ctl_count = 0U;
190 }
191 }
192 } else {
193 if (0U != g_device_address) {
194 USBD_REG_SET(USBD_DADDR, DADDR_USBEN | g_device_address);
195 g_device_address = 0U;
196 }
197 }
198 } else {
199 ep->trs_len -= ep->trs_count;
200
201 if (0U == ep->trs_len) {
202 if (USBD_CONFIGURED == pudev->status) {
203 pudev->class_data_handler(pudev, USBD_TX, ep_num);
204 }
205 } else {
206 usbd_ep_tx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len);
207 }
208 }
209
210 return USBD_OK;
211 }
EP0_IN
#define EP0_IN
Definition: usbd_regs.h:172
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
DADDR_USBEN
#define DADDR_USBEN
Definition: usbd_regs.h:75
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
EP0
#define EP0
Definition: usbd_regs.h:189
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
usbd_core_handle_struct::ctl_count
uint32_t ctl_count
Definition: usbd_core.h:136
usbd_core_handle_struct::class_data_handler
usbd_status_enum(* class_data_handler)(void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num)
Definition: usbd_core.h:154
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
usb_ep_struct
Definition: usbd_core.h:102
USBD_OK
Definition: usbd_core.h:84
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
USBD_CONTRL_STATUS_RX
#define USBD_CONTRL_STATUS_RX()
Definition: usbd_core.h:39
USBD_DADDR
#define USBD_DADDR
Definition: usbd_regs.h:27
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
NULL
#define NULL
Definition: usbd_std.h:20
USBD_CONFIGURED
Definition: usbd_core.h:76
g_device_address
uint8_t g_device_address
Definition: usbd_std.c:16
usbd_core_handle_struct::status
uint8_t status
Definition: usbd_core.h:129
USBD_TX
Definition: usbd_core.h:67
uint8_t usbd_out_transaction | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

data out stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_num | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 113 of file usbd_std.c.

114 {
115 usb_ep_struct *ep = &pudev->out_ep[ep_num];
116
117 if (0U == ep_num) {
118 if (0U != pudev->ctl_count) {
119 if (ep->trs_len > ep->maxpacket) {
120 /* one data packet has been received, update trs_len */
121 ep->trs_len -= ep->maxpacket;
122
123 /* continue to receive remain data */
124 usbd_ep_rx(pudev, EP0_OUT, ep->trs_buf, (uint16_t)ep->trs_len);
125 } else {
126 if (USBD_CONFIGURED == pudev->status) {
127 /* device class handle */
128 pudev->class_data_handler(pudev, USBD_RX, EP0);
129 }
130
131 /* enter the control transaction status stage */
132 USBD_CONTRL_STATUS_TX();
133
134 pudev->ctl_count = 0U;
135 }
136 } else {
137 /* clear endpoint status_out status */
138 USBD_STATUS_OUT_CLEAR(EP0);
139 }
140 } else {
141 if (USBD_CONFIGURED == pudev->status) {
142 pudev->class_data_handler(pudev, USBD_RX, ep_num);
143 }
144 }
145 return USBD_OK;
146 }
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
EP0
#define EP0
Definition: usbd_regs.h:189
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
USBD_CONTRL_STATUS_TX
#define USBD_CONTRL_STATUS_TX()
Definition: usbd_core.h:33
usbd_core_handle_struct::ctl_count
uint32_t ctl_count
Definition: usbd_core.h:136
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
usbd_core_handle_struct::class_data_handler
usbd_status_enum(* class_data_handler)(void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num)
Definition: usbd_core.h:154
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
usb_ep_struct
Definition: usbd_core.h:102
USBD_OK
Definition: usbd_core.h:84
USBD_CONFIGURED
Definition: usbd_core.h:76
USBD_RX
Definition: usbd_core.h:66
usbd_core_handle_struct::status
uint8_t status
Definition: usbd_core.h:129
USBD_STATUS_OUT_CLEAR
#define USBD_STATUS_OUT_CLEAR(ep_num)
Definition: usbd_regs.h:238
EP0_OUT
#define EP0_OUT
Definition: usbd_regs.h:171
void usbd_setup_request_parse | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

decode setup data packet

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
none

Definition at line 812 of file usbd_std.c.

813 {
814 uint8_t *setup_data = pudev->setup_packet;
815
816 req->bmRequestType = *setup_data;
817 req->bRequest = *(uint8_t *)(setup_data + 1U);
818 req->wValue = SWAPBYTE (setup_data + 2U);
819 req->wIndex = SWAPBYTE (setup_data + 4U);
820 req->wLength = SWAPBYTE (setup_data + 6U);
821
822 pudev->ctl_count = req->wLength;
823 }
usb_device_req_struct::wIndex
uint16_t wIndex
Definition: usbd_core.h:120
usb_device_req_struct::wLength
uint16_t wLength
Definition: usbd_core.h:121
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usbd_core_handle_struct::ctl_count
uint32_t ctl_count
Definition: usbd_core.h:136
usbd_core_handle_struct::setup_packet
uint8_t setup_packet[8]
Definition: usbd_core.h:135
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usbd_core.h:117
usb_device_req_struct::bRequest
uint8_t bRequest
Definition: usbd_core.h:118
usb_device_req_struct::wValue
uint16_t wValue
Definition: usbd_core.h:119
uint8_t usbd_setup_transaction ( usbd_core_handle_struct * pudev )

USB setup stage processing.

Parameters
[in] | pudev | pointer to USB device instance
[out] | none
Return values
USB device operation status

Definition at line 80 of file usbd_std.c.

81 {
82 usb_device_req_struct req;
83
84 usbd_setup_request_parse (pudev, &req);
85
86 switch (req.bmRequestType & USB_REQ_MASK) {
87 /* standard device request */
88 case USB_STANDARD_REQ:
89 usbd_standard_request(pudev, &req);
90 break;
91 /* device class request */
92 case USB_CLASS_REQ:
93 usbd_device_class_request(pudev, &req);
94 break;
95 /* vendor defined request */
96 case USB_VENDOR_REQ:
97 usbd_vendor_request(pudev, &req);
98 break;
99 default:
100 usbd_ep_stall(pudev, 0x00U);
101 break;
102 }
103 return USBD_OK;
104 }
usbd_standard_request
uint8_t usbd_standard_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB standard device request
Definition: usbd_std.c:220
USB_VENDOR_REQ
#define USB_VENDOR_REQ
Definition: usbd_std.h:36
USB_CLASS_REQ
#define USB_CLASS_REQ
Definition: usbd_std.h:35
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usb_device_req_struct
Definition: usbd_core.h:115
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usbd_core.h:117
usbd_device_class_request
uint8_t usbd_device_class_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB device class request
Definition: usbd_std.c:235
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
USBD_OK
Definition: usbd_core.h:84
USB_REQ_MASK
#define USB_REQ_MASK
Definition: usbd_std.h:37
usbd_vendor_request
uint8_t usbd_vendor_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB vendor request
Definition: usbd_std.c:268
usbd_setup_request_parse
void usbd_setup_request_parse(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
decode setup data packet
Definition: usbd_std.c:812
uint8_t usbd_standard_request | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB standard device request

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
USB device operation status

Definition at line 220 of file usbd_std.c.

221 {
222 /* call device request handle function */
223 (*standard_device_request[req->bRequest])(pudev, req);
224
225 return USBD_OK;
226 }
USBD_OK
Definition: usbd_core.h:84
usb_device_req_struct::bRequest
uint8_t bRequest
Definition: usbd_core.h:118
uint8_t usbd_vendor_request | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB vendor request

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB vendor request
[out] | none
Return values
USB device operation status

Definition at line 268 of file usbd_std.c.

269 {
270 /* added by user */
271
272 return USBD_OK;
273 }
USBD_OK
Definition: usbd_core.h:84
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Source Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Source
Source Directory Reference

Files

file | usbd_core.c [code]
file | usbd_int.c [code]
file | usbd_pwr.c [code]
USB device power management driver.
file | usbd_std.c [code]


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Source/usbd_core.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Source
Functions | Variables
usbd_core.c File Reference
#include "usbd_core.h"
#include "usbd_std.h"

Go to the source code of this file.

Functions

void | usbd_core_init (usbd_core_handle_struct *pudev)
device core register initialization More...
void | user_buffer_free (uint8_t ep_num, uint8_t dir)
free buffer used from application by toggling the SW_BUF byte More...
void | usbd_core_deinit (void)
device core register configure when stop device More...
void | usbd_ep_init (usbd_core_handle_struct *pudev, void *ep_desc)
endpoint initialization More...
void | usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr)
configure the endpoint when it is disabled More...
void | usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data More...
void | usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data More...
void | usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status More...
void | usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status More...
uint8_t | usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr)
get the endpoint status More...
void | usbd_ep_data_write (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
write datas from user fifo to USBRAM More...
void | usbd_ep_data_read (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
read datas from USBRAM to user fifo More...
uint16_t | usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num)
get the received data length More...

Variables

uint32_t | g_interrupt_mask = 0U
uint32_t | g_free_buf_addr = ENDP_BUF_ADDR
usbd_ep_buf_struct * pbuf_reg = (usbd_ep_buf_struct *)USBD_RAM

Function Documentation

void usbd_core_deinit ( void )

device core register configure when stop device

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 81 of file usbd_core.c.

82 {
83 /* disable all interrupts and set USB reset */
84 USBD_REG_SET(USBD_CTL, CTL_SETRST);
85
86 /* clear all interrupt flags */
87 USBD_REG_SET(USBD_INTF, 0U);
88
89 /* close device */
90 USBD_REG_SET(USBD_CTL, CTL_SETRST | CTL_CLOSE);
91 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
CTL_SETRST
#define CTL_SETRST
Definition: usbd_regs.h:52
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CTL_CLOSE
#define CTL_CLOSE
Definition: usbd_regs.h:51
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
void usbd_core_init ( usbd_core_handle_struct * pudev )

device core register initialization

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 27 of file usbd_core.c.

28 {
29 /* disable remote wakeup feature */
30 pudev->remote_wakeup = 0U;
31
32 /* just reset the CLOSE bit */
33 USBD_REG_SET(USBD_CTL, CTL_SETRST);
34
35 /* may be need wait some time(tSTARTUP) ... */
36
37 /* clear SETRST bit in USBD_CTL register */
38 USBD_REG_SET(USBD_CTL, 0U);
39
40 /* clear all pending interrupts */
41 USBD_REG_SET(USBD_INTF, 0U);
42
43 /* set allocation buffer address */
44 USBD_REG_SET(USBD_BADDR, BUFFER_ADDRESS & 0xFFF8U);
45
46 g_interrupt_mask = IER_MASK;
47
48 #ifdef LPM_ENABLED
49 /* enable L1REQ interrupt */
50 USBD_REG_SET(USBD_LPMCS, LPMCS_LPMACK | LPMCS_LPMEN);
51 #endif /* LPM_ENABLED */
52
53 /* enable all interrupts mask bits */
54 USBD_REG_SET(USBD_CTL, g_interrupt_mask);
55 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
g_interrupt_mask
uint32_t g_interrupt_mask
Definition: usbd_core.c:16
CTL_SETRST
#define CTL_SETRST
Definition: usbd_regs.h:52
USBD_LPMCS
#define USBD_LPMCS
Definition: usbd_regs.h:34
LPMCS_LPMACK
#define LPMCS_LPMACK
Definition: usbd_regs.h:93
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
usbd_core_handle_struct::remote_wakeup
uint8_t remote_wakeup
Definition: usbd_core.h:131
USBD_BADDR
#define USBD_BADDR
Definition: usbd_regs.h:28
IER_MASK
#define IER_MASK
Definition: usbd_core.h:20
LPMCS_LPMEN
#define LPMCS_LPMEN
Definition: usbd_regs.h:94
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
void usbd_ep_clear_stall | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

clear endpoint stalled status

Parameters
[in] | pudev | pointer to usb core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[out] | none
Return values
none

Definition at line 297 of file usbd_core.c.

298 {
299 uint8_t ep_num = ep_addr & 0x7FU;
300 usb_ep_struct *ep;
301
302 if (ep_addr >> 7U) {
303 ep = &pudev->in_ep[ep_num];
304
305 /* clear endpoint data toggle bit */
306 USBD_DTG_TX_CLEAR(ep_num);
307
308 /* clear endpoint stall status */
309 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID);
310 } else {
311 ep = &pudev->out_ep[ep_num];
312
313 /* clear endpoint data toggle bit */
314 USBD_DTG_RX_CLEAR(ep_num);
315
316 /* clear endpoint stall status */
317 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID);
318 }
319
320 ep->stall = 0U;
321 }
EPRX_VALID
#define EPRX_VALID
Definition: usbd_regs.h:127
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
usb_ep_struct
Definition: usbd_core.h:102
EPTX_VALID
#define EPTX_VALID
Definition: usbd_regs.h:118
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
usb_ep_struct::stall
uint8_t stall
Definition: usbd_core.h:105
USBD_DTG_RX_CLEAR
#define USBD_DTG_RX_CLEAR(ep_num)
Definition: usbd_regs.h:249
USBD_DTG_TX_CLEAR
#define USBD_DTG_TX_CLEAR(ep_num)
Definition: usbd_regs.h:256
void usbd_ep_data_read | ( | uint8_t * | user_fifo,
 |  | uint16_t | usbram_addr,
 |  | uint16_t | bytes
 | ) |  |

read datas from USBRAM to user fifo

Parameters
[in] | user_fifo | pointer to user fifo
[in] | usbram_addr | the allocation buffer address of the endpoint
[in] | bytes | the bytes count of the read datas
[out] | none
Return values
none

Definition at line 369 of file usbd_core.c.

370 {
371 uint32_t n;
372 uint32_t *read_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM));
373
374 for (n = 0U; n < (bytes + 1U) / 2U; n++) {
375 *((__packed uint16_t*)user_fifo) = (uint16_t)*read_addr++;
376 user_fifo += 2U;
377 }
378 }
USBD_RAM
#define USBD_RAM
Definition: usbd_regs.h:20
void usbd_ep_data_write | ( | uint8_t * | user_fifo,
 |  | uint16_t | usbram_addr,
 |  | uint16_t | bytes
 | ) |  |

write datas from user fifo to USBRAM

Parameters
[in] | user_fifo | pointer to user fifo
[in] | usbram_addr | the allocation buffer address of the endpoint
[in] | bytes | the bytes count of the write datas
[out] | none
Return values
none

Definition at line 350 of file usbd_core.c.

351 {
352 uint32_t n;
353 uint32_t *write_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM));
354
355 for (n = 0U; n < (bytes + 1U) / 2U; n++) {
356 *write_addr++ = *((__packed uint16_t*)user_fifo);
357 user_fifo += 2U;
358 }
359 }
USBD_RAM
#define USBD_RAM
Definition: usbd_regs.h:20
void usbd_ep_deinit | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

configure the endpoint when it is disabled

Parameters
[in] | pudev | pointer to USB core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[out] | none
Return values
none

Definition at line 173 of file usbd_core.c.

174 {
175 uint8_t ep_num = ep_addr & 0x7F;
176
177 if (ep_addr >> 7) {
178 USBD_DTG_TX_CLEAR(ep_num);
179
180 /* configure the endpoint status as DISABLED */
181 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_DISABLED);
182 } else {
183 USBD_DTG_RX_CLEAR(ep_num);
184
185 /* configure the endpoint status as DISABLED */
186 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED);
187 }
188 }
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
EPRX_DISABLED
#define EPRX_DISABLED
Definition: usbd_regs.h:124
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
EPTX_DISABLED
#define EPTX_DISABLED
Definition: usbd_regs.h:115
USBD_DTG_RX_CLEAR
#define USBD_DTG_RX_CLEAR(ep_num)
Definition: usbd_regs.h:249
USBD_DTG_TX_CLEAR
#define USBD_DTG_TX_CLEAR(ep_num)
Definition: usbd_regs.h:256
void usbd_ep_init | ( | usbd_core_handle_struct * | pudev,
 |  | void * | ep_desc
 | ) |  |

endpoint initialization

Parameters
[in] | pudev | pointer to USB core instance
[in] | pep_desc | pointer to endpoint descriptor
[out] | none
Return values
none

Definition at line 100 of file usbd_core.c.

101 {
102 usb_ep_struct *ep;
103 uint8_t ep_num = ((usb_descriptor_endpoint_struct *)ep_desc)->bEndpointAddress & 0x0FU;
104 uint32_t reg_value = ((usb_descriptor_endpoint_struct *)ep_desc)->wMaxPacketSize;
105
106 if (((usb_descriptor_endpoint_struct *)ep_desc)->bEndpointAddress >> 7U) {
107 ep = &pudev->in_ep[ep_num];
108
109 ep->maxpacket = reg_value;
110
111 /* set the endpoint transmit buffer address */
112 (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr;
113
114 reg_value = (reg_value + 1U) & ~1U;
115
116 /* configure the endpoint status as NAK status */
117 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK);
118 } else {
119 ep = &pudev->out_ep[ep_num];
120
121 ep->maxpacket = reg_value;
122
123 /* set the endpoint receive buffer address */
124 (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr;
125
126 if (reg_value > 62U) {
127 reg_value = (reg_value + 31U) & ~31U;
128 (pbuf_reg + ep_num)->rx_count = ((reg_value << 5U) - 1U) | 0x8000U;
129 } else {
130 reg_value = (reg_value + 1U) & ~1U;
131 (pbuf_reg + ep_num)->rx_count = reg_value << 9U;
132 }
133
134 /* configure the endpoint status as NAK status */
135 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_NAK);
136 }
137
138 g_free_buf_addr += reg_value;
139
140 /* set the endpoint type */
141 switch (((usb_descriptor_endpoint_struct *)ep_desc)->bmAttributes & USB_EPTYPE_MASK) {
142 case ENDP_CONTROL:
143 reg_value = EP_CONTROL;
144 break;
145 case ENDP_BULK:
146 reg_value = EP_BULK;
147 break;
148 case ENDP_INT:
149 reg_value = EP_INTERRUPT;
150 break;
151 case ENDP_ISOC:
152 reg_value = EP_ISO;
153 break;
154 default:
155 break;
156 }
157
158 USBD_REG_SET(USBD_EPxCS(ep_num), reg_value | ep_num);
159
160 ep->stall = 0;
161 }
EP_ISO
#define EP_ISO
Definition: usbd_regs.h:105
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
ENDP_INT
Definition: usbd_core.h:53
ENDP_ISOC
Definition: usbd_core.h:51
EPRX_NAK
#define EPRX_NAK
Definition: usbd_regs.h:126
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
EP_CONTROL
#define EP_CONTROL
Definition: usbd_regs.h:104
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
usb_ep_struct
Definition: usbd_core.h:102
EP_BULK
#define EP_BULK
Definition: usbd_regs.h:103
ENDP_BULK
Definition: usbd_core.h:52
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
ENDP_CONTROL
Definition: usbd_core.h:50
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
usb_ep_struct::stall
uint8_t stall
Definition: usbd_core.h:105
USBD_EPxCS
#define USBD_EPxCS(ep_id)
Definition: usbd_regs.h:31
pbuf_reg
usbd_ep_buf_struct * pbuf_reg
Definition: usbd_core.c:19
EP_INTERRUPT
#define EP_INTERRUPT
Definition: usbd_regs.h:106
g_free_buf_addr
uint32_t g_free_buf_addr
Definition: usbd_core.c:17
USB_EPTYPE_MASK
#define USB_EPTYPE_MASK
Definition: usbd_std.h:73
EPTX_NAK
#define EPTX_NAK
Definition: usbd_regs.h:117
void usbd_ep_rx | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint16_t | buf_len
 | ) |  |

endpoint prepare to receive data

Parameters
[in] | pudev | pointer to usb core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[in] | pbuf | user buffer address pointer
[in] | buf_len | buffer length
[out] | none
Return values
none

Definition at line 202 of file usbd_core.c.

203 {
204 usb_ep_struct *ep;
205 uint8_t ep_num = ep_addr & 0x7FU;
206
207 ep = &pudev->out_ep[ep_num];
208
209 /* configure the transaction level parameters */
210 ep->trs_buf = pbuf;
211 ep->trs_len = buf_len;
212
213 /* enable endpoint to receive */
214 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID);
215 }
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
EPRX_VALID
#define EPRX_VALID
Definition: usbd_regs.h:127
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
usb_ep_struct
Definition: usbd_core.h:102
void usbd_ep_stall | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

set an endpoint to STALL status

Parameters
[in] | pudev | pointer to usb core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[out] | none
Return values
none

Definition at line 264 of file usbd_core.c.

265 {
266 uint8_t ep_num = ep_addr & 0x7FU;
267 usb_ep_struct *ep;
268
269 if (ep_addr >> 7U) {
270 ep = &pudev->in_ep[ep_num];
271
272 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_STALL);
273 } else {
274 ep = &pudev->out_ep[ep_num];
275
276 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_STALL);
277 }
278
279 ep->stall = 1U;
280
281 if (0U == ep_num) {
282 /* control endpoint need to be stalled in two directions */
283 USBD_ENDP_RX_TX_STATUS_SET(ep_num, EPRX_STALL, EPTX_STALL);
284 }
285 }
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
USBD_ENDP_RX_TX_STATUS_SET
#define USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx)
Definition: usbd_regs.h:226
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
usb_ep_struct
Definition: usbd_core.h:102
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
EPTX_STALL
#define EPTX_STALL
Definition: usbd_regs.h:116
usb_ep_struct::stall
uint8_t stall
Definition: usbd_core.h:105
EPRX_STALL
#define EPRX_STALL
Definition: usbd_regs.h:125
uint8_t usbd_ep_status_get | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

get the endpoint status

Parameters
[in] | pudev | pointer to usb core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[out] | none
Return values
endpoint status

Definition at line 333 of file usbd_core.c.

334 {
335 if (ep_addr >> 7U) {
336 return (uint8_t)USBD_ENDP_TX_STATUS_GET((ep_addr & 0x7FU));
337 } else {
338 return (uint8_t)USBD_ENDP_RX_STATUS_GET(ep_addr);
339 }
340 }
USBD_ENDP_RX_STATUS_GET
#define USBD_ENDP_RX_STATUS_GET(ep_num)
Definition: usbd_regs.h:223
USBD_ENDP_TX_STATUS_GET
#define USBD_ENDP_TX_STATUS_GET(ep_num)
Definition: usbd_regs.h:222
void usbd_ep_tx | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint16_t | buf_len
 | ) |  |

endpoint prepare to transmit data

Parameters
[in] | pudev | pointer to USB core instance
[in] | ep_addr | endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0)
[in] | pbuf | transmit buffer address pointer
[in] | buf_len | buffer length
[out] | none
Return values
none

Definition at line 229 of file usbd_core.c.

230 {
231 __IO uint32_t len = 0U;
232 uint8_t ep_num = ep_addr & 0x7FU;
233 usb_ep_struct *ep = &pudev->in_ep[ep_num];
234
235 /* configure the transaction level parameters */
236 ep->trs_buf = pbuf;
237 ep->trs_len = buf_len;
238 ep->trs_count = 0U;
239
240 /* transmit length is more than one packet */
241 if (ep->trs_len > ep->maxpacket) {
242 len = ep->maxpacket;
243 } else {
244 len = ep->trs_len;
245 }
246
247 usbd_ep_data_write(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, (uint16_t)len);
248 (pbuf_reg + ep_num)->tx_count = (uint16_t)len;
249
250 /* enable endpoint to transmit */
251 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID);
252 }
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
usb_ep_struct
Definition: usbd_core.h:102
EPTX_VALID
#define EPTX_VALID
Definition: usbd_regs.h:118
usbd_ep_data_write
void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
write datas from user fifo to USBRAM
Definition: usbd_core.c:350
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
pbuf_reg
usbd_ep_buf_struct * pbuf_reg
Definition: usbd_core.c:19
uint16_t usbd_rx_count_get | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

get the received data length

Parameters
[in] | pudev | pointer to USB core instance
[in] | ep_num | endpoint identifier which is in (0..7)
[out] | none
Return values
received data length

Definition at line 387 of file usbd_core.c.

388 {
389 return (uint16_t)pudev->out_ep[ep_num].trs_count;
390 }
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
void user_buffer_free | ( | uint8_t | ep_num,
 |  | uint8_t | dir
 | ) |  |

free buffer used from application by toggling the SW_BUF byte

Parameters
[in] | ep_num | endpoint identifier (0..7)
[in] | dir | endpoint direction which can be OUT(0) or IN(1)
[out] | none
Return values
None

Definition at line 64 of file usbd_core.c.

65 {
66 if (DBUF_EP_OUT == dir) {
67 USBD_SWBUF_RX_TOGGLE(ep_num);
68 } else if (DBUF_EP_IN == dir) {
69 USBD_SWBUF_TX_TOGGLE(ep_num);
70 } else {
71 /* no operation */
72 }
73 }
DBUF_EP_IN
Definition: usbd_regs.h:164
USBD_SWBUF_TX_TOGGLE
#define USBD_SWBUF_TX_TOGGLE(ep_num)
Definition: usbd_regs.h:268
USBD_SWBUF_RX_TOGGLE
#define USBD_SWBUF_RX_TOGGLE(ep_num)
Definition: usbd_regs.h:269
DBUF_EP_OUT
Definition: usbd_regs.h:165

Variable Documentation

uint32_t g_free_buf_addr = ENDP_BUF_ADDR

Definition at line 17 of file usbd_core.c.

uint32_t g_interrupt_mask = 0U

Definition at line 16 of file usbd_core.c.

usbd_ep_buf_struct* pbuf_reg = (usbd_ep_buf_struct *)USBD_RAM

Definition at line 19 of file usbd_core.c.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Source/usbd_int.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Source
Functions | Variables
usbd_int.c File Reference
#include "usbd_int.h"

Go to the source code of this file.

Functions

void usbd_isr (void)
USB interrupt events service routine. More...

Variables

uint32_t | g_interrupt_mask
__IO uint8_t | g_suspend_enabled
__IO uint8_t | g_remote_wakeup_on
__IO uint8_t | g_ESOF_count

Function Documentation

void usbd_isr ( void )

USB interrupt events service routine.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 39 of file usbd_int.c.

40 {
41 __IO uint16_t interrupt_flag = 0U;
42 __IO uint16_t ctlr = 0U;
43
44 interrupt_flag = USBD_REG_GET(USBD_INTF);
45
46 if (g_interrupt_mask & INTF_STIF & interrupt_flag) {
47 /* the endpoint successful transfer interrupt service */
48 usbd_intf_lpst(&usb_device_dev);
49 }
50
51 if (g_interrupt_mask & INTF_WKUPIF & interrupt_flag) {
52 /* clear wakeup interrupt flag in INTF */
53 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_WKUPIF);
54
55 /* USB wakeup interrupt handle */
56 usbd_intf_wakeup(&usb_device_dev);
57
58 #ifdef LPM_ENABLED
59 /* clear L1 remote wakeup flag */
60 L1_remote_wakeup = 0;
61 #endif /* LPM_ENABLED */
62 }
63
64 if (g_interrupt_mask & INTF_SPSIF & interrupt_flag) {
65 if(!(USBD_REG_GET(USBD_CTL) & CTL_RSREQ)) {
66 /* process library core layer suspend routine*/
67 usbd_intf_suspend(&usb_device_dev);
68
69 /* clear of suspend interrupt flag bit must be done after setting of CTLR_SETSPS */
70 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SPSIF);
71 }
72 }
73
74 if (g_interrupt_mask & INTF_SOFIF & interrupt_flag) {
75 /* clear SOF interrupt flag in INTF */
76 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SOFIF);
77
78 /* USB SOF interrupt handle */
79 usbd_intf_sof(&usb_device_dev);
80 }
81
82 if (g_interrupt_mask & INTF_ESOFIF & interrupt_flag) {
83 /* clear ESOF interrupt flag in INTF */
84 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_ESOFIF);
85
86 /* USB ESOF interrupt handle */
87 usbd_intf_esof(&usb_device_dev);
88 }
89
90 if (g_interrupt_mask & INTF_RSTIF & interrupt_flag) {
91 /* clear reset interrupt flag in INTF */
92 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_RSTIF);
93
94 /* USB reset interrupt handle */
95 usbd_intf_reset(&usb_device_dev);
96 }
97
98 #ifdef LPM_ENABLED
99 if (g_interrupt_mask & INTF_L1REQ & interrupt_flag) {
100 /* clear L1 ST bit in LPM INTF */
101 USBD_REG_SET(USBD_INTF, CLR_L1REQ);
102
103 /* read BESL field from subendpoint0 register which coressponds to HIRD parameter in LPM spec */
104 besl = (USBD_REG_GET(USBD_LPMCS) & LPMCS_BLSTAT) >> 4;
105
106 /* read BREMOTEWAKE bit from subendpoint0 register which corresponding to bRemoteWake bit in LPM request */
107 L1_remote_wakeup = (USBD_REG_GET(USBD_LPMCS) & LPMCS_REMWK) >> 8;
108
109 /* process USB device core layer suspend routine */
110 /* enter USB model in suspend and system in low power mode (DEEP_SLEEP mode) */
111 usbd_intf_suspend(&usb_device_dev);
112 }
113 #endif /* LPM_ENABLED */
114 }
INTF_STIF
#define INTF_STIF
Definition: usbd_regs.h:55
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
USBD_LPMCS
#define USBD_LPMCS
Definition: usbd_regs.h:34
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
INTF_L1REQ
#define INTF_L1REQ
Definition: usbd_regs.h:63
LPMCS_BLSTAT
#define LPMCS_BLSTAT
Definition: usbd_regs.h:91
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CLR_SPSIF
#define CLR_SPSIF
Definition: usbd_regs.h:142
INTF_SOFIF
#define INTF_SOFIF
Definition: usbd_regs.h:61
CLR_ESOFIF
#define CLR_ESOFIF
Definition: usbd_regs.h:145
g_interrupt_mask
uint32_t g_interrupt_mask
Definition: usbd_core.c:16
CLR_SOFIF
#define CLR_SOFIF
Definition: usbd_regs.h:144
LPMCS_REMWK
#define LPMCS_REMWK
Definition: usbd_regs.h:92
CLR_L1REQ
#define CLR_L1REQ
Definition: usbd_regs.h:146
INTF_RSTIF
#define INTF_RSTIF
Definition: usbd_regs.h:60
INTF_ESOFIF
#define INTF_ESOFIF
Definition: usbd_regs.h:62
INTF_SPSIF
#define INTF_SPSIF
Definition: usbd_regs.h:59
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
CTL_RSREQ
#define CTL_RSREQ
Definition: usbd_regs.h:48
INTF_WKUPIF
#define INTF_WKUPIF
Definition: usbd_regs.h:58
CLR_WKUPIF
#define CLR_WKUPIF
Definition: usbd_regs.h:141
CLR_RSTIF
#define CLR_RSTIF
Definition: usbd_regs.h:143
usb_device_dev
usbd_core_handle_struct usb_device_dev

Variable Documentation

__IO uint8_t g_ESOF_count

Definition at line 19 of file usbd_pwr.c.

uint32_t g_interrupt_mask

Definition at line 16 of file usbd_core.c.

__IO uint8_t g_remote_wakeup_on

Definition at line 21 of file usbd_pwr.c.

__IO uint8_t g_suspend_enabled

Definition at line 20 of file usbd_pwr.c.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Source/usbd_pwr.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Source
Functions | Variables
usbd_pwr.c File Reference

USB device power management driver. More...

#include "usbd_pwr.h"

Go to the source code of this file.

Functions

void | resume_mcu (void)
USB wakeup first operation is to wakeup mcu. More...
void | usbd_suspend (void)
set USB device to suspend mode More...
void | usbd_remote_wakeup_active (void)
start to remote wakeup More...

Variables

__IO uint8_t | g_ESOF_count = 0U
__IO uint8_t | g_suspend_enabled = 1U
__IO uint8_t | g_remote_wakeup_on = 0U

Detailed Description

USB device power management driver.

Definition in file usbd_pwr.c.

Function Documentation

void resume_mcu ( void )

USB wakeup first operation is to wakeup mcu.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 33 of file usbd_pwr.c.

34 {
35 /* clear low_power mode bit in USBD_CTL */
36 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM));
37
38 #ifdef USBD_LOWPWR_MODE_ENABLE
39
40 /* restore normal operations */
41 lowpower_mode_exit();
42
43 #endif /* USBD_LOWPWR_MODE_ENABLE */
44
45 /* clear SETSPS bit */
46 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS));
47 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CTL_LOWM
#define CTL_LOWM
Definition: usbd_regs.h:50
CTL_SETSPS
#define CTL_SETSPS
Definition: usbd_regs.h:49
void usbd_remote_wakeup_active ( void )

start to remote wakeup

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 119 of file usbd_pwr.c.

120 {
121 resume_mcu();
122
123 #ifdef LPM_ENABLED
124 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ);
125
126 L1_resume = 1U;
127 #else
128 g_remote_wakeup_on = 1U;
129
130 g_ESOF_count = 15U;
131 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ);
132 #endif /* LPM_ENABLED */
133 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
g_remote_wakeup_on
__IO uint8_t g_remote_wakeup_on
Definition: usbd_pwr.c:21
resume_mcu
void resume_mcu(void)
USB wakeup first operation is to wakeup mcu.
Definition: usbd_pwr.c:33
g_ESOF_count
__IO uint8_t g_ESOF_count
Definition: usbd_pwr.c:19
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CTL_L1RSREQ
#define CTL_L1RSREQ
Definition: usbd_regs.h:47
CTL_RSREQ
#define CTL_RSREQ
Definition: usbd_regs.h:48
void usbd_suspend ( void )

set USB device to suspend mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 91 of file usbd_pwr.c.

92 {
93 /* set usb module to suspend and low-power mode */
94 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM);
95
96 #ifdef USBD_LOWPWR_MODE_ENABLE
97
98 /* check wakeup flag is set */
99 if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) {
100 /* enter DEEP_SLEEP mode with LDO in low power mode */
101 pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
102 } else {
103 /* clear wakeup interrupt flag */
104 USBD_REG_SET(USBD_INTF, CLR_WKUPIF);
105
106 /* clear set_suspend flag */
107 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS);
108 }
109
110 #endif /* USBD_LOWPWR_MODE_ENABLE */
111 }
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
CTL_LOWM
#define CTL_LOWM
Definition: usbd_regs.h:50
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
INTF_WKUPIF
#define INTF_WKUPIF
Definition: usbd_regs.h:58
CTL_SETSPS
#define CTL_SETSPS
Definition: usbd_regs.h:49
CLR_WKUPIF
#define CLR_WKUPIF
Definition: usbd_regs.h:141
pmu_to_deepsleepmode
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode.
Definition: gd32f10x_pmu.c:98
PMU_LDO_LOWPOWER
#define PMU_LDO_LOWPOWER
Definition: gd32f10x_pmu.h:60

Variable Documentation

__IO uint8_t g_ESOF_count = 0U

Definition at line 19 of file usbd_pwr.c.

__IO uint8_t g_remote_wakeup_on = 0U

Definition at line 21 of file usbd_pwr.c.

__IO uint8_t g_suspend_enabled = 1U

Definition at line 20 of file usbd_pwr.c.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Source/usbd_std.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Source
Functions | Variables
usbd_std.c File Reference
#include "usbd_std.h"

Go to the source code of this file.

Functions

uint8_t | usbd_setup_transaction (usbd_core_handle_struct *pudev)
USB setup stage processing. More...
uint8_t | usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num)
data out stage processing More...
uint8_t | usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num)
data in stage processing More...
uint8_t | usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB standard device request More...
uint8_t | usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB device class request More...
uint8_t | usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB vendor request More...
void | usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
decode setup data packet More...
void | usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB enumeration error event More...

Variables

uint8_t g_device_address = 0U

Function Documentation

uint8_t usbd_device_class_request | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB device class request

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device class request
[out] | none
Return values
USB device operation status

Definition at line 235 of file usbd_std.c.

236 {
237 usbd_status_enum ret;
238
239 switch (pudev->status) {
240 case USBD_CONFIGURED:
241 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
242 /* call device class handle function */
243 ret = (usbd_status_enum)(pudev->class_req_handler(pudev, req));
244
245 if ((0U == req->wLength) && (USBD_OK == ret)) {
246 /* no data stage */
247 USBD_CONTRL_STATUS_TX();
248 }
249 } else {
250 usbd_enum_error(pudev, req);
251 }
252 break;
253 default:
254 usbd_enum_error(pudev, req);
255 break;
256 }
257
258 return USBD_OK;
259 }
usb_device_req_struct::wIndex
uint16_t wIndex
Definition: usbd_core.h:120
usb_device_req_struct::wLength
uint16_t wLength
Definition: usbd_core.h:121
USBD_CONTRL_STATUS_TX
#define USBD_CONTRL_STATUS_TX()
Definition: usbd_core.h:33
LOWBYTE
#define LOWBYTE(x)
Definition: usbd_std.h:81
USBD_OK
Definition: usbd_core.h:84
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
USBD_CONFIGURED
Definition: usbd_core.h:76
usbd_enum_error
void usbd_enum_error(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB enumeration error event
Definition: usbd_std.c:832
usbd_core_handle_struct::class_req_handler
usbd_status_enum(* class_req_handler)(void *pudev, usb_device_req_struct *req)
Definition: usbd_core.h:153
usbd_core_handle_struct::status
uint8_t status
Definition: usbd_core.h:129
void usbd_enum_error | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB enumeration error event

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
none

Definition at line 832 of file usbd_std.c.

833 {
834 usbd_ep_stall(pudev, EP0);
835 }
EP0
#define EP0
Definition: usbd_regs.h:189
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
uint8_t usbd_in_transaction | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

data in stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_num | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 155 of file usbd_std.c.

156 {
157 usb_ep_struct *ep = &pudev->in_ep[ep_num];
158
159 if (0U == ep_num) {
160 if (0U != pudev->ctl_count) {
161 if (ep->trs_len > ep->maxpacket) {
162 /* one data packet has been transmited, update trs_len */
163 ep->trs_len -= ep->maxpacket;
164
165 /* continue to transmit remain data */
166 usbd_ep_tx (pudev, EP0_IN, ep->trs_buf, (uint16_t)ep->trs_len);
167
168 usbd_ep_rx (pudev, 0, NULL, 0);
169 } else {
170 #ifndef USB_DFU
171 /* transmit length is maxpacket multiple, so send zero length packet */
172 if ((0U == (ep->trs_len % ep->maxpacket)) && (ep->trs_len < pudev->ctl_count)) {
173 usbd_ep_tx (pudev, EP0_IN, NULL, 0U);
174
175 pudev->ctl_count = 0U;
176
177 usbd_ep_rx (pudev, 0, NULL, 0);
178 } else
179 #endif /* USB_DFU */
180 {
181 ep->trs_len = 0U;
182
183 if (USBD_CONFIGURED == pudev->status) {
184 pudev->class_data_handler(pudev, USBD_TX, EP0);
185 }
186
187 USBD_CONTRL_STATUS_RX();
188
189 pudev->ctl_count = 0U;
190 }
191 }
192 } else {
193 if (0U != g_device_address) {
194 USBD_REG_SET(USBD_DADDR, DADDR_USBEN | g_device_address);
195 g_device_address = 0U;
196 }
197 }
198 } else {
199 ep->trs_len -= ep->trs_count;
200
201 if (0U == ep->trs_len) {
202 if (USBD_CONFIGURED == pudev->status) {
203 pudev->class_data_handler(pudev, USBD_TX, ep_num);
204 }
205 } else {
206 usbd_ep_tx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len);
207 }
208 }
209
210 return USBD_OK;
211 }
EP0_IN
#define EP0_IN
Definition: usbd_regs.h:172
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
DADDR_USBEN
#define DADDR_USBEN
Definition: usbd_regs.h:75
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
EP0
#define EP0
Definition: usbd_regs.h:189
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
usbd_core_handle_struct::ctl_count
uint32_t ctl_count
Definition: usbd_core.h:136
usbd_core_handle_struct::class_data_handler
usbd_status_enum(* class_data_handler)(void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num)
Definition: usbd_core.h:154
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
usb_ep_struct
Definition: usbd_core.h:102
USBD_OK
Definition: usbd_core.h:84
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
USBD_CONTRL_STATUS_RX
#define USBD_CONTRL_STATUS_RX()
Definition: usbd_core.h:39
USBD_DADDR
#define USBD_DADDR
Definition: usbd_regs.h:27
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
NULL
#define NULL
Definition: usbd_std.h:20
USBD_CONFIGURED
Definition: usbd_core.h:76
g_device_address
uint8_t g_device_address
Definition: usbd_std.c:16
usbd_core_handle_struct::status
uint8_t status
Definition: usbd_core.h:129
USBD_TX
Definition: usbd_core.h:67
uint8_t usbd_out_transaction | ( | usbd_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

data out stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_num | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 113 of file usbd_std.c.

114 {
115 usb_ep_struct *ep = &pudev->out_ep[ep_num];
116
117 if (0U == ep_num) {
118 if (0U != pudev->ctl_count) {
119 if (ep->trs_len > ep->maxpacket) {
120 /* one data packet has been received, update trs_len */
121 ep->trs_len -= ep->maxpacket;
122
123 /* continue to receive remain data */
124 usbd_ep_rx(pudev, EP0_OUT, ep->trs_buf, (uint16_t)ep->trs_len);
125 } else {
126 if (USBD_CONFIGURED == pudev->status) {
127 /* device class handle */
128 pudev->class_data_handler(pudev, USBD_RX, EP0);
129 }
130
131 /* enter the control transaction status stage */
132 USBD_CONTRL_STATUS_TX();
133
134 pudev->ctl_count = 0U;
135 }
136 } else {
137 /* clear endpoint status_out status */
138 USBD_STATUS_OUT_CLEAR(EP0);
139 }
140 } else {
141 if (USBD_CONFIGURED == pudev->status) {
142 pudev->class_data_handler(pudev, USBD_RX, ep_num);
143 }
144 }
145 return USBD_OK;
146 }
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
EP0
#define EP0
Definition: usbd_regs.h:189
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
USBD_CONTRL_STATUS_TX
#define USBD_CONTRL_STATUS_TX()
Definition: usbd_core.h:33
usbd_core_handle_struct::ctl_count
uint32_t ctl_count
Definition: usbd_core.h:136
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
usbd_core_handle_struct::class_data_handler
usbd_status_enum(* class_data_handler)(void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num)
Definition: usbd_core.h:154
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
usb_ep_struct
Definition: usbd_core.h:102
USBD_OK
Definition: usbd_core.h:84
USBD_CONFIGURED
Definition: usbd_core.h:76
USBD_RX
Definition: usbd_core.h:66
usbd_core_handle_struct::status
uint8_t status
Definition: usbd_core.h:129
USBD_STATUS_OUT_CLEAR
#define USBD_STATUS_OUT_CLEAR(ep_num)
Definition: usbd_regs.h:238
EP0_OUT
#define EP0_OUT
Definition: usbd_regs.h:171
void usbd_setup_request_parse | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

decode setup data packet

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
none

Definition at line 812 of file usbd_std.c.

813 {
814 uint8_t *setup_data = pudev->setup_packet;
815
816 req->bmRequestType = *setup_data;
817 req->bRequest = *(uint8_t *)(setup_data + 1U);
818 req->wValue = SWAPBYTE (setup_data + 2U);
819 req->wIndex = SWAPBYTE (setup_data + 4U);
820 req->wLength = SWAPBYTE (setup_data + 6U);
821
822 pudev->ctl_count = req->wLength;
823 }
usb_device_req_struct::wIndex
uint16_t wIndex
Definition: usbd_core.h:120
usb_device_req_struct::wLength
uint16_t wLength
Definition: usbd_core.h:121
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usbd_core_handle_struct::ctl_count
uint32_t ctl_count
Definition: usbd_core.h:136
usbd_core_handle_struct::setup_packet
uint8_t setup_packet[8]
Definition: usbd_core.h:135
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usbd_core.h:117
usb_device_req_struct::bRequest
uint8_t bRequest
Definition: usbd_core.h:118
usb_device_req_struct::wValue
uint16_t wValue
Definition: usbd_core.h:119
uint8_t usbd_setup_transaction ( usbd_core_handle_struct * pudev )

USB setup stage processing.

Parameters
[in] | pudev | pointer to USB device instance
[out] | none
Return values
USB device operation status

Definition at line 80 of file usbd_std.c.

81 {
82 usb_device_req_struct req;
83
84 usbd_setup_request_parse (pudev, &req);
85
86 switch (req.bmRequestType & USB_REQ_MASK) {
87 /* standard device request */
88 case USB_STANDARD_REQ:
89 usbd_standard_request(pudev, &req);
90 break;
91 /* device class request */
92 case USB_CLASS_REQ:
93 usbd_device_class_request(pudev, &req);
94 break;
95 /* vendor defined request */
96 case USB_VENDOR_REQ:
97 usbd_vendor_request(pudev, &req);
98 break;
99 default:
100 usbd_ep_stall(pudev, 0x00U);
101 break;
102 }
103 return USBD_OK;
104 }
usbd_standard_request
uint8_t usbd_standard_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB standard device request
Definition: usbd_std.c:220
USB_VENDOR_REQ
#define USB_VENDOR_REQ
Definition: usbd_std.h:36
USB_CLASS_REQ
#define USB_CLASS_REQ
Definition: usbd_std.h:35
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usb_device_req_struct
Definition: usbd_core.h:115
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usbd_core.h:117
usbd_device_class_request
uint8_t usbd_device_class_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB device class request
Definition: usbd_std.c:235
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
USBD_OK
Definition: usbd_core.h:84
USB_REQ_MASK
#define USB_REQ_MASK
Definition: usbd_std.h:37
usbd_vendor_request
uint8_t usbd_vendor_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB vendor request
Definition: usbd_std.c:268
usbd_setup_request_parse
void usbd_setup_request_parse(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
decode setup data packet
Definition: usbd_std.c:812
uint8_t usbd_standard_request | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB standard device request

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
USB device operation status

Definition at line 220 of file usbd_std.c.

221 {
222 /* call device request handle function */
223 (*standard_device_request[req->bRequest])(pudev, req);
224
225 return USBD_OK;
226 }
USBD_OK
Definition: usbd_core.h:84
usb_device_req_struct::bRequest
uint8_t bRequest
Definition: usbd_core.h:118
uint8_t usbd_vendor_request | ( | usbd_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB vendor request

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB vendor request
[out] | none
Return values
USB device operation status

Definition at line 268 of file usbd_std.c.

269 {
270 /* added by user */
271
272 return USBD_OK;
273 }
USBD_OK
Definition: usbd_core.h:84

Variable Documentation

uint8_t g_device_address = 0U

Definition at line 16 of file usbd_std.c.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
GD32F10x_usbfs_driver Directory Reference

Directories

directory | Include
directory | Source


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Include Directory Reference

Files

file | usb_core.h [code]
USB core driver header file.
file | usb_defines.h [code]
USB core defines.
file | usb_regs.h [code]
USB FS cell registers definition and handle macros.
file | usb_std.h [code]
USB 2.0 standard defines.
file | usbd_core.h [code]
file | usbd_int.h [code]
file | usbd_std.h [code]
file | usbh_core.h [code]
header file for usbh_core.c
file | usbh_ctrl.h [code]
header file for usbh_ctrl.c
file | usbh_hcs.h [code]
header file for usbh_hcs.c
file | usbh_int.h [code]
USB host mode interrupt handler header file.
file | usbh_std.h [code]
header file for usbh_std.c


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_defines.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Macros | Enumerations
usb_defines.h File Reference

USB core defines. More...

#include "usb_conf.h"

Go to the source code of this file.

Macros

#define | NULL (void *)0
#define | USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */
#define | USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */
#define | USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */
#define | USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */
#define | USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */
#define | USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */
#define | USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */
#define | USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */
#define | USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */
#define | USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */
#define | USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */
#define | USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */
#define | DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
#define | DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
#define | DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */
#define | DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */
#define | GRSTATR_RPCKST_IN 2U /* IN data packet received */
#define | GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */
#define | GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */
#define | GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */
#define | DEVICE_MODE 0U /* USB core in device mode */
#define | HOST_MODE 1U /* USB core in host mode */
#define | OTG_MODE 2U /* USB core in OTG mode */
#define | USB_EPTYPE_CTRL 0U /* USB control endpoint type */
#define | USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */
#define | USB_EPTYPE_BULK 2U /* USB bulk endpoint type */
#define | USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */
#define | USB_EPTYPE_MASK 3U /* USB endpoint type mask */
#define | RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */
#define | RXSTAT_DATA_UPDT 2U /* OUT data packet received */
#define | RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */
#define | RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */
#define | RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */
#define | DPID_DATA0 0U /* device endpoint data PID is DATA0 */
#define | DPID_DATA1 2U /* device endpoint data PID is DATA1 */
#define | DPID_DATA2 1U /* device endpoint data PID is DATA2 */
#define | DPID_MDATA 3U /* device endpoint data PID is MDATA */
#define | HC_PID_DATA0 0U /* host channel data PID is DATA0 */
#define | HC_PID_DATA2 1U /* host channel data PID is DATA2 */
#define | HC_PID_DATA1 2U /* host channel data PID is DATA1 */
#define | HC_PID_SETUP 3U /* host channel data PID is SETUP */
#define | HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */
#define | HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */
#define | HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */
#define | HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */
#define | HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */
#define | HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */
#define | HCCHAR_CTRL 0U /* control channel type */
#define | HCCHAR_ISOC 1U /* synchronous channel type */
#define | HCCHAR_BULK 2U /* bulk channel type */
#define | HCCHAR_INTR 3U /* interrupt channel type */

Enumerations

enum | usb_core_id_enum { USB_HS_CORE_ID = 0, USB_FS_CORE_ID = 1 }
enum | usb_speed_enum { USB_SPEED_UNKNOWN = 0, USB_SPEED_LOW, USB_SPEED_FULL, USB_SPEED_HIGH }

Detailed Description

USB core defines.

Definition in file usb_defines.h.

Macro Definition Documentation

#define DEVICE_MODE 0U /* USB core in device mode */

Definition at line 48 of file usb_defines.h.

#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */

Definition at line 64 of file usb_defines.h.

#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */

Definition at line 65 of file usb_defines.h.

#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */

Definition at line 66 of file usb_defines.h.

#define DPID_MDATA 3U /* device endpoint data PID is MDATA */

Definition at line 67 of file usb_defines.h.

#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */

Definition at line 39 of file usb_defines.h.

#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */

Definition at line 41 of file usb_defines.h.

#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */

Definition at line 38 of file usb_defines.h.

#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */

Definition at line 40 of file usb_defines.h.

#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */

Definition at line 46 of file usb_defines.h.

#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */

Definition at line 45 of file usb_defines.h.

#define GRSTATR_RPCKST_IN 2U /* IN data packet received */

Definition at line 43 of file usb_defines.h.

#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */

Definition at line 44 of file usb_defines.h.

#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */

Definition at line 69 of file usb_defines.h.

#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */

Definition at line 71 of file usb_defines.h.

#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */

Definition at line 70 of file usb_defines.h.

#define HC_PID_SETUP 3U /* host channel data PID is SETUP */

Definition at line 72 of file usb_defines.h.

#define HCCHAR_BULK 2U /* bulk channel type */

Definition at line 84 of file usb_defines.h.

#define HCCHAR_CTRL 0U /* control channel type */

Definition at line 82 of file usb_defines.h.

#define HCCHAR_INTR 3U /* interrupt channel type */

Definition at line 85 of file usb_defines.h.

#define HCCHAR_ISOC 1U /* synchronous channel type */

Definition at line 83 of file usb_defines.h.

#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */

Definition at line 78 of file usb_defines.h.

#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */

Definition at line 79 of file usb_defines.h.

#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */

Definition at line 80 of file usb_defines.h.

#define HOST_MODE 1U /* USB core in host mode */

Definition at line 49 of file usb_defines.h.

#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */

Definition at line 75 of file usb_defines.h.

#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */

Definition at line 74 of file usb_defines.h.

#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */

Definition at line 76 of file usb_defines.h.

#define NULL (void *)0

USB null marco value

Definition at line 19 of file usb_defines.h.

#define OTG_MODE 2U /* USB core in OTG mode */

Definition at line 50 of file usb_defines.h.

#define RXSTAT_DATA_UPDT 2U /* OUT data packet received */

Definition at line 59 of file usb_defines.h.

#define RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */

Definition at line 58 of file usb_defines.h.

#define RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */

Definition at line 61 of file usb_defines.h.

#define RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */

Definition at line 62 of file usb_defines.h.

#define RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */

Definition at line 60 of file usb_defines.h.

#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */

Definition at line 36 of file usb_defines.h.

#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */

Definition at line 23 of file usb_defines.h.

#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */

Definition at line 22 of file usb_defines.h.

#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */

Definition at line 35 of file usb_defines.h.

#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */

Definition at line 54 of file usb_defines.h.

#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */

Definition at line 52 of file usb_defines.h.

#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */

Definition at line 55 of file usb_defines.h.

#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */

Definition at line 53 of file usb_defines.h.

#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */

Definition at line 56 of file usb_defines.h.

#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */

Definition at line 27 of file usb_defines.h.

#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */

Definition at line 28 of file usb_defines.h.

#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */

Definition at line 26 of file usb_defines.h.

#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */

Definition at line 25 of file usb_defines.h.

#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */

Definition at line 32 of file usb_defines.h.

#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */

Definition at line 33 of file usb_defines.h.

#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */

Definition at line 31 of file usb_defines.h.

#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */

Definition at line 30 of file usb_defines.h.

Enumeration Type Documentation

enum usb_core_id_enum
Enumerator
USB_HS_CORE_ID
USB_FS_CORE_ID

Definition at line 87 of file usb_defines.h.

88 {
89 USB_HS_CORE_ID = 0,
90 USB_FS_CORE_ID = 1
91 }usb_core_id_enum;
USB_HS_CORE_ID
Definition: usb_defines.h:89
USB_FS_CORE_ID
Definition: usb_defines.h:90
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:87
enum usb_speed_enum
Enumerator
USB_SPEED_UNKNOWN
USB_SPEED_LOW
USB_SPEED_FULL
USB_SPEED_HIGH

Definition at line 93 of file usb_defines.h.

94 {
95 USB_SPEED_UNKNOWN = 0,
96 USB_SPEED_LOW,
97 USB_SPEED_FULL,
98 USB_SPEED_HIGH
99 }usb_speed_enum;
USB_SPEED_FULL
Definition: usb_defines.h:97
usb_speed_enum
usb_speed_enum
Definition: usb_defines.h:93
USB_SPEED_UNKNOWN
Definition: usb_defines.h:95
USB_SPEED_HIGH
Definition: usb_defines.h:98
USB_SPEED_LOW
Definition: usb_defines.h:96
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_regs.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Macros
usb_regs.h File Reference

USB FS cell registers definition and handle macros. More...

#include "usb_conf.h"

Go to the source code of this file.

Macros

#define | USBFS USBFS_BASE
#define | LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U))
#define | LOCATE_HCHCTL(x) (0x500U + 0x20U * (x))
#define | LOCATE_HCHINTF(x) (0x508U + 0x20U * (x))
#define | LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x))
#define | LOCATE_HCHLEN(x) (0x510U + 0x20U * (x))
#define | LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x))
#define | LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x))
#define | LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x))
#define | LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x))
#define | LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x))
#define | LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x))
#define | LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x))
#define | LOCATE_FIFO(x) (((x) + 1U) << 12U)
#define | USB_GOTGCS REG32(((USBFS) + 0x0000U))
#define | USB_GOTGINTF REG32(((USBFS) + 0x0004U))
#define | USB_GAHBCS REG32(((USBFS) + 0x0008U))
#define | USB_GUSBCS REG32(((USBFS) + 0x000CU))
#define | USB_GRSTCTL REG32(((USBFS) + 0x0010U))
#define | USB_GINTF REG32(((USBFS) + 0x0014U))
#define | USB_GINTEN REG32(((USBFS) + 0x0018U))
#define | USB_GRSTATR REG32(((USBFS) + 0x001CU))
#define | USB_GRSTATP REG32(((USBFS) + 0x0020U))
#define | USB_GRFLEN REG32(((USBFS) + 0x0024U))
#define | USB_HNPTFLEN REG32(((USBFS) + 0x0028U))
#define | USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U))
#define | USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU))
#define | USB_GCCFG REG32(((USBFS) + 0x0038U))
#define | USB_CID REG32(((USBFS) + 0x003CU))
#define | USB_HPTFLEN REG32(((USBFS) + 0x0100U))
#define | USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x)))
#define | USB_HCTL REG32(((USBFS) + 0x0400U))
#define | USB_HFT REG32(((USBFS) + 0x0404U))
#define | USB_HFINFR REG32(((USBFS) + 0x0408U))
#define | USB_HPTFQSTAT REG32(((USBFS) + 0x0410U))
#define | USB_HACHINT REG32(((USBFS) + 0x0414U))
#define | USB_HACHINTEN REG32(((USBFS) + 0x0418U))
#define | USB_HPCS REG32(((USBFS) + 0x0440U))
#define | USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x)))
#define | USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x)))
#define | USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x)))
#define | USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x)))
#define | USB_DCFG REG32(((USBFS) + 0x0800U))
#define | USB_DCTL REG32(((USBFS) + 0x0804U))
#define | USB_DSTAT REG32(((USBFS) + 0x0808U))
#define | USB_DIEPINTEN REG32(((USBFS) + 0x0810U))
#define | USB_DOEPINTEN REG32(((USBFS) + 0x0814U))
#define | USB_DAEPINT REG32(((USBFS) + 0x0818U))
#define | USB_DAEPINTEN REG32(((USBFS) + 0x081CU))
#define | USB_DVBUSDT REG32(((USBFS) + 0x0828U))
#define | USB_DVBUSPT REG32(((USBFS) + 0x082CU))
#define | USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U))
#define | USB_DEP1INT REG32(((USBFS) + 0x0838U))
#define | USB_DEP1INTEN REG32(((USBFS) + 0x083CU))
#define | USB_DIEP1INTEN REG32(((USBFS) + 0x0844U))
#define | USB_DOEP1INTEN REG32(((USBFS) + 0x0884U))
#define | USB_DIEP0CTL REG32(((USBFS) + 0x0900U))
#define | USB_DIEP0LEN REG32(((USBFS) + 0x0910U))
#define | USB_DOEP0CTL REG32(((USBFS) + 0x0B00U))
#define | USB_DOEP0LEN REG32(((USBFS) + 0x0B10U))
#define | USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x)))
#define | USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x)))
#define | USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x)))
#define | USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x)))
#define | USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x)))
#define | USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x)))
#define | USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x)))
#define | USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U))
#define | USB_FIFO(x) (&REG32(((USBFS) + LOCATE_FIFO(x))))
#define | GOTGCS_BSV BIT(19)
#define | GOTGCS_ASV BIT(18)
#define | GOTGCS_DI BIT(17)
#define | GOTGCS_IDPS BIT(16)
#define | GOTGCS_DHNPEN BIT(11)
#define | GOTGCS_HHNPEN BIT(10)
#define | GOTGCS_HNPREQ BIT(9)
#define | GOTGCS_HNPS BIT(8)
#define | GOTGCS_SRPREQ BIT(1)
#define | GOTGCS_SRPS BIT(0)
#define | GOTGINTF_DF BIT(19)
#define | GOTGINTF_ADTO BIT(18)
#define | GOTGINTF_HNPDET BIT(17)
#define | GOTGINTF_HNPEND BIT(9)
#define | GOTGINTF_SRPEND BIT(8)
#define | GOTGINTF_SESEND BIT(2)
#define | GAHBCS_PTXFTH BIT(8)
#define | GAHBCS_TXFTH BIT(7)
#define | GAHBCS_GINTEN BIT(0)
#define | GUSBCS_FDM BIT(30)
#define | GUSBCS_FHM BIT(29)
#define | GUSBCS_UTT BITS(10, 13)
#define | GUSBCS_HNPCEN BIT(9)
#define | GUSBCS_SRPCEN BIT(8)
#define | GUSBCS_TOC BITS(0, 2)
#define | GRSTCTL_TXFNUM BITS(6, 10)
#define | GRSTCTL_TXFF BIT(5)
#define | GRSTCTL_RXFF BIT(4)
#define | GRSTCTL_HFCRST BIT(2)
#define | GRSTCTL_HCSRST BIT(1)
#define | GRSTCTL_CSRST BIT(0)
#define | GINTF_WKUPIF BIT(31)
#define | GINTF_SESIF BIT(30)
#define | GINTF_DISCIF BIT(29)
#define | GINTF_IDPSC BIT(28)
#define | GINTF_PTXFEIF BIT(26)
#define | GINTF_HCIF BIT(25)
#define | GINTF_HPIF BIT(24)
#define | GINTF_PXNCIF BIT(21)
#define | GINTF_ISOONCIF BIT(21)
#define | GINTF_ISOINCIF BIT(20)
#define | GINTF_OEPIF BIT(19)
#define | GINTF_IEPIF BIT(18)
#define | GINTF_EOPFIF BIT(15)
#define | GINTF_ISOOPDIF BIT(14)
#define | GINTF_ENUMF BIT(13)
#define | GINTF_RST BIT(12)
#define | GINTF_SP BIT(11)
#define | GINTF_ESP BIT(10)
#define | GINTF_GONAK BIT(7)
#define | GINTF_GNPINAK BIT(6)
#define | GINTF_NPTXFEIF BIT(5)
#define | GINTF_RXFNEIF BIT(4)
#define | GINTF_SOF BIT(3)
#define | GINTF_OTGIF BIT(2)
#define | GINTF_MFIF BIT(1)
#define | GINTF_COPM BIT(0)
#define | GINTEN_WKUPIE BIT(31)
#define | GINTEN_SESIE BIT(30)
#define | GINTEN_DISCIE BIT(29)
#define | GINTEN_IDPSCIE BIT(28)
#define | GINTEN_PTXFEIE BIT(26)
#define | GINTEN_HCIE BIT(25)
#define | GINTEN_HPIE BIT(24)
#define | GINTEN_PXNCIE BIT(21)
#define | GINTEN_ISOONCIE BIT(21)
#define | GINTEN_ISOINCIE BIT(20)
#define | GINTEN_OEPIE BIT(19)
#define | GINTEN_IEPIE BIT(18)
#define | GINTEN_EOPFIE BIT(15)
#define | GINTEN_ISOOPDIE BIT(14)
#define | GINTEN_ENUMFIE BIT(13)
#define | GINTEN_RSTIE BIT(12)
#define | GINTEN_SPIE BIT(11)
#define | GINTEN_ESPIE BIT(10)
#define | GINTEN_GONAKIE BIT(7)
#define | GINTEN_GNPINAKIE BIT(6)
#define | GINTEN_NPTXFEIE BIT(5)
#define | GINTEN_RXFNEIE BIT(4)
#define | GINTEN_SOFIE BIT(3)
#define | GINTEN_OTGIE BIT(2)
#define | GINTEN_MFIE BIT(1)
#define | GRSTATRP_RPCKST BITS(17, 20)
#define | GRSTATRP_DPID BITS(15, 16)
#define | GRSTATRP_BCOUNT BITS(4, 14)
#define | GRSTATRP_CNUM BITS(0, 3)
#define | GRSTATRP_EPNUM BITS(0, 3)
#define | GRFLEN_RXFD BITS(0, 15)
#define | HNPTFLEN_HNPTXFD BITS(16, 31)
#define | HNPTFLEN_HNPTXRSAR BITS(0, 15)
#define | DIEP0TFLEN_IEP0TXFD BITS(16, 31)
#define | DIEP0TFLEN_IEP0TXRSAR BITS(0, 15)
#define | HNPTFQSTAT_NPTXRQTOP BITS(24, 30)
#define | HNPTFQSTAT_NPTXRQS BITS(16, 23)
#define | HNPTFQSTAT_NPTXFS BITS(0, 15)
#define | HNPTFQSTAT_CNUM BITS(27, 30)
#define | HNPTFQSTAT_EPNUM BITS(27, 30)
#define | HNPTFQSTAT_TYPE BITS(25, 26)
#define | HNPTFQSTAT_TMF BIT(24)
#define | GCCFG_VBUSIG BIT(21)
#define | GCCFG_SOFOEN BIT(20)
#define | GCCFG_VBUSBCEN BIT(19)
#define | GCCFG_VBUSACEN BIT(18)
#define | GCCFG_PWRON BIT(16)
#define | CID_CID BITS(0, 31)
#define | HPTFLEN_HPTXFD BITS(16, 31)
#define | HPTFLEN_HPTXFSAR BITS(0, 15)
#define | DIEPTFLEN_IEPTXFD BITS(16, 31)
#define | DIEPTFLEN_IEPTXRSAR BITS(0, 15)
#define | HCTL_CLKSEL BITS(0, 1)
#define | HFT_FRI BITS(0, 15)
#define | HFINFR_FRT BITS(16, 31)
#define | HFINFR_FRNUM BITS(0, 15)
#define | HPTFQSTAT_PTXREQT BITS(24, 31)
#define | HPTFQSTAT_PTXREQS BITS(16, 23)
#define | HPTFQSTAT_PTXFS BITS(0, 15)
#define | HPTFQSTAT_OEFRM BIT(31)
#define | HPTFQSTAT_CNUM BITS(27, 30)
#define | HPTFQSTAT_EPNUM BITS(27, 30)
#define | HPTFQSTAT_TYPE BITS(25, 26)
#define | HPTFQSTAT_TMF BIT(24)
#define | HACHINT_HACHINT BITS(0, 7)
#define | HACHINTEN_CINTEN BITS(0, 7)
#define | HPCS_PS BITS(17, 18)
#define | HPCS_PP BIT(12)
#define | HPCS_PLST BITS(10, 11)
#define | HPCS_PRST BIT(8)
#define | HPCS_PSP BIT(7)
#define | HPCS_PREM BIT(6)
#define | HPCS_PEDC BIT(3)
#define | HPCS_PE BIT(2)
#define | HPCS_PCD BIT(1)
#define | HPCS_PCST BIT(0)
#define | HCHCTL_CEN BIT(31)
#define | HCHCTL_CDIS BIT(30)
#define | HCHCTL_ODDFRM BIT(29)
#define | HCHCTL_DAR BITS(22, 28)
#define | HCHCTL_MPC BITS(20, 21)
#define | HCHCTL_EPTYPE BITS(18, 19)
#define | HCHCTL_LSD BIT(17)
#define | HCHCTL_EPDIR BIT(15)
#define | HCHCTL_EPNUM BITS(11, 14)
#define | HCHCTL_MPL BITS(0, 10)
#define | HCHINTF_DTER BIT(10)
#define | HCHINTF_REQOVR BIT(9)
#define | HCHINTF_BBER BIT(8)
#define | HCHINTF_USBER BIT(7)
#define | HCHINTF_NYET BIT(6)
#define | HCHINTF_ACK BIT(5)
#define | HCHINTF_NAK BIT(4)
#define | HCHINTF_STALL BIT(3)
#define | HCHINTF_CH BIT(1)
#define | HCHINTF_TF BIT(0)
#define | HCHINTEN_DTERIE BIT(10)
#define | HCHINTEN_REQOVRIE BIT(9)
#define | HCHINTEN_BBERIE BIT(8)
#define | HCHINTEN_USBERIE BIT(7)
#define | HCHINTEN_NYETIE BIT(6)
#define | HCHINTEN_ACKIE BIT(5)
#define | HCHINTEN_NAKIE BIT(4)
#define | HCHINTEN_STALLIE BIT(3)
#define | HCHINTEN_CHIE BIT(1)
#define | HCHINTEN_TFIE BIT(0)
#define | HCHLEN_DPID BITS(29, 30)
#define | HCHLEN_PCNT BITS(19, 28)
#define | HCHLEN_TLEN BITS(0, 18)
#define | DCFG_EOPFT BITS(11, 12)
#define | DCFG_DAR BITS(4, 10)
#define | DCFG_NZLSOH BIT(2)
#define | DCFG_DS BITS(0, 1)
#define | DCTL_POIF BIT(11)
#define | DCTL_CGONAK BIT(10)
#define | DCTL_SGONAK BIT(9)
#define | DCTL_CGINAK BIT(8)
#define | DCTL_SGINAK BIT(7)
#define | DCTL_GONS BIT(3)
#define | DCTL_GINS BIT(2)
#define | DCTL_SD BIT(1)
#define | DCTL_RWKUP BIT(0)
#define | DSTAT_FNRSOF BITS(8, 21)
#define | DSTAT_ES BITS(1, 2)
#define | DSTAT_SPST BIT(0)
#define | DIEPINTEN_TXFEEN BIT(7)
#define | DIEPINTEN_IEPNEEN BIT(6)
#define | DIEPINTEN_EPTXFUDEN BIT(4)
#define | DIEPINTEN_CITOEN BIT(3)
#define | DIEPINTEN_EPDISEN BIT(1)
#define | DIEPINTEN_TFEN BIT(0)
#define | DOEPINTEN_BTBSTPEN BIT(6)
#define | DOEPINTEN_EPRXFOVREN BIT(4)
#define | DOEPINTEN_STPFEN BIT(3)
#define | DOEPINTEN_EPDISEN BIT(1)
#define | DOEPINTEN_TFEN BIT(0)
#define | DAEPINT_OEPITB BITS(16, 21)
#define | DAEPINT_IEPITB BITS(0, 5)
#define | DAEPINTEN_OEPIE BITS(16, 21)
#define | DAEPINTEN_IEPIE BITS(0, 3)
#define | DVBUSDT_DVBUSDT BITS(0, 15)
#define | DVBUSPT_DVBUSPT BITS(0, 11)
#define | DIEPFEINTEN_IEPTXFEIE BITS(0, 3)
#define | DEP0CTL_EPEN BIT(31)
#define | DEP0CTL_EPD BIT(30)
#define | DEP0CTL_SNAK BIT(27)
#define | DEP0CTL_CNAK BIT(26)
#define | DIEP0CTL_TXFNUM BITS(22, 25)
#define | DEP0CTL_STALL BIT(21)
#define | DEP0CTL_EPTYPE BITS(18, 19)
#define | DEP0CTL_NAKS BIT(17)
#define | DEP0CTL_EPACT BIT(15)
#define | DEP0CTL_MPL BITS(0, 1)
#define | DEPCTL_EPEN BIT(31)
#define | DEPCTL_EPD BIT(30)
#define | DEPCTL_SODDFRM BIT(29)
#define | DEPCTL_SD1PID BIT(29)
#define | DEPCTL_SEVNFRM BIT(28)
#define | DEPCTL_SD0PID BIT(28)
#define | DEPCTL_SNAK BIT(27)
#define | DEPCTL_CNAK BIT(26)
#define | DIEPCTL_TXFNUM BITS(22, 25)
#define | DEPCTL_STALL BIT(21)
#define | DEPCTL_EPTYPE BITS(18, 19)
#define | DEPCTL_NAKS BIT(17)
#define | DEPCTL_EOFRM BIT(16)
#define | DEPCTL_DPID BIT(16)
#define | DEPCTL_EPACT BIT(15)
#define | DEPCTL_MPL BITS(0, 10)
#define | DIEPINTF_TXFE BIT(7)
#define | DIEPINTF_IEPNE BIT(6)
#define | DIEPINTF_EPTXFUD BIT(4)
#define | DIEPINTF_CITO BIT(3)
#define | DIEPINTF_EPDIS BIT(1)
#define | DIEPINTF_TF BIT(0)
#define | DOEPINTF_BTBSTP BIT(6)
#define | DOEPINTF_EPRXFOVR BIT(4)
#define | DOEPINTF_STPF BIT(3)
#define | DOEPINTF_EPDIS BIT(1)
#define | DOEPINTF_TF BIT(0)
#define | DIEP0LEN_PCNT BITS(19, 20)
#define | DIEP0LEN_TLEN BITS(0, 6)
#define | DOEP0LEN_STPCNT BITS(29, 30)
#define | DOEP0LEN_PCNT BIT(19)
#define | DOEP0LEN_TLEN BITS(0, 6)
#define | DOEPLEN_RXDPID BITS(29, 30)
#define | DOEPLEN_STPCNT BITS(29, 30)
#define | DIEPLEN_MCNT BITS(29, 30)
#define | DEPLEN_PCNT BITS(19, 28)
#define | DEPLEN_TLEN BITS(0, 18)
#define | DIEPTFSTAT_IEPTFS BITS(0, 15)
#define | PWRCLKCTL_SHCLK BIT(1)
#define | PWRCLKCTL_SUCLK BIT(0)
#define | DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U))
#define | USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U)
#define | USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U)
#define | USB_SPEED_INP_FULL DCFG_DEVSPEED(3U)
#define | GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U))
#define | TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U)
#define | TXFIFO_EMPTY GAHBCS_TFEL(1U)
#define | GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U))
#define | DMA_INCR0 GAHBCS_DMAINCR(0U)
#define | DMA_INCR1 GAHBCS_DMAINCR(1U)
#define | DMA_INCR4 GAHBCS_DMAINCR(3U)
#define | DMA_INCR8 GAHBCS_DMAINCR(5U)
#define | DMA_INCR16 GAHBCS_DMAINCR(7U)
#define | DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U))
#define | FRAME_INTERVAL_80 DCFG_PFRI(0U)
#define | FRAME_INTERVAL_85 DCFG_PFRI(1U)
#define | FRAME_INTERVAL_90 DCFG_PFRI(2U)
#define | FRAME_INTERVAL_95 DCFG_PFRI(3U)
#define | DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U))
#define | EP0MPL_64 DEP0_MPL(0U)
#define | EP0MPL_32 DEP0_MPL(1U)
#define | EP0MPL_16 DEP0_MPL(2U)
#define | EP0MPL_8 DEP0_MPL(3U)
#define | EP0_OUT ((uint8_t)0x00U)
#define | EP0_IN ((uint8_t)0x80U)
#define | EP1_OUT ((uint8_t)0x01U)
#define | EP1_IN ((uint8_t)0x81U)
#define | EP2_OUT ((uint8_t)0x02U)
#define | EP2_IN ((uint8_t)0x82U)
#define | EP3_OUT ((uint8_t)0x03U)
#define | EP3_IN ((uint8_t)0x83U)
#define | USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN)
#define | USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN)
#define | USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM)
#define | USB_CORE_INTR_READ(x)
#define | USB_DAOEP_INTR_READ(x)
#define | USB_DOEP_INTR_READ(x, EpID)
#define | USB_DAIEP_INTR_READ(x)
#define | USB_DIEP_INTR_READ(x, EpID)
#define | USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP)
#define | USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP)
#define | USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD)
#define | USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD)
#define | USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U)
#define | USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U))
#define | USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC))
#define | USB_FSLSCLOCK_INIT(ClockFreq)
#define | USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17)
#define | USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU)

Detailed Description

USB FS cell registers definition and handle macros.

Definition in file usb_regs.h.

Macro Definition Documentation

#define CID_CID BITS(0, 31)

core ID

Definition at line 227 of file usb_regs.h.

#define DAEPINT_IEPITB BITS(0, 5)

device all IN endpoint interrupt bits

Definition at line 359 of file usb_regs.h.

#define DAEPINT_OEPITB BITS(16, 21)

device all OUT endpoint interrupt bits

Definition at line 358 of file usb_regs.h.

#define DAEPINTEN_IEPIE BITS(0, 3)

IN endpoint interrupt enable

Definition at line 363 of file usb_regs.h.

#define DAEPINTEN_OEPIE BITS(16, 21)

OUT endpoint interrupt enable

Definition at line 362 of file usb_regs.h.

#define DCFG_DAR BITS(4, 10)

device address

Definition at line 322 of file usb_regs.h.

#define DCFG_DEVSPEED ( regval ) (DCFG_DS & ((regval) << 0U))

device speed configuration

Definition at line 444 of file usb_regs.h.

#define DCFG_DS BITS(0, 1)

device speed

Definition at line 324 of file usb_regs.h.

#define DCFG_EOPFT BITS(11, 12)

end of periodic frame time

Definition at line 321 of file usb_regs.h.

#define DCFG_NZLSOH BIT(2)

non-zero-length status OUT handshake

Definition at line 323 of file usb_regs.h.

#define DCFG_PFRI ( regval ) (DCFG_EOPFT & ((regval) << 11U))

end of periodic frame time configuration

Definition at line 463 of file usb_regs.h.

#define DCTL_CGINAK BIT(8)

clear global IN NAK

Definition at line 330 of file usb_regs.h.

#define DCTL_CGONAK BIT(10)

clear global OUT NAK

Definition at line 328 of file usb_regs.h.

#define DCTL_GINS BIT(2)

global IN NAK status

Definition at line 333 of file usb_regs.h.

#define DCTL_GONS BIT(3)

global OUT NAK status

Definition at line 332 of file usb_regs.h.

#define DCTL_POIF BIT(11)

power-on initialization finished

Definition at line 327 of file usb_regs.h.

#define DCTL_RWKUP BIT(0)

remote wakeup

Definition at line 335 of file usb_regs.h.

#define DCTL_SD BIT(1)

soft disconnect

Definition at line 334 of file usb_regs.h.

#define DCTL_SGINAK BIT(7)

set global IN NAK

Definition at line 331 of file usb_regs.h.

#define DCTL_SGONAK BIT(9)

set global OUT NAK

Definition at line 329 of file usb_regs.h.

#define DEP0_MPL ( regval ) (DEP0CTL_MPL & ((regval) << 0U))

maximum packet length configuration

Definition at line 470 of file usb_regs.h.

#define DEP0CTL_CNAK BIT(26)

clear NAK

Definition at line 378 of file usb_regs.h.

#define DEP0CTL_EPACT BIT(15)

endpoint active

Definition at line 383 of file usb_regs.h.

#define DEP0CTL_EPD BIT(30)

endpoint disable

Definition at line 376 of file usb_regs.h.

#define DEP0CTL_EPEN BIT(31)

endpoint enable

Definition at line 375 of file usb_regs.h.

#define DEP0CTL_EPTYPE BITS(18, 19)

endpoint type

Definition at line 381 of file usb_regs.h.

#define DEP0CTL_MPL BITS(0, 1)

maximum packet length

Definition at line 384 of file usb_regs.h.

#define DEP0CTL_NAKS BIT(17)

NAK status

Definition at line 382 of file usb_regs.h.

#define DEP0CTL_SNAK BIT(27)

set NAK

Definition at line 377 of file usb_regs.h.

#define DEP0CTL_STALL BIT(21)

STALL handshake

Definition at line 380 of file usb_regs.h.

#define DEPCTL_CNAK BIT(26)

clear NAK

Definition at line 394 of file usb_regs.h.

#define DEPCTL_DPID BIT(16)

endpoint data PID

Definition at line 401 of file usb_regs.h.

#define DEPCTL_EOFRM BIT(16)

even/odd frame

Definition at line 400 of file usb_regs.h.

#define DEPCTL_EPACT BIT(15)

endpoint active

Definition at line 402 of file usb_regs.h.

#define DEPCTL_EPD BIT(30)

endpoint disable

Definition at line 388 of file usb_regs.h.

#define DEPCTL_EPEN BIT(31)

endpoint enable

Definition at line 387 of file usb_regs.h.

#define DEPCTL_EPTYPE BITS(18, 19)

endpoint type

Definition at line 398 of file usb_regs.h.

#define DEPCTL_MPL BITS(0, 10)

maximum packet length

Definition at line 403 of file usb_regs.h.

#define DEPCTL_NAKS BIT(17)

NAK status

Definition at line 399 of file usb_regs.h.

#define DEPCTL_SD0PID BIT(28)

set DATA0 PID

Definition at line 392 of file usb_regs.h.

#define DEPCTL_SD1PID BIT(29)

set DATA1 PID

Definition at line 390 of file usb_regs.h.

#define DEPCTL_SEVNFRM BIT(28)

set even frame

Definition at line 391 of file usb_regs.h.

#define DEPCTL_SNAK BIT(27)

set NAK

Definition at line 393 of file usb_regs.h.

#define DEPCTL_SODDFRM BIT(29)

set odd frame

Definition at line 389 of file usb_regs.h.

#define DEPCTL_STALL BIT(21)

STALL handshake

Definition at line 396 of file usb_regs.h.

#define DEPLEN_PCNT BITS(19, 28)

packet count

Definition at line 433 of file usb_regs.h.

#define DEPLEN_TLEN BITS(0, 18)

transfer length

Definition at line 434 of file usb_regs.h.

#define DIEP0CTL_TXFNUM BITS(22, 25)

tx FIFO number

Definition at line 379 of file usb_regs.h.

#define DIEP0LEN_PCNT BITS(19, 20)

packet count

Definition at line 421 of file usb_regs.h.

#define DIEP0LEN_TLEN BITS(0, 6)

transfer length

Definition at line 422 of file usb_regs.h.

#define DIEP0TFLEN_IEP0TXFD BITS(16, 31)

IN Endpoint 0 Tx FIFO depth

Definition at line 207 of file usb_regs.h.

#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15)

IN Endpoint 0 TX RAM start address

Definition at line 208 of file usb_regs.h.

#define DIEPCTL_TXFNUM BITS(22, 25)

tx FIFO number

Definition at line 395 of file usb_regs.h.

#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3)

IN endpoint Tx FIFO empty interrupt enable bits

Definition at line 372 of file usb_regs.h.

#define DIEPINTEN_CITOEN BIT(3)

control In Timeout interrupt enable bit

Definition at line 346 of file usb_regs.h.

#define DIEPINTEN_EPDISEN BIT(1)

endpoint disabled interrupt enable bit

Definition at line 347 of file usb_regs.h.

#define DIEPINTEN_EPTXFUDEN BIT(4)

endpoint Tx FIFO underrun interrupt enable bit

Definition at line 345 of file usb_regs.h.

#define DIEPINTEN_IEPNEEN BIT(6)

IN endpoint NAK effective interrupt enable bit

Definition at line 344 of file usb_regs.h.

#define DIEPINTEN_TFEN BIT(0)

transfer finished interrupt enable bit

Definition at line 348 of file usb_regs.h.

#define DIEPINTEN_TXFEEN BIT(7)

transmit FIFO empty interrupt enable bit

Definition at line 343 of file usb_regs.h.

#define DIEPINTF_CITO BIT(3)

control In Timeout interrupt

Definition at line 409 of file usb_regs.h.

#define DIEPINTF_EPDIS BIT(1)

endpoint disabled

Definition at line 410 of file usb_regs.h.

#define DIEPINTF_EPTXFUD BIT(4)

endpoint Tx FIFO underrun

Definition at line 408 of file usb_regs.h.

#define DIEPINTF_IEPNE BIT(6)

IN endpoint NAK effective

Definition at line 407 of file usb_regs.h.

#define DIEPINTF_TF BIT(0)

transfer finished

Definition at line 411 of file usb_regs.h.

#define DIEPINTF_TXFE BIT(7)

transmit FIFO empty

Definition at line 406 of file usb_regs.h.

#define DIEPLEN_MCNT BITS(29, 30)

multi count

Definition at line 432 of file usb_regs.h.

#define DIEPTFLEN_IEPTXFD BITS(16, 31)

IN endpoint Tx FIFO x depth

Definition at line 234 of file usb_regs.h.

#define DIEPTFLEN_IEPTXRSAR BITS(0, 15)

IN endpoint FIFOx Tx x RAM start address

Definition at line 235 of file usb_regs.h.

#define DIEPTFSTAT_IEPTFS BITS(0, 15)

IN endpoint¡¯s Tx FIFO space remaining

Definition at line 437 of file usb_regs.h.

#define DMA_INCR0 GAHBCS_DMAINCR(0U)

single burst type used by DMA

Definition at line 457 of file usb_regs.h.

#define DMA_INCR1 GAHBCS_DMAINCR(1U)

4-beat incrementing burst type used by DMA

Definition at line 458 of file usb_regs.h.

#define DMA_INCR16 GAHBCS_DMAINCR(7U)

32-beat incrementing burst type used by DMA

Definition at line 461 of file usb_regs.h.

#define DMA_INCR4 GAHBCS_DMAINCR(3U)

8-beat incrementing burst type used by DMA

Definition at line 459 of file usb_regs.h.

#define DMA_INCR8 GAHBCS_DMAINCR(5U)

16-beat incrementing burst type used by DMA

Definition at line 460 of file usb_regs.h.

#define DOEP0LEN_PCNT BIT(19)

packet count

Definition at line 426 of file usb_regs.h.

#define DOEP0LEN_STPCNT BITS(29, 30)

SETUP packet count

Definition at line 425 of file usb_regs.h.

#define DOEP0LEN_TLEN BITS(0, 6)

transfer length

Definition at line 427 of file usb_regs.h.

#define DOEPINTEN_BTBSTPEN BIT(6)

back-to-back SETUP packets interrupt enable bit

Definition at line 351 of file usb_regs.h.

#define DOEPINTEN_EPDISEN BIT(1)

endpoint disabled interrupt enable bit

Definition at line 354 of file usb_regs.h.

#define DOEPINTEN_EPRXFOVREN BIT(4)

endpoint Rx FIFO overrun interrupt enable bit

Definition at line 352 of file usb_regs.h.

#define DOEPINTEN_STPFEN BIT(3)

SETUP phase finished interrupt enable bit

Definition at line 353 of file usb_regs.h.

#define DOEPINTEN_TFEN BIT(0)

transfer finished interrupt enable bit

Definition at line 355 of file usb_regs.h.

#define DOEPINTF_BTBSTP BIT(6)

back-to-back SETUP packets

Definition at line 414 of file usb_regs.h.

#define DOEPINTF_EPDIS BIT(1)

endpoint disabled

Definition at line 417 of file usb_regs.h.

#define DOEPINTF_EPRXFOVR BIT(4)

endpoint Rx FIFO overrun

Definition at line 415 of file usb_regs.h.

#define DOEPINTF_STPF BIT(3)

SETUP phase finished

Definition at line 416 of file usb_regs.h.

#define DOEPINTF_TF BIT(0)

transfer finished

Definition at line 418 of file usb_regs.h.

#define DOEPLEN_RXDPID BITS(29, 30)

received data PID

Definition at line 430 of file usb_regs.h.

#define DOEPLEN_STPCNT BITS(29, 30)

SETUP packet count

Definition at line 431 of file usb_regs.h.

#define DSTAT_ES BITS(1, 2)

enumerated speed

Definition at line 339 of file usb_regs.h.

#define DSTAT_FNRSOF BITS(8, 21)

the frame number of the received SOF.

Definition at line 338 of file usb_regs.h.

#define DSTAT_SPST BIT(0)

suspend status

Definition at line 340 of file usb_regs.h.

#define DVBUSDT_DVBUSDT BITS(0, 15)

device VBUS discharge time

Definition at line 366 of file usb_regs.h.

#define DVBUSPT_DVBUSPT BITS(0, 11)

device VBUS pulsing time

Definition at line 369 of file usb_regs.h.

#define EP0_IN ((uint8_t)0x80U)

endpoint in 0

Definition at line 481 of file usb_regs.h.

#define EP0_OUT ((uint8_t)0x00U)

endpoint out 0

Definition at line 480 of file usb_regs.h.

#define EP0MPL_16 DEP0_MPL(2U)

maximum packet length 16 bytes

Definition at line 474 of file usb_regs.h.

#define EP0MPL_32 DEP0_MPL(1U)

maximum packet length 32 bytes

Definition at line 473 of file usb_regs.h.

#define EP0MPL_64 DEP0_MPL(0U)

maximum packet length 64 bytes

Definition at line 472 of file usb_regs.h.

#define EP0MPL_8 DEP0_MPL(3U)

maximum packet length 8 bytes

Definition at line 475 of file usb_regs.h.

#define EP1_IN ((uint8_t)0x81U)

endpoint in 1

Definition at line 483 of file usb_regs.h.

#define EP1_OUT ((uint8_t)0x01U)

endpoint out 1

Definition at line 482 of file usb_regs.h.

#define EP2_IN ((uint8_t)0x82U)

endpoint in 2

Definition at line 485 of file usb_regs.h.

#define EP2_OUT ((uint8_t)0x02U)

endpoint out 2

Definition at line 484 of file usb_regs.h.

#define EP3_IN ((uint8_t)0x83U)

endpoint in 3

Definition at line 487 of file usb_regs.h.

#define EP3_OUT ((uint8_t)0x03U)

endpoint out 3

Definition at line 486 of file usb_regs.h.

#define FRAME_INTERVAL_80 DCFG_PFRI(0U)

80% of the frame time

Definition at line 465 of file usb_regs.h.

#define FRAME_INTERVAL_85 DCFG_PFRI(1U)

85% of the frame time

Definition at line 466 of file usb_regs.h.

#define FRAME_INTERVAL_90 DCFG_PFRI(2U)

90% of the frame time

Definition at line 467 of file usb_regs.h.

#define FRAME_INTERVAL_95 DCFG_PFRI(3U)

95% of the frame time

Definition at line 468 of file usb_regs.h.

#define GAHBCS_DMAINCR ( regval ) (GAHBCS_BURST & ((regval) << 1U))

AHB burst type used by DMA

Definition at line 455 of file usb_regs.h.

#define GAHBCS_GINTEN BIT(0)

global interrupt enable

Definition at line 119 of file usb_regs.h.

#define GAHBCS_PTXFTH BIT(8)

periodic Tx FIFO threshold

Definition at line 117 of file usb_regs.h.

#define GAHBCS_TFEL ( regval ) (GAHBCS_TXFTH & ((regval) << 7U))

device speed configuration

Definition at line 450 of file usb_regs.h.

#define GAHBCS_TXFTH BIT(7)

tx FIFO threshold

Definition at line 118 of file usb_regs.h.

#define GCCFG_PWRON BIT(16)

power on

Definition at line 224 of file usb_regs.h.

#define GCCFG_SOFOEN BIT(20)

SOF output enable

Definition at line 221 of file usb_regs.h.

#define GCCFG_VBUSACEN BIT(18)

the VBUS A-device comparer enable

Definition at line 223 of file usb_regs.h.

#define GCCFG_VBUSBCEN BIT(19)

the VBUS B-device comparer enable

Definition at line 222 of file usb_regs.h.

#define GCCFG_VBUSIG BIT(21)

vbus ignored

Definition at line 220 of file usb_regs.h.

#define GINTEN_DISCIE BIT(29)

disconnect interrupt enable

Definition at line 168 of file usb_regs.h.

#define GINTEN_ENUMFIE BIT(13)

enumeration finish enable

Definition at line 180 of file usb_regs.h.

#define GINTEN_EOPFIE BIT(15)

end of periodic frame interrupt enable

Definition at line 178 of file usb_regs.h.

#define GINTEN_ESPIE BIT(10)

early suspend interrupt enable

Definition at line 183 of file usb_regs.h.

#define GINTEN_GNPINAKIE BIT(6)

global non-periodic IN NAK effective interrupt enable

Definition at line 185 of file usb_regs.h.

#define GINTEN_GONAKIE BIT(7)

global OUT NAK effective interrupt enable

Definition at line 184 of file usb_regs.h.

#define GINTEN_HCIE BIT(25)

host channels interrupt enable

Definition at line 171 of file usb_regs.h.

#define GINTEN_HPIE BIT(24)

host port interrupt enable

Definition at line 172 of file usb_regs.h.

#define GINTEN_IDPSCIE BIT(28)

id pin status change interrupt enable

Definition at line 169 of file usb_regs.h.

#define GINTEN_IEPIE BIT(18)

IN endpoints interrupt enable

Definition at line 177 of file usb_regs.h.

#define GINTEN_ISOINCIE BIT(20)

isochronous IN transfer not complete interrupt enable

Definition at line 175 of file usb_regs.h.

#define GINTEN_ISOONCIE BIT(21)

isochronous OUT transfer not complete interrupt enable

Definition at line 174 of file usb_regs.h.

#define GINTEN_ISOOPDIE BIT(14)

isochronous OUT packet dropped interrupt enable

Definition at line 179 of file usb_regs.h.

#define GINTEN_MFIE BIT(1)

mode fault interrupt enable

Definition at line 190 of file usb_regs.h.

#define GINTEN_NPTXFEIE BIT(5)

non-periodic Tx FIFO empty interrupt enable

Definition at line 186 of file usb_regs.h.

#define GINTEN_OEPIE BIT(19)

OUT endpoints interrupt enable

Definition at line 176 of file usb_regs.h.

#define GINTEN_OTGIE BIT(2)

OTG interrupt enable

Definition at line 189 of file usb_regs.h.

#define GINTEN_PTXFEIE BIT(26)

periodic tx FIFO empty interrupt enable

Definition at line 170 of file usb_regs.h.

#define GINTEN_PXNCIE BIT(21)

periodic transfer not complete interrupt enable

Definition at line 173 of file usb_regs.h.

#define GINTEN_RSTIE BIT(12)

USB reset interrupt enable

Definition at line 181 of file usb_regs.h.

#define GINTEN_RXFNEIE BIT(4)

receive FIFO non-empty interrupt enable

Definition at line 187 of file usb_regs.h.

#define GINTEN_SESIE BIT(30)

session interrupt enable

Definition at line 167 of file usb_regs.h.

#define GINTEN_SOFIE BIT(3)

start of frame interrupt enable

Definition at line 188 of file usb_regs.h.

#define GINTEN_SPIE BIT(11)

USB suspend interrupt enable

Definition at line 182 of file usb_regs.h.

#define GINTEN_WKUPIE BIT(31)

wakeup interrupt enable

Definition at line 166 of file usb_regs.h.

#define GINTF_COPM BIT(0)

current operation mode

Definition at line 163 of file usb_regs.h.

#define GINTF_DISCIF BIT(29)

disconnect interrupt flag

Definition at line 140 of file usb_regs.h.

#define GINTF_ENUMF BIT(13)

enumeration finished

Definition at line 152 of file usb_regs.h.

#define GINTF_EOPFIF BIT(15)

end of periodic frame interrupt flag

Definition at line 150 of file usb_regs.h.

#define GINTF_ESP BIT(10)

early suspend

Definition at line 155 of file usb_regs.h.

#define GINTF_GNPINAK BIT(6)

global IN non-periodic NAK effective

Definition at line 157 of file usb_regs.h.

#define GINTF_GONAK BIT(7)

global OUT NAK effective

Definition at line 156 of file usb_regs.h.

#define GINTF_HCIF BIT(25)

host channels interrupt flag

Definition at line 143 of file usb_regs.h.

#define GINTF_HPIF BIT(24)

host port interrupt flag

Definition at line 144 of file usb_regs.h.

#define GINTF_IDPSC BIT(28)

id pin status change

Definition at line 141 of file usb_regs.h.

#define GINTF_IEPIF BIT(18)

IN endpoint interrupt flag

Definition at line 149 of file usb_regs.h.

#define GINTF_ISOINCIF BIT(20)

isochronous IN transfer not complete interrupt flag

Definition at line 147 of file usb_regs.h.

#define GINTF_ISOONCIF BIT(21)

isochronous OUT transfer not complete interrupt flag

Definition at line 146 of file usb_regs.h.

#define GINTF_ISOOPDIF BIT(14)

isochronous OUT packet dropped interrupt flag

Definition at line 151 of file usb_regs.h.

#define GINTF_MFIF BIT(1)

mode fault interrupt flag

Definition at line 162 of file usb_regs.h.

#define GINTF_NPTXFEIF BIT(5)

non-periodic tx FIFO empty interrupt flag

Definition at line 158 of file usb_regs.h.

#define GINTF_OEPIF BIT(19)

OUT endpoint interrupt flag

Definition at line 148 of file usb_regs.h.

#define GINTF_OTGIF BIT(2)

OTG interrupt flag

Definition at line 161 of file usb_regs.h.

#define GINTF_PTXFEIF BIT(26)

periodic tx FIFO empty interrupt flag

Definition at line 142 of file usb_regs.h.

#define GINTF_PXNCIF BIT(21)

periodic transfer not complete interrupt flag

Definition at line 145 of file usb_regs.h.

#define GINTF_RST BIT(12)

USB reset

Definition at line 153 of file usb_regs.h.

#define GINTF_RXFNEIF BIT(4)

rx FIFO non-empty interrupt flag

Definition at line 159 of file usb_regs.h.

#define GINTF_SESIF BIT(30)

session interrupt flag

Definition at line 139 of file usb_regs.h.

#define GINTF_SOF BIT(3)

start of frame

Definition at line 160 of file usb_regs.h.

#define GINTF_SP BIT(11)

USB suspend

Definition at line 154 of file usb_regs.h.

#define GINTF_WKUPIF BIT(31)

wakeup interrupt flag

Definition at line 138 of file usb_regs.h.

#define GOTGCS_ASV BIT(18)

A-session valid

Definition at line 98 of file usb_regs.h.

#define GOTGCS_BSV BIT(19)

B-Session Valid

Definition at line 97 of file usb_regs.h.

#define GOTGCS_DHNPEN BIT(11)

device HNP enable

Definition at line 101 of file usb_regs.h.

#define GOTGCS_DI BIT(17)

debounce interval

Definition at line 99 of file usb_regs.h.

#define GOTGCS_HHNPEN BIT(10)

host HNP enable

Definition at line 102 of file usb_regs.h.

#define GOTGCS_HNPREQ BIT(9)

HNP request

Definition at line 103 of file usb_regs.h.

#define GOTGCS_HNPS BIT(8)

HNP successes

Definition at line 104 of file usb_regs.h.

#define GOTGCS_IDPS BIT(16)

id pin status

Definition at line 100 of file usb_regs.h.

#define GOTGCS_SRPREQ BIT(1)

SRP request

Definition at line 105 of file usb_regs.h.

#define GOTGCS_SRPS BIT(0)

SRP successes

Definition at line 106 of file usb_regs.h.

#define GOTGINTF_ADTO BIT(18)

A-device timeout

Definition at line 110 of file usb_regs.h.

#define GOTGINTF_DF BIT(19)

debounce finish

Definition at line 109 of file usb_regs.h.

#define GOTGINTF_HNPDET BIT(17)

host negotiation request detected

Definition at line 111 of file usb_regs.h.

#define GOTGINTF_HNPEND BIT(9)

HNP end

Definition at line 112 of file usb_regs.h.

#define GOTGINTF_SESEND BIT(2)

session end

Definition at line 114 of file usb_regs.h.

#define GOTGINTF_SRPEND BIT(8)

SRP end

Definition at line 113 of file usb_regs.h.

#define GRFLEN_RXFD BITS(0, 15)

rx FIFO depth

Definition at line 200 of file usb_regs.h.

#define GRSTATRP_BCOUNT BITS(4, 14)

byte count

Definition at line 195 of file usb_regs.h.

#define GRSTATRP_CNUM BITS(0, 3)

channel number

Definition at line 196 of file usb_regs.h.

#define GRSTATRP_DPID BITS(15, 16)

data PID

Definition at line 194 of file usb_regs.h.

#define GRSTATRP_EPNUM BITS(0, 3)

endpoint number

Definition at line 197 of file usb_regs.h.

#define GRSTATRP_RPCKST BITS(17, 20)

received packet status

Definition at line 193 of file usb_regs.h.

#define GRSTCTL_CSRST BIT(0)

core soft reset

Definition at line 135 of file usb_regs.h.

#define GRSTCTL_HCSRST BIT(1)

HCLK soft reset

Definition at line 134 of file usb_regs.h.

#define GRSTCTL_HFCRST BIT(2)

host frame counter reset

Definition at line 133 of file usb_regs.h.

#define GRSTCTL_RXFF BIT(4)

rx FIFO flush

Definition at line 132 of file usb_regs.h.

#define GRSTCTL_TXFF BIT(5)

tx FIFO flush

Definition at line 131 of file usb_regs.h.

#define GRSTCTL_TXFNUM BITS(6, 10)

tx FIFO number

Definition at line 130 of file usb_regs.h.

#define GUSBCS_FDM BIT(30)

force device mode

Definition at line 122 of file usb_regs.h.

#define GUSBCS_FHM BIT(29)

force host mode

Definition at line 123 of file usb_regs.h.

#define GUSBCS_HNPCEN BIT(9)

HNP capability enable

Definition at line 125 of file usb_regs.h.

#define GUSBCS_SRPCEN BIT(8)

SRP capability enable

Definition at line 126 of file usb_regs.h.

#define GUSBCS_TOC BITS(0, 2)

timeout calibration

Definition at line 127 of file usb_regs.h.

#define GUSBCS_UTT BITS(10, 13)

USB turnaround time

Definition at line 124 of file usb_regs.h.

#define HACHINT_HACHINT BITS(0, 7)

host all channel interrupts

Definition at line 258 of file usb_regs.h.

#define HACHINTEN_CINTEN BITS(0, 7)

channel interrupt enable

Definition at line 261 of file usb_regs.h.

#define HCHCTL_CDIS BIT(30)

channel disable

Definition at line 277 of file usb_regs.h.

#define HCHCTL_CEN BIT(31)

channel enable

Definition at line 276 of file usb_regs.h.

#define HCHCTL_DAR BITS(22, 28)

device address

Definition at line 279 of file usb_regs.h.

#define HCHCTL_EPDIR BIT(15)

endpoint direction

Definition at line 283 of file usb_regs.h.

#define HCHCTL_EPNUM BITS(11, 14)

endpoint number

Definition at line 284 of file usb_regs.h.

#define HCHCTL_EPTYPE BITS(18, 19)

endpoint type

Definition at line 281 of file usb_regs.h.

#define HCHCTL_LSD BIT(17)

low-speed device

Definition at line 282 of file usb_regs.h.

#define HCHCTL_MPC BITS(20, 21)

multiple packet count

Definition at line 280 of file usb_regs.h.

#define HCHCTL_MPL BITS(0, 10)

maximum packet length

Definition at line 285 of file usb_regs.h.

#define HCHCTL_ODDFRM BIT(29)

odd frame

Definition at line 278 of file usb_regs.h.

#define HCHINTEN_ACKIE BIT(5)

ACK interrupt enable

Definition at line 305 of file usb_regs.h.

#define HCHINTEN_BBERIE BIT(8)

babble error interrupt enable

Definition at line 302 of file usb_regs.h.

#define HCHINTEN_CHIE BIT(1)

channel halted interrupt enable

Definition at line 308 of file usb_regs.h.

#define HCHINTEN_DTERIE BIT(10)

data toggle error interrupt enable

Definition at line 300 of file usb_regs.h.

#define HCHINTEN_NAKIE BIT(4)

NAK interrupt enable

Definition at line 306 of file usb_regs.h.

#define HCHINTEN_NYETIE BIT(6)

NYET interrupt enable

Definition at line 304 of file usb_regs.h.

#define HCHINTEN_REQOVRIE BIT(9)

request queue overrun interrupt enable

Definition at line 301 of file usb_regs.h.

#define HCHINTEN_STALLIE BIT(3)

STALL interrupt enable

Definition at line 307 of file usb_regs.h.

#define HCHINTEN_TFIE BIT(0)

transfer finished interrupt enable

Definition at line 309 of file usb_regs.h.

#define HCHINTEN_USBERIE BIT(7)

USB bus error interrupt enable

Definition at line 303 of file usb_regs.h.

#define HCHINTF_ACK BIT(5)

ACK

Definition at line 293 of file usb_regs.h.

#define HCHINTF_BBER BIT(8)

babble error

Definition at line 290 of file usb_regs.h.

#define HCHINTF_CH BIT(1)

channel halted

Definition at line 296 of file usb_regs.h.

#define HCHINTF_DTER BIT(10)

data toggle error

Definition at line 288 of file usb_regs.h.

#define HCHINTF_NAK BIT(4)

NAK

Definition at line 294 of file usb_regs.h.

#define HCHINTF_NYET BIT(6)

NYET

Definition at line 292 of file usb_regs.h.

#define HCHINTF_REQOVR BIT(9)

request queue overrun

Definition at line 289 of file usb_regs.h.

#define HCHINTF_STALL BIT(3)

STALL

Definition at line 295 of file usb_regs.h.

#define HCHINTF_TF BIT(0)

transfer finished

Definition at line 297 of file usb_regs.h.

#define HCHINTF_USBER BIT(7)

USB bus Error

Definition at line 291 of file usb_regs.h.

#define HCHLEN_DPID BITS(29, 30)

data PID

Definition at line 312 of file usb_regs.h.

#define HCHLEN_PCNT BITS(19, 28)

packet count

Definition at line 313 of file usb_regs.h.

#define HCHLEN_TLEN BITS(0, 18)

transfer length

Definition at line 314 of file usb_regs.h.

#define HCTL_CLKSEL BITS(0, 1)

clock select for USB clock

Definition at line 238 of file usb_regs.h.

#define HFINFR_FRNUM BITS(0, 15)

frame number

Definition at line 245 of file usb_regs.h.

#define HFINFR_FRT BITS(16, 31)

frame remaining time

Definition at line 244 of file usb_regs.h.

#define HFT_FRI BITS(0, 15)

frame interval

Definition at line 241 of file usb_regs.h.

#define HNPTFLEN_HNPTXFD BITS(16, 31)

non-periodic Tx FIFO depth

Definition at line 203 of file usb_regs.h.

#define HNPTFLEN_HNPTXRSAR BITS(0, 15)

non-periodic Tx RAM start address

Definition at line 204 of file usb_regs.h.

#define HNPTFQSTAT_CNUM BITS(27, 30)

channel number

Definition at line 214 of file usb_regs.h.

#define HNPTFQSTAT_EPNUM BITS(27, 30)

endpoint number

Definition at line 215 of file usb_regs.h.

#define HNPTFQSTAT_NPTXFS BITS(0, 15)

non-periodic Tx FIFO space

Definition at line 213 of file usb_regs.h.

#define HNPTFQSTAT_NPTXRQS BITS(16, 23)

non-periodic Tx request queue space

Definition at line 212 of file usb_regs.h.

#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30)

top entry of the non-periodic Tx request queue

Definition at line 211 of file usb_regs.h.

#define HNPTFQSTAT_TMF BIT(24)

terminate flag

Definition at line 217 of file usb_regs.h.

#define HNPTFQSTAT_TYPE BITS(25, 26)

token type

Definition at line 216 of file usb_regs.h.

#define HPCS_PCD BIT(1)

port connect detected

Definition at line 272 of file usb_regs.h.

#define HPCS_PCST BIT(0)

port connect status

Definition at line 273 of file usb_regs.h.

#define HPCS_PE BIT(2)

port enable

Definition at line 271 of file usb_regs.h.

#define HPCS_PEDC BIT(3)

port enable/disable change

Definition at line 270 of file usb_regs.h.

#define HPCS_PLST BITS(10, 11)

port line status

Definition at line 266 of file usb_regs.h.

#define HPCS_PP BIT(12)

port power

Definition at line 265 of file usb_regs.h.

#define HPCS_PREM BIT(6)

port resume

Definition at line 269 of file usb_regs.h.

#define HPCS_PRST BIT(8)

port reset

Definition at line 267 of file usb_regs.h.

#define HPCS_PS BITS(17, 18)

port speed

Definition at line 264 of file usb_regs.h.

#define HPCS_PSP BIT(7)

port suspend

Definition at line 268 of file usb_regs.h.

#define HPTFLEN_HPTXFD BITS(16, 31)

host periodic Tx FIFO depth

Definition at line 230 of file usb_regs.h.

#define HPTFLEN_HPTXFSAR BITS(0, 15)

host periodic Tx RAM start address

Definition at line 231 of file usb_regs.h.

#define HPTFQSTAT_CNUM BITS(27, 30)

channel number

Definition at line 252 of file usb_regs.h.

#define HPTFQSTAT_EPNUM BITS(27, 30)

endpoint number

Definition at line 253 of file usb_regs.h.

#define HPTFQSTAT_OEFRM BIT(31)

odd/eveb frame

Definition at line 251 of file usb_regs.h.

#define HPTFQSTAT_PTXFS BITS(0, 15)

periodic Tx FIFO space

Definition at line 250 of file usb_regs.h.

#define HPTFQSTAT_PTXREQS BITS(16, 23)

periodic Tx request queue space

Definition at line 249 of file usb_regs.h.

#define HPTFQSTAT_PTXREQT BITS(24, 31)

top entry of the periodic Tx request queue

Definition at line 248 of file usb_regs.h.

#define HPTFQSTAT_TMF BIT(24)

terminate flag

Definition at line 255 of file usb_regs.h.

#define HPTFQSTAT_TYPE BITS(25, 26)

token type

Definition at line 254 of file usb_regs.h.

#define LOCATE_DIEPCTL ( x ) (0x900U + 0x20U * (x))

locate device IN endpoint-x control registers

Definition at line 26 of file usb_regs.h.

#define LOCATE_DIEPINTF ( x ) (0x908U + 0x20U * (x))

locate device IN endpoint-x interrupt flag registers

Definition at line 28 of file usb_regs.h.

#define LOCATE_DIEPLEN ( x ) (0x910U + 0x20U * (x))

locate device IN endpoint-x transfer length registers

Definition at line 30 of file usb_regs.h.

#define LOCATE_DIEPTFLEN ( x ) (0x104U + 4U * ((x) - 1U))

locate device IN endpoint-x (x = 1..3) transfer length registers

Definition at line 21 of file usb_regs.h.

#define LOCATE_DIEPxTFSTAT ( x ) (0x918U + 0x20U * (x))

locate Device IN endpoint-x transmit FIFO status register

Definition at line 32 of file usb_regs.h.

#define LOCATE_DOEPCTL ( x ) (0xB00U + 0x20U * (x))

locate device OUT endpoint-x control registers

Definition at line 27 of file usb_regs.h.

#define LOCATE_DOEPINTF ( x ) (0xB08U + 0x20U * (x))

locate device OUT endpoint-x interrupt flag registers

Definition at line 29 of file usb_regs.h.

#define LOCATE_DOEPLEN ( x ) (0xB10U + 0x20U * (x))

locate device OUT endpoint-x transfer length registers

Definition at line 31 of file usb_regs.h.

#define LOCATE_FIFO ( x ) (((x) + 1U) << 12U)

locate FIFO-x memory

Definition at line 33 of file usb_regs.h.

#define LOCATE_HCHCTL ( x ) (0x500U + 0x20U * (x))

locate host channel-x control registers

Definition at line 22 of file usb_regs.h.

#define LOCATE_HCHINTEN ( x ) (0x50CU + 0x20U * (x))

locate host channel-x interrupt enable registers

Definition at line 24 of file usb_regs.h.

#define LOCATE_HCHINTF ( x ) (0x508U + 0x20U * (x))

locate host channel-x interrupt flag registers

Definition at line 23 of file usb_regs.h.

#define LOCATE_HCHLEN ( x ) (0x510U + 0x20U * (x))

locate host channel-x transfer length registers

Definition at line 25 of file usb_regs.h.

#define PWRCLKCTL_SHCLK BIT(1)

stop HCLK

Definition at line 440 of file usb_regs.h.

#define PWRCLKCTL_SUCLK BIT(0)

stop the USB clock

Definition at line 441 of file usb_regs.h.

#define TXFIFO_EMPTY GAHBCS_TFEL(1U)

Tx FIFO completely empty

Definition at line 453 of file usb_regs.h.

#define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U)

Tx FIFO half empty

Definition at line 452 of file usb_regs.h.

#define USB_CID REG32(((USBFS) + 0x003CU))

core id register

Definition at line 50 of file usb_regs.h.

#define USB_CORE_INTR_READ ( x )
Value:
do { \
uint32_t global_intf = USB_GINTF; \
(x) = global_intf & USB_GINTEN; \
} while(0)
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:42
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:41

Definition at line 499 of file usb_regs.h.

#define USB_CURRENT_FRAME_GET ( ) (USB_HFINFR & 0xFFFFU)

Definition at line 572 of file usb_regs.h.

#define USB_CURRENT_MODE_GET ( ) (USB_GINTF & GINTF_COPM)

Definition at line 496 of file usb_regs.h.

#define USB_CURRENT_SPEED_GET ( ) ((USB_HPCS & HPCS_PS) >> 17)

Definition at line 569 of file usb_regs.h.

#define USB_DAEPINT REG32(((USBFS) + 0x0818U))

device all endpoints interrupt register

Definition at line 71 of file usb_regs.h.

#define USB_DAEPINTEN REG32(((USBFS) + 0x081CU))

device all endpoints interrupt enable register

Definition at line 72 of file usb_regs.h.

#define USB_DAIEP_INTR_READ ( x )
Value:
do { \
uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
uint32_t dev_all_ep_int = USB_DAEPINT; \
uint32_t in_ep_intb = DAEPINT_IEPITB; \
(x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \
} while(0)
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:72
USB_DAEPINT
#define USB_DAEPINT
Definition: usb_regs.h:71
DAEPINT_IEPITB
#define DAEPINT_IEPITB
Definition: usb_regs.h:359

Definition at line 522 of file usb_regs.h.

#define USB_DAOEP_INTR_READ ( x )
Value:
do { \
uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
uint32_t dev_all_ep_int = USB_DAEPINT; \
uint32_t out_ep_intb = DAEPINT_OEPITB; \
(x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \
} while(0)
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:72
USB_DAEPINT
#define USB_DAEPINT
Definition: usb_regs.h:71
DAEPINT_OEPITB
#define DAEPINT_OEPITB
Definition: usb_regs.h:358

Definition at line 506 of file usb_regs.h.

#define USB_DCFG REG32(((USBFS) + 0x0800U))

device configuration register

Definition at line 66 of file usb_regs.h.

#define USB_DCTL REG32(((USBFS) + 0x0804U))

device control register

Definition at line 67 of file usb_regs.h.

#define USB_DEP1INT REG32(((USBFS) + 0x0838U))

device endpoint 1 interrupt register

Definition at line 76 of file usb_regs.h.

#define USB_DEP1INTEN REG32(((USBFS) + 0x083CU))

device endpoint 1 interrupt enable register

Definition at line 77 of file usb_regs.h.

#define USB_DIEP0CTL REG32(((USBFS) + 0x0900U))

device IN endpoint 0 control register

Definition at line 80 of file usb_regs.h.

#define USB_DIEP0LEN REG32(((USBFS) + 0x0910U))

device IN endpoint 0 transfer length register

Definition at line 81 of file usb_regs.h.

#define USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U))

device IN endpoint 0 transmit FIFO length register

Definition at line 47 of file usb_regs.h.

#define USB_DIEP1INTEN REG32(((USBFS) + 0x0844U))

device IN endpoint 1 interrupt enable register

Definition at line 78 of file usb_regs.h.

#define USB_DIEP_INTR_READ | ( | x,
 |  | EpID
 | ) |
Value:
do { \
uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \
uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \
uint32_t dev_inep_inten = USB_DIEPINTEN; \
(x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \
} while(0)
USB_DIEPxINTF
#define USB_DIEPxINTF(x)
Definition: usb_regs.h:86
USB_DIEPINTEN
#define USB_DIEPINTEN
Definition: usb_regs.h:69
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:75

Definition at line 532 of file usb_regs.h.

#define USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U))

device IN endpoint FIFO empty interrupt enable register

Definition at line 75 of file usb_regs.h.

#define USB_DIEPINTEN REG32(((USBFS) + 0x0810U))

device IN endpoint common interrupt enable register

Definition at line 69 of file usb_regs.h.

#define USB_DIEPxCTL ( x ) REG32(((USBFS) + LOCATE_DIEPCTL(x)))

device IN endpoint-x control register

Definition at line 84 of file usb_regs.h.

#define USB_DIEPxINTF ( x ) REG32(((USBFS) + LOCATE_DIEPINTF(x)))

device IN endpoint-x interrupt flag register

Definition at line 86 of file usb_regs.h.

#define USB_DIEPxLEN ( x ) REG32(((USBFS) + LOCATE_DIEPLEN(x)))

device IN endpoint-x transfer length register

Definition at line 88 of file usb_regs.h.

#define USB_DIEPxTFLEN ( x ) REG32(((USBFS) + LOCATE_DIEPTFLEN(x)))

device IN endpoint transmit FIFO length register

Definition at line 52 of file usb_regs.h.

#define USB_DIEPxTFSTAT ( x ) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x)))

device IN endpoint-x transmit FIFO status register

Definition at line 90 of file usb_regs.h.

#define USB_DOEP0CTL REG32(((USBFS) + 0x0B00U))

device OUT endpoint 0 control register

Definition at line 82 of file usb_regs.h.

#define USB_DOEP0LEN REG32(((USBFS) + 0x0B10U))

device OUT endpoint 0 transfer length register

Definition at line 83 of file usb_regs.h.

#define USB_DOEP1INTEN REG32(((USBFS) + 0x0884U))

device OUT endpoint 1 interrupt enable register

Definition at line 79 of file usb_regs.h.

#define USB_DOEP_INTR_READ | ( | x,
 |  | EpID
 | ) |
Value:
do { \
uint32_t out_epintf = USB_DOEPxINTF(EpID); \
(x) = out_epintf & USB_DOEPINTEN; \
} while(0)
USB_DOEPINTEN
#define USB_DOEPINTEN
Definition: usb_regs.h:70
USB_DOEPxINTF
#define USB_DOEPxINTF(x)
Definition: usb_regs.h:87

Definition at line 515 of file usb_regs.h.

#define USB_DOEPINTEN REG32(((USBFS) + 0x0814U))

device OUT endpoint common interrupt enable register

Definition at line 70 of file usb_regs.h.

#define USB_DOEPxCTL ( x ) REG32(((USBFS) + LOCATE_DOEPCTL(x)))

device OUT endpoint-x control register

Definition at line 85 of file usb_regs.h.

#define USB_DOEPxINTF ( x ) REG32(((USBFS) + LOCATE_DOEPINTF(x)))

device OUT endpoint-x interrupt flag register

Definition at line 87 of file usb_regs.h.

#define USB_DOEPxLEN ( x ) REG32(((USBFS) + LOCATE_DOEPLEN(x)))

device OUT endpoint-x transfer length register

Definition at line 89 of file usb_regs.h.

#define USB_DSTAT REG32(((USBFS) + 0x0808U))

device status register

Definition at line 68 of file usb_regs.h.

#define USB_DVBUSDT REG32(((USBFS) + 0x0828U))

device vbus discharge time register

Definition at line 73 of file usb_regs.h.

#define USB_DVBUSPT REG32(((USBFS) + 0x082CU))

device vbus pulsing time register

Definition at line 74 of file usb_regs.h.

#define USB_EVEN_FRAME ( ) (!(USB_HFINFR & 0x01U))

Definition at line 556 of file usb_regs.h.

#define USB_FIFO ( x ) (&REG32(((USBFS) + LOCATE_FIFO(x))))

FIFO memory

Definition at line 94 of file usb_regs.h.

#define USB_FSLSCLOCK_INIT ( ClockFreq )
Value:
do { \
USB_HCTL &= ~HCTL_CLKSEL; \
USB_HCTL |= ClockFreq; \
} while(0)
USB_HCTL
#define USB_HCTL
Definition: usb_regs.h:54
HCTL_CLKSEL
#define HCTL_CLKSEL
Definition: usb_regs.h:238

Definition at line 562 of file usb_regs.h.

#define USB_GAHBCS REG32(((USBFS) + 0x0008U))

global AHB control and status register

Definition at line 38 of file usb_regs.h.

#define USB_GCCFG REG32(((USBFS) + 0x0038U))

global core configuration register

Definition at line 49 of file usb_regs.h.

#define USB_GINTEN REG32(((USBFS) + 0x0018U))

global interrupt enable register

Definition at line 42 of file usb_regs.h.

#define USB_GINTF REG32(((USBFS) + 0x0014U))

global interrupt flag register

Definition at line 41 of file usb_regs.h.

#define USB_GLOBAL_INT_DISABLE ( ) (USB_GAHBCS &= ~GAHBCS_GINTEN)

Definition at line 493 of file usb_regs.h.

#define USB_GLOBAL_INT_ENABLE ( ) (USB_GAHBCS |= GAHBCS_GINTEN)

Definition at line 490 of file usb_regs.h.

#define USB_GOTGCS REG32(((USBFS) + 0x0000U))

global OTG control and status register

Definition at line 36 of file usb_regs.h.

#define USB_GOTGINTF REG32(((USBFS) + 0x0004U))

global OTG interrupt flag register

Definition at line 37 of file usb_regs.h.

#define USB_GRFLEN REG32(((USBFS) + 0x0024U))

global receive FIFO length register

Definition at line 45 of file usb_regs.h.

#define USB_GRSTATP REG32(((USBFS) + 0x0020U))

global receive status read and pop register

Definition at line 44 of file usb_regs.h.

#define USB_GRSTATR REG32(((USBFS) + 0x001CU))

global receive status read register

Definition at line 43 of file usb_regs.h.

#define USB_GRSTCTL REG32(((USBFS) + 0x0010U))

global reset control register

Definition at line 40 of file usb_regs.h.

#define USB_GUSBCS REG32(((USBFS) + 0x000CU))

global USB control and status register

Definition at line 39 of file usb_regs.h.

#define USB_HACHINT REG32(((USBFS) + 0x0414U))

host all channels interrupt register

Definition at line 58 of file usb_regs.h.

#define USB_HACHINTEN REG32(((USBFS) + 0x0418U))

host all channels interrupt enable register

Definition at line 59 of file usb_regs.h.

#define USB_HCHxCTL ( x ) REG32(((USBFS) + LOCATE_HCHCTL(x)))

host channel-x control register

Definition at line 61 of file usb_regs.h.

#define USB_HCHxINTEN ( x ) REG32(((USBFS) + LOCATE_HCHINTEN(x)))

host channel-x interrupt enable register

Definition at line 63 of file usb_regs.h.

#define USB_HCHxINTF ( x ) REG32(((USBFS) + LOCATE_HCHINTF(x)))

host channel-x interrupt flag register

Definition at line 62 of file usb_regs.h.

#define USB_HCHxLEN ( x ) REG32(((USBFS) + LOCATE_HCHLEN(x)))

host channel-x tranfer length register

Definition at line 64 of file usb_regs.h.

#define USB_HCTL REG32(((USBFS) + 0x0400U))

host control register

Definition at line 54 of file usb_regs.h.

#define USB_HFINFR REG32(((USBFS) + 0x0408U))

host frame information remaining register

Definition at line 56 of file usb_regs.h.

#define USB_HFT REG32(((USBFS) + 0x0404U))

host frame interval register

Definition at line 55 of file usb_regs.h.

#define USB_HNPTFLEN REG32(((USBFS) + 0x0028U))

host non-periodic transmit FIFO length register

Definition at line 46 of file usb_regs.h.

#define USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU))

host non-periodic transmint FIFO/queue status register

Definition at line 48 of file usb_regs.h.

#define USB_HPCS REG32(((USBFS) + 0x0440U))

host port control and status register

Definition at line 60 of file usb_regs.h.

#define USB_HPTFLEN REG32(((USBFS) + 0x0100U))

host periodic transmit FIFO length register

Definition at line 51 of file usb_regs.h.

#define USB_HPTFQSTAT REG32(((USBFS) + 0x0410U))

host periodic transmit FIFO/queue status register

Definition at line 57 of file usb_regs.h.

#define USB_PORT_READ ( ) (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC))

Definition at line 559 of file usb_regs.h.

#define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U))

power and clock register

Definition at line 92 of file usb_regs.h.

#define USB_REMOTE_WAKEUP_RESET ( ) (USB_DCTL &= ~DCTL_RWKUP)

Definition at line 544 of file usb_regs.h.

#define USB_REMOTE_WAKEUP_SET ( ) (USB_DCTL |= DCTL_RWKUP)

Definition at line 541 of file usb_regs.h.

#define USB_SET_DEVADDR ( DevAddr ) (USB_DCFG |= (DevAddr) << 4U)

Definition at line 553 of file usb_regs.h.

#define USB_SOFT_DISCONNECT_DISABLE ( ) (USB_DCTL &= ~DCTL_SD)

Definition at line 550 of file usb_regs.h.

#define USB_SOFT_DISCONNECT_ENABLE ( ) (USB_DCTL |= DCTL_SD)

Definition at line 547 of file usb_regs.h.

#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U)

device external PHY full speed

Definition at line 447 of file usb_regs.h.

#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U)

device external PHY high speed

Definition at line 446 of file usb_regs.h.

#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U)

device internal PHY full speed

Definition at line 448 of file usb_regs.h.

#define USBFS USBFS_BASE

base address of USBFS registers

Definition at line 18 of file usb_regs.h.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Data Structures | Macros
usb_std.h File Reference

USB 2.0 standard defines. More...

#include "usb_conf.h"

Go to the source code of this file.

Data Structures

union | usb_setup_union
struct | usb_setup_union::_setup_packet_struct
struct | usb_descriptor_header_struct
struct | usb_descriptor_device_struct
struct | usb_descriptor_configuration_struct
struct | usb_descriptor_interface_struct
struct | usb_descriptor_endpoint_struct
struct | usb_descriptor_language_id_struct

Macros

#define | USB_DEV_QUALIFIER_DESC_LEN 0x0AU
#define | USB_DEV_DESC_LEN 0x12U
#define | USB_CFG_DESC_LEN 0x09U
#define | USB_IF_DESC_LEN 0x09U
#define | USB_EP_DESC_LEN 0x07U
#define | USB_OTG_DESC_LEN 0x03U
#define | USB_DIR_MASK 0x80U
#define | USB_DIR_OUT 0x00U
#define | USB_DIR_IN 0x80U
#define | USB_STANDARD_REQ 0x00U
#define | USB_CLASS_REQ 0x20U
#define | USB_VENDOR_REQ 0x40U
#define | USB_REQ_MASK 0x60U
#define | USB_REQTYPE_DEVICE 0x00U
#define | USB_REQTYPE_INTERFACE 0x01U
#define | USB_REQTYPE_ENDPOINT 0x02U
#define | USB_REQTYPE_MASK 0x03U
#define | USBREQ_GET_STATUS 0x00U
#define | USBREQ_CLEAR_FEATURE 0x01U
#define | USBREQ_SET_FEATURE 0x03U
#define | USBREQ_SET_ADDRESS 0x05U
#define | USBREQ_GET_DESCRIPTOR 0x06U
#define | USBREQ_SET_DESCRIPTOR 0x07U
#define | USBREQ_GET_CONFIGURATION 0x08U
#define | USBREQ_SET_CONFIGURATION 0x09U
#define | USBREQ_GET_INTERFACE 0x0AU
#define | USBREQ_SET_INTERFACE 0x0BU
#define | USBREQ_SYNCH_FRAME 0x0CU
#define | USB_DESCTYPE_DEVICE 0x01U
#define | USB_DESCTYPE_CONFIGURATION 0x02U
#define | USB_DESCTYPE_STRING 0x03U
#define | USB_DESCTYPE_INTERFACE 0x04U
#define | USB_DESCTYPE_ENDPOINT 0x05U
#define | USB_DESCTYPE_DEVICE_QUALIFIER 0x06U
#define | USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U
#define | USB_DESCTYPE_INTERFACE_POWER 0x08U
#define | USB_DESCTYPE_HID 0x21U
#define | USB_DESCTYPE_HID_REPORT 0x22U
#define | USB_DEVDESC_SIZE 18U
#define | USB_CFGDESC_SIZE 9U
#define | USB_INTDESC_SIZE 9U
#define | USB_EPDESC_SIZE 7U
#define | USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U)
#define | USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U)
#define | USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U)
#define | USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)
#define | USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)
#define | USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U)
#define | USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U)
#define | USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U)
#define | USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U)
#define | USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U)
#define | SWAPBYTE(addr)
#define | USB_MSC_CLASS 0x08U
#define | USB_HID_CLASS 0x03U
#define | HID_BOOT_CODE 0x01U
#define | HID_KEYBRD_BOOT_CODE 0x01U
#define | HID_MOUSE_BOOT_CODE 0x02U
#define | DATA_STAGE_TIMEOUT 5000U
#define | NODATA_STAGE_TIMEOUT 50U
#define | USBH_CFG_DESC_SET_SIZE

Detailed Description

USB 2.0 standard defines.

Definition in file usb_std.h.

Macro Definition Documentation

#define DATA_STAGE_TIMEOUT 5000U

USB data stage timeout

Definition at line 100 of file usb_std.h.

#define HID_BOOT_CODE 0x01U

USB HID boot code

Definition at line 94 of file usb_std.h.

#define HID_KEYBRD_BOOT_CODE 0x01U

USB HID keyboard boot code

Definition at line 95 of file usb_std.h.

#define HID_MOUSE_BOOT_CODE 0x02U

USB HID mouse boot code

Definition at line 96 of file usb_std.h.

#define NODATA_STAGE_TIMEOUT 50U

USB no data stage timeout

Definition at line 101 of file usb_std.h.

#define SWAPBYTE ( addr )
Value:
(((uint16_t)(*((uint8_t *)(addr)))) + \
(uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))

Definition at line 86 of file usb_std.h.

#define USB_CFG_DESC_LEN 0x09U

USB device configuration descriptor length

Definition at line 20 of file usb_std.h.

#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U)

USB configuration operation marco

Definition at line 76 of file usb_std.h.

#define USB_CFGDESC_SIZE 9U

USB configure descriptor size

Definition at line 69 of file usb_std.h.

#define USB_CLASS_REQ 0x20U

USB class request

Definition at line 32 of file usb_std.h.

#define USB_DESCTYPE_CONFIGURATION 0x02U

USB configuration descriptor type

Definition at line 57 of file usb_std.h.

#define USB_DESCTYPE_DEVICE 0x01U

USB device descriptor type

Definition at line 56 of file usb_std.h.

#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U

USB device qualtfier descriptor type

Definition at line 61 of file usb_std.h.

#define USB_DESCTYPE_ENDPOINT 0x05U

USB endpoint descriptor type

Definition at line 60 of file usb_std.h.

#define USB_DESCTYPE_HID 0x21U

USB HID descriptor type

Definition at line 65 of file usb_std.h.

#define USB_DESCTYPE_HID_REPORT 0x22U

USB HID report descriptor type

Definition at line 66 of file usb_std.h.

#define USB_DESCTYPE_INTERFACE 0x04U

USB interface descriptor type

Definition at line 59 of file usb_std.h.

#define USB_DESCTYPE_INTERFACE_POWER 0x08U

USB interface power descriptor type

Definition at line 63 of file usb_std.h.

#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U

USB other speed configuration descriptor type

Definition at line 62 of file usb_std.h.

#define USB_DESCTYPE_STRING 0x03U

USB string descriptor type

Definition at line 58 of file usb_std.h.

#define USB_DEV_DESC_LEN 0x12U

USB device descriptor length

Definition at line 19 of file usb_std.h.

#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU

USB device qualifier descriptor length

Definition at line 18 of file usb_std.h.

#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U)

USB device operation marco

Definition at line 75 of file usb_std.h.

#define USB_DEVDESC_SIZE 18U

USB device descriptor size

Definition at line 68 of file usb_std.h.

#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U)

USB device qualifier operation marco

Definition at line 80 of file usb_std.h.

#define USB_DIR_IN 0x80U

USB transfer IN direction

Definition at line 28 of file usb_std.h.

#define USB_DIR_MASK 0x80U

USB transfer direction mask

Definition at line 26 of file usb_std.h.

#define USB_DIR_OUT 0x00U

USB transfer OUT direction

Definition at line 27 of file usb_std.h.

#define USB_EP_DESC_LEN 0x07U

USB device endpoint descriptor length

Definition at line 22 of file usb_std.h.

#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)

USB endpoint operation marco

Definition at line 79 of file usb_std.h.

#define USB_EPDESC_SIZE 7U

USB endpoint descriptor size

Definition at line 71 of file usb_std.h.

#define USB_HID_CLASS 0x03U

USB HID class

Definition at line 91 of file usb_std.h.

#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U)

USB HID operation marco

Definition at line 84 of file usb_std.h.

#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U)

USB HID report operation marco

Definition at line 83 of file usb_std.h.

#define USB_IF_DESC_LEN 0x09U

USB device interface descriptor length

Definition at line 21 of file usb_std.h.

#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)

USB interface operation marco

Definition at line 78 of file usb_std.h.

#define USB_INTDESC_SIZE 9U

USB interface descriptor size

Definition at line 70 of file usb_std.h.

#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U)

USB interface power operation marco

Definition at line 82 of file usb_std.h.

#define USB_MSC_CLASS 0x08U

USB MSC class

Definition at line 90 of file usb_std.h.

#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U)

USB other speed configuration operation marco

Definition at line 81 of file usb_std.h.

#define USB_OTG_DESC_LEN 0x03U

USB device OTG descriptor length

Definition at line 23 of file usb_std.h.

#define USB_REQ_MASK 0x60U

USB request mask

Definition at line 34 of file usb_std.h.

#define USB_REQTYPE_DEVICE 0x00U

USB device request type

Definition at line 37 of file usb_std.h.

#define USB_REQTYPE_ENDPOINT 0x02U

USB endpoint request type

Definition at line 39 of file usb_std.h.

#define USB_REQTYPE_INTERFACE 0x01U

USB interface request type

Definition at line 38 of file usb_std.h.

#define USB_REQTYPE_MASK 0x03U

USB request type mask

Definition at line 40 of file usb_std.h.

#define USB_STANDARD_REQ 0x00U

USB standard request

Definition at line 31 of file usb_std.h.

#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U)

USB string operation marco

Definition at line 77 of file usb_std.h.

#define USB_VENDOR_REQ 0x40U

USB vebdor request

Definition at line 33 of file usb_std.h.

#define USBH_CFG_DESC_SET_SIZE
Value:
(USB_CFGDESC_SIZE + USB_INTDESC_SIZE \
+ (USBH_MAX_EP_NUM * USB_EPDESC_SIZE))
USB_EPDESC_SIZE
#define USB_EPDESC_SIZE
Definition: usb_std.h:71
USB_INTDESC_SIZE
#define USB_INTDESC_SIZE
Definition: usb_std.h:70
USB_CFGDESC_SIZE
#define USB_CFGDESC_SIZE
Definition: usb_std.h:69

USB host set configuration descriptor size

Definition at line 103 of file usb_std.h.

#define USBREQ_CLEAR_FEATURE 0x01U

USB clear feature request

Definition at line 44 of file usb_std.h.

#define USBREQ_GET_CONFIGURATION 0x08U

USB get configuration request

Definition at line 49 of file usb_std.h.

#define USBREQ_GET_DESCRIPTOR 0x06U

USB get descriptor request

Definition at line 47 of file usb_std.h.

#define USBREQ_GET_INTERFACE 0x0AU

USB get interface request

Definition at line 51 of file usb_std.h.

#define USBREQ_GET_STATUS 0x00U

USB get status request

Definition at line 43 of file usb_std.h.

#define USBREQ_SET_ADDRESS 0x05U

USB set address request

Definition at line 46 of file usb_std.h.

#define USBREQ_SET_CONFIGURATION 0x09U

USB set configuration request

Definition at line 50 of file usb_std.h.

#define USBREQ_SET_DESCRIPTOR 0x07U

USB set descriptor request

Definition at line 48 of file usb_std.h.

#define USBREQ_SET_FEATURE 0x03U

USB set feature request

Definition at line 45 of file usb_std.h.

#define USBREQ_SET_INTERFACE 0x0BU

USB set interface request

Definition at line 52 of file usb_std.h.

#define USBREQ_SYNCH_FRAME 0x0CU

USB synchronize frame request

Definition at line 53 of file usb_std.h.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbd_core.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Macros | Functions
usbd_core.h File Reference
#include "usbd_conf.h"
#include "usb_core.h"
#include "usbd_std.h"

Go to the source code of this file.

Macros

#define | USB_STATUS_DEFAULT 1U /* default status */
#define | USB_STATUS_ADDRESSED 2U /* addressed status */
#define | USB_STATUS_CONFIGURED 3U /* configured status */
#define | USB_STATUS_SUSPENDED 4U /* suspended status */

Functions

void | usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initailizes the USB device-mode handler stack More...
void | usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc)
endpoint initialization More...
void | usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr)
endpoint deinitialize More...
void | usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data More...
void | usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data More...
usbd_status_enum | usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel More...
usbd_status_enum | usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
receive data on the control channel More...
usbd_status_enum | usbd_ctlstatus_tx (usb_core_handle_struct *pudev)
transmit status on the control channel More...
usbd_status_enum | usbd_ctlstatus_rx (usb_core_handle_struct *pudev)
receive status on the control channel More...
void | usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status More...
void | usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status More...
void | usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr)
flushes the FIFOs More...
uint16_t | usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num)
get the received data length More...

Macro Definition Documentation

#define USB_STATUS_ADDRESSED 2U /* addressed status */

Definition at line 22 of file usbd_core.h.

#define USB_STATUS_CONFIGURED 3U /* configured status */

Definition at line 23 of file usbd_core.h.

#define USB_STATUS_DEFAULT 1U /* default status */

Definition at line 21 of file usbd_core.h.

#define USB_STATUS_SUSPENDED 4U /* suspended status */

Definition at line 24 of file usbd_core.h.

Function Documentation

usbd_status_enum usbd_ctlrx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | pbuf,
 |  | uint16_t | len
 | ) |  |

receive data on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
usb device operation status

Definition at line 334 of file usbd_core.c.

335 {
336 pudev->dev.sum_len = len;
337 pudev->dev.remain_len = len;
338 pudev->dev.ctl_status = USB_CTRL_DATA_OUT;
339
340 usbd_ep_rx (pudev, 0U, pbuf, len);
341
342 return USBD_OK;
343 }
USB_CTRL_DATA_OUT
Definition: usb_core.h:86
USBD_OK
Definition: usbd_core.h:84
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usbd_status_enum usbd_ctlstatus_rx ( usb_core_handle_struct * pudev )

receive status on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
usb device operation status

Definition at line 368 of file usbd_core.c.

369 {
370 pudev->dev.ctl_status = USB_CTRL_STATUS_OUT;
371
372 usbd_ep_rx (pudev, 0U, NULL, 0U);
373
374 usb_ep0_startout(pudev);
375
376 return USBD_OK;
377 }
USB_CTRL_STATUS_OUT
Definition: usb_core.h:88
USBD_OK
Definition: usbd_core.h:84
NULL
#define NULL
Definition: usbd_std.h:20
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usbd_status_enum usbd_ctlstatus_tx ( usb_core_handle_struct * pudev )

transmit status on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
usb device operation status

Definition at line 351 of file usbd_core.c.

352 {
353 pudev->dev.ctl_status = USB_CTRL_STATUS_IN;
354
355 usbd_ep_tx (pudev, 0U, NULL, 0U);
356
357 usb_ep0_startout(pudev);
358
359 return USBD_OK;
360 }
USB_CTRL_STATUS_IN
Definition: usb_core.h:87
USBD_OK
Definition: usbd_core.h:84
NULL
#define NULL
Definition: usbd_std.h:20
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
usbd_status_enum usbd_ctltx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | pbuf,
 |  | uint16_t | len
 | ) |  |

transmit data on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
usb device operation status

Definition at line 313 of file usbd_core.c.

314 {
315 usbd_status_enum ret = USBD_OK;
316
317 pudev->dev.sum_len = len;
318 pudev->dev.remain_len = len;
319 pudev->dev.ctl_status = USB_CTRL_DATA_IN;
320
321 usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len);
322
323 return ret;
324 }
USB_CTRL_DATA_IN
Definition: usb_core.h:85
USBD_OK
Definition: usbd_core.h:84
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
void usbd_ep_clear_stall | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

clear endpoint stalled status

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 416 of file usbd_core.c.

417 {
418 usb_ep_struct *ep;
419 uint8_t ep_num = ep_addr & 0x7FU;
420 __IO uint32_t devepctl = 0U;
421
422 if(ep_addr >> 7){
423 ep = &pudev->dev.in_ep[ep_num];
424
425 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
426
427 /* clear the IN endpoint stall bits */
428 devepctl &= ~DEPCTL_STALL;
429
430 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
431 devepctl |= DEPCTL_SEVNFRM;
432 }
433
434 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
435 } else {
436 ep = &pudev->dev.out_ep[ep_num];
437
438 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
439
440 /* clear the OUT endpoint stall bits */
441 devepctl &= ~DEPCTL_STALL;
442
443 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
444 devepctl |= DEPCTL_SEVNFRM;
445 }
446
447 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
448 }
449 }
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:55
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
usb_ep_struct
Definition: usbd_core.h:102
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:396
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:391
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:54
void usbd_ep_deinit | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

endpoint deinitialize

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 134 of file usbd_core.c.

135 {
136 uint32_t devepinten = 0U;
137 uint8_t ep_num = ep_addr & 0x7FU;
138
139 if (ep_addr >> 7) {
140 devepinten |= 1U << ep_num;
141
142 USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
143 } else {
144 devepinten |= (1U << ep_num) << 16U;
145
146 USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
147 }
148
149 /* disable the interrupts for this endpoint */
150 USB_DAEPINTEN &= ~devepinten;
151 }
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:72
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:402
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
void usbd_ep_fifo_flush | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

flushes the FIFOs

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 458 of file usbd_core.c.

459 {
460 if (ep_addr >> 7) {
461 usb_txfifo_flush(pudev, ep_addr & 0x7FU);
462 } else {
463 usb_rxfifo_flush(pudev);
464 }
465 }
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:211
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:238
void usbd_ep_init | ( | usb_core_handle_struct * | pudev,
 |  | const usb_descriptor_endpoint_struct * | ep_desc
 | ) |  |

endpoint initialization

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_desc | pointer to usb endpoint descriptor
[out] | none
Return values
none

Definition at line 67 of file usbd_core.c.

68 {
69 usb_ep_struct *ep;
70 usb_dir_enum ep_dir;
71
72 uint32_t devepinten = 0U;
73 uint32_t devepctl = 0U;
74
75 uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU;
76 uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK;
77 uint16_t ep_mps = ep_desc->wMaxPacketSize;
78
79 if (ep_desc->bEndpointAddress >> 7) {
80 ep = &pudev->dev.in_ep[ep_num];
81
82 devepinten |= 1U << ep_num;
83 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
84
85 ep_dir = USB_TX;
86 } else {
87 ep = &pudev->dev.out_ep[ep_num];
88
89 devepinten |= (1U << ep_num) << 16;
90 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
91
92 ep_dir = USB_RX;
93 }
94
95 /* if the endpoint is not active, need change the endpoint control register */
96 if (!(devepctl & DEPCTL_EPACT)) {
97 devepctl &= ~DEPCTL_MPL;
98 devepctl |= ep_mps;
99
100 devepctl &= ~DEPCTL_EPTYPE;
101 devepctl |= (uint32_t)ep_type << 18;
102
103 if (USB_TX == ep_dir) {
104 devepctl &= ~DIEPCTL_TXFNUM;
105 devepctl |= (uint32_t)ep_num << 22;
106 }
107
108 devepctl |= DEPCTL_SD0PID;
109 devepctl |= DEPCTL_EPACT;
110 }
111
112 if (USB_TX == ep_dir) {
113 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
114 } else if (USB_RX == ep_dir) {
115 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
116 } else {
117 /* no operation */
118 }
119
120 ep->endp_mps = ep_mps;
121 ep->endp_type = ep_type;
122
123 /* enable the interrupts for this endpoint */
124 USB_DAEPINTEN |= devepinten;
125 }
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:162
USB_TX
Definition: usb_core.h:96
DEPCTL_EPTYPE
#define DEPCTL_EPTYPE
Definition: usb_regs.h:398
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:72
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usbd_std.h:161
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:402
USB_RX
Definition: usb_core.h:95
usb_ep_struct
Definition: usbd_core.h:102
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:93
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
DEPCTL_MPL
#define DEPCTL_MPL
Definition: usb_regs.h:403
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usbd_std.h:163
DIEPCTL_TXFNUM
#define DIEPCTL_TXFNUM
Definition: usb_regs.h:395
USB_EPTYPE_MASK
#define USB_EPTYPE_MASK
Definition: usbd_std.h:73
DEPCTL_SD0PID
#define DEPCTL_SD0PID
Definition: usb_regs.h:392
void usbd_ep_rx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint16_t | buf_len
 | ) |  |

endpoint prepare to receive data

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[in] | pbuf | pointer to buffer
[in] | buf_len | buffer length
[out] | none
Return values
none

Definition at line 162 of file usbd_core.c.

163 {
164 usb_ep_struct *ep;
165 uint8_t ep_num = ep_addr & 0x7FU;
166 uint32_t devepctl = 0U, devepxlen = 0U;
167
168 ep = &pudev->dev.out_ep[ep_num];
169
170 /* setup and start the Xfer */
171 ep->xfer_buff = pbuf;
172 ep->xfer_len = buf_len;
173 ep->xfer_count = 0U;
174
175 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
176 devepxlen = USB_DOEPxLEN((uint16_t)ep_num);
177
178 devepxlen &= ~DEPLEN_TLEN;
179 devepxlen &= ~DEPLEN_PCNT;
180
181 /* zero length packet */
182 if (0U == ep->xfer_len) {
183 /* set the transfer length to max packet size */
184 devepxlen |= ep->endp_mps;
185
186 /* set the transfer packet count to 1 */
187 devepxlen |= 1U << 19U;
188 } else {
189
190 if (0U == ep_num) {
191 /* set the transfer length to max packet size */
192 devepxlen |= ep->endp_mps;
193
194 /* set the transfer packet count to 1 */
195 devepxlen |= 1U << 19U;
196 } else {
197 /* configure the transfer size and packet count as follows:
198 * pktcnt = N
199 * xfersize = N * maxpacket
200 */
201 devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U;
202 devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps;
203 }
204 }
205
206 USB_DOEPxLEN((uint16_t)ep_num) = devepxlen;
207
208 if (USB_EPTYPE_ISOC == ep->endp_type) {
209 if (ep->endp_frame) {
210 devepctl |= DEPCTL_SODDFRM;
211 } else {
212 devepctl |= DEPCTL_SEVNFRM;
213 }
214 }
215
216 /* enable the endpoint and clear the NAK */
217 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
218
219 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
220 }
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:53
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:109
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:387
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:108
usb_ep_struct::endp_frame
uint8_t endp_frame
Definition: usb_core.h:103
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:434
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:433
usb_ep_struct
Definition: usbd_core.h:102
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:89
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:394
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:391
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:389
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
void usbd_ep_stall | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

set an endpoint to STALL status

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 386 of file usbd_core.c.

387 {
388 uint8_t ep_num = ep_addr & 0x7FU;
389 __IO uint32_t devepctl = 0U;
390
391 if (ep_addr >> 7U) {
392 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
393
394 /* set the endpoint disable bit */
395 if (devepctl & DEPCTL_EPEN) {
396 devepctl |= DEPCTL_EPD;
397 }
398
399 /* set the endpoint stall bit */
400 devepctl |= DEPCTL_STALL;
401
402 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
403 } else {
404 /* set the endpoint stall bit */
405 USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL;
406 }
407 }
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:387
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:388
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:396
void usbd_ep_tx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint32_t | buf_len
 | ) |  |

endpoint prepare to transmit data

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
none

Definition at line 231 of file usbd_core.c.

232 {
233 usb_ep_struct *ep;
234 uint8_t ep_num = ep_addr & 0x7FU;
235 __IO uint32_t devepctl = 0U;
236 __IO uint32_t deveplen = 0U;
237
238 ep = &pudev->dev.in_ep[ep_num];
239
240 /* setup and start the transfer */
241 ep->xfer_buff = pbuf;
242 ep->xfer_len = buf_len;
243 ep->xfer_count = 0U;
244
245 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
246 deveplen = USB_DIEPxLEN((uint16_t)ep_num);
247
248 /* clear transfer length to 0 */
249 deveplen &= ~DEPLEN_TLEN;
250
251 /* clear transfer packet to 0 */
252 deveplen &= ~DEPLEN_PCNT;
253
254 /* zero length packet */
255 if (0U == ep->xfer_len) {
256 /* set transfer packet count to 1 */
257 deveplen |= 1U << 19U;
258 } else {
259 if (0U == ep_num) {
260 if (ep->xfer_len > ep->endp_mps) {
261 ep->xfer_len = ep->endp_mps;
262 }
263
264 deveplen |= 1U << 19U;
265 } else {
266 deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U;
267 }
268
269 /* configure the transfer size and packet count as follows:
270 * xfersize = N * maxpacket + short_packet
271 * pktcnt = N + (short_packet exist ? 1 : 0)
272 */
273 deveplen |= ep->xfer_len;
274
275 if (USB_EPTYPE_ISOC == ep->endp_type) {
276 deveplen |= DIEPLEN_MCNT & (1U << 29U);
277 }
278 }
279
280 USB_DIEPxLEN((uint16_t)ep_num) = deveplen;
281
282 if (USB_EPTYPE_ISOC == ep->endp_type) {
283 if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) {
284 devepctl |= DEPCTL_SODDFRM;
285 } else {
286 devepctl |= DEPCTL_SEVNFRM;
287 }
288 }
289
290 /* enable the endpoint and clear the NAK */
291 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
292
293 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
294
295 if (USB_EPTYPE_ISOC != ep->endp_type) {
296 /* enable the Tx FIFO empty interrupt for this endpoint */
297 if (ep->xfer_len > 0U) {
298 USB_DIEPFEINTEN |= 1U << ep_num;
299 }
300 } else {
301 usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len);
302 }
303 }
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:53
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:109
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:387
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:82
DIEPLEN_MCNT
#define DIEPLEN_MCNT
Definition: usb_regs.h:432
USB_DIEPxLEN
#define USB_DIEPxLEN(x)
Definition: usb_regs.h:88
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:108
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:434
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:433
usb_ep_struct
Definition: usbd_core.h:102
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:68
DSTAT_FNRSOF
#define DSTAT_FNRSOF
Definition: usb_regs.h:338
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:75
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:394
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:391
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:389
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
void usbd_init | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initailizes the USB device-mode handler stack

Parameters
[in] | pudev | pointer to usb device instance
[in] | core_id | USB core ID
[out] | none
Return values
none

Definition at line 23 of file usbd_core.c.

24 {
25 /* select USB core */
26 usb_core_select (pudev, core_id);
27
28 pudev->dev.status = USB_STATUS_DEFAULT;
29
30 /* disable USB global interrupt */
31 USB_GLOBAL_INT_DISABLE();
32
33 /* init the core (common init.) */
34 usb_core_init(pudev);
35
36 /* force device mode*/
37 usb_mode_set(pudev, DEVICE_MODE);
38
39 /* set device disconnect */
40 USB_SOFT_DISCONNECT_ENABLE();
41
42 if ((void *)0 != pudev->mdelay) {
43 pudev->mdelay(3U);
44 }
45
46 /* init device */
47 usb_devcore_init(pudev);
48
49 /* set device Connect */
50 USB_SOFT_DISCONNECT_DISABLE();
51
52 if ((void *)0 != pudev->mdelay) {
53 pudev->mdelay(3U);
54 }
55
56 /* enable USB global interrupt */
57 USB_GLOBAL_INT_ENABLE();
58 }
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:128
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:268
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:21
USB_SOFT_DISCONNECT_DISABLE
#define USB_SOFT_DISCONNECT_DISABLE()
Definition: usb_regs.h:550
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:493
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:490
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:170
USB_SOFT_DISCONNECT_ENABLE
#define USB_SOFT_DISCONNECT_ENABLE()
Definition: usb_regs.h:547
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:48
uint16_t usbd_rxcount_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

get the received data length

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_num | endpoint identifier which is in (0..3)
[out] | none
Return values
received data length

Definition at line 474 of file usbd_core.c.

475 {
476 return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count;
477 }


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbd_int.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Data Structures | Functions | Variables
usbd_int.h File Reference
#include "usbd_core.h"

Go to the source code of this file.

Data Structures

struct usbd_int_cb_struct

Functions

uint32_t usbd_isr (usb_core_handle_struct *pudev)
USB device-mode interrupts global service routine handler. More...

Variables

usbd_int_cb_struct * usbd_int_fops

Function Documentation

uint32_t usbd_isr ( usb_core_handle_struct * pudev )

USB device-mode interrupts global service routine handler.

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
operation status

Definition at line 58 of file usbd_int.c.

59 {
60 uint32_t retval = 0U;
61 uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN;
62
63 /* ensure the core is in device mode */
64 if (DEVICE_MODE == USB_CURRENT_MODE_GET()) {
65 int_status = gintf & ginten;
66
67 /* there are no interrupts, avoid spurious interrupt */
68 if (!int_status) {
69 return 0U;
70 }
71
72 /* OUT endpoints interrupts */
73 if (int_status & GINTF_OEPIF) {
74 retval |= usbd_intf_outep(pudev);
75 }
76
77 /* IN endpoints interrupts */
78 if (int_status & GINTF_IEPIF) {
79 retval |= usbd_intf_inep(pudev);
80 }
81
82 /* mode mismatch interrupt */
83 if (int_status & GINTF_MFIF) {
84 /* clear interrupt */
85 USB_GINTF = GINTF_MFIF;
86 }
87
88 /* early suspend interrupt */
89 if (int_status & GINTF_ESP) {
90 retval |= usbd_intf_earlysuspend(pudev);
91 }
92
93 /* suspend interrupt */
94 if (int_status & GINTF_SP) {
95 retval |= usbd_intf_suspend(pudev);
96 }
97
98 /* wakeup interrupt */
99 if (int_status & GINTF_WKUPIF) {
100 retval |= usbd_intf_resume(pudev);
101 }
102
103 /* start of frame interrupt */
104 if (int_status & GINTF_SOF) {
105 retval |= usbd_intf_sof(pudev);
106 }
107
108 /* reveive fifo not empty interrupt */
109 if (int_status & GINTF_RXFNEIF) {
110 retval |= usbd_intf_rxfifo(pudev);
111 }
112
113 /* USB reset interrupt */
114 if (int_status & GINTF_RST) {
115 retval |= usbd_intf_reset(pudev);
116 }
117
118 /* enumeration has been finished interrupt */
119 if (int_status & GINTF_ENUMF) {
120 retval |= usbd_intf_enumfinish(pudev);
121 }
122
123 /* incomplete synchronization in transfer interrupt*/
124 if (int_status & GINTF_ISOINCIF) {
125 retval |= usbd_intf_isoinincomplete(pudev);
126 }
127
128 /* incomplete synchronization out transfer interrupt*/
129 if (int_status & GINTF_ISOONCIF) {
130 retval |= usbd_intf_isooutincomplete(pudev);
131 }
132
133 #ifdef VBUS_SENSING_ENABLED
134
135 /* session request interrupt */
136 if (int_status & GINTF_SESIF) {
137 retval |= usbd_intf_sessionrequest(pudev);
138 }
139
140 /* OTG mode interrupt */
141 if (int_status & GINTF_OTGIF) {
142 retval |= usbd_intf_otg(pudev);
143 }
144 #endif /* VBUS_SENSING_ENABLED */
145 }
146
147 return retval;
148 }
GINTF_IEPIF
#define GINTF_IEPIF
Definition: usb_regs.h:149
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:159
GINTF_ISOINCIF
#define GINTF_ISOINCIF
Definition: usb_regs.h:147
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:42
GINTF_SESIF
#define GINTF_SESIF
Definition: usb_regs.h:139
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:41
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:496
GINTF_OEPIF
#define GINTF_OEPIF
Definition: usb_regs.h:148
GINTF_ESP
#define GINTF_ESP
Definition: usb_regs.h:155
GINTF_OTGIF
#define GINTF_OTGIF
Definition: usb_regs.h:161
GINTF_SP
#define GINTF_SP
Definition: usb_regs.h:154
GINTF_WKUPIF
#define GINTF_WKUPIF
Definition: usb_regs.h:138
GINTF_RST
#define GINTF_RST
Definition: usb_regs.h:153
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:146
GINTF_ENUMF
#define GINTF_ENUMF
Definition: usb_regs.h:152
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:160
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:48
GINTF_MFIF
#define GINTF_MFIF
Definition: usb_regs.h:162

Variable Documentation

usbd_int_cb_struct* usbd_int_fops


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbd_std.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Macros | Functions
usbd_std.h File Reference
#include "usb_std.h"
#include "usbd_core.h"
#include "usbd_conf.h"
#include <wchar.h>

Go to the source code of this file.

Macros

#define | USBD_LANGID_STR_IDX 0x00U
#define | USBD_MFC_STR_IDX 0x01U
#define | USBD_PRODUCT_STR_IDX 0x02U
#define | USBD_SERIAL_STR_IDX 0x03U
#define | USBD_CONFIG_STR_IDX 0x04U
#define | USBD_INTERFACE_STR_IDX 0x05U
#define | USB_STATUS_REMOTE_WAKEUP 0x02U
#define | USB_STATUS_SELF_POWERED 0x01U
#define | USB_FEATURE_ENDP_HALT 0x00U
#define | USB_FEATURE_REMOTE_WAKEUP 0x01U
#define | USB_FEATURE_TEST_MODE 0x02U
#define | ENG_LANGID 0x0409U
#define | CHN_LANGID 0x0804U
#define | USB_DEVICE_DESC_SIZE 0x12U
#define | LOWBYTE(x) ((uint8_t)((x) & 0x00FFU))
#define | HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))
#define | USB_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | WIDE_STRING(string) _WIDE_STRING(string)
#define | _WIDE_STRING(string) L##string
#define | USBD_STRING_DESC(string)
#define | IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))

Functions

usbd_status_enum | usbd_setup_transaction (usb_core_handle_struct *pudev)
USB setup stage processing. More...
usbd_status_enum | usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
data out stage processing More...
usbd_status_enum | usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
data in stage processing More...
void | usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB low level error event More...

Macro Definition Documentation

#define _WIDE_STRING ( string ) L##string

Definition at line 46 of file usbd_std.h.

#define CHN_LANGID 0x0804U

USB chinese language id

Definition at line 36 of file usbd_std.h.

#define ENG_LANGID 0x0409U

USB english language id

Definition at line 35 of file usbd_std.h.

#define HIGHBYTE ( x ) ((uint8_t)(((x) & 0xFF00U) >> 8U))

USB highbyte operation marco

Definition at line 41 of file usbd_std.h.

#define IS_NOT_EP0 ( ep_addr ) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))

Definition at line 59 of file usbd_std.h.

#define LOWBYTE ( x ) ((uint8_t)((x) & 0x00FFU))

USB lowbyte operation marco

Definition at line 40 of file usbd_std.h.

#define USB_DEVICE_DESC_SIZE 0x12U

USB device descriptor size

Definition at line 38 of file usbd_std.h.

#define USB_FEATURE_ENDP_HALT 0x00U

USB halt endpoint feature

Definition at line 31 of file usbd_std.h.

#define USB_FEATURE_REMOTE_WAKEUP 0x01U

USB remote wakeup feature

Definition at line 32 of file usbd_std.h.

#define USB_FEATURE_TEST_MODE 0x02U

USB test mode feature

Definition at line 33 of file usbd_std.h.

#define USB_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

USB minimum operation marco

Definition at line 43 of file usbd_std.h.

#define USB_STATUS_REMOTE_WAKEUP 0x02U

USB remote wakeup status

Definition at line 28 of file usbd_std.h.

#define USB_STATUS_SELF_POWERED 0x01U

USB self power status

Definition at line 29 of file usbd_std.h.

#define USBD_CONFIG_STR_IDX 0x04U

USB configuration string index

Definition at line 25 of file usbd_std.h.

#define USBD_INTERFACE_STR_IDX 0x05U

USB interface string index

Definition at line 26 of file usbd_std.h.

#define USBD_LANGID_STR_IDX 0x00U

USB language ID string index

Definition at line 21 of file usbd_std.h.

#define USBD_MFC_STR_IDX 0x01U

USB manufacturer string index

Definition at line 22 of file usbd_std.h.

#define USBD_PRODUCT_STR_IDX 0x02U

USB product string index

Definition at line 23 of file usbd_std.h.

#define USBD_SERIAL_STR_IDX 0x03U

USB serial string index

Definition at line 24 of file usbd_std.h.

#define USBD_STRING_DESC ( string )
Value:
(uint8_t *)&(struct { \
uint8_t _len; \
uint8_t _type; \
wchar_t _data[sizeof(string)]; \
}) { \
sizeof(WIDE_STRING(string)) + 2U - 2U, \
USB_DESCTYPE_STRING, \
WIDE_STRING(string) \
}
WIDE_STRING
#define WIDE_STRING(string)
Definition: usbd_std.h:45
USB_DESCTYPE_STRING
#define USB_DESCTYPE_STRING
Definition: usbd_std.h:56

Definition at line 48 of file usbd_std.h.

#define WIDE_STRING ( string ) _WIDE_STRING(string)

Definition at line 45 of file usbd_std.h.

Function Documentation

void usbd_enum_error | ( | usb_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB low level error event

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
none

Definition at line 689 of file usbd_std.c.

690 {
691 usbd_ep_stall(pudev, 0x80U);
692 usbd_ep_stall(pudev, 0x00U);
693 usb_ep0_startout(pudev);
694 }
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usbd_status_enum usbd_in_transaction | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | endp_num
 | ) |  |

data in stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_id | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 143 of file usbd_std.c.

144 {
145 usb_ep_struct *ep;
146
147 if (0U == endp_num) {
148 ep = &pudev->dev.in_ep[0];
149
150 if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) {
151 if (pudev->dev.remain_len > ep->endp_mps) {
152 pudev->dev.remain_len -= ep->endp_mps;
153
154 usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len);
155
156 usbd_ep_rx (pudev, 0U, NULL, 0U);
157 } else {
158 /* last packet is MPS multiple, so send ZLP packet */
159 if ((pudev->dev.sum_len % ep->endp_mps == 0U) &&
160 (pudev->dev.sum_len >= ep->endp_mps) &&
161 (pudev->dev.sum_len < pudev->dev.ctl_len)) {
162 usbd_ep_tx (pudev, 0U, NULL, 0U);
163 pudev->dev.ctl_len = 0U;
164
165 usbd_ep_rx (pudev, 0U, NULL, 0U);
166 } else {
167 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
168 pudev->dev.class_data_handler(pudev, USB_TX, 0U);
169 }
170
171 usbd_ctlstatus_rx(pudev);
172 }
173 }
174 }
175 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
176 pudev->dev.class_data_handler(pudev, USB_TX, endp_num);
177 } else {
178 /* no operation */
179 }
180
181 return USBD_OK;
182 }
USB_TX
Definition: usb_core.h:96
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
USB_CTRL_DATA_IN
Definition: usb_core.h:85
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:368
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usb_ep_struct
Definition: usbd_core.h:102
USBD_OK
Definition: usbd_core.h:84
NULL
#define NULL
Definition: usbd_std.h:20
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:23
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
usbd_status_enum usbd_out_transaction | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | endp_num
 | ) |  |

data out stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_id | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 104 of file usbd_std.c.

105 {
106 usb_ep_struct *ep;
107
108 if (0U == endp_num) {
109 ep = &pudev->dev.out_ep[0];
110
111 if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) {
112 if (pudev->dev.remain_len > ep->endp_mps) {
113 pudev->dev.remain_len -= ep->endp_mps;
114
115 usbd_ep_rx (pudev,
116 0U,
117 ep->xfer_buff,
118 (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps));
119 } else {
120 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
121 pudev->dev.class_data_handler(pudev, USB_RX, 0U);
122 }
123
124 usbd_ctlstatus_tx(pudev);
125 }
126 }
127 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
128 pudev->dev.class_data_handler(pudev, USB_RX, endp_num);
129 } else {
130 /* no operation */
131 }
132
133 return USBD_OK;
134 }
USB_CTRL_DATA_OUT
Definition: usb_core.h:86
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:351
USB_RX
Definition: usb_core.h:95
usb_ep_struct
Definition: usbd_core.h:102
USBD_OK
Definition: usbd_core.h:84
USB_MIN
#define USB_MIN(a, b)
Definition: usbd_std.h:43
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:23
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
usbd_status_enum usbd_setup_transaction ( usb_core_handle_struct * pudev )

USB setup stage processing.

Parameters
[in] | pudev | pointer to USB device instance
[out] | none
Return values
USB device operation status

Definition at line 70 of file usbd_std.c.

71 {
72 usb_device_req_struct req;
73
74 usbd_setup_request_parse(pudev, &req);
75
76 switch (req.bmRequestType & USB_REQ_MASK) {
77 /* standard device request */
78 case USB_STANDARD_REQ:
79 usbd_standard_request(pudev, &req);
80 break;
81 /* device class request */
82 case USB_CLASS_REQ:
83 usbd_device_class_request(pudev, &req);
84 break;
85 /* vendor defined request */
86 case USB_VENDOR_REQ:
87 usbd_vendor_request(pudev, &req);
88 break;
89 default:
90 usbd_ep_stall(pudev, req.bmRequestType & 0x80U);
91 break;
92 }
93
94 return USBD_OK;
95 }
usbd_standard_request
uint8_t usbd_standard_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB standard device request
Definition: usbd_std.c:220
USB_VENDOR_REQ
#define USB_VENDOR_REQ
Definition: usbd_std.h:36
USB_CLASS_REQ
#define USB_CLASS_REQ
Definition: usbd_std.h:35
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usb_device_req_struct
Definition: usbd_core.h:115
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usbd_core.h:117
usbd_device_class_request
uint8_t usbd_device_class_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB device class request
Definition: usbd_std.c:235
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
USBD_OK
Definition: usbd_core.h:84
USB_REQ_MASK
#define USB_REQ_MASK
Definition: usbd_std.h:37
usbd_vendor_request
uint8_t usbd_vendor_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB vendor request
Definition: usbd_std.c:268
usbd_setup_request_parse
void usbd_setup_request_parse(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
decode setup data packet
Definition: usbd_std.c:812
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Data Structures | Macros | Typedefs | Enumerations | Functions
usbh_core.h File Reference

header file for usbh_core.c More...

#include "usbh_conf.h"
#include "usb_std.h"
#include "usb_core.h"

Go to the source code of this file.

Data Structures

struct | usbh_ctrl_struct
struct | usbh_device_struct
struct | usbh_user_callback_struct
struct | backup_state_struct
struct | usbh_host_struct
struct | state_table_struct
struct | usbh_state_stack_struct
struct | usbh_state_regist_table_struct
struct | usbh_state_handle_struct

Macros

#define | MSC_CLASS 0x08
#define | HID_CLASS 0x03
#define | MSC_PROTOCOL 0x50
#define | CBI_PROTOCOL 0x01
#define | USBH_DEVICE_ADDRESS_DEFAULT 0U
#define | USBH_DEVICE_ADDRESS 1U
#define | USBH_MAX_ERROR_COUNT 2U
#define | HOST_USER_SELECT_CONFIGURATION 1U
#define | HOST_USER_CLASS_ACTIVE 2U
#define | HOST_USER_CLASS_SELECTED 3U
#define | HOST_USER_CONNECTION 4U
#define | HOST_USER_DISCONNECTION 5U
#define | HOST_USER_UNRECOVERED_ERROR 6U
#define | MAX_USBH_STATE_STACK_DEEP 4
#define | MAX_USBH_STATE_TABLE_NUM 10U
#define | HOST_FSM_ID 0U
#define | ENUM_FSM_ID 1U
#define | CMD_FSM_ID 2U
#define | CTRL_FSM_ID 3U
#define | CLASS_REQ_FSM_ID 4U
#define | CLASS_FSM_ID 5U
#define | UP_STATE 100U
#define | GO_TO_UP_STATE_EVENT 100U
#define | HOST_HANDLE_TABLE_SIZE 9U

Typedefs

typedef usbh_status_enum(* ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)

Enumerations

enum host_state_enum {
HOST_IDLE = 0, HOST_DEV_ATTACHED, HOST_DEV_DETACHED, HOST_DETECT_DEV_SPEED,
HOST_ENUMERATION, HOST_CLASS_REQUEST, HOST_CLASS, HOST_USER_INPUT,
HOST_SUSPENDED, HOST_ERROR
}
enum host_event_enum {
HOST_EVENT_ATTACHED = 0, HOST_EVENT_ENUM, HOST_EVENT_USER_INPUT, HOST_EVENT_CLASS_REQ,
HOST_EVENT_CLASS, HOST_EVENT_ERROR, HOST_EVENT_DEV_DETACHED, HOST_EVENT_IDLE
}
enum enum_state_enum {
ENUM_IDLE = 0, ENUM_SET_ADDR, ENUM_GET_FULL_DEV_DESC, ENUM_GET_CFG_DESC,
ENUM_GET_FULL_CFG_DESC, ENUM_GET_MFC_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC,
ENUM_SET_CONFIGURATION, ENUM_DEV_CONFIGURED
}
enum ctrl_state_enum {
CTRL_IDLE = 0, CTRL_SETUP, CTRL_DATA, CTRL_STATUS,
CTRL_ERROR, CTRL_STALLED, CTRL_COMPLETE
}
enum usbh_status_enum {
USBH_OK = 0, USBH_BUSY, USBH_FAIL, USBH_NOT_SUPPORTED,
USBH_UNRECOVERED_ERROR, USBH_SPEED_UNKNOWN_ERROR, USBH_APPLY_DEINIT
}
enum usbh_user_status_enum { USBH_USER_NO_RESP = 0, USBH_USER_RESP_OK = 1 }

Functions

usbh_status_enum | host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of HOST state More...
uint32_t | hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize the host portion of the driver. More...
uint32_t | hcd_is_device_connected (usb_core_handle_struct *pudev)
check if the device is connected. More...
urb_state_enum | hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate More...
uint32_t | hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate More...
usbh_status_enum | usbh_deinit (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
de-initialize host More...
void | scd_init (usbh_state_handle_struct *pustate)
state core driver init More...
void | scd_table_regist (usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist More...
void | scd_begin (usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin More...
void | scd_state_move (usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state More...
usbh_status_enum | scd_event_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle More...
void | scd_table_push (usbh_state_handle_struct *pustate)
state core driver table push More...
void | scd_table_pop (usbh_state_handle_struct *pustate)
state core driver table pop More...
usbh_status_enum | only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move More...
usbh_status_enum | goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state More...

Detailed Description

header file for usbh_core.c

Definition in file usbh_core.h.

Macro Definition Documentation

#define CBI_PROTOCOL 0x01

the CBI protocal define

Definition at line 23 of file usbh_core.h.

#define CLASS_FSM_ID 5U

the class state table id

Definition at line 44 of file usbh_core.h.

#define CLASS_REQ_FSM_ID 4U

the class req state table id

Definition at line 43 of file usbh_core.h.

#define CMD_FSM_ID 2U

the cmd state table id

Definition at line 41 of file usbh_core.h.

#define CTRL_FSM_ID 3U

the ctrl state table id

Definition at line 42 of file usbh_core.h.

#define ENUM_FSM_ID 1U

the enum state table id

Definition at line 40 of file usbh_core.h.

#define GO_TO_UP_STATE_EVENT 100U

go to up state event define

Definition at line 47 of file usbh_core.h.

#define HID_CLASS 0x03

the HID class define

Definition at line 21 of file usbh_core.h.

#define HOST_FSM_ID 0U

the host state table id

Definition at line 39 of file usbh_core.h.

#define HOST_HANDLE_TABLE_SIZE 9U

the host handle table size define

Definition at line 49 of file usbh_core.h.

#define HOST_USER_CLASS_ACTIVE 2U

the user class active define

Definition at line 30 of file usbh_core.h.

#define HOST_USER_CLASS_SELECTED 3U

the user class selected define

Definition at line 31 of file usbh_core.h.

#define HOST_USER_CONNECTION 4U

the user connecttion define

Definition at line 32 of file usbh_core.h.

#define HOST_USER_DISCONNECTION 5U

the user disconnection define

Definition at line 33 of file usbh_core.h.

#define HOST_USER_SELECT_CONFIGURATION 1U

the user select configuration define

Definition at line 29 of file usbh_core.h.

#define HOST_USER_UNRECOVERED_ERROR 6U

the user unrecovered error define

Definition at line 34 of file usbh_core.h.

#define MAX_USBH_STATE_STACK_DEEP 4

the max state stack deep define

Definition at line 36 of file usbh_core.h.

#define MAX_USBH_STATE_TABLE_NUM 10U

the max state table number

Definition at line 37 of file usbh_core.h.

#define MSC_CLASS 0x08

the MSC class define

Definition at line 20 of file usbh_core.h.

#define MSC_PROTOCOL 0x50

the MSC protocal define

Definition at line 22 of file usbh_core.h.

#define UP_STATE 100U

up state define

Definition at line 46 of file usbh_core.h.

#define USBH_DEVICE_ADDRESS 1U

the device address define

Definition at line 26 of file usbh_core.h.

#define USBH_DEVICE_ADDRESS_DEFAULT 0U

the default device address define

Definition at line 25 of file usbh_core.h.

#define USBH_MAX_ERROR_COUNT 2U

the max error count define

Definition at line 27 of file usbh_core.h.

Typedef Documentation

typedef usbh_status_enum(* ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)

Definition at line 200 of file usbh_core.h.

Enumeration Type Documentation

enum ctrl_state_enum
Enumerator
CTRL_IDLE
CTRL_SETUP
CTRL_DATA
CTRL_STATUS
CTRL_ERROR
CTRL_STALLED
CTRL_COMPLETE

Definition at line 95 of file usbh_core.h.

96 {
97 CTRL_IDLE = 0, /* the ctrl idle state definition */
98 CTRL_SETUP, /* the ctrl setup state definition */
99 CTRL_DATA, /* the ctrl data state definition */
100 CTRL_STATUS, /* the ctrl status state definition */
101 CTRL_ERROR, /* the ctrl error state definition */
102 CTRL_STALLED, /* the ctrl stalled state definition */
103 CTRL_COMPLETE /* the ctrl complete state definition */
104 }ctrl_state_enum;
CTRL_IDLE
Definition: usbh_core.h:97
CTRL_ERROR
Definition: usbh_core.h:101
ctrl_state_enum
ctrl_state_enum
Definition: usbh_core.h:95
CTRL_STATUS
Definition: usbh_core.h:100
CTRL_STALLED
Definition: usbh_core.h:102
CTRL_SETUP
Definition: usbh_core.h:98
CTRL_COMPLETE
Definition: usbh_core.h:103
CTRL_DATA
Definition: usbh_core.h:99
enum enum_state_enum
Enumerator
ENUM_IDLE
ENUM_SET_ADDR
ENUM_GET_FULL_DEV_DESC
ENUM_GET_CFG_DESC
ENUM_GET_FULL_CFG_DESC
ENUM_GET_MFC_STRING_DESC
ENUM_GET_PRODUCT_STRING_DESC
ENUM_GET_SERIALNUM_STRING_DESC
ENUM_SET_CONFIGURATION
ENUM_DEV_CONFIGURED

Definition at line 80 of file usbh_core.h.

81 {
82 ENUM_IDLE = 0, /* the enum idle state definition */
83 ENUM_SET_ADDR, /* the enum set address state definition */
84 ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */
85 ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */
86 ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */
87 ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */
88 ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */
89 ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */
90 ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */
91 ENUM_DEV_CONFIGURED /* the enum device configuration state definition */
92 }enum_state_enum;
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:91
ENUM_IDLE
Definition: usbh_core.h:82
ENUM_GET_PRODUCT_STRING_DESC
Definition: usbh_core.h:88
ENUM_GET_CFG_DESC
Definition: usbh_core.h:85
ENUM_SET_ADDR
Definition: usbh_core.h:83
enum_state_enum
enum_state_enum
Definition: usbh_core.h:80
ENUM_SET_CONFIGURATION
Definition: usbh_core.h:90
ENUM_GET_FULL_CFG_DESC
Definition: usbh_core.h:86
ENUM_GET_FULL_DEV_DESC
Definition: usbh_core.h:84
ENUM_GET_MFC_STRING_DESC
Definition: usbh_core.h:87
ENUM_GET_SERIALNUM_STRING_DESC
Definition: usbh_core.h:89
enum host_event_enum
Enumerator
HOST_EVENT_ATTACHED
HOST_EVENT_ENUM
HOST_EVENT_USER_INPUT
HOST_EVENT_CLASS_REQ
HOST_EVENT_CLASS
HOST_EVENT_ERROR
HOST_EVENT_DEV_DETACHED
HOST_EVENT_IDLE

Definition at line 67 of file usbh_core.h.

68 {
69 HOST_EVENT_ATTACHED = 0, /* the host attached event */
70 HOST_EVENT_ENUM, /* the host enum event */
71 HOST_EVENT_USER_INPUT, /* the host user input event */
72 HOST_EVENT_CLASS_REQ, /* the host class request event */
73 HOST_EVENT_CLASS, /* the host class event */
74 HOST_EVENT_ERROR, /* the host error event */
75 HOST_EVENT_DEV_DETACHED, /* the host device detached event */
76 HOST_EVENT_IDLE /* the host idle event */
77 }host_event_enum;
HOST_EVENT_IDLE
Definition: usbh_core.h:76
HOST_EVENT_CLASS_REQ
Definition: usbh_core.h:72
HOST_EVENT_CLASS
Definition: usbh_core.h:73
HOST_EVENT_ENUM
Definition: usbh_core.h:70
HOST_EVENT_ERROR
Definition: usbh_core.h:74
host_event_enum
host_event_enum
Definition: usbh_core.h:67
HOST_EVENT_DEV_DETACHED
Definition: usbh_core.h:75
HOST_EVENT_ATTACHED
Definition: usbh_core.h:69
HOST_EVENT_USER_INPUT
Definition: usbh_core.h:71
enum host_state_enum
Enumerator
HOST_IDLE
HOST_DEV_ATTACHED
HOST_DEV_DETACHED
HOST_DETECT_DEV_SPEED
HOST_ENUMERATION
HOST_CLASS_REQUEST
HOST_CLASS
HOST_USER_INPUT
HOST_SUSPENDED
HOST_ERROR

Definition at line 52 of file usbh_core.h.

53 {
54 HOST_IDLE = 0, /* the host idle state definition */
55 HOST_DEV_ATTACHED, /* the host device attached state definition */
56 HOST_DEV_DETACHED, /* the host device detached state definition */
57 HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */
58 HOST_ENUMERATION, /* the host enumeration state definition */
59 HOST_CLASS_REQUEST, /* the host class request state definition */
60 HOST_CLASS, /* the host class state definition */
61 HOST_USER_INPUT, /* the host user input state definition */
62 HOST_SUSPENDED, /* the host suspended state definition */
63 HOST_ERROR /* the host error state definition */
64 }host_state_enum;
HOST_SUSPENDED
Definition: usbh_core.h:62
HOST_CLASS
Definition: usbh_core.h:60
HOST_ERROR
Definition: usbh_core.h:63
HOST_DEV_DETACHED
Definition: usbh_core.h:56
HOST_DEV_ATTACHED
Definition: usbh_core.h:55
HOST_ENUMERATION
Definition: usbh_core.h:58
host_state_enum
host_state_enum
Definition: usbh_core.h:52
HOST_DETECT_DEV_SPEED
Definition: usbh_core.h:57
HOST_CLASS_REQUEST
Definition: usbh_core.h:59
HOST_USER_INPUT
Definition: usbh_core.h:61
HOST_IDLE
Definition: usbh_core.h:54
enum usbh_status_enum
Enumerator
USBH_OK
USBH_BUSY
USBH_FAIL
USBH_NOT_SUPPORTED
USBH_UNRECOVERED_ERROR
USBH_SPEED_UNKNOWN_ERROR
USBH_APPLY_DEINIT

Definition at line 107 of file usbh_core.h.

108 {
109 USBH_OK = 0, /* the usbh ok status definition */
110 USBH_BUSY, /* the usbh busy status definition */
111 USBH_FAIL, /* the usbh fail status definition */
112 USBH_NOT_SUPPORTED, /* the usbh not supported status definition */
113 USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */
114 USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */
115 USBH_APPLY_DEINIT /* the usbh apply deinit status definition */
116 }usbh_status_enum;
USBH_NOT_SUPPORTED
Definition: usbh_core.h:112
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
USBH_APPLY_DEINIT
Definition: usbh_core.h:115
USBH_UNRECOVERED_ERROR
Definition: usbh_core.h:113
USBH_SPEED_UNKNOWN_ERROR
Definition: usbh_core.h:114
USBH_OK
Definition: usbh_core.h:109
USBH_FAIL
Definition: usbh_core.h:111
USBH_BUSY
Definition: usbh_core.h:110
enum usbh_user_status_enum
Enumerator
USBH_USER_NO_RESP
USBH_USER_RESP_OK

Definition at line 119 of file usbh_core.h.

120 {
121 USBH_USER_NO_RESP = 0, /* the user no response */
122 USBH_USER_RESP_OK = 1, /* the user response ok */
123 }usbh_user_status_enum;
usbh_user_status_enum
usbh_user_status_enum
Definition: usbh_core.h:119
USBH_USER_RESP_OK
Definition: usbh_core.h:122
USBH_USER_NO_RESP
Definition: usbh_core.h:121

Function Documentation

usbh_status_enum goto_up_state_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the function to the up state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 706 of file usbh_core.c.

707 {
708 scd_table_pop((usbh_state_handle_struct *)pustate);
709
710 return USBH_OK;
711 }
usbh_state_handle_struct
Definition: usbh_core.h:228
scd_table_pop
void scd_table_pop(usbh_state_handle_struct *pustate)
state core driver table pop
Definition: usbh_core.c:645
USBH_OK
Definition: usbh_core.h:109
uint32_t hcd_init | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initialize the host portion of the driver.

Parameters
[in] | pudev | pointer to usb device
[in] | core_id | usb otg core identifier(high-speed or full-speed)
[out] | none
Return values
operation status

Definition at line 386 of file usbh_core.c.

387 {
388 pudev->host.connect_status = 0U;
389
390 pudev->host.host_channel[0].endp_mps = 8U;
391
392 usb_core_select(pudev, core_id);
393
394 #ifndef DUAL_ROLE_MODE_ENABLED
395
396 USB_GLOBAL_INT_DISABLE();
397
398 usb_core_init(pudev);
399
400 /* force host mode*/
401 usb_mode_set(pudev, HOST_MODE);
402
403 usb_hostcore_init(pudev);
404
405 USB_GLOBAL_INT_ENABLE();
406
407 #endif
408
409 return 0U;
410 }
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:128
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:49
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:268
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:493
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:490
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:170
uint32_t hcd_is_device_connected ( usb_core_handle_struct * pudev )

check if the device is connected.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
device connection status. 1 -> connected and 0 -> disconnected

Definition at line 418 of file usbh_core.c.

419 {
420 return (uint32_t)(pudev->host.connect_status);
421 }
urb_state_enum hcd_urb_state_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function returns the last URBstate

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
urb_state_enum

Definition at line 430 of file usbh_core.c.

431 {
432 return pudev->host.host_channel[channel_num].urb_state;
433 }
uint32_t hcd_xfer_count_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function returns the last URBstate

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
No. of data bytes transferred

Definition at line 442 of file usbh_core.c.

443 {
444 return pudev->host.host_channel[channel_num].xfer_count;
445 }
usbh_status_enum host_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of HOST state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 89 of file usbh_core.c.

92 {
93 usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate;
94
95 scd_begin(p_state, HOST_FSM_ID);
96
97 if (-1 == p_state->usbh_current_state_stack_top) {
98 uint8_t cur_state = p_state->usbh_current_state;
99
100 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) {
101 if (HOST_DEV_DETACHED != cur_state) {
102 p_state->usbh_current_state = HOST_DEV_DETACHED;
103 cur_state = HOST_DEV_DETACHED;
104 }
105 }
106
107 host_state_handle[cur_state](pudev, puhost, p_state);
108 } else {
109 uint8_t stack0_state = p_state->stack[0].state;
110
111 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) {
112 if (HOST_DEV_DETACHED != stack0_state) {
113 p_state->stack[0].state = HOST_DEV_DETACHED;
114 stack0_state = HOST_DEV_DETACHED;
115 p_state->usbh_current_state = HOST_DEV_DETACHED;
116 }
117 }
118
119 host_state_handle[stack0_state](pudev, puhost, p_state);
120 }
121
122 return USBH_OK;
123 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
usbh_state_handle_struct
Definition: usbh_core.h:228
hcd_is_device_connected
uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
check if the device is connected.
Definition: usbh_core.c:418
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
HOST_DEV_DETACHED
Definition: usbh_core.h:56
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:39
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
host_state_handle
void(* host_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_core.c:52
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
USBH_OK
Definition: usbh_core.h:109
HOST_IDLE
Definition: usbh_core.h:54
usbh_status_enum only_state_move | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the function is only used to state move

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 693 of file usbh_core.c.

694 {
695 return USBH_OK;
696 }
USBH_OK
Definition: usbh_core.h:109
void scd_begin | ( | usbh_state_handle_struct * | pustate,
 |  | uint8_t | table_id
 | ) |  |

state core driver begin

Parameters
[in] | pustate | pointer to usb state driver
[in] | table_id | the id of the table to begin
[out] | none
Return values
none

Definition at line 539 of file usbh_core.c.

540 {
541 uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num;
542 usbh_state_regist_table_struct *cur_state_reg_table;
543
544 for (i = 0U; i < table_num; i++) {
545 cur_state_reg_table = &pustate->usbh_regist_state_table[i];
546
547 if (table_id == cur_state_reg_table->id) {
548 pustate->usbh_current_state_table = cur_state_reg_table->table;
549 pustate->usbh_current_state_table_size = cur_state_reg_table->table_size;
550 break;
551 }
552 }
553 }
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:237
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:238
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:224
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:222
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:223
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
usbh_state_regist_table_struct
Definition: usbh_core.h:220
usbh_status_enum scd_event_handle | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | usbh_state_handle_struct * | pustate,
 |  | uint8_t | event,
 |  | uint8_t | state
 | ) |  |

state core driver event handle

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[in] | event | the current event
[in] | state | the current state
[out] | none
Return values
host status

Definition at line 577 of file usbh_core.c.

582 {
583 uint8_t i = 0U;
584 ACT_FUN event_act_fun = NULL;
585 state_table_struct *backup_state_t = pustate->usbh_current_state_table;
586 state_table_struct *executive_state_table = pustate->usbh_current_state_table;
587
588 /* look up the table to find the action function */
589 for (i = 0U; i < pustate->usbh_current_state_table_size; i++) {
590 if (state == executive_state_table->cur_state) {
591 if (event == executive_state_table->cur_event) {
592 state = executive_state_table->next_state;
593 event_act_fun = executive_state_table->event_action_fun;
594 break;
595 } else {
596 executive_state_table++;
597 }
598 } else {
599 executive_state_table++;
600 }
601 }
602
603 pustate->usbh_current_state_table = backup_state_t;
604
605 /* if the action function is not NULL, execute the action function */
606 if (event_act_fun) {
607 if (event_act_fun == &only_state_move) {
608 pustate->usbh_current_state = state;
609 } else {
610 return event_act_fun(pudev, puhost, pustate);
611 }
612 }
613
614 return USBH_BUSY;
615 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
state_table_struct::event_action_fun
ACT_FUN event_action_fun
Definition: usbh_core.h:208
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
state_table_struct::next_state
uint8_t next_state
Definition: usbh_core.h:207
state_table_struct
Definition: usbh_core.h:203
state_table_struct::cur_state
uint8_t cur_state
Definition: usbh_core.h:205
ACT_FUN
usbh_status_enum(* ACT_FUN)(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
Definition: usbh_core.h:200
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
NULL
#define NULL
Definition: usbd_std.h:20
USBH_BUSY
Definition: usbh_core.h:110
state_table_struct::cur_event
uint8_t cur_event
Definition: usbh_core.h:206
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:693
void scd_init ( usbh_state_handle_struct * pustate )

state core driver init

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 485 of file usbh_core.c.

486 {
487 /* init the state core */
488 pustate->usbh_current_state = 0U;
489 pustate->usbh_current_state_table = NULL;
490 pustate->usbh_current_state_table_size = 0U;
491
492 pustate->usbh_current_state_stack_top = -1;
493 pustate->stack->state = 0U;
494 pustate->stack->table_size = 0U;
495 pustate->stack->table = NULL;
496
497 pustate->usbh_regist_state_table_num = 0U;
498 pustate->usbh_regist_state_table->table = NULL;
499 pustate->usbh_regist_state_table->table_size = 0U;
500 pustate->usbh_regist_state_table->id = 0U;
501
502 /* init the control and the enumeration polling handle flag */
503 ctrl_polling_handle_flag = 0U;
504 enum_polling_handle_flag = 0U;
505 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:20
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:237
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:238
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:224
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:222
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:215
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:17
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:223
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:216
NULL
#define NULL
Definition: usbd_std.h:20
void scd_state_move | ( | usbh_state_handle_struct * | pustate,
 |  | uint8_t | state
 | ) |  |

state core driver move state

Parameters
[in] | pustate | pointer to usb state driver
[in] | state | the state to move
[out] | none
Return values
none

Definition at line 562 of file usbh_core.c.

563 {
564 pustate->usbh_current_state = state;
565 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
void scd_table_pop ( usbh_state_handle_struct * pustate )

state core driver table pop

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 645 of file usbh_core.c.

646 {
647 usbh_state_stack_struct *top_state_element;
648
649 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
650
651 if (pustate->usbh_current_state_stack_top > -1) {
652 /* get the current state table from the state stack */
653 pustate->usbh_current_state = top_state_element->state;
654 pustate->usbh_current_state_table = top_state_element->table;
655 pustate->usbh_current_state_table_size = top_state_element->table_size;
656 pustate->usbh_current_state_stack_top--;
657 }
658 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
usbh_state_stack_struct
Definition: usbh_core.h:212
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:215
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:216
void scd_table_push ( usbh_state_handle_struct * pustate )

state core driver table push

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 623 of file usbh_core.c.

624 {
625 usbh_state_stack_struct *top_state_element;
626
627 if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) {
628 pustate->usbh_current_state_stack_top++;
629
630 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
631
632 /* put the current state table into the state stack */
633 top_state_element->state = pustate->usbh_current_state;
634 top_state_element->table = pustate->usbh_current_state_table;
635 top_state_element->table_size = pustate->usbh_current_state_table_size;
636 }
637 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
usbh_state_stack_struct
Definition: usbh_core.h:212
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:215
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:216
MAX_USBH_STATE_STACK_DEEP
#define MAX_USBH_STATE_STACK_DEEP
Definition: usbh_core.h:36
void scd_table_regist | ( | usbh_state_handle_struct * | pustate,
 |  | state_table_struct * | pstate_table,
 |  | uint8_t | table_id,
 |  | uint8_t | current_table_size
 | ) |  |

state core driver table regist

Parameters
[in] | pustate | pointer to usb state driver
[in] | pstate_table | pointer to the table to regist
[in] | table_id | the id of the table to regist
[in] | current_table_size | the size of the current table to regist
[out] | none
Return values
none

Definition at line 516 of file usbh_core.c.

520 {
521 usbh_state_regist_table_struct *cur_state_reg_table;
522
523 cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num];
524
525 cur_state_reg_table->id = table_id;
526 cur_state_reg_table->table = pstate_table;
527 cur_state_reg_table->table_size = current_table_size;
528
529 pustate->usbh_regist_state_table_num++;
530 }
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:237
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:238
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:224
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:222
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:223
usbh_state_regist_table_struct
Definition: usbh_core.h:220
usbh_status_enum usbh_deinit | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | usbh_state_handle_struct * | pustate
 | ) |  |

de-initialize host

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[out] | none
Return values
host status

Definition at line 454 of file usbh_core.c.

457 {
458 /* software init */
459
460 puhost->control.ep0_size = USB_MAX_EP0_SIZE;
461
462 puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT;
463 puhost->device.speed = HPRT_PRTSPD_FULL_SPEED;
464
465 usbh_channel_free(pudev, puhost->control.hc_in_num);
466 usbh_channel_free(pudev, puhost->control.hc_out_num);
467
468 scd_init(pustate);
469 scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE);
470 scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE);
471 scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE);
472
473 scd_begin(pustate,HOST_FSM_ID);
474 scd_state_move(pustate, HOST_IDLE);
475
476 return USBH_OK;
477 }
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:40
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:115
host_handle_table
state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE]
Definition: usbh_core.c:67
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:42
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:128
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
scd_table_regist
void scd_table_regist(usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist
Definition: usbh_core.c:516
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:130
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
scd_init
void scd_init(usbh_state_handle_struct *pustate)
state core driver init
Definition: usbh_core.c:485
CTRL_HANDLE_TABLE_SIZE
#define CTRL_HANDLE_TABLE_SIZE
Definition: usbh_ctrl.h:19
usbh_device_struct::speed
uint8_t speed
Definition: usbh_core.h:142
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:39
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:141
ctrl_handle_table
state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Definition: usbh_ctrl.c:47
HPRT_PRTSPD_FULL_SPEED
#define HPRT_PRTSPD_FULL_SPEED
Definition: usb_defines.h:75
USB_MAX_EP0_SIZE
#define USB_MAX_EP0_SIZE
Definition: usb_core.h:20
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:193
USBH_OK
Definition: usbh_core.h:109
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:24
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:49
HOST_IDLE
Definition: usbh_core.h:54
USBH_DEVICE_ADDRESS_DEFAULT
#define USBH_DEVICE_ADDRESS_DEFAULT
Definition: usbh_core.h:25
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:129
HOST_HANDLE_TABLE_SIZE
#define HOST_HANDLE_TABLE_SIZE
Definition: usbh_core.h:49
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_ctrl.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Macros | Enumerations | Functions | Variables
usbh_ctrl.h File Reference

header file for usbh_ctrl.c More...

#include "usbh_core.h"
#include "usbh_usr.h"

Go to the source code of this file.

Macros

#define CTRL_HANDLE_TABLE_SIZE 13U

Enumerations

enum ctrl_event_enum {
CTRL_EVENT_IDLE = 0, CTRL_EVENT_SETUP, CTRL_EVENT_DATA, CTRL_EVENT_STATUS,
CTRL_EVENT_COMPLETE, CTRL_EVENT_ERROR, CTRL_EVENT_STALLED
}

Functions

usbh_status_enum | ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state More...
usbh_status_enum | usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len)
send datas from the host channel More...
usbh_status_enum | usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
send the setup packet to the device More...
uint32_t | hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer More...

Variables

state_table_struct ctrl_handle_table [CTRL_HANDLE_TABLE_SIZE]
uint8_t ctrl_polling_handle_flag

Detailed Description

header file for usbh_ctrl.c

Definition in file usbh_ctrl.h.

Macro Definition Documentation

#define CTRL_HANDLE_TABLE_SIZE 13U

the ctrl handle table size define

Definition at line 19 of file usbh_ctrl.h.

Enumeration Type Documentation

enum ctrl_event_enum
Enumerator
CTRL_EVENT_IDLE
CTRL_EVENT_SETUP
CTRL_EVENT_DATA
CTRL_EVENT_STATUS
CTRL_EVENT_COMPLETE
CTRL_EVENT_ERROR
CTRL_EVENT_STALLED

Definition at line 25 of file usbh_ctrl.h.

26 {
27 CTRL_EVENT_IDLE = 0, /* the ctrl idle event */
28 CTRL_EVENT_SETUP, /* the ctrl setup event */
29 CTRL_EVENT_DATA, /* the ctrl data event */
30 CTRL_EVENT_STATUS, /* the ctrl status event */
31 CTRL_EVENT_COMPLETE, /* the ctrl complete event */
32 CTRL_EVENT_ERROR, /* the ctrl error event */
33 CTRL_EVENT_STALLED, /* the ctrl stalled event */
34 }ctrl_event_enum;
CTRL_EVENT_ERROR
Definition: usbh_ctrl.h:32
CTRL_EVENT_SETUP
Definition: usbh_ctrl.h:28
CTRL_EVENT_DATA
Definition: usbh_ctrl.h:29
ctrl_event_enum
ctrl_event_enum
Definition: usbh_ctrl.h:25
CTRL_EVENT_STALLED
Definition: usbh_ctrl.h:33
CTRL_EVENT_COMPLETE
Definition: usbh_ctrl.h:31
CTRL_EVENT_IDLE
Definition: usbh_ctrl.h:27
CTRL_EVENT_STATUS
Definition: usbh_ctrl.h:30

Function Documentation

usbh_status_enum ctrl_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of CTRL state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 73 of file usbh_ctrl.c.

76 {
77 usbh_status_enum exe_state = USBH_BUSY;
78 usbh_state_handle_struct *p_state;
79
80 p_state = (usbh_state_handle_struct *)pustate;
81
82 /* if first enter this function, begin the ctrl state */
83 if (0U == ctrl_polling_handle_flag) {
84 ctrl_polling_handle_flag = 1U;
85 scd_table_push(p_state);
86 scd_state_move(p_state, CTRL_IDLE);
87 }
88
89 /* base on the current state to handle the ctrl state */
90 scd_begin(p_state, CTRL_FSM_ID);
91 ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
92
93 /* determine the control transfer whether to complete */
94 switch (puhost->usbh_backup_state.ctrl_backup_state) {
95 case CTRL_COMPLETE:
96 ctrl_polling_handle_flag = 0U;
97 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
98 exe_state = USBH_OK;
99 break;
100 case CTRL_STALLED:
101 ctrl_polling_handle_flag = 0U;
102 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
103 exe_state = USBH_NOT_SUPPORTED;
104 break;
105 case CTRL_ERROR:
106 ctrl_polling_handle_flag = 0U;
107 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
108 exe_state = USBH_FAIL;
109 break;
110 default:
111 exe_state = USBH_BUSY;
112 break;
113 }
114
115 return exe_state;
116 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
usbh_state_handle_struct
Definition: usbh_core.h:228
ctrl_state_handle
void(* ctrl_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_ctrl.c:33
CTRL_IDLE
Definition: usbh_core.h:97
CTRL_ERROR
Definition: usbh_core.h:101
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:42
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:17
USBH_NOT_SUPPORTED
Definition: usbh_core.h:112
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
CTRL_STALLED
Definition: usbh_core.h:102
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:623
USBH_OK
Definition: usbh_core.h:109
USBH_FAIL
Definition: usbh_core.h:111
CTRL_COMPLETE
Definition: usbh_core.h:103
USBH_BUSY
Definition: usbh_core.h:110
uint32_t hcd_submit_request | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function prepare a hc and start a transfer

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
host operation status

Definition at line 605 of file usbh_ctrl.c.

606 {
607 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
608
609 puhc->urb_state = URB_IDLE;
610 puhc->xfer_count = 0U;
611
612 return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num);
613 }
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:173
URB_IDLE
Definition: usb_core.h:51
usb_hostchannel_struct
Definition: usb_core.h:155
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:168
usbh_status_enum usbh_ctltx_setup | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | buf,
 |  | uint8_t | hc_num
 | ) |  |

send the setup packet to the device

Parameters
[in] | pudev | pointer to usb device
[in] | buf | buffer pointer from which the data will be send to device
[in] | hc_num | host channel number
[out] | none
Return values
host operation status

Definition at line 587 of file usbh_ctrl.c.

588 {
589 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
590
591 puhc->DPID = HC_PID_SETUP;
592 puhc->xfer_buff = buf;
593 puhc->xfer_len = USBH_SETUP_PACKET_SIZE;
594
595 return (usbh_status_enum)hcd_submit_request (pudev, hc_num);
596 }
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:605
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:166
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
usb_hostchannel_struct
Definition: usb_core.h:155
USBH_SETUP_PACKET_SIZE
#define USBH_SETUP_PACKET_SIZE
Definition: usbh_std.h:23
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:159
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:167
HC_PID_SETUP
#define HC_PID_SETUP
Definition: usb_defines.h:72
usbh_status_enum usbh_xfer | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | buf,
 |  | uint8_t | hc_num,
 |  | uint16_t | len
 | ) |  |

send datas from the host channel

Parameters
[in] | pudev | pointer to usb device
[in] | buf | data buffer address to send datas
[in] | hc_num | the number of the host channel
[in] | len | length of the send data
[out] | none
Return values
host operation status

Definition at line 494 of file usbh_ctrl.c.

498 {
499 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
500
501 puhc->xfer_buff = buf;
502 puhc->xfer_len = len;
503
504 switch (puhc->endp_type) {
505 case USB_EPTYPE_CTRL:
506 if (0U == puhc->endp_in) {
507 if (0U == len) {
508 /* for status out stage, length = 0, status out pid = 1 */
509 puhc->data_tg_out = 1U;
510 }
511
512 /* set the data toggle bit as per the flag */
513 if (0U == puhc->data_tg_out) {
514 /* put the pid 0 */
515 puhc->DPID = HC_PID_DATA0;
516 } else {
517 /* put the pid 1 */
518 puhc->DPID = HC_PID_DATA1;
519 }
520 } else {
521 puhc->DPID = HC_PID_DATA1;
522 }
523 break;
524
525 case USB_EPTYPE_ISOC:
526 puhc->DPID = HC_PID_DATA0;
527 break;
528
529 case USB_EPTYPE_BULK:
530 if (0U == puhc->endp_in) {
531 /* set the data toggle bit as per the flag */
532 if (0U == puhc->data_tg_out) {
533 /* put the pid 0 */
534 puhc->DPID = HC_PID_DATA0;
535 } else {
536 /* put the pid 1 */
537 puhc->DPID = HC_PID_DATA1;
538 }
539 } else {
540 if (0U == puhc->data_tg_in) {
541 puhc->DPID = HC_PID_DATA0;
542 } else {
543 puhc->DPID = HC_PID_DATA1;
544 }
545 }
546 break;
547
548 case USB_EPTYPE_INTR:
549 if (0U == puhc->endp_in) {
550 if (0U == puhc->data_tg_out) {
551 puhc->DPID = HC_PID_DATA0;
552 } else {
553 puhc->DPID = HC_PID_DATA1;
554 }
555
556 /* toggle data pid */
557 puhc->data_tg_out ^= 1U;
558 } else {
559 if (0U == puhc->data_tg_in) {
560 puhc->DPID = HC_PID_DATA0;
561 } else {
562 puhc->DPID = HC_PID_DATA1;
563 }
564
565 /* toggle data pid */
566 puhc->data_tg_in ^= 1U;
567 }
568 break;
569
570 default:
571 break;
572 }
573
574 hcd_submit_request (pudev, hc_num);
575
576 return USBH_OK;
577 }
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:605
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:53
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:166
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:176
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:55
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:161
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:52
HC_PID_DATA1
#define HC_PID_DATA1
Definition: usb_defines.h:71
usb_hostchannel_struct
Definition: usb_core.h:155
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:175
HC_PID_DATA0
#define HC_PID_DATA0
Definition: usb_defines.h:69
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:159
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:167
USBH_OK
Definition: usbh_core.h:109
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:162
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:54

Variable Documentation

state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]

Definition at line 47 of file usbh_ctrl.c.

uint8_t ctrl_polling_handle_flag

Definition at line 17 of file usbh_ctrl.c.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_hcs.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Macros | Functions
usbh_hcs.h File Reference

header file for usbh_hcs.c More...

#include "usbh_core.h"

Go to the source code of this file.

Macros

#define | HC_MAX 8U
#define | HC_OK 0x0000U
#define | HC_USED 0x8000U
#define | HC_ERROR 0xFFFFU
#define | HC_USED_MASK 0x7FFFU

Functions

uint8_t | usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe More...
uint8_t | usbh_allchannel_dealloc (usb_core_handle_struct *pudev)
free all usb host channel More...
uint8_t | usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel More...
uint8_t | usbh_channel_open (usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel More...
uint8_t | usbh_channel_modify (usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel More...

Detailed Description

header file for usbh_hcs.c

Definition in file usbh_hcs.h.

Macro Definition Documentation

#define HC_ERROR 0xFFFFU

Definition at line 22 of file usbh_hcs.h.

#define HC_MAX 8U

Definition at line 18 of file usbh_hcs.h.

#define HC_OK 0x0000U

Definition at line 20 of file usbh_hcs.h.

#define HC_USED 0x8000U

Definition at line 21 of file usbh_hcs.h.

#define HC_USED_MASK 0x7FFFU

Definition at line 23 of file usbh_hcs.h.

Function Documentation

uint8_t usbh_allchannel_dealloc ( usb_core_handle_struct * pudev )

free all usb host channel

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
host operation status

Definition at line 130 of file usbh_hcs.c.

131 {
132 uint8_t index;
133
134 for (index = 2U; index < HC_MAX; index ++) {
135 pudev->host.host_channel[index].info = 0U;
136 }
137
138 return USBH_OK;
139 }
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:18
USBH_OK
Definition: usbh_core.h:109
uint8_t usbh_channel_alloc | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

allocate a new channel for the pipe

Parameters
[in] | pudev | pointer to usb device
[in] | ep_addr | endpoint for which the channel to be allocated
[out] | none
Return values
host channel number

Definition at line 97 of file usbh_hcs.c.

98 {
99 uint16_t hc_num = usbh_freechannel_get(pudev);
100
101 if ((uint16_t)HC_ERROR != hc_num) {
102 pudev->host.host_channel[hc_num].info = HC_USED | ep_addr;
103 }
104
105 return (uint8_t)hc_num;
106 }
HC_USED
#define HC_USED
Definition: usbh_hcs.h:21
HC_ERROR
#define HC_ERROR
Definition: usbh_hcs.h:22
uint8_t usbh_channel_free | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | index
 | ) |  |

free the usb host channel

Parameters
[in] | pudev | pointer to usb device
[in] | index | channel number to be freed which is in (0..7)
[out] | none
Return values
host operation status

Definition at line 115 of file usbh_hcs.c.

116 {
117 if (index < HC_MAX) {
118 pudev->host.host_channel[index].info &= HC_USED_MASK;
119 }
120
121 return USBH_OK;
122 }
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:18
HC_USED_MASK
#define HC_USED_MASK
Definition: usbh_hcs.h:23
USBH_OK
Definition: usbh_core.h:109
uint8_t usbh_channel_modify | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num,
 |  | uint8_t | dev_addr,
 |  | uint8_t | dev_speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | ep_mps
 | ) |  |

modify a channel

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[in] | dev_addr | USB Device address allocated to attached device
[in] | dev_speed | USB device speed (Full speed/Low speed)
[in] | ep_type | endpoint type (bulk/int/ctl)
[in] | ep_mps | max packet size
[out] | none
Return values
operation status

Definition at line 64 of file usbh_hcs.c.

70 {
71 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
72
73 if (0U != dev_addr) {
74 puhc->dev_addr = dev_addr;
75 }
76
77 if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) {
78 puhc->endp_mps = ep_mps;
79 }
80
81 if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) {
82 puhc->dev_speed = dev_speed;
83 }
84
85 usb_hostchannel_init(pudev, channel_num);
86
87 return (uint8_t)HC_OK;
88 }
usb_hostchannel_struct
Definition: usb_core.h:155
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:163
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:157
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:158
HC_OK
#define HC_OK
Definition: usbh_hcs.h:20
uint8_t usbh_channel_open | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num,
 |  | uint8_t | dev_addr,
 |  | uint8_t | dev_speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | ep_mps
 | ) |  |

open a channel

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[in] | dev_addr | USB device address allocated to attached device
[in] | dev_speed | USB device speed (Full speed/Low speed)
[in] | ep_type | endpoint type (bulk/int/ctl)
[in] | ep_mps | max packet size
[out] | none
Return values
operation status

Definition at line 28 of file usbh_hcs.c.

34 {
35 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
36 uint16_t channel_info = puhc->info;
37
38 puhc->endp_id = (uint8_t)channel_info & 0x7FU;
39 puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7;
40 puhc->endp_type = ep_type;
41 puhc->endp_mps = ep_mps;
42 puhc->dev_addr = dev_addr;
43 puhc->dev_speed = dev_speed;
44
45 puhc->data_tg_in = 0U;
46 puhc->data_tg_out = 0U;
47
48 usb_hostchannel_init(pudev, channel_num);
49
50 return (uint8_t)HC_OK;
51 }
usb_hostchannel_struct::info
uint16_t info
Definition: usb_core.h:164
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:176
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:161
usb_hostchannel_struct
Definition: usb_core.h:155
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:175
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:163
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:157
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:158
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:162
HC_OK
#define HC_OK
Definition: usbh_hcs.h:20
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:160
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_int.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Data Structures | Functions | Variables
usbh_int.h File Reference

USB host mode interrupt handler header file. More...

#include "usb_core.h"

Go to the source code of this file.

Data Structures

struct usbh_hcd_int_cb_struct

Functions

uint32_t usbh_isr (usb_core_handle_struct *pudev)
handle global host interrupt More...

Variables

usbh_hcd_int_cb_struct * usbh_hcd_int_fops

Detailed Description

USB host mode interrupt handler header file.

Definition in file usbh_int.h.

Function Documentation

uint32_t usbh_isr ( usb_core_handle_struct * pudev )

handle global host interrupt

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
operation status

Definition at line 34 of file usbh_int.c.

35 {
36 uint32_t retval = 0U;
37 __IO uint32_t int_flag = 0U;
38
39 /* check if host mode */
40 if (USB_CURRENT_MODE_GET() == HOST_MODE) {
41 USB_CORE_INTR_READ(int_flag);
42
43 if (!int_flag) {
44 return 0U;
45 }
46
47 /* start of frame interrupt handle */
48 if (int_flag & GINTF_SOF) {
49 retval |= usbh_intf_sof (pudev);
50 }
51
52 /* Rx FIFO non-empty interrupt handle */
53 if (int_flag & GINTF_RXFNEIF) {
54 retval |= usbh_intf_rxfifo_noempty (pudev);
55 }
56
57 /* Non-Periodic Tx FIFO empty interrupt hanlde */
58 if (int_flag & GINTF_NPTXFEIF) {
59 retval |= usbh_intf_nptxfifo_empty (pudev);
60 }
61
62 /* periodic Tx FIFO empty interrupt handle */
63 if (int_flag & GINTF_PTXFEIF) {
64 retval |= usbh_intf_ptxfifo_empty (pudev);
65 }
66
67 /* host channels interrupt handle */
68 if (int_flag & GINTF_HCIF) {
69 retval |= usbh_intf_hc (pudev);
70 }
71
72 /* host port interrupt handle */
73 if (int_flag & GINTF_HPIF) {
74 retval |= usbh_intf_port (pudev);
75 }
76
77 /* disconnect interrupt handle */
78 if (int_flag & GINTF_DISCIF) {
79 retval |= usbh_intf_disconnect (pudev);
80 }
81
82 /* isochronous IN transfer not complete interrupt handle */
83 if (int_flag & GINTF_ISOONCIF) {
84 retval |= usbh_intf_iso_incomplete_xfer (pudev);
85 }
86 }
87
88 return retval;
89 }
USB_CORE_INTR_READ
#define USB_CORE_INTR_READ(x)
Definition: usb_regs.h:499
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:49
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:159
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:496
GINTF_HCIF
#define GINTF_HCIF
Definition: usb_regs.h:143
GINTF_HPIF
#define GINTF_HPIF
Definition: usb_regs.h:144
GINTF_NPTXFEIF
#define GINTF_NPTXFEIF
Definition: usb_regs.h:158
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:146
GINTF_PTXFEIF
#define GINTF_PTXFEIF
Definition: usb_regs.h:142
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:160
GINTF_DISCIF
#define GINTF_DISCIF
Definition: usb_regs.h:140

Variable Documentation

usbh_hcd_int_cb_struct* usbh_hcd_int_fops

Definition at line 34 of file usbh_core.c.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_std.h File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
Macros | Enumerations | Functions | Variables
usbh_std.h File Reference

header file for usbh_std.c More...

#include "usbh_core.h"
#include "usbh_usr.h"

Go to the source code of this file.

Macros

#define | FEATURE_SELECTOR_ENDPOINT 0x00U
#define | FEATURE_SELECTOR_DEVICE 0x01U
#define | USBH_SETUP_PACKET_SIZE 8U /* setup packet size */
#define | ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */

Enumerations

enum enum_event_enum {
ENUN_EVENT_IDLE = 0, ENUM_EVENT_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC,
ENUN_EVENT_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC,
ENUN_EVENT_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED
}

Functions

usbh_status_enum | enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state More...
void | usbh_enum_desc_get (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t *buf, uint8_t req_type, uint16_t value_idx, uint16_t len)
get descriptor in usb host enumeration stage More...
void | usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address)
set address in usb host enumeration stage More...
void | usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx)
set configuration in usb host enumeration stage More...
void | usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
parse the device descriptor More...
void | usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], uint8_t *buf, uint16_t len)
parse the configuration descriptor More...
void | usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor More...
void | usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor More...
void | usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len)
parse the string descriptor More...
usb_descriptor_header_struct * | usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header More...

Variables

uint8_t | usbh_cfg_desc [512]
uint8_t | enum_polling_handle_flag
state_table_struct enum_handle_table [ENUM_HANDLE_TABLE_SIZE]

Detailed Description

header file for usbh_std.c

Definition in file usbh_std.h.

Macro Definition Documentation

#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */

Definition at line 24 of file usbh_std.h.

#define FEATURE_SELECTOR_DEVICE 0x01U

Definition at line 21 of file usbh_std.h.

#define FEATURE_SELECTOR_ENDPOINT 0x00U

Definition at line 20 of file usbh_std.h.

#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */

Definition at line 23 of file usbh_std.h.

Enumeration Type Documentation

enum enum_event_enum
Enumerator
ENUN_EVENT_IDLE
ENUM_EVENT_SET_ADDR
ENUN_EVENT_GET_FULL_DEV_DESC
ENUN_EVENT_GET_CFG_DESC
ENUN_EVENT_GET_FULL_CFG_DESC
ENUN_EVENT_GET_MFC_STRING_DESC
ENUN_EVENT_GET_PRODUCT_STRING_DESC
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
ENUN_EVENT_SET_CONFIGURATION
ENUN_EVENT_DEV_CONFIGURED

Definition at line 30 of file usbh_std.h.

31 {
32 ENUN_EVENT_IDLE = 0, /* the enum idle event */
33 ENUM_EVENT_SET_ADDR, /* the enum set address event */
34 ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */
35 ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */
36 ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */
37 ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */
38 ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */
39 ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */
40 ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */
41 ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */
42 }enum_event_enum;
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
Definition: usbh_std.h:39
enum_event_enum
enum_event_enum
Definition: usbh_std.h:30
ENUN_EVENT_DEV_CONFIGURED
Definition: usbh_std.h:41
ENUN_EVENT_SET_CONFIGURATION
Definition: usbh_std.h:40
ENUN_EVENT_GET_PRODUCT_STRING_DESC
Definition: usbh_std.h:38
ENUN_EVENT_GET_CFG_DESC
Definition: usbh_std.h:35
ENUN_EVENT_GET_FULL_CFG_DESC
Definition: usbh_std.h:36
ENUN_EVENT_GET_MFC_STRING_DESC
Definition: usbh_std.h:37
ENUN_EVENT_GET_FULL_DEV_DESC
Definition: usbh_std.h:34
ENUN_EVENT_IDLE
Definition: usbh_std.h:32
ENUM_EVENT_SET_ADDR
Definition: usbh_std.h:33

Function Documentation

usbh_status_enum enum_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of enumeration state

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | pustate | pointer to USB state driver
[out] | none
Return values
usb host status

Definition at line 72 of file usbh_std.c.

73 {
74 usbh_status_enum exe_state = USBH_BUSY;
75 usbh_state_handle_struct *p_state;
76 p_state = (usbh_state_handle_struct *)pustate;
77
78 if (0U == enum_polling_handle_flag) {
79 enum_polling_handle_flag = 1U;
80 scd_table_push(p_state);
81 scd_state_move(p_state, ENUM_IDLE);
82 }
83
84 /* start the enumeration state handle */
85 scd_begin(p_state,ENUM_FSM_ID);
86
87 if (0U == p_state->usbh_current_state_stack_top) {
88 enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
89 } else {
90 enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state);
91 }
92
93 /* determine the enumeration whether to complete */
94 if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) {
95 puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE;
96 enum_polling_handle_flag = 0U;
97 exe_state = USBH_OK;
98 }
99
100 return exe_state;
101 }
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:91
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:20
usbh_state_handle_struct
Definition: usbh_core.h:228
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:40
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
ENUM_IDLE
Definition: usbh_core.h:82
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
backup_state_struct::enum_backup_state
enum_state_enum enum_backup_state
Definition: usbh_core.h:182
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
enum_state_handle
void(* enum_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_std.c:34
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:191
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:623
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
USBH_OK
Definition: usbh_core.h:109
USBH_BUSY
Definition: usbh_core.h:110
void usbh_cfg_desc_parse | ( | usb_descriptor_configuration_struct * | cfg_desc,
 |  | usb_descriptor_interface_struct * | itf_desc,
 |  | usb_descriptor_endpoint_struct | ep_desc[][USBH_MAX_EP_NUM],
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

parse the configuration descriptor

Parameters
[in] | cfg_desc | configuration descriptor address
[in] | itf_desc | interface descriptor address
[in] | ep_desc | endpoint descriptor address
[in] | buf | buffer where the source descriptor is available
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 638 of file usbh_std.c.

643 {
644 usb_descriptor_interface_struct *pitf = NULL;
645 usb_descriptor_interface_struct temp_pitf;
646 usb_descriptor_endpoint_struct *pep = NULL;
647 usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf;
648
649 uint8_t itf_ix = 0U;
650 uint8_t ep_ix = 0U;
651 uint16_t ptr = 0U;
652 static uint8_t prev_itf = 0U;
653 static uint16_t prev_ep_size = 0U;
654
655 /* parse configuration descriptor */
656 cfg_desc->Header.bLength = *(uint8_t *)(buf + 0);
657 cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
658 cfg_desc->wTotalLength = SWAPBYTE(buf + 2);
659 cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4);
660 cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5);
661 cfg_desc->iConfiguration = *(uint8_t *)(buf + 6);
662 cfg_desc->bmAttributes = *(uint8_t *)(buf + 7);
663 cfg_desc->bMaxPower = *(uint8_t *)(buf + 8);
664
665 if (len > USB_CFGDESC_SIZE) {
666 ptr = USB_CFG_DESC_LEN;
667
668 if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) {
669 pitf = (usb_descriptor_interface_struct *)0;
670
671 for (; ptr < cfg_desc->wTotalLength; ) {
672 pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr);
673
674 if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) {
675 itf_ix = *((uint8_t *)pdesc + 2U);
676 pitf = &itf_desc[itf_ix];
677
678 if (*((uint8_t *)pdesc + 3U) < 3U) {
679 usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc);
680
681 /* parse endpoint descriptors relative to the current interface */
682 if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) {
683 for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) {
684 pdesc = usbh_next_desc_get((void* )pdesc, &ptr);
685
686 if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) {
687 pep = &ep_desc[itf_ix][ep_ix];
688
689 if (prev_itf != itf_ix) {
690 prev_itf = itf_ix;
691 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
692 } else {
693 if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) {
694 break;
695 } else {
696 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
697 }
698 }
699
700 usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc);
701 prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4);
702 ep_ix++;
703 }
704 }
705 }
706 }
707 }
708 }
709 }
710
711 prev_ep_size = 0U;
712 prev_itf = 0U;
713 }
714 }
usb_descriptor_configuration_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:136
USB_DESCTYPE_INTERFACE
#define USB_DESCTYPE_INTERFACE
Definition: usbd_std.h:57
usb_descriptor_configuration_struct::wTotalLength
uint16_t wTotalLength
Definition: usbd_std.h:132
usb_descriptor_configuration_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:130
usbh_endpoint_desc_parse
void usbh_endpoint_desc_parse(usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor
Definition: usbh_std.c:743
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usbd_std.h:148
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
usb_descriptor_interface_struct
Definition: usbd_std.h:142
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usb_descriptor_header_struct
Definition: usbd_std.h:102
USB_CFG_DESC_LEN
#define USB_CFG_DESC_LEN
Definition: usbd_std.h:25
usbh_interface_desc_parse
void usbh_interface_desc_parse(usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor
Definition: usbh_std.c:723
usb_descriptor_configuration_struct::bConfigurationValue
uint8_t bConfigurationValue
Definition: usbd_std.h:134
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
usbh_next_desc_get
usb_descriptor_header_struct * usbh_next_desc_get(uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header
Definition: usbh_std.c:796
usb_descriptor_configuration_struct::bNumInterfaces
uint8_t bNumInterfaces
Definition: usbd_std.h:133
USB_CFGDESC_SIZE
#define USB_CFGDESC_SIZE
Definition: usb_std.h:69
usb_descriptor_configuration_struct::iConfiguration
uint8_t iConfiguration
Definition: usbd_std.h:135
USB_DESCTYPE_ENDPOINT
#define USB_DESCTYPE_ENDPOINT
Definition: usbd_std.h:58
NULL
#define NULL
Definition: usbd_std.h:20
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_configuration_struct::bMaxPower
uint8_t bMaxPower
Definition: usbd_std.h:137
void usbh_device_desc_parse | ( | usb_descriptor_device_struct * | dev_desc,
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

parse the device descriptor

Parameters
[in] | dev_desc | device_descriptor destinaton address
[in] | buf | buffer where the source descriptor is available
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 606 of file usbh_std.c.

607 {
608 dev_desc->Header.bLength = *(uint8_t *)(buf + 0);
609 dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
610 dev_desc->bcdUSB = SWAPBYTE(buf + 2);
611 dev_desc->bDeviceClass = *(uint8_t *)(buf + 4);
612 dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5);
613 dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6);
614 dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7);
615
616 if (len > 8U){
617 /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */
618 dev_desc->idVendor = SWAPBYTE(buf + 8);
619 dev_desc->idProduct = SWAPBYTE(buf + 10);
620 dev_desc->bcdDevice = SWAPBYTE(buf + 12);
621 dev_desc->iManufacturer = *(uint8_t *)(buf + 14);
622 dev_desc->iProduct = *(uint8_t *)(buf + 15);
623 dev_desc->iSerialNumber = *(uint8_t *)(buf + 16);
624 dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17);
625 }
626 }
usb_descriptor_device_struct::idProduct
uint16_t idProduct
Definition: usbd_std.h:118
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usb_descriptor_device_struct::bcdUSB
uint16_t bcdUSB
Definition: usbd_std.h:112
usb_descriptor_device_struct::bDeviceProtocol
uint8_t bDeviceProtocol
Definition: usbd_std.h:115
usb_descriptor_device_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:110
usb_descriptor_device_struct::bcdDevice
uint16_t bcdDevice
Definition: usbd_std.h:119
usb_descriptor_device_struct::bDeviceSubClass
uint8_t bDeviceSubClass
Definition: usbd_std.h:114
usb_descriptor_device_struct::bNumberConfigurations
uint8_t bNumberConfigurations
Definition: usbd_std.h:123
usb_descriptor_device_struct::idVendor
uint16_t idVendor
Definition: usbd_std.h:117
usb_descriptor_device_struct::iProduct
uint8_t iProduct
Definition: usbd_std.h:121
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_device_struct::bDeviceClass
uint8_t bDeviceClass
Definition: usbd_std.h:113
usb_descriptor_device_struct::bMaxPacketSize0
uint8_t bMaxPacketSize0
Definition: usbd_std.h:116
usb_descriptor_device_struct::iManufacturer
uint8_t iManufacturer
Definition: usbd_std.h:120
usb_descriptor_device_struct::iSerialNumber
uint8_t iSerialNumber
Definition: usbd_std.h:122
void usbh_endpoint_desc_parse | ( | usb_descriptor_endpoint_struct * | ep_desc,
 |  | uint8_t * | buf
 | ) |  |

parse the endpoint descriptor

Parameters
[in] | ep_desc | endpoint descriptor destination address
[in] | buf | buffer where the parsed descriptor stored
[out] | none
Return values
none

Definition at line 743 of file usbh_std.c.

744 {
745 ep_desc->Header.bLength = *(uint8_t *)(buf + 0);
746 ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
747 ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2);
748 ep_desc->bmAttributes = *(uint8_t *)(buf + 3);
749 ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4);
750 ep_desc->bInterval = *(uint8_t *)(buf + 6);
751 }
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:162
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usbd_std.h:161
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usbd_std.h:163
usb_descriptor_endpoint_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:159
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_endpoint_struct::bInterval
uint8_t bInterval
Definition: usbd_std.h:164
void usbh_enum_addr_set | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint8_t | device_address
 | ) |  |

set address in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | device_address | the device address
[out] | none
Return values
none

Definition at line 560 of file usbh_std.c.

563 {
564 usb_setup_union *p_setup = &(puhost->control.setup);
565
566 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
567 p_setup->b.bRequest = USBREQ_SET_ADDRESS;
568 p_setup->b.wValue = (uint16_t)device_address;
569 p_setup->b.wIndex = 0U;
570 p_setup->b.wLength = 0U;
571 puhost->control.buff = 0U;
572 puhost->control.length = 0U;
573 }
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:117
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:114
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:134
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usbd_std.h:39
usb_setup_union
Definition: usb_std.h:108
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:118
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:27
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:116
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:132
USBREQ_SET_ADDRESS
#define USBREQ_SET_ADDRESS
Definition: usbd_std.h:47
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:115
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:135
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_enum_cfg_set | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint16_t | cfg_idx
 | ) |  |

set configuration in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | cfg_idx | the index of the configuration
[out] | none
Return values
none

Definition at line 583 of file usbh_std.c.

586 {
587 usb_setup_union *p_setup = &(puhost->control.setup);
588
589 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
590 p_setup->b.bRequest = USBREQ_SET_CONFIGURATION;
591 p_setup->b.wValue = cfg_idx;
592 p_setup->b.wIndex = 0U;
593 p_setup->b.wLength = 0U;
594 puhost->control.buff = 0;
595 puhost->control.length = 0U;
596 }
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:117
USBREQ_SET_CONFIGURATION
#define USBREQ_SET_CONFIGURATION
Definition: usbd_std.h:50
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:114
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:134
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usbd_std.h:39
usb_setup_union
Definition: usb_std.h:108
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:118
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:27
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:116
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:132
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:115
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:135
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_enum_desc_get | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint8_t * | buf,
 |  | uint8_t | req_type,
 |  | uint16_t | value_idx,
 |  | uint16_t | len
 | ) |  |

get descriptor in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | buf | buffer to store the descriptor
[in] | ReqType | descriptor type
[in] | ValueIdx | wValue for the GetDescriptr request
[in] | Len | length of the descriptor
[out] | none
Return values
none

Definition at line 526 of file usbh_std.c.

532 {
533 usb_setup_union *pSetup = &(puhost->control.setup);
534
535 pSetup->b.bmRequestType = USB_DIR_IN | req_type;
536 pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR;
537 pSetup->b.wValue = value_idx;
538
539 if (USB_STRDESC == (value_idx & 0xff00U)){
540 pSetup->b.wIndex = 0x0409U;
541 } else {
542 pSetup->b.wIndex = 0U;
543 }
544
545 pSetup->b.wLength = len;
546
547 puhost->control.buff = buf;
548 puhost->control.length = len;
549
550 }
USB_STRDESC
#define USB_STRDESC
Definition: usb_std.h:77
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:117
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:114
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:134
usb_setup_union
Definition: usb_std.h:108
USBREQ_GET_DESCRIPTOR
#define USBREQ_GET_DESCRIPTOR
Definition: usbd_std.h:48
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:118
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:116
USB_DIR_IN
#define USB_DIR_IN
Definition: usb_std.h:28
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:132
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:115
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:135
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_interface_desc_parse | ( | usb_descriptor_interface_struct * | itf_desc,
 |  | uint8_t * | buf
 | ) |  |

parse the interface descriptor

Parameters
[in] | itf_desc | interface descriptor destination
[in] | buf | buffer where the descriptor data is available
[out] | none
Return values
none

Definition at line 723 of file usbh_std.c.

724 {
725 itf_desc->Header.bLength = *(uint8_t *)(buf + 0);
726 itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
727 itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2);
728 itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3);
729 itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4);
730 itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5);
731 itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6);
732 itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7);
733 itf_desc->iInterface = *(uint8_t *)(buf + 8);
734 }
usb_descriptor_interface_struct::bInterfaceProtocol
uint8_t bInterfaceProtocol
Definition: usbd_std.h:151
usb_descriptor_interface_struct::iInterface
uint8_t iInterface
Definition: usbd_std.h:152
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usbd_std.h:148
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
usb_descriptor_interface_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:144
usb_descriptor_interface_struct::bInterfaceClass
uint8_t bInterfaceClass
Definition: usbd_std.h:149
usb_descriptor_interface_struct::bInterfaceSubClass
uint8_t bInterfaceSubClass
Definition: usbd_std.h:150
usb_descriptor_interface_struct::bAlternateSetting
uint8_t bAlternateSetting
Definition: usbd_std.h:147
usb_descriptor_interface_struct::bInterfaceNumber
uint8_t bInterfaceNumber
Definition: usbd_std.h:146
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_header_struct* usbh_next_desc_get | ( | uint8_t * | pbuf,
 |  | uint16_t * | ptr
 | ) |  |

get the next descriptor header

Parameters
[in] | pbuf | pointer to buffer where the cfg descriptor is available
[in] | ptr | data popinter inside the configuration descriptor
[out] | none
Return values
next descriptor header

Definition at line 796 of file usbh_std.c.

797 {
798 uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength;
799
800 usb_descriptor_header_struct *pnext;
801
802 *ptr += len;
803
804 pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len);
805
806 return(pnext);
807 }
usb_descriptor_header_struct
Definition: usbd_std.h:102
void usbh_string_desc_parse | ( | uint8_t * | psrc,
 |  | uint8_t * | pdest,
 |  | uint16_t | len
 | ) |  |

parse the string descriptor

Parameters
[in] | psrc | source pointer containing the descriptor data
[in] | pdest | destination address pointer
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 761 of file usbh_std.c.

762 {
763 uint16_t strlength;
764 uint16_t idx;
765
766 /* the unicode string descriptor is not null-terminated. the string length is
767 computed by substracting two from the value of the first byte of the descriptor.
768 */
769
770 /* check which is lower size, the size of string or the length of bytes read from the device */
771
772 if (USB_DESCTYPE_STRING == psrc[1]){
773 /* make sure the descriptor is string type */
774
775 /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */
776 strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len);
777 psrc += 2; /* adjust the offset ignoring the string len and descriptor type */
778
779 for (idx = 0U; idx < strlength; idx += 2U) {
780 /* copy only the string and ignore the unicode id, hence add the src */
781 *pdest = psrc[idx];
782 pdest++;
783 }
784
785 *pdest = 0U; /* mark end of string */
786 }
787 }
USB_DESCTYPE_STRING
#define USB_DESCTYPE_STRING
Definition: usbd_std.h:56

Variable Documentation

state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]

Definition at line 49 of file usbh_std.c.

uint8_t enum_polling_handle_flag

Definition at line 20 of file usbh_std.c.

uint8_t usbh_cfg_desc[512]

Definition at line 19 of file usbh_std.c.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source Directory Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Source Directory Reference

Files

file | usb_core.c [code]
USB core driver which can operate in host-mode and device-mode.
file | usbd_core.c [code]
file | usbd_int.c [code]
file | usbd_std.c [code]
file | usbh_core.c [code]
this file implements the functions for the core state machine process
file | usbh_ctrl.c [code]
this file implements the functions for the control transmit process
file | usbh_hcs.c [code]
this file implements functions for opening and closing host channels
file | usbh_int.c [code]
USB host mode interrupt handler file.
file | usbh_std.c [code]
USB 2.0 standard function definition.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usb_core.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Functions
usb_core.c File Reference

USB core driver which can operate in host-mode and device-mode. More...

#include "usb_core.h"

Go to the source code of this file.

Functions

usb_status_enum | usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint More...
void * | usb_fifo_read (uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint More...
usb_status_enum | usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters More...
usb_status_enum | usb_core_init (usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation More...
usb_status_enum | usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs More...
usb_status_enum | usb_rxfifo_flush (usb_core_handle_struct *pudev)
flush the entire Rx FIFO More...
usb_status_enum | usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device) More...

Detailed Description

USB core driver which can operate in host-mode and device-mode.

Definition in file usb_core.c.

Function Documentation

usb_status_enum usb_core_init ( usb_core_handle_struct * pudev )

initializes the USB controller registers and prepares the core device mode or host mode operation

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 170 of file usb_core.c.

171 {
172 /* soft reset the core */
173 usb_core_reset(pudev);
174
175 /* active the transceiver and enable vbus sensing */
176 USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN;
177
178 /* set Tx FIFO empty level to half empty mode */
179 USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF;
180
181 #ifndef VBUS_SENSING_ENABLED
182 USB_GCCFG |= GCCFG_VBUSIG;
183 #endif /* VBUS_SENSING_ENABLED */
184
185 if(pudev->cfg.sof_output){
186 USB_GCCFG |= GCCFG_SOFOEN;
187 }
188
189 if (NULL != pudev->mdelay) {
190 pudev->mdelay(20U);
191 }
192
193
194 #ifdef USE_OTG_MODE
195 /* enable OTG features */
196 USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP;
197 USB_OTG_EnableCommonInt(pudev);
198
199 #endif /* USE_OTG_MODE */
200
201 return USB_OK;
202 }
USB_GCCFG
#define USB_GCCFG
Definition: usb_regs.h:49
GAHBCS_TXFTH
#define GAHBCS_TXFTH
Definition: usb_regs.h:118
GCCFG_VBUSBCEN
#define GCCFG_VBUSBCEN
Definition: usb_regs.h:222
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:39
GCCFG_PWRON
#define GCCFG_PWRON
Definition: usb_regs.h:224
USB_OK
Definition: usb_core.h:30
TXFIFO_EMPTY_HALF
#define TXFIFO_EMPTY_HALF
Definition: usb_regs.h:452
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
GCCFG_SOFOEN
#define GCCFG_SOFOEN
Definition: usb_regs.h:221
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:67
GCCFG_VBUSACEN
#define GCCFG_VBUSACEN
Definition: usb_regs.h:223
GCCFG_VBUSIG
#define GCCFG_VBUSIG
Definition: usb_regs.h:220
NULL
#define NULL
Definition: usbd_std.h:20
USB_GAHBCS
#define USB_GAHBCS
Definition: usb_regs.h:38
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:203
usb_status_enum usb_core_select | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initialize core parameters

Parameters
[in] | pudev | pointer to usb device
[in] | core_id | USB core id
[out] | none
Return values
operation status

Definition at line 128 of file usb_core.c.

129 {
130 /* at startup the core is in FS mode */
131 pudev->cfg.core_speed = USB_CORE_SPEED_FULL;
132 pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE;
133
134 /* initialize the core parameters */
135 if (USB_FS_CORE_ID == core_id) {
136
137 pudev->cfg.core_id = USB_FS_CORE_ID;
138
139 /* set the host channel numbers */
140 pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT;
141
142 /* set the device endpoint numbers */
143 pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT;
144
145 /* fifo size is in terms of DWORD */
146 pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN;
147
148 /* OTG_FS core use embedded physical layer */
149 pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY;
150
151 #ifdef USBFS_SOF_OUTPUT_ENABLED
152 pudev->cfg.sof_output = 1U;
153 #endif /* USBFS_SOF_OUTPUT_ENABLED */
154
155 #ifdef USBFS_LOW_PWR_MGMT_SUPPORT
156 pudev->cfg.low_power = 1U;
157 #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */
158 }
159
160 return USB_OK;
161 }
USBFS_MAX_PACKET_SIZE
#define USBFS_MAX_PACKET_SIZE
Definition: usb_defines.h:25
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:66
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:69
USBFS_MAX_HOST_CHANNELCOUNT
#define USBFS_MAX_HOST_CHANNELCOUNT
Definition: usb_defines.h:26
USB_OK
Definition: usb_core.h:30
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:64
USB_CORE_SPEED_FULL
#define USB_CORE_SPEED_FULL
Definition: usb_defines.h:23
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:67
USB_CORE_EMBEDDED_PHY
#define USB_CORE_EMBEDDED_PHY
Definition: usb_defines.h:36
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:63
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:68
USB_FS_CORE_ID
Definition: usb_defines.h:90
USBFS_MAX_FIFO_WORDLEN
#define USBFS_MAX_FIFO_WORDLEN
Definition: usb_defines.h:28
USBFS_MAX_DEV_EPCOUNT
#define USBFS_MAX_DEV_EPCOUNT
Definition: usb_defines.h:27
usb_core_cfgs_struct::max_fifo_size
uint16_t max_fifo_size
Definition: usb_core.h:70
usb_core_cfgs_struct::core_id
uint8_t core_id
Definition: usb_core.h:62
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:65
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:203
void* usb_fifo_read | ( | uint8_t * | dest,
 |  | uint16_t | len
 | ) |  |

read a packet from the Rx FIFO associated with the endpoint

Parameters
[in] | dest | pointer to destination buffer
[in] | len | packet length
[out] | none
Return values
void type pointer

Definition at line 105 of file usb_core.c.

106 {
107 uint32_t i = 0U;
108 uint32_t count32b = (len + 3U) / 4U;
109
110 __IO uint32_t *fifo = USB_FIFO(0U);
111
112 for (i = 0U; i < count32b; i++) {
113 *(__packed uint32_t *)dest = *fifo;
114
115 dest += 4U;
116 }
117
118 return ((void *)dest);
119 }
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:94
usb_status_enum usb_fifo_write | ( | uint8_t * | src,
 |  | uint8_t | chep_num,
 |  | uint16_t | len
 | ) |  |

write a packet into the Tx FIFO associated with the endpoint

Parameters
[in] | src | pointer to source buffer
[in] | chep_num | channel or endpoint identifier which is in (0..3)
[in] | len | packet length
[out] | none
Return values
operation status

Definition at line 82 of file usb_core.c.

83 {
84 uint32_t count32b = 0U, i = 0U;
85 __IO uint32_t *fifo = USB_FIFO(chep_num);
86
87 count32b = (len + 3U) / 4U;
88
89 for (i = 0U; i < count32b; i++) {
90 *fifo = *((__packed uint32_t *)src);
91
92 src += 4U;
93 }
94
95 return USB_OK;
96 }
USB_OK
Definition: usb_core.h:30
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:94
usb_status_enum usb_mode_set | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | mode
 | ) |  |

set operation mode (host or device)

Parameters
[in] | pudev | pointer to usb device
[in] mode operation mode which need to set
  • HOST_MODE
  • DEVICE_MODE
[out] | none
Return values
operation status

Definition at line 268 of file usb_core.c.

269 {
270 if (HOST_MODE == mode) {
271 USB_GUSBCS &= ~GUSBCS_FDM;
272 USB_GUSBCS |= GUSBCS_FHM;
273 } else if (DEVICE_MODE == mode) {
274 USB_GUSBCS &= ~GUSBCS_FHM;
275 USB_GUSBCS |= GUSBCS_FDM;
276 } else {
277 /* no operation */
278 }
279
280 if (NULL != pudev->mdelay) {
281 pudev->mdelay(50U);
282 }
283
284 return USB_OK;
285 }
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:49
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:39
GUSBCS_FDM
#define GUSBCS_FDM
Definition: usb_regs.h:122
USB_OK
Definition: usb_core.h:30
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
GUSBCS_FHM
#define GUSBCS_FHM
Definition: usb_regs.h:123
NULL
#define NULL
Definition: usbd_std.h:20
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:48
usb_status_enum usb_rxfifo_flush ( usb_core_handle_struct * pudev )

flush the entire Rx FIFO

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 238 of file usb_core.c.

239 {
240 uint32_t count = 0U;
241
242 USB_GRSTCTL = GRSTCTL_RXFF;
243
244 /* wait for Rx FIFO flush bit is set */
245 do {
246 if (++count > 200000U) {
247 break;
248 }
249 } while (USB_GRSTCTL & GRSTCTL_RXFF);
250
251 /* wait for 3 PHY clocks */
252 if (NULL != pudev->udelay) {
253 pudev->udelay(3U);
254 }
255
256 return USB_OK;
257 }
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:217
USB_OK
Definition: usb_core.h:30
GRSTCTL_RXFF
#define GRSTCTL_RXFF
Definition: usb_regs.h:132
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:40
NULL
#define NULL
Definition: usbd_std.h:20
usb_status_enum usb_txfifo_flush | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | fifo_num
 | ) |  |

flush a Tx FIFO or all Tx FIFOs

Parameters
[in] | pudev | pointer to usb device
[in] | fifo_num | FIFO number which is in (0..3)
[out] | none
Return values
operation status

Definition at line 211 of file usb_core.c.

212 {
213 uint32_t count = 0U;
214
215 USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF;
216
217 /* wait for Tx FIFO flush bit is set */
218 do {
219 if (++count > 200000U) {
220 break;
221 }
222 } while (USB_GRSTCTL & GRSTCTL_TXFF);
223
224 /* wait for 3 PHY clocks */
225 if (NULL != pudev->udelay) {
226 pudev->udelay(3U);
227 }
228
229 return USB_OK;
230 }
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:217
USB_OK
Definition: usb_core.h:30
GRSTCTL_TXFF
#define GRSTCTL_TXFF
Definition: usb_regs.h:131
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:40
NULL
#define NULL
Definition: usbd_std.h:20
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbd_core.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Functions
usbd_core.c File Reference
#include "usbd_core.h"
#include "usbd_std.h"

Go to the source code of this file.

Functions

void | usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initailizes the USB device-mode handler stack More...
void | usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc)
endpoint initialization More...
void | usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr)
endpoint deinitialize More...
void | usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data More...
void | usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data More...
usbd_status_enum | usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel More...
usbd_status_enum | usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
receive data on the control channel More...
usbd_status_enum | usbd_ctlstatus_tx (usb_core_handle_struct *pudev)
transmit status on the control channel More...
usbd_status_enum | usbd_ctlstatus_rx (usb_core_handle_struct *pudev)
receive status on the control channel More...
void | usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status More...
void | usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status More...
void | usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr)
flushes the FIFOs More...
uint16_t | usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num)
get the received data length More...

Function Documentation

usbd_status_enum usbd_ctlrx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | pbuf,
 |  | uint16_t | len
 | ) |  |

receive data on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
usb device operation status

Definition at line 334 of file usbd_core.c.

335 {
336 pudev->dev.sum_len = len;
337 pudev->dev.remain_len = len;
338 pudev->dev.ctl_status = USB_CTRL_DATA_OUT;
339
340 usbd_ep_rx (pudev, 0U, pbuf, len);
341
342 return USBD_OK;
343 }
USB_CTRL_DATA_OUT
Definition: usb_core.h:86
USBD_OK
Definition: usbd_core.h:84
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usbd_status_enum usbd_ctlstatus_rx ( usb_core_handle_struct * pudev )

receive status on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
usb device operation status

Definition at line 368 of file usbd_core.c.

369 {
370 pudev->dev.ctl_status = USB_CTRL_STATUS_OUT;
371
372 usbd_ep_rx (pudev, 0U, NULL, 0U);
373
374 usb_ep0_startout(pudev);
375
376 return USBD_OK;
377 }
USB_CTRL_STATUS_OUT
Definition: usb_core.h:88
USBD_OK
Definition: usbd_core.h:84
NULL
#define NULL
Definition: usbd_std.h:20
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usbd_status_enum usbd_ctlstatus_tx ( usb_core_handle_struct * pudev )

transmit status on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
usb device operation status

Definition at line 351 of file usbd_core.c.

352 {
353 pudev->dev.ctl_status = USB_CTRL_STATUS_IN;
354
355 usbd_ep_tx (pudev, 0U, NULL, 0U);
356
357 usb_ep0_startout(pudev);
358
359 return USBD_OK;
360 }
USB_CTRL_STATUS_IN
Definition: usb_core.h:87
USBD_OK
Definition: usbd_core.h:84
NULL
#define NULL
Definition: usbd_std.h:20
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
usbd_status_enum usbd_ctltx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | pbuf,
 |  | uint16_t | len
 | ) |  |

transmit data on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
usb device operation status

Definition at line 313 of file usbd_core.c.

314 {
315 usbd_status_enum ret = USBD_OK;
316
317 pudev->dev.sum_len = len;
318 pudev->dev.remain_len = len;
319 pudev->dev.ctl_status = USB_CTRL_DATA_IN;
320
321 usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len);
322
323 return ret;
324 }
USB_CTRL_DATA_IN
Definition: usb_core.h:85
USBD_OK
Definition: usbd_core.h:84
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
void usbd_ep_clear_stall | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

clear endpoint stalled status

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 416 of file usbd_core.c.

417 {
418 usb_ep_struct *ep;
419 uint8_t ep_num = ep_addr & 0x7FU;
420 __IO uint32_t devepctl = 0U;
421
422 if(ep_addr >> 7){
423 ep = &pudev->dev.in_ep[ep_num];
424
425 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
426
427 /* clear the IN endpoint stall bits */
428 devepctl &= ~DEPCTL_STALL;
429
430 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
431 devepctl |= DEPCTL_SEVNFRM;
432 }
433
434 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
435 } else {
436 ep = &pudev->dev.out_ep[ep_num];
437
438 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
439
440 /* clear the OUT endpoint stall bits */
441 devepctl &= ~DEPCTL_STALL;
442
443 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
444 devepctl |= DEPCTL_SEVNFRM;
445 }
446
447 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
448 }
449 }
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:55
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
usb_ep_struct
Definition: usbd_core.h:102
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:396
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:391
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:54
void usbd_ep_deinit | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

endpoint deinitialize

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 134 of file usbd_core.c.

135 {
136 uint32_t devepinten = 0U;
137 uint8_t ep_num = ep_addr & 0x7FU;
138
139 if (ep_addr >> 7) {
140 devepinten |= 1U << ep_num;
141
142 USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
143 } else {
144 devepinten |= (1U << ep_num) << 16U;
145
146 USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
147 }
148
149 /* disable the interrupts for this endpoint */
150 USB_DAEPINTEN &= ~devepinten;
151 }
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:72
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:402
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
void usbd_ep_fifo_flush | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

flushes the FIFOs

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 458 of file usbd_core.c.

459 {
460 if (ep_addr >> 7) {
461 usb_txfifo_flush(pudev, ep_addr & 0x7FU);
462 } else {
463 usb_rxfifo_flush(pudev);
464 }
465 }
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:211
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:238
void usbd_ep_init | ( | usb_core_handle_struct * | pudev,
 |  | const usb_descriptor_endpoint_struct * | ep_desc
 | ) |  |

endpoint initialization

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_desc | pointer to usb endpoint descriptor
[out] | none
Return values
none

Definition at line 67 of file usbd_core.c.

68 {
69 usb_ep_struct *ep;
70 usb_dir_enum ep_dir;
71
72 uint32_t devepinten = 0U;
73 uint32_t devepctl = 0U;
74
75 uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU;
76 uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK;
77 uint16_t ep_mps = ep_desc->wMaxPacketSize;
78
79 if (ep_desc->bEndpointAddress >> 7) {
80 ep = &pudev->dev.in_ep[ep_num];
81
82 devepinten |= 1U << ep_num;
83 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
84
85 ep_dir = USB_TX;
86 } else {
87 ep = &pudev->dev.out_ep[ep_num];
88
89 devepinten |= (1U << ep_num) << 16;
90 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
91
92 ep_dir = USB_RX;
93 }
94
95 /* if the endpoint is not active, need change the endpoint control register */
96 if (!(devepctl & DEPCTL_EPACT)) {
97 devepctl &= ~DEPCTL_MPL;
98 devepctl |= ep_mps;
99
100 devepctl &= ~DEPCTL_EPTYPE;
101 devepctl |= (uint32_t)ep_type << 18;
102
103 if (USB_TX == ep_dir) {
104 devepctl &= ~DIEPCTL_TXFNUM;
105 devepctl |= (uint32_t)ep_num << 22;
106 }
107
108 devepctl |= DEPCTL_SD0PID;
109 devepctl |= DEPCTL_EPACT;
110 }
111
112 if (USB_TX == ep_dir) {
113 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
114 } else if (USB_RX == ep_dir) {
115 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
116 } else {
117 /* no operation */
118 }
119
120 ep->endp_mps = ep_mps;
121 ep->endp_type = ep_type;
122
123 /* enable the interrupts for this endpoint */
124 USB_DAEPINTEN |= devepinten;
125 }
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:162
USB_TX
Definition: usb_core.h:96
DEPCTL_EPTYPE
#define DEPCTL_EPTYPE
Definition: usb_regs.h:398
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:72
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usbd_std.h:161
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:402
USB_RX
Definition: usb_core.h:95
usb_ep_struct
Definition: usbd_core.h:102
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:93
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
DEPCTL_MPL
#define DEPCTL_MPL
Definition: usb_regs.h:403
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usbd_std.h:163
DIEPCTL_TXFNUM
#define DIEPCTL_TXFNUM
Definition: usb_regs.h:395
USB_EPTYPE_MASK
#define USB_EPTYPE_MASK
Definition: usbd_std.h:73
DEPCTL_SD0PID
#define DEPCTL_SD0PID
Definition: usb_regs.h:392
void usbd_ep_rx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint16_t | buf_len
 | ) |  |

endpoint prepare to receive data

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[in] | pbuf | pointer to buffer
[in] | buf_len | buffer length
[out] | none
Return values
none

Definition at line 162 of file usbd_core.c.

163 {
164 usb_ep_struct *ep;
165 uint8_t ep_num = ep_addr & 0x7FU;
166 uint32_t devepctl = 0U, devepxlen = 0U;
167
168 ep = &pudev->dev.out_ep[ep_num];
169
170 /* setup and start the Xfer */
171 ep->xfer_buff = pbuf;
172 ep->xfer_len = buf_len;
173 ep->xfer_count = 0U;
174
175 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
176 devepxlen = USB_DOEPxLEN((uint16_t)ep_num);
177
178 devepxlen &= ~DEPLEN_TLEN;
179 devepxlen &= ~DEPLEN_PCNT;
180
181 /* zero length packet */
182 if (0U == ep->xfer_len) {
183 /* set the transfer length to max packet size */
184 devepxlen |= ep->endp_mps;
185
186 /* set the transfer packet count to 1 */
187 devepxlen |= 1U << 19U;
188 } else {
189
190 if (0U == ep_num) {
191 /* set the transfer length to max packet size */
192 devepxlen |= ep->endp_mps;
193
194 /* set the transfer packet count to 1 */
195 devepxlen |= 1U << 19U;
196 } else {
197 /* configure the transfer size and packet count as follows:
198 * pktcnt = N
199 * xfersize = N * maxpacket
200 */
201 devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U;
202 devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps;
203 }
204 }
205
206 USB_DOEPxLEN((uint16_t)ep_num) = devepxlen;
207
208 if (USB_EPTYPE_ISOC == ep->endp_type) {
209 if (ep->endp_frame) {
210 devepctl |= DEPCTL_SODDFRM;
211 } else {
212 devepctl |= DEPCTL_SEVNFRM;
213 }
214 }
215
216 /* enable the endpoint and clear the NAK */
217 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
218
219 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
220 }
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:53
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:109
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:387
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:108
usb_ep_struct::endp_frame
uint8_t endp_frame
Definition: usb_core.h:103
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:434
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:433
usb_ep_struct
Definition: usbd_core.h:102
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:89
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:394
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:391
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:389
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
void usbd_ep_stall | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

set an endpoint to STALL status

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 386 of file usbd_core.c.

387 {
388 uint8_t ep_num = ep_addr & 0x7FU;
389 __IO uint32_t devepctl = 0U;
390
391 if (ep_addr >> 7U) {
392 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
393
394 /* set the endpoint disable bit */
395 if (devepctl & DEPCTL_EPEN) {
396 devepctl |= DEPCTL_EPD;
397 }
398
399 /* set the endpoint stall bit */
400 devepctl |= DEPCTL_STALL;
401
402 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
403 } else {
404 /* set the endpoint stall bit */
405 USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL;
406 }
407 }
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:387
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:388
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:396
void usbd_ep_tx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint32_t | buf_len
 | ) |  |

endpoint prepare to transmit data

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
none

Definition at line 231 of file usbd_core.c.

232 {
233 usb_ep_struct *ep;
234 uint8_t ep_num = ep_addr & 0x7FU;
235 __IO uint32_t devepctl = 0U;
236 __IO uint32_t deveplen = 0U;
237
238 ep = &pudev->dev.in_ep[ep_num];
239
240 /* setup and start the transfer */
241 ep->xfer_buff = pbuf;
242 ep->xfer_len = buf_len;
243 ep->xfer_count = 0U;
244
245 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
246 deveplen = USB_DIEPxLEN((uint16_t)ep_num);
247
248 /* clear transfer length to 0 */
249 deveplen &= ~DEPLEN_TLEN;
250
251 /* clear transfer packet to 0 */
252 deveplen &= ~DEPLEN_PCNT;
253
254 /* zero length packet */
255 if (0U == ep->xfer_len) {
256 /* set transfer packet count to 1 */
257 deveplen |= 1U << 19U;
258 } else {
259 if (0U == ep_num) {
260 if (ep->xfer_len > ep->endp_mps) {
261 ep->xfer_len = ep->endp_mps;
262 }
263
264 deveplen |= 1U << 19U;
265 } else {
266 deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U;
267 }
268
269 /* configure the transfer size and packet count as follows:
270 * xfersize = N * maxpacket + short_packet
271 * pktcnt = N + (short_packet exist ? 1 : 0)
272 */
273 deveplen |= ep->xfer_len;
274
275 if (USB_EPTYPE_ISOC == ep->endp_type) {
276 deveplen |= DIEPLEN_MCNT & (1U << 29U);
277 }
278 }
279
280 USB_DIEPxLEN((uint16_t)ep_num) = deveplen;
281
282 if (USB_EPTYPE_ISOC == ep->endp_type) {
283 if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) {
284 devepctl |= DEPCTL_SODDFRM;
285 } else {
286 devepctl |= DEPCTL_SEVNFRM;
287 }
288 }
289
290 /* enable the endpoint and clear the NAK */
291 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
292
293 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
294
295 if (USB_EPTYPE_ISOC != ep->endp_type) {
296 /* enable the Tx FIFO empty interrupt for this endpoint */
297 if (ep->xfer_len > 0U) {
298 USB_DIEPFEINTEN |= 1U << ep_num;
299 }
300 } else {
301 usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len);
302 }
303 }
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:53
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:109
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:387
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:82
DIEPLEN_MCNT
#define DIEPLEN_MCNT
Definition: usb_regs.h:432
USB_DIEPxLEN
#define USB_DIEPxLEN(x)
Definition: usb_regs.h:88
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:108
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:434
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:433
usb_ep_struct
Definition: usbd_core.h:102
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:68
DSTAT_FNRSOF
#define DSTAT_FNRSOF
Definition: usb_regs.h:338
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:75
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:394
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:391
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:389
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
void usbd_init | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initailizes the USB device-mode handler stack

Parameters
[in] | pudev | pointer to usb device instance
[in] | core_id | USB core ID
[out] | none
Return values
none

Definition at line 23 of file usbd_core.c.

24 {
25 /* select USB core */
26 usb_core_select (pudev, core_id);
27
28 pudev->dev.status = USB_STATUS_DEFAULT;
29
30 /* disable USB global interrupt */
31 USB_GLOBAL_INT_DISABLE();
32
33 /* init the core (common init.) */
34 usb_core_init(pudev);
35
36 /* force device mode*/
37 usb_mode_set(pudev, DEVICE_MODE);
38
39 /* set device disconnect */
40 USB_SOFT_DISCONNECT_ENABLE();
41
42 if ((void *)0 != pudev->mdelay) {
43 pudev->mdelay(3U);
44 }
45
46 /* init device */
47 usb_devcore_init(pudev);
48
49 /* set device Connect */
50 USB_SOFT_DISCONNECT_DISABLE();
51
52 if ((void *)0 != pudev->mdelay) {
53 pudev->mdelay(3U);
54 }
55
56 /* enable USB global interrupt */
57 USB_GLOBAL_INT_ENABLE();
58 }
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:128
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:268
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:21
USB_SOFT_DISCONNECT_DISABLE
#define USB_SOFT_DISCONNECT_DISABLE()
Definition: usb_regs.h:550
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:493
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:490
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:170
USB_SOFT_DISCONNECT_ENABLE
#define USB_SOFT_DISCONNECT_ENABLE()
Definition: usb_regs.h:547
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:48
uint16_t usbd_rxcount_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

get the received data length

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_num | endpoint identifier which is in (0..3)
[out] | none
Return values
received data length

Definition at line 474 of file usbd_core.c.

475 {
476 return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count;
477 }


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbd_int.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Functions
usbd_int.c File Reference
#include "usbd_int.h"
#include "usbd_std.h"

Go to the source code of this file.

Functions

uint32_t usbd_isr (usb_core_handle_struct *pudev)
USB device-mode interrupts global service routine handler. More...

Function Documentation

uint32_t usbd_isr ( usb_core_handle_struct * pudev )

USB device-mode interrupts global service routine handler.

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
operation status

Definition at line 58 of file usbd_int.c.

59 {
60 uint32_t retval = 0U;
61 uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN;
62
63 /* ensure the core is in device mode */
64 if (DEVICE_MODE == USB_CURRENT_MODE_GET()) {
65 int_status = gintf & ginten;
66
67 /* there are no interrupts, avoid spurious interrupt */
68 if (!int_status) {
69 return 0U;
70 }
71
72 /* OUT endpoints interrupts */
73 if (int_status & GINTF_OEPIF) {
74 retval |= usbd_intf_outep(pudev);
75 }
76
77 /* IN endpoints interrupts */
78 if (int_status & GINTF_IEPIF) {
79 retval |= usbd_intf_inep(pudev);
80 }
81
82 /* mode mismatch interrupt */
83 if (int_status & GINTF_MFIF) {
84 /* clear interrupt */
85 USB_GINTF = GINTF_MFIF;
86 }
87
88 /* early suspend interrupt */
89 if (int_status & GINTF_ESP) {
90 retval |= usbd_intf_earlysuspend(pudev);
91 }
92
93 /* suspend interrupt */
94 if (int_status & GINTF_SP) {
95 retval |= usbd_intf_suspend(pudev);
96 }
97
98 /* wakeup interrupt */
99 if (int_status & GINTF_WKUPIF) {
100 retval |= usbd_intf_resume(pudev);
101 }
102
103 /* start of frame interrupt */
104 if (int_status & GINTF_SOF) {
105 retval |= usbd_intf_sof(pudev);
106 }
107
108 /* reveive fifo not empty interrupt */
109 if (int_status & GINTF_RXFNEIF) {
110 retval |= usbd_intf_rxfifo(pudev);
111 }
112
113 /* USB reset interrupt */
114 if (int_status & GINTF_RST) {
115 retval |= usbd_intf_reset(pudev);
116 }
117
118 /* enumeration has been finished interrupt */
119 if (int_status & GINTF_ENUMF) {
120 retval |= usbd_intf_enumfinish(pudev);
121 }
122
123 /* incomplete synchronization in transfer interrupt*/
124 if (int_status & GINTF_ISOINCIF) {
125 retval |= usbd_intf_isoinincomplete(pudev);
126 }
127
128 /* incomplete synchronization out transfer interrupt*/
129 if (int_status & GINTF_ISOONCIF) {
130 retval |= usbd_intf_isooutincomplete(pudev);
131 }
132
133 #ifdef VBUS_SENSING_ENABLED
134
135 /* session request interrupt */
136 if (int_status & GINTF_SESIF) {
137 retval |= usbd_intf_sessionrequest(pudev);
138 }
139
140 /* OTG mode interrupt */
141 if (int_status & GINTF_OTGIF) {
142 retval |= usbd_intf_otg(pudev);
143 }
144 #endif /* VBUS_SENSING_ENABLED */
145 }
146
147 return retval;
148 }
GINTF_IEPIF
#define GINTF_IEPIF
Definition: usb_regs.h:149
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:159
GINTF_ISOINCIF
#define GINTF_ISOINCIF
Definition: usb_regs.h:147
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:42
GINTF_SESIF
#define GINTF_SESIF
Definition: usb_regs.h:139
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:41
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:496
GINTF_OEPIF
#define GINTF_OEPIF
Definition: usb_regs.h:148
GINTF_ESP
#define GINTF_ESP
Definition: usb_regs.h:155
GINTF_OTGIF
#define GINTF_OTGIF
Definition: usb_regs.h:161
GINTF_SP
#define GINTF_SP
Definition: usb_regs.h:154
GINTF_WKUPIF
#define GINTF_WKUPIF
Definition: usb_regs.h:138
GINTF_RST
#define GINTF_RST
Definition: usb_regs.h:153
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:146
GINTF_ENUMF
#define GINTF_ENUMF
Definition: usb_regs.h:152
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:160
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:48
GINTF_MFIF
#define GINTF_MFIF
Definition: usb_regs.h:162
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbd_std.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Functions
usbd_std.c File Reference
#include "usbd_std.h"
#include "usb_core.h"

Go to the source code of this file.

Functions

usbd_status_enum | usbd_setup_transaction (usb_core_handle_struct *pudev)
USB setup stage processing. More...
usbd_status_enum | usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
data out stage processing More...
usbd_status_enum | usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
data in stage processing More...
void | usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB low level error event More...

Function Documentation

void usbd_enum_error | ( | usb_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB low level error event

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
none

Definition at line 689 of file usbd_std.c.

690 {
691 usbd_ep_stall(pudev, 0x80U);
692 usbd_ep_stall(pudev, 0x00U);
693 usb_ep0_startout(pudev);
694 }
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usbd_status_enum usbd_in_transaction | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | endp_num
 | ) |  |

data in stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_id | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 143 of file usbd_std.c.

144 {
145 usb_ep_struct *ep;
146
147 if (0U == endp_num) {
148 ep = &pudev->dev.in_ep[0];
149
150 if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) {
151 if (pudev->dev.remain_len > ep->endp_mps) {
152 pudev->dev.remain_len -= ep->endp_mps;
153
154 usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len);
155
156 usbd_ep_rx (pudev, 0U, NULL, 0U);
157 } else {
158 /* last packet is MPS multiple, so send ZLP packet */
159 if ((pudev->dev.sum_len % ep->endp_mps == 0U) &&
160 (pudev->dev.sum_len >= ep->endp_mps) &&
161 (pudev->dev.sum_len < pudev->dev.ctl_len)) {
162 usbd_ep_tx (pudev, 0U, NULL, 0U);
163 pudev->dev.ctl_len = 0U;
164
165 usbd_ep_rx (pudev, 0U, NULL, 0U);
166 } else {
167 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
168 pudev->dev.class_data_handler(pudev, USB_TX, 0U);
169 }
170
171 usbd_ctlstatus_rx(pudev);
172 }
173 }
174 }
175 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
176 pudev->dev.class_data_handler(pudev, USB_TX, endp_num);
177 } else {
178 /* no operation */
179 }
180
181 return USBD_OK;
182 }
USB_TX
Definition: usb_core.h:96
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
USB_CTRL_DATA_IN
Definition: usb_core.h:85
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:368
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usb_ep_struct
Definition: usbd_core.h:102
USBD_OK
Definition: usbd_core.h:84
NULL
#define NULL
Definition: usbd_std.h:20
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:23
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
usbd_status_enum usbd_out_transaction | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | endp_num
 | ) |  |

data out stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_id | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 104 of file usbd_std.c.

105 {
106 usb_ep_struct *ep;
107
108 if (0U == endp_num) {
109 ep = &pudev->dev.out_ep[0];
110
111 if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) {
112 if (pudev->dev.remain_len > ep->endp_mps) {
113 pudev->dev.remain_len -= ep->endp_mps;
114
115 usbd_ep_rx (pudev,
116 0U,
117 ep->xfer_buff,
118 (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps));
119 } else {
120 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
121 pudev->dev.class_data_handler(pudev, USB_RX, 0U);
122 }
123
124 usbd_ctlstatus_tx(pudev);
125 }
126 }
127 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
128 pudev->dev.class_data_handler(pudev, USB_RX, endp_num);
129 } else {
130 /* no operation */
131 }
132
133 return USBD_OK;
134 }
USB_CTRL_DATA_OUT
Definition: usb_core.h:86
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:351
USB_RX
Definition: usb_core.h:95
usb_ep_struct
Definition: usbd_core.h:102
USBD_OK
Definition: usbd_core.h:84
USB_MIN
#define USB_MIN(a, b)
Definition: usbd_std.h:43
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:23
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
usbd_status_enum usbd_setup_transaction ( usb_core_handle_struct * pudev )

USB setup stage processing.

Parameters
[in] | pudev | pointer to USB device instance
[out] | none
Return values
USB device operation status

Definition at line 70 of file usbd_std.c.

71 {
72 usb_device_req_struct req;
73
74 usbd_setup_request_parse(pudev, &req);
75
76 switch (req.bmRequestType & USB_REQ_MASK) {
77 /* standard device request */
78 case USB_STANDARD_REQ:
79 usbd_standard_request(pudev, &req);
80 break;
81 /* device class request */
82 case USB_CLASS_REQ:
83 usbd_device_class_request(pudev, &req);
84 break;
85 /* vendor defined request */
86 case USB_VENDOR_REQ:
87 usbd_vendor_request(pudev, &req);
88 break;
89 default:
90 usbd_ep_stall(pudev, req.bmRequestType & 0x80U);
91 break;
92 }
93
94 return USBD_OK;
95 }
usbd_standard_request
uint8_t usbd_standard_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB standard device request
Definition: usbd_std.c:220
USB_VENDOR_REQ
#define USB_VENDOR_REQ
Definition: usbd_std.h:36
USB_CLASS_REQ
#define USB_CLASS_REQ
Definition: usbd_std.h:35
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usb_device_req_struct
Definition: usbd_core.h:115
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usbd_core.h:117
usbd_device_class_request
uint8_t usbd_device_class_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB device class request
Definition: usbd_std.c:235
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
USBD_OK
Definition: usbd_core.h:84
USB_REQ_MASK
#define USB_REQ_MASK
Definition: usbd_std.h:37
usbd_vendor_request
uint8_t usbd_vendor_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB vendor request
Definition: usbd_std.c:268
usbd_setup_request_parse
void usbd_setup_request_parse(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
decode setup data packet
Definition: usbd_std.c:812
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_core.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Functions | Variables
usbh_core.c File Reference

this file implements the functions for the core state machine process More...

#include "usbh_hcs.h"
#include "usbh_core.h"
#include "usbh_int.h"
#include "stdio.h"
#include "usbh_std.h"
#include "usbh_ctrl.h"
#include "usb_core.h"

Go to the source code of this file.

Functions

uint8_t | usbh_sof (usb_core_handle_struct *pudev)
usb sof callback function from the interrupt. More...
uint8_t | usbh_connected (usb_core_handle_struct *pudev)
usb connect callback function from the interrupt. More...
uint8_t | usbh_disconnected (usb_core_handle_struct *pudev)
usb disconnect callback function from the interrupt. More...
usbh_status_enum | host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of HOST state More...
uint32_t | hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize the host portion of the driver. More...
uint32_t | hcd_is_device_connected (usb_core_handle_struct *pudev)
check if the device is connected. More...
urb_state_enum | hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate More...
uint32_t | hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate More...
usbh_status_enum | usbh_deinit (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
de-initialize host More...
void | scd_init (usbh_state_handle_struct *pustate)
state core driver init More...
void | scd_table_regist (usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist More...
void | scd_begin (usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin More...
void | scd_state_move (usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state More...
usbh_status_enum | scd_event_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle More...
void | scd_table_push (usbh_state_handle_struct *pustate)
state core driver table push More...
void | scd_table_pop (usbh_state_handle_struct *pustate)
state core driver table pop More...
usbh_status_enum | only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move More...
usbh_status_enum | goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state More...

Variables

class_polling_fun_cb_struct | class_polling_cb
usbh_hcd_int_cb_struct usbh_hcd_int_cb
usbh_hcd_int_cb_struct * usbh_hcd_int_fops = &usbh_hcd_int_cb
usbh_state_handle_struct usbh_state_core
void(* | host_state_handle [])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
state_table_struct host_handle_table [HOST_HANDLE_TABLE_SIZE]

Detailed Description

this file implements the functions for the core state machine process

Definition in file usbh_core.c.

Function Documentation

usbh_status_enum goto_up_state_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the function to the up state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 706 of file usbh_core.c.

707 {
708 scd_table_pop((usbh_state_handle_struct *)pustate);
709
710 return USBH_OK;
711 }
usbh_state_handle_struct
Definition: usbh_core.h:228
scd_table_pop
void scd_table_pop(usbh_state_handle_struct *pustate)
state core driver table pop
Definition: usbh_core.c:645
USBH_OK
Definition: usbh_core.h:109
uint32_t hcd_init | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initialize the host portion of the driver.

Parameters
[in] | pudev | pointer to usb device
[in] | core_id | usb otg core identifier(high-speed or full-speed)
[out] | none
Return values
operation status

Definition at line 386 of file usbh_core.c.

387 {
388 pudev->host.connect_status = 0U;
389
390 pudev->host.host_channel[0].endp_mps = 8U;
391
392 usb_core_select(pudev, core_id);
393
394 #ifndef DUAL_ROLE_MODE_ENABLED
395
396 USB_GLOBAL_INT_DISABLE();
397
398 usb_core_init(pudev);
399
400 /* force host mode*/
401 usb_mode_set(pudev, HOST_MODE);
402
403 usb_hostcore_init(pudev);
404
405 USB_GLOBAL_INT_ENABLE();
406
407 #endif
408
409 return 0U;
410 }
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:128
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:49
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:268
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:493
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:490
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:170
uint32_t hcd_is_device_connected ( usb_core_handle_struct * pudev )

check if the device is connected.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
device connection status. 1 -> connected and 0 -> disconnected

Definition at line 418 of file usbh_core.c.

419 {
420 return (uint32_t)(pudev->host.connect_status);
421 }
urb_state_enum hcd_urb_state_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function returns the last URBstate

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
urb_state_enum

Definition at line 430 of file usbh_core.c.

431 {
432 return pudev->host.host_channel[channel_num].urb_state;
433 }
uint32_t hcd_xfer_count_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function returns the last URBstate

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
No. of data bytes transferred

Definition at line 442 of file usbh_core.c.

443 {
444 return pudev->host.host_channel[channel_num].xfer_count;
445 }
usbh_status_enum host_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of HOST state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 89 of file usbh_core.c.

92 {
93 usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate;
94
95 scd_begin(p_state, HOST_FSM_ID);
96
97 if (-1 == p_state->usbh_current_state_stack_top) {
98 uint8_t cur_state = p_state->usbh_current_state;
99
100 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) {
101 if (HOST_DEV_DETACHED != cur_state) {
102 p_state->usbh_current_state = HOST_DEV_DETACHED;
103 cur_state = HOST_DEV_DETACHED;
104 }
105 }
106
107 host_state_handle[cur_state](pudev, puhost, p_state);
108 } else {
109 uint8_t stack0_state = p_state->stack[0].state;
110
111 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) {
112 if (HOST_DEV_DETACHED != stack0_state) {
113 p_state->stack[0].state = HOST_DEV_DETACHED;
114 stack0_state = HOST_DEV_DETACHED;
115 p_state->usbh_current_state = HOST_DEV_DETACHED;
116 }
117 }
118
119 host_state_handle[stack0_state](pudev, puhost, p_state);
120 }
121
122 return USBH_OK;
123 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
usbh_state_handle_struct
Definition: usbh_core.h:228
hcd_is_device_connected
uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
check if the device is connected.
Definition: usbh_core.c:418
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
HOST_DEV_DETACHED
Definition: usbh_core.h:56
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:39
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
host_state_handle
void(* host_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_core.c:52
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
USBH_OK
Definition: usbh_core.h:109
HOST_IDLE
Definition: usbh_core.h:54
usbh_status_enum only_state_move | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the function is only used to state move

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 693 of file usbh_core.c.

694 {
695 return USBH_OK;
696 }
USBH_OK
Definition: usbh_core.h:109
void scd_begin | ( | usbh_state_handle_struct * | pustate,
 |  | uint8_t | table_id
 | ) |  |

state core driver begin

Parameters
[in] | pustate | pointer to usb state driver
[in] | table_id | the id of the table to begin
[out] | none
Return values
none

Definition at line 539 of file usbh_core.c.

540 {
541 uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num;
542 usbh_state_regist_table_struct *cur_state_reg_table;
543
544 for (i = 0U; i < table_num; i++) {
545 cur_state_reg_table = &pustate->usbh_regist_state_table[i];
546
547 if (table_id == cur_state_reg_table->id) {
548 pustate->usbh_current_state_table = cur_state_reg_table->table;
549 pustate->usbh_current_state_table_size = cur_state_reg_table->table_size;
550 break;
551 }
552 }
553 }
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:237
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:238
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:224
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:222
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:223
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
usbh_state_regist_table_struct
Definition: usbh_core.h:220
usbh_status_enum scd_event_handle | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | usbh_state_handle_struct * | pustate,
 |  | uint8_t | event,
 |  | uint8_t | state
 | ) |  |

state core driver event handle

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[in] | event | the current event
[in] | state | the current state
[out] | none
Return values
host status

Definition at line 577 of file usbh_core.c.

582 {
583 uint8_t i = 0U;
584 ACT_FUN event_act_fun = NULL;
585 state_table_struct *backup_state_t = pustate->usbh_current_state_table;
586 state_table_struct *executive_state_table = pustate->usbh_current_state_table;
587
588 /* look up the table to find the action function */
589 for (i = 0U; i < pustate->usbh_current_state_table_size; i++) {
590 if (state == executive_state_table->cur_state) {
591 if (event == executive_state_table->cur_event) {
592 state = executive_state_table->next_state;
593 event_act_fun = executive_state_table->event_action_fun;
594 break;
595 } else {
596 executive_state_table++;
597 }
598 } else {
599 executive_state_table++;
600 }
601 }
602
603 pustate->usbh_current_state_table = backup_state_t;
604
605 /* if the action function is not NULL, execute the action function */
606 if (event_act_fun) {
607 if (event_act_fun == &only_state_move) {
608 pustate->usbh_current_state = state;
609 } else {
610 return event_act_fun(pudev, puhost, pustate);
611 }
612 }
613
614 return USBH_BUSY;
615 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
state_table_struct::event_action_fun
ACT_FUN event_action_fun
Definition: usbh_core.h:208
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
state_table_struct::next_state
uint8_t next_state
Definition: usbh_core.h:207
state_table_struct
Definition: usbh_core.h:203
state_table_struct::cur_state
uint8_t cur_state
Definition: usbh_core.h:205
ACT_FUN
usbh_status_enum(* ACT_FUN)(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
Definition: usbh_core.h:200
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
NULL
#define NULL
Definition: usbd_std.h:20
USBH_BUSY
Definition: usbh_core.h:110
state_table_struct::cur_event
uint8_t cur_event
Definition: usbh_core.h:206
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:693
void scd_init ( usbh_state_handle_struct * pustate )

state core driver init

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 485 of file usbh_core.c.

486 {
487 /* init the state core */
488 pustate->usbh_current_state = 0U;
489 pustate->usbh_current_state_table = NULL;
490 pustate->usbh_current_state_table_size = 0U;
491
492 pustate->usbh_current_state_stack_top = -1;
493 pustate->stack->state = 0U;
494 pustate->stack->table_size = 0U;
495 pustate->stack->table = NULL;
496
497 pustate->usbh_regist_state_table_num = 0U;
498 pustate->usbh_regist_state_table->table = NULL;
499 pustate->usbh_regist_state_table->table_size = 0U;
500 pustate->usbh_regist_state_table->id = 0U;
501
502 /* init the control and the enumeration polling handle flag */
503 ctrl_polling_handle_flag = 0U;
504 enum_polling_handle_flag = 0U;
505 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:20
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:237
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:238
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:224
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:222
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:215
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:17
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:223
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:216
NULL
#define NULL
Definition: usbd_std.h:20
void scd_state_move | ( | usbh_state_handle_struct * | pustate,
 |  | uint8_t | state
 | ) |  |

state core driver move state

Parameters
[in] | pustate | pointer to usb state driver
[in] | state | the state to move
[out] | none
Return values
none

Definition at line 562 of file usbh_core.c.

563 {
564 pustate->usbh_current_state = state;
565 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
void scd_table_pop ( usbh_state_handle_struct * pustate )

state core driver table pop

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 645 of file usbh_core.c.

646 {
647 usbh_state_stack_struct *top_state_element;
648
649 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
650
651 if (pustate->usbh_current_state_stack_top > -1) {
652 /* get the current state table from the state stack */
653 pustate->usbh_current_state = top_state_element->state;
654 pustate->usbh_current_state_table = top_state_element->table;
655 pustate->usbh_current_state_table_size = top_state_element->table_size;
656 pustate->usbh_current_state_stack_top--;
657 }
658 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
usbh_state_stack_struct
Definition: usbh_core.h:212
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:215
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:216
void scd_table_push ( usbh_state_handle_struct * pustate )

state core driver table push

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 623 of file usbh_core.c.

624 {
625 usbh_state_stack_struct *top_state_element;
626
627 if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) {
628 pustate->usbh_current_state_stack_top++;
629
630 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
631
632 /* put the current state table into the state stack */
633 top_state_element->state = pustate->usbh_current_state;
634 top_state_element->table = pustate->usbh_current_state_table;
635 top_state_element->table_size = pustate->usbh_current_state_table_size;
636 }
637 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
usbh_state_stack_struct
Definition: usbh_core.h:212
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:215
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:216
MAX_USBH_STATE_STACK_DEEP
#define MAX_USBH_STATE_STACK_DEEP
Definition: usbh_core.h:36
void scd_table_regist | ( | usbh_state_handle_struct * | pustate,
 |  | state_table_struct * | pstate_table,
 |  | uint8_t | table_id,
 |  | uint8_t | current_table_size
 | ) |  |

state core driver table regist

Parameters
[in] | pustate | pointer to usb state driver
[in] | pstate_table | pointer to the table to regist
[in] | table_id | the id of the table to regist
[in] | current_table_size | the size of the current table to regist
[out] | none
Return values
none

Definition at line 516 of file usbh_core.c.

520 {
521 usbh_state_regist_table_struct *cur_state_reg_table;
522
523 cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num];
524
525 cur_state_reg_table->id = table_id;
526 cur_state_reg_table->table = pstate_table;
527 cur_state_reg_table->table_size = current_table_size;
528
529 pustate->usbh_regist_state_table_num++;
530 }
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:237
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:238
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:224
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:222
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:223
usbh_state_regist_table_struct
Definition: usbh_core.h:220
uint8_t usbh_connected ( usb_core_handle_struct * pudev )

usb connect callback function from the interrupt.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 347 of file usbh_core.c.

348 {
349 pudev->host.connect_status = 1U;
350
351 return 0U;
352 }
usbh_status_enum usbh_deinit | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | usbh_state_handle_struct * | pustate
 | ) |  |

de-initialize host

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[out] | none
Return values
host status

Definition at line 454 of file usbh_core.c.

457 {
458 /* software init */
459
460 puhost->control.ep0_size = USB_MAX_EP0_SIZE;
461
462 puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT;
463 puhost->device.speed = HPRT_PRTSPD_FULL_SPEED;
464
465 usbh_channel_free(pudev, puhost->control.hc_in_num);
466 usbh_channel_free(pudev, puhost->control.hc_out_num);
467
468 scd_init(pustate);
469 scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE);
470 scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE);
471 scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE);
472
473 scd_begin(pustate,HOST_FSM_ID);
474 scd_state_move(pustate, HOST_IDLE);
475
476 return USBH_OK;
477 }
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:40
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:115
host_handle_table
state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE]
Definition: usbh_core.c:67
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:42
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:128
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
scd_table_regist
void scd_table_regist(usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist
Definition: usbh_core.c:516
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:130
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
scd_init
void scd_init(usbh_state_handle_struct *pustate)
state core driver init
Definition: usbh_core.c:485
CTRL_HANDLE_TABLE_SIZE
#define CTRL_HANDLE_TABLE_SIZE
Definition: usbh_ctrl.h:19
usbh_device_struct::speed
uint8_t speed
Definition: usbh_core.h:142
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:39
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:141
ctrl_handle_table
state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Definition: usbh_ctrl.c:47
HPRT_PRTSPD_FULL_SPEED
#define HPRT_PRTSPD_FULL_SPEED
Definition: usb_defines.h:75
USB_MAX_EP0_SIZE
#define USB_MAX_EP0_SIZE
Definition: usb_core.h:20
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:193
USBH_OK
Definition: usbh_core.h:109
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:24
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:49
HOST_IDLE
Definition: usbh_core.h:54
USBH_DEVICE_ADDRESS_DEFAULT
#define USBH_DEVICE_ADDRESS_DEFAULT
Definition: usbh_core.h:25
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:129
HOST_HANDLE_TABLE_SIZE
#define HOST_HANDLE_TABLE_SIZE
Definition: usbh_core.h:49
uint8_t usbh_disconnected ( usb_core_handle_struct * pudev )

usb disconnect callback function from the interrupt.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 360 of file usbh_core.c.

361 {
362 pudev->host.connect_status = 0U;
363
364 return 0U;
365 }
uint8_t usbh_sof ( usb_core_handle_struct * pudev )

usb sof callback function from the interrupt.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 373 of file usbh_core.c.

374 {
375 /* this callback could be used to implement a scheduler process */
376 return 0U;
377 }

Variable Documentation

class_polling_fun_cb_struct class_polling_cb
state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE]
Initial value:
=
{
{HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move },
{HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move },
{HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move },
{HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move },
{HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move },
{HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move },
{HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move },
{HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move },
{HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move },
}
HOST_EVENT_IDLE
Definition: usbh_core.h:76
HOST_EVENT_CLASS_REQ
Definition: usbh_core.h:72
HOST_EVENT_CLASS
Definition: usbh_core.h:73
HOST_EVENT_ENUM
Definition: usbh_core.h:70
HOST_CLASS
Definition: usbh_core.h:60
HOST_ERROR
Definition: usbh_core.h:63
HOST_DEV_DETACHED
Definition: usbh_core.h:56
HOST_EVENT_ERROR
Definition: usbh_core.h:74
HOST_DEV_ATTACHED
Definition: usbh_core.h:55
HOST_ENUMERATION
Definition: usbh_core.h:58
HOST_EVENT_ATTACHED
Definition: usbh_core.h:69
HOST_CLASS_REQUEST
Definition: usbh_core.h:59
HOST_USER_INPUT
Definition: usbh_core.h:61
HOST_IDLE
Definition: usbh_core.h:54
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:693
HOST_EVENT_USER_INPUT
Definition: usbh_core.h:71

Definition at line 67 of file usbh_core.c.

void(* host_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Initial value:
=
{
host_idle_handle,
host_dev_attached_handle,
host_dev_detached_handle,
host_detect_dev_speed_handle,
host_enum_handle,
host_class_request_handle,
host_class_handle,
host_user_input_handle,
host_suspended_handle,
host_error_handle,
}

Definition at line 52 of file usbh_core.c.

usbh_hcd_int_cb_struct usbh_hcd_int_cb
Initial value:
=
{
usbh_sof,
usbh_connected,
usbh_disconnected,
}
usbh_connected
uint8_t usbh_connected(usb_core_handle_struct *pudev)
usb connect callback function from the interrupt.
Definition: usbh_core.c:347
usbh_sof
uint8_t usbh_sof(usb_core_handle_struct *pudev)
usb sof callback function from the interrupt.
Definition: usbh_core.c:373
usbh_disconnected
uint8_t usbh_disconnected(usb_core_handle_struct *pudev)
usb disconnect callback function from the interrupt.
Definition: usbh_core.c:360

Definition at line 27 of file usbh_core.c.

usbh_hcd_int_cb_struct* usbh_hcd_int_fops = &usbh_hcd_int_cb

Definition at line 34 of file usbh_core.c.

usbh_state_handle_struct usbh_state_core


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_ctrl.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Functions | Variables
usbh_ctrl.c File Reference

this file implements the functions for the control transmit process More...

#include "usbh_core.h"
#include "usbh_std.h"
#include "usbh_ctrl.h"

Go to the source code of this file.

Functions

usbh_status_enum | ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state More...
usbh_status_enum | usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len)
send datas from the host channel More...
usbh_status_enum | usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
send the setup packet to the device More...
uint32_t | hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer More...

Variables

uint8_t | ctrl_polling_handle_flag = 0U
uint8_t | ctrl_setup_wait_flag = 0U
uint8_t | ctrl_data_wait_flag = 0U
uint8_t | ctrl_status_wait_flag = 0U
void(* | ctrl_state_handle [])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
state_table_struct ctrl_handle_table [CTRL_HANDLE_TABLE_SIZE]

Detailed Description

this file implements the functions for the control transmit process

Definition in file usbh_ctrl.c.

Function Documentation

usbh_status_enum ctrl_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of CTRL state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 73 of file usbh_ctrl.c.

76 {
77 usbh_status_enum exe_state = USBH_BUSY;
78 usbh_state_handle_struct *p_state;
79
80 p_state = (usbh_state_handle_struct *)pustate;
81
82 /* if first enter this function, begin the ctrl state */
83 if (0U == ctrl_polling_handle_flag) {
84 ctrl_polling_handle_flag = 1U;
85 scd_table_push(p_state);
86 scd_state_move(p_state, CTRL_IDLE);
87 }
88
89 /* base on the current state to handle the ctrl state */
90 scd_begin(p_state, CTRL_FSM_ID);
91 ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
92
93 /* determine the control transfer whether to complete */
94 switch (puhost->usbh_backup_state.ctrl_backup_state) {
95 case CTRL_COMPLETE:
96 ctrl_polling_handle_flag = 0U;
97 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
98 exe_state = USBH_OK;
99 break;
100 case CTRL_STALLED:
101 ctrl_polling_handle_flag = 0U;
102 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
103 exe_state = USBH_NOT_SUPPORTED;
104 break;
105 case CTRL_ERROR:
106 ctrl_polling_handle_flag = 0U;
107 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
108 exe_state = USBH_FAIL;
109 break;
110 default:
111 exe_state = USBH_BUSY;
112 break;
113 }
114
115 return exe_state;
116 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
usbh_state_handle_struct
Definition: usbh_core.h:228
ctrl_state_handle
void(* ctrl_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_ctrl.c:33
CTRL_IDLE
Definition: usbh_core.h:97
CTRL_ERROR
Definition: usbh_core.h:101
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:42
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:17
USBH_NOT_SUPPORTED
Definition: usbh_core.h:112
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
CTRL_STALLED
Definition: usbh_core.h:102
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:623
USBH_OK
Definition: usbh_core.h:109
USBH_FAIL
Definition: usbh_core.h:111
CTRL_COMPLETE
Definition: usbh_core.h:103
USBH_BUSY
Definition: usbh_core.h:110
uint32_t hcd_submit_request | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function prepare a hc and start a transfer

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
host operation status

Definition at line 605 of file usbh_ctrl.c.

606 {
607 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
608
609 puhc->urb_state = URB_IDLE;
610 puhc->xfer_count = 0U;
611
612 return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num);
613 }
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:173
URB_IDLE
Definition: usb_core.h:51
usb_hostchannel_struct
Definition: usb_core.h:155
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:168
usbh_status_enum usbh_ctltx_setup | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | buf,
 |  | uint8_t | hc_num
 | ) |  |

send the setup packet to the device

Parameters
[in] | pudev | pointer to usb device
[in] | buf | buffer pointer from which the data will be send to device
[in] | hc_num | host channel number
[out] | none
Return values
host operation status

Definition at line 587 of file usbh_ctrl.c.

588 {
589 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
590
591 puhc->DPID = HC_PID_SETUP;
592 puhc->xfer_buff = buf;
593 puhc->xfer_len = USBH_SETUP_PACKET_SIZE;
594
595 return (usbh_status_enum)hcd_submit_request (pudev, hc_num);
596 }
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:605
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:166
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
usb_hostchannel_struct
Definition: usb_core.h:155
USBH_SETUP_PACKET_SIZE
#define USBH_SETUP_PACKET_SIZE
Definition: usbh_std.h:23
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:159
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:167
HC_PID_SETUP
#define HC_PID_SETUP
Definition: usb_defines.h:72
usbh_status_enum usbh_xfer | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | buf,
 |  | uint8_t | hc_num,
 |  | uint16_t | len
 | ) |  |

send datas from the host channel

Parameters
[in] | pudev | pointer to usb device
[in] | buf | data buffer address to send datas
[in] | hc_num | the number of the host channel
[in] | len | length of the send data
[out] | none
Return values
host operation status

Definition at line 494 of file usbh_ctrl.c.

498 {
499 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
500
501 puhc->xfer_buff = buf;
502 puhc->xfer_len = len;
503
504 switch (puhc->endp_type) {
505 case USB_EPTYPE_CTRL:
506 if (0U == puhc->endp_in) {
507 if (0U == len) {
508 /* for status out stage, length = 0, status out pid = 1 */
509 puhc->data_tg_out = 1U;
510 }
511
512 /* set the data toggle bit as per the flag */
513 if (0U == puhc->data_tg_out) {
514 /* put the pid 0 */
515 puhc->DPID = HC_PID_DATA0;
516 } else {
517 /* put the pid 1 */
518 puhc->DPID = HC_PID_DATA1;
519 }
520 } else {
521 puhc->DPID = HC_PID_DATA1;
522 }
523 break;
524
525 case USB_EPTYPE_ISOC:
526 puhc->DPID = HC_PID_DATA0;
527 break;
528
529 case USB_EPTYPE_BULK:
530 if (0U == puhc->endp_in) {
531 /* set the data toggle bit as per the flag */
532 if (0U == puhc->data_tg_out) {
533 /* put the pid 0 */
534 puhc->DPID = HC_PID_DATA0;
535 } else {
536 /* put the pid 1 */
537 puhc->DPID = HC_PID_DATA1;
538 }
539 } else {
540 if (0U == puhc->data_tg_in) {
541 puhc->DPID = HC_PID_DATA0;
542 } else {
543 puhc->DPID = HC_PID_DATA1;
544 }
545 }
546 break;
547
548 case USB_EPTYPE_INTR:
549 if (0U == puhc->endp_in) {
550 if (0U == puhc->data_tg_out) {
551 puhc->DPID = HC_PID_DATA0;
552 } else {
553 puhc->DPID = HC_PID_DATA1;
554 }
555
556 /* toggle data pid */
557 puhc->data_tg_out ^= 1U;
558 } else {
559 if (0U == puhc->data_tg_in) {
560 puhc->DPID = HC_PID_DATA0;
561 } else {
562 puhc->DPID = HC_PID_DATA1;
563 }
564
565 /* toggle data pid */
566 puhc->data_tg_in ^= 1U;
567 }
568 break;
569
570 default:
571 break;
572 }
573
574 hcd_submit_request (pudev, hc_num);
575
576 return USBH_OK;
577 }
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:605
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:53
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:166
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:176
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:55
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:161
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:52
HC_PID_DATA1
#define HC_PID_DATA1
Definition: usb_defines.h:71
usb_hostchannel_struct
Definition: usb_core.h:155
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:175
HC_PID_DATA0
#define HC_PID_DATA0
Definition: usb_defines.h:69
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:159
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:167
USBH_OK
Definition: usbh_core.h:109
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:162
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:54

Variable Documentation

uint8_t ctrl_data_wait_flag = 0U

Definition at line 19 of file usbh_ctrl.c.

state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Initial value:
=
{
{CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move },
{CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move },
{CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move },
{CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
{CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move },
{CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
{CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move },
{CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move },
{CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
{CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move },
{CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
{CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
{CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
}
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:706
CTRL_EVENT_ERROR
Definition: usbh_ctrl.h:32
CTRL_IDLE
Definition: usbh_core.h:97
CTRL_ERROR
Definition: usbh_core.h:101
UP_STATE
#define UP_STATE
Definition: usbh_core.h:46
CTRL_EVENT_SETUP
Definition: usbh_ctrl.h:28
GO_TO_UP_STATE_EVENT
#define GO_TO_UP_STATE_EVENT
Definition: usbh_core.h:47
CTRL_STATUS
Definition: usbh_core.h:100
CTRL_STALLED
Definition: usbh_core.h:102
CTRL_EVENT_DATA
Definition: usbh_ctrl.h:29
CTRL_EVENT_STALLED
Definition: usbh_ctrl.h:33
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:693
CTRL_SETUP
Definition: usbh_core.h:98
CTRL_EVENT_COMPLETE
Definition: usbh_ctrl.h:31
CTRL_COMPLETE
Definition: usbh_core.h:103
CTRL_DATA
Definition: usbh_core.h:99
CTRL_EVENT_STATUS
Definition: usbh_ctrl.h:30

Definition at line 47 of file usbh_ctrl.c.

uint8_t ctrl_polling_handle_flag = 0U

Definition at line 17 of file usbh_ctrl.c.

uint8_t ctrl_setup_wait_flag = 0U

Definition at line 18 of file usbh_ctrl.c.

void(* ctrl_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Initial value:
=
{
ctrl_idle_handle,
ctrl_setup_handle,
ctrl_data_handle,
ctrl_status_handle,
ctrl_error_handle,
ctrl_stalled_handle,
ctrl_complete_handle,
}

Definition at line 33 of file usbh_ctrl.c.

uint8_t ctrl_status_wait_flag = 0U

Definition at line 20 of file usbh_ctrl.c.


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_hcs.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Functions
usbh_hcs.c File Reference

this file implements functions for opening and closing host channels More...

#include "usbh_hcs.h"

Go to the source code of this file.

Functions

uint8_t | usbh_channel_open (usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel More...
uint8_t | usbh_channel_modify (usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel More...
uint8_t | usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe More...
uint8_t | usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel More...
uint8_t | usbh_allchannel_dealloc (usb_core_handle_struct *pudev)
free all usb host channel More...

Detailed Description

this file implements functions for opening and closing host channels

Definition in file usbh_hcs.c.

Function Documentation

uint8_t usbh_allchannel_dealloc ( usb_core_handle_struct * pudev )

free all usb host channel

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
host operation status

Definition at line 130 of file usbh_hcs.c.

131 {
132 uint8_t index;
133
134 for (index = 2U; index < HC_MAX; index ++) {
135 pudev->host.host_channel[index].info = 0U;
136 }
137
138 return USBH_OK;
139 }
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:18
USBH_OK
Definition: usbh_core.h:109
uint8_t usbh_channel_alloc | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

allocate a new channel for the pipe

Parameters
[in] | pudev | pointer to usb device
[in] | ep_addr | endpoint for which the channel to be allocated
[out] | none
Return values
host channel number

Definition at line 97 of file usbh_hcs.c.

98 {
99 uint16_t hc_num = usbh_freechannel_get(pudev);
100
101 if ((uint16_t)HC_ERROR != hc_num) {
102 pudev->host.host_channel[hc_num].info = HC_USED | ep_addr;
103 }
104
105 return (uint8_t)hc_num;
106 }
HC_USED
#define HC_USED
Definition: usbh_hcs.h:21
HC_ERROR
#define HC_ERROR
Definition: usbh_hcs.h:22
uint8_t usbh_channel_free | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | index
 | ) |  |

free the usb host channel

Parameters
[in] | pudev | pointer to usb device
[in] | index | channel number to be freed which is in (0..7)
[out] | none
Return values
host operation status

Definition at line 115 of file usbh_hcs.c.

116 {
117 if (index < HC_MAX) {
118 pudev->host.host_channel[index].info &= HC_USED_MASK;
119 }
120
121 return USBH_OK;
122 }
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:18
HC_USED_MASK
#define HC_USED_MASK
Definition: usbh_hcs.h:23
USBH_OK
Definition: usbh_core.h:109
uint8_t usbh_channel_modify | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num,
 |  | uint8_t | dev_addr,
 |  | uint8_t | dev_speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | ep_mps
 | ) |  |

modify a channel

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[in] | dev_addr | USB Device address allocated to attached device
[in] | dev_speed | USB device speed (Full speed/Low speed)
[in] | ep_type | endpoint type (bulk/int/ctl)
[in] | ep_mps | max packet size
[out] | none
Return values
operation status

Definition at line 64 of file usbh_hcs.c.

70 {
71 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
72
73 if (0U != dev_addr) {
74 puhc->dev_addr = dev_addr;
75 }
76
77 if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) {
78 puhc->endp_mps = ep_mps;
79 }
80
81 if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) {
82 puhc->dev_speed = dev_speed;
83 }
84
85 usb_hostchannel_init(pudev, channel_num);
86
87 return (uint8_t)HC_OK;
88 }
usb_hostchannel_struct
Definition: usb_core.h:155
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:163
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:157
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:158
HC_OK
#define HC_OK
Definition: usbh_hcs.h:20
uint8_t usbh_channel_open | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num,
 |  | uint8_t | dev_addr,
 |  | uint8_t | dev_speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | ep_mps
 | ) |  |

open a channel

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[in] | dev_addr | USB device address allocated to attached device
[in] | dev_speed | USB device speed (Full speed/Low speed)
[in] | ep_type | endpoint type (bulk/int/ctl)
[in] | ep_mps | max packet size
[out] | none
Return values
operation status

Definition at line 28 of file usbh_hcs.c.

34 {
35 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
36 uint16_t channel_info = puhc->info;
37
38 puhc->endp_id = (uint8_t)channel_info & 0x7FU;
39 puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7;
40 puhc->endp_type = ep_type;
41 puhc->endp_mps = ep_mps;
42 puhc->dev_addr = dev_addr;
43 puhc->dev_speed = dev_speed;
44
45 puhc->data_tg_in = 0U;
46 puhc->data_tg_out = 0U;
47
48 usb_hostchannel_init(pudev, channel_num);
49
50 return (uint8_t)HC_OK;
51 }
usb_hostchannel_struct::info
uint16_t info
Definition: usb_core.h:164
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:176
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:161
usb_hostchannel_struct
Definition: usb_core.h:155
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:175
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:163
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:157
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:158
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:162
HC_OK
#define HC_OK
Definition: usbh_hcs.h:20
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:160
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_int.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Functions
usbh_int.c File Reference

USB host mode interrupt handler file. More...

#include "usb_core.h"
#include "usb_defines.h"
#include "usbh_int.h"

Go to the source code of this file.

Functions

uint32_t usbh_isr (usb_core_handle_struct *pudev)
handle global host interrupt More...

Detailed Description

USB host mode interrupt handler file.

Definition in file usbh_int.c.

Function Documentation

uint32_t usbh_isr ( usb_core_handle_struct * pudev )

handle global host interrupt

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
operation status

Definition at line 34 of file usbh_int.c.

35 {
36 uint32_t retval = 0U;
37 __IO uint32_t int_flag = 0U;
38
39 /* check if host mode */
40 if (USB_CURRENT_MODE_GET() == HOST_MODE) {
41 USB_CORE_INTR_READ(int_flag);
42
43 if (!int_flag) {
44 return 0U;
45 }
46
47 /* start of frame interrupt handle */
48 if (int_flag & GINTF_SOF) {
49 retval |= usbh_intf_sof (pudev);
50 }
51
52 /* Rx FIFO non-empty interrupt handle */
53 if (int_flag & GINTF_RXFNEIF) {
54 retval |= usbh_intf_rxfifo_noempty (pudev);
55 }
56
57 /* Non-Periodic Tx FIFO empty interrupt hanlde */
58 if (int_flag & GINTF_NPTXFEIF) {
59 retval |= usbh_intf_nptxfifo_empty (pudev);
60 }
61
62 /* periodic Tx FIFO empty interrupt handle */
63 if (int_flag & GINTF_PTXFEIF) {
64 retval |= usbh_intf_ptxfifo_empty (pudev);
65 }
66
67 /* host channels interrupt handle */
68 if (int_flag & GINTF_HCIF) {
69 retval |= usbh_intf_hc (pudev);
70 }
71
72 /* host port interrupt handle */
73 if (int_flag & GINTF_HPIF) {
74 retval |= usbh_intf_port (pudev);
75 }
76
77 /* disconnect interrupt handle */
78 if (int_flag & GINTF_DISCIF) {
79 retval |= usbh_intf_disconnect (pudev);
80 }
81
82 /* isochronous IN transfer not complete interrupt handle */
83 if (int_flag & GINTF_ISOONCIF) {
84 retval |= usbh_intf_iso_incomplete_xfer (pudev);
85 }
86 }
87
88 return retval;
89 }
USB_CORE_INTR_READ
#define USB_CORE_INTR_READ(x)
Definition: usb_regs.h:499
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:49
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:159
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:496
GINTF_HCIF
#define GINTF_HCIF
Definition: usb_regs.h:143
GINTF_HPIF
#define GINTF_HPIF
Definition: usb_regs.h:144
GINTF_NPTXFEIF
#define GINTF_NPTXFEIF
Definition: usb_regs.h:158
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:146
GINTF_PTXFEIF
#define GINTF_PTXFEIF
Definition: usb_regs.h:142
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:160
GINTF_DISCIF
#define GINTF_DISCIF
Definition: usb_regs.h:140
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_std.c File Reference

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
Functions | Variables
usbh_std.c File Reference

USB 2.0 standard function definition. More...

#include "usbh_core.h"
#include "usbh_usr.h"
#include "usbh_std.h"
#include "usbh_ctrl.h"

Go to the source code of this file.

Functions

usbh_status_enum | enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state More...
void | usbh_enum_desc_get (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t *buf, uint8_t req_type, uint16_t value_idx, uint16_t len)
get descriptor in usb host enumeration stage More...
void | usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address)
set address in usb host enumeration stage More...
void | usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx)
set configuration in usb host enumeration stage More...
void | usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
parse the device descriptor More...
void | usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], uint8_t *buf, uint16_t len)
parse the configuration descriptor More...
void | usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor More...
void | usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor More...
void | usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len)
parse the string descriptor More...
usb_descriptor_header_struct * | usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header More...

Variables

uint8_t | local_buffer [64]
uint8_t | usbh_cfg_desc [512]
uint8_t | enum_polling_handle_flag = 0U
void(* | enum_state_handle [])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
state_table_struct enum_handle_table [ENUM_HANDLE_TABLE_SIZE]

Detailed Description

USB 2.0 standard function definition.

Definition in file usbh_std.c.

Function Documentation

usbh_status_enum enum_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of enumeration state

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | pustate | pointer to USB state driver
[out] | none
Return values
usb host status

Definition at line 72 of file usbh_std.c.

73 {
74 usbh_status_enum exe_state = USBH_BUSY;
75 usbh_state_handle_struct *p_state;
76 p_state = (usbh_state_handle_struct *)pustate;
77
78 if (0U == enum_polling_handle_flag) {
79 enum_polling_handle_flag = 1U;
80 scd_table_push(p_state);
81 scd_state_move(p_state, ENUM_IDLE);
82 }
83
84 /* start the enumeration state handle */
85 scd_begin(p_state,ENUM_FSM_ID);
86
87 if (0U == p_state->usbh_current_state_stack_top) {
88 enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
89 } else {
90 enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state);
91 }
92
93 /* determine the enumeration whether to complete */
94 if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) {
95 puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE;
96 enum_polling_handle_flag = 0U;
97 exe_state = USBH_OK;
98 }
99
100 return exe_state;
101 }
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:91
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:20
usbh_state_handle_struct
Definition: usbh_core.h:228
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:40
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
ENUM_IDLE
Definition: usbh_core.h:82
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
backup_state_struct::enum_backup_state
enum_state_enum enum_backup_state
Definition: usbh_core.h:182
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
enum_state_handle
void(* enum_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_std.c:34
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:191
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:623
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
USBH_OK
Definition: usbh_core.h:109
USBH_BUSY
Definition: usbh_core.h:110
void usbh_cfg_desc_parse | ( | usb_descriptor_configuration_struct * | cfg_desc,
 |  | usb_descriptor_interface_struct * | itf_desc,
 |  | usb_descriptor_endpoint_struct | ep_desc[][USBH_MAX_EP_NUM],
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

parse the configuration descriptor

Parameters
[in] | cfg_desc | configuration descriptor address
[in] | itf_desc | interface descriptor address
[in] | ep_desc | endpoint descriptor address
[in] | buf | buffer where the source descriptor is available
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 638 of file usbh_std.c.

643 {
644 usb_descriptor_interface_struct *pitf = NULL;
645 usb_descriptor_interface_struct temp_pitf;
646 usb_descriptor_endpoint_struct *pep = NULL;
647 usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf;
648
649 uint8_t itf_ix = 0U;
650 uint8_t ep_ix = 0U;
651 uint16_t ptr = 0U;
652 static uint8_t prev_itf = 0U;
653 static uint16_t prev_ep_size = 0U;
654
655 /* parse configuration descriptor */
656 cfg_desc->Header.bLength = *(uint8_t *)(buf + 0);
657 cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
658 cfg_desc->wTotalLength = SWAPBYTE(buf + 2);
659 cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4);
660 cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5);
661 cfg_desc->iConfiguration = *(uint8_t *)(buf + 6);
662 cfg_desc->bmAttributes = *(uint8_t *)(buf + 7);
663 cfg_desc->bMaxPower = *(uint8_t *)(buf + 8);
664
665 if (len > USB_CFGDESC_SIZE) {
666 ptr = USB_CFG_DESC_LEN;
667
668 if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) {
669 pitf = (usb_descriptor_interface_struct *)0;
670
671 for (; ptr < cfg_desc->wTotalLength; ) {
672 pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr);
673
674 if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) {
675 itf_ix = *((uint8_t *)pdesc + 2U);
676 pitf = &itf_desc[itf_ix];
677
678 if (*((uint8_t *)pdesc + 3U) < 3U) {
679 usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc);
680
681 /* parse endpoint descriptors relative to the current interface */
682 if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) {
683 for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) {
684 pdesc = usbh_next_desc_get((void* )pdesc, &ptr);
685
686 if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) {
687 pep = &ep_desc[itf_ix][ep_ix];
688
689 if (prev_itf != itf_ix) {
690 prev_itf = itf_ix;
691 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
692 } else {
693 if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) {
694 break;
695 } else {
696 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
697 }
698 }
699
700 usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc);
701 prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4);
702 ep_ix++;
703 }
704 }
705 }
706 }
707 }
708 }
709 }
710
711 prev_ep_size = 0U;
712 prev_itf = 0U;
713 }
714 }
usb_descriptor_configuration_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:136
USB_DESCTYPE_INTERFACE
#define USB_DESCTYPE_INTERFACE
Definition: usbd_std.h:57
usb_descriptor_configuration_struct::wTotalLength
uint16_t wTotalLength
Definition: usbd_std.h:132
usb_descriptor_configuration_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:130
usbh_endpoint_desc_parse
void usbh_endpoint_desc_parse(usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor
Definition: usbh_std.c:743
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usbd_std.h:148
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
usb_descriptor_interface_struct
Definition: usbd_std.h:142
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usb_descriptor_header_struct
Definition: usbd_std.h:102
USB_CFG_DESC_LEN
#define USB_CFG_DESC_LEN
Definition: usbd_std.h:25
usbh_interface_desc_parse
void usbh_interface_desc_parse(usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor
Definition: usbh_std.c:723
usb_descriptor_configuration_struct::bConfigurationValue
uint8_t bConfigurationValue
Definition: usbd_std.h:134
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
usbh_next_desc_get
usb_descriptor_header_struct * usbh_next_desc_get(uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header
Definition: usbh_std.c:796
usb_descriptor_configuration_struct::bNumInterfaces
uint8_t bNumInterfaces
Definition: usbd_std.h:133
USB_CFGDESC_SIZE
#define USB_CFGDESC_SIZE
Definition: usb_std.h:69
usb_descriptor_configuration_struct::iConfiguration
uint8_t iConfiguration
Definition: usbd_std.h:135
USB_DESCTYPE_ENDPOINT
#define USB_DESCTYPE_ENDPOINT
Definition: usbd_std.h:58
NULL
#define NULL
Definition: usbd_std.h:20
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_configuration_struct::bMaxPower
uint8_t bMaxPower
Definition: usbd_std.h:137
void usbh_device_desc_parse | ( | usb_descriptor_device_struct * | dev_desc,
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

parse the device descriptor

Parameters
[in] | dev_desc | device_descriptor destinaton address
[in] | buf | buffer where the source descriptor is available
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 606 of file usbh_std.c.

607 {
608 dev_desc->Header.bLength = *(uint8_t *)(buf + 0);
609 dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
610 dev_desc->bcdUSB = SWAPBYTE(buf + 2);
611 dev_desc->bDeviceClass = *(uint8_t *)(buf + 4);
612 dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5);
613 dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6);
614 dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7);
615
616 if (len > 8U){
617 /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */
618 dev_desc->idVendor = SWAPBYTE(buf + 8);
619 dev_desc->idProduct = SWAPBYTE(buf + 10);
620 dev_desc->bcdDevice = SWAPBYTE(buf + 12);
621 dev_desc->iManufacturer = *(uint8_t *)(buf + 14);
622 dev_desc->iProduct = *(uint8_t *)(buf + 15);
623 dev_desc->iSerialNumber = *(uint8_t *)(buf + 16);
624 dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17);
625 }
626 }
usb_descriptor_device_struct::idProduct
uint16_t idProduct
Definition: usbd_std.h:118
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usb_descriptor_device_struct::bcdUSB
uint16_t bcdUSB
Definition: usbd_std.h:112
usb_descriptor_device_struct::bDeviceProtocol
uint8_t bDeviceProtocol
Definition: usbd_std.h:115
usb_descriptor_device_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:110
usb_descriptor_device_struct::bcdDevice
uint16_t bcdDevice
Definition: usbd_std.h:119
usb_descriptor_device_struct::bDeviceSubClass
uint8_t bDeviceSubClass
Definition: usbd_std.h:114
usb_descriptor_device_struct::bNumberConfigurations
uint8_t bNumberConfigurations
Definition: usbd_std.h:123
usb_descriptor_device_struct::idVendor
uint16_t idVendor
Definition: usbd_std.h:117
usb_descriptor_device_struct::iProduct
uint8_t iProduct
Definition: usbd_std.h:121
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_device_struct::bDeviceClass
uint8_t bDeviceClass
Definition: usbd_std.h:113
usb_descriptor_device_struct::bMaxPacketSize0
uint8_t bMaxPacketSize0
Definition: usbd_std.h:116
usb_descriptor_device_struct::iManufacturer
uint8_t iManufacturer
Definition: usbd_std.h:120
usb_descriptor_device_struct::iSerialNumber
uint8_t iSerialNumber
Definition: usbd_std.h:122
void usbh_endpoint_desc_parse | ( | usb_descriptor_endpoint_struct * | ep_desc,
 |  | uint8_t * | buf
 | ) |  |

parse the endpoint descriptor

Parameters
[in] | ep_desc | endpoint descriptor destination address
[in] | buf | buffer where the parsed descriptor stored
[out] | none
Return values
none

Definition at line 743 of file usbh_std.c.

744 {
745 ep_desc->Header.bLength = *(uint8_t *)(buf + 0);
746 ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
747 ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2);
748 ep_desc->bmAttributes = *(uint8_t *)(buf + 3);
749 ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4);
750 ep_desc->bInterval = *(uint8_t *)(buf + 6);
751 }
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:162
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usbd_std.h:161
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usbd_std.h:163
usb_descriptor_endpoint_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:159
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_endpoint_struct::bInterval
uint8_t bInterval
Definition: usbd_std.h:164
void usbh_enum_addr_set | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint8_t | device_address
 | ) |  |

set address in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | device_address | the device address
[out] | none
Return values
none

Definition at line 560 of file usbh_std.c.

563 {
564 usb_setup_union *p_setup = &(puhost->control.setup);
565
566 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
567 p_setup->b.bRequest = USBREQ_SET_ADDRESS;
568 p_setup->b.wValue = (uint16_t)device_address;
569 p_setup->b.wIndex = 0U;
570 p_setup->b.wLength = 0U;
571 puhost->control.buff = 0U;
572 puhost->control.length = 0U;
573 }
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:117
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:114
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:134
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usbd_std.h:39
usb_setup_union
Definition: usb_std.h:108
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:118
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:27
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:116
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:132
USBREQ_SET_ADDRESS
#define USBREQ_SET_ADDRESS
Definition: usbd_std.h:47
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:115
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:135
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_enum_cfg_set | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint16_t | cfg_idx
 | ) |  |

set configuration in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | cfg_idx | the index of the configuration
[out] | none
Return values
none

Definition at line 583 of file usbh_std.c.

586 {
587 usb_setup_union *p_setup = &(puhost->control.setup);
588
589 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
590 p_setup->b.bRequest = USBREQ_SET_CONFIGURATION;
591 p_setup->b.wValue = cfg_idx;
592 p_setup->b.wIndex = 0U;
593 p_setup->b.wLength = 0U;
594 puhost->control.buff = 0;
595 puhost->control.length = 0U;
596 }
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:117
USBREQ_SET_CONFIGURATION
#define USBREQ_SET_CONFIGURATION
Definition: usbd_std.h:50
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:114
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:134
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usbd_std.h:39
usb_setup_union
Definition: usb_std.h:108
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:118
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:27
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:116
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:132
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:115
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:135
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_enum_desc_get | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint8_t * | buf,
 |  | uint8_t | req_type,
 |  | uint16_t | value_idx,
 |  | uint16_t | len
 | ) |  |

get descriptor in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | buf | buffer to store the descriptor
[in] | ReqType | descriptor type
[in] | ValueIdx | wValue for the GetDescriptr request
[in] | Len | length of the descriptor
[out] | none
Return values
none

Definition at line 526 of file usbh_std.c.

532 {
533 usb_setup_union *pSetup = &(puhost->control.setup);
534
535 pSetup->b.bmRequestType = USB_DIR_IN | req_type;
536 pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR;
537 pSetup->b.wValue = value_idx;
538
539 if (USB_STRDESC == (value_idx & 0xff00U)){
540 pSetup->b.wIndex = 0x0409U;
541 } else {
542 pSetup->b.wIndex = 0U;
543 }
544
545 pSetup->b.wLength = len;
546
547 puhost->control.buff = buf;
548 puhost->control.length = len;
549
550 }
USB_STRDESC
#define USB_STRDESC
Definition: usb_std.h:77
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:117
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:114
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:134
usb_setup_union
Definition: usb_std.h:108
USBREQ_GET_DESCRIPTOR
#define USBREQ_GET_DESCRIPTOR
Definition: usbd_std.h:48
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:118
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:116
USB_DIR_IN
#define USB_DIR_IN
Definition: usb_std.h:28
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:132
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:115
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:135
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_interface_desc_parse | ( | usb_descriptor_interface_struct * | itf_desc,
 |  | uint8_t * | buf
 | ) |  |

parse the interface descriptor

Parameters
[in] | itf_desc | interface descriptor destination
[in] | buf | buffer where the descriptor data is available
[out] | none
Return values
none

Definition at line 723 of file usbh_std.c.

724 {
725 itf_desc->Header.bLength = *(uint8_t *)(buf + 0);
726 itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
727 itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2);
728 itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3);
729 itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4);
730 itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5);
731 itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6);
732 itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7);
733 itf_desc->iInterface = *(uint8_t *)(buf + 8);
734 }
usb_descriptor_interface_struct::bInterfaceProtocol
uint8_t bInterfaceProtocol
Definition: usbd_std.h:151
usb_descriptor_interface_struct::iInterface
uint8_t iInterface
Definition: usbd_std.h:152
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usbd_std.h:148
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
usb_descriptor_interface_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:144
usb_descriptor_interface_struct::bInterfaceClass
uint8_t bInterfaceClass
Definition: usbd_std.h:149
usb_descriptor_interface_struct::bInterfaceSubClass
uint8_t bInterfaceSubClass
Definition: usbd_std.h:150
usb_descriptor_interface_struct::bAlternateSetting
uint8_t bAlternateSetting
Definition: usbd_std.h:147
usb_descriptor_interface_struct::bInterfaceNumber
uint8_t bInterfaceNumber
Definition: usbd_std.h:146
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_header_struct* usbh_next_desc_get | ( | uint8_t * | pbuf,
 |  | uint16_t * | ptr
 | ) |  |

get the next descriptor header

Parameters
[in] | pbuf | pointer to buffer where the cfg descriptor is available
[in] | ptr | data popinter inside the configuration descriptor
[out] | none
Return values
next descriptor header

Definition at line 796 of file usbh_std.c.

797 {
798 uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength;
799
800 usb_descriptor_header_struct *pnext;
801
802 *ptr += len;
803
804 pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len);
805
806 return(pnext);
807 }
usb_descriptor_header_struct
Definition: usbd_std.h:102
void usbh_string_desc_parse | ( | uint8_t * | psrc,
 |  | uint8_t * | pdest,
 |  | uint16_t | len
 | ) |  |

parse the string descriptor

Parameters
[in] | psrc | source pointer containing the descriptor data
[in] | pdest | destination address pointer
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 761 of file usbh_std.c.

762 {
763 uint16_t strlength;
764 uint16_t idx;
765
766 /* the unicode string descriptor is not null-terminated. the string length is
767 computed by substracting two from the value of the first byte of the descriptor.
768 */
769
770 /* check which is lower size, the size of string or the length of bytes read from the device */
771
772 if (USB_DESCTYPE_STRING == psrc[1]){
773 /* make sure the descriptor is string type */
774
775 /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */
776 strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len);
777 psrc += 2; /* adjust the offset ignoring the string len and descriptor type */
778
779 for (idx = 0U; idx < strlength; idx += 2U) {
780 /* copy only the string and ignore the unicode id, hence add the src */
781 *pdest = psrc[idx];
782 pdest++;
783 }
784
785 *pdest = 0U; /* mark end of string */
786 }
787 }
USB_DESCTYPE_STRING
#define USB_DESCTYPE_STRING
Definition: usbd_std.h:56

Variable Documentation

state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Initial value:
=
{
{ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move },
{ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move },
{ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move },
{ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move },
{ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move },
{ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move },
{ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move },
{ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move },
{ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move },
{ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
}
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:91
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:706
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
Definition: usbh_std.h:39
ENUN_EVENT_DEV_CONFIGURED
Definition: usbh_std.h:41
ENUM_IDLE
Definition: usbh_core.h:82
ENUN_EVENT_SET_CONFIGURATION
Definition: usbh_std.h:40
ENUM_GET_PRODUCT_STRING_DESC
Definition: usbh_core.h:88
ENUM_GET_CFG_DESC
Definition: usbh_core.h:85
ENUN_EVENT_GET_PRODUCT_STRING_DESC
Definition: usbh_std.h:38
ENUN_EVENT_GET_CFG_DESC
Definition: usbh_std.h:35
ENUN_EVENT_GET_FULL_CFG_DESC
Definition: usbh_std.h:36
ENUN_EVENT_GET_MFC_STRING_DESC
Definition: usbh_std.h:37
UP_STATE
#define UP_STATE
Definition: usbh_core.h:46
GO_TO_UP_STATE_EVENT
#define GO_TO_UP_STATE_EVENT
Definition: usbh_core.h:47
ENUN_EVENT_GET_FULL_DEV_DESC
Definition: usbh_std.h:34
ENUM_SET_ADDR
Definition: usbh_core.h:83
ENUM_SET_CONFIGURATION
Definition: usbh_core.h:90
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:693
ENUM_GET_FULL_CFG_DESC
Definition: usbh_core.h:86
ENUM_GET_FULL_DEV_DESC
Definition: usbh_core.h:84
ENUM_EVENT_SET_ADDR
Definition: usbh_std.h:33
ENUM_GET_MFC_STRING_DESC
Definition: usbh_core.h:87
ENUM_GET_SERIALNUM_STRING_DESC
Definition: usbh_core.h:89

Definition at line 49 of file usbh_std.c.

uint8_t enum_polling_handle_flag = 0U

Definition at line 20 of file usbh_std.c.

void(* enum_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Initial value:
=
{
enum_idle_handle,
enum_set_addr_handle,
enum_get_full_dev_desc_handle,
enum_get_cfg_desc_handle,
enum_get_full_cfg_desc_handle,
enum_get_mfc_string_desc_handle,
enum_get_product_string_desc_handle,
enum_get_serialnum_string_desc_handle,
enum_set_configuration_handle,
enum_dev_configured_handle,
}

Definition at line 34 of file usbh_std.c.

uint8_t local_buffer[64]

Definition at line 18 of file usbh_std.c.

uint8_t usbh_cfg_desc[512]

Definition at line 19 of file usbh_std.c.


GD32F10x_Firmware_Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • _ENET_DELAY_ : gd32f10x_enet.h
  • _EP_ADDR_SET : usbd_regs.h
  • _WIDE_STRING : usbd_std.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ACT_FUN : usbh_core.h
  • ADC0 : gd32f10x_adc.h
  • ADC0_1_2_EXTTRIG_INSERTED_NONE : gd32f10x_adc.h
  • ADC0_1_2_EXTTRIG_REGULAR_NONE : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_EXTI_15 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T0_CH3 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T0_TRGO : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T1_CH0 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T1_TRGO : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T2_CH3 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T3_TRGO : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T7_CH3 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_EXTI_11 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T0_CH0 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T0_CH1 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T0_CH2 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T1_CH1 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T2_TRGO : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T3_CH3 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T7_TRGO : gd32f10x_adc.h
  • ADC1 : gd32f10x_adc.h
  • ADC2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T0_CH3 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T0_TRGO : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T3_CH2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T4_CH3 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T4_TRGO : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T7_CH1 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T7_CH3 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T0_CH2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T1_CH2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T2_CH0 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T4_CH0 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T4_CH2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T7_CH0 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T7_TRGO : gd32f10x_adc.h
  • adc_calibration_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_CHANNEL_0 : gd32f10x_adc.h
  • ADC_CHANNEL_1 : gd32f10x_adc.h
  • ADC_CHANNEL_10 : gd32f10x_adc.h
  • ADC_CHANNEL_11 : gd32f10x_adc.h
  • ADC_CHANNEL_12 : gd32f10x_adc.h
  • ADC_CHANNEL_13 : gd32f10x_adc.h
  • ADC_CHANNEL_14 : gd32f10x_adc.h
  • ADC_CHANNEL_15 : gd32f10x_adc.h
  • ADC_CHANNEL_16 : gd32f10x_adc.h
  • ADC_CHANNEL_17 : gd32f10x_adc.h
  • ADC_CHANNEL_2 : gd32f10x_adc.h
  • ADC_CHANNEL_3 : gd32f10x_adc.h
  • ADC_CHANNEL_4 : gd32f10x_adc.h
  • ADC_CHANNEL_5 : gd32f10x_adc.h
  • ADC_CHANNEL_6 : gd32f10x_adc.h
  • ADC_CHANNEL_7 : gd32f10x_adc.h
  • ADC_CHANNEL_8 : gd32f10x_adc.h
  • ADC_CHANNEL_9 : gd32f10x_adc.h
  • ADC_CHANNEL_DISCON_DISABLE : gd32f10x_adc.h
  • adc_channel_length_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_CONTINUOUS_MODE : gd32f10x_adc.h
  • ADC_CTL0 : gd32f10x_adc.h
  • ADC_CTL0_DISIC : gd32f10x_adc.h
  • ADC_CTL0_DISNUM : gd32f10x_adc.h
  • ADC_CTL0_DISRC : gd32f10x_adc.h
  • ADC_CTL0_DRES : gd32f10x_adc.h
  • ADC_CTL0_EOCIE : gd32f10x_adc.h
  • ADC_CTL0_EOICIE : gd32f10x_adc.h
  • ADC_CTL0_ICA : gd32f10x_adc.h
  • ADC_CTL0_IWDEN : gd32f10x_adc.h
  • ADC_CTL0_RWDEN : gd32f10x_adc.h
  • ADC_CTL0_SM : gd32f10x_adc.h
  • ADC_CTL0_SYNCM : gd32f10x_adc.h
  • ADC_CTL0_WDCHSEL : gd32f10x_adc.h
  • ADC_CTL0_WDEIE : gd32f10x_adc.h
  • ADC_CTL0_WDSC : gd32f10x_adc.h
  • ADC_CTL1 : gd32f10x_adc.h
  • ADC_CTL1_ADCON : gd32f10x_adc.h
  • ADC_CTL1_CLB : gd32f10x_adc.h
  • ADC_CTL1_CTN : gd32f10x_adc.h
  • ADC_CTL1_DAL : gd32f10x_adc.h
  • ADC_CTL1_DMA : gd32f10x_adc.h
  • ADC_CTL1_ETEIC : gd32f10x_adc.h
  • ADC_CTL1_ETERC : gd32f10x_adc.h
  • ADC_CTL1_ETSIC : gd32f10x_adc.h
  • ADC_CTL1_ETSRC : gd32f10x_adc.h
  • ADC_CTL1_RSTCLB : gd32f10x_adc.h
  • ADC_CTL1_SWICST : gd32f10x_adc.h
  • ADC_CTL1_SWRCST : gd32f10x_adc.h
  • ADC_CTL1_TSVREN : gd32f10x_adc.h
  • adc_data_alignment_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_DATAALIGN_LEFT : gd32f10x_adc.h
  • ADC_DATAALIGN_RIGHT : gd32f10x_adc.h
  • ADC_DAUL_INSERTED_PARALLEL : gd32f10x_adc.h
  • ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST : gd32f10x_adc.h
  • ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW : gd32f10x_adc.h
  • ADC_DAUL_INSERTED_TRRIGGER_ROTATION : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_FOLLOWUP_FAST : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_FOLLOWUP_SLOW : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_PARALLEL : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION : gd32f10x_adc.h
  • adc_deinit() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_disable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_discontinuous_mode_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_dma_mode_disable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_dma_mode_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_external_trigger_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_external_trigger_source_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_flag_clear() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_FLAG_EOC : gd32f10x_adc.h
  • ADC_FLAG_EOIC : gd32f10x_adc.h
  • adc_flag_get() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_FLAG_STIC : gd32f10x_adc.h
  • ADC_FLAG_STRC : gd32f10x_adc.h
  • ADC_FLAG_WDE : gd32f10x_adc.h
  • ADC_IDATA0 : gd32f10x_adc.h
  • ADC_IDATA1 : gd32f10x_adc.h
  • ADC_IDATA2 : gd32f10x_adc.h
  • ADC_IDATA3 : gd32f10x_adc.h
  • ADC_IDATAX_IDATAN : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_0 : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_1 : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_2 : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_3 : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_AUTO : gd32f10x_adc.h
  • adc_inserted_channel_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_inserted_channel_offset_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_inserted_data_read() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_inserted_software_startconv_flag_get() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_INT_EOC : gd32f10x_adc.h
  • ADC_INT_EOIC : gd32f10x_adc.h
  • ADC_INT_WDE : gd32f10x_adc.h
  • adc_interrupt_disable() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_interrupt_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_interrupt_flag_clear() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_interrupt_flag_get() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_IOFF0 : gd32f10x_adc.h
  • ADC_IOFF1 : gd32f10x_adc.h
  • ADC_IOFF2 : gd32f10x_adc.h
  • ADC_IOFF3 : gd32f10x_adc.h
  • ADC_IOFFX_IOFF : gd32f10x_adc.h
  • ADC_ISQ : gd32f10x_adc.h
  • ADC_ISQ_IL : gd32f10x_adc.h
  • ADC_ISQ_ISQN : gd32f10x_adc.h
  • adc_mode_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_MODE_FREE : gd32f10x_adc.h
  • ADC_RDATA : gd32f10x_adc.h
  • ADC_RDATA_ADC1RDTR : gd32f10x_adc.h
  • ADC_RDATA_RDATA : gd32f10x_adc.h
  • ADC_REGULAR_CHANNEL : gd32f10x_adc.h
  • adc_regular_channel_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_regular_data_read() : gd32f10x_adc.c , gd32f10x_adc.h
  • ADC_REGULAR_INSERTED_CHANNEL : gd32f10x_adc.h
  • adc_regular_software_startconv_flag_get() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_RSQ0 : gd32f10x_adc.h
  • ADC_RSQ0_RL : gd32f10x_adc.h
  • ADC_RSQ1 : gd32f10x_adc.h
  • ADC_RSQ2 : gd32f10x_adc.h
  • ADC_RSQX_RSQN : gd32f10x_adc.h
  • ADC_SAMPLETIME_13POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_1POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_239POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_28POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_41POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_55POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_71POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_7POINT5 : gd32f10x_adc.h
  • ADC_SAMPT0 : gd32f10x_adc.h
  • ADC_SAMPT1 : gd32f10x_adc.h
  • ADC_SAMPTX_SPTN : gd32f10x_adc.h
  • ADC_SCAN_MODE : gd32f10x_adc.h
  • adc_software_trigger_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_special_function_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_STAT : gd32f10x_adc.h
  • ADC_STAT_EOC : gd32f10x_adc.h
  • ADC_STAT_EOIC : gd32f10x_adc.h
  • ADC_STAT_STIC : gd32f10x_adc.h
  • ADC_STAT_STRC : gd32f10x_adc.h
  • ADC_STAT_WDE : gd32f10x_adc.h
  • adc_sync_mode_convert_value_read() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_tempsensor_vrefint_disable() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_tempsensor_vrefint_enable() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_watchdog_disable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_watchdog_group_channel_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_watchdog_single_channel_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_watchdog_threshold_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • ADC_WDHT : gd32f10x_adc.h
  • ADC_WDHT_WDHT : gd32f10x_adc.h
  • ADC_WDLT : gd32f10x_adc.h
  • ADC_WDLT_WDLT : gd32f10x_adc.h
  • AFIO : gd32f10x_gpio.h
  • AFIO_EC : gd32f10x_gpio.h
  • AFIO_EC_EOE : gd32f10x_gpio.h
  • AFIO_EC_PIN : gd32f10x_gpio.h
  • AFIO_EC_PORT : gd32f10x_gpio.h
  • AFIO_EXTI0_SS : gd32f10x_gpio.h
  • AFIO_EXTI10_SS : gd32f10x_gpio.h
  • AFIO_EXTI11_SS : gd32f10x_gpio.h
  • AFIO_EXTI12_SS : gd32f10x_gpio.h
  • AFIO_EXTI13_SS : gd32f10x_gpio.h
  • AFIO_EXTI14_SS : gd32f10x_gpio.h
  • AFIO_EXTI15_SS : gd32f10x_gpio.h
  • AFIO_EXTI1_SS : gd32f10x_gpio.h
  • AFIO_EXTI2_SS : gd32f10x_gpio.h
  • AFIO_EXTI3_SS : gd32f10x_gpio.h
  • AFIO_EXTI4_SS : gd32f10x_gpio.h
  • AFIO_EXTI5_SS : gd32f10x_gpio.h
  • AFIO_EXTI6_SS : gd32f10x_gpio.h
  • AFIO_EXTI7_SS : gd32f10x_gpio.h
  • AFIO_EXTI8_SS : gd32f10x_gpio.h
  • AFIO_EXTI9_SS : gd32f10x_gpio.h
  • AFIO_EXTI_SOURCE_FIELDS : gd32f10x_gpio.c
  • AFIO_EXTISS0 : gd32f10x_gpio.h
  • AFIO_EXTISS1 : gd32f10x_gpio.h
  • AFIO_EXTISS2 : gd32f10x_gpio.h
  • AFIO_EXTISS3 : gd32f10x_gpio.h
  • AFIO_PCF0 : gd32f10x_gpio.h
  • AFIO_PCF0_CAN0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_CAN1_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_ENET_PHY_SEL : gd32f10x_gpio.h
  • AFIO_PCF0_ENET_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_I2C0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_PD01_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_PTP_PPS_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_SPI0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_SPI2_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_SWJ_CFG : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER1_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER1ITR0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER2_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER3_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER4CH3_IREMAP : gd32f10x_gpio.h
  • AFIO_PCF0_USART0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_USART1_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_USART2_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1 : gd32f10x_gpio.h
  • AFIO_PCF1_FIELDS : gd32f10x_gpio.c
  • AFIO_PCF1_FSMC_NADV : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER10_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER12_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER13_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER8_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER9_REMAP : gd32f10x_gpio.h
  • AHBEN_REG_OFFSET : gd32f10x_rcu.h
  • AHBRST_REG_OFFSET : gd32f10x_rcu.h
  • ALL_DMA_REG : gd32f10x_enet.h
  • ALL_MAC_REG : gd32f10x_enet.h
  • ALL_MSC_REG : gd32f10x_enet.h
  • ALL_PTP_REG : gd32f10x_enet.h
  • APB1EN_REG_OFFSET : gd32f10x_rcu.h
  • APB1RST_REG_OFFSET : gd32f10x_rcu.h
  • APB2EN_REG_OFFSET : gd32f10x_rcu.h
  • APB2RST_REG_OFFSET : gd32f10x_rcu.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BANK0_SNCTL0_REGION_RESET : gd32f10x_exmc.c
  • BANK0_SNCTL1_2_3_REGION_RESET : gd32f10x_exmc.c
  • BANK0_SNTCFG_RESET : gd32f10x_exmc.c
  • BANK0_SNWTCFG_RESET : gd32f10x_exmc.c
  • BANK1_2_NPATCFG_RESET : gd32f10x_exmc.c
  • BANK1_2_NPCTCFG_RESET : gd32f10x_exmc.c
  • BANK1_2_NPCTL_RESET : gd32f10x_exmc.c
  • BANK1_2_NPINTEN_RESET : gd32f10x_exmc.c
  • BANK3_NPATCFG_RESET : gd32f10x_exmc.c
  • BANK3_NPCTCFG_RESET : gd32f10x_exmc.c
  • BANK3_NPCTL_RESET : gd32f10x_exmc.c
  • BANK3_NPINTEN_RESET : gd32f10x_exmc.c
  • BANK3_PIOTCFG3_RESET : gd32f10x_exmc.c
  • BDCTL_REG_OFFSET : gd32f10x_rcu.h
  • BDCTL_RTCSRC : gd32f10x_rcu.h
  • bit_status : gd32f10x_gpio.h
  • BKP : gd32f10x_bkp.h
  • BKP_DATA : gd32f10x_bkp.h
  • BKP_DATA0 : gd32f10x_bkp.h
  • BKP_DATA0_9 : gd32f10x_bkp.h
  • BKP_DATA1 : gd32f10x_bkp.h
  • BKP_DATA10 : gd32f10x_bkp.h
  • BKP_DATA10_41 : gd32f10x_bkp.h
  • BKP_DATA11 : gd32f10x_bkp.h
  • BKP_DATA12 : gd32f10x_bkp.h
  • BKP_DATA13 : gd32f10x_bkp.h
  • BKP_DATA14 : gd32f10x_bkp.h
  • BKP_DATA15 : gd32f10x_bkp.h
  • BKP_DATA16 : gd32f10x_bkp.h
  • BKP_DATA17 : gd32f10x_bkp.h
  • BKP_DATA18 : gd32f10x_bkp.h
  • BKP_DATA19 : gd32f10x_bkp.h
  • BKP_DATA2 : gd32f10x_bkp.h
  • BKP_DATA20 : gd32f10x_bkp.h
  • BKP_DATA21 : gd32f10x_bkp.h
  • BKP_DATA22 : gd32f10x_bkp.h
  • BKP_DATA23 : gd32f10x_bkp.h
  • BKP_DATA24 : gd32f10x_bkp.h
  • BKP_DATA25 : gd32f10x_bkp.h
  • BKP_DATA26 : gd32f10x_bkp.h
  • BKP_DATA27 : gd32f10x_bkp.h
  • BKP_DATA28 : gd32f10x_bkp.h
  • BKP_DATA29 : gd32f10x_bkp.h
  • BKP_DATA3 : gd32f10x_bkp.h
  • BKP_DATA30 : gd32f10x_bkp.h
  • BKP_DATA31 : gd32f10x_bkp.h
  • BKP_DATA32 : gd32f10x_bkp.h
  • BKP_DATA33 : gd32f10x_bkp.h
  • BKP_DATA34 : gd32f10x_bkp.h
  • BKP_DATA35 : gd32f10x_bkp.h
  • BKP_DATA36 : gd32f10x_bkp.h
  • BKP_DATA37 : gd32f10x_bkp.h
  • BKP_DATA38 : gd32f10x_bkp.h
  • BKP_DATA39 : gd32f10x_bkp.h
  • BKP_DATA4 : gd32f10x_bkp.h
  • BKP_DATA40 : gd32f10x_bkp.h
  • BKP_DATA41 : gd32f10x_bkp.h
  • BKP_DATA5 : gd32f10x_bkp.h
  • BKP_DATA6 : gd32f10x_bkp.h
  • BKP_DATA7 : gd32f10x_bkp.h
  • BKP_DATA8 : gd32f10x_bkp.h
  • BKP_DATA9 : gd32f10x_bkp.h
  • BKP_DATA_0 : gd32f10x_bkp.h
  • BKP_DATA_1 : gd32f10x_bkp.h
  • BKP_DATA_10 : gd32f10x_bkp.h
  • BKP_DATA_11 : gd32f10x_bkp.h
  • BKP_DATA_12 : gd32f10x_bkp.h
  • BKP_DATA_13 : gd32f10x_bkp.h
  • BKP_DATA_14 : gd32f10x_bkp.h
  • BKP_DATA_15 : gd32f10x_bkp.h
  • BKP_DATA_16 : gd32f10x_bkp.h
  • BKP_DATA_17 : gd32f10x_bkp.h
  • BKP_DATA_18 : gd32f10x_bkp.h
  • BKP_DATA_19 : gd32f10x_bkp.h
  • BKP_DATA_2 : gd32f10x_bkp.h
  • BKP_DATA_20 : gd32f10x_bkp.h
  • BKP_DATA_21 : gd32f10x_bkp.h
  • BKP_DATA_22 : gd32f10x_bkp.h
  • BKP_DATA_23 : gd32f10x_bkp.h
  • BKP_DATA_24 : gd32f10x_bkp.h
  • BKP_DATA_25 : gd32f10x_bkp.h
  • BKP_DATA_26 : gd32f10x_bkp.h
  • BKP_DATA_27 : gd32f10x_bkp.h
  • BKP_DATA_28 : gd32f10x_bkp.h
  • BKP_DATA_29 : gd32f10x_bkp.h
  • BKP_DATA_3 : gd32f10x_bkp.h
  • BKP_DATA_30 : gd32f10x_bkp.h
  • BKP_DATA_31 : gd32f10x_bkp.h
  • BKP_DATA_32 : gd32f10x_bkp.h
  • BKP_DATA_33 : gd32f10x_bkp.h
  • BKP_DATA_34 : gd32f10x_bkp.h
  • BKP_DATA_35 : gd32f10x_bkp.h
  • BKP_DATA_36 : gd32f10x_bkp.h
  • BKP_DATA_37 : gd32f10x_bkp.h
  • BKP_DATA_38 : gd32f10x_bkp.h
  • BKP_DATA_39 : gd32f10x_bkp.h
  • BKP_DATA_4 : gd32f10x_bkp.h
  • BKP_DATA_40 : gd32f10x_bkp.h
  • BKP_DATA_41 : gd32f10x_bkp.h
  • BKP_DATA_5 : gd32f10x_bkp.h
  • BKP_DATA_6 : gd32f10x_bkp.h
  • BKP_DATA_7 : gd32f10x_bkp.h
  • BKP_DATA_8 : gd32f10x_bkp.h
  • BKP_DATA_9 : gd32f10x_bkp.h
  • BKP_DATA_GET : gd32f10x_bkp.h
  • bkp_data_register_enum : gd32f10x_bkp.h
  • bkp_deinit() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_flag_clear() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_flag_get() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • BKP_FLAG_TAMPER : gd32f10x_bkp.h
  • BKP_INT_FLAG_TAMPER : gd32f10x_bkp.h
  • bkp_interrupt_flag_clear() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_interrupt_flag_get() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • BKP_OCTL : gd32f10x_bkp.h
  • BKP_OCTL_ASOEN : gd32f10x_bkp.h
  • BKP_OCTL_COEN : gd32f10x_bkp.h
  • BKP_OCTL_RCCV : gd32f10x_bkp.h
  • BKP_OCTL_ROSEL : gd32f10x_bkp.h
  • bkp_read_data() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • bkp_rtc_calibration_output_disable() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • bkp_rtc_calibration_output_enable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_rtc_calibration_value_set() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_rtc_output_select() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_rtc_signal_output_disable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_rtc_signal_output_enable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_tamper_active_level_set() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • bkp_tamper_detection_disable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_tamper_detection_enable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_tamper_interrupt_disable() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • bkp_tamper_interrupt_enable() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • BKP_TPCS : gd32f10x_bkp.h
  • BKP_TPCS_TEF : gd32f10x_bkp.h
  • BKP_TPCS_TER : gd32f10x_bkp.h
  • BKP_TPCS_TIF : gd32f10x_bkp.h
  • BKP_TPCS_TIR : gd32f10x_bkp.h
  • BKP_TPCS_TPIE : gd32f10x_bkp.h
  • BKP_TPCTL : gd32f10x_bkp.h
  • BKP_TPCTL_TPAL : gd32f10x_bkp.h
  • BKP_TPCTL_TPEN : gd32f10x_bkp.h
  • bkp_write_data() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • BLKNUM_OFFSET : usbd_regs.h
  • BLKSIZE2_MASK : usbd_regs.h
  • BLKSIZE2_OFFSETMASK : usbd_regs.h
  • BLKSIZE32_MASK : usbd_regs.h
  • BLKSIZE32_OFFSETMASK : usbd_regs.h
  • BLKSIZE_OFFSET : usbd_regs.h
  • BT_BAUDPSC : gd32f10x_can.h
  • BT_BS1 : gd32f10x_can.h
  • BT_BS2 : gd32f10x_can.h
  • BT_MODE : gd32f10x_can.h
  • BT_SJW : gd32f10x_can.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CAN0 : gd32f10x_can.h
  • CAN1 : gd32f10x_can.h
  • can1_filter_start_bank() : gd32f10x_can.c , gd32f10x_can.h
  • CAN_BIT_POS : gd32f10x_can.h
  • CAN_BIT_POS0 : gd32f10x_can.h
  • CAN_BIT_POS1 : gd32f10x_can.h
  • CAN_BT : gd32f10x_can.h
  • CAN_BT_BAUDPSC : gd32f10x_can.h
  • CAN_BT_BS1 : gd32f10x_can.h
  • CAN_BT_BS1_10TQ : gd32f10x_can.h
  • CAN_BT_BS1_11TQ : gd32f10x_can.h
  • CAN_BT_BS1_12TQ : gd32f10x_can.h
  • CAN_BT_BS1_13TQ : gd32f10x_can.h
  • CAN_BT_BS1_14TQ : gd32f10x_can.h
  • CAN_BT_BS1_15TQ : gd32f10x_can.h
  • CAN_BT_BS1_16TQ : gd32f10x_can.h
  • CAN_BT_BS1_1TQ : gd32f10x_can.h
  • CAN_BT_BS1_2TQ : gd32f10x_can.h
  • CAN_BT_BS1_3TQ : gd32f10x_can.h
  • CAN_BT_BS1_4TQ : gd32f10x_can.h
  • CAN_BT_BS1_5TQ : gd32f10x_can.h
  • CAN_BT_BS1_6TQ : gd32f10x_can.h
  • CAN_BT_BS1_7TQ : gd32f10x_can.h
  • CAN_BT_BS1_8TQ : gd32f10x_can.h
  • CAN_BT_BS1_9TQ : gd32f10x_can.h
  • CAN_BT_BS2 : gd32f10x_can.h
  • CAN_BT_BS2_1TQ : gd32f10x_can.h
  • CAN_BT_BS2_2TQ : gd32f10x_can.h
  • CAN_BT_BS2_3TQ : gd32f10x_can.h
  • CAN_BT_BS2_4TQ : gd32f10x_can.h
  • CAN_BT_BS2_5TQ : gd32f10x_can.h
  • CAN_BT_BS2_6TQ : gd32f10x_can.h
  • CAN_BT_BS2_7TQ : gd32f10x_can.h
  • CAN_BT_BS2_8TQ : gd32f10x_can.h
  • CAN_BT_LCMOD : gd32f10x_can.h
  • CAN_BT_SCMOD : gd32f10x_can.h
  • CAN_BT_SJW : gd32f10x_can.h
  • CAN_BT_SJW_1TQ : gd32f10x_can.h
  • CAN_BT_SJW_2TQ : gd32f10x_can.h
  • CAN_BT_SJW_3TQ : gd32f10x_can.h
  • CAN_BT_SJW_4TQ : gd32f10x_can.h
  • CAN_CTL : gd32f10x_can.h
  • CAN_CTL_ABOR : gd32f10x_can.h
  • CAN_CTL_ARD : gd32f10x_can.h
  • CAN_CTL_AWU : gd32f10x_can.h
  • CAN_CTL_DFZ : gd32f10x_can.h
  • CAN_CTL_IWMOD : gd32f10x_can.h
  • CAN_CTL_RFOD : gd32f10x_can.h
  • CAN_CTL_SLPWMOD : gd32f10x_can.h
  • CAN_CTL_SWRST : gd32f10x_can.h
  • CAN_CTL_TFO : gd32f10x_can.h
  • CAN_CTL_TTC : gd32f10x_can.h
  • can_debug_freeze_disable() : gd32f10x_can.h , gd32f10x_can.c
  • can_debug_freeze_enable() : gd32f10x_can.h , gd32f10x_can.c
  • can_deinit() : gd32f10x_can.h , gd32f10x_can.c
  • CAN_EFID_MASK : gd32f10x_can.h
  • CAN_ERR : gd32f10x_can.h
  • CAN_ERR_BOERR : gd32f10x_can.h
  • CAN_ERR_ERRN : gd32f10x_can.h
  • CAN_ERR_PERR : gd32f10x_can.h
  • CAN_ERR_RECNT : gd32f10x_can.h
  • CAN_ERR_TECNT : gd32f10x_can.h
  • CAN_ERR_WERR : gd32f10x_can.h
  • CAN_ERRN_0 : gd32f10x_can.h
  • CAN_ERRN_1 : gd32f10x_can.h
  • CAN_ERRN_2 : gd32f10x_can.h
  • CAN_ERRN_3 : gd32f10x_can.h
  • CAN_ERRN_4 : gd32f10x_can.h
  • CAN_ERRN_5 : gd32f10x_can.h
  • CAN_ERRN_6 : gd32f10x_can.h
  • CAN_ERRN_7 : gd32f10x_can.h
  • CAN_ERROR_ACK : gd32f10x_can.h
  • CAN_ERROR_BITDOMINANTER : gd32f10x_can.h
  • CAN_ERROR_BITRECESSIVE : gd32f10x_can.h
  • CAN_ERROR_CRC : gd32f10x_can.h
  • can_error_enum : gd32f10x_can.h
  • CAN_ERROR_FILL : gd32f10x_can.h
  • CAN_ERROR_FORMATE : gd32f10x_can.h
  • can_error_get() : gd32f10x_can.h , gd32f10x_can.c
  • CAN_ERROR_NONE : gd32f10x_can.h
  • CAN_ERROR_SOFTWARECFG : gd32f10x_can.h
  • CAN_F0DATA0 : gd32f10x_can.h
  • CAN_F0DATA1 : gd32f10x_can.h
  • CAN_F10DATA0 : gd32f10x_can.h
  • CAN_F10DATA1 : gd32f10x_can.h
  • CAN_F11DATA0 : gd32f10x_can.h
  • CAN_F11DATA1 : gd32f10x_can.h
  • CAN_F12DATA0 : gd32f10x_can.h
  • CAN_F12DATA1 : gd32f10x_can.h
  • CAN_F13DATA0 : gd32f10x_can.h
  • CAN_F13DATA1 : gd32f10x_can.h
  • CAN_F14DATA0 : gd32f10x_can.h
  • CAN_F14DATA1 : gd32f10x_can.h
  • CAN_F15DATA0 : gd32f10x_can.h
  • CAN_F15DATA1 : gd32f10x_can.h
  • CAN_F16DATA0 : gd32f10x_can.h
  • CAN_F16DATA1 : gd32f10x_can.h
  • CAN_F17DATA0 : gd32f10x_can.h
  • CAN_F17DATA1 : gd32f10x_can.h
  • CAN_F18DATA0 : gd32f10x_can.h
  • CAN_F18DATA1 : gd32f10x_can.h
  • CAN_F19DATA0 : gd32f10x_can.h
  • CAN_F19DATA1 : gd32f10x_can.h
  • CAN_F1DATA0 : gd32f10x_can.h
  • CAN_F1DATA1 : gd32f10x_can.h
  • CAN_F20DATA0 : gd32f10x_can.h
  • CAN_F20DATA1 : gd32f10x_can.h
  • CAN_F21DATA0 : gd32f10x_can.h
  • CAN_F21DATA1 : gd32f10x_can.h
  • CAN_F22DATA0 : gd32f10x_can.h
  • CAN_F22DATA1 : gd32f10x_can.h
  • CAN_F23DATA0 : gd32f10x_can.h
  • CAN_F23DATA1 : gd32f10x_can.h
  • CAN_F24DATA0 : gd32f10x_can.h
  • CAN_F24DATA1 : gd32f10x_can.h
  • CAN_F25DATA0 : gd32f10x_can.h
  • CAN_F25DATA1 : gd32f10x_can.h
  • CAN_F26DATA0 : gd32f10x_can.h
  • CAN_F26DATA1 : gd32f10x_can.h
  • CAN_F27DATA0 : gd32f10x_can.h
  • CAN_F27DATA1 : gd32f10x_can.h
  • CAN_F2DATA0 : gd32f10x_can.h
  • CAN_F2DATA1 : gd32f10x_can.h
  • CAN_F3DATA0 : gd32f10x_can.h
  • CAN_F3DATA1 : gd32f10x_can.h
  • CAN_F4DATA0 : gd32f10x_can.h
  • CAN_F4DATA1 : gd32f10x_can.h
  • CAN_F5DATA0 : gd32f10x_can.h
  • CAN_F5DATA1 : gd32f10x_can.h
  • CAN_F6DATA0 : gd32f10x_can.h
  • CAN_F6DATA1 : gd32f10x_can.h
  • CAN_F7DATA0 : gd32f10x_can.h
  • CAN_F7DATA1 : gd32f10x_can.h
  • CAN_F8DATA0 : gd32f10x_can.h
  • CAN_F8DATA1 : gd32f10x_can.h
  • CAN_F9DATA0 : gd32f10x_can.h
  • CAN_F9DATA1 : gd32f10x_can.h
  • CAN_FAFIFO : gd32f10x_can.h
  • CAN_FAFIFOR_FAF : gd32f10x_can.h
  • CAN_FCTL : gd32f10x_can.h
  • CAN_FCTL_FLD : gd32f10x_can.h
  • CAN_FCTL_HBC1F : gd32f10x_can.h
  • CAN_FDATA0 : gd32f10x_can.h
  • CAN_FDATA1 : gd32f10x_can.h
  • CAN_FDATA_FD : gd32f10x_can.h
  • CAN_FF_EXTENDED : gd32f10x_can.h
  • CAN_FF_STANDARD : gd32f10x_can.h
  • CAN_FIFO0 : gd32f10x_can.h
  • CAN_FIFO1 : gd32f10x_can.h
  • can_fifo_release() : gd32f10x_can.h , gd32f10x_can.c
  • can_filter_init() : gd32f10x_can.h , gd32f10x_can.c
  • CAN_FILTER_MASK_16BITS : gd32f10x_can.h
  • CAN_FILTERBITS_16BIT : gd32f10x_can.h
  • CAN_FILTERBITS_32BIT : gd32f10x_can.h
  • CAN_FILTERMODE_LIST : gd32f10x_can.h
  • CAN_FILTERMODE_MASK : gd32f10x_can.h
  • CAN_FLAG_BOERR : gd32f10x_can.h
  • can_flag_clear() : gd32f10x_can.h , gd32f10x_can.c
  • can_flag_enum : gd32f10x_can.h
  • can_flag_get() : gd32f10x_can.h , gd32f10x_can.c
  • CAN_FLAG_MTE0 : gd32f10x_can.h
  • CAN_FLAG_MTE1 : gd32f10x_can.h
  • CAN_FLAG_MTE2 : gd32f10x_can.h
  • CAN_FLAG_MTF0 : gd32f10x_can.h
  • CAN_FLAG_MTF1 : gd32f10x_can.h
  • CAN_FLAG_MTF2 : gd32f10x_can.h
  • CAN_FLAG_PERR : gd32f10x_can.h
  • CAN_FLAG_RFF0 : gd32f10x_can.h
  • CAN_FLAG_RFF1 : gd32f10x_can.h
  • CAN_FLAG_RFO0 : gd32f10x_can.h
  • CAN_FLAG_RFO1 : gd32f10x_can.h
  • CAN_FLAG_WERR : gd32f10x_can.h
  • CAN_FMCFG : gd32f10x_can.h
  • CAN_FMCFG_FMOD : gd32f10x_can.h
  • CAN_FSCFG : gd32f10x_can.h
  • CAN_FSCFG_FS : gd32f10x_can.h
  • CAN_FT_DATA : gd32f10x_can.h
  • CAN_FT_REMOTE : gd32f10x_can.h
  • CAN_FW : gd32f10x_can.h
  • CAN_FW_FW : gd32f10x_can.h
  • can_init() : gd32f10x_can.h , gd32f10x_can.c
  • CAN_INT_BO : gd32f10x_can.h
  • CAN_INT_ERR : gd32f10x_can.h
  • CAN_INT_ERRN : gd32f10x_can.h
  • CAN_INT_FLAG_ERRIF : gd32f10x_can.h
  • CAN_INT_FLAG_MTF0 : gd32f10x_can.h
  • CAN_INT_FLAG_MTF1 : gd32f10x_can.h
  • CAN_INT_FLAG_MTF2 : gd32f10x_can.h
  • CAN_INT_FLAG_RFF0 : gd32f10x_can.h
  • CAN_INT_FLAG_RFF1 : gd32f10x_can.h
  • CAN_INT_FLAG_RFO0 : gd32f10x_can.h
  • CAN_INT_FLAG_RFO1 : gd32f10x_can.h
  • CAN_INT_FLAG_SLPIF : gd32f10x_can.h
  • CAN_INT_FLAG_WUIF : gd32f10x_can.h
  • CAN_INT_PERR : gd32f10x_can.h
  • CAN_INT_RFF0 : gd32f10x_can.h
  • CAN_INT_RFF1 : gd32f10x_can.h
  • CAN_INT_RFNE0 : gd32f10x_can.h
  • CAN_INT_RFNE1 : gd32f10x_can.h
  • CAN_INT_RFO0 : gd32f10x_can.h
  • CAN_INT_RFO1 : gd32f10x_can.h
  • CAN_INT_SLPW : gd32f10x_can.h
  • CAN_INT_TME : gd32f10x_can.h
  • CAN_INT_WAKEUP : gd32f10x_can.h
  • CAN_INT_WERR : gd32f10x_can.h
  • CAN_INTEN : gd32f10x_can.h
  • CAN_INTEN_BOIE : gd32f10x_can.h
  • CAN_INTEN_ERRIE : gd32f10x_can.h
  • CAN_INTEN_ERRNIE : gd32f10x_can.h
  • CAN_INTEN_PERRIE : gd32f10x_can.h
  • CAN_INTEN_RFFIE0 : gd32f10x_can.h
  • CAN_INTEN_RFFIE1 : gd32f10x_can.h
  • CAN_INTEN_RFNEIE0 : gd32f10x_can.h
  • CAN_INTEN_RFNEIE1 : gd32f10x_can.h
  • CAN_INTEN_RFOIE0 : gd32f10x_can.h
  • CAN_INTEN_RFOIE1 : gd32f10x_can.h
  • CAN_INTEN_SLPWIE : gd32f10x_can.h
  • CAN_INTEN_TMEIE : gd32f10x_can.h
  • CAN_INTEN_WERRIE : gd32f10x_can.h
  • CAN_INTEN_WIE : gd32f10x_can.h
  • can_interrupt_disable() : gd32f10x_can.h , gd32f10x_can.c
  • can_interrupt_enable() : gd32f10x_can.h , gd32f10x_can.c
  • can_interrupt_flag_clear() : gd32f10x_can.h , gd32f10x_can.c
  • can_interrupt_flag_enum : gd32f10x_can.h
  • can_interrupt_flag_get() : gd32f10x_can.h , gd32f10x_can.c
  • CAN_LOOPBACK_MODE : gd32f10x_can.h
  • CAN_MAILBOX0 : gd32f10x_can.h
  • CAN_MAILBOX1 : gd32f10x_can.h
  • CAN_MAILBOX2 : gd32f10x_can.h
  • can_message_receive() : gd32f10x_can.h , gd32f10x_can.c
  • can_message_transmit() : gd32f10x_can.h , gd32f10x_can.c
  • CAN_MODE_INITIALIZE : gd32f10x_can.h
  • CAN_MODE_NORMAL : gd32f10x_can.h
  • CAN_MODE_SLEEP : gd32f10x_can.h
  • CAN_NOMAILBOX : gd32f10x_can.h
  • CAN_NORMAL_MODE : gd32f10x_can.h
  • can_receive_error_number_get() : gd32f10x_can.h , gd32f10x_can.c
  • can_receive_message_length_get() : gd32f10x_can.c , gd32f10x_can.h
  • CAN_REG_VAL : gd32f10x_can.h
  • CAN_REG_VALS : gd32f10x_can.h
  • CAN_REGIDX_BIT : gd32f10x_can.h
  • CAN_REGIDX_BITS : gd32f10x_can.h
  • CAN_RFIF_RFL_MASK : gd32f10x_can.h
  • CAN_RFIFO0 : gd32f10x_can.h
  • CAN_RFIFO0_RFD0 : gd32f10x_can.h
  • CAN_RFIFO0_RFF0 : gd32f10x_can.h
  • CAN_RFIFO0_RFL0 : gd32f10x_can.h
  • CAN_RFIFO0_RFO0 : gd32f10x_can.h
  • CAN_RFIFO1 : gd32f10x_can.h
  • CAN_RFIFO1_RFD1 : gd32f10x_can.h
  • CAN_RFIFO1_RFF1 : gd32f10x_can.h
  • CAN_RFIFO1_RFL1 : gd32f10x_can.h
  • CAN_RFIFO1_RFO1 : gd32f10x_can.h
  • CAN_RFIFOMDATA0 : gd32f10x_can.h
  • CAN_RFIFOMDATA00 : gd32f10x_can.h
  • CAN_RFIFOMDATA01 : gd32f10x_can.h
  • CAN_RFIFOMDATA0_DB0 : gd32f10x_can.h
  • CAN_RFIFOMDATA0_DB1 : gd32f10x_can.h
  • CAN_RFIFOMDATA0_DB2 : gd32f10x_can.h
  • CAN_RFIFOMDATA0_DB3 : gd32f10x_can.h
  • CAN_RFIFOMDATA1 : gd32f10x_can.h
  • CAN_RFIFOMDATA10 : gd32f10x_can.h
  • CAN_RFIFOMDATA11 : gd32f10x_can.h
  • CAN_RFIFOMDATA1_DB4 : gd32f10x_can.h
  • CAN_RFIFOMDATA1_DB5 : gd32f10x_can.h
  • CAN_RFIFOMDATA1_DB6 : gd32f10x_can.h
  • CAN_RFIFOMDATA1_DB7 : gd32f10x_can.h
  • CAN_RFIFOMI : gd32f10x_can.h
  • CAN_RFIFOMI0 : gd32f10x_can.h
  • CAN_RFIFOMI1 : gd32f10x_can.h
  • CAN_RFIFOMI_EFID : gd32f10x_can.h
  • CAN_RFIFOMI_FF : gd32f10x_can.h
  • CAN_RFIFOMI_FT : gd32f10x_can.h
  • CAN_RFIFOMI_SFID : gd32f10x_can.h
  • CAN_RFIFOMP : gd32f10x_can.h
  • CAN_RFIFOMP0 : gd32f10x_can.h
  • CAN_RFIFOMP1 : gd32f10x_can.h
  • CAN_RFIFOMP_DLENC : gd32f10x_can.h
  • CAN_RFIFOMP_FI : gd32f10x_can.h
  • CAN_RFIFOMP_TS : gd32f10x_can.h
  • CAN_SFID_MASK : gd32f10x_can.h
  • CAN_SILENT_LOOPBACK_MODE : gd32f10x_can.h
  • CAN_SILENT_MODE : gd32f10x_can.h
  • CAN_STAT : gd32f10x_can.h
  • CAN_STAT_ERRIF : gd32f10x_can.h
  • CAN_STAT_IWS : gd32f10x_can.h
  • CAN_STAT_LASTRX : gd32f10x_can.h
  • CAN_STAT_RS : gd32f10x_can.h
  • CAN_STAT_RXL : gd32f10x_can.h
  • CAN_STAT_SLPIF : gd32f10x_can.h
  • CAN_STAT_SLPWS : gd32f10x_can.h
  • CAN_STAT_TS : gd32f10x_can.h
  • CAN_STAT_WUIF : gd32f10x_can.h
  • CAN_STATE_PENDING : gd32f10x_can.h
  • can_time_trigger_mode_disable() : gd32f10x_can.h , gd32f10x_can.c
  • can_time_trigger_mode_enable() : gd32f10x_can.c , gd32f10x_can.h
  • CAN_TIMEOUT : gd32f10x_can.h
  • CAN_TMDATA0 : gd32f10x_can.h
  • CAN_TMDATA00 : gd32f10x_can.h
  • CAN_TMDATA01 : gd32f10x_can.h
  • CAN_TMDATA02 : gd32f10x_can.h
  • CAN_TMDATA0_DB0 : gd32f10x_can.h
  • CAN_TMDATA0_DB1 : gd32f10x_can.h
  • CAN_TMDATA0_DB2 : gd32f10x_can.h
  • CAN_TMDATA0_DB3 : gd32f10x_can.h
  • CAN_TMDATA1 : gd32f10x_can.h
  • CAN_TMDATA10 : gd32f10x_can.h
  • CAN_TMDATA11 : gd32f10x_can.h
  • CAN_TMDATA12 : gd32f10x_can.h
  • CAN_TMDATA1_DB4 : gd32f10x_can.h
  • CAN_TMDATA1_DB5 : gd32f10x_can.h
  • CAN_TMDATA1_DB6 : gd32f10x_can.h
  • CAN_TMDATA1_DB7 : gd32f10x_can.h
  • CAN_TMI : gd32f10x_can.h
  • CAN_TMI0 : gd32f10x_can.h
  • CAN_TMI1 : gd32f10x_can.h
  • CAN_TMI2 : gd32f10x_can.h
  • CAN_TMI_EFID : gd32f10x_can.h
  • CAN_TMI_FF : gd32f10x_can.h
  • CAN_TMI_FT : gd32f10x_can.h
  • CAN_TMI_SFID : gd32f10x_can.h
  • CAN_TMI_TEN : gd32f10x_can.h
  • CAN_TMP : gd32f10x_can.h
  • CAN_TMP0 : gd32f10x_can.h
  • CAN_TMP1 : gd32f10x_can.h
  • CAN_TMP2 : gd32f10x_can.h
  • CAN_TMP_DLENC : gd32f10x_can.h
  • CAN_TMP_TS : gd32f10x_can.h
  • CAN_TMP_TSEN : gd32f10x_can.h
  • can_transmission_stop() : gd32f10x_can.h , gd32f10x_can.c
  • can_transmit_error_number_get() : gd32f10x_can.h , gd32f10x_can.c
  • CAN_TRANSMIT_FAILED : gd32f10x_can.h
  • CAN_TRANSMIT_NOMAILBOX : gd32f10x_can.h
  • CAN_TRANSMIT_OK : gd32f10x_can.h
  • CAN_TRANSMIT_PENDING : gd32f10x_can.h
  • can_transmit_state_enum : gd32f10x_can.h
  • can_transmit_states() : gd32f10x_can.h , gd32f10x_can.c
  • CAN_TSTAT : gd32f10x_can.h
  • CAN_TSTAT_MAL0 : gd32f10x_can.h
  • CAN_TSTAT_MAL1 : gd32f10x_can.h
  • CAN_TSTAT_MAL2 : gd32f10x_can.h
  • CAN_TSTAT_MST0 : gd32f10x_can.h
  • CAN_TSTAT_MST1 : gd32f10x_can.h
  • CAN_TSTAT_MST2 : gd32f10x_can.h
  • CAN_TSTAT_MTE0 : gd32f10x_can.h
  • CAN_TSTAT_MTE1 : gd32f10x_can.h
  • CAN_TSTAT_MTE2 : gd32f10x_can.h
  • CAN_TSTAT_MTF0 : gd32f10x_can.h
  • CAN_TSTAT_MTF1 : gd32f10x_can.h
  • CAN_TSTAT_MTF2 : gd32f10x_can.h
  • CAN_TSTAT_MTFNERR0 : gd32f10x_can.h
  • CAN_TSTAT_MTFNERR1 : gd32f10x_can.h
  • CAN_TSTAT_MTFNERR2 : gd32f10x_can.h
  • CAN_TSTAT_NUM : gd32f10x_can.h
  • CAN_TSTAT_TME0 : gd32f10x_can.h
  • CAN_TSTAT_TME1 : gd32f10x_can.h
  • CAN_TSTAT_TME2 : gd32f10x_can.h
  • CAN_TSTAT_TMLS0 : gd32f10x_can.h
  • CAN_TSTAT_TMLS1 : gd32f10x_can.h
  • CAN_TSTAT_TMLS2 : gd32f10x_can.h
  • can_wakeup() : gd32f10x_can.h , gd32f10x_can.c
  • can_working_mode_set() : gd32f10x_can.h , gd32f10x_can.c
  • CBI_PROTOCOL : usbh_core.h
  • CCHP_PROT : gd32f10x_timer.h
  • CFG0_AHBPSC : gd32f10x_rcu.h
  • CFG0_APB1PSC : gd32f10x_rcu.h
  • CFG0_APB2PSC : gd32f10x_rcu.h
  • CFG0_CKOUT0SEL : gd32f10x_rcu.h
  • CFG0_PLLMF : gd32f10x_rcu.h
  • CFG0_REG_OFFSET : gd32f10x_rcu.h
  • CFG0_SCS : gd32f10x_rcu.h
  • CFG0_SCSS : gd32f10x_rcu.h
  • CFG0_USBPSC : gd32f10x_rcu.h
  • CFG1_PLL1MF : gd32f10x_rcu.h
  • CFG1_PLL2MF : gd32f10x_rcu.h
  • CFG1_PREDV0 : gd32f10x_rcu.h
  • CFG1_PREDV1 : gd32f10x_rcu.h
  • CFG1_REG_OFFSET : gd32f10x_rcu.h
  • CFG_PSC : gd32f10x_wwdgt.h
  • CFG_WIN : gd32f10x_wwdgt.c
  • CHCTL_MWIDTH : gd32f10x_dma.h
  • CHCTL_PRIO : gd32f10x_dma.h
  • CHCTL_PWIDTH : gd32f10x_dma.h
  • CHN_LANGID : usbd_std.h
  • CID_CID : usb_regs.h
  • CK_AHB : gd32f10x_rcu.h
  • CK_APB1 : gd32f10x_rcu.h
  • CK_APB2 : gd32f10x_rcu.h
  • CK_SYS : gd32f10x_rcu.h
  • CKCFG_DTCY : gd32f10x_i2c.h
  • CLASS_FSM_ID : usbh_core.h
  • class_polling_cb : usbh_core.c
  • CLASS_REQ_FSM_ID : usbh_core.h
  • CLKCTL_BUSMODE : gd32f10x_sdio.h
  • CLR_ERRIF : usbd_regs.h
  • CLR_ESOFIF : usbd_regs.h
  • CLR_L1REQ : usbd_regs.h
  • CLR_PMOUIF : usbd_regs.h
  • CLR_RSTIF : usbd_regs.h
  • CLR_SOFIF : usbd_regs.h
  • CLR_SPSIF : usbd_regs.h
  • CLR_STIF : usbd_regs.h
  • CLR_WKUPIF : usbd_regs.h
  • CLT2_CTSEN : gd32f10x_usart.h
  • CLT2_DENR : gd32f10x_usart.h
  • CLT2_DENT : gd32f10x_usart.h
  • CLT2_RTSEN : gd32f10x_usart.h
  • CMD_FSM_ID : usbh_core.h
  • CMDCTL_CMDRESP : gd32f10x_sdio.h
  • CRC : gd32f10x_crc.h
  • crc_block_data_calculate() : gd32f10x_crc.c , gd32f10x_crc.h
  • CRC_CTL : gd32f10x_crc.h
  • CRC_CTL_RST : gd32f10x_crc.h
  • CRC_DATA : gd32f10x_crc.h
  • CRC_DATA_DATA : gd32f10x_crc.h
  • crc_data_register_read() : gd32f10x_crc.c , gd32f10x_crc.h
  • crc_data_register_reset() : gd32f10x_crc.c , gd32f10x_crc.h
  • crc_deinit() : gd32f10x_crc.h , gd32f10x_crc.c
  • CRC_FDATA : gd32f10x_crc.h
  • CRC_FDATA_FDATA : gd32f10x_crc.h
  • crc_free_data_register_read() : gd32f10x_crc.c , gd32f10x_crc.h
  • crc_free_data_register_write() : gd32f10x_crc.c , gd32f10x_crc.h
  • crc_single_data_calculate() : gd32f10x_crc.h , gd32f10x_crc.c
  • CTL0_CAM : gd32f10x_timer.h
  • CTL0_CKDIV : gd32f10x_timer.h
  • CTL0_DISNUM : gd32f10x_adc.h
  • CTL0_PM : gd32f10x_usart.h
  • CTL0_PSC : gd32f10x_spi.h
  • CTL0_REN : gd32f10x_usart.h
  • CTL0_SYNCM : gd32f10x_adc.h
  • CTL0_TEN : gd32f10x_usart.h
  • CTL0_TRACE_MODE : gd32f10x_dbg.h
  • CTL0_WL : gd32f10x_usart.h
  • CTL0_WM : gd32f10x_usart.h
  • CTL1_CLEN : gd32f10x_usart.h
  • CTL1_CPH : gd32f10x_usart.h
  • CTL1_CPL : gd32f10x_usart.h
  • CTL1_ETSIC : gd32f10x_adc.h
  • CTL1_ETSRC : gd32f10x_adc.h
  • CTL1_LBLEN : gd32f10x_usart.h
  • CTL1_MMC : gd32f10x_timer.h
  • CTL1_STB : gd32f10x_usart.h
  • CTL2_IRLP : gd32f10x_usart.h
  • CTL_CLOSE : usbd_regs.h
  • CTL_CMD : gd32f10x_fwdgt.c
  • CTL_CNT : gd32f10x_wwdgt.c
  • CTL_DTSEL : gd32f10x_dac.h
  • CTL_DWM : gd32f10x_dac.h
  • CTL_ERRIE : usbd_regs.h
  • CTL_ESOFIE : usbd_regs.h
  • CTL_L1REQIE : usbd_regs.h
  • CTL_L1RSREQ : usbd_regs.h
  • CTL_LOWM : usbd_regs.h
  • CTL_LVDT : gd32f10x_pmu.h
  • CTL_PMOUIE : usbd_regs.h
  • CTL_REG_OFFSET : gd32f10x_rcu.h
  • CTL_RSREQ : usbd_regs.h
  • CTL_RSTIE : usbd_regs.h
  • CTL_SETRST : usbd_regs.h
  • CTL_SETSPS : usbd_regs.h
  • CTL_SOFIE : usbd_regs.h
  • CTL_SPSIE : usbd_regs.h
  • CTL_STIE : usbd_regs.h
  • CTL_WKUPIE : usbd_regs.h
  • CTRL_COMPLETE : usbh_core.h
  • CTRL_DATA : usbh_core.h
  • ctrl_data_wait_flag : usbh_ctrl.c
  • CTRL_ERROR : usbh_core.h
  • CTRL_EVENT_COMPLETE : usbh_ctrl.h
  • CTRL_EVENT_DATA : usbh_ctrl.h
  • ctrl_event_enum : usbh_ctrl.h
  • CTRL_EVENT_ERROR : usbh_ctrl.h
  • CTRL_EVENT_IDLE : usbh_ctrl.h
  • CTRL_EVENT_SETUP : usbh_ctrl.h
  • CTRL_EVENT_STALLED : usbh_ctrl.h
  • CTRL_EVENT_STATUS : usbh_ctrl.h
  • CTRL_FSM_ID : usbh_core.h
  • ctrl_handle_table : usbh_ctrl.c , usbh_ctrl.h
  • CTRL_HANDLE_TABLE_SIZE : usbh_ctrl.h
  • CTRL_IDLE : usbh_core.h
  • ctrl_polling_handle_flag : usbh_ctrl.c , usbh_ctrl.h
  • CTRL_SETUP : usbh_core.h
  • ctrl_setup_wait_flag : usbh_ctrl.c
  • CTRL_STALLED : usbh_core.h
  • ctrl_state_enum : usbh_core.h
  • ctrl_state_handle : usbh_ctrl.c
  • ctrl_state_polling_fun() : usbh_ctrl.h , usbh_ctrl.c
  • CTRL_STATUS : usbh_core.h
  • ctrl_status_wait_flag : usbh_ctrl.c


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • u
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC : gd32f10x_dac.h
  • DAC0 : gd32f10x_dac.h
  • DAC0_DO : gd32f10x_dac.h
  • DAC0_DO_DAC0_DO : gd32f10x_dac.h
  • DAC0_L12DH : gd32f10x_dac.h
  • DAC0_L12DH_DAC0_DH : gd32f10x_dac.h
  • DAC0_R12DH : gd32f10x_dac.h
  • DAC0_R12DH_DAC0_DH : gd32f10x_dac.h
  • DAC0_R8DH : gd32f10x_dac.h
  • DAC0_R8DH_DAC0_DH : gd32f10x_dac.h
  • DAC1 : gd32f10x_dac.h
  • DAC1_DO : gd32f10x_dac.h
  • DAC1_DO_DAC1_DO : gd32f10x_dac.h
  • DAC1_L12DH : gd32f10x_dac.h
  • DAC1_L12DH_DAC1_DH : gd32f10x_dac.h
  • DAC1_R12DH : gd32f10x_dac.h
  • DAC1_R12DH_DAC1_DH : gd32f10x_dac.h
  • DAC1_R8DH : gd32f10x_dac.h
  • DAC1_R8DH_DAC1_DH : gd32f10x_dac.h
  • DAC_ALIGN_12B_L : gd32f10x_dac.h
  • DAC_ALIGN_12B_R : gd32f10x_dac.h
  • DAC_ALIGN_8B_R : gd32f10x_dac.h
  • dac_concurrent_data_set() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_concurrent_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_concurrent_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_concurrent_output_buffer_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_concurrent_output_buffer_enable() : gd32f10x_dac.c , gd32f10x_dac.h
  • dac_concurrent_software_trigger_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_concurrent_software_trigger_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • DAC_CTL : gd32f10x_dac.h
  • DAC_CTL_DBOFF0 : gd32f10x_dac.h
  • DAC_CTL_DBOFF1 : gd32f10x_dac.h
  • DAC_CTL_DDMAEN0 : gd32f10x_dac.h
  • DAC_CTL_DDMAEN1 : gd32f10x_dac.h
  • DAC_CTL_DEN0 : gd32f10x_dac.h
  • DAC_CTL_DEN1 : gd32f10x_dac.h
  • DAC_CTL_DTEN0 : gd32f10x_dac.h
  • DAC_CTL_DTEN1 : gd32f10x_dac.h
  • DAC_CTL_DTSEL0 : gd32f10x_dac.h
  • DAC_CTL_DTSEL1 : gd32f10x_dac.h
  • DAC_CTL_DWBW0 : gd32f10x_dac.h
  • DAC_CTL_DWBW1 : gd32f10x_dac.h
  • DAC_CTL_DWM0 : gd32f10x_dac.h
  • DAC_CTL_DWM1 : gd32f10x_dac.h
  • dac_data_set() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_deinit() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_dma_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_dma_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • DAC_LFSR_BIT0 : gd32f10x_dac.h
  • DAC_LFSR_BITS10_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS11_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS1_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS2_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS3_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS4_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS5_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS6_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS7_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS8_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS9_0 : gd32f10x_dac.h
  • dac_lfsr_noise_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_output_buffer_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_output_buffer_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_output_value_get() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_software_trigger_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_software_trigger_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • DAC_SWT : gd32f10x_dac.h
  • DAC_SWT_SWTR0 : gd32f10x_dac.h
  • DAC_SWT_SWTR1 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_1 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_1023 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_127 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_15 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_2047 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_255 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_3 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_31 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_4095 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_511 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_63 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_7 : gd32f10x_dac.h
  • dac_triangle_noise_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_trigger_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_trigger_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • DAC_TRIGGER_EXTI_9 : gd32f10x_dac.h
  • DAC_TRIGGER_SOFTWARE : gd32f10x_dac.h
  • dac_trigger_source_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • DAC_TRIGGER_T1_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T3_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T4_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T5_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T6_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T7_TRGO : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_1 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_10 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_11 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_12 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_2 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_3 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_4 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_5 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_6 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_7 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_8 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_9 : gd32f10x_dac.h
  • dac_wave_bit_width_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • DAC_WAVE_DISABLE : gd32f10x_dac.h
  • dac_wave_mode_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • DAC_WAVE_MODE_LFSR : gd32f10x_dac.h
  • DAC_WAVE_MODE_TRIANGLE : gd32f10x_dac.h
  • DACC_L12DH : gd32f10x_dac.h
  • DACC_L12DH_DAC0_DH : gd32f10x_dac.h
  • DACC_L12DH_DAC1_DH : gd32f10x_dac.h
  • DACC_R12DH : gd32f10x_dac.h
  • DACC_R12DH_DAC0_DH : gd32f10x_dac.h
  • DACC_R12DH_DAC1_DH : gd32f10x_dac.h
  • DACC_R8DH : gd32f10x_dac.h
  • DACC_R8DH_DAC0_DH : gd32f10x_dac.h
  • DACC_R8DH_DAC1_DH : gd32f10x_dac.h
  • DADDR_USBDAR : usbd_regs.h
  • DADDR_USBEN : usbd_regs.h
  • DAEPINT_IEPITB : usb_regs.h
  • DAEPINT_OEPITB : usb_regs.h
  • DAEPINTEN_IEPIE : usb_regs.h
  • DAEPINTEN_OEPIE : usb_regs.h
  • DATA_ALIGN : gd32f10x_dac.h
  • DATA_RECV : gd32f10x_i2c.h
  • DATA_STAGE_TIMEOUT : usb_std.h
  • DATA_TRANS : gd32f10x_i2c.h
  • DATACTL_BLKSZ : gd32f10x_sdio.h
  • DBG : gd32f10x_dbg.h
  • DBG_CAN0_HOLD : gd32f10x_dbg.h
  • DBG_CTL0 : gd32f10x_dbg.h
  • DBG_CTL0_CAN0_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_DSLP_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_FWDGT_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_I2C0_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_I2C1_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_SLP_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_STB_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER0_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER10_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER11_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER12_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER13_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER1_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER2_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER3_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER4_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER5_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER6_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER7_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER8_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER9_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TRACE_IOEN : gd32f10x_dbg.h
  • DBG_CTL0_TRACE_MODE : gd32f10x_dbg.h
  • DBG_CTL0_WWDGT_HOLD : gd32f10x_dbg.h
  • DBG_FWDGT_HOLD : gd32f10x_dbg.h
  • DBG_I2C0_HOLD : gd32f10x_dbg.h
  • DBG_I2C1_HOLD : gd32f10x_dbg.h
  • DBG_ID : gd32f10x_dbg.h
  • dbg_id_get() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • DBG_ID_ID_CODE : gd32f10x_dbg.h
  • DBG_LOW_POWER_DEEPSLEEP : gd32f10x_dbg.h
  • dbg_low_power_disable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_low_power_enable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • DBG_LOW_POWER_SLEEP : gd32f10x_dbg.h
  • DBG_LOW_POWER_STANDBY : gd32f10x_dbg.h
  • dbg_periph_disable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_periph_enable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_periph_enum : gd32f10x_dbg.h
  • DBG_TIMER0_HOLD : gd32f10x_dbg.h
  • DBG_TIMER1_HOLD : gd32f10x_dbg.h
  • DBG_TIMER2_HOLD : gd32f10x_dbg.h
  • DBG_TIMER3_HOLD : gd32f10x_dbg.h
  • DBG_TIMER4_HOLD : gd32f10x_dbg.h
  • DBG_TIMER5_HOLD : gd32f10x_dbg.h
  • DBG_TIMER6_HOLD : gd32f10x_dbg.h
  • DBG_TIMER7_HOLD : gd32f10x_dbg.h
  • dbg_trace_pin_disable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_trace_pin_enable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_trace_pin_mode_set() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • DBG_WWDGT_HOLD : gd32f10x_dbg.h
  • dbuf_ep_dir_enum : usbd_regs.h
  • DBUF_EP_ERR : usbd_regs.h
  • DBUF_EP_IN : usbd_regs.h
  • DBUF_EP_OUT : usbd_regs.h
  • DCFG_DAR : usb_regs.h
  • DCFG_DEVSPEED : usb_regs.h
  • DCFG_DS : usb_regs.h
  • DCFG_EOPFT : usb_regs.h
  • DCFG_NZLSOH : usb_regs.h
  • DCFG_PFRI : usb_regs.h
  • DCTL_CGINAK : usb_regs.h
  • DCTL_CGONAK : usb_regs.h
  • DCTL_GINS : usb_regs.h
  • DCTL_GONS : usb_regs.h
  • DCTL_POIF : usb_regs.h
  • DCTL_RWKUP : usb_regs.h
  • DCTL_SD : usb_regs.h
  • DCTL_SGINAK : usb_regs.h
  • DCTL_SGONAK : usb_regs.h
  • DEFAULT_RESET_VALUE : gd32f10x_sdio.c
  • DEP0_MPL : usb_regs.h
  • DEP0CTL_CNAK : usb_regs.h
  • DEP0CTL_EPACT : usb_regs.h
  • DEP0CTL_EPD : usb_regs.h
  • DEP0CTL_EPEN : usb_regs.h
  • DEP0CTL_EPTYPE : usb_regs.h
  • DEP0CTL_MPL : usb_regs.h
  • DEP0CTL_NAKS : usb_regs.h
  • DEP0CTL_SNAK : usb_regs.h
  • DEP0CTL_STALL : usb_regs.h
  • DEPCTL_CNAK : usb_regs.h
  • DEPCTL_DPID : usb_regs.h
  • DEPCTL_EOFRM : usb_regs.h
  • DEPCTL_EPACT : usb_regs.h
  • DEPCTL_EPD : usb_regs.h
  • DEPCTL_EPEN : usb_regs.h
  • DEPCTL_EPTYPE : usb_regs.h
  • DEPCTL_MPL : usb_regs.h
  • DEPCTL_NAKS : usb_regs.h
  • DEPCTL_SD0PID : usb_regs.h
  • DEPCTL_SD1PID : usb_regs.h
  • DEPCTL_SEVNFRM : usb_regs.h
  • DEPCTL_SNAK : usb_regs.h
  • DEPCTL_SODDFRM : usb_regs.h
  • DEPCTL_STALL : usb_regs.h
  • DEPLEN_PCNT : usb_regs.h
  • DEPLEN_TLEN : usb_regs.h
  • DEVICE_MODE : usb_defines.h
  • DIEP0CTL_TXFNUM : usb_regs.h
  • DIEP0LEN_PCNT : usb_regs.h
  • DIEP0LEN_TLEN : usb_regs.h
  • DIEP0TFLEN_IEP0TXFD : usb_regs.h
  • DIEP0TFLEN_IEP0TXRSAR : usb_regs.h
  • DIEPCTL_TXFNUM : usb_regs.h
  • DIEPFEINTEN_IEPTXFEIE : usb_regs.h
  • DIEPINTEN_CITOEN : usb_regs.h
  • DIEPINTEN_EPDISEN : usb_regs.h
  • DIEPINTEN_EPTXFUDEN : usb_regs.h
  • DIEPINTEN_IEPNEEN : usb_regs.h
  • DIEPINTEN_TFEN : usb_regs.h
  • DIEPINTEN_TXFEEN : usb_regs.h
  • DIEPINTF_CITO : usb_regs.h
  • DIEPINTF_EPDIS : usb_regs.h
  • DIEPINTF_EPTXFUD : usb_regs.h
  • DIEPINTF_IEPNE : usb_regs.h
  • DIEPINTF_TF : usb_regs.h
  • DIEPINTF_TXFE : usb_regs.h
  • DIEPLEN_MCNT : usb_regs.h
  • DIEPTFLEN_IEPTXFD : usb_regs.h
  • DIEPTFLEN_IEPTXRSAR : usb_regs.h
  • DIEPTFSTAT_IEPTFS : usb_regs.h
  • DMA0 : gd32f10x_dma.h
  • DMA1 : gd32f10x_dma.h
  • DMA_ARBITRATION_OPTION : gd32f10x_enet.h
  • DMA_BCTL_DPSL : gd32f10x_enet.h
  • DMA_BCTL_MASK : gd32f10x_enet.h
  • DMA_BCTL_PGBL : gd32f10x_enet.h
  • DMA_BCTL_RTPR : gd32f10x_enet.h
  • DMA_BCTL_RXDP : gd32f10x_enet.h
  • DMA_CH0 : gd32f10x_dma.h
  • DMA_CH0CNT : gd32f10x_dma.h
  • DMA_CH0CTL : gd32f10x_dma.h
  • DMA_CH0MADDR : gd32f10x_dma.h
  • DMA_CH0PADDR : gd32f10x_dma.h
  • DMA_CH1 : gd32f10x_dma.h
  • DMA_CH1CNT : gd32f10x_dma.h
  • DMA_CH1CTL : gd32f10x_dma.h
  • DMA_CH1MADDR : gd32f10x_dma.h
  • DMA_CH1PADDR : gd32f10x_dma.h
  • DMA_CH2 : gd32f10x_dma.h
  • DMA_CH2CNT : gd32f10x_dma.h
  • DMA_CH2CTL : gd32f10x_dma.h
  • DMA_CH2MADDR : gd32f10x_dma.h
  • DMA_CH2PADDR : gd32f10x_dma.h
  • DMA_CH3 : gd32f10x_dma.h
  • DMA_CH3CNT : gd32f10x_dma.h
  • DMA_CH3CTL : gd32f10x_dma.h
  • DMA_CH3MADDR : gd32f10x_dma.h
  • DMA_CH3PADDR : gd32f10x_dma.h
  • DMA_CH4 : gd32f10x_dma.h
  • DMA_CH4CNT : gd32f10x_dma.h
  • DMA_CH4CTL : gd32f10x_dma.h
  • DMA_CH4MADDR : gd32f10x_dma.h
  • DMA_CH4PADDR : gd32f10x_dma.h
  • DMA_CH5 : gd32f10x_dma.h
  • DMA_CH5CNT : gd32f10x_dma.h
  • DMA_CH5CTL : gd32f10x_dma.h
  • DMA_CH5MADDR : gd32f10x_dma.h
  • DMA_CH5PADDR : gd32f10x_dma.h
  • DMA_CH6 : gd32f10x_dma.h
  • DMA_CH6CNT : gd32f10x_dma.h
  • DMA_CH6CTL : gd32f10x_dma.h
  • DMA_CH6MADDR : gd32f10x_dma.h
  • DMA_CH6PADDR : gd32f10x_dma.h
  • DMA_CHANNEL_CNT_MASK : gd32f10x_dma.h
  • dma_channel_disable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_channel_enable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_channel_enum : gd32f10x_dma.h
  • DMA_CHCNT : gd32f10x_dma.h
  • DMA_CHCNT_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHCTL : gd32f10x_dma.h
  • DMA_CHCTL_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHINTF_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHMADDR : gd32f10x_dma.h
  • DMA_CHMADDR_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHPADDR : gd32f10x_dma.h
  • DMA_CHPADDR_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHXCNT_CNT : gd32f10x_dma.h
  • DMA_CHXCTL_CHEN : gd32f10x_dma.h
  • DMA_CHXCTL_CMEN : gd32f10x_dma.h
  • DMA_CHXCTL_DIR : gd32f10x_dma.h
  • DMA_CHXCTL_ERRIE : gd32f10x_dma.h
  • DMA_CHXCTL_FTFIE : gd32f10x_dma.h
  • DMA_CHXCTL_HTFIE : gd32f10x_dma.h
  • DMA_CHXCTL_M2M : gd32f10x_dma.h
  • DMA_CHXCTL_MNAGA : gd32f10x_dma.h
  • DMA_CHXCTL_MWIDTH : gd32f10x_dma.h
  • DMA_CHXCTL_PNAGA : gd32f10x_dma.h
  • DMA_CHXCTL_PRIO : gd32f10x_dma.h
  • DMA_CHXCTL_PWIDTH : gd32f10x_dma.h
  • DMA_CHXMADDR_MADDR : gd32f10x_dma.h
  • DMA_CHXPADDR_PADDR : gd32f10x_dma.h
  • DMA_CIRCULAR_MODE_DISABLE : gd32f10x_dma.h
  • DMA_CIRCULAR_MODE_ENABLE : gd32f10x_dma.h
  • dma_circulation_disable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_circulation_enable() : gd32f10x_dma.h , gd32f10x_dma.c
  • DMA_CRBADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_CRDADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_CTBADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_CTDADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_CTL_MASK : gd32f10x_enet.h
  • DMA_CTL_RTHC : gd32f10x_enet.h
  • DMA_CTL_TTHC : gd32f10x_enet.h
  • dma_current_ptp_rxdesc : gd32f10x_enet.c
  • dma_current_ptp_txdesc : gd32f10x_enet.c
  • dma_current_rxdesc : gd32f10x_enet.c
  • dma_current_txdesc : gd32f10x_enet.c
  • dma_deinit() : gd32f10x_dma.h , gd32f10x_dma.c
  • DMA_FLAG_ADD : gd32f10x_dma.h
  • dma_flag_clear() : gd32f10x_dma.h , gd32f10x_dma.c
  • DMA_FLAG_ERR : gd32f10x_dma.h
  • DMA_FLAG_FTF : gd32f10x_dma.h
  • DMA_FLAG_G : gd32f10x_dma.h
  • dma_flag_get() : gd32f10x_dma.c , gd32f10x_dma.h
  • DMA_FLAG_HTF : gd32f10x_dma.h
  • DMA_INCR0 : usb_regs.h
  • DMA_INCR1 : usb_regs.h
  • DMA_INCR16 : usb_regs.h
  • DMA_INCR4 : usb_regs.h
  • DMA_INCR8 : usb_regs.h
  • dma_init() : gd32f10x_dma.h , gd32f10x_dma.c
  • DMA_INT_ERR : gd32f10x_dma.h
  • DMA_INT_FLAG_ERR : gd32f10x_dma.h
  • DMA_INT_FLAG_FTF : gd32f10x_dma.h
  • DMA_INT_FLAG_G : gd32f10x_dma.h
  • DMA_INT_FLAG_HTF : gd32f10x_dma.h
  • DMA_INT_FTF : gd32f10x_dma.h
  • DMA_INT_HTF : gd32f10x_dma.h
  • DMA_INTC : gd32f10x_dma.h
  • DMA_INTC_ERRIFC : gd32f10x_dma.h
  • DMA_INTC_FTFIFC : gd32f10x_dma.h
  • DMA_INTC_GIFC : gd32f10x_dma.h
  • DMA_INTC_HTFIFC : gd32f10x_dma.h
  • DMA_INTEN_REG_OFFSET : gd32f10x_enet.h
  • dma_interrupt_disable() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_interrupt_enable() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_interrupt_flag_clear() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_interrupt_flag_get() : gd32f10x_dma.c , gd32f10x_dma.h
  • DMA_INTF : gd32f10x_dma.h
  • DMA_INTF_ERRIF : gd32f10x_dma.h
  • DMA_INTF_FTFIF : gd32f10x_dma.h
  • DMA_INTF_GIF : gd32f10x_dma.h
  • DMA_INTF_HTFIF : gd32f10x_dma.h
  • DMA_MAXBURST_OPTION : gd32f10x_enet.h
  • dma_memory_address_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • DMA_MEMORY_INCREASE_DISABLE : gd32f10x_dma.h
  • dma_memory_increase_disable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_memory_increase_enable() : gd32f10x_dma.h , gd32f10x_dma.c
  • DMA_MEMORY_INCREASE_ENABLE : gd32f10x_dma.h
  • dma_memory_to_memory_disable() : gd32f10x_dma.h , gd32f10x_dma.c
  • DMA_MEMORY_TO_MEMORY_DISABLE : gd32f10x_dma.h
  • dma_memory_to_memory_enable() : gd32f10x_dma.h , gd32f10x_dma.c
  • DMA_MEMORY_TO_MEMORY_ENABLE : gd32f10x_dma.h
  • DMA_MEMORY_TO_PERIPHERAL : gd32f10x_dma.h
  • DMA_MEMORY_WIDTH_16BIT : gd32f10x_dma.h
  • DMA_MEMORY_WIDTH_32BIT : gd32f10x_dma.h
  • DMA_MEMORY_WIDTH_8BIT : gd32f10x_dma.h
  • dma_memory_width_config() : gd32f10x_dma.h , gd32f10x_dma.c
  • DMA_OPTION : gd32f10x_enet.h
  • dma_periph_address_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_periph_increase_disable() : gd32f10x_dma.c
  • DMA_PERIPH_INCREASE_DISABLE : gd32f10x_dma.h
  • dma_periph_increase_disable() : gd32f10x_dma.h
  • DMA_PERIPH_INCREASE_ENABLE : gd32f10x_dma.h
  • dma_periph_increase_enable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_periph_width_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • DMA_PERIPHERAL_TO_MEMORY : gd32f10x_dma.h
  • DMA_PERIPHERAL_WIDTH_16BIT : gd32f10x_dma.h
  • DMA_PERIPHERAL_WIDTH_32BIT : gd32f10x_dma.h
  • DMA_PERIPHERAL_WIDTH_8BIT : gd32f10x_dma.h
  • dma_priority_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • DMA_PRIORITY_HIGH : gd32f10x_dma.h
  • DMA_PRIORITY_LOW : gd32f10x_dma.h
  • DMA_PRIORITY_MEDIUM : gd32f10x_dma.h
  • DMA_PRIORITY_ULTRA_HIGH : gd32f10x_dma.h
  • DMA_RDTADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_STAT_REG_OFFSET : gd32f10x_enet.h
  • DMA_TDTADDR_REG_OFFSET : gd32f10x_enet.h
  • dma_transfer_direction_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_transfer_number_config() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_transfer_number_get() : gd32f10x_dma.c , gd32f10x_dma.h
  • DMA_WRONG_HANDLE : gd32f10x_dma.c
  • DMABUS_OPTION : gd32f10x_enet.h
  • DMACFG_DMATA : gd32f10x_timer.h
  • DMACFG_DMATC : gd32f10x_timer.h
  • DOEP0LEN_PCNT : usb_regs.h
  • DOEP0LEN_STPCNT : usb_regs.h
  • DOEP0LEN_TLEN : usb_regs.h
  • DOEPINTEN_BTBSTPEN : usb_regs.h
  • DOEPINTEN_EPDISEN : usb_regs.h
  • DOEPINTEN_EPRXFOVREN : usb_regs.h
  • DOEPINTEN_STPFEN : usb_regs.h
  • DOEPINTEN_TFEN : usb_regs.h
  • DOEPINTF_BTBSTP : usb_regs.h
  • DOEPINTF_EPDIS : usb_regs.h
  • DOEPINTF_EPRXFOVR : usb_regs.h
  • DOEPINTF_STPF : usb_regs.h
  • DOEPINTF_TF : usb_regs.h
  • DOEPLEN_RXDPID : usb_regs.h
  • DOEPLEN_STPCNT : usb_regs.h
  • DP83848 : gd32f10x_enet.h
  • DPID_DATA0 : usb_defines.h
  • DPID_DATA1 : usb_defines.h
  • DPID_DATA2 : usb_defines.h
  • DPID_MDATA : usb_defines.h
  • DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ : usb_defines.h
  • DSTAT_ENUMSPD_FS_PHY_48MHZ : usb_defines.h
  • DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ : usb_defines.h
  • DSTAT_ENUMSPD_LS_PHY_6MHZ : usb_defines.h
  • DSTAT_ES : usb_regs.h
  • DSTAT_FNRSOF : usb_regs.h
  • DSTAT_SPST : usb_regs.h
  • DSV_DSLPVS : gd32f10x_rcu.h
  • DVBUSDT_DVBUSDT : usb_regs.h
  • DVBUSPT_DVBUSPT : usb_regs.h
  • DWBW : gd32f10x_dac.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • ENDP_BUF_ADDR : usbd_core.h
  • ENDP_BULK : usbd_core.h
  • ENDP_CONTROL : usbd_core.h
  • ENDP_DBL_BUF : usbd_core.h
  • ENDP_INT : usbd_core.h
  • ENDP_ISOC : usbd_core.h
  • ENDP_RXSTAT : usbd_regs.h
  • ENDP_SNG_BUF : usbd_core.h
  • ENDP_TXSTAT : usbd_regs.h
  • ENDP_TYPE : usbd_regs.h
  • ENET : gd32f10x_enet.h
  • ENET_100M_FULLDUPLEX : gd32f10x_enet.h
  • ENET_100M_HALFDUPLEX : gd32f10x_enet.h
  • ENET_10M_FULLDUPLEX : gd32f10x_enet.h
  • ENET_10M_HALFDUPLEX : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_1024BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_1280BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_1536BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_1792BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_256BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_512BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_768BYTES : gd32f10x_enet.h
  • ENET_ADDRESS_ALIGN_DISABLE : gd32f10x_enet.h
  • ENET_ADDRESS_ALIGN_ENABLE : gd32f10x_enet.h
  • enet_address_filter_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_ADDRESS_FILTER_DA : gd32f10x_enet.h
  • enet_address_filter_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_address_filter_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_ADDRESS_FILTER_SA : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE0 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE1 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE2 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE3 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE4 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE5 : gd32f10x_enet.h
  • ENET_ADDRH_BASE : gd32f10x_enet.h
  • ENET_ADDRL_BASE : gd32f10x_enet.h
  • ENET_ARBITRATION_RXPRIORTX : gd32f10x_enet.h
  • ENET_ARBITRATION_RXTX_1_1 : gd32f10x_enet.h
  • ENET_ARBITRATION_RXTX_2_1 : gd32f10x_enet.h
  • ENET_ARBITRATION_RXTX_3_1 : gd32f10x_enet.h
  • ENET_ARBITRATION_RXTX_4_1 : gd32f10x_enet.h
  • ENET_AUTO_NEGOTIATION : gd32f10x_enet.h
  • ENET_AUTO_PADCRC_DROP : gd32f10x_enet.h
  • ENET_AUTO_PADCRC_DROP_DISABLE : gd32f10x_enet.h
  • ENET_AUTO_PADCRC_DROP_ENABLE : gd32f10x_enet.h
  • ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES : gd32f10x_enet.h
  • ENET_AUTOCHECKSUM_DROP_FAILFRAMES : gd32f10x_enet.h
  • ENET_BACK_PRESSURE : gd32f10x_enet.h
  • ENET_BACK_PRESSURE_DISABLE : gd32f10x_enet.h
  • ENET_BACK_PRESSURE_ENABLE : gd32f10x_enet.h
  • ENET_BACKOFFLIMIT_1 : gd32f10x_enet.h
  • ENET_BACKOFFLIMIT_10 : gd32f10x_enet.h
  • ENET_BACKOFFLIMIT_4 : gd32f10x_enet.h
  • ENET_BACKOFFLIMIT_8 : gd32f10x_enet.h
  • ENET_BIT_POS : gd32f10x_enet.h
  • ENET_BROADCAST_FRAMES_DROP : gd32f10x_enet.h
  • ENET_BROADCAST_FRAMES_PASS : gd32f10x_enet.h
  • ENET_BROADCASTFRAMES_DISABLE : gd32f10x_enet.h
  • ENET_BROADCASTFRAMES_ENABLE : gd32f10x_enet.h
  • ENET_CARRIERSENSE_DISABLE : gd32f10x_enet.h
  • ENET_CARRIERSENSE_ENABLE : gd32f10x_enet.h
  • ENET_CHECKSUM_DISABLE : gd32f10x_enet.h
  • ENET_CHECKSUM_IPV4HEADER : gd32f10x_enet.h
  • ENET_CHECKSUM_TCPUDPICMP_FULL : gd32f10x_enet.h
  • ENET_CHECKSUM_TCPUDPICMP_SEGMENT : gd32f10x_enet.h
  • ENET_CHECKSUMOFFLOAD_DISABLE : gd32f10x_enet.h
  • ENET_CHECKSUMOFFLOAD_ENABLE : gd32f10x_enet.h
  • enet_chksumconf_enum : gd32f10x_enet.h
  • enet_current_desc_address_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_DEACTIVE_THRESHOLD_1024BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_1280BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_1536BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_1792BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_256BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_512BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_768BYTES : gd32f10x_enet.h
  • enet_debug_status_get() : gd32f10x_enet.h
  • ENET_DEFERRALCHECK_DISABLE : gd32f10x_enet.h
  • ENET_DEFERRALCHECK_ENABLE : gd32f10x_enet.h
  • enet_deinit() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_DELAY_TO : gd32f10x_enet.h
  • enet_desc_flag_clear() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_desc_flag_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_desc_flag_set() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_desc_information_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_desc_reg_enum : gd32f10x_enet.h
  • enet_descriptors_chain_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_descriptors_ring_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_descstate_enum : gd32f10x_enet.h
  • ENET_DEST_FILTER_INVERSE : gd32f10x_enet.h
  • ENET_DEST_FILTER_INVERSE_DISABLE : gd32f10x_enet.h
  • ENET_DEST_FILTER_INVERSE_ENABLE : gd32f10x_enet.h
  • enet_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_DMA_BCTL : gd32f10x_enet.h
  • ENET_DMA_BCTL_AA : gd32f10x_enet.h
  • ENET_DMA_BCTL_DAB : gd32f10x_enet.h
  • ENET_DMA_BCTL_DPSL : gd32f10x_enet.h
  • ENET_DMA_BCTL_FB : gd32f10x_enet.h
  • ENET_DMA_BCTL_FPBL : gd32f10x_enet.h
  • ENET_DMA_BCTL_PGBL : gd32f10x_enet.h
  • ENET_DMA_BCTL_RTPR : gd32f10x_enet.h
  • ENET_DMA_BCTL_RXDP : gd32f10x_enet.h
  • ENET_DMA_BCTL_SWR : gd32f10x_enet.h
  • ENET_DMA_BCTL_UIP : gd32f10x_enet.h
  • ENET_DMA_CRBADDR : gd32f10x_enet.h
  • ENET_DMA_CRBADDR_RBAP : gd32f10x_enet.h
  • ENET_DMA_CRDADDR : gd32f10x_enet.h
  • ENET_DMA_CRDADDR_RDAP : gd32f10x_enet.h
  • ENET_DMA_CTBADDR : gd32f10x_enet.h
  • ENET_DMA_CTBADDR_TBAP : gd32f10x_enet.h
  • ENET_DMA_CTDADDR : gd32f10x_enet.h
  • ENET_DMA_CTDADDR_TDAP : gd32f10x_enet.h
  • ENET_DMA_CTL : gd32f10x_enet.h
  • ENET_DMA_CTL_DAFRF : gd32f10x_enet.h
  • ENET_DMA_CTL_DTCERFD : gd32f10x_enet.h
  • ENET_DMA_CTL_FERF : gd32f10x_enet.h
  • ENET_DMA_CTL_FTF : gd32f10x_enet.h
  • ENET_DMA_CTL_FUF : gd32f10x_enet.h
  • ENET_DMA_CTL_OSF : gd32f10x_enet.h
  • ENET_DMA_CTL_RSFD : gd32f10x_enet.h
  • ENET_DMA_CTL_RTHC : gd32f10x_enet.h
  • ENET_DMA_CTL_SRE : gd32f10x_enet.h
  • ENET_DMA_CTL_STE : gd32f10x_enet.h
  • ENET_DMA_CTL_TSFD : gd32f10x_enet.h
  • ENET_DMA_CTL_TTHC : gd32f10x_enet.h
  • enet_dma_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_dma_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_DMA_FLAG_AI : gd32f10x_enet.h
  • ENET_DMA_FLAG_AI_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_EB_ACCESS_ERROR : gd32f10x_enet.h
  • ENET_DMA_FLAG_EB_DMA_ERROR : gd32f10x_enet.h
  • ENET_DMA_FLAG_EB_TRANSFER_ERROR : gd32f10x_enet.h
  • ENET_DMA_FLAG_ER : gd32f10x_enet.h
  • ENET_DMA_FLAG_ER_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_ET : gd32f10x_enet.h
  • ENET_DMA_FLAG_ET_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_FBE : gd32f10x_enet.h
  • ENET_DMA_FLAG_FBE_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_MSC : gd32f10x_enet.h
  • ENET_DMA_FLAG_NI : gd32f10x_enet.h
  • ENET_DMA_FLAG_NI_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RBU : gd32f10x_enet.h
  • ENET_DMA_FLAG_RBU_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RO : gd32f10x_enet.h
  • ENET_DMA_FLAG_RO_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RPS : gd32f10x_enet.h
  • ENET_DMA_FLAG_RPS_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RS : gd32f10x_enet.h
  • ENET_DMA_FLAG_RS_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RWT : gd32f10x_enet.h
  • ENET_DMA_FLAG_RWT_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TBU : gd32f10x_enet.h
  • ENET_DMA_FLAG_TBU_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TJT : gd32f10x_enet.h
  • ENET_DMA_FLAG_TJT_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TPS : gd32f10x_enet.h
  • ENET_DMA_FLAG_TPS_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TS : gd32f10x_enet.h
  • ENET_DMA_FLAG_TS_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TST : gd32f10x_enet.h
  • ENET_DMA_FLAG_TU : gd32f10x_enet.h
  • ENET_DMA_FLAG_TU_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_WUM : gd32f10x_enet.h
  • ENET_DMA_INT_AIE : gd32f10x_enet.h
  • ENET_DMA_INT_ERIE : gd32f10x_enet.h
  • ENET_DMA_INT_ETIE : gd32f10x_enet.h
  • ENET_DMA_INT_FBEIE : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_AI : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_AI_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_ER : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_ER_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_ET : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_ET_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_FBE : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_FBE_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_MSC : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_NI : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_NI_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RBU : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RBU_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RO : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RO_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RPS : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RPS_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RS : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RS_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RWT : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RWT_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TBU : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TBU_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TJT : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TJT_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TPS : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TPS_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TS : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TS_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TST : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TU : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TU_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_WUM : gd32f10x_enet.h
  • ENET_DMA_INT_NIE : gd32f10x_enet.h
  • ENET_DMA_INT_RBUIE : gd32f10x_enet.h
  • ENET_DMA_INT_RIE : gd32f10x_enet.h
  • ENET_DMA_INT_ROIE : gd32f10x_enet.h
  • ENET_DMA_INT_RPSIE : gd32f10x_enet.h
  • ENET_DMA_INT_RWTIE : gd32f10x_enet.h
  • ENET_DMA_INT_TBUIE : gd32f10x_enet.h
  • ENET_DMA_INT_TIE : gd32f10x_enet.h
  • ENET_DMA_INT_TJTIE : gd32f10x_enet.h
  • ENET_DMA_INT_TPSIE : gd32f10x_enet.h
  • ENET_DMA_INT_TUIE : gd32f10x_enet.h
  • ENET_DMA_INTEN : gd32f10x_enet.h
  • ENET_DMA_INTEN_AIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_ERIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_ETIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_FBEIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_NIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_RBUIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_RIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_ROIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_RPSIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_RWTIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TBUIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TJTIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TPSIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TUIE : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT_MSFA : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT_MSFC : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT_OBFOC : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT_OBMFC : gd32f10x_enet.h
  • ENET_DMA_RDTADDR : gd32f10x_enet.h
  • ENET_DMA_RDTADDR_SRT : gd32f10x_enet.h
  • ENET_DMA_RPEN : gd32f10x_enet.h
  • ENET_DMA_RPEN_RPE : gd32f10x_enet.h
  • ENET_DMA_RX : gd32f10x_enet.h
  • ENET_DMA_STAT : gd32f10x_enet.h
  • ENET_DMA_STAT_AI : gd32f10x_enet.h
  • ENET_DMA_STAT_EB : gd32f10x_enet.h
  • ENET_DMA_STAT_ER : gd32f10x_enet.h
  • ENET_DMA_STAT_ET : gd32f10x_enet.h
  • ENET_DMA_STAT_FBE : gd32f10x_enet.h
  • ENET_DMA_STAT_MSC : gd32f10x_enet.h
  • ENET_DMA_STAT_NI : gd32f10x_enet.h
  • ENET_DMA_STAT_RBU : gd32f10x_enet.h
  • ENET_DMA_STAT_RO : gd32f10x_enet.h
  • ENET_DMA_STAT_RP : gd32f10x_enet.h
  • ENET_DMA_STAT_RPS : gd32f10x_enet.h
  • ENET_DMA_STAT_RS : gd32f10x_enet.h
  • ENET_DMA_STAT_RWT : gd32f10x_enet.h
  • ENET_DMA_STAT_TBU : gd32f10x_enet.h
  • ENET_DMA_STAT_TJT : gd32f10x_enet.h
  • ENET_DMA_STAT_TP : gd32f10x_enet.h
  • ENET_DMA_STAT_TPS : gd32f10x_enet.h
  • ENET_DMA_STAT_TS : gd32f10x_enet.h
  • ENET_DMA_STAT_TST : gd32f10x_enet.h
  • ENET_DMA_STAT_TU : gd32f10x_enet.h
  • ENET_DMA_STAT_WUM : gd32f10x_enet.h
  • ENET_DMA_TDTADDR : gd32f10x_enet.h
  • ENET_DMA_TDTADDR_STT : gd32f10x_enet.h
  • ENET_DMA_TPEN : gd32f10x_enet.h
  • ENET_DMA_TPEN_TPE : gd32f10x_enet.h
  • ENET_DMA_TX : gd32f10x_enet.h
  • enet_dmadirection_enum : gd32f10x_enet.h
  • enet_dmaprocess_resume() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_dmaprocess_state_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_ERROR_DESC_ACCESS : gd32f10x_enet.h
  • ENET_ERROR_READ_TRANSFER : gd32f10x_enet.h
  • ENET_ERROR_TXDATA_TRANSFER : gd32f10x_enet.h
  • ENET_FILTER_MODE_EITHER : gd32f10x_enet.h
  • ENET_FIXED_BURST_DISABLE : gd32f10x_enet.h
  • ENET_FIXED_BURST_ENABLE : gd32f10x_enet.h
  • enet_flag_clear() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_flag_clear_enum : gd32f10x_enet.h
  • enet_flag_enum : gd32f10x_enet.h
  • enet_flag_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_fliter_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_fliter_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_flowcontrol_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_flowcontrol_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_flowcontrol_threshold_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_FLUSH_RXFRAME_DISABLE : gd32f10x_enet.h
  • ENET_FLUSH_RXFRAME_ENABLE : gd32f10x_enet.h
  • ENET_FORWARD_ERRFRAMES : gd32f10x_enet.h
  • ENET_FORWARD_ERRFRAMES_DISABLE : gd32f10x_enet.h
  • ENET_FORWARD_ERRFRAMES_ENABLE : gd32f10x_enet.h
  • enet_forward_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_forward_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_FORWARD_UNDERSZ_GOODFRAMES : gd32f10x_enet.h
  • ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE : gd32f10x_enet.h
  • ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE : gd32f10x_enet.h
  • enet_frame_receive() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_frame_transmit() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_frmrecept_enum : gd32f10x_enet.h
  • ENET_GET_MACADDR : gd32f10x_enet.h
  • enet_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_initpara_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_initpara_reset() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_int_enum : gd32f10x_enet.h
  • enet_int_flag_clear_enum : gd32f10x_enet.h
  • enet_int_flag_enum : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_40BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_48BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_56BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_64BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_72BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_80BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_88BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_96BIT : gd32f10x_enet.h
  • enet_interrupt_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_interrupt_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_interrupt_flag_clear() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_interrupt_flag_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_JABBER_DISABLE : gd32f10x_enet.h
  • ENET_JABBER_ENABLE : gd32f10x_enet.h
  • ENET_LOOPBACKMODE : gd32f10x_enet.h
  • ENET_LOOPBACKMODE_DISABLE : gd32f10x_enet.h
  • ENET_LOOPBACKMODE_ENABLE : gd32f10x_enet.h
  • ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT : gd32f10x_enet.h
  • ENET_MAC_ADDR0H : gd32f10x_enet.h
  • ENET_MAC_ADDR0H_ADDR0H : gd32f10x_enet.h
  • ENET_MAC_ADDR0H_MO : gd32f10x_enet.h
  • ENET_MAC_ADDR0L : gd32f10x_enet.h
  • ENET_MAC_ADDR0L_ADDR0L : gd32f10x_enet.h
  • ENET_MAC_ADDR1H : gd32f10x_enet.h
  • ENET_MAC_ADDR1H_ADDR1H : gd32f10x_enet.h
  • ENET_MAC_ADDR1H_AFE : gd32f10x_enet.h
  • ENET_MAC_ADDR1H_MB : gd32f10x_enet.h
  • ENET_MAC_ADDR1H_SAF : gd32f10x_enet.h
  • ENET_MAC_ADDR1L : gd32f10x_enet.h
  • ENET_MAC_ADDR1L_ADDR1L : gd32f10x_enet.h
  • ENET_MAC_ADDR2H_ADDR2H : gd32f10x_enet.h
  • ENET_MAC_ADDR2H_AFE : gd32f10x_enet.h
  • ENET_MAC_ADDR2H_MB : gd32f10x_enet.h
  • ENET_MAC_ADDR2H_SAF : gd32f10x_enet.h
  • ENET_MAC_ADDR2L : gd32f10x_enet.h
  • ENET_MAC_ADDR2L_ADDR2L : gd32f10x_enet.h
  • ENET_MAC_ADDR3H : gd32f10x_enet.h
  • ENET_MAC_ADDR3H_ADDR3H : gd32f10x_enet.h
  • ENET_MAC_ADDR3H_AFE : gd32f10x_enet.h
  • ENET_MAC_ADDR3H_MB : gd32f10x_enet.h
  • ENET_MAC_ADDR3H_SAF : gd32f10x_enet.h
  • ENET_MAC_ADDR3L : gd32f10x_enet.h
  • ENET_MAC_ADDR3L_ADDR3L : gd32f10x_enet.h
  • ENET_MAC_ADDRESS0 : gd32f10x_enet.h
  • ENET_MAC_ADDRESS1 : gd32f10x_enet.h
  • ENET_MAC_ADDRESS2 : gd32f10x_enet.h
  • ENET_MAC_ADDRESS3 : gd32f10x_enet.h
  • enet_mac_address_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_mac_address_set() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_MAC_ADDT2H : gd32f10x_enet.h
  • ENET_MAC_CFG : gd32f10x_enet.h
  • ENET_MAC_CFG_APCD : gd32f10x_enet.h
  • ENET_MAC_CFG_BOL : gd32f10x_enet.h
  • ENET_MAC_CFG_CSD : gd32f10x_enet.h
  • ENET_MAC_CFG_DFC : gd32f10x_enet.h
  • ENET_MAC_CFG_DPM : gd32f10x_enet.h
  • ENET_MAC_CFG_IGBS : gd32f10x_enet.h
  • ENET_MAC_CFG_IPFCO : gd32f10x_enet.h
  • ENET_MAC_CFG_JBD : gd32f10x_enet.h
  • ENET_MAC_CFG_LBM : gd32f10x_enet.h
  • ENET_MAC_CFG_REN : gd32f10x_enet.h
  • ENET_MAC_CFG_ROD : gd32f10x_enet.h
  • ENET_MAC_CFG_RTD : gd32f10x_enet.h
  • ENET_MAC_CFG_SPD : gd32f10x_enet.h
  • ENET_MAC_CFG_TEN : gd32f10x_enet.h
  • ENET_MAC_CFG_WDD : gd32f10x_enet.h
  • ENET_MAC_FCTH : gd32f10x_enet.h
  • ENET_MAC_FCTH_RFA : gd32f10x_enet.h
  • ENET_MAC_FCTH_RFD : gd32f10x_enet.h
  • ENET_MAC_FCTL : gd32f10x_enet.h
  • ENET_MAC_FCTL_DZQP : gd32f10x_enet.h
  • ENET_MAC_FCTL_FLCBBKPA : gd32f10x_enet.h
  • ENET_MAC_FCTL_PLTS : gd32f10x_enet.h
  • ENET_MAC_FCTL_PTM : gd32f10x_enet.h
  • ENET_MAC_FCTL_RFCEN : gd32f10x_enet.h
  • ENET_MAC_FCTL_TFCEN : gd32f10x_enet.h
  • ENET_MAC_FCTL_UPFDT : gd32f10x_enet.h
  • ENET_MAC_FLAG_FLOWCONTROL : gd32f10x_enet.h
  • ENET_MAC_FLAG_MPKR : gd32f10x_enet.h
  • ENET_MAC_FLAG_MSC : gd32f10x_enet.h
  • ENET_MAC_FLAG_MSCR : gd32f10x_enet.h
  • ENET_MAC_FLAG_MSCT : gd32f10x_enet.h
  • ENET_MAC_FLAG_TMST : gd32f10x_enet.h
  • ENET_MAC_FLAG_WUFR : gd32f10x_enet.h
  • ENET_MAC_FLAG_WUM : gd32f10x_enet.h
  • ENET_MAC_FRMF : gd32f10x_enet.h
  • ENET_MAC_FRMF_BFRMD : gd32f10x_enet.h
  • ENET_MAC_FRMF_DAIFLT : gd32f10x_enet.h
  • ENET_MAC_FRMF_FAR : gd32f10x_enet.h
  • ENET_MAC_FRMF_HMF : gd32f10x_enet.h
  • ENET_MAC_FRMF_HPFLT : gd32f10x_enet.h
  • ENET_MAC_FRMF_HUF : gd32f10x_enet.h
  • ENET_MAC_FRMF_MFD : gd32f10x_enet.h
  • ENET_MAC_FRMF_PCFRM : gd32f10x_enet.h
  • ENET_MAC_FRMF_PM : gd32f10x_enet.h
  • ENET_MAC_FRMF_SAFLT : gd32f10x_enet.h
  • ENET_MAC_FRMF_SAIFLT : gd32f10x_enet.h
  • ENET_MAC_HLH : gd32f10x_enet.h
  • ENET_MAC_HLH_HLH : gd32f10x_enet.h
  • ENET_MAC_HLL : gd32f10x_enet.h
  • ENET_MAC_HLL_HLL : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_MSC : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_MSCR : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_MSCT : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_TMST : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_WUM : gd32f10x_enet.h
  • ENET_MAC_INT_TMSTIM : gd32f10x_enet.h
  • ENET_MAC_INT_WUMIM : gd32f10x_enet.h
  • ENET_MAC_INTF : gd32f10x_enet.h
  • ENET_MAC_INTF_MSC : gd32f10x_enet.h
  • ENET_MAC_INTF_MSCR : gd32f10x_enet.h
  • ENET_MAC_INTF_MSCT : gd32f10x_enet.h
  • ENET_MAC_INTF_TMST : gd32f10x_enet.h
  • ENET_MAC_INTF_WUM : gd32f10x_enet.h
  • ENET_MAC_INTMSK : gd32f10x_enet.h
  • ENET_MAC_INTMSK_TMSTIM : gd32f10x_enet.h
  • ENET_MAC_INTMSK_WUMIM : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_CLR : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_PA : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_PB : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_PR : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_PW : gd32f10x_enet.h
  • ENET_MAC_PHY_DATA : gd32f10x_enet.h
  • ENET_MAC_PHY_DATA_PD : gd32f10x_enet.h
  • ENET_MAC_RWFF : gd32f10x_enet.h
  • ENET_MAC_RWFF_DATA : gd32f10x_enet.h
  • ENET_MAC_VLT : gd32f10x_enet.h
  • ENET_MAC_VLT_VLTC : gd32f10x_enet.h
  • ENET_MAC_VLT_VLTI : gd32f10x_enet.h
  • ENET_MAC_WUM : gd32f10x_enet.h
  • ENET_MAC_WUM_GU : gd32f10x_enet.h
  • ENET_MAC_WUM_MPEN : gd32f10x_enet.h
  • ENET_MAC_WUM_MPKR : gd32f10x_enet.h
  • ENET_MAC_WUM_PWD : gd32f10x_enet.h
  • ENET_MAC_WUM_WFEN : gd32f10x_enet.h
  • ENET_MAC_WUM_WUFFRPR : gd32f10x_enet.h
  • ENET_MAC_WUM_WUFR : gd32f10x_enet.h
  • enet_macaddress_enum : gd32f10x_enet.h
  • ENET_MAX_FRAME_SIZE : gd32f10x_enet.h
  • ENET_MDC_HCLK_DIV16 : gd32f10x_enet.h
  • ENET_MDC_HCLK_DIV26 : gd32f10x_enet.h
  • ENET_MDC_HCLK_DIV42 : gd32f10x_enet.h
  • ENET_MDC_HCLK_DIV62 : gd32f10x_enet.h
  • enet_mediamode_enum : gd32f10x_enet.h
  • enet_missed_frame_counter_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_MODE_FULLDUPLEX : gd32f10x_enet.h
  • ENET_MODE_HALFDUPLEX : gd32f10x_enet.h
  • enet_msc_counter_enum : gd32f10x_enet.h
  • ENET_MSC_COUNTER_STOP_ROLLOVER : gd32f10x_enet.h
  • ENET_MSC_COUNTERS_FREEZE : gd32f10x_enet.h
  • enet_msc_counters_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_msc_counters_reset() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_MSC_CTL : gd32f10x_enet.h
  • ENET_MSC_CTL_CTR : gd32f10x_enet.h
  • ENET_MSC_CTL_CTSR : gd32f10x_enet.h
  • ENET_MSC_CTL_MCFZ : gd32f10x_enet.h
  • ENET_MSC_CTL_RTOR : gd32f10x_enet.h
  • enet_msc_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_msc_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_MSC_FLAG_RFAE : gd32f10x_enet.h
  • ENET_MSC_FLAG_RFCE : gd32f10x_enet.h
  • ENET_MSC_FLAG_RGUF : gd32f10x_enet.h
  • ENET_MSC_FLAG_TGF : gd32f10x_enet.h
  • ENET_MSC_FLAG_TGFMSC : gd32f10x_enet.h
  • ENET_MSC_FLAG_TGFSC : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_RFAE : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_RFCE : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_RGUF : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_TGF : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_TGFMSC : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_TGFSC : gd32f10x_enet.h
  • ENET_MSC_INT_RFAEIM : gd32f10x_enet.h
  • ENET_MSC_INT_RFCEIM : gd32f10x_enet.h
  • ENET_MSC_INT_RGUFIM : gd32f10x_enet.h
  • ENET_MSC_INT_TGFIM : gd32f10x_enet.h
  • ENET_MSC_INT_TGFMSCIM : gd32f10x_enet.h
  • ENET_MSC_INT_TGFSCIM : gd32f10x_enet.h
  • ENET_MSC_MSCCNT : gd32f10x_enet.h
  • ENET_MSC_MSCCNT_MSCC : gd32f10x_enet.h
  • ENET_MSC_RESET_ON_READ : gd32f10x_enet.h
  • ENET_MSC_RFAECNT : gd32f10x_enet.h
  • ENET_MSC_RFAECNT_RFAER : gd32f10x_enet.h
  • ENET_MSC_RFCECNT : gd32f10x_enet.h
  • ENET_MSC_RFCECNT_RFCER : gd32f10x_enet.h
  • ENET_MSC_RGUFCNT : gd32f10x_enet.h
  • ENET_MSC_RGUFCNT_RGUF : gd32f10x_enet.h
  • ENET_MSC_RINTF : gd32f10x_enet.h
  • ENET_MSC_RINTF_RFAE : gd32f10x_enet.h
  • ENET_MSC_RINTF_RFCE : gd32f10x_enet.h
  • ENET_MSC_RINTF_RGUF : gd32f10x_enet.h
  • ENET_MSC_RINTMSK : gd32f10x_enet.h
  • ENET_MSC_RINTMSK_RFAEIM : gd32f10x_enet.h
  • ENET_MSC_RINTMSK_RFCEIM : gd32f10x_enet.h
  • ENET_MSC_RINTMSK_RGUFIM : gd32f10x_enet.h
  • ENET_MSC_RX_RFAECNT : gd32f10x_enet.h
  • ENET_MSC_RX_RFCECNT : gd32f10x_enet.h
  • ENET_MSC_RX_RGUFCNT : gd32f10x_enet.h
  • ENET_MSC_SCCNT : gd32f10x_enet.h
  • ENET_MSC_SCCNT_SCC : gd32f10x_enet.h
  • ENET_MSC_TGFCNT : gd32f10x_enet.h
  • ENET_MSC_TGFCNT_TGF : gd32f10x_enet.h
  • ENET_MSC_TINTF : gd32f10x_enet.h
  • ENET_MSC_TINTF_TGF : gd32f10x_enet.h
  • ENET_MSC_TINTF_TGFMSC : gd32f10x_enet.h
  • ENET_MSC_TINTF_TGFSC : gd32f10x_enet.h
  • ENET_MSC_TINTMSK : gd32f10x_enet.h
  • ENET_MSC_TINTMSK_TGFIM : gd32f10x_enet.h
  • ENET_MSC_TINTMSK_TGFMSCIM : gd32f10x_enet.h
  • ENET_MSC_TINTMSK_TGFSCIM : gd32f10x_enet.h
  • ENET_MSC_TX_MSCCNT : gd32f10x_enet.h
  • ENET_MSC_TX_SCCNT : gd32f10x_enet.h
  • ENET_MSC_TX_TGFCNT : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_HASH : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_HASH_MODE : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_HASH_OR_PERFECT : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_NONE : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_PASS : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_PERFECT : gd32f10x_enet.h
  • ENET_NO_AUTOCHECKSUM : gd32f10x_enet.h
  • ENET_NO_FLUSH_RXFRAME : gd32f10x_enet.h
  • ENET_NOCOPY_FRAME_RECEIVE : gd32f10x_enet.h
  • ENET_NOCOPY_FRAME_TRANSMIT : gd32f10x_enet.h
  • ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE : gd32f10x_enet.h
  • ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE : gd32f10x_enet.h
  • enet_option_enum : gd32f10x_enet.h
  • enet_pauseframe_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_pauseframe_detect_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_pauseframe_generate() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_PAUSETIME_MINUS144 : gd32f10x_enet.h
  • ENET_PAUSETIME_MINUS256 : gd32f10x_enet.h
  • ENET_PAUSETIME_MINUS28 : gd32f10x_enet.h
  • ENET_PAUSETIME_MINUS4 : gd32f10x_enet.h
  • ENET_PCFRM_FORWARD_ALL : gd32f10x_enet.h
  • ENET_PCFRM_FORWARD_FILTERED : gd32f10x_enet.h
  • ENET_PCFRM_PREVENT_ALL : gd32f10x_enet.h
  • ENET_PCFRM_PREVENT_PAUSEFRAME : gd32f10x_enet.h
  • ENET_PGBL_16BEAT : gd32f10x_enet.h
  • ENET_PGBL_1BEAT : gd32f10x_enet.h
  • ENET_PGBL_2BEAT : gd32f10x_enet.h
  • ENET_PGBL_32BEAT : gd32f10x_enet.h
  • ENET_PGBL_4BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_128BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_16BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_32BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_4BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_64BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_8BEAT : gd32f10x_enet.h
  • ENET_PGBL_8BEAT : gd32f10x_enet.h
  • enet_phy_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_PHY_READ : gd32f10x_enet.h
  • ENET_PHY_WRITE : gd32f10x_enet.h
  • enet_phy_write_read() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_phydirection_enum : gd32f10x_enet.h
  • enet_phyloopback_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_phyloopback_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_PROMISCUOUS_DISABLE : gd32f10x_enet.h
  • ENET_PROMISCUOUS_ENABLE : gd32f10x_enet.h
  • ENET_PROMISCUOUS_MODE : gd32f10x_enet.h
  • ENET_PTP_ADD_TO_TIME : gd32f10x_enet.h
  • ENET_PTP_ADDEND_UPDATE : gd32f10x_enet.h
  • enet_ptp_coarsecorrection_systime_update() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_PTP_COARSEMODE : gd32f10x_enet.h
  • ENET_PTP_ETH : gd32f10x_enet.h
  • ENET_PTP_ETH_ETSH : gd32f10x_enet.h
  • ENET_PTP_ETL : gd32f10x_enet.h
  • ENET_PTP_ETL_ETSL : gd32f10x_enet.h
  • enet_ptp_expected_time_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_finecorrection_adjfreq() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_finecorrection_settime() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_PTP_FINEMODE : gd32f10x_enet.h
  • enet_ptp_flag_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_function_enum : gd32f10x_enet.h
  • enet_ptp_nanosecond_2_subsecond() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_normal_descriptors_chain_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_normal_descriptors_ring_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_pps_output_frequency_config() : gd32f10x_enet.h
  • ENET_PTP_SSINC : gd32f10x_enet.h
  • ENET_PTP_SSINC_STMSSI : gd32f10x_enet.h
  • enet_ptp_start() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_subsecond_2_nanosecond() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_subsecond_increment_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_PTP_SUBSTRACT_FROM_TIME : gd32f10x_enet.h
  • enet_ptp_system_time_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_PTP_SYSTIME_INIT : gd32f10x_enet.h
  • ENET_PTP_SYSTIME_UPDATE : gd32f10x_enet.h
  • ENET_PTP_TIME_NEGATIVE : gd32f10x_enet.h
  • ENET_PTP_TIME_POSITIVE : gd32f10x_enet.h
  • enet_ptp_timestamp_addend_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_timestamp_function_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_PTP_TIMESTAMP_INT : gd32f10x_enet.h
  • enet_ptp_timestamp_update_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_PTP_TSADDEND : gd32f10x_enet.h
  • ENET_PTP_TSADDEND_TMSA : gd32f10x_enet.h
  • ENET_PTP_TSCTL : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSARU : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSEN : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSFCU : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSITEN : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSSTI : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSSTU : gd32f10x_enet.h
  • ENET_PTP_TSH : gd32f10x_enet.h
  • ENET_PTP_TSH_STMS : gd32f10x_enet.h
  • ENET_PTP_TSL : gd32f10x_enet.h
  • ENET_PTP_TSL_STMSS : gd32f10x_enet.h
  • ENET_PTP_TSL_STS : gd32f10x_enet.h
  • ENET_PTP_TSUH : gd32f10x_enet.h
  • ENET_PTP_TSUH_TMSUS : gd32f10x_enet.h
  • ENET_PTP_TSUL : gd32f10x_enet.h
  • ENET_PTP_TSUL_TMSUPNS : gd32f10x_enet.h
  • ENET_PTP_TSUL_TMSUSS : gd32f10x_enet.h
  • enet_ptpframe_receive_normal_mode() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptpframe_transmit_normal_mode() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_RANGE : gd32f10x_enet.h
  • ENET_RDES0_CERR : gd32f10x_enet.h
  • ENET_RDES0_DAFF : gd32f10x_enet.h
  • ENET_RDES0_DAV : gd32f10x_enet.h
  • ENET_RDES0_DBERR : gd32f10x_enet.h
  • ENET_RDES0_DERR : gd32f10x_enet.h
  • ENET_RDES0_ERRS : gd32f10x_enet.h
  • ENET_RDES0_FDES : gd32f10x_enet.h
  • ENET_RDES0_FRML : gd32f10x_enet.h
  • ENET_RDES0_FRMT : gd32f10x_enet.h
  • ENET_RDES0_IPHERR : gd32f10x_enet.h
  • ENET_RDES0_LCO : gd32f10x_enet.h
  • ENET_RDES0_LDES : gd32f10x_enet.h
  • ENET_RDES0_LERR : gd32f10x_enet.h
  • ENET_RDES0_OERR : gd32f10x_enet.h
  • ENET_RDES0_PCERR : gd32f10x_enet.h
  • ENET_RDES0_RERR : gd32f10x_enet.h
  • ENET_RDES0_RWDT : gd32f10x_enet.h
  • ENET_RDES0_SAFF : gd32f10x_enet.h
  • ENET_RDES0_VTAG : gd32f10x_enet.h
  • ENET_RDES1_DINTC : gd32f10x_enet.h
  • ENET_RDES1_RB1S : gd32f10x_enet.h
  • ENET_RDES1_RB2S : gd32f10x_enet.h
  • ENET_RDES1_RCHM : gd32f10x_enet.h
  • ENET_RDES1_RERM : gd32f10x_enet.h
  • ENET_RDES2_RB1AP : gd32f10x_enet.h
  • ENET_RDES3_RB2AP : gd32f10x_enet.h
  • ENET_RECEIVE_COMPLETE_INT_DISABLE : gd32f10x_enet.h
  • ENET_RECEIVE_COMPLETE_INT_ENABLE : gd32f10x_enet.h
  • ENET_RECEIVEALL : gd32f10x_enet.h
  • ENET_RECEIVEOWN_DISABLE : gd32f10x_enet.h
  • ENET_RECEIVEOWN_ENABLE : gd32f10x_enet.h
  • ENET_REG_READ : gd32f10x_enet.h
  • ENET_REG_VAL : gd32f10x_enet.h
  • ENET_REG_WRITE : gd32f10x_enet.h
  • enet_regdirection_enum : gd32f10x_enet.h
  • ENET_REGIDX_BIT : gd32f10x_enet.h
  • enet_registers_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_registers_type_enum : gd32f10x_enet.h
  • ENET_RESET_TO : gd32f10x_enet.h
  • ENET_RETRYTRANSMISSION_DISABLE : gd32f10x_enet.h
  • ENET_RETRYTRANSMISSION_ENABLE : gd32f10x_enet.h
  • ENET_RX_CURRENT_BUFFER : gd32f10x_enet.h
  • ENET_RX_CURRENT_DESC : gd32f10x_enet.h
  • enet_rx_desc_delay_receive_complete_interrupt() : gd32f10x_enet.h
  • enet_rx_desc_immediate_receive_complete_interrupt() : gd32f10x_enet.c , gd32f10x_enet.h
  • ENET_RX_DESC_TABLE : gd32f10x_enet.h
  • enet_rx_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_rx_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_RX_FILTER_DISABLE : gd32f10x_enet.h
  • ENET_RX_FILTER_ENABLE : gd32f10x_enet.h
  • ENET_RX_FLOWCONTROL : gd32f10x_enet.h
  • ENET_RX_FLOWCONTROL_DISABLE : gd32f10x_enet.h
  • ENET_RX_FLOWCONTROL_ENABLE : gd32f10x_enet.h
  • ENET_RX_MODE_CUTTHROUGH : gd32f10x_enet.h
  • ENET_RX_MODE_STOREFORWARD : gd32f10x_enet.h
  • ENET_RX_STATE_CLOSING : gd32f10x_enet.h
  • ENET_RX_STATE_FETCHING : gd32f10x_enet.h
  • ENET_RX_STATE_QUEUING : gd32f10x_enet.h
  • ENET_RX_STATE_STOPPED : gd32f10x_enet.h
  • ENET_RX_STATE_SUSPENDED : gd32f10x_enet.h
  • ENET_RX_STATE_WAITING : gd32f10x_enet.h
  • ENET_RX_THRESHOLD_128BYTES : gd32f10x_enet.h
  • ENET_RX_THRESHOLD_32BYTES : gd32f10x_enet.h
  • ENET_RX_THRESHOLD_64BYTES : gd32f10x_enet.h
  • ENET_RX_THRESHOLD_96BYTES : gd32f10x_enet.h
  • ENET_RXBUF_NUM : gd32f10x_enet.h
  • ENET_RXBUF_SIZE : gd32f10x_enet.h
  • ENET_RXDP_16BEAT : gd32f10x_enet.h
  • ENET_RXDP_1BEAT : gd32f10x_enet.h
  • ENET_RXDP_2BEAT : gd32f10x_enet.h
  • ENET_RXDP_32BEAT : gd32f10x_enet.h
  • ENET_RXDP_4BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_128BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_16BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_32BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_4BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_64BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_8BEAT : gd32f10x_enet.h
  • ENET_RXDP_8BEAT : gd32f10x_enet.h
  • enet_rxframe_drop() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_rxframe_size_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_rxprocess_check_recovery() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_RXTX_DIFFERENT_PGBL : gd32f10x_enet.h
  • ENET_RXTX_SAME_PGBL : gd32f10x_enet.h
  • ENET_RXTX_TIMESTAMP : gd32f10x_enet.h
  • ENET_SECONDFRAME_OPT : gd32f10x_enet.h
  • ENET_SECONDFRAME_OPT_DISABLE : gd32f10x_enet.h
  • ENET_SECONDFRAME_OPT_ENABLE : gd32f10x_enet.h
  • ENET_SET_MACADDRH : gd32f10x_enet.h
  • ENET_SET_MACADDRL : gd32f10x_enet.h
  • enet_software_reset() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_SPEEDMODE_100M : gd32f10x_enet.h
  • ENET_SPEEDMODE_10M : gd32f10x_enet.h
  • ENET_SRC_FILTER : gd32f10x_enet.h
  • ENET_SRC_FILTER_DISABLE : gd32f10x_enet.h
  • ENET_SRC_FILTER_INVERSE : gd32f10x_enet.h
  • ENET_SRC_FILTER_INVERSE_ENABLE : gd32f10x_enet.h
  • ENET_SRC_FILTER_NORMAL_ENABLE : gd32f10x_enet.h
  • ENET_TCPIP_CKSUMERROR_ACCEPT : gd32f10x_enet.h
  • ENET_TCPIP_CKSUMERROR_DROP : gd32f10x_enet.h
  • ENET_TDES0_CM : gd32f10x_enet.h
  • ENET_TDES0_COCNT : gd32f10x_enet.h
  • ENET_TDES0_DAV : gd32f10x_enet.h
  • ENET_TDES0_DB : gd32f10x_enet.h
  • ENET_TDES0_DCRC : gd32f10x_enet.h
  • ENET_TDES0_DPAD : gd32f10x_enet.h
  • ENET_TDES0_ECO : gd32f10x_enet.h
  • ENET_TDES0_ES : gd32f10x_enet.h
  • ENET_TDES0_EXD : gd32f10x_enet.h
  • ENET_TDES0_FRMF : gd32f10x_enet.h
  • ENET_TDES0_FSG : gd32f10x_enet.h
  • ENET_TDES0_INTC : gd32f10x_enet.h
  • ENET_TDES0_IPHE : gd32f10x_enet.h
  • ENET_TDES0_IPPE : gd32f10x_enet.h
  • ENET_TDES0_JT : gd32f10x_enet.h
  • ENET_TDES0_LCA : gd32f10x_enet.h
  • ENET_TDES0_LCO : gd32f10x_enet.h
  • ENET_TDES0_LSG : gd32f10x_enet.h
  • ENET_TDES0_NCA : gd32f10x_enet.h
  • ENET_TDES0_TCHM : gd32f10x_enet.h
  • ENET_TDES0_TERM : gd32f10x_enet.h
  • ENET_TDES0_TTMSS : gd32f10x_enet.h
  • ENET_TDES0_TTSEN : gd32f10x_enet.h
  • ENET_TDES0_UFE : gd32f10x_enet.h
  • ENET_TDES0_VFRM : gd32f10x_enet.h
  • ENET_TDES1_TB1S : gd32f10x_enet.h
  • ENET_TDES1_TB2S : gd32f10x_enet.h
  • ENET_TDES2_TB1AP : gd32f10x_enet.h
  • ENET_TDES3_TB2AP : gd32f10x_enet.h
  • enet_transmit_checksum_config() : gd32f10x_enet.c , gd32f10x_enet.h
  • ENET_TX_CURRENT_BUFFER : gd32f10x_enet.h
  • ENET_TX_CURRENT_DESC : gd32f10x_enet.h
  • ENET_TX_DESC_TABLE : gd32f10x_enet.h
  • enet_tx_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_tx_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_TX_FLOWCONTROL : gd32f10x_enet.h
  • ENET_TX_FLOWCONTROL_DISABLE : gd32f10x_enet.h
  • ENET_TX_FLOWCONTROL_ENABLE : gd32f10x_enet.h
  • ENET_TX_MODE_CUTTHROUGH : gd32f10x_enet.h
  • ENET_TX_MODE_STOREFORWARD : gd32f10x_enet.h
  • ENET_TX_STATE_CLOSING : gd32f10x_enet.h
  • ENET_TX_STATE_FETCHING : gd32f10x_enet.h
  • ENET_TX_STATE_READING : gd32f10x_enet.h
  • ENET_TX_STATE_STOPPED : gd32f10x_enet.h
  • ENET_TX_STATE_SUSPENDED : gd32f10x_enet.h
  • ENET_TX_STATE_WAITING : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_128BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_16BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_192BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_24BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_256BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_32BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_40BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_64BYTES : gd32f10x_enet.h
  • ENET_TXBUF_NUM : gd32f10x_enet.h
  • ENET_TXBUF_SIZE : gd32f10x_enet.h
  • enet_txfifo_flush() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_UNICAST_FILTER_EITHER : gd32f10x_enet.h
  • ENET_UNICAST_FILTER_HASH : gd32f10x_enet.h
  • ENET_UNICAST_FILTER_HASH_MODE : gd32f10x_enet.h
  • ENET_UNICAST_FILTER_PERFECT : gd32f10x_enet.h
  • ENET_UNIQUE_PAUSEDETECT : gd32f10x_enet.h
  • ENET_VLANTAGCOMPARISON_12BIT : gd32f10x_enet.h
  • ENET_VLANTAGCOMPARISON_16BIT : gd32f10x_enet.h
  • ENET_WATCHDOG_DISABLE : gd32f10x_enet.h
  • ENET_WATCHDOG_ENABLE : gd32f10x_enet.h
  • enet_wum_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_wum_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_wum_filter_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_wum_filter_register_pointer_reset() : gd32f10x_enet.h , gd32f10x_enet.c
  • ENET_WUM_FLAG_MPKR : gd32f10x_enet.h
  • ENET_WUM_FLAG_WUFFRPR : gd32f10x_enet.h
  • ENET_WUM_FLAG_WUFR : gd32f10x_enet.h
  • ENET_WUM_GLOBAL_UNICAST : gd32f10x_enet.h
  • ENET_WUM_MAGIC_PACKET_FRAME : gd32f10x_enet.h
  • ENET_WUM_POWER_DOWN : gd32f10x_enet.h
  • ENET_WUM_WAKE_UP_FRAME : gd32f10x_enet.h
  • ENET_ZERO_QUANTA_PAUSE : gd32f10x_enet.h
  • ENET_ZERO_QUANTA_PAUSE_DISABLE : gd32f10x_enet.h
  • ENET_ZERO_QUANTA_PAUSE_ENABLE : gd32f10x_enet.h
  • ENG_LANGID : usbd_std.h
  • ENUM_DEV_CONFIGURED : usbh_core.h
  • enum_event_enum : usbh_std.h
  • ENUM_EVENT_SET_ADDR : usbh_std.h
  • ENUM_FSM_ID : usbh_core.h
  • ENUM_GET_CFG_DESC : usbh_core.h
  • ENUM_GET_FULL_CFG_DESC : usbh_core.h
  • ENUM_GET_FULL_DEV_DESC : usbh_core.h
  • ENUM_GET_MFC_STRING_DESC : usbh_core.h
  • ENUM_GET_PRODUCT_STRING_DESC : usbh_core.h
  • ENUM_GET_SERIALNUM_STRING_DESC : usbh_core.h
  • enum_handle_table : usbh_std.h , usbh_std.c
  • ENUM_HANDLE_TABLE_SIZE : usbh_std.h
  • ENUM_IDLE : usbh_core.h
  • enum_polling_handle_flag : usbh_std.h , usbh_std.c
  • ENUM_SET_ADDR : usbh_core.h
  • ENUM_SET_CONFIGURATION : usbh_core.h
  • enum_state_enum : usbh_core.h
  • enum_state_handle : usbh_std.c
  • enum_state_polling_fun() : usbh_std.c , usbh_std.h
  • ENUN_EVENT_DEV_CONFIGURED : usbh_std.h
  • ENUN_EVENT_GET_CFG_DESC : usbh_std.h
  • ENUN_EVENT_GET_FULL_CFG_DESC : usbh_std.h
  • ENUN_EVENT_GET_FULL_DEV_DESC : usbh_std.h
  • ENUN_EVENT_GET_MFC_STRING_DESC : usbh_std.h
  • ENUN_EVENT_GET_PRODUCT_STRING_DESC : usbh_std.h
  • ENUN_EVENT_GET_SERIALNUM_STRING_DESC : usbh_std.h
  • ENUN_EVENT_IDLE : usbh_std.h
  • ENUN_EVENT_SET_CONFIGURATION : usbh_std.h
  • EP0 : usbd_regs.h
  • EP0_IN : usb_regs.h , usbd_regs.h
  • EP0_OUT : usbd_regs.h , usb_regs.h
  • EP0MPL_16 : usb_regs.h
  • EP0MPL_32 : usb_regs.h
  • EP0MPL_64 : usb_regs.h
  • EP0MPL_8 : usb_regs.h
  • EP1 : usbd_regs.h
  • EP1_IN : usbd_regs.h , usb_regs.h
  • EP1_OUT : usbd_regs.h , usb_regs.h
  • EP2 : usbd_regs.h
  • EP2_IN : usbd_regs.h , usb_regs.h
  • EP2_OUT : usb_regs.h , usbd_regs.h
  • EP3 : usbd_regs.h
  • EP3_IN : usbd_regs.h , usb_regs.h
  • EP3_OUT : usbd_regs.h , usb_regs.h
  • EP4 : usbd_regs.h
  • EP4_IN : usbd_regs.h
  • EP4_OUT : usbd_regs.h
  • EP5 : usbd_regs.h
  • EP5_IN : usbd_regs.h
  • EP5_OUT : usbd_regs.h
  • EP6 : usbd_regs.h
  • EP6_IN : usbd_regs.h
  • EP6_OUT : usbd_regs.h
  • EP7 : usbd_regs.h
  • EP7_IN : usbd_regs.h
  • EP7_OUT : usbd_regs.h
  • EP_BULK : usbd_regs.h
  • EP_CONTROL : usbd_regs.h
  • EP_CTL_MASK : usbd_regs.h
  • EP_INTERRUPT : usbd_regs.h
  • EP_ISO : usbd_regs.h
  • EPCS_MASK : usbd_regs.h
  • EPKCTL_MASK : usbd_regs.h
  • EPRCNT_BLKNUM : usbd_regs.h
  • EPRCNT_BLKSIZ : usbd_regs.h
  • EPRCNT_CNT : usbd_regs.h
  • EPRX_DISABLED : usbd_regs.h
  • EPRX_DTGMASK : usbd_regs.h
  • EPRX_NAK : usbd_regs.h
  • EPRX_STALL : usbd_regs.h
  • EPRX_VALID : usbd_regs.h
  • EPTCNT_CNT : usbd_regs.h
  • EPTX_DISABLED : usbd_regs.h
  • EPTX_DTGMASK : usbd_regs.h
  • EPTX_NAK : usbd_regs.h
  • EPTX_STALL : usbd_regs.h
  • EPTX_VALID : usbd_regs.h
  • EPxCS_ADDR : usbd_regs.h
  • EPxCS_CTL : usbd_regs.h
  • EPxCS_KCTL : usbd_regs.h
  • EPxCS_RX_DTG : usbd_regs.h
  • EPxCS_RX_ST : usbd_regs.h
  • EPxCS_RX_STA : usbd_regs.h
  • EPxCS_SETUP : usbd_regs.h
  • EPxCS_TX_DTG : usbd_regs.h
  • EPxCS_TX_ST : usbd_regs.h
  • EPxCS_TX_STA : usbd_regs.h
  • ERR_ERRN : gd32f10x_can.h
  • ERR_REG_OFFSET : gd32f10x_can.h
  • ETH_DMARXDESC_SIZE : gd32f10x_enet.h
  • ETH_DMATXDESC_SIZE : gd32f10x_enet.h
  • ETH_WAKEUP_REGISTER_LENGTH : gd32f10x_enet.h
  • EXMC : gd32f10x_exmc.h
  • EXMC_ACCESS_MODE_A : gd32f10x_exmc.h
  • EXMC_ACCESS_MODE_B : gd32f10x_exmc.h
  • EXMC_ACCESS_MODE_C : gd32f10x_exmc.h
  • EXMC_ACCESS_MODE_D : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_10_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_11_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_12_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_13_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_14_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_15_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_16_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_1_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_2_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_3_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_4_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_5_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_6_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_7_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_8_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_9_HCLK : gd32f10x_exmc.h
  • EXMC_ASYN_WRITE : gd32f10x_exmc.h
  • EXMC_BANK0_NORSRAM_REGION0 : gd32f10x_exmc.h
  • EXMC_BANK0_NORSRAM_REGION1 : gd32f10x_exmc.h
  • EXMC_BANK0_NORSRAM_REGION2 : gd32f10x_exmc.h
  • EXMC_BANK0_NORSRAM_REGION3 : gd32f10x_exmc.h
  • EXMC_BANK1_NAND : gd32f10x_exmc.h
  • EXMC_BANK2_NAND : gd32f10x_exmc.h
  • EXMC_BANK3_PCCARD : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_10_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_11_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_12_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_13_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_14_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_15_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_16_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_1_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_2_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_3_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_4_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_5_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_6_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_7_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_8_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_9_HCLK : gd32f10x_exmc.h
  • EXMC_DATALAT_10_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_11_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_12_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_13_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_14_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_15_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_16_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_17_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_2_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_3_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_4_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_5_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_6_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_7_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_8_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_9_CLK : gd32f10x_exmc.h
  • exmc_ecc_get() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • EXMC_ECC_SIZE_1024BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_2048BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_256BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_4096BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_512BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_8192BYTES : gd32f10x_exmc.h
  • exmc_flag_clear() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_flag_get() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_interrupt_disable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_interrupt_enable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_interrupt_flag_clear() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_interrupt_flag_get() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • EXMC_MEMORY_TYPE_NOR : gd32f10x_exmc.h
  • EXMC_MEMORY_TYPE_PSRAM : gd32f10x_exmc.h
  • EXMC_MEMORY_TYPE_SRAM : gd32f10x_exmc.h
  • EXMC_NAND_DATABUS_WIDTH_16B : gd32f10x_exmc.h
  • EXMC_NAND_DATABUS_WIDTH_8B : gd32f10x_exmc.h
  • exmc_nand_deinit() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_nand_disable() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_nand_ecc_config() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_nand_enable() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_nand_init() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_nand_parameter_init() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • EXMC_NAND_PCCARD_FLAG_FALL : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_FLAG_FIFOE : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_FLAG_LEVEL : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_FLAG_RISE : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_INT_FALL : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_INT_LEVEL : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_INT_RISE : gd32f10x_exmc.h
  • EXMC_NECC : gd32f10x_exmc.h
  • EXMC_NECC1 : gd32f10x_exmc.h
  • EXMC_NECC2 : gd32f10x_exmc.h
  • EXMC_NECC_ECC : gd32f10x_exmc.h
  • EXMC_NOR_DATABUS_WIDTH_16B : gd32f10x_exmc.h
  • EXMC_NOR_DATABUS_WIDTH_8B : gd32f10x_exmc.h
  • exmc_norsram_deinit() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_norsram_disable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_norsram_enable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_norsram_init() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_norsram_parameter_init() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • EXMC_NPATCFG : gd32f10x_exmc.h
  • EXMC_NPATCFG1 : gd32f10x_exmc.h
  • EXMC_NPATCFG2 : gd32f10x_exmc.h
  • EXMC_NPATCFG3 : gd32f10x_exmc.h
  • EXMC_NPATCFG_ATTHIZ : gd32f10x_exmc.h
  • EXMC_NPATCFG_ATTHLD : gd32f10x_exmc.h
  • EXMC_NPATCFG_ATTSET : gd32f10x_exmc.h
  • EXMC_NPATCFG_ATTWAIT : gd32f10x_exmc.h
  • EXMC_NPCTCFG : gd32f10x_exmc.h
  • EXMC_NPCTCFG1 : gd32f10x_exmc.h
  • EXMC_NPCTCFG2 : gd32f10x_exmc.h
  • EXMC_NPCTCFG3 : gd32f10x_exmc.h
  • EXMC_NPCTCFG_COMHIZ : gd32f10x_exmc.h
  • EXMC_NPCTCFG_COMHLD : gd32f10x_exmc.h
  • EXMC_NPCTCFG_COMSET : gd32f10x_exmc.h
  • EXMC_NPCTCFG_COMWAIT : gd32f10x_exmc.h
  • EXMC_NPCTL : gd32f10x_exmc.h
  • EXMC_NPCTL1 : gd32f10x_exmc.h
  • EXMC_NPCTL2 : gd32f10x_exmc.h
  • EXMC_NPCTL3 : gd32f10x_exmc.h
  • EXMC_NPCTL_ATR : gd32f10x_exmc.h
  • EXMC_NPCTL_CTR : gd32f10x_exmc.h
  • EXMC_NPCTL_ECCEN : gd32f10x_exmc.h
  • EXMC_NPCTL_ECCSZ : gd32f10x_exmc.h
  • EXMC_NPCTL_NDBKEN : gd32f10x_exmc.h
  • EXMC_NPCTL_NDTP : gd32f10x_exmc.h
  • EXMC_NPCTL_NDW : gd32f10x_exmc.h
  • EXMC_NPCTL_NDWTEN : gd32f10x_exmc.h
  • EXMC_NPINTEN : gd32f10x_exmc.h
  • EXMC_NPINTEN1 : gd32f10x_exmc.h
  • EXMC_NPINTEN2 : gd32f10x_exmc.h
  • EXMC_NPINTEN3 : gd32f10x_exmc.h
  • EXMC_NPINTEN_FFEPT : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTFEN : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTFS : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTHEN : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTHS : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTREN : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTRS : gd32f10x_exmc.h
  • EXMC_NWAIT_CONFIG_BEFORE : gd32f10x_exmc.h
  • EXMC_NWAIT_CONFIG_DURING : gd32f10x_exmc.h
  • EXMC_NWAIT_POLARITY_HIGH : gd32f10x_exmc.h
  • EXMC_NWAIT_POLARITY_LOW : gd32f10x_exmc.h
  • exmc_pccard_deinit() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_pccard_disable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_pccard_enable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_pccard_init() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_pccard_parameter_init() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • EXMC_PIOTCFG3 : gd32f10x_exmc.h
  • EXMC_PIOTCFG3_IOHIZ : gd32f10x_exmc.h
  • EXMC_PIOTCFG3_IOHLD : gd32f10x_exmc.h
  • EXMC_PIOTCFG3_IOSET : gd32f10x_exmc.h
  • EXMC_PIOTCFG3_IOWAIT : gd32f10x_exmc.h
  • EXMC_SNCTL : gd32f10x_exmc.h
  • EXMC_SNCTL0 : gd32f10x_exmc.h
  • EXMC_SNCTL1 : gd32f10x_exmc.h
  • EXMC_SNCTL2 : gd32f10x_exmc.h
  • EXMC_SNCTL3 : gd32f10x_exmc.h
  • EXMC_SNCTL_ASYNCWAIT : gd32f10x_exmc.h
  • EXMC_SNCTL_EXMODEN : gd32f10x_exmc.h
  • EXMC_SNCTL_NRBKEN : gd32f10x_exmc.h
  • EXMC_SNCTL_NREN : gd32f10x_exmc.h
  • EXMC_SNCTL_NRMUX : gd32f10x_exmc.h
  • EXMC_SNCTL_NRTP : gd32f10x_exmc.h
  • EXMC_SNCTL_NRW : gd32f10x_exmc.h
  • EXMC_SNCTL_NRWTCFG : gd32f10x_exmc.h
  • EXMC_SNCTL_NRWTEN : gd32f10x_exmc.h
  • EXMC_SNCTL_NRWTPOL : gd32f10x_exmc.h
  • EXMC_SNCTL_SBRSTEN : gd32f10x_exmc.h
  • EXMC_SNCTL_SYNCWR : gd32f10x_exmc.h
  • EXMC_SNCTL_WRAPEN : gd32f10x_exmc.h
  • EXMC_SNCTL_WREN : gd32f10x_exmc.h
  • EXMC_SNTCFG : gd32f10x_exmc.h
  • EXMC_SNTCFG0 : gd32f10x_exmc.h
  • EXMC_SNTCFG1 : gd32f10x_exmc.h
  • EXMC_SNTCFG2 : gd32f10x_exmc.h
  • EXMC_SNTCFG3 : gd32f10x_exmc.h
  • EXMC_SNTCFG_AHLD : gd32f10x_exmc.h
  • EXMC_SNTCFG_ASET : gd32f10x_exmc.h
  • EXMC_SNTCFG_ASYNCMOD : gd32f10x_exmc.h
  • EXMC_SNTCFG_BUSLAT : gd32f10x_exmc.h
  • EXMC_SNTCFG_CKDIV : gd32f10x_exmc.h
  • EXMC_SNTCFG_DLAT : gd32f10x_exmc.h
  • EXMC_SNTCFG_DSET : gd32f10x_exmc.h
  • EXMC_SNWTCFG : gd32f10x_exmc.h
  • EXMC_SNWTCFG0 : gd32f10x_exmc.h
  • EXMC_SNWTCFG1 : gd32f10x_exmc.h
  • EXMC_SNWTCFG2 : gd32f10x_exmc.h
  • EXMC_SNWTCFG3 : gd32f10x_exmc.h
  • EXMC_SNWTCFG_CKDIV : gd32f10x_exmc.h
  • EXMC_SNWTCFG_DLAT : gd32f10x_exmc.h
  • EXMC_SNWTCFG_WAHLD : gd32f10x_exmc.h
  • EXMC_SNWTCFG_WASET : gd32f10x_exmc.h
  • EXMC_SNWTCFG_WASYNCMOD : gd32f10x_exmc.h
  • EXMC_SNWTCFG_WDSET : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_10_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_11_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_12_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_13_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_14_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_15_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_16_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_2_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_3_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_4_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_5_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_6_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_7_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_8_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_9_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_DISABLE : gd32f10x_exmc.h
  • EXMC_SYN_WRITE : gd32f10x_exmc.h
  • EXTI : gd32f10x_exti.h
  • EXTI_0 : gd32f10x_exti.h
  • EXTI_1 : gd32f10x_exti.h
  • EXTI_10 : gd32f10x_exti.h
  • EXTI_11 : gd32f10x_exti.h
  • EXTI_12 : gd32f10x_exti.h
  • EXTI_13 : gd32f10x_exti.h
  • EXTI_14 : gd32f10x_exti.h
  • EXTI_15 : gd32f10x_exti.h
  • EXTI_16 : gd32f10x_exti.h
  • EXTI_17 : gd32f10x_exti.h
  • EXTI_18 : gd32f10x_exti.h
  • EXTI_19 : gd32f10x_exti.h
  • EXTI_2 : gd32f10x_exti.h
  • EXTI_3 : gd32f10x_exti.h
  • EXTI_4 : gd32f10x_exti.h
  • EXTI_5 : gd32f10x_exti.h
  • EXTI_6 : gd32f10x_exti.h
  • EXTI_7 : gd32f10x_exti.h
  • EXTI_8 : gd32f10x_exti.h
  • EXTI_9 : gd32f10x_exti.h
  • exti_deinit() : gd32f10x_exti.c , gd32f10x_exti.h
  • EXTI_EVEN : gd32f10x_exti.h
  • EXTI_EVEN_EVEN0 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN1 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN10 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN11 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN12 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN13 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN14 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN15 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN16 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN17 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN18 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN19 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN2 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN3 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN4 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN5 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN6 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN7 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN8 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN9 : gd32f10x_exti.h
  • EXTI_EVENT : gd32f10x_exti.h
  • exti_event_disable() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_event_enable() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_flag_clear() : gd32f10x_exti.c , gd32f10x_exti.h
  • exti_flag_get() : gd32f10x_exti.h , gd32f10x_exti.c
  • EXTI_FTEN : gd32f10x_exti.h
  • EXTI_FTEN_FTEN0 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN1 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN10 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN11 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN12 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN13 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN14 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN15 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN16 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN17 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN18 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN19 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN2 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN3 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN4 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN5 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN6 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN7 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN8 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN9 : gd32f10x_exti.h
  • exti_init() : gd32f10x_exti.h , gd32f10x_exti.c
  • EXTI_INTEN : gd32f10x_exti.h
  • EXTI_INTEN_INTEN0 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN1 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN10 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN11 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN12 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN13 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN14 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN15 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN16 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN17 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN18 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN19 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN2 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN3 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN4 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN5 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN6 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN7 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN8 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN9 : gd32f10x_exti.h
  • EXTI_INTERRUPT : gd32f10x_exti.h
  • exti_interrupt_disable() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_interrupt_enable() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_interrupt_flag_clear() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_interrupt_flag_get() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_line_enum : gd32f10x_exti.h
  • exti_mode_enum : gd32f10x_exti.h
  • EXTI_PD : gd32f10x_exti.h
  • EXTI_PD_PD0 : gd32f10x_exti.h
  • EXTI_PD_PD1 : gd32f10x_exti.h
  • EXTI_PD_PD10 : gd32f10x_exti.h
  • EXTI_PD_PD11 : gd32f10x_exti.h
  • EXTI_PD_PD12 : gd32f10x_exti.h
  • EXTI_PD_PD13 : gd32f10x_exti.h
  • EXTI_PD_PD14 : gd32f10x_exti.h
  • EXTI_PD_PD15 : gd32f10x_exti.h
  • EXTI_PD_PD16 : gd32f10x_exti.h
  • EXTI_PD_PD17 : gd32f10x_exti.h
  • EXTI_PD_PD18 : gd32f10x_exti.h
  • EXTI_PD_PD19 : gd32f10x_exti.h
  • EXTI_PD_PD2 : gd32f10x_exti.h
  • EXTI_PD_PD3 : gd32f10x_exti.h
  • EXTI_PD_PD4 : gd32f10x_exti.h
  • EXTI_PD_PD5 : gd32f10x_exti.h
  • EXTI_PD_PD6 : gd32f10x_exti.h
  • EXTI_PD_PD7 : gd32f10x_exti.h
  • EXTI_PD_PD8 : gd32f10x_exti.h
  • EXTI_PD_PD9 : gd32f10x_exti.h
  • EXTI_RTEN : gd32f10x_exti.h
  • EXTI_RTEN_RTEN0 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN1 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN10 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN11 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN12 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN13 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN14 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN15 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN16 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN17 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN18 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN19 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN2 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN3 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN4 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN5 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN6 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN7 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN8 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN9 : gd32f10x_exti.h
  • exti_software_interrupt_disable() : gd32f10x_exti.c , gd32f10x_exti.h
  • exti_software_interrupt_enable() : gd32f10x_exti.c , gd32f10x_exti.h
  • EXTI_SWIEV : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV0 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV1 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV10 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV11 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV12 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV13 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV14 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV15 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV16 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV17 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV18 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV19 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV2 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV3 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV4 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV5 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV6 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV7 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV8 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV9 : gd32f10x_exti.h
  • EXTI_TRIG_BOTH : gd32f10x_exti.h
  • EXTI_TRIG_FALLING : gd32f10x_exti.h
  • EXTI_TRIG_RISING : gd32f10x_exti.h
  • exti_trig_type_enum : gd32f10x_exti.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FCTL_HBC1F : gd32f10x_can.h
  • FDATA_MASK_HIGH : gd32f10x_can.h
  • FDATA_MASK_LOW : gd32f10x_can.h
  • FEATURE_SELECTOR_DEVICE : usbh_std.h
  • FEATURE_SELECTOR_ENDPOINT : usbh_std.h
  • FILTER_OPTION : gd32f10x_enet.h
  • FLOWCTL_OPTION : gd32f10x_enet.h
  • FMC : gd32f10x_fmc.h
  • FMC_ADDR0 : gd32f10x_fmc.h
  • FMC_ADDR0_ADDR : gd32f10x_fmc.h
  • FMC_ADDR1 : gd32f10x_fmc.h
  • FMC_ADDR1_ADDR : gd32f10x_fmc.h
  • FMC_BANK0_END_ADDRESS : gd32f10x_fmc.h
  • fmc_bank0_erase() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank0_lock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank0_ready_wait() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • FMC_BANK0_SIZE : gd32f10x_fmc.h
  • fmc_bank0_state_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank0_unlock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank1_erase() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank1_lock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank1_ready_wait() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank1_state_get() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • fmc_bank1_unlock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • FMC_BIT_POS : gd32f10x_fmc.h
  • FMC_BIT_POS0 : gd32f10x_fmc.h
  • FMC_BIT_POS1 : gd32f10x_fmc.h
  • FMC_BUSY : gd32f10x_fmc.h
  • FMC_CTL0 : gd32f10x_fmc.h
  • FMC_CTL0_ENDIE : gd32f10x_fmc.h
  • FMC_CTL0_ERRIE : gd32f10x_fmc.h
  • FMC_CTL0_LK : gd32f10x_fmc.h
  • FMC_CTL0_MER : gd32f10x_fmc.h
  • FMC_CTL0_OBER : gd32f10x_fmc.h
  • FMC_CTL0_OBPG : gd32f10x_fmc.h
  • FMC_CTL0_OBWEN : gd32f10x_fmc.h
  • FMC_CTL0_PER : gd32f10x_fmc.h
  • FMC_CTL0_PG : gd32f10x_fmc.h
  • FMC_CTL0_REG_OFFSET : gd32f10x_fmc.h
  • FMC_CTL0_START : gd32f10x_fmc.h
  • FMC_CTL1 : gd32f10x_fmc.h
  • FMC_CTL1_ENDIE : gd32f10x_fmc.h
  • FMC_CTL1_ERRIE : gd32f10x_fmc.h
  • FMC_CTL1_LK : gd32f10x_fmc.h
  • FMC_CTL1_MER : gd32f10x_fmc.h
  • FMC_CTL1_PER : gd32f10x_fmc.h
  • FMC_CTL1_PG : gd32f10x_fmc.h
  • FMC_CTL1_REG_OFFSET : gd32f10x_fmc.h
  • FMC_CTL1_START : gd32f10x_fmc.h
  • FMC_FLAG_BANK0_BUSY : gd32f10x_fmc.h
  • FMC_FLAG_BANK0_END : gd32f10x_fmc.h
  • FMC_FLAG_BANK0_PGERR : gd32f10x_fmc.h
  • FMC_FLAG_BANK0_WPERR : gd32f10x_fmc.h
  • FMC_FLAG_BANK1_BUSY : gd32f10x_fmc.h
  • FMC_FLAG_BANK1_END : gd32f10x_fmc.h
  • FMC_FLAG_BANK1_PGERR : gd32f10x_fmc.h
  • FMC_FLAG_BANK1_WPERR : gd32f10x_fmc.h
  • fmc_flag_clear() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_flag_enum : gd32f10x_fmc.h
  • fmc_flag_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • FMC_FLAG_OBERR : gd32f10x_fmc.h
  • fmc_halfword_program() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • FMC_INT_BANK0_END : gd32f10x_fmc.h
  • FMC_INT_BANK0_ERR : gd32f10x_fmc.h
  • FMC_INT_BANK1_END : gd32f10x_fmc.h
  • FMC_INT_BANK1_ERR : gd32f10x_fmc.h
  • fmc_int_enum : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK0_END : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK0_PGERR : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK0_WPERR : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK1_END : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK1_PGERR : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK1_WPERR : gd32f10x_fmc.h
  • fmc_interrupt_disable() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_interrupt_enable() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_interrupt_flag_clear() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_interrupt_flag_enum : gd32f10x_fmc.h
  • fmc_interrupt_flag_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • FMC_KEY0 : gd32f10x_fmc.h
  • FMC_KEY0_KEY : gd32f10x_fmc.h
  • FMC_KEY1 : gd32f10x_fmc.h
  • FMC_KEY1_KEY : gd32f10x_fmc.h
  • fmc_lock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_mass_erase() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • FMC_NSPC : gd32f10x_fmc.h
  • FMC_OBKEY : gd32f10x_fmc.h
  • FMC_OBKEY_OBKEY : gd32f10x_fmc.h
  • FMC_OBSTAT : gd32f10x_fmc.h
  • FMC_OBSTAT_DATA : gd32f10x_fmc.h
  • FMC_OBSTAT_OBERR : gd32f10x_fmc.h
  • FMC_OBSTAT_REG_OFFSET : gd32f10x_fmc.h
  • FMC_OBSTAT_SPC : gd32f10x_fmc.h
  • FMC_OBSTAT_USER : gd32f10x_fmc.h
  • fmc_page_erase() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • FMC_PGERR : gd32f10x_fmc.h
  • FMC_PID : gd32f10x_fmc.h
  • FMC_PID_PID : gd32f10x_fmc.h
  • FMC_READY : gd32f10x_fmc.h
  • FMC_REG_OFFSET_GET : gd32f10x_fmc.h
  • FMC_REG_VAL : gd32f10x_fmc.h
  • FMC_REG_VALS : gd32f10x_fmc.h
  • FMC_REGIDX_BIT : gd32f10x_fmc.h
  • FMC_REGIDX_BITS : gd32f10x_fmc.h
  • FMC_SIZE : gd32f10x_fmc.h
  • FMC_STAT0 : gd32f10x_fmc.h
  • FMC_STAT0_BUSY : gd32f10x_fmc.h
  • FMC_STAT0_ENDF : gd32f10x_fmc.h
  • FMC_STAT0_PGERR : gd32f10x_fmc.h
  • FMC_STAT0_REG_OFFSET : gd32f10x_fmc.h
  • FMC_STAT0_WPERR : gd32f10x_fmc.h
  • FMC_STAT1 : gd32f10x_fmc.h
  • FMC_STAT1_BUSY : gd32f10x_fmc.h
  • FMC_STAT1_ENDF : gd32f10x_fmc.h
  • FMC_STAT1_PGERR : gd32f10x_fmc.h
  • FMC_STAT1_REG_OFFSET : gd32f10x_fmc.h
  • FMC_STAT1_WPERR : gd32f10x_fmc.h
  • fmc_state_enum : gd32f10x_fmc.h
  • FMC_TIMEOUT_COUNT : gd32f10x_fmc.h
  • FMC_TOERR : gd32f10x_fmc.h
  • fmc_unlock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • FMC_USPC : gd32f10x_fmc.h
  • fmc_word_program() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • FMC_WP : gd32f10x_fmc.h
  • FMC_WP_WP : gd32f10x_fmc.h
  • FMC_WPERR : gd32f10x_fmc.h
  • FMC_WS : gd32f10x_fmc.h
  • FMC_WS_WSCNT : gd32f10x_fmc.h
  • fmc_wscnt_set() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • FMC_WSEN : gd32f10x_fmc.h
  • FMC_WSEN_WSEN : gd32f10x_fmc.h
  • FORWARD_OPTION : gd32f10x_enet.h
  • FRAME_INTERVAL_80 : usb_regs.h
  • FRAME_INTERVAL_85 : usb_regs.h
  • FRAME_INTERVAL_90 : usb_regs.h
  • FRAME_INTERVAL_95 : usb_regs.h
  • FWDGT : gd32f10x_fwdgt.h
  • fwdgt_config() : gd32f10x_fwdgt.h , gd32f10x_fwdgt.c
  • fwdgt_counter_reload() : gd32f10x_fwdgt.c , gd32f10x_fwdgt.h
  • FWDGT_CTL : gd32f10x_fwdgt.h
  • FWDGT_CTL_CMD : gd32f10x_fwdgt.h
  • fwdgt_enable() : gd32f10x_fwdgt.h , gd32f10x_fwdgt.c
  • fwdgt_flag_get() : gd32f10x_fwdgt.h , gd32f10x_fwdgt.c
  • FWDGT_FLAG_PUD : gd32f10x_fwdgt.h
  • FWDGT_FLAG_RUD : gd32f10x_fwdgt.h
  • FWDGT_KEY_ENABLE : gd32f10x_fwdgt.h
  • FWDGT_KEY_RELOAD : gd32f10x_fwdgt.h
  • FWDGT_PSC : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV128 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV16 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV256 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV32 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV4 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV64 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV8 : gd32f10x_fwdgt.h
  • FWDGT_PSC_PSC : gd32f10x_fwdgt.h
  • FWDGT_PSC_TIMEOUT : gd32f10x_fwdgt.h
  • FWDGT_RLD : gd32f10x_fwdgt.h
  • FWDGT_RLD_RLD : gd32f10x_fwdgt.h
  • FWDGT_RLD_TIMEOUT : gd32f10x_fwdgt.h
  • FWDGT_STAT : gd32f10x_fwdgt.h
  • FWDGT_STAT_PUD : gd32f10x_fwdgt.h
  • FWDGT_STAT_RUD : gd32f10x_fwdgt.h
  • fwdgt_write_disable() : gd32f10x_fwdgt.h , gd32f10x_fwdgt.c
  • FWDGT_WRITEACCESS_DISABLE : gd32f10x_fwdgt.h
  • FWDGT_WRITEACCESS_ENABLE : gd32f10x_fwdgt.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • g_device_address : usbd_std.c
  • g_ESOF_count : usbd_int.c , usbd_pwr.c
  • g_free_buf_addr : usbd_core.h , usbd_core.c
  • g_interrupt_mask : usbd_core.c , usbd_int.c
  • g_remote_wakeup_on : usbd_int.c , usbd_pwr.c
  • g_suspend_enabled : usbd_int.c , usbd_pwr.c
  • GAHBCS_DMAINCR : usb_regs.h
  • GAHBCS_GINTEN : usb_regs.h
  • GAHBCS_PTXFTH : usb_regs.h
  • GAHBCS_TFEL : usb_regs.h
  • GAHBCS_TXFTH : usb_regs.h
  • GCCFG_PWRON : usb_regs.h
  • GCCFG_SOFOEN : usb_regs.h
  • GCCFG_VBUSACEN : usb_regs.h
  • GCCFG_VBUSBCEN : usb_regs.h
  • GCCFG_VBUSIG : usb_regs.h
  • GET_DMA_BCTL_DPSL : gd32f10x_enet.h
  • GET_DMA_MFBOCNT_MSFA : gd32f10x_enet.h
  • GET_DMA_MFBOCNT_MSFC : gd32f10x_enet.h
  • GET_DMA_STAT_EB : gd32f10x_enet.h
  • GET_DMA_STAT_RP : gd32f10x_enet.h
  • GET_DMA_STAT_TP : gd32f10x_enet.h
  • GET_PTP_TSL_STMSS : gd32f10x_enet.h
  • GET_PTP_TSL_STS : gd32f10x_enet.h
  • GET_RDES0_FRML : gd32f10x_enet.h
  • GET_RDES1_RB1S : gd32f10x_enet.h
  • GET_RDES1_RB2S : gd32f10x_enet.h
  • GET_RDES4_IPPLDT : gd32f10x_enet.h
  • GET_RDES4_PTPMT : gd32f10x_enet.h
  • GET_TDES0_COCNT : gd32f10x_enet.h
  • GINTEN_DISCIE : usb_regs.h
  • GINTEN_ENUMFIE : usb_regs.h
  • GINTEN_EOPFIE : usb_regs.h
  • GINTEN_ESPIE : usb_regs.h
  • GINTEN_GNPINAKIE : usb_regs.h
  • GINTEN_GONAKIE : usb_regs.h
  • GINTEN_HCIE : usb_regs.h
  • GINTEN_HPIE : usb_regs.h
  • GINTEN_IDPSCIE : usb_regs.h
  • GINTEN_IEPIE : usb_regs.h
  • GINTEN_ISOINCIE : usb_regs.h
  • GINTEN_ISOONCIE : usb_regs.h
  • GINTEN_ISOOPDIE : usb_regs.h
  • GINTEN_MFIE : usb_regs.h
  • GINTEN_NPTXFEIE : usb_regs.h
  • GINTEN_OEPIE : usb_regs.h
  • GINTEN_OTGIE : usb_regs.h
  • GINTEN_PTXFEIE : usb_regs.h
  • GINTEN_PXNCIE : usb_regs.h
  • GINTEN_RSTIE : usb_regs.h
  • GINTEN_RXFNEIE : usb_regs.h
  • GINTEN_SESIE : usb_regs.h
  • GINTEN_SOFIE : usb_regs.h
  • GINTEN_SPIE : usb_regs.h
  • GINTEN_WKUPIE : usb_regs.h
  • GINTF_COPM : usb_regs.h
  • GINTF_DISCIF : usb_regs.h
  • GINTF_ENUMF : usb_regs.h
  • GINTF_EOPFIF : usb_regs.h
  • GINTF_ESP : usb_regs.h
  • GINTF_GNPINAK : usb_regs.h
  • GINTF_GONAK : usb_regs.h
  • GINTF_HCIF : usb_regs.h
  • GINTF_HPIF : usb_regs.h
  • GINTF_IDPSC : usb_regs.h
  • GINTF_IEPIF : usb_regs.h
  • GINTF_ISOINCIF : usb_regs.h
  • GINTF_ISOONCIF : usb_regs.h
  • GINTF_ISOOPDIF : usb_regs.h
  • GINTF_MFIF : usb_regs.h
  • GINTF_NPTXFEIF : usb_regs.h
  • GINTF_OEPIF : usb_regs.h
  • GINTF_OTGIF : usb_regs.h
  • GINTF_PTXFEIF : usb_regs.h
  • GINTF_PXNCIF : usb_regs.h
  • GINTF_RST : usb_regs.h
  • GINTF_RXFNEIF : usb_regs.h
  • GINTF_SESIF : usb_regs.h
  • GINTF_SOF : usb_regs.h
  • GINTF_SP : usb_regs.h
  • GINTF_WKUPIF : usb_regs.h
  • GO_TO_UP_STATE_EVENT : usbh_core.h
  • GOTGCS_ASV : usb_regs.h
  • GOTGCS_BSV : usb_regs.h
  • GOTGCS_DHNPEN : usb_regs.h
  • GOTGCS_DI : usb_regs.h
  • GOTGCS_HHNPEN : usb_regs.h
  • GOTGCS_HNPREQ : usb_regs.h
  • GOTGCS_HNPS : usb_regs.h
  • GOTGCS_IDPS : usb_regs.h
  • GOTGCS_SRPREQ : usb_regs.h
  • GOTGCS_SRPS : usb_regs.h
  • GOTGINTF_ADTO : usb_regs.h
  • GOTGINTF_DF : usb_regs.h
  • GOTGINTF_HNPDET : usb_regs.h
  • GOTGINTF_HNPEND : usb_regs.h
  • GOTGINTF_SESEND : usb_regs.h
  • GOTGINTF_SRPEND : usb_regs.h
  • goto_up_state_fun() : usbh_core.h , usbh_core.c
  • GPIO_ADC0_ETRGINS_REMAP : gd32f10x_gpio.h
  • GPIO_ADC0_ETRGREG_REMAP : gd32f10x_gpio.h
  • GPIO_ADC1_ETRGINS_REMAP : gd32f10x_gpio.h
  • GPIO_ADC1_ETRGREG_REMAP : gd32f10x_gpio.h
  • gpio_afio_deinit() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • GPIO_BC : gd32f10x_gpio.h
  • GPIO_BC_CR0 : gd32f10x_gpio.h
  • GPIO_BC_CR1 : gd32f10x_gpio.h
  • GPIO_BC_CR10 : gd32f10x_gpio.h
  • GPIO_BC_CR11 : gd32f10x_gpio.h
  • GPIO_BC_CR12 : gd32f10x_gpio.h
  • GPIO_BC_CR13 : gd32f10x_gpio.h
  • GPIO_BC_CR14 : gd32f10x_gpio.h
  • GPIO_BC_CR15 : gd32f10x_gpio.h
  • GPIO_BC_CR2 : gd32f10x_gpio.h
  • GPIO_BC_CR3 : gd32f10x_gpio.h
  • GPIO_BC_CR4 : gd32f10x_gpio.h
  • GPIO_BC_CR5 : gd32f10x_gpio.h
  • GPIO_BC_CR6 : gd32f10x_gpio.h
  • GPIO_BC_CR7 : gd32f10x_gpio.h
  • GPIO_BC_CR8 : gd32f10x_gpio.h
  • GPIO_BC_CR9 : gd32f10x_gpio.h
  • gpio_bit_reset() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_bit_set() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_bit_write() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • GPIO_BOP : gd32f10x_gpio.h
  • GPIO_BOP_BOP0 : gd32f10x_gpio.h
  • GPIO_BOP_BOP1 : gd32f10x_gpio.h
  • GPIO_BOP_BOP10 : gd32f10x_gpio.h
  • GPIO_BOP_BOP11 : gd32f10x_gpio.h
  • GPIO_BOP_BOP12 : gd32f10x_gpio.h
  • GPIO_BOP_BOP13 : gd32f10x_gpio.h
  • GPIO_BOP_BOP14 : gd32f10x_gpio.h
  • GPIO_BOP_BOP15 : gd32f10x_gpio.h
  • GPIO_BOP_BOP2 : gd32f10x_gpio.h
  • GPIO_BOP_BOP3 : gd32f10x_gpio.h
  • GPIO_BOP_BOP4 : gd32f10x_gpio.h
  • GPIO_BOP_BOP5 : gd32f10x_gpio.h
  • GPIO_BOP_BOP6 : gd32f10x_gpio.h
  • GPIO_BOP_BOP7 : gd32f10x_gpio.h
  • GPIO_BOP_BOP8 : gd32f10x_gpio.h
  • GPIO_BOP_BOP9 : gd32f10x_gpio.h
  • GPIO_BOP_CR0 : gd32f10x_gpio.h
  • GPIO_BOP_CR1 : gd32f10x_gpio.h
  • GPIO_BOP_CR10 : gd32f10x_gpio.h
  • GPIO_BOP_CR11 : gd32f10x_gpio.h
  • GPIO_BOP_CR12 : gd32f10x_gpio.h
  • GPIO_BOP_CR13 : gd32f10x_gpio.h
  • GPIO_BOP_CR14 : gd32f10x_gpio.h
  • GPIO_BOP_CR15 : gd32f10x_gpio.h
  • GPIO_BOP_CR2 : gd32f10x_gpio.h
  • GPIO_BOP_CR3 : gd32f10x_gpio.h
  • GPIO_BOP_CR4 : gd32f10x_gpio.h
  • GPIO_BOP_CR5 : gd32f10x_gpio.h
  • GPIO_BOP_CR6 : gd32f10x_gpio.h
  • GPIO_BOP_CR7 : gd32f10x_gpio.h
  • GPIO_BOP_CR8 : gd32f10x_gpio.h
  • GPIO_BOP_CR9 : gd32f10x_gpio.h
  • GPIO_CAN0_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_CAN0_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIO_CAN1_REMAP : gd32f10x_gpio.h
  • GPIO_CAN_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_CAN_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIO_CTL0 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL0 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL1 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL2 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL3 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL4 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL5 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL6 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL7 : gd32f10x_gpio.h
  • GPIO_CTL0_MD0 : gd32f10x_gpio.h
  • GPIO_CTL0_MD1 : gd32f10x_gpio.h
  • GPIO_CTL0_MD2 : gd32f10x_gpio.h
  • GPIO_CTL0_MD3 : gd32f10x_gpio.h
  • GPIO_CTL0_MD4 : gd32f10x_gpio.h
  • GPIO_CTL0_MD5 : gd32f10x_gpio.h
  • GPIO_CTL0_MD6 : gd32f10x_gpio.h
  • GPIO_CTL0_MD7 : gd32f10x_gpio.h
  • GPIO_CTL1 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL10 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL11 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL12 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL13 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL14 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL15 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL8 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL9 : gd32f10x_gpio.h
  • GPIO_CTL1_MD10 : gd32f10x_gpio.h
  • GPIO_CTL1_MD11 : gd32f10x_gpio.h
  • GPIO_CTL1_MD12 : gd32f10x_gpio.h
  • GPIO_CTL1_MD13 : gd32f10x_gpio.h
  • GPIO_CTL1_MD14 : gd32f10x_gpio.h
  • GPIO_CTL1_MD15 : gd32f10x_gpio.h
  • GPIO_CTL1_MD8 : gd32f10x_gpio.h
  • GPIO_CTL1_MD9 : gd32f10x_gpio.h
  • gpio_deinit() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • GPIO_ENET_PHY_MII : gd32f10x_gpio.h
  • GPIO_ENET_PHY_RMII : gd32f10x_gpio.h
  • GPIO_ENET_REMAP : gd32f10x_gpio.h
  • gpio_ethernet_phy_select() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_event_output_config() : gd32f10x_gpio.c , gd32f10x_gpio.h
  • gpio_event_output_disable() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_event_output_enable() : gd32f10x_gpio.c , gd32f10x_gpio.h
  • GPIO_EVENT_PIN_0 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_1 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_10 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_11 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_12 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_13 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_14 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_15 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_2 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_3 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_4 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_5 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_6 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_7 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_8 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_9 : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOA : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOB : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOC : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOD : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOE : gd32f10x_gpio.h
  • gpio_exti_source_select() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • GPIO_FSMC_NADV_REMAP : gd32f10x_gpio.h
  • GPIO_I2C0_REMAP : gd32f10x_gpio.h
  • gpio_init() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_input_bit_get() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_input_port_get() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • GPIO_ISTAT : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT0 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT1 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT10 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT11 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT12 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT13 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT14 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT15 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT2 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT3 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT4 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT5 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT6 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT7 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT8 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT9 : gd32f10x_gpio.h
  • GPIO_LOCK : gd32f10x_gpio.h
  • GPIO_LOCK_LK0 : gd32f10x_gpio.h
  • GPIO_LOCK_LK1 : gd32f10x_gpio.h
  • GPIO_LOCK_LK10 : gd32f10x_gpio.h
  • GPIO_LOCK_LK11 : gd32f10x_gpio.h
  • GPIO_LOCK_LK12 : gd32f10x_gpio.h
  • GPIO_LOCK_LK13 : gd32f10x_gpio.h
  • GPIO_LOCK_LK14 : gd32f10x_gpio.h
  • GPIO_LOCK_LK15 : gd32f10x_gpio.h
  • GPIO_LOCK_LK2 : gd32f10x_gpio.h
  • GPIO_LOCK_LK3 : gd32f10x_gpio.h
  • GPIO_LOCK_LK4 : gd32f10x_gpio.h
  • GPIO_LOCK_LK5 : gd32f10x_gpio.h
  • GPIO_LOCK_LK6 : gd32f10x_gpio.h
  • GPIO_LOCK_LK7 : gd32f10x_gpio.h
  • GPIO_LOCK_LK8 : gd32f10x_gpio.h
  • GPIO_LOCK_LK9 : gd32f10x_gpio.h
  • GPIO_LOCK_LKK : gd32f10x_gpio.h
  • GPIO_MODE_AF_OD : gd32f10x_gpio.h
  • GPIO_MODE_AF_PP : gd32f10x_gpio.h
  • GPIO_MODE_AIN : gd32f10x_gpio.h
  • GPIO_MODE_IN_FLOATING : gd32f10x_gpio.h
  • GPIO_MODE_IPD : gd32f10x_gpio.h
  • GPIO_MODE_IPU : gd32f10x_gpio.h
  • GPIO_MODE_MASK : gd32f10x_gpio.h
  • GPIO_MODE_OUT_OD : gd32f10x_gpio.h
  • GPIO_MODE_OUT_PP : gd32f10x_gpio.h
  • GPIO_MODE_SET : gd32f10x_gpio.h
  • GPIO_OCTL : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL0 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL1 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL10 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL11 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL12 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL13 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL14 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL15 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL2 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL3 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL4 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL5 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL6 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL7 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL8 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL9 : gd32f10x_gpio.h
  • GPIO_OSPEED_10MHZ : gd32f10x_gpio.h
  • GPIO_OSPEED_2MHZ : gd32f10x_gpio.h
  • GPIO_OSPEED_50MHZ : gd32f10x_gpio.h
  • gpio_output_bit_get() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_output_port_get() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • GPIO_PD01_REMAP : gd32f10x_gpio.h
  • GPIO_PIN_0 : gd32f10x_gpio.h
  • GPIO_PIN_1 : gd32f10x_gpio.h
  • GPIO_PIN_10 : gd32f10x_gpio.h
  • GPIO_PIN_11 : gd32f10x_gpio.h
  • GPIO_PIN_12 : gd32f10x_gpio.h
  • GPIO_PIN_13 : gd32f10x_gpio.h
  • GPIO_PIN_14 : gd32f10x_gpio.h
  • GPIO_PIN_15 : gd32f10x_gpio.h
  • GPIO_PIN_2 : gd32f10x_gpio.h
  • GPIO_PIN_3 : gd32f10x_gpio.h
  • GPIO_PIN_4 : gd32f10x_gpio.h
  • GPIO_PIN_5 : gd32f10x_gpio.h
  • GPIO_PIN_6 : gd32f10x_gpio.h
  • GPIO_PIN_7 : gd32f10x_gpio.h
  • GPIO_PIN_8 : gd32f10x_gpio.h
  • GPIO_PIN_9 : gd32f10x_gpio.h
  • GPIO_PIN_ALL : gd32f10x_gpio.h
  • gpio_pin_lock() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_pin_remap_config() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • GPIO_PIN_SOURCE_0 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_1 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_10 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_11 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_12 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_13 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_14 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_15 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_2 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_3 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_4 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_5 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_6 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_7 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_8 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_9 : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOA : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOB : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOC : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOD : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOE : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOF : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOG : gd32f10x_gpio.h
  • gpio_port_write() : gd32f10x_gpio.c , gd32f10x_gpio.h
  • GPIO_PTP_PPS_REMAP : gd32f10x_gpio.h
  • GPIO_SPI0_REMAP : gd32f10x_gpio.h
  • GPIO_SPI2_REMAP : gd32f10x_gpio.h
  • GPIO_SWJ_DISABLE_REMAP : gd32f10x_gpio.h
  • GPIO_SWJ_NONJTRST_REMAP : gd32f10x_gpio.h
  • GPIO_SWJ_SWDPENABLE_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER0_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER0_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER10_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER12_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER13_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER1_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER1_PARTIAL_REMAP0 : gd32f10x_gpio.h
  • GPIO_TIMER1_PARTIAL_REMAP1 : gd32f10x_gpio.h
  • GPIO_TIMER1ITR0_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER2_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER2_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER3_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER4CH3_IREMAP : gd32f10x_gpio.h
  • GPIO_TIMER8_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER9_REMAP : gd32f10x_gpio.h
  • GPIO_USART0_REMAP : gd32f10x_gpio.h
  • GPIO_USART1_REMAP : gd32f10x_gpio.h
  • GPIO_USART2_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_USART2_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIOA : gd32f10x_gpio.h
  • GPIOB : gd32f10x_gpio.h
  • GPIOC : gd32f10x_gpio.h
  • GPIOD : gd32f10x_gpio.h
  • GPIOE : gd32f10x_gpio.h
  • GPIOF : gd32f10x_gpio.h
  • GPIOG : gd32f10x_gpio.h
  • GRFLEN_RXFD : usb_regs.h
  • GRSTATR_RPCKST_CH_HALTED : usb_defines.h
  • GRSTATR_RPCKST_DATA_TOGGLE_ERR : usb_defines.h
  • GRSTATR_RPCKST_IN : usb_defines.h
  • GRSTATR_RPCKST_IN_XFER_COMP : usb_defines.h
  • GRSTATRP_BCOUNT : usb_regs.h
  • GRSTATRP_CNUM : usb_regs.h
  • GRSTATRP_DPID : usb_regs.h
  • GRSTATRP_EPNUM : usb_regs.h
  • GRSTATRP_RPCKST : usb_regs.h
  • GRSTCTL_CSRST : usb_regs.h
  • GRSTCTL_HCSRST : usb_regs.h
  • GRSTCTL_HFCRST : usb_regs.h
  • GRSTCTL_RXFF : usb_regs.h
  • GRSTCTL_TXFF : usb_regs.h
  • GRSTCTL_TXFNUM : usb_regs.h
  • GUSBCS_FDM : usb_regs.h
  • GUSBCS_FHM : usb_regs.h
  • GUSBCS_HNPCEN : usb_regs.h
  • GUSBCS_SRPCEN : usb_regs.h
  • GUSBCS_TOC : usb_regs.h
  • GUSBCS_UTT : usb_regs.h


GD32F10x_Firmware_Library: Globals

  • All
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  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HACHINT_HACHINT : usb_regs.h
  • HACHINTEN_CINTEN : usb_regs.h
  • HALFDUPLEX_OPTION : gd32f10x_enet.h
  • HASHH_OPTION : gd32f10x_enet.h
  • HASHL_OPTION : gd32f10x_enet.h
  • HC_BBERR : usb_core.h
  • HC_DTGERR : usb_core.h
  • HC_ERROR : usbh_hcs.h
  • HC_HALTED : usb_core.h
  • HC_IDLE : usb_core.h
  • HC_MAX : usbh_hcs.h
  • HC_MAX_PACKET_COUNT : usb_core.h
  • HC_NAK : usb_core.h
  • HC_NYET : usb_core.h
  • HC_OK : usbh_hcs.h
  • HC_PID_DATA0 : usb_defines.h
  • HC_PID_DATA1 : usb_defines.h
  • HC_PID_DATA2 : usb_defines.h
  • HC_PID_SETUP : usb_defines.h
  • HC_STALL : usb_core.h
  • hc_status_enum : usb_core.h
  • HC_TRACERR : usb_core.h
  • HC_USED : usbh_hcs.h
  • HC_USED_MASK : usbh_hcs.h
  • HC_XF : usb_core.h
  • HCCHAR_BULK : usb_defines.h
  • HCCHAR_CTRL : usb_defines.h
  • HCCHAR_INTR : usb_defines.h
  • HCCHAR_ISOC : usb_defines.h
  • hcd_init() : usbh_core.h , usbh_core.c
  • hcd_is_device_connected() : usbh_core.h , usbh_core.c
  • hcd_submit_request() : usbh_ctrl.h , usbh_ctrl.c
  • hcd_urb_state_get() : usbh_core.h , usbh_core.c
  • hcd_xfer_count_get() : usbh_core.h , usbh_core.c
  • HCHCTL_CDIS : usb_regs.h
  • HCHCTL_CEN : usb_regs.h
  • HCHCTL_DAR : usb_regs.h
  • HCHCTL_EPDIR : usb_regs.h
  • HCHCTL_EPNUM : usb_regs.h
  • HCHCTL_EPTYPE : usb_regs.h
  • HCHCTL_LSD : usb_regs.h
  • HCHCTL_MPC : usb_regs.h
  • HCHCTL_MPL : usb_regs.h
  • HCHCTL_ODDFRM : usb_regs.h
  • HCHINTEN_ACKIE : usb_regs.h
  • HCHINTEN_BBERIE : usb_regs.h
  • HCHINTEN_CHIE : usb_regs.h
  • HCHINTEN_DTERIE : usb_regs.h
  • HCHINTEN_NAKIE : usb_regs.h
  • HCHINTEN_NYETIE : usb_regs.h
  • HCHINTEN_REQOVRIE : usb_regs.h
  • HCHINTEN_STALLIE : usb_regs.h
  • HCHINTEN_TFIE : usb_regs.h
  • HCHINTEN_USBERIE : usb_regs.h
  • HCHINTF_ACK : usb_regs.h
  • HCHINTF_BBER : usb_regs.h
  • HCHINTF_CH : usb_regs.h
  • HCHINTF_DTER : usb_regs.h
  • HCHINTF_NAK : usb_regs.h
  • HCHINTF_NYET : usb_regs.h
  • HCHINTF_REQOVR : usb_regs.h
  • HCHINTF_STALL : usb_regs.h
  • HCHINTF_TF : usb_regs.h
  • HCHINTF_USBER : usb_regs.h
  • HCHLEN_DPID : usb_regs.h
  • HCHLEN_PCNT : usb_regs.h
  • HCHLEN_TLEN : usb_regs.h
  • HCTL_CLKSEL : usb_regs.h
  • HCTLR_30_60_MHZ : usb_defines.h
  • HCTLR_48_MHZ : usb_defines.h
  • HCTLR_6_MHZ : usb_defines.h
  • HFINFR_FRNUM : usb_regs.h
  • HFINFR_FRT : usb_regs.h
  • HFT_FRI : usb_regs.h
  • HID_BOOT_CODE : usb_std.h
  • HID_CLASS : usbh_core.h
  • HID_KEYBRD_BOOT_CODE : usb_std.h
  • HID_MOUSE_BOOT_CODE : usb_std.h
  • HIGHBYTE : usbd_std.h
  • HNPTFLEN_HNPTXFD : usb_regs.h
  • HNPTFLEN_HNPTXRSAR : usb_regs.h
  • HNPTFQSTAT_CNUM : usb_regs.h
  • HNPTFQSTAT_EPNUM : usb_regs.h
  • HNPTFQSTAT_NPTXFS : usb_regs.h
  • HNPTFQSTAT_NPTXRQS : usb_regs.h
  • HNPTFQSTAT_NPTXRQTOP : usb_regs.h
  • HNPTFQSTAT_TMF : usb_regs.h
  • HNPTFQSTAT_TYPE : usb_regs.h
  • HOST_CLASS : usbh_core.h
  • HOST_CLASS_REQUEST : usbh_core.h
  • HOST_DETECT_DEV_SPEED : usbh_core.h
  • HOST_DEV_ATTACHED : usbh_core.h
  • HOST_DEV_DETACHED : usbh_core.h
  • HOST_ENUMERATION : usbh_core.h
  • HOST_ERROR : usbh_core.h
  • HOST_EVENT_ATTACHED : usbh_core.h
  • HOST_EVENT_CLASS : usbh_core.h
  • HOST_EVENT_CLASS_REQ : usbh_core.h
  • HOST_EVENT_DEV_DETACHED : usbh_core.h
  • HOST_EVENT_ENUM : usbh_core.h
  • host_event_enum : usbh_core.h
  • HOST_EVENT_ERROR : usbh_core.h
  • HOST_EVENT_IDLE : usbh_core.h
  • HOST_EVENT_USER_INPUT : usbh_core.h
  • HOST_FSM_ID : usbh_core.h
  • host_handle_table : usbh_core.c
  • HOST_HANDLE_TABLE_SIZE : usbh_core.h
  • HOST_IDLE : usbh_core.h
  • HOST_MODE : usb_defines.h
  • host_state_enum : usbh_core.h
  • host_state_handle : usbh_core.c
  • host_state_polling_fun() : usbh_core.c , usbh_core.h
  • HOST_SUSPENDED : usbh_core.h
  • HOST_USER_CLASS_ACTIVE : usbh_core.h
  • HOST_USER_CLASS_SELECTED : usbh_core.h
  • HOST_USER_CONNECTION : usbh_core.h
  • HOST_USER_DISCONNECTION : usbh_core.h
  • HOST_USER_INPUT : usbh_core.h
  • HOST_USER_SELECT_CONFIGURATION : usbh_core.h
  • HOST_USER_UNRECOVERED_ERROR : usbh_core.h
  • HPCS_PCD : usb_regs.h
  • HPCS_PCST : usb_regs.h
  • HPCS_PE : usb_regs.h
  • HPCS_PEDC : usb_regs.h
  • HPCS_PLST : usb_regs.h
  • HPCS_PP : usb_regs.h
  • HPCS_PREM : usb_regs.h
  • HPCS_PRST : usb_regs.h
  • HPCS_PS : usb_regs.h
  • HPCS_PSP : usb_regs.h
  • HPRT_PRTSPD_FULL_SPEED : usb_defines.h
  • HPRT_PRTSPD_HIGH_SPEED : usb_defines.h
  • HPRT_PRTSPD_LOW_SPEED : usb_defines.h
  • HPTFLEN_HPTXFD : usb_regs.h
  • HPTFLEN_HPTXFSAR : usb_regs.h
  • HPTFQSTAT_CNUM : usb_regs.h
  • HPTFQSTAT_EPNUM : usb_regs.h
  • HPTFQSTAT_OEFRM : usb_regs.h
  • HPTFQSTAT_PTXFS : usb_regs.h
  • HPTFQSTAT_PTXREQS : usb_regs.h
  • HPTFQSTAT_PTXREQT : usb_regs.h
  • HPTFQSTAT_TMF : usb_regs.h
  • HPTFQSTAT_TYPE : usb_regs.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C0 : gd32f10x_i2c.h
  • I2C1 : gd32f10x_i2c.h
  • i2c_ack_config() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • I2C_ACK_DISABLE : gd32f10x_i2c.h
  • I2C_ACK_ENABLE : gd32f10x_i2c.h
  • i2c_ackpos_config() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • I2C_ACKPOS_CURRENT : gd32f10x_i2c.h
  • I2C_ACKPOS_NEXT : gd32f10x_i2c.h
  • I2C_ADDFORMAT_10BITS : gd32f10x_i2c.h
  • I2C_ADDFORMAT_7BITS : gd32f10x_i2c.h
  • I2C_ARP_DISABLE : gd32f10x_i2c.h
  • I2C_ARP_ENABLE : gd32f10x_i2c.h
  • I2C_CKCFG : gd32f10x_i2c.h
  • I2C_CKCFG_CLKC : gd32f10x_i2c.h
  • I2C_CKCFG_DTCY : gd32f10x_i2c.h
  • I2C_CKCFG_FAST : gd32f10x_i2c.h
  • i2c_clock_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_CTL0 : gd32f10x_i2c.h
  • I2C_CTL0_ACKEN : gd32f10x_i2c.h
  • I2C_CTL0_ARPEN : gd32f10x_i2c.h
  • I2C_CTL0_DISSTRC : gd32f10x_i2c.h
  • I2C_CTL0_GCEN : gd32f10x_i2c.h
  • I2C_CTL0_I2CEN : gd32f10x_i2c.h
  • I2C_CTL0_PECEN : gd32f10x_i2c.h
  • I2C_CTL0_PECTRANS : gd32f10x_i2c.h
  • I2C_CTL0_POAP : gd32f10x_i2c.h
  • I2C_CTL0_SALT : gd32f10x_i2c.h
  • I2C_CTL0_SMBEN : gd32f10x_i2c.h
  • I2C_CTL0_SMBSEL : gd32f10x_i2c.h
  • I2C_CTL0_SRESET : gd32f10x_i2c.h
  • I2C_CTL0_START : gd32f10x_i2c.h
  • I2C_CTL0_STOP : gd32f10x_i2c.h
  • I2C_CTL1 : gd32f10x_i2c.h
  • I2C_CTL1_BUFIE : gd32f10x_i2c.h
  • I2C_CTL1_DMALST : gd32f10x_i2c.h
  • I2C_CTL1_DMAON : gd32f10x_i2c.h
  • I2C_CTL1_ERRIE : gd32f10x_i2c.h
  • I2C_CTL1_EVIE : gd32f10x_i2c.h
  • I2C_CTL1_I2CCLK : gd32f10x_i2c.h
  • I2C_DATA : gd32f10x_i2c.h
  • i2c_data_receive() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_data_transmit() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_DATA_TRB : gd32f10x_i2c.h
  • i2c_deinit() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_disable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_dma_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_dma_last_transfer_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_DMA_OFF : gd32f10x_i2c.h
  • I2C_DMA_ON : gd32f10x_i2c.h
  • I2C_DMALST_OFF : gd32f10x_i2c.h
  • I2C_DMALST_ON : gd32f10x_i2c.h
  • I2C_DTCY_16_9 : gd32f10x_i2c.h
  • I2C_DTCY_2 : gd32f10x_i2c.h
  • I2C_DUADEN_DISABLE : gd32f10x_i2c.h
  • I2C_DUADEN_ENABLE : gd32f10x_i2c.h
  • i2c_dualaddr_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_FLAG_ADD10SEND : gd32f10x_i2c.h
  • I2C_FLAG_ADDSEND : gd32f10x_i2c.h
  • I2C_FLAG_AERR : gd32f10x_i2c.h
  • I2C_FLAG_BERR : gd32f10x_i2c.h
  • I2C_FLAG_BTC : gd32f10x_i2c.h
  • i2c_flag_clear() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_FLAG_DEFSMB : gd32f10x_i2c.h
  • I2C_FLAG_DUMOD : gd32f10x_i2c.h
  • i2c_flag_get() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_FLAG_HSTSMB : gd32f10x_i2c.h
  • I2C_FLAG_I2CBSY : gd32f10x_i2c.h
  • I2C_FLAG_LOSTARB : gd32f10x_i2c.h
  • I2C_FLAG_MASK : gd32f10x_i2c.c
  • I2C_FLAG_MASTER : gd32f10x_i2c.h
  • I2C_FLAG_OUERR : gd32f10x_i2c.h
  • I2C_FLAG_PECERR : gd32f10x_i2c.h
  • I2C_FLAG_RBNE : gd32f10x_i2c.h
  • I2C_FLAG_RXGC : gd32f10x_i2c.h
  • I2C_FLAG_SBSEND : gd32f10x_i2c.h
  • I2C_FLAG_SMBALT : gd32f10x_i2c.h
  • I2C_FLAG_SMBTO : gd32f10x_i2c.h
  • I2C_FLAG_STPDET : gd32f10x_i2c.h
  • I2C_FLAG_TBE : gd32f10x_i2c.h
  • I2C_FLAG_TRS : gd32f10x_i2c.h
  • I2C_GCEN_DISABLE : gd32f10x_i2c.h
  • I2C_GCEN_ENABLE : gd32f10x_i2c.h
  • I2C_I2CMODE_ENABLE : gd32f10x_i2c.h
  • I2C_INT_BUF : gd32f10x_i2c.h
  • I2C_INT_ERR : gd32f10x_i2c.h
  • I2C_INT_EV : gd32f10x_i2c.h
  • I2C_INT_FLAG_ADD10SEND : gd32f10x_i2c.h
  • I2C_INT_FLAG_ADDSEND : gd32f10x_i2c.h
  • I2C_INT_FLAG_AERR : gd32f10x_i2c.h
  • I2C_INT_FLAG_BERR : gd32f10x_i2c.h
  • I2C_INT_FLAG_BTC : gd32f10x_i2c.h
  • I2C_INT_FLAG_LOSTARB : gd32f10x_i2c.h
  • I2C_INT_FLAG_OUERR : gd32f10x_i2c.h
  • I2C_INT_FLAG_PECERR : gd32f10x_i2c.h
  • I2C_INT_FLAG_RBNE : gd32f10x_i2c.h
  • I2C_INT_FLAG_SBSEND : gd32f10x_i2c.h
  • I2C_INT_FLAG_SMBALT : gd32f10x_i2c.h
  • I2C_INT_FLAG_SMBTO : gd32f10x_i2c.h
  • I2C_INT_FLAG_STPDET : gd32f10x_i2c.h
  • I2C_INT_FLAG_TBE : gd32f10x_i2c.h
  • i2c_interrupt_disable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_interrupt_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_interrupt_flag_clear() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_interrupt_flag_get() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_master_addressing() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_mode_addr_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_PEC_DISABLE : gd32f10x_i2c.h
  • i2c_pec_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_PEC_ENABLE : gd32f10x_i2c.h
  • i2c_pec_transfer_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_pec_value_get() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_PECTRANS_DISABLE : gd32f10x_i2c.h
  • I2C_PECTRANS_ENABLE : gd32f10x_i2c.h
  • I2C_RECEIVER : gd32f10x_i2c.h
  • I2C_RT : gd32f10x_i2c.h
  • I2C_RT_RISETIME : gd32f10x_i2c.h
  • I2C_SADDR0 : gd32f10x_i2c.h
  • I2C_SADDR0_ADDFORMAT : gd32f10x_i2c.h
  • I2C_SADDR0_ADDRESS : gd32f10x_i2c.h
  • I2C_SADDR0_ADDRESS0 : gd32f10x_i2c.h
  • I2C_SADDR0_ADDRESS_H : gd32f10x_i2c.h
  • I2C_SADDR1 : gd32f10x_i2c.h
  • I2C_SADDR1_ADDRESS2 : gd32f10x_i2c.h
  • I2C_SADDR1_DUADEN : gd32f10x_i2c.h
  • I2C_SALTSEND_DISABLE : gd32f10x_i2c.h
  • I2C_SALTSEND_ENABLE : gd32f10x_i2c.h
  • I2C_SCLSTRETCH_DISABLE : gd32f10x_i2c.h
  • I2C_SCLSTRETCH_ENABLE : gd32f10x_i2c.h
  • i2c_slave_response_to_gcall_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_smbus_arp_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_SMBUS_DEVICE : gd32f10x_i2c.h
  • I2C_SMBUS_HOST : gd32f10x_i2c.h
  • i2c_smbus_issue_alert() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_smbus_type_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_SMBUSMODE_ENABLE : gd32f10x_i2c.h
  • i2c_software_reset_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • I2C_SRESET_RESET : gd32f10x_i2c.h
  • I2C_SRESET_SET : gd32f10x_i2c.h
  • i2c_start_on_bus() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • I2C_STAT0 : gd32f10x_i2c.h
  • I2C_STAT0_ADD10SEND : gd32f10x_i2c.h
  • I2C_STAT0_ADDSEND : gd32f10x_i2c.h
  • I2C_STAT0_AERR : gd32f10x_i2c.h
  • I2C_STAT0_BERR : gd32f10x_i2c.h
  • I2C_STAT0_BTC : gd32f10x_i2c.h
  • I2C_STAT0_LOSTARB : gd32f10x_i2c.h
  • I2C_STAT0_OUERR : gd32f10x_i2c.h
  • I2C_STAT0_PECERR : gd32f10x_i2c.h
  • I2C_STAT0_RBNE : gd32f10x_i2c.h
  • I2C_STAT0_SBSEND : gd32f10x_i2c.h
  • I2C_STAT0_SMBALT : gd32f10x_i2c.h
  • I2C_STAT0_SMBTO : gd32f10x_i2c.h
  • I2C_STAT0_STPDET : gd32f10x_i2c.h
  • I2C_STAT0_TBE : gd32f10x_i2c.h
  • I2C_STAT1 : gd32f10x_i2c.h
  • I2C_STAT1_DEFSMB : gd32f10x_i2c.h
  • I2C_STAT1_DUMODF : gd32f10x_i2c.h
  • I2C_STAT1_ECV : gd32f10x_i2c.h
  • I2C_STAT1_HSTSMB : gd32f10x_i2c.h
  • I2C_STAT1_I2CBSY : gd32f10x_i2c.h
  • I2C_STAT1_MASTER : gd32f10x_i2c.h
  • I2C_STAT1_RXGC : gd32f10x_i2c.h
  • I2C_STAT1_TRS : gd32f10x_i2c.h
  • i2c_stop_on_bus() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_stretch_scl_low_config() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • I2C_TRANSMITTER : gd32f10x_i2c.h
  • I2CCLK_MAX : gd32f10x_i2c.c
  • I2S1_CLOCK_SEL : gd32f10x_spi.c
  • I2S2_CLOCK_SEL : gd32f10x_spi.c
  • I2S_AUDIOSAMPLE_11K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_16K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_192K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_22K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_32K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_44K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_48K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_8K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_96K : gd32f10x_spi.h
  • I2S_CKPL_HIGH : gd32f10x_spi.h
  • I2S_CKPL_LOW : gd32f10x_spi.h
  • I2S_CLOCK_DIV_MASK : gd32f10x_spi.c
  • I2S_CLOCK_MUL_MASK : gd32f10x_spi.c
  • i2s_disable() : gd32f10x_spi.h , gd32f10x_spi.c
  • i2s_enable() : gd32f10x_spi.h , gd32f10x_spi.c
  • I2S_FLAG_CH : gd32f10x_spi.h
  • I2S_FLAG_RBNE : gd32f10x_spi.h
  • I2S_FLAG_RXORERR : gd32f10x_spi.h
  • I2S_FLAG_TBE : gd32f10x_spi.h
  • I2S_FLAG_TRANS : gd32f10x_spi.h
  • I2S_FLAG_TXURERR : gd32f10x_spi.h
  • I2S_FRAMEFORMAT_DT16B_CH16B : gd32f10x_spi.h
  • I2S_FRAMEFORMAT_DT16B_CH32B : gd32f10x_spi.h
  • I2S_FRAMEFORMAT_DT24B_CH32B : gd32f10x_spi.h
  • I2S_FRAMEFORMAT_DT32B_CH32B : gd32f10x_spi.h
  • i2s_init() : gd32f10x_spi.c , gd32f10x_spi.h
  • I2S_INIT_MASK : gd32f10x_spi.c
  • I2S_INT_FLAG_TXURERR : gd32f10x_spi.h
  • I2S_MCKOUT_DISABLE : gd32f10x_spi.h
  • I2S_MCKOUT_ENABLE : gd32f10x_spi.h
  • I2S_MODE_MASTERRX : gd32f10x_spi.h
  • I2S_MODE_MASTERTX : gd32f10x_spi.h
  • I2S_MODE_SLAVERX : gd32f10x_spi.h
  • I2S_MODE_SLAVETX : gd32f10x_spi.h
  • i2s_psc_config() : gd32f10x_spi.c , gd32f10x_spi.h
  • I2S_STD_LSB : gd32f10x_spi.h
  • I2S_STD_MSB : gd32f10x_spi.h
  • I2S_STD_PCMLONG : gd32f10x_spi.h
  • I2S_STD_PCMSHORT : gd32f10x_spi.h
  • I2S_STD_PHILLIPS : gd32f10x_spi.h
  • I2SCTL_DTLEN : gd32f10x_spi.h
  • I2SCTL_I2SOPMOD : gd32f10x_spi.h
  • I2SCTL_I2SSTD : gd32f10x_spi.h
  • IER_MASK : usbd_core.h
  • IF_USE_EXTERNPHY_LIB : gd32f10x_enet.h
  • INT_REG_OFFSET : gd32f10x_rcu.h
  • INTEN_INTS_OFFSET : gd32f10x_exmc.c
  • INTERFRAMEGAP_OPTION : gd32f10x_enet.h
  • INTF_DIR : usbd_regs.h
  • INTF_EPNUM : usbd_regs.h
  • INTF_ERRIF : usbd_regs.h
  • INTF_ESOFIF : usbd_regs.h
  • INTF_L1REQ : usbd_regs.h
  • INTF_PMOUIF : usbd_regs.h
  • INTF_RSTIF : usbd_regs.h
  • INTF_SOFIF : usbd_regs.h
  • INTF_SPSIF : usbd_regs.h
  • INTF_STIF : usbd_regs.h
  • INTF_WKUPIF : usbd_regs.h
  • IOFFX_IOFF : gd32f10x_adc.h
  • IS_NOT_EP0 : usbd_std.h
  • ISQ_IL : gd32f10x_adc.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LAN8700 : gd32f10x_enet.h
  • local_buffer : usbh_std.c
  • LOCATE_DIEPCTL : usb_regs.h
  • LOCATE_DIEPINTF : usb_regs.h
  • LOCATE_DIEPLEN : usb_regs.h
  • LOCATE_DIEPTFLEN : usb_regs.h
  • LOCATE_DIEPxTFSTAT : usb_regs.h
  • LOCATE_DOEPCTL : usb_regs.h
  • LOCATE_DOEPINTF : usb_regs.h
  • LOCATE_DOEPLEN : usb_regs.h
  • LOCATE_FIFO : usb_regs.h
  • LOCATE_HCHCTL : usb_regs.h
  • LOCATE_HCHINTEN : usb_regs.h
  • LOCATE_HCHINTF : usb_regs.h
  • LOCATE_HCHLEN : usb_regs.h
  • LOWBYTE : usbd_std.h
  • LPMCS_BLSTAT : usbd_regs.h
  • LPMCS_LPMACK : usbd_regs.h
  • LPMCS_LPMEN : usbd_regs.h
  • LPMCS_REMWK : usbd_regs.h
  • LSB_16BIT_MASK : gd32f10x_gpio.c
  • LXTAL_STARTUP_TIMEOUT : gd32f10x_rcu.c


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAC_ADDR0H_ADDR0H : gd32f10x_enet.h
  • MAC_ADDR123H_ADDR123H : gd32f10x_enet.h
  • MAC_CFG_BOL : gd32f10x_enet.h
  • MAC_CFG_IGBS : gd32f10x_enet.h
  • MAC_CFG_MASK : gd32f10x_enet.h
  • MAC_FCTH_RFA : gd32f10x_enet.h
  • MAC_FCTH_RFD : gd32f10x_enet.h
  • MAC_FCTL_MASK : gd32f10x_enet.h
  • MAC_FCTL_PLTS : gd32f10x_enet.h
  • MAC_FCTL_PTM : gd32f10x_enet.h
  • MAC_FCTL_REG_OFFSET : gd32f10x_enet.h
  • MAC_FRMF_PCFRM : gd32f10x_enet.h
  • MAC_INTF_REG_OFFSET : gd32f10x_enet.h
  • MAC_INTMSK_REG_OFFSET : gd32f10x_enet.h
  • MAC_PHY_CTL_CLR : gd32f10x_enet.h
  • MAC_PHY_CTL_PA : gd32f10x_enet.h
  • MAC_PHY_CTL_PR : gd32f10x_enet.h
  • MAC_PHY_DATA_PD : gd32f10x_enet.h
  • MAC_VLT_VLTI : gd32f10x_enet.h
  • MAC_WUM_REG_OFFSET : gd32f10x_enet.h
  • MAX_USBH_STATE_STACK_DEEP : usbh_core.h
  • MAX_USBH_STATE_TABLE_NUM : usbh_core.h
  • MIN : usbd_std.h
  • MSC_CLASS : usbh_core.h
  • MSC_MSCCNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_PROTOCOL : usbh_core.h
  • MSC_RFAECNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_RFCECNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_RGUFCNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_RINTF_REG_OFFSET : gd32f10x_enet.h
  • MSC_RINTMSK_REG_OFFSET : gd32f10x_enet.h
  • MSC_SCCNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_TGFCNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_TINTF_REG_OFFSET : gd32f10x_enet.h
  • MSC_TINTMSK_REG_OFFSET : gd32f10x_enet.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
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  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NODATA_STAGE_TIMEOUT : usb_std.h
  • NPATCFG_ATTHIZ_OFFSET : gd32f10x_exmc.c
  • NPATCFG_ATTHLD_OFFSET : gd32f10x_exmc.c
  • NPATCFG_ATTWAIT_OFFSET : gd32f10x_exmc.c
  • NPCTCFG_COMHIZ_OFFSET : gd32f10x_exmc.c
  • NPCTCFG_COMHLD_OFFSET : gd32f10x_exmc.c
  • NPCTCFG_COMWAIT_OFFSET : gd32f10x_exmc.c
  • NPCTL_ATR : gd32f10x_exmc.h
  • NPCTL_CTR : gd32f10x_exmc.h
  • NPCTL_ECCEN_OFFSET : gd32f10x_exmc.c
  • NPCTL_ECCSZ : gd32f10x_exmc.h
  • NPCTL_NDW : gd32f10x_exmc.h
  • NPCTL_NDWTEN_OFFSET : gd32f10x_exmc.c
  • NULL : usbd_std.h , usb_defines.h
  • NVIC_AIRCR_VECTKEY_MASK : gd32f10x_misc.h
  • nvic_irq_disable() : gd32f10x_misc.h , gd32f10x_misc.c
  • nvic_irq_enable() : gd32f10x_misc.c , gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE0_SUB4 : gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE1_SUB3 : gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE2_SUB2 : gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE3_SUB1 : gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE4_SUB0 : gd32f10x_misc.h
  • nvic_priority_group_set() : gd32f10x_misc.h , gd32f10x_misc.c
  • nvic_vector_table_set() : gd32f10x_misc.c , gd32f10x_misc.h
  • NVIC_VECTTAB_FLASH : gd32f10x_misc.h
  • NVIC_VECTTAB_OFFSET_MASK : gd32f10x_misc.h
  • NVIC_VECTTAB_RAM : gd32f10x_misc.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
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  • i
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB : gd32f10x_fmc.h
  • OB_BOOT_B0 : gd32f10x_fmc.h
  • OB_BOOT_B1 : gd32f10x_fmc.h
  • ob_data_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_data_program() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • OB_DEEPSLEEP_NRST : gd32f10x_fmc.h
  • OB_DEEPSLEEP_RST : gd32f10x_fmc.h
  • ob_erase() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • OB_FWDGT_HW : gd32f10x_fmc.h
  • OB_FWDGT_SW : gd32f10x_fmc.h
  • ob_lock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_security_protection_config() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • OB_SPC : gd32f10x_fmc.h
  • ob_spc_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • OB_SPC_SPC : gd32f10x_fmc.h
  • OB_SPC_SPC_N : gd32f10x_fmc.h
  • OB_STDBY_NRST : gd32f10x_fmc.h
  • OB_STDBY_RST : gd32f10x_fmc.h
  • ob_unlock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • OB_USER : gd32f10x_fmc.h
  • ob_user_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • OB_USER_MASK : gd32f10x_fmc.h
  • OB_USER_USER : gd32f10x_fmc.h
  • OB_USER_USER_N : gd32f10x_fmc.h
  • ob_user_write() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • OB_WP0 : gd32f10x_fmc.h
  • OB_WP0_WP0 : gd32f10x_fmc.h
  • OB_WP1 : gd32f10x_fmc.h
  • OB_WP1_WP1 : gd32f10x_fmc.h
  • OB_WP2 : gd32f10x_fmc.h
  • OB_WP2_WP2 : gd32f10x_fmc.h
  • OB_WP3 : gd32f10x_fmc.h
  • OB_WP3_WP3 : gd32f10x_fmc.h
  • OB_WP_0 : gd32f10x_fmc.h
  • OB_WP_1 : gd32f10x_fmc.h
  • OB_WP_10 : gd32f10x_fmc.h
  • OB_WP_11 : gd32f10x_fmc.h
  • OB_WP_12 : gd32f10x_fmc.h
  • OB_WP_13 : gd32f10x_fmc.h
  • OB_WP_14 : gd32f10x_fmc.h
  • OB_WP_15 : gd32f10x_fmc.h
  • OB_WP_16 : gd32f10x_fmc.h
  • OB_WP_17 : gd32f10x_fmc.h
  • OB_WP_18 : gd32f10x_fmc.h
  • OB_WP_19 : gd32f10x_fmc.h
  • OB_WP_2 : gd32f10x_fmc.h
  • OB_WP_20 : gd32f10x_fmc.h
  • OB_WP_21 : gd32f10x_fmc.h
  • OB_WP_22 : gd32f10x_fmc.h
  • OB_WP_23 : gd32f10x_fmc.h
  • OB_WP_24 : gd32f10x_fmc.h
  • OB_WP_25 : gd32f10x_fmc.h
  • OB_WP_26 : gd32f10x_fmc.h
  • OB_WP_27 : gd32f10x_fmc.h
  • OB_WP_28 : gd32f10x_fmc.h
  • OB_WP_29 : gd32f10x_fmc.h
  • OB_WP_3 : gd32f10x_fmc.h
  • OB_WP_30 : gd32f10x_fmc.h
  • OB_WP_31 : gd32f10x_fmc.h
  • OB_WP_4 : gd32f10x_fmc.h
  • OB_WP_5 : gd32f10x_fmc.h
  • OB_WP_6 : gd32f10x_fmc.h
  • OB_WP_7 : gd32f10x_fmc.h
  • OB_WP_8 : gd32f10x_fmc.h
  • OB_WP_9 : gd32f10x_fmc.h
  • OB_WP_ALL : gd32f10x_fmc.h
  • ob_write_protection_enable() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_write_protection_get() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • OCTL_RCCV : gd32f10x_bkp.h
  • only_state_move() : usbh_core.h , usbh_core.c
  • OSC_STARTUP_TIMEOUT : gd32f10x_rcu.c
  • OTG_MODE : usb_defines.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • _
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • pbuf_reg : usbd_core.h , usbd_core.c
  • PCF_LOCATION1_MASK : gd32f10x_gpio.c
  • PCF_LOCATION2_MASK : gd32f10x_gpio.c
  • PCF_POSITION_MASK : gd32f10x_gpio.c
  • PCF_SWJCFG_MASK : gd32f10x_gpio.c
  • PHY_ADDRESS : gd32f10x_enet.h
  • PHY_AUTONEGO_COMPLETE : gd32f10x_enet.h
  • PHY_AUTONEGOTIATION : gd32f10x_enet.h
  • PHY_CONFIGDELAY : gd32f10x_enet.h
  • PHY_DUPLEX_STATUS : gd32f10x_enet.h
  • PHY_FULLDUPLEX_100M : gd32f10x_enet.h
  • PHY_FULLDUPLEX_10M : gd32f10x_enet.h
  • PHY_HALFDUPLEX_100M : gd32f10x_enet.h
  • PHY_HALFDUPLEX_10M : gd32f10x_enet.h
  • PHY_ISOLATE : gd32f10x_enet.h
  • PHY_JABBER_DETECTION : gd32f10x_enet.h
  • PHY_LINKED_STATUS : gd32f10x_enet.h
  • PHY_LOOPBACK : gd32f10x_enet.h
  • PHY_POWERDOWN : gd32f10x_enet.h
  • PHY_READ_TO : gd32f10x_enet.h
  • PHY_REG_BCR : gd32f10x_enet.h
  • PHY_REG_BSR : gd32f10x_enet.h
  • PHY_RESET : gd32f10x_enet.h
  • PHY_RESETDELAY : gd32f10x_enet.h
  • PHY_RESTART_AUTONEGOTIATION : gd32f10x_enet.h
  • PHY_SPEED_STATUS : gd32f10x_enet.h
  • PHY_SR : gd32f10x_enet.h
  • PHY_TYPE : gd32f10x_enet.h
  • PHY_WRITE_TO : gd32f10x_enet.h
  • PIOTCFG_IOHIZ_OFFSET : gd32f10x_exmc.c
  • PIOTCFG_IOHLD_OFFSET : gd32f10x_exmc.c
  • PIOTCFG_IOWAIT_OFFSET : gd32f10x_exmc.c
  • PLLMF_4 : gd32f10x_rcu.h
  • PMU : gd32f10x_pmu.h
  • pmu_backup_write_disable() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_backup_write_enable() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • PMU_CS : gd32f10x_pmu.h
  • PMU_CS_LVDF : gd32f10x_pmu.h
  • PMU_CS_STBF : gd32f10x_pmu.h
  • PMU_CS_WUF : gd32f10x_pmu.h
  • PMU_CS_WUPEN : gd32f10x_pmu.h
  • PMU_CTL : gd32f10x_pmu.h
  • PMU_CTL_BKPWEN : gd32f10x_pmu.h
  • PMU_CTL_LDOLP : gd32f10x_pmu.h
  • PMU_CTL_LVDEN : gd32f10x_pmu.h
  • PMU_CTL_LVDT : gd32f10x_pmu.h
  • PMU_CTL_STBMOD : gd32f10x_pmu.h
  • PMU_CTL_STBRST : gd32f10x_pmu.h
  • PMU_CTL_WURST : gd32f10x_pmu.h
  • pmu_deinit() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_flag_clear() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_flag_get() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • PMU_FLAG_LVD : gd32f10x_pmu.h
  • PMU_FLAG_RESET_STANDBY : gd32f10x_pmu.h
  • PMU_FLAG_RESET_WAKEUP : gd32f10x_pmu.h
  • PMU_FLAG_STANDBY : gd32f10x_pmu.h
  • PMU_FLAG_WAKEUP : gd32f10x_pmu.h
  • PMU_LDO_LOWPOWER : gd32f10x_pmu.h
  • PMU_LDO_NORMAL : gd32f10x_pmu.h
  • pmu_lvd_disable() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_lvd_select() : gd32f10x_pmu.c , gd32f10x_pmu.h
  • PMU_LVDT_0 : gd32f10x_pmu.h
  • PMU_LVDT_1 : gd32f10x_pmu.h
  • PMU_LVDT_2 : gd32f10x_pmu.h
  • PMU_LVDT_3 : gd32f10x_pmu.h
  • PMU_LVDT_4 : gd32f10x_pmu.h
  • PMU_LVDT_5 : gd32f10x_pmu.h
  • PMU_LVDT_6 : gd32f10x_pmu.h
  • PMU_LVDT_7 : gd32f10x_pmu.h
  • pmu_to_deepsleepmode() : gd32f10x_pmu.c , gd32f10x_pmu.h
  • pmu_to_sleepmode() : gd32f10x_pmu.c , gd32f10x_pmu.h
  • pmu_to_standbymode() : gd32f10x_pmu.c , gd32f10x_pmu.h
  • pmu_wakeup_pin_disable() : gd32f10x_pmu.c , gd32f10x_pmu.h
  • pmu_wakeup_pin_enable() : gd32f10x_pmu.c , gd32f10x_pmu.h
  • PSC_PSC : gd32f10x_fwdgt.h
  • PTP_SSINC_STMSSI : gd32f10x_enet.h
  • PTP_TSUL_TMSUSS : gd32f10x_enet.h
  • PWRCLKCTL_SHCLK : usb_regs.h
  • PWRCLKCTL_SUCLK : usb_regs.h
  • PWRCTL_PWRCTL : gd32f10x_sdio.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
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  • f
  • g
  • h
  • i
  • l
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  • r
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCU : gd32f10x_rcu.h
  • RCU_ADC0 : gd32f10x_rcu.h
  • RCU_ADC0RST : gd32f10x_rcu.h
  • RCU_ADC1 : gd32f10x_rcu.h
  • RCU_ADC1RST : gd32f10x_rcu.h
  • rcu_adc_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_AF : gd32f10x_rcu.h
  • RCU_AFRST : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV1 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV128 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV16 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV2 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV256 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV4 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV512 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV64 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV8 : gd32f10x_rcu.h
  • rcu_ahb_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_AHBEN : gd32f10x_rcu.h
  • RCU_AHBEN_CRCEN : gd32f10x_rcu.h
  • RCU_AHBEN_DMA0EN : gd32f10x_rcu.h
  • RCU_AHBEN_DMA1EN : gd32f10x_rcu.h
  • RCU_AHBEN_EXMCEN : gd32f10x_rcu.h
  • RCU_AHBEN_FMCSPEN : gd32f10x_rcu.h
  • RCU_AHBEN_SDIOEN : gd32f10x_rcu.h
  • RCU_AHBEN_SRAMSPEN : gd32f10x_rcu.h
  • RCU_AHBRST_ENETRST : gd32f10x_rcu.h
  • RCU_AHBRST_USBFSRST : gd32f10x_rcu.h
  • rcu_all_reset_flag_clear() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV1 : gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV16 : gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV2 : gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV4 : gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV8 : gd32f10x_rcu.h
  • rcu_apb1_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_APB1EN : gd32f10x_rcu.h
  • RCU_APB1EN_BKPIEN : gd32f10x_rcu.h
  • RCU_APB1EN_CAN0EN : gd32f10x_rcu.h
  • RCU_APB1EN_CAN1EN : gd32f10x_rcu.h
  • RCU_APB1EN_DACEN : gd32f10x_rcu.h
  • RCU_APB1EN_I2C0EN : gd32f10x_rcu.h
  • RCU_APB1EN_I2C1EN : gd32f10x_rcu.h
  • RCU_APB1EN_PMUEN : gd32f10x_rcu.h
  • RCU_APB1EN_SPI1EN : gd32f10x_rcu.h
  • RCU_APB1EN_SPI2EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER11EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER12EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER13EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER1EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER2EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER3EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER4EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER5EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER6EN : gd32f10x_rcu.h
  • RCU_APB1EN_UART3EN : gd32f10x_rcu.h
  • RCU_APB1EN_UART4EN : gd32f10x_rcu.h
  • RCU_APB1EN_USART1EN : gd32f10x_rcu.h
  • RCU_APB1EN_USART2EN : gd32f10x_rcu.h
  • RCU_APB1EN_USBDEN : gd32f10x_rcu.h
  • RCU_APB1EN_WWDGTEN : gd32f10x_rcu.h
  • RCU_APB1RST : gd32f10x_rcu.h
  • RCU_APB1RST_BKPIRST : gd32f10x_rcu.h
  • RCU_APB1RST_CAN0RST : gd32f10x_rcu.h
  • RCU_APB1RST_CAN1RST : gd32f10x_rcu.h
  • RCU_APB1RST_DACRST : gd32f10x_rcu.h
  • RCU_APB1RST_I2C0RST : gd32f10x_rcu.h
  • RCU_APB1RST_I2C1RST : gd32f10x_rcu.h
  • RCU_APB1RST_PMURST : gd32f10x_rcu.h
  • RCU_APB1RST_SPI1RST : gd32f10x_rcu.h
  • RCU_APB1RST_SPI2RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER11RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER12RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER13RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER1RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER2RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER3RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER4RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER5RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER6RST : gd32f10x_rcu.h
  • RCU_APB1RST_UART3RST : gd32f10x_rcu.h
  • RCU_APB1RST_UART4RST : gd32f10x_rcu.h
  • RCU_APB1RST_USART1RST : gd32f10x_rcu.h
  • RCU_APB1RST_USART2RST : gd32f10x_rcu.h
  • RCU_APB1RST_USBDRST : gd32f10x_rcu.h
  • RCU_APB1RST_WWDGTRST : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV1 : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV16 : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV2 : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV4 : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV8 : gd32f10x_rcu.h
  • rcu_apb2_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_APB2EN : gd32f10x_rcu.h
  • RCU_APB2EN_ADC0EN : gd32f10x_rcu.h
  • RCU_APB2EN_ADC1EN : gd32f10x_rcu.h
  • RCU_APB2EN_AFEN : gd32f10x_rcu.h
  • RCU_APB2EN_PAEN : gd32f10x_rcu.h
  • RCU_APB2EN_PBEN : gd32f10x_rcu.h
  • RCU_APB2EN_PCEN : gd32f10x_rcu.h
  • RCU_APB2EN_PDEN : gd32f10x_rcu.h
  • RCU_APB2EN_PEEN : gd32f10x_rcu.h
  • RCU_APB2EN_PFEN : gd32f10x_rcu.h
  • RCU_APB2EN_PGEN : gd32f10x_rcu.h
  • RCU_APB2EN_SPI0EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER0EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER10EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER7EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER8EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER9EN : gd32f10x_rcu.h
  • RCU_APB2EN_USART0EN : gd32f10x_rcu.h
  • RCU_APB2RST : gd32f10x_rcu.h
  • RCU_APB2RST_ADC0RST : gd32f10x_rcu.h
  • RCU_APB2RST_ADC1RST : gd32f10x_rcu.h
  • RCU_APB2RST_AFRST : gd32f10x_rcu.h
  • RCU_APB2RST_PARST : gd32f10x_rcu.h
  • RCU_APB2RST_PBRST : gd32f10x_rcu.h
  • RCU_APB2RST_PCRST : gd32f10x_rcu.h
  • RCU_APB2RST_PDRST : gd32f10x_rcu.h
  • RCU_APB2RST_PERST : gd32f10x_rcu.h
  • RCU_APB2RST_PFRST : gd32f10x_rcu.h
  • RCU_APB2RST_PGRST : gd32f10x_rcu.h
  • RCU_APB2RST_SPI0RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER0RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER10RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER7RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER8RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER9RST : gd32f10x_rcu.h
  • RCU_APB2RST_USART0RST : gd32f10x_rcu.h
  • RCU_BDCTL : gd32f10x_rcu.h
  • RCU_BDCTL_BKPRST : gd32f10x_rcu.h
  • RCU_BDCTL_LXTALBPS : gd32f10x_rcu.h
  • RCU_BDCTL_LXTALEN : gd32f10x_rcu.h
  • RCU_BDCTL_LXTALSTB : gd32f10x_rcu.h
  • RCU_BDCTL_RTCEN : gd32f10x_rcu.h
  • RCU_BDCTL_RTCSRC : gd32f10x_rcu.h
  • RCU_BIT_POS : gd32f10x_rcu.h
  • rcu_bkp_reset_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_bkp_reset_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_BKPI : gd32f10x_rcu.h
  • RCU_BKPIRST : gd32f10x_rcu.h
  • RCU_CAN0 : gd32f10x_rcu.h
  • RCU_CAN0RST : gd32f10x_rcu.h
  • RCU_CAN1 : gd32f10x_rcu.h
  • RCU_CAN1RST : gd32f10x_rcu.h
  • RCU_CFG0 : gd32f10x_rcu.h
  • RCU_CFG0_ADCPSC : gd32f10x_rcu.h
  • RCU_CFG0_ADCPSC_2 : gd32f10x_rcu.h
  • RCU_CFG0_AHBPSC : gd32f10x_rcu.h
  • RCU_CFG0_APB1PSC : gd32f10x_rcu.h
  • RCU_CFG0_APB2PSC : gd32f10x_rcu.h
  • RCU_CFG0_CKOUT0SEL : gd32f10x_rcu.h
  • RCU_CFG0_PLLMF : gd32f10x_rcu.h
  • RCU_CFG0_PLLMF_4 : gd32f10x_rcu.h
  • RCU_CFG0_PLLSEL : gd32f10x_rcu.h
  • RCU_CFG0_PREDV0 : gd32f10x_rcu.h
  • RCU_CFG0_SCS : gd32f10x_rcu.h
  • RCU_CFG0_SCSS : gd32f10x_rcu.h
  • RCU_CFG0_USBDPSC : gd32f10x_rcu.h
  • RCU_CFG1_I2S1SEL : gd32f10x_rcu.h
  • RCU_CFG1_I2S2SEL : gd32f10x_rcu.h
  • RCU_CFG1_PLL1MF : gd32f10x_rcu.h
  • RCU_CFG1_PLL2MF : gd32f10x_rcu.h
  • RCU_CFG1_PREDV0 : gd32f10x_rcu.h
  • RCU_CFG1_PREDV0SEL : gd32f10x_rcu.h
  • RCU_CFG1_PREDV1 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV12 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV16 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV2 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV4 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV6 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV8 : gd32f10x_rcu.h
  • rcu_ckout0_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_CKOUT0SRC_CKPLL1 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_CKPLL2 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_CKPLL2_DIV2 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_CKPLL_DIV2 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_CKSYS : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_EXT1 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_HXTAL : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_IRC8M : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_NONE : gd32f10x_rcu.h
  • RCU_CKSYSSRC_HXTAL : gd32f10x_rcu.h
  • RCU_CKSYSSRC_IRC8M : gd32f10x_rcu.h
  • RCU_CKSYSSRC_PLL : gd32f10x_rcu.h
  • RCU_CKUSB_CKPLL_DIV1 : gd32f10x_rcu.h
  • RCU_CKUSB_CKPLL_DIV1_5 : gd32f10x_rcu.h
  • RCU_CKUSB_CKPLL_DIV2 : gd32f10x_rcu.h
  • RCU_CKUSB_CKPLL_DIV2_5 : gd32f10x_rcu.h
  • rcu_clock_freq_enum : gd32f10x_rcu.h
  • rcu_clock_freq_get() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_CRC : gd32f10x_rcu.h
  • RCU_CTL : gd32f10x_rcu.h
  • RCU_CTL_CKMEN : gd32f10x_rcu.h
  • RCU_CTL_HXTALBPS : gd32f10x_rcu.h
  • RCU_CTL_HXTALEN : gd32f10x_rcu.h
  • RCU_CTL_HXTALSTB : gd32f10x_rcu.h
  • RCU_CTL_IRC8MADJ : gd32f10x_rcu.h
  • RCU_CTL_IRC8MCALIB : gd32f10x_rcu.h
  • RCU_CTL_IRC8MEN : gd32f10x_rcu.h
  • RCU_CTL_IRC8MSTB : gd32f10x_rcu.h
  • RCU_CTL_PLLEN : gd32f10x_rcu.h
  • RCU_CTL_PLLSTB : gd32f10x_rcu.h
  • RCU_DAC : gd32f10x_rcu.h
  • RCU_DACRST : gd32f10x_rcu.h
  • RCU_DEEPSLEEP_V_0_9 : gd32f10x_rcu.h
  • RCU_DEEPSLEEP_V_1_0 : gd32f10x_rcu.h
  • RCU_DEEPSLEEP_V_1_1 : gd32f10x_rcu.h
  • RCU_DEEPSLEEP_V_1_2 : gd32f10x_rcu.h
  • rcu_deepsleep_voltage_set() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_deinit() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_DMA0 : gd32f10x_rcu.h
  • RCU_DMA1 : gd32f10x_rcu.h
  • RCU_DSV : gd32f10x_rcu.h
  • RCU_DSV_DSLPVS : gd32f10x_rcu.h
  • RCU_ENETRST : gd32f10x_rcu.h
  • RCU_EXMC : gd32f10x_rcu.h
  • rcu_flag_enum : gd32f10x_rcu.h
  • RCU_FLAG_EPRST : gd32f10x_rcu.h
  • RCU_FLAG_FWDGTRST : gd32f10x_rcu.h
  • rcu_flag_get() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_FLAG_HXTALSTB : gd32f10x_rcu.h
  • RCU_FLAG_IRC40KSTB : gd32f10x_rcu.h
  • RCU_FLAG_IRC8MSTB : gd32f10x_rcu.h
  • RCU_FLAG_LPRST : gd32f10x_rcu.h
  • RCU_FLAG_LXTALSTB : gd32f10x_rcu.h
  • RCU_FLAG_PLL1STB : gd32f10x_rcu.h
  • RCU_FLAG_PLL2STB : gd32f10x_rcu.h
  • RCU_FLAG_PLLSTB : gd32f10x_rcu.h
  • RCU_FLAG_PORRST : gd32f10x_rcu.h
  • RCU_FLAG_SWRST : gd32f10x_rcu.h
  • RCU_FLAG_WWDGTRST : gd32f10x_rcu.h
  • RCU_FMC_SLP : gd32f10x_rcu.h
  • RCU_GPIOA : gd32f10x_rcu.h
  • RCU_GPIOARST : gd32f10x_rcu.h
  • RCU_GPIOB : gd32f10x_rcu.h
  • RCU_GPIOBRST : gd32f10x_rcu.h
  • RCU_GPIOC : gd32f10x_rcu.h
  • RCU_GPIOCRST : gd32f10x_rcu.h
  • RCU_GPIOD : gd32f10x_rcu.h
  • RCU_GPIODRST : gd32f10x_rcu.h
  • RCU_GPIOE : gd32f10x_rcu.h
  • RCU_GPIOERST : gd32f10x_rcu.h
  • RCU_GPIOF : gd32f10x_rcu.h
  • RCU_GPIOFRST : gd32f10x_rcu.h
  • RCU_GPIOG : gd32f10x_rcu.h
  • RCU_GPIOGRST : gd32f10x_rcu.h
  • RCU_HXTAL : gd32f10x_rcu.h
  • rcu_hxtal_clock_monitor_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_hxtal_clock_monitor_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_I2C0 : gd32f10x_rcu.h
  • RCU_I2C0RST : gd32f10x_rcu.h
  • RCU_I2C1 : gd32f10x_rcu.h
  • RCU_I2C1RST : gd32f10x_rcu.h
  • rcu_i2s1_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_I2S1SRC_CKPLL2_MUL2 : gd32f10x_rcu.h
  • RCU_I2S1SRC_CKSYS : gd32f10x_rcu.h
  • rcu_i2s2_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_I2S2SRC_CKPLL2_MUL2 : gd32f10x_rcu.h
  • RCU_I2S2SRC_CKSYS : gd32f10x_rcu.h
  • RCU_INT : gd32f10x_rcu.h
  • RCU_INT_CKMIC : gd32f10x_rcu.h
  • RCU_INT_CKMIF : gd32f10x_rcu.h
  • rcu_int_enum : gd32f10x_rcu.h
  • RCU_INT_FLAG_CKM : gd32f10x_rcu.h
  • RCU_INT_FLAG_CKM_CLR : gd32f10x_rcu.h
  • rcu_int_flag_clear_enum : gd32f10x_rcu.h
  • rcu_int_flag_enum : gd32f10x_rcu.h
  • RCU_INT_FLAG_HXTALSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_HXTALSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_IRC40KSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_IRC40KSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_IRC8MSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_IRC8MSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_LXTALSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_LXTALSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLL1STB : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLL1STB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLL2STB : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLL2STB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLLSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLLSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_HXTALSTB : gd32f10x_rcu.h
  • RCU_INT_HXTALSTBIC : gd32f10x_rcu.h
  • RCU_INT_HXTALSTBIE : gd32f10x_rcu.h
  • RCU_INT_HXTALSTBIF : gd32f10x_rcu.h
  • RCU_INT_IRC40KSTB : gd32f10x_rcu.h
  • RCU_INT_IRC40KSTBIC : gd32f10x_rcu.h
  • RCU_INT_IRC40KSTBIE : gd32f10x_rcu.h
  • RCU_INT_IRC40KSTBIF : gd32f10x_rcu.h
  • RCU_INT_IRC8MSTB : gd32f10x_rcu.h
  • RCU_INT_IRC8MSTBIC : gd32f10x_rcu.h
  • RCU_INT_IRC8MSTBIE : gd32f10x_rcu.h
  • RCU_INT_IRC8MSTBIF : gd32f10x_rcu.h
  • RCU_INT_LXTALSTB : gd32f10x_rcu.h
  • RCU_INT_LXTALSTBIC : gd32f10x_rcu.h
  • RCU_INT_LXTALSTBIE : gd32f10x_rcu.h
  • RCU_INT_LXTALSTBIF : gd32f10x_rcu.h
  • RCU_INT_PLL1STB : gd32f10x_rcu.h
  • RCU_INT_PLL2STB : gd32f10x_rcu.h
  • RCU_INT_PLLSTB : gd32f10x_rcu.h
  • RCU_INT_PLLSTBIC : gd32f10x_rcu.h
  • RCU_INT_PLLSTBIE : gd32f10x_rcu.h
  • RCU_INT_PLLSTBIF : gd32f10x_rcu.h
  • rcu_interrupt_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_interrupt_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_interrupt_flag_clear() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_interrupt_flag_get() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_IRC40K : gd32f10x_rcu.h
  • RCU_IRC8M : gd32f10x_rcu.h
  • rcu_irc8m_adjust_value_set() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_LXTAL : gd32f10x_rcu.h
  • rcu_osci_bypass_mode_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_osci_bypass_mode_enable() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • rcu_osci_off() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_osci_on() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_osci_stab_wait() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_osci_type_enum : gd32f10x_rcu.h
  • rcu_periph_clock_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_clock_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_clock_sleep_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_clock_sleep_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_enum : gd32f10x_rcu.h
  • rcu_periph_reset_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_reset_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_reset_enum : gd32f10x_rcu.h
  • rcu_periph_sleep_enum : gd32f10x_rcu.h
  • RCU_PLL1_CK : gd32f10x_rcu.h
  • RCU_PLL1_MUL10 : gd32f10x_rcu.h
  • RCU_PLL1_MUL11 : gd32f10x_rcu.h
  • RCU_PLL1_MUL12 : gd32f10x_rcu.h
  • RCU_PLL1_MUL13 : gd32f10x_rcu.h
  • RCU_PLL1_MUL14 : gd32f10x_rcu.h
  • RCU_PLL1_MUL15 : gd32f10x_rcu.h
  • RCU_PLL1_MUL16 : gd32f10x_rcu.h
  • RCU_PLL1_MUL20 : gd32f10x_rcu.h
  • RCU_PLL1_MUL8 : gd32f10x_rcu.h
  • RCU_PLL1_MUL9 : gd32f10x_rcu.h
  • RCU_PLL2_CK : gd32f10x_rcu.h
  • RCU_PLL2_MUL10 : gd32f10x_rcu.h
  • RCU_PLL2_MUL11 : gd32f10x_rcu.h
  • RCU_PLL2_MUL12 : gd32f10x_rcu.h
  • RCU_PLL2_MUL13 : gd32f10x_rcu.h
  • RCU_PLL2_MUL14 : gd32f10x_rcu.h
  • RCU_PLL2_MUL15 : gd32f10x_rcu.h
  • RCU_PLL2_MUL16 : gd32f10x_rcu.h
  • RCU_PLL2_MUL20 : gd32f10x_rcu.h
  • RCU_PLL2_MUL8 : gd32f10x_rcu.h
  • RCU_PLL2_MUL9 : gd32f10x_rcu.h
  • RCU_PLL_CK : gd32f10x_rcu.h
  • rcu_pll_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_PLL_MUL10 : gd32f10x_rcu.h
  • RCU_PLL_MUL11 : gd32f10x_rcu.h
  • RCU_PLL_MUL12 : gd32f10x_rcu.h
  • RCU_PLL_MUL13 : gd32f10x_rcu.h
  • RCU_PLL_MUL14 : gd32f10x_rcu.h
  • RCU_PLL_MUL15 : gd32f10x_rcu.h
  • RCU_PLL_MUL16 : gd32f10x_rcu.h
  • RCU_PLL_MUL17 : gd32f10x_rcu.h
  • RCU_PLL_MUL18 : gd32f10x_rcu.h
  • RCU_PLL_MUL19 : gd32f10x_rcu.h
  • RCU_PLL_MUL2 : gd32f10x_rcu.h
  • RCU_PLL_MUL20 : gd32f10x_rcu.h
  • RCU_PLL_MUL21 : gd32f10x_rcu.h
  • RCU_PLL_MUL22 : gd32f10x_rcu.h
  • RCU_PLL_MUL23 : gd32f10x_rcu.h
  • RCU_PLL_MUL24 : gd32f10x_rcu.h
  • RCU_PLL_MUL25 : gd32f10x_rcu.h
  • RCU_PLL_MUL26 : gd32f10x_rcu.h
  • RCU_PLL_MUL27 : gd32f10x_rcu.h
  • RCU_PLL_MUL28 : gd32f10x_rcu.h
  • RCU_PLL_MUL29 : gd32f10x_rcu.h
  • RCU_PLL_MUL3 : gd32f10x_rcu.h
  • RCU_PLL_MUL30 : gd32f10x_rcu.h
  • RCU_PLL_MUL31 : gd32f10x_rcu.h
  • RCU_PLL_MUL32 : gd32f10x_rcu.h
  • RCU_PLL_MUL4 : gd32f10x_rcu.h
  • RCU_PLL_MUL5 : gd32f10x_rcu.h
  • RCU_PLL_MUL6 : gd32f10x_rcu.h
  • RCU_PLL_MUL7 : gd32f10x_rcu.h
  • RCU_PLL_MUL8 : gd32f10x_rcu.h
  • RCU_PLL_MUL9 : gd32f10x_rcu.h
  • RCU_PLLSRC_HXTAL : gd32f10x_rcu.h
  • RCU_PLLSRC_IRC8M_DIV2 : gd32f10x_rcu.h
  • RCU_PMU : gd32f10x_rcu.h
  • RCU_PMURST : gd32f10x_rcu.h
  • rcu_predv0_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_PREDV0_DIV1 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV10 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV11 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV12 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV13 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV14 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV15 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV16 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV2 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV3 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV4 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV5 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV6 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV7 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV8 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV9 : gd32f10x_rcu.h
  • RCU_PREDV0SRC_CKPLL1 : gd32f10x_rcu.h
  • RCU_PREDV0SRC_HXTAL : gd32f10x_rcu.h
  • RCU_PREDV1_DIV1 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV10 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV11 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV12 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV13 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV14 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV15 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV16 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV2 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV3 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV4 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV5 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV6 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV7 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV8 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV9 : gd32f10x_rcu.h
  • RCU_REG_VAL : gd32f10x_rcu.h
  • RCU_REGIDX_BIT : gd32f10x_rcu.h
  • RCU_RSTSCK : gd32f10x_rcu.h
  • RCU_RSTSCK_EPRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_FWDGTRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_IRC40KEN : gd32f10x_rcu.h
  • RCU_RSTSCK_IRC40KSTB : gd32f10x_rcu.h
  • RCU_RSTSCK_LPRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_PORRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_RSTFC : gd32f10x_rcu.h
  • RCU_RSTSCK_SWRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_WWDGTRSTF : gd32f10x_rcu.h
  • RCU_RTC : gd32f10x_rcu.h
  • rcu_rtc_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_RTCSRC_HXTAL_DIV_128 : gd32f10x_rcu.h
  • RCU_RTCSRC_IRC40K : gd32f10x_rcu.h
  • RCU_RTCSRC_LXTAL : gd32f10x_rcu.h
  • RCU_RTCSRC_NONE : gd32f10x_rcu.h
  • RCU_SCSS_HXTAL : gd32f10x_rcu.h
  • RCU_SCSS_IRC8M : gd32f10x_rcu.h
  • RCU_SCSS_PLL : gd32f10x_rcu.h
  • RCU_SDIO : gd32f10x_rcu.h
  • RCU_SPI0 : gd32f10x_rcu.h
  • RCU_SPI0RST : gd32f10x_rcu.h
  • RCU_SPI1 : gd32f10x_rcu.h
  • RCU_SPI1RST : gd32f10x_rcu.h
  • RCU_SPI2 : gd32f10x_rcu.h
  • RCU_SPI2RST : gd32f10x_rcu.h
  • RCU_SRAM_SLP : gd32f10x_rcu.h
  • rcu_system_clock_source_config() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • rcu_system_clock_source_get() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • RCU_TIMER0 : gd32f10x_rcu.h
  • RCU_TIMER0RST : gd32f10x_rcu.h
  • RCU_TIMER1 : gd32f10x_rcu.h
  • RCU_TIMER10 : gd32f10x_rcu.h
  • RCU_TIMER10RST : gd32f10x_rcu.h
  • RCU_TIMER11 : gd32f10x_rcu.h
  • RCU_TIMER11RST : gd32f10x_rcu.h
  • RCU_TIMER12 : gd32f10x_rcu.h
  • RCU_TIMER12RST : gd32f10x_rcu.h
  • RCU_TIMER13 : gd32f10x_rcu.h
  • RCU_TIMER13RST : gd32f10x_rcu.h
  • RCU_TIMER1RST : gd32f10x_rcu.h
  • RCU_TIMER2 : gd32f10x_rcu.h
  • RCU_TIMER2RST : gd32f10x_rcu.h
  • RCU_TIMER3 : gd32f10x_rcu.h
  • RCU_TIMER3RST : gd32f10x_rcu.h
  • RCU_TIMER4 : gd32f10x_rcu.h
  • RCU_TIMER4RST : gd32f10x_rcu.h
  • RCU_TIMER5 : gd32f10x_rcu.h
  • RCU_TIMER5RST : gd32f10x_rcu.h
  • RCU_TIMER6 : gd32f10x_rcu.h
  • RCU_TIMER6RST : gd32f10x_rcu.h
  • RCU_TIMER7 : gd32f10x_rcu.h
  • RCU_TIMER7RST : gd32f10x_rcu.h
  • RCU_TIMER8 : gd32f10x_rcu.h
  • RCU_TIMER8RST : gd32f10x_rcu.h
  • RCU_TIMER9 : gd32f10x_rcu.h
  • RCU_TIMER9RST : gd32f10x_rcu.h
  • RCU_UART3 : gd32f10x_rcu.h
  • RCU_UART3RST : gd32f10x_rcu.h
  • RCU_UART4 : gd32f10x_rcu.h
  • RCU_UART4RST : gd32f10x_rcu.h
  • RCU_USART0 : gd32f10x_rcu.h
  • RCU_USART0RST : gd32f10x_rcu.h
  • RCU_USART1 : gd32f10x_rcu.h
  • RCU_USART1RST : gd32f10x_rcu.h
  • RCU_USART2 : gd32f10x_rcu.h
  • RCU_USART2RST : gd32f10x_rcu.h
  • rcu_usb_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • RCU_USBD : gd32f10x_rcu.h
  • RCU_USBDRST : gd32f10x_rcu.h
  • RCU_USBFSRST : gd32f10x_rcu.h
  • RCU_WWDGT : gd32f10x_rcu.h
  • RCU_WWDGTRST : gd32f10x_rcu.h
  • RDES0_FRML : gd32f10x_enet.h
  • RDES4_IPPLDT : gd32f10x_enet.h
  • RDES4_PTPMT : gd32f10x_enet.h
  • resume_mcu() : usbd_pwr.h , usbd_pwr.c
  • RFIFO0_REG_OFFSET : gd32f10x_can.h
  • RFIFO1_REG_OFFSET : gd32f10x_can.h
  • RFIFOMDATA0_DB0 : gd32f10x_can.h
  • RFIFOMDATA0_DB1 : gd32f10x_can.h
  • RFIFOMDATA0_DB2 : gd32f10x_can.h
  • RFIFOMDATA0_DB3 : gd32f10x_can.h
  • RFIFOMDATA1_DB4 : gd32f10x_can.h
  • RFIFOMDATA1_DB5 : gd32f10x_can.h
  • RFIFOMDATA1_DB6 : gd32f10x_can.h
  • RFIFOMDATA1_DB7 : gd32f10x_can.h
  • RFIFOMI_EFID : gd32f10x_can.h
  • RFIFOMI_SFID : gd32f10x_can.h
  • RFIFOMP_DLENC : gd32f10x_can.h
  • RFIFOMP_FI : gd32f10x_can.h
  • RLD_RLD : gd32f10x_fwdgt.c
  • RSQ0_RL : gd32f10x_adc.h
  • RSTSCK_REG_OFFSET : gd32f10x_rcu.h
  • RTC : gd32f10x_rtc.h
  • rtc_alarm_config() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • RTC_ALRMH : gd32f10x_rtc.h
  • RTC_ALRMH_ALRM : gd32f10x_rtc.h
  • RTC_ALRML : gd32f10x_rtc.h
  • RTC_ALRML_ALRM : gd32f10x_rtc.h
  • RTC_CNTH : gd32f10x_rtc.h
  • RTC_CNTH_CNT : gd32f10x_rtc.h
  • RTC_CNTL : gd32f10x_rtc.h
  • RTC_CNTL_CNT : gd32f10x_rtc.h
  • rtc_configuration_mode_enter() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • rtc_configuration_mode_exit() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • rtc_counter_get() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • rtc_counter_set() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • RTC_CTL : gd32f10x_rtc.h
  • RTC_CTL_ALRMIF : gd32f10x_rtc.h
  • RTC_CTL_CMF : gd32f10x_rtc.h
  • RTC_CTL_LWOFF : gd32f10x_rtc.h
  • RTC_CTL_OVIF : gd32f10x_rtc.h
  • RTC_CTL_RSYNF : gd32f10x_rtc.h
  • RTC_CTL_SCIF : gd32f10x_rtc.h
  • RTC_DIVH : gd32f10x_rtc.h
  • RTC_DIVH_DIV : gd32f10x_rtc.h
  • rtc_divider_get() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • RTC_DIVL : gd32f10x_rtc.h
  • RTC_DIVL_DIV : gd32f10x_rtc.h
  • RTC_FLAG_ALARM : gd32f10x_rtc.h
  • rtc_flag_clear() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • rtc_flag_get() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • RTC_FLAG_LWOF : gd32f10x_rtc.h
  • RTC_FLAG_OVERFLOW : gd32f10x_rtc.h
  • RTC_FLAG_RSYN : gd32f10x_rtc.h
  • RTC_FLAG_SECOND : gd32f10x_rtc.h
  • RTC_HIGH_VALUE : gd32f10x_rtc.h
  • RTC_INT_ALARM : gd32f10x_rtc.h
  • RTC_INT_OVERFLOW : gd32f10x_rtc.h
  • RTC_INT_SECOND : gd32f10x_rtc.h
  • RTC_INTEN : gd32f10x_rtc.h
  • RTC_INTEN_ALRMIE : gd32f10x_rtc.h
  • RTC_INTEN_OVIE : gd32f10x_rtc.h
  • RTC_INTEN_SCIE : gd32f10x_rtc.h
  • rtc_interrupt_disable() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • rtc_interrupt_enable() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • RTC_LOW_VALUE : gd32f10x_rtc.h
  • rtc_lwoff_wait() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • RTC_OUTPUT_ALARM_PULSE : gd32f10x_bkp.h
  • RTC_OUTPUT_SECOND_PULSE : gd32f10x_bkp.h
  • rtc_prescaler_set() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • RTC_PSCH : gd32f10x_rtc.h
  • RTC_PSCH_PSC : gd32f10x_rtc.h
  • RTC_PSCL : gd32f10x_rtc.h
  • RTC_PSCL_PSC : gd32f10x_rtc.h
  • rtc_register_sync_wait() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • RX_MAX_DATA_LENGTH : usb_core.h
  • RXCNT_OFFSET : usbd_regs.h
  • RXDESC_BUFFER_1_ADDR : gd32f10x_enet.h
  • RXDESC_BUFFER_1_SIZE : gd32f10x_enet.h
  • RXDESC_BUFFER_2_SIZE : gd32f10x_enet.h
  • RXDESC_FRAME_LENGTH : gd32f10x_enet.h
  • RXSTAT_DATA_UPDT : usb_defines.h
  • RXSTAT_GOUT_NAK : usb_defines.h
  • RXSTAT_SETUP_COMP : usb_defines.h
  • RXSTAT_SETUP_UPDT : usb_defines.h
  • RXSTAT_XFER_COMP : usb_defines.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SADDR0_ADDFORMAT : gd32f10x_i2c.h
  • SAMPTX_SPT : gd32f10x_adc.h
  • SCB_LPM_DEEPSLEEP : gd32f10x_misc.h
  • SCB_LPM_SLEEP_EXIT_ISR : gd32f10x_misc.h
  • SCB_LPM_WAKE_BY_ALL_INT : gd32f10x_misc.h
  • SCB_SCR_SEVONPEND : gd32f10x_misc.h
  • SCB_SCR_SLEEPDEEP : gd32f10x_misc.h
  • SCB_SCR_SLEEPONEXIT : gd32f10x_misc.h
  • scd_begin() : usbh_core.h , usbh_core.c
  • scd_event_handle() : usbh_core.h , usbh_core.c
  • scd_init() : usbh_core.h , usbh_core.c
  • scd_state_move() : usbh_core.c , usbh_core.h
  • scd_table_pop() : usbh_core.h , usbh_core.c
  • scd_table_push() : usbh_core.h , usbh_core.c
  • scd_table_regist() : usbh_core.h , usbh_core.c
  • SDIO : gd32f10x_sdio.h
  • sdio_bus_mode_set() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_BUSMODE_1BIT : gd32f10x_sdio.h
  • SDIO_BUSMODE_4BIT : gd32f10x_sdio.h
  • SDIO_BUSMODE_8BIT : gd32f10x_sdio.h
  • sdio_ceata_command_completion_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_ceata_command_completion_enable() : gd32f10x_sdio.c , gd32f10x_sdio.h
  • sdio_ceata_command_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_ceata_command_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_ceata_interrupt_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_ceata_interrupt_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_CLKCTL : gd32f10x_sdio.h
  • SDIO_CLKCTL_BUSMODE : gd32f10x_sdio.h
  • SDIO_CLKCTL_CLKBYP : gd32f10x_sdio.h
  • SDIO_CLKCTL_CLKEDGE : gd32f10x_sdio.h
  • SDIO_CLKCTL_CLKEN : gd32f10x_sdio.h
  • SDIO_CLKCTL_CLKPWRSAV : gd32f10x_sdio.h
  • SDIO_CLKCTL_DIV : gd32f10x_sdio.h
  • SDIO_CLKCTL_HWCLKEN : gd32f10x_sdio.h
  • sdio_clock_config() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_clock_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_clock_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_CLOCKBYPASS_DISABLE : gd32f10x_sdio.h
  • SDIO_CLOCKBYPASS_ENABLE : gd32f10x_sdio.h
  • SDIO_CLOCKPWRSAVE_DISABLE : gd32f10x_sdio.h
  • SDIO_CLOCKPWRSAVE_ENABLE : gd32f10x_sdio.h
  • SDIO_CMDAGMT : gd32f10x_sdio.h
  • SDIO_CMDAGMT_CMDAGMT : gd32f10x_sdio.h
  • SDIO_CMDCTL : gd32f10x_sdio.h
  • SDIO_CMDCTL_ATAEN : gd32f10x_sdio.h
  • SDIO_CMDCTL_CMDIDX : gd32f10x_sdio.h
  • SDIO_CMDCTL_CMDRESP : gd32f10x_sdio.h
  • SDIO_CMDCTL_CSMEN : gd32f10x_sdio.h
  • SDIO_CMDCTL_ENCMDC : gd32f10x_sdio.h
  • SDIO_CMDCTL_INTWAIT : gd32f10x_sdio.h
  • SDIO_CMDCTL_NINTEN : gd32f10x_sdio.h
  • SDIO_CMDCTL_SUSPEND : gd32f10x_sdio.h
  • SDIO_CMDCTL_WAITDEND : gd32f10x_sdio.h
  • sdio_command_index_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_command_response_config() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_csm_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_csm_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_config() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_counter_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_read() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_transfer_config() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_write() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_DATABLOCKSIZE_1024BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_128BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_16384BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_16BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_1BYTE : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_2048BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_256BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_2BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_32BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_4096BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_4BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_512BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_64BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_8192BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_8BYTES : gd32f10x_sdio.h
  • SDIO_DATACNT : gd32f10x_sdio.h
  • SDIO_DATACTL : gd32f10x_sdio.h
  • SDIO_DATACTL_BLKSZ : gd32f10x_sdio.h
  • SDIO_DATACTL_DATADIR : gd32f10x_sdio.h
  • SDIO_DATACTL_DATAEN : gd32f10x_sdio.h
  • SDIO_DATACTL_DMAEN : gd32f10x_sdio.h
  • SDIO_DATACTL_IOEN : gd32f10x_sdio.h
  • SDIO_DATACTL_RWEN : gd32f10x_sdio.h
  • SDIO_DATACTL_RWSTOP : gd32f10x_sdio.h
  • SDIO_DATACTL_RWTYPE : gd32f10x_sdio.h
  • SDIO_DATACTL_TRANSMOD : gd32f10x_sdio.h
  • SDIO_DATALEN : gd32f10x_sdio.h
  • SDIO_DATALEN_DATALEN : gd32f10x_sdio.h
  • SDIO_DATATO : gd32f10x_sdio.h
  • SDIO_DATATO_DATATO : gd32f10x_sdio.h
  • sdio_deinit() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_dma_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_dma_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_dsm_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_dsm_enable() : gd32f10x_sdio.c , gd32f10x_sdio.h
  • SDIO_FIFO : gd32f10x_sdio.h
  • sdio_fifo_counter_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_FIFO_FIFODT : gd32f10x_sdio.h
  • SDIO_FIFOCNT : gd32f10x_sdio.h
  • SDIO_FLAG_ATAEND : gd32f10x_sdio.h
  • SDIO_FLAG_CCRCERR : gd32f10x_sdio.h
  • sdio_flag_clear() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_FLAG_CMDRECV : gd32f10x_sdio.h
  • SDIO_FLAG_CMDRUN : gd32f10x_sdio.h
  • SDIO_FLAG_CMDSEND : gd32f10x_sdio.h
  • SDIO_FLAG_CMDTMOUT : gd32f10x_sdio.h
  • SDIO_FLAG_DTBLKEND : gd32f10x_sdio.h
  • SDIO_FLAG_DTCRCERR : gd32f10x_sdio.h
  • SDIO_FLAG_DTEND : gd32f10x_sdio.h
  • SDIO_FLAG_DTTMOUT : gd32f10x_sdio.h
  • sdio_flag_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_FLAG_RFE : gd32f10x_sdio.h
  • SDIO_FLAG_RFF : gd32f10x_sdio.h
  • SDIO_FLAG_RFH : gd32f10x_sdio.h
  • SDIO_FLAG_RXDTVAL : gd32f10x_sdio.h
  • SDIO_FLAG_RXORE : gd32f10x_sdio.h
  • SDIO_FLAG_RXRUN : gd32f10x_sdio.h
  • SDIO_FLAG_SDIOINT : gd32f10x_sdio.h
  • SDIO_FLAG_STBITE : gd32f10x_sdio.h
  • SDIO_FLAG_TFE : gd32f10x_sdio.h
  • SDIO_FLAG_TFF : gd32f10x_sdio.h
  • SDIO_FLAG_TFH : gd32f10x_sdio.h
  • SDIO_FLAG_TXDTVAL : gd32f10x_sdio.h
  • SDIO_FLAG_TXRUN : gd32f10x_sdio.h
  • SDIO_FLAG_TXURE : gd32f10x_sdio.h
  • sdio_hardware_clock_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_hardware_clock_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_INT_ATAEND : gd32f10x_sdio.h
  • SDIO_INT_CCRCERR : gd32f10x_sdio.h
  • SDIO_INT_CMDRECV : gd32f10x_sdio.h
  • SDIO_INT_CMDRUN : gd32f10x_sdio.h
  • SDIO_INT_CMDSEND : gd32f10x_sdio.h
  • SDIO_INT_CMDTMOUT : gd32f10x_sdio.h
  • SDIO_INT_DTBLKEND : gd32f10x_sdio.h
  • SDIO_INT_DTCRCERR : gd32f10x_sdio.h
  • SDIO_INT_DTEND : gd32f10x_sdio.h
  • SDIO_INT_DTTMOUT : gd32f10x_sdio.h
  • SDIO_INT_FLAG_ATAEND : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CCRCERR : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CMDRECV : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CMDRUN : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CMDSEND : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CMDTMOUT : gd32f10x_sdio.h
  • SDIO_INT_FLAG_DTBLKEND : gd32f10x_sdio.h
  • SDIO_INT_FLAG_DTCRCERR : gd32f10x_sdio.h
  • SDIO_INT_FLAG_DTEND : gd32f10x_sdio.h
  • SDIO_INT_FLAG_DTTMOUT : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RFE : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RFF : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RFH : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RXDTVAL : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RXORE : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RXRUN : gd32f10x_sdio.h
  • SDIO_INT_FLAG_SDIOINT : gd32f10x_sdio.h
  • SDIO_INT_FLAG_STBITE : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TFE : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TFF : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TFH : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TXDTVAL : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TXRUN : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TXURE : gd32f10x_sdio.h
  • SDIO_INT_RFE : gd32f10x_sdio.h
  • SDIO_INT_RFF : gd32f10x_sdio.h
  • SDIO_INT_RFH : gd32f10x_sdio.h
  • SDIO_INT_RXDTVAL : gd32f10x_sdio.h
  • SDIO_INT_RXORE : gd32f10x_sdio.h
  • SDIO_INT_RXRUN : gd32f10x_sdio.h
  • SDIO_INT_SDIOINT : gd32f10x_sdio.h
  • SDIO_INT_STBITE : gd32f10x_sdio.h
  • SDIO_INT_TFE : gd32f10x_sdio.h
  • SDIO_INT_TFF : gd32f10x_sdio.h
  • SDIO_INT_TFH : gd32f10x_sdio.h
  • SDIO_INT_TXDTVAL : gd32f10x_sdio.h
  • SDIO_INT_TXRUN : gd32f10x_sdio.h
  • SDIO_INT_TXURE : gd32f10x_sdio.h
  • SDIO_INTC : gd32f10x_sdio.h
  • SDIO_INTC_ATAENDC : gd32f10x_sdio.h
  • SDIO_INTC_CCRCERRC : gd32f10x_sdio.h
  • SDIO_INTC_CMDRECVC : gd32f10x_sdio.h
  • SDIO_INTC_CMDSENDC : gd32f10x_sdio.h
  • SDIO_INTC_CMDTMOUTC : gd32f10x_sdio.h
  • SDIO_INTC_DTBLKENDC : gd32f10x_sdio.h
  • SDIO_INTC_DTCRCERRC : gd32f10x_sdio.h
  • SDIO_INTC_DTENDC : gd32f10x_sdio.h
  • SDIO_INTC_DTTMOUTC : gd32f10x_sdio.h
  • SDIO_INTC_RXOREC : gd32f10x_sdio.h
  • SDIO_INTC_SDIOINTC : gd32f10x_sdio.h
  • SDIO_INTC_STBITEC : gd32f10x_sdio.h
  • SDIO_INTC_TXUREC : gd32f10x_sdio.h
  • SDIO_INTEN : gd32f10x_sdio.h
  • SDIO_INTEN_ATAENDIE : gd32f10x_sdio.h
  • SDIO_INTEN_CCRCERRIE : gd32f10x_sdio.h
  • SDIO_INTEN_CMDRECVIE : gd32f10x_sdio.h
  • SDIO_INTEN_CMDRUNIE : gd32f10x_sdio.h
  • SDIO_INTEN_CMDSENDIE : gd32f10x_sdio.h
  • SDIO_INTEN_CMDTMOUTIE : gd32f10x_sdio.h
  • SDIO_INTEN_DTBLKENDIE : gd32f10x_sdio.h
  • SDIO_INTEN_DTCRCERRIE : gd32f10x_sdio.h
  • SDIO_INTEN_DTENDIE : gd32f10x_sdio.h
  • SDIO_INTEN_DTTMOUTIE : gd32f10x_sdio.h
  • SDIO_INTEN_RFEIE : gd32f10x_sdio.h
  • SDIO_INTEN_RFFIE : gd32f10x_sdio.h
  • SDIO_INTEN_RFHIE : gd32f10x_sdio.h
  • SDIO_INTEN_RXDTVALIE : gd32f10x_sdio.h
  • SDIO_INTEN_RXOREIE : gd32f10x_sdio.h
  • SDIO_INTEN_RXRUNIE : gd32f10x_sdio.h
  • SDIO_INTEN_SDIOINTIE : gd32f10x_sdio.h
  • SDIO_INTEN_STBITEIE : gd32f10x_sdio.h
  • SDIO_INTEN_TFEIE : gd32f10x_sdio.h
  • SDIO_INTEN_TFFIE : gd32f10x_sdio.h
  • SDIO_INTEN_TFHIE : gd32f10x_sdio.h
  • SDIO_INTEN_TXDTVALIE : gd32f10x_sdio.h
  • SDIO_INTEN_TXRUNIE : gd32f10x_sdio.h
  • SDIO_INTEN_TXUREIE : gd32f10x_sdio.h
  • sdio_interrupt_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_interrupt_enable() : gd32f10x_sdio.c , gd32f10x_sdio.h
  • sdio_interrupt_flag_clear() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_interrupt_flag_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_operation_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_operation_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_POWER_OFF : gd32f10x_sdio.h
  • SDIO_POWER_ON : gd32f10x_sdio.h
  • sdio_power_state_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_power_state_set() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_PWRCTL : gd32f10x_sdio.h
  • SDIO_PWRCTL_PWRCTL : gd32f10x_sdio.h
  • sdio_readwait_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_readwait_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_readwait_type_set() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_READWAITTYPE_CLK : gd32f10x_sdio.h
  • SDIO_READWAITTYPE_DAT2 : gd32f10x_sdio.h
  • SDIO_RESP0 : gd32f10x_sdio.h
  • SDIO_RESP1 : gd32f10x_sdio.h
  • SDIO_RESP2 : gd32f10x_sdio.h
  • SDIO_RESP3 : gd32f10x_sdio.h
  • SDIO_RESPONSE0 : gd32f10x_sdio.h
  • SDIO_RESPONSE1 : gd32f10x_sdio.h
  • SDIO_RESPONSE2 : gd32f10x_sdio.h
  • SDIO_RESPONSE3 : gd32f10x_sdio.h
  • sdio_response_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_RESPONSETYPE_LONG : gd32f10x_sdio.h
  • SDIO_RESPONSETYPE_NO : gd32f10x_sdio.h
  • SDIO_RESPONSETYPE_SHORT : gd32f10x_sdio.h
  • SDIO_RSPCMDIDX : gd32f10x_sdio.h
  • SDIO_SDIOCLKEDGE_FALLING : gd32f10x_sdio.h
  • SDIO_SDIOCLKEDGE_RISING : gd32f10x_sdio.h
  • SDIO_STAT : gd32f10x_sdio.h
  • SDIO_STAT_ATAEND : gd32f10x_sdio.h
  • SDIO_STAT_CCRCERR : gd32f10x_sdio.h
  • SDIO_STAT_CMDRECV : gd32f10x_sdio.h
  • SDIO_STAT_CMDRUN : gd32f10x_sdio.h
  • SDIO_STAT_CMDSEND : gd32f10x_sdio.h
  • SDIO_STAT_CMDTMOUT : gd32f10x_sdio.h
  • SDIO_STAT_DTBLKEND : gd32f10x_sdio.h
  • SDIO_STAT_DTCRCERR : gd32f10x_sdio.h
  • SDIO_STAT_DTEND : gd32f10x_sdio.h
  • SDIO_STAT_DTTMOUT : gd32f10x_sdio.h
  • SDIO_STAT_RFE : gd32f10x_sdio.h
  • SDIO_STAT_RFF : gd32f10x_sdio.h
  • SDIO_STAT_RFH : gd32f10x_sdio.h
  • SDIO_STAT_RXDTVAL : gd32f10x_sdio.h
  • SDIO_STAT_RXORE : gd32f10x_sdio.h
  • SDIO_STAT_RXRUN : gd32f10x_sdio.h
  • SDIO_STAT_SDIOINT : gd32f10x_sdio.h
  • SDIO_STAT_STBITE : gd32f10x_sdio.h
  • SDIO_STAT_TFE : gd32f10x_sdio.h
  • SDIO_STAT_TFF : gd32f10x_sdio.h
  • SDIO_STAT_TFH : gd32f10x_sdio.h
  • SDIO_STAT_TXDTVAL : gd32f10x_sdio.h
  • SDIO_STAT_TXRUN : gd32f10x_sdio.h
  • SDIO_STAT_TXURE : gd32f10x_sdio.h
  • sdio_stop_readwait_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_stop_readwait_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_suspend_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_suspend_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_TRANSDIRECTION_TOCARD : gd32f10x_sdio.h
  • SDIO_TRANSDIRECTION_TOSDIO : gd32f10x_sdio.h
  • SDIO_TRANSMODE_BLOCK : gd32f10x_sdio.h
  • SDIO_TRANSMODE_STREAM : gd32f10x_sdio.h
  • sdio_wait_type_set() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • SDIO_WAITTYPE_DATAEND : gd32f10x_sdio.h
  • SDIO_WAITTYPE_INTERRUPT : gd32f10x_sdio.h
  • SDIO_WAITTYPE_NO : gd32f10x_sdio.h
  • SEL_HXTAL : gd32f10x_rcu.c
  • SEL_IRC8M : gd32f10x_rcu.c
  • SEL_PLL : gd32f10x_rcu.c
  • SMCFG_ETPSC : gd32f10x_timer.h
  • SMCFG_SMC : gd32f10x_timer.h
  • SMCFG_TRGSEL : gd32f10x_timer.h
  • SNCTL_ASYNCWAIT_OFFSET : gd32f10x_exmc.c
  • SNCTL_EXMODEN_OFFSET : gd32f10x_exmc.c
  • SNCTL_NRMUX_OFFSET : gd32f10x_exmc.c
  • SNCTL_NRTP : gd32f10x_exmc.h
  • SNCTL_NRW : gd32f10x_exmc.h
  • SNCTL_NRWTEN_OFFSET : gd32f10x_exmc.c
  • SNCTL_SBRSTEN_OFFSET : gd32f10x_exmc.c
  • SNCTL_WRAPEN_OFFSET : gd32f10x_exmc.c
  • SNCTL_WREN_OFFSET : gd32f10x_exmc.c
  • SNTCFG_AHLD_OFFSET : gd32f10x_exmc.c
  • SNTCFG_ASYNCMOD : gd32f10x_exmc.h
  • SNTCFG_BUSLAT_OFFSET : gd32f10x_exmc.c
  • SNTCFG_CKDIV : gd32f10x_exmc.h
  • SNTCFG_DLAT : gd32f10x_exmc.h
  • SNTCFG_DSET_OFFSET : gd32f10x_exmc.c
  • SNWTCFG_WAHLD_OFFSET : gd32f10x_exmc.c
  • SNWTCFG_WBUSLAT_OFFSET : gd32f10x_exmc.c
  • SNWTCFG_WDSET_OFFSET : gd32f10x_exmc.c
  • SPI0 : gd32f10x_spi.h
  • SPI1 : gd32f10x_spi.h
  • SPI2 : gd32f10x_spi.h
  • SPI_BIDIRECTIONAL_RECEIVE : gd32f10x_spi.h
  • spi_bidirectional_transfer_config() : gd32f10x_spi.h , gd32f10x_spi.c
  • SPI_BIDIRECTIONAL_TRANSMIT : gd32f10x_spi.h
  • SPI_CK_PL_HIGH_PH_1EDGE : gd32f10x_spi.h
  • SPI_CK_PL_HIGH_PH_2EDGE : gd32f10x_spi.h
  • SPI_CK_PL_LOW_PH_1EDGE : gd32f10x_spi.h
  • SPI_CK_PL_LOW_PH_2EDGE : gd32f10x_spi.h
  • spi_crc_error_clear() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_get() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_next() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_crc_off() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_on() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_polynomial_get() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_polynomial_set() : gd32f10x_spi.c , gd32f10x_spi.h
  • SPI_CRC_RX : gd32f10x_spi.h
  • SPI_CRC_TX : gd32f10x_spi.h
  • SPI_CRCPOLY : gd32f10x_spi.h
  • SPI_CRCPOLY_CPR : gd32f10x_spi.h
  • SPI_CTL0 : gd32f10x_spi.h
  • SPI_CTL0_BDEN : gd32f10x_spi.h
  • SPI_CTL0_BDOEN : gd32f10x_spi.h
  • SPI_CTL0_CKPH : gd32f10x_spi.h
  • SPI_CTL0_CKPL : gd32f10x_spi.h
  • SPI_CTL0_CRCEN : gd32f10x_spi.h
  • SPI_CTL0_CRCNT : gd32f10x_spi.h
  • SPI_CTL0_FF16 : gd32f10x_spi.h
  • SPI_CTL0_LF : gd32f10x_spi.h
  • SPI_CTL0_MSTMOD : gd32f10x_spi.h
  • SPI_CTL0_PSC : gd32f10x_spi.h
  • SPI_CTL0_RO : gd32f10x_spi.h
  • SPI_CTL0_SPIEN : gd32f10x_spi.h
  • SPI_CTL0_SWNSS : gd32f10x_spi.h
  • SPI_CTL0_SWNSSEN : gd32f10x_spi.h
  • SPI_CTL1 : gd32f10x_spi.h
  • SPI_CTL1_DMAREN : gd32f10x_spi.h
  • SPI_CTL1_DMATEN : gd32f10x_spi.h
  • SPI_CTL1_ERRIE : gd32f10x_spi.h
  • SPI_CTL1_NSSDRV : gd32f10x_spi.h
  • SPI_CTL1_RBNEIE : gd32f10x_spi.h
  • SPI_CTL1_TBEIE : gd32f10x_spi.h
  • SPI_DATA : gd32f10x_spi.h
  • SPI_DATA_DATA : gd32f10x_spi.h
  • spi_disable() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_dma_disable() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_dma_enable() : gd32f10x_spi.h , gd32f10x_spi.c
  • SPI_DMA_RECEIVE : gd32f10x_spi.h
  • SPI_DMA_TRANSMIT : gd32f10x_spi.h
  • spi_enable() : gd32f10x_spi.h , gd32f10x_spi.c
  • SPI_ENDIAN_LSB : gd32f10x_spi.h
  • SPI_ENDIAN_MSB : gd32f10x_spi.h
  • SPI_FLAG_CONFERR : gd32f10x_spi.h
  • SPI_FLAG_CRCERR : gd32f10x_spi.h
  • SPI_FLAG_RBNE : gd32f10x_spi.h
  • SPI_FLAG_RXORERR : gd32f10x_spi.h
  • SPI_FLAG_TBE : gd32f10x_spi.h
  • SPI_FLAG_TRANS : gd32f10x_spi.h
  • SPI_FRAMESIZE_16BIT : gd32f10x_spi.h
  • SPI_FRAMESIZE_8BIT : gd32f10x_spi.h
  • spi_i2s_data_frame_format_config() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_data_receive() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_i2s_data_transmit() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_deinit() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_i2s_flag_get() : gd32f10x_spi.c , gd32f10x_spi.h
  • SPI_I2S_INT_ERR : gd32f10x_spi.h
  • SPI_I2S_INT_FLAG_RBNE : gd32f10x_spi.h
  • SPI_I2S_INT_FLAG_RXORERR : gd32f10x_spi.h
  • SPI_I2S_INT_FLAG_TBE : gd32f10x_spi.h
  • SPI_I2S_INT_RBNE : gd32f10x_spi.h
  • SPI_I2S_INT_TBE : gd32f10x_spi.h
  • spi_i2s_interrupt_disable() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_interrupt_enable() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_interrupt_flag_get() : gd32f10x_spi.h , gd32f10x_spi.c
  • SPI_I2SCTL : gd32f10x_spi.h
  • SPI_I2SCTL_CHLEN : gd32f10x_spi.h
  • SPI_I2SCTL_CKPL : gd32f10x_spi.h
  • SPI_I2SCTL_DTLEN : gd32f10x_spi.h
  • SPI_I2SCTL_I2SEN : gd32f10x_spi.h
  • SPI_I2SCTL_I2SOPMOD : gd32f10x_spi.h
  • SPI_I2SCTL_I2SSEL : gd32f10x_spi.h
  • SPI_I2SCTL_I2SSTD : gd32f10x_spi.h
  • SPI_I2SCTL_PCMSMOD : gd32f10x_spi.h
  • SPI_I2SPSC : gd32f10x_spi.h
  • SPI_I2SPSC_DIV : gd32f10x_spi.h
  • SPI_I2SPSC_MCKOEN : gd32f10x_spi.h
  • SPI_I2SPSC_OF : gd32f10x_spi.h
  • spi_init() : gd32f10x_spi.h , gd32f10x_spi.c
  • SPI_INIT_MASK : gd32f10x_spi.c
  • SPI_INT_FLAG_CONFERR : gd32f10x_spi.h
  • SPI_INT_FLAG_CRCERR : gd32f10x_spi.h
  • SPI_MASTER : gd32f10x_spi.h
  • SPI_NSS_HARD : gd32f10x_spi.h
  • spi_nss_internal_high() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_nss_internal_low() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_nss_output_disable() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_nss_output_enable() : gd32f10x_spi.h , gd32f10x_spi.c
  • SPI_NSS_SOFT : gd32f10x_spi.h
  • SPI_PSC_128 : gd32f10x_spi.h
  • SPI_PSC_16 : gd32f10x_spi.h
  • SPI_PSC_2 : gd32f10x_spi.h
  • SPI_PSC_256 : gd32f10x_spi.h
  • SPI_PSC_32 : gd32f10x_spi.h
  • SPI_PSC_4 : gd32f10x_spi.h
  • SPI_PSC_64 : gd32f10x_spi.h
  • SPI_PSC_8 : gd32f10x_spi.h
  • SPI_RCRC : gd32f10x_spi.h
  • SPI_RCRC_RCR : gd32f10x_spi.h
  • SPI_SLAVE : gd32f10x_spi.h
  • SPI_STAT : gd32f10x_spi.h
  • SPI_STAT_CONFERR : gd32f10x_spi.h
  • SPI_STAT_CRCERR : gd32f10x_spi.h
  • SPI_STAT_I2SCH : gd32f10x_spi.h
  • SPI_STAT_RBNE : gd32f10x_spi.h
  • SPI_STAT_RXORERR : gd32f10x_spi.h
  • SPI_STAT_TBE : gd32f10x_spi.h
  • SPI_STAT_TRANS : gd32f10x_spi.h
  • SPI_STAT_TXURERR : gd32f10x_spi.h
  • SPI_TCRC : gd32f10x_spi.h
  • SPI_TCRC_TCR : gd32f10x_spi.h
  • SPI_TRANSMODE_BDRECEIVE : gd32f10x_spi.h
  • SPI_TRANSMODE_BDTRANSMIT : gd32f10x_spi.h
  • SPI_TRANSMODE_FULLDUPLEX : gd32f10x_spi.h
  • SPI_TRANSMODE_RECEIVEONLY : gd32f10x_spi.h
  • STAT_FCNT : usbd_regs.h
  • STAT_LOCK : usbd_regs.h
  • STAT_REG_OFFSET : gd32f10x_can.h
  • STAT_RXDM : usbd_regs.h
  • STAT_RXDP : usbd_regs.h
  • STAT_SOFLN : usbd_regs.h
  • STORE_OPTION : gd32f10x_enet.h
  • SWAPBYTE : usb_std.h , usbd_std.h
  • system_lowpower_reset() : gd32f10x_misc.c , gd32f10x_misc.h
  • system_lowpower_set() : gd32f10x_misc.c , gd32f10x_misc.h
  • SYSTICK_CLKSOURCE_HCLK : gd32f10x_misc.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : gd32f10x_misc.h
  • systick_clksource_set() : gd32f10x_misc.c , gd32f10x_misc.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
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  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TAMPER_FLAG_SHIFT : gd32f10x_bkp.c
  • TAMPER_PIN_ACTIVE_HIGH : gd32f10x_bkp.h
  • TAMPER_PIN_ACTIVE_LOW : gd32f10x_bkp.h
  • TDES0_CM : gd32f10x_enet.h
  • TDES0_CONT : gd32f10x_enet.h
  • TDES1_TB1S : gd32f10x_enet.h
  • TDES1_TB2S : gd32f10x_enet.h
  • TIMER0 : gd32f10x_timer.h
  • TIMER1 : gd32f10x_timer.h
  • TIMER10 : gd32f10x_timer.h
  • TIMER11 : gd32f10x_timer.h
  • TIMER12 : gd32f10x_timer.h
  • TIMER13 : gd32f10x_timer.h
  • TIMER2 : gd32f10x_timer.h
  • TIMER3 : gd32f10x_timer.h
  • TIMER4 : gd32f10x_timer.h
  • TIMER5 : gd32f10x_timer.h
  • TIMER6 : gd32f10x_timer.h
  • TIMER7 : gd32f10x_timer.h
  • TIMER8 : gd32f10x_timer.h
  • TIMER9 : gd32f10x_timer.h
  • timer_auto_reload_shadow_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_auto_reload_shadow_enable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_automatic_output_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_automatic_output_enable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_autoreload_value_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_break_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_BREAK_DISABLE : gd32f10x_timer.h
  • timer_break_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_break_enable() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_BREAK_ENABLE : gd32f10x_timer.h
  • TIMER_BREAK_POLARITY_HIGH : gd32f10x_timer.h
  • TIMER_BREAK_POLARITY_LOW : gd32f10x_timer.h
  • TIMER_CAR : gd32f10x_timer.h
  • TIMER_CAR_CARL : gd32f10x_timer.h
  • TIMER_CCHP : gd32f10x_timer.h
  • TIMER_CCHP_BRKEN : gd32f10x_timer.h
  • TIMER_CCHP_BRKP : gd32f10x_timer.h
  • TIMER_CCHP_DTCFG : gd32f10x_timer.h
  • TIMER_CCHP_IOS : gd32f10x_timer.h
  • TIMER_CCHP_OAEN : gd32f10x_timer.h
  • TIMER_CCHP_POEN : gd32f10x_timer.h
  • TIMER_CCHP_PROT : gd32f10x_timer.h
  • TIMER_CCHP_PROT_0 : gd32f10x_timer.h
  • TIMER_CCHP_PROT_1 : gd32f10x_timer.h
  • TIMER_CCHP_PROT_2 : gd32f10x_timer.h
  • TIMER_CCHP_PROT_OFF : gd32f10x_timer.h
  • TIMER_CCHP_ROS : gd32f10x_timer.h
  • TIMER_CCX_DISABLE : gd32f10x_timer.h
  • TIMER_CCX_ENABLE : gd32f10x_timer.h
  • TIMER_CCXN_DISABLE : gd32f10x_timer.h
  • TIMER_CCXN_ENABLE : gd32f10x_timer.h
  • TIMER_CH0CV : gd32f10x_timer.h
  • TIMER_CH0CV_CH0VAL : gd32f10x_timer.h
  • TIMER_CH1CV : gd32f10x_timer.h
  • TIMER_CH1CV_CH1VAL : gd32f10x_timer.h
  • TIMER_CH2CV : gd32f10x_timer.h
  • TIMER_CH2CV_CH2VAL : gd32f10x_timer.h
  • TIMER_CH3CV : gd32f10x_timer.h
  • TIMER_CH3CV_CH3VAL : gd32f10x_timer.h
  • TIMER_CH_0 : gd32f10x_timer.h
  • TIMER_CH_1 : gd32f10x_timer.h
  • TIMER_CH_2 : gd32f10x_timer.h
  • TIMER_CH_3 : gd32f10x_timer.h
  • timer_channel_capture_value_register_read() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_complementary_output_polarity_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_complementary_output_state_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_control_shadow_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_control_shadow_update_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_dma_request_source_select() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_input_capture_prescaler_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_clear_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_fast_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_mode_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_polarity_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_pulse_value_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_shadow_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_state_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_CHCTL0 : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0CAPFLT : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0CAPPSC : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0COMCEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0COMCTL : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0COMFEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0COMSEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0MS : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1CAPFLT : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1CAPPSC : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1COMCEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1COMCTL : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1COMFEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1COMSEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1MS : gd32f10x_timer.h
  • TIMER_CHCTL1 : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2CAPFLT : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2CAPPSC : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2COMCEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2COMCTL : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2COMFEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2COMSEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2MS : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3CAPFLT : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3CAPPSC : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3COMCEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3COMCTL : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3COMFEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3COMSEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3MS : gd32f10x_timer.h
  • TIMER_CHCTL2 : gd32f10x_timer.h
  • TIMER_CHCTL2_CH0EN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH0NEN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH0NP : gd32f10x_timer.h
  • TIMER_CHCTL2_CH0P : gd32f10x_timer.h
  • TIMER_CHCTL2_CH1EN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH1NEN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH1NP : gd32f10x_timer.h
  • TIMER_CHCTL2_CH1P : gd32f10x_timer.h
  • TIMER_CHCTL2_CH2EN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH2NEN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH2NP : gd32f10x_timer.h
  • TIMER_CHCTL2_CH2P : gd32f10x_timer.h
  • TIMER_CHCTL2_CH3EN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH3P : gd32f10x_timer.h
  • TIMER_CKDIV_DIV1 : gd32f10x_timer.h
  • TIMER_CKDIV_DIV2 : gd32f10x_timer.h
  • TIMER_CKDIV_DIV4 : gd32f10x_timer.h
  • TIMER_CNT : gd32f10x_timer.h
  • TIMER_CNT_CNT : gd32f10x_timer.h
  • timer_counter_alignment() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_COUNTER_CENTER_BOTH : gd32f10x_timer.h
  • TIMER_COUNTER_CENTER_DOWN : gd32f10x_timer.h
  • TIMER_COUNTER_CENTER_UP : gd32f10x_timer.h
  • TIMER_COUNTER_DOWN : gd32f10x_timer.h
  • timer_counter_down_direction() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_COUNTER_EDGE : gd32f10x_timer.h
  • timer_counter_read() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_COUNTER_UP : gd32f10x_timer.h
  • timer_counter_up_direction() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_counter_value_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_CREP : gd32f10x_timer.h
  • TIMER_CREP_CREP : gd32f10x_timer.h
  • TIMER_CTL0 : gd32f10x_timer.h
  • TIMER_CTL0_ARSE : gd32f10x_timer.h
  • TIMER_CTL0_CAM : gd32f10x_timer.h
  • TIMER_CTL0_CEN : gd32f10x_timer.h
  • TIMER_CTL0_CKDIV : gd32f10x_timer.h
  • TIMER_CTL0_DIR : gd32f10x_timer.h
  • TIMER_CTL0_SPM : gd32f10x_timer.h
  • TIMER_CTL0_UPDIS : gd32f10x_timer.h
  • TIMER_CTL0_UPS : gd32f10x_timer.h
  • TIMER_CTL1 : gd32f10x_timer.h
  • TIMER_CTL1_CCSE : gd32f10x_timer.h
  • TIMER_CTL1_CCUC : gd32f10x_timer.h
  • TIMER_CTL1_DMAS : gd32f10x_timer.h
  • TIMER_CTL1_ISO0 : gd32f10x_timer.h
  • TIMER_CTL1_ISO0N : gd32f10x_timer.h
  • TIMER_CTL1_ISO1 : gd32f10x_timer.h
  • TIMER_CTL1_ISO1N : gd32f10x_timer.h
  • TIMER_CTL1_ISO2 : gd32f10x_timer.h
  • TIMER_CTL1_ISO2N : gd32f10x_timer.h
  • TIMER_CTL1_ISO3 : gd32f10x_timer.h
  • TIMER_CTL1_MMC : gd32f10x_timer.h
  • TIMER_CTL1_TI0S : gd32f10x_timer.h
  • timer_deinit() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_DMA_CH0D : gd32f10x_timer.h
  • TIMER_DMA_CH1D : gd32f10x_timer.h
  • TIMER_DMA_CH2D : gd32f10x_timer.h
  • TIMER_DMA_CH3D : gd32f10x_timer.h
  • TIMER_DMA_CMTD : gd32f10x_timer.h
  • timer_dma_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_dma_enable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_dma_transfer_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_DMA_TRGD : gd32f10x_timer.h
  • TIMER_DMA_UPD : gd32f10x_timer.h
  • TIMER_DMACFG : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CAR : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CCHP : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CH0CV : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CH1CV : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CH2CV : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CH3CV : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CHCTL0 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CHCTL1 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CHCTL2 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CNT : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CREP : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CTL0 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CTL1 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_DMACFG : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_DMAINTEN : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_DMATB : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_INTF : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_PSC : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_SMCFG : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_SWEVG : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_10TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_11TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_12TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_13TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_14TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_15TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_16TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_17TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_18TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_1TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_2TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_3TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_4TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_5TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_6TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_7TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_8TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_9TRANSFER : gd32f10x_timer.h
  • TIMER_DMAINTEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_BRKIE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH0DEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH0IE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH1DEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH1IE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH2DEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH2IE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH3DEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH3IE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CMTDEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CMTIE : gd32f10x_timer.h
  • TIMER_DMAINTEN_TRGDEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_TRGIE : gd32f10x_timer.h
  • TIMER_DMAINTEN_UPDEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_UPIE : gd32f10x_timer.h
  • TIMER_DMAREQUEST_CHANNELEVENT : gd32f10x_timer.h
  • TIMER_DMAREQUEST_UPDATEEVENT : gd32f10x_timer.h
  • TIMER_DMATB : gd32f10x_timer.h
  • TIMER_DMATB_DMATB : gd32f10x_timer.h
  • timer_enable() : gd32f10x_timer.c , gd32f10x_timer.h
  • TIMER_ENCODER_MODE0 : gd32f10x_timer.h
  • TIMER_ENCODER_MODE1 : gd32f10x_timer.h
  • TIMER_ENCODER_MODE2 : gd32f10x_timer.h
  • TIMER_ETP_FALLING : gd32f10x_timer.h
  • TIMER_ETP_RISING : gd32f10x_timer.h
  • timer_event_software_generate() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_EVENT_SRC_BRKG : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CH0G : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CH1G : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CH2G : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CH3G : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CMTG : gd32f10x_timer.h
  • TIMER_EVENT_SRC_TRGG : gd32f10x_timer.h
  • TIMER_EVENT_SRC_UPG : gd32f10x_timer.h
  • TIMER_EXT_TRI_PSC_DIV2 : gd32f10x_timer.h
  • TIMER_EXT_TRI_PSC_DIV4 : gd32f10x_timer.h
  • TIMER_EXT_TRI_PSC_DIV8 : gd32f10x_timer.h
  • TIMER_EXT_TRI_PSC_OFF : gd32f10x_timer.h
  • timer_external_clock_mode0_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_external_clock_mode1_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_external_clock_mode1_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_external_trigger_as_external_clock_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_external_trigger_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_FLAG_BRK : gd32f10x_timer.h
  • TIMER_FLAG_CH0 : gd32f10x_timer.h
  • TIMER_FLAG_CH0O : gd32f10x_timer.h
  • TIMER_FLAG_CH1 : gd32f10x_timer.h
  • TIMER_FLAG_CH1O : gd32f10x_timer.h
  • TIMER_FLAG_CH2 : gd32f10x_timer.h
  • TIMER_FLAG_CH2O : gd32f10x_timer.h
  • TIMER_FLAG_CH3 : gd32f10x_timer.h
  • TIMER_FLAG_CH3O : gd32f10x_timer.h
  • timer_flag_clear() : gd32f10x_timer.c , gd32f10x_timer.h
  • TIMER_FLAG_CMT : gd32f10x_timer.h
  • timer_flag_get() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_FLAG_TRG : gd32f10x_timer.h
  • TIMER_FLAG_UP : gd32f10x_timer.h
  • timer_hall_mode_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_HALLINTERFACE_DISABLE : gd32f10x_timer.h
  • TIMER_HALLINTERFACE_ENABLE : gd32f10x_timer.h
  • TIMER_IC_POLARITY_BOTH_EDGE : gd32f10x_timer.h
  • TIMER_IC_POLARITY_FALLING : gd32f10x_timer.h
  • TIMER_IC_POLARITY_RISING : gd32f10x_timer.h
  • TIMER_IC_PSC_DIV1 : gd32f10x_timer.h
  • TIMER_IC_PSC_DIV2 : gd32f10x_timer.h
  • TIMER_IC_PSC_DIV4 : gd32f10x_timer.h
  • TIMER_IC_PSC_DIV8 : gd32f10x_timer.h
  • TIMER_IC_SELECTION_DIRECTTI : gd32f10x_timer.h
  • TIMER_IC_SELECTION_INDIRECTTI : gd32f10x_timer.h
  • TIMER_IC_SELECTION_ITS : gd32f10x_timer.h
  • timer_init() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_input_capture_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_input_pwm_capture_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_input_trigger_source_select() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_INT_BRK : gd32f10x_timer.h
  • TIMER_INT_CH0 : gd32f10x_timer.h
  • TIMER_INT_CH1 : gd32f10x_timer.h
  • TIMER_INT_CH2 : gd32f10x_timer.h
  • TIMER_INT_CH3 : gd32f10x_timer.h
  • TIMER_INT_CMT : gd32f10x_timer.h
  • TIMER_INT_FLAG_BRK : gd32f10x_timer.h
  • TIMER_INT_FLAG_CH0 : gd32f10x_timer.h
  • TIMER_INT_FLAG_CH1 : gd32f10x_timer.h
  • TIMER_INT_FLAG_CH2 : gd32f10x_timer.h
  • TIMER_INT_FLAG_CH3 : gd32f10x_timer.h
  • TIMER_INT_FLAG_CMT : gd32f10x_timer.h
  • TIMER_INT_FLAG_TRG : gd32f10x_timer.h
  • TIMER_INT_FLAG_UP : gd32f10x_timer.h
  • TIMER_INT_TRG : gd32f10x_timer.h
  • TIMER_INT_UP : gd32f10x_timer.h
  • timer_internal_clock_config() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_internal_trigger_as_external_clock_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_interrupt_disable() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_interrupt_enable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_interrupt_flag_clear() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_interrupt_flag_get() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_INTF : gd32f10x_timer.h
  • TIMER_INTF_BRKIF : gd32f10x_timer.h
  • TIMER_INTF_CH0IF : gd32f10x_timer.h
  • TIMER_INTF_CH0OF : gd32f10x_timer.h
  • TIMER_INTF_CH1IF : gd32f10x_timer.h
  • TIMER_INTF_CH1OF : gd32f10x_timer.h
  • TIMER_INTF_CH2IF : gd32f10x_timer.h
  • TIMER_INTF_CH2OF : gd32f10x_timer.h
  • TIMER_INTF_CH3IF : gd32f10x_timer.h
  • TIMER_INTF_CH3OF : gd32f10x_timer.h
  • TIMER_INTF_CMTIF : gd32f10x_timer.h
  • TIMER_INTF_TRGIF : gd32f10x_timer.h
  • TIMER_INTF_UPIF : gd32f10x_timer.h
  • TIMER_IOS_STATE_DISABLE : gd32f10x_timer.h
  • TIMER_IOS_STATE_ENABLE : gd32f10x_timer.h
  • timer_master_output_trigger_source_select() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_master_slave_mode_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_MASTER_SLAVE_MODE_DISABLE : gd32f10x_timer.h
  • TIMER_MASTER_SLAVE_MODE_ENABLE : gd32f10x_timer.h
  • TIMER_OC_CLEAR_DISABLE : gd32f10x_timer.h
  • TIMER_OC_CLEAR_ENABLE : gd32f10x_timer.h
  • TIMER_OC_FAST_DISABLE : gd32f10x_timer.h
  • TIMER_OC_FAST_ENABLE : gd32f10x_timer.h
  • TIMER_OC_IDLE_STATE_HIGH : gd32f10x_timer.h
  • TIMER_OC_IDLE_STATE_LOW : gd32f10x_timer.h
  • TIMER_OC_MODE_ACTIVE : gd32f10x_timer.h
  • TIMER_OC_MODE_HIGH : gd32f10x_timer.h
  • TIMER_OC_MODE_INACTIVE : gd32f10x_timer.h
  • TIMER_OC_MODE_LOW : gd32f10x_timer.h
  • TIMER_OC_MODE_PWM0 : gd32f10x_timer.h
  • TIMER_OC_MODE_PWM1 : gd32f10x_timer.h
  • TIMER_OC_MODE_TIMING : gd32f10x_timer.h
  • TIMER_OC_MODE_TOGGLE : gd32f10x_timer.h
  • TIMER_OC_POLARITY_HIGH : gd32f10x_timer.h
  • TIMER_OC_POLARITY_LOW : gd32f10x_timer.h
  • TIMER_OC_SHADOW_DISABLE : gd32f10x_timer.h
  • TIMER_OC_SHADOW_ENABLE : gd32f10x_timer.h
  • TIMER_OCN_IDLE_STATE_HIGH : gd32f10x_timer.h
  • TIMER_OCN_IDLE_STATE_LOW : gd32f10x_timer.h
  • TIMER_OCN_POLARITY_HIGH : gd32f10x_timer.h
  • TIMER_OCN_POLARITY_LOW : gd32f10x_timer.h
  • TIMER_OPTION : gd32f10x_enet.h
  • TIMER_OUTAUTO_DISABLE : gd32f10x_timer.h
  • TIMER_OUTAUTO_ENABLE : gd32f10x_timer.h
  • timer_prescaler_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_prescaler_read() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_primary_output_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_PSC : gd32f10x_timer.h
  • TIMER_PSC_PSC : gd32f10x_timer.h
  • TIMER_PSC_RELOAD_NOW : gd32f10x_timer.h
  • TIMER_PSC_RELOAD_UPDATE : gd32f10x_timer.h
  • timer_quadrature_decoder_mode_config() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_repetition_value_config() : gd32f10x_timer.c , gd32f10x_timer.h
  • TIMER_ROS_STATE_DISABLE : gd32f10x_timer.h
  • TIMER_ROS_STATE_ENABLE : gd32f10x_timer.h
  • timer_single_pulse_mode_config() : gd32f10x_timer.c , gd32f10x_timer.h
  • TIMER_SLAVE_MODE_DISABLE : gd32f10x_timer.h
  • TIMER_SLAVE_MODE_EVENT : gd32f10x_timer.h
  • TIMER_SLAVE_MODE_EXTERNAL0 : gd32f10x_timer.h
  • TIMER_SLAVE_MODE_PAUSE : gd32f10x_timer.h
  • TIMER_SLAVE_MODE_RESTART : gd32f10x_timer.h
  • timer_slave_mode_select() : gd32f10x_timer.h , gd32f10x_timer.c
  • TIMER_SMCFG : gd32f10x_timer.h
  • TIMER_SMCFG_ETFC : gd32f10x_timer.h
  • TIMER_SMCFG_ETP : gd32f10x_timer.h
  • TIMER_SMCFG_ETPSC : gd32f10x_timer.h
  • TIMER_SMCFG_MSM : gd32f10x_timer.h
  • TIMER_SMCFG_SMC : gd32f10x_timer.h
  • TIMER_SMCFG_SMC1 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGS : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_CI0F_ED : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_CI0FE0 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_CI1FE1 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ETIFP : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ITI0 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ITI1 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ITI2 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ITI3 : gd32f10x_timer.h
  • TIMER_SP_MODE_REPETITIVE : gd32f10x_timer.h
  • TIMER_SP_MODE_SINGLE : gd32f10x_timer.h
  • TIMER_SWEVG : gd32f10x_timer.h
  • TIMER_SWEVG_BRKG : gd32f10x_timer.h
  • TIMER_SWEVG_CH0G : gd32f10x_timer.h
  • TIMER_SWEVG_CH1G : gd32f10x_timer.h
  • TIMER_SWEVG_CH2G : gd32f10x_timer.h
  • TIMER_SWEVG_CH3G : gd32f10x_timer.h
  • TIMER_SWEVG_CMTG : gd32f10x_timer.h
  • TIMER_SWEVG_TRGG : gd32f10x_timer.h
  • TIMER_SWEVG_UPG : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_CC0 : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_ENABLE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_O0CPRE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_O1CPRE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_O2CPRE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_O3CPRE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_RESET : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_UPDATE : gd32f10x_timer.h
  • timer_update_event_disable() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_update_event_enable() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_update_source_config() : gd32f10x_timer.c , gd32f10x_timer.h
  • TIMER_UPDATE_SRC_GLOBAL : gd32f10x_timer.h
  • TIMER_UPDATE_SRC_REGULAR : gd32f10x_timer.h
  • TIMER_UPDATECTL_CCU : gd32f10x_timer.h
  • TIMER_UPDATECTL_CCUTRI : gd32f10x_timer.h
  • TMDATA0_DB0 : gd32f10x_can.h
  • TMDATA0_DB1 : gd32f10x_can.h
  • TMDATA0_DB2 : gd32f10x_can.h
  • TMDATA0_DB3 : gd32f10x_can.h
  • TMDATA1_DB4 : gd32f10x_can.h
  • TMDATA1_DB5 : gd32f10x_can.h
  • TMDATA1_DB6 : gd32f10x_can.h
  • TMDATA1_DB7 : gd32f10x_can.h
  • TMI_EFID : gd32f10x_can.h
  • TMI_SFID : gd32f10x_can.h
  • TRACE_MODE_ASYNC : gd32f10x_dbg.h
  • TRACE_MODE_SYNC_DATASIZE_1 : gd32f10x_dbg.h
  • TRACE_MODE_SYNC_DATASIZE_2 : gd32f10x_dbg.h
  • TRACE_MODE_SYNC_DATASIZE_4 : gd32f10x_dbg.h
  • TSTAT_REG_OFFSET : gd32f10x_can.h
  • TXCNT_OFFSET : usbd_regs.h
  • TXDESC_BUFFER_1_ADDR : gd32f10x_enet.h
  • TXDESC_COLLISION_COUNT : gd32f10x_enet.h
  • TXFIFO_EMPTY : usb_regs.h
  • TXFIFO_EMPTY_HALF : usb_regs.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART3 : gd32f10x_usart.h
  • UART4 : gd32f10x_usart.h
  • UNLOCK_KEY0 : gd32f10x_fmc.h
  • UNLOCK_KEY1 : gd32f10x_fmc.h
  • UP_STATE : usbh_core.h
  • URB_DONE : usb_core.h
  • URB_ERROR : usb_core.h
  • URB_IDLE : usb_core.h
  • URB_NOTREADY : usb_core.h
  • URB_PING : usb_core.h
  • URB_STALL : usb_core.h
  • urb_state_enum : usb_core.h
  • USART0 : gd32f10x_usart.h
  • USART1 : gd32f10x_usart.h
  • USART2 : gd32f10x_usart.h
  • usart_address_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_BAUD : gd32f10x_usart.h
  • USART_BAUD_FRADIV : gd32f10x_usart.h
  • USART_BAUD_INTDIV : gd32f10x_usart.h
  • usart_baudrate_set() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_BIT_POS : gd32f10x_usart.h
  • USART_BIT_POS2 : gd32f10x_usart.h
  • USART_CLEN_EN : gd32f10x_usart.h
  • USART_CLEN_NONE : gd32f10x_usart.h
  • USART_CPH_1CK : gd32f10x_usart.h
  • USART_CPH_2CK : gd32f10x_usart.h
  • USART_CPL_HIGH : gd32f10x_usart.h
  • USART_CPL_LOW : gd32f10x_usart.h
  • USART_CTL0 : gd32f10x_usart.h
  • USART_CTL0_IDLEIE : gd32f10x_usart.h
  • USART_CTL0_PCEN : gd32f10x_usart.h
  • USART_CTL0_PERRIE : gd32f10x_usart.h
  • USART_CTL0_PM : gd32f10x_usart.h
  • USART_CTL0_RBNEIE : gd32f10x_usart.h
  • USART_CTL0_REG_OFFSET : gd32f10x_usart.h
  • USART_CTL0_REN : gd32f10x_usart.h
  • USART_CTL0_RWU : gd32f10x_usart.h
  • USART_CTL0_SBKCMD : gd32f10x_usart.h
  • USART_CTL0_TBEIE : gd32f10x_usart.h
  • USART_CTL0_TCIE : gd32f10x_usart.h
  • USART_CTL0_TEN : gd32f10x_usart.h
  • USART_CTL0_UEN : gd32f10x_usart.h
  • USART_CTL0_WL : gd32f10x_usart.h
  • USART_CTL0_WM : gd32f10x_usart.h
  • USART_CTL1 : gd32f10x_usart.h
  • USART_CTL1_ADDR : gd32f10x_usart.h
  • USART_CTL1_CKEN : gd32f10x_usart.h
  • USART_CTL1_CLEN : gd32f10x_usart.h
  • USART_CTL1_CPH : gd32f10x_usart.h
  • USART_CTL1_CPL : gd32f10x_usart.h
  • USART_CTL1_LBDIE : gd32f10x_usart.h
  • USART_CTL1_LBLEN : gd32f10x_usart.h
  • USART_CTL1_LMEN : gd32f10x_usart.h
  • USART_CTL1_REG_OFFSET : gd32f10x_usart.h
  • USART_CTL1_STB : gd32f10x_usart.h
  • USART_CTL2 : gd32f10x_usart.h
  • USART_CTL2_CTSEN : gd32f10x_usart.h
  • USART_CTL2_CTSIE : gd32f10x_usart.h
  • USART_CTL2_DENR : gd32f10x_usart.h
  • USART_CTL2_DENT : gd32f10x_usart.h
  • USART_CTL2_ERRIE : gd32f10x_usart.h
  • USART_CTL2_HDEN : gd32f10x_usart.h
  • USART_CTL2_IREN : gd32f10x_usart.h
  • USART_CTL2_IRLP : gd32f10x_usart.h
  • USART_CTL2_NKEN : gd32f10x_usart.h
  • USART_CTL2_REG_OFFSET : gd32f10x_usart.h
  • USART_CTL2_RTSEN : gd32f10x_usart.h
  • USART_CTL2_SCEN : gd32f10x_usart.h
  • USART_CTS_DISABLE : gd32f10x_usart.h
  • USART_CTS_ENABLE : gd32f10x_usart.h
  • USART_DATA : gd32f10x_usart.h
  • USART_DATA_DATA : gd32f10x_usart.h
  • usart_data_receive() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_data_transmit() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_deinit() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_DENR_DISABLE : gd32f10x_usart.h
  • USART_DENR_ENABLE : gd32f10x_usart.h
  • USART_DENT_DISABLE : gd32f10x_usart.h
  • USART_DENT_ENABLE : gd32f10x_usart.h
  • usart_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_dma_receive_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_dma_transmit_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_flag_clear() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_FLAG_CTSF : gd32f10x_usart.h
  • usart_flag_enum : gd32f10x_usart.h
  • USART_FLAG_FERR : gd32f10x_usart.h
  • usart_flag_get() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_FLAG_IDLEF : gd32f10x_usart.h
  • USART_FLAG_LBDF : gd32f10x_usart.h
  • USART_FLAG_NERR : gd32f10x_usart.h
  • USART_FLAG_ORERR : gd32f10x_usart.h
  • USART_FLAG_PERR : gd32f10x_usart.h
  • USART_FLAG_RBNE : gd32f10x_usart.h
  • USART_FLAG_TBE : gd32f10x_usart.h
  • USART_FLAG_TC : gd32f10x_usart.h
  • USART_GP : gd32f10x_usart.h
  • USART_GP_GUAT : gd32f10x_usart.h
  • USART_GP_PSC : gd32f10x_usart.h
  • usart_guard_time_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_halfduplex_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_halfduplex_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_hardware_flow_cts_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_hardware_flow_rts_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_INT_CTS : gd32f10x_usart.h
  • USART_INT_ERR : gd32f10x_usart.h
  • USART_INT_FLAG_CTS : gd32f10x_usart.h
  • USART_INT_FLAG_ERR_FERR : gd32f10x_usart.h
  • USART_INT_FLAG_ERR_NERR : gd32f10x_usart.h
  • USART_INT_FLAG_ERR_ORERR : gd32f10x_usart.h
  • USART_INT_FLAG_IDLE : gd32f10x_usart.h
  • USART_INT_FLAG_LBD : gd32f10x_usart.h
  • USART_INT_FLAG_PERR : gd32f10x_usart.h
  • USART_INT_FLAG_RBNE : gd32f10x_usart.h
  • USART_INT_FLAG_RBNE_ORERR : gd32f10x_usart.h
  • USART_INT_FLAG_TBE : gd32f10x_usart.h
  • USART_INT_FLAG_TC : gd32f10x_usart.h
  • USART_INT_IDLE : gd32f10x_usart.h
  • USART_INT_LBD : gd32f10x_usart.h
  • USART_INT_PERR : gd32f10x_usart.h
  • USART_INT_RBNE : gd32f10x_usart.h
  • USART_INT_TBE : gd32f10x_usart.h
  • USART_INT_TC : gd32f10x_usart.h
  • usart_interrupt_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_interrupt_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_interrupt_enum : gd32f10x_usart.h
  • usart_interrupt_flag_clear() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_interrupt_flag_enum : gd32f10x_usart.h
  • usart_interrupt_flag_get() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_irda_lowpower_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_irda_mode_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_irda_mode_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_IRLP_LOW : gd32f10x_usart.h
  • USART_IRLP_NORMAL : gd32f10x_usart.h
  • USART_LBLEN_10B : gd32f10x_usart.h
  • USART_LBLEN_11B : gd32f10x_usart.h
  • usart_lin_break_dection_length_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_lin_mode_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_lin_mode_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_mute_mode_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_mute_mode_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_mute_mode_wakeup_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_parity_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_PM_EVEN : gd32f10x_usart.h
  • USART_PM_NONE : gd32f10x_usart.h
  • USART_PM_ODD : gd32f10x_usart.h
  • usart_prescaler_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_receive_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_RECEIVE_DISABLE : gd32f10x_usart.h
  • USART_RECEIVE_ENABLE : gd32f10x_usart.h
  • USART_REG_VAL : gd32f10x_usart.h
  • USART_REG_VAL2 : gd32f10x_usart.h
  • USART_REGIDX_BIT : gd32f10x_usart.h
  • USART_REGIDX_BIT2 : gd32f10x_usart.h
  • USART_RTS_DISABLE : gd32f10x_usart.h
  • USART_RTS_ENABLE : gd32f10x_usart.h
  • usart_send_break() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_smartcard_mode_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_smartcard_mode_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_smartcard_mode_nack_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_smartcard_mode_nack_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_STAT : gd32f10x_usart.h
  • USART_STAT_CTSF : gd32f10x_usart.h
  • USART_STAT_FERR : gd32f10x_usart.h
  • USART_STAT_IDLEF : gd32f10x_usart.h
  • USART_STAT_LBDF : gd32f10x_usart.h
  • USART_STAT_NERR : gd32f10x_usart.h
  • USART_STAT_ORERR : gd32f10x_usart.h
  • USART_STAT_PERR : gd32f10x_usart.h
  • USART_STAT_RBNE : gd32f10x_usart.h
  • USART_STAT_REG_OFFSET : gd32f10x_usart.h
  • USART_STAT_TBE : gd32f10x_usart.h
  • USART_STAT_TC : gd32f10x_usart.h
  • USART_STB_0_5BIT : gd32f10x_usart.h
  • USART_STB_1_5BIT : gd32f10x_usart.h
  • USART_STB_1BIT : gd32f10x_usart.h
  • USART_STB_2BIT : gd32f10x_usart.h
  • usart_stop_bit_set() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_synchronous_clock_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_synchronous_clock_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_synchronous_clock_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_transmit_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • USART_TRANSMIT_DISABLE : gd32f10x_usart.h
  • USART_TRANSMIT_ENABLE : gd32f10x_usart.h
  • USART_WL_8BIT : gd32f10x_usart.h
  • USART_WL_9BIT : gd32f10x_usart.h
  • USART_WM_ADDR : gd32f10x_usart.h
  • USART_WM_IDLE : gd32f10x_usart.h
  • usart_word_length_set() : gd32f10x_usart.h , gd32f10x_usart.c
  • USB_CFG_DESC_LEN : usbd_std.h , usb_std.h
  • USB_CFGDESC : usb_std.h
  • USB_CFGDESC_SIZE : usb_std.h
  • USB_CID : usb_regs.h
  • USB_CLASS_REQ : usbd_std.h , usb_std.h
  • USB_CORE_EMBEDDED_PHY : usb_defines.h
  • usb_core_id_enum : usb_defines.h
  • usb_core_init() : usb_core.h , usb_core.c
  • USB_CORE_INTR_READ : usb_regs.h
  • usb_core_select() : usb_core.h , usb_core.c
  • USB_CORE_SPEED_FULL : usb_defines.h
  • USB_CORE_SPEED_HIGH : usb_defines.h
  • USB_CORE_ULPI_PHY : usb_defines.h
  • USB_CTRL_DATA_IN : usb_core.h
  • USB_CTRL_DATA_OUT : usb_core.h
  • USB_CTRL_IDLE : usb_core.h
  • USB_CTRL_SETUP : usb_core.h
  • USB_CTRL_STALL : usb_core.h
  • USB_CTRL_STATUS_IN : usb_core.h
  • USB_CTRL_STATUS_OUT : usb_core.h
  • USB_CURRENT_FRAME_GET : usb_regs.h
  • USB_CURRENT_MODE_GET : usb_regs.h
  • USB_CURRENT_SPEED_GET : usb_regs.h
  • USB_DAEPINT : usb_regs.h
  • USB_DAEPINTEN : usb_regs.h
  • USB_DAIEP_INTR_READ : usb_regs.h
  • USB_DAOEP_INTR_READ : usb_regs.h
  • USB_DCFG : usb_regs.h
  • USB_DCTL : usb_regs.h
  • USB_DEP1INT : usb_regs.h
  • USB_DEP1INTEN : usb_regs.h
  • USB_DESCTYPE_BOS : usbd_std.h
  • USB_DESCTYPE_CONFIGURATION : usbd_std.h , usb_std.h
  • USB_DESCTYPE_DEVICE : usbd_std.h , usb_std.h
  • USB_DESCTYPE_DEVICE_QUALIFIER : usbd_std.h , usb_std.h
  • USB_DESCTYPE_ENDPOINT : usbd_std.h , usb_std.h
  • USB_DESCTYPE_HID : usb_std.h
  • USB_DESCTYPE_HID_REPORT : usb_std.h
  • USB_DESCTYPE_INTERFACE : usbd_std.h , usb_std.h
  • USB_DESCTYPE_INTERFACE_POWER : usb_std.h
  • USB_DESCTYPE_OTHER_SPEED_CONFIGURATION : usbd_std.h , usb_std.h
  • USB_DESCTYPE_STRING : usbd_std.h , usb_std.h
  • USB_DEV_DESC_LEN : usb_std.h
  • USB_DEV_QUALIFIER_DESC_LEN : usbd_std.h , usb_std.h
  • USB_DEVDESC : usb_std.h
  • USB_DEVDESC_SIZE : usb_std.h
  • USB_DEVICE_DESC_SIZE : usbd_std.h
  • usb_device_dev : usbd_int.h
  • USB_DEVQUADESC : usb_std.h
  • USB_DIEP0CTL : usb_regs.h
  • USB_DIEP0LEN : usb_regs.h
  • USB_DIEP0TFLEN : usb_regs.h
  • USB_DIEP1INTEN : usb_regs.h
  • USB_DIEP_INTR_READ : usb_regs.h
  • USB_DIEPFEINTEN : usb_regs.h
  • USB_DIEPINTEN : usb_regs.h
  • USB_DIEPxCTL : usb_regs.h
  • USB_DIEPxINTF : usb_regs.h
  • USB_DIEPxLEN : usb_regs.h
  • USB_DIEPxTFLEN : usb_regs.h
  • USB_DIEPxTFSTAT : usb_regs.h
  • usb_dir_enum : usb_core.h
  • USB_DIR_IN : usb_std.h
  • USB_DIR_MASK : usb_std.h
  • USB_DIR_OUT : usb_std.h
  • USB_DOEP0CTL : usb_regs.h
  • USB_DOEP0LEN : usb_regs.h
  • USB_DOEP1INTEN : usb_regs.h
  • USB_DOEP_INTR_READ : usb_regs.h
  • USB_DOEPINTEN : usb_regs.h
  • USB_DOEPxCTL : usb_regs.h
  • USB_DOEPxINTF : usb_regs.h
  • USB_DOEPxLEN : usb_regs.h
  • USB_DSTAT : usb_regs.h
  • USB_DVBUSDT : usb_regs.h
  • USB_DVBUSPT : usb_regs.h
  • USB_EP_DESC_LEN : usb_std.h
  • USB_EPDESC : usb_std.h
  • USB_EPDESC_SIZE : usb_std.h
  • USB_EPTYPE_BULK : usb_defines.h
  • USB_EPTYPE_CTRL : usb_defines.h
  • USB_EPTYPE_INTR : usb_defines.h
  • USB_EPTYPE_ISOC : usb_defines.h
  • USB_EPTYPE_MASK : usbd_std.h , usb_defines.h
  • USB_EVEN_FRAME : usb_regs.h
  • USB_FAIL : usb_core.h
  • USB_FEATURE_ENDP_HALT : usbd_std.h
  • USB_FEATURE_REMOTE_WAKEUP : usbd_std.h
  • USB_FEATURE_TEST_MODE : usbd_std.h
  • USB_FIFO : usb_regs.h
  • usb_fifo_read() : usb_core.h , usb_core.c
  • usb_fifo_write() : usb_core.h , usb_core.c
  • USB_FS_CORE_ID : usb_defines.h
  • USB_FSLSCLOCK_INIT : usb_regs.h
  • USB_GAHBCS : usb_regs.h
  • USB_GCCFG : usb_regs.h
  • USB_GINTEN : usb_regs.h
  • USB_GINTF : usb_regs.h
  • USB_GLOBAL_INT_DISABLE : usb_regs.h
  • USB_GLOBAL_INT_ENABLE : usb_regs.h
  • USB_GOTGCS : usb_regs.h
  • USB_GOTGINTF : usb_regs.h
  • USB_GRFLEN : usb_regs.h
  • USB_GRSTATP : usb_regs.h
  • USB_GRSTATR : usb_regs.h
  • USB_GRSTCTL : usb_regs.h
  • USB_GUSBCS : usb_regs.h
  • USB_HACHINT : usb_regs.h
  • USB_HACHINTEN : usb_regs.h
  • USB_HCHxCTL : usb_regs.h
  • USB_HCHxINTEN : usb_regs.h
  • USB_HCHxINTF : usb_regs.h
  • USB_HCHxLEN : usb_regs.h
  • USB_HCTL : usb_regs.h
  • USB_HFINFR : usb_regs.h
  • USB_HFT : usb_regs.h
  • USB_HID_CLASS : usb_std.h
  • USB_HIDDESC : usb_std.h
  • USB_HIDREPDESC : usb_std.h
  • USB_HNPTFLEN : usb_regs.h
  • USB_HNPTFQSTAT : usb_regs.h
  • USB_HPCS : usb_regs.h
  • USB_HPTFLEN : usb_regs.h
  • USB_HPTFQSTAT : usb_regs.h
  • USB_HS_CORE_ID : usb_defines.h
  • USB_IF_DESC_LEN : usb_std.h
  • USB_INTDESC : usb_std.h
  • USB_INTDESC_SIZE : usb_std.h
  • USB_INTPWRDESC : usb_std.h
  • USB_MAX_DEV_EPCOUNT : usb_core.h
  • USB_MAX_EP0_SIZE : usb_core.h
  • USB_MAX_FIFOS : usb_core.h
  • USB_MIN : usbd_std.h
  • usb_mode_set() : usb_core.h , usb_core.c
  • USB_MSC_CLASS : usb_std.h
  • USB_OK : usb_core.h
  • USB_OSPCFGDESC : usb_std.h
  • USB_OTG_DESC_LEN : usb_std.h
  • USB_PORT_READ : usb_regs.h
  • USB_PWRCLKCTL : usb_regs.h
  • USB_REMOTE_WAKEUP_RESET : usb_regs.h
  • USB_REMOTE_WAKEUP_SET : usb_regs.h
  • USB_REQ_MASK : usbd_std.h , usb_std.h
  • USB_REQ_RECIPIENT_MASK : usbd_std.h
  • USB_REQTYPE_DEVICE : usb_std.h , usbd_std.h
  • USB_REQTYPE_ENDPOINT : usbd_std.h , usb_std.h
  • USB_REQTYPE_INTERFACE : usbd_std.h , usb_std.h
  • USB_REQTYPE_MASK : usb_std.h
  • USB_RX : usb_core.h
  • usb_rxfifo_flush() : usb_core.c , usb_core.h
  • USB_SET_DEVADDR : usb_regs.h
  • USB_SOFT_DISCONNECT_DISABLE : usb_regs.h
  • USB_SOFT_DISCONNECT_ENABLE : usb_regs.h
  • usb_speed_enum : usb_defines.h
  • USB_SPEED_EXP_FULL : usb_regs.h
  • USB_SPEED_EXP_HIGH : usb_regs.h
  • USB_SPEED_FULL : usb_defines.h
  • USB_SPEED_HIGH : usb_defines.h
  • USB_SPEED_INP_FULL : usb_regs.h
  • USB_SPEED_LOW : usb_defines.h
  • USB_SPEED_UNKNOWN : usb_defines.h
  • USB_STANDARD_REQ : usbd_std.h , usb_std.h
  • USB_STATUS_ADDRESSED : usbd_core.h
  • USB_STATUS_CONFIGURED : usbd_core.h
  • USB_STATUS_DEFAULT : usbd_core.h
  • usb_status_enum : usb_core.h
  • USB_STATUS_REMOTE_WAKEUP : usbd_std.h
  • USB_STATUS_SELF_POWERED : usbd_std.h
  • USB_STATUS_SUSPENDED : usbd_core.h
  • USB_STRDESC : usb_std.h
  • USB_TX : usb_core.h
  • usb_txfifo_flush() : usb_core.h , usb_core.c
  • USB_VENDOR_REQ : usbd_std.h , usb_std.h
  • USBD : usbd_regs.h
  • USBD_ADDRESSED : usbd_core.h
  • USBD_BADDR : usbd_regs.h
  • USBD_BUSY : usb_core.h , usbd_core.h
  • USBD_CONFIG_STR_IDX : usbd_std.h
  • USBD_CONFIGURED : usbd_core.h
  • USBD_CONNECTED : usbd_core.h
  • USBD_CONTRL_STATUS_RX : usbd_core.h
  • USBD_CONTRL_STATUS_TX : usbd_core.h
  • usbd_control_state_enum : usb_core.h
  • usbd_core_deinit() : usbd_core.h , usbd_core.c
  • usbd_core_init() : usbd_core.h , usbd_core.c
  • USBD_CTL : usbd_regs.h
  • usbd_ctlrx() : usbd_core.h , usbd_core.c
  • usbd_ctlstatus_rx() : usbd_core.c , usbd_core.h
  • usbd_ctlstatus_tx() : usbd_core.c , usbd_core.h
  • usbd_ctltx() : usbd_core.h , usbd_core.c
  • USBD_DADDR : usbd_regs.h
  • USBD_DEFAULT : usbd_core.h
  • usbd_device_class_request() : usbd_std.c , usbd_std.h
  • usbd_dir_enum : usbd_core.h
  • USBD_DTG_RX_CLEAR : usbd_regs.h
  • USBD_DTG_RX_TOGGLE : usbd_regs.h
  • USBD_DTG_TX_CLEAR : usbd_regs.h
  • USBD_DTG_TX_TOGGLE : usbd_regs.h
  • USBD_ENDP_DOUBLE_BUF_CLEAR : usbd_regs.h
  • USBD_ENDP_DOUBLE_BUF_SET : usbd_regs.h
  • USBD_ENDP_KIND_CLEAR : usbd_regs.h
  • USBD_ENDP_KIND_SET : usbd_regs.h
  • USBD_ENDP_RX_STAT_CLEAR : usbd_regs.h
  • USBD_ENDP_RX_STATUS_GET : usbd_regs.h
  • USBD_ENDP_RX_STATUS_SET : usbd_regs.h
  • USBD_ENDP_RX_TX_STATUS_SET : usbd_regs.h
  • USBD_ENDP_TX_STAT_CLEAR : usbd_regs.h
  • USBD_ENDP_TX_STATUS_GET : usbd_regs.h
  • USBD_ENDP_TX_STATUS_SET : usbd_regs.h
  • usbd_enum_error() : usbd_std.h , usbd_std.c , usbd_std.h , usbd_std.c
  • USBD_EP0_MAX_SIZE : usbd_core.h
  • usbd_ep_clear_stall() : usbd_core.c , usbd_core.h
  • usbd_ep_data_read() : usbd_core.c , usbd_core.h
  • usbd_ep_data_write() : usbd_core.c , usbd_core.h
  • usbd_ep_deinit() : usbd_core.c , usbd_core.h , usbd_core.c
  • usbd_ep_fifo_flush() : usbd_core.c , usbd_core.h
  • usbd_ep_init() : usbd_core.c , usbd_core.h
  • usbd_ep_rx() : usbd_core.c , usbd_core.h
  • usbd_ep_stall() : usbd_core.c , usbd_core.h
  • usbd_ep_status_get() : usbd_core.h , usbd_core.c
  • usbd_ep_tx() : usbd_core.h , usbd_core.c
  • usbd_epkind_enum : usbd_core.h
  • usbd_eptype_enum : usbd_core.h
  • USBD_EPxCS : usbd_regs.h
  • USBD_FAIL : usb_core.h , usbd_core.h
  • usbd_in_transaction() : usbd_std.c , usbd_std.h , usbd_std.c , usbd_std.h
  • usbd_init() : usbd_core.c , usbd_core.h
  • usbd_int_fops : usbd_int.h
  • USBD_INTERFACE_STR_IDX : usbd_std.h
  • USBD_INTF : usbd_regs.h
  • usbd_isr() : usbd_int.h , usbd_int.c
  • USBD_LANGID_STR_IDX : usbd_std.h
  • USBD_LPMCS : usbd_regs.h
  • USBD_MFC_STR_IDX : usbd_std.h
  • USBD_OK : usb_core.h , usbd_core.h
  • usbd_out_transaction() : usbd_std.h , usbd_std.c , usbd_std.h , usbd_std.c
  • USBD_PRODUCT_STR_IDX : usbd_std.h
  • USBD_RAM : usbd_regs.h
  • USBD_REG_GET : usbd_regs.h
  • USBD_REG_SET : usbd_regs.h
  • usbd_remote_wakeup_active() : usbd_pwr.h , usbd_pwr.c
  • usbd_run_status_enum : usbd_core.h
  • USBD_RX : usbd_core.h
  • usbd_rx_count_get() : usbd_core.c , usbd_core.h
  • usbd_rxcount_get() : usbd_core.c , usbd_core.h
  • USBD_SERIAL_STR_IDX : usbd_std.h
  • usbd_setup_request_parse() : usbd_std.h , usbd_std.c
  • usbd_setup_transaction() : usbd_std.h , usbd_std.c , usbd_std.h , usbd_std.c
  • usbd_standard_request() : usbd_std.c , usbd_std.h
  • USBD_STAT : usbd_regs.h
  • usbd_status_enum : usbd_core.h , usb_core.h
  • USBD_STATUS_OUT_CLEAR : usbd_regs.h
  • USBD_STATUS_OUT_SET : usbd_regs.h
  • USBD_STRING_DESC : usbd_std.h
  • usbd_suspend() : usbd_pwr.c , usbd_pwr.h
  • USBD_SUSPENDED : usbd_core.h
  • USBD_SWBUF_RX_TOGGLE : usbd_regs.h
  • USBD_SWBUF_TX_TOGGLE : usbd_regs.h
  • USBD_TX : usbd_core.h
  • USBD_UNCONNECTED : usbd_core.h
  • usbd_vendor_request() : usbd_std.c , usbd_std.h
  • USBFS : usb_regs.h
  • USBFS_MAX_DEV_EPCOUNT : usb_defines.h
  • USBFS_MAX_FIFO_WORDLEN : usb_defines.h
  • USBFS_MAX_HOST_CHANNELCOUNT : usb_defines.h
  • USBFS_MAX_PACKET_SIZE : usb_defines.h
  • usbh_allchannel_dealloc() : usbh_hcs.c , usbh_hcs.h
  • USBH_APPLY_DEINIT : usbh_core.h
  • USBH_BUSY : usbh_core.h
  • usbh_cfg_desc : usbh_std.h , usbh_std.c
  • usbh_cfg_desc_parse() : usbh_std.c , usbh_std.h
  • USBH_CFG_DESC_SET_SIZE : usb_std.h
  • usbh_channel_alloc() : usbh_hcs.h , usbh_hcs.c
  • usbh_channel_free() : usbh_hcs.c , usbh_hcs.h
  • usbh_channel_modify() : usbh_hcs.h , usbh_hcs.c
  • usbh_channel_open() : usbh_hcs.c , usbh_hcs.h
  • usbh_connected() : usbh_core.c
  • usbh_ctltx_setup() : usbh_ctrl.h , usbh_ctrl.c
  • usbh_deinit() : usbh_core.h , usbh_core.c
  • USBH_DEVICE_ADDRESS : usbh_core.h
  • USBH_DEVICE_ADDRESS_DEFAULT : usbh_core.h
  • usbh_device_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_disconnected() : usbh_core.c
  • usbh_endpoint_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_enum_addr_set() : usbh_std.c , usbh_std.h
  • usbh_enum_cfg_set() : usbh_std.h , usbh_std.c
  • usbh_enum_desc_get() : usbh_std.h , usbh_std.c
  • USBH_FAIL : usbh_core.h
  • usbh_hcd_int_cb : usbh_core.c
  • usbh_hcd_int_fops : usbh_int.h , usbh_core.c
  • usbh_interface_desc_parse() : usbh_std.c , usbh_std.h
  • usbh_isr() : usbh_int.c , usbh_int.h
  • USBH_MAX_ERROR_COUNT : usbh_core.h
  • usbh_next_desc_get() : usbh_std.h , usbh_std.c
  • USBH_NOT_SUPPORTED : usbh_core.h
  • USBH_OK : usbh_core.h
  • USBH_SETUP_PACKET_SIZE : usbh_std.h
  • usbh_sof() : usbh_core.c
  • USBH_SPEED_UNKNOWN_ERROR : usbh_core.h
  • usbh_state_core : usbh_core.c
  • usbh_status_enum : usbh_core.h
  • usbh_string_desc_parse() : usbh_std.c , usbh_std.h
  • USBH_UNRECOVERED_ERROR : usbh_core.h
  • USBH_USER_NO_RESP : usbh_core.h
  • USBH_USER_RESP_OK : usbh_core.h
  • usbh_user_status_enum : usbh_core.h
  • usbh_xfer() : usbh_ctrl.h , usbh_ctrl.c
  • USBHS_MAX_DEV_EPCOUNT : usb_defines.h
  • USBHS_MAX_FIFO_WORDLEN : usb_defines.h
  • USBHS_MAX_HOST_CHANNELCOUNT : usb_defines.h
  • USBHS_MAX_PACKET_SIZE : usb_defines.h
  • USBREQ_CLEAR_FEATURE : usb_std.h , usbd_std.h
  • USBREQ_GET_CONFIGURATION : usbd_std.h , usb_std.h
  • USBREQ_GET_DESCRIPTOR : usbd_std.h , usb_std.h
  • USBREQ_GET_INTERFACE : usb_std.h , usbd_std.h
  • USBREQ_GET_STATUS : usb_std.h , usbd_std.h
  • USBREQ_SET_ADDRESS : usb_std.h , usbd_std.h
  • USBREQ_SET_CONFIGURATION : usb_std.h , usbd_std.h
  • USBREQ_SET_DESCRIPTOR : usb_std.h
  • USBREQ_SET_FEATURE : usb_std.h , usbd_std.h
  • USBREQ_SET_INTERFACE : usb_std.h , usbd_std.h
  • USBREQ_SYNCH_FRAME : usb_std.h
  • user_buffer_free() : usbd_core.h , usbd_core.c


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
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  • f
  • g
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  • i
  • l
  • m
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  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • VLAN_OPTION : gd32f10x_enet.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WDHT_WDHT : gd32f10x_adc.h
  • WDLT_WDLT : gd32f10x_adc.h
  • WFE_CMD : gd32f10x_pmu.h
  • WFI_CMD : gd32f10x_pmu.h
  • WIDE_STRING : usbd_std.h
  • WS_WSCNT : gd32f10x_fmc.h
  • WS_WSCNT_0 : gd32f10x_fmc.h
  • WS_WSCNT_1 : gd32f10x_fmc.h
  • WS_WSCNT_2 : gd32f10x_fmc.h
  • WWDGT : gd32f10x_wwdgt.h
  • WWDGT_CFG : gd32f10x_wwdgt.h
  • WWDGT_CFG_EWIE : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC_DIV1 : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC_DIV2 : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC_DIV4 : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC_DIV8 : gd32f10x_wwdgt.h
  • WWDGT_CFG_WIN : gd32f10x_wwdgt.h
  • wwdgt_config() : gd32f10x_wwdgt.h , gd32f10x_wwdgt.c
  • wwdgt_counter_update() : gd32f10x_wwdgt.c , gd32f10x_wwdgt.h
  • WWDGT_CTL : gd32f10x_wwdgt.h
  • WWDGT_CTL_CNT : gd32f10x_wwdgt.h
  • WWDGT_CTL_WDGTEN : gd32f10x_wwdgt.h
  • wwdgt_deinit() : gd32f10x_wwdgt.h , gd32f10x_wwdgt.c
  • wwdgt_enable() : gd32f10x_wwdgt.h , gd32f10x_wwdgt.c
  • wwdgt_flag_clear() : gd32f10x_wwdgt.c , gd32f10x_wwdgt.h
  • wwdgt_flag_get() : gd32f10x_wwdgt.c , gd32f10x_wwdgt.h
  • wwdgt_interrupt_enable() : gd32f10x_wwdgt.c , gd32f10x_wwdgt.h
  • WWDGT_STAT : gd32f10x_wwdgt.h
  • WWDGT_STAT_EWIF : gd32f10x_wwdgt.h


GD32F10x_Firmware_Library: Globals

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- a -

  • adc_calibration_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_channel_length_config() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_data_alignment_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_deinit() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_disable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_discontinuous_mode_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_dma_mode_disable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_dma_mode_enable() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_external_trigger_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_external_trigger_source_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_flag_clear() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_flag_get() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_inserted_channel_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_inserted_channel_offset_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_inserted_data_read() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_inserted_software_startconv_flag_get() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_interrupt_disable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_interrupt_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_interrupt_flag_clear() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_interrupt_flag_get() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_mode_config() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_regular_channel_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_regular_data_read() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_regular_software_startconv_flag_get() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_software_trigger_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_special_function_config() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_sync_mode_convert_value_read() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_tempsensor_vrefint_disable() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_tempsensor_vrefint_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_watchdog_disable() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_watchdog_group_channel_enable() : gd32f10x_adc.c , gd32f10x_adc.h
  • adc_watchdog_single_channel_enable() : gd32f10x_adc.h , gd32f10x_adc.c
  • adc_watchdog_threshold_config() : gd32f10x_adc.h , gd32f10x_adc.c


GD32F10x_Firmware_Library: Globals

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- b -

  • bkp_deinit() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_flag_clear() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • bkp_flag_get() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_interrupt_flag_clear() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • bkp_interrupt_flag_get() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_read_data() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_rtc_calibration_output_disable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_rtc_calibration_output_enable() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • bkp_rtc_calibration_value_set() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_rtc_output_select() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_rtc_signal_output_disable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_rtc_signal_output_enable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_tamper_active_level_set() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_tamper_detection_disable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_tamper_detection_enable() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • bkp_tamper_interrupt_disable() : gd32f10x_bkp.c , gd32f10x_bkp.h
  • bkp_tamper_interrupt_enable() : gd32f10x_bkp.h , gd32f10x_bkp.c
  • bkp_write_data() : gd32f10x_bkp.c , gd32f10x_bkp.h


GD32F10x_Firmware_Library: Globals

  • All
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- c -

  • can1_filter_start_bank() : gd32f10x_can.h , gd32f10x_can.c
  • can_debug_freeze_disable() : gd32f10x_can.c , gd32f10x_can.h
  • can_debug_freeze_enable() : gd32f10x_can.h , gd32f10x_can.c
  • can_deinit() : gd32f10x_can.c , gd32f10x_can.h
  • can_error_get() : gd32f10x_can.h , gd32f10x_can.c
  • can_fifo_release() : gd32f10x_can.h , gd32f10x_can.c
  • can_filter_init() : gd32f10x_can.h , gd32f10x_can.c
  • can_flag_clear() : gd32f10x_can.c , gd32f10x_can.h
  • can_flag_get() : gd32f10x_can.h , gd32f10x_can.c
  • can_init() : gd32f10x_can.h , gd32f10x_can.c
  • can_interrupt_disable() : gd32f10x_can.h , gd32f10x_can.c
  • can_interrupt_enable() : gd32f10x_can.h , gd32f10x_can.c
  • can_interrupt_flag_clear() : gd32f10x_can.h , gd32f10x_can.c
  • can_interrupt_flag_get() : gd32f10x_can.h , gd32f10x_can.c
  • can_message_receive() : gd32f10x_can.h , gd32f10x_can.c
  • can_message_transmit() : gd32f10x_can.c , gd32f10x_can.h
  • can_receive_error_number_get() : gd32f10x_can.h , gd32f10x_can.c
  • can_receive_message_length_get() : gd32f10x_can.h , gd32f10x_can.c
  • can_time_trigger_mode_disable() : gd32f10x_can.h , gd32f10x_can.c
  • can_time_trigger_mode_enable() : gd32f10x_can.c , gd32f10x_can.h
  • can_transmission_stop() : gd32f10x_can.h , gd32f10x_can.c
  • can_transmit_error_number_get() : gd32f10x_can.c , gd32f10x_can.h
  • can_transmit_states() : gd32f10x_can.h , gd32f10x_can.c
  • can_wakeup() : gd32f10x_can.h , gd32f10x_can.c
  • can_working_mode_set() : gd32f10x_can.c , gd32f10x_can.h
  • crc_block_data_calculate() : gd32f10x_crc.h , gd32f10x_crc.c
  • crc_data_register_read() : gd32f10x_crc.c , gd32f10x_crc.h
  • crc_data_register_reset() : gd32f10x_crc.h , gd32f10x_crc.c
  • crc_deinit() : gd32f10x_crc.h , gd32f10x_crc.c
  • crc_free_data_register_read() : gd32f10x_crc.h , gd32f10x_crc.c
  • crc_free_data_register_write() : gd32f10x_crc.h , gd32f10x_crc.c
  • crc_single_data_calculate() : gd32f10x_crc.h , gd32f10x_crc.c
  • ctrl_state_polling_fun() : usbh_ctrl.c , usbh_ctrl.h


GD32F10x_Firmware_Library: Globals

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- d -

  • dac_concurrent_data_set() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_concurrent_disable() : gd32f10x_dac.c , gd32f10x_dac.h
  • dac_concurrent_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_concurrent_output_buffer_disable() : gd32f10x_dac.c , gd32f10x_dac.h
  • dac_concurrent_output_buffer_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_concurrent_software_trigger_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_concurrent_software_trigger_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_data_set() : gd32f10x_dac.c , gd32f10x_dac.h
  • dac_deinit() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_dma_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_dma_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_lfsr_noise_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_output_buffer_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_output_buffer_enable() : gd32f10x_dac.c , gd32f10x_dac.h
  • dac_output_value_get() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_software_trigger_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_software_trigger_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_triangle_noise_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_trigger_disable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_trigger_enable() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_trigger_source_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_wave_bit_width_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • dac_wave_mode_config() : gd32f10x_dac.h , gd32f10x_dac.c
  • dbg_id_get() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_low_power_disable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_low_power_enable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_periph_disable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_periph_enable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_trace_pin_disable() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dbg_trace_pin_enable() : gd32f10x_dbg.c , gd32f10x_dbg.h
  • dbg_trace_pin_mode_set() : gd32f10x_dbg.h , gd32f10x_dbg.c
  • dma_channel_disable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_channel_enable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_circulation_disable() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_circulation_enable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_deinit() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_flag_clear() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_flag_get() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_init() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_interrupt_disable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_interrupt_enable() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_interrupt_flag_clear() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_interrupt_flag_get() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_memory_address_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_memory_increase_disable() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_memory_increase_enable() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_memory_to_memory_disable() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_memory_to_memory_enable() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_memory_width_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_periph_address_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_periph_increase_disable() : gd32f10x_dma.h , gd32f10x_dma.c
  • dma_periph_increase_enable() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_periph_width_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_priority_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_transfer_direction_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_transfer_number_config() : gd32f10x_dma.c , gd32f10x_dma.h
  • dma_transfer_number_get() : gd32f10x_dma.h , gd32f10x_dma.c


GD32F10x_Firmware_Library: Globals

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- e -

  • enet_address_filter_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_address_filter_disable() : gd32f10x_enet.c , gd32f10x_enet.h
  • enet_address_filter_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_current_desc_address_get() : gd32f10x_enet.c , gd32f10x_enet.h
  • enet_debug_status_get() : gd32f10x_enet.h
  • enet_deinit() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_desc_flag_clear() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_desc_flag_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_desc_flag_set() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_desc_information_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_descriptors_chain_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_descriptors_ring_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_dma_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_dma_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_dmaprocess_resume() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_dmaprocess_state_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_flag_clear() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_flag_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_fliter_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_fliter_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_flowcontrol_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_flowcontrol_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_flowcontrol_threshold_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_forward_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_forward_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_frame_receive() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_frame_transmit() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_initpara_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_initpara_reset() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_interrupt_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_interrupt_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_interrupt_flag_clear() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_interrupt_flag_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_mac_address_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_mac_address_set() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_missed_frame_counter_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_msc_counters_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_msc_counters_reset() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_msc_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_msc_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_pauseframe_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_pauseframe_detect_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_pauseframe_generate() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_phy_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_phy_write_read() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_phyloopback_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_phyloopback_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_coarsecorrection_systime_update() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_expected_time_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_feature_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_finecorrection_adjfreq() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_finecorrection_settime() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_flag_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_nanosecond_2_subsecond() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_normal_descriptors_chain_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_normal_descriptors_ring_init() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_pps_output_frequency_config() : gd32f10x_enet.h
  • enet_ptp_start() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_subsecond_2_nanosecond() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_subsecond_increment_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_system_time_get() : gd32f10x_enet.c , gd32f10x_enet.h
  • enet_ptp_timestamp_addend_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_timestamp_function_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptp_timestamp_update_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_ptpframe_receive_normal_mode() : gd32f10x_enet.c , gd32f10x_enet.h
  • enet_ptpframe_transmit_normal_mode() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_registers_get() : gd32f10x_enet.c , gd32f10x_enet.h
  • enet_rx_desc_delay_receive_complete_interrupt() : gd32f10x_enet.h
  • enet_rx_desc_immediate_receive_complete_interrupt() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_rx_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_rx_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_rxframe_drop() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_rxframe_size_get() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_rxprocess_check_recovery() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_software_reset() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_transmit_checksum_config() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_tx_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_tx_enable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_txfifo_flush() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_wum_feature_disable() : gd32f10x_enet.h , gd32f10x_enet.c
  • enet_wum_feature_enable() : gd32f10x_enet.c , gd32f10x_enet.h
  • enet_wum_filter_config() : gd32f10x_enet.c , gd32f10x_enet.h
  • enet_wum_filter_register_pointer_reset() : gd32f10x_enet.h , gd32f10x_enet.c
  • enum_state_polling_fun() : usbh_std.c , usbh_std.h
  • exmc_ecc_get() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_flag_clear() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_flag_get() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_interrupt_disable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_interrupt_enable() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_interrupt_flag_clear() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_interrupt_flag_get() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_nand_deinit() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_nand_disable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_nand_ecc_config() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_nand_enable() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_nand_init() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_nand_parameter_init() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_norsram_deinit() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_norsram_disable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_norsram_enable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_norsram_init() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_norsram_parameter_init() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_pccard_deinit() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_pccard_disable() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_pccard_enable() : gd32f10x_exmc.c , gd32f10x_exmc.h
  • exmc_pccard_init() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exmc_pccard_parameter_init() : gd32f10x_exmc.h , gd32f10x_exmc.c
  • exti_deinit() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_event_disable() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_event_enable() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_flag_clear() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_flag_get() : gd32f10x_exti.c , gd32f10x_exti.h
  • exti_init() : gd32f10x_exti.c , gd32f10x_exti.h
  • exti_interrupt_disable() : gd32f10x_exti.c , gd32f10x_exti.h
  • exti_interrupt_enable() : gd32f10x_exti.c , gd32f10x_exti.h
  • exti_interrupt_flag_clear() : gd32f10x_exti.c , gd32f10x_exti.h
  • exti_interrupt_flag_get() : gd32f10x_exti.c , gd32f10x_exti.h
  • exti_software_interrupt_disable() : gd32f10x_exti.h , gd32f10x_exti.c
  • exti_software_interrupt_enable() : gd32f10x_exti.h , gd32f10x_exti.c


GD32F10x_Firmware_Library: Globals

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- f -

  • fmc_bank0_erase() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank0_lock() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • fmc_bank0_ready_wait() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank0_state_get() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • fmc_bank0_unlock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank1_erase() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank1_lock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank1_ready_wait() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • fmc_bank1_state_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_bank1_unlock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_flag_clear() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_flag_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_halfword_program() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_interrupt_disable() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_interrupt_enable() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_interrupt_flag_clear() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • fmc_interrupt_flag_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_lock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_mass_erase() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_page_erase() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • fmc_unlock() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • fmc_word_program() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • fmc_wscnt_set() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • fwdgt_config() : gd32f10x_fwdgt.h , gd32f10x_fwdgt.c
  • fwdgt_counter_reload() : gd32f10x_fwdgt.h , gd32f10x_fwdgt.c
  • fwdgt_enable() : gd32f10x_fwdgt.h , gd32f10x_fwdgt.c
  • fwdgt_flag_get() : gd32f10x_fwdgt.h , gd32f10x_fwdgt.c
  • fwdgt_write_disable() : gd32f10x_fwdgt.c , gd32f10x_fwdgt.h


GD32F10x_Firmware_Library: Globals

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- g -

  • goto_up_state_fun() : usbh_core.h , usbh_core.c
  • gpio_afio_deinit() : gd32f10x_gpio.c , gd32f10x_gpio.h
  • gpio_bit_reset() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_bit_set() : gd32f10x_gpio.c , gd32f10x_gpio.h
  • gpio_bit_write() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_deinit() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_ethernet_phy_select() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_event_output_config() : gd32f10x_gpio.c , gd32f10x_gpio.h
  • gpio_event_output_disable() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_event_output_enable() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_exti_source_select() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_init() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_input_bit_get() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_input_port_get() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_output_bit_get() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_output_port_get() : gd32f10x_gpio.c , gd32f10x_gpio.h
  • gpio_pin_lock() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_pin_remap_config() : gd32f10x_gpio.h , gd32f10x_gpio.c
  • gpio_port_write() : gd32f10x_gpio.h , gd32f10x_gpio.c


GD32F10x_Firmware_Library: Globals

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- h -

  • hcd_init() : usbh_core.h , usbh_core.c
  • hcd_is_device_connected() : usbh_core.c , usbh_core.h
  • hcd_submit_request() : usbh_ctrl.h , usbh_ctrl.c
  • hcd_urb_state_get() : usbh_core.c , usbh_core.h
  • hcd_xfer_count_get() : usbh_core.c , usbh_core.h
  • host_state_polling_fun() : usbh_core.h , usbh_core.c


GD32F10x_Firmware_Library: Globals

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- i -

  • i2c_ack_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_ackpos_config() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • i2c_clock_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_data_receive() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • i2c_data_transmit() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_deinit() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_disable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_dma_enable() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • i2c_dma_last_transfer_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_dualaddr_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_flag_clear() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_flag_get() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_interrupt_disable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_interrupt_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_interrupt_flag_clear() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • i2c_interrupt_flag_get() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_master_addressing() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_mode_addr_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_pec_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_pec_transfer_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_pec_value_get() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • i2c_slave_response_to_gcall_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_smbus_arp_enable() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_smbus_issue_alert() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_smbus_type_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_software_reset_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_start_on_bus() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2c_stop_on_bus() : gd32f10x_i2c.c , gd32f10x_i2c.h
  • i2c_stretch_scl_low_config() : gd32f10x_i2c.h , gd32f10x_i2c.c
  • i2s_disable() : gd32f10x_spi.c , gd32f10x_spi.h
  • i2s_enable() : gd32f10x_spi.c , gd32f10x_spi.h
  • i2s_init() : gd32f10x_spi.h , gd32f10x_spi.c
  • i2s_psc_config() : gd32f10x_spi.h , gd32f10x_spi.c


GD32F10x_Firmware_Library: Globals

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- n -

  • nvic_irq_disable() : gd32f10x_misc.h , gd32f10x_misc.c
  • nvic_irq_enable() : gd32f10x_misc.c , gd32f10x_misc.h
  • nvic_priority_group_set() : gd32f10x_misc.h , gd32f10x_misc.c
  • nvic_vector_table_set() : gd32f10x_misc.c , gd32f10x_misc.h


GD32F10x_Firmware_Library: Globals

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- o -

  • ob_data_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_data_program() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • ob_erase() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_lock() : gd32f10x_fmc.c , gd32f10x_fmc.h
  • ob_security_protection_config() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_spc_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_unlock() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_user_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_user_write() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_write_protection_enable() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • ob_write_protection_get() : gd32f10x_fmc.h , gd32f10x_fmc.c
  • only_state_move() : usbh_core.c , usbh_core.h


GD32F10x_Firmware_Library: Globals

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- p -

  • pmu_backup_write_disable() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_backup_write_enable() : gd32f10x_pmu.c , gd32f10x_pmu.h
  • pmu_deinit() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_flag_clear() : gd32f10x_pmu.c , gd32f10x_pmu.h
  • pmu_flag_get() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_lvd_disable() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_lvd_select() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_to_deepsleepmode() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_to_sleepmode() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_to_standbymode() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_wakeup_pin_disable() : gd32f10x_pmu.h , gd32f10x_pmu.c
  • pmu_wakeup_pin_enable() : gd32f10x_pmu.c , gd32f10x_pmu.h


GD32F10x_Firmware_Library: Globals

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- r -

  • rcu_adc_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_ahb_clock_config() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • rcu_all_reset_flag_clear() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_apb1_clock_config() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • rcu_apb2_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_bkp_reset_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_bkp_reset_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_ckout0_config() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • rcu_clock_freq_get() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_deepsleep_voltage_set() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_deinit() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_flag_get() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_hxtal_clock_monitor_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_hxtal_clock_monitor_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_i2s1_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_i2s2_clock_config() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • rcu_interrupt_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_interrupt_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_interrupt_flag_clear() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_interrupt_flag_get() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_irc8m_adjust_value_set() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_osci_bypass_mode_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_osci_bypass_mode_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_osci_off() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_osci_on() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_osci_stab_wait() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_clock_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_clock_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_clock_sleep_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_clock_sleep_enable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_reset_disable() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_periph_reset_enable() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • rcu_pll_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_predv0_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_rtc_clock_config() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_system_clock_source_config() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • rcu_system_clock_source_get() : gd32f10x_rcu.h , gd32f10x_rcu.c
  • rcu_usb_clock_config() : gd32f10x_rcu.c , gd32f10x_rcu.h
  • resume_mcu() : usbd_pwr.h , usbd_pwr.c
  • rtc_alarm_config() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • rtc_configuration_mode_enter() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • rtc_configuration_mode_exit() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • rtc_counter_get() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • rtc_counter_set() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • rtc_divider_get() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • rtc_flag_clear() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • rtc_flag_get() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • rtc_interrupt_disable() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • rtc_interrupt_enable() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • rtc_lwoff_wait() : gd32f10x_rtc.c , gd32f10x_rtc.h
  • rtc_prescaler_set() : gd32f10x_rtc.h , gd32f10x_rtc.c
  • rtc_register_sync_wait() : gd32f10x_rtc.h , gd32f10x_rtc.c


GD32F10x_Firmware_Library: Globals

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- s -

  • scd_begin() : usbh_core.h , usbh_core.c
  • scd_event_handle() : usbh_core.c , usbh_core.h
  • scd_init() : usbh_core.h , usbh_core.c
  • scd_state_move() : usbh_core.c , usbh_core.h
  • scd_table_pop() : usbh_core.h , usbh_core.c
  • scd_table_push() : usbh_core.h , usbh_core.c
  • scd_table_regist() : usbh_core.h , usbh_core.c
  • sdio_bus_mode_set() : gd32f10x_sdio.c , gd32f10x_sdio.h
  • sdio_ceata_command_completion_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_ceata_command_completion_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_ceata_command_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_ceata_command_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_ceata_interrupt_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_ceata_interrupt_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_clock_config() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_clock_disable() : gd32f10x_sdio.c , gd32f10x_sdio.h
  • sdio_clock_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_command_index_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_command_response_config() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_csm_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_csm_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_config() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_counter_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_read() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_transfer_config() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_data_write() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_deinit() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_dma_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_dma_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_dsm_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_dsm_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_fifo_counter_get() : gd32f10x_sdio.c , gd32f10x_sdio.h
  • sdio_flag_clear() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_flag_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_hardware_clock_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_hardware_clock_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_interrupt_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_interrupt_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_interrupt_flag_clear() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_interrupt_flag_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_operation_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_operation_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_power_state_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_power_state_set() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_readwait_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_readwait_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_readwait_type_set() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_response_get() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_stop_readwait_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_stop_readwait_enable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_suspend_disable() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • sdio_suspend_enable() : gd32f10x_sdio.c , gd32f10x_sdio.h
  • sdio_wait_type_set() : gd32f10x_sdio.h , gd32f10x_sdio.c
  • spi_bidirectional_transfer_config() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_crc_error_clear() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_get() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_next() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_crc_off() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_on() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_polynomial_get() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_crc_polynomial_set() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_disable() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_dma_disable() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_dma_enable() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_enable() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_i2s_data_frame_format_config() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_data_receive() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_i2s_data_transmit() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_deinit() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_flag_get() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_interrupt_disable() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_interrupt_enable() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_i2s_interrupt_flag_get() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_init() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_nss_internal_high() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_nss_internal_low() : gd32f10x_spi.h , gd32f10x_spi.c
  • spi_nss_output_disable() : gd32f10x_spi.c , gd32f10x_spi.h
  • spi_nss_output_enable() : gd32f10x_spi.c , gd32f10x_spi.h
  • system_lowpower_reset() : gd32f10x_misc.h , gd32f10x_misc.c
  • system_lowpower_set() : gd32f10x_misc.c , gd32f10x_misc.h
  • systick_clksource_set() : gd32f10x_misc.h , gd32f10x_misc.c


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
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- t -

  • timer_auto_reload_shadow_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_auto_reload_shadow_enable() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_automatic_output_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_automatic_output_enable() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_autoreload_value_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_break_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_break_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_break_enable() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_channel_capture_value_register_read() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_complementary_output_polarity_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_complementary_output_state_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_control_shadow_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_control_shadow_update_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_dma_request_source_select() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_input_capture_prescaler_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_clear_config() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_channel_output_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_fast_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_mode_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_polarity_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_pulse_value_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_shadow_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_channel_output_state_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_counter_alignment() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_counter_down_direction() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_counter_read() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_counter_up_direction() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_counter_value_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_deinit() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_dma_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_dma_enable() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_dma_transfer_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_enable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_event_software_generate() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_external_clock_mode0_config() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_external_clock_mode1_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_external_clock_mode1_disable() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_external_trigger_as_external_clock_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_external_trigger_config() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_flag_clear() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_flag_get() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_hall_mode_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_init() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_input_capture_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_input_pwm_capture_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_input_trigger_source_select() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_internal_clock_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_internal_trigger_as_external_clock_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_interrupt_disable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_interrupt_enable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_interrupt_flag_clear() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_interrupt_flag_get() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_master_output_trigger_source_select() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_master_slave_mode_config() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_prescaler_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_prescaler_read() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_primary_output_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_quadrature_decoder_mode_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_repetition_value_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_single_pulse_mode_config() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_slave_mode_select() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_update_event_disable() : gd32f10x_timer.c , gd32f10x_timer.h
  • timer_update_event_enable() : gd32f10x_timer.h , gd32f10x_timer.c
  • timer_update_source_config() : gd32f10x_timer.h , gd32f10x_timer.c


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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- u -

  • usart_address_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_baudrate_set() : gd32f10x_usart.c , gd32f10x_usart.h
  • usart_data_receive() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_data_transmit() : gd32f10x_usart.c , gd32f10x_usart.h
  • usart_deinit() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_dma_receive_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_dma_transmit_config() : gd32f10x_usart.c , gd32f10x_usart.h
  • usart_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_flag_clear() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_flag_get() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_guard_time_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_halfduplex_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_halfduplex_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_hardware_flow_cts_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_hardware_flow_rts_config() : gd32f10x_usart.c , gd32f10x_usart.h
  • usart_interrupt_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_interrupt_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_interrupt_flag_clear() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_interrupt_flag_get() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_irda_lowpower_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_irda_mode_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_irda_mode_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_lin_break_dection_length_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_lin_mode_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_lin_mode_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_mute_mode_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_mute_mode_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_mute_mode_wakeup_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_parity_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_prescaler_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_receive_config() : gd32f10x_usart.c , gd32f10x_usart.h
  • usart_send_break() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_smartcard_mode_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_smartcard_mode_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_smartcard_mode_nack_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_smartcard_mode_nack_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_stop_bit_set() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_synchronous_clock_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_synchronous_clock_disable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_synchronous_clock_enable() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_transmit_config() : gd32f10x_usart.h , gd32f10x_usart.c
  • usart_word_length_set() : gd32f10x_usart.h , gd32f10x_usart.c
  • usb_core_init() : usb_core.h , usb_core.c
  • usb_core_select() : usb_core.h , usb_core.c
  • usb_fifo_read() : usb_core.h , usb_core.c
  • usb_fifo_write() : usb_core.h , usb_core.c
  • usb_mode_set() : usb_core.h , usb_core.c
  • usb_rxfifo_flush() : usb_core.h , usb_core.c
  • usb_txfifo_flush() : usb_core.h , usb_core.c
  • usbd_core_deinit() : usbd_core.h , usbd_core.c
  • usbd_core_init() : usbd_core.h , usbd_core.c
  • usbd_ctlrx() : usbd_core.h , usbd_core.c
  • usbd_ctlstatus_rx() : usbd_core.h , usbd_core.c
  • usbd_ctlstatus_tx() : usbd_core.h , usbd_core.c
  • usbd_ctltx() : usbd_core.h , usbd_core.c
  • usbd_device_class_request() : usbd_std.h , usbd_std.c
  • usbd_enum_error() : usbd_std.h , usbd_std.c , usbd_std.h , usbd_std.c
  • usbd_ep_clear_stall() : usbd_core.h , usbd_core.c , usbd_core.h , usbd_core.c
  • usbd_ep_data_read() : usbd_core.h , usbd_core.c
  • usbd_ep_data_write() : usbd_core.h , usbd_core.c
  • usbd_ep_deinit() : usbd_core.c , usbd_core.h , usbd_core.c , usbd_core.h
  • usbd_ep_fifo_flush() : usbd_core.h , usbd_core.c
  • usbd_ep_init() : usbd_core.h , usbd_core.c , usbd_core.h
  • usbd_ep_rx() : usbd_core.h , usbd_core.c , usbd_core.h
  • usbd_ep_stall() : usbd_core.h , usbd_core.c , usbd_core.h
  • usbd_ep_status_get() : usbd_core.h , usbd_core.c
  • usbd_ep_tx() : usbd_core.h , usbd_core.c , usbd_core.h , usbd_core.c
  • usbd_in_transaction() : usbd_std.h , usbd_std.c , usbd_std.h
  • usbd_init() : usbd_core.c , usbd_core.h
  • usbd_isr() : usbd_int.h , usbd_int.c , usbd_int.h
  • usbd_out_transaction() : usbd_std.h , usbd_std.c , usbd_std.h
  • usbd_remote_wakeup_active() : usbd_pwr.c , usbd_pwr.h
  • usbd_rx_count_get() : usbd_core.c , usbd_core.h
  • usbd_rxcount_get() : usbd_core.c , usbd_core.h
  • usbd_setup_request_parse() : usbd_std.c , usbd_std.h
  • usbd_setup_transaction() : usbd_std.c , usbd_std.h
  • usbd_standard_request() : usbd_std.h , usbd_std.c
  • usbd_suspend() : usbd_pwr.c , usbd_pwr.h
  • usbd_vendor_request() : usbd_std.h , usbd_std.c
  • usbh_allchannel_dealloc() : usbh_hcs.h , usbh_hcs.c
  • usbh_cfg_desc_parse() : usbh_std.c , usbh_std.h
  • usbh_channel_alloc() : usbh_hcs.c , usbh_hcs.h
  • usbh_channel_free() : usbh_hcs.c , usbh_hcs.h
  • usbh_channel_modify() : usbh_hcs.h , usbh_hcs.c
  • usbh_channel_open() : usbh_hcs.c , usbh_hcs.h
  • usbh_connected() : usbh_core.c
  • usbh_ctltx_setup() : usbh_ctrl.h , usbh_ctrl.c
  • usbh_deinit() : usbh_core.c , usbh_core.h
  • usbh_device_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_disconnected() : usbh_core.c
  • usbh_endpoint_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_enum_addr_set() : usbh_std.h , usbh_std.c
  • usbh_enum_cfg_set() : usbh_std.h , usbh_std.c
  • usbh_enum_desc_get() : usbh_std.h , usbh_std.c
  • usbh_interface_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_isr() : usbh_int.c , usbh_int.h
  • usbh_next_desc_get() : usbh_std.c , usbh_std.h
  • usbh_sof() : usbh_core.c
  • usbh_string_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_xfer() : usbh_ctrl.h , usbh_ctrl.c
  • user_buffer_free() : usbd_core.h , usbd_core.c


GD32F10x_Firmware_Library: Globals

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  • w

- w -

  • wwdgt_config() : gd32f10x_wwdgt.h , gd32f10x_wwdgt.c
  • wwdgt_counter_update() : gd32f10x_wwdgt.c , gd32f10x_wwdgt.h
  • wwdgt_deinit() : gd32f10x_wwdgt.h , gd32f10x_wwdgt.c
  • wwdgt_enable() : gd32f10x_wwdgt.c , gd32f10x_wwdgt.h
  • wwdgt_flag_clear() : gd32f10x_wwdgt.h , gd32f10x_wwdgt.c
  • wwdgt_flag_get() : gd32f10x_wwdgt.h , gd32f10x_wwdgt.c
  • wwdgt_interrupt_enable() : gd32f10x_wwdgt.c , gd32f10x_wwdgt.h


GD32F10x_Firmware_Library: Globals

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  • c
  • d
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  • h
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  • p
  • u

- c -

  • class_polling_cb : usbh_core.c
  • ctrl_data_wait_flag : usbh_ctrl.c
  • ctrl_handle_table : usbh_ctrl.h , usbh_ctrl.c
  • ctrl_polling_handle_flag : usbh_ctrl.h , usbh_ctrl.c
  • ctrl_setup_wait_flag : usbh_ctrl.c
  • ctrl_state_handle : usbh_ctrl.c
  • ctrl_status_wait_flag : usbh_ctrl.c

- d -

  • dma_current_ptp_rxdesc : gd32f10x_enet.c
  • dma_current_ptp_txdesc : gd32f10x_enet.c
  • dma_current_rxdesc : gd32f10x_enet.c
  • dma_current_txdesc : gd32f10x_enet.c

- e -

  • enum_handle_table : usbh_std.h , usbh_std.c
  • enum_polling_handle_flag : usbh_std.h , usbh_std.c
  • enum_state_handle : usbh_std.c

- g -

  • g_device_address : usbd_std.c
  • g_ESOF_count : usbd_int.c , usbd_pwr.c
  • g_free_buf_addr : usbd_core.h , usbd_core.c
  • g_interrupt_mask : usbd_core.c , usbd_int.c
  • g_remote_wakeup_on : usbd_int.c , usbd_pwr.c
  • g_suspend_enabled : usbd_int.c , usbd_pwr.c

- h -

  • host_handle_table : usbh_core.c
  • host_state_handle : usbh_core.c

- l -

  • local_buffer : usbh_std.c

- p -

  • pbuf_reg : usbd_core.h , usbd_core.c

- u -

  • usb_device_dev : usbd_int.h
  • usbd_int_fops : usbd_int.h
  • usbh_cfg_desc : usbh_std.h , usbh_std.c
  • usbh_hcd_int_cb : usbh_core.c
  • usbh_hcd_int_fops : usbh_int.h , usbh_core.c
  • usbh_state_core : usbh_core.c


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • ACT_FUN : usbh_core.h
  • bit_status : gd32f10x_gpio.h


GD32F10x_Firmware_Library: Globals

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  • b
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- b -

  • bkp_data_register_enum : gd32f10x_bkp.h

- c -

  • can_error_enum : gd32f10x_can.h
  • can_flag_enum : gd32f10x_can.h
  • can_interrupt_flag_enum : gd32f10x_can.h
  • can_transmit_state_enum : gd32f10x_can.h
  • ctrl_event_enum : usbh_ctrl.h
  • ctrl_state_enum : usbh_core.h

- d -

  • dbg_periph_enum : gd32f10x_dbg.h
  • dbuf_ep_dir_enum : usbd_regs.h
  • dma_channel_enum : gd32f10x_dma.h

- e -

  • enet_chksumconf_enum : gd32f10x_enet.h
  • enet_desc_reg_enum : gd32f10x_enet.h
  • enet_descstate_enum : gd32f10x_enet.h
  • enet_dmadirection_enum : gd32f10x_enet.h
  • enet_flag_clear_enum : gd32f10x_enet.h
  • enet_flag_enum : gd32f10x_enet.h
  • enet_frmrecept_enum : gd32f10x_enet.h
  • enet_int_enum : gd32f10x_enet.h
  • enet_int_flag_clear_enum : gd32f10x_enet.h
  • enet_int_flag_enum : gd32f10x_enet.h
  • enet_macaddress_enum : gd32f10x_enet.h
  • enet_mediamode_enum : gd32f10x_enet.h
  • enet_msc_counter_enum : gd32f10x_enet.h
  • enet_option_enum : gd32f10x_enet.h
  • enet_phydirection_enum : gd32f10x_enet.h
  • enet_ptp_function_enum : gd32f10x_enet.h
  • enet_regdirection_enum : gd32f10x_enet.h
  • enet_registers_type_enum : gd32f10x_enet.h
  • enum_event_enum : usbh_std.h
  • enum_state_enum : usbh_core.h
  • exti_line_enum : gd32f10x_exti.h
  • exti_mode_enum : gd32f10x_exti.h
  • exti_trig_type_enum : gd32f10x_exti.h

- f -

  • fmc_flag_enum : gd32f10x_fmc.h
  • fmc_int_enum : gd32f10x_fmc.h
  • fmc_interrupt_flag_enum : gd32f10x_fmc.h
  • fmc_state_enum : gd32f10x_fmc.h

- h -

  • hc_status_enum : usb_core.h
  • host_event_enum : usbh_core.h
  • host_state_enum : usbh_core.h

- r -

  • rcu_clock_freq_enum : gd32f10x_rcu.h
  • rcu_flag_enum : gd32f10x_rcu.h
  • rcu_int_enum : gd32f10x_rcu.h
  • rcu_int_flag_clear_enum : gd32f10x_rcu.h
  • rcu_int_flag_enum : gd32f10x_rcu.h
  • rcu_osci_type_enum : gd32f10x_rcu.h
  • rcu_periph_enum : gd32f10x_rcu.h
  • rcu_periph_reset_enum : gd32f10x_rcu.h
  • rcu_periph_sleep_enum : gd32f10x_rcu.h

- u -

  • urb_state_enum : usb_core.h
  • usart_flag_enum : gd32f10x_usart.h
  • usart_interrupt_enum : gd32f10x_usart.h
  • usart_interrupt_flag_enum : gd32f10x_usart.h
  • usb_core_id_enum : usb_defines.h
  • usb_dir_enum : usb_core.h
  • usb_speed_enum : usb_defines.h
  • usb_status_enum : usb_core.h
  • usbd_control_state_enum : usb_core.h
  • usbd_dir_enum : usbd_core.h
  • usbd_epkind_enum : usbd_core.h
  • usbd_eptype_enum : usbd_core.h
  • usbd_run_status_enum : usbd_core.h
  • usbd_status_enum : usbd_core.h , usb_core.h
  • usbh_status_enum : usbh_core.h
  • usbh_user_status_enum : usbh_core.h


GD32F10x_Firmware_Library: Globals

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- a -

  • ALL_DMA_REG : gd32f10x_enet.h
  • ALL_MAC_REG : gd32f10x_enet.h
  • ALL_MSC_REG : gd32f10x_enet.h
  • ALL_PTP_REG : gd32f10x_enet.h


GD32F10x_Firmware_Library: Globals

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- b -

  • BKP_DATA_0 : gd32f10x_bkp.h
  • BKP_DATA_1 : gd32f10x_bkp.h
  • BKP_DATA_10 : gd32f10x_bkp.h
  • BKP_DATA_11 : gd32f10x_bkp.h
  • BKP_DATA_12 : gd32f10x_bkp.h
  • BKP_DATA_13 : gd32f10x_bkp.h
  • BKP_DATA_14 : gd32f10x_bkp.h
  • BKP_DATA_15 : gd32f10x_bkp.h
  • BKP_DATA_16 : gd32f10x_bkp.h
  • BKP_DATA_17 : gd32f10x_bkp.h
  • BKP_DATA_18 : gd32f10x_bkp.h
  • BKP_DATA_19 : gd32f10x_bkp.h
  • BKP_DATA_2 : gd32f10x_bkp.h
  • BKP_DATA_20 : gd32f10x_bkp.h
  • BKP_DATA_21 : gd32f10x_bkp.h
  • BKP_DATA_22 : gd32f10x_bkp.h
  • BKP_DATA_23 : gd32f10x_bkp.h
  • BKP_DATA_24 : gd32f10x_bkp.h
  • BKP_DATA_25 : gd32f10x_bkp.h
  • BKP_DATA_26 : gd32f10x_bkp.h
  • BKP_DATA_27 : gd32f10x_bkp.h
  • BKP_DATA_28 : gd32f10x_bkp.h
  • BKP_DATA_29 : gd32f10x_bkp.h
  • BKP_DATA_3 : gd32f10x_bkp.h
  • BKP_DATA_30 : gd32f10x_bkp.h
  • BKP_DATA_31 : gd32f10x_bkp.h
  • BKP_DATA_32 : gd32f10x_bkp.h
  • BKP_DATA_33 : gd32f10x_bkp.h
  • BKP_DATA_34 : gd32f10x_bkp.h
  • BKP_DATA_35 : gd32f10x_bkp.h
  • BKP_DATA_36 : gd32f10x_bkp.h
  • BKP_DATA_37 : gd32f10x_bkp.h
  • BKP_DATA_38 : gd32f10x_bkp.h
  • BKP_DATA_39 : gd32f10x_bkp.h
  • BKP_DATA_4 : gd32f10x_bkp.h
  • BKP_DATA_40 : gd32f10x_bkp.h
  • BKP_DATA_41 : gd32f10x_bkp.h
  • BKP_DATA_5 : gd32f10x_bkp.h
  • BKP_DATA_6 : gd32f10x_bkp.h
  • BKP_DATA_7 : gd32f10x_bkp.h
  • BKP_DATA_8 : gd32f10x_bkp.h
  • BKP_DATA_9 : gd32f10x_bkp.h


GD32F10x_Firmware_Library: Globals

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- c -

  • CAN_ERROR_ACK : gd32f10x_can.h
  • CAN_ERROR_BITDOMINANTER : gd32f10x_can.h
  • CAN_ERROR_BITRECESSIVE : gd32f10x_can.h
  • CAN_ERROR_CRC : gd32f10x_can.h
  • CAN_ERROR_FILL : gd32f10x_can.h
  • CAN_ERROR_FORMATE : gd32f10x_can.h
  • CAN_ERROR_NONE : gd32f10x_can.h
  • CAN_ERROR_SOFTWARECFG : gd32f10x_can.h
  • CAN_FLAG_BOERR : gd32f10x_can.h
  • CAN_FLAG_MTE0 : gd32f10x_can.h
  • CAN_FLAG_MTE1 : gd32f10x_can.h
  • CAN_FLAG_MTE2 : gd32f10x_can.h
  • CAN_FLAG_MTF0 : gd32f10x_can.h
  • CAN_FLAG_MTF1 : gd32f10x_can.h
  • CAN_FLAG_MTF2 : gd32f10x_can.h
  • CAN_FLAG_PERR : gd32f10x_can.h
  • CAN_FLAG_RFF0 : gd32f10x_can.h
  • CAN_FLAG_RFF1 : gd32f10x_can.h
  • CAN_FLAG_RFO0 : gd32f10x_can.h
  • CAN_FLAG_RFO1 : gd32f10x_can.h
  • CAN_FLAG_WERR : gd32f10x_can.h
  • CAN_INT_FLAG_ERRIF : gd32f10x_can.h
  • CAN_INT_FLAG_MTF0 : gd32f10x_can.h
  • CAN_INT_FLAG_MTF1 : gd32f10x_can.h
  • CAN_INT_FLAG_MTF2 : gd32f10x_can.h
  • CAN_INT_FLAG_RFF0 : gd32f10x_can.h
  • CAN_INT_FLAG_RFF1 : gd32f10x_can.h
  • CAN_INT_FLAG_RFO0 : gd32f10x_can.h
  • CAN_INT_FLAG_RFO1 : gd32f10x_can.h
  • CAN_INT_FLAG_SLPIF : gd32f10x_can.h
  • CAN_INT_FLAG_WUIF : gd32f10x_can.h
  • CAN_TRANSMIT_FAILED : gd32f10x_can.h
  • CAN_TRANSMIT_NOMAILBOX : gd32f10x_can.h
  • CAN_TRANSMIT_OK : gd32f10x_can.h
  • CAN_TRANSMIT_PENDING : gd32f10x_can.h
  • CK_AHB : gd32f10x_rcu.h
  • CK_APB1 : gd32f10x_rcu.h
  • CK_APB2 : gd32f10x_rcu.h
  • CK_SYS : gd32f10x_rcu.h
  • CTRL_COMPLETE : usbh_core.h
  • CTRL_DATA : usbh_core.h
  • CTRL_ERROR : usbh_core.h
  • CTRL_EVENT_COMPLETE : usbh_ctrl.h
  • CTRL_EVENT_DATA : usbh_ctrl.h
  • CTRL_EVENT_ERROR : usbh_ctrl.h
  • CTRL_EVENT_IDLE : usbh_ctrl.h
  • CTRL_EVENT_SETUP : usbh_ctrl.h
  • CTRL_EVENT_STALLED : usbh_ctrl.h
  • CTRL_EVENT_STATUS : usbh_ctrl.h
  • CTRL_IDLE : usbh_core.h
  • CTRL_SETUP : usbh_core.h
  • CTRL_STALLED : usbh_core.h
  • CTRL_STATUS : usbh_core.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • a
  • b
  • c
  • d
  • e
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  • r
  • s
  • t
  • u
  • v

- d -

  • DBG_CAN0_HOLD : gd32f10x_dbg.h
  • DBG_FWDGT_HOLD : gd32f10x_dbg.h
  • DBG_I2C0_HOLD : gd32f10x_dbg.h
  • DBG_I2C1_HOLD : gd32f10x_dbg.h
  • DBG_TIMER0_HOLD : gd32f10x_dbg.h
  • DBG_TIMER1_HOLD : gd32f10x_dbg.h
  • DBG_TIMER2_HOLD : gd32f10x_dbg.h
  • DBG_TIMER3_HOLD : gd32f10x_dbg.h
  • DBG_TIMER4_HOLD : gd32f10x_dbg.h
  • DBG_TIMER5_HOLD : gd32f10x_dbg.h
  • DBG_TIMER6_HOLD : gd32f10x_dbg.h
  • DBG_TIMER7_HOLD : gd32f10x_dbg.h
  • DBG_WWDGT_HOLD : gd32f10x_dbg.h
  • DBUF_EP_ERR : usbd_regs.h
  • DBUF_EP_IN : usbd_regs.h
  • DBUF_EP_OUT : usbd_regs.h
  • DMA_ARBITRATION_OPTION : gd32f10x_enet.h
  • DMA_CH0 : gd32f10x_dma.h
  • DMA_CH1 : gd32f10x_dma.h
  • DMA_CH2 : gd32f10x_dma.h
  • DMA_CH3 : gd32f10x_dma.h
  • DMA_CH4 : gd32f10x_dma.h
  • DMA_CH5 : gd32f10x_dma.h
  • DMA_CH6 : gd32f10x_dma.h
  • DMA_MAXBURST_OPTION : gd32f10x_enet.h
  • DMA_OPTION : gd32f10x_enet.h
  • DMABUS_OPTION : gd32f10x_enet.h


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • a
  • b
  • c
  • d
  • e
  • f
  • h
  • i
  • r
  • s
  • t
  • u
  • v

- e -

  • ENDP_BULK : usbd_core.h
  • ENDP_CONTROL : usbd_core.h
  • ENDP_DBL_BUF : usbd_core.h
  • ENDP_INT : usbd_core.h
  • ENDP_ISOC : usbd_core.h
  • ENDP_SNG_BUF : usbd_core.h
  • ENET_100M_FULLDUPLEX : gd32f10x_enet.h
  • ENET_100M_HALFDUPLEX : gd32f10x_enet.h
  • ENET_10M_FULLDUPLEX : gd32f10x_enet.h
  • ENET_10M_HALFDUPLEX : gd32f10x_enet.h
  • ENET_AUTO_NEGOTIATION : gd32f10x_enet.h
  • ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES : gd32f10x_enet.h
  • ENET_AUTOCHECKSUM_DROP_FAILFRAMES : gd32f10x_enet.h
  • ENET_BROADCAST_FRAMES_DROP : gd32f10x_enet.h
  • ENET_BROADCAST_FRAMES_PASS : gd32f10x_enet.h
  • ENET_DMA_FLAG_AI : gd32f10x_enet.h
  • ENET_DMA_FLAG_AI_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_EB_ACCESS_ERROR : gd32f10x_enet.h
  • ENET_DMA_FLAG_EB_DMA_ERROR : gd32f10x_enet.h
  • ENET_DMA_FLAG_EB_TRANSFER_ERROR : gd32f10x_enet.h
  • ENET_DMA_FLAG_ER : gd32f10x_enet.h
  • ENET_DMA_FLAG_ER_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_ET : gd32f10x_enet.h
  • ENET_DMA_FLAG_ET_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_FBE : gd32f10x_enet.h
  • ENET_DMA_FLAG_FBE_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_MSC : gd32f10x_enet.h
  • ENET_DMA_FLAG_NI : gd32f10x_enet.h
  • ENET_DMA_FLAG_NI_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RBU : gd32f10x_enet.h
  • ENET_DMA_FLAG_RBU_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RO : gd32f10x_enet.h
  • ENET_DMA_FLAG_RO_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RPS : gd32f10x_enet.h
  • ENET_DMA_FLAG_RPS_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RS : gd32f10x_enet.h
  • ENET_DMA_FLAG_RS_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_RWT : gd32f10x_enet.h
  • ENET_DMA_FLAG_RWT_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TBU : gd32f10x_enet.h
  • ENET_DMA_FLAG_TBU_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TJT : gd32f10x_enet.h
  • ENET_DMA_FLAG_TJT_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TPS : gd32f10x_enet.h
  • ENET_DMA_FLAG_TPS_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TS : gd32f10x_enet.h
  • ENET_DMA_FLAG_TS_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_TST : gd32f10x_enet.h
  • ENET_DMA_FLAG_TU : gd32f10x_enet.h
  • ENET_DMA_FLAG_TU_CLR : gd32f10x_enet.h
  • ENET_DMA_FLAG_WUM : gd32f10x_enet.h
  • ENET_DMA_INT_AIE : gd32f10x_enet.h
  • ENET_DMA_INT_ERIE : gd32f10x_enet.h
  • ENET_DMA_INT_ETIE : gd32f10x_enet.h
  • ENET_DMA_INT_FBEIE : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_AI : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_AI_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_ER : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_ER_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_ET : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_ET_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_FBE : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_FBE_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_MSC : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_NI : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_NI_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RBU : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RBU_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RO : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RO_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RPS : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RPS_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RS : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RS_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RWT : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_RWT_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TBU : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TBU_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TJT : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TJT_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TPS : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TPS_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TS : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TS_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TST : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TU : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_TU_CLR : gd32f10x_enet.h
  • ENET_DMA_INT_FLAG_WUM : gd32f10x_enet.h
  • ENET_DMA_INT_NIE : gd32f10x_enet.h
  • ENET_DMA_INT_RBUIE : gd32f10x_enet.h
  • ENET_DMA_INT_RIE : gd32f10x_enet.h
  • ENET_DMA_INT_ROIE : gd32f10x_enet.h
  • ENET_DMA_INT_RPSIE : gd32f10x_enet.h
  • ENET_DMA_INT_RWTIE : gd32f10x_enet.h
  • ENET_DMA_INT_TBUIE : gd32f10x_enet.h
  • ENET_DMA_INT_TIE : gd32f10x_enet.h
  • ENET_DMA_INT_TJTIE : gd32f10x_enet.h
  • ENET_DMA_INT_TPSIE : gd32f10x_enet.h
  • ENET_DMA_INT_TUIE : gd32f10x_enet.h
  • ENET_DMA_RX : gd32f10x_enet.h
  • ENET_DMA_TX : gd32f10x_enet.h
  • ENET_LOOPBACKMODE : gd32f10x_enet.h
  • ENET_MAC_ADDRESS0 : gd32f10x_enet.h
  • ENET_MAC_ADDRESS1 : gd32f10x_enet.h
  • ENET_MAC_ADDRESS2 : gd32f10x_enet.h
  • ENET_MAC_ADDRESS3 : gd32f10x_enet.h
  • ENET_MAC_FLAG_FLOWCONTROL : gd32f10x_enet.h
  • ENET_MAC_FLAG_MPKR : gd32f10x_enet.h
  • ENET_MAC_FLAG_MSC : gd32f10x_enet.h
  • ENET_MAC_FLAG_MSCR : gd32f10x_enet.h
  • ENET_MAC_FLAG_MSCT : gd32f10x_enet.h
  • ENET_MAC_FLAG_TMST : gd32f10x_enet.h
  • ENET_MAC_FLAG_WUFR : gd32f10x_enet.h
  • ENET_MAC_FLAG_WUM : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_MSC : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_MSCR : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_MSCT : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_TMST : gd32f10x_enet.h
  • ENET_MAC_INT_FLAG_WUM : gd32f10x_enet.h
  • ENET_MAC_INT_TMSTIM : gd32f10x_enet.h
  • ENET_MAC_INT_WUMIM : gd32f10x_enet.h
  • ENET_MSC_FLAG_RFAE : gd32f10x_enet.h
  • ENET_MSC_FLAG_RFCE : gd32f10x_enet.h
  • ENET_MSC_FLAG_RGUF : gd32f10x_enet.h
  • ENET_MSC_FLAG_TGF : gd32f10x_enet.h
  • ENET_MSC_FLAG_TGFMSC : gd32f10x_enet.h
  • ENET_MSC_FLAG_TGFSC : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_RFAE : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_RFCE : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_RGUF : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_TGF : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_TGFMSC : gd32f10x_enet.h
  • ENET_MSC_INT_FLAG_TGFSC : gd32f10x_enet.h
  • ENET_MSC_INT_RFAEIM : gd32f10x_enet.h
  • ENET_MSC_INT_RFCEIM : gd32f10x_enet.h
  • ENET_MSC_INT_RGUFIM : gd32f10x_enet.h
  • ENET_MSC_INT_TGFIM : gd32f10x_enet.h
  • ENET_MSC_INT_TGFMSCIM : gd32f10x_enet.h
  • ENET_MSC_INT_TGFSCIM : gd32f10x_enet.h
  • ENET_MSC_RX_RFAECNT : gd32f10x_enet.h
  • ENET_MSC_RX_RFCECNT : gd32f10x_enet.h
  • ENET_MSC_RX_RGUFCNT : gd32f10x_enet.h
  • ENET_MSC_TX_MSCCNT : gd32f10x_enet.h
  • ENET_MSC_TX_SCCNT : gd32f10x_enet.h
  • ENET_MSC_TX_TGFCNT : gd32f10x_enet.h
  • ENET_NO_AUTOCHECKSUM : gd32f10x_enet.h
  • ENET_PHY_READ : gd32f10x_enet.h
  • ENET_PHY_WRITE : gd32f10x_enet.h
  • ENET_PROMISCUOUS_MODE : gd32f10x_enet.h
  • ENET_PTP_ADDEND_UPDATE : gd32f10x_enet.h
  • ENET_PTP_COARSEMODE : gd32f10x_enet.h
  • ENET_PTP_FINEMODE : gd32f10x_enet.h
  • ENET_PTP_SYSTIME_INIT : gd32f10x_enet.h
  • ENET_PTP_SYSTIME_UPDATE : gd32f10x_enet.h
  • ENET_RECEIVEALL : gd32f10x_enet.h
  • ENET_REG_READ : gd32f10x_enet.h
  • ENET_REG_WRITE : gd32f10x_enet.h
  • ENET_RX_CURRENT_BUFFER : gd32f10x_enet.h
  • ENET_RX_CURRENT_DESC : gd32f10x_enet.h
  • ENET_RX_DESC_TABLE : gd32f10x_enet.h
  • ENET_TX_CURRENT_BUFFER : gd32f10x_enet.h
  • ENET_TX_CURRENT_DESC : gd32f10x_enet.h
  • ENET_TX_DESC_TABLE : gd32f10x_enet.h
  • ENUM_DEV_CONFIGURED : usbh_core.h
  • ENUM_EVENT_SET_ADDR : usbh_std.h
  • ENUM_GET_CFG_DESC : usbh_core.h
  • ENUM_GET_FULL_CFG_DESC : usbh_core.h
  • ENUM_GET_FULL_DEV_DESC : usbh_core.h
  • ENUM_GET_MFC_STRING_DESC : usbh_core.h
  • ENUM_GET_PRODUCT_STRING_DESC : usbh_core.h
  • ENUM_GET_SERIALNUM_STRING_DESC : usbh_core.h
  • ENUM_IDLE : usbh_core.h
  • ENUM_SET_ADDR : usbh_core.h
  • ENUM_SET_CONFIGURATION : usbh_core.h
  • ENUN_EVENT_DEV_CONFIGURED : usbh_std.h
  • ENUN_EVENT_GET_CFG_DESC : usbh_std.h
  • ENUN_EVENT_GET_FULL_CFG_DESC : usbh_std.h
  • ENUN_EVENT_GET_FULL_DEV_DESC : usbh_std.h
  • ENUN_EVENT_GET_MFC_STRING_DESC : usbh_std.h
  • ENUN_EVENT_GET_PRODUCT_STRING_DESC : usbh_std.h
  • ENUN_EVENT_GET_SERIALNUM_STRING_DESC : usbh_std.h
  • ENUN_EVENT_IDLE : usbh_std.h
  • ENUN_EVENT_SET_CONFIGURATION : usbh_std.h
  • EXTI_0 : gd32f10x_exti.h
  • EXTI_1 : gd32f10x_exti.h
  • EXTI_10 : gd32f10x_exti.h
  • EXTI_11 : gd32f10x_exti.h
  • EXTI_12 : gd32f10x_exti.h
  • EXTI_13 : gd32f10x_exti.h
  • EXTI_14 : gd32f10x_exti.h
  • EXTI_15 : gd32f10x_exti.h
  • EXTI_16 : gd32f10x_exti.h
  • EXTI_17 : gd32f10x_exti.h
  • EXTI_18 : gd32f10x_exti.h
  • EXTI_19 : gd32f10x_exti.h
  • EXTI_2 : gd32f10x_exti.h
  • EXTI_3 : gd32f10x_exti.h
  • EXTI_4 : gd32f10x_exti.h
  • EXTI_5 : gd32f10x_exti.h
  • EXTI_6 : gd32f10x_exti.h
  • EXTI_7 : gd32f10x_exti.h
  • EXTI_8 : gd32f10x_exti.h
  • EXTI_9 : gd32f10x_exti.h
  • EXTI_EVENT : gd32f10x_exti.h
  • EXTI_INTERRUPT : gd32f10x_exti.h
  • EXTI_TRIG_BOTH : gd32f10x_exti.h
  • EXTI_TRIG_FALLING : gd32f10x_exti.h
  • EXTI_TRIG_RISING : gd32f10x_exti.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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  • Enumerator
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  • h
  • i
  • r
  • s
  • t
  • u
  • v

- f -

  • FILTER_OPTION : gd32f10x_enet.h
  • FLOWCTL_OPTION : gd32f10x_enet.h
  • FMC_BUSY : gd32f10x_fmc.h
  • FMC_FLAG_BANK0_BUSY : gd32f10x_fmc.h
  • FMC_FLAG_BANK0_END : gd32f10x_fmc.h
  • FMC_FLAG_BANK0_PGERR : gd32f10x_fmc.h
  • FMC_FLAG_BANK0_WPERR : gd32f10x_fmc.h
  • FMC_FLAG_BANK1_BUSY : gd32f10x_fmc.h
  • FMC_FLAG_BANK1_END : gd32f10x_fmc.h
  • FMC_FLAG_BANK1_PGERR : gd32f10x_fmc.h
  • FMC_FLAG_BANK1_WPERR : gd32f10x_fmc.h
  • FMC_FLAG_OBERR : gd32f10x_fmc.h
  • FMC_INT_BANK0_END : gd32f10x_fmc.h
  • FMC_INT_BANK0_ERR : gd32f10x_fmc.h
  • FMC_INT_BANK1_END : gd32f10x_fmc.h
  • FMC_INT_BANK1_ERR : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK0_END : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK0_PGERR : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK0_WPERR : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK1_END : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK1_PGERR : gd32f10x_fmc.h
  • FMC_INT_FLAG_BANK1_WPERR : gd32f10x_fmc.h
  • FMC_PGERR : gd32f10x_fmc.h
  • FMC_READY : gd32f10x_fmc.h
  • FMC_TOERR : gd32f10x_fmc.h
  • FMC_WPERR : gd32f10x_fmc.h
  • FORWARD_OPTION : gd32f10x_enet.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
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  • Enumerator
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  • d
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  • h
  • i
  • r
  • s
  • t
  • u
  • v

- h -

  • HALFDUPLEX_OPTION : gd32f10x_enet.h
  • HASHH_OPTION : gd32f10x_enet.h
  • HASHL_OPTION : gd32f10x_enet.h
  • HC_BBERR : usb_core.h
  • HC_DTGERR : usb_core.h
  • HC_HALTED : usb_core.h
  • HC_IDLE : usb_core.h
  • HC_NAK : usb_core.h
  • HC_NYET : usb_core.h
  • HC_STALL : usb_core.h
  • HC_TRACERR : usb_core.h
  • HC_XF : usb_core.h
  • HOST_CLASS : usbh_core.h
  • HOST_CLASS_REQUEST : usbh_core.h
  • HOST_DETECT_DEV_SPEED : usbh_core.h
  • HOST_DEV_ATTACHED : usbh_core.h
  • HOST_DEV_DETACHED : usbh_core.h
  • HOST_ENUMERATION : usbh_core.h
  • HOST_ERROR : usbh_core.h
  • HOST_EVENT_ATTACHED : usbh_core.h
  • HOST_EVENT_CLASS : usbh_core.h
  • HOST_EVENT_CLASS_REQ : usbh_core.h
  • HOST_EVENT_DEV_DETACHED : usbh_core.h
  • HOST_EVENT_ENUM : usbh_core.h
  • HOST_EVENT_ERROR : usbh_core.h
  • HOST_EVENT_IDLE : usbh_core.h
  • HOST_EVENT_USER_INPUT : usbh_core.h
  • HOST_IDLE : usbh_core.h
  • HOST_SUSPENDED : usbh_core.h
  • HOST_USER_INPUT : usbh_core.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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  • Functions
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  • r
  • s
  • t
  • u
  • v

- i -

  • INTERFRAMEGAP_OPTION : gd32f10x_enet.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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  • Functions
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- r -

  • RCU_ADC0 : gd32f10x_rcu.h
  • RCU_ADC0RST : gd32f10x_rcu.h
  • RCU_ADC1 : gd32f10x_rcu.h
  • RCU_ADC1RST : gd32f10x_rcu.h
  • RCU_AF : gd32f10x_rcu.h
  • RCU_AFRST : gd32f10x_rcu.h
  • RCU_BKPI : gd32f10x_rcu.h
  • RCU_BKPIRST : gd32f10x_rcu.h
  • RCU_CAN0 : gd32f10x_rcu.h
  • RCU_CAN0RST : gd32f10x_rcu.h
  • RCU_CAN1 : gd32f10x_rcu.h
  • RCU_CAN1RST : gd32f10x_rcu.h
  • RCU_CRC : gd32f10x_rcu.h
  • RCU_DAC : gd32f10x_rcu.h
  • RCU_DACRST : gd32f10x_rcu.h
  • RCU_DMA0 : gd32f10x_rcu.h
  • RCU_DMA1 : gd32f10x_rcu.h
  • RCU_ENETRST : gd32f10x_rcu.h
  • RCU_EXMC : gd32f10x_rcu.h
  • RCU_FLAG_EPRST : gd32f10x_rcu.h
  • RCU_FLAG_FWDGTRST : gd32f10x_rcu.h
  • RCU_FLAG_HXTALSTB : gd32f10x_rcu.h
  • RCU_FLAG_IRC40KSTB : gd32f10x_rcu.h
  • RCU_FLAG_IRC8MSTB : gd32f10x_rcu.h
  • RCU_FLAG_LPRST : gd32f10x_rcu.h
  • RCU_FLAG_LXTALSTB : gd32f10x_rcu.h
  • RCU_FLAG_PLL1STB : gd32f10x_rcu.h
  • RCU_FLAG_PLL2STB : gd32f10x_rcu.h
  • RCU_FLAG_PLLSTB : gd32f10x_rcu.h
  • RCU_FLAG_PORRST : gd32f10x_rcu.h
  • RCU_FLAG_SWRST : gd32f10x_rcu.h
  • RCU_FLAG_WWDGTRST : gd32f10x_rcu.h
  • RCU_FMC_SLP : gd32f10x_rcu.h
  • RCU_GPIOA : gd32f10x_rcu.h
  • RCU_GPIOARST : gd32f10x_rcu.h
  • RCU_GPIOB : gd32f10x_rcu.h
  • RCU_GPIOBRST : gd32f10x_rcu.h
  • RCU_GPIOC : gd32f10x_rcu.h
  • RCU_GPIOCRST : gd32f10x_rcu.h
  • RCU_GPIOD : gd32f10x_rcu.h
  • RCU_GPIODRST : gd32f10x_rcu.h
  • RCU_GPIOE : gd32f10x_rcu.h
  • RCU_GPIOERST : gd32f10x_rcu.h
  • RCU_GPIOF : gd32f10x_rcu.h
  • RCU_GPIOFRST : gd32f10x_rcu.h
  • RCU_GPIOG : gd32f10x_rcu.h
  • RCU_GPIOGRST : gd32f10x_rcu.h
  • RCU_HXTAL : gd32f10x_rcu.h
  • RCU_I2C0 : gd32f10x_rcu.h
  • RCU_I2C0RST : gd32f10x_rcu.h
  • RCU_I2C1 : gd32f10x_rcu.h
  • RCU_I2C1RST : gd32f10x_rcu.h
  • RCU_INT_FLAG_CKM : gd32f10x_rcu.h
  • RCU_INT_FLAG_CKM_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_HXTALSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_HXTALSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_IRC40KSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_IRC40KSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_IRC8MSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_IRC8MSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_LXTALSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_LXTALSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLL1STB : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLL1STB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLL2STB : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLL2STB_CLR : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLLSTB : gd32f10x_rcu.h
  • RCU_INT_FLAG_PLLSTB_CLR : gd32f10x_rcu.h
  • RCU_INT_HXTALSTB : gd32f10x_rcu.h
  • RCU_INT_IRC40KSTB : gd32f10x_rcu.h
  • RCU_INT_IRC8MSTB : gd32f10x_rcu.h
  • RCU_INT_LXTALSTB : gd32f10x_rcu.h
  • RCU_INT_PLL1STB : gd32f10x_rcu.h
  • RCU_INT_PLL2STB : gd32f10x_rcu.h
  • RCU_INT_PLLSTB : gd32f10x_rcu.h
  • RCU_IRC40K : gd32f10x_rcu.h
  • RCU_IRC8M : gd32f10x_rcu.h
  • RCU_LXTAL : gd32f10x_rcu.h
  • RCU_PLL1_CK : gd32f10x_rcu.h
  • RCU_PLL2_CK : gd32f10x_rcu.h
  • RCU_PLL_CK : gd32f10x_rcu.h
  • RCU_PMU : gd32f10x_rcu.h
  • RCU_PMURST : gd32f10x_rcu.h
  • RCU_RTC : gd32f10x_rcu.h
  • RCU_SDIO : gd32f10x_rcu.h
  • RCU_SPI0 : gd32f10x_rcu.h
  • RCU_SPI0RST : gd32f10x_rcu.h
  • RCU_SPI1 : gd32f10x_rcu.h
  • RCU_SPI1RST : gd32f10x_rcu.h
  • RCU_SPI2 : gd32f10x_rcu.h
  • RCU_SPI2RST : gd32f10x_rcu.h
  • RCU_SRAM_SLP : gd32f10x_rcu.h
  • RCU_TIMER0 : gd32f10x_rcu.h
  • RCU_TIMER0RST : gd32f10x_rcu.h
  • RCU_TIMER1 : gd32f10x_rcu.h
  • RCU_TIMER10 : gd32f10x_rcu.h
  • RCU_TIMER10RST : gd32f10x_rcu.h
  • RCU_TIMER11 : gd32f10x_rcu.h
  • RCU_TIMER11RST : gd32f10x_rcu.h
  • RCU_TIMER12 : gd32f10x_rcu.h
  • RCU_TIMER12RST : gd32f10x_rcu.h
  • RCU_TIMER13 : gd32f10x_rcu.h
  • RCU_TIMER13RST : gd32f10x_rcu.h
  • RCU_TIMER1RST : gd32f10x_rcu.h
  • RCU_TIMER2 : gd32f10x_rcu.h
  • RCU_TIMER2RST : gd32f10x_rcu.h
  • RCU_TIMER3 : gd32f10x_rcu.h
  • RCU_TIMER3RST : gd32f10x_rcu.h
  • RCU_TIMER4 : gd32f10x_rcu.h
  • RCU_TIMER4RST : gd32f10x_rcu.h
  • RCU_TIMER5 : gd32f10x_rcu.h
  • RCU_TIMER5RST : gd32f10x_rcu.h
  • RCU_TIMER6 : gd32f10x_rcu.h
  • RCU_TIMER6RST : gd32f10x_rcu.h
  • RCU_TIMER7 : gd32f10x_rcu.h
  • RCU_TIMER7RST : gd32f10x_rcu.h
  • RCU_TIMER8 : gd32f10x_rcu.h
  • RCU_TIMER8RST : gd32f10x_rcu.h
  • RCU_TIMER9 : gd32f10x_rcu.h
  • RCU_TIMER9RST : gd32f10x_rcu.h
  • RCU_UART3 : gd32f10x_rcu.h
  • RCU_UART3RST : gd32f10x_rcu.h
  • RCU_UART4 : gd32f10x_rcu.h
  • RCU_UART4RST : gd32f10x_rcu.h
  • RCU_USART0 : gd32f10x_rcu.h
  • RCU_USART0RST : gd32f10x_rcu.h
  • RCU_USART1 : gd32f10x_rcu.h
  • RCU_USART1RST : gd32f10x_rcu.h
  • RCU_USART2 : gd32f10x_rcu.h
  • RCU_USART2RST : gd32f10x_rcu.h
  • RCU_USBD : gd32f10x_rcu.h
  • RCU_USBDRST : gd32f10x_rcu.h
  • RCU_USBFSRST : gd32f10x_rcu.h
  • RCU_WWDGT : gd32f10x_rcu.h
  • RCU_WWDGTRST : gd32f10x_rcu.h
  • RXDESC_BUFFER_1_ADDR : gd32f10x_enet.h
  • RXDESC_BUFFER_1_SIZE : gd32f10x_enet.h
  • RXDESC_BUFFER_2_SIZE : gd32f10x_enet.h
  • RXDESC_FRAME_LENGTH : gd32f10x_enet.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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- s -

  • STORE_OPTION : gd32f10x_enet.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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- t -

  • TIMER_OPTION : gd32f10x_enet.h
  • TXDESC_BUFFER_1_ADDR : gd32f10x_enet.h
  • TXDESC_COLLISION_COUNT : gd32f10x_enet.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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- u -

  • URB_DONE : usb_core.h
  • URB_ERROR : usb_core.h
  • URB_IDLE : usb_core.h
  • URB_NOTREADY : usb_core.h
  • URB_PING : usb_core.h
  • URB_STALL : usb_core.h
  • USART_FLAG_CTSF : gd32f10x_usart.h
  • USART_FLAG_FERR : gd32f10x_usart.h
  • USART_FLAG_IDLEF : gd32f10x_usart.h
  • USART_FLAG_LBDF : gd32f10x_usart.h
  • USART_FLAG_NERR : gd32f10x_usart.h
  • USART_FLAG_ORERR : gd32f10x_usart.h
  • USART_FLAG_PERR : gd32f10x_usart.h
  • USART_FLAG_RBNE : gd32f10x_usart.h
  • USART_FLAG_TBE : gd32f10x_usart.h
  • USART_FLAG_TC : gd32f10x_usart.h
  • USART_INT_CTS : gd32f10x_usart.h
  • USART_INT_ERR : gd32f10x_usart.h
  • USART_INT_FLAG_CTS : gd32f10x_usart.h
  • USART_INT_FLAG_ERR_FERR : gd32f10x_usart.h
  • USART_INT_FLAG_ERR_NERR : gd32f10x_usart.h
  • USART_INT_FLAG_ERR_ORERR : gd32f10x_usart.h
  • USART_INT_FLAG_IDLE : gd32f10x_usart.h
  • USART_INT_FLAG_LBD : gd32f10x_usart.h
  • USART_INT_FLAG_PERR : gd32f10x_usart.h
  • USART_INT_FLAG_RBNE : gd32f10x_usart.h
  • USART_INT_FLAG_RBNE_ORERR : gd32f10x_usart.h
  • USART_INT_FLAG_TBE : gd32f10x_usart.h
  • USART_INT_FLAG_TC : gd32f10x_usart.h
  • USART_INT_IDLE : gd32f10x_usart.h
  • USART_INT_LBD : gd32f10x_usart.h
  • USART_INT_PERR : gd32f10x_usart.h
  • USART_INT_RBNE : gd32f10x_usart.h
  • USART_INT_TBE : gd32f10x_usart.h
  • USART_INT_TC : gd32f10x_usart.h
  • USB_CTRL_DATA_IN : usb_core.h
  • USB_CTRL_DATA_OUT : usb_core.h
  • USB_CTRL_IDLE : usb_core.h
  • USB_CTRL_SETUP : usb_core.h
  • USB_CTRL_STALL : usb_core.h
  • USB_CTRL_STATUS_IN : usb_core.h
  • USB_CTRL_STATUS_OUT : usb_core.h
  • USB_FAIL : usb_core.h
  • USB_FS_CORE_ID : usb_defines.h
  • USB_HS_CORE_ID : usb_defines.h
  • USB_OK : usb_core.h
  • USB_RX : usb_core.h
  • USB_SPEED_FULL : usb_defines.h
  • USB_SPEED_HIGH : usb_defines.h
  • USB_SPEED_LOW : usb_defines.h
  • USB_SPEED_UNKNOWN : usb_defines.h
  • USB_TX : usb_core.h
  • USBD_ADDRESSED : usbd_core.h
  • USBD_BUSY : usbd_core.h , usb_core.h
  • USBD_CONFIGURED : usbd_core.h
  • USBD_CONNECTED : usbd_core.h
  • USBD_DEFAULT : usbd_core.h
  • USBD_FAIL : usbd_core.h , usb_core.h
  • USBD_OK : usb_core.h , usbd_core.h
  • USBD_RX : usbd_core.h
  • USBD_SUSPENDED : usbd_core.h
  • USBD_TX : usbd_core.h
  • USBD_UNCONNECTED : usbd_core.h
  • USBH_APPLY_DEINIT : usbh_core.h
  • USBH_BUSY : usbh_core.h
  • USBH_FAIL : usbh_core.h
  • USBH_NOT_SUPPORTED : usbh_core.h
  • USBH_OK : usbh_core.h
  • USBH_SPEED_UNKNOWN_ERROR : usbh_core.h
  • USBH_UNRECOVERED_ERROR : usbh_core.h
  • USBH_USER_NO_RESP : usbh_core.h
  • USBH_USER_RESP_OK : usbh_core.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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- v -

  • VLAN_OPTION : gd32f10x_enet.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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- _ -

  • _ENET_DELAY_ : gd32f10x_enet.h
  • _EP_ADDR_SET : usbd_regs.h
  • _WIDE_STRING : usbd_std.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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  • w

- a -

  • ADC0 : gd32f10x_adc.h
  • ADC0_1_2_EXTTRIG_INSERTED_NONE : gd32f10x_adc.h
  • ADC0_1_2_EXTTRIG_REGULAR_NONE : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_EXTI_15 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T0_CH3 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T0_TRGO : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T1_CH0 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T1_TRGO : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T2_CH3 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T3_TRGO : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_INSERTED_T7_CH3 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_EXTI_11 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T0_CH0 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T0_CH1 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T0_CH2 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T1_CH1 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T2_TRGO : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T3_CH3 : gd32f10x_adc.h
  • ADC0_1_EXTTRIG_REGULAR_T7_TRGO : gd32f10x_adc.h
  • ADC1 : gd32f10x_adc.h
  • ADC2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T0_CH3 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T0_TRGO : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T3_CH2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T4_CH3 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T4_TRGO : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T7_CH1 : gd32f10x_adc.h
  • ADC2_EXTTRIG_INSERTED_T7_CH3 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T0_CH2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T1_CH2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T2_CH0 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T4_CH0 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T4_CH2 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T7_CH0 : gd32f10x_adc.h
  • ADC2_EXTTRIG_REGULAR_T7_TRGO : gd32f10x_adc.h
  • ADC_CHANNEL_0 : gd32f10x_adc.h
  • ADC_CHANNEL_1 : gd32f10x_adc.h
  • ADC_CHANNEL_10 : gd32f10x_adc.h
  • ADC_CHANNEL_11 : gd32f10x_adc.h
  • ADC_CHANNEL_12 : gd32f10x_adc.h
  • ADC_CHANNEL_13 : gd32f10x_adc.h
  • ADC_CHANNEL_14 : gd32f10x_adc.h
  • ADC_CHANNEL_15 : gd32f10x_adc.h
  • ADC_CHANNEL_16 : gd32f10x_adc.h
  • ADC_CHANNEL_17 : gd32f10x_adc.h
  • ADC_CHANNEL_2 : gd32f10x_adc.h
  • ADC_CHANNEL_3 : gd32f10x_adc.h
  • ADC_CHANNEL_4 : gd32f10x_adc.h
  • ADC_CHANNEL_5 : gd32f10x_adc.h
  • ADC_CHANNEL_6 : gd32f10x_adc.h
  • ADC_CHANNEL_7 : gd32f10x_adc.h
  • ADC_CHANNEL_8 : gd32f10x_adc.h
  • ADC_CHANNEL_9 : gd32f10x_adc.h
  • ADC_CHANNEL_DISCON_DISABLE : gd32f10x_adc.h
  • ADC_CONTINUOUS_MODE : gd32f10x_adc.h
  • ADC_CTL0 : gd32f10x_adc.h
  • ADC_CTL0_DISIC : gd32f10x_adc.h
  • ADC_CTL0_DISNUM : gd32f10x_adc.h
  • ADC_CTL0_DISRC : gd32f10x_adc.h
  • ADC_CTL0_DRES : gd32f10x_adc.h
  • ADC_CTL0_EOCIE : gd32f10x_adc.h
  • ADC_CTL0_EOICIE : gd32f10x_adc.h
  • ADC_CTL0_ICA : gd32f10x_adc.h
  • ADC_CTL0_IWDEN : gd32f10x_adc.h
  • ADC_CTL0_RWDEN : gd32f10x_adc.h
  • ADC_CTL0_SM : gd32f10x_adc.h
  • ADC_CTL0_SYNCM : gd32f10x_adc.h
  • ADC_CTL0_WDCHSEL : gd32f10x_adc.h
  • ADC_CTL0_WDEIE : gd32f10x_adc.h
  • ADC_CTL0_WDSC : gd32f10x_adc.h
  • ADC_CTL1 : gd32f10x_adc.h
  • ADC_CTL1_ADCON : gd32f10x_adc.h
  • ADC_CTL1_CLB : gd32f10x_adc.h
  • ADC_CTL1_CTN : gd32f10x_adc.h
  • ADC_CTL1_DAL : gd32f10x_adc.h
  • ADC_CTL1_DMA : gd32f10x_adc.h
  • ADC_CTL1_ETEIC : gd32f10x_adc.h
  • ADC_CTL1_ETERC : gd32f10x_adc.h
  • ADC_CTL1_ETSIC : gd32f10x_adc.h
  • ADC_CTL1_ETSRC : gd32f10x_adc.h
  • ADC_CTL1_RSTCLB : gd32f10x_adc.h
  • ADC_CTL1_SWICST : gd32f10x_adc.h
  • ADC_CTL1_SWRCST : gd32f10x_adc.h
  • ADC_CTL1_TSVREN : gd32f10x_adc.h
  • ADC_DATAALIGN_LEFT : gd32f10x_adc.h
  • ADC_DATAALIGN_RIGHT : gd32f10x_adc.h
  • ADC_DAUL_INSERTED_PARALLEL : gd32f10x_adc.h
  • ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST : gd32f10x_adc.h
  • ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW : gd32f10x_adc.h
  • ADC_DAUL_INSERTED_TRRIGGER_ROTATION : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_FOLLOWUP_FAST : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_FOLLOWUP_SLOW : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_PARALLEL : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL : gd32f10x_adc.h
  • ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION : gd32f10x_adc.h
  • ADC_FLAG_EOC : gd32f10x_adc.h
  • ADC_FLAG_EOIC : gd32f10x_adc.h
  • ADC_FLAG_STIC : gd32f10x_adc.h
  • ADC_FLAG_STRC : gd32f10x_adc.h
  • ADC_FLAG_WDE : gd32f10x_adc.h
  • ADC_IDATA0 : gd32f10x_adc.h
  • ADC_IDATA1 : gd32f10x_adc.h
  • ADC_IDATA2 : gd32f10x_adc.h
  • ADC_IDATA3 : gd32f10x_adc.h
  • ADC_IDATAX_IDATAN : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_0 : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_1 : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_2 : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_3 : gd32f10x_adc.h
  • ADC_INSERTED_CHANNEL_AUTO : gd32f10x_adc.h
  • ADC_INT_EOC : gd32f10x_adc.h
  • ADC_INT_EOIC : gd32f10x_adc.h
  • ADC_INT_WDE : gd32f10x_adc.h
  • ADC_IOFF0 : gd32f10x_adc.h
  • ADC_IOFF1 : gd32f10x_adc.h
  • ADC_IOFF2 : gd32f10x_adc.h
  • ADC_IOFF3 : gd32f10x_adc.h
  • ADC_IOFFX_IOFF : gd32f10x_adc.h
  • ADC_ISQ : gd32f10x_adc.h
  • ADC_ISQ_IL : gd32f10x_adc.h
  • ADC_ISQ_ISQN : gd32f10x_adc.h
  • ADC_MODE_FREE : gd32f10x_adc.h
  • ADC_RDATA : gd32f10x_adc.h
  • ADC_RDATA_ADC1RDTR : gd32f10x_adc.h
  • ADC_RDATA_RDATA : gd32f10x_adc.h
  • ADC_REGULAR_CHANNEL : gd32f10x_adc.h
  • ADC_REGULAR_INSERTED_CHANNEL : gd32f10x_adc.h
  • ADC_RSQ0 : gd32f10x_adc.h
  • ADC_RSQ0_RL : gd32f10x_adc.h
  • ADC_RSQ1 : gd32f10x_adc.h
  • ADC_RSQ2 : gd32f10x_adc.h
  • ADC_RSQX_RSQN : gd32f10x_adc.h
  • ADC_SAMPLETIME_13POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_1POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_239POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_28POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_41POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_55POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_71POINT5 : gd32f10x_adc.h
  • ADC_SAMPLETIME_7POINT5 : gd32f10x_adc.h
  • ADC_SAMPT0 : gd32f10x_adc.h
  • ADC_SAMPT1 : gd32f10x_adc.h
  • ADC_SAMPTX_SPTN : gd32f10x_adc.h
  • ADC_SCAN_MODE : gd32f10x_adc.h
  • ADC_STAT : gd32f10x_adc.h
  • ADC_STAT_EOC : gd32f10x_adc.h
  • ADC_STAT_EOIC : gd32f10x_adc.h
  • ADC_STAT_STIC : gd32f10x_adc.h
  • ADC_STAT_STRC : gd32f10x_adc.h
  • ADC_STAT_WDE : gd32f10x_adc.h
  • ADC_WDHT : gd32f10x_adc.h
  • ADC_WDHT_WDHT : gd32f10x_adc.h
  • ADC_WDLT : gd32f10x_adc.h
  • ADC_WDLT_WDLT : gd32f10x_adc.h
  • AFIO : gd32f10x_gpio.h
  • AFIO_EC : gd32f10x_gpio.h
  • AFIO_EC_EOE : gd32f10x_gpio.h
  • AFIO_EC_PIN : gd32f10x_gpio.h
  • AFIO_EC_PORT : gd32f10x_gpio.h
  • AFIO_EXTI0_SS : gd32f10x_gpio.h
  • AFIO_EXTI10_SS : gd32f10x_gpio.h
  • AFIO_EXTI11_SS : gd32f10x_gpio.h
  • AFIO_EXTI12_SS : gd32f10x_gpio.h
  • AFIO_EXTI13_SS : gd32f10x_gpio.h
  • AFIO_EXTI14_SS : gd32f10x_gpio.h
  • AFIO_EXTI15_SS : gd32f10x_gpio.h
  • AFIO_EXTI1_SS : gd32f10x_gpio.h
  • AFIO_EXTI2_SS : gd32f10x_gpio.h
  • AFIO_EXTI3_SS : gd32f10x_gpio.h
  • AFIO_EXTI4_SS : gd32f10x_gpio.h
  • AFIO_EXTI5_SS : gd32f10x_gpio.h
  • AFIO_EXTI6_SS : gd32f10x_gpio.h
  • AFIO_EXTI7_SS : gd32f10x_gpio.h
  • AFIO_EXTI8_SS : gd32f10x_gpio.h
  • AFIO_EXTI9_SS : gd32f10x_gpio.h
  • AFIO_EXTI_SOURCE_FIELDS : gd32f10x_gpio.c
  • AFIO_EXTISS0 : gd32f10x_gpio.h
  • AFIO_EXTISS1 : gd32f10x_gpio.h
  • AFIO_EXTISS2 : gd32f10x_gpio.h
  • AFIO_EXTISS3 : gd32f10x_gpio.h
  • AFIO_PCF0 : gd32f10x_gpio.h
  • AFIO_PCF0_CAN0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_CAN1_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_ENET_PHY_SEL : gd32f10x_gpio.h
  • AFIO_PCF0_ENET_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_I2C0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_PD01_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_PTP_PPS_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_SPI0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_SPI2_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_SWJ_CFG : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER1_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER1ITR0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER2_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER3_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_TIMER4CH3_IREMAP : gd32f10x_gpio.h
  • AFIO_PCF0_USART0_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_USART1_REMAP : gd32f10x_gpio.h
  • AFIO_PCF0_USART2_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1 : gd32f10x_gpio.h
  • AFIO_PCF1_FIELDS : gd32f10x_gpio.c
  • AFIO_PCF1_FSMC_NADV : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER10_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER12_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER13_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER8_REMAP : gd32f10x_gpio.h
  • AFIO_PCF1_TIMER9_REMAP : gd32f10x_gpio.h
  • AHBEN_REG_OFFSET : gd32f10x_rcu.h
  • AHBRST_REG_OFFSET : gd32f10x_rcu.h
  • APB1EN_REG_OFFSET : gd32f10x_rcu.h
  • APB1RST_REG_OFFSET : gd32f10x_rcu.h
  • APB2EN_REG_OFFSET : gd32f10x_rcu.h
  • APB2RST_REG_OFFSET : gd32f10x_rcu.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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- b -

  • BANK0_SNCTL0_REGION_RESET : gd32f10x_exmc.c
  • BANK0_SNCTL1_2_3_REGION_RESET : gd32f10x_exmc.c
  • BANK0_SNTCFG_RESET : gd32f10x_exmc.c
  • BANK0_SNWTCFG_RESET : gd32f10x_exmc.c
  • BANK1_2_NPATCFG_RESET : gd32f10x_exmc.c
  • BANK1_2_NPCTCFG_RESET : gd32f10x_exmc.c
  • BANK1_2_NPCTL_RESET : gd32f10x_exmc.c
  • BANK1_2_NPINTEN_RESET : gd32f10x_exmc.c
  • BANK3_NPATCFG_RESET : gd32f10x_exmc.c
  • BANK3_NPCTCFG_RESET : gd32f10x_exmc.c
  • BANK3_NPCTL_RESET : gd32f10x_exmc.c
  • BANK3_NPINTEN_RESET : gd32f10x_exmc.c
  • BANK3_PIOTCFG3_RESET : gd32f10x_exmc.c
  • BDCTL_REG_OFFSET : gd32f10x_rcu.h
  • BDCTL_RTCSRC : gd32f10x_rcu.h
  • BKP : gd32f10x_bkp.h
  • BKP_DATA : gd32f10x_bkp.h
  • BKP_DATA0 : gd32f10x_bkp.h
  • BKP_DATA0_9 : gd32f10x_bkp.h
  • BKP_DATA1 : gd32f10x_bkp.h
  • BKP_DATA10 : gd32f10x_bkp.h
  • BKP_DATA10_41 : gd32f10x_bkp.h
  • BKP_DATA11 : gd32f10x_bkp.h
  • BKP_DATA12 : gd32f10x_bkp.h
  • BKP_DATA13 : gd32f10x_bkp.h
  • BKP_DATA14 : gd32f10x_bkp.h
  • BKP_DATA15 : gd32f10x_bkp.h
  • BKP_DATA16 : gd32f10x_bkp.h
  • BKP_DATA17 : gd32f10x_bkp.h
  • BKP_DATA18 : gd32f10x_bkp.h
  • BKP_DATA19 : gd32f10x_bkp.h
  • BKP_DATA2 : gd32f10x_bkp.h
  • BKP_DATA20 : gd32f10x_bkp.h
  • BKP_DATA21 : gd32f10x_bkp.h
  • BKP_DATA22 : gd32f10x_bkp.h
  • BKP_DATA23 : gd32f10x_bkp.h
  • BKP_DATA24 : gd32f10x_bkp.h
  • BKP_DATA25 : gd32f10x_bkp.h
  • BKP_DATA26 : gd32f10x_bkp.h
  • BKP_DATA27 : gd32f10x_bkp.h
  • BKP_DATA28 : gd32f10x_bkp.h
  • BKP_DATA29 : gd32f10x_bkp.h
  • BKP_DATA3 : gd32f10x_bkp.h
  • BKP_DATA30 : gd32f10x_bkp.h
  • BKP_DATA31 : gd32f10x_bkp.h
  • BKP_DATA32 : gd32f10x_bkp.h
  • BKP_DATA33 : gd32f10x_bkp.h
  • BKP_DATA34 : gd32f10x_bkp.h
  • BKP_DATA35 : gd32f10x_bkp.h
  • BKP_DATA36 : gd32f10x_bkp.h
  • BKP_DATA37 : gd32f10x_bkp.h
  • BKP_DATA38 : gd32f10x_bkp.h
  • BKP_DATA39 : gd32f10x_bkp.h
  • BKP_DATA4 : gd32f10x_bkp.h
  • BKP_DATA40 : gd32f10x_bkp.h
  • BKP_DATA41 : gd32f10x_bkp.h
  • BKP_DATA5 : gd32f10x_bkp.h
  • BKP_DATA6 : gd32f10x_bkp.h
  • BKP_DATA7 : gd32f10x_bkp.h
  • BKP_DATA8 : gd32f10x_bkp.h
  • BKP_DATA9 : gd32f10x_bkp.h
  • BKP_DATA_GET : gd32f10x_bkp.h
  • BKP_FLAG_TAMPER : gd32f10x_bkp.h
  • BKP_INT_FLAG_TAMPER : gd32f10x_bkp.h
  • BKP_OCTL : gd32f10x_bkp.h
  • BKP_OCTL_ASOEN : gd32f10x_bkp.h
  • BKP_OCTL_COEN : gd32f10x_bkp.h
  • BKP_OCTL_RCCV : gd32f10x_bkp.h
  • BKP_OCTL_ROSEL : gd32f10x_bkp.h
  • BKP_TPCS : gd32f10x_bkp.h
  • BKP_TPCS_TEF : gd32f10x_bkp.h
  • BKP_TPCS_TER : gd32f10x_bkp.h
  • BKP_TPCS_TIF : gd32f10x_bkp.h
  • BKP_TPCS_TIR : gd32f10x_bkp.h
  • BKP_TPCS_TPIE : gd32f10x_bkp.h
  • BKP_TPCTL : gd32f10x_bkp.h
  • BKP_TPCTL_TPAL : gd32f10x_bkp.h
  • BKP_TPCTL_TPEN : gd32f10x_bkp.h
  • BLKNUM_OFFSET : usbd_regs.h
  • BLKSIZE2_MASK : usbd_regs.h
  • BLKSIZE2_OFFSETMASK : usbd_regs.h
  • BLKSIZE32_MASK : usbd_regs.h
  • BLKSIZE32_OFFSETMASK : usbd_regs.h
  • BLKSIZE_OFFSET : usbd_regs.h
  • BT_BAUDPSC : gd32f10x_can.h
  • BT_BS1 : gd32f10x_can.h
  • BT_BS2 : gd32f10x_can.h
  • BT_MODE : gd32f10x_can.h
  • BT_SJW : gd32f10x_can.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • u
  • w

- c -

  • CAN0 : gd32f10x_can.h
  • CAN1 : gd32f10x_can.h
  • CAN_BIT_POS : gd32f10x_can.h
  • CAN_BIT_POS0 : gd32f10x_can.h
  • CAN_BIT_POS1 : gd32f10x_can.h
  • CAN_BT : gd32f10x_can.h
  • CAN_BT_BAUDPSC : gd32f10x_can.h
  • CAN_BT_BS1 : gd32f10x_can.h
  • CAN_BT_BS1_10TQ : gd32f10x_can.h
  • CAN_BT_BS1_11TQ : gd32f10x_can.h
  • CAN_BT_BS1_12TQ : gd32f10x_can.h
  • CAN_BT_BS1_13TQ : gd32f10x_can.h
  • CAN_BT_BS1_14TQ : gd32f10x_can.h
  • CAN_BT_BS1_15TQ : gd32f10x_can.h
  • CAN_BT_BS1_16TQ : gd32f10x_can.h
  • CAN_BT_BS1_1TQ : gd32f10x_can.h
  • CAN_BT_BS1_2TQ : gd32f10x_can.h
  • CAN_BT_BS1_3TQ : gd32f10x_can.h
  • CAN_BT_BS1_4TQ : gd32f10x_can.h
  • CAN_BT_BS1_5TQ : gd32f10x_can.h
  • CAN_BT_BS1_6TQ : gd32f10x_can.h
  • CAN_BT_BS1_7TQ : gd32f10x_can.h
  • CAN_BT_BS1_8TQ : gd32f10x_can.h
  • CAN_BT_BS1_9TQ : gd32f10x_can.h
  • CAN_BT_BS2 : gd32f10x_can.h
  • CAN_BT_BS2_1TQ : gd32f10x_can.h
  • CAN_BT_BS2_2TQ : gd32f10x_can.h
  • CAN_BT_BS2_3TQ : gd32f10x_can.h
  • CAN_BT_BS2_4TQ : gd32f10x_can.h
  • CAN_BT_BS2_5TQ : gd32f10x_can.h
  • CAN_BT_BS2_6TQ : gd32f10x_can.h
  • CAN_BT_BS2_7TQ : gd32f10x_can.h
  • CAN_BT_BS2_8TQ : gd32f10x_can.h
  • CAN_BT_LCMOD : gd32f10x_can.h
  • CAN_BT_SCMOD : gd32f10x_can.h
  • CAN_BT_SJW : gd32f10x_can.h
  • CAN_BT_SJW_1TQ : gd32f10x_can.h
  • CAN_BT_SJW_2TQ : gd32f10x_can.h
  • CAN_BT_SJW_3TQ : gd32f10x_can.h
  • CAN_BT_SJW_4TQ : gd32f10x_can.h
  • CAN_CTL : gd32f10x_can.h
  • CAN_CTL_ABOR : gd32f10x_can.h
  • CAN_CTL_ARD : gd32f10x_can.h
  • CAN_CTL_AWU : gd32f10x_can.h
  • CAN_CTL_DFZ : gd32f10x_can.h
  • CAN_CTL_IWMOD : gd32f10x_can.h
  • CAN_CTL_RFOD : gd32f10x_can.h
  • CAN_CTL_SLPWMOD : gd32f10x_can.h
  • CAN_CTL_SWRST : gd32f10x_can.h
  • CAN_CTL_TFO : gd32f10x_can.h
  • CAN_CTL_TTC : gd32f10x_can.h
  • CAN_EFID_MASK : gd32f10x_can.h
  • CAN_ERR : gd32f10x_can.h
  • CAN_ERR_BOERR : gd32f10x_can.h
  • CAN_ERR_ERRN : gd32f10x_can.h
  • CAN_ERR_PERR : gd32f10x_can.h
  • CAN_ERR_RECNT : gd32f10x_can.h
  • CAN_ERR_TECNT : gd32f10x_can.h
  • CAN_ERR_WERR : gd32f10x_can.h
  • CAN_ERRN_0 : gd32f10x_can.h
  • CAN_ERRN_1 : gd32f10x_can.h
  • CAN_ERRN_2 : gd32f10x_can.h
  • CAN_ERRN_3 : gd32f10x_can.h
  • CAN_ERRN_4 : gd32f10x_can.h
  • CAN_ERRN_5 : gd32f10x_can.h
  • CAN_ERRN_6 : gd32f10x_can.h
  • CAN_ERRN_7 : gd32f10x_can.h
  • CAN_F0DATA0 : gd32f10x_can.h
  • CAN_F0DATA1 : gd32f10x_can.h
  • CAN_F10DATA0 : gd32f10x_can.h
  • CAN_F10DATA1 : gd32f10x_can.h
  • CAN_F11DATA0 : gd32f10x_can.h
  • CAN_F11DATA1 : gd32f10x_can.h
  • CAN_F12DATA0 : gd32f10x_can.h
  • CAN_F12DATA1 : gd32f10x_can.h
  • CAN_F13DATA0 : gd32f10x_can.h
  • CAN_F13DATA1 : gd32f10x_can.h
  • CAN_F14DATA0 : gd32f10x_can.h
  • CAN_F14DATA1 : gd32f10x_can.h
  • CAN_F15DATA0 : gd32f10x_can.h
  • CAN_F15DATA1 : gd32f10x_can.h
  • CAN_F16DATA0 : gd32f10x_can.h
  • CAN_F16DATA1 : gd32f10x_can.h
  • CAN_F17DATA0 : gd32f10x_can.h
  • CAN_F17DATA1 : gd32f10x_can.h
  • CAN_F18DATA0 : gd32f10x_can.h
  • CAN_F18DATA1 : gd32f10x_can.h
  • CAN_F19DATA0 : gd32f10x_can.h
  • CAN_F19DATA1 : gd32f10x_can.h
  • CAN_F1DATA0 : gd32f10x_can.h
  • CAN_F1DATA1 : gd32f10x_can.h
  • CAN_F20DATA0 : gd32f10x_can.h
  • CAN_F20DATA1 : gd32f10x_can.h
  • CAN_F21DATA0 : gd32f10x_can.h
  • CAN_F21DATA1 : gd32f10x_can.h
  • CAN_F22DATA0 : gd32f10x_can.h
  • CAN_F22DATA1 : gd32f10x_can.h
  • CAN_F23DATA0 : gd32f10x_can.h
  • CAN_F23DATA1 : gd32f10x_can.h
  • CAN_F24DATA0 : gd32f10x_can.h
  • CAN_F24DATA1 : gd32f10x_can.h
  • CAN_F25DATA0 : gd32f10x_can.h
  • CAN_F25DATA1 : gd32f10x_can.h
  • CAN_F26DATA0 : gd32f10x_can.h
  • CAN_F26DATA1 : gd32f10x_can.h
  • CAN_F27DATA0 : gd32f10x_can.h
  • CAN_F27DATA1 : gd32f10x_can.h
  • CAN_F2DATA0 : gd32f10x_can.h
  • CAN_F2DATA1 : gd32f10x_can.h
  • CAN_F3DATA0 : gd32f10x_can.h
  • CAN_F3DATA1 : gd32f10x_can.h
  • CAN_F4DATA0 : gd32f10x_can.h
  • CAN_F4DATA1 : gd32f10x_can.h
  • CAN_F5DATA0 : gd32f10x_can.h
  • CAN_F5DATA1 : gd32f10x_can.h
  • CAN_F6DATA0 : gd32f10x_can.h
  • CAN_F6DATA1 : gd32f10x_can.h
  • CAN_F7DATA0 : gd32f10x_can.h
  • CAN_F7DATA1 : gd32f10x_can.h
  • CAN_F8DATA0 : gd32f10x_can.h
  • CAN_F8DATA1 : gd32f10x_can.h
  • CAN_F9DATA0 : gd32f10x_can.h
  • CAN_F9DATA1 : gd32f10x_can.h
  • CAN_FAFIFO : gd32f10x_can.h
  • CAN_FAFIFOR_FAF : gd32f10x_can.h
  • CAN_FCTL : gd32f10x_can.h
  • CAN_FCTL_FLD : gd32f10x_can.h
  • CAN_FCTL_HBC1F : gd32f10x_can.h
  • CAN_FDATA0 : gd32f10x_can.h
  • CAN_FDATA1 : gd32f10x_can.h
  • CAN_FDATA_FD : gd32f10x_can.h
  • CAN_FF_EXTENDED : gd32f10x_can.h
  • CAN_FF_STANDARD : gd32f10x_can.h
  • CAN_FIFO0 : gd32f10x_can.h
  • CAN_FIFO1 : gd32f10x_can.h
  • CAN_FILTER_MASK_16BITS : gd32f10x_can.h
  • CAN_FILTERBITS_16BIT : gd32f10x_can.h
  • CAN_FILTERBITS_32BIT : gd32f10x_can.h
  • CAN_FILTERMODE_LIST : gd32f10x_can.h
  • CAN_FILTERMODE_MASK : gd32f10x_can.h
  • CAN_FMCFG : gd32f10x_can.h
  • CAN_FMCFG_FMOD : gd32f10x_can.h
  • CAN_FSCFG : gd32f10x_can.h
  • CAN_FSCFG_FS : gd32f10x_can.h
  • CAN_FT_DATA : gd32f10x_can.h
  • CAN_FT_REMOTE : gd32f10x_can.h
  • CAN_FW : gd32f10x_can.h
  • CAN_FW_FW : gd32f10x_can.h
  • CAN_INT_BO : gd32f10x_can.h
  • CAN_INT_ERR : gd32f10x_can.h
  • CAN_INT_ERRN : gd32f10x_can.h
  • CAN_INT_PERR : gd32f10x_can.h
  • CAN_INT_RFF0 : gd32f10x_can.h
  • CAN_INT_RFF1 : gd32f10x_can.h
  • CAN_INT_RFNE0 : gd32f10x_can.h
  • CAN_INT_RFNE1 : gd32f10x_can.h
  • CAN_INT_RFO0 : gd32f10x_can.h
  • CAN_INT_RFO1 : gd32f10x_can.h
  • CAN_INT_SLPW : gd32f10x_can.h
  • CAN_INT_TME : gd32f10x_can.h
  • CAN_INT_WAKEUP : gd32f10x_can.h
  • CAN_INT_WERR : gd32f10x_can.h
  • CAN_INTEN : gd32f10x_can.h
  • CAN_INTEN_BOIE : gd32f10x_can.h
  • CAN_INTEN_ERRIE : gd32f10x_can.h
  • CAN_INTEN_ERRNIE : gd32f10x_can.h
  • CAN_INTEN_PERRIE : gd32f10x_can.h
  • CAN_INTEN_RFFIE0 : gd32f10x_can.h
  • CAN_INTEN_RFFIE1 : gd32f10x_can.h
  • CAN_INTEN_RFNEIE0 : gd32f10x_can.h
  • CAN_INTEN_RFNEIE1 : gd32f10x_can.h
  • CAN_INTEN_RFOIE0 : gd32f10x_can.h
  • CAN_INTEN_RFOIE1 : gd32f10x_can.h
  • CAN_INTEN_SLPWIE : gd32f10x_can.h
  • CAN_INTEN_TMEIE : gd32f10x_can.h
  • CAN_INTEN_WERRIE : gd32f10x_can.h
  • CAN_INTEN_WIE : gd32f10x_can.h
  • CAN_LOOPBACK_MODE : gd32f10x_can.h
  • CAN_MAILBOX0 : gd32f10x_can.h
  • CAN_MAILBOX1 : gd32f10x_can.h
  • CAN_MAILBOX2 : gd32f10x_can.h
  • CAN_MODE_INITIALIZE : gd32f10x_can.h
  • CAN_MODE_NORMAL : gd32f10x_can.h
  • CAN_MODE_SLEEP : gd32f10x_can.h
  • CAN_NOMAILBOX : gd32f10x_can.h
  • CAN_NORMAL_MODE : gd32f10x_can.h
  • CAN_REG_VAL : gd32f10x_can.h
  • CAN_REG_VALS : gd32f10x_can.h
  • CAN_REGIDX_BIT : gd32f10x_can.h
  • CAN_REGIDX_BITS : gd32f10x_can.h
  • CAN_RFIF_RFL_MASK : gd32f10x_can.h
  • CAN_RFIFO0 : gd32f10x_can.h
  • CAN_RFIFO0_RFD0 : gd32f10x_can.h
  • CAN_RFIFO0_RFF0 : gd32f10x_can.h
  • CAN_RFIFO0_RFL0 : gd32f10x_can.h
  • CAN_RFIFO0_RFO0 : gd32f10x_can.h
  • CAN_RFIFO1 : gd32f10x_can.h
  • CAN_RFIFO1_RFD1 : gd32f10x_can.h
  • CAN_RFIFO1_RFF1 : gd32f10x_can.h
  • CAN_RFIFO1_RFL1 : gd32f10x_can.h
  • CAN_RFIFO1_RFO1 : gd32f10x_can.h
  • CAN_RFIFOMDATA0 : gd32f10x_can.h
  • CAN_RFIFOMDATA00 : gd32f10x_can.h
  • CAN_RFIFOMDATA01 : gd32f10x_can.h
  • CAN_RFIFOMDATA0_DB0 : gd32f10x_can.h
  • CAN_RFIFOMDATA0_DB1 : gd32f10x_can.h
  • CAN_RFIFOMDATA0_DB2 : gd32f10x_can.h
  • CAN_RFIFOMDATA0_DB3 : gd32f10x_can.h
  • CAN_RFIFOMDATA1 : gd32f10x_can.h
  • CAN_RFIFOMDATA10 : gd32f10x_can.h
  • CAN_RFIFOMDATA11 : gd32f10x_can.h
  • CAN_RFIFOMDATA1_DB4 : gd32f10x_can.h
  • CAN_RFIFOMDATA1_DB5 : gd32f10x_can.h
  • CAN_RFIFOMDATA1_DB6 : gd32f10x_can.h
  • CAN_RFIFOMDATA1_DB7 : gd32f10x_can.h
  • CAN_RFIFOMI : gd32f10x_can.h
  • CAN_RFIFOMI0 : gd32f10x_can.h
  • CAN_RFIFOMI1 : gd32f10x_can.h
  • CAN_RFIFOMI_EFID : gd32f10x_can.h
  • CAN_RFIFOMI_FF : gd32f10x_can.h
  • CAN_RFIFOMI_FT : gd32f10x_can.h
  • CAN_RFIFOMI_SFID : gd32f10x_can.h
  • CAN_RFIFOMP : gd32f10x_can.h
  • CAN_RFIFOMP0 : gd32f10x_can.h
  • CAN_RFIFOMP1 : gd32f10x_can.h
  • CAN_RFIFOMP_DLENC : gd32f10x_can.h
  • CAN_RFIFOMP_FI : gd32f10x_can.h
  • CAN_RFIFOMP_TS : gd32f10x_can.h
  • CAN_SFID_MASK : gd32f10x_can.h
  • CAN_SILENT_LOOPBACK_MODE : gd32f10x_can.h
  • CAN_SILENT_MODE : gd32f10x_can.h
  • CAN_STAT : gd32f10x_can.h
  • CAN_STAT_ERRIF : gd32f10x_can.h
  • CAN_STAT_IWS : gd32f10x_can.h
  • CAN_STAT_LASTRX : gd32f10x_can.h
  • CAN_STAT_RS : gd32f10x_can.h
  • CAN_STAT_RXL : gd32f10x_can.h
  • CAN_STAT_SLPIF : gd32f10x_can.h
  • CAN_STAT_SLPWS : gd32f10x_can.h
  • CAN_STAT_TS : gd32f10x_can.h
  • CAN_STAT_WUIF : gd32f10x_can.h
  • CAN_STATE_PENDING : gd32f10x_can.h
  • CAN_TIMEOUT : gd32f10x_can.h
  • CAN_TMDATA0 : gd32f10x_can.h
  • CAN_TMDATA00 : gd32f10x_can.h
  • CAN_TMDATA01 : gd32f10x_can.h
  • CAN_TMDATA02 : gd32f10x_can.h
  • CAN_TMDATA0_DB0 : gd32f10x_can.h
  • CAN_TMDATA0_DB1 : gd32f10x_can.h
  • CAN_TMDATA0_DB2 : gd32f10x_can.h
  • CAN_TMDATA0_DB3 : gd32f10x_can.h
  • CAN_TMDATA1 : gd32f10x_can.h
  • CAN_TMDATA10 : gd32f10x_can.h
  • CAN_TMDATA11 : gd32f10x_can.h
  • CAN_TMDATA12 : gd32f10x_can.h
  • CAN_TMDATA1_DB4 : gd32f10x_can.h
  • CAN_TMDATA1_DB5 : gd32f10x_can.h
  • CAN_TMDATA1_DB6 : gd32f10x_can.h
  • CAN_TMDATA1_DB7 : gd32f10x_can.h
  • CAN_TMI : gd32f10x_can.h
  • CAN_TMI0 : gd32f10x_can.h
  • CAN_TMI1 : gd32f10x_can.h
  • CAN_TMI2 : gd32f10x_can.h
  • CAN_TMI_EFID : gd32f10x_can.h
  • CAN_TMI_FF : gd32f10x_can.h
  • CAN_TMI_FT : gd32f10x_can.h
  • CAN_TMI_SFID : gd32f10x_can.h
  • CAN_TMI_TEN : gd32f10x_can.h
  • CAN_TMP : gd32f10x_can.h
  • CAN_TMP0 : gd32f10x_can.h
  • CAN_TMP1 : gd32f10x_can.h
  • CAN_TMP2 : gd32f10x_can.h
  • CAN_TMP_DLENC : gd32f10x_can.h
  • CAN_TMP_TS : gd32f10x_can.h
  • CAN_TMP_TSEN : gd32f10x_can.h
  • CAN_TSTAT : gd32f10x_can.h
  • CAN_TSTAT_MAL0 : gd32f10x_can.h
  • CAN_TSTAT_MAL1 : gd32f10x_can.h
  • CAN_TSTAT_MAL2 : gd32f10x_can.h
  • CAN_TSTAT_MST0 : gd32f10x_can.h
  • CAN_TSTAT_MST1 : gd32f10x_can.h
  • CAN_TSTAT_MST2 : gd32f10x_can.h
  • CAN_TSTAT_MTE0 : gd32f10x_can.h
  • CAN_TSTAT_MTE1 : gd32f10x_can.h
  • CAN_TSTAT_MTE2 : gd32f10x_can.h
  • CAN_TSTAT_MTF0 : gd32f10x_can.h
  • CAN_TSTAT_MTF1 : gd32f10x_can.h
  • CAN_TSTAT_MTF2 : gd32f10x_can.h
  • CAN_TSTAT_MTFNERR0 : gd32f10x_can.h
  • CAN_TSTAT_MTFNERR1 : gd32f10x_can.h
  • CAN_TSTAT_MTFNERR2 : gd32f10x_can.h
  • CAN_TSTAT_NUM : gd32f10x_can.h
  • CAN_TSTAT_TME0 : gd32f10x_can.h
  • CAN_TSTAT_TME1 : gd32f10x_can.h
  • CAN_TSTAT_TME2 : gd32f10x_can.h
  • CAN_TSTAT_TMLS0 : gd32f10x_can.h
  • CAN_TSTAT_TMLS1 : gd32f10x_can.h
  • CAN_TSTAT_TMLS2 : gd32f10x_can.h
  • CBI_PROTOCOL : usbh_core.h
  • CCHP_PROT : gd32f10x_timer.h
  • CFG0_AHBPSC : gd32f10x_rcu.h
  • CFG0_APB1PSC : gd32f10x_rcu.h
  • CFG0_APB2PSC : gd32f10x_rcu.h
  • CFG0_CKOUT0SEL : gd32f10x_rcu.h
  • CFG0_PLLMF : gd32f10x_rcu.h
  • CFG0_REG_OFFSET : gd32f10x_rcu.h
  • CFG0_SCS : gd32f10x_rcu.h
  • CFG0_SCSS : gd32f10x_rcu.h
  • CFG0_USBPSC : gd32f10x_rcu.h
  • CFG1_PLL1MF : gd32f10x_rcu.h
  • CFG1_PLL2MF : gd32f10x_rcu.h
  • CFG1_PREDV0 : gd32f10x_rcu.h
  • CFG1_PREDV1 : gd32f10x_rcu.h
  • CFG1_REG_OFFSET : gd32f10x_rcu.h
  • CFG_PSC : gd32f10x_wwdgt.h
  • CFG_WIN : gd32f10x_wwdgt.c
  • CHCTL_MWIDTH : gd32f10x_dma.h
  • CHCTL_PRIO : gd32f10x_dma.h
  • CHCTL_PWIDTH : gd32f10x_dma.h
  • CHN_LANGID : usbd_std.h
  • CID_CID : usb_regs.h
  • CKCFG_DTCY : gd32f10x_i2c.h
  • CLASS_FSM_ID : usbh_core.h
  • CLASS_REQ_FSM_ID : usbh_core.h
  • CLKCTL_BUSMODE : gd32f10x_sdio.h
  • CLR_ERRIF : usbd_regs.h
  • CLR_ESOFIF : usbd_regs.h
  • CLR_L1REQ : usbd_regs.h
  • CLR_PMOUIF : usbd_regs.h
  • CLR_RSTIF : usbd_regs.h
  • CLR_SOFIF : usbd_regs.h
  • CLR_SPSIF : usbd_regs.h
  • CLR_STIF : usbd_regs.h
  • CLR_WKUPIF : usbd_regs.h
  • CLT2_CTSEN : gd32f10x_usart.h
  • CLT2_DENR : gd32f10x_usart.h
  • CLT2_DENT : gd32f10x_usart.h
  • CLT2_RTSEN : gd32f10x_usart.h
  • CMD_FSM_ID : usbh_core.h
  • CMDCTL_CMDRESP : gd32f10x_sdio.h
  • CRC : gd32f10x_crc.h
  • CRC_CTL : gd32f10x_crc.h
  • CRC_CTL_RST : gd32f10x_crc.h
  • CRC_DATA : gd32f10x_crc.h
  • CRC_DATA_DATA : gd32f10x_crc.h
  • CRC_FDATA : gd32f10x_crc.h
  • CRC_FDATA_FDATA : gd32f10x_crc.h
  • CTL0_CAM : gd32f10x_timer.h
  • CTL0_CKDIV : gd32f10x_timer.h
  • CTL0_DISNUM : gd32f10x_adc.h
  • CTL0_PM : gd32f10x_usart.h
  • CTL0_PSC : gd32f10x_spi.h
  • CTL0_REN : gd32f10x_usart.h
  • CTL0_SYNCM : gd32f10x_adc.h
  • CTL0_TEN : gd32f10x_usart.h
  • CTL0_TRACE_MODE : gd32f10x_dbg.h
  • CTL0_WL : gd32f10x_usart.h
  • CTL0_WM : gd32f10x_usart.h
  • CTL1_CLEN : gd32f10x_usart.h
  • CTL1_CPH : gd32f10x_usart.h
  • CTL1_CPL : gd32f10x_usart.h
  • CTL1_ETSIC : gd32f10x_adc.h
  • CTL1_ETSRC : gd32f10x_adc.h
  • CTL1_LBLEN : gd32f10x_usart.h
  • CTL1_MMC : gd32f10x_timer.h
  • CTL1_STB : gd32f10x_usart.h
  • CTL2_IRLP : gd32f10x_usart.h
  • CTL_CLOSE : usbd_regs.h
  • CTL_CMD : gd32f10x_fwdgt.c
  • CTL_CNT : gd32f10x_wwdgt.c
  • CTL_DTSEL : gd32f10x_dac.h
  • CTL_DWM : gd32f10x_dac.h
  • CTL_ERRIE : usbd_regs.h
  • CTL_ESOFIE : usbd_regs.h
  • CTL_L1REQIE : usbd_regs.h
  • CTL_L1RSREQ : usbd_regs.h
  • CTL_LOWM : usbd_regs.h
  • CTL_LVDT : gd32f10x_pmu.h
  • CTL_PMOUIE : usbd_regs.h
  • CTL_REG_OFFSET : gd32f10x_rcu.h
  • CTL_RSREQ : usbd_regs.h
  • CTL_RSTIE : usbd_regs.h
  • CTL_SETRST : usbd_regs.h
  • CTL_SETSPS : usbd_regs.h
  • CTL_SOFIE : usbd_regs.h
  • CTL_SPSIE : usbd_regs.h
  • CTL_STIE : usbd_regs.h
  • CTL_WKUPIE : usbd_regs.h
  • CTRL_FSM_ID : usbh_core.h
  • CTRL_HANDLE_TABLE_SIZE : usbh_ctrl.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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- d -

  • DAC : gd32f10x_dac.h
  • DAC0 : gd32f10x_dac.h
  • DAC0_DO : gd32f10x_dac.h
  • DAC0_DO_DAC0_DO : gd32f10x_dac.h
  • DAC0_L12DH : gd32f10x_dac.h
  • DAC0_L12DH_DAC0_DH : gd32f10x_dac.h
  • DAC0_R12DH : gd32f10x_dac.h
  • DAC0_R12DH_DAC0_DH : gd32f10x_dac.h
  • DAC0_R8DH : gd32f10x_dac.h
  • DAC0_R8DH_DAC0_DH : gd32f10x_dac.h
  • DAC1 : gd32f10x_dac.h
  • DAC1_DO : gd32f10x_dac.h
  • DAC1_DO_DAC1_DO : gd32f10x_dac.h
  • DAC1_L12DH : gd32f10x_dac.h
  • DAC1_L12DH_DAC1_DH : gd32f10x_dac.h
  • DAC1_R12DH : gd32f10x_dac.h
  • DAC1_R12DH_DAC1_DH : gd32f10x_dac.h
  • DAC1_R8DH : gd32f10x_dac.h
  • DAC1_R8DH_DAC1_DH : gd32f10x_dac.h
  • DAC_ALIGN_12B_L : gd32f10x_dac.h
  • DAC_ALIGN_12B_R : gd32f10x_dac.h
  • DAC_ALIGN_8B_R : gd32f10x_dac.h
  • DAC_CTL : gd32f10x_dac.h
  • DAC_CTL_DBOFF0 : gd32f10x_dac.h
  • DAC_CTL_DBOFF1 : gd32f10x_dac.h
  • DAC_CTL_DDMAEN0 : gd32f10x_dac.h
  • DAC_CTL_DDMAEN1 : gd32f10x_dac.h
  • DAC_CTL_DEN0 : gd32f10x_dac.h
  • DAC_CTL_DEN1 : gd32f10x_dac.h
  • DAC_CTL_DTEN0 : gd32f10x_dac.h
  • DAC_CTL_DTEN1 : gd32f10x_dac.h
  • DAC_CTL_DTSEL0 : gd32f10x_dac.h
  • DAC_CTL_DTSEL1 : gd32f10x_dac.h
  • DAC_CTL_DWBW0 : gd32f10x_dac.h
  • DAC_CTL_DWBW1 : gd32f10x_dac.h
  • DAC_CTL_DWM0 : gd32f10x_dac.h
  • DAC_CTL_DWM1 : gd32f10x_dac.h
  • DAC_LFSR_BIT0 : gd32f10x_dac.h
  • DAC_LFSR_BITS10_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS11_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS1_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS2_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS3_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS4_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS5_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS6_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS7_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS8_0 : gd32f10x_dac.h
  • DAC_LFSR_BITS9_0 : gd32f10x_dac.h
  • DAC_SWT : gd32f10x_dac.h
  • DAC_SWT_SWTR0 : gd32f10x_dac.h
  • DAC_SWT_SWTR1 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_1 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_1023 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_127 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_15 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_2047 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_255 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_3 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_31 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_4095 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_511 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_63 : gd32f10x_dac.h
  • DAC_TRIANGLE_AMPLITUDE_7 : gd32f10x_dac.h
  • DAC_TRIGGER_EXTI_9 : gd32f10x_dac.h
  • DAC_TRIGGER_SOFTWARE : gd32f10x_dac.h
  • DAC_TRIGGER_T1_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T3_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T4_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T5_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T6_TRGO : gd32f10x_dac.h
  • DAC_TRIGGER_T7_TRGO : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_1 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_10 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_11 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_12 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_2 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_3 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_4 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_5 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_6 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_7 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_8 : gd32f10x_dac.h
  • DAC_WAVE_BIT_WIDTH_9 : gd32f10x_dac.h
  • DAC_WAVE_DISABLE : gd32f10x_dac.h
  • DAC_WAVE_MODE_LFSR : gd32f10x_dac.h
  • DAC_WAVE_MODE_TRIANGLE : gd32f10x_dac.h
  • DACC_L12DH : gd32f10x_dac.h
  • DACC_L12DH_DAC0_DH : gd32f10x_dac.h
  • DACC_L12DH_DAC1_DH : gd32f10x_dac.h
  • DACC_R12DH : gd32f10x_dac.h
  • DACC_R12DH_DAC0_DH : gd32f10x_dac.h
  • DACC_R12DH_DAC1_DH : gd32f10x_dac.h
  • DACC_R8DH : gd32f10x_dac.h
  • DACC_R8DH_DAC0_DH : gd32f10x_dac.h
  • DACC_R8DH_DAC1_DH : gd32f10x_dac.h
  • DADDR_USBDAR : usbd_regs.h
  • DADDR_USBEN : usbd_regs.h
  • DAEPINT_IEPITB : usb_regs.h
  • DAEPINT_OEPITB : usb_regs.h
  • DAEPINTEN_IEPIE : usb_regs.h
  • DAEPINTEN_OEPIE : usb_regs.h
  • DATA_ALIGN : gd32f10x_dac.h
  • DATA_RECV : gd32f10x_i2c.h
  • DATA_STAGE_TIMEOUT : usb_std.h
  • DATA_TRANS : gd32f10x_i2c.h
  • DATACTL_BLKSZ : gd32f10x_sdio.h
  • DBG : gd32f10x_dbg.h
  • DBG_CTL0 : gd32f10x_dbg.h
  • DBG_CTL0_CAN0_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_DSLP_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_FWDGT_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_I2C0_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_I2C1_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_SLP_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_STB_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER0_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER10_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER11_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER12_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER13_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER1_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER2_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER3_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER4_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER5_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER6_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER7_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER8_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TIMER9_HOLD : gd32f10x_dbg.h
  • DBG_CTL0_TRACE_IOEN : gd32f10x_dbg.h
  • DBG_CTL0_TRACE_MODE : gd32f10x_dbg.h
  • DBG_CTL0_WWDGT_HOLD : gd32f10x_dbg.h
  • DBG_ID : gd32f10x_dbg.h
  • DBG_ID_ID_CODE : gd32f10x_dbg.h
  • DBG_LOW_POWER_DEEPSLEEP : gd32f10x_dbg.h
  • DBG_LOW_POWER_SLEEP : gd32f10x_dbg.h
  • DBG_LOW_POWER_STANDBY : gd32f10x_dbg.h
  • DCFG_DAR : usb_regs.h
  • DCFG_DEVSPEED : usb_regs.h
  • DCFG_DS : usb_regs.h
  • DCFG_EOPFT : usb_regs.h
  • DCFG_NZLSOH : usb_regs.h
  • DCFG_PFRI : usb_regs.h
  • DCTL_CGINAK : usb_regs.h
  • DCTL_CGONAK : usb_regs.h
  • DCTL_GINS : usb_regs.h
  • DCTL_GONS : usb_regs.h
  • DCTL_POIF : usb_regs.h
  • DCTL_RWKUP : usb_regs.h
  • DCTL_SD : usb_regs.h
  • DCTL_SGINAK : usb_regs.h
  • DCTL_SGONAK : usb_regs.h
  • DEFAULT_RESET_VALUE : gd32f10x_sdio.c
  • DEP0_MPL : usb_regs.h
  • DEP0CTL_CNAK : usb_regs.h
  • DEP0CTL_EPACT : usb_regs.h
  • DEP0CTL_EPD : usb_regs.h
  • DEP0CTL_EPEN : usb_regs.h
  • DEP0CTL_EPTYPE : usb_regs.h
  • DEP0CTL_MPL : usb_regs.h
  • DEP0CTL_NAKS : usb_regs.h
  • DEP0CTL_SNAK : usb_regs.h
  • DEP0CTL_STALL : usb_regs.h
  • DEPCTL_CNAK : usb_regs.h
  • DEPCTL_DPID : usb_regs.h
  • DEPCTL_EOFRM : usb_regs.h
  • DEPCTL_EPACT : usb_regs.h
  • DEPCTL_EPD : usb_regs.h
  • DEPCTL_EPEN : usb_regs.h
  • DEPCTL_EPTYPE : usb_regs.h
  • DEPCTL_MPL : usb_regs.h
  • DEPCTL_NAKS : usb_regs.h
  • DEPCTL_SD0PID : usb_regs.h
  • DEPCTL_SD1PID : usb_regs.h
  • DEPCTL_SEVNFRM : usb_regs.h
  • DEPCTL_SNAK : usb_regs.h
  • DEPCTL_SODDFRM : usb_regs.h
  • DEPCTL_STALL : usb_regs.h
  • DEPLEN_PCNT : usb_regs.h
  • DEPLEN_TLEN : usb_regs.h
  • DEVICE_MODE : usb_defines.h
  • DIEP0CTL_TXFNUM : usb_regs.h
  • DIEP0LEN_PCNT : usb_regs.h
  • DIEP0LEN_TLEN : usb_regs.h
  • DIEP0TFLEN_IEP0TXFD : usb_regs.h
  • DIEP0TFLEN_IEP0TXRSAR : usb_regs.h
  • DIEPCTL_TXFNUM : usb_regs.h
  • DIEPFEINTEN_IEPTXFEIE : usb_regs.h
  • DIEPINTEN_CITOEN : usb_regs.h
  • DIEPINTEN_EPDISEN : usb_regs.h
  • DIEPINTEN_EPTXFUDEN : usb_regs.h
  • DIEPINTEN_IEPNEEN : usb_regs.h
  • DIEPINTEN_TFEN : usb_regs.h
  • DIEPINTEN_TXFEEN : usb_regs.h
  • DIEPINTF_CITO : usb_regs.h
  • DIEPINTF_EPDIS : usb_regs.h
  • DIEPINTF_EPTXFUD : usb_regs.h
  • DIEPINTF_IEPNE : usb_regs.h
  • DIEPINTF_TF : usb_regs.h
  • DIEPINTF_TXFE : usb_regs.h
  • DIEPLEN_MCNT : usb_regs.h
  • DIEPTFLEN_IEPTXFD : usb_regs.h
  • DIEPTFLEN_IEPTXRSAR : usb_regs.h
  • DIEPTFSTAT_IEPTFS : usb_regs.h
  • DMA0 : gd32f10x_dma.h
  • DMA1 : gd32f10x_dma.h
  • DMA_BCTL_DPSL : gd32f10x_enet.h
  • DMA_BCTL_MASK : gd32f10x_enet.h
  • DMA_BCTL_PGBL : gd32f10x_enet.h
  • DMA_BCTL_RTPR : gd32f10x_enet.h
  • DMA_BCTL_RXDP : gd32f10x_enet.h
  • DMA_CH0CNT : gd32f10x_dma.h
  • DMA_CH0CTL : gd32f10x_dma.h
  • DMA_CH0MADDR : gd32f10x_dma.h
  • DMA_CH0PADDR : gd32f10x_dma.h
  • DMA_CH1CNT : gd32f10x_dma.h
  • DMA_CH1CTL : gd32f10x_dma.h
  • DMA_CH1MADDR : gd32f10x_dma.h
  • DMA_CH1PADDR : gd32f10x_dma.h
  • DMA_CH2CNT : gd32f10x_dma.h
  • DMA_CH2CTL : gd32f10x_dma.h
  • DMA_CH2MADDR : gd32f10x_dma.h
  • DMA_CH2PADDR : gd32f10x_dma.h
  • DMA_CH3CNT : gd32f10x_dma.h
  • DMA_CH3CTL : gd32f10x_dma.h
  • DMA_CH3MADDR : gd32f10x_dma.h
  • DMA_CH3PADDR : gd32f10x_dma.h
  • DMA_CH4CNT : gd32f10x_dma.h
  • DMA_CH4CTL : gd32f10x_dma.h
  • DMA_CH4MADDR : gd32f10x_dma.h
  • DMA_CH4PADDR : gd32f10x_dma.h
  • DMA_CH5CNT : gd32f10x_dma.h
  • DMA_CH5CTL : gd32f10x_dma.h
  • DMA_CH5MADDR : gd32f10x_dma.h
  • DMA_CH5PADDR : gd32f10x_dma.h
  • DMA_CH6CNT : gd32f10x_dma.h
  • DMA_CH6CTL : gd32f10x_dma.h
  • DMA_CH6MADDR : gd32f10x_dma.h
  • DMA_CH6PADDR : gd32f10x_dma.h
  • DMA_CHANNEL_CNT_MASK : gd32f10x_dma.h
  • DMA_CHCNT : gd32f10x_dma.h
  • DMA_CHCNT_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHCTL : gd32f10x_dma.h
  • DMA_CHCTL_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHINTF_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHMADDR : gd32f10x_dma.h
  • DMA_CHMADDR_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHPADDR : gd32f10x_dma.h
  • DMA_CHPADDR_RESET_VALUE : gd32f10x_dma.h
  • DMA_CHXCNT_CNT : gd32f10x_dma.h
  • DMA_CHXCTL_CHEN : gd32f10x_dma.h
  • DMA_CHXCTL_CMEN : gd32f10x_dma.h
  • DMA_CHXCTL_DIR : gd32f10x_dma.h
  • DMA_CHXCTL_ERRIE : gd32f10x_dma.h
  • DMA_CHXCTL_FTFIE : gd32f10x_dma.h
  • DMA_CHXCTL_HTFIE : gd32f10x_dma.h
  • DMA_CHXCTL_M2M : gd32f10x_dma.h
  • DMA_CHXCTL_MNAGA : gd32f10x_dma.h
  • DMA_CHXCTL_MWIDTH : gd32f10x_dma.h
  • DMA_CHXCTL_PNAGA : gd32f10x_dma.h
  • DMA_CHXCTL_PRIO : gd32f10x_dma.h
  • DMA_CHXCTL_PWIDTH : gd32f10x_dma.h
  • DMA_CHXMADDR_MADDR : gd32f10x_dma.h
  • DMA_CHXPADDR_PADDR : gd32f10x_dma.h
  • DMA_CIRCULAR_MODE_DISABLE : gd32f10x_dma.h
  • DMA_CIRCULAR_MODE_ENABLE : gd32f10x_dma.h
  • DMA_CRBADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_CRDADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_CTBADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_CTDADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_CTL_MASK : gd32f10x_enet.h
  • DMA_CTL_RTHC : gd32f10x_enet.h
  • DMA_CTL_TTHC : gd32f10x_enet.h
  • DMA_FLAG_ADD : gd32f10x_dma.h
  • DMA_FLAG_ERR : gd32f10x_dma.h
  • DMA_FLAG_FTF : gd32f10x_dma.h
  • DMA_FLAG_G : gd32f10x_dma.h
  • DMA_FLAG_HTF : gd32f10x_dma.h
  • DMA_INCR0 : usb_regs.h
  • DMA_INCR1 : usb_regs.h
  • DMA_INCR16 : usb_regs.h
  • DMA_INCR4 : usb_regs.h
  • DMA_INCR8 : usb_regs.h
  • DMA_INT_ERR : gd32f10x_dma.h
  • DMA_INT_FLAG_ERR : gd32f10x_dma.h
  • DMA_INT_FLAG_FTF : gd32f10x_dma.h
  • DMA_INT_FLAG_G : gd32f10x_dma.h
  • DMA_INT_FLAG_HTF : gd32f10x_dma.h
  • DMA_INT_FTF : gd32f10x_dma.h
  • DMA_INT_HTF : gd32f10x_dma.h
  • DMA_INTC : gd32f10x_dma.h
  • DMA_INTC_ERRIFC : gd32f10x_dma.h
  • DMA_INTC_FTFIFC : gd32f10x_dma.h
  • DMA_INTC_GIFC : gd32f10x_dma.h
  • DMA_INTC_HTFIFC : gd32f10x_dma.h
  • DMA_INTEN_REG_OFFSET : gd32f10x_enet.h
  • DMA_INTF : gd32f10x_dma.h
  • DMA_INTF_ERRIF : gd32f10x_dma.h
  • DMA_INTF_FTFIF : gd32f10x_dma.h
  • DMA_INTF_GIF : gd32f10x_dma.h
  • DMA_INTF_HTFIF : gd32f10x_dma.h
  • DMA_MEMORY_INCREASE_DISABLE : gd32f10x_dma.h
  • DMA_MEMORY_INCREASE_ENABLE : gd32f10x_dma.h
  • DMA_MEMORY_TO_MEMORY_DISABLE : gd32f10x_dma.h
  • DMA_MEMORY_TO_MEMORY_ENABLE : gd32f10x_dma.h
  • DMA_MEMORY_TO_PERIPHERAL : gd32f10x_dma.h
  • DMA_MEMORY_WIDTH_16BIT : gd32f10x_dma.h
  • DMA_MEMORY_WIDTH_32BIT : gd32f10x_dma.h
  • DMA_MEMORY_WIDTH_8BIT : gd32f10x_dma.h
  • DMA_PERIPH_INCREASE_DISABLE : gd32f10x_dma.h
  • DMA_PERIPH_INCREASE_ENABLE : gd32f10x_dma.h
  • DMA_PERIPHERAL_TO_MEMORY : gd32f10x_dma.h
  • DMA_PERIPHERAL_WIDTH_16BIT : gd32f10x_dma.h
  • DMA_PERIPHERAL_WIDTH_32BIT : gd32f10x_dma.h
  • DMA_PERIPHERAL_WIDTH_8BIT : gd32f10x_dma.h
  • DMA_PRIORITY_HIGH : gd32f10x_dma.h
  • DMA_PRIORITY_LOW : gd32f10x_dma.h
  • DMA_PRIORITY_MEDIUM : gd32f10x_dma.h
  • DMA_PRIORITY_ULTRA_HIGH : gd32f10x_dma.h
  • DMA_RDTADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_STAT_REG_OFFSET : gd32f10x_enet.h
  • DMA_TDTADDR_REG_OFFSET : gd32f10x_enet.h
  • DMA_WRONG_HANDLE : gd32f10x_dma.c
  • DMACFG_DMATA : gd32f10x_timer.h
  • DMACFG_DMATC : gd32f10x_timer.h
  • DOEP0LEN_PCNT : usb_regs.h
  • DOEP0LEN_STPCNT : usb_regs.h
  • DOEP0LEN_TLEN : usb_regs.h
  • DOEPINTEN_BTBSTPEN : usb_regs.h
  • DOEPINTEN_EPDISEN : usb_regs.h
  • DOEPINTEN_EPRXFOVREN : usb_regs.h
  • DOEPINTEN_STPFEN : usb_regs.h
  • DOEPINTEN_TFEN : usb_regs.h
  • DOEPINTF_BTBSTP : usb_regs.h
  • DOEPINTF_EPDIS : usb_regs.h
  • DOEPINTF_EPRXFOVR : usb_regs.h
  • DOEPINTF_STPF : usb_regs.h
  • DOEPINTF_TF : usb_regs.h
  • DOEPLEN_RXDPID : usb_regs.h
  • DOEPLEN_STPCNT : usb_regs.h
  • DP83848 : gd32f10x_enet.h
  • DPID_DATA0 : usb_defines.h
  • DPID_DATA1 : usb_defines.h
  • DPID_DATA2 : usb_defines.h
  • DPID_MDATA : usb_defines.h
  • DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ : usb_defines.h
  • DSTAT_ENUMSPD_FS_PHY_48MHZ : usb_defines.h
  • DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ : usb_defines.h
  • DSTAT_ENUMSPD_LS_PHY_6MHZ : usb_defines.h
  • DSTAT_ES : usb_regs.h
  • DSTAT_FNRSOF : usb_regs.h
  • DSTAT_SPST : usb_regs.h
  • DSV_DSLPVS : gd32f10x_rcu.h
  • DVBUSDT_DVBUSDT : usb_regs.h
  • DVBUSPT_DVBUSPT : usb_regs.h
  • DWBW : gd32f10x_dac.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- e -

  • ENDP_BUF_ADDR : usbd_core.h
  • ENDP_RXSTAT : usbd_regs.h
  • ENDP_TXSTAT : usbd_regs.h
  • ENDP_TYPE : usbd_regs.h
  • ENET : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_1024BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_1280BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_1536BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_1792BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_256BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_512BYTES : gd32f10x_enet.h
  • ENET_ACTIVE_THRESHOLD_768BYTES : gd32f10x_enet.h
  • ENET_ADDRESS_ALIGN_DISABLE : gd32f10x_enet.h
  • ENET_ADDRESS_ALIGN_ENABLE : gd32f10x_enet.h
  • ENET_ADDRESS_FILTER_DA : gd32f10x_enet.h
  • ENET_ADDRESS_FILTER_SA : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE0 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE1 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE2 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE3 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE4 : gd32f10x_enet.h
  • ENET_ADDRESS_MASK_BYTE5 : gd32f10x_enet.h
  • ENET_ADDRH_BASE : gd32f10x_enet.h
  • ENET_ADDRL_BASE : gd32f10x_enet.h
  • ENET_ARBITRATION_RXPRIORTX : gd32f10x_enet.h
  • ENET_ARBITRATION_RXTX_1_1 : gd32f10x_enet.h
  • ENET_ARBITRATION_RXTX_2_1 : gd32f10x_enet.h
  • ENET_ARBITRATION_RXTX_3_1 : gd32f10x_enet.h
  • ENET_ARBITRATION_RXTX_4_1 : gd32f10x_enet.h
  • ENET_AUTO_PADCRC_DROP : gd32f10x_enet.h
  • ENET_AUTO_PADCRC_DROP_DISABLE : gd32f10x_enet.h
  • ENET_AUTO_PADCRC_DROP_ENABLE : gd32f10x_enet.h
  • ENET_BACK_PRESSURE : gd32f10x_enet.h
  • ENET_BACK_PRESSURE_DISABLE : gd32f10x_enet.h
  • ENET_BACK_PRESSURE_ENABLE : gd32f10x_enet.h
  • ENET_BACKOFFLIMIT_1 : gd32f10x_enet.h
  • ENET_BACKOFFLIMIT_10 : gd32f10x_enet.h
  • ENET_BACKOFFLIMIT_4 : gd32f10x_enet.h
  • ENET_BACKOFFLIMIT_8 : gd32f10x_enet.h
  • ENET_BIT_POS : gd32f10x_enet.h
  • ENET_BROADCASTFRAMES_DISABLE : gd32f10x_enet.h
  • ENET_BROADCASTFRAMES_ENABLE : gd32f10x_enet.h
  • ENET_CARRIERSENSE_DISABLE : gd32f10x_enet.h
  • ENET_CARRIERSENSE_ENABLE : gd32f10x_enet.h
  • ENET_CHECKSUM_DISABLE : gd32f10x_enet.h
  • ENET_CHECKSUM_IPV4HEADER : gd32f10x_enet.h
  • ENET_CHECKSUM_TCPUDPICMP_FULL : gd32f10x_enet.h
  • ENET_CHECKSUM_TCPUDPICMP_SEGMENT : gd32f10x_enet.h
  • ENET_CHECKSUMOFFLOAD_DISABLE : gd32f10x_enet.h
  • ENET_CHECKSUMOFFLOAD_ENABLE : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_1024BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_1280BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_1536BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_1792BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_256BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_512BYTES : gd32f10x_enet.h
  • ENET_DEACTIVE_THRESHOLD_768BYTES : gd32f10x_enet.h
  • ENET_DEFERRALCHECK_DISABLE : gd32f10x_enet.h
  • ENET_DEFERRALCHECK_ENABLE : gd32f10x_enet.h
  • ENET_DELAY_TO : gd32f10x_enet.h
  • ENET_DEST_FILTER_INVERSE : gd32f10x_enet.h
  • ENET_DEST_FILTER_INVERSE_DISABLE : gd32f10x_enet.h
  • ENET_DEST_FILTER_INVERSE_ENABLE : gd32f10x_enet.h
  • ENET_DMA_BCTL : gd32f10x_enet.h
  • ENET_DMA_BCTL_AA : gd32f10x_enet.h
  • ENET_DMA_BCTL_DAB : gd32f10x_enet.h
  • ENET_DMA_BCTL_DPSL : gd32f10x_enet.h
  • ENET_DMA_BCTL_FB : gd32f10x_enet.h
  • ENET_DMA_BCTL_FPBL : gd32f10x_enet.h
  • ENET_DMA_BCTL_PGBL : gd32f10x_enet.h
  • ENET_DMA_BCTL_RTPR : gd32f10x_enet.h
  • ENET_DMA_BCTL_RXDP : gd32f10x_enet.h
  • ENET_DMA_BCTL_SWR : gd32f10x_enet.h
  • ENET_DMA_BCTL_UIP : gd32f10x_enet.h
  • ENET_DMA_CRBADDR : gd32f10x_enet.h
  • ENET_DMA_CRBADDR_RBAP : gd32f10x_enet.h
  • ENET_DMA_CRDADDR : gd32f10x_enet.h
  • ENET_DMA_CRDADDR_RDAP : gd32f10x_enet.h
  • ENET_DMA_CTBADDR : gd32f10x_enet.h
  • ENET_DMA_CTBADDR_TBAP : gd32f10x_enet.h
  • ENET_DMA_CTDADDR : gd32f10x_enet.h
  • ENET_DMA_CTDADDR_TDAP : gd32f10x_enet.h
  • ENET_DMA_CTL : gd32f10x_enet.h
  • ENET_DMA_CTL_DAFRF : gd32f10x_enet.h
  • ENET_DMA_CTL_DTCERFD : gd32f10x_enet.h
  • ENET_DMA_CTL_FERF : gd32f10x_enet.h
  • ENET_DMA_CTL_FTF : gd32f10x_enet.h
  • ENET_DMA_CTL_FUF : gd32f10x_enet.h
  • ENET_DMA_CTL_OSF : gd32f10x_enet.h
  • ENET_DMA_CTL_RSFD : gd32f10x_enet.h
  • ENET_DMA_CTL_RTHC : gd32f10x_enet.h
  • ENET_DMA_CTL_SRE : gd32f10x_enet.h
  • ENET_DMA_CTL_STE : gd32f10x_enet.h
  • ENET_DMA_CTL_TSFD : gd32f10x_enet.h
  • ENET_DMA_CTL_TTHC : gd32f10x_enet.h
  • ENET_DMA_INTEN : gd32f10x_enet.h
  • ENET_DMA_INTEN_AIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_ERIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_ETIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_FBEIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_NIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_RBUIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_RIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_ROIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_RPSIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_RWTIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TBUIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TJTIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TPSIE : gd32f10x_enet.h
  • ENET_DMA_INTEN_TUIE : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT_MSFA : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT_MSFC : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT_OBFOC : gd32f10x_enet.h
  • ENET_DMA_MFBOCNT_OBMFC : gd32f10x_enet.h
  • ENET_DMA_RDTADDR : gd32f10x_enet.h
  • ENET_DMA_RDTADDR_SRT : gd32f10x_enet.h
  • ENET_DMA_RPEN : gd32f10x_enet.h
  • ENET_DMA_RPEN_RPE : gd32f10x_enet.h
  • ENET_DMA_STAT : gd32f10x_enet.h
  • ENET_DMA_STAT_AI : gd32f10x_enet.h
  • ENET_DMA_STAT_EB : gd32f10x_enet.h
  • ENET_DMA_STAT_ER : gd32f10x_enet.h
  • ENET_DMA_STAT_ET : gd32f10x_enet.h
  • ENET_DMA_STAT_FBE : gd32f10x_enet.h
  • ENET_DMA_STAT_MSC : gd32f10x_enet.h
  • ENET_DMA_STAT_NI : gd32f10x_enet.h
  • ENET_DMA_STAT_RBU : gd32f10x_enet.h
  • ENET_DMA_STAT_RO : gd32f10x_enet.h
  • ENET_DMA_STAT_RP : gd32f10x_enet.h
  • ENET_DMA_STAT_RPS : gd32f10x_enet.h
  • ENET_DMA_STAT_RS : gd32f10x_enet.h
  • ENET_DMA_STAT_RWT : gd32f10x_enet.h
  • ENET_DMA_STAT_TBU : gd32f10x_enet.h
  • ENET_DMA_STAT_TJT : gd32f10x_enet.h
  • ENET_DMA_STAT_TP : gd32f10x_enet.h
  • ENET_DMA_STAT_TPS : gd32f10x_enet.h
  • ENET_DMA_STAT_TS : gd32f10x_enet.h
  • ENET_DMA_STAT_TST : gd32f10x_enet.h
  • ENET_DMA_STAT_TU : gd32f10x_enet.h
  • ENET_DMA_STAT_WUM : gd32f10x_enet.h
  • ENET_DMA_TDTADDR : gd32f10x_enet.h
  • ENET_DMA_TDTADDR_STT : gd32f10x_enet.h
  • ENET_DMA_TPEN : gd32f10x_enet.h
  • ENET_DMA_TPEN_TPE : gd32f10x_enet.h
  • ENET_ERROR_DESC_ACCESS : gd32f10x_enet.h
  • ENET_ERROR_READ_TRANSFER : gd32f10x_enet.h
  • ENET_ERROR_TXDATA_TRANSFER : gd32f10x_enet.h
  • ENET_FILTER_MODE_EITHER : gd32f10x_enet.h
  • ENET_FIXED_BURST_DISABLE : gd32f10x_enet.h
  • ENET_FIXED_BURST_ENABLE : gd32f10x_enet.h
  • ENET_FLUSH_RXFRAME_DISABLE : gd32f10x_enet.h
  • ENET_FLUSH_RXFRAME_ENABLE : gd32f10x_enet.h
  • ENET_FORWARD_ERRFRAMES : gd32f10x_enet.h
  • ENET_FORWARD_ERRFRAMES_DISABLE : gd32f10x_enet.h
  • ENET_FORWARD_ERRFRAMES_ENABLE : gd32f10x_enet.h
  • ENET_FORWARD_UNDERSZ_GOODFRAMES : gd32f10x_enet.h
  • ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE : gd32f10x_enet.h
  • ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE : gd32f10x_enet.h
  • ENET_GET_MACADDR : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_40BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_48BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_56BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_64BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_72BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_80BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_88BIT : gd32f10x_enet.h
  • ENET_INTERFRAMEGAP_96BIT : gd32f10x_enet.h
  • ENET_JABBER_DISABLE : gd32f10x_enet.h
  • ENET_JABBER_ENABLE : gd32f10x_enet.h
  • ENET_LOOPBACKMODE_DISABLE : gd32f10x_enet.h
  • ENET_LOOPBACKMODE_ENABLE : gd32f10x_enet.h
  • ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT : gd32f10x_enet.h
  • ENET_MAC_ADDR0H : gd32f10x_enet.h
  • ENET_MAC_ADDR0H_ADDR0H : gd32f10x_enet.h
  • ENET_MAC_ADDR0H_MO : gd32f10x_enet.h
  • ENET_MAC_ADDR0L : gd32f10x_enet.h
  • ENET_MAC_ADDR0L_ADDR0L : gd32f10x_enet.h
  • ENET_MAC_ADDR1H : gd32f10x_enet.h
  • ENET_MAC_ADDR1H_ADDR1H : gd32f10x_enet.h
  • ENET_MAC_ADDR1H_AFE : gd32f10x_enet.h
  • ENET_MAC_ADDR1H_MB : gd32f10x_enet.h
  • ENET_MAC_ADDR1H_SAF : gd32f10x_enet.h
  • ENET_MAC_ADDR1L : gd32f10x_enet.h
  • ENET_MAC_ADDR1L_ADDR1L : gd32f10x_enet.h
  • ENET_MAC_ADDR2H_ADDR2H : gd32f10x_enet.h
  • ENET_MAC_ADDR2H_AFE : gd32f10x_enet.h
  • ENET_MAC_ADDR2H_MB : gd32f10x_enet.h
  • ENET_MAC_ADDR2H_SAF : gd32f10x_enet.h
  • ENET_MAC_ADDR2L : gd32f10x_enet.h
  • ENET_MAC_ADDR2L_ADDR2L : gd32f10x_enet.h
  • ENET_MAC_ADDR3H : gd32f10x_enet.h
  • ENET_MAC_ADDR3H_ADDR3H : gd32f10x_enet.h
  • ENET_MAC_ADDR3H_AFE : gd32f10x_enet.h
  • ENET_MAC_ADDR3H_MB : gd32f10x_enet.h
  • ENET_MAC_ADDR3H_SAF : gd32f10x_enet.h
  • ENET_MAC_ADDR3L : gd32f10x_enet.h
  • ENET_MAC_ADDR3L_ADDR3L : gd32f10x_enet.h
  • ENET_MAC_ADDT2H : gd32f10x_enet.h
  • ENET_MAC_CFG : gd32f10x_enet.h
  • ENET_MAC_CFG_APCD : gd32f10x_enet.h
  • ENET_MAC_CFG_BOL : gd32f10x_enet.h
  • ENET_MAC_CFG_CSD : gd32f10x_enet.h
  • ENET_MAC_CFG_DFC : gd32f10x_enet.h
  • ENET_MAC_CFG_DPM : gd32f10x_enet.h
  • ENET_MAC_CFG_IGBS : gd32f10x_enet.h
  • ENET_MAC_CFG_IPFCO : gd32f10x_enet.h
  • ENET_MAC_CFG_JBD : gd32f10x_enet.h
  • ENET_MAC_CFG_LBM : gd32f10x_enet.h
  • ENET_MAC_CFG_REN : gd32f10x_enet.h
  • ENET_MAC_CFG_ROD : gd32f10x_enet.h
  • ENET_MAC_CFG_RTD : gd32f10x_enet.h
  • ENET_MAC_CFG_SPD : gd32f10x_enet.h
  • ENET_MAC_CFG_TEN : gd32f10x_enet.h
  • ENET_MAC_CFG_WDD : gd32f10x_enet.h
  • ENET_MAC_FCTH : gd32f10x_enet.h
  • ENET_MAC_FCTH_RFA : gd32f10x_enet.h
  • ENET_MAC_FCTH_RFD : gd32f10x_enet.h
  • ENET_MAC_FCTL : gd32f10x_enet.h
  • ENET_MAC_FCTL_DZQP : gd32f10x_enet.h
  • ENET_MAC_FCTL_FLCBBKPA : gd32f10x_enet.h
  • ENET_MAC_FCTL_PLTS : gd32f10x_enet.h
  • ENET_MAC_FCTL_PTM : gd32f10x_enet.h
  • ENET_MAC_FCTL_RFCEN : gd32f10x_enet.h
  • ENET_MAC_FCTL_TFCEN : gd32f10x_enet.h
  • ENET_MAC_FCTL_UPFDT : gd32f10x_enet.h
  • ENET_MAC_FRMF : gd32f10x_enet.h
  • ENET_MAC_FRMF_BFRMD : gd32f10x_enet.h
  • ENET_MAC_FRMF_DAIFLT : gd32f10x_enet.h
  • ENET_MAC_FRMF_FAR : gd32f10x_enet.h
  • ENET_MAC_FRMF_HMF : gd32f10x_enet.h
  • ENET_MAC_FRMF_HPFLT : gd32f10x_enet.h
  • ENET_MAC_FRMF_HUF : gd32f10x_enet.h
  • ENET_MAC_FRMF_MFD : gd32f10x_enet.h
  • ENET_MAC_FRMF_PCFRM : gd32f10x_enet.h
  • ENET_MAC_FRMF_PM : gd32f10x_enet.h
  • ENET_MAC_FRMF_SAFLT : gd32f10x_enet.h
  • ENET_MAC_FRMF_SAIFLT : gd32f10x_enet.h
  • ENET_MAC_HLH : gd32f10x_enet.h
  • ENET_MAC_HLH_HLH : gd32f10x_enet.h
  • ENET_MAC_HLL : gd32f10x_enet.h
  • ENET_MAC_HLL_HLL : gd32f10x_enet.h
  • ENET_MAC_INTF : gd32f10x_enet.h
  • ENET_MAC_INTF_MSC : gd32f10x_enet.h
  • ENET_MAC_INTF_MSCR : gd32f10x_enet.h
  • ENET_MAC_INTF_MSCT : gd32f10x_enet.h
  • ENET_MAC_INTF_TMST : gd32f10x_enet.h
  • ENET_MAC_INTF_WUM : gd32f10x_enet.h
  • ENET_MAC_INTMSK : gd32f10x_enet.h
  • ENET_MAC_INTMSK_TMSTIM : gd32f10x_enet.h
  • ENET_MAC_INTMSK_WUMIM : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_CLR : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_PA : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_PB : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_PR : gd32f10x_enet.h
  • ENET_MAC_PHY_CTL_PW : gd32f10x_enet.h
  • ENET_MAC_PHY_DATA : gd32f10x_enet.h
  • ENET_MAC_PHY_DATA_PD : gd32f10x_enet.h
  • ENET_MAC_RWFF : gd32f10x_enet.h
  • ENET_MAC_RWFF_DATA : gd32f10x_enet.h
  • ENET_MAC_VLT : gd32f10x_enet.h
  • ENET_MAC_VLT_VLTC : gd32f10x_enet.h
  • ENET_MAC_VLT_VLTI : gd32f10x_enet.h
  • ENET_MAC_WUM : gd32f10x_enet.h
  • ENET_MAC_WUM_GU : gd32f10x_enet.h
  • ENET_MAC_WUM_MPEN : gd32f10x_enet.h
  • ENET_MAC_WUM_MPKR : gd32f10x_enet.h
  • ENET_MAC_WUM_PWD : gd32f10x_enet.h
  • ENET_MAC_WUM_WFEN : gd32f10x_enet.h
  • ENET_MAC_WUM_WUFFRPR : gd32f10x_enet.h
  • ENET_MAC_WUM_WUFR : gd32f10x_enet.h
  • ENET_MAX_FRAME_SIZE : gd32f10x_enet.h
  • ENET_MDC_HCLK_DIV16 : gd32f10x_enet.h
  • ENET_MDC_HCLK_DIV26 : gd32f10x_enet.h
  • ENET_MDC_HCLK_DIV42 : gd32f10x_enet.h
  • ENET_MDC_HCLK_DIV62 : gd32f10x_enet.h
  • ENET_MODE_FULLDUPLEX : gd32f10x_enet.h
  • ENET_MODE_HALFDUPLEX : gd32f10x_enet.h
  • ENET_MSC_COUNTER_STOP_ROLLOVER : gd32f10x_enet.h
  • ENET_MSC_COUNTERS_FREEZE : gd32f10x_enet.h
  • ENET_MSC_CTL : gd32f10x_enet.h
  • ENET_MSC_CTL_CTR : gd32f10x_enet.h
  • ENET_MSC_CTL_CTSR : gd32f10x_enet.h
  • ENET_MSC_CTL_MCFZ : gd32f10x_enet.h
  • ENET_MSC_CTL_RTOR : gd32f10x_enet.h
  • ENET_MSC_MSCCNT : gd32f10x_enet.h
  • ENET_MSC_MSCCNT_MSCC : gd32f10x_enet.h
  • ENET_MSC_RESET_ON_READ : gd32f10x_enet.h
  • ENET_MSC_RFAECNT : gd32f10x_enet.h
  • ENET_MSC_RFAECNT_RFAER : gd32f10x_enet.h
  • ENET_MSC_RFCECNT : gd32f10x_enet.h
  • ENET_MSC_RFCECNT_RFCER : gd32f10x_enet.h
  • ENET_MSC_RGUFCNT : gd32f10x_enet.h
  • ENET_MSC_RGUFCNT_RGUF : gd32f10x_enet.h
  • ENET_MSC_RINTF : gd32f10x_enet.h
  • ENET_MSC_RINTF_RFAE : gd32f10x_enet.h
  • ENET_MSC_RINTF_RFCE : gd32f10x_enet.h
  • ENET_MSC_RINTF_RGUF : gd32f10x_enet.h
  • ENET_MSC_RINTMSK : gd32f10x_enet.h
  • ENET_MSC_RINTMSK_RFAEIM : gd32f10x_enet.h
  • ENET_MSC_RINTMSK_RFCEIM : gd32f10x_enet.h
  • ENET_MSC_RINTMSK_RGUFIM : gd32f10x_enet.h
  • ENET_MSC_SCCNT : gd32f10x_enet.h
  • ENET_MSC_SCCNT_SCC : gd32f10x_enet.h
  • ENET_MSC_TGFCNT : gd32f10x_enet.h
  • ENET_MSC_TGFCNT_TGF : gd32f10x_enet.h
  • ENET_MSC_TINTF : gd32f10x_enet.h
  • ENET_MSC_TINTF_TGF : gd32f10x_enet.h
  • ENET_MSC_TINTF_TGFMSC : gd32f10x_enet.h
  • ENET_MSC_TINTF_TGFSC : gd32f10x_enet.h
  • ENET_MSC_TINTMSK : gd32f10x_enet.h
  • ENET_MSC_TINTMSK_TGFIM : gd32f10x_enet.h
  • ENET_MSC_TINTMSK_TGFMSCIM : gd32f10x_enet.h
  • ENET_MSC_TINTMSK_TGFSCIM : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_HASH : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_HASH_MODE : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_HASH_OR_PERFECT : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_NONE : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_PASS : gd32f10x_enet.h
  • ENET_MULTICAST_FILTER_PERFECT : gd32f10x_enet.h
  • ENET_NO_FLUSH_RXFRAME : gd32f10x_enet.h
  • ENET_NOCOPY_FRAME_RECEIVE : gd32f10x_enet.h
  • ENET_NOCOPY_FRAME_TRANSMIT : gd32f10x_enet.h
  • ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE : gd32f10x_enet.h
  • ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE : gd32f10x_enet.h
  • ENET_PAUSETIME_MINUS144 : gd32f10x_enet.h
  • ENET_PAUSETIME_MINUS256 : gd32f10x_enet.h
  • ENET_PAUSETIME_MINUS28 : gd32f10x_enet.h
  • ENET_PAUSETIME_MINUS4 : gd32f10x_enet.h
  • ENET_PCFRM_FORWARD_ALL : gd32f10x_enet.h
  • ENET_PCFRM_FORWARD_FILTERED : gd32f10x_enet.h
  • ENET_PCFRM_PREVENT_ALL : gd32f10x_enet.h
  • ENET_PCFRM_PREVENT_PAUSEFRAME : gd32f10x_enet.h
  • ENET_PGBL_16BEAT : gd32f10x_enet.h
  • ENET_PGBL_1BEAT : gd32f10x_enet.h
  • ENET_PGBL_2BEAT : gd32f10x_enet.h
  • ENET_PGBL_32BEAT : gd32f10x_enet.h
  • ENET_PGBL_4BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_128BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_16BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_32BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_4BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_64BEAT : gd32f10x_enet.h
  • ENET_PGBL_4xPGBL_8BEAT : gd32f10x_enet.h
  • ENET_PGBL_8BEAT : gd32f10x_enet.h
  • ENET_PROMISCUOUS_DISABLE : gd32f10x_enet.h
  • ENET_PROMISCUOUS_ENABLE : gd32f10x_enet.h
  • ENET_PTP_ADD_TO_TIME : gd32f10x_enet.h
  • ENET_PTP_ETH : gd32f10x_enet.h
  • ENET_PTP_ETH_ETSH : gd32f10x_enet.h
  • ENET_PTP_ETL : gd32f10x_enet.h
  • ENET_PTP_ETL_ETSL : gd32f10x_enet.h
  • ENET_PTP_SSINC : gd32f10x_enet.h
  • ENET_PTP_SSINC_STMSSI : gd32f10x_enet.h
  • ENET_PTP_SUBSTRACT_FROM_TIME : gd32f10x_enet.h
  • ENET_PTP_TIME_NEGATIVE : gd32f10x_enet.h
  • ENET_PTP_TIME_POSITIVE : gd32f10x_enet.h
  • ENET_PTP_TIMESTAMP_INT : gd32f10x_enet.h
  • ENET_PTP_TSADDEND : gd32f10x_enet.h
  • ENET_PTP_TSADDEND_TMSA : gd32f10x_enet.h
  • ENET_PTP_TSCTL : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSARU : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSEN : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSFCU : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSITEN : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSSTI : gd32f10x_enet.h
  • ENET_PTP_TSCTL_TMSSTU : gd32f10x_enet.h
  • ENET_PTP_TSH : gd32f10x_enet.h
  • ENET_PTP_TSH_STMS : gd32f10x_enet.h
  • ENET_PTP_TSL : gd32f10x_enet.h
  • ENET_PTP_TSL_STMSS : gd32f10x_enet.h
  • ENET_PTP_TSL_STS : gd32f10x_enet.h
  • ENET_PTP_TSUH : gd32f10x_enet.h
  • ENET_PTP_TSUH_TMSUS : gd32f10x_enet.h
  • ENET_PTP_TSUL : gd32f10x_enet.h
  • ENET_PTP_TSUL_TMSUPNS : gd32f10x_enet.h
  • ENET_PTP_TSUL_TMSUSS : gd32f10x_enet.h
  • ENET_RANGE : gd32f10x_enet.h
  • ENET_RDES0_CERR : gd32f10x_enet.h
  • ENET_RDES0_DAFF : gd32f10x_enet.h
  • ENET_RDES0_DAV : gd32f10x_enet.h
  • ENET_RDES0_DBERR : gd32f10x_enet.h
  • ENET_RDES0_DERR : gd32f10x_enet.h
  • ENET_RDES0_ERRS : gd32f10x_enet.h
  • ENET_RDES0_FDES : gd32f10x_enet.h
  • ENET_RDES0_FRML : gd32f10x_enet.h
  • ENET_RDES0_FRMT : gd32f10x_enet.h
  • ENET_RDES0_IPHERR : gd32f10x_enet.h
  • ENET_RDES0_LCO : gd32f10x_enet.h
  • ENET_RDES0_LDES : gd32f10x_enet.h
  • ENET_RDES0_LERR : gd32f10x_enet.h
  • ENET_RDES0_OERR : gd32f10x_enet.h
  • ENET_RDES0_PCERR : gd32f10x_enet.h
  • ENET_RDES0_RERR : gd32f10x_enet.h
  • ENET_RDES0_RWDT : gd32f10x_enet.h
  • ENET_RDES0_SAFF : gd32f10x_enet.h
  • ENET_RDES0_VTAG : gd32f10x_enet.h
  • ENET_RDES1_DINTC : gd32f10x_enet.h
  • ENET_RDES1_RB1S : gd32f10x_enet.h
  • ENET_RDES1_RB2S : gd32f10x_enet.h
  • ENET_RDES1_RCHM : gd32f10x_enet.h
  • ENET_RDES1_RERM : gd32f10x_enet.h
  • ENET_RDES2_RB1AP : gd32f10x_enet.h
  • ENET_RDES3_RB2AP : gd32f10x_enet.h
  • ENET_RECEIVE_COMPLETE_INT_DISABLE : gd32f10x_enet.h
  • ENET_RECEIVE_COMPLETE_INT_ENABLE : gd32f10x_enet.h
  • ENET_RECEIVEOWN_DISABLE : gd32f10x_enet.h
  • ENET_RECEIVEOWN_ENABLE : gd32f10x_enet.h
  • ENET_REG_VAL : gd32f10x_enet.h
  • ENET_REGIDX_BIT : gd32f10x_enet.h
  • ENET_RESET_TO : gd32f10x_enet.h
  • ENET_RETRYTRANSMISSION_DISABLE : gd32f10x_enet.h
  • ENET_RETRYTRANSMISSION_ENABLE : gd32f10x_enet.h
  • ENET_RX_FILTER_DISABLE : gd32f10x_enet.h
  • ENET_RX_FILTER_ENABLE : gd32f10x_enet.h
  • ENET_RX_FLOWCONTROL : gd32f10x_enet.h
  • ENET_RX_FLOWCONTROL_DISABLE : gd32f10x_enet.h
  • ENET_RX_FLOWCONTROL_ENABLE : gd32f10x_enet.h
  • ENET_RX_MODE_CUTTHROUGH : gd32f10x_enet.h
  • ENET_RX_MODE_STOREFORWARD : gd32f10x_enet.h
  • ENET_RX_STATE_CLOSING : gd32f10x_enet.h
  • ENET_RX_STATE_FETCHING : gd32f10x_enet.h
  • ENET_RX_STATE_QUEUING : gd32f10x_enet.h
  • ENET_RX_STATE_STOPPED : gd32f10x_enet.h
  • ENET_RX_STATE_SUSPENDED : gd32f10x_enet.h
  • ENET_RX_STATE_WAITING : gd32f10x_enet.h
  • ENET_RX_THRESHOLD_128BYTES : gd32f10x_enet.h
  • ENET_RX_THRESHOLD_32BYTES : gd32f10x_enet.h
  • ENET_RX_THRESHOLD_64BYTES : gd32f10x_enet.h
  • ENET_RX_THRESHOLD_96BYTES : gd32f10x_enet.h
  • ENET_RXBUF_NUM : gd32f10x_enet.h
  • ENET_RXBUF_SIZE : gd32f10x_enet.h
  • ENET_RXDP_16BEAT : gd32f10x_enet.h
  • ENET_RXDP_1BEAT : gd32f10x_enet.h
  • ENET_RXDP_2BEAT : gd32f10x_enet.h
  • ENET_RXDP_32BEAT : gd32f10x_enet.h
  • ENET_RXDP_4BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_128BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_16BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_32BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_4BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_64BEAT : gd32f10x_enet.h
  • ENET_RXDP_4xPGBL_8BEAT : gd32f10x_enet.h
  • ENET_RXDP_8BEAT : gd32f10x_enet.h
  • ENET_RXTX_DIFFERENT_PGBL : gd32f10x_enet.h
  • ENET_RXTX_SAME_PGBL : gd32f10x_enet.h
  • ENET_RXTX_TIMESTAMP : gd32f10x_enet.h
  • ENET_SECONDFRAME_OPT : gd32f10x_enet.h
  • ENET_SECONDFRAME_OPT_DISABLE : gd32f10x_enet.h
  • ENET_SECONDFRAME_OPT_ENABLE : gd32f10x_enet.h
  • ENET_SET_MACADDRH : gd32f10x_enet.h
  • ENET_SET_MACADDRL : gd32f10x_enet.h
  • ENET_SPEEDMODE_100M : gd32f10x_enet.h
  • ENET_SPEEDMODE_10M : gd32f10x_enet.h
  • ENET_SRC_FILTER : gd32f10x_enet.h
  • ENET_SRC_FILTER_DISABLE : gd32f10x_enet.h
  • ENET_SRC_FILTER_INVERSE : gd32f10x_enet.h
  • ENET_SRC_FILTER_INVERSE_ENABLE : gd32f10x_enet.h
  • ENET_SRC_FILTER_NORMAL_ENABLE : gd32f10x_enet.h
  • ENET_TCPIP_CKSUMERROR_ACCEPT : gd32f10x_enet.h
  • ENET_TCPIP_CKSUMERROR_DROP : gd32f10x_enet.h
  • ENET_TDES0_CM : gd32f10x_enet.h
  • ENET_TDES0_COCNT : gd32f10x_enet.h
  • ENET_TDES0_DAV : gd32f10x_enet.h
  • ENET_TDES0_DB : gd32f10x_enet.h
  • ENET_TDES0_DCRC : gd32f10x_enet.h
  • ENET_TDES0_DPAD : gd32f10x_enet.h
  • ENET_TDES0_ECO : gd32f10x_enet.h
  • ENET_TDES0_ES : gd32f10x_enet.h
  • ENET_TDES0_EXD : gd32f10x_enet.h
  • ENET_TDES0_FRMF : gd32f10x_enet.h
  • ENET_TDES0_FSG : gd32f10x_enet.h
  • ENET_TDES0_INTC : gd32f10x_enet.h
  • ENET_TDES0_IPHE : gd32f10x_enet.h
  • ENET_TDES0_IPPE : gd32f10x_enet.h
  • ENET_TDES0_JT : gd32f10x_enet.h
  • ENET_TDES0_LCA : gd32f10x_enet.h
  • ENET_TDES0_LCO : gd32f10x_enet.h
  • ENET_TDES0_LSG : gd32f10x_enet.h
  • ENET_TDES0_NCA : gd32f10x_enet.h
  • ENET_TDES0_TCHM : gd32f10x_enet.h
  • ENET_TDES0_TERM : gd32f10x_enet.h
  • ENET_TDES0_TTMSS : gd32f10x_enet.h
  • ENET_TDES0_TTSEN : gd32f10x_enet.h
  • ENET_TDES0_UFE : gd32f10x_enet.h
  • ENET_TDES0_VFRM : gd32f10x_enet.h
  • ENET_TDES1_TB1S : gd32f10x_enet.h
  • ENET_TDES1_TB2S : gd32f10x_enet.h
  • ENET_TDES2_TB1AP : gd32f10x_enet.h
  • ENET_TDES3_TB2AP : gd32f10x_enet.h
  • ENET_TX_FLOWCONTROL : gd32f10x_enet.h
  • ENET_TX_FLOWCONTROL_DISABLE : gd32f10x_enet.h
  • ENET_TX_FLOWCONTROL_ENABLE : gd32f10x_enet.h
  • ENET_TX_MODE_CUTTHROUGH : gd32f10x_enet.h
  • ENET_TX_MODE_STOREFORWARD : gd32f10x_enet.h
  • ENET_TX_STATE_CLOSING : gd32f10x_enet.h
  • ENET_TX_STATE_FETCHING : gd32f10x_enet.h
  • ENET_TX_STATE_READING : gd32f10x_enet.h
  • ENET_TX_STATE_STOPPED : gd32f10x_enet.h
  • ENET_TX_STATE_SUSPENDED : gd32f10x_enet.h
  • ENET_TX_STATE_WAITING : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_128BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_16BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_192BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_24BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_256BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_32BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_40BYTES : gd32f10x_enet.h
  • ENET_TX_THRESHOLD_64BYTES : gd32f10x_enet.h
  • ENET_TXBUF_NUM : gd32f10x_enet.h
  • ENET_TXBUF_SIZE : gd32f10x_enet.h
  • ENET_UNICAST_FILTER_EITHER : gd32f10x_enet.h
  • ENET_UNICAST_FILTER_HASH : gd32f10x_enet.h
  • ENET_UNICAST_FILTER_HASH_MODE : gd32f10x_enet.h
  • ENET_UNICAST_FILTER_PERFECT : gd32f10x_enet.h
  • ENET_UNIQUE_PAUSEDETECT : gd32f10x_enet.h
  • ENET_VLANTAGCOMPARISON_12BIT : gd32f10x_enet.h
  • ENET_VLANTAGCOMPARISON_16BIT : gd32f10x_enet.h
  • ENET_WATCHDOG_DISABLE : gd32f10x_enet.h
  • ENET_WATCHDOG_ENABLE : gd32f10x_enet.h
  • ENET_WUM_FLAG_MPKR : gd32f10x_enet.h
  • ENET_WUM_FLAG_WUFFRPR : gd32f10x_enet.h
  • ENET_WUM_FLAG_WUFR : gd32f10x_enet.h
  • ENET_WUM_GLOBAL_UNICAST : gd32f10x_enet.h
  • ENET_WUM_MAGIC_PACKET_FRAME : gd32f10x_enet.h
  • ENET_WUM_POWER_DOWN : gd32f10x_enet.h
  • ENET_WUM_WAKE_UP_FRAME : gd32f10x_enet.h
  • ENET_ZERO_QUANTA_PAUSE : gd32f10x_enet.h
  • ENET_ZERO_QUANTA_PAUSE_DISABLE : gd32f10x_enet.h
  • ENET_ZERO_QUANTA_PAUSE_ENABLE : gd32f10x_enet.h
  • ENG_LANGID : usbd_std.h
  • ENUM_FSM_ID : usbh_core.h
  • ENUM_HANDLE_TABLE_SIZE : usbh_std.h
  • EP0 : usbd_regs.h
  • EP0_IN : usbd_regs.h , usb_regs.h
  • EP0_OUT : usbd_regs.h , usb_regs.h
  • EP0MPL_16 : usb_regs.h
  • EP0MPL_32 : usb_regs.h
  • EP0MPL_64 : usb_regs.h
  • EP0MPL_8 : usb_regs.h
  • EP1 : usbd_regs.h
  • EP1_IN : usbd_regs.h , usb_regs.h
  • EP1_OUT : usbd_regs.h , usb_regs.h
  • EP2 : usbd_regs.h
  • EP2_IN : usbd_regs.h , usb_regs.h
  • EP2_OUT : usbd_regs.h , usb_regs.h
  • EP3 : usbd_regs.h
  • EP3_IN : usbd_regs.h , usb_regs.h
  • EP3_OUT : usb_regs.h , usbd_regs.h
  • EP4 : usbd_regs.h
  • EP4_IN : usbd_regs.h
  • EP4_OUT : usbd_regs.h
  • EP5 : usbd_regs.h
  • EP5_IN : usbd_regs.h
  • EP5_OUT : usbd_regs.h
  • EP6 : usbd_regs.h
  • EP6_IN : usbd_regs.h
  • EP6_OUT : usbd_regs.h
  • EP7 : usbd_regs.h
  • EP7_IN : usbd_regs.h
  • EP7_OUT : usbd_regs.h
  • EP_BULK : usbd_regs.h
  • EP_CONTROL : usbd_regs.h
  • EP_CTL_MASK : usbd_regs.h
  • EP_INTERRUPT : usbd_regs.h
  • EP_ISO : usbd_regs.h
  • EPCS_MASK : usbd_regs.h
  • EPKCTL_MASK : usbd_regs.h
  • EPRCNT_BLKNUM : usbd_regs.h
  • EPRCNT_BLKSIZ : usbd_regs.h
  • EPRCNT_CNT : usbd_regs.h
  • EPRX_DISABLED : usbd_regs.h
  • EPRX_DTGMASK : usbd_regs.h
  • EPRX_NAK : usbd_regs.h
  • EPRX_STALL : usbd_regs.h
  • EPRX_VALID : usbd_regs.h
  • EPTCNT_CNT : usbd_regs.h
  • EPTX_DISABLED : usbd_regs.h
  • EPTX_DTGMASK : usbd_regs.h
  • EPTX_NAK : usbd_regs.h
  • EPTX_STALL : usbd_regs.h
  • EPTX_VALID : usbd_regs.h
  • EPxCS_ADDR : usbd_regs.h
  • EPxCS_CTL : usbd_regs.h
  • EPxCS_KCTL : usbd_regs.h
  • EPxCS_RX_DTG : usbd_regs.h
  • EPxCS_RX_ST : usbd_regs.h
  • EPxCS_RX_STA : usbd_regs.h
  • EPxCS_SETUP : usbd_regs.h
  • EPxCS_TX_DTG : usbd_regs.h
  • EPxCS_TX_ST : usbd_regs.h
  • EPxCS_TX_STA : usbd_regs.h
  • ERR_ERRN : gd32f10x_can.h
  • ERR_REG_OFFSET : gd32f10x_can.h
  • ETH_DMARXDESC_SIZE : gd32f10x_enet.h
  • ETH_DMATXDESC_SIZE : gd32f10x_enet.h
  • ETH_WAKEUP_REGISTER_LENGTH : gd32f10x_enet.h
  • EXMC : gd32f10x_exmc.h
  • EXMC_ACCESS_MODE_A : gd32f10x_exmc.h
  • EXMC_ACCESS_MODE_B : gd32f10x_exmc.h
  • EXMC_ACCESS_MODE_C : gd32f10x_exmc.h
  • EXMC_ACCESS_MODE_D : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_10_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_11_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_12_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_13_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_14_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_15_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_16_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_1_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_2_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_3_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_4_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_5_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_6_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_7_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_8_HCLK : gd32f10x_exmc.h
  • EXMC_ALE_RE_DELAY_9_HCLK : gd32f10x_exmc.h
  • EXMC_ASYN_WRITE : gd32f10x_exmc.h
  • EXMC_BANK0_NORSRAM_REGION0 : gd32f10x_exmc.h
  • EXMC_BANK0_NORSRAM_REGION1 : gd32f10x_exmc.h
  • EXMC_BANK0_NORSRAM_REGION2 : gd32f10x_exmc.h
  • EXMC_BANK0_NORSRAM_REGION3 : gd32f10x_exmc.h
  • EXMC_BANK1_NAND : gd32f10x_exmc.h
  • EXMC_BANK2_NAND : gd32f10x_exmc.h
  • EXMC_BANK3_PCCARD : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_10_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_11_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_12_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_13_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_14_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_15_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_16_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_1_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_2_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_3_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_4_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_5_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_6_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_7_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_8_HCLK : gd32f10x_exmc.h
  • EXMC_CLE_RE_DELAY_9_HCLK : gd32f10x_exmc.h
  • EXMC_DATALAT_10_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_11_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_12_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_13_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_14_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_15_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_16_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_17_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_2_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_3_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_4_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_5_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_6_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_7_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_8_CLK : gd32f10x_exmc.h
  • EXMC_DATALAT_9_CLK : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_1024BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_2048BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_256BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_4096BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_512BYTES : gd32f10x_exmc.h
  • EXMC_ECC_SIZE_8192BYTES : gd32f10x_exmc.h
  • EXMC_MEMORY_TYPE_NOR : gd32f10x_exmc.h
  • EXMC_MEMORY_TYPE_PSRAM : gd32f10x_exmc.h
  • EXMC_MEMORY_TYPE_SRAM : gd32f10x_exmc.h
  • EXMC_NAND_DATABUS_WIDTH_16B : gd32f10x_exmc.h
  • EXMC_NAND_DATABUS_WIDTH_8B : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_FLAG_FALL : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_FLAG_FIFOE : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_FLAG_LEVEL : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_FLAG_RISE : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_INT_FALL : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_INT_LEVEL : gd32f10x_exmc.h
  • EXMC_NAND_PCCARD_INT_RISE : gd32f10x_exmc.h
  • EXMC_NECC : gd32f10x_exmc.h
  • EXMC_NECC1 : gd32f10x_exmc.h
  • EXMC_NECC2 : gd32f10x_exmc.h
  • EXMC_NECC_ECC : gd32f10x_exmc.h
  • EXMC_NOR_DATABUS_WIDTH_16B : gd32f10x_exmc.h
  • EXMC_NOR_DATABUS_WIDTH_8B : gd32f10x_exmc.h
  • EXMC_NPATCFG : gd32f10x_exmc.h
  • EXMC_NPATCFG1 : gd32f10x_exmc.h
  • EXMC_NPATCFG2 : gd32f10x_exmc.h
  • EXMC_NPATCFG3 : gd32f10x_exmc.h
  • EXMC_NPATCFG_ATTHIZ : gd32f10x_exmc.h
  • EXMC_NPATCFG_ATTHLD : gd32f10x_exmc.h
  • EXMC_NPATCFG_ATTSET : gd32f10x_exmc.h
  • EXMC_NPATCFG_ATTWAIT : gd32f10x_exmc.h
  • EXMC_NPCTCFG : gd32f10x_exmc.h
  • EXMC_NPCTCFG1 : gd32f10x_exmc.h
  • EXMC_NPCTCFG2 : gd32f10x_exmc.h
  • EXMC_NPCTCFG3 : gd32f10x_exmc.h
  • EXMC_NPCTCFG_COMHIZ : gd32f10x_exmc.h
  • EXMC_NPCTCFG_COMHLD : gd32f10x_exmc.h
  • EXMC_NPCTCFG_COMSET : gd32f10x_exmc.h
  • EXMC_NPCTCFG_COMWAIT : gd32f10x_exmc.h
  • EXMC_NPCTL : gd32f10x_exmc.h
  • EXMC_NPCTL1 : gd32f10x_exmc.h
  • EXMC_NPCTL2 : gd32f10x_exmc.h
  • EXMC_NPCTL3 : gd32f10x_exmc.h
  • EXMC_NPCTL_ATR : gd32f10x_exmc.h
  • EXMC_NPCTL_CTR : gd32f10x_exmc.h
  • EXMC_NPCTL_ECCEN : gd32f10x_exmc.h
  • EXMC_NPCTL_ECCSZ : gd32f10x_exmc.h
  • EXMC_NPCTL_NDBKEN : gd32f10x_exmc.h
  • EXMC_NPCTL_NDTP : gd32f10x_exmc.h
  • EXMC_NPCTL_NDW : gd32f10x_exmc.h
  • EXMC_NPCTL_NDWTEN : gd32f10x_exmc.h
  • EXMC_NPINTEN : gd32f10x_exmc.h
  • EXMC_NPINTEN1 : gd32f10x_exmc.h
  • EXMC_NPINTEN2 : gd32f10x_exmc.h
  • EXMC_NPINTEN3 : gd32f10x_exmc.h
  • EXMC_NPINTEN_FFEPT : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTFEN : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTFS : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTHEN : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTHS : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTREN : gd32f10x_exmc.h
  • EXMC_NPINTEN_INTRS : gd32f10x_exmc.h
  • EXMC_NWAIT_CONFIG_BEFORE : gd32f10x_exmc.h
  • EXMC_NWAIT_CONFIG_DURING : gd32f10x_exmc.h
  • EXMC_NWAIT_POLARITY_HIGH : gd32f10x_exmc.h
  • EXMC_NWAIT_POLARITY_LOW : gd32f10x_exmc.h
  • EXMC_PIOTCFG3 : gd32f10x_exmc.h
  • EXMC_PIOTCFG3_IOHIZ : gd32f10x_exmc.h
  • EXMC_PIOTCFG3_IOHLD : gd32f10x_exmc.h
  • EXMC_PIOTCFG3_IOSET : gd32f10x_exmc.h
  • EXMC_PIOTCFG3_IOWAIT : gd32f10x_exmc.h
  • EXMC_SNCTL : gd32f10x_exmc.h
  • EXMC_SNCTL0 : gd32f10x_exmc.h
  • EXMC_SNCTL1 : gd32f10x_exmc.h
  • EXMC_SNCTL2 : gd32f10x_exmc.h
  • EXMC_SNCTL3 : gd32f10x_exmc.h
  • EXMC_SNCTL_ASYNCWAIT : gd32f10x_exmc.h
  • EXMC_SNCTL_EXMODEN : gd32f10x_exmc.h
  • EXMC_SNCTL_NRBKEN : gd32f10x_exmc.h
  • EXMC_SNCTL_NREN : gd32f10x_exmc.h
  • EXMC_SNCTL_NRMUX : gd32f10x_exmc.h
  • EXMC_SNCTL_NRTP : gd32f10x_exmc.h
  • EXMC_SNCTL_NRW : gd32f10x_exmc.h
  • EXMC_SNCTL_NRWTCFG : gd32f10x_exmc.h
  • EXMC_SNCTL_NRWTEN : gd32f10x_exmc.h
  • EXMC_SNCTL_NRWTPOL : gd32f10x_exmc.h
  • EXMC_SNCTL_SBRSTEN : gd32f10x_exmc.h
  • EXMC_SNCTL_SYNCWR : gd32f10x_exmc.h
  • EXMC_SNCTL_WRAPEN : gd32f10x_exmc.h
  • EXMC_SNCTL_WREN : gd32f10x_exmc.h
  • EXMC_SNTCFG : gd32f10x_exmc.h
  • EXMC_SNTCFG0 : gd32f10x_exmc.h
  • EXMC_SNTCFG1 : gd32f10x_exmc.h
  • EXMC_SNTCFG2 : gd32f10x_exmc.h
  • EXMC_SNTCFG3 : gd32f10x_exmc.h
  • EXMC_SNTCFG_AHLD : gd32f10x_exmc.h
  • EXMC_SNTCFG_ASET : gd32f10x_exmc.h
  • EXMC_SNTCFG_ASYNCMOD : gd32f10x_exmc.h
  • EXMC_SNTCFG_BUSLAT : gd32f10x_exmc.h
  • EXMC_SNTCFG_CKDIV : gd32f10x_exmc.h
  • EXMC_SNTCFG_DLAT : gd32f10x_exmc.h
  • EXMC_SNTCFG_DSET : gd32f10x_exmc.h
  • EXMC_SNWTCFG : gd32f10x_exmc.h
  • EXMC_SNWTCFG0 : gd32f10x_exmc.h
  • EXMC_SNWTCFG1 : gd32f10x_exmc.h
  • EXMC_SNWTCFG2 : gd32f10x_exmc.h
  • EXMC_SNWTCFG3 : gd32f10x_exmc.h
  • EXMC_SNWTCFG_CKDIV : gd32f10x_exmc.h
  • EXMC_SNWTCFG_DLAT : gd32f10x_exmc.h
  • EXMC_SNWTCFG_WAHLD : gd32f10x_exmc.h
  • EXMC_SNWTCFG_WASET : gd32f10x_exmc.h
  • EXMC_SNWTCFG_WASYNCMOD : gd32f10x_exmc.h
  • EXMC_SNWTCFG_WDSET : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_10_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_11_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_12_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_13_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_14_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_15_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_16_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_2_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_3_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_4_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_5_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_6_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_7_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_8_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_9_CLK : gd32f10x_exmc.h
  • EXMC_SYN_CLOCK_RATIO_DISABLE : gd32f10x_exmc.h
  • EXMC_SYN_WRITE : gd32f10x_exmc.h
  • EXTI : gd32f10x_exti.h
  • EXTI_EVEN : gd32f10x_exti.h
  • EXTI_EVEN_EVEN0 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN1 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN10 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN11 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN12 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN13 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN14 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN15 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN16 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN17 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN18 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN19 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN2 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN3 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN4 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN5 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN6 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN7 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN8 : gd32f10x_exti.h
  • EXTI_EVEN_EVEN9 : gd32f10x_exti.h
  • EXTI_FTEN : gd32f10x_exti.h
  • EXTI_FTEN_FTEN0 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN1 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN10 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN11 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN12 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN13 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN14 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN15 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN16 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN17 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN18 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN19 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN2 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN3 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN4 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN5 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN6 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN7 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN8 : gd32f10x_exti.h
  • EXTI_FTEN_FTEN9 : gd32f10x_exti.h
  • EXTI_INTEN : gd32f10x_exti.h
  • EXTI_INTEN_INTEN0 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN1 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN10 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN11 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN12 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN13 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN14 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN15 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN16 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN17 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN18 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN19 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN2 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN3 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN4 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN5 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN6 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN7 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN8 : gd32f10x_exti.h
  • EXTI_INTEN_INTEN9 : gd32f10x_exti.h
  • EXTI_PD : gd32f10x_exti.h
  • EXTI_PD_PD0 : gd32f10x_exti.h
  • EXTI_PD_PD1 : gd32f10x_exti.h
  • EXTI_PD_PD10 : gd32f10x_exti.h
  • EXTI_PD_PD11 : gd32f10x_exti.h
  • EXTI_PD_PD12 : gd32f10x_exti.h
  • EXTI_PD_PD13 : gd32f10x_exti.h
  • EXTI_PD_PD14 : gd32f10x_exti.h
  • EXTI_PD_PD15 : gd32f10x_exti.h
  • EXTI_PD_PD16 : gd32f10x_exti.h
  • EXTI_PD_PD17 : gd32f10x_exti.h
  • EXTI_PD_PD18 : gd32f10x_exti.h
  • EXTI_PD_PD19 : gd32f10x_exti.h
  • EXTI_PD_PD2 : gd32f10x_exti.h
  • EXTI_PD_PD3 : gd32f10x_exti.h
  • EXTI_PD_PD4 : gd32f10x_exti.h
  • EXTI_PD_PD5 : gd32f10x_exti.h
  • EXTI_PD_PD6 : gd32f10x_exti.h
  • EXTI_PD_PD7 : gd32f10x_exti.h
  • EXTI_PD_PD8 : gd32f10x_exti.h
  • EXTI_PD_PD9 : gd32f10x_exti.h
  • EXTI_RTEN : gd32f10x_exti.h
  • EXTI_RTEN_RTEN0 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN1 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN10 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN11 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN12 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN13 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN14 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN15 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN16 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN17 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN18 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN19 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN2 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN3 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN4 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN5 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN6 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN7 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN8 : gd32f10x_exti.h
  • EXTI_RTEN_RTEN9 : gd32f10x_exti.h
  • EXTI_SWIEV : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV0 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV1 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV10 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV11 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV12 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV13 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV14 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV15 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV16 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV17 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV18 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV19 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV2 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV3 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV4 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV5 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV6 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV7 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV8 : gd32f10x_exti.h
  • EXTI_SWIEV_SWIEV9 : gd32f10x_exti.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • w

- f -

  • FCTL_HBC1F : gd32f10x_can.h
  • FDATA_MASK_HIGH : gd32f10x_can.h
  • FDATA_MASK_LOW : gd32f10x_can.h
  • FEATURE_SELECTOR_DEVICE : usbh_std.h
  • FEATURE_SELECTOR_ENDPOINT : usbh_std.h
  • FMC : gd32f10x_fmc.h
  • FMC_ADDR0 : gd32f10x_fmc.h
  • FMC_ADDR0_ADDR : gd32f10x_fmc.h
  • FMC_ADDR1 : gd32f10x_fmc.h
  • FMC_ADDR1_ADDR : gd32f10x_fmc.h
  • FMC_BANK0_END_ADDRESS : gd32f10x_fmc.h
  • FMC_BANK0_SIZE : gd32f10x_fmc.h
  • FMC_BIT_POS : gd32f10x_fmc.h
  • FMC_BIT_POS0 : gd32f10x_fmc.h
  • FMC_BIT_POS1 : gd32f10x_fmc.h
  • FMC_CTL0 : gd32f10x_fmc.h
  • FMC_CTL0_ENDIE : gd32f10x_fmc.h
  • FMC_CTL0_ERRIE : gd32f10x_fmc.h
  • FMC_CTL0_LK : gd32f10x_fmc.h
  • FMC_CTL0_MER : gd32f10x_fmc.h
  • FMC_CTL0_OBER : gd32f10x_fmc.h
  • FMC_CTL0_OBPG : gd32f10x_fmc.h
  • FMC_CTL0_OBWEN : gd32f10x_fmc.h
  • FMC_CTL0_PER : gd32f10x_fmc.h
  • FMC_CTL0_PG : gd32f10x_fmc.h
  • FMC_CTL0_REG_OFFSET : gd32f10x_fmc.h
  • FMC_CTL0_START : gd32f10x_fmc.h
  • FMC_CTL1 : gd32f10x_fmc.h
  • FMC_CTL1_ENDIE : gd32f10x_fmc.h
  • FMC_CTL1_ERRIE : gd32f10x_fmc.h
  • FMC_CTL1_LK : gd32f10x_fmc.h
  • FMC_CTL1_MER : gd32f10x_fmc.h
  • FMC_CTL1_PER : gd32f10x_fmc.h
  • FMC_CTL1_PG : gd32f10x_fmc.h
  • FMC_CTL1_REG_OFFSET : gd32f10x_fmc.h
  • FMC_CTL1_START : gd32f10x_fmc.h
  • FMC_KEY0 : gd32f10x_fmc.h
  • FMC_KEY0_KEY : gd32f10x_fmc.h
  • FMC_KEY1 : gd32f10x_fmc.h
  • FMC_KEY1_KEY : gd32f10x_fmc.h
  • FMC_NSPC : gd32f10x_fmc.h
  • FMC_OBKEY : gd32f10x_fmc.h
  • FMC_OBKEY_OBKEY : gd32f10x_fmc.h
  • FMC_OBSTAT : gd32f10x_fmc.h
  • FMC_OBSTAT_DATA : gd32f10x_fmc.h
  • FMC_OBSTAT_OBERR : gd32f10x_fmc.h
  • FMC_OBSTAT_REG_OFFSET : gd32f10x_fmc.h
  • FMC_OBSTAT_SPC : gd32f10x_fmc.h
  • FMC_OBSTAT_USER : gd32f10x_fmc.h
  • FMC_PID : gd32f10x_fmc.h
  • FMC_PID_PID : gd32f10x_fmc.h
  • FMC_REG_OFFSET_GET : gd32f10x_fmc.h
  • FMC_REG_VAL : gd32f10x_fmc.h
  • FMC_REG_VALS : gd32f10x_fmc.h
  • FMC_REGIDX_BIT : gd32f10x_fmc.h
  • FMC_REGIDX_BITS : gd32f10x_fmc.h
  • FMC_SIZE : gd32f10x_fmc.h
  • FMC_STAT0 : gd32f10x_fmc.h
  • FMC_STAT0_BUSY : gd32f10x_fmc.h
  • FMC_STAT0_ENDF : gd32f10x_fmc.h
  • FMC_STAT0_PGERR : gd32f10x_fmc.h
  • FMC_STAT0_REG_OFFSET : gd32f10x_fmc.h
  • FMC_STAT0_WPERR : gd32f10x_fmc.h
  • FMC_STAT1 : gd32f10x_fmc.h
  • FMC_STAT1_BUSY : gd32f10x_fmc.h
  • FMC_STAT1_ENDF : gd32f10x_fmc.h
  • FMC_STAT1_PGERR : gd32f10x_fmc.h
  • FMC_STAT1_REG_OFFSET : gd32f10x_fmc.h
  • FMC_STAT1_WPERR : gd32f10x_fmc.h
  • FMC_TIMEOUT_COUNT : gd32f10x_fmc.h
  • FMC_USPC : gd32f10x_fmc.h
  • FMC_WP : gd32f10x_fmc.h
  • FMC_WP_WP : gd32f10x_fmc.h
  • FMC_WS : gd32f10x_fmc.h
  • FMC_WS_WSCNT : gd32f10x_fmc.h
  • FMC_WSEN : gd32f10x_fmc.h
  • FMC_WSEN_WSEN : gd32f10x_fmc.h
  • FRAME_INTERVAL_80 : usb_regs.h
  • FRAME_INTERVAL_85 : usb_regs.h
  • FRAME_INTERVAL_90 : usb_regs.h
  • FRAME_INTERVAL_95 : usb_regs.h
  • FWDGT : gd32f10x_fwdgt.h
  • FWDGT_CTL : gd32f10x_fwdgt.h
  • FWDGT_CTL_CMD : gd32f10x_fwdgt.h
  • FWDGT_FLAG_PUD : gd32f10x_fwdgt.h
  • FWDGT_FLAG_RUD : gd32f10x_fwdgt.h
  • FWDGT_KEY_ENABLE : gd32f10x_fwdgt.h
  • FWDGT_KEY_RELOAD : gd32f10x_fwdgt.h
  • FWDGT_PSC : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV128 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV16 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV256 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV32 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV4 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV64 : gd32f10x_fwdgt.h
  • FWDGT_PSC_DIV8 : gd32f10x_fwdgt.h
  • FWDGT_PSC_PSC : gd32f10x_fwdgt.h
  • FWDGT_PSC_TIMEOUT : gd32f10x_fwdgt.h
  • FWDGT_RLD : gd32f10x_fwdgt.h
  • FWDGT_RLD_RLD : gd32f10x_fwdgt.h
  • FWDGT_RLD_TIMEOUT : gd32f10x_fwdgt.h
  • FWDGT_STAT : gd32f10x_fwdgt.h
  • FWDGT_STAT_PUD : gd32f10x_fwdgt.h
  • FWDGT_STAT_RUD : gd32f10x_fwdgt.h
  • FWDGT_WRITEACCESS_DISABLE : gd32f10x_fwdgt.h
  • FWDGT_WRITEACCESS_ENABLE : gd32f10x_fwdgt.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • w

- g -

  • GAHBCS_DMAINCR : usb_regs.h
  • GAHBCS_GINTEN : usb_regs.h
  • GAHBCS_PTXFTH : usb_regs.h
  • GAHBCS_TFEL : usb_regs.h
  • GAHBCS_TXFTH : usb_regs.h
  • GCCFG_PWRON : usb_regs.h
  • GCCFG_SOFOEN : usb_regs.h
  • GCCFG_VBUSACEN : usb_regs.h
  • GCCFG_VBUSBCEN : usb_regs.h
  • GCCFG_VBUSIG : usb_regs.h
  • GET_DMA_BCTL_DPSL : gd32f10x_enet.h
  • GET_DMA_MFBOCNT_MSFA : gd32f10x_enet.h
  • GET_DMA_MFBOCNT_MSFC : gd32f10x_enet.h
  • GET_DMA_STAT_EB : gd32f10x_enet.h
  • GET_DMA_STAT_RP : gd32f10x_enet.h
  • GET_DMA_STAT_TP : gd32f10x_enet.h
  • GET_PTP_TSL_STMSS : gd32f10x_enet.h
  • GET_PTP_TSL_STS : gd32f10x_enet.h
  • GET_RDES0_FRML : gd32f10x_enet.h
  • GET_RDES1_RB1S : gd32f10x_enet.h
  • GET_RDES1_RB2S : gd32f10x_enet.h
  • GET_RDES4_IPPLDT : gd32f10x_enet.h
  • GET_RDES4_PTPMT : gd32f10x_enet.h
  • GET_TDES0_COCNT : gd32f10x_enet.h
  • GINTEN_DISCIE : usb_regs.h
  • GINTEN_ENUMFIE : usb_regs.h
  • GINTEN_EOPFIE : usb_regs.h
  • GINTEN_ESPIE : usb_regs.h
  • GINTEN_GNPINAKIE : usb_regs.h
  • GINTEN_GONAKIE : usb_regs.h
  • GINTEN_HCIE : usb_regs.h
  • GINTEN_HPIE : usb_regs.h
  • GINTEN_IDPSCIE : usb_regs.h
  • GINTEN_IEPIE : usb_regs.h
  • GINTEN_ISOINCIE : usb_regs.h
  • GINTEN_ISOONCIE : usb_regs.h
  • GINTEN_ISOOPDIE : usb_regs.h
  • GINTEN_MFIE : usb_regs.h
  • GINTEN_NPTXFEIE : usb_regs.h
  • GINTEN_OEPIE : usb_regs.h
  • GINTEN_OTGIE : usb_regs.h
  • GINTEN_PTXFEIE : usb_regs.h
  • GINTEN_PXNCIE : usb_regs.h
  • GINTEN_RSTIE : usb_regs.h
  • GINTEN_RXFNEIE : usb_regs.h
  • GINTEN_SESIE : usb_regs.h
  • GINTEN_SOFIE : usb_regs.h
  • GINTEN_SPIE : usb_regs.h
  • GINTEN_WKUPIE : usb_regs.h
  • GINTF_COPM : usb_regs.h
  • GINTF_DISCIF : usb_regs.h
  • GINTF_ENUMF : usb_regs.h
  • GINTF_EOPFIF : usb_regs.h
  • GINTF_ESP : usb_regs.h
  • GINTF_GNPINAK : usb_regs.h
  • GINTF_GONAK : usb_regs.h
  • GINTF_HCIF : usb_regs.h
  • GINTF_HPIF : usb_regs.h
  • GINTF_IDPSC : usb_regs.h
  • GINTF_IEPIF : usb_regs.h
  • GINTF_ISOINCIF : usb_regs.h
  • GINTF_ISOONCIF : usb_regs.h
  • GINTF_ISOOPDIF : usb_regs.h
  • GINTF_MFIF : usb_regs.h
  • GINTF_NPTXFEIF : usb_regs.h
  • GINTF_OEPIF : usb_regs.h
  • GINTF_OTGIF : usb_regs.h
  • GINTF_PTXFEIF : usb_regs.h
  • GINTF_PXNCIF : usb_regs.h
  • GINTF_RST : usb_regs.h
  • GINTF_RXFNEIF : usb_regs.h
  • GINTF_SESIF : usb_regs.h
  • GINTF_SOF : usb_regs.h
  • GINTF_SP : usb_regs.h
  • GINTF_WKUPIF : usb_regs.h
  • GO_TO_UP_STATE_EVENT : usbh_core.h
  • GOTGCS_ASV : usb_regs.h
  • GOTGCS_BSV : usb_regs.h
  • GOTGCS_DHNPEN : usb_regs.h
  • GOTGCS_DI : usb_regs.h
  • GOTGCS_HHNPEN : usb_regs.h
  • GOTGCS_HNPREQ : usb_regs.h
  • GOTGCS_HNPS : usb_regs.h
  • GOTGCS_IDPS : usb_regs.h
  • GOTGCS_SRPREQ : usb_regs.h
  • GOTGCS_SRPS : usb_regs.h
  • GOTGINTF_ADTO : usb_regs.h
  • GOTGINTF_DF : usb_regs.h
  • GOTGINTF_HNPDET : usb_regs.h
  • GOTGINTF_HNPEND : usb_regs.h
  • GOTGINTF_SESEND : usb_regs.h
  • GOTGINTF_SRPEND : usb_regs.h
  • GPIO_ADC0_ETRGINS_REMAP : gd32f10x_gpio.h
  • GPIO_ADC0_ETRGREG_REMAP : gd32f10x_gpio.h
  • GPIO_ADC1_ETRGINS_REMAP : gd32f10x_gpio.h
  • GPIO_ADC1_ETRGREG_REMAP : gd32f10x_gpio.h
  • GPIO_BC : gd32f10x_gpio.h
  • GPIO_BC_CR0 : gd32f10x_gpio.h
  • GPIO_BC_CR1 : gd32f10x_gpio.h
  • GPIO_BC_CR10 : gd32f10x_gpio.h
  • GPIO_BC_CR11 : gd32f10x_gpio.h
  • GPIO_BC_CR12 : gd32f10x_gpio.h
  • GPIO_BC_CR13 : gd32f10x_gpio.h
  • GPIO_BC_CR14 : gd32f10x_gpio.h
  • GPIO_BC_CR15 : gd32f10x_gpio.h
  • GPIO_BC_CR2 : gd32f10x_gpio.h
  • GPIO_BC_CR3 : gd32f10x_gpio.h
  • GPIO_BC_CR4 : gd32f10x_gpio.h
  • GPIO_BC_CR5 : gd32f10x_gpio.h
  • GPIO_BC_CR6 : gd32f10x_gpio.h
  • GPIO_BC_CR7 : gd32f10x_gpio.h
  • GPIO_BC_CR8 : gd32f10x_gpio.h
  • GPIO_BC_CR9 : gd32f10x_gpio.h
  • GPIO_BOP : gd32f10x_gpio.h
  • GPIO_BOP_BOP0 : gd32f10x_gpio.h
  • GPIO_BOP_BOP1 : gd32f10x_gpio.h
  • GPIO_BOP_BOP10 : gd32f10x_gpio.h
  • GPIO_BOP_BOP11 : gd32f10x_gpio.h
  • GPIO_BOP_BOP12 : gd32f10x_gpio.h
  • GPIO_BOP_BOP13 : gd32f10x_gpio.h
  • GPIO_BOP_BOP14 : gd32f10x_gpio.h
  • GPIO_BOP_BOP15 : gd32f10x_gpio.h
  • GPIO_BOP_BOP2 : gd32f10x_gpio.h
  • GPIO_BOP_BOP3 : gd32f10x_gpio.h
  • GPIO_BOP_BOP4 : gd32f10x_gpio.h
  • GPIO_BOP_BOP5 : gd32f10x_gpio.h
  • GPIO_BOP_BOP6 : gd32f10x_gpio.h
  • GPIO_BOP_BOP7 : gd32f10x_gpio.h
  • GPIO_BOP_BOP8 : gd32f10x_gpio.h
  • GPIO_BOP_BOP9 : gd32f10x_gpio.h
  • GPIO_BOP_CR0 : gd32f10x_gpio.h
  • GPIO_BOP_CR1 : gd32f10x_gpio.h
  • GPIO_BOP_CR10 : gd32f10x_gpio.h
  • GPIO_BOP_CR11 : gd32f10x_gpio.h
  • GPIO_BOP_CR12 : gd32f10x_gpio.h
  • GPIO_BOP_CR13 : gd32f10x_gpio.h
  • GPIO_BOP_CR14 : gd32f10x_gpio.h
  • GPIO_BOP_CR15 : gd32f10x_gpio.h
  • GPIO_BOP_CR2 : gd32f10x_gpio.h
  • GPIO_BOP_CR3 : gd32f10x_gpio.h
  • GPIO_BOP_CR4 : gd32f10x_gpio.h
  • GPIO_BOP_CR5 : gd32f10x_gpio.h
  • GPIO_BOP_CR6 : gd32f10x_gpio.h
  • GPIO_BOP_CR7 : gd32f10x_gpio.h
  • GPIO_BOP_CR8 : gd32f10x_gpio.h
  • GPIO_BOP_CR9 : gd32f10x_gpio.h
  • GPIO_CAN0_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_CAN0_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIO_CAN1_REMAP : gd32f10x_gpio.h
  • GPIO_CAN_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_CAN_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIO_CTL0 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL0 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL1 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL2 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL3 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL4 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL5 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL6 : gd32f10x_gpio.h
  • GPIO_CTL0_CTL7 : gd32f10x_gpio.h
  • GPIO_CTL0_MD0 : gd32f10x_gpio.h
  • GPIO_CTL0_MD1 : gd32f10x_gpio.h
  • GPIO_CTL0_MD2 : gd32f10x_gpio.h
  • GPIO_CTL0_MD3 : gd32f10x_gpio.h
  • GPIO_CTL0_MD4 : gd32f10x_gpio.h
  • GPIO_CTL0_MD5 : gd32f10x_gpio.h
  • GPIO_CTL0_MD6 : gd32f10x_gpio.h
  • GPIO_CTL0_MD7 : gd32f10x_gpio.h
  • GPIO_CTL1 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL10 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL11 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL12 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL13 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL14 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL15 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL8 : gd32f10x_gpio.h
  • GPIO_CTL1_CTL9 : gd32f10x_gpio.h
  • GPIO_CTL1_MD10 : gd32f10x_gpio.h
  • GPIO_CTL1_MD11 : gd32f10x_gpio.h
  • GPIO_CTL1_MD12 : gd32f10x_gpio.h
  • GPIO_CTL1_MD13 : gd32f10x_gpio.h
  • GPIO_CTL1_MD14 : gd32f10x_gpio.h
  • GPIO_CTL1_MD15 : gd32f10x_gpio.h
  • GPIO_CTL1_MD8 : gd32f10x_gpio.h
  • GPIO_CTL1_MD9 : gd32f10x_gpio.h
  • GPIO_ENET_PHY_MII : gd32f10x_gpio.h
  • GPIO_ENET_PHY_RMII : gd32f10x_gpio.h
  • GPIO_ENET_REMAP : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_0 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_1 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_10 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_11 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_12 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_13 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_14 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_15 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_2 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_3 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_4 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_5 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_6 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_7 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_8 : gd32f10x_gpio.h
  • GPIO_EVENT_PIN_9 : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOA : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOB : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOC : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOD : gd32f10x_gpio.h
  • GPIO_EVENT_PORT_GPIOE : gd32f10x_gpio.h
  • GPIO_FSMC_NADV_REMAP : gd32f10x_gpio.h
  • GPIO_I2C0_REMAP : gd32f10x_gpio.h
  • GPIO_ISTAT : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT0 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT1 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT10 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT11 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT12 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT13 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT14 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT15 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT2 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT3 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT4 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT5 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT6 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT7 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT8 : gd32f10x_gpio.h
  • GPIO_ISTAT_ISTAT9 : gd32f10x_gpio.h
  • GPIO_LOCK : gd32f10x_gpio.h
  • GPIO_LOCK_LK0 : gd32f10x_gpio.h
  • GPIO_LOCK_LK1 : gd32f10x_gpio.h
  • GPIO_LOCK_LK10 : gd32f10x_gpio.h
  • GPIO_LOCK_LK11 : gd32f10x_gpio.h
  • GPIO_LOCK_LK12 : gd32f10x_gpio.h
  • GPIO_LOCK_LK13 : gd32f10x_gpio.h
  • GPIO_LOCK_LK14 : gd32f10x_gpio.h
  • GPIO_LOCK_LK15 : gd32f10x_gpio.h
  • GPIO_LOCK_LK2 : gd32f10x_gpio.h
  • GPIO_LOCK_LK3 : gd32f10x_gpio.h
  • GPIO_LOCK_LK4 : gd32f10x_gpio.h
  • GPIO_LOCK_LK5 : gd32f10x_gpio.h
  • GPIO_LOCK_LK6 : gd32f10x_gpio.h
  • GPIO_LOCK_LK7 : gd32f10x_gpio.h
  • GPIO_LOCK_LK8 : gd32f10x_gpio.h
  • GPIO_LOCK_LK9 : gd32f10x_gpio.h
  • GPIO_LOCK_LKK : gd32f10x_gpio.h
  • GPIO_MODE_AF_OD : gd32f10x_gpio.h
  • GPIO_MODE_AF_PP : gd32f10x_gpio.h
  • GPIO_MODE_AIN : gd32f10x_gpio.h
  • GPIO_MODE_IN_FLOATING : gd32f10x_gpio.h
  • GPIO_MODE_IPD : gd32f10x_gpio.h
  • GPIO_MODE_IPU : gd32f10x_gpio.h
  • GPIO_MODE_MASK : gd32f10x_gpio.h
  • GPIO_MODE_OUT_OD : gd32f10x_gpio.h
  • GPIO_MODE_OUT_PP : gd32f10x_gpio.h
  • GPIO_MODE_SET : gd32f10x_gpio.h
  • GPIO_OCTL : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL0 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL1 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL10 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL11 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL12 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL13 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL14 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL15 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL2 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL3 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL4 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL5 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL6 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL7 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL8 : gd32f10x_gpio.h
  • GPIO_OCTL_OCTL9 : gd32f10x_gpio.h
  • GPIO_OSPEED_10MHZ : gd32f10x_gpio.h
  • GPIO_OSPEED_2MHZ : gd32f10x_gpio.h
  • GPIO_OSPEED_50MHZ : gd32f10x_gpio.h
  • GPIO_PD01_REMAP : gd32f10x_gpio.h
  • GPIO_PIN_0 : gd32f10x_gpio.h
  • GPIO_PIN_1 : gd32f10x_gpio.h
  • GPIO_PIN_10 : gd32f10x_gpio.h
  • GPIO_PIN_11 : gd32f10x_gpio.h
  • GPIO_PIN_12 : gd32f10x_gpio.h
  • GPIO_PIN_13 : gd32f10x_gpio.h
  • GPIO_PIN_14 : gd32f10x_gpio.h
  • GPIO_PIN_15 : gd32f10x_gpio.h
  • GPIO_PIN_2 : gd32f10x_gpio.h
  • GPIO_PIN_3 : gd32f10x_gpio.h
  • GPIO_PIN_4 : gd32f10x_gpio.h
  • GPIO_PIN_5 : gd32f10x_gpio.h
  • GPIO_PIN_6 : gd32f10x_gpio.h
  • GPIO_PIN_7 : gd32f10x_gpio.h
  • GPIO_PIN_8 : gd32f10x_gpio.h
  • GPIO_PIN_9 : gd32f10x_gpio.h
  • GPIO_PIN_ALL : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_0 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_1 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_10 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_11 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_12 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_13 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_14 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_15 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_2 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_3 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_4 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_5 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_6 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_7 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_8 : gd32f10x_gpio.h
  • GPIO_PIN_SOURCE_9 : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOA : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOB : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOC : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOD : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOE : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOF : gd32f10x_gpio.h
  • GPIO_PORT_SOURCE_GPIOG : gd32f10x_gpio.h
  • GPIO_PTP_PPS_REMAP : gd32f10x_gpio.h
  • GPIO_SPI0_REMAP : gd32f10x_gpio.h
  • GPIO_SPI2_REMAP : gd32f10x_gpio.h
  • GPIO_SWJ_DISABLE_REMAP : gd32f10x_gpio.h
  • GPIO_SWJ_NONJTRST_REMAP : gd32f10x_gpio.h
  • GPIO_SWJ_SWDPENABLE_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER0_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER0_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER10_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER12_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER13_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER1_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER1_PARTIAL_REMAP0 : gd32f10x_gpio.h
  • GPIO_TIMER1_PARTIAL_REMAP1 : gd32f10x_gpio.h
  • GPIO_TIMER1ITR0_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER2_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER2_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER3_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER4CH3_IREMAP : gd32f10x_gpio.h
  • GPIO_TIMER8_REMAP : gd32f10x_gpio.h
  • GPIO_TIMER9_REMAP : gd32f10x_gpio.h
  • GPIO_USART0_REMAP : gd32f10x_gpio.h
  • GPIO_USART1_REMAP : gd32f10x_gpio.h
  • GPIO_USART2_FULL_REMAP : gd32f10x_gpio.h
  • GPIO_USART2_PARTIAL_REMAP : gd32f10x_gpio.h
  • GPIOA : gd32f10x_gpio.h
  • GPIOB : gd32f10x_gpio.h
  • GPIOC : gd32f10x_gpio.h
  • GPIOD : gd32f10x_gpio.h
  • GPIOE : gd32f10x_gpio.h
  • GPIOF : gd32f10x_gpio.h
  • GPIOG : gd32f10x_gpio.h
  • GRFLEN_RXFD : usb_regs.h
  • GRSTATR_RPCKST_CH_HALTED : usb_defines.h
  • GRSTATR_RPCKST_DATA_TOGGLE_ERR : usb_defines.h
  • GRSTATR_RPCKST_IN : usb_defines.h
  • GRSTATR_RPCKST_IN_XFER_COMP : usb_defines.h
  • GRSTATRP_BCOUNT : usb_regs.h
  • GRSTATRP_CNUM : usb_regs.h
  • GRSTATRP_DPID : usb_regs.h
  • GRSTATRP_EPNUM : usb_regs.h
  • GRSTATRP_RPCKST : usb_regs.h
  • GRSTCTL_CSRST : usb_regs.h
  • GRSTCTL_HCSRST : usb_regs.h
  • GRSTCTL_HFCRST : usb_regs.h
  • GRSTCTL_RXFF : usb_regs.h
  • GRSTCTL_TXFF : usb_regs.h
  • GRSTCTL_TXFNUM : usb_regs.h
  • GUSBCS_FDM : usb_regs.h
  • GUSBCS_FHM : usb_regs.h
  • GUSBCS_HNPCEN : usb_regs.h
  • GUSBCS_SRPCEN : usb_regs.h
  • GUSBCS_TOC : usb_regs.h
  • GUSBCS_UTT : usb_regs.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
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- h -

  • HACHINT_HACHINT : usb_regs.h
  • HACHINTEN_CINTEN : usb_regs.h
  • HC_ERROR : usbh_hcs.h
  • HC_MAX : usbh_hcs.h
  • HC_MAX_PACKET_COUNT : usb_core.h
  • HC_OK : usbh_hcs.h
  • HC_PID_DATA0 : usb_defines.h
  • HC_PID_DATA1 : usb_defines.h
  • HC_PID_DATA2 : usb_defines.h
  • HC_PID_SETUP : usb_defines.h
  • HC_USED : usbh_hcs.h
  • HC_USED_MASK : usbh_hcs.h
  • HCCHAR_BULK : usb_defines.h
  • HCCHAR_CTRL : usb_defines.h
  • HCCHAR_INTR : usb_defines.h
  • HCCHAR_ISOC : usb_defines.h
  • HCHCTL_CDIS : usb_regs.h
  • HCHCTL_CEN : usb_regs.h
  • HCHCTL_DAR : usb_regs.h
  • HCHCTL_EPDIR : usb_regs.h
  • HCHCTL_EPNUM : usb_regs.h
  • HCHCTL_EPTYPE : usb_regs.h
  • HCHCTL_LSD : usb_regs.h
  • HCHCTL_MPC : usb_regs.h
  • HCHCTL_MPL : usb_regs.h
  • HCHCTL_ODDFRM : usb_regs.h
  • HCHINTEN_ACKIE : usb_regs.h
  • HCHINTEN_BBERIE : usb_regs.h
  • HCHINTEN_CHIE : usb_regs.h
  • HCHINTEN_DTERIE : usb_regs.h
  • HCHINTEN_NAKIE : usb_regs.h
  • HCHINTEN_NYETIE : usb_regs.h
  • HCHINTEN_REQOVRIE : usb_regs.h
  • HCHINTEN_STALLIE : usb_regs.h
  • HCHINTEN_TFIE : usb_regs.h
  • HCHINTEN_USBERIE : usb_regs.h
  • HCHINTF_ACK : usb_regs.h
  • HCHINTF_BBER : usb_regs.h
  • HCHINTF_CH : usb_regs.h
  • HCHINTF_DTER : usb_regs.h
  • HCHINTF_NAK : usb_regs.h
  • HCHINTF_NYET : usb_regs.h
  • HCHINTF_REQOVR : usb_regs.h
  • HCHINTF_STALL : usb_regs.h
  • HCHINTF_TF : usb_regs.h
  • HCHINTF_USBER : usb_regs.h
  • HCHLEN_DPID : usb_regs.h
  • HCHLEN_PCNT : usb_regs.h
  • HCHLEN_TLEN : usb_regs.h
  • HCTL_CLKSEL : usb_regs.h
  • HCTLR_30_60_MHZ : usb_defines.h
  • HCTLR_48_MHZ : usb_defines.h
  • HCTLR_6_MHZ : usb_defines.h
  • HFINFR_FRNUM : usb_regs.h
  • HFINFR_FRT : usb_regs.h
  • HFT_FRI : usb_regs.h
  • HID_BOOT_CODE : usb_std.h
  • HID_CLASS : usbh_core.h
  • HID_KEYBRD_BOOT_CODE : usb_std.h
  • HID_MOUSE_BOOT_CODE : usb_std.h
  • HIGHBYTE : usbd_std.h
  • HNPTFLEN_HNPTXFD : usb_regs.h
  • HNPTFLEN_HNPTXRSAR : usb_regs.h
  • HNPTFQSTAT_CNUM : usb_regs.h
  • HNPTFQSTAT_EPNUM : usb_regs.h
  • HNPTFQSTAT_NPTXFS : usb_regs.h
  • HNPTFQSTAT_NPTXRQS : usb_regs.h
  • HNPTFQSTAT_NPTXRQTOP : usb_regs.h
  • HNPTFQSTAT_TMF : usb_regs.h
  • HNPTFQSTAT_TYPE : usb_regs.h
  • HOST_FSM_ID : usbh_core.h
  • HOST_HANDLE_TABLE_SIZE : usbh_core.h
  • HOST_MODE : usb_defines.h
  • HOST_USER_CLASS_ACTIVE : usbh_core.h
  • HOST_USER_CLASS_SELECTED : usbh_core.h
  • HOST_USER_CONNECTION : usbh_core.h
  • HOST_USER_DISCONNECTION : usbh_core.h
  • HOST_USER_SELECT_CONFIGURATION : usbh_core.h
  • HOST_USER_UNRECOVERED_ERROR : usbh_core.h
  • HPCS_PCD : usb_regs.h
  • HPCS_PCST : usb_regs.h
  • HPCS_PE : usb_regs.h
  • HPCS_PEDC : usb_regs.h
  • HPCS_PLST : usb_regs.h
  • HPCS_PP : usb_regs.h
  • HPCS_PREM : usb_regs.h
  • HPCS_PRST : usb_regs.h
  • HPCS_PS : usb_regs.h
  • HPCS_PSP : usb_regs.h
  • HPRT_PRTSPD_FULL_SPEED : usb_defines.h
  • HPRT_PRTSPD_HIGH_SPEED : usb_defines.h
  • HPRT_PRTSPD_LOW_SPEED : usb_defines.h
  • HPTFLEN_HPTXFD : usb_regs.h
  • HPTFLEN_HPTXFSAR : usb_regs.h
  • HPTFQSTAT_CNUM : usb_regs.h
  • HPTFQSTAT_EPNUM : usb_regs.h
  • HPTFQSTAT_OEFRM : usb_regs.h
  • HPTFQSTAT_PTXFS : usb_regs.h
  • HPTFQSTAT_PTXREQS : usb_regs.h
  • HPTFQSTAT_PTXREQT : usb_regs.h
  • HPTFQSTAT_TMF : usb_regs.h
  • HPTFQSTAT_TYPE : usb_regs.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
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  • u
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- i -

  • I2C0 : gd32f10x_i2c.h
  • I2C1 : gd32f10x_i2c.h
  • I2C_ACK_DISABLE : gd32f10x_i2c.h
  • I2C_ACK_ENABLE : gd32f10x_i2c.h
  • I2C_ACKPOS_CURRENT : gd32f10x_i2c.h
  • I2C_ACKPOS_NEXT : gd32f10x_i2c.h
  • I2C_ADDFORMAT_10BITS : gd32f10x_i2c.h
  • I2C_ADDFORMAT_7BITS : gd32f10x_i2c.h
  • I2C_ARP_DISABLE : gd32f10x_i2c.h
  • I2C_ARP_ENABLE : gd32f10x_i2c.h
  • I2C_CKCFG : gd32f10x_i2c.h
  • I2C_CKCFG_CLKC : gd32f10x_i2c.h
  • I2C_CKCFG_DTCY : gd32f10x_i2c.h
  • I2C_CKCFG_FAST : gd32f10x_i2c.h
  • I2C_CTL0 : gd32f10x_i2c.h
  • I2C_CTL0_ACKEN : gd32f10x_i2c.h
  • I2C_CTL0_ARPEN : gd32f10x_i2c.h
  • I2C_CTL0_DISSTRC : gd32f10x_i2c.h
  • I2C_CTL0_GCEN : gd32f10x_i2c.h
  • I2C_CTL0_I2CEN : gd32f10x_i2c.h
  • I2C_CTL0_PECEN : gd32f10x_i2c.h
  • I2C_CTL0_PECTRANS : gd32f10x_i2c.h
  • I2C_CTL0_POAP : gd32f10x_i2c.h
  • I2C_CTL0_SALT : gd32f10x_i2c.h
  • I2C_CTL0_SMBEN : gd32f10x_i2c.h
  • I2C_CTL0_SMBSEL : gd32f10x_i2c.h
  • I2C_CTL0_SRESET : gd32f10x_i2c.h
  • I2C_CTL0_START : gd32f10x_i2c.h
  • I2C_CTL0_STOP : gd32f10x_i2c.h
  • I2C_CTL1 : gd32f10x_i2c.h
  • I2C_CTL1_BUFIE : gd32f10x_i2c.h
  • I2C_CTL1_DMALST : gd32f10x_i2c.h
  • I2C_CTL1_DMAON : gd32f10x_i2c.h
  • I2C_CTL1_ERRIE : gd32f10x_i2c.h
  • I2C_CTL1_EVIE : gd32f10x_i2c.h
  • I2C_CTL1_I2CCLK : gd32f10x_i2c.h
  • I2C_DATA : gd32f10x_i2c.h
  • I2C_DATA_TRB : gd32f10x_i2c.h
  • I2C_DMA_OFF : gd32f10x_i2c.h
  • I2C_DMA_ON : gd32f10x_i2c.h
  • I2C_DMALST_OFF : gd32f10x_i2c.h
  • I2C_DMALST_ON : gd32f10x_i2c.h
  • I2C_DTCY_16_9 : gd32f10x_i2c.h
  • I2C_DTCY_2 : gd32f10x_i2c.h
  • I2C_DUADEN_DISABLE : gd32f10x_i2c.h
  • I2C_DUADEN_ENABLE : gd32f10x_i2c.h
  • I2C_FLAG_ADD10SEND : gd32f10x_i2c.h
  • I2C_FLAG_ADDSEND : gd32f10x_i2c.h
  • I2C_FLAG_AERR : gd32f10x_i2c.h
  • I2C_FLAG_BERR : gd32f10x_i2c.h
  • I2C_FLAG_BTC : gd32f10x_i2c.h
  • I2C_FLAG_DEFSMB : gd32f10x_i2c.h
  • I2C_FLAG_DUMOD : gd32f10x_i2c.h
  • I2C_FLAG_HSTSMB : gd32f10x_i2c.h
  • I2C_FLAG_I2CBSY : gd32f10x_i2c.h
  • I2C_FLAG_LOSTARB : gd32f10x_i2c.h
  • I2C_FLAG_MASK : gd32f10x_i2c.c
  • I2C_FLAG_MASTER : gd32f10x_i2c.h
  • I2C_FLAG_OUERR : gd32f10x_i2c.h
  • I2C_FLAG_PECERR : gd32f10x_i2c.h
  • I2C_FLAG_RBNE : gd32f10x_i2c.h
  • I2C_FLAG_RXGC : gd32f10x_i2c.h
  • I2C_FLAG_SBSEND : gd32f10x_i2c.h
  • I2C_FLAG_SMBALT : gd32f10x_i2c.h
  • I2C_FLAG_SMBTO : gd32f10x_i2c.h
  • I2C_FLAG_STPDET : gd32f10x_i2c.h
  • I2C_FLAG_TBE : gd32f10x_i2c.h
  • I2C_FLAG_TRS : gd32f10x_i2c.h
  • I2C_GCEN_DISABLE : gd32f10x_i2c.h
  • I2C_GCEN_ENABLE : gd32f10x_i2c.h
  • I2C_I2CMODE_ENABLE : gd32f10x_i2c.h
  • I2C_INT_BUF : gd32f10x_i2c.h
  • I2C_INT_ERR : gd32f10x_i2c.h
  • I2C_INT_EV : gd32f10x_i2c.h
  • I2C_INT_FLAG_ADD10SEND : gd32f10x_i2c.h
  • I2C_INT_FLAG_ADDSEND : gd32f10x_i2c.h
  • I2C_INT_FLAG_AERR : gd32f10x_i2c.h
  • I2C_INT_FLAG_BERR : gd32f10x_i2c.h
  • I2C_INT_FLAG_BTC : gd32f10x_i2c.h
  • I2C_INT_FLAG_LOSTARB : gd32f10x_i2c.h
  • I2C_INT_FLAG_OUERR : gd32f10x_i2c.h
  • I2C_INT_FLAG_PECERR : gd32f10x_i2c.h
  • I2C_INT_FLAG_RBNE : gd32f10x_i2c.h
  • I2C_INT_FLAG_SBSEND : gd32f10x_i2c.h
  • I2C_INT_FLAG_SMBALT : gd32f10x_i2c.h
  • I2C_INT_FLAG_SMBTO : gd32f10x_i2c.h
  • I2C_INT_FLAG_STPDET : gd32f10x_i2c.h
  • I2C_INT_FLAG_TBE : gd32f10x_i2c.h
  • I2C_PEC_DISABLE : gd32f10x_i2c.h
  • I2C_PEC_ENABLE : gd32f10x_i2c.h
  • I2C_PECTRANS_DISABLE : gd32f10x_i2c.h
  • I2C_PECTRANS_ENABLE : gd32f10x_i2c.h
  • I2C_RECEIVER : gd32f10x_i2c.h
  • I2C_RT : gd32f10x_i2c.h
  • I2C_RT_RISETIME : gd32f10x_i2c.h
  • I2C_SADDR0 : gd32f10x_i2c.h
  • I2C_SADDR0_ADDFORMAT : gd32f10x_i2c.h
  • I2C_SADDR0_ADDRESS : gd32f10x_i2c.h
  • I2C_SADDR0_ADDRESS0 : gd32f10x_i2c.h
  • I2C_SADDR0_ADDRESS_H : gd32f10x_i2c.h
  • I2C_SADDR1 : gd32f10x_i2c.h
  • I2C_SADDR1_ADDRESS2 : gd32f10x_i2c.h
  • I2C_SADDR1_DUADEN : gd32f10x_i2c.h
  • I2C_SALTSEND_DISABLE : gd32f10x_i2c.h
  • I2C_SALTSEND_ENABLE : gd32f10x_i2c.h
  • I2C_SCLSTRETCH_DISABLE : gd32f10x_i2c.h
  • I2C_SCLSTRETCH_ENABLE : gd32f10x_i2c.h
  • I2C_SMBUS_DEVICE : gd32f10x_i2c.h
  • I2C_SMBUS_HOST : gd32f10x_i2c.h
  • I2C_SMBUSMODE_ENABLE : gd32f10x_i2c.h
  • I2C_SRESET_RESET : gd32f10x_i2c.h
  • I2C_SRESET_SET : gd32f10x_i2c.h
  • I2C_STAT0 : gd32f10x_i2c.h
  • I2C_STAT0_ADD10SEND : gd32f10x_i2c.h
  • I2C_STAT0_ADDSEND : gd32f10x_i2c.h
  • I2C_STAT0_AERR : gd32f10x_i2c.h
  • I2C_STAT0_BERR : gd32f10x_i2c.h
  • I2C_STAT0_BTC : gd32f10x_i2c.h
  • I2C_STAT0_LOSTARB : gd32f10x_i2c.h
  • I2C_STAT0_OUERR : gd32f10x_i2c.h
  • I2C_STAT0_PECERR : gd32f10x_i2c.h
  • I2C_STAT0_RBNE : gd32f10x_i2c.h
  • I2C_STAT0_SBSEND : gd32f10x_i2c.h
  • I2C_STAT0_SMBALT : gd32f10x_i2c.h
  • I2C_STAT0_SMBTO : gd32f10x_i2c.h
  • I2C_STAT0_STPDET : gd32f10x_i2c.h
  • I2C_STAT0_TBE : gd32f10x_i2c.h
  • I2C_STAT1 : gd32f10x_i2c.h
  • I2C_STAT1_DEFSMB : gd32f10x_i2c.h
  • I2C_STAT1_DUMODF : gd32f10x_i2c.h
  • I2C_STAT1_ECV : gd32f10x_i2c.h
  • I2C_STAT1_HSTSMB : gd32f10x_i2c.h
  • I2C_STAT1_I2CBSY : gd32f10x_i2c.h
  • I2C_STAT1_MASTER : gd32f10x_i2c.h
  • I2C_STAT1_RXGC : gd32f10x_i2c.h
  • I2C_STAT1_TRS : gd32f10x_i2c.h
  • I2C_TRANSMITTER : gd32f10x_i2c.h
  • I2CCLK_MAX : gd32f10x_i2c.c
  • I2S1_CLOCK_SEL : gd32f10x_spi.c
  • I2S2_CLOCK_SEL : gd32f10x_spi.c
  • I2S_AUDIOSAMPLE_11K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_16K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_192K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_22K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_32K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_44K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_48K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_8K : gd32f10x_spi.h
  • I2S_AUDIOSAMPLE_96K : gd32f10x_spi.h
  • I2S_CKPL_HIGH : gd32f10x_spi.h
  • I2S_CKPL_LOW : gd32f10x_spi.h
  • I2S_CLOCK_DIV_MASK : gd32f10x_spi.c
  • I2S_CLOCK_MUL_MASK : gd32f10x_spi.c
  • I2S_FLAG_CH : gd32f10x_spi.h
  • I2S_FLAG_RBNE : gd32f10x_spi.h
  • I2S_FLAG_RXORERR : gd32f10x_spi.h
  • I2S_FLAG_TBE : gd32f10x_spi.h
  • I2S_FLAG_TRANS : gd32f10x_spi.h
  • I2S_FLAG_TXURERR : gd32f10x_spi.h
  • I2S_FRAMEFORMAT_DT16B_CH16B : gd32f10x_spi.h
  • I2S_FRAMEFORMAT_DT16B_CH32B : gd32f10x_spi.h
  • I2S_FRAMEFORMAT_DT24B_CH32B : gd32f10x_spi.h
  • I2S_FRAMEFORMAT_DT32B_CH32B : gd32f10x_spi.h
  • I2S_INIT_MASK : gd32f10x_spi.c
  • I2S_INT_FLAG_TXURERR : gd32f10x_spi.h
  • I2S_MCKOUT_DISABLE : gd32f10x_spi.h
  • I2S_MCKOUT_ENABLE : gd32f10x_spi.h
  • I2S_MODE_MASTERRX : gd32f10x_spi.h
  • I2S_MODE_MASTERTX : gd32f10x_spi.h
  • I2S_MODE_SLAVERX : gd32f10x_spi.h
  • I2S_MODE_SLAVETX : gd32f10x_spi.h
  • I2S_STD_LSB : gd32f10x_spi.h
  • I2S_STD_MSB : gd32f10x_spi.h
  • I2S_STD_PCMLONG : gd32f10x_spi.h
  • I2S_STD_PCMSHORT : gd32f10x_spi.h
  • I2S_STD_PHILLIPS : gd32f10x_spi.h
  • I2SCTL_DTLEN : gd32f10x_spi.h
  • I2SCTL_I2SOPMOD : gd32f10x_spi.h
  • I2SCTL_I2SSTD : gd32f10x_spi.h
  • IER_MASK : usbd_core.h
  • IF_USE_EXTERNPHY_LIB : gd32f10x_enet.h
  • INT_REG_OFFSET : gd32f10x_rcu.h
  • INTEN_INTS_OFFSET : gd32f10x_exmc.c
  • INTF_DIR : usbd_regs.h
  • INTF_EPNUM : usbd_regs.h
  • INTF_ERRIF : usbd_regs.h
  • INTF_ESOFIF : usbd_regs.h
  • INTF_L1REQ : usbd_regs.h
  • INTF_PMOUIF : usbd_regs.h
  • INTF_RSTIF : usbd_regs.h
  • INTF_SOFIF : usbd_regs.h
  • INTF_SPSIF : usbd_regs.h
  • INTF_STIF : usbd_regs.h
  • INTF_WKUPIF : usbd_regs.h
  • IOFFX_IOFF : gd32f10x_adc.h
  • IS_NOT_EP0 : usbd_std.h
  • ISQ_IL : gd32f10x_adc.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
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- l -

  • LAN8700 : gd32f10x_enet.h
  • LOCATE_DIEPCTL : usb_regs.h
  • LOCATE_DIEPINTF : usb_regs.h
  • LOCATE_DIEPLEN : usb_regs.h
  • LOCATE_DIEPTFLEN : usb_regs.h
  • LOCATE_DIEPxTFSTAT : usb_regs.h
  • LOCATE_DOEPCTL : usb_regs.h
  • LOCATE_DOEPINTF : usb_regs.h
  • LOCATE_DOEPLEN : usb_regs.h
  • LOCATE_FIFO : usb_regs.h
  • LOCATE_HCHCTL : usb_regs.h
  • LOCATE_HCHINTEN : usb_regs.h
  • LOCATE_HCHINTF : usb_regs.h
  • LOCATE_HCHLEN : usb_regs.h
  • LOWBYTE : usbd_std.h
  • LPMCS_BLSTAT : usbd_regs.h
  • LPMCS_LPMACK : usbd_regs.h
  • LPMCS_LPMEN : usbd_regs.h
  • LPMCS_REMWK : usbd_regs.h
  • LSB_16BIT_MASK : gd32f10x_gpio.c
  • LXTAL_STARTUP_TIMEOUT : gd32f10x_rcu.c
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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- m -

  • MAC_ADDR0H_ADDR0H : gd32f10x_enet.h
  • MAC_ADDR123H_ADDR123H : gd32f10x_enet.h
  • MAC_CFG_BOL : gd32f10x_enet.h
  • MAC_CFG_IGBS : gd32f10x_enet.h
  • MAC_CFG_MASK : gd32f10x_enet.h
  • MAC_FCTH_RFA : gd32f10x_enet.h
  • MAC_FCTH_RFD : gd32f10x_enet.h
  • MAC_FCTL_MASK : gd32f10x_enet.h
  • MAC_FCTL_PLTS : gd32f10x_enet.h
  • MAC_FCTL_PTM : gd32f10x_enet.h
  • MAC_FCTL_REG_OFFSET : gd32f10x_enet.h
  • MAC_FRMF_PCFRM : gd32f10x_enet.h
  • MAC_INTF_REG_OFFSET : gd32f10x_enet.h
  • MAC_INTMSK_REG_OFFSET : gd32f10x_enet.h
  • MAC_PHY_CTL_CLR : gd32f10x_enet.h
  • MAC_PHY_CTL_PA : gd32f10x_enet.h
  • MAC_PHY_CTL_PR : gd32f10x_enet.h
  • MAC_PHY_DATA_PD : gd32f10x_enet.h
  • MAC_VLT_VLTI : gd32f10x_enet.h
  • MAC_WUM_REG_OFFSET : gd32f10x_enet.h
  • MAX_USBH_STATE_STACK_DEEP : usbh_core.h
  • MAX_USBH_STATE_TABLE_NUM : usbh_core.h
  • MIN : usbd_std.h
  • MSC_CLASS : usbh_core.h
  • MSC_MSCCNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_PROTOCOL : usbh_core.h
  • MSC_RFAECNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_RFCECNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_RGUFCNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_RINTF_REG_OFFSET : gd32f10x_enet.h
  • MSC_RINTMSK_REG_OFFSET : gd32f10x_enet.h
  • MSC_SCCNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_TGFCNT_REG_OFFSET : gd32f10x_enet.h
  • MSC_TINTF_REG_OFFSET : gd32f10x_enet.h
  • MSC_TINTMSK_REG_OFFSET : gd32f10x_enet.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
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  • w

- n -

  • NODATA_STAGE_TIMEOUT : usb_std.h
  • NPATCFG_ATTHIZ_OFFSET : gd32f10x_exmc.c
  • NPATCFG_ATTHLD_OFFSET : gd32f10x_exmc.c
  • NPATCFG_ATTWAIT_OFFSET : gd32f10x_exmc.c
  • NPCTCFG_COMHIZ_OFFSET : gd32f10x_exmc.c
  • NPCTCFG_COMHLD_OFFSET : gd32f10x_exmc.c
  • NPCTCFG_COMWAIT_OFFSET : gd32f10x_exmc.c
  • NPCTL_ATR : gd32f10x_exmc.h
  • NPCTL_CTR : gd32f10x_exmc.h
  • NPCTL_ECCEN_OFFSET : gd32f10x_exmc.c
  • NPCTL_ECCSZ : gd32f10x_exmc.h
  • NPCTL_NDW : gd32f10x_exmc.h
  • NPCTL_NDWTEN_OFFSET : gd32f10x_exmc.c
  • NULL : usb_defines.h , usbd_std.h
  • NVIC_AIRCR_VECTKEY_MASK : gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE0_SUB4 : gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE1_SUB3 : gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE2_SUB2 : gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE3_SUB1 : gd32f10x_misc.h
  • NVIC_PRIGROUP_PRE4_SUB0 : gd32f10x_misc.h
  • NVIC_VECTTAB_FLASH : gd32f10x_misc.h
  • NVIC_VECTTAB_OFFSET_MASK : gd32f10x_misc.h
  • NVIC_VECTTAB_RAM : gd32f10x_misc.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

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  • Functions
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- o -

  • OB : gd32f10x_fmc.h
  • OB_BOOT_B0 : gd32f10x_fmc.h
  • OB_BOOT_B1 : gd32f10x_fmc.h
  • OB_DEEPSLEEP_NRST : gd32f10x_fmc.h
  • OB_DEEPSLEEP_RST : gd32f10x_fmc.h
  • OB_FWDGT_HW : gd32f10x_fmc.h
  • OB_FWDGT_SW : gd32f10x_fmc.h
  • OB_SPC : gd32f10x_fmc.h
  • OB_SPC_SPC : gd32f10x_fmc.h
  • OB_SPC_SPC_N : gd32f10x_fmc.h
  • OB_STDBY_NRST : gd32f10x_fmc.h
  • OB_STDBY_RST : gd32f10x_fmc.h
  • OB_USER : gd32f10x_fmc.h
  • OB_USER_MASK : gd32f10x_fmc.h
  • OB_USER_USER : gd32f10x_fmc.h
  • OB_USER_USER_N : gd32f10x_fmc.h
  • OB_WP0 : gd32f10x_fmc.h
  • OB_WP0_WP0 : gd32f10x_fmc.h
  • OB_WP1 : gd32f10x_fmc.h
  • OB_WP1_WP1 : gd32f10x_fmc.h
  • OB_WP2 : gd32f10x_fmc.h
  • OB_WP2_WP2 : gd32f10x_fmc.h
  • OB_WP3 : gd32f10x_fmc.h
  • OB_WP3_WP3 : gd32f10x_fmc.h
  • OB_WP_0 : gd32f10x_fmc.h
  • OB_WP_1 : gd32f10x_fmc.h
  • OB_WP_10 : gd32f10x_fmc.h
  • OB_WP_11 : gd32f10x_fmc.h
  • OB_WP_12 : gd32f10x_fmc.h
  • OB_WP_13 : gd32f10x_fmc.h
  • OB_WP_14 : gd32f10x_fmc.h
  • OB_WP_15 : gd32f10x_fmc.h
  • OB_WP_16 : gd32f10x_fmc.h
  • OB_WP_17 : gd32f10x_fmc.h
  • OB_WP_18 : gd32f10x_fmc.h
  • OB_WP_19 : gd32f10x_fmc.h
  • OB_WP_2 : gd32f10x_fmc.h
  • OB_WP_20 : gd32f10x_fmc.h
  • OB_WP_21 : gd32f10x_fmc.h
  • OB_WP_22 : gd32f10x_fmc.h
  • OB_WP_23 : gd32f10x_fmc.h
  • OB_WP_24 : gd32f10x_fmc.h
  • OB_WP_25 : gd32f10x_fmc.h
  • OB_WP_26 : gd32f10x_fmc.h
  • OB_WP_27 : gd32f10x_fmc.h
  • OB_WP_28 : gd32f10x_fmc.h
  • OB_WP_29 : gd32f10x_fmc.h
  • OB_WP_3 : gd32f10x_fmc.h
  • OB_WP_30 : gd32f10x_fmc.h
  • OB_WP_31 : gd32f10x_fmc.h
  • OB_WP_4 : gd32f10x_fmc.h
  • OB_WP_5 : gd32f10x_fmc.h
  • OB_WP_6 : gd32f10x_fmc.h
  • OB_WP_7 : gd32f10x_fmc.h
  • OB_WP_8 : gd32f10x_fmc.h
  • OB_WP_9 : gd32f10x_fmc.h
  • OB_WP_ALL : gd32f10x_fmc.h
  • OCTL_RCCV : gd32f10x_bkp.h
  • OSC_STARTUP_TIMEOUT : gd32f10x_rcu.c
  • OTG_MODE : usb_defines.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
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- p -

  • PCF_LOCATION1_MASK : gd32f10x_gpio.c
  • PCF_LOCATION2_MASK : gd32f10x_gpio.c
  • PCF_POSITION_MASK : gd32f10x_gpio.c
  • PCF_SWJCFG_MASK : gd32f10x_gpio.c
  • PHY_ADDRESS : gd32f10x_enet.h
  • PHY_AUTONEGO_COMPLETE : gd32f10x_enet.h
  • PHY_AUTONEGOTIATION : gd32f10x_enet.h
  • PHY_CONFIGDELAY : gd32f10x_enet.h
  • PHY_DUPLEX_STATUS : gd32f10x_enet.h
  • PHY_FULLDUPLEX_100M : gd32f10x_enet.h
  • PHY_FULLDUPLEX_10M : gd32f10x_enet.h
  • PHY_HALFDUPLEX_100M : gd32f10x_enet.h
  • PHY_HALFDUPLEX_10M : gd32f10x_enet.h
  • PHY_ISOLATE : gd32f10x_enet.h
  • PHY_JABBER_DETECTION : gd32f10x_enet.h
  • PHY_LINKED_STATUS : gd32f10x_enet.h
  • PHY_LOOPBACK : gd32f10x_enet.h
  • PHY_POWERDOWN : gd32f10x_enet.h
  • PHY_READ_TO : gd32f10x_enet.h
  • PHY_REG_BCR : gd32f10x_enet.h
  • PHY_REG_BSR : gd32f10x_enet.h
  • PHY_RESET : gd32f10x_enet.h
  • PHY_RESETDELAY : gd32f10x_enet.h
  • PHY_RESTART_AUTONEGOTIATION : gd32f10x_enet.h
  • PHY_SPEED_STATUS : gd32f10x_enet.h
  • PHY_SR : gd32f10x_enet.h
  • PHY_TYPE : gd32f10x_enet.h
  • PHY_WRITE_TO : gd32f10x_enet.h
  • PIOTCFG_IOHIZ_OFFSET : gd32f10x_exmc.c
  • PIOTCFG_IOHLD_OFFSET : gd32f10x_exmc.c
  • PIOTCFG_IOWAIT_OFFSET : gd32f10x_exmc.c
  • PLLMF_4 : gd32f10x_rcu.h
  • PMU : gd32f10x_pmu.h
  • PMU_CS : gd32f10x_pmu.h
  • PMU_CS_LVDF : gd32f10x_pmu.h
  • PMU_CS_STBF : gd32f10x_pmu.h
  • PMU_CS_WUF : gd32f10x_pmu.h
  • PMU_CS_WUPEN : gd32f10x_pmu.h
  • PMU_CTL : gd32f10x_pmu.h
  • PMU_CTL_BKPWEN : gd32f10x_pmu.h
  • PMU_CTL_LDOLP : gd32f10x_pmu.h
  • PMU_CTL_LVDEN : gd32f10x_pmu.h
  • PMU_CTL_LVDT : gd32f10x_pmu.h
  • PMU_CTL_STBMOD : gd32f10x_pmu.h
  • PMU_CTL_STBRST : gd32f10x_pmu.h
  • PMU_CTL_WURST : gd32f10x_pmu.h
  • PMU_FLAG_LVD : gd32f10x_pmu.h
  • PMU_FLAG_RESET_STANDBY : gd32f10x_pmu.h
  • PMU_FLAG_RESET_WAKEUP : gd32f10x_pmu.h
  • PMU_FLAG_STANDBY : gd32f10x_pmu.h
  • PMU_FLAG_WAKEUP : gd32f10x_pmu.h
  • PMU_LDO_LOWPOWER : gd32f10x_pmu.h
  • PMU_LDO_NORMAL : gd32f10x_pmu.h
  • PMU_LVDT_0 : gd32f10x_pmu.h
  • PMU_LVDT_1 : gd32f10x_pmu.h
  • PMU_LVDT_2 : gd32f10x_pmu.h
  • PMU_LVDT_3 : gd32f10x_pmu.h
  • PMU_LVDT_4 : gd32f10x_pmu.h
  • PMU_LVDT_5 : gd32f10x_pmu.h
  • PMU_LVDT_6 : gd32f10x_pmu.h
  • PMU_LVDT_7 : gd32f10x_pmu.h
  • PSC_PSC : gd32f10x_fwdgt.h
  • PTP_SSINC_STMSSI : gd32f10x_enet.h
  • PTP_TSUL_TMSUSS : gd32f10x_enet.h
  • PWRCLKCTL_SHCLK : usb_regs.h
  • PWRCLKCTL_SUCLK : usb_regs.h
  • PWRCTL_PWRCTL : gd32f10x_sdio.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • r
  • s
  • t
  • u
  • w

- r -

  • RCU : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV1 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV128 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV16 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV2 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV256 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV4 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV512 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV64 : gd32f10x_rcu.h
  • RCU_AHB_CKSYS_DIV8 : gd32f10x_rcu.h
  • RCU_AHBEN : gd32f10x_rcu.h
  • RCU_AHBEN_CRCEN : gd32f10x_rcu.h
  • RCU_AHBEN_DMA0EN : gd32f10x_rcu.h
  • RCU_AHBEN_DMA1EN : gd32f10x_rcu.h
  • RCU_AHBEN_EXMCEN : gd32f10x_rcu.h
  • RCU_AHBEN_FMCSPEN : gd32f10x_rcu.h
  • RCU_AHBEN_SDIOEN : gd32f10x_rcu.h
  • RCU_AHBEN_SRAMSPEN : gd32f10x_rcu.h
  • RCU_AHBRST_ENETRST : gd32f10x_rcu.h
  • RCU_AHBRST_USBFSRST : gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV1 : gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV16 : gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV2 : gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV4 : gd32f10x_rcu.h
  • RCU_APB1_CKAHB_DIV8 : gd32f10x_rcu.h
  • RCU_APB1EN : gd32f10x_rcu.h
  • RCU_APB1EN_BKPIEN : gd32f10x_rcu.h
  • RCU_APB1EN_CAN0EN : gd32f10x_rcu.h
  • RCU_APB1EN_CAN1EN : gd32f10x_rcu.h
  • RCU_APB1EN_DACEN : gd32f10x_rcu.h
  • RCU_APB1EN_I2C0EN : gd32f10x_rcu.h
  • RCU_APB1EN_I2C1EN : gd32f10x_rcu.h
  • RCU_APB1EN_PMUEN : gd32f10x_rcu.h
  • RCU_APB1EN_SPI1EN : gd32f10x_rcu.h
  • RCU_APB1EN_SPI2EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER11EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER12EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER13EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER1EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER2EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER3EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER4EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER5EN : gd32f10x_rcu.h
  • RCU_APB1EN_TIMER6EN : gd32f10x_rcu.h
  • RCU_APB1EN_UART3EN : gd32f10x_rcu.h
  • RCU_APB1EN_UART4EN : gd32f10x_rcu.h
  • RCU_APB1EN_USART1EN : gd32f10x_rcu.h
  • RCU_APB1EN_USART2EN : gd32f10x_rcu.h
  • RCU_APB1EN_USBDEN : gd32f10x_rcu.h
  • RCU_APB1EN_WWDGTEN : gd32f10x_rcu.h
  • RCU_APB1RST : gd32f10x_rcu.h
  • RCU_APB1RST_BKPIRST : gd32f10x_rcu.h
  • RCU_APB1RST_CAN0RST : gd32f10x_rcu.h
  • RCU_APB1RST_CAN1RST : gd32f10x_rcu.h
  • RCU_APB1RST_DACRST : gd32f10x_rcu.h
  • RCU_APB1RST_I2C0RST : gd32f10x_rcu.h
  • RCU_APB1RST_I2C1RST : gd32f10x_rcu.h
  • RCU_APB1RST_PMURST : gd32f10x_rcu.h
  • RCU_APB1RST_SPI1RST : gd32f10x_rcu.h
  • RCU_APB1RST_SPI2RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER11RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER12RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER13RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER1RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER2RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER3RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER4RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER5RST : gd32f10x_rcu.h
  • RCU_APB1RST_TIMER6RST : gd32f10x_rcu.h
  • RCU_APB1RST_UART3RST : gd32f10x_rcu.h
  • RCU_APB1RST_UART4RST : gd32f10x_rcu.h
  • RCU_APB1RST_USART1RST : gd32f10x_rcu.h
  • RCU_APB1RST_USART2RST : gd32f10x_rcu.h
  • RCU_APB1RST_USBDRST : gd32f10x_rcu.h
  • RCU_APB1RST_WWDGTRST : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV1 : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV16 : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV2 : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV4 : gd32f10x_rcu.h
  • RCU_APB2_CKAHB_DIV8 : gd32f10x_rcu.h
  • RCU_APB2EN : gd32f10x_rcu.h
  • RCU_APB2EN_ADC0EN : gd32f10x_rcu.h
  • RCU_APB2EN_ADC1EN : gd32f10x_rcu.h
  • RCU_APB2EN_AFEN : gd32f10x_rcu.h
  • RCU_APB2EN_PAEN : gd32f10x_rcu.h
  • RCU_APB2EN_PBEN : gd32f10x_rcu.h
  • RCU_APB2EN_PCEN : gd32f10x_rcu.h
  • RCU_APB2EN_PDEN : gd32f10x_rcu.h
  • RCU_APB2EN_PEEN : gd32f10x_rcu.h
  • RCU_APB2EN_PFEN : gd32f10x_rcu.h
  • RCU_APB2EN_PGEN : gd32f10x_rcu.h
  • RCU_APB2EN_SPI0EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER0EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER10EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER7EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER8EN : gd32f10x_rcu.h
  • RCU_APB2EN_TIMER9EN : gd32f10x_rcu.h
  • RCU_APB2EN_USART0EN : gd32f10x_rcu.h
  • RCU_APB2RST : gd32f10x_rcu.h
  • RCU_APB2RST_ADC0RST : gd32f10x_rcu.h
  • RCU_APB2RST_ADC1RST : gd32f10x_rcu.h
  • RCU_APB2RST_AFRST : gd32f10x_rcu.h
  • RCU_APB2RST_PARST : gd32f10x_rcu.h
  • RCU_APB2RST_PBRST : gd32f10x_rcu.h
  • RCU_APB2RST_PCRST : gd32f10x_rcu.h
  • RCU_APB2RST_PDRST : gd32f10x_rcu.h
  • RCU_APB2RST_PERST : gd32f10x_rcu.h
  • RCU_APB2RST_PFRST : gd32f10x_rcu.h
  • RCU_APB2RST_PGRST : gd32f10x_rcu.h
  • RCU_APB2RST_SPI0RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER0RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER10RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER7RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER8RST : gd32f10x_rcu.h
  • RCU_APB2RST_TIMER9RST : gd32f10x_rcu.h
  • RCU_APB2RST_USART0RST : gd32f10x_rcu.h
  • RCU_BDCTL : gd32f10x_rcu.h
  • RCU_BDCTL_BKPRST : gd32f10x_rcu.h
  • RCU_BDCTL_LXTALBPS : gd32f10x_rcu.h
  • RCU_BDCTL_LXTALEN : gd32f10x_rcu.h
  • RCU_BDCTL_LXTALSTB : gd32f10x_rcu.h
  • RCU_BDCTL_RTCEN : gd32f10x_rcu.h
  • RCU_BDCTL_RTCSRC : gd32f10x_rcu.h
  • RCU_BIT_POS : gd32f10x_rcu.h
  • RCU_CFG0 : gd32f10x_rcu.h
  • RCU_CFG0_ADCPSC : gd32f10x_rcu.h
  • RCU_CFG0_ADCPSC_2 : gd32f10x_rcu.h
  • RCU_CFG0_AHBPSC : gd32f10x_rcu.h
  • RCU_CFG0_APB1PSC : gd32f10x_rcu.h
  • RCU_CFG0_APB2PSC : gd32f10x_rcu.h
  • RCU_CFG0_CKOUT0SEL : gd32f10x_rcu.h
  • RCU_CFG0_PLLMF : gd32f10x_rcu.h
  • RCU_CFG0_PLLMF_4 : gd32f10x_rcu.h
  • RCU_CFG0_PLLSEL : gd32f10x_rcu.h
  • RCU_CFG0_PREDV0 : gd32f10x_rcu.h
  • RCU_CFG0_SCS : gd32f10x_rcu.h
  • RCU_CFG0_SCSS : gd32f10x_rcu.h
  • RCU_CFG0_USBDPSC : gd32f10x_rcu.h
  • RCU_CFG1_I2S1SEL : gd32f10x_rcu.h
  • RCU_CFG1_I2S2SEL : gd32f10x_rcu.h
  • RCU_CFG1_PLL1MF : gd32f10x_rcu.h
  • RCU_CFG1_PLL2MF : gd32f10x_rcu.h
  • RCU_CFG1_PREDV0 : gd32f10x_rcu.h
  • RCU_CFG1_PREDV0SEL : gd32f10x_rcu.h
  • RCU_CFG1_PREDV1 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV12 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV16 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV2 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV4 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV6 : gd32f10x_rcu.h
  • RCU_CKADC_CKAPB2_DIV8 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_CKPLL1 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_CKPLL2 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_CKPLL2_DIV2 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_CKPLL_DIV2 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_CKSYS : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_EXT1 : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_HXTAL : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_IRC8M : gd32f10x_rcu.h
  • RCU_CKOUT0SRC_NONE : gd32f10x_rcu.h
  • RCU_CKSYSSRC_HXTAL : gd32f10x_rcu.h
  • RCU_CKSYSSRC_IRC8M : gd32f10x_rcu.h
  • RCU_CKSYSSRC_PLL : gd32f10x_rcu.h
  • RCU_CKUSB_CKPLL_DIV1 : gd32f10x_rcu.h
  • RCU_CKUSB_CKPLL_DIV1_5 : gd32f10x_rcu.h
  • RCU_CKUSB_CKPLL_DIV2 : gd32f10x_rcu.h
  • RCU_CKUSB_CKPLL_DIV2_5 : gd32f10x_rcu.h
  • RCU_CTL : gd32f10x_rcu.h
  • RCU_CTL_CKMEN : gd32f10x_rcu.h
  • RCU_CTL_HXTALBPS : gd32f10x_rcu.h
  • RCU_CTL_HXTALEN : gd32f10x_rcu.h
  • RCU_CTL_HXTALSTB : gd32f10x_rcu.h
  • RCU_CTL_IRC8MADJ : gd32f10x_rcu.h
  • RCU_CTL_IRC8MCALIB : gd32f10x_rcu.h
  • RCU_CTL_IRC8MEN : gd32f10x_rcu.h
  • RCU_CTL_IRC8MSTB : gd32f10x_rcu.h
  • RCU_CTL_PLLEN : gd32f10x_rcu.h
  • RCU_CTL_PLLSTB : gd32f10x_rcu.h
  • RCU_DEEPSLEEP_V_0_9 : gd32f10x_rcu.h
  • RCU_DEEPSLEEP_V_1_0 : gd32f10x_rcu.h
  • RCU_DEEPSLEEP_V_1_1 : gd32f10x_rcu.h
  • RCU_DEEPSLEEP_V_1_2 : gd32f10x_rcu.h
  • RCU_DSV : gd32f10x_rcu.h
  • RCU_DSV_DSLPVS : gd32f10x_rcu.h
  • RCU_I2S1SRC_CKPLL2_MUL2 : gd32f10x_rcu.h
  • RCU_I2S1SRC_CKSYS : gd32f10x_rcu.h
  • RCU_I2S2SRC_CKPLL2_MUL2 : gd32f10x_rcu.h
  • RCU_I2S2SRC_CKSYS : gd32f10x_rcu.h
  • RCU_INT : gd32f10x_rcu.h
  • RCU_INT_CKMIC : gd32f10x_rcu.h
  • RCU_INT_CKMIF : gd32f10x_rcu.h
  • RCU_INT_HXTALSTBIC : gd32f10x_rcu.h
  • RCU_INT_HXTALSTBIE : gd32f10x_rcu.h
  • RCU_INT_HXTALSTBIF : gd32f10x_rcu.h
  • RCU_INT_IRC40KSTBIC : gd32f10x_rcu.h
  • RCU_INT_IRC40KSTBIE : gd32f10x_rcu.h
  • RCU_INT_IRC40KSTBIF : gd32f10x_rcu.h
  • RCU_INT_IRC8MSTBIC : gd32f10x_rcu.h
  • RCU_INT_IRC8MSTBIE : gd32f10x_rcu.h
  • RCU_INT_IRC8MSTBIF : gd32f10x_rcu.h
  • RCU_INT_LXTALSTBIC : gd32f10x_rcu.h
  • RCU_INT_LXTALSTBIE : gd32f10x_rcu.h
  • RCU_INT_LXTALSTBIF : gd32f10x_rcu.h
  • RCU_INT_PLLSTBIC : gd32f10x_rcu.h
  • RCU_INT_PLLSTBIE : gd32f10x_rcu.h
  • RCU_INT_PLLSTBIF : gd32f10x_rcu.h
  • RCU_PLL1_MUL10 : gd32f10x_rcu.h
  • RCU_PLL1_MUL11 : gd32f10x_rcu.h
  • RCU_PLL1_MUL12 : gd32f10x_rcu.h
  • RCU_PLL1_MUL13 : gd32f10x_rcu.h
  • RCU_PLL1_MUL14 : gd32f10x_rcu.h
  • RCU_PLL1_MUL15 : gd32f10x_rcu.h
  • RCU_PLL1_MUL16 : gd32f10x_rcu.h
  • RCU_PLL1_MUL20 : gd32f10x_rcu.h
  • RCU_PLL1_MUL8 : gd32f10x_rcu.h
  • RCU_PLL1_MUL9 : gd32f10x_rcu.h
  • RCU_PLL2_MUL10 : gd32f10x_rcu.h
  • RCU_PLL2_MUL11 : gd32f10x_rcu.h
  • RCU_PLL2_MUL12 : gd32f10x_rcu.h
  • RCU_PLL2_MUL13 : gd32f10x_rcu.h
  • RCU_PLL2_MUL14 : gd32f10x_rcu.h
  • RCU_PLL2_MUL15 : gd32f10x_rcu.h
  • RCU_PLL2_MUL16 : gd32f10x_rcu.h
  • RCU_PLL2_MUL20 : gd32f10x_rcu.h
  • RCU_PLL2_MUL8 : gd32f10x_rcu.h
  • RCU_PLL2_MUL9 : gd32f10x_rcu.h
  • RCU_PLL_MUL10 : gd32f10x_rcu.h
  • RCU_PLL_MUL11 : gd32f10x_rcu.h
  • RCU_PLL_MUL12 : gd32f10x_rcu.h
  • RCU_PLL_MUL13 : gd32f10x_rcu.h
  • RCU_PLL_MUL14 : gd32f10x_rcu.h
  • RCU_PLL_MUL15 : gd32f10x_rcu.h
  • RCU_PLL_MUL16 : gd32f10x_rcu.h
  • RCU_PLL_MUL17 : gd32f10x_rcu.h
  • RCU_PLL_MUL18 : gd32f10x_rcu.h
  • RCU_PLL_MUL19 : gd32f10x_rcu.h
  • RCU_PLL_MUL2 : gd32f10x_rcu.h
  • RCU_PLL_MUL20 : gd32f10x_rcu.h
  • RCU_PLL_MUL21 : gd32f10x_rcu.h
  • RCU_PLL_MUL22 : gd32f10x_rcu.h
  • RCU_PLL_MUL23 : gd32f10x_rcu.h
  • RCU_PLL_MUL24 : gd32f10x_rcu.h
  • RCU_PLL_MUL25 : gd32f10x_rcu.h
  • RCU_PLL_MUL26 : gd32f10x_rcu.h
  • RCU_PLL_MUL27 : gd32f10x_rcu.h
  • RCU_PLL_MUL28 : gd32f10x_rcu.h
  • RCU_PLL_MUL29 : gd32f10x_rcu.h
  • RCU_PLL_MUL3 : gd32f10x_rcu.h
  • RCU_PLL_MUL30 : gd32f10x_rcu.h
  • RCU_PLL_MUL31 : gd32f10x_rcu.h
  • RCU_PLL_MUL32 : gd32f10x_rcu.h
  • RCU_PLL_MUL4 : gd32f10x_rcu.h
  • RCU_PLL_MUL5 : gd32f10x_rcu.h
  • RCU_PLL_MUL6 : gd32f10x_rcu.h
  • RCU_PLL_MUL7 : gd32f10x_rcu.h
  • RCU_PLL_MUL8 : gd32f10x_rcu.h
  • RCU_PLL_MUL9 : gd32f10x_rcu.h
  • RCU_PLLSRC_HXTAL : gd32f10x_rcu.h
  • RCU_PLLSRC_IRC8M_DIV2 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV1 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV10 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV11 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV12 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV13 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV14 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV15 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV16 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV2 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV3 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV4 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV5 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV6 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV7 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV8 : gd32f10x_rcu.h
  • RCU_PREDV0_DIV9 : gd32f10x_rcu.h
  • RCU_PREDV0SRC_CKPLL1 : gd32f10x_rcu.h
  • RCU_PREDV0SRC_HXTAL : gd32f10x_rcu.h
  • RCU_PREDV1_DIV1 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV10 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV11 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV12 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV13 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV14 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV15 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV16 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV2 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV3 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV4 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV5 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV6 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV7 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV8 : gd32f10x_rcu.h
  • RCU_PREDV1_DIV9 : gd32f10x_rcu.h
  • RCU_REG_VAL : gd32f10x_rcu.h
  • RCU_REGIDX_BIT : gd32f10x_rcu.h
  • RCU_RSTSCK : gd32f10x_rcu.h
  • RCU_RSTSCK_EPRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_FWDGTRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_IRC40KEN : gd32f10x_rcu.h
  • RCU_RSTSCK_IRC40KSTB : gd32f10x_rcu.h
  • RCU_RSTSCK_LPRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_PORRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_RSTFC : gd32f10x_rcu.h
  • RCU_RSTSCK_SWRSTF : gd32f10x_rcu.h
  • RCU_RSTSCK_WWDGTRSTF : gd32f10x_rcu.h
  • RCU_RTCSRC_HXTAL_DIV_128 : gd32f10x_rcu.h
  • RCU_RTCSRC_IRC40K : gd32f10x_rcu.h
  • RCU_RTCSRC_LXTAL : gd32f10x_rcu.h
  • RCU_RTCSRC_NONE : gd32f10x_rcu.h
  • RCU_SCSS_HXTAL : gd32f10x_rcu.h
  • RCU_SCSS_IRC8M : gd32f10x_rcu.h
  • RCU_SCSS_PLL : gd32f10x_rcu.h
  • RDES0_FRML : gd32f10x_enet.h
  • RDES4_IPPLDT : gd32f10x_enet.h
  • RDES4_PTPMT : gd32f10x_enet.h
  • RFIFO0_REG_OFFSET : gd32f10x_can.h
  • RFIFO1_REG_OFFSET : gd32f10x_can.h
  • RFIFOMDATA0_DB0 : gd32f10x_can.h
  • RFIFOMDATA0_DB1 : gd32f10x_can.h
  • RFIFOMDATA0_DB2 : gd32f10x_can.h
  • RFIFOMDATA0_DB3 : gd32f10x_can.h
  • RFIFOMDATA1_DB4 : gd32f10x_can.h
  • RFIFOMDATA1_DB5 : gd32f10x_can.h
  • RFIFOMDATA1_DB6 : gd32f10x_can.h
  • RFIFOMDATA1_DB7 : gd32f10x_can.h
  • RFIFOMI_EFID : gd32f10x_can.h
  • RFIFOMI_SFID : gd32f10x_can.h
  • RFIFOMP_DLENC : gd32f10x_can.h
  • RFIFOMP_FI : gd32f10x_can.h
  • RLD_RLD : gd32f10x_fwdgt.c
  • RSQ0_RL : gd32f10x_adc.h
  • RSTSCK_REG_OFFSET : gd32f10x_rcu.h
  • RTC : gd32f10x_rtc.h
  • RTC_ALRMH : gd32f10x_rtc.h
  • RTC_ALRMH_ALRM : gd32f10x_rtc.h
  • RTC_ALRML : gd32f10x_rtc.h
  • RTC_ALRML_ALRM : gd32f10x_rtc.h
  • RTC_CNTH : gd32f10x_rtc.h
  • RTC_CNTH_CNT : gd32f10x_rtc.h
  • RTC_CNTL : gd32f10x_rtc.h
  • RTC_CNTL_CNT : gd32f10x_rtc.h
  • RTC_CTL : gd32f10x_rtc.h
  • RTC_CTL_ALRMIF : gd32f10x_rtc.h
  • RTC_CTL_CMF : gd32f10x_rtc.h
  • RTC_CTL_LWOFF : gd32f10x_rtc.h
  • RTC_CTL_OVIF : gd32f10x_rtc.h
  • RTC_CTL_RSYNF : gd32f10x_rtc.h
  • RTC_CTL_SCIF : gd32f10x_rtc.h
  • RTC_DIVH : gd32f10x_rtc.h
  • RTC_DIVH_DIV : gd32f10x_rtc.h
  • RTC_DIVL : gd32f10x_rtc.h
  • RTC_DIVL_DIV : gd32f10x_rtc.h
  • RTC_FLAG_ALARM : gd32f10x_rtc.h
  • RTC_FLAG_LWOF : gd32f10x_rtc.h
  • RTC_FLAG_OVERFLOW : gd32f10x_rtc.h
  • RTC_FLAG_RSYN : gd32f10x_rtc.h
  • RTC_FLAG_SECOND : gd32f10x_rtc.h
  • RTC_HIGH_VALUE : gd32f10x_rtc.h
  • RTC_INT_ALARM : gd32f10x_rtc.h
  • RTC_INT_OVERFLOW : gd32f10x_rtc.h
  • RTC_INT_SECOND : gd32f10x_rtc.h
  • RTC_INTEN : gd32f10x_rtc.h
  • RTC_INTEN_ALRMIE : gd32f10x_rtc.h
  • RTC_INTEN_OVIE : gd32f10x_rtc.h
  • RTC_INTEN_SCIE : gd32f10x_rtc.h
  • RTC_LOW_VALUE : gd32f10x_rtc.h
  • RTC_OUTPUT_ALARM_PULSE : gd32f10x_bkp.h
  • RTC_OUTPUT_SECOND_PULSE : gd32f10x_bkp.h
  • RTC_PSCH : gd32f10x_rtc.h
  • RTC_PSCH_PSC : gd32f10x_rtc.h
  • RTC_PSCL : gd32f10x_rtc.h
  • RTC_PSCL_PSC : gd32f10x_rtc.h
  • RX_MAX_DATA_LENGTH : usb_core.h
  • RXCNT_OFFSET : usbd_regs.h
  • RXSTAT_DATA_UPDT : usb_defines.h
  • RXSTAT_GOUT_NAK : usb_defines.h
  • RXSTAT_SETUP_COMP : usb_defines.h
  • RXSTAT_SETUP_UPDT : usb_defines.h
  • RXSTAT_XFER_COMP : usb_defines.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- s -

  • SADDR0_ADDFORMAT : gd32f10x_i2c.h
  • SAMPTX_SPT : gd32f10x_adc.h
  • SCB_LPM_DEEPSLEEP : gd32f10x_misc.h
  • SCB_LPM_SLEEP_EXIT_ISR : gd32f10x_misc.h
  • SCB_LPM_WAKE_BY_ALL_INT : gd32f10x_misc.h
  • SCB_SCR_SEVONPEND : gd32f10x_misc.h
  • SCB_SCR_SLEEPDEEP : gd32f10x_misc.h
  • SCB_SCR_SLEEPONEXIT : gd32f10x_misc.h
  • SDIO : gd32f10x_sdio.h
  • SDIO_BUSMODE_1BIT : gd32f10x_sdio.h
  • SDIO_BUSMODE_4BIT : gd32f10x_sdio.h
  • SDIO_BUSMODE_8BIT : gd32f10x_sdio.h
  • SDIO_CLKCTL : gd32f10x_sdio.h
  • SDIO_CLKCTL_BUSMODE : gd32f10x_sdio.h
  • SDIO_CLKCTL_CLKBYP : gd32f10x_sdio.h
  • SDIO_CLKCTL_CLKEDGE : gd32f10x_sdio.h
  • SDIO_CLKCTL_CLKEN : gd32f10x_sdio.h
  • SDIO_CLKCTL_CLKPWRSAV : gd32f10x_sdio.h
  • SDIO_CLKCTL_DIV : gd32f10x_sdio.h
  • SDIO_CLKCTL_HWCLKEN : gd32f10x_sdio.h
  • SDIO_CLOCKBYPASS_DISABLE : gd32f10x_sdio.h
  • SDIO_CLOCKBYPASS_ENABLE : gd32f10x_sdio.h
  • SDIO_CLOCKPWRSAVE_DISABLE : gd32f10x_sdio.h
  • SDIO_CLOCKPWRSAVE_ENABLE : gd32f10x_sdio.h
  • SDIO_CMDAGMT : gd32f10x_sdio.h
  • SDIO_CMDAGMT_CMDAGMT : gd32f10x_sdio.h
  • SDIO_CMDCTL : gd32f10x_sdio.h
  • SDIO_CMDCTL_ATAEN : gd32f10x_sdio.h
  • SDIO_CMDCTL_CMDIDX : gd32f10x_sdio.h
  • SDIO_CMDCTL_CMDRESP : gd32f10x_sdio.h
  • SDIO_CMDCTL_CSMEN : gd32f10x_sdio.h
  • SDIO_CMDCTL_ENCMDC : gd32f10x_sdio.h
  • SDIO_CMDCTL_INTWAIT : gd32f10x_sdio.h
  • SDIO_CMDCTL_NINTEN : gd32f10x_sdio.h
  • SDIO_CMDCTL_SUSPEND : gd32f10x_sdio.h
  • SDIO_CMDCTL_WAITDEND : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_1024BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_128BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_16384BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_16BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_1BYTE : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_2048BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_256BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_2BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_32BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_4096BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_4BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_512BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_64BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_8192BYTES : gd32f10x_sdio.h
  • SDIO_DATABLOCKSIZE_8BYTES : gd32f10x_sdio.h
  • SDIO_DATACNT : gd32f10x_sdio.h
  • SDIO_DATACTL : gd32f10x_sdio.h
  • SDIO_DATACTL_BLKSZ : gd32f10x_sdio.h
  • SDIO_DATACTL_DATADIR : gd32f10x_sdio.h
  • SDIO_DATACTL_DATAEN : gd32f10x_sdio.h
  • SDIO_DATACTL_DMAEN : gd32f10x_sdio.h
  • SDIO_DATACTL_IOEN : gd32f10x_sdio.h
  • SDIO_DATACTL_RWEN : gd32f10x_sdio.h
  • SDIO_DATACTL_RWSTOP : gd32f10x_sdio.h
  • SDIO_DATACTL_RWTYPE : gd32f10x_sdio.h
  • SDIO_DATACTL_TRANSMOD : gd32f10x_sdio.h
  • SDIO_DATALEN : gd32f10x_sdio.h
  • SDIO_DATALEN_DATALEN : gd32f10x_sdio.h
  • SDIO_DATATO : gd32f10x_sdio.h
  • SDIO_DATATO_DATATO : gd32f10x_sdio.h
  • SDIO_FIFO : gd32f10x_sdio.h
  • SDIO_FIFO_FIFODT : gd32f10x_sdio.h
  • SDIO_FIFOCNT : gd32f10x_sdio.h
  • SDIO_FLAG_ATAEND : gd32f10x_sdio.h
  • SDIO_FLAG_CCRCERR : gd32f10x_sdio.h
  • SDIO_FLAG_CMDRECV : gd32f10x_sdio.h
  • SDIO_FLAG_CMDRUN : gd32f10x_sdio.h
  • SDIO_FLAG_CMDSEND : gd32f10x_sdio.h
  • SDIO_FLAG_CMDTMOUT : gd32f10x_sdio.h
  • SDIO_FLAG_DTBLKEND : gd32f10x_sdio.h
  • SDIO_FLAG_DTCRCERR : gd32f10x_sdio.h
  • SDIO_FLAG_DTEND : gd32f10x_sdio.h
  • SDIO_FLAG_DTTMOUT : gd32f10x_sdio.h
  • SDIO_FLAG_RFE : gd32f10x_sdio.h
  • SDIO_FLAG_RFF : gd32f10x_sdio.h
  • SDIO_FLAG_RFH : gd32f10x_sdio.h
  • SDIO_FLAG_RXDTVAL : gd32f10x_sdio.h
  • SDIO_FLAG_RXORE : gd32f10x_sdio.h
  • SDIO_FLAG_RXRUN : gd32f10x_sdio.h
  • SDIO_FLAG_SDIOINT : gd32f10x_sdio.h
  • SDIO_FLAG_STBITE : gd32f10x_sdio.h
  • SDIO_FLAG_TFE : gd32f10x_sdio.h
  • SDIO_FLAG_TFF : gd32f10x_sdio.h
  • SDIO_FLAG_TFH : gd32f10x_sdio.h
  • SDIO_FLAG_TXDTVAL : gd32f10x_sdio.h
  • SDIO_FLAG_TXRUN : gd32f10x_sdio.h
  • SDIO_FLAG_TXURE : gd32f10x_sdio.h
  • SDIO_INT_ATAEND : gd32f10x_sdio.h
  • SDIO_INT_CCRCERR : gd32f10x_sdio.h
  • SDIO_INT_CMDRECV : gd32f10x_sdio.h
  • SDIO_INT_CMDRUN : gd32f10x_sdio.h
  • SDIO_INT_CMDSEND : gd32f10x_sdio.h
  • SDIO_INT_CMDTMOUT : gd32f10x_sdio.h
  • SDIO_INT_DTBLKEND : gd32f10x_sdio.h
  • SDIO_INT_DTCRCERR : gd32f10x_sdio.h
  • SDIO_INT_DTEND : gd32f10x_sdio.h
  • SDIO_INT_DTTMOUT : gd32f10x_sdio.h
  • SDIO_INT_FLAG_ATAEND : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CCRCERR : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CMDRECV : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CMDRUN : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CMDSEND : gd32f10x_sdio.h
  • SDIO_INT_FLAG_CMDTMOUT : gd32f10x_sdio.h
  • SDIO_INT_FLAG_DTBLKEND : gd32f10x_sdio.h
  • SDIO_INT_FLAG_DTCRCERR : gd32f10x_sdio.h
  • SDIO_INT_FLAG_DTEND : gd32f10x_sdio.h
  • SDIO_INT_FLAG_DTTMOUT : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RFE : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RFF : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RFH : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RXDTVAL : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RXORE : gd32f10x_sdio.h
  • SDIO_INT_FLAG_RXRUN : gd32f10x_sdio.h
  • SDIO_INT_FLAG_SDIOINT : gd32f10x_sdio.h
  • SDIO_INT_FLAG_STBITE : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TFE : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TFF : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TFH : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TXDTVAL : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TXRUN : gd32f10x_sdio.h
  • SDIO_INT_FLAG_TXURE : gd32f10x_sdio.h
  • SDIO_INT_RFE : gd32f10x_sdio.h
  • SDIO_INT_RFF : gd32f10x_sdio.h
  • SDIO_INT_RFH : gd32f10x_sdio.h
  • SDIO_INT_RXDTVAL : gd32f10x_sdio.h
  • SDIO_INT_RXORE : gd32f10x_sdio.h
  • SDIO_INT_RXRUN : gd32f10x_sdio.h
  • SDIO_INT_SDIOINT : gd32f10x_sdio.h
  • SDIO_INT_STBITE : gd32f10x_sdio.h
  • SDIO_INT_TFE : gd32f10x_sdio.h
  • SDIO_INT_TFF : gd32f10x_sdio.h
  • SDIO_INT_TFH : gd32f10x_sdio.h
  • SDIO_INT_TXDTVAL : gd32f10x_sdio.h
  • SDIO_INT_TXRUN : gd32f10x_sdio.h
  • SDIO_INT_TXURE : gd32f10x_sdio.h
  • SDIO_INTC : gd32f10x_sdio.h
  • SDIO_INTC_ATAENDC : gd32f10x_sdio.h
  • SDIO_INTC_CCRCERRC : gd32f10x_sdio.h
  • SDIO_INTC_CMDRECVC : gd32f10x_sdio.h
  • SDIO_INTC_CMDSENDC : gd32f10x_sdio.h
  • SDIO_INTC_CMDTMOUTC : gd32f10x_sdio.h
  • SDIO_INTC_DTBLKENDC : gd32f10x_sdio.h
  • SDIO_INTC_DTCRCERRC : gd32f10x_sdio.h
  • SDIO_INTC_DTENDC : gd32f10x_sdio.h
  • SDIO_INTC_DTTMOUTC : gd32f10x_sdio.h
  • SDIO_INTC_RXOREC : gd32f10x_sdio.h
  • SDIO_INTC_SDIOINTC : gd32f10x_sdio.h
  • SDIO_INTC_STBITEC : gd32f10x_sdio.h
  • SDIO_INTC_TXUREC : gd32f10x_sdio.h
  • SDIO_INTEN : gd32f10x_sdio.h
  • SDIO_INTEN_ATAENDIE : gd32f10x_sdio.h
  • SDIO_INTEN_CCRCERRIE : gd32f10x_sdio.h
  • SDIO_INTEN_CMDRECVIE : gd32f10x_sdio.h
  • SDIO_INTEN_CMDRUNIE : gd32f10x_sdio.h
  • SDIO_INTEN_CMDSENDIE : gd32f10x_sdio.h
  • SDIO_INTEN_CMDTMOUTIE : gd32f10x_sdio.h
  • SDIO_INTEN_DTBLKENDIE : gd32f10x_sdio.h
  • SDIO_INTEN_DTCRCERRIE : gd32f10x_sdio.h
  • SDIO_INTEN_DTENDIE : gd32f10x_sdio.h
  • SDIO_INTEN_DTTMOUTIE : gd32f10x_sdio.h
  • SDIO_INTEN_RFEIE : gd32f10x_sdio.h
  • SDIO_INTEN_RFFIE : gd32f10x_sdio.h
  • SDIO_INTEN_RFHIE : gd32f10x_sdio.h
  • SDIO_INTEN_RXDTVALIE : gd32f10x_sdio.h
  • SDIO_INTEN_RXOREIE : gd32f10x_sdio.h
  • SDIO_INTEN_RXRUNIE : gd32f10x_sdio.h
  • SDIO_INTEN_SDIOINTIE : gd32f10x_sdio.h
  • SDIO_INTEN_STBITEIE : gd32f10x_sdio.h
  • SDIO_INTEN_TFEIE : gd32f10x_sdio.h
  • SDIO_INTEN_TFFIE : gd32f10x_sdio.h
  • SDIO_INTEN_TFHIE : gd32f10x_sdio.h
  • SDIO_INTEN_TXDTVALIE : gd32f10x_sdio.h
  • SDIO_INTEN_TXRUNIE : gd32f10x_sdio.h
  • SDIO_INTEN_TXUREIE : gd32f10x_sdio.h
  • SDIO_POWER_OFF : gd32f10x_sdio.h
  • SDIO_POWER_ON : gd32f10x_sdio.h
  • SDIO_PWRCTL : gd32f10x_sdio.h
  • SDIO_PWRCTL_PWRCTL : gd32f10x_sdio.h
  • SDIO_READWAITTYPE_CLK : gd32f10x_sdio.h
  • SDIO_READWAITTYPE_DAT2 : gd32f10x_sdio.h
  • SDIO_RESP0 : gd32f10x_sdio.h
  • SDIO_RESP1 : gd32f10x_sdio.h
  • SDIO_RESP2 : gd32f10x_sdio.h
  • SDIO_RESP3 : gd32f10x_sdio.h
  • SDIO_RESPONSE0 : gd32f10x_sdio.h
  • SDIO_RESPONSE1 : gd32f10x_sdio.h
  • SDIO_RESPONSE2 : gd32f10x_sdio.h
  • SDIO_RESPONSE3 : gd32f10x_sdio.h
  • SDIO_RESPONSETYPE_LONG : gd32f10x_sdio.h
  • SDIO_RESPONSETYPE_NO : gd32f10x_sdio.h
  • SDIO_RESPONSETYPE_SHORT : gd32f10x_sdio.h
  • SDIO_RSPCMDIDX : gd32f10x_sdio.h
  • SDIO_SDIOCLKEDGE_FALLING : gd32f10x_sdio.h
  • SDIO_SDIOCLKEDGE_RISING : gd32f10x_sdio.h
  • SDIO_STAT : gd32f10x_sdio.h
  • SDIO_STAT_ATAEND : gd32f10x_sdio.h
  • SDIO_STAT_CCRCERR : gd32f10x_sdio.h
  • SDIO_STAT_CMDRECV : gd32f10x_sdio.h
  • SDIO_STAT_CMDRUN : gd32f10x_sdio.h
  • SDIO_STAT_CMDSEND : gd32f10x_sdio.h
  • SDIO_STAT_CMDTMOUT : gd32f10x_sdio.h
  • SDIO_STAT_DTBLKEND : gd32f10x_sdio.h
  • SDIO_STAT_DTCRCERR : gd32f10x_sdio.h
  • SDIO_STAT_DTEND : gd32f10x_sdio.h
  • SDIO_STAT_DTTMOUT : gd32f10x_sdio.h
  • SDIO_STAT_RFE : gd32f10x_sdio.h
  • SDIO_STAT_RFF : gd32f10x_sdio.h
  • SDIO_STAT_RFH : gd32f10x_sdio.h
  • SDIO_STAT_RXDTVAL : gd32f10x_sdio.h
  • SDIO_STAT_RXORE : gd32f10x_sdio.h
  • SDIO_STAT_RXRUN : gd32f10x_sdio.h
  • SDIO_STAT_SDIOINT : gd32f10x_sdio.h
  • SDIO_STAT_STBITE : gd32f10x_sdio.h
  • SDIO_STAT_TFE : gd32f10x_sdio.h
  • SDIO_STAT_TFF : gd32f10x_sdio.h
  • SDIO_STAT_TFH : gd32f10x_sdio.h
  • SDIO_STAT_TXDTVAL : gd32f10x_sdio.h
  • SDIO_STAT_TXRUN : gd32f10x_sdio.h
  • SDIO_STAT_TXURE : gd32f10x_sdio.h
  • SDIO_TRANSDIRECTION_TOCARD : gd32f10x_sdio.h
  • SDIO_TRANSDIRECTION_TOSDIO : gd32f10x_sdio.h
  • SDIO_TRANSMODE_BLOCK : gd32f10x_sdio.h
  • SDIO_TRANSMODE_STREAM : gd32f10x_sdio.h
  • SDIO_WAITTYPE_DATAEND : gd32f10x_sdio.h
  • SDIO_WAITTYPE_INTERRUPT : gd32f10x_sdio.h
  • SDIO_WAITTYPE_NO : gd32f10x_sdio.h
  • SEL_HXTAL : gd32f10x_rcu.c
  • SEL_IRC8M : gd32f10x_rcu.c
  • SEL_PLL : gd32f10x_rcu.c
  • SMCFG_ETPSC : gd32f10x_timer.h
  • SMCFG_SMC : gd32f10x_timer.h
  • SMCFG_TRGSEL : gd32f10x_timer.h
  • SNCTL_ASYNCWAIT_OFFSET : gd32f10x_exmc.c
  • SNCTL_EXMODEN_OFFSET : gd32f10x_exmc.c
  • SNCTL_NRMUX_OFFSET : gd32f10x_exmc.c
  • SNCTL_NRTP : gd32f10x_exmc.h
  • SNCTL_NRW : gd32f10x_exmc.h
  • SNCTL_NRWTEN_OFFSET : gd32f10x_exmc.c
  • SNCTL_SBRSTEN_OFFSET : gd32f10x_exmc.c
  • SNCTL_WRAPEN_OFFSET : gd32f10x_exmc.c
  • SNCTL_WREN_OFFSET : gd32f10x_exmc.c
  • SNTCFG_AHLD_OFFSET : gd32f10x_exmc.c
  • SNTCFG_ASYNCMOD : gd32f10x_exmc.h
  • SNTCFG_BUSLAT_OFFSET : gd32f10x_exmc.c
  • SNTCFG_CKDIV : gd32f10x_exmc.h
  • SNTCFG_DLAT : gd32f10x_exmc.h
  • SNTCFG_DSET_OFFSET : gd32f10x_exmc.c
  • SNWTCFG_WAHLD_OFFSET : gd32f10x_exmc.c
  • SNWTCFG_WBUSLAT_OFFSET : gd32f10x_exmc.c
  • SNWTCFG_WDSET_OFFSET : gd32f10x_exmc.c
  • SPI0 : gd32f10x_spi.h
  • SPI1 : gd32f10x_spi.h
  • SPI2 : gd32f10x_spi.h
  • SPI_BIDIRECTIONAL_RECEIVE : gd32f10x_spi.h
  • SPI_BIDIRECTIONAL_TRANSMIT : gd32f10x_spi.h
  • SPI_CK_PL_HIGH_PH_1EDGE : gd32f10x_spi.h
  • SPI_CK_PL_HIGH_PH_2EDGE : gd32f10x_spi.h
  • SPI_CK_PL_LOW_PH_1EDGE : gd32f10x_spi.h
  • SPI_CK_PL_LOW_PH_2EDGE : gd32f10x_spi.h
  • SPI_CRC_RX : gd32f10x_spi.h
  • SPI_CRC_TX : gd32f10x_spi.h
  • SPI_CRCPOLY : gd32f10x_spi.h
  • SPI_CRCPOLY_CPR : gd32f10x_spi.h
  • SPI_CTL0 : gd32f10x_spi.h
  • SPI_CTL0_BDEN : gd32f10x_spi.h
  • SPI_CTL0_BDOEN : gd32f10x_spi.h
  • SPI_CTL0_CKPH : gd32f10x_spi.h
  • SPI_CTL0_CKPL : gd32f10x_spi.h
  • SPI_CTL0_CRCEN : gd32f10x_spi.h
  • SPI_CTL0_CRCNT : gd32f10x_spi.h
  • SPI_CTL0_FF16 : gd32f10x_spi.h
  • SPI_CTL0_LF : gd32f10x_spi.h
  • SPI_CTL0_MSTMOD : gd32f10x_spi.h
  • SPI_CTL0_PSC : gd32f10x_spi.h
  • SPI_CTL0_RO : gd32f10x_spi.h
  • SPI_CTL0_SPIEN : gd32f10x_spi.h
  • SPI_CTL0_SWNSS : gd32f10x_spi.h
  • SPI_CTL0_SWNSSEN : gd32f10x_spi.h
  • SPI_CTL1 : gd32f10x_spi.h
  • SPI_CTL1_DMAREN : gd32f10x_spi.h
  • SPI_CTL1_DMATEN : gd32f10x_spi.h
  • SPI_CTL1_ERRIE : gd32f10x_spi.h
  • SPI_CTL1_NSSDRV : gd32f10x_spi.h
  • SPI_CTL1_RBNEIE : gd32f10x_spi.h
  • SPI_CTL1_TBEIE : gd32f10x_spi.h
  • SPI_DATA : gd32f10x_spi.h
  • SPI_DATA_DATA : gd32f10x_spi.h
  • SPI_DMA_RECEIVE : gd32f10x_spi.h
  • SPI_DMA_TRANSMIT : gd32f10x_spi.h
  • SPI_ENDIAN_LSB : gd32f10x_spi.h
  • SPI_ENDIAN_MSB : gd32f10x_spi.h
  • SPI_FLAG_CONFERR : gd32f10x_spi.h
  • SPI_FLAG_CRCERR : gd32f10x_spi.h
  • SPI_FLAG_RBNE : gd32f10x_spi.h
  • SPI_FLAG_RXORERR : gd32f10x_spi.h
  • SPI_FLAG_TBE : gd32f10x_spi.h
  • SPI_FLAG_TRANS : gd32f10x_spi.h
  • SPI_FRAMESIZE_16BIT : gd32f10x_spi.h
  • SPI_FRAMESIZE_8BIT : gd32f10x_spi.h
  • SPI_I2S_INT_ERR : gd32f10x_spi.h
  • SPI_I2S_INT_FLAG_RBNE : gd32f10x_spi.h
  • SPI_I2S_INT_FLAG_RXORERR : gd32f10x_spi.h
  • SPI_I2S_INT_FLAG_TBE : gd32f10x_spi.h
  • SPI_I2S_INT_RBNE : gd32f10x_spi.h
  • SPI_I2S_INT_TBE : gd32f10x_spi.h
  • SPI_I2SCTL : gd32f10x_spi.h
  • SPI_I2SCTL_CHLEN : gd32f10x_spi.h
  • SPI_I2SCTL_CKPL : gd32f10x_spi.h
  • SPI_I2SCTL_DTLEN : gd32f10x_spi.h
  • SPI_I2SCTL_I2SEN : gd32f10x_spi.h
  • SPI_I2SCTL_I2SOPMOD : gd32f10x_spi.h
  • SPI_I2SCTL_I2SSEL : gd32f10x_spi.h
  • SPI_I2SCTL_I2SSTD : gd32f10x_spi.h
  • SPI_I2SCTL_PCMSMOD : gd32f10x_spi.h
  • SPI_I2SPSC : gd32f10x_spi.h
  • SPI_I2SPSC_DIV : gd32f10x_spi.h
  • SPI_I2SPSC_MCKOEN : gd32f10x_spi.h
  • SPI_I2SPSC_OF : gd32f10x_spi.h
  • SPI_INIT_MASK : gd32f10x_spi.c
  • SPI_INT_FLAG_CONFERR : gd32f10x_spi.h
  • SPI_INT_FLAG_CRCERR : gd32f10x_spi.h
  • SPI_MASTER : gd32f10x_spi.h
  • SPI_NSS_HARD : gd32f10x_spi.h
  • SPI_NSS_SOFT : gd32f10x_spi.h
  • SPI_PSC_128 : gd32f10x_spi.h
  • SPI_PSC_16 : gd32f10x_spi.h
  • SPI_PSC_2 : gd32f10x_spi.h
  • SPI_PSC_256 : gd32f10x_spi.h
  • SPI_PSC_32 : gd32f10x_spi.h
  • SPI_PSC_4 : gd32f10x_spi.h
  • SPI_PSC_64 : gd32f10x_spi.h
  • SPI_PSC_8 : gd32f10x_spi.h
  • SPI_RCRC : gd32f10x_spi.h
  • SPI_RCRC_RCR : gd32f10x_spi.h
  • SPI_SLAVE : gd32f10x_spi.h
  • SPI_STAT : gd32f10x_spi.h
  • SPI_STAT_CONFERR : gd32f10x_spi.h
  • SPI_STAT_CRCERR : gd32f10x_spi.h
  • SPI_STAT_I2SCH : gd32f10x_spi.h
  • SPI_STAT_RBNE : gd32f10x_spi.h
  • SPI_STAT_RXORERR : gd32f10x_spi.h
  • SPI_STAT_TBE : gd32f10x_spi.h
  • SPI_STAT_TRANS : gd32f10x_spi.h
  • SPI_STAT_TXURERR : gd32f10x_spi.h
  • SPI_TCRC : gd32f10x_spi.h
  • SPI_TCRC_TCR : gd32f10x_spi.h
  • SPI_TRANSMODE_BDRECEIVE : gd32f10x_spi.h
  • SPI_TRANSMODE_BDTRANSMIT : gd32f10x_spi.h
  • SPI_TRANSMODE_FULLDUPLEX : gd32f10x_spi.h
  • SPI_TRANSMODE_RECEIVEONLY : gd32f10x_spi.h
  • STAT_FCNT : usbd_regs.h
  • STAT_LOCK : usbd_regs.h
  • STAT_REG_OFFSET : gd32f10x_can.h
  • STAT_RXDM : usbd_regs.h
  • STAT_RXDP : usbd_regs.h
  • STAT_SOFLN : usbd_regs.h
  • SWAPBYTE : usb_std.h , usbd_std.h
  • SYSTICK_CLKSOURCE_HCLK : gd32f10x_misc.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : gd32f10x_misc.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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- t -

  • TAMPER_FLAG_SHIFT : gd32f10x_bkp.c
  • TAMPER_PIN_ACTIVE_HIGH : gd32f10x_bkp.h
  • TAMPER_PIN_ACTIVE_LOW : gd32f10x_bkp.h
  • TDES0_CM : gd32f10x_enet.h
  • TDES0_CONT : gd32f10x_enet.h
  • TDES1_TB1S : gd32f10x_enet.h
  • TDES1_TB2S : gd32f10x_enet.h
  • TIMER0 : gd32f10x_timer.h
  • TIMER1 : gd32f10x_timer.h
  • TIMER10 : gd32f10x_timer.h
  • TIMER11 : gd32f10x_timer.h
  • TIMER12 : gd32f10x_timer.h
  • TIMER13 : gd32f10x_timer.h
  • TIMER2 : gd32f10x_timer.h
  • TIMER3 : gd32f10x_timer.h
  • TIMER4 : gd32f10x_timer.h
  • TIMER5 : gd32f10x_timer.h
  • TIMER6 : gd32f10x_timer.h
  • TIMER7 : gd32f10x_timer.h
  • TIMER8 : gd32f10x_timer.h
  • TIMER9 : gd32f10x_timer.h
  • TIMER_BREAK_DISABLE : gd32f10x_timer.h
  • TIMER_BREAK_ENABLE : gd32f10x_timer.h
  • TIMER_BREAK_POLARITY_HIGH : gd32f10x_timer.h
  • TIMER_BREAK_POLARITY_LOW : gd32f10x_timer.h
  • TIMER_CAR : gd32f10x_timer.h
  • TIMER_CAR_CARL : gd32f10x_timer.h
  • TIMER_CCHP : gd32f10x_timer.h
  • TIMER_CCHP_BRKEN : gd32f10x_timer.h
  • TIMER_CCHP_BRKP : gd32f10x_timer.h
  • TIMER_CCHP_DTCFG : gd32f10x_timer.h
  • TIMER_CCHP_IOS : gd32f10x_timer.h
  • TIMER_CCHP_OAEN : gd32f10x_timer.h
  • TIMER_CCHP_POEN : gd32f10x_timer.h
  • TIMER_CCHP_PROT : gd32f10x_timer.h
  • TIMER_CCHP_PROT_0 : gd32f10x_timer.h
  • TIMER_CCHP_PROT_1 : gd32f10x_timer.h
  • TIMER_CCHP_PROT_2 : gd32f10x_timer.h
  • TIMER_CCHP_PROT_OFF : gd32f10x_timer.h
  • TIMER_CCHP_ROS : gd32f10x_timer.h
  • TIMER_CCX_DISABLE : gd32f10x_timer.h
  • TIMER_CCX_ENABLE : gd32f10x_timer.h
  • TIMER_CCXN_DISABLE : gd32f10x_timer.h
  • TIMER_CCXN_ENABLE : gd32f10x_timer.h
  • TIMER_CH0CV : gd32f10x_timer.h
  • TIMER_CH0CV_CH0VAL : gd32f10x_timer.h
  • TIMER_CH1CV : gd32f10x_timer.h
  • TIMER_CH1CV_CH1VAL : gd32f10x_timer.h
  • TIMER_CH2CV : gd32f10x_timer.h
  • TIMER_CH2CV_CH2VAL : gd32f10x_timer.h
  • TIMER_CH3CV : gd32f10x_timer.h
  • TIMER_CH3CV_CH3VAL : gd32f10x_timer.h
  • TIMER_CH_0 : gd32f10x_timer.h
  • TIMER_CH_1 : gd32f10x_timer.h
  • TIMER_CH_2 : gd32f10x_timer.h
  • TIMER_CH_3 : gd32f10x_timer.h
  • TIMER_CHCTL0 : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0CAPFLT : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0CAPPSC : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0COMCEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0COMCTL : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0COMFEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0COMSEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH0MS : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1CAPFLT : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1CAPPSC : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1COMCEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1COMCTL : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1COMFEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1COMSEN : gd32f10x_timer.h
  • TIMER_CHCTL0_CH1MS : gd32f10x_timer.h
  • TIMER_CHCTL1 : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2CAPFLT : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2CAPPSC : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2COMCEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2COMCTL : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2COMFEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2COMSEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH2MS : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3CAPFLT : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3CAPPSC : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3COMCEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3COMCTL : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3COMFEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3COMSEN : gd32f10x_timer.h
  • TIMER_CHCTL1_CH3MS : gd32f10x_timer.h
  • TIMER_CHCTL2 : gd32f10x_timer.h
  • TIMER_CHCTL2_CH0EN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH0NEN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH0NP : gd32f10x_timer.h
  • TIMER_CHCTL2_CH0P : gd32f10x_timer.h
  • TIMER_CHCTL2_CH1EN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH1NEN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH1NP : gd32f10x_timer.h
  • TIMER_CHCTL2_CH1P : gd32f10x_timer.h
  • TIMER_CHCTL2_CH2EN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH2NEN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH2NP : gd32f10x_timer.h
  • TIMER_CHCTL2_CH2P : gd32f10x_timer.h
  • TIMER_CHCTL2_CH3EN : gd32f10x_timer.h
  • TIMER_CHCTL2_CH3P : gd32f10x_timer.h
  • TIMER_CKDIV_DIV1 : gd32f10x_timer.h
  • TIMER_CKDIV_DIV2 : gd32f10x_timer.h
  • TIMER_CKDIV_DIV4 : gd32f10x_timer.h
  • TIMER_CNT : gd32f10x_timer.h
  • TIMER_CNT_CNT : gd32f10x_timer.h
  • TIMER_COUNTER_CENTER_BOTH : gd32f10x_timer.h
  • TIMER_COUNTER_CENTER_DOWN : gd32f10x_timer.h
  • TIMER_COUNTER_CENTER_UP : gd32f10x_timer.h
  • TIMER_COUNTER_DOWN : gd32f10x_timer.h
  • TIMER_COUNTER_EDGE : gd32f10x_timer.h
  • TIMER_COUNTER_UP : gd32f10x_timer.h
  • TIMER_CREP : gd32f10x_timer.h
  • TIMER_CREP_CREP : gd32f10x_timer.h
  • TIMER_CTL0 : gd32f10x_timer.h
  • TIMER_CTL0_ARSE : gd32f10x_timer.h
  • TIMER_CTL0_CAM : gd32f10x_timer.h
  • TIMER_CTL0_CEN : gd32f10x_timer.h
  • TIMER_CTL0_CKDIV : gd32f10x_timer.h
  • TIMER_CTL0_DIR : gd32f10x_timer.h
  • TIMER_CTL0_SPM : gd32f10x_timer.h
  • TIMER_CTL0_UPDIS : gd32f10x_timer.h
  • TIMER_CTL0_UPS : gd32f10x_timer.h
  • TIMER_CTL1 : gd32f10x_timer.h
  • TIMER_CTL1_CCSE : gd32f10x_timer.h
  • TIMER_CTL1_CCUC : gd32f10x_timer.h
  • TIMER_CTL1_DMAS : gd32f10x_timer.h
  • TIMER_CTL1_ISO0 : gd32f10x_timer.h
  • TIMER_CTL1_ISO0N : gd32f10x_timer.h
  • TIMER_CTL1_ISO1 : gd32f10x_timer.h
  • TIMER_CTL1_ISO1N : gd32f10x_timer.h
  • TIMER_CTL1_ISO2 : gd32f10x_timer.h
  • TIMER_CTL1_ISO2N : gd32f10x_timer.h
  • TIMER_CTL1_ISO3 : gd32f10x_timer.h
  • TIMER_CTL1_MMC : gd32f10x_timer.h
  • TIMER_CTL1_TI0S : gd32f10x_timer.h
  • TIMER_DMA_CH0D : gd32f10x_timer.h
  • TIMER_DMA_CH1D : gd32f10x_timer.h
  • TIMER_DMA_CH2D : gd32f10x_timer.h
  • TIMER_DMA_CH3D : gd32f10x_timer.h
  • TIMER_DMA_CMTD : gd32f10x_timer.h
  • TIMER_DMA_TRGD : gd32f10x_timer.h
  • TIMER_DMA_UPD : gd32f10x_timer.h
  • TIMER_DMACFG : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CAR : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CCHP : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CH0CV : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CH1CV : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CH2CV : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CH3CV : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CHCTL0 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CHCTL1 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CHCTL2 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CNT : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CREP : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CTL0 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_CTL1 : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_DMACFG : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_DMAINTEN : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_DMATB : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_INTF : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_PSC : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_SMCFG : gd32f10x_timer.h
  • TIMER_DMACFG_DMATA_SWEVG : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_10TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_11TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_12TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_13TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_14TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_15TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_16TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_17TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_18TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_1TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_2TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_3TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_4TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_5TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_6TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_7TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_8TRANSFER : gd32f10x_timer.h
  • TIMER_DMACFG_DMATC_9TRANSFER : gd32f10x_timer.h
  • TIMER_DMAINTEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_BRKIE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH0DEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH0IE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH1DEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH1IE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH2DEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH2IE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH3DEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CH3IE : gd32f10x_timer.h
  • TIMER_DMAINTEN_CMTDEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_CMTIE : gd32f10x_timer.h
  • TIMER_DMAINTEN_TRGDEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_TRGIE : gd32f10x_timer.h
  • TIMER_DMAINTEN_UPDEN : gd32f10x_timer.h
  • TIMER_DMAINTEN_UPIE : gd32f10x_timer.h
  • TIMER_DMAREQUEST_CHANNELEVENT : gd32f10x_timer.h
  • TIMER_DMAREQUEST_UPDATEEVENT : gd32f10x_timer.h
  • TIMER_DMATB : gd32f10x_timer.h
  • TIMER_DMATB_DMATB : gd32f10x_timer.h
  • TIMER_ENCODER_MODE0 : gd32f10x_timer.h
  • TIMER_ENCODER_MODE1 : gd32f10x_timer.h
  • TIMER_ENCODER_MODE2 : gd32f10x_timer.h
  • TIMER_ETP_FALLING : gd32f10x_timer.h
  • TIMER_ETP_RISING : gd32f10x_timer.h
  • TIMER_EVENT_SRC_BRKG : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CH0G : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CH1G : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CH2G : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CH3G : gd32f10x_timer.h
  • TIMER_EVENT_SRC_CMTG : gd32f10x_timer.h
  • TIMER_EVENT_SRC_TRGG : gd32f10x_timer.h
  • TIMER_EVENT_SRC_UPG : gd32f10x_timer.h
  • TIMER_EXT_TRI_PSC_DIV2 : gd32f10x_timer.h
  • TIMER_EXT_TRI_PSC_DIV4 : gd32f10x_timer.h
  • TIMER_EXT_TRI_PSC_DIV8 : gd32f10x_timer.h
  • TIMER_EXT_TRI_PSC_OFF : gd32f10x_timer.h
  • TIMER_FLAG_BRK : gd32f10x_timer.h
  • TIMER_FLAG_CH0 : gd32f10x_timer.h
  • TIMER_FLAG_CH0O : gd32f10x_timer.h
  • TIMER_FLAG_CH1 : gd32f10x_timer.h
  • TIMER_FLAG_CH1O : gd32f10x_timer.h
  • TIMER_FLAG_CH2 : gd32f10x_timer.h
  • TIMER_FLAG_CH2O : gd32f10x_timer.h
  • TIMER_FLAG_CH3 : gd32f10x_timer.h
  • TIMER_FLAG_CH3O : gd32f10x_timer.h
  • TIMER_FLAG_CMT : gd32f10x_timer.h
  • TIMER_FLAG_TRG : gd32f10x_timer.h
  • TIMER_FLAG_UP : gd32f10x_timer.h
  • TIMER_HALLINTERFACE_DISABLE : gd32f10x_timer.h
  • TIMER_HALLINTERFACE_ENABLE : gd32f10x_timer.h
  • TIMER_IC_POLARITY_BOTH_EDGE : gd32f10x_timer.h
  • TIMER_IC_POLARITY_FALLING : gd32f10x_timer.h
  • TIMER_IC_POLARITY_RISING : gd32f10x_timer.h
  • TIMER_IC_PSC_DIV1 : gd32f10x_timer.h
  • TIMER_IC_PSC_DIV2 : gd32f10x_timer.h
  • TIMER_IC_PSC_DIV4 : gd32f10x_timer.h
  • TIMER_IC_PSC_DIV8 : gd32f10x_timer.h
  • TIMER_IC_SELECTION_DIRECTTI : gd32f10x_timer.h
  • TIMER_IC_SELECTION_INDIRECTTI : gd32f10x_timer.h
  • TIMER_IC_SELECTION_ITS : gd32f10x_timer.h
  • TIMER_INT_BRK : gd32f10x_timer.h
  • TIMER_INT_CH0 : gd32f10x_timer.h
  • TIMER_INT_CH1 : gd32f10x_timer.h
  • TIMER_INT_CH2 : gd32f10x_timer.h
  • TIMER_INT_CH3 : gd32f10x_timer.h
  • TIMER_INT_CMT : gd32f10x_timer.h
  • TIMER_INT_FLAG_BRK : gd32f10x_timer.h
  • TIMER_INT_FLAG_CH0 : gd32f10x_timer.h
  • TIMER_INT_FLAG_CH1 : gd32f10x_timer.h
  • TIMER_INT_FLAG_CH2 : gd32f10x_timer.h
  • TIMER_INT_FLAG_CH3 : gd32f10x_timer.h
  • TIMER_INT_FLAG_CMT : gd32f10x_timer.h
  • TIMER_INT_FLAG_TRG : gd32f10x_timer.h
  • TIMER_INT_FLAG_UP : gd32f10x_timer.h
  • TIMER_INT_TRG : gd32f10x_timer.h
  • TIMER_INT_UP : gd32f10x_timer.h
  • TIMER_INTF : gd32f10x_timer.h
  • TIMER_INTF_BRKIF : gd32f10x_timer.h
  • TIMER_INTF_CH0IF : gd32f10x_timer.h
  • TIMER_INTF_CH0OF : gd32f10x_timer.h
  • TIMER_INTF_CH1IF : gd32f10x_timer.h
  • TIMER_INTF_CH1OF : gd32f10x_timer.h
  • TIMER_INTF_CH2IF : gd32f10x_timer.h
  • TIMER_INTF_CH2OF : gd32f10x_timer.h
  • TIMER_INTF_CH3IF : gd32f10x_timer.h
  • TIMER_INTF_CH3OF : gd32f10x_timer.h
  • TIMER_INTF_CMTIF : gd32f10x_timer.h
  • TIMER_INTF_TRGIF : gd32f10x_timer.h
  • TIMER_INTF_UPIF : gd32f10x_timer.h
  • TIMER_IOS_STATE_DISABLE : gd32f10x_timer.h
  • TIMER_IOS_STATE_ENABLE : gd32f10x_timer.h
  • TIMER_MASTER_SLAVE_MODE_DISABLE : gd32f10x_timer.h
  • TIMER_MASTER_SLAVE_MODE_ENABLE : gd32f10x_timer.h
  • TIMER_OC_CLEAR_DISABLE : gd32f10x_timer.h
  • TIMER_OC_CLEAR_ENABLE : gd32f10x_timer.h
  • TIMER_OC_FAST_DISABLE : gd32f10x_timer.h
  • TIMER_OC_FAST_ENABLE : gd32f10x_timer.h
  • TIMER_OC_IDLE_STATE_HIGH : gd32f10x_timer.h
  • TIMER_OC_IDLE_STATE_LOW : gd32f10x_timer.h
  • TIMER_OC_MODE_ACTIVE : gd32f10x_timer.h
  • TIMER_OC_MODE_HIGH : gd32f10x_timer.h
  • TIMER_OC_MODE_INACTIVE : gd32f10x_timer.h
  • TIMER_OC_MODE_LOW : gd32f10x_timer.h
  • TIMER_OC_MODE_PWM0 : gd32f10x_timer.h
  • TIMER_OC_MODE_PWM1 : gd32f10x_timer.h
  • TIMER_OC_MODE_TIMING : gd32f10x_timer.h
  • TIMER_OC_MODE_TOGGLE : gd32f10x_timer.h
  • TIMER_OC_POLARITY_HIGH : gd32f10x_timer.h
  • TIMER_OC_POLARITY_LOW : gd32f10x_timer.h
  • TIMER_OC_SHADOW_DISABLE : gd32f10x_timer.h
  • TIMER_OC_SHADOW_ENABLE : gd32f10x_timer.h
  • TIMER_OCN_IDLE_STATE_HIGH : gd32f10x_timer.h
  • TIMER_OCN_IDLE_STATE_LOW : gd32f10x_timer.h
  • TIMER_OCN_POLARITY_HIGH : gd32f10x_timer.h
  • TIMER_OCN_POLARITY_LOW : gd32f10x_timer.h
  • TIMER_OUTAUTO_DISABLE : gd32f10x_timer.h
  • TIMER_OUTAUTO_ENABLE : gd32f10x_timer.h
  • TIMER_PSC : gd32f10x_timer.h
  • TIMER_PSC_PSC : gd32f10x_timer.h
  • TIMER_PSC_RELOAD_NOW : gd32f10x_timer.h
  • TIMER_PSC_RELOAD_UPDATE : gd32f10x_timer.h
  • TIMER_ROS_STATE_DISABLE : gd32f10x_timer.h
  • TIMER_ROS_STATE_ENABLE : gd32f10x_timer.h
  • TIMER_SLAVE_MODE_DISABLE : gd32f10x_timer.h
  • TIMER_SLAVE_MODE_EVENT : gd32f10x_timer.h
  • TIMER_SLAVE_MODE_EXTERNAL0 : gd32f10x_timer.h
  • TIMER_SLAVE_MODE_PAUSE : gd32f10x_timer.h
  • TIMER_SLAVE_MODE_RESTART : gd32f10x_timer.h
  • TIMER_SMCFG : gd32f10x_timer.h
  • TIMER_SMCFG_ETFC : gd32f10x_timer.h
  • TIMER_SMCFG_ETP : gd32f10x_timer.h
  • TIMER_SMCFG_ETPSC : gd32f10x_timer.h
  • TIMER_SMCFG_MSM : gd32f10x_timer.h
  • TIMER_SMCFG_SMC : gd32f10x_timer.h
  • TIMER_SMCFG_SMC1 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGS : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_CI0F_ED : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_CI0FE0 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_CI1FE1 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ETIFP : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ITI0 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ITI1 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ITI2 : gd32f10x_timer.h
  • TIMER_SMCFG_TRGSEL_ITI3 : gd32f10x_timer.h
  • TIMER_SP_MODE_REPETITIVE : gd32f10x_timer.h
  • TIMER_SP_MODE_SINGLE : gd32f10x_timer.h
  • TIMER_SWEVG : gd32f10x_timer.h
  • TIMER_SWEVG_BRKG : gd32f10x_timer.h
  • TIMER_SWEVG_CH0G : gd32f10x_timer.h
  • TIMER_SWEVG_CH1G : gd32f10x_timer.h
  • TIMER_SWEVG_CH2G : gd32f10x_timer.h
  • TIMER_SWEVG_CH3G : gd32f10x_timer.h
  • TIMER_SWEVG_CMTG : gd32f10x_timer.h
  • TIMER_SWEVG_TRGG : gd32f10x_timer.h
  • TIMER_SWEVG_UPG : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_CC0 : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_ENABLE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_O0CPRE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_O1CPRE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_O2CPRE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_O3CPRE : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_RESET : gd32f10x_timer.h
  • TIMER_TRI_OUT_SRC_UPDATE : gd32f10x_timer.h
  • TIMER_UPDATE_SRC_GLOBAL : gd32f10x_timer.h
  • TIMER_UPDATE_SRC_REGULAR : gd32f10x_timer.h
  • TIMER_UPDATECTL_CCU : gd32f10x_timer.h
  • TIMER_UPDATECTL_CCUTRI : gd32f10x_timer.h
  • TMDATA0_DB0 : gd32f10x_can.h
  • TMDATA0_DB1 : gd32f10x_can.h
  • TMDATA0_DB2 : gd32f10x_can.h
  • TMDATA0_DB3 : gd32f10x_can.h
  • TMDATA1_DB4 : gd32f10x_can.h
  • TMDATA1_DB5 : gd32f10x_can.h
  • TMDATA1_DB6 : gd32f10x_can.h
  • TMDATA1_DB7 : gd32f10x_can.h
  • TMI_EFID : gd32f10x_can.h
  • TMI_SFID : gd32f10x_can.h
  • TRACE_MODE_ASYNC : gd32f10x_dbg.h
  • TRACE_MODE_SYNC_DATASIZE_1 : gd32f10x_dbg.h
  • TRACE_MODE_SYNC_DATASIZE_2 : gd32f10x_dbg.h
  • TRACE_MODE_SYNC_DATASIZE_4 : gd32f10x_dbg.h
  • TSTAT_REG_OFFSET : gd32f10x_can.h
  • TXCNT_OFFSET : usbd_regs.h
  • TXFIFO_EMPTY : usb_regs.h
  • TXFIFO_EMPTY_HALF : usb_regs.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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- u -

  • UART3 : gd32f10x_usart.h
  • UART4 : gd32f10x_usart.h
  • UNLOCK_KEY0 : gd32f10x_fmc.h
  • UNLOCK_KEY1 : gd32f10x_fmc.h
  • UP_STATE : usbh_core.h
  • USART0 : gd32f10x_usart.h
  • USART1 : gd32f10x_usart.h
  • USART2 : gd32f10x_usart.h
  • USART_BAUD : gd32f10x_usart.h
  • USART_BAUD_FRADIV : gd32f10x_usart.h
  • USART_BAUD_INTDIV : gd32f10x_usart.h
  • USART_BIT_POS : gd32f10x_usart.h
  • USART_BIT_POS2 : gd32f10x_usart.h
  • USART_CLEN_EN : gd32f10x_usart.h
  • USART_CLEN_NONE : gd32f10x_usart.h
  • USART_CPH_1CK : gd32f10x_usart.h
  • USART_CPH_2CK : gd32f10x_usart.h
  • USART_CPL_HIGH : gd32f10x_usart.h
  • USART_CPL_LOW : gd32f10x_usart.h
  • USART_CTL0 : gd32f10x_usart.h
  • USART_CTL0_IDLEIE : gd32f10x_usart.h
  • USART_CTL0_PCEN : gd32f10x_usart.h
  • USART_CTL0_PERRIE : gd32f10x_usart.h
  • USART_CTL0_PM : gd32f10x_usart.h
  • USART_CTL0_RBNEIE : gd32f10x_usart.h
  • USART_CTL0_REG_OFFSET : gd32f10x_usart.h
  • USART_CTL0_REN : gd32f10x_usart.h
  • USART_CTL0_RWU : gd32f10x_usart.h
  • USART_CTL0_SBKCMD : gd32f10x_usart.h
  • USART_CTL0_TBEIE : gd32f10x_usart.h
  • USART_CTL0_TCIE : gd32f10x_usart.h
  • USART_CTL0_TEN : gd32f10x_usart.h
  • USART_CTL0_UEN : gd32f10x_usart.h
  • USART_CTL0_WL : gd32f10x_usart.h
  • USART_CTL0_WM : gd32f10x_usart.h
  • USART_CTL1 : gd32f10x_usart.h
  • USART_CTL1_ADDR : gd32f10x_usart.h
  • USART_CTL1_CKEN : gd32f10x_usart.h
  • USART_CTL1_CLEN : gd32f10x_usart.h
  • USART_CTL1_CPH : gd32f10x_usart.h
  • USART_CTL1_CPL : gd32f10x_usart.h
  • USART_CTL1_LBDIE : gd32f10x_usart.h
  • USART_CTL1_LBLEN : gd32f10x_usart.h
  • USART_CTL1_LMEN : gd32f10x_usart.h
  • USART_CTL1_REG_OFFSET : gd32f10x_usart.h
  • USART_CTL1_STB : gd32f10x_usart.h
  • USART_CTL2 : gd32f10x_usart.h
  • USART_CTL2_CTSEN : gd32f10x_usart.h
  • USART_CTL2_CTSIE : gd32f10x_usart.h
  • USART_CTL2_DENR : gd32f10x_usart.h
  • USART_CTL2_DENT : gd32f10x_usart.h
  • USART_CTL2_ERRIE : gd32f10x_usart.h
  • USART_CTL2_HDEN : gd32f10x_usart.h
  • USART_CTL2_IREN : gd32f10x_usart.h
  • USART_CTL2_IRLP : gd32f10x_usart.h
  • USART_CTL2_NKEN : gd32f10x_usart.h
  • USART_CTL2_REG_OFFSET : gd32f10x_usart.h
  • USART_CTL2_RTSEN : gd32f10x_usart.h
  • USART_CTL2_SCEN : gd32f10x_usart.h
  • USART_CTS_DISABLE : gd32f10x_usart.h
  • USART_CTS_ENABLE : gd32f10x_usart.h
  • USART_DATA : gd32f10x_usart.h
  • USART_DATA_DATA : gd32f10x_usart.h
  • USART_DENR_DISABLE : gd32f10x_usart.h
  • USART_DENR_ENABLE : gd32f10x_usart.h
  • USART_DENT_DISABLE : gd32f10x_usart.h
  • USART_DENT_ENABLE : gd32f10x_usart.h
  • USART_GP : gd32f10x_usart.h
  • USART_GP_GUAT : gd32f10x_usart.h
  • USART_GP_PSC : gd32f10x_usart.h
  • USART_IRLP_LOW : gd32f10x_usart.h
  • USART_IRLP_NORMAL : gd32f10x_usart.h
  • USART_LBLEN_10B : gd32f10x_usart.h
  • USART_LBLEN_11B : gd32f10x_usart.h
  • USART_PM_EVEN : gd32f10x_usart.h
  • USART_PM_NONE : gd32f10x_usart.h
  • USART_PM_ODD : gd32f10x_usart.h
  • USART_RECEIVE_DISABLE : gd32f10x_usart.h
  • USART_RECEIVE_ENABLE : gd32f10x_usart.h
  • USART_REG_VAL : gd32f10x_usart.h
  • USART_REG_VAL2 : gd32f10x_usart.h
  • USART_REGIDX_BIT : gd32f10x_usart.h
  • USART_REGIDX_BIT2 : gd32f10x_usart.h
  • USART_RTS_DISABLE : gd32f10x_usart.h
  • USART_RTS_ENABLE : gd32f10x_usart.h
  • USART_STAT : gd32f10x_usart.h
  • USART_STAT_CTSF : gd32f10x_usart.h
  • USART_STAT_FERR : gd32f10x_usart.h
  • USART_STAT_IDLEF : gd32f10x_usart.h
  • USART_STAT_LBDF : gd32f10x_usart.h
  • USART_STAT_NERR : gd32f10x_usart.h
  • USART_STAT_ORERR : gd32f10x_usart.h
  • USART_STAT_PERR : gd32f10x_usart.h
  • USART_STAT_RBNE : gd32f10x_usart.h
  • USART_STAT_REG_OFFSET : gd32f10x_usart.h
  • USART_STAT_TBE : gd32f10x_usart.h
  • USART_STAT_TC : gd32f10x_usart.h
  • USART_STB_0_5BIT : gd32f10x_usart.h
  • USART_STB_1_5BIT : gd32f10x_usart.h
  • USART_STB_1BIT : gd32f10x_usart.h
  • USART_STB_2BIT : gd32f10x_usart.h
  • USART_TRANSMIT_DISABLE : gd32f10x_usart.h
  • USART_TRANSMIT_ENABLE : gd32f10x_usart.h
  • USART_WL_8BIT : gd32f10x_usart.h
  • USART_WL_9BIT : gd32f10x_usart.h
  • USART_WM_ADDR : gd32f10x_usart.h
  • USART_WM_IDLE : gd32f10x_usart.h
  • USB_CFG_DESC_LEN : usbd_std.h , usb_std.h
  • USB_CFGDESC : usb_std.h
  • USB_CFGDESC_SIZE : usb_std.h
  • USB_CID : usb_regs.h
  • USB_CLASS_REQ : usbd_std.h , usb_std.h
  • USB_CORE_EMBEDDED_PHY : usb_defines.h
  • USB_CORE_INTR_READ : usb_regs.h
  • USB_CORE_SPEED_FULL : usb_defines.h
  • USB_CORE_SPEED_HIGH : usb_defines.h
  • USB_CORE_ULPI_PHY : usb_defines.h
  • USB_CURRENT_FRAME_GET : usb_regs.h
  • USB_CURRENT_MODE_GET : usb_regs.h
  • USB_CURRENT_SPEED_GET : usb_regs.h
  • USB_DAEPINT : usb_regs.h
  • USB_DAEPINTEN : usb_regs.h
  • USB_DAIEP_INTR_READ : usb_regs.h
  • USB_DAOEP_INTR_READ : usb_regs.h
  • USB_DCFG : usb_regs.h
  • USB_DCTL : usb_regs.h
  • USB_DEP1INT : usb_regs.h
  • USB_DEP1INTEN : usb_regs.h
  • USB_DESCTYPE_BOS : usbd_std.h
  • USB_DESCTYPE_CONFIGURATION : usbd_std.h , usb_std.h
  • USB_DESCTYPE_DEVICE : usbd_std.h , usb_std.h
  • USB_DESCTYPE_DEVICE_QUALIFIER : usbd_std.h , usb_std.h
  • USB_DESCTYPE_ENDPOINT : usbd_std.h , usb_std.h
  • USB_DESCTYPE_HID : usb_std.h
  • USB_DESCTYPE_HID_REPORT : usb_std.h
  • USB_DESCTYPE_INTERFACE : usbd_std.h , usb_std.h
  • USB_DESCTYPE_INTERFACE_POWER : usb_std.h
  • USB_DESCTYPE_OTHER_SPEED_CONFIGURATION : usbd_std.h , usb_std.h
  • USB_DESCTYPE_STRING : usbd_std.h , usb_std.h
  • USB_DEV_DESC_LEN : usb_std.h
  • USB_DEV_QUALIFIER_DESC_LEN : usbd_std.h , usb_std.h
  • USB_DEVDESC : usb_std.h
  • USB_DEVDESC_SIZE : usb_std.h
  • USB_DEVICE_DESC_SIZE : usbd_std.h
  • USB_DEVQUADESC : usb_std.h
  • USB_DIEP0CTL : usb_regs.h
  • USB_DIEP0LEN : usb_regs.h
  • USB_DIEP0TFLEN : usb_regs.h
  • USB_DIEP1INTEN : usb_regs.h
  • USB_DIEP_INTR_READ : usb_regs.h
  • USB_DIEPFEINTEN : usb_regs.h
  • USB_DIEPINTEN : usb_regs.h
  • USB_DIEPxCTL : usb_regs.h
  • USB_DIEPxINTF : usb_regs.h
  • USB_DIEPxLEN : usb_regs.h
  • USB_DIEPxTFLEN : usb_regs.h
  • USB_DIEPxTFSTAT : usb_regs.h
  • USB_DIR_IN : usb_std.h
  • USB_DIR_MASK : usb_std.h
  • USB_DIR_OUT : usb_std.h
  • USB_DOEP0CTL : usb_regs.h
  • USB_DOEP0LEN : usb_regs.h
  • USB_DOEP1INTEN : usb_regs.h
  • USB_DOEP_INTR_READ : usb_regs.h
  • USB_DOEPINTEN : usb_regs.h
  • USB_DOEPxCTL : usb_regs.h
  • USB_DOEPxINTF : usb_regs.h
  • USB_DOEPxLEN : usb_regs.h
  • USB_DSTAT : usb_regs.h
  • USB_DVBUSDT : usb_regs.h
  • USB_DVBUSPT : usb_regs.h
  • USB_EP_DESC_LEN : usb_std.h
  • USB_EPDESC : usb_std.h
  • USB_EPDESC_SIZE : usb_std.h
  • USB_EPTYPE_BULK : usb_defines.h
  • USB_EPTYPE_CTRL : usb_defines.h
  • USB_EPTYPE_INTR : usb_defines.h
  • USB_EPTYPE_ISOC : usb_defines.h
  • USB_EPTYPE_MASK : usb_defines.h , usbd_std.h
  • USB_EVEN_FRAME : usb_regs.h
  • USB_FEATURE_ENDP_HALT : usbd_std.h
  • USB_FEATURE_REMOTE_WAKEUP : usbd_std.h
  • USB_FEATURE_TEST_MODE : usbd_std.h
  • USB_FIFO : usb_regs.h
  • USB_FSLSCLOCK_INIT : usb_regs.h
  • USB_GAHBCS : usb_regs.h
  • USB_GCCFG : usb_regs.h
  • USB_GINTEN : usb_regs.h
  • USB_GINTF : usb_regs.h
  • USB_GLOBAL_INT_DISABLE : usb_regs.h
  • USB_GLOBAL_INT_ENABLE : usb_regs.h
  • USB_GOTGCS : usb_regs.h
  • USB_GOTGINTF : usb_regs.h
  • USB_GRFLEN : usb_regs.h
  • USB_GRSTATP : usb_regs.h
  • USB_GRSTATR : usb_regs.h
  • USB_GRSTCTL : usb_regs.h
  • USB_GUSBCS : usb_regs.h
  • USB_HACHINT : usb_regs.h
  • USB_HACHINTEN : usb_regs.h
  • USB_HCHxCTL : usb_regs.h
  • USB_HCHxINTEN : usb_regs.h
  • USB_HCHxINTF : usb_regs.h
  • USB_HCHxLEN : usb_regs.h
  • USB_HCTL : usb_regs.h
  • USB_HFINFR : usb_regs.h
  • USB_HFT : usb_regs.h
  • USB_HID_CLASS : usb_std.h
  • USB_HIDDESC : usb_std.h
  • USB_HIDREPDESC : usb_std.h
  • USB_HNPTFLEN : usb_regs.h
  • USB_HNPTFQSTAT : usb_regs.h
  • USB_HPCS : usb_regs.h
  • USB_HPTFLEN : usb_regs.h
  • USB_HPTFQSTAT : usb_regs.h
  • USB_IF_DESC_LEN : usb_std.h
  • USB_INTDESC : usb_std.h
  • USB_INTDESC_SIZE : usb_std.h
  • USB_INTPWRDESC : usb_std.h
  • USB_MAX_DEV_EPCOUNT : usb_core.h
  • USB_MAX_EP0_SIZE : usb_core.h
  • USB_MAX_FIFOS : usb_core.h
  • USB_MIN : usbd_std.h
  • USB_MSC_CLASS : usb_std.h
  • USB_OSPCFGDESC : usb_std.h
  • USB_OTG_DESC_LEN : usb_std.h
  • USB_PORT_READ : usb_regs.h
  • USB_PWRCLKCTL : usb_regs.h
  • USB_REMOTE_WAKEUP_RESET : usb_regs.h
  • USB_REMOTE_WAKEUP_SET : usb_regs.h
  • USB_REQ_MASK : usbd_std.h , usb_std.h
  • USB_REQ_RECIPIENT_MASK : usbd_std.h
  • USB_REQTYPE_DEVICE : usbd_std.h , usb_std.h
  • USB_REQTYPE_ENDPOINT : usbd_std.h , usb_std.h
  • USB_REQTYPE_INTERFACE : usb_std.h , usbd_std.h
  • USB_REQTYPE_MASK : usb_std.h
  • USB_SET_DEVADDR : usb_regs.h
  • USB_SOFT_DISCONNECT_DISABLE : usb_regs.h
  • USB_SOFT_DISCONNECT_ENABLE : usb_regs.h
  • USB_SPEED_EXP_FULL : usb_regs.h
  • USB_SPEED_EXP_HIGH : usb_regs.h
  • USB_SPEED_INP_FULL : usb_regs.h
  • USB_STANDARD_REQ : usb_std.h , usbd_std.h
  • USB_STATUS_ADDRESSED : usbd_core.h
  • USB_STATUS_CONFIGURED : usbd_core.h
  • USB_STATUS_DEFAULT : usbd_core.h
  • USB_STATUS_REMOTE_WAKEUP : usbd_std.h
  • USB_STATUS_SELF_POWERED : usbd_std.h
  • USB_STATUS_SUSPENDED : usbd_core.h
  • USB_STRDESC : usb_std.h
  • USB_VENDOR_REQ : usbd_std.h , usb_std.h
  • USBD : usbd_regs.h
  • USBD_BADDR : usbd_regs.h
  • USBD_CONFIG_STR_IDX : usbd_std.h
  • USBD_CONTRL_STATUS_RX : usbd_core.h
  • USBD_CONTRL_STATUS_TX : usbd_core.h
  • USBD_CTL : usbd_regs.h
  • USBD_DADDR : usbd_regs.h
  • USBD_DTG_RX_CLEAR : usbd_regs.h
  • USBD_DTG_RX_TOGGLE : usbd_regs.h
  • USBD_DTG_TX_CLEAR : usbd_regs.h
  • USBD_DTG_TX_TOGGLE : usbd_regs.h
  • USBD_ENDP_DOUBLE_BUF_CLEAR : usbd_regs.h
  • USBD_ENDP_DOUBLE_BUF_SET : usbd_regs.h
  • USBD_ENDP_KIND_CLEAR : usbd_regs.h
  • USBD_ENDP_KIND_SET : usbd_regs.h
  • USBD_ENDP_RX_STAT_CLEAR : usbd_regs.h
  • USBD_ENDP_RX_STATUS_GET : usbd_regs.h
  • USBD_ENDP_RX_STATUS_SET : usbd_regs.h
  • USBD_ENDP_RX_TX_STATUS_SET : usbd_regs.h
  • USBD_ENDP_TX_STAT_CLEAR : usbd_regs.h
  • USBD_ENDP_TX_STATUS_GET : usbd_regs.h
  • USBD_ENDP_TX_STATUS_SET : usbd_regs.h
  • USBD_EP0_MAX_SIZE : usbd_core.h
  • USBD_EPxCS : usbd_regs.h
  • USBD_INTERFACE_STR_IDX : usbd_std.h
  • USBD_INTF : usbd_regs.h
  • USBD_LANGID_STR_IDX : usbd_std.h
  • USBD_LPMCS : usbd_regs.h
  • USBD_MFC_STR_IDX : usbd_std.h
  • USBD_PRODUCT_STR_IDX : usbd_std.h
  • USBD_RAM : usbd_regs.h
  • USBD_REG_GET : usbd_regs.h
  • USBD_REG_SET : usbd_regs.h
  • USBD_SERIAL_STR_IDX : usbd_std.h
  • USBD_STAT : usbd_regs.h
  • USBD_STATUS_OUT_CLEAR : usbd_regs.h
  • USBD_STATUS_OUT_SET : usbd_regs.h
  • USBD_STRING_DESC : usbd_std.h
  • USBD_SWBUF_RX_TOGGLE : usbd_regs.h
  • USBD_SWBUF_TX_TOGGLE : usbd_regs.h
  • USBFS : usb_regs.h
  • USBFS_MAX_DEV_EPCOUNT : usb_defines.h
  • USBFS_MAX_FIFO_WORDLEN : usb_defines.h
  • USBFS_MAX_HOST_CHANNELCOUNT : usb_defines.h
  • USBFS_MAX_PACKET_SIZE : usb_defines.h
  • USBH_CFG_DESC_SET_SIZE : usb_std.h
  • USBH_DEVICE_ADDRESS : usbh_core.h
  • USBH_DEVICE_ADDRESS_DEFAULT : usbh_core.h
  • USBH_MAX_ERROR_COUNT : usbh_core.h
  • USBH_SETUP_PACKET_SIZE : usbh_std.h
  • USBHS_MAX_DEV_EPCOUNT : usb_defines.h
  • USBHS_MAX_FIFO_WORDLEN : usb_defines.h
  • USBHS_MAX_HOST_CHANNELCOUNT : usb_defines.h
  • USBHS_MAX_PACKET_SIZE : usb_defines.h
  • USBREQ_CLEAR_FEATURE : usb_std.h , usbd_std.h
  • USBREQ_GET_CONFIGURATION : usb_std.h , usbd_std.h
  • USBREQ_GET_DESCRIPTOR : usb_std.h , usbd_std.h
  • USBREQ_GET_INTERFACE : usb_std.h , usbd_std.h
  • USBREQ_GET_STATUS : usbd_std.h , usb_std.h
  • USBREQ_SET_ADDRESS : usb_std.h , usbd_std.h
  • USBREQ_SET_CONFIGURATION : usb_std.h , usbd_std.h
  • USBREQ_SET_DESCRIPTOR : usb_std.h
  • USBREQ_SET_FEATURE : usbd_std.h , usb_std.h
  • USBREQ_SET_INTERFACE : usb_std.h , usbd_std.h
  • USBREQ_SYNCH_FRAME : usb_std.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- w -

  • WDHT_WDHT : gd32f10x_adc.h
  • WDLT_WDLT : gd32f10x_adc.h
  • WFE_CMD : gd32f10x_pmu.h
  • WFI_CMD : gd32f10x_pmu.h
  • WIDE_STRING : usbd_std.h
  • WS_WSCNT : gd32f10x_fmc.h
  • WS_WSCNT_0 : gd32f10x_fmc.h
  • WS_WSCNT_1 : gd32f10x_fmc.h
  • WS_WSCNT_2 : gd32f10x_fmc.h
  • WWDGT : gd32f10x_wwdgt.h
  • WWDGT_CFG : gd32f10x_wwdgt.h
  • WWDGT_CFG_EWIE : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC_DIV1 : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC_DIV2 : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC_DIV4 : gd32f10x_wwdgt.h
  • WWDGT_CFG_PSC_DIV8 : gd32f10x_wwdgt.h
  • WWDGT_CFG_WIN : gd32f10x_wwdgt.h
  • WWDGT_CTL : gd32f10x_wwdgt.h
  • WWDGT_CTL_CNT : gd32f10x_wwdgt.h
  • WWDGT_CTL_WDGTEN : gd32f10x_wwdgt.h
  • WWDGT_STAT : gd32f10x_wwdgt.h
  • WWDGT_STAT_EWIF : gd32f10x_wwdgt.h
Generated on Tue Jul 18 2017 09:24:19 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: Main Page

GD32F10x_Firmware_Library Documentation
Generated on Tue Jul 18 2017 09:24:18 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_hcs.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usbh_hcs.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBH_HCS_H
14 #define USBH_HCS_H
15
16 #include "usbh_core.h"
17
18 #define HC_MAX 8U
19
20 #define HC_OK 0x0000U
21 #define HC_USED 0x8000U
22 #define HC_ERROR 0xFFFFU
23 #define HC_USED_MASK 0x7FFFU
24
25 /* function declarations */
26 /* allocate a new channel for the pipe */
27 uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr);
28 /* free all usb host channel */
29 uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev);
30 /* free the usb host channel */
31 uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index);
32 /* open a channel */
33 uint8_t usbh_channel_open (usb_core_handle_struct *pudev,
34 uint8_t channel_num,
35 uint8_t dev_addr,
36 uint8_t dev_speed,
37 uint8_t ep_type,
38 uint16_t ep_mps);
39 /* modify a channel */
40 uint8_t usbh_channel_modify (usb_core_handle_struct *pudev,
41 uint8_t channel_num,
42 uint8_t dev_addr,
43 uint8_t dev_speed,
44 uint8_t ep_type,
45 uint16_t ep_mps);
46
47 #endif /* USBH_HCS_H */
usbh_core.h
header file for usbh_core.c
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:115
usbh_channel_modify
uint8_t usbh_channel_modify(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel
Definition: usbh_hcs.c:64
usb_core_handle_struct
Definition: usb_core.h:201
usbh_allchannel_dealloc
uint8_t usbh_allchannel_dealloc(usb_core_handle_struct *pudev)
free all usb host channel
Definition: usbh_hcs.c:130
usbh_channel_open
uint8_t usbh_channel_open(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel
Definition: usbh_hcs.c:28
usbh_channel_alloc
uint8_t usbh_channel_alloc(usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe
Definition: usbh_hcs.c:97
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_dbg.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_DBG_H
14 #define GD32F10X_DBG_H
15
16 #include "gd32f10x.h"
17
18 /* DBG definitions */
19 #define DBG DBG_BASE
20
21 /* registers definitions */
22 #define DBG_ID REG32(DBG + 0x00U)
23 #define DBG_CTL0 REG32(DBG + 0x04U)
25 /* bits definitions */
26 /* DBG_ID */
27 #define DBG_ID_ID_CODE BITS(0,31)
29 /* DBG_CTL0 */
30 #define DBG_CTL0_SLP_HOLD BIT(0)
31 #define DBG_CTL0_DSLP_HOLD BIT(1)
32 #define DBG_CTL0_STB_HOLD BIT(2)
33 #define DBG_CTL0_TRACE_IOEN BIT(5)
34 #define DBG_CTL0_TRACE_MODE BITS(6,7)
35 #define DBG_CTL0_FWDGT_HOLD BIT(8)
36 #define DBG_CTL0_WWDGT_HOLD BIT(9)
37 #define DBG_CTL0_TIMER0_HOLD BIT(10)
38 #define DBG_CTL0_TIMER1_HOLD BIT(11)
39 #define DBG_CTL0_TIMER2_HOLD BIT(12)
40 #define DBG_CTL0_TIMER3_HOLD BIT(13)
41 #define DBG_CTL0_CAN0_HOLD BIT(14)
42 #define DBG_CTL0_I2C0_HOLD BIT(15)
43 #define DBG_CTL0_I2C1_HOLD BIT(16)
44 #define DBG_CTL0_TIMER4_HOLD BIT(17)
45 #define DBG_CTL0_TIMER5_HOLD BIT(18)
46 #define DBG_CTL0_TIMER6_HOLD BIT(19)
47 #define DBG_CTL0_TIMER7_HOLD BIT(20)
48 #ifdef GD32F10x_CL
49 #define DBG_CTL0_CAN1_HOLD BIT(21)
50 #endif /* GD32F10x_CL */
51 #ifdef GD32F10X_XD
52 #define DBG_CTL0_TIMER11_HOLD BIT(25)
53 #define DBG_CTL0_TIMER12_HOLD BIT(26)
54 #define DBG_CTL0_TIMER13_HOLD BIT(27)
55 #define DBG_CTL0_TIMER8_HOLD BIT(28)
56 #define DBG_CTL0_TIMER9_HOLD BIT(29)
57 #define DBG_CTL0_TIMER10_HOLD BIT(30)
58 #endif /* GD32F10x_XD */
59
60 /* constants definitions */
61 #define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD
62 #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD
63 #define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD
65 typedef enum
66 {
67 DBG_FWDGT_HOLD = BIT(8),
68 DBG_WWDGT_HOLD = BIT(9),
69 DBG_TIMER0_HOLD = BIT(10),
70 DBG_TIMER1_HOLD = BIT(11),
71 DBG_TIMER2_HOLD = BIT(12),
72 DBG_TIMER3_HOLD = BIT(13),
73 DBG_CAN0_HOLD = BIT(14),
74 DBG_I2C0_HOLD = BIT(15),
75 DBG_I2C1_HOLD = BIT(16),
76 DBG_TIMER4_HOLD = BIT(17),
77 DBG_TIMER5_HOLD = BIT(18),
78 DBG_TIMER6_HOLD = BIT(19),
79 DBG_TIMER7_HOLD = BIT(20),
80 #ifdef GD32F10x_CL
81 DBG_CAN1_HOLD = BIT(21),
82 #endif /* GD32F10x_CL */
83 #if (defined(GD32F10x_XD) || defined(GD32F10x_CL))
84 DBG_TIMER11_HOLD = BIT(25),
85 DBG_TIMER12_HOLD = BIT(26),
86 DBG_TIMER13_HOLD = BIT(27),
87 DBG_TIMER8_HOLD = BIT(28),
88 DBG_TIMER9_HOLD = BIT(29),
89 DBG_TIMER10_HOLD = BIT(30),
90 #endif /* GD32F10x_XD || GD32F10x_CL*/
91 }dbg_periph_enum;
92
93 #define CTL0_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
94 #define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0)
95 #define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1)
96 #define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2)
97 #define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3)
99 /* function declarations */
100 /* read DBG_ID code register */
101 uint32_t dbg_id_get(void);
102
103 /* enable low power behavior when the MCU is in debug mode */
104 void dbg_low_power_enable(uint32_t dbg_low_power);
105 /* disable low power behavior when the MCU is in debug mode */
106 void dbg_low_power_disable(uint32_t dbg_low_power);
107
108 /* enable peripheral behavior when the MCU is in debug mode */
109 void dbg_periph_enable(dbg_periph_enum dbg_periph);
110 /* disable peripheral behavior when the MCU is in debug mode */
111 void dbg_periph_disable(dbg_periph_enum dbg_periph);
112
113 /* enable trace pin assignment */
114 void dbg_trace_pin_enable(void);
115 /* disable trace pin assignment */
116 void dbg_trace_pin_disable(void);
117 /* set trace pin mode */
118 void dbg_trace_pin_mode_set(uint32_t trace_mode);
119
120 #endif /* GD32F10x_DBG_H */
DBG_I2C1_HOLD
Definition: gd32f10x_dbg.h:75
dbg_periph_enum
dbg_periph_enum
Definition: gd32f10x_dbg.h:65
DBG_CAN0_HOLD
Definition: gd32f10x_dbg.h:73
dbg_periph_enable
void dbg_periph_enable(dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:68
DBG_TIMER7_HOLD
Definition: gd32f10x_dbg.h:79
DBG_TIMER4_HOLD
Definition: gd32f10x_dbg.h:76
dbg_periph_disable
void dbg_periph_disable(dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:85
dbg_low_power_enable
void dbg_low_power_enable(uint32_t dbg_low_power)
enable low power behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:36
dbg_trace_pin_disable
void dbg_trace_pin_disable(void)
disable trace pin assignment
Definition: gd32f10x_dbg.c:107
DBG_WWDGT_HOLD
Definition: gd32f10x_dbg.h:68
DBG_TIMER6_HOLD
Definition: gd32f10x_dbg.h:78
dbg_trace_pin_enable
void dbg_trace_pin_enable(void)
enable trace pin assignment
Definition: gd32f10x_dbg.c:96
DBG_FWDGT_HOLD
Definition: gd32f10x_dbg.h:67
DBG_TIMER3_HOLD
Definition: gd32f10x_dbg.h:72
dbg_trace_pin_mode_set
void dbg_trace_pin_mode_set(uint32_t trace_mode)
trace pin mode selection
Definition: gd32f10x_dbg.c:122
DBG_TIMER5_HOLD
Definition: gd32f10x_dbg.h:77
dbg_id_get
uint32_t dbg_id_get(void)
read DBG_ID code register
Definition: gd32f10x_dbg.c:21
DBG_I2C0_HOLD
Definition: gd32f10x_dbg.h:74
dbg_low_power_disable
void dbg_low_power_disable(uint32_t dbg_low_power)
disable low power behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:51
DBG_TIMER2_HOLD
Definition: gd32f10x_dbg.h:71
DBG_TIMER1_HOLD
Definition: gd32f10x_dbg.h:70
DBG_TIMER0_HOLD
Definition: gd32f10x_dbg.h:69
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_dma.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_DMA_H
14 #define GD32F10X_DMA_H
15
16 #include "gd32f10x.h"
17
18 /* DMA definitions */
19 #define DMA0 (DMA_BASE)
20 #define DMA1 (DMA_BASE + 0x0400U)
22 /* registers definitions */
23 #define DMA_INTF(dmax) REG32((dmax) + 0x00U)
24 #define DMA_INTC(dmax) REG32((dmax) + 0x04U)
26 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U)
27 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU)
28 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U)
29 #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U)
31 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU)
32 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U)
33 #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U)
34 #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U)
36 #define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U)
37 #define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U)
38 #define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U)
39 #define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU)
41 #define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U)
42 #define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U)
43 #define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU)
44 #define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U)
46 #define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U)
47 #define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU)
48 #define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U)
49 #define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U)
51 #define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU)
52 #define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U)
53 #define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U)
54 #define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U)
56 #define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U)
57 #define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U)
58 #define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U)
59 #define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU)
61 /* bits definitions */
62 /* DMA_INTF */
63 #define DMA_INTF_GIF BIT(0)
64 #define DMA_INTF_FTFIF BIT(1)
65 #define DMA_INTF_HTFIF BIT(2)
66 #define DMA_INTF_ERRIF BIT(3)
68 /* DMA_INTC */
69 #define DMA_INTC_GIFC BIT(0)
70 #define DMA_INTC_FTFIFC BIT(1)
71 #define DMA_INTC_HTFIFC BIT(2)
72 #define DMA_INTC_ERRIFC BIT(3)
74 /* DMA_CHxCTL, x=0..6 */
75 #define DMA_CHXCTL_CHEN BIT(0)
76 #define DMA_CHXCTL_FTFIE BIT(1)
77 #define DMA_CHXCTL_HTFIE BIT(2)
78 #define DMA_CHXCTL_ERRIE BIT(3)
79 #define DMA_CHXCTL_DIR BIT(4)
80 #define DMA_CHXCTL_CMEN BIT(5)
81 #define DMA_CHXCTL_PNAGA BIT(6)
82 #define DMA_CHXCTL_MNAGA BIT(7)
83 #define DMA_CHXCTL_PWIDTH BITS(8,9)
84 #define DMA_CHXCTL_MWIDTH BITS(10,11)
85 #define DMA_CHXCTL_PRIO BITS(12,13)
86 #define DMA_CHXCTL_M2M BIT(14)
88 /* DMA_CHxCNT, x=0..6 */
89 #define DMA_CHXCNT_CNT BITS(0,15)
91 /* DMA_CHxPADDR, x=0..6 */
92 #define DMA_CHXPADDR_PADDR BITS(0,31)
94 /* DMA_CHxMADDR, x=0..6 */
95 #define DMA_CHXMADDR_MADDR BITS(0,31)
97 /* constants definitions */
98 /* DMA channel select */
99 typedef enum
100 {
101 DMA_CH0 = 0,
102 DMA_CH1,
103 DMA_CH2,
104 DMA_CH3,
105 DMA_CH4,
106 DMA_CH5,
107 DMA_CH6
108 } dma_channel_enum;
109
110 /* DMA initialize struct */
111 typedef struct
112 {
113 uint32_t periph_addr;
114 uint32_t periph_width;
115 uint32_t memory_addr;
116 uint32_t memory_width;
117 uint32_t number;
118 uint32_t priority;
119 uint8_t periph_inc;
120 uint8_t memory_inc;
121 uint8_t direction;
123 } dma_parameter_struct;
124
125 #define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U))
127 /* DMA_register address */
128 #define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel))
129 #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel))
130 #define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel))
131 #define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel))
133 /* DMA reset value */
134 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U)
135 #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U)
136 #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U)
137 #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U)
138 #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
139 DMA_INTF_HTFIF | DMA_INTF_ERRIF)
141 /* DMA_INTF register */
142 /* interrupt flag bits */
143 #define DMA_INT_FLAG_G DMA_INTF_GIF
144 #define DMA_INT_FLAG_FTF DMA_INTF_FTFIF
145 #define DMA_INT_FLAG_HTF DMA_INTF_HTFIF
146 #define DMA_INT_FLAG_ERR DMA_INTF_ERRIF
148 /* flag bits */
149 #define DMA_FLAG_G DMA_INTF_GIF
150 #define DMA_FLAG_FTF DMA_INTF_FTFIF
151 #define DMA_FLAG_HTF DMA_INTF_HTFIF
152 #define DMA_FLAG_ERR DMA_INTF_ERRIF
154 /* DMA_CHxCTL register */
155 /* interrupt enable bits */
156 #define DMA_INT_FTF DMA_CHXCTL_FTFIE
157 #define DMA_INT_HTF DMA_CHXCTL_HTFIE
158 #define DMA_INT_ERR DMA_CHXCTL_ERRIE
160 /* transfer direction */
161 #define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U)
162 #define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U)
163 /* circular mode */
164 #define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U)
165 #define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U)
167 /* peripheral increasing mode */
168 #define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U)
169 #define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U)
171 /* memory increasing mode */
172 #define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U)
173 #define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U)
175 /* transfer data size of peripheral */
176 #define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8))
177 #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0)
178 #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1)
179 #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2)
181 /* transfer data size of memory */
182 #define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10))
183 #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0)
184 #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1)
185 #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2)
187 /* channel priority level */
188 #define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12))
189 #define DMA_PRIORITY_LOW CHCTL_PRIO(0)
190 #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1)
191 #define DMA_PRIORITY_HIGH CHCTL_PRIO(2)
192 #define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3)
194 /* memory to memory mode */
195 #define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U)
196 #define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U)
198 /* DMA_CHxCNT register */
199 /* transfer counter */
200 #define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT
202 /* function declarations */
203 /* deinitialize DMA a channel registers */
204 void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
205 /* initialize DMA channel */
206 void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct);
207 /* enable DMA circulation mode */
208 void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
209 /* disable DMA circulation mode */
210 void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
211 /* enable memory to memory mode */
212 void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
213 /* disable memory to memory mode */
214 void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
215 /* enable DMA channel */
216 void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
217 /* disable DMA channel */
218 void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
219
220 /* set DMA peripheral base address */
221 void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
222 /* set DMA memory base address */
223 void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
224 /* set the number of remaining data to be transferred by the DMA */
225 void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
226 /* get the number of remaining data to be transferred by the DMA */
227 uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
228 /* configure priority level of DMA channel */
229 void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
230 /* configure transfer data size of memory */
231 void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
232 /* configure transfer data size of peripheral */
233 void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
234 /* enable next address increasement algorithm of memory */
235 void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
236 /* disable next address increasement algorithm of memory */
237 void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
238 /* enable next address increasement algorithm of peripheral */
239 void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
240 /* disable next address increasement algorithm of peripheral */
241 void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
242 /* configure the direction of data transfer on the channel */
243 void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction);
244
245 /* check DMA flag is set or not */
246 FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
247 /* clear DMA a channel flag */
248 void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
249 /* check DMA flag and interrupt enable bit is set or not */
250 FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
251 /* clear DMA a channel flag */
252 void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
253 /* enable DMA interrupt */
254 void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
255 /* disable DMA interrupt */
256 void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
257
258 #endif /* GD32F10X_DMA_H */
dma_circulation_disable
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable DMA circulation mode
Definition: gd32f10x_dma.c:135
dma_init
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct)
initialize DMA channel
Definition: gd32f10x_dma.c:63
dma_parameter_struct::priority
uint32_t priority
Definition: gd32f10x_dma.h:118
dma_parameter_struct::memory_width
uint32_t memory_width
Definition: gd32f10x_dma.h:116
dma_channel_enum
dma_channel_enum
Definition: gd32f10x_dma.h:99
dma_transfer_direction_config
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
configure the direction of data transfer on the channel
Definition: gd32f10x_dma.c:463
dma_transfer_number_config
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
set the number of remaining data to be transferred by the DMA
Definition: gd32f10x_dma.c:264
dma_memory_width_config
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
configure transfer data size of memory
Definition: gd32f10x_dma.c:334
dma_parameter_struct::periph_inc
uint8_t periph_inc
Definition: gd32f10x_dma.h:119
dma_memory_to_memory_enable
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable memory to memory mode
Definition: gd32f10x_dma.c:153
dma_memory_increase_disable
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable next address increasement algorithm of memory
Definition: gd32f10x_dma.c:406
dma_interrupt_enable
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
enable DMA interrupt
Definition: gd32f10x_dma.c:600
dma_interrupt_flag_clear
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag
Definition: gd32f10x_dma.c:581
DMA_CH3
Definition: gd32f10x_dma.h:104
dma_deinit
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
deinitialize DMA a channel registers
Definition: gd32f10x_dma.c:28
DMA_CH4
Definition: gd32f10x_dma.h:105
dma_periph_width_config
void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
configure transfer data size of peripheral
Definition: gd32f10x_dma.c:363
dma_parameter_struct
Definition: gd32f10x_dma.h:111
DMA_CH6
Definition: gd32f10x_dma.h:107
dma_parameter_struct::number
uint32_t number
Definition: gd32f10x_dma.h:117
DMA_CH2
Definition: gd32f10x_dma.h:103
dma_memory_address_config
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
set DMA memory base address
Definition: gd32f10x_dma.c:245
dma_flag_clear
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag
Definition: gd32f10x_dma.c:519
DMA_CH5
Definition: gd32f10x_dma.h:106
dma_parameter_struct::periph_width
uint32_t periph_width
Definition: gd32f10x_dma.h:114
dma_memory_increase_enable
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable next address increasement algorithm of memory
Definition: gd32f10x_dma.c:388
dma_circulation_enable
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable DMA circulation mode
Definition: gd32f10x_dma.c:117
dma_parameter_struct::memory_inc
uint8_t memory_inc
Definition: gd32f10x_dma.h:120
dma_parameter_struct::direction
uint8_t direction
Definition: gd32f10x_dma.h:121
dma_interrupt_disable
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
disable DMA interrupt
Definition: gd32f10x_dma.c:623
dma_flag_get
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
check DMA flag is set or not
Definition: gd32f10x_dma.c:491
dma_channel_enable
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable DMA channel
Definition: gd32f10x_dma.c:189
dma_channel_disable
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable DMA channel
Definition: gd32f10x_dma.c:207
dma_periph_address_config
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
set DMA peripheral base address
Definition: gd32f10x_dma.c:226
DMA_CH1
Definition: gd32f10x_dma.h:102
dma_transfer_number_get
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
get the number of remaining data to be transferred by the DMA
Definition: gd32f10x_dma.c:282
dma_periph_increase_enable
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable next address increasement algorithm of peripheral
Definition: gd32f10x_dma.c:424
DMA_CH0
Definition: gd32f10x_dma.h:101
dma_interrupt_flag_get
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
check DMA flag and interrupt enable bit is set or not
Definition: gd32f10x_dma.c:538
dma_memory_to_memory_disable
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable memory to memory mode
Definition: gd32f10x_dma.c:171
dma_periph_increase_disable
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable next address increasement algorithm of peripheral
Definition: gd32f10x_dma.c:442
dma_priority_config
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
configure priority level of DMA channel
Definition: gd32f10x_dma.c:305
dma_parameter_struct::periph_addr
uint32_t periph_addr
Definition: gd32f10x_dma.h:113
dma_parameter_struct::memory_addr
uint32_t memory_addr
Definition: gd32f10x_dma.h:115
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_dbg.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_dbg.h"
14
21 uint32_t dbg_id_get(void)
22 {
23 return DBG_ID;
24 }
25
36 void dbg_low_power_enable(uint32_t dbg_low_power)
37 {
38 DBG_CTL0 |= dbg_low_power;
39 }
40
51 void dbg_low_power_disable(uint32_t dbg_low_power)
52 {
53 DBG_CTL0 &= ~dbg_low_power;
54 }
55
68 void dbg_periph_enable(dbg_periph_enum dbg_periph)
69 {
70 DBG_CTL0 |= (uint32_t)dbg_periph;
71 }
72
85 void dbg_periph_disable(dbg_periph_enum dbg_periph)
86 {
87 DBG_CTL0 &= ~(uint32_t)dbg_periph;
88 }
89
96 void dbg_trace_pin_enable(void)
97 {
98 DBG_CTL0 |= DBG_CTL0_TRACE_IOEN;
99 }
100
107 void dbg_trace_pin_disable(void)
108 {
109 DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
110 }
111
122 void dbg_trace_pin_mode_set(uint32_t trace_mode)
123 {
124 DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE;
125 DBG_CTL0 |= trace_mode;
126 }
DBG_CTL0_TRACE_MODE
#define DBG_CTL0_TRACE_MODE
Definition: gd32f10x_dbg.h:34
dbg_periph_enum
dbg_periph_enum
Definition: gd32f10x_dbg.h:65
DBG_CTL0
#define DBG_CTL0
Definition: gd32f10x_dbg.h:23
dbg_periph_enable
void dbg_periph_enable(dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:68
dbg_trace_pin_disable
void dbg_trace_pin_disable(void)
disable trace pin assignment
Definition: gd32f10x_dbg.c:107
dbg_low_power_disable
void dbg_low_power_disable(uint32_t dbg_low_power)
disable low power behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:51
dbg_periph_disable
void dbg_periph_disable(dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:85
DBG_ID
#define DBG_ID
Definition: gd32f10x_dbg.h:22
dbg_low_power_enable
void dbg_low_power_enable(uint32_t dbg_low_power)
enable low power behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:36
dbg_trace_pin_mode_set
void dbg_trace_pin_mode_set(uint32_t trace_mode)
trace pin mode selection
Definition: gd32f10x_dbg.c:122
gd32f10x_dbg.h
definitions for the DBG
DBG_CTL0_TRACE_IOEN
#define DBG_CTL0_TRACE_IOEN
Definition: gd32f10x_dbg.h:33
dbg_trace_pin_enable
void dbg_trace_pin_enable(void)
enable trace pin assignment
Definition: gd32f10x_dbg.c:96
dbg_id_get
uint32_t dbg_id_get(void)
read DBG_ID code register
Definition: gd32f10x_dbg.c:21
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_timer.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_timer.h"
14
21 void timer_deinit(uint32_t timer_periph)
22 {
23 switch(timer_periph){
24 case TIMER0:
25 /* reset TIMER0 */
26 rcu_periph_reset_enable(RCU_TIMER0RST);
27 rcu_periph_reset_disable(RCU_TIMER0RST);
28 break;
29 case TIMER1:
30 /* reset TIMER1 */
31 rcu_periph_reset_enable(RCU_TIMER1RST);
32 rcu_periph_reset_disable(RCU_TIMER1RST);
33 break;
34 case TIMER2:
35 /* reset TIMER2 */
36 rcu_periph_reset_enable(RCU_TIMER2RST);
37 rcu_periph_reset_disable(RCU_TIMER2RST);
38 break;
39 case TIMER3:
40 /* reset TIMER3 */
41 rcu_periph_reset_enable(RCU_TIMER3RST);
42 rcu_periph_reset_disable(RCU_TIMER3RST);
43 break;
44 case TIMER4:
45 /* reset TIMER4 */
46 rcu_periph_reset_enable(RCU_TIMER4RST);
47 rcu_periph_reset_disable(RCU_TIMER4RST);
48 break;
49 case TIMER5:
50 /* reset TIMER5 */
51 rcu_periph_reset_enable(RCU_TIMER5RST);
52 rcu_periph_reset_disable(RCU_TIMER5RST);
53 break;
54 case TIMER6:
55 /* reset TIMER6 */
56 rcu_periph_reset_enable(RCU_TIMER6RST);
57 rcu_periph_reset_disable(RCU_TIMER6RST);
58 break;
59 case TIMER7:
60 /* reset TIMER7 */
61 rcu_periph_reset_enable(RCU_TIMER7RST);
62 rcu_periph_reset_disable(RCU_TIMER7RST);
63 break;
64 #ifdef GD32F10X_XD
65 case TIMER8:
66 /* reset TIMER8 */
67 rcu_periph_reset_enable(RCU_TIMER8RST);
68 rcu_periph_reset_disable(RCU_TIMER8RST);
69 break;
70 case TIMER9:
71 /* reset TIMER9 */
72 rcu_periph_reset_enable(RCU_TIMER9RST);
73 rcu_periph_reset_disable(RCU_TIMER9RST);
74 break;
75 case TIMER10:
76 /* reset TIMER10 */
77 rcu_periph_reset_enable(RCU_TIMER10RST);
78 rcu_periph_reset_disable(RCU_TIMER10RST);
79 break;
80 case TIMER11:
81 /* reset TIMER11 */
82 rcu_periph_reset_enable(RCU_TIMER11RST);
83 rcu_periph_reset_disable(RCU_TIMER11RST);
84 break;
85 case TIMER12:
86 /* reset TIMER12 */
87 rcu_periph_reset_enable(RCU_TIMER12RST);
88 rcu_periph_reset_disable(RCU_TIMER12RST);
89 break;
90 case TIMER13:
91 /* reset TIMER13 */
92 rcu_periph_reset_enable(RCU_TIMER13RST);
93 rcu_periph_reset_disable(RCU_TIMER13RST);
94 break;
95 #endif /* GD32F10X_XD */
96 default:
97 break;
98 }
99 }
100
114 void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
115 {
116 /* configure the counter prescaler value */
117 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
118
119 /* configure the counter direction and aligned mode */
120 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) ||
121 (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) ||
122 (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)){
123 TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM);
124 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
125 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
126 }
127
128 /* configure the autoreload value */
129 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
130
131 if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
132 /* reset the CKDIV bit */
133 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV;
134 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
135 }
136
137 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
138 /* configure the repetition counter value */
139 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
140 }
141
142 /* generate an update event */
143 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
144 }
145
152 void timer_enable(uint32_t timer_periph)
153 {
154 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
155 }
156
163 void timer_disable(uint32_t timer_periph)
164 {
165 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
166 }
167
174 void timer_auto_reload_shadow_enable(uint32_t timer_periph)
175 {
176 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
177 }
178
185 void timer_auto_reload_shadow_disable(uint32_t timer_periph)
186 {
187 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
188 }
189
196 void timer_update_event_enable(uint32_t timer_periph)
197 {
198 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
199 }
200
207 void timer_update_event_disable(uint32_t timer_periph)
208 {
209 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
210 }
211
223 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
224 {
225 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
226 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
227 }
228
235 void timer_counter_up_direction(uint32_t timer_periph)
236 {
237 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
238 }
239
246 void timer_counter_down_direction(uint32_t timer_periph)
247 {
248 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
249 }
250
261 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
262 {
263 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
264
265 if(TIMER_PSC_RELOAD_NOW == pscreload){
266 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
267 }
268 }
269
277 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
278 {
279 TIMER_CREP(timer_periph) = (uint32_t)repetition;
280 }
281
289 void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
290 {
291 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
292 }
293
301 void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
302 {
303 TIMER_CNT(timer_periph) = (uint32_t)counter;
304 }
305
312 uint32_t timer_counter_read(uint32_t timer_periph)
313 {
314 uint32_t count_value = 0U;
315 count_value = TIMER_CNT(timer_periph);
316 return (count_value);
317 }
318
325 uint16_t timer_prescaler_read(uint32_t timer_periph)
326 {
327 uint16_t prescaler_value = 0U;
328 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
329 return (prescaler_value);
330 }
331
341 void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode)
342 {
343 if(TIMER_SP_MODE_SINGLE == spmode){
344 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
345 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
346 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
347 }else{
348 }
349 }
350
360 void timer_update_source_config(uint32_t timer_periph, uint8_t update)
361 {
362 if(TIMER_UPDATE_SRC_REGULAR == update){
363 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
364 }else if(update == TIMER_UPDATE_SRC_GLOBAL){
365 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
366 }else{
367 }
368 }
369
385 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
386 {
387 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
388 }
389
405 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
406 {
407 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
408 }
409
425 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
426 {
427 uint32_t val;
428 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
429 if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
430 return SET;
431 }else{
432 return RESET;
433 }
434 }
435
451 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
452 {
453 TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt);
454 }
455
475 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
476 {
477 if(RESET != (TIMER_INTF(timer_periph) & flag)){
478 return SET;
479 }else{
480 return RESET;
481 }
482 }
483
503 void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
504 {
505 TIMER_INTF(timer_periph) &= (~(uint32_t)flag);
506 }
507
522 void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
523 {
524 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
525 }
526
541 void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
542 {
543 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
544 }
545
555 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
556 {
557 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
558 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
559 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
560 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
561 }else{
562 }
563 }
564
594 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
595 {
596 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
597 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
598 }
599
615 void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
616 {
617 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
618 }
619
634 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
635 {
636 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
637 ((uint32_t)(breakpara->ideloffstate)) |
638 ((uint32_t)(breakpara->deadtime)) |
639 ((uint32_t)(breakpara->breakpolarity)) |
640 ((uint32_t)(breakpara->outputautostate)) |
641 ((uint32_t)(breakpara->protectmode)) |
642 ((uint32_t)(breakpara->breakstate))) ;
643 }
644
651 void timer_break_enable(uint32_t timer_periph)
652 {
653 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
654 }
655
662 void timer_break_disable(uint32_t timer_periph)
663 {
664 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
665 }
666
673 void timer_automatic_output_enable(uint32_t timer_periph)
674 {
675 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
676 }
677
684 void timer_automatic_output_disable(uint32_t timer_periph)
685 {
686 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
687 }
688
696 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
697 {
698 if(ENABLE == newvalue){
699 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
700 }else{
701 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
702 }
703 }
704
712 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
713 {
714 if(ENABLE == newvalue){
715 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
716 }else{
717 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
718 }
719 }
720
730 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
731 {
732 if(TIMER_UPDATECTL_CCU == ccuctl){
733 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
734 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
735 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
736 }else{
737 }
738 }
739
758 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
759 {
760 switch(channel){
761 /* configure TIMER_CH_0 */
762 case TIMER_CH_0:
763 /* reset the CH0EN bit */
764 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
765 /* set the CH0EN bit */
766 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
767 /* reset the CH0P bit */
768 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
769 /* set the CH0P bit */
770 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
771
772 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
773 /* reset the CH0NEN bit */
774 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
775 /* set the CH0NEN bit */
776 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
777 /* reset the CH0NP bit */
778 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
779 /* set the CH0NP bit */
780 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
781 /* reset the ISO0 bit */
782 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
783 /* set the ISO0 bit */
784 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
785 /* reset the ISO0N bit */
786 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
787 /* set the ISO0N bit */
788 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
789 }
790 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
791 break;
792 /* configure TIMER_CH_1 */
793 case TIMER_CH_1:
794 /* reset the CH1EN bit */
795 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
796 /* set the CH1EN bit */
797 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 4U);
798 /* reset the CH1P bit */
799 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
800 /* set the CH1P bit */
801 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U);
802
803 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
804 /* reset the CH1NEN bit */
805 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
806 /* set the CH1NEN bit */
807 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U);
808 /* reset the CH1NP bit */
809 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
810 /* set the CH1NP bit */
811 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U);
812 /* reset the ISO1 bit */
813 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
814 /* set the ISO1 bit */
815 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U);
816 /* reset the ISO1N bit */
817 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
818 /* set the ISO1N bit */
819 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U);
820 }
821 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
822 break;
823 /* configure TIMER_CH_2 */
824 case TIMER_CH_2:
825 /* reset the CH2EN bit */
826 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
827 /* set the CH2EN bit */
828 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 8U);
829 /* reset the CH2P bit */
830 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
831 /* set the CH2P bit */
832 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U);
833
834 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
835 /* reset the CH2NEN bit */
836 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
837 /* set the CH2NEN bit */
838 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U);
839 /* reset the CH2NP bit */
840 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
841 /* set the CH2NP bit */
842 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U);
843 /* reset the ISO2 bit */
844 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
845 /* set the ISO2 bit */
846 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U);
847 /* reset the ISO2N bit */
848 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
849 /* set the ISO2N bit */
850 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U);
851 }
852 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
853 break;
854 /* configure TIMER_CH_3 */
855 case TIMER_CH_3:
856 /* reset the CH3EN bit */
857 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
858 /* set the CH3EN bit */
859 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 12U);
860 /* reset the CH3P bit */
861 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
862 /* set the CH3P bit */
863 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U);
864
865 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
866 /* reset the ISO3 bit */
867 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
868 /* set the ISO3 bit */
869 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U);
870 }
871 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
872 break;
873 default:
874 break;
875 }
876 }
877
898 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
899 {
900 switch(channel){
901 /* configure TIMER_CH_0 */
902 case TIMER_CH_0:
903 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
904 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
905 break;
906 /* configure TIMER_CH_1 */
907 case TIMER_CH_1:
908 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
909 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U);
910 break;
911 /* configure TIMER_CH_2 */
912 case TIMER_CH_2:
913 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
914 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
915 break;
916 /* configure TIMER_CH_3 */
917 case TIMER_CH_3:
918 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
919 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U);
920 break;
921 default:
922 break;
923 }
924 }
925
938 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
939 {
940 switch(channel){
941 case TIMER_CH_0:
942 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
943 break;
944 case TIMER_CH_1:
945 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
946 break;
947 case TIMER_CH_2:
948 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
949 break;
950 case TIMER_CH_3:
951 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
952 break;
953 default:
954 break;
955 }
956 }
957
972 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
973 {
974 switch(channel){
975 /* configure TIMER_CH_0 */
976 case TIMER_CH_0:
977 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
978 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
979 break;
980 /* configure TIMER_CH_1 */
981 case TIMER_CH_1:
982 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
983 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
984 break;
985 /* configure TIMER_CH_2 */
986 case TIMER_CH_2:
987 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
988 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
989 break;
990 /* configure TIMER_CH_3 */
991 case TIMER_CH_3:
992 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
993 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
994 break;
995 default:
996 break;
997 }
998 }
999
1014 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
1015 {
1016 switch(channel){
1017 /* configure TIMER_CH_0 */
1018 case TIMER_CH_0:
1019 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
1020 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
1021 break;
1022 /* configure TIMER_CH_1 */
1023 case TIMER_CH_1:
1024 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
1025 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1026 break;
1027 /* configure TIMER_CH_2 */
1028 case TIMER_CH_2:
1029 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
1030 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
1031 break;
1032 /* configure TIMER_CH_3 */
1033 case TIMER_CH_3:
1034 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
1035 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1036 break;
1037 default:
1038 break;
1039 }
1040 }
1041
1056 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
1057 {
1058 switch(channel){
1059 /* configure TIMER_CH_0 */
1060 case TIMER_CH_0:
1061 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1062 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1063 break;
1064 /* configure TIMER_CH_1 */
1065 case TIMER_CH_1:
1066 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1067 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1068 break;
1069 /* configure TIMER_CH_2 */
1070 case TIMER_CH_2:
1071 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1072 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1073 break;
1074 /* configure TIMER_CH_3 */
1075 case TIMER_CH_3:
1076 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1077 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1078 break;
1079 default:
1080 break;
1081 }
1082 }
1083
1098 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
1099 {
1100 switch(channel){
1101 /* configure TIMER_CH_0 */
1102 case TIMER_CH_0:
1103 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1104 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1105 break;
1106 /* configure TIMER_CH_1 */
1107 case TIMER_CH_1:
1108 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1109 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1110 break;
1111 /* configure TIMER_CH_2 */
1112 case TIMER_CH_2:
1113 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1114 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1115 break;
1116 /* configure TIMER_CH_3 */
1117 case TIMER_CH_3:
1118 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1119 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1120 break;
1121 default:
1122 break;
1123 }
1124 }
1125
1139 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
1140 {
1141 switch(channel){
1142 /* configure TIMER_CH_0 */
1143 case TIMER_CH_0:
1144 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1145 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1146 break;
1147 /* configure TIMER_CH_1 */
1148 case TIMER_CH_1:
1149 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1150 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1151 break;
1152 /* configure TIMER_CH_2 */
1153 case TIMER_CH_2:
1154 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1155 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1156 break;
1157 default:
1158 break;
1159 }
1160 }
1161
1176 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
1177 {
1178 switch(channel){
1179 /* configure TIMER_CH_0 */
1180 case TIMER_CH_0:
1181 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1182 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1183 break;
1184 /* configure TIMER_CH_1 */
1185 case TIMER_CH_1:
1186 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1187 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1188 break;
1189 /* configure TIMER_CH_2 */
1190 case TIMER_CH_2:
1191 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1192 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1193 break;
1194 /* configure TIMER_CH_3 */
1195 case TIMER_CH_3:
1196 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1197 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1198 break;
1199 default:
1200 break;
1201 }
1202 }
1203
1217 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
1218 {
1219 switch(channel){
1220 /* configure TIMER_CH_0 */
1221 case TIMER_CH_0:
1222 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1223 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1224 break;
1225 /* configure TIMER_CH_1 */
1226 case TIMER_CH_1:
1227 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1228 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1229 break;
1230 /* configure TIMER_CH_2 */
1231 case TIMER_CH_2:
1232 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1233 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1234 break;
1235 default:
1236 break;
1237 }
1238 }
1239
1256 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara)
1257 {
1258 switch(channel){
1259 /* configure TIMER_CH_0 */
1260 case TIMER_CH_0:
1261 /* reset the CH0EN bit */
1262 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1263
1264 /* reset the CH0P and CH0NP bits */
1265 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1266 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1267 /* reset the CH0MS bit */
1268 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1269 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1270 /* reset the CH0CAPFLT bit */
1271 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1272 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1273
1274 /* set the CH0EN bit */
1275 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1276 break;
1277
1278 /* configure TIMER_CH_1 */
1279 case TIMER_CH_1:
1280 /* reset the CH1EN bit */
1281 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1282
1283 /* reset the CH1P and CH1NP bits */
1284 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1285 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 4U);
1286 /* reset the CH1MS bit */
1287 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1288 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U);
1289 /* reset the CH1CAPFLT bit */
1290 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1291 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U);
1292
1293 /* set the CH1EN bit */
1294 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1295 break;
1296 /* configure TIMER_CH_2 */
1297 case TIMER_CH_2:
1298 /* reset the CH2EN bit */
1299 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1300
1301 /* reset the CH2P and CH2NP bits */
1302 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
1303 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 8U);
1304
1305 /* reset the CH2MS bit */
1306 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1307 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1308
1309 /* reset the CH2CAPFLT bit */
1310 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1311 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 4U);
1312
1313 /* set the CH2EN bit */
1314 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1315 break;
1316 /* configure TIMER_CH_3 */
1317 case TIMER_CH_3:
1318 /* reset the CH3EN bit */
1319 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1320
1321 /* reset the CH3P bits */
1322 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P));
1323 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 12U);
1324
1325 /* reset the CH3MS bit */
1326 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1327 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U);
1328
1329 /* reset the CH3CAPFLT bit */
1330 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1331 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U);
1332
1333 /* set the CH3EN bit */
1334 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1335 break;
1336 default:
1337 break;
1338 }
1339 /* configure TIMER channel input capture prescaler value */
1340 timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler));
1341 }
1342
1359 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
1360 {
1361 switch(channel){
1362 /* configure TIMER_CH_0 */
1363 case TIMER_CH_0:
1364 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1365 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1366 break;
1367 /* configure TIMER_CH_1 */
1368 case TIMER_CH_1:
1369 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1370 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1371 break;
1372 /* configure TIMER_CH_2 */
1373 case TIMER_CH_2:
1374 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1375 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1376 break;
1377 /* configure TIMER_CH_3 */
1378 case TIMER_CH_3:
1379 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1380 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1381 break;
1382 default:
1383 break;
1384 }
1385 }
1386
1398 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
1399 {
1400 uint32_t count_value = 0U;
1401
1402 switch(channel){
1403 case TIMER_CH_0:
1404 count_value = TIMER_CH0CV(timer_periph);
1405 break;
1406 case TIMER_CH_1:
1407 count_value = TIMER_CH1CV(timer_periph);
1408 break;
1409 case TIMER_CH_2:
1410 count_value = TIMER_CH2CV(timer_periph);
1411 break;
1412 case TIMER_CH_3:
1413 count_value = TIMER_CH3CV(timer_periph);
1414 break;
1415 default:
1416 break;
1417 }
1418 return (count_value);
1419 }
1420
1435 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
1436 {
1437 uint16_t icpolarity = 0x0U;
1438 uint16_t icselection = 0x0U;
1439
1440 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1441 icpolarity = TIMER_IC_POLARITY_FALLING;
1442 }else{
1443 icpolarity = TIMER_IC_POLARITY_RISING;
1444 }
1445
1446 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1447 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1448 }else{
1449 icselection = TIMER_IC_SELECTION_DIRECTTI;
1450 }
1451
1452 if(TIMER_CH_0 == channel){
1453 /* reset the CH0EN bit */
1454 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1455 /* reset the CH0P and CH0NP bits */
1456 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1457 /* set the CH0P and CH0NP bits */
1458 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1459 /* reset the CH0MS bit */
1460 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1461 /* set the CH0MS bit */
1462 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1463 /* reset the CH0CAPFLT bit */
1464 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1465 /* set the CH0CAPFLT bit */
1466 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1467 /* set the CH0EN bit */
1468 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1469 /* configure TIMER channel input capture prescaler value */
1470 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1471
1472 /* reset the CH1EN bit */
1473 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1474 /* reset the CH1P and CH1NP bits */
1475 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1476 /* set the CH1P and CH1NP bits */
1477 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U);
1478 /* reset the CH1MS bit */
1479 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1480 /* set the CH1MS bit */
1481 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U);
1482 /* reset the CH1CAPFLT bit */
1483 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1484 /* set the CH1CAPFLT bit */
1485 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U);
1486 /* set the CH1EN bit */
1487 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1488 /* configure TIMER channel input capture prescaler value */
1489 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1490 }else{
1491 /* reset the CH1EN bit */
1492 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1493 /* reset the CH1P and CH1NP bits */
1494 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1495 /* set the CH1P and CH1NP bits */
1496 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U);
1497 /* reset the CH1MS bit */
1498 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1499 /* set the CH1MS bit */
1500 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U);
1501 /* reset the CH1CAPFLT bit */
1502 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1503 /* set the CH1CAPFLT bit */
1504 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U);
1505 /* set the CH1EN bit */
1506 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1507 /* configure TIMER channel input capture prescaler value */
1508 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1509
1510 /* reset the CH0EN bit */
1511 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1512 /* reset the CH0P and CH0NP bits */
1513 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1514 /* set the CH0P and CH0NP bits */
1515 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1516 /* reset the CH0MS bit */
1517 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1518 /* set the CH0MS bit */
1519 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1520 /* reset the CH0CAPFLT bit */
1521 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1522 /* set the CH0CAPFLT bit */
1523 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1524 /* set the CH0EN bit */
1525 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1526 /* configure TIMER channel input capture prescaler value */
1527 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1528 }
1529 }
1530
1540 void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode)
1541 {
1542 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1543 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1544 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1545 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1546 }else{
1547 }
1548 }
1549
1565 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
1566 {
1567 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1568 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1569 }
1570
1586 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
1587 {
1588 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1589 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1590 }
1591
1608 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
1609 {
1610 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1611
1612 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1613 }
1614
1624 void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave)
1625 {
1626 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1627 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1628 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1629 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1630 }else{
1631 }
1632 }
1633
1649 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler,
1650 uint32_t expolarity, uint32_t extfilter)
1651 {
1652 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP|TIMER_SMCFG_ETPSC|TIMER_SMCFG_ETFC));
1653 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler|expolarity);
1654 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter<< 8U);
1655 }
1656
1673 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode,
1674 uint16_t ic0polarity, uint16_t ic1polarity)
1675 {
1676 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1677 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1678
1679 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1680 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U));
1681
1682 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1683 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1684 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity<< 4U));
1685 }
1686
1693 void timer_internal_clock_config(uint32_t timer_periph)
1694 {
1695 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1696 }
1697
1709 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
1710 {
1711 timer_input_trigger_source_select(timer_periph,intrigger);
1712 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1713 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1714 }
1715
1730 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger,
1731 uint16_t expolarity, uint32_t extfilter)
1732 {
1733 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1734 /* reset the CH1EN bit */
1735 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1736 /* reset the CH1NP bit */
1737 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1738 /* set the CH1NP bit */
1739 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U);
1740 /* reset the CH1MS bit */
1741 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1742 /* set the CH1MS bit */
1743 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U);
1744 /* reset the CH1CAPFLT bit */
1745 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1746 /* set the CH1CAPFLT bit */
1747 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U);
1748 /* set the CH1EN bit */
1749 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1750 }else{
1751 /* reset the CH0EN bit */
1752 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1753 /* reset the CH0P and CH0NP bits */
1754 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1755 /* set the CH0P and CH0NP bits */
1756 TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity;
1757 /* reset the CH0MS bit */
1758 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1759 /* set the CH0MS bit */
1760 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1761 /* reset the CH0CAPFLT bit */
1762 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1763 /* reset the CH0CAPFLT bit */
1764 TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter;
1765 /* set the CH0EN bit */
1766 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1767 }
1768 /* select TIMER input trigger source */
1769 timer_input_trigger_source_select(timer_periph,extrigger);
1770 /* reset the SMC bit */
1771 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1772 /* set the SMC bit */
1773 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1774 }
1775
1791 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler,
1792 uint32_t expolarity, uint32_t extfilter)
1793 {
1794 /* configure TIMER external trigger input */
1795 timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter);
1796
1797 /* reset the SMC bit,TRGS bit */
1798 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1799 /* set the SMC bit,TRGS bit */
1800 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1801 }
1802
1818 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler,
1819 uint32_t expolarity, uint32_t extfilter)
1820 {
1821 /* configure TIMER external trigger input */
1822 timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter);
1823
1824 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1825 }
1826
1833 void timer_external_clock_mode1_disable(uint32_t timer_periph)
1834 {
1835 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1836 }
timer_init
void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara)
initialize TIMER counter
Definition: gd32f10x_timer.c:114
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f10x_timer.h:175
timer_slave_mode_select
void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
select TIMER slave mode
Definition: gd32f10x_timer.c:1608
TIMER_CTL1_ISO2
#define TIMER_CTL1_ISO2
Definition: gd32f10x_timer.h:77
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f10x_timer.h:170
timer_channel_output_state_config
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
configure TIMER channel enable state
Definition: gd32f10x_timer.c:1176
timer_master_slave_mode_config
void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave)
configure TIMER master slave mode
Definition: gd32f10x_timer.c:1624
timer_break_parameter_struct::deadtime
uint16_t deadtime
Definition: gd32f10x_timer.h:241
TIMER_CTL1_ISO3
#define TIMER_CTL1_ISO3
Definition: gd32f10x_timer.h:79
RCU_TIMER11RST
Definition: gd32f10x_rcu.h:452
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f10x_timer.h:39
timer_external_trigger_as_external_clock_config
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
configure TIMER the external trigger as external clock input
Definition: gd32f10x_timer.c:1730
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f10x_timer.h:173
TIMER_CHCTL0_CH0COMCTL
#define TIMER_CHCTL0_CH0COMCTL
Definition: gd32f10x_timer.h:136
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f10x_timer.h:263
timer_auto_reload_shadow_enable
void timer_auto_reload_shadow_enable(uint32_t timer_periph)
enable the auto reload shadow function
Definition: gd32f10x_timer.c:174
TIMER_CHCTL0_CH0CAPPSC
#define TIMER_CHCTL0_CH0CAPPSC
Definition: gd32f10x_timer.h:144
TIMER7
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Definition: gd32f10x_timer.h:26
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uint16_t ocnidlestate
Definition: gd32f10x_timer.h:256
TIMER_SMCFG_ETPSC
#define TIMER_SMCFG_ETPSC
Definition: gd32f10x_timer.h:86
timer_single_pulse_mode_config
void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode)
configure TIMER single pulse mode
Definition: gd32f10x_timer.c:341
timer_counter_up_direction
void timer_counter_up_direction(uint32_t timer_periph)
set TIMER counter up direction
Definition: gd32f10x_timer.c:235
timer_counter_value_config
void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
configure TIMER counter register value
Definition: gd32f10x_timer.c:301
timer_channel_capture_value_register_read
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
read TIMER channel capture compare register value
Definition: gd32f10x_timer.c:1398
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#define TIMER_CTL0_SPM
Definition: gd32f10x_timer.h:61
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#define TIMER_CHCTL2_CH2NP
Definition: gd32f10x_timer.h:179
RCU_TIMER2RST
Definition: gd32f10x_rcu.h:446
timer_channel_control_shadow_update_config
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
configure TIMER channel control shadow register update control
Definition: gd32f10x_timer.c:730
timer_dma_transfer_config
void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
configure the TIMER DMA transfer
Definition: gd32f10x_timer.c:594
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#define TIMER_CHCTL0_CH1COMFEN
Definition: gd32f10x_timer.h:139
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#define TIMER_CHCTL1_CH2MS
Definition: gd32f10x_timer.h:151
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Definition: gd32f10x_timer.h:42
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#define TIMER_SP_MODE_REPETITIVE
Definition: gd32f10x_timer.h:392
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Definition: gd32f10x_timer.h:62
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void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
clear TIMER interrupt flag
Definition: gd32f10x_timer.c:451
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void timer_break_disable(uint32_t timer_periph)
disable TIMER break function
Definition: gd32f10x_timer.c:662
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#define TIMER_SWEVG_UPG
Definition: gd32f10x_timer.h:122
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uint32_t ideloffstate
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Definition: gd32f10x_timer.h:49
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Definition: gd32f10x_timer.h:428
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#define TIMER_SMCFG_SMC
Definition: gd32f10x_timer.h:82
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#define TIMER_CHCTL1_CH2COMCTL
Definition: gd32f10x_timer.h:154
timer_hall_mode_config
void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode)
configure TIMER hall sensor mode
Definition: gd32f10x_timer.c:1540
RCU_TIMER8RST
Definition: gd32f10x_rcu.h:495
TIMER_UPDATE_SRC_GLOBAL
#define TIMER_UPDATE_SRC_GLOBAL
Definition: gd32f10x_timer.h:396
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void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
configure TIMER primary output function
Definition: gd32f10x_timer.c:696
TIMER13
#define TIMER13
Definition: gd32f10x_timer.h:32
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#define TIMER_CTL1_ISO0
Definition: gd32f10x_timer.h:73
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Definition: gd32f10x_rcu.h:489
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#define TIMER_CTL1_TI0S
Definition: gd32f10x_timer.h:72
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#define TIMER_UPDATECTL_CCU
Definition: gd32f10x_timer.h:478
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#define TIMER_CTL1_DMAS
Definition: gd32f10x_timer.h:70
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void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f10x_timer.c:1359
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void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara)
configure TIMER break function
Definition: gd32f10x_timer.c:634
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void timer_auto_reload_shadow_disable(uint32_t timer_periph)
disable the auto reload shadow function
Definition: gd32f10x_timer.c:185
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#define TIMER_DMAREQUEST_CHANNELEVENT
Definition: gd32f10x_timer.h:313
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Definition: gd32f10x_rcu.h:449
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#define TIMER_CH2CV(timerx)
Definition: gd32f10x_timer.h:50
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void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode0
Definition: gd32f10x_timer.c:1791
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void timer_deinit(uint32_t timer_periph)
deinit a TIMER
Definition: gd32f10x_timer.c:21
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#define TIMER_PSC_RELOAD_NOW
Definition: gd32f10x_timer.h:377
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#define TIMER_CHCTL1_CH2COMSEN
Definition: gd32f10x_timer.h:153
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#define TIMER_SWEVG(timerx)
Definition: gd32f10x_timer.h:40
timer_master_output_trigger_source_select
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
select TIMER master mode output trigger source
Definition: gd32f10x_timer.c:1586
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#define TIMER_CAR(timerx)
Definition: gd32f10x_timer.h:46
RCU_TIMER4RST
Definition: gd32f10x_rcu.h:448
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#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f10x_timer.h:147
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uint16_t ocpolarity
Definition: gd32f10x_timer.h:253
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#define TIMER_CHCTL0_CH1COMCTL
Definition: gd32f10x_timer.h:141
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#define TIMER_CCHP(timerx)
Definition: gd32f10x_timer.h:52
RCU_TIMER6RST
Definition: gd32f10x_rcu.h:450
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f10x_timer.c:1649
TIMER_CCHP_POEN
#define TIMER_CCHP_POEN
Definition: gd32f10x_timer.h:215
TIMER9
#define TIMER9
Definition: gd32f10x_timer.h:28
TIMER_CHCTL1_CH3CAPPSC
#define TIMER_CHCTL1_CH3CAPPSC
Definition: gd32f10x_timer.h:164
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#define TIMER_HALLINTERFACE_ENABLE
Definition: gd32f10x_timer.h:546
timer_automatic_output_enable
void timer_automatic_output_enable(uint32_t timer_periph)
enable TIMER output automatic function
Definition: gd32f10x_timer.c:673
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f10x_timer.h:180
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#define TIMER_CHCTL0(timerx)
Definition: gd32f10x_timer.h:41
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f10x_timer.h:37
TIMER5
#define TIMER5
Definition: gd32f10x_timer.h:24
TIMER11
#define TIMER11
Definition: gd32f10x_timer.h:30
TIMER8
#define TIMER8
Definition: gd32f10x_timer.h:27
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f10x_timer.h:429
timer_counter_down_direction
void timer_counter_down_direction(uint32_t timer_periph)
set TIMER counter down direction
Definition: gd32f10x_timer.c:246
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f10x_timer.h:178
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#define TIMER_DMAREQUEST_UPDATEEVENT
Definition: gd32f10x_timer.h:312
TIMER_SMCFG_TRGSEL_CI1FE1
#define TIMER_SMCFG_TRGSEL_CI1FE1
Definition: gd32f10x_timer.h:505
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f10x_timer.h:36
TIMER_UPDATE_SRC_REGULAR
#define TIMER_UPDATE_SRC_REGULAR
Definition: gd32f10x_timer.h:395
TIMER_CTL1_ISO2N
#define TIMER_CTL1_ISO2N
Definition: gd32f10x_timer.h:78
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f10x_timer.h:58
TIMER_CTL0_CKDIV
#define TIMER_CTL0_CKDIV
Definition: gd32f10x_timer.h:65
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f10x_timer.h:38
timer_internal_trigger_as_external_clock_config
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
configure TIMER the internal trigger as external clock input
Definition: gd32f10x_timer.c:1709
TIMER_CHCTL0_CH1COMCEN
#define TIMER_CHCTL0_CH1COMCEN
Definition: gd32f10x_timer.h:142
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f10x_timer.h:264
TIMER_CHCTL0_CH0COMSEN
#define TIMER_CHCTL0_CH0COMSEN
Definition: gd32f10x_timer.h:135
timer_dma_enable
void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
enable the TIMER DMA
Definition: gd32f10x_timer.c:522
TIMER_CHCTL2_CH1NEN
#define TIMER_CHCTL2_CH1NEN
Definition: gd32f10x_timer.h:174
TIMER_IC_SELECTION_INDIRECTTI
#define TIMER_IC_SELECTION_INDIRECTTI
Definition: gd32f10x_timer.h:488
TIMER12
#define TIMER12
Definition: gd32f10x_timer.h:31
timer_flag_clear
void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
clear TIMER flags
Definition: gd32f10x_timer.c:503
TIMER_CHCTL1_CH3COMFEN
#define TIMER_CHCTL1_CH3COMFEN
Definition: gd32f10x_timer.h:157
TIMER0
#define TIMER0
Definition: gd32f10x_timer.h:19
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f10x_timer.h:176
TIMER_CHCTL1_CH3CAPFLT
#define TIMER_CHCTL1_CH3CAPFLT
Definition: gd32f10x_timer.h:165
TIMER_IC_POLARITY_RISING
#define TIMER_IC_POLARITY_RISING
Definition: gd32f10x_timer.h:482
TIMER_CCHP_BRKEN
#define TIMER_CCHP_BRKEN
Definition: gd32f10x_timer.h:212
TIMER_CTL0_UPDIS
#define TIMER_CTL0_UPDIS
Definition: gd32f10x_timer.h:59
TIMER_SMCFG_ETP
#define TIMER_SMCFG_ETP
Definition: gd32f10x_timer.h:88
timer_channel_output_mode_config
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
configure TIMER channel output compare mode
Definition: gd32f10x_timer.c:898
timer_internal_clock_config
void timer_internal_clock_config(uint32_t timer_periph)
configure TIMER internal clock mode
Definition: gd32f10x_timer.c:1693
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f10x_timer.h:87
timer_parameter_struct::clockdivision
uint16_t clockdivision
Definition: gd32f10x_timer.h:232
TIMER_CHCTL0_CH1CAPPSC
#define TIMER_CHCTL0_CH1CAPPSC
Definition: gd32f10x_timer.h:146
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f10x_timer.h:487
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f10x_timer.h:528
timer_dma_disable
void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
disable the TIMER DMA
Definition: gd32f10x_timer.c:541
TIMER_CTL1_ISO0N
#define TIMER_CTL1_ISO0N
Definition: gd32f10x_timer.h:74
gd32f10x_timer.h
definitions for the TIMER
timer_break_parameter_struct::outputautostate
uint16_t outputautostate
Definition: gd32f10x_timer.h:243
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f10x_timer.c:1565
TIMER_CHCTL0_CH0COMFEN
#define TIMER_CHCTL0_CH0COMFEN
Definition: gd32f10x_timer.h:134
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f10x_timer.h:64
RCU_TIMER1RST
Definition: gd32f10x_rcu.h:445
timer_interrupt_disable
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
disable the TIMER interrupt
Definition: gd32f10x_timer.c:405
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f10x_timer.h:172
timer_channel_dma_request_source_select
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
channel DMA request source selection
Definition: gd32f10x_timer.c:555
timer_input_pwm_capture_config
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
configure TIMER input pwm capture function
Definition: gd32f10x_timer.c:1435
RCU_TIMER9RST
Definition: gd32f10x_rcu.h:496
RCU_TIMER12RST
Definition: gd32f10x_rcu.h:453
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f10x_timer.h:169
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f10x_timer.h:51
TIMER_CTL1_ISO1N
#define TIMER_CTL1_ISO1N
Definition: gd32f10x_timer.h:76
timer_channel_output_fast_config
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
configure TIMER channel output fast function
Definition: gd32f10x_timer.c:1014
timer_autoreload_value_config
void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
configure TIMER autoreload register value
Definition: gd32f10x_timer.c:289
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f10x_timer.h:171
TIMER1
#define TIMER1
Definition: gd32f10x_timer.h:20
TIMER_CHCTL1_CH2COMCEN
#define TIMER_CHCTL1_CH2COMCEN
Definition: gd32f10x_timer.h:155
timer_break_enable
void timer_break_enable(uint32_t timer_periph)
enable TIMER break function
Definition: gd32f10x_timer.c:651
TIMER_DMACFG
#define TIMER_DMACFG(timerx)
Definition: gd32f10x_timer.h:53
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f10x_timer.h:214
timer_repetition_value_config
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
configure TIMER repetition register value
Definition: gd32f10x_timer.c:277
RCU_TIMER10RST
Definition: gd32f10x_rcu.h:497
timer_channel_output_config
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
configure TIMER channel output function
Definition: gd32f10x_timer.c:758
timer_external_clock_mode1_config
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode1
Definition: gd32f10x_timer.c:1818
timer_flag_get
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
get TIMER flags
Definition: gd32f10x_timer.c:475
timer_external_clock_mode1_disable
void timer_external_clock_mode1_disable(uint32_t timer_periph)
disable TIMER the external clock mode1
Definition: gd32f10x_timer.c:1833
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f10x_timer.h:45
TIMER_DMACFG_DMATA
#define TIMER_DMACFG_DMATA
Definition: gd32f10x_timer.h:218
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f10x_timer.h:47
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f10x_timer.h:177
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f10x_timer.h:262
timer_break_parameter_struct
Definition: gd32f10x_timer.h:237
timer_counter_read
uint32_t timer_counter_read(uint32_t timer_periph)
read TIMER counter value
Definition: gd32f10x_timer.c:312
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
timer_break_parameter_struct::runoffstate
uint16_t runoffstate
Definition: gd32f10x_timer.h:239
TIMER2
#define TIMER2
Definition: gd32f10x_timer.h:21
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f10x_timer.h:133
TIMER_SP_MODE_SINGLE
#define TIMER_SP_MODE_SINGLE
Definition: gd32f10x_timer.h:391
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
timer_disable
void timer_disable(uint32_t timer_periph)
disable a TIMER
Definition: gd32f10x_timer.c:163
TIMER_DMACFG_DMATC
#define TIMER_DMACFG_DMATC
Definition: gd32f10x_timer.h:219
TIMER6
#define TIMER6
Definition: gd32f10x_timer.h:25
TIMER_SMCFG_TRGSEL_ETIFP
#define TIMER_SMCFG_TRGSEL_ETIFP
Definition: gd32f10x_timer.h:506
timer_oc_parameter_struct::outputstate
uint32_t outputstate
Definition: gd32f10x_timer.h:251
timer_oc_parameter_struct::ocidlestate
uint16_t ocidlestate
Definition: gd32f10x_timer.h:255
timer_break_parameter_struct::breakpolarity
uint16_t breakpolarity
Definition: gd32f10x_timer.h:242
timer_parameter_struct::repetitioncounter
uint8_t repetitioncounter
Definition: gd32f10x_timer.h:233
timer_break_parameter_struct::breakstate
uint16_t breakstate
Definition: gd32f10x_timer.h:245
TIMER_CHCTL1_CH2CAPPSC
#define TIMER_CHCTL1_CH2CAPPSC
Definition: gd32f10x_timer.h:162
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f10x_timer.h:145
TIMER_CHCTL1_CH3COMSEN
#define TIMER_CHCTL1_CH3COMSEN
Definition: gd32f10x_timer.h:158
TIMER_CHCTL1_CH3COMCEN
#define TIMER_CHCTL1_CH3COMCEN
Definition: gd32f10x_timer.h:160
timer_quadrature_decoder_mode_config
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
configure TIMER quadrature decoder mode
Definition: gd32f10x_timer.c:1673
TIMER_CTL0_UPS
#define TIMER_CTL0_UPS
Definition: gd32f10x_timer.h:60
timer_update_event_disable
void timer_update_event_disable(uint32_t timer_periph)
disable the update event
Definition: gd32f10x_timer.c:207
TIMER_CTL1_CCUC
#define TIMER_CTL1_CCUC
Definition: gd32f10x_timer.h:69
timer_update_source_config
void timer_update_source_config(uint32_t timer_periph, uint8_t update)
configure TIMER update source
Definition: gd32f10x_timer.c:360
TIMER_SMCFG_MSM
#define TIMER_SMCFG_MSM
Definition: gd32f10x_timer.h:84
TIMER_CHCTL0_CH1COMSEN
#define TIMER_CHCTL0_CH1COMSEN
Definition: gd32f10x_timer.h:140
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f10x_timer.h:426
timer_channel_complementary_output_polarity_config
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
configure TIMER channel complementary output polarity
Definition: gd32f10x_timer.c:1139
TIMER_CTL1_MMC
#define TIMER_CTL1_MMC
Definition: gd32f10x_timer.h:71
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f10x_timer.h:43
RCU_TIMER3RST
Definition: gd32f10x_rcu.h:447
TIMER_IC_POLARITY_FALLING
#define TIMER_IC_POLARITY_FALLING
Definition: gd32f10x_timer.h:483
timer_interrupt_flag_get
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
get timer interrupt flag
Definition: gd32f10x_timer.c:425
timer_event_software_generate
void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
software generate events
Definition: gd32f10x_timer.c:615
TIMER_CHCTL0_CH0COMCEN
#define TIMER_CHCTL0_CH0COMCEN
Definition: gd32f10x_timer.h:137
timer_channel_complementary_output_state_config
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
configure TIMER channel complementary output enable state
Definition: gd32f10x_timer.c:1217
TIMER3
#define TIMER3
Definition: gd32f10x_timer.h:22
timer_counter_alignment
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
set TIMER counter alignment mode
Definition: gd32f10x_timer.c:223
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f10x_timer.h:168
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f10x_timer.h:138
TIMER_CHCTL1_CH2CAPFLT
#define TIMER_CHCTL1_CH2CAPFLT
Definition: gd32f10x_timer.h:163
TIMER_CTL1_ISO1
#define TIMER_CTL1_ISO1
Definition: gd32f10x_timer.h:75
timer_enable
void timer_enable(uint32_t timer_periph)
enable a TIMER
Definition: gd32f10x_timer.c:152
timer_update_event_enable
void timer_update_event_enable(uint32_t timer_periph)
enable the update event
Definition: gd32f10x_timer.c:196
timer_prescaler_read
uint16_t timer_prescaler_read(uint32_t timer_periph)
read TIMER prescaler value
Definition: gd32f10x_timer.c:325
TIMER_UPDATECTL_CCUTRI
#define TIMER_UPDATECTL_CCUTRI
Definition: gd32f10x_timer.h:479
timer_channel_control_shadow_config
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
channel capture/compare control shadow register enable
Definition: gd32f10x_timer.c:712
timer_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f10x_timer.h:228
TIMER_MASTER_SLAVE_MODE_DISABLE
#define TIMER_MASTER_SLAVE_MODE_DISABLE
Definition: gd32f10x_timer.h:532
timer_oc_parameter_struct::ocnpolarity
uint16_t ocnpolarity
Definition: gd32f10x_timer.h:254
timer_automatic_output_disable
void timer_automatic_output_disable(uint32_t timer_periph)
disable TIMER output automatic function
Definition: gd32f10x_timer.c:684
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f10x_timer.h:83
timer_channel_output_polarity_config
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
configure TIMER channel output polarity
Definition: gd32f10x_timer.c:1098
TIMER_CNT
#define TIMER_CNT(timerx)
Definition: gd32f10x_timer.h:44
timer_prescaler_config
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
configure TIMER prescaler
Definition: gd32f10x_timer.c:261
TIMER_MASTER_SLAVE_MODE_ENABLE
#define TIMER_MASTER_SLAVE_MODE_ENABLE
Definition: gd32f10x_timer.h:531
timer_parameter_struct
Definition: gd32f10x_timer.h:226
TIMER_CHCTL1_CH2COMFEN
#define TIMER_CHCTL1_CH2COMFEN
Definition: gd32f10x_timer.h:152
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f10x_timer.h:427
timer_channel_output_clear_config
void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
configure TIMER channel output clear function
Definition: gd32f10x_timer.c:1056
timer_interrupt_enable
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
enable the TIMER interrupt
Definition: gd32f10x_timer.c:385
timer_parameter_struct::period
uint32_t period
Definition: gd32f10x_timer.h:231
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f10x_timer.h:181
timer_oc_parameter_struct
Definition: gd32f10x_timer.h:249
timer_break_parameter_struct::protectmode
uint16_t protectmode
Definition: gd32f10x_timer.h:244
TIMER10
#define TIMER10
Definition: gd32f10x_timer.h:29
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f10x_timer.h:35
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f10x_timer.h:48
timer_channel_output_shadow_config
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
configure TIMER channel output shadow function
Definition: gd32f10x_timer.c:972
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f10x_timer.h:63
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f10x_timer.h:265
timer_input_capture_config
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
configure TIMER input capture parameter
Definition: gd32f10x_timer.c:1256
timer_channel_output_pulse_value_config
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
configure TIMER channel output pulse value
Definition: gd32f10x_timer.c:938
TIMER_HALLINTERFACE_DISABLE
#define TIMER_HALLINTERFACE_DISABLE
Definition: gd32f10x_timer.h:547
RCU_TIMER0RST
Definition: gd32f10x_rcu.h:487
RCU_TIMER13RST
Definition: gd32f10x_rcu.h:454
timer_oc_parameter_struct::outputnstate
uint16_t outputnstate
Definition: gd32f10x_timer.h:252
TIMER_CTL1_CCSE
#define TIMER_CTL1_CCSE
Definition: gd32f10x_timer.h:68
TIMER_CHCTL1_CH3MS
#define TIMER_CHCTL1_CH3MS
Definition: gd32f10x_timer.h:156
TIMER_CHCTL1_CH3COMCTL
#define TIMER_CHCTL1_CH3COMCTL
Definition: gd32f10x_timer.h:159
timer_ic_parameter_struct
Definition: gd32f10x_timer.h:260
timer_parameter_struct::alignedmode
uint16_t alignedmode
Definition: gd32f10x_timer.h:229
timer_parameter_struct::counterdirection
uint16_t counterdirection
Definition: gd32f10x_timer.h:230
TIMER_SMCFG_ETFC
#define TIMER_SMCFG_ETFC
Definition: gd32f10x_timer.h:85
TIMER4
#define TIMER4
Definition: gd32f10x_timer.h:23
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_can.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_can.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10x_CAN_H
14 #define GD32F10x_CAN_H
15
16 #include "gd32f10x.h"
17
18 /* CAN definitions */
19 #define CAN0 CAN_BASE
20 #define CAN1 (CAN0 + 0x00000400U)
22 /* registers definitions */
23 #define CAN_CTL(canx) REG32((canx) + 0x00U)
24 #define CAN_STAT(canx) REG32((canx) + 0x04U)
25 #define CAN_TSTAT(canx) REG32((canx) + 0x08U)
26 #define CAN_RFIFO0(canx) REG32((canx) + 0x0CU)
27 #define CAN_RFIFO1(canx) REG32((canx) + 0x10U)
28 #define CAN_INTEN(canx) REG32((canx) + 0x14U)
29 #define CAN_ERR(canx) REG32((canx) + 0x18U)
30 #define CAN_BT(canx) REG32((canx) + 0x1CU)
31 #define CAN_TMI0(canx) REG32((canx) + 0x180U)
32 #define CAN_TMP0(canx) REG32((canx) + 0x184U)
33 #define CAN_TMDATA00(canx) REG32((canx) + 0x188U)
34 #define CAN_TMDATA10(canx) REG32((canx) + 0x18CU)
35 #define CAN_TMI1(canx) REG32((canx) + 0x190U)
36 #define CAN_TMP1(canx) REG32((canx) + 0x194U)
37 #define CAN_TMDATA01(canx) REG32((canx) + 0x198U)
38 #define CAN_TMDATA11(canx) REG32((canx) + 0x19CU)
39 #define CAN_TMI2(canx) REG32((canx) + 0x1A0U)
40 #define CAN_TMP2(canx) REG32((canx) + 0x1A4U)
41 #define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U)
42 #define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU)
43 #define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U)
44 #define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U)
45 #define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U)
46 #define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU)
47 #define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U)
48 #define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U)
49 #define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U)
50 #define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU)
51 #define CAN_FCTL(canx) REG32((canx) + 0x200U)
52 #define CAN_FMCFG(canx) REG32((canx) + 0x204U)
53 #define CAN_FSCFG(canx) REG32((canx) + 0x20CU)
54 #define CAN_FAFIFO(canx) REG32((canx) + 0x214U)
55 #define CAN_FW(canx) REG32((canx) + 0x21CU)
56 #define CAN_F0DATA0(canx) REG32((canx) + 0x240U)
57 #define CAN_F1DATA0(canx) REG32((canx) + 0x248U)
58 #define CAN_F2DATA0(canx) REG32((canx) + 0x250U)
59 #define CAN_F3DATA0(canx) REG32((canx) + 0x258U)
60 #define CAN_F4DATA0(canx) REG32((canx) + 0x260U)
61 #define CAN_F5DATA0(canx) REG32((canx) + 0x268U)
62 #define CAN_F6DATA0(canx) REG32((canx) + 0x270U)
63 #define CAN_F7DATA0(canx) REG32((canx) + 0x278U)
64 #define CAN_F8DATA0(canx) REG32((canx) + 0x280U)
65 #define CAN_F9DATA0(canx) REG32((canx) + 0x288U)
66 #define CAN_F10DATA0(canx) REG32((canx) + 0x290U)
67 #define CAN_F11DATA0(canx) REG32((canx) + 0x298U)
68 #define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U)
69 #define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U)
70 #define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U)
71 #define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U)
72 #define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U)
73 #define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U)
74 #define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U)
75 #define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U)
76 #define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U)
77 #define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U)
78 #define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U)
79 #define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U)
80 #define CAN_F24DATA0(canx) REG32((canx) + 0x300U)
81 #define CAN_F25DATA0(canx) REG32((canx) + 0x308U)
82 #define CAN_F26DATA0(canx) REG32((canx) + 0x310U)
83 #define CAN_F27DATA0(canx) REG32((canx) + 0x318U)
84 #define CAN_F0DATA1(canx) REG32((canx) + 0x244U)
85 #define CAN_F1DATA1(canx) REG32((canx) + 0x24CU)
86 #define CAN_F2DATA1(canx) REG32((canx) + 0x254U)
87 #define CAN_F3DATA1(canx) REG32((canx) + 0x25CU)
88 #define CAN_F4DATA1(canx) REG32((canx) + 0x264U)
89 #define CAN_F5DATA1(canx) REG32((canx) + 0x26CU)
90 #define CAN_F6DATA1(canx) REG32((canx) + 0x274U)
91 #define CAN_F7DATA1(canx) REG32((canx) + 0x27CU)
92 #define CAN_F8DATA1(canx) REG32((canx) + 0x284U)
93 #define CAN_F9DATA1(canx) REG32((canx) + 0x28CU)
94 #define CAN_F10DATA1(canx) REG32((canx) + 0x294U)
95 #define CAN_F11DATA1(canx) REG32((canx) + 0x29CU)
96 #define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U)
97 #define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU)
98 #define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U)
99 #define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU)
100 #define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U)
101 #define CAN_F17DATA1(canx) REG32((canx) + 0x24CU)
102 #define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U)
103 #define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU)
104 #define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U)
105 #define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU)
106 #define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U)
107 #define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU)
108 #define CAN_F24DATA1(canx) REG32((canx) + 0x304U)
109 #define CAN_F25DATA1(canx) REG32((canx) + 0x30CU)
110 #define CAN_F26DATA1(canx) REG32((canx) + 0x314U)
111 #define CAN_F27DATA1(canx) REG32((canx) + 0x31CU)
113 /* CAN transmit mailbox bank */
114 #define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U))
115 #define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U))
116 #define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U))
117 #define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U))
119 /* CAN filter bank */
120 #define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U)
121 #define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U)
123 /* CAN receive fifo mailbox bank */
124 #define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U))
125 #define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U))
126 #define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U))
127 #define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U))
129 /* bits definitions */
130 /* CAN_CTL */
131 #define CAN_CTL_IWMOD BIT(0)
132 #define CAN_CTL_SLPWMOD BIT(1)
133 #define CAN_CTL_TFO BIT(2)
134 #define CAN_CTL_RFOD BIT(3)
135 #define CAN_CTL_ARD BIT(4)
136 #define CAN_CTL_AWU BIT(5)
137 #define CAN_CTL_ABOR BIT(6)
138 #define CAN_CTL_TTC BIT(7)
139 #define CAN_CTL_SWRST BIT(15)
140 #define CAN_CTL_DFZ BIT(16)
142 /* CAN_STAT */
143 #define CAN_STAT_IWS BIT(0)
144 #define CAN_STAT_SLPWS BIT(1)
145 #define CAN_STAT_ERRIF BIT(2)
146 #define CAN_STAT_WUIF BIT(3)
147 #define CAN_STAT_SLPIF BIT(4)
148 #define CAN_STAT_TS BIT(8)
149 #define CAN_STAT_RS BIT(9)
150 #define CAN_STAT_LASTRX BIT(10)
151 #define CAN_STAT_RXL BIT(11)
153 /* CAN_TSTAT */
154 #define CAN_TSTAT_MTF0 BIT(0)
155 #define CAN_TSTAT_MTFNERR0 BIT(1)
156 #define CAN_TSTAT_MAL0 BIT(2)
157 #define CAN_TSTAT_MTE0 BIT(3)
158 #define CAN_TSTAT_MST0 BIT(7)
159 #define CAN_TSTAT_MTF1 BIT(8)
160 #define CAN_TSTAT_MTFNERR1 BIT(9)
161 #define CAN_TSTAT_MAL1 BIT(10)
162 #define CAN_TSTAT_MTE1 BIT(11)
163 #define CAN_TSTAT_MST1 BIT(15)
164 #define CAN_TSTAT_MTF2 BIT(16)
165 #define CAN_TSTAT_MTFNERR2 BIT(17)
166 #define CAN_TSTAT_MAL2 BIT(18)
167 #define CAN_TSTAT_MTE2 BIT(19)
168 #define CAN_TSTAT_MST2 BIT(23)
169 #define CAN_TSTAT_NUM BITS(24,25)
170 #define CAN_TSTAT_TME0 BIT(26)
171 #define CAN_TSTAT_TME1 BIT(27)
172 #define CAN_TSTAT_TME2 BIT(28)
173 #define CAN_TSTAT_TMLS0 BIT(29)
174 #define CAN_TSTAT_TMLS1 BIT(30)
175 #define CAN_TSTAT_TMLS2 BIT(31)
177 /* CAN_RFIFO0 */
178 #define CAN_RFIFO0_RFL0 BITS(0,1)
179 #define CAN_RFIFO0_RFF0 BIT(3)
180 #define CAN_RFIFO0_RFO0 BIT(4)
181 #define CAN_RFIFO0_RFD0 BIT(5)
183 /* CAN_RFIFO1 */
184 #define CAN_RFIFO1_RFL1 BITS(0,1)
185 #define CAN_RFIFO1_RFF1 BIT(3)
186 #define CAN_RFIFO1_RFO1 BIT(4)
187 #define CAN_RFIFO1_RFD1 BIT(5)
189 /* CAN_INTEN */
190 #define CAN_INTEN_TMEIE BIT(0)
191 #define CAN_INTEN_RFNEIE0 BIT(1)
192 #define CAN_INTEN_RFFIE0 BIT(2)
193 #define CAN_INTEN_RFOIE0 BIT(3)
194 #define CAN_INTEN_RFNEIE1 BIT(4)
195 #define CAN_INTEN_RFFIE1 BIT(5)
196 #define CAN_INTEN_RFOIE1 BIT(6)
197 #define CAN_INTEN_WERRIE BIT(8)
198 #define CAN_INTEN_PERRIE BIT(9)
199 #define CAN_INTEN_BOIE BIT(10)
200 #define CAN_INTEN_ERRNIE BIT(11)
201 #define CAN_INTEN_ERRIE BIT(15)
202 #define CAN_INTEN_WIE BIT(16)
203 #define CAN_INTEN_SLPWIE BIT(17)
205 /* CAN_ERR */
206 #define CAN_ERR_WERR BIT(0)
207 #define CAN_ERR_PERR BIT(1)
208 #define CAN_ERR_BOERR BIT(2)
209 #define CAN_ERR_ERRN BITS(4,6)
210 #define CAN_ERR_TECNT BITS(16,23)
211 #define CAN_ERR_RECNT BITS(24,31)
213 /* CAN_BT */
214 #define CAN_BT_BAUDPSC BITS(0,9)
215 #define CAN_BT_BS1 BITS(16,19)
216 #define CAN_BT_BS2 BITS(20,22)
217 #define CAN_BT_SJW BITS(24,25)
218 #define CAN_BT_LCMOD BIT(30)
219 #define CAN_BT_SCMOD BIT(31)
221 /* CAN_TMIx */
222 #define CAN_TMI_TEN BIT(0)
223 #define CAN_TMI_FT BIT(1)
224 #define CAN_TMI_FF BIT(2)
225 #define CAN_TMI_EFID BITS(3,31)
226 #define CAN_TMI_SFID BITS(21,31)
228 /* CAN_TMPx */
229 #define CAN_TMP_DLENC BITS(0,3)
230 #define CAN_TMP_TSEN BIT(8)
231 #define CAN_TMP_TS BITS(16,31)
233 /* CAN_TMDATA0x */
234 #define CAN_TMDATA0_DB0 BITS(0,7)
235 #define CAN_TMDATA0_DB1 BITS(8,15)
236 #define CAN_TMDATA0_DB2 BITS(16,23)
237 #define CAN_TMDATA0_DB3 BITS(24,31)
239 /* CAN_TMDATA1x */
240 #define CAN_TMDATA1_DB4 BITS(0,7)
241 #define CAN_TMDATA1_DB5 BITS(8,15)
242 #define CAN_TMDATA1_DB6 BITS(16,23)
243 #define CAN_TMDATA1_DB7 BITS(24,31)
245 /* CAN_RFIFOMIx */
246 #define CAN_RFIFOMI_FT BIT(1)
247 #define CAN_RFIFOMI_FF BIT(2)
248 #define CAN_RFIFOMI_EFID BITS(3,31)
249 #define CAN_RFIFOMI_SFID BITS(21,31)
251 /* CAN_RFIFOMPx */
252 #define CAN_RFIFOMP_DLENC BITS(0,3)
253 #define CAN_RFIFOMP_FI BITS(8,15)
254 #define CAN_RFIFOMP_TS BITS(16,31)
256 /* CAN_RFIFOMDATA0x */
257 #define CAN_RFIFOMDATA0_DB0 BITS(0,7)
258 #define CAN_RFIFOMDATA0_DB1 BITS(8,15)
259 #define CAN_RFIFOMDATA0_DB2 BITS(16,23)
260 #define CAN_RFIFOMDATA0_DB3 BITS(24,31)
262 /* CAN_RFIFOMDATA1x */
263 #define CAN_RFIFOMDATA1_DB4 BITS(0,7)
264 #define CAN_RFIFOMDATA1_DB5 BITS(8,15)
265 #define CAN_RFIFOMDATA1_DB6 BITS(16,23)
266 #define CAN_RFIFOMDATA1_DB7 BITS(24,31)
268 /* CAN_FCTL */
269 #define CAN_FCTL_FLD BIT(0)
270 #define CAN_FCTL_HBC1F BITS(8,13)
272 /* CAN_FMCFG */
273 #define CAN_FMCFG_FMOD(regval) BIT(regval)
275 /* CAN_FSCFG */
276 #define CAN_FSCFG_FS(regval) BIT(regval)
278 /* CAN_FAFIFO */
279 #define CAN_FAFIFOR_FAF(regval) BIT(regval)
281 /* CAN_FW */
282 #define CAN_FW_FW(regval) BIT(regval)
284 /* CAN_FxDATAy */
285 #define CAN_FDATA_FD BITS(0,31)
287 /* consts definitions */
288 /* define the CAN bit position and its register index offset */
289 #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
290 #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
291 #define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
292
293 #define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
294 #define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
295 #define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
296 #define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
297
298 /* register offset */
299 #define STAT_REG_OFFSET ((uint8_t)0x04U)
300 #define TSTAT_REG_OFFSET ((uint8_t)0x08U)
301 #define RFIFO0_REG_OFFSET ((uint8_t)0x0CU)
302 #define RFIFO1_REG_OFFSET ((uint8_t)0x10U)
303 #define ERR_REG_OFFSET ((uint8_t)0x18U)
305 /* CAN flags */
306 typedef enum
307 {
308 /* flags in TSTAT register */
309 CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U),
310 CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U),
311 CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U),
312 CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U),
313 CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U),
314 CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U),
315 /* flags in RFIFO0 register */
316 CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U),
317 CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U),
318 /* flags in RFIFO1 register */
319 CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U),
320 CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U),
321 /* flags in ERR register */
322 CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U),
323 CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U),
324 CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U),
325 }can_flag_enum;
326
327 /* CAN interrupt flags */
328 typedef enum
329 {
330 /* interrupt flags in STAT register */
331 CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U),
332 CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16),
333 CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15),
334 /* interrupt flags in TSTAT register */
335 CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U),
336 CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U),
337 CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U),
338 /* interrupt flags in RFIFO0 register */
339 CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U),
340 CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U),
341 /* interrupt flags in RFIFO0 register */
342 CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U),
343 CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U),
344 }can_interrupt_flag_enum;
345
346 /* CAN initiliaze parameters struct */
347 typedef struct
348 {
349 uint8_t working_mode;
350 uint8_t resync_jump_width;
351 uint8_t time_segment_1;
352 uint8_t time_segment_2;
353 ControlStatus time_triggered;
354 ControlStatus auto_bus_off_recovery;
355 ControlStatus auto_wake_up;
356 ControlStatus auto_retrans;
357 ControlStatus rec_fifo_overwrite;
358 ControlStatus trans_fifo_order;
359 uint16_t prescaler;
360 }can_parameter_struct;
361
362 /* CAN transmit message struct */
363 typedef struct
364 {
365 uint32_t tx_sfid;
366 uint32_t tx_efid;
367 uint8_t tx_ff;
368 uint8_t tx_ft;
369 uint8_t tx_dlen;
370 uint8_t tx_data[8];
371 }can_trasnmit_message_struct;
372
373 /* CAN receive message struct */
374 typedef struct
375 {
376 uint32_t rx_sfid;
377 uint32_t rx_efid;
378 uint8_t rx_ff;
379 uint8_t rx_ft;
380 uint8_t rx_dlen;
381 uint8_t rx_data[8];
382 uint8_t rx_fi;
383 } can_receive_message_struct;
384
385 /* CAN filter parameters struct */
386 typedef struct
387 {
388 uint16_t filter_list_high;
389 uint16_t filter_list_low;
390 uint16_t filter_mask_high;
391 uint16_t filter_mask_low;
392 uint16_t filter_fifo_number;
393 uint16_t filter_number;
394 uint16_t filter_mode;
395 uint16_t filter_bits;
396 ControlStatus filter_enable;
397 }can_filter_parameter_struct;
398
399 /* CAN errors */
400 typedef enum
401 {
402 CAN_ERROR_NONE = 0,
403 CAN_ERROR_FILL,
404 CAN_ERROR_FORMATE,
405 CAN_ERROR_ACK,
406 CAN_ERROR_BITRECESSIVE,
407 CAN_ERROR_BITDOMINANTER,
408 CAN_ERROR_CRC,
409 CAN_ERROR_SOFTWARECFG,
410 }can_error_enum;
411
412 /* transmit states */
413 typedef enum
414 {
415 CAN_TRANSMIT_FAILED = 0,
416 CAN_TRANSMIT_OK = 1,
417 CAN_TRANSMIT_PENDING = 2,
418 CAN_TRANSMIT_NOMAILBOX = 4,
419 }can_transmit_state_enum;
420
421 /* CAN baudrate prescaler*/
422 #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
423
424 /* CAN bit segment 1*/
425 #define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
426
427 /* CAN bit segment 2*/
428 #define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
429
430 /* CAN resynchronization jump width*/
431 #define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
432
433 /* CAN communication mode*/
434 #define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
435
436 /* CAN FDATA high 16 bits */
437 #define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
438
439 /* CAN FDATA low 16 bits */
440 #define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
441
442 /* CAN1 filter start bank_number*/
443 #define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
444
445 /* CAN transmit mailbox extended identifier*/
446 #define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
447
448 /* CAN transmit mailbox standard identifier*/
449 #define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
450
451 /* transmit data byte 0 */
452 #define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
453
454 /* transmit data byte 1 */
455 #define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
456
457 /* transmit data byte 2 */
458 #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
459
460 /* transmit data byte 3 */
461 #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
462
463 /* transmit data byte 4 */
464 #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
465
466 /* transmit data byte 5 */
467 #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
468
469 /* transmit data byte 6 */
470 #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
471
472 /* transmit data byte 7 */
473 #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
474
475 /* receive mailbox extended identifier*/
476 #define RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31)
477
478 /* receive mailbox standrad identifier*/
479 #define RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31)
480
481 /* receive data length */
482 #define RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3)
483
484 /* the index of the filter by which the frame is passed */
485 #define RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15)
486
487 /* receive data byte 0 */
488 #define RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7)
489
490 /* receive data byte 1 */
491 #define RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15)
492
493 /* receive data byte 2 */
494 #define RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23)
495
496 /* receive data byte 3 */
497 #define RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31)
498
499 /* receive data byte 4 */
500 #define RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7)
501
502 /* receive data byte 5 */
503 #define RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15)
504
505 /* receive data byte 6 */
506 #define RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23)
507
508 /* receive data byte 7 */
509 #define RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31)
510
511 /* CAN errors */
512 #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
513 #define CAN_ERRN_0 ERR_ERRN(0) /* no error */
514 #define CAN_ERRN_1 ERR_ERRN(1)
515 #define CAN_ERRN_2 ERR_ERRN(2)
516 #define CAN_ERRN_3 ERR_ERRN(3)
517 #define CAN_ERRN_4 ERR_ERRN(4)
518 #define CAN_ERRN_5 ERR_ERRN(5)
519 #define CAN_ERRN_6 ERR_ERRN(6)
520 #define CAN_ERRN_7 ERR_ERRN(7)
522 #define CAN_STATE_PENDING ((uint32_t)0x00000000U)
524 /* CAN communication mode */
525 #define CAN_NORMAL_MODE ((uint8_t)0x00U)
526 #define CAN_LOOPBACK_MODE ((uint8_t)0x01U)
527 #define CAN_SILENT_MODE ((uint8_t)0x02U)
528 #define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U)
530 /* CAN resynchronisation jump width */
531 #define CAN_BT_SJW_1TQ ((uint8_t)0x00U)
532 #define CAN_BT_SJW_2TQ ((uint8_t)0x01U)
533 #define CAN_BT_SJW_3TQ ((uint8_t)0x02U)
534 #define CAN_BT_SJW_4TQ ((uint8_t)0x03U)
536 /* CAN time segment 1 */
537 #define CAN_BT_BS1_1TQ ((uint8_t)0x00U)
538 #define CAN_BT_BS1_2TQ ((uint8_t)0x01U)
539 #define CAN_BT_BS1_3TQ ((uint8_t)0x02U)
540 #define CAN_BT_BS1_4TQ ((uint8_t)0x03U)
541 #define CAN_BT_BS1_5TQ ((uint8_t)0x04U)
542 #define CAN_BT_BS1_6TQ ((uint8_t)0x05U)
543 #define CAN_BT_BS1_7TQ ((uint8_t)0x06U)
544 #define CAN_BT_BS1_8TQ ((uint8_t)0x07U)
545 #define CAN_BT_BS1_9TQ ((uint8_t)0x08U)
546 #define CAN_BT_BS1_10TQ ((uint8_t)0x09U)
547 #define CAN_BT_BS1_11TQ ((uint8_t)0x0AU)
548 #define CAN_BT_BS1_12TQ ((uint8_t)0x0BU)
549 #define CAN_BT_BS1_13TQ ((uint8_t)0x0CU)
550 #define CAN_BT_BS1_14TQ ((uint8_t)0x0DU)
551 #define CAN_BT_BS1_15TQ ((uint8_t)0x0EU)
552 #define CAN_BT_BS1_16TQ ((uint8_t)0x0FU)
554 /* CAN time segment 2 */
555 #define CAN_BT_BS2_1TQ ((uint8_t)0x00U)
556 #define CAN_BT_BS2_2TQ ((uint8_t)0x01U)
557 #define CAN_BT_BS2_3TQ ((uint8_t)0x02U)
558 #define CAN_BT_BS2_4TQ ((uint8_t)0x03U)
559 #define CAN_BT_BS2_5TQ ((uint8_t)0x04U)
560 #define CAN_BT_BS2_6TQ ((uint8_t)0x05U)
561 #define CAN_BT_BS2_7TQ ((uint8_t)0x06U)
562 #define CAN_BT_BS2_8TQ ((uint8_t)0x07U)
564 /* CAN mailbox number */
565 #define CAN_MAILBOX0 ((uint8_t)0x00U)
566 #define CAN_MAILBOX1 ((uint8_t)0x01U)
567 #define CAN_MAILBOX2 ((uint8_t)0x02U)
568 #define CAN_NOMAILBOX ((uint8_t)0x03U)
570 /* CAN frame format */
571 #define CAN_FF_STANDARD ((uint32_t)0x00000000U)
572 #define CAN_FF_EXTENDED ((uint32_t)0x00000004U)
574 /* CAN receive fifo */
575 #define CAN_FIFO0 ((uint8_t)0x00U)
576 #define CAN_FIFO1 ((uint8_t)0x01U)
578 /* frame number of receive fifo */
579 #define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U)
581 #define CAN_SFID_MASK ((uint32_t)0x000007FFU)
582 #define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU)
584 /* CAN working mode */
585 #define CAN_MODE_INITIALIZE ((uint8_t)0x01U)
586 #define CAN_MODE_NORMAL ((uint8_t)0x02U)
587 #define CAN_MODE_SLEEP ((uint8_t)0x04U)
589 /* filter bits */
590 #define CAN_FILTERBITS_16BIT ((uint8_t)0x00U)
591 #define CAN_FILTERBITS_32BIT ((uint8_t)0x01U)
593 /* filter mode */
594 #define CAN_FILTERMODE_MASK ((uint8_t)0x00U)
595 #define CAN_FILTERMODE_LIST ((uint8_t)0x01U)
597 /* filter 16 bits mask */
598 #define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU)
599
600 /* frame type */
601 #define CAN_FT_DATA ((uint32_t)0x00000000U)
602 #define CAN_FT_REMOTE ((uint32_t)0x00000002U)
604 /* CAN timeout */
605 #define CAN_TIMEOUT ((uint32_t)0x0000FFFFU)
607 /* interrupt enable bits */
608 #define CAN_INT_TME CAN_INTEN_TMEIE
609 #define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0
610 #define CAN_INT_RFF0 CAN_INTEN_RFFIE0
611 #define CAN_INT_RFO0 CAN_INTEN_RFOIE0
612 #define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1
613 #define CAN_INT_RFF1 CAN_INTEN_RFFIE1
614 #define CAN_INT_RFO1 CAN_INTEN_RFOIE1
615 #define CAN_INT_WERR CAN_INTEN_WERRIE
616 #define CAN_INT_PERR CAN_INTEN_PERRIE
617 #define CAN_INT_BO CAN_INTEN_BOIE
618 #define CAN_INT_ERRN CAN_INTEN_ERRNIE
619 #define CAN_INT_ERR CAN_INTEN_ERRIE
620 #define CAN_INT_WAKEUP CAN_INTEN_WIE
621 #define CAN_INT_SLPW CAN_INTEN_SLPWIE
623 /* function declarations */
624 /* deinitialize CAN */
625 void can_deinit(uint32_t can_periph);
626 /* initialize CAN */
627 ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init);
628 /* CAN filter init */
629 void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init);
630 /* set can1 fliter start bank number */
631 void can1_filter_start_bank(uint8_t start_bank);
632
633 /* enable functions */
634 /* CAN debug freeze enable */
635 void can_debug_freeze_enable(uint32_t can_periph);
636 /* CAN debug freeze disable */
637 void can_debug_freeze_disable(uint32_t can_periph);
638 /* CAN time triggle mode enable */
639 void can_time_trigger_mode_enable(uint32_t can_periph);
640 /* CAN time triggle mode disable */
641 void can_time_trigger_mode_disable(uint32_t can_periph);
642
643 /* transmit functions */
644 /* transmit CAN message */
645 uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message);
646 /* get CAN transmit state */
647 can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
648 /* stop CAN transmission */
649 void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
650 /* CAN receive message */
651 void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message);
652 /* CAN release fifo */
653 void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
654 /* CAN receive message length */
655 uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
656 /* CAN working mode */
657 ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
658 /* CAN wakeup from sleep mode */
659 ErrStatus can_wakeup(uint32_t can_periph);
660
661 /* CAN get error */
662 can_error_enum can_error_get(uint32_t can_periph);
663 /* get CAN receive error number */
664 uint8_t can_receive_error_number_get(uint32_t can_periph);
665 /* get CAN transmit error number */
666 uint8_t can_transmit_error_number_get(uint32_t can_periph);
667
668 /* CAN interrupt enable */
669 void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
670 /* CAN interrupt disable */
671 void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
672 /* CAN get flag state */
673 FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
674 /* CAN clear flag state */
675 void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
676 /* CAN get interrupt flag state */
677 FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
678 /* CAN clear interrupt flag state */
679 void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
680
681 #endif /* GD32F10x_CAN_H */
CAN_FLAG_MTE1
Definition: gd32f10x_can.h:310
CAN_INT_FLAG_RFO0
Definition: gd32f10x_can.h:339
STAT_REG_OFFSET
#define STAT_REG_OFFSET
Definition: gd32f10x_can.h:299
can_receive_message_struct::rx_ft
uint8_t rx_ft
Definition: gd32f10x_can.h:379
CAN_INT_FLAG_MTF0
Definition: gd32f10x_can.h:337
can_receive_error_number_get
uint8_t can_receive_error_number_get(uint32_t can_periph)
get CAN receive error number
Definition: gd32f10x_can.c:657
can_error_enum
can_error_enum
Definition: gd32f10x_can.h:400
CAN_REGIDX_BITS
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1)
Definition: gd32f10x_can.h:293
can_parameter_struct::auto_wake_up
ControlStatus auto_wake_up
Definition: gd32f10x_can.h:355
can_transmit_state_enum
can_transmit_state_enum
Definition: gd32f10x_can.h:413
can_filter_parameter_struct::filter_list_high
uint16_t filter_list_high
Definition: gd32f10x_can.h:388
CAN_FLAG_MTE0
Definition: gd32f10x_can.h:311
ERR_REG_OFFSET
#define ERR_REG_OFFSET
Definition: gd32f10x_can.h:303
CAN_REGIDX_BIT
#define CAN_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_can.h:289
can_interrupt_disable
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
disable CAN interrupt
Definition: gd32f10x_can.c:729
CAN_INT_FLAG_SLPIF
Definition: gd32f10x_can.h:331
can_trasnmit_message_struct::tx_ft
uint8_t tx_ft
Definition: gd32f10x_can.h:368
can_transmission_stop
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
stop CAN transmission
Definition: gd32f10x_can.c:436
can_interrupt_flag_enum
can_interrupt_flag_enum
Definition: gd32f10x_can.h:328
can_receive_message_struct::rx_ff
uint8_t rx_ff
Definition: gd32f10x_can.h:378
can_error_get
can_error_enum can_error_get(uint32_t can_periph)
get CAN error type
Definition: gd32f10x_can.c:640
CAN_INT_FLAG_ERRIF
Definition: gd32f10x_can.h:333
can_trasnmit_message_struct::tx_dlen
uint8_t tx_dlen
Definition: gd32f10x_can.h:369
can_filter_parameter_struct::filter_list_low
uint16_t filter_list_low
Definition: gd32f10x_can.h:389
can1_filter_start_bank
void can1_filter_start_bank(uint8_t start_bank)
set CAN1 fliter start bank number
Definition: gd32f10x_can.c:220
CAN_FLAG_MTF2
Definition: gd32f10x_can.h:312
CAN_INT_FLAG_RFF1
Definition: gd32f10x_can.h:343
CAN_FLAG_MTF0
Definition: gd32f10x_can.h:314
can_filter_parameter_struct::filter_mode
uint16_t filter_mode
Definition: gd32f10x_can.h:394
can_trasnmit_message_struct
Definition: gd32f10x_can.h:363
CAN_ERROR_FORMATE
Definition: gd32f10x_can.h:404
CAN_FLAG_MTE2
Definition: gd32f10x_can.h:309
can_parameter_struct::time_segment_1
uint8_t time_segment_1
Definition: gd32f10x_can.h:351
can_parameter_struct
Definition: gd32f10x_can.h:347
CAN_INT_FLAG_WUIF
Definition: gd32f10x_can.h:332
CAN_TRANSMIT_FAILED
Definition: gd32f10x_can.h:415
CAN_ERROR_ACK
Definition: gd32f10x_can.h:405
CAN_FLAG_BOERR
Definition: gd32f10x_can.h:322
can_transmit_error_number_get
uint8_t can_transmit_error_number_get(uint32_t can_periph)
get CAN transmit error number
Definition: gd32f10x_can.c:672
can_filter_init
void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init)
initialize CAN filter
Definition: gd32f10x_can.c:148
can_trasnmit_message_struct::tx_sfid
uint32_t tx_sfid
Definition: gd32f10x_can.h:365
CAN_INT_FLAG_MTF2
Definition: gd32f10x_can.h:335
can_receive_message_struct::rx_fi
uint8_t rx_fi
Definition: gd32f10x_can.h:382
CAN_ERROR_NONE
Definition: gd32f10x_can.h:402
can_interrupt_enable
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
enable CAN interrupt
Definition: gd32f10x_can.c:702
can_filter_parameter_struct::filter_mask_low
uint16_t filter_mask_low
Definition: gd32f10x_can.h:391
can_trasnmit_message_struct::tx_ff
uint8_t tx_ff
Definition: gd32f10x_can.h:367
can_filter_parameter_struct::filter_number
uint16_t filter_number
Definition: gd32f10x_can.h:393
can_debug_freeze_disable
void can_debug_freeze_disable(uint32_t can_periph)
disable CAN debug freeze
Definition: gd32f10x_can.c:261
can_transmit_states
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number)
get CAN transmit state
Definition: gd32f10x_can.c:385
CAN_INT_FLAG_MTF1
Definition: gd32f10x_can.h:336
can_parameter_struct::auto_bus_off_recovery
ControlStatus auto_bus_off_recovery
Definition: gd32f10x_can.h:354
can_parameter_struct::resync_jump_width
uint8_t resync_jump_width
Definition: gd32f10x_can.h:350
CAN_FLAG_RFO0
Definition: gd32f10x_can.h:316
CAN_FLAG_WERR
Definition: gd32f10x_can.h:324
CAN_ERROR_SOFTWARECFG
Definition: gd32f10x_can.h:409
can_parameter_struct::rec_fifo_overwrite
ControlStatus rec_fifo_overwrite
Definition: gd32f10x_can.h:357
can_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f10x_can.h:359
can_trasnmit_message_struct::tx_efid
uint32_t tx_efid
Definition: gd32f10x_can.h:366
can_working_mode_set
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
set CAN working mode
Definition: gd32f10x_can.c:555
can_parameter_struct::time_triggered
ControlStatus time_triggered
Definition: gd32f10x_can.h:353
RFIFO1_REG_OFFSET
#define RFIFO1_REG_OFFSET
Definition: gd32f10x_can.h:302
can_flag_clear
void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
clear CAN flag state
Definition: gd32f10x_can.c:784
can_flag_get
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
get CAN flag state
Definition: gd32f10x_can.c:756
can_filter_parameter_struct::filter_mask_high
uint16_t filter_mask_high
Definition: gd32f10x_can.h:390
can_debug_freeze_enable
void can_debug_freeze_enable(uint32_t can_periph)
enable CAN debug freeze
Definition: gd32f10x_can.c:238
CAN_FLAG_RFO1
Definition: gd32f10x_can.h:319
CAN_FLAG_MTF1
Definition: gd32f10x_can.h:313
CAN_ERROR_BITDOMINANTER
Definition: gd32f10x_can.h:407
CAN_ERROR_BITRECESSIVE
Definition: gd32f10x_can.h:406
CAN_INT_FLAG_RFO1
Definition: gd32f10x_can.h:342
TSTAT_REG_OFFSET
#define TSTAT_REG_OFFSET
Definition: gd32f10x_can.h:300
can_flag_enum
can_flag_enum
Definition: gd32f10x_can.h:306
CAN_TRANSMIT_NOMAILBOX
Definition: gd32f10x_can.h:418
CAN_TRANSMIT_PENDING
Definition: gd32f10x_can.h:417
can_receive_message_struct::rx_sfid
uint32_t rx_sfid
Definition: gd32f10x_can.h:376
can_receive_message_struct::rx_efid
uint32_t rx_efid
Definition: gd32f10x_can.h:377
can_interrupt_flag_get
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag)
get CAN interrupt flag state
Definition: gd32f10x_can.c:808
can_receive_message_struct::rx_dlen
uint8_t rx_dlen
Definition: gd32f10x_can.h:380
can_message_transmit
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message)
transmit CAN message
Definition: gd32f10x_can.c:329
can_time_trigger_mode_disable
void can_time_trigger_mode_disable(uint32_t can_periph)
disable CAN time trigger mode
Definition: gd32f10x_can.c:303
can_interrupt_flag_clear
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag)
clear CAN interrupt flag state
Definition: gd32f10x_can.c:843
CAN_FLAG_RFF1
Definition: gd32f10x_can.h:320
can_filter_parameter_struct::filter_bits
uint16_t filter_bits
Definition: gd32f10x_can.h:395
can_message_receive
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message)
CAN receive message.
Definition: gd32f10x_can.c:465
can_parameter_struct::trans_fifo_order
ControlStatus trans_fifo_order
Definition: gd32f10x_can.h:358
CAN_TRANSMIT_OK
Definition: gd32f10x_can.h:416
CAN_INT_FLAG_RFF0
Definition: gd32f10x_can.h:340
can_receive_message_length_get
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
CAN receive message length.
Definition: gd32f10x_can.c:530
can_parameter_struct::time_segment_2
uint8_t time_segment_2
Definition: gd32f10x_can.h:352
can_filter_parameter_struct::filter_enable
ControlStatus filter_enable
Definition: gd32f10x_can.h:396
can_wakeup
ErrStatus can_wakeup(uint32_t can_periph)
wake up CAN
Definition: gd32f10x_can.c:614
can_init
ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init)
initialize CAN
Definition: gd32f10x_can.c:59
can_filter_parameter_struct
Definition: gd32f10x_can.h:386
can_fifo_release
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number)
release FIFO0
Definition: gd32f10x_can.c:510
can_parameter_struct::auto_retrans
ControlStatus auto_retrans
Definition: gd32f10x_can.h:356
RFIFO0_REG_OFFSET
#define RFIFO0_REG_OFFSET
Definition: gd32f10x_can.h:301
can_deinit
void can_deinit(uint32_t can_periph)
deinitialize CAN
Definition: gd32f10x_can.c:22
CAN_FLAG_RFF0
Definition: gd32f10x_can.h:317
can_filter_parameter_struct::filter_fifo_number
uint16_t filter_fifo_number
Definition: gd32f10x_can.h:392
can_receive_message_struct
Definition: gd32f10x_can.h:374
CAN_ERROR_CRC
Definition: gd32f10x_can.h:408
CAN_ERROR_FILL
Definition: gd32f10x_can.h:403
can_time_trigger_mode_enable
void can_time_trigger_mode_enable(uint32_t can_periph)
enable CAN time trigger mode
Definition: gd32f10x_can.c:284
CAN_FLAG_PERR
Definition: gd32f10x_can.h:323
can_parameter_struct::working_mode
uint8_t working_mode
Definition: gd32f10x_can.h:349
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_sdio.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_SDIO_H
14 #define GD32F10X_SDIO_H
15
16 #include "gd32f10x.h"
17
18 /* SDIO definitions */
19 #define SDIO SDIO_BASE
20
21 /* registers definitions */
22 #define SDIO_PWRCTL REG32(SDIO + 0x00U)
23 #define SDIO_CLKCTL REG32(SDIO + 0x04U)
24 #define SDIO_CMDAGMT REG32(SDIO + 0x08U)
25 #define SDIO_CMDCTL REG32(SDIO + 0x0CU)
26 #define SDIO_RSPCMDIDX REG32(SDIO + 0x10U)
27 #define SDIO_RESP0 REG32(SDIO + 0x14U)
28 #define SDIO_RESP1 REG32(SDIO + 0x18U)
29 #define SDIO_RESP2 REG32(SDIO + 0x1CU)
30 #define SDIO_RESP3 REG32(SDIO + 0x20U)
31 #define SDIO_DATATO REG32(SDIO + 0x24U)
32 #define SDIO_DATALEN REG32(SDIO + 0x28U)
33 #define SDIO_DATACTL REG32(SDIO + 0x2CU)
34 #define SDIO_DATACNT REG32(SDIO + 0x30U)
35 #define SDIO_STAT REG32(SDIO + 0x34U)
36 #define SDIO_INTC REG32(SDIO + 0x38U)
37 #define SDIO_INTEN REG32(SDIO + 0x3CU)
38 #define SDIO_FIFOCNT REG32(SDIO + 0x48U)
39 #define SDIO_FIFO REG32(SDIO + 0x80U)
41 /* bits definitions */
42 /* SDIO_PWRCTL */
43 #define SDIO_PWRCTL_PWRCTL BITS(0,1)
45 /* SDIO_CLKCTL */
46 #define SDIO_CLKCTL_DIV BITS(0,7)
47 #define SDIO_CLKCTL_CLKEN BIT(8)
48 #define SDIO_CLKCTL_CLKPWRSAV BIT(9)
49 #define SDIO_CLKCTL_CLKBYP BIT(10)
50 #define SDIO_CLKCTL_BUSMODE BITS(11,12)
51 #define SDIO_CLKCTL_CLKEDGE BIT(13)
52 #define SDIO_CLKCTL_HWCLKEN BIT(14)
54 /* SDIO_CMDAGMT */
55 #define SDIO_CMDAGMT_CMDAGMT BITS(0,31)
57 /* SDIO_CMDCTL */
58 #define SDIO_CMDCTL_CMDIDX BITS(0,5)
59 #define SDIO_CMDCTL_CMDRESP BITS(6,7)
60 #define SDIO_CMDCTL_INTWAIT BIT(8)
61 #define SDIO_CMDCTL_WAITDEND BIT(9)
62 #define SDIO_CMDCTL_CSMEN BIT(10)
63 #define SDIO_CMDCTL_SUSPEND BIT(11)
64 #define SDIO_CMDCTL_ENCMDC BIT(12)
65 #define SDIO_CMDCTL_NINTEN BIT(13)
66 #define SDIO_CMDCTL_ATAEN BIT(14)
68 /* SDIO_DATATO */
69 #define SDIO_DATATO_DATATO BITS(0,31)
71 /* SDIO_DATALEN */
72 #define SDIO_DATALEN_DATALEN BITS(0,24)
74 /* SDIO_DATACTL */
75 #define SDIO_DATACTL_DATAEN BIT(0)
76 #define SDIO_DATACTL_DATADIR BIT(1)
77 #define SDIO_DATACTL_TRANSMOD BIT(2)
78 #define SDIO_DATACTL_DMAEN BIT(3)
79 #define SDIO_DATACTL_BLKSZ BITS(4,7)
80 #define SDIO_DATACTL_RWEN BIT(8)
81 #define SDIO_DATACTL_RWSTOP BIT(9)
82 #define SDIO_DATACTL_RWTYPE BIT(10)
83 #define SDIO_DATACTL_IOEN BIT(11)
85 /* SDIO_STAT */
86 #define SDIO_STAT_CCRCERR BIT(0)
87 #define SDIO_STAT_DTCRCERR BIT(1)
88 #define SDIO_STAT_CMDTMOUT BIT(2)
89 #define SDIO_STAT_DTTMOUT BIT(3)
90 #define SDIO_STAT_TXURE BIT(4)
91 #define SDIO_STAT_RXORE BIT(5)
92 #define SDIO_STAT_CMDRECV BIT(6)
93 #define SDIO_STAT_CMDSEND BIT(7)
94 #define SDIO_STAT_DTEND BIT(8)
95 #define SDIO_STAT_STBITE BIT(9)
96 #define SDIO_STAT_DTBLKEND BIT(10)
97 #define SDIO_STAT_CMDRUN BIT(11)
98 #define SDIO_STAT_TXRUN BIT(12)
99 #define SDIO_STAT_RXRUN BIT(13)
100 #define SDIO_STAT_TFH BIT(14)
101 #define SDIO_STAT_RFH BIT(15)
102 #define SDIO_STAT_TFF BIT(16)
103 #define SDIO_STAT_RFF BIT(17)
104 #define SDIO_STAT_TFE BIT(18)
105 #define SDIO_STAT_RFE BIT(19)
106 #define SDIO_STAT_TXDTVAL BIT(20)
107 #define SDIO_STAT_RXDTVAL BIT(21)
108 #define SDIO_STAT_SDIOINT BIT(22)
109 #define SDIO_STAT_ATAEND BIT(23)
111 /* SDIO_INTC */
112 #define SDIO_INTC_CCRCERRC BIT(0)
113 #define SDIO_INTC_DTCRCERRC BIT(1)
114 #define SDIO_INTC_CMDTMOUTC BIT(2)
115 #define SDIO_INTC_DTTMOUTC BIT(3)
116 #define SDIO_INTC_TXUREC BIT(4)
117 #define SDIO_INTC_RXOREC BIT(5)
118 #define SDIO_INTC_CMDRECVC BIT(6)
119 #define SDIO_INTC_CMDSENDC BIT(7)
120 #define SDIO_INTC_DTENDC BIT(8)
121 #define SDIO_INTC_STBITEC BIT(9)
122 #define SDIO_INTC_DTBLKENDC BIT(10)
123 #define SDIO_INTC_SDIOINTC BIT(22)
124 #define SDIO_INTC_ATAENDC BIT(23)
126 /* SDIO_INTEN */
127 #define SDIO_INTEN_CCRCERRIE BIT(0)
128 #define SDIO_INTEN_DTCRCERRIE BIT(1)
129 #define SDIO_INTEN_CMDTMOUTIE BIT(2)
130 #define SDIO_INTEN_DTTMOUTIE BIT(3)
131 #define SDIO_INTEN_TXUREIE BIT(4)
132 #define SDIO_INTEN_RXOREIE BIT(5)
133 #define SDIO_INTEN_CMDRECVIE BIT(6)
134 #define SDIO_INTEN_CMDSENDIE BIT(7)
135 #define SDIO_INTEN_DTENDIE BIT(8)
136 #define SDIO_INTEN_STBITEIE BIT(9)
137 #define SDIO_INTEN_DTBLKENDIE BIT(10)
138 #define SDIO_INTEN_CMDRUNIE BIT(11)
139 #define SDIO_INTEN_TXRUNIE BIT(12)
140 #define SDIO_INTEN_RXRUNIE BIT(13)
141 #define SDIO_INTEN_TFHIE BIT(14)
142 #define SDIO_INTEN_RFHIE BIT(15)
143 #define SDIO_INTEN_TFFIE BIT(16)
144 #define SDIO_INTEN_RFFIE BIT(17)
145 #define SDIO_INTEN_TFEIE BIT(18)
146 #define SDIO_INTEN_RFEIE BIT(19)
147 #define SDIO_INTEN_TXDTVALIE BIT(20)
148 #define SDIO_INTEN_RXDTVALIE BIT(21)
149 #define SDIO_INTEN_SDIOINTIE BIT(22)
150 #define SDIO_INTEN_ATAENDIE BIT(23)
152 /* SDIO_FIFO */
153 #define SDIO_FIFO_FIFODT BITS(0,31)
155 /* constants definitions */
156 /* SDIO flags */
157 #define SDIO_FLAG_CCRCERR BIT(0)
158 #define SDIO_FLAG_DTCRCERR BIT(1)
159 #define SDIO_FLAG_CMDTMOUT BIT(2)
160 #define SDIO_FLAG_DTTMOUT BIT(3)
161 #define SDIO_FLAG_TXURE BIT(4)
162 #define SDIO_FLAG_RXORE BIT(5)
163 #define SDIO_FLAG_CMDRECV BIT(6)
164 #define SDIO_FLAG_CMDSEND BIT(7)
165 #define SDIO_FLAG_DTEND BIT(8)
166 #define SDIO_FLAG_STBITE BIT(9)
167 #define SDIO_FLAG_DTBLKEND BIT(10)
168 #define SDIO_FLAG_CMDRUN BIT(11)
169 #define SDIO_FLAG_TXRUN BIT(12)
170 #define SDIO_FLAG_RXRUN BIT(13)
171 #define SDIO_FLAG_TFH BIT(14)
172 #define SDIO_FLAG_RFH BIT(15)
173 #define SDIO_FLAG_TFF BIT(16)
174 #define SDIO_FLAG_RFF BIT(17)
175 #define SDIO_FLAG_TFE BIT(18)
176 #define SDIO_FLAG_RFE BIT(19)
177 #define SDIO_FLAG_TXDTVAL BIT(20)
178 #define SDIO_FLAG_RXDTVAL BIT(21)
179 #define SDIO_FLAG_SDIOINT BIT(22)
180 #define SDIO_FLAG_ATAEND BIT(23)
182 /* SDIO interrupt enable or disable */
183 #define SDIO_INT_CCRCERR BIT(0)
184 #define SDIO_INT_DTCRCERR BIT(1)
185 #define SDIO_INT_CMDTMOUT BIT(2)
186 #define SDIO_INT_DTTMOUT BIT(3)
187 #define SDIO_INT_TXURE BIT(4)
188 #define SDIO_INT_RXORE BIT(5)
189 #define SDIO_INT_CMDRECV BIT(6)
190 #define SDIO_INT_CMDSEND BIT(7)
191 #define SDIO_INT_DTEND BIT(8)
192 #define SDIO_INT_STBITE BIT(9)
193 #define SDIO_INT_DTBLKEND BIT(10)
194 #define SDIO_INT_CMDRUN BIT(11)
195 #define SDIO_INT_TXRUN BIT(12)
196 #define SDIO_INT_RXRUN BIT(13)
197 #define SDIO_INT_TFH BIT(14)
198 #define SDIO_INT_RFH BIT(15)
199 #define SDIO_INT_TFF BIT(16)
200 #define SDIO_INT_RFF BIT(17)
201 #define SDIO_INT_TFE BIT(18)
202 #define SDIO_INT_RFE BIT(19)
203 #define SDIO_INT_TXDTVAL BIT(20)
204 #define SDIO_INT_RXDTVAL BIT(21)
205 #define SDIO_INT_SDIOINT BIT(22)
206 #define SDIO_INT_ATAEND BIT(23)
208 /* SDIO interrupt flags */
209 #define SDIO_INT_FLAG_CCRCERR BIT(0)
210 #define SDIO_INT_FLAG_DTCRCERR BIT(1)
211 #define SDIO_INT_FLAG_CMDTMOUT BIT(2)
212 #define SDIO_INT_FLAG_DTTMOUT BIT(3)
213 #define SDIO_INT_FLAG_TXURE BIT(4)
214 #define SDIO_INT_FLAG_RXORE BIT(5)
215 #define SDIO_INT_FLAG_CMDRECV BIT(6)
216 #define SDIO_INT_FLAG_CMDSEND BIT(7)
217 #define SDIO_INT_FLAG_DTEND BIT(8)
218 #define SDIO_INT_FLAG_STBITE BIT(9)
219 #define SDIO_INT_FLAG_DTBLKEND BIT(10)
220 #define SDIO_INT_FLAG_CMDRUN BIT(11)
221 #define SDIO_INT_FLAG_TXRUN BIT(12)
222 #define SDIO_INT_FLAG_RXRUN BIT(13)
223 #define SDIO_INT_FLAG_TFH BIT(14)
224 #define SDIO_INT_FLAG_RFH BIT(15)
225 #define SDIO_INT_FLAG_TFF BIT(16)
226 #define SDIO_INT_FLAG_RFF BIT(17)
227 #define SDIO_INT_FLAG_TFE BIT(18)
228 #define SDIO_INT_FLAG_RFE BIT(19)
229 #define SDIO_INT_FLAG_TXDTVAL BIT(20)
230 #define SDIO_INT_FLAG_RXDTVAL BIT(21)
231 #define SDIO_INT_FLAG_SDIOINT BIT(22)
232 #define SDIO_INT_FLAG_ATAEND BIT(23)
234 /* SDIO power control */
235 #define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
236 #define SDIO_POWER_OFF PWRCTL_PWRCTL(0)
237 #define SDIO_POWER_ON PWRCTL_PWRCTL(3)
239 /* SDIO card bus mode control */
240 #define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
241 #define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0)
242 #define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1)
243 #define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2)
245 /* SDIO_CLK clock edge selection */
246 #define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U
247 #define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE
249 /* clock bypass enable or disable */
250 #define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U
251 #define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP
253 /* SDIO_CLK clock dynamic switch on/off for power saving */
254 #define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U
255 #define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV
257 /* SDIO command response type */
258 #define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
259 #define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0)
260 #define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1)
261 #define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3)
263 /* command state machine wait type */
264 #define SDIO_WAITTYPE_NO (uint32_t)0x00000000U
265 #define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT
266 #define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND
268 #define SDIO_RESPONSE0 (uint32_t)0x00000000U
269 #define SDIO_RESPONSE1 (uint32_t)0x00000001U
270 #define SDIO_RESPONSE2 (uint32_t)0x00000002U
271 #define SDIO_RESPONSE3 (uint32_t)0x00000003U
273 /* SDIO data block size */
274 #define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
275 #define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0)
276 #define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1)
277 #define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2)
278 #define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3)
279 #define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4)
280 #define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5)
281 #define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6)
282 #define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7)
283 #define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8)
284 #define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9)
285 #define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10)
286 #define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11)
287 #define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12)
288 #define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13)
289 #define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14)
291 /* SDIO data transfer mode */
292 #define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U
293 #define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD
295 /* SDIO data transfer direction */
296 #define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U
297 #define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR
299 /* SDIO read wait type */
300 #define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U
301 #define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE
303 /* function declarations */
304 /* deinitialize the SDIO */
305 void sdio_deinit(void);
306 /* configure the SDIO clock */
307 void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division);
308 /* enable hardware clock control */
309 void sdio_hardware_clock_enable(void);
310 /* disable hardware clock control */
311 void sdio_hardware_clock_disable(void);
312 /* set different SDIO card bus mode */
313 void sdio_bus_mode_set(uint32_t bus_mode);
314 /* set the SDIO power state */
315 void sdio_power_state_set(uint32_t power_state);
316 /* get the SDIO power state */
317 uint32_t sdio_power_state_get(void);
318 /* enable SDIO_CLK clock output */
319 void sdio_clock_enable(void);
320 /* disable SDIO_CLK clock output */
321 void sdio_clock_disable(void);
322
323 /* configure the command index, argument, response type, wait type and CSM to send command */
324 /* configure the command and response */
325 void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
326 /* set the command state machine wait type */
327 void sdio_wait_type_set(uint32_t wait_type);
328 /* enable the CSM(command state machine) */
329 void sdio_csm_enable(void);
330 /* disable the CSM(command state machine) */
331 void sdio_csm_disable(void);
332 /* get the last response command index */
333 uint8_t sdio_command_index_get(void);
334 /* get the response for the last received command */
335 uint32_t sdio_response_get(uint32_t responsex);
336
337 /* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */
338 /* configure the data timeout, data length and data block size */
339 void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
340 /* configure the data transfer mode and direction */
341 void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction);
342 /* enable the DSM(data state machine) for data transfer */
343 void sdio_dsm_enable(void);
344 /* disable the DSM(data state machine) */
345 void sdio_dsm_disable(void);
346 /* write data(one word) to the transmit FIFO */
347 void sdio_data_write(uint32_t data);
348 /* read data(one word) from the receive FIFO */
349 uint32_t sdio_data_read(void);
350 /* get the number of remaining data bytes to be transferred to card */
351 uint32_t sdio_data_counter_get(void);
352 /* get the number of words remaining to be written or read from FIFO */
353 uint32_t sdio_fifo_counter_get(void);
354 /* enable the DMA request for SDIO */
355 void sdio_dma_enable(void);
356 /* disable the DMA request for SDIO */
357 void sdio_dma_disable(void);
358
359 /* get the flags state of SDIO */
360 FlagStatus sdio_flag_get(uint32_t flag);
361 /* clear the pending flags of SDIO */
362 void sdio_flag_clear(uint32_t flag);
363 /* enable the SDIO interrupt */
364 void sdio_interrupt_enable(uint32_t int_flag);
365 /* disable the SDIO interrupt */
366 void sdio_interrupt_disable(uint32_t int_flag);
367 /* get the interrupt flags state of SDIO */
368 FlagStatus sdio_interrupt_flag_get(uint32_t int_flag);
369 /* clear the interrupt pending flags of SDIO */
370 void sdio_interrupt_flag_clear(uint32_t int_flag);
371
372 /* enable the read wait mode(SD I/O only) */
373 void sdio_readwait_enable(void);
374 /* disable the read wait mode(SD I/O only) */
375 void sdio_readwait_disable(void);
376 /* enable the function that stop the read wait process(SD I/O only) */
377 void sdio_stop_readwait_enable(void);
378 /* disable the function that stop the read wait process(SD I/O only) */
379 void sdio_stop_readwait_disable(void);
380 /* set the read wait type(SD I/O only) */
381 void sdio_readwait_type_set(uint32_t readwait_type);
382 /* enable the SD I/O mode specific operation(SD I/O only) */
383 void sdio_operation_enable(void);
384 /* disable the SD I/O mode specific operation(SD I/O only) */
385 void sdio_operation_disable(void);
386 /* enable the SD I/O suspend operation(SD I/O only) */
387 void sdio_suspend_enable(void);
388 /* disable the SD I/O suspend operation(SD I/O only) */
389 void sdio_suspend_disable(void);
390
391 /* enable the CE-ATA command(CE-ATA only) */
392 void sdio_ceata_command_enable(void);
393 /* disable the CE-ATA command(CE-ATA only) */
394 void sdio_ceata_command_disable(void);
395 /* enable the CE-ATA interrupt(CE-ATA only) */
396 void sdio_ceata_interrupt_enable(void);
397 /* disable the CE-ATA interrupt(CE-ATA only) */
398 void sdio_ceata_interrupt_disable(void);
399 /* enable the CE-ATA command completion signal(CE-ATA only) */
400 void sdio_ceata_command_completion_enable(void);
401 /* disable the CE-ATA command completion signal(CE-ATA only) */
402 void sdio_ceata_command_completion_disable(void);
403
404 #endif /* GD32F10X_SDIO_H */
sdio_data_write
void sdio_data_write(uint32_t data)
write data(one word) to the transmit FIFO
Definition: gd32f10x_sdio.c:339
sdio_ceata_command_completion_enable
void sdio_ceata_command_completion_enable(void)
enable the CE-ATA command completion signal(CE-ATA only)
Definition: gd32f10x_sdio.c:755
sdio_power_state_get
uint32_t sdio_power_state_get(void)
get the SDIO power state
Definition: gd32f10x_sdio.c:122
sdio_ceata_command_completion_disable
void sdio_ceata_command_completion_disable(void)
disable the CE-ATA command completion signal(CE-ATA only)
Definition: gd32f10x_sdio.c:766
sdio_fifo_counter_get
uint32_t sdio_fifo_counter_get(void)
get the number of words remaining to be written or read from FIFO
Definition: gd32f10x_sdio.c:372
sdio_clock_config
void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division)
configure the SDIO clock
Definition: gd32f10x_sdio.c:51
sdio_command_index_get
uint8_t sdio_command_index_get(void)
get the last response command index
Definition: gd32f10x_sdio.c:218
sdio_bus_mode_set
void sdio_bus_mode_set(uint32_t bus_mode)
set different SDIO card bus mode
Definition: gd32f10x_sdio.c:94
sdio_clock_enable
void sdio_clock_enable(void)
enable SDIO_CLK clock output
Definition: gd32f10x_sdio.c:133
sdio_data_counter_get
uint32_t sdio_data_counter_get(void)
get the number of remaining data bytes to be transferred to card
Definition: gd32f10x_sdio.c:361
sdio_data_transfer_config
void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction)
configure the data transfer mode and direction
Definition: gd32f10x_sdio.c:301
sdio_dsm_disable
void sdio_dsm_disable(void)
disable the DSM(data state machine)
Definition: gd32f10x_sdio.c:328
sdio_readwait_disable
void sdio_readwait_disable(void)
disable the read wait mode(SD I/O only)
Definition: gd32f10x_sdio.c:617
sdio_ceata_command_disable
void sdio_ceata_command_disable(void)
disable the CE-ATA command(CE-ATA only)
Definition: gd32f10x_sdio.c:722
sdio_dma_enable
void sdio_dma_enable(void)
enable the DMA request for SDIO
Definition: gd32f10x_sdio.c:383
sdio_readwait_enable
void sdio_readwait_enable(void)
enable the read wait mode(SD I/O only)
Definition: gd32f10x_sdio.c:606
sdio_dsm_enable
void sdio_dsm_enable(void)
enable the DSM(data state machine) for data transfer
Definition: gd32f10x_sdio.c:317
sdio_response_get
uint32_t sdio_response_get(uint32_t responsex)
get the response for the last received command
Definition: gd32f10x_sdio.c:233
sdio_csm_disable
void sdio_csm_disable(void)
disable the CSM(command state machine)
Definition: gd32f10x_sdio.c:207
sdio_flag_clear
void sdio_flag_clear(uint32_t flag)
clear the pending flags of SDIO
Definition: gd32f10x_sdio.c:457
sdio_suspend_disable
void sdio_suspend_disable(void)
disable the SD I/O suspend operation(SD I/O only)
Definition: gd32f10x_sdio.c:700
sdio_interrupt_flag_get
FlagStatus sdio_interrupt_flag_get(uint32_t int_flag)
get the interrupt flags state of SDIO
Definition: gd32f10x_sdio.c:562
sdio_ceata_interrupt_disable
void sdio_ceata_interrupt_disable(void)
disable the CE-ATA interrupt(CE-ATA only)
Definition: gd32f10x_sdio.c:744
sdio_flag_get
FlagStatus sdio_flag_get(uint32_t flag)
get the flags state of SDIO
Definition: gd32f10x_sdio.c:429
sdio_hardware_clock_disable
void sdio_hardware_clock_disable(void)
disable hardware clock control
Definition: gd32f10x_sdio.c:80
sdio_clock_disable
void sdio_clock_disable(void)
disable SDIO_CLK clock output
Definition: gd32f10x_sdio.c:144
sdio_deinit
void sdio_deinit(void)
deinitialize the SDIO
Definition: gd32f10x_sdio.c:23
sdio_interrupt_disable
void sdio_interrupt_disable(uint32_t int_flag)
disable the SDIO interrupt
Definition: gd32f10x_sdio.c:527
sdio_hardware_clock_enable
void sdio_hardware_clock_enable(void)
enable hardware clock control
Definition: gd32f10x_sdio.c:69
sdio_wait_type_set
void sdio_wait_type_set(uint32_t wait_type)
set the command state machine wait type
Definition: gd32f10x_sdio.c:182
sdio_data_read
uint32_t sdio_data_read(void)
read data(one word) from the receive FIFO
Definition: gd32f10x_sdio.c:350
sdio_power_state_set
void sdio_power_state_set(uint32_t power_state)
set the SDIO power state
Definition: gd32f10x_sdio.c:109
sdio_operation_disable
void sdio_operation_disable(void)
disable the SD I/O mode specific operation(SD I/O only)
Definition: gd32f10x_sdio.c:678
sdio_readwait_type_set
void sdio_readwait_type_set(uint32_t readwait_type)
set the read wait type(SD I/O only)
Definition: gd32f10x_sdio.c:652
sdio_ceata_command_enable
void sdio_ceata_command_enable(void)
enable the CE-ATA command(CE-ATA only)
Definition: gd32f10x_sdio.c:711
sdio_suspend_enable
void sdio_suspend_enable(void)
enable the SD I/O suspend operation(SD I/O only)
Definition: gd32f10x_sdio.c:689
sdio_csm_enable
void sdio_csm_enable(void)
enable the CSM(command state machine)
Definition: gd32f10x_sdio.c:196
sdio_command_response_config
void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type)
configure the command and response
Definition: gd32f10x_sdio.c:160
sdio_data_config
void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize)
configure the data timeout, data length and data block size
Definition: gd32f10x_sdio.c:278
sdio_stop_readwait_enable
void sdio_stop_readwait_enable(void)
enable the function that stop the read wait process(SD I/O only)
Definition: gd32f10x_sdio.c:628
sdio_operation_enable
void sdio_operation_enable(void)
enable the SD I/O mode specific operation(SD I/O only)
Definition: gd32f10x_sdio.c:667
sdio_stop_readwait_disable
void sdio_stop_readwait_disable(void)
disable the function that stop the read wait process(SD I/O only)
Definition: gd32f10x_sdio.c:639
sdio_ceata_interrupt_enable
void sdio_ceata_interrupt_enable(void)
enable the CE-ATA interrupt(CE-ATA only)
Definition: gd32f10x_sdio.c:733
sdio_interrupt_enable
void sdio_interrupt_enable(uint32_t int_flag)
enable the SDIO interrupt
Definition: gd32f10x_sdio.c:492
sdio_dma_disable
void sdio_dma_disable(void)
disable the DMA request for SDIO
Definition: gd32f10x_sdio.c:394
sdio_interrupt_flag_clear
void sdio_interrupt_flag_clear(uint32_t int_flag)
clear the interrupt pending flags of SDIO
Definition: gd32f10x_sdio.c:595
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_regs.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
usbd_regs.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBD_REGS_H
14 #define USBD_REGS_H
15
16 #include "usbd_conf.h"
17
18 /* USB device registers base address */
19 #define USBD USBD_BASE
20 #define USBD_RAM (APB1_BUS_BASE + 0x00006000U)
21
22 /* registers definitions */
23 /* common registers */
24 #define USBD_CTL (REG32(USBD + 0x40U))
25 #define USBD_INTF (REG32(USBD + 0x44U))
26 #define USBD_STAT (REG32(USBD + 0x48U))
27 #define USBD_DADDR (REG32(USBD + 0x4CU))
28 #define USBD_BADDR (REG32(USBD + 0x50U))
30 /* endpoint control and status register */
31 #define USBD_EPxCS(ep_id) (REG32(USBD + (ep_id) * 4U))
33 /* LPM Registers */
34 #define USBD_LPMCS (REG32(USBD + 0x54U))
36 /* bits definitions */
37 /* USBD_CTL */
38 #define CTL_STIE BIT(15)
39 #define CTL_PMOUIE BIT(14)
40 #define CTL_ERRIE BIT(13)
41 #define CTL_WKUPIE BIT(12)
42 #define CTL_SPSIE BIT(11)
43 #define CTL_RSTIE BIT(10)
44 #define CTL_SOFIE BIT(9)
45 #define CTL_ESOFIE BIT(8)
46 #define CTL_L1REQIE BIT(7)
47 #define CTL_L1RSREQ BIT(5)
48 #define CTL_RSREQ BIT(4)
49 #define CTL_SETSPS BIT(3)
50 #define CTL_LOWM BIT(2)
51 #define CTL_CLOSE BIT(1)
52 #define CTL_SETRST BIT(0)
54 /* USBD_INTF */
55 #define INTF_STIF BIT(15)
56 #define INTF_PMOUIF BIT(14)
57 #define INTF_ERRIF BIT(13)
58 #define INTF_WKUPIF BIT(12)
59 #define INTF_SPSIF BIT(11)
60 #define INTF_RSTIF BIT(10)
61 #define INTF_SOFIF BIT(9)
62 #define INTF_ESOFIF BIT(8)
63 #define INTF_L1REQ BIT(7)
64 #define INTF_DIR BIT(4)
65 #define INTF_EPNUM BITS(0, 3)
67 /* USBD_STAT */
68 #define STAT_RXDP BIT(15)
69 #define STAT_RXDM BIT(14)
70 #define STAT_LOCK BIT(13)
71 #define STAT_SOFLN BITS(11, 12)
72 #define STAT_FCNT BITS(0, 10)
74 /* USBD_DADDR */
75 #define DADDR_USBEN BIT(7)
76 #define DADDR_USBDAR BITS(0, 6)
78 /* USBD_EPxCS */
79 #define EPxCS_RX_ST BIT(15)
80 #define EPxCS_RX_DTG BIT(14)
81 #define EPxCS_RX_STA BITS(12, 13)
82 #define EPxCS_SETUP BIT(11)
83 #define EPxCS_CTL BITS(9, 10)
84 #define EPxCS_KCTL BIT(8)
85 #define EPxCS_TX_ST BIT(7)
86 #define EPxCS_TX_DTG BIT(6)
87 #define EPxCS_TX_STA BITS(4, 5)
88 #define EPxCS_ADDR BITS(0, 3)
90 /* USBD_LPMCS */
91 #define LPMCS_BLSTAT BITS(4, 7)
92 #define LPMCS_REMWK BIT(3)
93 #define LPMCS_LPMACK BIT(1)
94 #define LPMCS_LPMEN BIT(0)
96 /* constants definitions */
97 /* endpoint control and status register mask (no toggle fields) */
98 #define EPCS_MASK (EPxCS_RX_ST|EPxCS_SETUP|EPxCS_CTL|EPxCS_KCTL|EPxCS_TX_ST|EPxCS_ADDR)
99
100 /* EPxCS_CTL[1:0] endpoint type control */
101 #define ENDP_TYPE(regval) (EPxCS_CTL & ((regval) << 9U))
102
103 #define EP_BULK ENDP_TYPE(0U) /* bulk transfers */
104 #define EP_CONTROL ENDP_TYPE(1U) /* control transfers */
105 #define EP_ISO ENDP_TYPE(2U) /* isochronous transfers */
106 #define EP_INTERRUPT ENDP_TYPE(3U) /* interrupt transfers */
107 #define EP_CTL_MASK (~EPxCS_CTL & EPCS_MASK)
108
109 /* endpoint kind control mask */
110 #define EPKCTL_MASK (~EPxCS_KCTL & EPCS_MASK)
111
112 /* EPxCS_TX_STA[1:0] status for Tx transfer */
113 #define ENDP_TXSTAT(regval) (EPxCS_TX_STA & ((regval) << 4U))
114
115 #define EPTX_DISABLED ENDP_TXSTAT(0U) /* transmission state is disabled */
116 #define EPTX_STALL ENDP_TXSTAT(1U) /* transmission state is STALL */
117 #define EPTX_NAK ENDP_TXSTAT(2U) /* transmission state is NAK */
118 #define EPTX_VALID ENDP_TXSTAT(3U) /* transmission state is enabled */
119 #define EPTX_DTGMASK (EPxCS_TX_STA | EPCS_MASK)
120
121 /* EPxCS_RX_STA[1:0] status for Rx transfer */
122 #define ENDP_RXSTAT(regval) (EPxCS_RX_STA & ((regval) << 12U))
123
124 #define EPRX_DISABLED ENDP_RXSTAT(0U) /* reception state is disabled */
125 #define EPRX_STALL ENDP_RXSTAT(1U) /* reception state is STALL */
126 #define EPRX_NAK ENDP_RXSTAT(2U) /* reception state is NAK */
127 #define EPRX_VALID ENDP_RXSTAT(3U) /* reception state is enabled */
128 #define EPRX_DTGMASK (EPxCS_RX_STA | EPCS_MASK)
129
130 /* endpoint receive/transmission counter register bit definitions */
131 #define EPRCNT_BLKSIZ BIT(15) /* reception data block size */
132 #define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */
133 #define EPRCNT_CNT BITS(0, 9) /* reception data count */
134
135 #define EPTCNT_CNT BITS(0, 9) /* transmisson data count */
136
137 /* interrupt flag clear bits */
138 #define CLR_STIF (~INTF_STIF)
139 #define CLR_PMOUIF (~INTF_PMOUIF)
140 #define CLR_ERRIF (~INTF_ERRIF)
141 #define CLR_WKUPIF (~INTF_WKUPIF)
142 #define CLR_SPSIF (~INTF_SPSIF)
143 #define CLR_RSTIF (~INTF_RSTIF)
144 #define CLR_SOFIF (~INTF_SOFIF)
145 #define CLR_ESOFIF (~INTF_ESOFIF)
146 #define CLR_L1REQ (~INTF_L1REQ)
147
148 /* endpoint receive/transmission counter register bit offset */
149 #define BLKSIZE_OFFSET (0x01U)
150 #define BLKNUM_OFFSET (0x05U)
151 #define RXCNT_OFFSET (0x0AU)
152
153 #define TXCNT_OFFSET (0x0AU)
154
155 #define BLKSIZE32_MASK (0x1fU)
156 #define BLKSIZE2_MASK (0x01U)
157
158 #define BLKSIZE32_OFFSETMASK (0x05U)
159 #define BLKSIZE2_OFFSETMASK (0x01U)
160
161 /* double buffer endpoint direction */
162 typedef enum
163 {
164 DBUF_EP_IN, /* double buffer IN direction */
165 DBUF_EP_OUT, /* double buffer OUT direction */
166 DBUF_EP_ERR, /* double buffer errer direction */
167 }dbuf_ep_dir_enum;
168
169 /* endpoints address */
170 /* first bit is direction(0 for Rx and 1 for Tx) */
171 #define EP0_OUT ((uint8_t)0x00) /* OUT endpoint 0 address */
172 #define EP0_IN ((uint8_t)0x80) /* IN endpoint 0 address */
173 #define EP1_OUT ((uint8_t)0x01) /* OUT endpoint 1 address */
174 #define EP1_IN ((uint8_t)0x81) /* IN endpoint 1 address */
175 #define EP2_OUT ((uint8_t)0x02) /* OUT endpoint 2 address */
176 #define EP2_IN ((uint8_t)0x82) /* IN endpoint 2 address */
177 #define EP3_OUT ((uint8_t)0x03) /* OUT endpoint 3 address */
178 #define EP3_IN ((uint8_t)0x83) /* IN endpoint 3 address */
179 #define EP4_OUT ((uint8_t)0x04) /* OUT endpoint 4 address */
180 #define EP4_IN ((uint8_t)0x84) /* IN endpoint 4 address */
181 #define EP5_OUT ((uint8_t)0x05) /* OUT endpoint 5 address */
182 #define EP5_IN ((uint8_t)0x85) /* IN endpoint 5 address */
183 #define EP6_OUT ((uint8_t)0x06) /* OUT endpoint 6 address */
184 #define EP6_IN ((uint8_t)0x86) /* IN endpoint 6 address */
185 #define EP7_OUT ((uint8_t)0x07) /* OUT endpoint 7 address */
186 #define EP7_IN ((uint8_t)0x87) /* IN endpoint 7 address */
187
188 /* endpoints_Identifier */
189 #define EP0 ((uint8_t)0) /* endpoint 0 ID */
190 #define EP1 ((uint8_t)1) /* endpoint 1 ID */
191 #define EP2 ((uint8_t)2) /* endpoint 2 ID */
192 #define EP3 ((uint8_t)3) /* endpoint 3 ID */
193 #define EP4 ((uint8_t)4) /* endpoint 4 ID */
194 #define EP5 ((uint8_t)5) /* endpoint 5 ID */
195 #define EP6 ((uint8_t)6) /* endpoint 6 ID */
196 #define EP7 ((uint8_t)7) /* endpoint 7 ID */
197
198 /* USBD operation macros */
199
200 /* set register value */
201 #define USBD_REG_SET(reg, regvalue) ((reg) = (uint16_t)(regvalue))
202
203 /* get register value */
204 #define USBD_REG_GET(reg) ((uint16_t)(reg))
205
206 #define _EP_ADDR_SET(ep_num, addr) USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK) | addr)
207
208 /* Tx or Rx transfer status setting (bits EPTX_STA[1:0]) */
209 #define USBD_ENDP_TX_STATUS_SET(ep_num, state) do {\
210 register uint16_t _regval; \
211 _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPTX_DTGMASK;\
212 USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \
213 } while(0)
214
215 #define USBD_ENDP_RX_STATUS_SET(ep_num, state) do {\
216 register uint16_t _regval; \
217 _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPRX_DTGMASK;\
218 USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \
219 } while(0)
220
221 /* Tx or Rx transfer status getting (bits EPxCS_RX_STA[1:0]) */
222 #define USBD_ENDP_TX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_STA)
223 #define USBD_ENDP_RX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_STA)
224
225 /* Rx and Tx transfer status setting (bits EPxCS_RX_STA[1:0] & EPxCS_TX_STA[1:0]) */
226 #define USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx) do {\
227 register uint16_t _regval; \
228 _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)(EPRX_DTGMASK | EPxCS_TX_STA) ;\
229 USBD_REG_SET(USBD_EPxCS(ep_num), (((_regval) ^ (state_rx)) ^ (state_tx))); \
230 } while(0)
231
232 /* set and clear endpoint kind (bit EPxCS_KCTL) */
233 #define USBD_ENDP_KIND_SET(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), ((USBD_REG_GET(USBD_EPxCS(ep_num)) | EPxCS_KCTL) & EPCS_MASK)))
234 #define USBD_ENDP_KIND_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPKCTL_MASK)))
235
236 /* set and clear directly STATUS_OUT state of endpoint */
237 #define USBD_STATUS_OUT_SET(ep_num) USBD_ENDP_KIND_SET(ep_num)
238 #define USBD_STATUS_OUT_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num)
239
240 /* clear bit EPxCS_RX_ST/EPxCS_TX_ST in the endpoint control and status register */
241 #define USBD_ENDP_RX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0x7FFFU & (uint16_t)EPCS_MASK))
242 #define USBD_ENDP_TX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0xFF7FU & (uint16_t)EPCS_MASK))
243
244 /* toggle EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */
245 #define USBD_DTG_RX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_RX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK)))
246 #define USBD_DTG_TX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_TX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK)))
247
248 /* clear EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */
249 #define USBD_DTG_RX_CLEAR(ep_num) do {\
250 if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_DTG) != 0U) {\
251 USBD_DTG_RX_TOGGLE(ep_num);\
252 } else {\
253 }\
254 } while(0)
255
256 #define USBD_DTG_TX_CLEAR(ep_num) do {\
257 if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_DTG) != 0U) {\
258 USBD_DTG_TX_TOGGLE(ep_num);\
259 } else {\
260 }\
261 } while(0)
262
263 /* set and clear directly double buffered feature of endpoint */
264 #define USBD_ENDP_DOUBLE_BUF_SET(ep_num) USBD_ENDP_KIND_SET(ep_num)
265 #define USBD_ENDP_DOUBLE_BUF_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num)
266
267 /* toggle SW_BUF bit in the double buffered endpoint */
268 #define USBD_SWBUF_TX_TOGGLE(ep_num) USBD_DTG_RX_TOGGLE(ep_num)
269 #define USBD_SWBUF_RX_TOGGLE(ep_num) USBD_DTG_TX_TOGGLE(ep_num)
270
271 #endif /* USBD_REGS_H */
DBUF_EP_IN
Definition: usbd_regs.h:164
dbuf_ep_dir_enum
dbuf_ep_dir_enum
Definition: usbd_regs.h:162
DBUF_EP_ERR
Definition: usbd_regs.h:166
DBUF_EP_OUT
Definition: usbd_regs.h:165
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_dma.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_dma.h"
14
15 #define DMA_WRONG_HANDLE while(1){}
16
17 static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx);
18
28 void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
29 {
30 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
31 DMA_WRONG_HANDLE
32 }
33
34 /* disable DMA a channel */
35 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
36 /* reset DMA channel registers */
37 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
38 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
39 DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
40 DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
41 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
42 }
43
63 void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct)
64 {
65 uint32_t ctl;
66
67 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
68 DMA_WRONG_HANDLE
69 }
70
71 /* configure peripheral base address */
72 DMA_CHPADDR(dma_periph, channelx) = init_struct.periph_addr;
73
74 /* configure memory base address */
75 DMA_CHMADDR(dma_periph, channelx) = init_struct.memory_addr;
76
77 /* configure the number of remaining data to be transferred */
78 DMA_CHCNT(dma_periph, channelx) = (init_struct.number & DMA_CHANNEL_CNT_MASK);
79
80 /* configure peripheral transfer width,memory transfer width, */
81 ctl = DMA_CHCTL(dma_periph, channelx);
82 ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
83 ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
84 DMA_CHCTL(dma_periph, channelx) = ctl;
85
86 /* configure peripheral increasing mode */
87 if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
88 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
89 }else{
90 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
91 }
92
93 /* configure memory increasing mode */
94 if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
95 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
96 }else{
97 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
98 }
99
100 /* configure the direction of data transfer */
101 if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
102 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
103 }else{
104 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
105 }
106 }
107
117 void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
118 {
119 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
120 DMA_WRONG_HANDLE
121 }
122
123 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
124 }
125
135 void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
136 {
137 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
138 DMA_WRONG_HANDLE
139 }
140
141 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
142 }
143
153 void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
154 {
155 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
156 DMA_WRONG_HANDLE
157 }
158
159 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
160 }
161
171 void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
172 {
173 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
174 DMA_WRONG_HANDLE
175 }
176
177 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
178 }
179
189 void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
190 {
191 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
192 DMA_WRONG_HANDLE
193 }
194
195 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
196 }
197
207 void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
208 {
209 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
210 DMA_WRONG_HANDLE
211 }
212
213 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
214 }
215
226 void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
227 {
228 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
229 DMA_WRONG_HANDLE
230 }
231
232 DMA_CHPADDR(dma_periph, channelx) = address;
233 }
234
245 void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
246 {
247 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
248 DMA_WRONG_HANDLE
249 }
250
251 DMA_CHMADDR(dma_periph, channelx) = address;
252 }
253
264 void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
265 {
266 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
267 DMA_WRONG_HANDLE
268 }
269
270 DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
271 }
272
282 uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
283 {
284 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
285 DMA_WRONG_HANDLE
286 }
287
288 return (uint32_t)DMA_CHCNT(dma_periph, channelx);
289 }
290
305 void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
306 {
307 uint32_t ctl;
308
309 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
310 DMA_WRONG_HANDLE
311 }
312
313 /* acquire DMA_CHxCTL register */
314 ctl = DMA_CHCTL(dma_periph, channelx);
315 /* assign regiser */
316 ctl &= ~DMA_CHXCTL_PRIO;
317 ctl |= priority;
318 DMA_CHCTL(dma_periph, channelx) = ctl;
319 }
320
334 void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
335 {
336 uint32_t ctl;
337
338 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
339 DMA_WRONG_HANDLE
340 }
341
342 /* acquire DMA_CHxCTL register */
343 ctl = DMA_CHCTL(dma_periph, channelx);
344 /* assign regiser */
345 ctl &= ~DMA_CHXCTL_MWIDTH;
346 ctl |= mwidth;
347 DMA_CHCTL(dma_periph, channelx) = ctl;
348 }
349
363 void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
364 {
365 uint32_t ctl;
366
367 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
368 DMA_WRONG_HANDLE
369 }
370
371 /* acquire DMA_CHxCTL register */
372 ctl = DMA_CHCTL(dma_periph, channelx);
373 /* assign regiser */
374 ctl &= ~DMA_CHXCTL_PWIDTH;
375 ctl |= pwidth;
376 DMA_CHCTL(dma_periph, channelx) = ctl;
377 }
378
388 void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
389 {
390 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
391 DMA_WRONG_HANDLE
392 }
393
394 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
395 }
396
406 void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
407 {
408 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
409 DMA_WRONG_HANDLE
410 }
411
412 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
413 }
414
424 void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
425 {
426 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
427 DMA_WRONG_HANDLE
428 }
429
430 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
431 }
432
442 void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
443 {
444 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
445 DMA_WRONG_HANDLE
446 }
447
448 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
449 }
450
463 void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
464 {
465 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
466 DMA_WRONG_HANDLE
467 }
468
469 if(DMA_PERIPHERAL_TO_MEMORY == direction){
470 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
471 } else {
472 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
473 }
474 }
475
491 FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
492 {
493 FlagStatus reval;
494
495 if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
496 reval = SET;
497 }else{
498 reval = RESET;
499 }
500
501 return reval;
502 }
503
519 void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
520 {
521 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
522 }
523
538 FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
539 {
540 uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
541
542 switch(flag){
543 case DMA_INT_FLAG_FTF:
544 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
545 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
546 break;
547 case DMA_INT_FLAG_HTF:
548 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
549 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
550 break;
551 case DMA_INT_FLAG_ERR:
552 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
553 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
554 break;
555 default:
556 DMA_WRONG_HANDLE
557 }
558
559 if(interrupt_flag && interrupt_enable){
560 return SET;
561 }else{
562 return RESET;
563 }
564 }
565
581 void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
582 {
583 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
584 }
585
600 void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
601 {
602 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
603 DMA_WRONG_HANDLE
604 }
605
606 DMA_CHCTL(dma_periph, channelx) |= source;
607 }
608
623 void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
624 {
625 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
626 DMA_WRONG_HANDLE
627 }
628
629 DMA_CHCTL(dma_periph, channelx) &= ~source;
630 }
631
641 static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx)
642 {
643 ErrStatus val = SUCCESS;
644
645 if(DMA1 == dma_periph){
646 if(channelx > DMA_CH4){
647 val = ERROR;
648 }
649 }
650
651 return val;
652 }
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f10x_dma.h:84
dma_channel_enable
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable DMA channel
Definition: gd32f10x_dma.c:189
DMA_WRONG_HANDLE
#define DMA_WRONG_HANDLE
Definition: gd32f10x_dma.c:15
DMA_CHMADDR
#define DMA_CHMADDR(dma, channel)
Definition: gd32f10x_dma.h:131
dma_parameter_struct::priority
uint32_t priority
Definition: gd32f10x_dma.h:118
dma_periph_increase_disable
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable next address increasement algorithm of peripheral
Definition: gd32f10x_dma.c:442
dma_interrupt_flag_clear
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag
Definition: gd32f10x_dma.c:581
dma_parameter_struct::memory_width
uint32_t memory_width
Definition: gd32f10x_dma.h:116
dma_channel_enum
dma_channel_enum
Definition: gd32f10x_dma.h:99
dma_priority_config
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
configure priority level of DMA channel
Definition: gd32f10x_dma.c:305
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f10x_dma.h:79
dma_parameter_struct::periph_inc
uint8_t periph_inc
Definition: gd32f10x_dma.h:119
dma_memory_to_memory_enable
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable memory to memory mode
Definition: gd32f10x_dma.c:153
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f10x_dma.h:81
dma_transfer_direction_config
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
configure the direction of data transfer on the channel
Definition: gd32f10x_dma.c:463
DMA_CHCNT
#define DMA_CHCNT(dma, channel)
Definition: gd32f10x_dma.h:129
DMA_PERIPH_INCREASE_ENABLE
#define DMA_PERIPH_INCREASE_ENABLE
Definition: gd32f10x_dma.h:169
dma_memory_increase_disable
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable next address increasement algorithm of memory
Definition: gd32f10x_dma.c:406
dma_interrupt_flag_get
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
check DMA flag and interrupt enable bit is set or not
Definition: gd32f10x_dma.c:538
DMA_CHXCTL_HTFIE
#define DMA_CHXCTL_HTFIE
Definition: gd32f10x_dma.h:77
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f10x_dma.h:83
DMA_CHANNEL_CNT_MASK
#define DMA_CHANNEL_CNT_MASK
Definition: gd32f10x_dma.h:200
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f10x_dma.h:82
dma_flag_clear
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag
Definition: gd32f10x_dma.c:519
dma_deinit
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
deinitialize DMA a channel registers
Definition: gd32f10x_dma.c:28
DMA_CHCTL
#define DMA_CHCTL(dma, channel)
Definition: gd32f10x_dma.h:128
DMA_CH4
Definition: gd32f10x_dma.h:105
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f10x_dma.h:125
dma_parameter_struct
Definition: gd32f10x_dma.h:111
dma_parameter_struct::number
uint32_t number
Definition: gd32f10x_dma.h:117
DMA_MEMORY_INCREASE_ENABLE
#define DMA_MEMORY_INCREASE_ENABLE
Definition: gd32f10x_dma.h:173
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f10x_dma.h:85
DMA_CHXCTL_FTFIE
#define DMA_CHXCTL_FTFIE
Definition: gd32f10x_dma.h:76
DMA_INTF
#define DMA_INTF(dmax)
Definition: gd32f10x_dma.h:23
dma_memory_increase_enable
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable next address increasement algorithm of memory
Definition: gd32f10x_dma.c:388
DMA_CHCTL_RESET_VALUE
#define DMA_CHCTL_RESET_VALUE
Definition: gd32f10x_dma.h:134
gd32f10x_dma.h
definitions for the DMA
dma_interrupt_enable
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
enable DMA interrupt
Definition: gd32f10x_dma.c:600
dma_init
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct)
initialize DMA channel
Definition: gd32f10x_dma.c:63
DMA_INT_FLAG_ERR
#define DMA_INT_FLAG_ERR
Definition: gd32f10x_dma.h:146
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f10x_dma.h:80
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f10x_dma.h:161
DMA_CHPADDR
#define DMA_CHPADDR(dma, channel)
Definition: gd32f10x_dma.h:130
dma_periph_address_config
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
set DMA peripheral base address
Definition: gd32f10x_dma.c:226
dma_memory_address_config
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
set DMA memory base address
Definition: gd32f10x_dma.c:245
dma_parameter_struct::periph_width
uint32_t periph_width
Definition: gd32f10x_dma.h:114
DMA_INT_FLAG_FTF
#define DMA_INT_FLAG_FTF
Definition: gd32f10x_dma.h:144
dma_parameter_struct::memory_inc
uint8_t memory_inc
Definition: gd32f10x_dma.h:120
DMA_CHMADDR_RESET_VALUE
#define DMA_CHMADDR_RESET_VALUE
Definition: gd32f10x_dma.h:137
dma_memory_width_config
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
configure transfer data size of memory
Definition: gd32f10x_dma.c:334
DMA1
#define DMA1
Definition: gd32f10x_dma.h:20
DMA_CHXCTL_ERRIE
#define DMA_CHXCTL_ERRIE
Definition: gd32f10x_dma.h:78
dma_parameter_struct::direction
uint8_t direction
Definition: gd32f10x_dma.h:121
dma_transfer_number_get
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
get the number of remaining data to be transferred by the DMA
Definition: gd32f10x_dma.c:282
DMA_INT_FLAG_HTF
#define DMA_INT_FLAG_HTF
Definition: gd32f10x_dma.h:145
dma_flag_get
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
check DMA flag is set or not
Definition: gd32f10x_dma.c:491
dma_interrupt_disable
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
disable DMA interrupt
Definition: gd32f10x_dma.c:623
dma_circulation_enable
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable DMA circulation mode
Definition: gd32f10x_dma.c:117
dma_circulation_disable
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable DMA circulation mode
Definition: gd32f10x_dma.c:135
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f10x_dma.h:75
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f10x_dma.h:86
dma_periph_increase_enable
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
enable next address increasement algorithm of peripheral
Definition: gd32f10x_dma.c:424
dma_transfer_number_config
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
set the number of remaining data to be transferred by the DMA
Definition: gd32f10x_dma.c:264
dma_channel_disable
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable DMA channel
Definition: gd32f10x_dma.c:207
dma_periph_width_config
void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
configure transfer data size of peripheral
Definition: gd32f10x_dma.c:363
dma_parameter_struct::periph_addr
uint32_t periph_addr
Definition: gd32f10x_dma.h:113
DMA_INTC
#define DMA_INTC(dmax)
Definition: gd32f10x_dma.h:24
dma_memory_to_memory_disable
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
disable memory to memory mode
Definition: gd32f10x_dma.c:171
DMA_CHCNT_RESET_VALUE
#define DMA_CHCNT_RESET_VALUE
Definition: gd32f10x_dma.h:135
DMA_CHINTF_RESET_VALUE
#define DMA_CHINTF_RESET_VALUE
Definition: gd32f10x_dma.h:138
dma_parameter_struct::memory_addr
uint32_t memory_addr
Definition: gd32f10x_dma.h:115
DMA_CHPADDR_RESET_VALUE
#define DMA_CHPADDR_RESET_VALUE
Definition: gd32f10x_dma.h:136
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_rcu.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_RCU_H
14 #define GD32F10X_RCU_H
15
16 #include "gd32f10x.h"
17
18 /* RCU definitions */
19 #define RCU RCU_BASE
20
21 /* registers definitions */
22 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
23 #define RCU_CTL REG32(RCU + 0x00U)
24 #define RCU_CFG0 REG32(RCU + 0x04U)
25 #define RCU_INT REG32(RCU + 0x08U)
26 #define RCU_APB2RST REG32(RCU + 0x0CU)
27 #define RCU_APB1RST REG32(RCU + 0x10U)
28 #define RCU_AHBEN REG32(RCU + 0x14U)
29 #define RCU_APB2EN REG32(RCU + 0x18U)
30 #define RCU_APB1EN REG32(RCU + 0x1CU)
31 #define RCU_BDCTL REG32(RCU + 0x20U)
32 #define RCU_RSTSCK REG32(RCU + 0x24U)
33 #define RCU_DSV REG32(RCU + 0x34U)
34 #elif defined(GD32F10X_CL)
35 #define RCU_CTL REG32(RCU + 0x00U)
36 #define RCU_CFG0 REG32(RCU + 0x04U)
37 #define RCU_INT REG32(RCU + 0x08U)
38 #define RCU_APB2RST REG32(RCU + 0x0CU)
39 #define RCU_APB1RST REG32(RCU + 0x10U)
40 #define RCU_AHBEN REG32(RCU + 0x14U)
41 #define RCU_APB2EN REG32(RCU + 0x18U)
42 #define RCU_APB1EN REG32(RCU + 0x1CU)
43 #define RCU_BDCTL REG32(RCU + 0x20U)
44 #define RCU_RSTSCK REG32(RCU + 0x24U)
45 #define RCU_AHBRST REG32(RCU + 0x28U)
46 #define RCU_CFG1 REG32(RCU + 0x2CU)
47 #define RCU_DSV REG32(RCU + 0x34U)
48 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
49
50 /* bits definitions */
51 /* RCU_CTL */
52 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
53 #define RCU_CTL_IRC8MEN BIT(0)
54 #define RCU_CTL_IRC8MSTB BIT(1)
55 #define RCU_CTL_IRC8MADJ BITS(3,7)
56 #define RCU_CTL_IRC8MCALIB BITS(8,15)
57 #define RCU_CTL_HXTALEN BIT(16)
58 #define RCU_CTL_HXTALSTB BIT(17)
59 #define RCU_CTL_HXTALBPS BIT(18)
60 #define RCU_CTL_CKMEN BIT(19)
61 #define RCU_CTL_PLLEN BIT(24)
62 #define RCU_CTL_PLLSTB BIT(25)
63 #elif defined(GD32F10X_CL)
64 #define RCU_CTL_IRC8MEN BIT(0)
65 #define RCU_CTL_IRC8MSTB BIT(1)
66 #define RCU_CTL_IRC8MADJ BITS(3,7)
67 #define RCU_CTL_IRC8MCALIB BITS(8,15)
68 #define RCU_CTL_HXTALEN BIT(16)
69 #define RCU_CTL_HXTALSTB BIT(17)
70 #define RCU_CTL_HXTALBPS BIT(18)
71 #define RCU_CTL_CKMEN BIT(19)
72 #define RCU_CTL_PLLEN BIT(24)
73 #define RCU_CTL_PLLSTB BIT(25)
74 #define RCU_CTL_PLL1EN BIT(26)
75 #define RCU_CTL_PLL1STB BIT(27)
76 #define RCU_CTL_PLL2EN BIT(28)
77 #define RCU_CTL_PLL2STB BIT(29)
78 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
79
80 /* RCU_CFG0 */
81 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
82 #define RCU_CFG0_SCS BITS(0,1)
83 #define RCU_CFG0_SCSS BITS(2,3)
84 #define RCU_CFG0_AHBPSC BITS(4,7)
85 #define RCU_CFG0_APB1PSC BITS(8,10)
86 #define RCU_CFG0_APB2PSC BITS(11,13)
87 #define RCU_CFG0_ADCPSC BITS(14,15)
88 #define RCU_CFG0_PLLSEL BIT(16)
89 #define RCU_CFG0_PREDV0 BIT(17)
90 #define RCU_CFG0_PLLMF BITS(18,21)
91 #define RCU_CFG0_USBDPSC BITS(22,23)
92 #define RCU_CFG0_CKOUT0SEL BITS(24,26)
93 #define RCU_CFG0_PLLMF_4 BIT(27)
94 #define RCU_CFG0_ADCPSC_2 BIT(28)
95 #elif defined(GD32F10X_CL)
96 #define RCU_CFG0_SCS BITS(0,1)
97 #define RCU_CFG0_SCSS BITS(2,3)
98 #define RCU_CFG0_AHBPSC BITS(4,7)
99 #define RCU_CFG0_APB1PSC BITS(8,10)
100 #define RCU_CFG0_APB2PSC BITS(11,13)
101 #define RCU_CFG0_ADCPSC BITS(14,15)
102 #define RCU_CFG0_PLLSEL BIT(16)
103 #define RCU_CFG0_PREDV0_LSB BIT(17)
104 #define RCU_CFG0_PLLMF BITS(18,21)
105 #define RCU_CFG0_USBFSPSC BITS(22,23)
106 #define RCU_CFG0_CKOUT0SEL BITS(24,27)
107 #define RCU_CFG0_ADCPSC_2 BIT(28)
108 #define RCU_CFG0_PLLMF_4 BIT(29)
109 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
110
111 /* RCU_INT */
112 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
113 #define RCU_INT_IRC40KSTBIF BIT(0)
114 #define RCU_INT_LXTALSTBIF BIT(1)
115 #define RCU_INT_IRC8MSTBIF BIT(2)
116 #define RCU_INT_HXTALSTBIF BIT(3)
117 #define RCU_INT_PLLSTBIF BIT(4)
118 #define RCU_INT_CKMIF BIT(7)
119 #define RCU_INT_IRC40KSTBIE BIT(8)
120 #define RCU_INT_LXTALSTBIE BIT(9)
121 #define RCU_INT_IRC8MSTBIE BIT(10)
122 #define RCU_INT_HXTALSTBIE BIT(11)
123 #define RCU_INT_PLLSTBIE BIT(12)
124 #define RCU_INT_IRC40KSTBIC BIT(16)
125 #define RCU_INT_LXTALSTBIC BIT(17)
126 #define RCU_INT_IRC8MSTBIC BIT(18)
127 #define RCU_INT_HXTALSTBIC BIT(19)
128 #define RCU_INT_PLLSTBIC BIT(20)
129 #define RCU_INT_CKMIC BIT(23)
130 #elif defined(GD32F10X_CL)
131 #define RCU_INT_IRC40KSTBIF BIT(0)
132 #define RCU_INT_LXTALSTBIF BIT(1)
133 #define RCU_INT_IRC8MSTBIF BIT(2)
134 #define RCU_INT_HXTALSTBIF BIT(3)
135 #define RCU_INT_PLLSTBIF BIT(4)
136 #define RCU_INT_PLL1STBIF BIT(5)
137 #define RCU_INT_PLL2STBIF BIT(6)
138 #define RCU_INT_CKMIF BIT(7)
139 #define RCU_INT_IRC40KSTBIE BIT(8)
140 #define RCU_INT_LXTALSTBIE BIT(9)
141 #define RCU_INT_IRC8MSTBIE BIT(10)
142 #define RCU_INT_HXTALSTBIE BIT(11)
143 #define RCU_INT_PLLSTBIE BIT(12)
144 #define RCU_INT_PLL1STBIE BIT(13)
145 #define RCU_INT_PLL2STBIE BIT(14)
146 #define RCU_INT_IRC40KSTBIC BIT(16)
147 #define RCU_INT_LXTALSTBIC BIT(17)
148 #define RCU_INT_IRC8MSTBIC BIT(18)
149 #define RCU_INT_HXTALSTBIC BIT(19)
150 #define RCU_INT_PLLSTBIC BIT(20)
151 #define RCU_INT_PLL1STBIC BIT(21)
152 #define RCU_INT_PLL2STBIC BIT(22)
153 #define RCU_INT_CKMIC BIT(23)
154 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
155
156 /* RCU_APB2RST */
157 #define RCU_APB2RST_AFRST BIT(0)
158 #define RCU_APB2RST_PARST BIT(2)
159 #define RCU_APB2RST_PBRST BIT(3)
160 #define RCU_APB2RST_PCRST BIT(4)
161 #define RCU_APB2RST_PDRST BIT(5)
162 #define RCU_APB2RST_PERST BIT(6)
163 #define RCU_APB2RST_PFRST BIT(7)
164 #define RCU_APB2RST_PGRST BIT(8)
165 #define RCU_APB2RST_ADC0RST BIT(9)
166 #define RCU_APB2RST_ADC1RST BIT(10)
167 #define RCU_APB2RST_TIMER0RST BIT(11)
168 #define RCU_APB2RST_SPI0RST BIT(12)
169 #define RCU_APB2RST_TIMER7RST BIT(13)
170 #define RCU_APB2RST_USART0RST BIT(14)
171 #ifndef GD32F10X_CL
172 #define RCU_APB2RST_ADC2RST BIT(15)
173 #endif /* GD32F10X_CL */
174 #ifdef GD32F10X_XD
175 #define RCU_APB2RST_TIMER8RST BIT(19)
176 #define RCU_APB2RST_TIMER9RST BIT(20)
177 #define RCU_APB2RST_TIMER10RST BIT(21)
178 #endif /* GD32F10X_XD */
179
180 /* RCU_APB1RST */
181 #define RCU_APB1RST_TIMER1RST BIT(0)
182 #define RCU_APB1RST_TIMER2RST BIT(1)
183 #define RCU_APB1RST_TIMER3RST BIT(2)
184 #define RCU_APB1RST_TIMER4RST BIT(3)
185 #define RCU_APB1RST_TIMER5RST BIT(4)
186 #define RCU_APB1RST_TIMER6RST BIT(5)
187 #ifdef GD32F10X_XD
188 #define RCU_APB1RST_TIMER11RST BIT(6)
189 #define RCU_APB1RST_TIMER12RST BIT(7)
190 #define RCU_APB1RST_TIMER13RST BIT(8)
191 #endif /* GD32F10X_XD */
192 #define RCU_APB1RST_WWDGTRST BIT(11)
193 #define RCU_APB1RST_SPI1RST BIT(14)
194 #define RCU_APB1RST_SPI2RST BIT(15)
195 #define RCU_APB1RST_USART1RST BIT(17)
196 #define RCU_APB1RST_USART2RST BIT(18)
197 #define RCU_APB1RST_UART3RST BIT(19)
198 #define RCU_APB1RST_UART4RST BIT(20)
199 #define RCU_APB1RST_I2C0RST BIT(21)
200 #define RCU_APB1RST_I2C1RST BIT(22)
201 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
202 #define RCU_APB1RST_USBDRST BIT(23)
203 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
204 #define RCU_APB1RST_CAN0RST BIT(25)
205 #ifdef GD32F10X_CL
206 #define RCU_APB1RST_CAN1RST BIT(26)
207 #endif /* GD32F10X_CL */
208 #define RCU_APB1RST_BKPIRST BIT(27)
209 #define RCU_APB1RST_PMURST BIT(28)
210 #define RCU_APB1RST_DACRST BIT(29)
212 /* RCU_AHBEN */
213 #define RCU_AHBEN_DMA0EN BIT(0)
214 #define RCU_AHBEN_DMA1EN BIT(1)
215 #define RCU_AHBEN_SRAMSPEN BIT(2)
216 #define RCU_AHBEN_FMCSPEN BIT(4)
217 #define RCU_AHBEN_CRCEN BIT(6)
218 #define RCU_AHBEN_EXMCEN BIT(8)
219 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
220 #define RCU_AHBEN_SDIOEN BIT(10)
221 #elif defined(GD32F10X_CL)
222 #define RCU_AHBEN_USBFSEN BIT(12)
223 #define RCU_AHBEN_ENETEN BIT(14)
224 #define RCU_AHBEN_ENETTXEN BIT(15)
225 #define RCU_AHBEN_ENETRXEN BIT(16)
226 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
227
228 /* RCU_APB2EN */
229 #define RCU_APB2EN_AFEN BIT(0)
230 #define RCU_APB2EN_PAEN BIT(2)
231 #define RCU_APB2EN_PBEN BIT(3)
232 #define RCU_APB2EN_PCEN BIT(4)
233 #define RCU_APB2EN_PDEN BIT(5)
234 #define RCU_APB2EN_PEEN BIT(6)
235 #define RCU_APB2EN_PFEN BIT(7)
236 #define RCU_APB2EN_PGEN BIT(8)
237 #define RCU_APB2EN_ADC0EN BIT(9)
238 #define RCU_APB2EN_ADC1EN BIT(10)
239 #define RCU_APB2EN_TIMER0EN BIT(11)
240 #define RCU_APB2EN_SPI0EN BIT(12)
241 #define RCU_APB2EN_TIMER7EN BIT(13)
242 #define RCU_APB2EN_USART0EN BIT(14)
243 #ifndef GD32F10X_CL
244 #define RCU_APB2EN_ADC2EN BIT(15)
245 #endif /* GD32F10X_CL */
246 #ifdef GD32F10X_XD
247 #define RCU_APB2EN_TIMER8EN BIT(19)
248 #define RCU_APB2EN_TIMER9EN BIT(20)
249 #define RCU_APB2EN_TIMER10EN BIT(21)
250 #endif /* GD32F10X_XD */
251
252 /* RCU_APB1EN */
253 #define RCU_APB1EN_TIMER1EN BIT(0)
254 #define RCU_APB1EN_TIMER2EN BIT(1)
255 #define RCU_APB1EN_TIMER3EN BIT(2)
256 #define RCU_APB1EN_TIMER4EN BIT(3)
257 #define RCU_APB1EN_TIMER5EN BIT(4)
258 #define RCU_APB1EN_TIMER6EN BIT(5)
259 #ifdef GD32F10X_XD
260 #define RCU_APB1EN_TIMER11EN BIT(6)
261 #define RCU_APB1EN_TIMER12EN BIT(7)
262 #define RCU_APB1EN_TIMER13EN BIT(8)
263 #endif /* GD32F10X_XD */
264 #define RCU_APB1EN_WWDGTEN BIT(11)
265 #define RCU_APB1EN_SPI1EN BIT(14)
266 #define RCU_APB1EN_SPI2EN BIT(15)
267 #define RCU_APB1EN_USART1EN BIT(17)
268 #define RCU_APB1EN_USART2EN BIT(18)
269 #define RCU_APB1EN_UART3EN BIT(19)
270 #define RCU_APB1EN_UART4EN BIT(20)
271 #define RCU_APB1EN_I2C0EN BIT(21)
272 #define RCU_APB1EN_I2C1EN BIT(22)
273 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
274 #define RCU_APB1EN_USBDEN BIT(23)
275 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
276 #define RCU_APB1EN_CAN0EN BIT(25)
277 #ifdef GD32F10X_CL
278 #define RCU_APB1EN_CAN1EN BIT(26)
279 #endif /* GD32F10X_CL */
280 #define RCU_APB1EN_BKPIEN BIT(27)
281 #define RCU_APB1EN_PMUEN BIT(28)
282 #define RCU_APB1EN_DACEN BIT(29)
284 /* RCU_BDCTL */
285 #define RCU_BDCTL_LXTALEN BIT(0)
286 #define RCU_BDCTL_LXTALSTB BIT(1)
287 #define RCU_BDCTL_LXTALBPS BIT(2)
288 #define RCU_BDCTL_RTCSRC BITS(8,9)
289 #define RCU_BDCTL_RTCEN BIT(15)
290 #define RCU_BDCTL_BKPRST BIT(16)
292 /* RCU_RSTSCK */
293 #define RCU_RSTSCK_IRC40KEN BIT(0)
294 #define RCU_RSTSCK_IRC40KSTB BIT(1)
295 #define RCU_RSTSCK_RSTFC BIT(24)
296 #define RCU_RSTSCK_EPRSTF BIT(26)
297 #define RCU_RSTSCK_PORRSTF BIT(27)
298 #define RCU_RSTSCK_SWRSTF BIT(28)
299 #define RCU_RSTSCK_FWDGTRSTF BIT(29)
300 #define RCU_RSTSCK_WWDGTRSTF BIT(30)
301 #define RCU_RSTSCK_LPRSTF BIT(31)
303 #ifdef GD32F10X_CL
304 /* RCU_AHBRST */
305 #define RCU_AHBRST_USBFSRST BIT(12)
306 #define RCU_AHBRST_ENETRST BIT(14)
307 #endif /* GD32F10X_CL */
308
309 #if defined(GD32F10X_CL)
310 /* RCU_CFG1 */
311 #define RCU_CFG1_PREDV0 BITS(0,3)
312 #define RCU_CFG1_PREDV1 BITS(4,7)
313 #define RCU_CFG1_PLL1MF BITS(8,11)
314 #define RCU_CFG1_PLL2MF BITS(12,15)
315 #define RCU_CFG1_PREDV0SEL BIT(16)
316 #define RCU_CFG1_I2S1SEL BIT(17)
317 #define RCU_CFG1_I2S2SEL BIT(18)
318 #endif /* GD32F10X_CL */
319
320 /* RCU_DSV */
321 #define RCU_DSV_DSLPVS BITS(0,2)
323 /* constants definitions */
324 /* define the peripheral clock enable bit position and its register index offset */
325 #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
326 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))
327 #define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
328
329 /* register offset */
330 /* peripherals enable */
331 #define AHBEN_REG_OFFSET 0x14U
332 #define APB1EN_REG_OFFSET 0x1CU
333 #define APB2EN_REG_OFFSET 0x18U
335 /* peripherals reset */
336 #define AHBRST_REG_OFFSET 0x28U
337 #define APB1RST_REG_OFFSET 0x10U
338 #define APB2RST_REG_OFFSET 0x0CU
339 #define RSTSCK_REG_OFFSET 0x24U
341 /* clock control */
342 #define CTL_REG_OFFSET 0x00U
343 #define BDCTL_REG_OFFSET 0x20U
345 /* clock stabilization and stuck interrupt */
346 #define INT_REG_OFFSET 0x08U
348 /* configuration register */
349 #define CFG0_REG_OFFSET 0x04U
350 #define CFG1_REG_OFFSET 0x2CU
352 /* peripheral clock enable */
353 typedef enum
354 {
355 /* AHB peripherals */
356 RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U),
357 RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U),
358 RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U),
359 RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U),
360 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
361 RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U),
362 #elif defined(GD32F10X_CL)
363 RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U),
364 RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U),
365 RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U),
366 RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U),
367 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
368
369 /* APB1 peripherals */
370 RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U),
371 RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U),
372 RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U),
373 RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U),
374 RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U),
375 RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U),
376 #if defined(GD32F10X_XD)
377 RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U),
378 RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U),
379 RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U),
380 #endif /* GD32F10X_XD */
381 RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U),
382 RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U),
383 RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U),
384 RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U),
385 RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U),
386 RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U),
387 RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U),
388 RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U),
389 RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U),
390 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
391 RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U),
392 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
393 RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U),
394 #ifdef GD32F10X_CL
395 RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U),
396 #endif /* GD32F10X_CL */
397 RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U),
398 RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U),
399 RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U),
400 RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U),
402 /* APB2 peripherals */
403 RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U),
404 RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U),
405 RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U),
406 RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U),
407 RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U),
408 RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U),
409 RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U),
410 RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U),
411 RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U),
412 RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U),
413 RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U),
414 RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U),
415 RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U),
416 RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U),
417 #ifndef GD32F10X_CL
418 RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U),
419 #endif /* GD32F10X_CL */
420 #ifdef GD32F10X_XD
421 RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U),
422 RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U),
423 RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U),
424 #endif /* GD32F10X_XD */
425 }rcu_periph_enum;
426
427 /* peripheral clock enable when sleep mode*/
428 typedef enum
429 {
430 /* AHB peripherals */
431 RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U),
432 RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U),
433 }rcu_periph_sleep_enum;
434
435 /* peripherals reset */
436 typedef enum
437 {
438 /* AHB peripherals */
439 #ifdef GD32F10X_CL
440 RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U),
441 RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U),
442 #endif /* GD32F10X_CL */
443
444 /* APB1 peripherals */
445 RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U),
446 RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U),
447 RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U),
448 RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U),
449 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U),
450 RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U),
451 #ifdef GD32F10X_XD
452 RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U),
453 RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U),
454 RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U),
455 #endif /* GD32F10X_XD */
456 RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U),
457 RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U),
458 RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U),
459 RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U),
460 RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U),
461 RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U),
462 RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U),
463 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U),
464 RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U),
465 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
466 RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U),
467 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
468 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U),
469 #ifdef GD32F10X_CL
470 RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U),
471 #endif /* GD32F10X_CL */
472 RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U),
473 RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U),
474 RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U),
476 /* APB2 peripherals */
477 RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U),
478 RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U),
479 RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U),
480 RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U),
481 RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U),
482 RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U),
483 RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U),
484 RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U),
485 RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U),
486 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U),
487 RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U),
488 RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U),
489 RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U),
490 RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U),
491 #ifndef GD32F10X_CL
492 RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U),
493 #endif /* GD32F10X_CL */
494 #ifdef GD32F10X_XD
495 RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U),
496 RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U),
497 RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U),
498 #endif /* GD32F10X_XD */
499 }rcu_periph_reset_enum;
500
501 /* clock stabilization and peripheral reset flags */
502 typedef enum
503 {
504 /* clock stabilization flags */
505 RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U),
506 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U),
507 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U),
508 #ifdef GD32F10X_CL
509 RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U),
510 RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U),
511 #endif /* GD32F10X_CL */
512 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U),
513 RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U),
514 /* reset source flags */
515 RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U),
516 RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U),
517 RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U),
518 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U),
519 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U),
520 RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U),
521 }rcu_flag_enum;
522
523 /* clock stabilization and ckm interrupt flags */
524 typedef enum
525 {
526 RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U),
527 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U),
528 RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U),
529 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U),
530 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U),
531 #ifdef GD32F10X_CL
532 RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U),
533 RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U),
534 #endif /* GD32F10X_CL */
535 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U),
536 }rcu_int_flag_enum;
537
538 /* clock stabilization and stuck interrupt flags clear */
539 typedef enum
540 {
541 RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U),
542 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U),
543 RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U),
544 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U),
545 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U),
546 #ifdef GD32F10X_CL
547 RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U),
548 RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U),
549 #endif /* GD32F10X_CL */
550 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U),
551 }rcu_int_flag_clear_enum;
552
553 /* clock stabilization interrupt enable or disable */
554 typedef enum
555 {
556 RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U),
557 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U),
558 RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U),
559 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U),
560 RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U),
561 #ifdef GD32F10X_CL
562 RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U),
563 RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U),
564 #endif /* GD32F10X_CL */
565 }rcu_int_enum;
566
567 /* oscillator types */
568 typedef enum
569 {
570 RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U),
571 RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U),
572 RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U),
573 RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U),
574 RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U),
575 #ifdef GD32F10X_CL
576 RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U),
577 RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U),
578 #endif /* GD32F10X_CL */
579 }rcu_osci_type_enum;
580
581 /* rcu clock frequency */
582 typedef enum
583 {
584 CK_SYS = 0,
585 CK_AHB,
586 CK_APB1,
587 CK_APB2,
588 }rcu_clock_freq_enum;
589
590 /* RCU_CFG0 register bit define */
591 /* system clock source select */
592 #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
593 #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0)
594 #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1)
595 #define RCU_CKSYSSRC_PLL CFG0_SCS(2)
597 /* system clock source select status */
598 #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
599 #define RCU_SCSS_IRC8M CFG0_SCSS(0)
600 #define RCU_SCSS_HXTAL CFG0_SCSS(1)
601 #define RCU_SCSS_PLL CFG0_SCSS(2)
603 /* AHB prescaler selection */
604 #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
605 #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0)
606 #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8)
607 #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9)
608 #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10)
609 #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11)
610 #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12)
611 #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13)
612 #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14)
613 #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15)
615 /* APB1 prescaler selection */
616 #define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
617 #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0)
618 #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4)
619 #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5)
620 #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6)
621 #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7)
623 /* APB2 prescaler selection */
624 #define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
625 #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0)
626 #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4)
627 #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5)
628 #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6)
629 #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7)
631 /* ADC prescaler select */
632 #define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U)
633 #define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U)
634 #define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U)
635 #define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U)
636 #define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U)
637 #define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U)
639 /* PLL clock source selection */
640 #define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U)
641 #define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL
643 /* PLL clock multiplication factor */
644 #define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */
645
646 #define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
647 #define RCU_PLL_MUL2 CFG0_PLLMF(0)
648 #define RCU_PLL_MUL3 CFG0_PLLMF(1)
649 #define RCU_PLL_MUL4 CFG0_PLLMF(2)
650 #define RCU_PLL_MUL5 CFG0_PLLMF(3)
651 #define RCU_PLL_MUL6 CFG0_PLLMF(4)
652 #define RCU_PLL_MUL7 CFG0_PLLMF(5)
653 #define RCU_PLL_MUL8 CFG0_PLLMF(6)
654 #define RCU_PLL_MUL9 CFG0_PLLMF(7)
655 #define RCU_PLL_MUL10 CFG0_PLLMF(8)
656 #define RCU_PLL_MUL11 CFG0_PLLMF(9)
657 #define RCU_PLL_MUL12 CFG0_PLLMF(10)
658 #define RCU_PLL_MUL13 CFG0_PLLMF(11)
659 #define RCU_PLL_MUL14 CFG0_PLLMF(12)
660 #if(defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
661 #define RCU_PLL_MUL15 CFG0_PLLMF(13)
662 #elif defined(GD32F10X_CL)
663 #define RCU_PLL_MUL6_5 CFG0_PLLMF(13)
664 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
665 #define RCU_PLL_MUL16 CFG0_PLLMF(14)
666 #define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0))
667 #define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1))
668 #define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2))
669 #define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3))
670 #define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4))
671 #define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5))
672 #define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6))
673 #define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7))
674 #define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8))
675 #define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9))
676 #define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10))
677 #define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11))
678 #define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12))
679 #define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13))
680 #define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14))
681 #define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15))
683 /* USBD/USBFS prescaler select */
684 #define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
685 #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0)
686 #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1)
687 #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2)
688 #define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3)
690 /* CKOUT0 Clock source selection */
691 #define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
692 #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0)
693 #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4)
694 #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5)
695 #define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6)
696 #define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7)
697 #ifdef GD32F10X_CL
698 #define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8)
699 #define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9)
700 #define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10)
701 #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11)
702 #endif /* GD32F10X_CL */
703
704 /* RTC clock entry selection */
705 #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
706 #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0)
707 #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1)
708 #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2)
709 #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3)
711 /* PREDV0 division factor */
712 #define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
713 #define RCU_PREDV0_DIV1 CFG1_PREDV0(0)
714 #define RCU_PREDV0_DIV2 CFG1_PREDV0(1)
715 #define RCU_PREDV0_DIV3 CFG1_PREDV0(2)
716 #define RCU_PREDV0_DIV4 CFG1_PREDV0(3)
717 #define RCU_PREDV0_DIV5 CFG1_PREDV0(4)
718 #define RCU_PREDV0_DIV6 CFG1_PREDV0(5)
719 #define RCU_PREDV0_DIV7 CFG1_PREDV0(6)
720 #define RCU_PREDV0_DIV8 CFG1_PREDV0(7)
721 #define RCU_PREDV0_DIV9 CFG1_PREDV0(8)
722 #define RCU_PREDV0_DIV10 CFG1_PREDV0(9)
723 #define RCU_PREDV0_DIV11 CFG1_PREDV0(10)
724 #define RCU_PREDV0_DIV12 CFG1_PREDV0(11)
725 #define RCU_PREDV0_DIV13 CFG1_PREDV0(12)
726 #define RCU_PREDV0_DIV14 CFG1_PREDV0(13)
727 #define RCU_PREDV0_DIV15 CFG1_PREDV0(14)
728 #define RCU_PREDV0_DIV16 CFG1_PREDV0(15)
730 /* PREDV1 division factor */
731 #define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
732 #define RCU_PREDV1_DIV1 CFG1_PREDV1(0)
733 #define RCU_PREDV1_DIV2 CFG1_PREDV1(1)
734 #define RCU_PREDV1_DIV3 CFG1_PREDV1(2)
735 #define RCU_PREDV1_DIV4 CFG1_PREDV1(3)
736 #define RCU_PREDV1_DIV5 CFG1_PREDV1(4)
737 #define RCU_PREDV1_DIV6 CFG1_PREDV1(5)
738 #define RCU_PREDV1_DIV7 CFG1_PREDV1(6)
739 #define RCU_PREDV1_DIV8 CFG1_PREDV1(7)
740 #define RCU_PREDV1_DIV9 CFG1_PREDV1(8)
741 #define RCU_PREDV1_DIV10 CFG1_PREDV1(9)
742 #define RCU_PREDV1_DIV11 CFG1_PREDV1(10)
743 #define RCU_PREDV1_DIV12 CFG1_PREDV1(11)
744 #define RCU_PREDV1_DIV13 CFG1_PREDV1(12)
745 #define RCU_PREDV1_DIV14 CFG1_PREDV1(13)
746 #define RCU_PREDV1_DIV15 CFG1_PREDV1(14)
747 #define RCU_PREDV1_DIV16 CFG1_PREDV1(15)
749 /* PLL1 clock multiplication factor */
750 #define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
751 #define RCU_PLL1_MUL8 CFG1_PLL1MF(6)
752 #define RCU_PLL1_MUL9 CFG1_PLL1MF(7)
753 #define RCU_PLL1_MUL10 CFG1_PLL1MF(8)
754 #define RCU_PLL1_MUL11 CFG1_PLL1MF(9)
755 #define RCU_PLL1_MUL12 CFG1_PLL1MF(10)
756 #define RCU_PLL1_MUL13 CFG1_PLL1MF(11)
757 #define RCU_PLL1_MUL14 CFG1_PLL1MF(12)
758 #define RCU_PLL1_MUL15 CFG1_PLL1MF(13)
759 #define RCU_PLL1_MUL16 CFG1_PLL1MF(14)
760 #define RCU_PLL1_MUL20 CFG1_PLL1MF(15)
762 /* PLL2 clock multiplication factor */
763 #define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12))
764 #define RCU_PLL2_MUL8 CFG1_PLL2MF(6)
765 #define RCU_PLL2_MUL9 CFG1_PLL2MF(7)
766 #define RCU_PLL2_MUL10 CFG1_PLL2MF(8)
767 #define RCU_PLL2_MUL11 CFG1_PLL2MF(9)
768 #define RCU_PLL2_MUL12 CFG1_PLL2MF(10)
769 #define RCU_PLL2_MUL13 CFG1_PLL2MF(11)
770 #define RCU_PLL2_MUL14 CFG1_PLL2MF(12)
771 #define RCU_PLL2_MUL15 CFG1_PLL2MF(13)
772 #define RCU_PLL2_MUL16 CFG1_PLL2MF(14)
773 #define RCU_PLL2_MUL20 CFG1_PLL2MF(15)
775 #ifdef GD32F10X_CL
776 /* PREDV0 input clock source selection */
777 #define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U)
778 #define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL
780 /* I2S1 clock source selection */
781 #define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U)
782 #define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL
784 /* I2S2 clock source selection */
785 #define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U)
786 #define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL
787 #endif /* GD32F10X_CL */
788
789 /* deep-sleep mode voltage */
790 #define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
791 #define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0)
792 #define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1)
793 #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2)
794 #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3)
796 /* function declarations */
797 /* deinitialize the RCU */
798 void rcu_deinit(void);
799 /* enable the peripherals clock */
800 void rcu_periph_clock_enable(rcu_periph_enum periph);
801 /* disable the peripherals clock */
802 void rcu_periph_clock_disable(rcu_periph_enum periph);
803 /* enable the peripherals clock when sleep mode */
804 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
805 /* disable the peripherals clock when sleep mode */
806 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
807 /* reset the peripherals */
808 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
809 /* disable reset the peripheral */
810 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
811 /* reset the BKP domain */
812 void rcu_bkp_reset_enable(void);
813 /* disable the BKP domain reset */
814 void rcu_bkp_reset_disable(void);
815
816 /* configure the system clock source */
817 void rcu_system_clock_source_config(uint32_t ck_sys);
818 /* get the system clock source */
819 uint32_t rcu_system_clock_source_get(void);
820 /* configure the AHB prescaler selection */
821 void rcu_ahb_clock_config(uint32_t ck_ahb);
822 /* configure the APB1 prescaler selection */
823 void rcu_apb1_clock_config(uint32_t ck_apb1);
824 /* configure the APB2 prescaler selection */
825 void rcu_apb2_clock_config(uint32_t ck_apb2);
826 /* configure the CK_OUT0 clock source and divider */
827 void rcu_ckout0_config(uint32_t ckout0_src);
828 /* configure the PLL clock source selection and PLL multiply factor */
829 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
830 #if(defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
831 /* configure the PREDV0 division factor and clock source */
832 void rcu_predv0_config(uint32_t predv0_div);
833 #elif defined(GD32F10X_CL)
834 /* configure the PREDV0 division factor and clock source */
835 void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div);
836 /* configure the PREDV1 division factor */
837 void rcu_predv1_config(uint32_t predv1_div);
838 /* configure the PLL1 clock */
839 void rcu_pll1_config(uint32_t pll_mul);
840 /* configure the PLL2 clock */
841 void rcu_pll2_config(uint32_t pll_mul);
842 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
843
844 /* configure the ADC division factor */
845 void rcu_adc_clock_config(uint32_t adc_psc);
846 /* configure the USBD/USBFS prescaler factor */
847 void rcu_usb_clock_config(uint32_t usb_psc);
848 /* configure the RTC clock source selection */
849 void rcu_rtc_clock_config(uint32_t rtc_clock_source);
850 #ifdef GD32F10X_CL
851 /* configure the I2S1 clock source selection */
852 void rcu_i2s1_clock_config(uint32_t i2s_clock_source);
853 /* configure the I2S2 clock source selection */
854 void rcu_i2s2_clock_config(uint32_t i2s_clock_source);
855 #endif /* GD32F10X_CL */
856
857
858 /* get the clock stabilization and periphral reset flags */
859 FlagStatus rcu_flag_get(rcu_flag_enum flag);
860 /* clear the reset flag */
861 void rcu_all_reset_flag_clear(void);
862 /* get the clock stabilization interrupt and ckm flags */
863 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
864 /* clear the interrupt flags */
865 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
866 /* enable the stabilization interrupt */
867 void rcu_interrupt_enable(rcu_int_enum stab_int);
868 /* disable the stabilization interrupt */
869 void rcu_interrupt_disable(rcu_int_enum stab_int);
870
871 /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */
872 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
873 /* turn on the oscillator */
874 void rcu_osci_on(rcu_osci_type_enum osci);
875 /* turn off the oscillator */
876 void rcu_osci_off(rcu_osci_type_enum osci);
877 /* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
878 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
879 /* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
880 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
881 /* enable the HXTAL clock monitor */
882 void rcu_hxtal_clock_monitor_enable(void);
883 /* disable the HXTAL clock monitor */
884 void rcu_hxtal_clock_monitor_disable(void);
885
886 /* set the IRC8M adjust value */
887 void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval);
888
889 /* set the deep sleep mode voltage */
890 void rcu_deepsleep_voltage_set(uint32_t dsvol);
891
892 /* get the system clock, bus and peripheral clock frequency */
893 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
894
895 #endif /* GD32F10X_RCU_H */
RCU_FLAG_PLL1STB
Definition: gd32f10x_rcu.h:509
RCU_INT_FLAG_HXTALSTB
Definition: gd32f10x_rcu.h:529
RCU_FLAG_PORRST
Definition: gd32f10x_rcu.h:516
RCU_ENETRST
Definition: gd32f10x_rcu.h:441
rcu_interrupt_enable
void rcu_interrupt_enable(rcu_int_enum stab_int)
enable the stabilization interrupt
Definition: gd32f10x_rcu.c:711
rcu_ckout0_config
void rcu_ckout0_config(uint32_t ckout0_src)
configure the CK_OUT0 clock source
Definition: gd32f10x_rcu.c:354
rcu_bkp_reset_enable
void rcu_bkp_reset_enable(void)
reset the BKP domain
Definition: gd32f10x_rcu.c:223
rcu_hxtal_clock_monitor_disable
void rcu_hxtal_clock_monitor_disable(void)
disable the HXTAL clock monitor
Definition: gd32f10x_rcu.c:990
RCU_TIMER11RST
Definition: gd32f10x_rcu.h:452
RCU_INT_FLAG_LXTALSTB
Definition: gd32f10x_rcu.h:527
RCU_USART1
Definition: gd32f10x_rcu.h:384
RCU_USART1RST
Definition: gd32f10x_rcu.h:459
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
RCU_I2C0RST
Definition: gd32f10x_rcu.h:463
RCU_INT_FLAG_PLLSTB
Definition: gd32f10x_rcu.h:530
rcu_osci_off
void rcu_osci_off(rcu_osci_type_enum osci)
turn off the oscillator
Definition: gd32f10x_rcu.c:889
rcu_interrupt_disable
void rcu_interrupt_disable(rcu_int_enum stab_int)
disable the stabilization interrupt
Definition: gd32f10x_rcu.c:730
RCU_FLAG_LPRST
Definition: gd32f10x_rcu.h:520
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
RCU_TIMER11
Definition: gd32f10x_rcu.h:377
RCU_GPIOGRST
Definition: gd32f10x_rcu.h:484
RCU_INT_FLAG_HXTALSTB_CLR
Definition: gd32f10x_rcu.h:544
RCU_INT_PLL2STB
Definition: gd32f10x_rcu.h:563
RSTSCK_REG_OFFSET
#define RSTSCK_REG_OFFSET
Definition: gd32f10x_rcu.h:339
RCU_SPI0
Definition: gd32f10x_rcu.h:414
RCU_TIMER10
Definition: gd32f10x_rcu.h:423
INT_REG_OFFSET
#define INT_REG_OFFSET
Definition: gd32f10x_rcu.h:346
rcu_int_enum
rcu_int_enum
Definition: gd32f10x_rcu.h:554
RCU_BKPIRST
Definition: gd32f10x_rcu.h:472
rcu_periph_clock_sleep_enable
void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
enable the peripherals clock when sleep mode
Definition: gd32f10x_rcu.c:142
RCU_FLAG_HXTALSTB
Definition: gd32f10x_rcu.h:506
RCU_TIMER2RST
Definition: gd32f10x_rcu.h:446
RCU_AF
Definition: gd32f10x_rcu.h:403
BDCTL_REG_OFFSET
#define BDCTL_REG_OFFSET
Definition: gd32f10x_rcu.h:343
RCU_I2C1RST
Definition: gd32f10x_rcu.h:464
RCU_INT_PLL1STB
Definition: gd32f10x_rcu.h:562
rcu_deepsleep_voltage_set
void rcu_deepsleep_voltage_set(uint32_t dsvol)
deep-sleep mode voltage select
Definition: gd32f10x_rcu.c:1022
RCU_CAN0RST
Definition: gd32f10x_rcu.h:468
RCU_TIMER5
Definition: gd32f10x_rcu.h:374
rcu_interrupt_flag_get
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
get the clock stabilization interrupt and ckm flags
Definition: gd32f10x_rcu.c:667
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_rcu.h:325
RCU_GPIOBRST
Definition: gd32f10x_rcu.h:479
RCU_WWDGT
Definition: gd32f10x_rcu.h:381
RCU_RTC
Definition: gd32f10x_rcu.h:400
CTL_REG_OFFSET
#define CTL_REG_OFFSET
Definition: gd32f10x_rcu.h:342
rcu_flag_enum
rcu_flag_enum
Definition: gd32f10x_rcu.h:502
RCU_SPI1RST
Definition: gd32f10x_rcu.h:457
RCU_INT_FLAG_CKM
Definition: gd32f10x_rcu.h:535
RCU_TIMER8RST
Definition: gd32f10x_rcu.h:495
rcu_interrupt_flag_clear
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
clear the interrupt flags
Definition: gd32f10x_rcu.c:692
RCU_INT_FLAG_CKM_CLR
Definition: gd32f10x_rcu.h:550
rcu_periph_clock_disable
void rcu_periph_clock_disable(rcu_periph_enum periph)
disable the peripherals clock
Definition: gd32f10x_rcu.c:128
RCU_INT_FLAG_PLLSTB_CLR
Definition: gd32f10x_rcu.h:545
RCU_TIMER7RST
Definition: gd32f10x_rcu.h:489
RCU_GPIOG
Definition: gd32f10x_rcu.h:410
RCU_TIMER8
Definition: gd32f10x_rcu.h:421
rcu_apb1_clock_config
void rcu_apb1_clock_config(uint32_t ck_apb1)
configure the APB1 clock prescaler selection
Definition: gd32f10x_rcu.c:304
RCU_INT_FLAG_LXTALSTB_CLR
Definition: gd32f10x_rcu.h:542
RCU_GPIOE
Definition: gd32f10x_rcu.h:408
RCU_TIMER5RST
Definition: gd32f10x_rcu.h:449
RCU_ADC0
Definition: gd32f10x_rcu.h:411
RCU_BKPI
Definition: gd32f10x_rcu.h:397
rcu_flag_get
FlagStatus rcu_flag_get(rcu_flag_enum flag)
get the clock stabilization and periphral reset flags
Definition: gd32f10x_rcu.c:631
RCU_ADC0RST
Definition: gd32f10x_rcu.h:485
rcu_deinit
void rcu_deinit(void)
deinitialize the RCU
Definition: gd32f10x_rcu.c:30
rcu_system_clock_source_get
uint32_t rcu_system_clock_source_get(void)
get the system clock source
Definition: gd32f10x_rcu.c:268
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
AHBRST_REG_OFFSET
#define AHBRST_REG_OFFSET
Definition: gd32f10x_rcu.h:336
RCU_TIMER4RST
Definition: gd32f10x_rcu.h:448
rcu_irc8m_adjust_value_set
void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
set the IRC8M adjust value
Definition: gd32f10x_rcu.c:1001
RCU_INT_LXTALSTB
Definition: gd32f10x_rcu.h:557
RCU_TIMER6RST
Definition: gd32f10x_rcu.h:450
RCU_SPI2
Definition: gd32f10x_rcu.h:383
RCU_FLAG_PLL2STB
Definition: gd32f10x_rcu.h:510
RCU_GPIOFRST
Definition: gd32f10x_rcu.h:483
rcu_periph_sleep_enum
rcu_periph_sleep_enum
Definition: gd32f10x_rcu.h:428
RCU_DAC
Definition: gd32f10x_rcu.h:399
RCU_DMA1
Definition: gd32f10x_rcu.h:357
RCU_TIMER6
Definition: gd32f10x_rcu.h:375
rcu_int_flag_enum
rcu_int_flag_enum
Definition: gd32f10x_rcu.h:524
rcu_usb_clock_config
void rcu_usb_clock_config(uint32_t usb_psc)
configure the USBD/USBFS prescaler factor
Definition: gd32f10x_rcu.c:534
RCU_INT_FLAG_PLL2STB_CLR
Definition: gd32f10x_rcu.h:548
rcu_osci_bypass_mode_disable
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
Definition: gd32f10x_rcu.c:942
rcu_osci_type_enum
rcu_osci_type_enum
Definition: gd32f10x_rcu.h:568
RCU_AFRST
Definition: gd32f10x_rcu.h:477
RCU_INT_FLAG_PLL1STB_CLR
Definition: gd32f10x_rcu.h:547
RCU_GPIODRST
Definition: gd32f10x_rcu.h:481
RCU_WWDGTRST
Definition: gd32f10x_rcu.h:456
rcu_apb2_clock_config
void rcu_apb2_clock_config(uint32_t ck_apb2)
configure the APB2 clock prescaler selection
Definition: gd32f10x_rcu.c:327
rcu_hxtal_clock_monitor_enable
void rcu_hxtal_clock_monitor_enable(void)
enable the HXTAL clock monitor
Definition: gd32f10x_rcu.c:979
APB2EN_REG_OFFSET
#define APB2EN_REG_OFFSET
Definition: gd32f10x_rcu.h:333
RCU_DMA0
Definition: gd32f10x_rcu.h:356
RCU_UART4
Definition: gd32f10x_rcu.h:387
RCU_FLAG_LXTALSTB
Definition: gd32f10x_rcu.h:512
rcu_i2s1_clock_config
void rcu_i2s1_clock_config(uint32_t i2s_clock_source)
configure the I2S1 clock source selection
Definition: gd32f10x_rcu.c:581
RCU_USBD
Definition: gd32f10x_rcu.h:391
AHBEN_REG_OFFSET
#define AHBEN_REG_OFFSET
Definition: gd32f10x_rcu.h:331
APB1RST_REG_OFFSET
#define APB1RST_REG_OFFSET
Definition: gd32f10x_rcu.h:337
RCU_FLAG_PLLSTB
Definition: gd32f10x_rcu.h:507
CK_SYS
Definition: gd32f10x_rcu.h:584
RCU_TIMER2
Definition: gd32f10x_rcu.h:371
RCU_TIMER4
Definition: gd32f10x_rcu.h:373
rcu_system_clock_source_config
void rcu_system_clock_source_config(uint32_t ck_sys)
configure the system clock source
Definition: gd32f10x_rcu.c:249
RCU_CRC
Definition: gd32f10x_rcu.h:358
RCU_INT_FLAG_PLL2STB
Definition: gd32f10x_rcu.h:533
rcu_periph_clock_sleep_disable
void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
disable the peripherals clock when sleep mode
Definition: gd32f10x_rcu.c:156
RCU_SRAM_SLP
Definition: gd32f10x_rcu.h:431
RCU_FLAG_SWRST
Definition: gd32f10x_rcu.h:517
RCU_TIMER12
Definition: gd32f10x_rcu.h:378
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
RCU_INT_FLAG_IRC8MSTB_CLR
Definition: gd32f10x_rcu.h:543
RCU_DACRST
Definition: gd32f10x_rcu.h:474
rcu_adc_clock_config
void rcu_adc_clock_config(uint32_t adc_psc)
configure the ADC prescaler factor
Definition: gd32f10x_rcu.c:493
RCU_INT_FLAG_PLL1STB
Definition: gd32f10x_rcu.h:532
RCU_PLL1_CK
Definition: gd32f10x_rcu.h:576
RCU_INT_IRC8MSTB
Definition: gd32f10x_rcu.h:558
RCU_GPIOC
Definition: gd32f10x_rcu.h:406
RCU_GPIOARST
Definition: gd32f10x_rcu.h:478
rcu_predv0_config
void rcu_predv0_config(uint32_t predv0_div)
configure the PREDV0 division factor
Definition: gd32f10x_rcu.c:396
RCU_TIMER13
Definition: gd32f10x_rcu.h:379
RCU_USBDRST
Definition: gd32f10x_rcu.h:466
RCU_TIMER1RST
Definition: gd32f10x_rcu.h:445
RCU_SPI1
Definition: gd32f10x_rcu.h:382
RCU_USART0
Definition: gd32f10x_rcu.h:416
RCU_INT_FLAG_IRC8MSTB
Definition: gd32f10x_rcu.h:528
RCU_I2C1
Definition: gd32f10x_rcu.h:389
rcu_clock_freq_enum
rcu_clock_freq_enum
Definition: gd32f10x_rcu.h:582
RCU_TIMER9RST
Definition: gd32f10x_rcu.h:496
RCU_TIMER12RST
Definition: gd32f10x_rcu.h:453
RCU_INT_IRC40KSTB
Definition: gd32f10x_rcu.h:556
RCU_GPIOA
Definition: gd32f10x_rcu.h:404
RCU_IRC40K
Definition: gd32f10x_rcu.h:573
RCU_SPI2RST
Definition: gd32f10x_rcu.h:458
RCU_UART3
Definition: gd32f10x_rcu.h:386
RCU_PMURST
Definition: gd32f10x_rcu.h:473
RCU_EXMC
Definition: gd32f10x_rcu.h:359
CK_APB2
Definition: gd32f10x_rcu.h:587
RCU_INT_HXTALSTB
Definition: gd32f10x_rcu.h:559
RCU_TIMER10RST
Definition: gd32f10x_rcu.h:497
rcu_all_reset_flag_clear
void rcu_all_reset_flag_clear(void)
clear all the reset flag
Definition: gd32f10x_rcu.c:647
rcu_osci_on
void rcu_osci_on(rcu_osci_type_enum osci)
turn on the oscillator
Definition: gd32f10x_rcu.c:870
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
CK_AHB
Definition: gd32f10x_rcu.h:585
RCU_USBFSRST
Definition: gd32f10x_rcu.h:440
RCU_FLAG_IRC8MSTB
Definition: gd32f10x_rcu.h:505
RCU_GPIOD
Definition: gd32f10x_rcu.h:407
rcu_pll_config
void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
configure the main PLL clock
Definition: gd32f10x_rcu.c:375
RCU_SPI0RST
Definition: gd32f10x_rcu.h:488
RCU_TIMER1
Definition: gd32f10x_rcu.h:370
RCU_FLAG_IRC40KSTB
Definition: gd32f10x_rcu.h:513
RCU_CAN1
Definition: gd32f10x_rcu.h:395
RCU_INT_FLAG_IRC40KSTB_CLR
Definition: gd32f10x_rcu.h:541
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
APB2RST_REG_OFFSET
#define APB2RST_REG_OFFSET
Definition: gd32f10x_rcu.h:338
RCU_FLAG_FWDGTRST
Definition: gd32f10x_rcu.h:518
RCU_GPIOCRST
Definition: gd32f10x_rcu.h:480
RCU_SDIO
Definition: gd32f10x_rcu.h:361
rcu_int_flag_clear_enum
rcu_int_flag_clear_enum
Definition: gd32f10x_rcu.h:539
RCU_USART0RST
Definition: gd32f10x_rcu.h:490
rcu_osci_stab_wait
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
wait for oscillator stabilization flags is SET or oscillator startup is timeout
Definition: gd32f10x_rcu.c:749
RCU_USART2RST
Definition: gd32f10x_rcu.h:460
RCU_TIMER3RST
Definition: gd32f10x_rcu.h:447
RCU_UART4RST
Definition: gd32f10x_rcu.h:462
RCU_FMC_SLP
Definition: gd32f10x_rcu.h:432
RCU_PLL2_CK
Definition: gd32f10x_rcu.h:577
rcu_rtc_clock_config
void rcu_rtc_clock_config(uint32_t rtc_clock_source)
configure the RTC clock source selection
Definition: gd32f10x_rcu.c:561
rcu_osci_bypass_mode_enable
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
Definition: gd32f10x_rcu.c:903
RCU_TIMER3
Definition: gd32f10x_rcu.h:372
RCU_TIMER0
Definition: gd32f10x_rcu.h:413
rcu_bkp_reset_disable
void rcu_bkp_reset_disable(void)
disable the BKP domain reset
Definition: gd32f10x_rcu.c:234
RCU_USART2
Definition: gd32f10x_rcu.h:385
APB1EN_REG_OFFSET
#define APB1EN_REG_OFFSET
Definition: gd32f10x_rcu.h:332
RCU_TIMER7
Definition: gd32f10x_rcu.h:415
CK_APB1
Definition: gd32f10x_rcu.h:586
RCU_I2C0
Definition: gd32f10x_rcu.h:388
RCU_ADC1RST
Definition: gd32f10x_rcu.h:486
RCU_CAN1RST
Definition: gd32f10x_rcu.h:470
RCU_INT_FLAG_IRC40KSTB
Definition: gd32f10x_rcu.h:526
RCU_UART3RST
Definition: gd32f10x_rcu.h:461
RCU_CAN0
Definition: gd32f10x_rcu.h:393
rcu_i2s2_clock_config
void rcu_i2s2_clock_config(uint32_t i2s_clock_source)
configure the I2S2 clock source selection
Definition: gd32f10x_rcu.c:600
RCU_GPIOERST
Definition: gd32f10x_rcu.h:482
RCU_TIMER9
Definition: gd32f10x_rcu.h:422
RCU_INT_PLLSTB
Definition: gd32f10x_rcu.h:560
RCU_ADC1
Definition: gd32f10x_rcu.h:412
RCU_GPIOF
Definition: gd32f10x_rcu.h:409
RCU_LXTAL
Definition: gd32f10x_rcu.h:571
rcu_periph_clock_enable
void rcu_periph_clock_enable(rcu_periph_enum periph)
enable the peripherals clock
Definition: gd32f10x_rcu.c:93
rcu_periph_enum
rcu_periph_enum
Definition: gd32f10x_rcu.h:353
RCU_FLAG_WWDGTRST
Definition: gd32f10x_rcu.h:519
RCU_TIMER0RST
Definition: gd32f10x_rcu.h:487
RCU_GPIOB
Definition: gd32f10x_rcu.h:405
RCU_TIMER13RST
Definition: gd32f10x_rcu.h:454
rcu_periph_reset_enum
rcu_periph_reset_enum
Definition: gd32f10x_rcu.h:436
RCU_PMU
Definition: gd32f10x_rcu.h:398
rcu_ahb_clock_config
void rcu_ahb_clock_config(uint32_t ck_ahb)
configure the AHB clock prescaler selection
Definition: gd32f10x_rcu.c:281
RCU_FLAG_EPRST
Definition: gd32f10x_rcu.h:515
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_core.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usbh_core.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBH_CORE_H
14 #define USBH_CORE_H
15
16 #include "usbh_conf.h"
17 #include "usb_std.h"
18 #include "usb_core.h"
19
20 #define MSC_CLASS 0x08
21 #define HID_CLASS 0x03
22 #define MSC_PROTOCOL 0x50
23 #define CBI_PROTOCOL 0x01
25 #define USBH_DEVICE_ADDRESS_DEFAULT 0U
26 #define USBH_DEVICE_ADDRESS 1U
27 #define USBH_MAX_ERROR_COUNT 2U
29 #define HOST_USER_SELECT_CONFIGURATION 1U
30 #define HOST_USER_CLASS_ACTIVE 2U
31 #define HOST_USER_CLASS_SELECTED 3U
32 #define HOST_USER_CONNECTION 4U
33 #define HOST_USER_DISCONNECTION 5U
34 #define HOST_USER_UNRECOVERED_ERROR 6U
36 #define MAX_USBH_STATE_STACK_DEEP 4
37 #define MAX_USBH_STATE_TABLE_NUM 10U
39 #define HOST_FSM_ID 0U
40 #define ENUM_FSM_ID 1U
41 #define CMD_FSM_ID 2U
42 #define CTRL_FSM_ID 3U
43 #define CLASS_REQ_FSM_ID 4U
44 #define CLASS_FSM_ID 5U
46 #define UP_STATE 100U
47 #define GO_TO_UP_STATE_EVENT 100U
49 #define HOST_HANDLE_TABLE_SIZE 9U
51 /* the enum of host state */
52 typedef enum
53 {
54 HOST_IDLE = 0, /* the host idle state definition */
55 HOST_DEV_ATTACHED, /* the host device attached state definition */
56 HOST_DEV_DETACHED, /* the host device detached state definition */
57 HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */
58 HOST_ENUMERATION, /* the host enumeration state definition */
59 HOST_CLASS_REQUEST, /* the host class request state definition */
60 HOST_CLASS, /* the host class state definition */
61 HOST_USER_INPUT, /* the host user input state definition */
62 HOST_SUSPENDED, /* the host suspended state definition */
63 HOST_ERROR /* the host error state definition */
64 }host_state_enum;
65
66 /* the enum of host event */
67 typedef enum
68 {
69 HOST_EVENT_ATTACHED = 0, /* the host attached event */
70 HOST_EVENT_ENUM, /* the host enum event */
71 HOST_EVENT_USER_INPUT, /* the host user input event */
72 HOST_EVENT_CLASS_REQ, /* the host class request event */
73 HOST_EVENT_CLASS, /* the host class event */
74 HOST_EVENT_ERROR, /* the host error event */
75 HOST_EVENT_DEV_DETACHED, /* the host device detached event */
76 HOST_EVENT_IDLE /* the host idle event */
77 }host_event_enum;
78
79 /* the enum of enum state */
80 typedef enum
81 {
82 ENUM_IDLE = 0, /* the enum idle state definition */
83 ENUM_SET_ADDR, /* the enum set address state definition */
84 ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */
85 ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */
86 ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */
87 ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */
88 ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */
89 ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */
90 ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */
91 ENUM_DEV_CONFIGURED /* the enum device configuration state definition */
92 }enum_state_enum;
93
94 /* the enum of ctrl state */
95 typedef enum
96 {
97 CTRL_IDLE = 0, /* the ctrl idle state definition */
98 CTRL_SETUP, /* the ctrl setup state definition */
99 CTRL_DATA, /* the ctrl data state definition */
100 CTRL_STATUS, /* the ctrl status state definition */
101 CTRL_ERROR, /* the ctrl error state definition */
102 CTRL_STALLED, /* the ctrl stalled state definition */
103 CTRL_COMPLETE /* the ctrl complete state definition */
104 }ctrl_state_enum;
105
106 /* the enum of host status */
107 typedef enum
108 {
109 USBH_OK = 0, /* the usbh ok status definition */
110 USBH_BUSY, /* the usbh busy status definition */
111 USBH_FAIL, /* the usbh fail status definition */
112 USBH_NOT_SUPPORTED, /* the usbh not supported status definition */
113 USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */
114 USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */
115 USBH_APPLY_DEINIT /* the usbh apply deinit status definition */
116 }usbh_status_enum;
117
118 /* the state of user action */
119 typedef enum
120 {
121 USBH_USER_NO_RESP = 0, /* the user no response */
122 USBH_USER_RESP_OK = 1, /* the user response ok */
123 }usbh_user_status_enum;
124
125 /* control transfer information */
126 typedef struct
127 {
128 uint8_t hc_in_num; /* the host in channel number */
129 uint8_t hc_out_num; /* the host out channel number */
130 uint8_t ep0_size; /* the endpoint 0 max packet size */
131 uint8_t error_count; /* the error count */
132 uint16_t length; /* the length */
133 uint16_t timer; /* the timer */
134 uint8_t *buff; /* the buffer */
135 usb_setup_union setup; /* the setup packet */
136 }usbh_ctrl_struct;
137
138 /* device property */
139 typedef struct
140 {
141 uint8_t address; /* the device address */
142 uint8_t speed; /* the device speed */
143 usb_descriptor_device_struct dev_desc; /* the device descripter */
144 usb_descriptor_configuration_struct cfg_desc; /* the configuration descripter */
145 usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]; /* the interface descripter */
146 usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; /* the endpoint descripter */
147 }usbh_device_struct;
148
149 /* user callbacks */
150 typedef struct
151 {
152 void (*init) (void); /* the user callback init function */
153 void (*deinit) (void); /* the user callback deinit function */
154 void (*device_connected) (void); /* the user callback device connected function */
155 void (*device_reset) (void); /* the user callback device reset function */
156 void (*device_disconnected) (void); /* the user callback device disconnected function */
157 void (*over_current_detected) (void); /* the user callback over current detected function */
158 void (*device_speed_detected) (uint8_t device_speed); /* the user callback device speed detected function */
159 void (*device_desc_available) (void *devDesc); /* the user callback device descrpiter available function */
160 void (*device_address_set) (void); /* the user callback set device address function */
161
162 void (*configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc,
163 usb_descriptor_interface_struct *itf_desc,
164 usb_descriptor_endpoint_struct *ep_desc);
165 /* the configuration descripter available function */
166
167 void (*manufacturer_string) (void *mfc_string); /* the user callback manufacturer string function */
168 void (*product_string) (void *prod_string); /* the user callback product string function */
169 void (*serial_num_string) (void *serial_string); /* the user callback serial number string function */
170 void (*enumeration_finish) (void); /* the user callback enumeration finish function */
171 usbh_user_status_enum (*user_input) (void); /* the user callback user input function */
172 int (*user_application) (usb_core_handle_struct *pudev, uint8_t id);
173 /* the user callback user appliction function */
174 void (*device_not_supported) (void); /* the user callback device not supported function */
175 void (*unrecovered_error) (void); /* the user callback unrecovered error function */
176 }usbh_user_callback_struct;
177
178 /* the backup state struct */
179 typedef struct
180 {
181 host_state_enum host_backup_state; /* the host backup state */
182 enum_state_enum enum_backup_state; /* the enum backup state */
183 ctrl_state_enum ctrl_backup_state; /* the ctrl backup state */
184 uint8_t class_req_backup_state;/* the class request backup state */
185 uint8_t class_backup_state; /* the class backup state */
186 } backup_state_struct;
187
188 /* host information */
189 typedef struct
190 {
191 backup_state_struct usbh_backup_state; /* the usbh backup state variable */
192 usbh_ctrl_struct control; /* the control struct variable */
193 usbh_device_struct device; /* the device struct variable */
194 usbh_user_callback_struct *usr_cb; /* the user callback function */
195 usbh_status_enum (*class_init) (usb_core_handle_struct *pudev, void *phost); /* the class init function */
196 void (*class_deinit) (usb_core_handle_struct *pudev, void *phost); /* the class deinit function */
197 }usbh_host_struct;
198
199 /* the action function definition */
200 typedef usbh_status_enum (*ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void* pustate);
201
202 /* the state table struct */
203 typedef struct
204 {
205 uint8_t cur_state; /* the current state */
206 uint8_t cur_event; /* the current event */
207 uint8_t next_state; /* the next state */
208 ACT_FUN event_action_fun; /* the event action function entry */
209 } state_table_struct;
210
211 /* the state stack struct */
212 typedef struct
213 {
214 uint8_t state; /* the state in state stack */
215 state_table_struct* table; /* the table in state stack */
216 uint8_t table_size; /* the table size in state stack */
217 } usbh_state_stack_struct;
218
219 /* the state regist table struct */
220 typedef struct
221 {
222 uint8_t id; /* the id of the state table */
223 state_table_struct* table; /* the table entry to regist */
224 uint8_t table_size; /* the table size to regist */
225 } usbh_state_regist_table_struct;
226
227 /* the state handle struct */
228 typedef struct
229 {
230 uint8_t usbh_current_state; /* current state */
231 uint8_t usbh_current_state_table_size; /* current state table size */
232 state_table_struct* usbh_current_state_table; /* current state table */
233
234 usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]; /* the stack of state table */
235 int8_t usbh_current_state_stack_top; /* the current state top */
236
237 usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]; /* the array of regist state table */
238 uint8_t usbh_regist_state_table_num; /* the number of regist state table */
239 } usbh_state_handle_struct;
240
241 /* function declarations */
242 /* the host core driver function */
243 usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
244 /* initialize the host portion of the driver */
245 uint32_t hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id);
246 /* check if the device is connected */
247 uint32_t hcd_is_device_connected (usb_core_handle_struct *pudev);
248 /* this function returns the last URBstate */
249 urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num);
250 /* this function returns the last URBstate */
251 uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num);
252 /* de-initialize host */
253 usbh_status_enum usbh_deinit (usb_core_handle_struct *pudev,
254 usbh_host_struct *puhost,
255 usbh_state_handle_struct* pustate);
256
257 /* the state core driver function */
258 /* state core driver init */
259 void scd_init (usbh_state_handle_struct* pustate);
260 /* state core driver table regist */
261 void scd_table_regist (usbh_state_handle_struct* pustate,
262 state_table_struct* pstate_table,
263 uint8_t table_id,
264 uint8_t current_table_size);
265 /* state core driver begin */
266 void scd_begin (usbh_state_handle_struct* pustate, uint8_t table_id);
267 /* state core driver move state */
268 void scd_state_move (usbh_state_handle_struct* pustate, uint8_t state);
269 /* state core driver event handle */
270 usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev,
271 usbh_host_struct *puhost,
272 usbh_state_handle_struct* pustate,
273 uint8_t event,
274 uint8_t state);
275 /* state core driver table push */
276 void scd_table_push (usbh_state_handle_struct* pustate);
277 /* state core driver table pop */
278 void scd_table_pop (usbh_state_handle_struct* pustate);
279 /* the function is only used to state move */
280 usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
281 /* the function to the up state */
282 usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
283
284 #endif /* USBH_CORE_H */
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:91
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
HOST_EVENT_IDLE
Definition: usbh_core.h:76
MAX_USBH_STATE_TABLE_NUM
#define MAX_USBH_STATE_TABLE_NUM
Definition: usbh_core.h:37
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:706
usbh_ctrl_struct
Definition: usbh_core.h:126
hcd_urb_state_get
urb_state_enum hcd_urb_state_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:430
usbh_deinit
usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
de-initialize host
Definition: usbh_core.c:454
usbh_user_status_enum
usbh_user_status_enum
Definition: usbh_core.h:119
usbh_state_handle_struct
Definition: usbh_core.h:228
HOST_EVENT_CLASS_REQ
Definition: usbh_core.h:72
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
scd_init
void scd_init(usbh_state_handle_struct *pustate)
state core driver init
Definition: usbh_core.c:485
HOST_EVENT_CLASS
Definition: usbh_core.h:73
backup_state_struct::ctrl_backup_state
ctrl_state_enum ctrl_backup_state
Definition: usbh_core.h:183
state_table_struct::event_action_fun
ACT_FUN event_action_fun
Definition: usbh_core.h:208
CTRL_IDLE
Definition: usbh_core.h:97
urb_state_enum
urb_state_enum
Definition: usb_core.h:49
ENUM_IDLE
Definition: usbh_core.h:82
CTRL_ERROR
Definition: usbh_core.h:101
usbh_ctrl_struct::timer
uint16_t timer
Definition: usbh_core.h:133
HOST_SUSPENDED
Definition: usbh_core.h:62
HOST_EVENT_ENUM
Definition: usbh_core.h:70
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:128
ENUM_GET_PRODUCT_STRING_DESC
Definition: usbh_core.h:88
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:134
usb_descriptor_interface_struct
Definition: usbd_std.h:142
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
HOST_CLASS
Definition: usbh_core.h:60
HOST_ERROR
Definition: usbh_core.h:63
ctrl_state_enum
ctrl_state_enum
Definition: usbh_core.h:95
usb_descriptor_device_struct
Definition: usbd_std.h:108
HOST_DEV_DETACHED
Definition: usbh_core.h:56
scd_table_pop
void scd_table_pop(usbh_state_handle_struct *pustate)
state core driver table pop
Definition: usbh_core.c:645
USBH_NOT_SUPPORTED
Definition: usbh_core.h:112
HOST_EVENT_ERROR
Definition: usbh_core.h:74
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
usb_setup_union
Definition: usb_std.h:108
ENUM_GET_CFG_DESC
Definition: usbh_core.h:85
usbh_host_struct
Definition: usbh_core.h:189
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:130
hcd_is_device_connected
uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
check if the device is connected.
Definition: usbh_core.c:418
HOST_DEV_ATTACHED
Definition: usbh_core.h:55
usbh_host_struct::usr_cb
usbh_user_callback_struct * usr_cb
Definition: usbh_core.h:194
host_event_enum
host_event_enum
Definition: usbh_core.h:67
backup_state_struct
Definition: usbh_core.h:179
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:238
usbh_device_struct
Definition: usbh_core.h:139
backup_state_struct::enum_backup_state
enum_state_enum enum_backup_state
Definition: usbh_core.h:182
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:224
CTRL_STATUS
Definition: usbh_core.h:100
usbh_device_struct::speed
uint8_t speed
Definition: usbh_core.h:142
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:222
state_table_struct::next_state
uint8_t next_state
Definition: usbh_core.h:207
usbh_ctrl_struct::error_count
uint8_t error_count
Definition: usbh_core.h:131
CTRL_STALLED
Definition: usbh_core.h:102
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
USBH_APPLY_DEINIT
Definition: usbh_core.h:115
HOST_ENUMERATION
Definition: usbh_core.h:58
host_state_enum
host_state_enum
Definition: usbh_core.h:52
USBH_UNRECOVERED_ERROR
Definition: usbh_core.h:113
ENUM_SET_ADDR
Definition: usbh_core.h:83
USBH_USER_RESP_OK
Definition: usbh_core.h:122
usbh_state_stack_struct
Definition: usbh_core.h:212
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
enum_state_enum
enum_state_enum
Definition: usbh_core.h:80
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
state_table_struct
Definition: usbh_core.h:203
HOST_DETECT_DEV_SPEED
Definition: usbh_core.h:57
scd_event_handle
usbh_status_enum scd_event_handle(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle
Definition: usbh_core.c:577
usbh_user_callback_struct
Definition: usbh_core.h:150
usb_core.h
USB core driver header file.
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:191
state_table_struct::cur_state
uint8_t cur_state
Definition: usbh_core.h:205
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:215
host_state_polling_fun
usbh_status_enum host_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of HOST state
Definition: usbh_core.c:89
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:623
backup_state_struct::class_req_backup_state
uint8_t class_req_backup_state
Definition: usbh_core.h:184
ACT_FUN
usbh_status_enum(* ACT_FUN)(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
Definition: usbh_core.h:200
ENUM_SET_CONFIGURATION
Definition: usbh_core.h:90
usbh_device_struct::cfg_desc
usb_descriptor_configuration_struct cfg_desc
Definition: usbh_core.h:144
hcd_init
uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize the host portion of the driver.
Definition: usbh_core.c:386
backup_state_struct::class_backup_state
uint8_t class_backup_state
Definition: usbh_core.h:185
HOST_EVENT_DEV_DETACHED
Definition: usbh_core.h:75
USBH_SPEED_UNKNOWN_ERROR
Definition: usbh_core.h:114
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:141
USBH_USER_NO_RESP
Definition: usbh_core.h:121
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:223
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:132
usb_core_handle_struct
Definition: usb_core.h:201
HOST_EVENT_ATTACHED
Definition: usbh_core.h:69
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:693
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:216
hcd_xfer_count_get
uint32_t hcd_xfer_count_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:442
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:193
USBH_OK
Definition: usbh_core.h:109
ENUM_GET_FULL_CFG_DESC
Definition: usbh_core.h:86
ENUM_GET_FULL_DEV_DESC
Definition: usbh_core.h:84
CTRL_SETUP
Definition: usbh_core.h:98
HOST_CLASS_REQUEST
Definition: usbh_core.h:59
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
usb_std.h
USB 2.0 standard defines.
USBH_FAIL
Definition: usbh_core.h:111
ENUM_GET_MFC_STRING_DESC
Definition: usbh_core.h:87
MAX_USBH_STATE_STACK_DEEP
#define MAX_USBH_STATE_STACK_DEEP
Definition: usbh_core.h:36
ENUM_GET_SERIALNUM_STRING_DESC
Definition: usbh_core.h:89
HOST_USER_INPUT
Definition: usbh_core.h:61
usbh_device_struct::dev_desc
usb_descriptor_device_struct dev_desc
Definition: usbh_core.h:143
usbh_state_regist_table_struct
Definition: usbh_core.h:220
HOST_IDLE
Definition: usbh_core.h:54
scd_table_regist
void scd_table_regist(usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist
Definition: usbh_core.c:516
CTRL_COMPLETE
Definition: usbh_core.h:103
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:129
USBH_BUSY
Definition: usbh_core.h:110
CTRL_DATA
Definition: usbh_core.h:99
state_table_struct::cur_event
uint8_t cur_event
Definition: usbh_core.h:206
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:87
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:135
usb_descriptor_configuration_struct
Definition: usbd_std.h:128
backup_state_struct::host_backup_state
host_state_enum host_backup_state
Definition: usbh_core.h:181
HOST_EVENT_USER_INPUT
Definition: usbh_core.h:71
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbd_int.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usbd_int.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBD_INT_H
14 #define USBD_INT_H
15
16 #include "usbd_core.h"
17
18 typedef struct
19 {
20 uint8_t (*SOF) (usb_core_handle_struct *pudev);
21 }usbd_int_cb_struct;
22
23 extern usbd_int_cb_struct *usbd_int_fops;
24
25 /* function declarations */
26 /* USB device-mode interrupts global service routine handler */
27 uint32_t usbd_isr (usb_core_handle_struct *pudev);
28
29 #endif /* USBD_INT_H */
30
usbd_int_fops
usbd_int_cb_struct * usbd_int_fops
usbd_isr
void usbd_isr(void)
USB interrupt events service routine.
Definition: usbd_int.c:39
usbd_core.h
usb_core_handle_struct
Definition: usb_core.h:201
usbd_int_cb_struct
Definition: usbd_int.h:22
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_rtc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_RTC_H
14 #define GD32F10X_RTC_H
15
16 #include "gd32f10x.h"
17
18 /* RTC definitions */
19 #define RTC RTC_BASE
20
21 /* registers definitions */
22 #define RTC_INTEN REG32(RTC + 0x00U)
23 #define RTC_CTL REG32(RTC + 0x04U)
24 #define RTC_PSCH REG32(RTC + 0x08U)
25 #define RTC_PSCL REG32(RTC + 0x0CU)
26 #define RTC_DIVH REG32(RTC + 0x10U)
27 #define RTC_DIVL REG32(RTC + 0x14U)
28 #define RTC_CNTH REG32(RTC + 0x18U)
29 #define RTC_CNTL REG32(RTC + 0x1CU)
30 #define RTC_ALRMH REG32(RTC + 0x20U)
31 #define RTC_ALRML REG32(RTC + 0x24U)
33 /* bits definitions */
34 /* RTC_INTEN */
35 #define RTC_INTEN_SCIE BIT(0)
36 #define RTC_INTEN_ALRMIE BIT(1)
37 #define RTC_INTEN_OVIE BIT(2)
39 /* RTC_CTL */
40 #define RTC_CTL_SCIF BIT(0)
41 #define RTC_CTL_ALRMIF BIT(1)
42 #define RTC_CTL_OVIF BIT(2)
43 #define RTC_CTL_RSYNF BIT(3)
44 #define RTC_CTL_CMF BIT(4)
45 #define RTC_CTL_LWOFF BIT(5)
47 #define RTC_PSCH_PSC BITS(0, 3)
48 #define RTC_PSCL_PSC BITS(0, 15)
49 #define RTC_DIVH_DIV BITS(0, 3)
50 #define RTC_DIVL_DIV BITS(0, 15)
51 #define RTC_CNTH_CNT BITS(0, 15)
52 #define RTC_CNTL_CNT BITS(0, 15)
53 #define RTC_ALRMH_ALRM BITS(0, 15)
54 #define RTC_ALRML_ALRM BITS(0, 15)
56 /* constants definitions */
57 #define RTC_HIGH_VALUE 0x000F0000U
58 #define RTC_LOW_VALUE 0x0000FFFFU
60 #define RTC_INT_SECOND RTC_INTEN_SCIE
61 #define RTC_INT_ALARM RTC_INTEN_ALRMIE
62 #define RTC_INT_OVERFLOW RTC_INTEN_OVIE
64 #define RTC_FLAG_SECOND RTC_CTL_SCIF
65 #define RTC_FLAG_ALARM RTC_CTL_ALRMIF
66 #define RTC_FLAG_OVERFLOW RTC_CTL_OVIF
67 #define RTC_FLAG_RSYN RTC_CTL_RSYNF
68 #define RTC_FLAG_LWOF RTC_CTL_LWOFF
70 /* function declarations */
71 /* enable RTC interrupt */
72 void rtc_interrupt_enable(uint32_t interrupt);
73 /* disable RTC interrupt */
74 void rtc_interrupt_disable(uint32_t interrupt);
75
76 /* enter RTC configuration mode */
77 void rtc_configuration_mode_enter(void);
78 /* exit RTC configuration mode */
79 void rtc_configuration_mode_exit(void);
80
81 /* wait RTC last write operation finished flag set */
82 void rtc_lwoff_wait(void);
83 /* wait RTC registers synchronized flag set */
84 void rtc_register_sync_wait(void);
85
86 /* get RTC counter value */
87 uint32_t rtc_counter_get(void);
88 /* set RTC counter value */
89 void rtc_counter_set(uint32_t cnt);
90
91 /* set RTC prescaler value */
92 void rtc_prescaler_set(uint32_t psc);
93 /* set RTC alarm value */
94 void rtc_alarm_config(uint32_t alarm);
95 /* get RTC divider value */
96 uint32_t rtc_divider_get(void);
97
98 /* get RTC flag status */
99 FlagStatus rtc_flag_get(uint32_t flag);
100 /* clear RTC flag status */
101 void rtc_flag_clear(uint32_t flag);
102
103 #endif /* GD32F10X_RTC_H */
rtc_divider_get
uint32_t rtc_divider_get(void)
get RTC divider value
Definition: gd32f10x_rtc.c:161
rtc_counter_set
void rtc_counter_set(uint32_t cnt)
set RTC counter value
Definition: gd32f10x_rtc.c:113
rtc_alarm_config
void rtc_alarm_config(uint32_t alarm)
set RTC alarm value
Definition: gd32f10x_rtc.c:145
rtc_prescaler_set
void rtc_prescaler_set(uint32_t psc)
set RTC prescaler value
Definition: gd32f10x_rtc.c:129
rtc_interrupt_disable
void rtc_interrupt_disable(uint32_t interrupt)
disable RTC interrupt
Definition: gd32f10x_rtc.c:38
rtc_register_sync_wait
void rtc_register_sync_wait(void)
wait RTC registers synchronized flag set
Definition: gd32f10x_rtc.c:84
rtc_interrupt_enable
void rtc_interrupt_enable(uint32_t interrupt)
enable RTC interrupt
Definition: gd32f10x_rtc.c:24
rtc_lwoff_wait
void rtc_lwoff_wait(void)
wait RTC last write operation finished flag set
Definition: gd32f10x_rtc.c:71
rtc_flag_clear
void rtc_flag_clear(uint32_t flag)
clear RTC flag status
Definition: gd32f10x_rtc.c:199
rtc_flag_get
FlagStatus rtc_flag_get(uint32_t flag)
get RTC flag status
Definition: gd32f10x_rtc.c:180
rtc_configuration_mode_exit
void rtc_configuration_mode_exit(void)
exit RTC configuration mode
Definition: gd32f10x_rtc.c:60
rtc_counter_get
uint32_t rtc_counter_get(void)
get RTC counter value
Definition: gd32f10x_rtc.c:99
rtc_configuration_mode_enter
void rtc_configuration_mode_enter(void)
enter RTC configuration mode
Definition: gd32f10x_rtc.c:49
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_spi.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_SPI_H
14 #define GD32F10X_SPI_H
15
16 #include "gd32f10x.h"
17
18 /* SPIx(x=0,1,2) definitions */
19 #define SPI0 (SPI_BASE + 0x0000F800U)
20 #define SPI1 SPI_BASE
21 #define SPI2 (SPI_BASE + 0x00000400U)
22
23 /* SPI registers definitions */
24 #define SPI_CTL0(spix) REG32((spix) + 0x00U)
25 #define SPI_CTL1(spix) REG32((spix) + 0x04U)
26 #define SPI_STAT(spix) REG32((spix) + 0x08U)
27 #define SPI_DATA(spix) REG32((spix) + 0x0CU)
28 #define SPI_CRCPOLY(spix) REG32((spix) + 0x10U)
29 #define SPI_RCRC(spix) REG32((spix) + 0x14U)
30 #define SPI_TCRC(spix) REG32((spix) + 0x18U)
31 #define SPI_I2SCTL(spix) REG32((spix) + 0x1CU)
32 #define SPI_I2SPSC(spix) REG32((spix) + 0x20U)
34 /* bits definitions */
35 /* SPI_CTL0 */
36 #define SPI_CTL0_CKPH BIT(0)
37 #define SPI_CTL0_CKPL BIT(1)
38 #define SPI_CTL0_MSTMOD BIT(2)
39 #define SPI_CTL0_PSC BITS(3,5)
40 #define SPI_CTL0_SPIEN BIT(6)
41 #define SPI_CTL0_LF BIT(7)
42 #define SPI_CTL0_SWNSS BIT(8)
43 #define SPI_CTL0_SWNSSEN BIT(9)
44 #define SPI_CTL0_RO BIT(10)
45 #define SPI_CTL0_FF16 BIT(11)
46 #define SPI_CTL0_CRCNT BIT(12)
47 #define SPI_CTL0_CRCEN BIT(13)
48 #define SPI_CTL0_BDOEN BIT(14)
49 #define SPI_CTL0_BDEN BIT(15)
51 /* SPI_CTL1 */
52 #define SPI_CTL1_DMAREN BIT(0)
53 #define SPI_CTL1_DMATEN BIT(1)
54 #define SPI_CTL1_NSSDRV BIT(2)
55 #define SPI_CTL1_ERRIE BIT(5)
56 #define SPI_CTL1_RBNEIE BIT(6)
57 #define SPI_CTL1_TBEIE BIT(7)
59 /* SPI_STAT */
60 #define SPI_STAT_RBNE BIT(0)
61 #define SPI_STAT_TBE BIT(1)
62 #define SPI_STAT_I2SCH BIT(2)
63 #define SPI_STAT_TXURERR BIT(3)
64 #define SPI_STAT_CRCERR BIT(4)
65 #define SPI_STAT_CONFERR BIT(5)
66 #define SPI_STAT_RXORERR BIT(6)
67 #define SPI_STAT_TRANS BIT(7)
69 /* SPI_DATA */
70 #define SPI_DATA_DATA BITS(0,15)
72 /* SPI_CRCPOLY */
73 #define SPI_CRCPOLY_CPR BITS(0,15)
75 /* SPI_RCRC */
76 #define SPI_RCRC_RCR BITS(0,15)
78 /* SPI_TCRC */
79 #define SPI_TCRC_TCR BITS(0,15)
81 /* SPI_I2SCTL */
82 #define SPI_I2SCTL_CHLEN BIT(0)
83 #define SPI_I2SCTL_DTLEN BITS(1,2)
84 #define SPI_I2SCTL_CKPL BIT(3)
85 #define SPI_I2SCTL_I2SSTD BITS(4,5)
86 #define SPI_I2SCTL_PCMSMOD BIT(7)
87 #define SPI_I2SCTL_I2SOPMOD BITS(8,9)
88 #define SPI_I2SCTL_I2SEN BIT(10)
89 #define SPI_I2SCTL_I2SSEL BIT(11)
91 /* SPI_I2SPSC */
92 #define SPI_I2SPSC_DIV BITS(0,7)
93 #define SPI_I2SPSC_OF BIT(8)
94 #define SPI_I2SPSC_MCKOEN BIT(9)
96 /* constants definitions */
97 /* SPI and I2S parameter struct definitions */
98 typedef struct
99 {
100 uint32_t device_mode;
101 uint32_t trans_mode;
102 uint32_t frame_size;
103 uint32_t nss;
104 uint32_t endian;
105 uint32_t clock_polarity_phase;
106 uint32_t prescale;
107 }spi_parameter_struct;
108
109 /* SPI mode definitions */
110 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)
111 #define SPI_SLAVE ((uint32_t)0x00000000U)
113 /* SPI bidirectional transfer direction */
114 #define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN
115 #define SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN
117 /* SPI transmit type */
118 #define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U)
119 #define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO
120 #define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN
121 #define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)
123 /* SPI frame size */
124 #define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16
125 #define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U)
127 /* SPI NSS control mode */
128 #define SPI_NSS_SOFT SPI_CTL0_SWNSSEN
129 #define SPI_NSS_HARD ((uint32_t)0x00000000U)
131 /* SPI transmit way */
132 #define SPI_ENDIAN_MSB ((uint32_t)0x00000000U)
133 #define SPI_ENDIAN_LSB SPI_CTL0_LF
135 /* SPI clock phase and polarity */
136 #define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U)
137 #define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL
138 #define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH
139 #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH)
141 /* SPI clock prescale factor */
142 #define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
143 #define SPI_PSC_2 CTL0_PSC(0)
144 #define SPI_PSC_4 CTL0_PSC(1)
145 #define SPI_PSC_8 CTL0_PSC(2)
146 #define SPI_PSC_16 CTL0_PSC(3)
147 #define SPI_PSC_32 CTL0_PSC(4)
148 #define SPI_PSC_64 CTL0_PSC(5)
149 #define SPI_PSC_128 CTL0_PSC(6)
150 #define SPI_PSC_256 CTL0_PSC(7)
152 /* I2S audio sample rate */
153 #define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U)
154 #define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U)
155 #define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U)
156 #define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U)
157 #define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U)
158 #define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U)
159 #define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U)
160 #define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U)
161 #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U)
163 /* I2S frame format */
164 #define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
165 #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0)
166 #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN)
167 #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN)
168 #define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN)
170 /* I2S master clock output */
171 #define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U)
172 #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN
174 /* I2S operation mode */
175 #define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
176 #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0)
177 #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1)
178 #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2)
179 #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3)
181 /* I2S standard */
182 #define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
183 #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0)
184 #define I2S_STD_MSB I2SCTL_I2SSTD(1)
185 #define I2S_STD_LSB I2SCTL_I2SSTD(2)
186 #define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3)
187 #define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD)
189 /* I2S clock polarity */
190 #define I2S_CKPL_LOW ((uint32_t)0x00000000U)
191 #define I2S_CKPL_HIGH SPI_I2SCTL_CKPL
193 /* SPI DMA constants definitions */
194 #define SPI_DMA_TRANSMIT ((uint8_t)0x00U)
195 #define SPI_DMA_RECEIVE ((uint8_t)0x01U)
197 /* SPI CRC constants definitions */
198 #define SPI_CRC_TX ((uint8_t)0x00U)
199 #define SPI_CRC_RX ((uint8_t)0x01U)
201 /* SPI/I2S interrupt enable/disable constants definitions */
202 #define SPI_I2S_INT_TBE ((uint8_t)0x00U)
203 #define SPI_I2S_INT_RBNE ((uint8_t)0x01U)
204 #define SPI_I2S_INT_ERR ((uint8_t)0x02U)
206 /* SPI/I2S interrupt flag constants definitions */
207 #define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U)
208 #define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U)
209 #define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U)
210 #define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U)
211 #define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U)
212 #define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U)
214 /* SPI/I2S flag definitions */
215 #define SPI_FLAG_RBNE SPI_STAT_RBNE
216 #define SPI_FLAG_TBE SPI_STAT_TBE
217 #define SPI_FLAG_CRCERR SPI_STAT_CRCERR
218 #define SPI_FLAG_CONFERR SPI_STAT_CONFERR
219 #define SPI_FLAG_RXORERR SPI_STAT_RXORERR
220 #define SPI_FLAG_TRANS SPI_STAT_TRANS
221 #define I2S_FLAG_RBNE SPI_STAT_RBNE
222 #define I2S_FLAG_TBE SPI_STAT_TBE
223 #define I2S_FLAG_CH SPI_STAT_I2SCH
224 #define I2S_FLAG_TXURERR SPI_STAT_TXURERR
225 #define I2S_FLAG_RXORERR SPI_STAT_RXORERR
226 #define I2S_FLAG_TRANS SPI_STAT_TRANS
228 /* function declarations */
229 /* reset SPI and I2S */
230 void spi_i2s_deinit(uint32_t spi_periph);
231 /* initialize SPI parameter */
232 void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
233 /* enable SPI */
234 void spi_enable(uint32_t spi_periph);
235 /* disable SPI */
236 void spi_disable(uint32_t spi_periph);
237
238 /* initialize I2S parameter */
239 void i2s_init(uint32_t spi_periph,uint32_t mode, uint32_t standard, uint32_t ckpl);
240 /* configure I2S prescaler */
241 void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
242 /* enable I2S */
243 void i2s_enable(uint32_t spi_periph);
244 /* disable I2S */
245 void i2s_disable(uint32_t spi_periph);
246
247 /* enable SPI NSS output */
248 void spi_nss_output_enable(uint32_t spi_periph);
249 /* disable SPI NSS output */
250 void spi_nss_output_disable(uint32_t spi_periph);
251 /* SPI NSS pin high level in software mode */
252 void spi_nss_internal_high(uint32_t spi_periph);
253 /* SPI NSS pin low level in software mode */
254 void spi_nss_internal_low(uint32_t spi_periph);
255
256 /* enable SPI DMA */
257 void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
258 /* disable SPI DMA */
259 void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
260
261 /* configure SPI/I2S data frame format */
262 void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
263 /* SPI transmit data */
264 void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
265 /* SPI receive data */
266 uint16_t spi_i2s_data_receive(uint32_t spi_periph);
267 /* configure SPI bidirectional transfer direction */
268 void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
269
270 /* enable SPI and I2S interrupt */
271 void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
272 /* disable SPI and I2S interrupt */
273 void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
274 /* get SPI and I2S interrupt status */
275 FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
276 /* get SPI and I2S flag status */
277 FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
278 /* clear SPI CRC error flag status */
279 void spi_crc_error_clear(uint32_t spi_periph);
280
281 /* turn on SPI CRC function */
282 void spi_crc_on(uint32_t spi_periph);
283 /* turn off SPI CRC function */
284 void spi_crc_off(uint32_t spi_periph);
285 /* set SPI CRC polynomial */
286 void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
287 /* get SPI CRC polynomial */
288 uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
289 /* SPI next data is CRC value */
290 void spi_crc_next(uint32_t spi_periph);
291 /* get SPI CRC send value or receive value */
292 uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
293
294 #endif /* GD32F10X_SPI_H */
spi_crc_error_clear
void spi_crc_error_clear(uint32_t spi_periph)
clear SPI CRC error flag status
Definition: gd32f10x_spi.c:576
spi_i2s_flag_get
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
get SPI and I2S flag status
Definition: gd32f10x_spi.c:561
spi_i2s_interrupt_flag_get
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
get SPI and I2S interrupt flag status
Definition: gd32f10x_spi.c:495
spi_i2s_data_transmit
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
SPI transmit data.
Definition: gd32f10x_spi.c:385
i2s_init
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
initialize I2S parameter
Definition: gd32f10x_spi.c:138
spi_parameter_struct::nss
uint32_t nss
Definition: gd32f10x_spi.h:103
spi_nss_output_disable
void spi_nss_output_disable(uint32_t spi_periph)
disable SPI NSS output
Definition: gd32f10x_spi.c:298
spi_parameter_struct::device_mode
uint32_t device_mode
Definition: gd32f10x_spi.h:100
spi_crc_polynomial_get
uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
get SPI CRC polynomial
Definition: gd32f10x_spi.c:622
i2s_psc_config
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
configure I2S prescaler
Definition: gd32f10x_spi.c:181
i2s_disable
void i2s_disable(uint32_t spi_periph)
disable I2S
Definition: gd32f10x_spi.c:276
spi_dma_disable
void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
disable SPI DMA send or receive
Definition: gd32f10x_spi.c:352
spi_bidirectional_transfer_config
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
configure SPI bidirectional transfer direction
Definition: gd32f10x_spi.c:409
spi_parameter_struct::frame_size
uint32_t frame_size
Definition: gd32f10x_spi.h:102
spi_crc_polynomial_set
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
set CRC polynomial
Definition: gd32f10x_spi.c:610
spi_i2s_deinit
void spi_i2s_deinit(uint32_t spi_periph)
reset SPI and I2S
Definition: gd32f10x_spi.c:29
spi_init
void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct)
initialize SPI parameter
Definition: gd32f10x_spi.c:69
spi_dma_enable
void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
enable SPI DMA send or receive
Definition: gd32f10x_spi.c:334
spi_enable
void spi_enable(uint32_t spi_periph)
enable SPI
Definition: gd32f10x_spi.c:102
spi_parameter_struct::trans_mode
uint32_t trans_mode
Definition: gd32f10x_spi.h:101
spi_i2s_interrupt_disable
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
disable SPI and I2S interrupt
Definition: gd32f10x_spi.c:462
spi_crc_next
void spi_crc_next(uint32_t spi_periph)
SPI next data is CRC value.
Definition: gd32f10x_spi.c:633
spi_parameter_struct::endian
uint32_t endian
Definition: gd32f10x_spi.h:104
spi_parameter_struct
Definition: gd32f10x_spi.h:98
spi_crc_on
void spi_crc_on(uint32_t spi_periph)
turn on CRC function
Definition: gd32f10x_spi.c:587
spi_disable
void spi_disable(uint32_t spi_periph)
disable SPI
Definition: gd32f10x_spi.c:113
i2s_enable
void i2s_enable(uint32_t spi_periph)
enable I2S
Definition: gd32f10x_spi.c:265
spi_crc_get
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
get SPI CRC send value or receive value
Definition: gd32f10x_spi.c:647
spi_nss_output_enable
void spi_nss_output_enable(uint32_t spi_periph)
enable SPI NSS output
Definition: gd32f10x_spi.c:287
spi_parameter_struct::clock_polarity_phase
uint32_t clock_polarity_phase
Definition: gd32f10x_spi.h:105
spi_crc_off
void spi_crc_off(uint32_t spi_periph)
turn off CRC function
Definition: gd32f10x_spi.c:598
spi_i2s_interrupt_enable
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
enable SPI and I2S interrupt
Definition: gd32f10x_spi.c:431
spi_i2s_data_receive
uint16_t spi_i2s_data_receive(uint32_t spi_periph)
SPI receive data.
Definition: gd32f10x_spi.c:396
spi_parameter_struct::prescale
uint32_t prescale
Definition: gd32f10x_spi.h:106
spi_nss_internal_low
void spi_nss_internal_low(uint32_t spi_periph)
SPI NSS pin low level in software mode.
Definition: gd32f10x_spi.c:320
spi_i2s_data_frame_format_config
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
configure SPI/I2S data frame format
Definition: gd32f10x_spi.c:370
spi_nss_internal_high
void spi_nss_internal_high(uint32_t spi_periph)
SPI NSS pin high level in software mode.
Definition: gd32f10x_spi.c:309
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_core.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usb_core.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USB_CORE_H
14 #define USB_CORE_H
15
16 #include "usb_conf.h"
17 #include "usb_regs.h"
18 #include "usb_defines.h"
19
20 #define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */
21 #define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */
22 #define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */
23
24 #define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT
25 #define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U)
26
27 /* USB core status */
28 typedef enum
29 {
30 USB_OK = 0, /* USB core OK status */
31 USB_FAIL /* USB core fail status */
32 }usb_status_enum;
33
34 /* USB host channel status */
35 typedef enum
36 {
37 HC_IDLE = 0, /* USB host channel idle status */
38 HC_XF, /* USB host channel transfer status */
39 HC_HALTED, /* USB host channel halted status */
40 HC_NAK, /* USB host channel nak status */
41 HC_NYET, /* USB host channel nyet status */
42 HC_STALL, /* USB host channel stall status */
43 HC_TRACERR, /* USB host channel tracerr status */
44 HC_BBERR, /* USB host channel bberr status */
45 HC_DTGERR, /* USB host channel dtgerr status */
46 }hc_status_enum;
47
48 /* USB URB(USB request block) state */
49 typedef enum
50 {
51 URB_IDLE = 0, /* USB URB idle status */
52 URB_DONE, /* USB URB done status */
53 URB_NOTREADY, /* USB URB notready status */
54 URB_ERROR, /* USB URB error status */
55 URB_STALL, /* USB URB stall status */
56 URB_PING /* USB URB ping status */
57 }urb_state_enum;
58
59 /* USB core configuration */
60 typedef struct
61 {
62 uint8_t core_id; /* USB core id */
63 uint8_t core_speed; /* USB core speed */
64 uint8_t phy_interface; /* USB PHY interface */
65 uint8_t host_channel_num; /* USB host channel number */
66 uint8_t dev_endp_num; /* USB device endpoint number */
67 uint8_t sof_output; /* USB SOF output */
68 uint8_t low_power; /* USB low power */
69 uint16_t max_packet_size; /* USB max packet size */
70 uint16_t max_fifo_size; /* USB fifo size */
71 }usb_core_cfgs_struct;
72
73 typedef enum
74 {
75 USBD_OK = 0, /* USB device ok status */
76 USBD_BUSY, /* USB device busy status */
77 USBD_FAIL, /* USB device fail stauts */
78 }usbd_status_enum;
79
80 /* USB control transfer state */
81 typedef enum
82 {
83 USB_CTRL_IDLE = 0, /* USB control transfer idle state */
84 USB_CTRL_SETUP, /* USB control transfer setup state */
85 USB_CTRL_DATA_IN, /* USB control transfer data in state */
86 USB_CTRL_DATA_OUT, /* USB control transfer data out state */
87 USB_CTRL_STATUS_IN, /* USB control transfer status in state*/
88 USB_CTRL_STATUS_OUT, /* USB control transfer status out state */
89 USB_CTRL_STALL /* USB control transfer stall state */
90 }usbd_control_state_enum;
91
92 /* USB transfer direction */
93 typedef enum
94 {
95 USB_RX = 0, /* receive direction type value */
96 USB_TX /* transmit direction type value */
97 }usb_dir_enum;
98
99 /* USB endpoint in device mode */
100 typedef struct
101 {
102 uint8_t endp_type; /* USB endpoint type */
103 uint8_t endp_frame; /* USB endpoint frame */
104 uint32_t endp_mps; /* USB endpoint max packet size */
105
106 /* Transaction level variables */
107 uint8_t *xfer_buff; /* USB transfer buffer */
108 uint32_t xfer_len; /* USB transfer length */
109 uint32_t xfer_count; /* USB transfer count */
110
111 uint32_t dma_addr; /* USBHS can use DMA */
112 }usb_ep_struct;
113
114 /* USB device standard request */
115 typedef struct
116 {
117 uint8_t bmRequestType; /* USB device request type */
118 uint8_t bRequest; /* USB device request */
119 uint16_t wValue; /* USB device request value */
120 uint16_t wIndex; /* USB device request index */
121 uint16_t wLength; /* USB device request length */
122 }usb_device_req_struct;
123
124 /* USB core device driver */
125 typedef struct
126 {
127 uint8_t config_num; /* USB configuration number */
128 uint8_t status; /* USB status */
129 uint8_t ctl_status; /* USB control status */
130 uint8_t prev_status; /* USB previous status */
131 uint8_t connection_status; /* USB connection status */
132 uint32_t remote_wakeup; /* USB remote wakeup */
133
134 /* transfer level variables */
135 uint32_t remain_len; /* USB remain length */
136 uint32_t sum_len; /* USB sum length */
137 uint32_t ctl_len; /* USB control length */
138 uint8_t setup_packet[8 * 3]; /* USB setup packet */
139
140 usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]; /* USB IN endpoint */
141 usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]; /* USB OUT endpoint */
142
143 uint8_t *dev_desc; /* device descriptor */
144 uint8_t *config_desc; /* configuration descriptor */
145 uint8_t* *strings; /* configuration strings */
146
147 /* device class handler */
148 uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */
149 uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */
150 uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */
151 uint8_t (*class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num); /* device data handler */
152 }dcd_dev_struct;
153
154 /* USB core host mode channel */
155 typedef struct
156 {
157 uint8_t dev_addr; /* device address */
158 uint8_t dev_speed; /* device speed */
159 uint8_t DPID; /* endpoint transfer data pid */
160 uint8_t endp_id; /* endpoint number */
161 uint8_t endp_in; /* endpoint in */
162 uint8_t endp_type; /* endpoint type */
163 uint16_t endp_mps; /* endpoint max pactet size */
164 uint16_t info; /* channel information */
165
166 uint8_t *xfer_buff; /* transfer buffer */
167 uint32_t xfer_len; /* transfer length */
168 uint32_t xfer_count; /* trasnfer count */
169
170 uint32_t err_count; /* USB transfer error count */
171
172 hc_status_enum status; /* channel status */
173 urb_state_enum urb_state; /* URB state */
174
175 uint8_t data_tg_in; /* data in toggle */
176 uint8_t data_tg_out; /* data out toggle */
177 }usb_hostchannel_struct;
178
179 /* USB core host driver */
180 typedef struct
181 {
182 uint8_t rx_buffer[RX_MAX_DATA_LENGTH]; /* rx buffer */
183 uint8_t connect_status; /* device connect status */
184 usb_hostchannel_struct host_channel[USB_MAX_FIFOS]; /* host channel */
185 void (*vbus_drive) (void *pudev, uint8_t state); /* the vbus driver function */
186 }hcd_dev_struct;
187
188 #ifdef USE_OTG_MODE
189
190 /* USB core OTG-mode driver */
191 typedef struct
192 {
193 uint8_t OTG_State; /* OTG state */
194 uint8_t OTG_PrevState; /* OTG previous state */
195 uint8_t OTG_Mode; /* OTG mode */
196 }otg_dev_struct;
197
198 #endif /* USE_OTG_MODE */
199
200 /* USB core driver */
201 typedef struct
202 {
203 usb_core_cfgs_struct cfg;
204
205 #ifdef USE_DEVICE_MODE
206 dcd_dev_struct dev;
207 #endif /* USE_DEVICE_MODE */
208
209 #ifdef USE_HOST_MODE
210 hcd_dev_struct host;
211 #endif /* USE_HOST_MODE */
212
213 #ifdef USE_OTG_MODE
214 otg_dev_struct otg;
215 #endif /* USE_OTG_MODE */
216
217 void (*udelay) (const uint32_t usec);
218 void (*mdelay) (const uint32_t msec);
219 }usb_core_handle_struct;
220
221 /* function declarations */
222
223 /* global APIs */
224 /* initializes the USB controller registers and prepares the core device mode or host mode operation */
225 usb_status_enum usb_core_init (usb_core_handle_struct *pudev);
226 /* initialize core parameters */
227 usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id);
228 /* read a packet from the Rx FIFO associated with the endpoint */
229 void* usb_fifo_read (uint8_t *dest, uint16_t len);
230 /* write a packet into the Tx FIFO associated with the endpoint */
231 usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len);
232 /* flush a Tx FIFO or all Tx FIFOs */
233 usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num);
234 /* flush the entire Rx FIFO */
235 usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev);
236 /* set operation mode (host or device) */
237 usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode);
238
239 /* host APIs */
240 #ifdef USE_HOST_MODE
241
242 /* initializes USB core for host mode */
243 usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev);
244 /* enables the host mode interrupts */
245 usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev);
246 /* initialize host channel */
247 usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_num);
248 /* halt channel */
249 usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num);
250 /* prepare host channel for transferring packets */
251 usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num);
252 /* reset host port */
253 uint32_t usb_port_reset (usb_core_handle_struct *pudev);
254 /* control the VBUS to power */
255 void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state);
256 /* stop the USB host and clean up fifos */
257 void usb_host_stop (usb_core_handle_struct *pudev);
258
259 #endif /* USE_HOST_MODE */
260
261 /* device APIs */
262 #ifdef USE_DEVICE_MODE
263
264 /* initialize USB core registers for device mode */
265 usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev);
266 /* configures endpoint 0 to receive SETUP packets */
267 void usb_ep0_startout (usb_core_handle_struct *pudev);
268 /* active remote wakeup signalling */
269 void usb_remotewakeup_active (usb_core_handle_struct *pudev);
270 /* active USB core clock */
271 void usb_clock_ungate (usb_core_handle_struct *pudev);
272 /* stop the device and clean up fifos */
273 void usb_device_stop (usb_core_handle_struct *pudev);
274
275 #endif /* USE_DEVICE_MODE */
276
277 #endif /* USB_CORE_H */
HC_NYET
Definition: usb_core.h:41
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:211
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:128
USB_CTRL_STATUS_OUT
Definition: usb_core.h:88
USB_MAX_DEV_EPCOUNT
#define USB_MAX_DEV_EPCOUNT
Definition: usb_core.h:24
HC_XF
Definition: usb_core.h:38
USB_TX
Definition: usb_core.h:96
dcd_dev_struct::config_num
uint8_t config_num
Definition: usb_core.h:127
usb_fifo_read
void * usb_fifo_read(uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint
Definition: usb_core.c:105
URB_STALL
Definition: usb_core.h:55
usb_hostchannel_struct::info
uint16_t info
Definition: usb_core.h:164
USBD_OK
Definition: usb_core.h:75
USB_CTRL_STATUS_IN
Definition: usb_core.h:87
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:268
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:173
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:238
usb_hostchannel_struct::status
hc_status_enum status
Definition: usb_core.h:172
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:109
urb_state_enum
urb_state_enum
Definition: usb_core.h:49
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:166
dcd_dev_struct::prev_status
uint8_t prev_status
Definition: usb_core.h:130
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:176
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:66
dcd_dev_struct::remain_len
uint32_t remain_len
Definition: usb_core.h:135
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:69
URB_PING
Definition: usb_core.h:56
hc_status_enum
hc_status_enum
Definition: usb_core.h:35
hcd_dev_struct
Definition: usb_core.h:180
usb_device_req_struct
Definition: usbd_core.h:115
USB_CTRL_DATA_IN
Definition: usb_core.h:85
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:82
USB_CTRL_STALL
Definition: usb_core.h:89
USB_OK
Definition: usb_core.h:30
HC_BBERR
Definition: usb_core.h:44
USB_CTRL_DATA_OUT
Definition: usb_core.h:86
USB_MAX_FIFOS
#define USB_MAX_FIFOS
Definition: usb_core.h:25
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:161
dcd_dev_struct::ctl_len
uint32_t ctl_len
Definition: usb_core.h:137
dcd_dev_struct::status
uint8_t status
Definition: usb_core.h:128
dcd_dev_struct
Definition: usb_core.h:125
HC_IDLE
Definition: usb_core.h:37
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
dcd_dev_struct::dev_desc
uint8_t * dev_desc
Definition: usb_core.h:143
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
URB_IDLE
Definition: usb_core.h:51
URB_NOTREADY
Definition: usb_core.h:53
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:64
dcd_dev_struct::strings
uint8_t ** strings
Definition: usb_core.h:145
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:108
dcd_dev_struct::ctl_status
uint8_t ctl_status
Definition: usb_core.h:129
usb_ep_struct::endp_frame
uint8_t endp_frame
Definition: usb_core.h:103
usb_hostchannel_struct::err_count
uint32_t err_count
Definition: usb_core.h:170
dcd_dev_struct::config_desc
uint8_t * config_desc
Definition: usb_core.h:144
usb_regs.h
USB FS cell registers definition and handle macros.
usb_hostchannel_struct
Definition: usb_core.h:155
dcd_dev_struct::connection_status
uint8_t connection_status
Definition: usb_core.h:131
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:67
USB_RX
Definition: usb_core.h:95
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:175
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:163
usb_ep_struct
Definition: usbd_core.h:102
HC_TRACERR
Definition: usb_core.h:43
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:63
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:68
usb_core_cfgs_struct
Definition: usb_core.h:60
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:159
HC_NAK
Definition: usb_core.h:40
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:93
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:167
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:73
HC_STALL
Definition: usb_core.h:42
usb_status_enum
usb_status_enum
Definition: usb_core.h:28
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:157
HC_HALTED
Definition: usb_core.h:39
USB_FAIL
Definition: usb_core.h:31
usb_core_handle_struct
Definition: usb_core.h:201
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:158
URB_ERROR
Definition: usb_core.h:54
dcd_dev_struct::remote_wakeup
uint32_t remote_wakeup
Definition: usb_core.h:132
usb_defines.h
USB core defines.
USB_CTRL_SETUP
Definition: usb_core.h:84
usb_core_cfgs_struct::max_fifo_size
uint16_t max_fifo_size
Definition: usb_core.h:70
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:162
HC_DTGERR
Definition: usb_core.h:45
usb_core_cfgs_struct::core_id
uint8_t core_id
Definition: usb_core.h:62
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:170
USBD_FAIL
Definition: usb_core.h:77
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:65
USBD_BUSY
Definition: usb_core.h:76
dcd_dev_struct::sum_len
uint32_t sum_len
Definition: usb_core.h:136
hcd_dev_struct::connect_status
uint8_t connect_status
Definition: usb_core.h:183
RX_MAX_DATA_LENGTH
#define RX_MAX_DATA_LENGTH
Definition: usb_core.h:21
URB_DONE
Definition: usb_core.h:52
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:168
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:87
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:203
USB_CTRL_IDLE
Definition: usb_core.h:83
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:160
usbd_control_state_enum
usbd_control_state_enum
Definition: usb_core.h:81
usb_ep_struct::dma_addr
uint32_t dma_addr
Definition: usb_core.h:111
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_std.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
usbh_std.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbh_core.h"
14 #include "usbh_usr.h"
15 #include "usbh_std.h"
16 #include "usbh_ctrl.h"
17
18 uint8_t local_buffer[64];
19 uint8_t usbh_cfg_desc[512];
20 uint8_t enum_polling_handle_flag = 0U;
21
22 static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
23 static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
24 static void enum_set_addr_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
25 static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
26 static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
27 static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
28 static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
29 static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
30 static void enum_set_configuration_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
31 static void enum_dev_configured_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
32
33 /* the enumeration state handle function array */
34 void (*enum_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) =
35 {
36 enum_idle_handle,
37 enum_set_addr_handle,
38 enum_get_full_dev_desc_handle,
39 enum_get_cfg_desc_handle,
40 enum_get_full_cfg_desc_handle,
41 enum_get_mfc_string_desc_handle,
42 enum_get_product_string_desc_handle,
43 enum_get_serialnum_string_desc_handle,
44 enum_set_configuration_handle,
45 enum_dev_configured_handle,
46 };
47
48 /* the enumeration state handle table */
49 state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE] =
50 {
51 /* the current state the current event the next state the event function */
52 {ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move },
53 {ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move },
54 {ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move },
55 {ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move },
56 {ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move },
57 {ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move },
58 {ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move },
59 {ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move },
60 {ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move },
61 {ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
62 };
63
72 usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
73 {
74 usbh_status_enum exe_state = USBH_BUSY;
75 usbh_state_handle_struct *p_state;
76 p_state = (usbh_state_handle_struct *)pustate;
77
78 if (0U == enum_polling_handle_flag) {
79 enum_polling_handle_flag = 1U;
80 scd_table_push(p_state);
81 scd_state_move(p_state, ENUM_IDLE);
82 }
83
84 /* start the enumeration state handle */
85 scd_begin(p_state,ENUM_FSM_ID);
86
87 if (0U == p_state->usbh_current_state_stack_top) {
88 enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
89 } else {
90 enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state);
91 }
92
93 /* determine the enumeration whether to complete */
94 if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) {
95 puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE;
96 enum_polling_handle_flag = 0U;
97 exe_state = USBH_OK;
98 }
99
100 return exe_state;
101 }
102
111 static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
112 {
113 puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE;
114
115 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
116 usbh_enum_desc_get(pudev,
117 puhost,
118 pudev->host.rx_buffer,
119 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
120 USB_DEVDESC,
121 8U);
122 if ((void *)0 != pudev->mdelay) {
123 pudev->mdelay(100U);
124 }
125 }
126
127 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
128 usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, 8U);
129 puhost->control.ep0_size = puhost->device.dev_desc.bMaxPacketSize0;
130
131 /* issue reset */
132 usb_port_reset(pudev);
133
134 /* modify control channels configuration for maxpacket size */
135 usbh_channel_modify (pudev,
136 puhost->control.hc_out_num,
137 0U,
138 0U,
139 0U,
140 (uint16_t)puhost->control.ep0_size);
141
142 usbh_channel_modify (pudev,
143 puhost->control.hc_in_num,
144 0U,
145 0U,
146 0U,
147 (uint16_t)puhost->control.ep0_size);
148
149 scd_event_handle(pudev,
150 puhost,
151 pustate,
152 ENUM_EVENT_SET_ADDR,
153 pustate->usbh_current_state);
154 }
155 }
156
165 static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev,
166 usbh_host_struct *puhost,
167 usbh_state_handle_struct *pustate)
168 {
169 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_DEV_DESC;
170
171 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
172 usbh_enum_desc_get(pudev,
173 puhost,
174 pudev->host.rx_buffer,
175 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
176 USB_DEVDESC,
177 USB_DEVDESC_SIZE);
178 }
179
180 if(USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){
181 usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, USB_DEVDESC_SIZE);
182 puhost->usr_cb->device_desc_available(&puhost->device.dev_desc);
183
184 scd_event_handle(pudev,
185 puhost,
186 pustate,
187 ENUN_EVENT_GET_CFG_DESC,
188 pustate->usbh_current_state);
189 }
190 }
191
200 static void enum_set_addr_handle (usb_core_handle_struct *pudev,
201 usbh_host_struct *puhost,
202 usbh_state_handle_struct *pustate)
203 {
204 puhost->usbh_backup_state.enum_backup_state = ENUM_SET_ADDR;
205
206 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
207 usbh_enum_addr_set(pudev, puhost,USBH_DEVICE_ADDRESS);
208 if ((void *)0 != pudev->mdelay) {
209 pudev->mdelay(100U);
210 }
211 }
212
213 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
214 if ((void *)0 != pudev->mdelay) {
215 pudev->mdelay(2U);
216 }
217 puhost->device.address = USBH_DEVICE_ADDRESS;
218
219 /* user callback for device address assigned */
220 puhost->usr_cb->device_address_set();
221
222 /* modify control channels to update device address */
223 usbh_channel_modify (pudev,
224 puhost->control.hc_in_num,
225 puhost->device.address,
226 0U,
227 0U,
228 0U);
229
230 usbh_channel_modify (pudev,
231 puhost->control.hc_out_num,
232 puhost->device.address,
233 0U,
234 0U,
235 0U);
236
237 scd_event_handle(pudev,
238 puhost,
239 pustate,
240 ENUN_EVENT_GET_FULL_DEV_DESC,
241 pustate->usbh_current_state);
242 }
243 }
244
253 static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev,
254 usbh_host_struct *puhost,
255 usbh_state_handle_struct *pustate)
256 {
257 uint16_t index = 0U;
258
259 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_CFG_DESC;
260
261 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
262 usbh_enum_desc_get(pudev,
263 puhost,
264 pudev->host.rx_buffer,
265 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
266 USB_CFGDESC,
267 USB_CFGDESC_SIZE);
268 }
269
270 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
271 /* save configuration descriptor for class parsing usage */
272 for (; index < USB_CFGDESC_SIZE; index ++) {
273 usbh_cfg_desc[index] = pudev->host.rx_buffer[index];
274 }
275
276 /* commands successfully sent and response received */
277 usbh_cfg_desc_parse (&puhost->device.cfg_desc,
278 puhost->device.itf_desc,
279 puhost->device.ep_desc,
280 pudev->host.rx_buffer,
281 USB_CFGDESC_SIZE);
282
283 scd_event_handle(pudev,
284 puhost,
285 pustate,
286 ENUN_EVENT_GET_FULL_CFG_DESC,
287 pustate->usbh_current_state);
288 }
289 }
290
299 static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev,
300 usbh_host_struct *puhost,
301 usbh_state_handle_struct *pustate)
302 {
303
304 uint16_t index = 0U;
305
306 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_CFG_DESC;
307
308 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
309 usbh_enum_desc_get (pudev, puhost, pudev->host.rx_buffer,
310 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
311 USB_CFGDESC, puhost->device.cfg_desc.wTotalLength);
312 }
313
314
315 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
316 /* save configuration descriptor for class parsing usage */
317 for (; index < puhost->device.cfg_desc.wTotalLength; index ++) {
318 usbh_cfg_desc[index] = pudev->host.rx_buffer[index];
319 }
320
321 /* commands successfully sent and response received */
322 usbh_cfg_desc_parse (&puhost->device.cfg_desc,
323 puhost->device.itf_desc,
324 puhost->device.ep_desc,
325 pudev->host.rx_buffer,
326 puhost->device.cfg_desc.wTotalLength);
327
328 /* User callback for configuration descriptors available */
329 puhost->usr_cb->configuration_desc_available(&puhost->device.cfg_desc,
330 puhost->device.itf_desc,
331 puhost->device.ep_desc[0]);
332
333 scd_event_handle(pudev,
334 puhost,
335 pustate,
336 ENUN_EVENT_GET_MFC_STRING_DESC,
337 pustate->usbh_current_state);
338 }
339 }
340
349 static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev,
350 usbh_host_struct *puhost,
351 usbh_state_handle_struct *pustate)
352 {
353 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_MFC_STRING_DESC;
354
355 if (0U != puhost->device.dev_desc.iManufacturer) {
356 if(CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
357 usbh_enum_desc_get(pudev,
358 puhost,
359 pudev->host.rx_buffer,
360 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
361 USB_STRDESC | puhost->device.dev_desc.iManufacturer,
362 0xffU);
363 }
364
365 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
366 usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU);
367 puhost->usr_cb->manufacturer_string(local_buffer);
368
369 scd_event_handle(pudev,
370 puhost,
371 pustate,
372 ENUN_EVENT_GET_PRODUCT_STRING_DESC,
373 pustate->usbh_current_state);
374 }
375 } else {
376 puhost->usr_cb->manufacturer_string("N/A");
377 scd_state_move((usbh_state_handle_struct *)pustate, ENUM_GET_PRODUCT_STRING_DESC);
378 }
379 }
380
389 static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev,
390 usbh_host_struct *puhost,
391 usbh_state_handle_struct *pustate)
392 {
393 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_PRODUCT_STRING_DESC;
394
395 if (0U != puhost->device.dev_desc.iProduct) {
396 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
397 usbh_enum_desc_get(pudev,
398 puhost,
399 pudev->host.rx_buffer,
400 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
401 USB_STRDESC | puhost->device.dev_desc.iProduct,
402 0xffU);
403 }
404
405 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
406 usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU);
407
408 /* user callback for product string */
409 puhost->usr_cb->product_string(local_buffer);
410
411 scd_event_handle(pudev,
412 puhost,
413 pustate,
414 ENUN_EVENT_GET_SERIALNUM_STRING_DESC,
415 pustate->usbh_current_state);
416 }
417 } else {
418 puhost->usr_cb->product_string("N/A");
419 scd_event_handle(pudev,
420 puhost,
421 pustate,
422 ENUN_EVENT_GET_SERIALNUM_STRING_DESC,
423 pustate->usbh_current_state);
424 }
425 }
426
435 static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev,
436 usbh_host_struct *puhost,
437 usbh_state_handle_struct *pustate)
438 {
439 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_SERIALNUM_STRING_DESC;
440
441 if (0U != puhost->device.dev_desc.iSerialNumber) {
442 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
443 usbh_enum_desc_get(pudev,
444 puhost,
445 pudev->host.rx_buffer,
446 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
447 USB_STRDESC | puhost->device.dev_desc.iSerialNumber,
448 0xffU);
449 }
450
451 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){
452 usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU);
453
454 /* user callback for product string */
455 puhost->usr_cb->serial_num_string(local_buffer);
456 scd_event_handle(pudev,
457 puhost,
458 pustate,
459 ENUN_EVENT_SET_CONFIGURATION,
460 pustate->usbh_current_state);
461 }
462 } else {
463 puhost->usr_cb->serial_num_string("N/A");
464 scd_event_handle(pudev,
465 puhost,
466 pustate,
467 ENUN_EVENT_SET_CONFIGURATION,
468 pustate->usbh_current_state);
469 }
470 }
471
480 static void enum_set_configuration_handle (usb_core_handle_struct *pudev,
481 usbh_host_struct *puhost,
482 usbh_state_handle_struct *pustate)
483 {
484 puhost->usbh_backup_state.enum_backup_state = ENUM_SET_CONFIGURATION;
485
486 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state ) {
487 usbh_enum_cfg_set(pudev, puhost, (uint16_t)puhost->device.cfg_desc.bConfigurationValue);
488 }
489
490 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
491 scd_event_handle(pudev,
492 puhost,
493 pustate,
494 ENUN_EVENT_DEV_CONFIGURED,
495 pustate->usbh_current_state);
496 }
497 }
498
507 static void enum_dev_configured_handle (usb_core_handle_struct *pudev,
508 usbh_host_struct *puhost,
509 usbh_state_handle_struct *pustate)
510 {
511 puhost->usbh_backup_state.enum_backup_state = ENUM_DEV_CONFIGURED;
512 scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state);
513 }
514
526 void usbh_enum_desc_get(usb_core_handle_struct *pudev,
527 usbh_host_struct *puhost,
528 uint8_t *buf,
529 uint8_t req_type,
530 uint16_t value_idx,
531 uint16_t len)
532 {
533 usb_setup_union *pSetup = &(puhost->control.setup);
534
535 pSetup->b.bmRequestType = USB_DIR_IN | req_type;
536 pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR;
537 pSetup->b.wValue = value_idx;
538
539 if (USB_STRDESC == (value_idx & 0xff00U)){
540 pSetup->b.wIndex = 0x0409U;
541 } else {
542 pSetup->b.wIndex = 0U;
543 }
544
545 pSetup->b.wLength = len;
546
547 puhost->control.buff = buf;
548 puhost->control.length = len;
549
550 }
551
560 void usbh_enum_addr_set(usb_core_handle_struct *pudev,
561 usbh_host_struct *puhost,
562 uint8_t device_address)
563 {
564 usb_setup_union *p_setup = &(puhost->control.setup);
565
566 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
567 p_setup->b.bRequest = USBREQ_SET_ADDRESS;
568 p_setup->b.wValue = (uint16_t)device_address;
569 p_setup->b.wIndex = 0U;
570 p_setup->b.wLength = 0U;
571 puhost->control.buff = 0U;
572 puhost->control.length = 0U;
573 }
574
583 void usbh_enum_cfg_set(usb_core_handle_struct *pudev,
584 usbh_host_struct *puhost,
585 uint16_t cfg_idx)
586 {
587 usb_setup_union *p_setup = &(puhost->control.setup);
588
589 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
590 p_setup->b.bRequest = USBREQ_SET_CONFIGURATION;
591 p_setup->b.wValue = cfg_idx;
592 p_setup->b.wIndex = 0U;
593 p_setup->b.wLength = 0U;
594 puhost->control.buff = 0;
595 puhost->control.length = 0U;
596 }
597
606 void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
607 {
608 dev_desc->Header.bLength = *(uint8_t *)(buf + 0);
609 dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
610 dev_desc->bcdUSB = SWAPBYTE(buf + 2);
611 dev_desc->bDeviceClass = *(uint8_t *)(buf + 4);
612 dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5);
613 dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6);
614 dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7);
615
616 if (len > 8U){
617 /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */
618 dev_desc->idVendor = SWAPBYTE(buf + 8);
619 dev_desc->idProduct = SWAPBYTE(buf + 10);
620 dev_desc->bcdDevice = SWAPBYTE(buf + 12);
621 dev_desc->iManufacturer = *(uint8_t *)(buf + 14);
622 dev_desc->iProduct = *(uint8_t *)(buf + 15);
623 dev_desc->iSerialNumber = *(uint8_t *)(buf + 16);
624 dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17);
625 }
626 }
627
638 void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc,
639 usb_descriptor_interface_struct *itf_desc,
640 usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM],
641 uint8_t *buf,
642 uint16_t len)
643 {
644 usb_descriptor_interface_struct *pitf = NULL;
645 usb_descriptor_interface_struct temp_pitf;
646 usb_descriptor_endpoint_struct *pep = NULL;
647 usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf;
648
649 uint8_t itf_ix = 0U;
650 uint8_t ep_ix = 0U;
651 uint16_t ptr = 0U;
652 static uint8_t prev_itf = 0U;
653 static uint16_t prev_ep_size = 0U;
654
655 /* parse configuration descriptor */
656 cfg_desc->Header.bLength = *(uint8_t *)(buf + 0);
657 cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
658 cfg_desc->wTotalLength = SWAPBYTE(buf + 2);
659 cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4);
660 cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5);
661 cfg_desc->iConfiguration = *(uint8_t *)(buf + 6);
662 cfg_desc->bmAttributes = *(uint8_t *)(buf + 7);
663 cfg_desc->bMaxPower = *(uint8_t *)(buf + 8);
664
665 if (len > USB_CFGDESC_SIZE) {
666 ptr = USB_CFG_DESC_LEN;
667
668 if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) {
669 pitf = (usb_descriptor_interface_struct *)0;
670
671 for (; ptr < cfg_desc->wTotalLength; ) {
672 pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr);
673
674 if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) {
675 itf_ix = *((uint8_t *)pdesc + 2U);
676 pitf = &itf_desc[itf_ix];
677
678 if (*((uint8_t *)pdesc + 3U) < 3U) {
679 usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc);
680
681 /* parse endpoint descriptors relative to the current interface */
682 if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) {
683 for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) {
684 pdesc = usbh_next_desc_get((void* )pdesc, &ptr);
685
686 if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) {
687 pep = &ep_desc[itf_ix][ep_ix];
688
689 if (prev_itf != itf_ix) {
690 prev_itf = itf_ix;
691 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
692 } else {
693 if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) {
694 break;
695 } else {
696 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
697 }
698 }
699
700 usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc);
701 prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4);
702 ep_ix++;
703 }
704 }
705 }
706 }
707 }
708 }
709 }
710
711 prev_ep_size = 0U;
712 prev_itf = 0U;
713 }
714 }
715
723 void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
724 {
725 itf_desc->Header.bLength = *(uint8_t *)(buf + 0);
726 itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
727 itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2);
728 itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3);
729 itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4);
730 itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5);
731 itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6);
732 itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7);
733 itf_desc->iInterface = *(uint8_t *)(buf + 8);
734 }
735
743 void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
744 {
745 ep_desc->Header.bLength = *(uint8_t *)(buf + 0);
746 ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
747 ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2);
748 ep_desc->bmAttributes = *(uint8_t *)(buf + 3);
749 ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4);
750 ep_desc->bInterval = *(uint8_t *)(buf + 6);
751 }
752
761 void usbh_string_desc_parse (uint8_t* psrc, uint8_t* pdest, uint16_t len)
762 {
763 uint16_t strlength;
764 uint16_t idx;
765
766 /* the unicode string descriptor is not null-terminated. the string length is
767 computed by substracting two from the value of the first byte of the descriptor.
768 */
769
770 /* check which is lower size, the size of string or the length of bytes read from the device */
771
772 if (USB_DESCTYPE_STRING == psrc[1]){
773 /* make sure the descriptor is string type */
774
775 /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */
776 strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len);
777 psrc += 2; /* adjust the offset ignoring the string len and descriptor type */
778
779 for (idx = 0U; idx < strlength; idx += 2U) {
780 /* copy only the string and ignore the unicode id, hence add the src */
781 *pdest = psrc[idx];
782 pdest++;
783 }
784
785 *pdest = 0U; /* mark end of string */
786 }
787 }
788
796 usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr)
797 {
798 uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength;
799
800 usb_descriptor_header_struct *pnext;
801
802 *ptr += len;
803
804 pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len);
805
806 return(pnext);
807 }
808
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:91
usb_descriptor_interface_struct::bInterfaceProtocol
uint8_t bInterfaceProtocol
Definition: usbd_std.h:151
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
USB_STRDESC
#define USB_STRDESC
Definition: usb_std.h:77
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:706
usb_descriptor_configuration_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:136
usbh_core.h
header file for usbh_core.c
usbh_std.h
header file for usbh_std.c
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
Definition: usbh_std.h:39
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:162
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:20
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:117
usb_descriptor_device_struct::idProduct
uint16_t idProduct
Definition: usbd_std.h:118
ctrl_state_polling_fun
usbh_status_enum ctrl_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state
Definition: usbh_ctrl.c:73
usb_descriptor_interface_struct::iInterface
uint8_t iInterface
Definition: usbd_std.h:152
USB_DESCTYPE_INTERFACE
#define USB_DESCTYPE_INTERFACE
Definition: usbd_std.h:57
usb_descriptor_configuration_struct::wTotalLength
uint16_t wTotalLength
Definition: usbd_std.h:132
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:49
usbh_state_handle_struct
Definition: usbh_core.h:228
usbh_user_callback_struct::serial_num_string
void(* serial_num_string)(void *serial_string)
Definition: usbh_core.h:169
usbh_enum_addr_set
void usbh_enum_addr_set(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address)
set address in usb host enumeration stage
Definition: usbh_std.c:560
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:40
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
usb_descriptor_configuration_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:130
ENUN_EVENT_DEV_CONFIGURED
Definition: usbh_std.h:41
backup_state_struct::ctrl_backup_state
ctrl_state_enum ctrl_backup_state
Definition: usbh_core.h:183
usbh_endpoint_desc_parse
void usbh_endpoint_desc_parse(usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor
Definition: usbh_std.c:743
CTRL_IDLE
Definition: usbh_core.h:97
USBREQ_SET_CONFIGURATION
#define USBREQ_SET_CONFIGURATION
Definition: usbd_std.h:50
ENUM_IDLE
Definition: usbh_core.h:82
usbh_cfg_desc
uint8_t usbh_cfg_desc[512]
Definition: usbh_std.c:19
usbh_device_struct::ep_desc
usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]
Definition: usbh_core.h:146
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:114
ENUN_EVENT_SET_CONFIGURATION
Definition: usbh_std.h:40
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usbd_std.h:148
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:128
usbh_user_callback_struct::product_string
void(* product_string)(void *prod_string)
Definition: usbh_core.h:168
ENUM_GET_PRODUCT_STRING_DESC
Definition: usbh_core.h:88
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:134
usb_descriptor_interface_struct
Definition: usbd_std.h:142
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usbd_std.h:39
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usb_descriptor_header_struct
Definition: usbd_std.h:102
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usbd_std.h:161
usb_descriptor_device_struct
Definition: usbd_std.h:108
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
usb_setup_union
Definition: usb_std.h:108
ENUM_GET_CFG_DESC
Definition: usbh_core.h:85
usbh_host_struct
Definition: usbh_core.h:189
usb_descriptor_device_struct::bcdUSB
uint16_t bcdUSB
Definition: usbd_std.h:112
ENUN_EVENT_GET_PRODUCT_STRING_DESC
Definition: usbh_std.h:38
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:130
usbh_cfg_desc_parse
void usbh_cfg_desc_parse(usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], uint8_t *buf, uint16_t len)
parse the configuration descriptor
Definition: usbh_std.c:638
usb_descriptor_interface_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:144
usbh_device_desc_parse
void usbh_device_desc_parse(usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
parse the device descriptor
Definition: usbh_std.c:606
ENUN_EVENT_GET_CFG_DESC
Definition: usbh_std.h:35
USBREQ_GET_DESCRIPTOR
#define USBREQ_GET_DESCRIPTOR
Definition: usbd_std.h:48
ENUN_EVENT_GET_FULL_CFG_DESC
Definition: usbh_std.h:36
USB_CFGDESC
#define USB_CFGDESC
Definition: usb_std.h:76
enum_state_polling_fun
usbh_status_enum enum_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state
Definition: usbh_std.c:72
ENUN_EVENT_GET_MFC_STRING_DESC
Definition: usbh_std.h:37
USB_CFG_DESC_LEN
#define USB_CFG_DESC_LEN
Definition: usbd_std.h:25
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
usbh_host_struct::usr_cb
usbh_user_callback_struct * usr_cb
Definition: usbh_core.h:194
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:118
backup_state_struct::enum_backup_state
enum_state_enum enum_backup_state
Definition: usbh_core.h:182
local_buffer
uint8_t local_buffer[64]
Definition: usbh_std.c:18
UP_STATE
#define UP_STATE
Definition: usbh_core.h:46
GO_TO_UP_STATE_EVENT
#define GO_TO_UP_STATE_EVENT
Definition: usbh_core.h:47
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:27
USB_DEVDESC_SIZE
#define USB_DEVDESC_SIZE
Definition: usb_std.h:68
usbh_user_callback_struct::device_address_set
void(* device_address_set)(void)
Definition: usbh_core.h:160
usb_descriptor_interface_struct::bInterfaceClass
uint8_t bInterfaceClass
Definition: usbd_std.h:149
usbh_ctrl.h
header file for usbh_ctrl.c
usbh_channel_modify
uint8_t usbh_channel_modify(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel
Definition: usbh_hcs.c:64
ENUN_EVENT_GET_FULL_DEV_DESC
Definition: usbh_std.h:34
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
enum_state_handle
void(* enum_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_std.c:34
usb_descriptor_device_struct::bDeviceProtocol
uint8_t bDeviceProtocol
Definition: usbd_std.h:115
ENUM_SET_ADDR
Definition: usbh_core.h:83
usbh_interface_desc_parse
void usbh_interface_desc_parse(usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor
Definition: usbh_std.c:723
usb_descriptor_device_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:110
usb_descriptor_configuration_struct::bConfigurationValue
uint8_t bConfigurationValue
Definition: usbd_std.h:134
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
usbh_user_callback_struct::configuration_desc_available
void(* configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct *ep_desc)
Definition: usbh_core.h:162
usb_descriptor_device_struct::bcdDevice
uint16_t bcdDevice
Definition: usbd_std.h:119
usb_descriptor_device_struct::bDeviceSubClass
uint8_t bDeviceSubClass
Definition: usbd_std.h:114
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
state_table_struct
Definition: usbh_core.h:203
USB_DESCTYPE_STRING
#define USB_DESCTYPE_STRING
Definition: usbd_std.h:56
usbh_string_desc_parse
void usbh_string_desc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len)
parse the string descriptor
Definition: usbh_std.c:761
USBH_DEVICE_ADDRESS
#define USBH_DEVICE_ADDRESS
Definition: usbh_core.h:26
usb_descriptor_interface_struct::bInterfaceSubClass
uint8_t bInterfaceSubClass
Definition: usbd_std.h:150
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
scd_event_handle
usbh_status_enum scd_event_handle(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle
Definition: usbh_core.c:577
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:191
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:116
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:623
usb_descriptor_device_struct::bNumberConfigurations
uint8_t bNumberConfigurations
Definition: usbd_std.h:123
ENUM_SET_CONFIGURATION
Definition: usbh_core.h:90
usbh_device_struct::cfg_desc
usb_descriptor_configuration_struct cfg_desc
Definition: usbh_core.h:144
USB_DIR_IN
#define USB_DIR_IN
Definition: usb_std.h:28
usb_descriptor_interface_struct::bAlternateSetting
uint8_t bAlternateSetting
Definition: usbd_std.h:147
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:141
usbh_user_callback_struct::manufacturer_string
void(* manufacturer_string)(void *mfc_string)
Definition: usbh_core.h:167
usbh_next_desc_get
usb_descriptor_header_struct * usbh_next_desc_get(uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header
Definition: usbh_std.c:796
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:132
usb_core_handle_struct
Definition: usb_core.h:201
USBREQ_SET_ADDRESS
#define USBREQ_SET_ADDRESS
Definition: usbd_std.h:47
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usbd_std.h:163
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
USB_DEVDESC
#define USB_DEVDESC
Definition: usb_std.h:75
usb_descriptor_configuration_struct::bNumInterfaces
uint8_t bNumInterfaces
Definition: usbd_std.h:133
usb_descriptor_endpoint_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:159
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:693
USB_CFGDESC_SIZE
#define USB_CFGDESC_SIZE
Definition: usb_std.h:69
usbh_user_callback_struct::device_desc_available
void(* device_desc_available)(void *devDesc)
Definition: usbh_core.h:159
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:193
USBH_OK
Definition: usbh_core.h:109
ENUM_GET_FULL_CFG_DESC
Definition: usbh_core.h:86
usb_descriptor_configuration_struct::iConfiguration
uint8_t iConfiguration
Definition: usbd_std.h:135
ENUM_GET_FULL_DEV_DESC
Definition: usbh_core.h:84
usb_descriptor_device_struct::idVendor
uint16_t idVendor
Definition: usbd_std.h:117
USB_DESCTYPE_ENDPOINT
#define USB_DESCTYPE_ENDPOINT
Definition: usbd_std.h:58
NULL
#define NULL
Definition: usbd_std.h:20
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:115
ENUM_EVENT_SET_ADDR
Definition: usbh_std.h:33
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:24
usb_descriptor_interface_struct::bInterfaceNumber
uint8_t bInterfaceNumber
Definition: usbd_std.h:146
ENUM_GET_MFC_STRING_DESC
Definition: usbh_core.h:87
usb_descriptor_device_struct::iProduct
uint8_t iProduct
Definition: usbd_std.h:121
ENUM_GET_SERIALNUM_STRING_DESC
Definition: usbh_core.h:89
usbh_device_struct::dev_desc
usb_descriptor_device_struct dev_desc
Definition: usbh_core.h:143
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_device_struct::bDeviceClass
uint8_t bDeviceClass
Definition: usbd_std.h:113
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:129
usb_descriptor_device_struct::bMaxPacketSize0
uint8_t bMaxPacketSize0
Definition: usbd_std.h:116
usb_descriptor_configuration_struct::bMaxPower
uint8_t bMaxPower
Definition: usbd_std.h:137
usb_descriptor_device_struct::iManufacturer
uint8_t iManufacturer
Definition: usbd_std.h:120
usbh_enum_cfg_set
void usbh_enum_cfg_set(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx)
set configuration in usb host enumeration stage
Definition: usbh_std.c:583
usbh_enum_desc_get
void usbh_enum_desc_get(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t *buf, uint8_t req_type, uint16_t value_idx, uint16_t len)
get descriptor in usb host enumeration stage
Definition: usbh_std.c:526
USBH_BUSY
Definition: usbh_core.h:110
usb_descriptor_endpoint_struct::bInterval
uint8_t bInterval
Definition: usbd_std.h:164
usb_descriptor_device_struct::iSerialNumber
uint8_t iSerialNumber
Definition: usbd_std.h:122
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:135
usb_descriptor_configuration_struct
Definition: usbd_std.h:128
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
usbh_device_struct::itf_desc
usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]
Definition: usbh_core.h:145
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbd_int.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
usbd_int.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbd_int.h"
14 #include "usbd_std.h"
15
16 /* interrupt handlers */
17 static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev);
18 static uint32_t usbd_intf_inep (usb_core_handle_struct *pudev);
19 static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev);
20 static uint32_t usbd_intf_suspend (usb_core_handle_struct *pudev);
21 static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev);
22 static uint32_t usbd_intf_sof (usb_core_handle_struct *pudev);
23 static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev);
24 static uint32_t usbd_intf_reset (usb_core_handle_struct *pudev);
25 static uint32_t usbd_intf_enumfinish (usb_core_handle_struct *pudev);
26 static uint32_t usbd_intf_isoinincomplete (usb_core_handle_struct *pudev);
27 static uint32_t usbd_intf_isooutincomplete (usb_core_handle_struct *pudev);
28
29 static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, uint8_t ep_num);
30
31 #ifdef VBUS_SENSING_ENABLED
32
33 static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev);
34 static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev);
35
36 #endif /* VBUS_SENSING_ENABLED */
37
38 static usb_speed_enum USB_SPEED[4] = {
39 [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH,
40 [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_FULL,
41 [DSTAT_ENUMSPD_FS_PHY_48MHZ] = USB_SPEED_FULL,
42 [DSTAT_ENUMSPD_LS_PHY_6MHZ] = USB_SPEED_LOW
43 };
44
45 static const uint8_t EP0_MAXLEN[4] = {
46 [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64,
47 [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64,
48 [DSTAT_ENUMSPD_FS_PHY_48MHZ] = EP0MPL_64,
49 [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8
50 };
51
58 uint32_t usbd_isr (usb_core_handle_struct *pudev)
59 {
60 uint32_t retval = 0U;
61 uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN;
62
63 /* ensure the core is in device mode */
64 if (DEVICE_MODE == USB_CURRENT_MODE_GET()) {
65 int_status = gintf & ginten;
66
67 /* there are no interrupts, avoid spurious interrupt */
68 if (!int_status) {
69 return 0U;
70 }
71
72 /* OUT endpoints interrupts */
73 if (int_status & GINTF_OEPIF) {
74 retval |= usbd_intf_outep(pudev);
75 }
76
77 /* IN endpoints interrupts */
78 if (int_status & GINTF_IEPIF) {
79 retval |= usbd_intf_inep(pudev);
80 }
81
82 /* mode mismatch interrupt */
83 if (int_status & GINTF_MFIF) {
84 /* clear interrupt */
85 USB_GINTF = GINTF_MFIF;
86 }
87
88 /* early suspend interrupt */
89 if (int_status & GINTF_ESP) {
90 retval |= usbd_intf_earlysuspend(pudev);
91 }
92
93 /* suspend interrupt */
94 if (int_status & GINTF_SP) {
95 retval |= usbd_intf_suspend(pudev);
96 }
97
98 /* wakeup interrupt */
99 if (int_status & GINTF_WKUPIF) {
100 retval |= usbd_intf_resume(pudev);
101 }
102
103 /* start of frame interrupt */
104 if (int_status & GINTF_SOF) {
105 retval |= usbd_intf_sof(pudev);
106 }
107
108 /* reveive fifo not empty interrupt */
109 if (int_status & GINTF_RXFNEIF) {
110 retval |= usbd_intf_rxfifo(pudev);
111 }
112
113 /* USB reset interrupt */
114 if (int_status & GINTF_RST) {
115 retval |= usbd_intf_reset(pudev);
116 }
117
118 /* enumeration has been finished interrupt */
119 if (int_status & GINTF_ENUMF) {
120 retval |= usbd_intf_enumfinish(pudev);
121 }
122
123 /* incomplete synchronization in transfer interrupt*/
124 if (int_status & GINTF_ISOINCIF) {
125 retval |= usbd_intf_isoinincomplete(pudev);
126 }
127
128 /* incomplete synchronization out transfer interrupt*/
129 if (int_status & GINTF_ISOONCIF) {
130 retval |= usbd_intf_isooutincomplete(pudev);
131 }
132
133 #ifdef VBUS_SENSING_ENABLED
134
135 /* session request interrupt */
136 if (int_status & GINTF_SESIF) {
137 retval |= usbd_intf_sessionrequest(pudev);
138 }
139
140 /* OTG mode interrupt */
141 if (int_status & GINTF_OTGIF) {
142 retval |= usbd_intf_otg(pudev);
143 }
144 #endif /* VBUS_SENSING_ENABLED */
145 }
146
147 return retval;
148 }
149
156 static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev)
157 {
158 uint8_t endp_num = 0U;
159 uint32_t endp_intr = 0U;
160
161 __IO uint32_t out_endp_intr = 0U;
162
163 /* read in the device interrupt bits */
164 USB_DAOEP_INTR_READ(endp_intr);
165
166 while (endp_intr) {
167 if (endp_intr & 0x1U) {
168 USB_DOEP_INTR_READ(out_endp_intr, (uint16_t)endp_num);
169
170 /* transfer complete interrupt */
171 if (out_endp_intr & DOEPINTF_TF) {
172 USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF;
173
174 /* data receive is completed */
175 usbd_out_transaction(pudev, endp_num);
176 }
177
178 /* endpoint disable interrupt */
179 if (out_endp_intr & DOEPINTF_EPDIS) {
180 USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_EPDIS;
181 }
182
183 /* setup phase finished interrupt (just for control endpoints) */
184 if (out_endp_intr & DOEPINTF_STPF) {
185 /* setup phase is completed */
186 usbd_setup_transaction(pudev);
187
188 USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_STPF;
189 }
190
191 /* back to back setup packets received */
192 if (out_endp_intr & DOEPINTF_BTBSTP) {
193 USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_BTBSTP;
194 }
195 }
196
197 endp_num ++;
198 endp_intr >>= 1;
199 }
200
201 return 1U;
202 }
203
210 static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev)
211 {
212 uint8_t endp_num = 0U;
213 uint32_t endp_intr = 0U;
214
215 __IO uint32_t in_endp_intr = 0U;
216
217 /* get all in endpoints which have interrupts */
218 USB_DAIEP_INTR_READ(endp_intr);
219
220 while (endp_intr) {
221 if (endp_intr & 0x1U) {
222 USB_DIEP_INTR_READ(in_endp_intr, (uint16_t)endp_num);
223
224 if (in_endp_intr & DIEPINTF_TF) {
225 /* disable the fifo empty interrupt for the endpoint */
226 USB_DIEPFEINTEN &= ~(0x1U << endp_num);
227
228 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TF;
229
230 /* data transmittion is completed */
231 usbd_in_transaction(pudev, endp_num);
232 }
233
234 if (in_endp_intr & DIEPINTF_CITO) {
235 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_CITO;
236 }
237
238 if (in_endp_intr & DIEPINTF_IEPNE) {
239 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_IEPNE;
240 }
241
242 if (in_endp_intr & DIEPINTF_EPDIS) {
243 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_EPDIS;
244 }
245
246 if (in_endp_intr & DIEPINTF_TXFE) {
247 usbd_emptytxfifo_write(pudev, endp_num);
248 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TXFE;
249 }
250 }
251
252 endp_num ++;
253 endp_intr >>= 1;
254 }
255
256 return 1U;
257 }
258
265 static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev)
266 {
267 USB_GINTEN &= ~GINTEN_ESPIE;
268 USB_GINTF = GINTF_ESP;
269
270 return 1U;
271 }
272
279 static uint32_t usbd_intf_suspend(usb_core_handle_struct *pudev)
280 {
281 __IO uint8_t low_power = pudev->cfg.low_power;
282 __IO uint8_t suspend = (uint8_t)(USB_DSTAT & DSTAT_SPST);
283 __IO uint8_t is_configured = (pudev->dev.status == USB_STATUS_CONFIGURED)? 1U : 0U;
284
285 pudev->dev.prev_status = pudev->dev.status;
286 pudev->dev.status = USB_STATUS_SUSPENDED;
287
288 if (low_power && suspend && is_configured) {
289 /* switch-off the otg clocks */
290 USB_PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK;
291
292 /* enter DEEP_SLEEP mode with LDO in low power mode */
293 pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
294 }
295
296 /* clear interrupt */
297 USB_GINTF = GINTF_SP;
298
299 return 1U;
300 }
301
308 static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev)
309 {
310 pudev->dev.status = pudev->dev.prev_status;
311 pudev->dev.status = USB_STATUS_CONFIGURED;
312
313 /* clear interrupt */
314 USB_GINTF = GINTF_WKUPIF;
315
316 return 1U;
317 }
318
325 static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev)
326 {
327 if (NULL != usbd_int_fops) {
328 usbd_int_fops->SOF(pudev);
329 }
330
331 USB_GINTF = GINTF_SOF;
332
333 return 1U;
334 }
335
342 static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev)
343 {
344 usb_ep_struct *ep;
345 uint8_t data_pid = 0U, endp_num = 0U;
346 uint32_t bcount = 0U, packet_num = 0U;
347
348 /* get the status from the top of the fifo (must be read to a variable) */
349 __IO uint32_t rx_status = USB_GRSTATP;
350
351 /* disable the rx fifo non-empty interrupt */
352 USB_GINTEN &= ~GINTEN_RXFNEIE;
353
354 endp_num = (uint8_t)(rx_status & GRSTATRP_EPNUM);
355 bcount = (rx_status & GRSTATRP_BCOUNT) >> 4U;
356 data_pid = (uint8_t)((rx_status & GRSTATRP_DPID) >> 15U);
357
358 /* ensure no-DMA mode can work */
359 packet_num = USB_DOEPxLEN((uint16_t)endp_num) & DEPLEN_PCNT;
360 if ((1U == endp_num) && (0U == packet_num)) {
361 uint32_t devepctl = USB_DOEPxCTL((uint16_t)endp_num);
362
363 devepctl |= DEPCTL_SNAK;
364 devepctl &= ~DEPCTL_EPEN;
365 devepctl &= ~DEPCTL_EPD;
366
367 USB_DOEPxCTL((uint16_t)endp_num) = devepctl;
368 }
369
370 ep = &pudev->dev.out_ep[endp_num];
371
372 switch ((rx_status & GRSTATRP_RPCKST) >> 17U) {
373 case RXSTAT_GOUT_NAK:
374 if(0U != bcount) {
375 return 0U;
376 }
377 break;
378 case RXSTAT_DATA_UPDT:
379 if (bcount > 0U) {
380 usb_fifo_read(ep->xfer_buff, (uint16_t)bcount);
381 ep->xfer_buff += bcount;
382 ep->xfer_count += bcount;
383 }
384 break;
385 case RXSTAT_XFER_COMP:
386 if (0U != bcount) {
387 return 0U;
388 }
389 break;
390 case RXSTAT_SETUP_COMP:
391 if(0U != bcount) {
392 return 0U;
393 }
394 break;
395 case RXSTAT_SETUP_UPDT:
396 *(uint32_t *)0x5000081CU |= 0x00020000U;
397 if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) {
398 /* copy the setup packet received in fifo into the setup buffer in ram */
399 usb_fifo_read(pudev->dev.setup_packet, 8U);
400
401 ep->xfer_count += bcount;
402 }
403 break;
404 default:
405 break;
406 }
407
408 /* enable the Rx fifo non-empty interrupt */
409 USB_GINTEN |= GINTEN_RXFNEIE;
410
411 return 1U;
412 }
413
420 static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev)
421 {
422 uint8_t i = 0U;
423 usb_ep_struct *ep;
424
425 /* clear the remote wakeup signaling */
426 USB_DCTL &= ~DCTL_RWKUP;
427
428 /* flush the tx fifo */
429 usb_txfifo_flush(pudev, 0U);
430
431 for (i = 0U; i < pudev->cfg.dev_endp_num; i++) {
432 USB_DIEPxINTF((uint16_t)i) = 0xFFU;
433 USB_DOEPxINTF((uint16_t)i) = 0xFFU;
434 }
435
436 /* clear all pending device endpoint interrupts */
437 USB_DAEPINT = 0xFFFFFFFFU;
438
439 /* enable endpoint 0 interrupts */
440 USB_DAEPINTEN &= ~DAEPINTEN_OEPIE;
441 USB_DAEPINTEN &= ~DAEPINTEN_IEPIE;
442 USB_DAEPINTEN = (1U << 16) | 1U;
443
444 /* enable out endpoint interrupts */
445 USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN;
446
447 /* enable in endpoint interrupts */
448 USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN;
449
450 /* reset device address */
451 USB_DCFG &= ~DCFG_DAR;
452 USB_DCFG |= 0U << 4U;
453
454 /* configure endpoint 0 to receive setup packets */
455 usb_ep0_startout(pudev);
456
457 /* clear usb reset interrupt */
458 USB_GINTF = GINTF_RST;
459
460 /* open EP0 IN */
461 ep = &pudev->dev.in_ep[0];
462
463 USB_DIEPxCTL(0U) &= ~DEP0CTL_MPL;
464 USB_DIEPxCTL(0U) &= ~DEPCTL_EPTYPE;
465 USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM;
466
467 if (!(USB_DIEPxCTL(0U) & DEP0CTL_EPACT)) {
468 USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE;
469 USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U);
470 USB_DIEPxCTL(0U) |= DEP0CTL_EPACT;
471 }
472
473 ep->endp_mps = USB_MAX_EP0_SIZE;
474 ep->endp_type = USB_EPTYPE_CTRL;
475
476 /* open EP0 OUT */
477 ep = &pudev->dev.out_ep[0];
478
479 USB_DOEPxCTL(0U) &= ~DEP0CTL_MPL;
480 USB_DOEPxCTL(0U) &= ~DEPCTL_EPTYPE;
481
482 if (!(USB_DOEPxCTL(0U) & DEP0CTL_EPACT)) {
483 USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE;
484 USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U);
485 USB_DOEPxCTL(0U) |= DEP0CTL_EPACT;
486 }
487
488 ep->endp_mps = USB_MAX_EP0_SIZE;
489 ep->endp_type = USB_EPTYPE_CTRL;
490
491 pudev->dev.status = USB_STATUS_DEFAULT;
492
493 return 1U;
494 }
495
502 static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev)
503 {
504 uint8_t enum_speed = (uint8_t)((USB_DSTAT & DSTAT_ES) >> 1U);
505
506 /* set the max packet size of devie in endpoint based on the enumeration speed */
507 USB_DIEPxCTL(0U) |= EP0_MAXLEN[enum_speed];
508
509 /* clear global IN NAK */
510 USB_DCTL &= ~DCTL_CGINAK;
511 USB_DCTL |= DCTL_CGINAK;
512
513 /* set USB turn-around time based on device speed and PHY interface */
514 if (USB_SPEED_HIGH == USB_SPEED[enum_speed]) {
515 pudev->cfg.core_speed = USB_CORE_SPEED_HIGH;
516 pudev->cfg.max_packet_size = USBHS_MAX_PACKET_SIZE;
517
518 USB_GUSBCS &= ~GUSBCS_UTT;
519 USB_GUSBCS |= 0x09U << 10;
520 } else {
521 pudev->cfg.core_speed = USB_CORE_SPEED_FULL;
522 pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE;
523
524 USB_GUSBCS &= ~GUSBCS_UTT;
525 USB_GUSBCS |= 0x05U << 10;
526 }
527
528 /* clear interrupt */
529 USB_GINTF = GINTF_ENUMF;
530
531 return 1U;
532 }
533
540 static uint32_t usbd_intf_isoinincomplete(usb_core_handle_struct *pudev)
541 {
542 // USBD_DCD_INT_fops->IsoINIncomplete (pudev);
543
544 /* clear interrupt */
545 USB_GINTF = GINTF_ISOINCIF;
546
547 return 1U;
548 }
549
556 static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev)
557 {
558 // USBD_DCD_INT_fops->IsoOUTIncomplete (pudev);
559
560 /* clear interrupt */
561 USB_GINTF = GINTF_ISOONCIF;
562
563 return 1U;
564 }
565
573 static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num)
574 {
575 uint32_t len = 0U, word_len = 0U, fifo_empty_mask = 0U;
576 usb_ep_struct *ep;
577
578 ep = &pudev->dev.in_ep[ep_num];
579 len = ep->xfer_len - ep->xfer_count;
580
581 if (len > ep->endp_mps) {
582 len = ep->endp_mps;
583 }
584
585 word_len = (len + 3U) / 4U;
586
587 while (((USB_DIEPxTFSTAT((uint16_t)ep_num) & DIEPTFSTAT_IEPTFS) > word_len) &&
588 (ep->xfer_count < ep->xfer_len)) {
589 /* write the FIFO */
590 len = ep->xfer_len - ep->xfer_count;
591
592 if (len > ep->endp_mps) {
593 len = ep->endp_mps;
594 }
595
596 word_len = (len + 3U) / 4U;
597
598 usb_fifo_write (ep->xfer_buff, ep_num, (uint16_t)len);
599
600 ep->xfer_buff += len;
601 ep->xfer_count += len;
602
603 if(ep->xfer_len == ep->xfer_count) {
604 fifo_empty_mask = 0x1U << ep_num;
605 USB_DIEPFEINTEN &= ~fifo_empty_mask;
606 }
607 }
608
609 return 1U;
610 }
611
612 #ifdef VBUS_SENSING_ENABLED
613
620 static uint32_t usbd_intf_sessionrequest(usb_core_handle_struct *pudev)
621 {
622 pudev->dev.connection_status = 1U;
623
624 /* clear the interrupt bit */
625 USB_GINTF = GINTF_SESIF;
626
627 return 1;
628 }
629
636 static uint32_t usbd_intf_otg(usb_core_handle_struct *pudev)
637 {
638 if (USB_GOTGINTF & GOTGINTF_SESEND) {
639 pudev->dev.class_deinit(pudev, 0);
640 pudev->dev.connection_status = 0;
641 }
642
643 /* clear OTG interrupt */
644 USB_GOTGINTF |= GOTGINTF_SESEND;
645
646 return 1;
647 }
648
649 #endif /* VBUS_SENSING_ENABLED */
GINTEN_ESPIE
#define GINTEN_ESPIE
Definition: usb_regs.h:183
DOEPINTEN_STPFEN
#define DOEPINTEN_STPFEN
Definition: usb_regs.h:353
USB_DIEPxTFSTAT
#define USB_DIEPxTFSTAT(x)
Definition: usb_regs.h:90
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:211
DIEPINTF_IEPNE
#define DIEPINTF_IEPNE
Definition: usb_regs.h:407
usbd_int_fops
usbd_int_cb_struct * usbd_int_fops
GINTF_IEPIF
#define GINTF_IEPIF
Definition: usb_regs.h:149
usb_fifo_read
void * usb_fifo_read(uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint
Definition: usb_core.c:105
USBFS_MAX_PACKET_SIZE
#define USBFS_MAX_PACKET_SIZE
Definition: usb_defines.h:25
DIEPINTEN_CITOEN
#define DIEPINTEN_CITOEN
Definition: usb_regs.h:346
DSTAT_ENUMSPD_LS_PHY_6MHZ
#define DSTAT_ENUMSPD_LS_PHY_6MHZ
Definition: usb_defines.h:40
USB_DOEPINTEN
#define USB_DOEPINTEN
Definition: usb_regs.h:70
USB_DIEPxINTF
#define USB_DIEPxINTF(x)
Definition: usb_regs.h:86
DEPCTL_EPTYPE
#define DEPCTL_EPTYPE
Definition: usb_regs.h:398
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:159
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:109
DOEPINTF_BTBSTP
#define DOEPINTF_BTBSTP
Definition: usb_regs.h:414
DIEPINTEN_EPDISEN
#define DIEPINTEN_EPDISEN
Definition: usb_regs.h:347
DIEPTFSTAT_IEPTFS
#define DIEPTFSTAT_IEPTFS
Definition: usb_regs.h:437
RXSTAT_DATA_UPDT
#define RXSTAT_DATA_UPDT
Definition: usb_defines.h:59
DEPCTL_SNAK
#define DEPCTL_SNAK
Definition: usb_regs.h:393
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:72
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:66
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
GINTF_ISOINCIF
#define GINTF_ISOINCIF
Definition: usb_regs.h:147
USB_DIEPINTEN
#define USB_DIEPINTEN
Definition: usb_regs.h:69
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:69
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:387
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:39
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:42
usbd_in_transaction
uint8_t usbd_in_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data in stage processing
Definition: usbd_std.c:155
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:82
GINTF_SESIF
#define GINTF_SESIF
Definition: usb_regs.h:139
USB_SPEED_FULL
Definition: usb_defines.h:97
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:41
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:52
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:388
DOEPINTF_EPDIS
#define DOEPINTF_EPDIS
Definition: usb_regs.h:417
GRSTATRP_DPID
#define GRSTATRP_DPID
Definition: usb_regs.h:194
DCTL_RWKUP
#define DCTL_RWKUP
Definition: usb_regs.h:335
usb_speed_enum
usb_speed_enum
Definition: usb_defines.h:93
GRSTATRP_RPCKST
#define GRSTATRP_RPCKST
Definition: usb_regs.h:193
usbd_int_cb_struct::SOF
uint8_t(* SOF)(usbd_core_handle_struct *pudev)
Definition: usbd_int.h:24
USB_PWRCLKCTL
#define USB_PWRCLKCTL
Definition: usb_regs.h:92
DCFG_DAR
#define DCFG_DAR
Definition: usb_regs.h:322
DCTL_CGINAK
#define DCTL_CGINAK
Definition: usb_regs.h:330
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
USB_DAIEP_INTR_READ
#define USB_DAIEP_INTR_READ(x)
Definition: usb_regs.h:522
USB_SPEED_HIGH
Definition: usb_defines.h:98
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
DIEPINTF_CITO
#define DIEPINTF_CITO
Definition: usb_regs.h:409
DIEPINTF_EPDIS
#define DIEPINTF_EPDIS
Definition: usb_regs.h:410
USB_DOEPxINTF
#define USB_DOEPxINTF(x)
Definition: usb_regs.h:87
DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ
#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ
Definition: usb_defines.h:39
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:108
DOEPINTEN_TFEN
#define DOEPINTEN_TFEN
Definition: usb_regs.h:355
USB_SPEED_LOW
Definition: usb_defines.h:96
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
USB_CORE_SPEED_FULL
#define USB_CORE_SPEED_FULL
Definition: usb_defines.h:23
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:496
DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ
#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ
Definition: usb_defines.h:38
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:433
DSTAT_ENUMSPD_FS_PHY_48MHZ
#define DSTAT_ENUMSPD_FS_PHY_48MHZ
Definition: usb_defines.h:41
DSTAT_ES
#define DSTAT_ES
Definition: usb_regs.h:339
GINTF_OEPIF
#define GINTF_OEPIF
Definition: usb_regs.h:148
DOEPINTF_STPF
#define DOEPINTF_STPF
Definition: usb_regs.h:416
USB_DAEPINT
#define USB_DAEPINT
Definition: usb_regs.h:71
usb_ep_struct
Definition: usbd_core.h:102
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:68
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:21
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:63
USB_GRSTATP
#define USB_GRSTATP
Definition: usb_regs.h:44
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:68
GINTF_ESP
#define GINTF_ESP
Definition: usb_regs.h:155
usbd_setup_transaction
uint8_t usbd_setup_transaction(usbd_core_handle_struct *pudev)
USB setup stage processing.
Definition: usbd_std.c:80
GRSTATRP_EPNUM
#define GRSTATRP_EPNUM
Definition: usb_regs.h:197
EP0MPL_64
#define EP0MPL_64
Definition: usb_regs.h:472
USB_DOEP_INTR_READ
#define USB_DOEP_INTR_READ(x, EpID)
Definition: usb_regs.h:515
USB_CORE_SPEED_HIGH
#define USB_CORE_SPEED_HIGH
Definition: usb_defines.h:22
DIEPINTF_TF
#define DIEPINTF_TF
Definition: usb_regs.h:411
EP0MPL_8
#define EP0MPL_8
Definition: usb_regs.h:475
DOEPINTEN_EPDISEN
#define DOEPINTEN_EPDISEN
Definition: usb_regs.h:354
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
USB_GOTGINTF
#define USB_GOTGINTF
Definition: usb_regs.h:37
DSTAT_SPST
#define DSTAT_SPST
Definition: usb_regs.h:340
GINTF_OTGIF
#define GINTF_OTGIF
Definition: usb_regs.h:161
GINTF_SP
#define GINTF_SP
Definition: usb_regs.h:154
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:75
RXSTAT_SETUP_COMP
#define RXSTAT_SETUP_COMP
Definition: usb_defines.h:61
GUSBCS_UTT
#define GUSBCS_UTT
Definition: usb_regs.h:124
usb_core_handle_struct
Definition: usb_core.h:201
RXSTAT_XFER_COMP
#define RXSTAT_XFER_COMP
Definition: usb_defines.h:60
USB_DIEP_INTR_READ
#define USB_DIEP_INTR_READ(x, EpID)
Definition: usb_regs.h:532
DAEPINTEN_IEPIE
#define DAEPINTEN_IEPIE
Definition: usb_regs.h:363
USB_MAX_EP0_SIZE
#define USB_MAX_EP0_SIZE
Definition: usb_core.h:20
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:89
GINTF_WKUPIF
#define GINTF_WKUPIF
Definition: usb_regs.h:138
USB_DAOEP_INTR_READ
#define USB_DAOEP_INTR_READ(x)
Definition: usb_regs.h:506
USB_STATUS_SUSPENDED
#define USB_STATUS_SUSPENDED
Definition: usbd_core.h:24
usbd_out_transaction
uint8_t usbd_out_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data out stage processing
Definition: usbd_std.c:113
NULL
#define NULL
Definition: usbd_std.h:20
GOTGINTF_SESEND
#define GOTGINTF_SESEND
Definition: usb_regs.h:114
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:23
GRSTATRP_BCOUNT
#define GRSTATRP_BCOUNT
Definition: usb_regs.h:195
PWRCLKCTL_SUCLK
#define PWRCLKCTL_SUCLK
Definition: usb_regs.h:441
GINTEN_RXFNEIE
#define GINTEN_RXFNEIE
Definition: usb_regs.h:187
GINTF_RST
#define GINTF_RST
Definition: usb_regs.h:153
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:146
DIEPINTEN_TFEN
#define DIEPINTEN_TFEN
Definition: usb_regs.h:348
USBHS_MAX_PACKET_SIZE
#define USBHS_MAX_PACKET_SIZE
Definition: usb_defines.h:30
DAEPINTEN_OEPIE
#define DAEPINTEN_OEPIE
Definition: usb_regs.h:362
DIEPCTL_TXFNUM
#define DIEPCTL_TXFNUM
Definition: usb_regs.h:395
usbd_isr
void usbd_isr(void)
USB interrupt events service routine.
Definition: usbd_int.c:39
USB_DCFG
#define USB_DCFG
Definition: usb_regs.h:66
DPID_DATA0
#define DPID_DATA0
Definition: usb_defines.h:64
GINTF_ENUMF
#define GINTF_ENUMF
Definition: usb_regs.h:152
pmu_to_deepsleepmode
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode.
Definition: gd32f10x_pmu.c:98
RXSTAT_GOUT_NAK
#define RXSTAT_GOUT_NAK
Definition: usb_defines.h:58
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:160
PMU_LDO_LOWPOWER
#define PMU_LDO_LOWPOWER
Definition: gd32f10x_pmu.h:60
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:48
DEP0CTL_MPL
#define DEP0CTL_MPL
Definition: usb_regs.h:384
USB_DCTL
#define USB_DCTL
Definition: usb_regs.h:67
DEP0CTL_EPACT
#define DEP0CTL_EPACT
Definition: usb_regs.h:383
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
GINTF_MFIF
#define GINTF_MFIF
Definition: usb_regs.h:162
RXSTAT_SETUP_UPDT
#define RXSTAT_SETUP_UPDT
Definition: usb_defines.h:62
DOEPINTF_TF
#define DOEPINTF_TF
Definition: usb_regs.h:418
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:203
PWRCLKCTL_SHCLK
#define PWRCLKCTL_SHCLK
Definition: usb_regs.h:440
DIEPINTF_TXFE
#define DIEPINTF_TXFE
Definition: usb_regs.h:406
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_int.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usbh_int.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBH_INT_H
14 #define USBH_INT_H
15
16 #include "usb_core.h"
17
18 typedef struct
19 {
20 uint8_t (*sof) (usb_core_handle_struct *pudev);
21 uint8_t (*device_connected) (usb_core_handle_struct *pudev);
22 uint8_t (*device_disconnected) (usb_core_handle_struct *pudev);
23 }usbh_hcd_int_cb_struct;
24
25 extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops;
26
27 /* function declarations */
28 /* handle global host interrupt */
29 uint32_t usbh_isr (usb_core_handle_struct *pudev);
30
31 #endif /* USBH_INT_H */
usbh_hcd_int_fops
usbh_hcd_int_cb_struct * usbh_hcd_int_fops
Definition: usbh_core.c:34
usb_core.h
USB core driver header file.
usb_core_handle_struct
Definition: usb_core.h:201
usbh_isr
uint32_t usbh_isr(usb_core_handle_struct *pudev)
handle global host interrupt
Definition: usbh_int.c:34
usbh_hcd_int_cb_struct
Definition: usbh_int.h:18
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Source/usbd_pwr.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Source
usbd_pwr.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbd_pwr.h"
14
15 #ifdef USBD_LOWPWR_MODE_ENABLE
16 static void lowpower_mode_exit (void);
17 #endif /* USBD_LOWPWR_MODE_ENABLE */
18
19 __IO uint8_t g_ESOF_count = 0U;
20 __IO uint8_t g_suspend_enabled = 1U;
21 __IO uint8_t g_remote_wakeup_on = 0U;
22
23 #ifdef LPM_ENABLED
24 extern __IO uint32_t L1_resume;
25 #endif /* LPM_ENABLED */
26
33 void resume_mcu (void)
34 {
35 /* clear low_power mode bit in USBD_CTL */
36 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM));
37
38 #ifdef USBD_LOWPWR_MODE_ENABLE
39
40 /* restore normal operations */
41 lowpower_mode_exit();
42
43 #endif /* USBD_LOWPWR_MODE_ENABLE */
44
45 /* clear SETSPS bit */
46 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS));
47 }
48
49 #ifdef USBD_LOWPWR_MODE_ENABLE
50
57 static void lowpower_mode_exit (void)
58 {
59 /* restore system clock */
60
61 /* enable HSE */
62 rcu_osci_on(RCU_HXTAL);
63
64 /* wait till HSE is ready */
65 while(RESET == rcu_flag_get(RCU_FLAG_HXTALSTB));
66
67 /* enable PLL */
68 rcu_osci_on(RCU_PLL_CK);
69
70 /* wait till PLL is ready */
71 while(RESET == rcu_flag_get(RCU_FLAG_PLLSTB));
72
73 /* select PLL as system clock source */
74 rcu_system_clock_source_config(RCU_CKSYSSRC_PLL);
75
76 /* wait till PLL is used as system clock source */
77 while(0x08 != rcu_system_clock_source_get());
78
79 /* low power sleep on exit disabled */
80 system_lowpower_reset(SCB_LPM_DEEPSLEEP);
81 }
82
83 #endif /* USBD_LOWPWR_MODE_ENABLE */
84
91 void usbd_suspend (void)
92 {
93 /* set usb module to suspend and low-power mode */
94 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM);
95
96 #ifdef USBD_LOWPWR_MODE_ENABLE
97
98 /* check wakeup flag is set */
99 if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) {
100 /* enter DEEP_SLEEP mode with LDO in low power mode */
101 pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
102 } else {
103 /* clear wakeup interrupt flag */
104 USBD_REG_SET(USBD_INTF, CLR_WKUPIF);
105
106 /* clear set_suspend flag */
107 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS);
108 }
109
110 #endif /* USBD_LOWPWR_MODE_ENABLE */
111 }
112
119 void usbd_remote_wakeup_active(void)
120 {
121 resume_mcu();
122
123 #ifdef LPM_ENABLED
124 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ);
125
126 L1_resume = 1U;
127 #else
128 g_remote_wakeup_on = 1U;
129
130 g_ESOF_count = 15U;
131 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ);
132 #endif /* LPM_ENABLED */
133 }
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
usbd_pwr.h
USB device power management functions prototype.
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
g_remote_wakeup_on
__IO uint8_t g_remote_wakeup_on
Definition: usbd_pwr.c:21
RCU_FLAG_HXTALSTB
Definition: gd32f10x_rcu.h:506
resume_mcu
void resume_mcu(void)
USB wakeup first operation is to wakeup mcu.
Definition: usbd_pwr.c:33
g_ESOF_count
__IO uint8_t g_ESOF_count
Definition: usbd_pwr.c:19
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
rcu_flag_get
FlagStatus rcu_flag_get(rcu_flag_enum flag)
get the clock stabilization and periphral reset flags
Definition: gd32f10x_rcu.c:631
system_lowpower_reset
void system_lowpower_reset(uint8_t lowpower_mode)
reset the state of the low power mode
Definition: gd32f10x_misc.c:124
rcu_system_clock_source_get
uint32_t rcu_system_clock_source_get(void)
get the system clock source
Definition: gd32f10x_rcu.c:268
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
RCU_FLAG_PLLSTB
Definition: gd32f10x_rcu.h:507
CTL_LOWM
#define CTL_LOWM
Definition: usbd_regs.h:50
rcu_system_clock_source_config
void rcu_system_clock_source_config(uint32_t ck_sys)
configure the system clock source
Definition: gd32f10x_rcu.c:249
usbd_remote_wakeup_active
void usbd_remote_wakeup_active(void)
start to remote wakeup
Definition: usbd_pwr.c:119
usbd_suspend
void usbd_suspend(void)
set USB device to suspend mode
Definition: usbd_pwr.c:91
rcu_osci_on
void rcu_osci_on(rcu_osci_type_enum osci)
turn on the oscillator
Definition: gd32f10x_rcu.c:870
CTL_L1RSREQ
#define CTL_L1RSREQ
Definition: usbd_regs.h:47
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
CTL_RSREQ
#define CTL_RSREQ
Definition: usbd_regs.h:48
g_suspend_enabled
__IO uint8_t g_suspend_enabled
Definition: usbd_pwr.c:20
INTF_WKUPIF
#define INTF_WKUPIF
Definition: usbd_regs.h:58
CTL_SETSPS
#define CTL_SETSPS
Definition: usbd_regs.h:49
CLR_WKUPIF
#define CLR_WKUPIF
Definition: usbd_regs.h:141
pmu_to_deepsleepmode
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode.
Definition: gd32f10x_pmu.c:98
PMU_LDO_LOWPOWER
#define PMU_LDO_LOWPOWER
Definition: gd32f10x_pmu.h:60
SCB_LPM_DEEPSLEEP
#define SCB_LPM_DEEPSLEEP
Definition: gd32f10x_misc.h:42
RCU_CKSYSSRC_PLL
#define RCU_CKSYSSRC_PLL
Definition: gd32f10x_rcu.h:595
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_usart.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_usart.h"
14
21 void usart_deinit(uint32_t usart_periph)
22 {
23 switch(usart_periph){
24 case USART0:
25 rcu_periph_reset_enable(RCU_USART0RST);
26 rcu_periph_reset_disable(RCU_USART0RST);
27 break;
28 case USART1:
29 rcu_periph_reset_enable(RCU_USART1RST);
30 rcu_periph_reset_disable(RCU_USART1RST);
31 break;
32 case USART2:
33 rcu_periph_reset_enable(RCU_USART2RST);
34 rcu_periph_reset_disable(RCU_USART2RST);
35 break;
36 case UART3:
37 rcu_periph_reset_enable(RCU_UART3RST);
38 rcu_periph_reset_disable(RCU_UART3RST);
39 break;
40 case UART4:
41 rcu_periph_reset_enable(RCU_UART4RST);
42 rcu_periph_reset_disable(RCU_UART4RST);
43 break;
44 default:
45 break;
46 }
47 }
48
56 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
57 {
58 uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U;
59 switch(usart_periph){
60 case USART0:
61 /* get clock frequency */
62 uclk=rcu_clock_freq_get(CK_APB2);
63 break;
64 case USART1:
65 uclk=rcu_clock_freq_get(CK_APB1);
66 break;
67 case USART2:
68 uclk=rcu_clock_freq_get(CK_APB1);
69 break;
70 case UART3:
71 uclk=rcu_clock_freq_get(CK_APB1);
72 break;
73 case UART4:
74 uclk=rcu_clock_freq_get(CK_APB1);
75 break;
76 default:
77 break;
78 }
79 /* oversampling by 16, configure the value of USART_BAUD */
80 udiv = (uclk+baudval/2U)/baudval;
81 intdiv = udiv & 0xfff0U;
82 fradiv = udiv & 0xfU;
83 USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
84 }
85
96 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
97 {
98 /* clear USART_CTL0 PM,PCEN bits */
99 USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
100 /* configure USART parity mode */
101 USART_CTL0(usart_periph) |= paritycfg ;
102 }
103
113 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
114 {
115 /* clear USART_CTL0 WL bit */
116 USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
117 /* configure USART word length */
118 USART_CTL0(usart_periph) |= wlen;
119 }
120
132 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
133 {
134 /* clear USART_CTL1 STB bits */
135 USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
136 /* configure USART stop bits */
137 USART_CTL1(usart_periph) |= stblen;
138 }
145 void usart_enable(uint32_t usart_periph)
146 {
147 USART_CTL0(usart_periph) |= USART_CTL0_UEN;
148 }
149
156 void usart_disable(uint32_t usart_periph)
157 {
158 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
159 }
160
170 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
171 {
172 uint32_t ctl = 0U;
173
174 ctl = USART_CTL0(usart_periph);
175 ctl &= ~USART_CTL0_TEN;
176 ctl |= txconfig;
177 /* configure transfer mode */
178 USART_CTL0(usart_periph) = ctl;
179 }
180
190 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
191 {
192 uint32_t ctl = 0U;
193
194 ctl = USART_CTL0(usart_periph);
195 ctl &= ~USART_CTL0_REN;
196 ctl |= rxconfig;
197 /* configure transfer mode */
198 USART_CTL0(usart_periph) = ctl;
199 }
200
208 void usart_data_transmit(uint32_t usart_periph, uint32_t data)
209 {
210 USART_DATA(usart_periph) = USART_DATA_DATA & data;
211 }
212
219 uint16_t usart_data_receive(uint32_t usart_periph)
220 {
221 return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U));
222 }
223
231 void usart_address_config(uint32_t usart_periph, uint8_t addr)
232 {
233 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
234 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr);
235 }
236
243 void usart_mute_mode_enable(uint32_t usart_periph)
244 {
245 USART_CTL0(usart_periph) |= USART_CTL0_RWU;
246 }
247
254 void usart_mute_mode_disable(uint32_t usart_periph)
255 {
256 USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU);
257 }
258
268 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
269 {
270 USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
271 USART_CTL0(usart_periph) |= wmethod;
272 }
273
280 void usart_lin_mode_enable(uint32_t usart_periph)
281 {
282 USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
283 }
284
291 void usart_lin_mode_disable(uint32_t usart_periph)
292 {
293 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
294 }
295
305 void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen)
306 {
307 USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN);
308 USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen);
309 }
310
317 void usart_send_break(uint32_t usart_periph)
318 {
319 USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD;
320 }
321
328 void usart_halfduplex_enable(uint32_t usart_periph)
329 {
330 USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
331 }
332
339 void usart_halfduplex_disable(uint32_t usart_periph)
340 {
341 USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
342 }
343
350 void usart_synchronous_clock_enable(uint32_t usart_periph)
351 {
352 USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
353 }
354
361 void usart_synchronous_clock_disable(uint32_t usart_periph)
362 {
363 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
364 }
365
381 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
382 {
383 uint32_t ctl = 0U;
384
385 /* read USART_CTL1 register */
386 ctl = USART_CTL1(usart_periph);
387 /* set CK length, CK phase, CK polarity */
388 ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl);
389
390 USART_CTL1(usart_periph) |= ctl;
391 }
392
400 void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut)
401 {
402 USART_GP(usart_periph) &= ~(USART_GP_GUAT);
403 USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8));
404 }
405
412 void usart_smartcard_mode_enable(uint32_t usart_periph)
413 {
414 USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
415 }
416
423 void usart_smartcard_mode_disable(uint32_t usart_periph)
424 {
425 USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
426 }
427
434 void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
435 {
436 USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
437 }
438
445 void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
446 {
447 USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
448 }
449
456 void usart_irda_mode_enable(uint32_t usart_periph)
457 {
458 USART_CTL2(usart_periph) |= USART_CTL2_IREN;
459 }
460
467 void usart_irda_mode_disable(uint32_t usart_periph)
468 {
469 USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
470 }
471
479 void usart_prescaler_config(uint32_t usart_periph, uint8_t psc)
480 {
481 USART_GP(usart_periph) &= ~(USART_GP_PSC);
482 USART_GP(usart_periph) |= psc;
483 }
484
494 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
495 {
496 USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP);
497 USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
498 }
499
509 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
510 {
511 uint32_t ctl = 0U;
512
513 ctl = USART_CTL2(usart_periph);
514 ctl &= ~USART_CTL2_RTSEN;
515 ctl |= rtsconfig;
516 /* configure RTS */
517 USART_CTL2(usart_periph) = ctl;
518 }
519
529 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
530 {
531 uint32_t ctl = 0U;
532
533 ctl = USART_CTL2(usart_periph);
534 ctl &= ~USART_CTL2_CTSEN;
535 ctl |= ctsconfig;
536 /* configure CTS */
537 USART_CTL2(usart_periph) = ctl;
538 }
539
549 void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
550 {
551 uint32_t ctl = 0U;
552
553 ctl = USART_CTL2(usart_periph);
554 ctl &= ~USART_CTL2_DENR;
555 ctl |= dmacmd;
556 /* configure DMA reception */
557 USART_CTL2(usart_periph) = ctl;
558 }
559
569 void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
570 {
571 uint32_t ctl = 0U;
572
573 ctl = USART_CTL2(usart_periph);
574 ctl &= ~USART_CTL2_DENT;
575 ctl |= dmacmd;
576 /* configure DMA transmission */
577 USART_CTL2(usart_periph) = ctl;
578 }
579
598 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
599 {
600 if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
601 return SET;
602 }else{
603 return RESET;
604 }
605 }
606
619 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
620 {
621 USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag));
622 }
623
639 void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag)
640 {
641 USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag));
642 }
643
659 void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag)
660 {
661 USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag));
662 }
663
682 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
683 {
684 uint32_t intenable = 0U, flagstatus = 0U;
685 /* get the interrupt enable bit status */
686 intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
687 /* get the corresponding flag bit status */
688 flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
689
690 if(flagstatus && intenable){
691 return SET;
692 }else{
693 return RESET;
694 }
695 }
696
708 void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
709 {
710 USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag));
711 }
USART_CTL0_RWU
#define USART_CTL0_RWU
Definition: gd32f10x_usart.h:56
usart_interrupt_flag_get
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
get USART interrupt and flag status
Definition: gd32f10x_usart.c:682
usart_irda_mode_disable
void usart_irda_mode_disable(uint32_t usart_periph)
disable IrDA mode
Definition: gd32f10x_usart.c:467
usart_data_transmit
void usart_data_transmit(uint32_t usart_periph, uint32_t data)
USART transmit data function.
Definition: gd32f10x_usart.c:208
USART_CTL1_CPH
#define USART_CTL1_CPH
Definition: gd32f10x_usart.h:75
RCU_USART1RST
Definition: gd32f10x_rcu.h:459
usart_halfduplex_disable
void usart_halfduplex_disable(uint32_t usart_periph)
disable half duplex mode
Definition: gd32f10x_usart.c:339
USART0
#define USART0
Definition: gd32f10x_usart.h:23
usart_deinit
void usart_deinit(uint32_t usart_periph)
reset USART/UART
Definition: gd32f10x_usart.c:21
usart_synchronous_clock_enable
void usart_synchronous_clock_enable(uint32_t usart_periph)
enable CK pin in synchronous mode
Definition: gd32f10x_usart.c:350
usart_prescaler_config
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc)
configure the peripheral clock prescaler in USART IrDA low-power mode
Definition: gd32f10x_usart.c:479
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f10x_usart.h:86
UART3
#define UART3
Definition: gd32f10x_usart.h:21
usart_smartcard_mode_nack_disable
void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
disable NACK in smartcard mode
Definition: gd32f10x_usart.c:445
usart_receive_config
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
configure USART receiver
Definition: gd32f10x_usart.c:190
USART_CTL2_IRLP
#define USART_CTL2_IRLP
Definition: gd32f10x_usart.h:84
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f10x_usart.h:29
USART_CTL0_SBKCMD
#define USART_CTL0_SBKCMD
Definition: gd32f10x_usart.h:55
usart_smartcard_mode_nack_enable
void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
enable NACK in smartcard mode
Definition: gd32f10x_usart.c:434
USART_CTL2_DENT
#define USART_CTL2_DENT
Definition: gd32f10x_usart.h:89
USART_GP_GUAT
#define USART_GP_GUAT
Definition: gd32f10x_usart.h:96
USART_CTL0_WM
#define USART_CTL0_WM
Definition: gd32f10x_usart.h:66
usart_disable
void usart_disable(uint32_t usart_periph)
disable USART
Definition: gd32f10x_usart.c:156
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f10x_usart.h:83
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f10x_usart.h:77
usart_stop_bit_set
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
configure USART stop bit length
Definition: gd32f10x_usart.c:132
USART_CTL0_TEN
#define USART_CTL0_TEN
Definition: gd32f10x_usart.h:58
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f10x_usart.h:102
USART_BAUD
#define USART_BAUD(usartx)
Definition: gd32f10x_usart.h:28
usart_dma_transmit_config
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA transmission
Definition: gd32f10x_usart.c:569
USART_CTL2_CTSEN
#define USART_CTL2_CTSEN
Definition: gd32f10x_usart.h:91
USART_BAUD_FRADIV
#define USART_BAUD_FRADIV
Definition: gd32f10x_usart.h:51
USART_CTL1_ADDR
#define USART_CTL1_ADDR
Definition: gd32f10x_usart.h:71
usart_lin_mode_enable
void usart_lin_mode_enable(uint32_t usart_periph)
enable LIN mode
Definition: gd32f10x_usart.c:280
USART_REG_VAL2
#define USART_REG_VAL2(usartx, offset)
Definition: gd32f10x_usart.h:105
USART_BAUD_INTDIV
#define USART_BAUD_INTDIV
Definition: gd32f10x_usart.h:52
USART1
#define USART1
Definition: gd32f10x_usart.h:19
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f10x_usart.h:106
usart_dma_receive_config
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA reception
Definition: gd32f10x_usart.c:549
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f10x_usart.h:30
usart_transmit_config
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
configure USART transmitter
Definition: gd32f10x_usart.c:170
USART_CTL2_RTSEN
#define USART_CTL2_RTSEN
Definition: gd32f10x_usart.h:90
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
USART_GP_PSC
#define USART_GP_PSC
Definition: gd32f10x_usart.h:95
usart_interrupt_disable
void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag)
disable USART interrupt
Definition: gd32f10x_usart.c:659
usart_lin_break_dection_length_config
void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen)
configure lin break frame length
Definition: gd32f10x_usart.c:305
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f10x_usart.h:87
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f10x_usart.h:85
usart_word_length_set
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
configure USART word length
Definition: gd32f10x_usart.c:113
usart_irda_lowpower_config
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
configure IrDA low-power
Definition: gd32f10x_usart.c:494
USART_CTL1_CLEN
#define USART_CTL1_CLEN
Definition: gd32f10x_usart.h:74
usart_hardware_flow_rts_config
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
configure hardware flow control RTS
Definition: gd32f10x_usart.c:509
usart_data_receive
uint16_t usart_data_receive(uint32_t usart_periph)
USART receive data function.
Definition: gd32f10x_usart.c:219
usart_mute_mode_wakeup_config
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
configure wakeup method in mute mode
Definition: gd32f10x_usart.c:268
usart_hardware_flow_cts_config
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
configure hardware flow control CTS
Definition: gd32f10x_usart.c:529
USART_DATA
#define USART_DATA(usartx)
Definition: gd32f10x_usart.h:27
usart_smartcard_mode_enable
void usart_smartcard_mode_enable(uint32_t usart_periph)
enable smartcard mode
Definition: gd32f10x_usart.c:412
usart_send_break
void usart_send_break(uint32_t usart_periph)
send break frame
Definition: gd32f10x_usart.c:317
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f10x_usart.h:68
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f10x_usart.h:101
USART_CTL0_REN
#define USART_CTL0_REN
Definition: gd32f10x_usart.h:57
usart_interrupt_flag_clear
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
clear USART interrupt flag in STAT register
Definition: gd32f10x_usart.c:708
USART_CTL1_LBLEN
#define USART_CTL1_LBLEN
Definition: gd32f10x_usart.h:72
CK_APB2
Definition: gd32f10x_rcu.h:587
USART_CTL1_CPL
#define USART_CTL1_CPL
Definition: gd32f10x_usart.h:76
usart_interrupt_enable
void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag)
enable USART interrupt
Definition: gd32f10x_usart.c:639
usart_synchronous_clock_config
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
configure USART synchronous mode parameters
Definition: gd32f10x_usart.c:381
usart_flag_get
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
get flag in STAT register
Definition: gd32f10x_usart.c:598
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
USART_DATA_DATA
#define USART_DATA_DATA
Definition: gd32f10x_usart.h:48
usart_smartcard_mode_disable
void usart_smartcard_mode_disable(uint32_t usart_periph)
disable smartcard mode
Definition: gd32f10x_usart.c:423
usart_synchronous_clock_disable
void usart_synchronous_clock_disable(uint32_t usart_periph)
disable CK pin in synchronous mode
Definition: gd32f10x_usart.c:361
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
usart_irda_mode_enable
void usart_irda_mode_enable(uint32_t usart_periph)
enable IrDA mode
Definition: gd32f10x_usart.c:456
usart_enable
void usart_enable(uint32_t usart_periph)
enable USART
Definition: gd32f10x_usart.c:145
usart_guard_time_config
void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut)
configure guard time value in smartcard mode
Definition: gd32f10x_usart.c:400
gd32f10x_usart.h
definitions for the USART
usart_address_config
void usart_address_config(uint32_t usart_periph, uint8_t addr)
configure the address of the USART in wake up by address match mode
Definition: gd32f10x_usart.c:231
RCU_USART0RST
Definition: gd32f10x_rcu.h:490
usart_flag_enum
usart_flag_enum
Definition: gd32f10x_usart.h:115
RCU_USART2RST
Definition: gd32f10x_rcu.h:460
RCU_UART4RST
Definition: gd32f10x_rcu.h:462
USART_CTL2_DENR
#define USART_CTL2_DENR
Definition: gd32f10x_usart.h:88
USART_CTL0_PM
#define USART_CTL0_PM
Definition: gd32f10x_usart.h:64
usart_mute_mode_enable
void usart_mute_mode_enable(uint32_t usart_periph)
receiver in mute mode
Definition: gd32f10x_usart.c:243
usart_baudrate_set
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
configure USART baud rate value
Definition: gd32f10x_usart.c:56
usart_halfduplex_enable
void usart_halfduplex_enable(uint32_t usart_periph)
enable half duplex mode
Definition: gd32f10x_usart.c:328
usart_flag_clear
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
clear flag in STAT register
Definition: gd32f10x_usart.c:619
usart_lin_mode_disable
void usart_lin_mode_disable(uint32_t usart_periph)
disable LIN mode
Definition: gd32f10x_usart.c:291
CK_APB1
Definition: gd32f10x_rcu.h:586
USART2
#define USART2
Definition: gd32f10x_usart.h:20
USART_GP
#define USART_GP(usartx)
Definition: gd32f10x_usart.h:32
UART4
#define UART4
Definition: gd32f10x_usart.h:22
usart_mute_mode_disable
void usart_mute_mode_disable(uint32_t usart_periph)
receiver in active mode
Definition: gd32f10x_usart.c:254
USART_CTL1_STB
#define USART_CTL1_STB
Definition: gd32f10x_usart.h:78
USART_CTL0_WL
#define USART_CTL0_WL
Definition: gd32f10x_usart.h:67
RCU_UART3RST
Definition: gd32f10x_rcu.h:461
usart_parity_config
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
configure USART parity
Definition: gd32f10x_usart.c:96
USART_CTL0_PCEN
#define USART_CTL0_PCEN
Definition: gd32f10x_usart.h:65
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f10x_usart.h:79
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f10x_usart.h:31
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_sdio.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_sdio.h"
14
15 #define DEFAULT_RESET_VALUE 0x00000000U
16
23 void sdio_deinit(void)
24 {
25 SDIO_PWRCTL = DEFAULT_RESET_VALUE;
26 SDIO_CLKCTL = DEFAULT_RESET_VALUE;
27 SDIO_CMDAGMT = DEFAULT_RESET_VALUE;
28 SDIO_CMDCTL = DEFAULT_RESET_VALUE;
29 SDIO_DATATO = DEFAULT_RESET_VALUE;
30 SDIO_DATALEN = DEFAULT_RESET_VALUE;
31 SDIO_DATACTL = DEFAULT_RESET_VALUE;
32 SDIO_INTC = DEFAULT_RESET_VALUE;
33 SDIO_INTEN = DEFAULT_RESET_VALUE;
34 }
35
51 void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division)
52 {
53 uint32_t clock_config = 0U;
54 clock_config = SDIO_CLKCTL;
55 /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */
56 clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV);
57
58 /* configure the SDIO_CLKCTL according to the parameters */
59 clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division);
60 SDIO_CLKCTL = clock_config;
61 }
62
69 void sdio_hardware_clock_enable(void)
70 {
71 SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN;
72 }
73
80 void sdio_hardware_clock_disable(void)
81 {
82 SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN;
83 }
84
94 void sdio_bus_mode_set(uint32_t bus_mode)
95 {
96 /* reset the SDIO card bus mode bits and set according to bus_mode */
97 SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE;
98 SDIO_CLKCTL |= bus_mode;
99 }
100
109 void sdio_power_state_set(uint32_t power_state)
110 {
111 SDIO_PWRCTL = power_state;
112 }
113
122 uint32_t sdio_power_state_get(void)
123 {
124 return SDIO_PWRCTL;
125 }
126
133 void sdio_clock_enable(void)
134 {
135 SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN;
136 }
137
144 void sdio_clock_disable(void)
145 {
146 SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN;
147 }
148
160 void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type)
161 {
162 uint32_t cmd_config = 0U;
163 /* reset the command index, command argument and response type */
164 SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT;
165 SDIO_CMDAGMT = cmd_argument;
166 cmd_config = SDIO_CMDCTL;
167 cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP);
168 /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */
169 cmd_config |= (cmd_index | response_type);
170 SDIO_CMDCTL = cmd_config;
171 }
172
182 void sdio_wait_type_set(uint32_t wait_type)
183 {
184 /* reset INTWAIT and WAITDEND */
185 SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND);
186 /* set the wait type according to wait_type */
187 SDIO_CMDCTL |= wait_type;
188 }
189
196 void sdio_csm_enable(void)
197 {
198 SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN;
199 }
200
207 void sdio_csm_disable(void)
208 {
209 SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN;
210 }
211
218 uint8_t sdio_command_index_get(void)
219 {
220 return (uint8_t)SDIO_RSPCMDIDX;
221 }
222
233 uint32_t sdio_response_get(uint32_t responsex)
234 {
235 uint32_t resp_content = 0U;
236 switch(responsex){
237 case SDIO_RESPONSE0:
238 resp_content = SDIO_RESP0;
239 break;
240 case SDIO_RESPONSE1:
241 resp_content = SDIO_RESP1;
242 break;
243 case SDIO_RESPONSE2:
244 resp_content = SDIO_RESP2;
245 break;
246 case SDIO_RESPONSE3:
247 resp_content = SDIO_RESP3;
248 break;
249 default:
250 break;
251 }
252 return resp_content;
253 }
254
278 void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize)
279 {
280 /* reset data timeout, data length and data block size */
281 SDIO_DATATO &= ~SDIO_DATATO_DATATO;
282 SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN;
283 SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ;
284 /* configure the related parameters of data */
285 SDIO_DATATO = data_timeout;
286 SDIO_DATALEN = data_length;
287 SDIO_DATACTL |= data_blocksize;
288 }
289
301 void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction)
302 {
303 uint32_t data_trans = 0U;
304 /* reset the data transfer mode, transfer direction and set according to the parameters */
305 data_trans = SDIO_DATACTL;
306 data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR);
307 data_trans |= (transfer_mode | transfer_direction);
308 SDIO_DATACTL = data_trans;
309 }
310
317 void sdio_dsm_enable(void)
318 {
319 SDIO_DATACTL |= SDIO_DATACTL_DATAEN;
320 }
321
328 void sdio_dsm_disable(void)
329 {
330 SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN;
331 }
332
339 void sdio_data_write(uint32_t data)
340 {
341 SDIO_FIFO = data;
342 }
343
350 uint32_t sdio_data_read(void)
351 {
352 return SDIO_FIFO;
353 }
354
361 uint32_t sdio_data_counter_get(void)
362 {
363 return SDIO_DATACNT;
364 }
365
372 uint32_t sdio_fifo_counter_get(void)
373 {
374 return SDIO_FIFOCNT;
375 }
376
383 void sdio_dma_enable(void)
384 {
385 SDIO_DATACTL |= SDIO_DATACTL_DMAEN;
386 }
387
394 void sdio_dma_disable(void)
395 {
396 SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN;
397 }
398
429 FlagStatus sdio_flag_get(uint32_t flag)
430 {
431 FlagStatus temp_flag = RESET;
432 if(RESET != (SDIO_STAT & flag)){
433 temp_flag = SET;
434 }
435 return temp_flag;
436 }
437
457 void sdio_flag_clear(uint32_t flag)
458 {
459 SDIO_INTC = flag;
460 }
461
492 void sdio_interrupt_enable(uint32_t int_flag)
493 {
494 SDIO_INTEN |= int_flag;
495 }
496
527 void sdio_interrupt_disable(uint32_t int_flag)
528 {
529 SDIO_INTEN &= ~int_flag;
530 }
531
562 FlagStatus sdio_interrupt_flag_get(uint32_t int_flag)
563 {
564 uint32_t state = 0U;
565 state = SDIO_STAT;
566 if(state & int_flag){
567 state = SDIO_INTEN;
568 /* check whether the corresponding bit in SDIO_INTEN is set or not */
569 if(state & int_flag){
570 return SET;
571 }
572 }
573 return RESET;
574 }
575
595 void sdio_interrupt_flag_clear(uint32_t int_flag)
596 {
597 SDIO_INTC = int_flag;
598 }
599
606 void sdio_readwait_enable(void)
607 {
608 SDIO_DATACTL |= SDIO_DATACTL_RWEN;
609 }
610
617 void sdio_readwait_disable(void)
618 {
619 SDIO_DATACTL &= ~SDIO_DATACTL_RWEN;
620 }
621
628 void sdio_stop_readwait_enable(void)
629 {
630 SDIO_DATACTL |= SDIO_DATACTL_RWSTOP;
631 }
632
639 void sdio_stop_readwait_disable(void)
640 {
641 SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP;
642 }
643
652 void sdio_readwait_type_set(uint32_t readwait_type)
653 {
654 if(SDIO_READWAITTYPE_CLK == readwait_type){
655 SDIO_DATACTL |= SDIO_DATACTL_RWTYPE;
656 }else{
657 SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE;
658 }
659 }
660
667 void sdio_operation_enable(void)
668 {
669 SDIO_DATACTL |= SDIO_DATACTL_IOEN;
670 }
671
678 void sdio_operation_disable(void)
679 {
680 SDIO_DATACTL &= ~SDIO_DATACTL_IOEN;
681 }
682
689 void sdio_suspend_enable(void)
690 {
691 SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND;
692 }
693
700 void sdio_suspend_disable(void)
701 {
702 SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND;
703 }
704
711 void sdio_ceata_command_enable(void)
712 {
713 SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN;
714 }
715
722 void sdio_ceata_command_disable(void)
723 {
724 SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN;
725 }
726
733 void sdio_ceata_interrupt_enable(void)
734 {
735 SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN;
736 }
737
744 void sdio_ceata_interrupt_disable(void)
745 {
746 SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN;
747 }
748
755 void sdio_ceata_command_completion_enable(void)
756 {
757 SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC;
758 }
759
766 void sdio_ceata_command_completion_disable(void)
767 {
768 SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC;
769 }
sdio_dma_enable
void sdio_dma_enable(void)
enable the DMA request for SDIO
Definition: gd32f10x_sdio.c:383
SDIO_DATACTL_RWSTOP
#define SDIO_DATACTL_RWSTOP
Definition: gd32f10x_sdio.h:81
sdio_ceata_command_completion_disable
void sdio_ceata_command_completion_disable(void)
disable the CE-ATA command completion signal(CE-ATA only)
Definition: gd32f10x_sdio.c:766
SDIO_CLKCTL
#define SDIO_CLKCTL
Definition: gd32f10x_sdio.h:23
sdio_data_transfer_config
void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction)
configure the data transfer mode and direction
Definition: gd32f10x_sdio.c:301
sdio_readwait_type_set
void sdio_readwait_type_set(uint32_t readwait_type)
set the read wait type(SD I/O only)
Definition: gd32f10x_sdio.c:652
sdio_dsm_disable
void sdio_dsm_disable(void)
disable the DSM(data state machine)
Definition: gd32f10x_sdio.c:328
sdio_dsm_enable
void sdio_dsm_enable(void)
enable the DSM(data state machine) for data transfer
Definition: gd32f10x_sdio.c:317
sdio_command_index_get
uint8_t sdio_command_index_get(void)
get the last response command index
Definition: gd32f10x_sdio.c:218
sdio_data_read
uint32_t sdio_data_read(void)
read data(one word) from the receive FIFO
Definition: gd32f10x_sdio.c:350
SDIO_DATATO
#define SDIO_DATATO
Definition: gd32f10x_sdio.h:31
sdio_hardware_clock_disable
void sdio_hardware_clock_disable(void)
disable hardware clock control
Definition: gd32f10x_sdio.c:80
sdio_data_config
void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize)
configure the data timeout, data length and data block size
Definition: gd32f10x_sdio.c:278
sdio_ceata_interrupt_enable
void sdio_ceata_interrupt_enable(void)
enable the CE-ATA interrupt(CE-ATA only)
Definition: gd32f10x_sdio.c:733
SDIO_CMDAGMT
#define SDIO_CMDAGMT
Definition: gd32f10x_sdio.h:24
sdio_data_counter_get
uint32_t sdio_data_counter_get(void)
get the number of remaining data bytes to be transferred to card
Definition: gd32f10x_sdio.c:361
SDIO_RESP0
#define SDIO_RESP0
Definition: gd32f10x_sdio.h:27
SDIO_PWRCTL
#define SDIO_PWRCTL
Definition: gd32f10x_sdio.h:22
sdio_fifo_counter_get
uint32_t sdio_fifo_counter_get(void)
get the number of words remaining to be written or read from FIFO
Definition: gd32f10x_sdio.c:372
sdio_deinit
void sdio_deinit(void)
deinitialize the SDIO
Definition: gd32f10x_sdio.c:23
SDIO_RESPONSE1
#define SDIO_RESPONSE1
Definition: gd32f10x_sdio.h:269
sdio_suspend_disable
void sdio_suspend_disable(void)
disable the SD I/O suspend operation(SD I/O only)
Definition: gd32f10x_sdio.c:700
sdio_stop_readwait_enable
void sdio_stop_readwait_enable(void)
enable the function that stop the read wait process(SD I/O only)
Definition: gd32f10x_sdio.c:628
SDIO_CLKCTL_HWCLKEN
#define SDIO_CLKCTL_HWCLKEN
Definition: gd32f10x_sdio.h:52
sdio_ceata_command_disable
void sdio_ceata_command_disable(void)
disable the CE-ATA command(CE-ATA only)
Definition: gd32f10x_sdio.c:722
SDIO_CMDCTL_CSMEN
#define SDIO_CMDCTL_CSMEN
Definition: gd32f10x_sdio.h:62
sdio_bus_mode_set
void sdio_bus_mode_set(uint32_t bus_mode)
set different SDIO card bus mode
Definition: gd32f10x_sdio.c:94
sdio_interrupt_enable
void sdio_interrupt_enable(uint32_t int_flag)
enable the SDIO interrupt
Definition: gd32f10x_sdio.c:492
SDIO_RESP1
#define SDIO_RESP1
Definition: gd32f10x_sdio.h:28
SDIO_CMDCTL_ATAEN
#define SDIO_CMDCTL_ATAEN
Definition: gd32f10x_sdio.h:66
sdio_ceata_command_enable
void sdio_ceata_command_enable(void)
enable the CE-ATA command(CE-ATA only)
Definition: gd32f10x_sdio.c:711
SDIO_CMDCTL_SUSPEND
#define SDIO_CMDCTL_SUSPEND
Definition: gd32f10x_sdio.h:63
SDIO_CLKCTL_CLKEDGE
#define SDIO_CLKCTL_CLKEDGE
Definition: gd32f10x_sdio.h:51
sdio_data_write
void sdio_data_write(uint32_t data)
write data(one word) to the transmit FIFO
Definition: gd32f10x_sdio.c:339
sdio_wait_type_set
void sdio_wait_type_set(uint32_t wait_type)
set the command state machine wait type
Definition: gd32f10x_sdio.c:182
SDIO_CMDCTL_CMDIDX
#define SDIO_CMDCTL_CMDIDX
Definition: gd32f10x_sdio.h:58
sdio_command_response_config
void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type)
configure the command and response
Definition: gd32f10x_sdio.c:160
sdio_ceata_interrupt_disable
void sdio_ceata_interrupt_disable(void)
disable the CE-ATA interrupt(CE-ATA only)
Definition: gd32f10x_sdio.c:744
SDIO_CMDCTL_ENCMDC
#define SDIO_CMDCTL_ENCMDC
Definition: gd32f10x_sdio.h:64
SDIO_READWAITTYPE_CLK
#define SDIO_READWAITTYPE_CLK
Definition: gd32f10x_sdio.h:301
sdio_interrupt_disable
void sdio_interrupt_disable(uint32_t int_flag)
disable the SDIO interrupt
Definition: gd32f10x_sdio.c:527
SDIO_CLKCTL_CLKBYP
#define SDIO_CLKCTL_CLKBYP
Definition: gd32f10x_sdio.h:49
SDIO_RSPCMDIDX
#define SDIO_RSPCMDIDX
Definition: gd32f10x_sdio.h:26
sdio_readwait_enable
void sdio_readwait_enable(void)
enable the read wait mode(SD I/O only)
Definition: gd32f10x_sdio.c:606
SDIO_FIFOCNT
#define SDIO_FIFOCNT
Definition: gd32f10x_sdio.h:38
SDIO_DATACTL_IOEN
#define SDIO_DATACTL_IOEN
Definition: gd32f10x_sdio.h:83
SDIO_FIFO
#define SDIO_FIFO
Definition: gd32f10x_sdio.h:39
sdio_readwait_disable
void sdio_readwait_disable(void)
disable the read wait mode(SD I/O only)
Definition: gd32f10x_sdio.c:617
SDIO_CMDCTL_INTWAIT
#define SDIO_CMDCTL_INTWAIT
Definition: gd32f10x_sdio.h:60
SDIO_RESPONSE2
#define SDIO_RESPONSE2
Definition: gd32f10x_sdio.h:270
sdio_hardware_clock_enable
void sdio_hardware_clock_enable(void)
enable hardware clock control
Definition: gd32f10x_sdio.c:69
SDIO_RESPONSE3
#define SDIO_RESPONSE3
Definition: gd32f10x_sdio.h:271
SDIO_DATALEN_DATALEN
#define SDIO_DATALEN_DATALEN
Definition: gd32f10x_sdio.h:72
SDIO_CMDCTL_NINTEN
#define SDIO_CMDCTL_NINTEN
Definition: gd32f10x_sdio.h:65
SDIO_CLKCTL_BUSMODE
#define SDIO_CLKCTL_BUSMODE
Definition: gd32f10x_sdio.h:50
SDIO_CMDCTL_CMDRESP
#define SDIO_CMDCTL_CMDRESP
Definition: gd32f10x_sdio.h:59
sdio_response_get
uint32_t sdio_response_get(uint32_t responsex)
get the response for the last received command
Definition: gd32f10x_sdio.c:233
SDIO_DATALEN
#define SDIO_DATALEN
Definition: gd32f10x_sdio.h:32
sdio_interrupt_flag_clear
void sdio_interrupt_flag_clear(uint32_t int_flag)
clear the interrupt pending flags of SDIO
Definition: gd32f10x_sdio.c:595
sdio_suspend_enable
void sdio_suspend_enable(void)
enable the SD I/O suspend operation(SD I/O only)
Definition: gd32f10x_sdio.c:689
SDIO_CLKCTL_CLKPWRSAV
#define SDIO_CLKCTL_CLKPWRSAV
Definition: gd32f10x_sdio.h:48
sdio_power_state_get
uint32_t sdio_power_state_get(void)
get the SDIO power state
Definition: gd32f10x_sdio.c:122
SDIO_DATACTL
#define SDIO_DATACTL
Definition: gd32f10x_sdio.h:33
SDIO_RESP2
#define SDIO_RESP2
Definition: gd32f10x_sdio.h:29
SDIO_DATACNT
#define SDIO_DATACNT
Definition: gd32f10x_sdio.h:34
sdio_clock_config
void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division)
configure the SDIO clock
Definition: gd32f10x_sdio.c:51
gd32f10x_sdio.h
definitions for the SDIO
SDIO_DATACTL_BLKSZ
#define SDIO_DATACTL_BLKSZ
Definition: gd32f10x_sdio.h:79
sdio_operation_disable
void sdio_operation_disable(void)
disable the SD I/O mode specific operation(SD I/O only)
Definition: gd32f10x_sdio.c:678
SDIO_STAT
#define SDIO_STAT
Definition: gd32f10x_sdio.h:35
SDIO_CLKCTL_DIV
#define SDIO_CLKCTL_DIV
Definition: gd32f10x_sdio.h:46
SDIO_CMDCTL
#define SDIO_CMDCTL
Definition: gd32f10x_sdio.h:25
SDIO_DATACTL_RWTYPE
#define SDIO_DATACTL_RWTYPE
Definition: gd32f10x_sdio.h:82
sdio_dma_disable
void sdio_dma_disable(void)
disable the DMA request for SDIO
Definition: gd32f10x_sdio.c:394
SDIO_INTEN
#define SDIO_INTEN
Definition: gd32f10x_sdio.h:37
SDIO_DATACTL_TRANSMOD
#define SDIO_DATACTL_TRANSMOD
Definition: gd32f10x_sdio.h:77
sdio_stop_readwait_disable
void sdio_stop_readwait_disable(void)
disable the function that stop the read wait process(SD I/O only)
Definition: gd32f10x_sdio.c:639
sdio_power_state_set
void sdio_power_state_set(uint32_t power_state)
set the SDIO power state
Definition: gd32f10x_sdio.c:109
sdio_flag_get
FlagStatus sdio_flag_get(uint32_t flag)
get the flags state of SDIO
Definition: gd32f10x_sdio.c:429
SDIO_DATACTL_DATADIR
#define SDIO_DATACTL_DATADIR
Definition: gd32f10x_sdio.h:76
SDIO_CMDCTL_WAITDEND
#define SDIO_CMDCTL_WAITDEND
Definition: gd32f10x_sdio.h:61
SDIO_RESP3
#define SDIO_RESP3
Definition: gd32f10x_sdio.h:30
SDIO_DATACTL_DMAEN
#define SDIO_DATACTL_DMAEN
Definition: gd32f10x_sdio.h:78
SDIO_CLKCTL_CLKEN
#define SDIO_CLKCTL_CLKEN
Definition: gd32f10x_sdio.h:47
sdio_clock_enable
void sdio_clock_enable(void)
enable SDIO_CLK clock output
Definition: gd32f10x_sdio.c:133
SDIO_DATACTL_RWEN
#define SDIO_DATACTL_RWEN
Definition: gd32f10x_sdio.h:80
sdio_clock_disable
void sdio_clock_disable(void)
disable SDIO_CLK clock output
Definition: gd32f10x_sdio.c:144
SDIO_INTC
#define SDIO_INTC
Definition: gd32f10x_sdio.h:36
sdio_csm_disable
void sdio_csm_disable(void)
disable the CSM(command state machine)
Definition: gd32f10x_sdio.c:207
sdio_flag_clear
void sdio_flag_clear(uint32_t flag)
clear the pending flags of SDIO
Definition: gd32f10x_sdio.c:457
SDIO_RESPONSE0
#define SDIO_RESPONSE0
Definition: gd32f10x_sdio.h:268
DEFAULT_RESET_VALUE
#define DEFAULT_RESET_VALUE
Definition: gd32f10x_sdio.c:15
sdio_interrupt_flag_get
FlagStatus sdio_interrupt_flag_get(uint32_t int_flag)
get the interrupt flags state of SDIO
Definition: gd32f10x_sdio.c:562
sdio_csm_enable
void sdio_csm_enable(void)
enable the CSM(command state machine)
Definition: gd32f10x_sdio.c:196
SDIO_DATATO_DATATO
#define SDIO_DATATO_DATATO
Definition: gd32f10x_sdio.h:69
sdio_operation_enable
void sdio_operation_enable(void)
enable the SD I/O mode specific operation(SD I/O only)
Definition: gd32f10x_sdio.c:667
sdio_ceata_command_completion_enable
void sdio_ceata_command_completion_enable(void)
enable the CE-ATA command completion signal(CE-ATA only)
Definition: gd32f10x_sdio.c:755
SDIO_DATACTL_DATAEN
#define SDIO_DATACTL_DATAEN
Definition: gd32f10x_sdio.h:75
SDIO_CMDAGMT_CMDAGMT
#define SDIO_CMDAGMT_CMDAGMT
Definition: gd32f10x_sdio.h:55
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_enet.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_enet.h"
14
15 #ifdef GD32F10X_CL
16
17 #if defined (__CC_ARM)
18 __align(4)
19 enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM];
20 __align(4)
21 enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM];
22 __align(4)
23 uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE];
24 __align(4)
25 uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE];
27 #elif defined ( __ICCARM__ )
28 #pragma data_alignment=4
29 enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM];
30 #pragma data_alignment=4
31 enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM];
32 #pragma data_alignment=4
33 uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE];
34 #pragma data_alignment=4
35 uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE];
37 #endif /* __CC_ARM */
38
39 /* global transmit and receive descriptors pointers */
40 enet_descriptors_struct *dma_current_txdesc;
41 enet_descriptors_struct *dma_current_rxdesc;
42
43 /* structure pointer of ptp descriptor for normal mode */
44 enet_descriptors_struct *dma_current_ptp_txdesc = NULL;
45 enet_descriptors_struct *dma_current_ptp_rxdesc = NULL;
46
47 /* init structure parameters for ENET initialization */
48 static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
49
50 /* array of register offset for debug information get */
51 static const uint16_t enet_reg_tab[] = {
52 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x1080, 0x001C, 0x0028, 0x002C,
53 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C,
54
55 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4,
56
57 0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720,
58
59 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1048, 0x104C,
60 0x1050, 0x1054};
61
62
69 void enet_deinit(void)
70 {
71 rcu_periph_reset_enable(RCU_ENETRST);
72 rcu_periph_reset_disable(RCU_ENETRST);
73 enet_initpara_reset();
74 }
75
176 void enet_initpara_config(enet_option_enum option, uint32_t para)
177 {
178 switch(option){
179 case FORWARD_OPTION:
180 /* choose to configure forward_frame, and save the configuration parameters */
181 enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION;
182 enet_initpara.forward_frame = para;
183 break;
184 case DMABUS_OPTION:
185 /* choose to configure dmabus_mode, and save the configuration parameters */
186 enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION;
187 enet_initpara.dmabus_mode = para;
188 break;
189 case DMA_MAXBURST_OPTION:
190 /* choose to configure dma_maxburst, and save the configuration parameters */
191 enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION;
192 enet_initpara.dma_maxburst = para;
193 break;
194 case DMA_ARBITRATION_OPTION:
195 /* choose to configure dma_arbitration, and save the configuration parameters */
196 enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION;
197 enet_initpara.dma_arbitration = para;
198 break;
199 case STORE_OPTION:
200 /* choose to configure store_forward_mode, and save the configuration parameters */
201 enet_initpara.option_enable |= (uint32_t)STORE_OPTION;
202 enet_initpara.store_forward_mode = para;
203 break;
204 case DMA_OPTION:
205 /* choose to configure dma_function, and save the configuration parameters */
206 enet_initpara.option_enable |= (uint32_t)DMA_OPTION;
207 enet_initpara.dma_function = para;
208 break;
209 case VLAN_OPTION:
210 /* choose to configure vlan_config, and save the configuration parameters */
211 enet_initpara.option_enable |= (uint32_t)VLAN_OPTION;
212 enet_initpara.vlan_config = para;
213 break;
214 case FLOWCTL_OPTION:
215 /* choose to configure flow_control, and save the configuration parameters */
216 enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION;
217 enet_initpara.flow_control = para;
218 break;
219 case HASHH_OPTION:
220 /* choose to configure hashtable_high, and save the configuration parameters */
221 enet_initpara.option_enable |= (uint32_t)HASHH_OPTION;
222 enet_initpara.hashtable_high = para;
223 break;
224 case HASHL_OPTION:
225 /* choose to configure hashtable_low, and save the configuration parameters */
226 enet_initpara.option_enable |= (uint32_t)HASHL_OPTION;
227 enet_initpara.hashtable_low = para;
228 break;
229 case FILTER_OPTION:
230 /* choose to configure framesfilter_mode, and save the configuration parameters */
231 enet_initpara.option_enable |= (uint32_t)FILTER_OPTION;
232 enet_initpara.framesfilter_mode = para;
233 break;
234 case HALFDUPLEX_OPTION:
235 /* choose to configure halfduplex_param, and save the configuration parameters */
236 enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION;
237 enet_initpara.halfduplex_param = para;
238 break;
239 case TIMER_OPTION:
240 /* choose to configure timer_config, and save the configuration parameters */
241 enet_initpara.option_enable |= (uint32_t)TIMER_OPTION;
242 enet_initpara.timer_config = para;
243 break;
244 case INTERFRAMEGAP_OPTION:
245 /* choose to configure interframegap, and save the configuration parameters */
246 enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION;
247 enet_initpara.interframegap = para;
248 break;
249 default:
250 break;
251 }
252 }
253
280 ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept)
281 {
282 uint32_t reg_value=0U, reg_temp = 0U, temp = 0U;
283 uint32_t media_temp = 0U;
284 uint32_t timeout = 0U;
285 uint16_t phy_value = 0U;
286 ErrStatus phy_state= ERROR, enet_state = ERROR;
287
288 /* PHY interface configuration, configure SMI clock and reset PHY chip */
289 if(ERROR == enet_phy_config()){
290 _ENET_DELAY_(PHY_RESETDELAY);
291 if(ERROR == enet_phy_config()){
292 return enet_state;
293 }
294 }
295 /* initialize ENET peripheral with generally concerned parameters */
296 enet_default_init();
297
298 /* 1st, configure mediamode */
299 media_temp = (uint32_t)mediamode;
300 /* if is PHY auto negotiation */
301 if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){
302 /* wait for PHY_LINKED_STATUS bit be set */
303 do{
304 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
305 phy_value &= PHY_LINKED_STATUS;
306 timeout++;
307 }while((RESET == phy_value) && (timeout < PHY_READ_TO));
308 /* return ERROR due to timeout */
309 if(PHY_READ_TO == timeout){
310 return enet_state;
311 }
312 /* reset timeout counter */
313 timeout = 0U;
314
315 /* enable auto-negotiation */
316 phy_value = PHY_AUTONEGOTIATION;
317 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
318 if(!phy_state){
319 /* return ERROR due to write timeout */
320 return enet_state;
321 }
322
323 /* wait for the PHY_AUTONEGO_COMPLETE bit be set */
324 do{
325 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
326 phy_value &= PHY_AUTONEGO_COMPLETE;
327 timeout++;
328 }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO));
329 /* return ERROR due to timeout */
330 if(PHY_READ_TO == timeout){
331 return enet_state;
332 }
333 /* reset timeout counter */
334 timeout = 0U;
335
336 /* read the result of the auto-negotiation */
337 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value);
338 /* configure the duplex mode of MAC following the auto-negotiation result */
339 if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){
340 media_temp = ENET_MODE_FULLDUPLEX;
341 }else{
342 media_temp = ENET_MODE_HALFDUPLEX;
343 }
344 /* configure the communication speed of MAC following the auto-negotiation result */
345 if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){
346 media_temp |= ENET_SPEEDMODE_10M;
347 }else{
348 media_temp |= ENET_SPEEDMODE_100M;
349 }
350 }else{
351 phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3);
352 phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1);
353 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
354 if(!phy_state){
355 /* return ERROR due to write timeout */
356 return enet_state;
357 }
358 /* PHY configuration need some time */
359 _ENET_DELAY_(PHY_CONFIGDELAY);
360 }
361 /* after configuring the PHY, use mediamode to configure registers */
362 reg_value = ENET_MAC_CFG;
363 /* configure ENET_MAC_CFG register */
364 reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM));
365 reg_value |= media_temp;
366 ENET_MAC_CFG = reg_value;
367
368
369 /* 2st, configure checksum */
370 if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){
371 ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE;
372
373 reg_value = ENET_DMA_CTL;
374 /* configure ENET_DMA_CTL register */
375 reg_value &= ~ENET_DMA_CTL_DTCERFD;
376 reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD);
377 ENET_DMA_CTL = reg_value;
378 }
379
380 /* 3rd, configure recept */
381 ENET_MAC_FRMF |= (uint32_t)recept;
382
383 /* 4th, configure different function options */
384 /* configure forward_frame related registers */
385 if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){
386 reg_temp = enet_initpara.forward_frame;
387
388 reg_value = ENET_MAC_CFG;
389 temp = reg_temp;
390 /* configure ENET_MAC_CFG register */
391 reg_value &= (~ENET_MAC_CFG_APCD);
392 temp &= ENET_MAC_CFG_APCD;
393 reg_value |= temp;
394 ENET_MAC_CFG = reg_value;
395
396 reg_value = ENET_DMA_CTL;
397 temp = reg_temp;
398 /* configure ENET_DMA_CTL register */
399 reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF));
400 temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2);
401 reg_value |= (temp >> 2);
402 ENET_DMA_CTL = reg_value;
403 }
404
405 /* configure dmabus_mode related registers */
406 if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){
407 temp = enet_initpara.dmabus_mode;
408
409 reg_value = ENET_DMA_BCTL;
410 /* configure ENET_DMA_BCTL register */
411 reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \
412 |ENET_DMA_BCTL_FPBL);
413 reg_value |= temp;
414 ENET_DMA_BCTL = reg_value;
415 }
416
417 /* configure dma_maxburst related registers */
418 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){
419 temp = enet_initpara.dma_maxburst;
420
421 reg_value = ENET_DMA_BCTL;
422 /* configure ENET_DMA_BCTL register */
423 reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP);
424 reg_value |= temp;
425 ENET_DMA_BCTL = reg_value;
426 }
427
428 /* configure dma_arbitration related registers */
429 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){
430 temp = enet_initpara.dma_arbitration;
431
432 reg_value = ENET_DMA_BCTL;
433 /* configure ENET_DMA_BCTL register */
434 reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB);
435 reg_value |= temp;
436 ENET_DMA_BCTL = reg_value;
437 }
438
439 /* configure store_forward_mode related registers */
440 if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){
441 temp = enet_initpara.store_forward_mode;
442
443 reg_value = ENET_DMA_CTL;
444 /* configure ENET_DMA_CTL register */
445 reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC);
446 reg_value |= temp;
447 ENET_DMA_CTL = reg_value;
448 }
449
450 /* configure dma_function related registers */
451 if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){
452 reg_temp = enet_initpara.dma_function;
453
454 reg_value = ENET_DMA_CTL;
455 /* configure ENET_DMA_CTL register */
456 reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF));
457 reg_value |= reg_temp;
458 ENET_DMA_CTL = reg_value;
459 }
460
461 /* configure vlan_config related registers */
462 if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){
463 reg_temp = enet_initpara.vlan_config;
464
465 reg_value = ENET_MAC_VLT;
466 /* configure ENET_MAC_VLT register */
467 reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC);
468 reg_value |= reg_temp;
469 ENET_MAC_VLT = reg_value;
470 }
471
472 /* configure flow_control related registers */
473 if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){
474 reg_temp = enet_initpara.flow_control;
475
476 reg_value = ENET_MAC_FCTL;
477 temp = reg_temp;
478 /* configure ENET_MAC_FCTL register */
479 reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
480 | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
481 temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
482 | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
483 reg_value |= temp;
484 ENET_MAC_FCTL = reg_value;
485
486 reg_value = ENET_MAC_FCTH;
487 temp = reg_temp;
488 /* configure ENET_MAC_FCTH register */
489 reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD);
490 temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8);
491 reg_value |= (temp >> 8);
492 ENET_MAC_FCTH = reg_value;
493 }
494
495 /* configure hashtable_high related registers */
496 if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){
497 ENET_MAC_HLH = enet_initpara.hashtable_high;
498 }
499
500 /* configure hashtable_low related registers */
501 if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){
502 ENET_MAC_HLL = enet_initpara.hashtable_low;
503 }
504
505 /* configure framesfilter_mode related registers */
506 if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){
507 reg_temp = enet_initpara.framesfilter_mode;
508
509 reg_value = ENET_MAC_FRMF;
510 /* configure ENET_MAC_FRMF register */
511 reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \
512 | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \
513 | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM);
514 reg_value |= reg_temp;
515 ENET_MAC_FRMF = reg_value;
516 }
517
518 /* configure halfduplex_param related registers */
519 if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){
520 reg_temp = enet_initpara.halfduplex_param;
521
522 reg_value = ENET_MAC_CFG;
523 /* configure ENET_MAC_CFG register */
524 reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \
525 | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC);
526 reg_value |= reg_temp;
527 ENET_MAC_CFG = reg_value;
528 }
529
530 /* configure timer_config related registers */
531 if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){
532 reg_temp = enet_initpara.timer_config;
533
534 reg_value = ENET_MAC_CFG;
535 /* configure ENET_MAC_CFG register */
536 reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD);
537 reg_value |= reg_temp;
538 ENET_MAC_CFG = reg_value;
539 }
540
541 /* configure interframegap related registers */
542 if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){
543 reg_temp = enet_initpara.interframegap;
544
545 reg_value = ENET_MAC_CFG;
546 /* configure ENET_MAC_CFG register */
547 reg_value &= ~ENET_MAC_CFG_IGBS;
548 reg_value |= reg_temp;
549 ENET_MAC_CFG = reg_value;
550 }
551
552 enet_state = SUCCESS;
553 return enet_state;
554 }
555
562 ErrStatus enet_software_reset(void)
563 {
564 uint32_t timeout = 0U;
565 ErrStatus enet_state = ERROR;
566 uint32_t dma_flag;
567
568 /* reset all core internal registers located in CLK_TX and CLK_RX */
569 ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR;
570
571 /* wait for reset operation complete */
572 do{
573 dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR);
574 timeout++;
575 }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout));
576
577 /* reset operation complete */
578 if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){
579 enet_state = SUCCESS;
580 }
581
582 return enet_state;
583 }
584
591 uint32_t enet_rxframe_size_get(void)
592 {
593 uint32_t size = 0U;
594 uint32_t status;
595
596 /* get rdes0 information of current RxDMA descriptor */
597 status = dma_current_rxdesc->status;
598
599 /* if the desciptor is owned by DMA */
600 if((uint32_t)RESET != (status & ENET_RDES0_DAV)){
601 return 0U;
602 }
603
604 /* if has any error, or the frame uses two or more descriptors */
605 if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) ||
606 (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) ||
607 (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){
608 /* drop current receive frame */
609 enet_rxframe_drop();
610
611 return 0U;
612 }
613
614 /* if is an ethernet-type frame, and IP frame payload error occurred */
615 if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) &&
616 (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){
617 /* drop current receive frame */
618 enet_rxframe_drop();
619
620 return 0U;
621 }
622
623 /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */
624 if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) &&
625 (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) &&
626 (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) &&
627 (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){
628 /* get the size of the received data including CRC */
629 size = GET_RDES0_FRML(status);
630 /* substract the CRC size */
631 size = size - 4U;
632 }
633
634 /* return packet size */
635 return size;
636 }
637
647 void enet_descriptors_chain_init(enet_dmadirection_enum direction)
648 {
649 uint32_t num = 0U, count = 0U, maxsize = 0U;
650 uint32_t desc_status = 0U, desc_bufsize = 0U;
651 enet_descriptors_struct *desc, *desc_tab;
652 uint8_t *buf;
653
654 /* if want to initialize DMA Tx descriptors */
655 if (ENET_DMA_TX == direction){
656 /* save a copy of the DMA Tx descriptors */
657 desc_tab = txdesc_tab;
658 buf = &tx_buff[0][0];
659 count = ENET_TXBUF_NUM;
660 maxsize = ENET_TXBUF_SIZE;
661
662 /* select chain mode */
663 desc_status = ENET_TDES0_TCHM;
664
665 /* configure DMA Tx descriptor table address register */
666 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
667 dma_current_txdesc = desc_tab;
668 }else{
669 /* if want to initialize DMA Rx descriptors */
670 /* save a copy of the DMA Rx descriptors */
671 desc_tab = rxdesc_tab;
672 buf = &rx_buff[0][0];
673 count = ENET_RXBUF_NUM;
674 maxsize = ENET_RXBUF_SIZE;
675
676 /* enable receiving */
677 desc_status = ENET_RDES0_DAV;
678 /* select receive chained mode and set buffer1 size */
679 desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
680
681 /* configure DMA Rx descriptor table address register */
682 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
683 dma_current_rxdesc = desc_tab;
684 }
685 dma_current_ptp_rxdesc = NULL;
686 dma_current_ptp_txdesc = NULL;
687
688 /* configure each descriptor */
689 for(num=0U; num < count; num++){
690 /* get the pointer to the next descriptor of the descriptor table */
691 desc = desc_tab + num;
692
693 /* configure descriptors */
694 desc->status = desc_status;
695 desc->control_buffer_size = desc_bufsize;
696 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
697
698 /* if is not the last descriptor */
699 if(num < (count - 1U)){
700 /* configure the next descriptor address */
701 desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
702 }else{
703 /* when it is the last descriptor, the next descriptor address
704 equals to first descriptor address in descriptor table */
705 desc->buffer2_next_desc_addr = (uint32_t) desc_tab;
706 }
707 }
708 }
709
719 void enet_descriptors_ring_init(enet_dmadirection_enum direction)
720 {
721 uint32_t num = 0U, count = 0U, maxsize = 0U;
722 uint32_t desc_status = 0U, desc_bufsize = 0U;
723 enet_descriptors_struct *desc;
724 enet_descriptors_struct *desc_tab;
725 uint8_t *buf;
726
727 /* configure descriptor skip length */
728 ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
729 ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
730
731 /* if want to initialize DMA Tx descriptors */
732 if (ENET_DMA_TX == direction){
733 /* save a copy of the DMA Tx descriptors */
734 desc_tab = txdesc_tab;
735 buf = &tx_buff[0][0];
736 count = ENET_TXBUF_NUM;
737 maxsize = ENET_TXBUF_SIZE;
738
739 /* configure DMA Tx descriptor table address register */
740 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
741 dma_current_txdesc = desc_tab;
742 }else{
743 /* if want to initialize DMA Rx descriptors */
744 /* save a copy of the DMA Rx descriptors */
745 desc_tab = rxdesc_tab;
746 buf = &rx_buff[0][0];
747 count = ENET_RXBUF_NUM;
748 maxsize = ENET_RXBUF_SIZE;
749
750 /* enable receiving */
751 desc_status = ENET_RDES0_DAV;
752 /* set buffer1 size */
753 desc_bufsize = ENET_RXBUF_SIZE;
754
755 /* configure DMA Rx descriptor table address register */
756 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
757 dma_current_rxdesc = desc_tab;
758 }
759 dma_current_ptp_rxdesc = NULL;
760 dma_current_ptp_txdesc = NULL;
761
762 /* configure each descriptor */
763 for(num=0U; num < count; num++){
764 /* get the pointer to the next descriptor of the descriptor table */
765 desc = desc_tab + num;
766
767 /* configure descriptors */
768 desc->status = desc_status;
769 desc->control_buffer_size = desc_bufsize;
770 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
771
772 /* when it is the last descriptor */
773 if(num == (count - 1U)){
774 if (ENET_DMA_TX == direction){
775 /* configure transmit end of ring mode */
776 desc->status |= ENET_TDES0_TERM;
777 }else{
778 /* configure receive end of ring mode */
779 desc->control_buffer_size |= ENET_RDES1_RERM;
780 }
781 }
782 }
783 }
784
792 ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize)
793 {
794 uint32_t offset = 0U, size = 0U;
795
796 /* the descriptor is busy due to own by the DMA */
797 if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
798 return ERROR;
799 }
800
801
802 /* if buffer pointer is null, indicates that users has copied data in application */
803 if(NULL != buffer){
804 /* if no error occurs, and the frame uses only one descriptor */
805 if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
806 (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
807 (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
808 /* get the frame length except CRC */
809 size = GET_RDES0_FRML(dma_current_rxdesc->status);
810 size = size - 4U;
811
812 /* to avoid situation that the frame size exceeds the buffer length */
813 if(size > bufsize){
814 return ERROR;
815 }
816
817 /* copy data from Rx buffer to application buffer */
818 for(offset = 0U; offset<size; offset++){
819 (*(buffer + offset)) = (*(__IO uint8_t *) (uint32_t)((dma_current_rxdesc->buffer1_addr) + offset));
820 }
821
822 }else{
823 /* return ERROR */
824 return ERROR;
825 }
826 }
827 /* enable reception, descriptor is owned by DMA */
828 dma_current_rxdesc->status = ENET_RDES0_DAV;
829
830 /* check Rx buffer unavailable flag status */
831 if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
832 /* clear RBU flag */
833 ENET_DMA_STAT = ENET_DMA_STAT_RBU;
834 /* resume DMA reception by writing to the RPEN register*/
835 ENET_DMA_RPEN = 0U;
836 }
837
838 /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */
839 /* chained mode */
840 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
841 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
842 }else{
843 /* ring mode */
844 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
845 /* if is the last descriptor in table, the next descriptor is the table header */
846 dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
847 }else{
848 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
849 dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
850 }
851 }
852
853 return SUCCESS;
854 }
855
864 ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length)
865 {
866 uint32_t offset = 0U;
867 uint32_t dma_tbu_flag, dma_tu_flag;
868
869 /* the descriptor is busy due to own by the DMA */
870 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
871 return ERROR;
872 }
873
874 /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */
875 if(length > ENET_MAX_FRAME_SIZE){
876 return ERROR;
877 }
878
879 /* if buffer pointer is null, indicates that users has handled data in application */
880 if(NULL != buffer){
881 /* copy frame data from application buffer to Tx buffer */
882 for(offset = 0U; offset < length; offset++){
883 (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
884 }
885 }
886
887 /* set the frame length */
888 dma_current_txdesc->control_buffer_size = length;
889 /* set the segment of frame, frame is transmitted in one descriptor */
890 dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
891 /* enable the DMA transmission */
892 dma_current_txdesc->status |= ENET_TDES0_DAV;
893
894 /* check Tx buffer unavailable flag status */
895 dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
896 dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
897
898 if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
899 /* clear TBU and TU flag */
900 ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
901 /* resume DMA transmission by writing to the TPEN register*/
902 ENET_DMA_TPEN = 0U;
903 }
904
905 /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/
906 /* chained mode */
907 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
908 dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr);
909 }else{
910 /* ring mode */
911 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
912 /* if is the last descriptor in table, the next descriptor is the table header */
913 dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
914 }else{
915 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
916 dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
917 }
918 }
919
920 return SUCCESS;
921 }
922
935 void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum)
936 {
937 desc->status &= ~ENET_TDES0_CM;
938 desc->status |= checksum;
939 }
940
947 void enet_enable(void)
948 {
949 enet_tx_enable();
950 enet_rx_enable();
951 }
952
959 void enet_disable(void)
960 {
961 enet_tx_disable();
962 enet_rx_disable();
963 }
964
978 void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[])
979 {
980 REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr);
981 REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr);
982 }
983
996 void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[])
997 {
998 paddr[0] = ENET_GET_MACADDR(mac_addr, 0U);
999 paddr[1] = ENET_GET_MACADDR(mac_addr, 1U);
1000 paddr[2] = ENET_GET_MACADDR(mac_addr, 2U);
1001 paddr[3] = ENET_GET_MACADDR(mac_addr, 3U);
1002 paddr[4] = ENET_GET_MACADDR(mac_addr, 4U);
1003 paddr[5] = ENET_GET_MACADDR(mac_addr, 5U);
1004 }
1005
1050 FlagStatus enet_flag_get(enet_flag_enum enet_flag)
1051 {
1052 if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){
1053 return SET;
1054 }else{
1055 return RESET;
1056 }
1057 }
1058
1081 void enet_flag_clear(enet_flag_clear_enum enet_flag)
1082 {
1083 /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */
1084 ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag));
1085 }
1086
1117 void enet_interrupt_enable(enet_int_enum enet_int)
1118 {
1119 if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
1120 /* ENET_DMA_INTEN register interrupt */
1121 ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
1122 }else{
1123 /* other INTMSK register interrupt */
1124 ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
1125 }
1126 }
1127
1158 void enet_interrupt_disable(enet_int_enum enet_int)
1159 {
1160 if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
1161 /* ENET_DMA_INTEN register interrupt */
1162 ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
1163 }else{
1164 /* other INTMSK register interrupt */
1165 ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
1166 }
1167 }
1168
1205 FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag)
1206 {
1207 if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){
1208 return SET;
1209 }else{
1210 return RESET;
1211 }
1212 }
1213
1236 void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear)
1237 {
1238 /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */
1239 ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear));
1240 }
1241
1248 void enet_tx_enable(void)
1249 {
1250 ENET_MAC_CFG |= ENET_MAC_CFG_TEN;
1251 enet_txfifo_flush();
1252 ENET_DMA_CTL |= ENET_DMA_CTL_STE;
1253 }
1254
1261 void enet_tx_disable(void)
1262 {
1263 ENET_DMA_CTL &= ~ENET_DMA_CTL_STE;
1264 enet_txfifo_flush();
1265 ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN;
1266 }
1267
1274 void enet_rx_enable(void)
1275 {
1276 ENET_MAC_CFG |= ENET_MAC_CFG_REN;
1277 ENET_DMA_CTL |= ENET_DMA_CTL_SRE;
1278 }
1279
1286 void enet_rx_disable(void)
1287 {
1288 ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE;
1289 ENET_MAC_CFG &= ~ENET_MAC_CFG_REN;
1290 }
1291
1304 void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num)
1305 {
1306 uint32_t offset = 0U, max = 0U, limit = 0U;
1307
1308 offset = (uint32_t)type;
1309 max = (uint32_t)type + num;
1310 limit = sizeof(enet_reg_tab)/sizeof(uint16_t);
1311
1312 /* prevent element in this array is out of range */
1313 if(max > limit){
1314 max = limit;
1315 }
1316
1317 for(; offset < max; offset++){
1318 /* get value of the corresponding register */
1319 *preg = REG32((ENET) + enet_reg_tab[offset]);
1320 preg++;
1321 }
1322 }
1323
1333 void enet_address_filter_enable(enet_macaddress_enum mac_addr)
1334 {
1335 REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE;
1336 }
1337
1348 void enet_address_filter_disable(enet_macaddress_enum mac_addr)
1349 {
1350 REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE;
1351 }
1352
1375 void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type)
1376 {
1377 uint32_t reg;
1378
1379 /* get the address filter register value which is to be configured */
1380 reg = REG32(ENET_ADDRH_BASE + mac_addr);
1381
1382 /* clear and configure the address filter register */
1383 reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF);
1384 reg |= (addr_mask | filter_type);
1385 REG32(ENET_ADDRH_BASE + mac_addr) = reg;
1386 }
1387
1394 ErrStatus enet_phy_config(void)
1395 {
1396 uint32_t ahbclk;
1397 uint32_t reg;
1398 uint16_t phy_value;
1399 ErrStatus enet_state = ERROR;
1400
1401 /* clear the previous MDC clock */
1402 reg = ENET_MAC_PHY_CTL;
1403 reg &= ~ENET_MAC_PHY_CTL_CLR;
1404
1405 /* get the HCLK frequency */
1406 ahbclk = rcu_clock_freq_get(CK_AHB);
1407
1408 /* configure MDC clock according to HCLK frequency range */
1409 if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){
1410 reg |= ENET_MDC_HCLK_DIV16;
1411 }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){
1412 reg |= ENET_MDC_HCLK_DIV26;
1413 }else if(ENET_RANGE(ahbclk, 60000000U, 90000000U)){
1414 reg |= ENET_MDC_HCLK_DIV42;
1415 }else if((ENET_RANGE(ahbclk, 90000000U, 108000000U))||(108000000U == ahbclk)){
1416 reg |= ENET_MDC_HCLK_DIV62;
1417 }else{
1418 return enet_state;
1419 }
1420 ENET_MAC_PHY_CTL = reg;
1421
1422 /* reset PHY */
1423 phy_value = PHY_RESET;
1424 if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
1425 return enet_state;
1426 }
1427 /* PHY reset need some time */
1428 _ENET_DELAY_(ENET_DELAY_TO);
1429
1430 /* check whether PHY reset is complete */
1431 if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
1432 return enet_state;
1433 }
1434
1435 /* PHY reset complete */
1436 if(RESET == (phy_value & PHY_RESET)){
1437 enet_state = SUCCESS;
1438 }
1439
1440 return enet_state;
1441 }
1442
1454 ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
1455 {
1456 uint32_t reg, phy_flag;
1457 uint32_t timeout = 0U;
1458 ErrStatus enet_state = ERROR;
1459
1460 /* configure ENET_MAC_PHY_CTL with write/read operation */
1461 reg = ENET_MAC_PHY_CTL;
1462 reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA);
1463 reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB);
1464
1465 /* if do the write operation, write value to the register */
1466 if(ENET_PHY_WRITE == direction){
1467 ENET_MAC_PHY_DATA = *pvalue;
1468 }
1469
1470 /* do PHY write/read operation, and wait the operation complete */
1471 ENET_MAC_PHY_CTL = reg;
1472 do{
1473 phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB);
1474 timeout++;
1475 }
1476 while((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
1477
1478 /* write/read operation complete */
1479 if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){
1480 enet_state = SUCCESS;
1481 }
1482
1483 /* if do the read operation, get value from the register */
1484 if(ENET_PHY_READ == direction){
1485 *pvalue = (uint16_t)ENET_MAC_PHY_DATA;
1486 }
1487
1488 return enet_state;
1489 }
1490
1497 ErrStatus enet_phyloopback_enable(void)
1498 {
1499 uint16_t temp_phy = 0U;
1500 ErrStatus phy_state = ERROR;
1501
1502 /* get the PHY configuration to update it */
1503 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1504
1505 /* enable the PHY loopback mode */
1506 temp_phy |= PHY_LOOPBACK;
1507
1508 /* update the PHY control register with the new configuration */
1509 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1510
1511 return phy_state;
1512 }
1513
1520 ErrStatus enet_phyloopback_disable(void)
1521 {
1522 uint16_t temp_phy = 0U;
1523 ErrStatus phy_state = ERROR;
1524
1525 /* get the PHY configuration to update it */
1526 enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1527
1528 /* disable the PHY loopback mode */
1529 temp_phy &= (uint16_t)~PHY_LOOPBACK;
1530
1531 /* update the PHY control register with the new configuration */
1532 phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
1533
1534 return phy_state;
1535 }
1536
1547 void enet_forward_feature_enable(uint32_t feature)
1548 {
1549 uint32_t mask;
1550
1551 mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
1552 ENET_MAC_CFG |= mask;
1553
1554 mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
1555 ENET_DMA_CTL |= (mask >> 2);
1556 }
1557
1568 void enet_forward_feature_disable(uint32_t feature)
1569 {
1570 uint32_t mask;
1571
1572 mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
1573 ENET_MAC_CFG &= ~mask;
1574
1575 mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
1576 ENET_DMA_CTL &= ~(mask >> 2);
1577 }
1578
1593 void enet_fliter_feature_enable(uint32_t feature)
1594 {
1595 ENET_MAC_FRMF |= feature;
1596 }
1597
1612 void enet_fliter_feature_disable(uint32_t feature)
1613 {
1614 ENET_MAC_FRMF &= ~feature;
1615 }
1616
1624 ErrStatus enet_pauseframe_generate(void)
1625 {
1626 ErrStatus enet_state =ERROR;
1627 uint32_t temp = 0U;
1628
1629 /* in full-duplex mode, must make sure this bit is 0 before writing register */
1630 temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA;
1631 if(RESET == temp){
1632 ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA;
1633 enet_state = SUCCESS;
1634 }
1635 return enet_state;
1636 }
1637
1649 void enet_pauseframe_detect_config(uint32_t detect)
1650 {
1651 ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT;
1652 ENET_MAC_FCTL |= detect;
1653 }
1654
1668 void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold)
1669 {
1670 ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS);
1671 ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold);
1672 }
1673
1698 void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active)
1699 {
1700 ENET_MAC_FCTH = ((deactive | active) >> 8);
1701 }
1702
1714 void enet_flowcontrol_feature_enable(uint32_t feature)
1715 {
1716 if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
1717 ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE;
1718 }
1719 feature &= ~ENET_ZERO_QUANTA_PAUSE;
1720 ENET_MAC_FCTL |= feature;
1721 }
1722
1734 void enet_flowcontrol_feature_disable(uint32_t feature)
1735 {
1736 if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
1737 ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE;
1738 }
1739 feature &= ~ENET_ZERO_QUANTA_PAUSE;
1740 ENET_MAC_FCTL &= ~feature;
1741 }
1742
1756 uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction)
1757 {
1758 uint32_t reval;
1759 reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction);
1760 return reval;
1761 }
1762
1773 void enet_dmaprocess_resume(enet_dmadirection_enum direction)
1774 {
1775 if(ENET_DMA_TX == direction){
1776 ENET_DMA_TPEN = 0U;
1777 }else{
1778 ENET_DMA_RPEN = 0U;
1779 }
1780 }
1781
1788 void enet_rxprocess_check_recovery(void)
1789 {
1790 uint32_t status;
1791
1792 /* get DAV information of current RxDMA descriptor */
1793 status = dma_current_rxdesc->status;
1794 status &= ENET_RDES0_DAV;
1795
1796 /* if current descriptor is owned by DMA, but the descriptor address mismatches with
1797 receive descriptor address pointer updated by RxDMA controller */
1798 if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) &&
1799 (ENET_RDES0_DAV == status)){
1800 dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR;
1801 }
1802 }
1803
1810 ErrStatus enet_txfifo_flush(void)
1811 {
1812 uint32_t flush_state;
1813 uint32_t timeout = 0U;
1814 ErrStatus enet_state = ERROR;
1815
1816 /* set the FTF bit for flushing transmit FIFO */
1817 ENET_DMA_CTL |= ENET_DMA_CTL_FTF;
1818 /* wait until the flush operation completes */
1819 do{
1820 flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF;
1821 timeout++;
1822 }while((RESET != flush_state) && (timeout < ENET_DELAY_TO));
1823 /* return ERROR due to timeout */
1824 if(RESET == flush_state){
1825 enet_state = SUCCESS;
1826 }
1827
1828 return enet_state;
1829 }
1830
1846 uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get)
1847 {
1848 uint32_t reval = 0U;
1849
1850 reval = REG32((ENET) +(uint32_t)addr_get);
1851 return reval;
1852 }
1853
1868 uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get)
1869 {
1870 uint32_t reval = 0xFFFFFFFFU;
1871
1872 switch(info_get){
1873 case RXDESC_BUFFER_1_SIZE:
1874 reval = GET_RDES1_RB1S(desc->control_buffer_size);
1875 break;
1876 case RXDESC_BUFFER_2_SIZE:
1877 reval = GET_RDES1_RB2S(desc->control_buffer_size);
1878 break;
1879 case RXDESC_FRAME_LENGTH:
1880 reval = GET_RDES0_FRML(desc->status);
1881 reval = reval - 4U;
1882
1883 break;
1884 case RXDESC_BUFFER_1_ADDR:
1885 reval = desc->buffer1_addr;
1886 break;
1887 case TXDESC_BUFFER_1_ADDR:
1888 reval = desc->buffer1_addr;
1889 break;
1890 case TXDESC_COLLISION_COUNT:
1891 reval = GET_TDES0_COCNT(desc->status);
1892 break;
1893 default:
1894 break;
1895 }
1896 return reval;
1897 }
1898
1906 void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop)
1907 {
1908 uint32_t temp_counter = 0U;
1909
1910 temp_counter = ENET_DMA_MFBOCNT;
1911 *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter);
1912 *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter);
1913 }
1914
1965 FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag)
1966 {
1967 FlagStatus enet_flag = RESET;
1968
1969 if ((uint32_t)RESET != (desc->status & desc_flag)){
1970 enet_flag = SET;
1971 }
1972
1973 return enet_flag;
1974 }
1975
1996 void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag)
1997 {
1998 desc->status |= desc_flag;
1999 }
2000
2021 void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag)
2022 {
2023 desc->status &= ~desc_flag;
2024 }
2025
2032 void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc)
2033 {
2034 desc->control_buffer_size &= ~ENET_RDES1_DINTC;
2035 }
2036
2043 void enet_rxframe_drop(void)
2044 {
2045 /* enable reception, descriptor is owned by DMA */
2046 dma_current_rxdesc->status = ENET_RDES0_DAV;
2047
2048 /* chained mode */
2049 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
2050 if(NULL != dma_current_ptp_rxdesc){
2051 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
2052 /* if it is the last ptp descriptor */
2053 if(0U != dma_current_ptp_rxdesc->status){
2054 /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
2055 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2056 }else{
2057 /* ponter to the next ptp descriptor */
2058 dma_current_ptp_rxdesc++;
2059 }
2060 }else{
2061 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
2062 }
2063
2064 }else{
2065 /* ring mode */
2066 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
2067 /* if is the last descriptor in table, the next descriptor is the table header */
2068 dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
2069 if(NULL != dma_current_ptp_rxdesc){
2070 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2071 }
2072 }else{
2073 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
2074 dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
2075 if(NULL != dma_current_ptp_rxdesc){
2076 dma_current_ptp_rxdesc++;
2077 }
2078 }
2079 }
2080 }
2081
2091 void enet_dma_feature_enable(uint32_t feature)
2092 {
2093 ENET_DMA_CTL |= feature;
2094 }
2095
2105 void enet_dma_feature_disable(uint32_t feature)
2106 {
2107 ENET_DMA_CTL &= ~feature;
2108 }
2109
2120 void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
2121 {
2122 uint32_t num = 0U, count = 0U, maxsize = 0U;
2123 uint32_t desc_status = 0U, desc_bufsize = 0U;
2124 enet_descriptors_struct *desc, *desc_tab;
2125 uint8_t *buf;
2126
2127 /* if want to initialize DMA Tx descriptors */
2128 if (ENET_DMA_TX == direction){
2129 /* save a copy of the DMA Tx descriptors */
2130 desc_tab = txdesc_tab;
2131 buf = &tx_buff[0][0];
2132 count = ENET_TXBUF_NUM;
2133 maxsize = ENET_TXBUF_SIZE;
2134
2135 /* select chain mode, and enable transmit timestamp function */
2136 desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN;
2137
2138 /* configure DMA Tx descriptor table address register */
2139 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
2140 dma_current_txdesc = desc_tab;
2141 dma_current_ptp_txdesc = desc_ptptab;
2142 }else{
2143 /* if want to initialize DMA Rx descriptors */
2144 /* save a copy of the DMA Rx descriptors */
2145 desc_tab = rxdesc_tab;
2146 buf = &rx_buff[0][0];
2147 count = ENET_RXBUF_NUM;
2148 maxsize = ENET_RXBUF_SIZE;
2149
2150 /* enable receiving */
2151 desc_status = ENET_RDES0_DAV;
2152 /* select receive chained mode and set buffer1 size */
2153 desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
2154
2155 /* configure DMA Rx descriptor table address register */
2156 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
2157 dma_current_rxdesc = desc_tab;
2158 dma_current_ptp_rxdesc = desc_ptptab;
2159 }
2160
2161 /* configure each descriptor */
2162 for(num = 0U; num < count; num++){
2163 /* get the pointer to the next descriptor of the descriptor table */
2164 desc = desc_tab + num;
2165
2166 /* configure descriptors */
2167 desc->status = desc_status;
2168 desc->control_buffer_size = desc_bufsize;
2169 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
2170
2171 /* if is not the last descriptor */
2172 if(num < (count - 1U)){
2173 /* configure the next descriptor address */
2174 desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
2175 }else{
2176 /* when it is the last descriptor, the next descriptor address
2177 equals to first descriptor address in descriptor table */
2178 desc->buffer2_next_desc_addr = (uint32_t)desc_tab;
2179 }
2180 /* set desc_ptptab equal to desc_tab */
2181 (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
2182 (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
2183 }
2184 /* when it is the last ptp descriptor, preserve the first descriptor
2185 address of desc_ptptab in ptp descriptor status */
2186 (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
2187 }
2188
2199 void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
2200 {
2201 uint32_t num = 0U, count = 0U, maxsize = 0U;
2202 uint32_t desc_status = 0U, desc_bufsize = 0U;
2203 enet_descriptors_struct *desc, *desc_tab;
2204 uint8_t *buf;
2205
2206 /* configure descriptor skip length */
2207 ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
2208 ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
2209
2210 /* if want to initialize DMA Tx descriptors */
2211 if (ENET_DMA_TX == direction){
2212 /* save a copy of the DMA Tx descriptors */
2213 desc_tab = txdesc_tab;
2214 buf = &tx_buff[0][0];
2215 count = ENET_TXBUF_NUM;
2216 maxsize = ENET_TXBUF_SIZE;
2217
2218 /* select ring mode, and enable transmit timestamp function */
2219 desc_status = ENET_TDES0_TTSEN;
2220
2221 /* configure DMA Tx descriptor table address register */
2222 ENET_DMA_TDTADDR = (uint32_t)desc_tab;
2223 dma_current_txdesc = desc_tab;
2224 dma_current_ptp_txdesc = desc_ptptab;
2225 }else{
2226 /* if want to initialize DMA Rx descriptors */
2227 /* save a copy of the DMA Rx descriptors */
2228 desc_tab = rxdesc_tab;
2229 buf = &rx_buff[0][0];
2230 count = ENET_RXBUF_NUM;
2231 maxsize = ENET_RXBUF_SIZE;
2232
2233 /* enable receiving */
2234 desc_status = ENET_RDES0_DAV;
2235 /* select receive ring mode and set buffer1 size */
2236 desc_bufsize = (uint32_t)ENET_RXBUF_SIZE;
2237
2238 /* configure DMA Rx descriptor table address register */
2239 ENET_DMA_RDTADDR = (uint32_t)desc_tab;
2240 dma_current_rxdesc = desc_tab;
2241 dma_current_ptp_rxdesc = desc_ptptab;
2242 }
2243
2244 /* configure each descriptor */
2245 for(num = 0U; num < count; num++){
2246 /* get the pointer to the next descriptor of the descriptor table */
2247 desc = desc_tab + num;
2248
2249 /* configure descriptors */
2250 desc->status = desc_status;
2251 desc->control_buffer_size = desc_bufsize;
2252 desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
2253
2254 /* when it is the last descriptor */
2255 if(num == (count - 1U)){
2256 if (ENET_DMA_TX == direction){
2257 /* configure transmit end of ring mode */
2258 desc->status |= ENET_TDES0_TERM;
2259 }else{
2260 /* configure receive end of ring mode */
2261 desc->control_buffer_size |= ENET_RDES1_RERM;
2262 }
2263 }
2264 /* set desc_ptptab equal to desc_tab */
2265 (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
2266 (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
2267 }
2268 /* when it is the last ptp descriptor, preserve the first descriptor
2269 address of desc_ptptab in ptp descriptor status */
2270 (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
2271 }
2272
2281 ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[])
2282 {
2283 uint32_t offset = 0U, size = 0U;
2284
2285 /* the descriptor is busy due to own by the DMA */
2286 if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
2287 return ERROR;
2288 }
2289
2290 /* if buffer pointer is null, indicates that users has copied data in application */
2291 if(NULL != buffer){
2292 /* if no error occurs, and the frame uses only one descriptor */
2293 if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
2294 ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
2295 ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
2296
2297 /* get the frame length except CRC */
2298 size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U;
2299
2300 /* to avoid situation that the frame size exceeds the buffer length */
2301 if(size > bufsize){
2302 return ERROR;
2303 }
2304
2305 /* copy data from Rx buffer to application buffer */
2306 for(offset = 0U; offset < size; offset++){
2307 (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset));
2308 }
2309
2310 }else{
2311 return ERROR;
2312 }
2313 }
2314 /* copy timestamp value from Rx descriptor to application array */
2315 timestamp[0] = dma_current_rxdesc->buffer1_addr;
2316 timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr;
2317
2318 dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ;
2319 dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr;
2320
2321 /* enable reception, descriptor is owned by DMA */
2322 dma_current_rxdesc->status = ENET_RDES0_DAV;
2323
2324 /* check Rx buffer unavailable flag status */
2325 if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
2326 /* clear RBU flag */
2327 ENET_DMA_STAT = ENET_DMA_STAT_RBU;
2328 /* resume DMA reception by writing to the RPEN register*/
2329 ENET_DMA_RPEN = 0U;
2330 }
2331
2332
2333 /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */
2334 /* chained mode */
2335 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
2336 dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
2337 /* if it is the last ptp descriptor */
2338 if(0U != dma_current_ptp_rxdesc->status){
2339 /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
2340 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2341 }else{
2342 /* ponter to the next ptp descriptor */
2343 dma_current_ptp_rxdesc++;
2344 }
2345 }else{
2346 /* ring mode */
2347 if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
2348 /* if is the last descriptor in table, the next descriptor is the table header */
2349 dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
2350 /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table,
2351 use the same table with RxDMA descriptor */
2352 dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
2353 }else{
2354 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
2355 dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
2356 dma_current_ptp_rxdesc ++;
2357 }
2358 }
2359
2360 return SUCCESS;
2361 }
2362
2372 ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[])
2373 {
2374 uint32_t offset = 0U, timeout = 0U;
2375 uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag;
2376
2377 /* the descriptor is busy due to own by the DMA */
2378 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
2379 return ERROR;
2380 }
2381
2382 /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */
2383 if(length > ENET_MAX_FRAME_SIZE){
2384 return ERROR;
2385 }
2386
2387 /* if buffer pointer is null, indicates that users has handled data in application */
2388 if(NULL != buffer){
2389 /* copy frame data from application buffer to Tx buffer */
2390 for(offset = 0U; offset < length; offset++){
2391 (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
2392 }
2393 }
2394 /* set the frame length */
2395 dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF);
2396 /* set the segment of frame, frame is transmitted in one descriptor */
2397 dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
2398 /* enable the DMA transmission */
2399 dma_current_txdesc->status |= ENET_TDES0_DAV;
2400
2401 /* check Tx buffer unavailable flag status */
2402 dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
2403 dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
2404
2405 if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
2406 /* clear TBU and TU flag */
2407 ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
2408 /* resume DMA transmission by writing to the TPEN register*/
2409 ENET_DMA_TPEN = 0U;
2410 }
2411
2412 /* if timestamp pointer is null, indicates that users don't care timestamp in application */
2413 if(NULL != timestamp){
2414 /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */
2415 do{
2416 tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS);
2417 timeout++;
2418 }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO));
2419
2420 /* return ERROR due to timeout */
2421 if(ENET_DELAY_TO == timeout){
2422 return ERROR;
2423 }
2424
2425 /* clear the ENET_TDES0_TTMSS flag */
2426 dma_current_txdesc->status &= ~ENET_TDES0_TTMSS;
2427 /* get the timestamp value of the transmit frame */
2428 timestamp[0] = dma_current_txdesc->buffer1_addr;
2429 timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr;
2430 }
2431 dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ;
2432 dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr;
2433
2434 /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */
2435 /* chained mode */
2436 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
2437 dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr);
2438 /* if it is the last ptp descriptor */
2439 if(0U != dma_current_ptp_txdesc->status){
2440 /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
2441 dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
2442 }else{
2443 /* ponter to the next ptp descriptor */
2444 dma_current_ptp_txdesc++;
2445 }
2446 }else{
2447 /* ring mode */
2448 if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
2449 /* if is the last descriptor in table, the next descriptor is the table header */
2450 dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
2451 /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table,
2452 use the same table with TxDMA descriptor */
2453 dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
2454 }else{
2455 /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
2456 dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
2457 dma_current_ptp_txdesc ++;
2458 }
2459 }
2460 return SUCCESS;
2461 }
2462
2469 void enet_wum_filter_register_pointer_reset(void)
2470 {
2471 ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR;
2472 }
2473
2480 void enet_wum_filter_config(uint32_t pdata[])
2481 {
2482 uint32_t num = 0U;
2483
2484 /* configure ENET_MAC_RWFF register */
2485 for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){
2486 ENET_MAC_RWFF = pdata[num];
2487 }
2488 }
2489
2500 void enet_wum_feature_enable(uint32_t feature)
2501 {
2502 ENET_MAC_WUM |= feature;
2503 }
2504
2514 void enet_wum_feature_disable(uint32_t feature)
2515 {
2516 ENET_MAC_WUM &= (~feature);
2517 }
2518
2525 void enet_msc_counters_reset(void)
2526 {
2527 /* reset all counters */
2528 ENET_MSC_CTL |= ENET_MSC_CTL_CTR;
2529 }
2530
2540 void enet_msc_feature_enable(uint32_t feature)
2541 {
2542 ENET_MSC_CTL |= feature;
2543 }
2544
2554 void enet_msc_feature_disable(uint32_t feature)
2555 {
2556 ENET_MSC_CTL &= (~feature);
2557 }
2558
2572 uint32_t enet_msc_counters_get(enet_msc_counter_enum counter)
2573 {
2574 uint32_t reval;
2575
2576 reval = REG32((ENET + (uint32_t)counter));
2577
2578 return reval;
2579 }
2580
2587 uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond)
2588 {
2589 uint64_t val = subsecond * 1000000000Ull;
2590 val >>= 31;
2591 return (uint32_t)val;
2592 }
2593
2600 uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
2601 {
2602 uint64_t val = nanosecond * 0x80000000Ull;
2603 val /= 1000000000U;
2604 return (uint32_t)val;
2605 }
2606
2616 void enet_ptp_feature_enable(uint32_t feature)
2617 {
2618 ENET_PTP_TSCTL |= feature;
2619 }
2620
2630 void enet_ptp_feature_disable(uint32_t feature)
2631 {
2632 ENET_PTP_TSCTL &= ~feature;
2633 }
2634
2647 ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
2648 {
2649 uint32_t temp_config = 0U, temp_state = 0U;
2650 uint32_t timeout = 0U;
2651 ErrStatus enet_state = SUCCESS;
2652
2653 switch(func){
2654 case ENET_PTP_ADDEND_UPDATE:
2655 /* this bit must be read as zero before application set it */
2656 do{
2657 temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU;
2658 timeout++;
2659 }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
2660 /* return ERROR due to timeout */
2661 if(ENET_DELAY_TO == timeout){
2662 enet_state = ERROR;
2663 }else{
2664 ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU;
2665 }
2666 break;
2667 case ENET_PTP_SYSTIME_UPDATE:
2668 /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */
2669 do{
2670 temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI);
2671 timeout++;
2672 }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
2673 /* return ERROR due to timeout */
2674 if(ENET_DELAY_TO == timeout){
2675 enet_state = ERROR;
2676 }else{
2677 ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU;
2678 }
2679 break;
2680 case ENET_PTP_SYSTIME_INIT:
2681 /* this bit must be read as zero before application set it */
2682 do{
2683 temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI;
2684 timeout++;
2685 }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
2686 /* return ERROR due to timeout */
2687 if(ENET_DELAY_TO == timeout){
2688 enet_state = ERROR;
2689 }else{
2690 ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI;
2691 }
2692 break;
2693 default:
2694 temp_config = (uint32_t)func & (~BIT(31));
2695 if(RESET != ((uint32_t)func & BIT(31))){
2696 ENET_PTP_TSCTL |= temp_config;
2697 }else{
2698 ENET_PTP_TSCTL &= ~temp_config;
2699 }
2700 break;
2701 }
2702
2703 return enet_state;
2704 }
2705
2713 void enet_ptp_subsecond_increment_config(uint32_t subsecond)
2714 {
2715 ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond);
2716 }
2717
2724 void enet_ptp_timestamp_addend_config(uint32_t add)
2725 {
2726 ENET_PTP_TSADDEND = add;
2727 }
2728
2741 void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
2742 {
2743 ENET_PTP_TSUH = second;
2744 ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond);
2745 }
2746
2754 void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond)
2755 {
2756 ENET_PTP_ETH = second;
2757 ENET_PTP_ETL = nanosecond;
2758 }
2759
2771 void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct)
2772 {
2773 uint32_t temp_sec = 0U, temp_subs = 0U;
2774
2775 /* get the value of sysytem time registers */
2776 temp_sec = (uint32_t)ENET_PTP_TSH;
2777 temp_subs = (uint32_t)ENET_PTP_TSL;
2778
2779 /* get sysytem time and construct the enet_ptp_systime_struct structure */
2780 systime_struct->second = temp_sec;
2781 systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs);
2782 systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond);
2783 systime_struct->sign = GET_PTP_TSL_STS(temp_subs);
2784 }
2785
2798 void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg)
2799 {
2800 /* mask the timestamp trigger interrupt */
2801 enet_interrupt_disable(ENET_MAC_INT_TMSTIM);
2802
2803 /* enable timestamp */
2804 enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP);
2805
2806 /* configure system time subsecond increment based on the PTP clock frequency */
2807 enet_ptp_subsecond_increment_config(accuracy_cfg);
2808
2809 if(ENET_PTP_FINEMODE == updatemethod){
2810 /* fine correction method: configure the timestamp addend, then update */
2811 enet_ptp_timestamp_addend_config(carry_cfg);
2812 enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
2813 /* wait until update is completed */
2814 while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){
2815 }
2816 }
2817
2818 /* choose the fine correction method */
2819 enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod);
2820
2821 /* initialize the system time */
2822 enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec);
2823 enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
2824 }
2825
2832 void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg)
2833 {
2834 /* re-configure the timestamp addend, then update */
2835 enet_ptp_timestamp_addend_config((uint32_t)carry_cfg);
2836 enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
2837 }
2838
2850 void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct)
2851 {
2852 uint32_t subsecond_val;
2853 uint32_t carry_cfg;
2854
2855 subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
2856
2857 /* save the carry_cfg value */
2858 carry_cfg = ENET_PTP_TSADDEND_TMSA;
2859
2860 /* update the system time */
2861 enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
2862 enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE);
2863
2864 /* wait until the update is completed */
2865 while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){
2866 }
2867
2868 /* write back the carry_cfg value, then update */
2869 enet_ptp_timestamp_addend_config(carry_cfg);
2870 enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
2871 }
2872
2884 void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct)
2885 {
2886 uint32_t subsecond_val;
2887
2888 subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
2889
2890 /* initialize the system time */
2891 enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
2892 enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
2893
2894 /* wait until the system time initialzation finished */
2895 while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){
2896 }
2897 }
2898
2908 FlagStatus enet_ptp_flag_get(uint32_t flag)
2909 {
2910 FlagStatus bitstatus = RESET;
2911
2912 if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){
2913 bitstatus = SET;
2914 }
2915
2916 return bitstatus;
2917 }
2918
2925 void enet_initpara_reset(void)
2926 {
2927 enet_initpara.option_enable = 0U;
2928 enet_initpara.forward_frame = 0U;
2929 enet_initpara.dmabus_mode = 0U;
2930 enet_initpara.dma_maxburst = 0U;
2931 enet_initpara.dma_arbitration = 0U;
2932 enet_initpara.store_forward_mode = 0U;
2933 enet_initpara.dma_function = 0U;
2934 enet_initpara.vlan_config = 0U;
2935 enet_initpara.flow_control = 0U;
2936 enet_initpara.hashtable_high = 0U;
2937 enet_initpara.hashtable_low = 0U;
2938 enet_initpara.framesfilter_mode = 0U;
2939 enet_initpara.halfduplex_param = 0U;
2940 enet_initpara.timer_config = 0U;
2941 enet_initpara.interframegap = 0U;
2942 }
2943
2950 static void enet_default_init(void)
2951 {
2952 uint32_t reg_value = 0U;
2953
2954 /* MAC */
2955 /* configure ENET_MAC_CFG register */
2956 reg_value = ENET_MAC_CFG;
2957 reg_value &= MAC_CFG_MASK;
2958 reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \
2959 | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \
2960 | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \
2961 | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \
2962 | ENET_DEFERRALCHECK_DISABLE \
2963 | ENET_AUTO_PADCRC_DROP_DISABLE \
2964 | ENET_CHECKSUMOFFLOAD_DISABLE;
2965 ENET_MAC_CFG = reg_value;
2966
2967 /* configure ENET_MAC_FRMF register */
2968 ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \
2969 |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \
2970 |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \
2971 |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE;
2972
2973 /* configure ENET_MAC_HLH, ENET_MAC_HLL register */
2974 ENET_MAC_HLH = 0x0U;
2975
2976 ENET_MAC_HLL = 0x0U;
2977
2978 /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */
2979 reg_value = ENET_MAC_FCTL;
2980 reg_value &= MAC_FCTL_MASK;
2981 reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \
2982 |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \
2983 |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE;
2984 ENET_MAC_FCTL = reg_value;
2985
2986 ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES;
2987
2988 /* configure ENET_MAC_VLT register */
2989 ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0);
2990
2991 /* DMA */
2992 /* configure ENET_DMA_CTL register */
2993 reg_value = ENET_DMA_CTL;
2994 reg_value &= DMA_CTL_MASK;
2995 reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \
2996 |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \
2997 |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \
2998 |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \
2999 |ENET_SECONDFRAME_OPT_DISABLE;
3000 ENET_DMA_CTL = reg_value;
3001
3002 /* configure ENET_DMA_BCTL register */
3003 reg_value = ENET_DMA_BCTL;
3004 reg_value &= DMA_BCTL_MASK;
3005 reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \
3006 |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \
3007 |ENET_FIXED_BURST_ENABLE;
3008 ENET_DMA_BCTL = reg_value;
3009 }
3010
3011 #ifndef USE_DELAY
3012
3018 static void enet_delay(uint32_t ncount)
3019 {
3020 uint32_t delay_time = 0U;
3021
3022 for(delay_time = ncount; delay_time != 0U; delay_time--){
3023 }
3024 }
3025 #endif /* USE_DELAY */
3026
3027 #endif /* GD32F10X_CL */
ENET_DMA_MFBOCNT
#define ENET_DMA_MFBOCNT
Definition: gd32f10x_enet.h:147
HALFDUPLEX_OPTION
Definition: gd32f10x_enet.h:755
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void enet_address_filter_disable(enet_macaddress_enum mac_addr)
disable the MAC address filter
Definition: gd32f10x_enet.c:1348
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#define ENET_RXBUF_NUM
Definition: gd32f10x_enet.h:25
ENET_RETRYTRANSMISSION_ENABLE
#define ENET_RETRYTRANSMISSION_ENABLE
Definition: gd32f10x_enet.h:917
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Definition: gd32f10x_rcu.h:441
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#define ENET_TX_FLOWCONTROL_DISABLE
Definition: gd32f10x_enet.h:999
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Definition: gd32f10x_enet.h:1128
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Definition: gd32f10x_enet.h:117
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#define ENET_WATCHDOG_ENABLE
Definition: gd32f10x_enet.h:893
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#define ENET_MAC_CFG_DPM
Definition: gd32f10x_enet.h:162
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Definition: gd32f10x_enet.h:508
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Definition: gd32f10x_enet.h:1244
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ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept)
initialize ENET peripheral with generally concerned parameters and the less cared parameters ...
Definition: gd32f10x_enet.c:280
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void enet_forward_feature_disable(uint32_t feature)
disable ENET forward feature
Definition: gd32f10x_enet.c:1568
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#define ENET_DMA_CTL_DAFRF
Definition: gd32f10x_enet.h:409
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#define ENET_RDES1_DINTC
Definition: gd32f10x_enet.h:511
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Definition: gd32f10x_enet.h:322
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Definition: gd32f10x_enet.h:142
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#define ENET_DMA_CTL_STE
Definition: gd32f10x_enet.h:405
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void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag)
set the bit flag of ENET DMA descriptor
Definition: gd32f10x_enet.c:1996
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#define ENET_DMA_CTL_SRE
Definition: gd32f10x_enet.h:400
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#define DMA_BCTL_MASK
Definition: gd32f10x_enet.h:1238
ENET_DMA_BCTL_RTPR
#define ENET_DMA_BCTL_RTPR
Definition: gd32f10x_enet.h:357
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#define ENET_DMA_BCTL_DPSL
Definition: gd32f10x_enet.h:355
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#define ENET_FORWARD_ERRFRAMES
Definition: gd32f10x_enet.h:1185
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Definition: gd32f10x_enet.h:180
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#define ETH_DMATXDESC_SIZE
Definition: gd32f10x_enet.h:1240
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#define ENET_SECONDFRAME_OPT_DISABLE
Definition: gd32f10x_enet.h:1192
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#define ENET_MAC_FCTL
Definition: gd32f10x_enet.h:101
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#define PHY_AUTONEGOTIATION
Definition: gd32f10x_enet.h:68
DMABUS_OPTION
Definition: gd32f10x_enet.h:745
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#define ENET_RXTX_TIMESTAMP
Definition: gd32f10x_enet.h:1063
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#define ENET_MAX_FRAME_SIZE
Definition: gd32f10x_enet.h:1256
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enet_phydirection_enum
Definition: gd32f10x_enet.h:806
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Definition: gd32f10x_enet.c:41
enet_ptp_coarsecorrection_systime_update
void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct)
update system time in coarse method
Definition: gd32f10x_enet.c:2850
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#define ENET_MSC_CTL_CTR
Definition: gd32f10x_enet.h:275
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#define ENET_MAC_FRMF_SAIFLT
Definition: gd32f10x_enet.h:179
HASHL_OPTION
Definition: gd32f10x_enet.h:753
ENET_MAC_FCTL_FLCBBKPA
#define ENET_MAC_FCTL_FLCBBKPA
Definition: gd32f10x_enet.h:201
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#define PHY_RESETDELAY
Definition: gd32f10x_enet.h:54
ENET_MAC_FCTH
#define ENET_MAC_FCTH
Definition: gd32f10x_enet.h:102
enet_rxframe_size_get
uint32_t enet_rxframe_size_get(void)
check receive frame valid and return frame size
Definition: gd32f10x_enet.c:591
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uint32_t dmabus_mode
Definition: gd32f10x_enet.h:844
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#define PHY_DUPLEX_STATUS
Definition: gd32f10x_enet.h:85
enet_phyloopback_enable
ErrStatus enet_phyloopback_enable(void)
enable the loopback function of PHY chip
Definition: gd32f10x_enet.c:1497
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#define ENET_PTP_TSCTL_TMSARU
Definition: gd32f10x_enet.h:324
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#define ENET_MAC_FRMF_HMF
Definition: gd32f10x_enet.h:174
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#define ENET_MAC_ADDR1H_SAF
Definition: gd32f10x_enet.h:250
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adjusting the clock frequency only in fine update mode
Definition: gd32f10x_enet.c:2724
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void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[])
get MAC address
Definition: gd32f10x_enet.c:996
enet_dma_feature_enable
void enet_dma_feature_enable(uint32_t feature)
enable DMA feature
Definition: gd32f10x_enet.c:2091
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
enet_msc_counter_enum
enet_msc_counter_enum
Definition: gd32f10x_enet.h:731
ENET_MAC_FRMF_DAIFLT
#define ENET_MAC_FRMF_DAIFLT
Definition: gd32f10x_enet.h:175
enet_wum_filter_config
void enet_wum_filter_config(uint32_t pdata[])
set the remote wakeup frame registers
Definition: gd32f10x_enet.c:2480
ENET_DMA_CTL_FERF
#define ENET_DMA_CTL_FERF
Definition: gd32f10x_enet.h:404
ENET_TCPIP_CKSUMERROR_DROP
#define ENET_TCPIP_CKSUMERROR_DROP
Definition: gd32f10x_enet.h:1171
enet_transmit_checksum_config
void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum)
configure the transmit IP frame checksum offload calculation and insertion
Definition: gd32f10x_enet.c:935
ENET_DELAY_TO
#define ENET_DELAY_TO
Definition: gd32f10x_enet.h:1259
FLOWCTL_OPTION
Definition: gd32f10x_enet.h:751
DMA_INTEN_REG_OFFSET
#define DMA_INTEN_REG_OFFSET
Definition: gd32f10x_enet.h:553
ENET_DMA_CTL_RTHC
#define ENET_DMA_CTL_RTHC
Definition: gd32f10x_enet.h:402
ENET_MAC_VLT_VLTC
#define ENET_MAC_VLT_VLTC
Definition: gd32f10x_enet.h:215
enet_current_desc_address_get
uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get)
get the transmit/receive address of current descriptor, or current buffer, or descriptor table ...
Definition: gd32f10x_enet.c:1846
enet_rx_desc_immediate_receive_complete_interrupt
void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc)
when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set ...
Definition: gd32f10x_enet.c:2032
ENET_PTP_ADD_TO_TIME
#define ENET_PTP_ADD_TO_TIME
Definition: gd32f10x_enet.h:1080
enet_wum_feature_disable
void enet_wum_feature_disable(uint32_t feature)
disable wakeup management features
Definition: gd32f10x_enet.c:2514
enet_ptp_flag_get
FlagStatus enet_ptp_flag_get(uint32_t flag)
get the ptp flag status
Definition: gd32f10x_enet.c:2908
enet_wum_filter_register_pointer_reset
void enet_wum_filter_register_pointer_reset(void)
wakeup frame filter register pointer reset
Definition: gd32f10x_enet.c:2469
ENET_UNIQUE_PAUSEDETECT
#define ENET_UNIQUE_PAUSEDETECT
Definition: gd32f10x_enet.h:992
enet_int_enum
enet_int_enum
Definition: gd32f10x_enet.h:629
ENET_RDES0_PCERR
#define ENET_RDES0_PCERR
Definition: gd32f10x_enet.h:486
ENET_ADDRH_BASE
#define ENET_ADDRH_BASE
Definition: gd32f10x_enet.h:531
PHY_SR
#define PHY_SR
Definition: gd32f10x_enet.h:83
ENET_RANGE
#define ENET_RANGE(hclk, n, m)
Definition: gd32f10x_enet.h:526
ENET_MAC_CFG
#define ENET_MAC_CFG
Definition: gd32f10x_enet.h:95
enet_phyloopback_disable
ErrStatus enet_phyloopback_disable(void)
disable the loopback function of PHY chip
Definition: gd32f10x_enet.c:1520
PHY_REG_BCR
#define PHY_REG_BCR
Definition: gd32f10x_enet.h:58
PHY_LOOPBACK
#define PHY_LOOPBACK
Definition: gd32f10x_enet.h:63
ENET_DMA_BCTL_DAB
#define ENET_DMA_BCTL_DAB
Definition: gd32f10x_enet.h:354
enet_desc_flag_get
FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag)
get the bit flag of ENET DMA descriptor
Definition: gd32f10x_enet.c:1965
ENET_RDES1_RERM
#define ENET_RDES1_RERM
Definition: gd32f10x_enet.h:509
enet_address_filter_enable
void enet_address_filter_enable(enet_macaddress_enum mac_addr)
enable the MAC address filter
Definition: gd32f10x_enet.c:1333
ENET_MAC_HLL
#define ENET_MAC_HLL
Definition: gd32f10x_enet.h:98
enet_desc_reg_enum
enet_desc_reg_enum
Definition: gd32f10x_enet.h:720
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
ENET_RX_MODE_STOREFORWARD
#define ENET_RX_MODE_STOREFORWARD
Definition: gd32f10x_enet.h:1173
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
enet_initpara_struct::dma_arbitration
uint32_t dma_arbitration
Definition: gd32f10x_enet.h:846
enet_initpara_struct::interframegap
uint32_t interframegap
Definition: gd32f10x_enet.h:856
enet_interrupt_flag_clear
void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear)
clear ENET DMA interrupt flag
Definition: gd32f10x_enet.c:1236
ENET_BACKOFFLIMIT_10
#define ENET_BACKOFFLIMIT_10
Definition: gd32f10x_enet.h:878
ENET_DMA_STAT_TU
#define ENET_DMA_STAT_TU
Definition: gd32f10x_enet.h:382
ENET_MAC_PHY_CTL_PA
#define ENET_MAC_PHY_CTL_PA
Definition: gd32f10x_enet.h:195
enet_descriptors_ring_init
void enet_descriptors_ring_init(enet_dmadirection_enum direction)
initialize the DMA Tx/Rx descriptors's parameters in ring mode
Definition: gd32f10x_enet.c:719
enet_ptp_systime_struct::sign
uint32_t sign
Definition: gd32f10x_enet.h:873
ENET_TDES0_TERM
#define ENET_TDES0_TERM
Definition: gd32f10x_enet.h:465
enet_msc_counters_get
uint32_t enet_msc_counters_get(enet_msc_counter_enum counter)
get MAC statistics counter
Definition: gd32f10x_enet.c:2572
ENET_RX_FILTER_ENABLE
#define ENET_RX_FILTER_ENABLE
Definition: gd32f10x_enet.h:935
ENET_DMA_CTL
#define ENET_DMA_CTL
Definition: gd32f10x_enet.h:145
enet_rxframe_drop
void enet_rxframe_drop(void)
drop current receive frame
Definition: gd32f10x_enet.c:2043
ENET_TX_MODE_STOREFORWARD
#define ENET_TX_MODE_STOREFORWARD
Definition: gd32f10x_enet.h:1180
ENET_DMA_BCTL_SWR
#define ENET_DMA_BCTL_SWR
Definition: gd32f10x_enet.h:353
ENET_TXBUF_SIZE
#define ENET_TXBUF_SIZE
Definition: gd32f10x_enet.h:37
ENET_MAC_PHY_CTL
#define ENET_MAC_PHY_CTL
Definition: gd32f10x_enet.h:99
ENET_MODE_FULLDUPLEX
#define ENET_MODE_FULLDUPLEX
Definition: gd32f10x_enet.h:911
GET_TDES0_COCNT
#define GET_TDES0_COCNT(regval)
Definition: gd32f10x_enet.h:1202
ENET_DMA_STAT_TBU
#define ENET_DMA_STAT_TBU
Definition: gd32f10x_enet.h:379
ENET_DMA_CTL_TTHC
#define ENET_DMA_CTL_TTHC
Definition: gd32f10x_enet.h:406
GET_RDES0_FRML
#define GET_RDES0_FRML(regval)
Definition: gd32f10x_enet.h:1217
enet_frame_transmit
ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length)
handle application buffer data to transmit it
Definition: gd32f10x_enet.c:864
ENET_BIT_POS
#define ENET_BIT_POS(val)
Definition: gd32f10x_enet.h:523
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
enet_pauseframe_generate
ErrStatus enet_pauseframe_generate(void)
generate the pause frame, ENET will send pause frame after enable transmit flow control this function...
Definition: gd32f10x_enet.c:1624
enet_phy_config
ErrStatus enet_phy_config(void)
PHY interface configuration (configure SMI clock and reset PHY chip)
Definition: gd32f10x_enet.c:1394
GET_DMA_BCTL_DPSL
#define GET_DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1085
enet_initpara_struct::hashtable_high
uint32_t hashtable_high
Definition: gd32f10x_enet.h:851
MAC_PHY_CTL_PR
#define MAC_PHY_CTL_PR(regval)
Definition: gd32f10x_enet.h:973
enet_macaddress_enum
enet_macaddress_enum
Definition: gd32f10x_enet.h:820
enet_initpara_struct::halfduplex_param
uint32_t halfduplex_param
Definition: gd32f10x_enet.h:854
ENET_TDES0_FSG
#define ENET_TDES0_FSG
Definition: gd32f10x_enet.h:470
enet_registers_get
void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num)
put registers value into the application buffer
Definition: gd32f10x_enet.c:1304
ENET_TXBUF_NUM
#define ENET_TXBUF_NUM
Definition: gd32f10x_enet.h:29
enet_msc_feature_disable
void enet_msc_feature_disable(uint32_t feature)
disable the MAC statistics counter features
Definition: gd32f10x_enet.c:2554
ENET_FLUSH_RXFRAME_ENABLE
#define ENET_FLUSH_RXFRAME_ENABLE
Definition: gd32f10x_enet.h:1176
enet_initpara_reset
void enet_initpara_reset(void)
reset the ENET initpara struct, call it before using enet_initpara_config()
Definition: gd32f10x_enet.c:2925
enet_frmrecept_enum
enet_frmrecept_enum
Definition: gd32f10x_enet.h:781
ENET_SPEEDMODE_10M
#define ENET_SPEEDMODE_10M
Definition: gd32f10x_enet.h:902
ENET_MAC_CFG_ROD
#define ENET_MAC_CFG_ROD
Definition: gd32f10x_enet.h:164
ENET_AUTO_PADCRC_DROP_DISABLE
#define ENET_AUTO_PADCRC_DROP_DISABLE
Definition: gd32f10x_enet.h:921
ENET_MAC_FCTL_DZQP
#define ENET_MAC_FCTL_DZQP
Definition: gd32f10x_enet.h:206
enet_flag_clear_enum
enet_flag_clear_enum
Definition: gd32f10x_enet.h:608
enet_forward_feature_enable
void enet_forward_feature_enable(uint32_t feature)
enable ENET forward feature
Definition: gd32f10x_enet.c:1547
ETH_WAKEUP_REGISTER_LENGTH
#define ETH_WAKEUP_REGISTER_LENGTH
Definition: gd32f10x_enet.h:1253
ENET_DMA_TDTADDR
#define ENET_DMA_TDTADDR
Definition: gd32f10x_enet.h:143
ENET_MAC_FRMF_PCFRM
#define ENET_MAC_FRMF_PCFRM
Definition: gd32f10x_enet.h:178
HASHH_OPTION
Definition: gd32f10x_enet.h:752
PHY_RESET
#define PHY_RESET
Definition: gd32f10x_enet.h:62
ENET_MDC_HCLK_DIV16
#define ENET_MDC_HCLK_DIV16
Definition: gd32f10x_enet.h:970
ENET_MDC_HCLK_DIV42
#define ENET_MDC_HCLK_DIV42
Definition: gd32f10x_enet.h:968
enet_mac_address_set
void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[])
configure MAC address
Definition: gd32f10x_enet.c:978
enet_ptp_systime_struct
Definition: gd32f10x_enet.h:869
ENET_DEFERRALCHECK_DISABLE
#define ENET_DEFERRALCHECK_DISABLE
Definition: gd32f10x_enet.h:925
enet_ptp_expected_time_config
void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond)
configure the expected target time
Definition: gd32f10x_enet.c:2754
ENET_PTP_TSUL
#define ENET_PTP_TSUL
Definition: gd32f10x_enet.h:134
ENET_DMA_TPEN
#define ENET_DMA_TPEN
Definition: gd32f10x_enet.h:140
ENET_RX_THRESHOLD_64BYTES
#define ENET_RX_THRESHOLD_64BYTES
Definition: gd32f10x_enet.h:1155
PTP_SSINC_STMSSI
#define PTP_SSINC_STMSSI(regval)
Definition: gd32f10x_enet.h:1067
ENET_MAC_PHY_CTL_PW
#define ENET_MAC_PHY_CTL_PW
Definition: gd32f10x_enet.h:192
ENET_GET_MACADDR
#define ENET_GET_MACADDR(offset, n)
Definition: gd32f10x_enet.h:533
ENET_DMA_CTL_RSFD
#define ENET_DMA_CTL_RSFD
Definition: gd32f10x_enet.h:410
RXDESC_FRAME_LENGTH
Definition: gd32f10x_enet.h:833
enet_ptp_subsecond_2_nanosecond
uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond)
change subsecond to nanosecond
Definition: gd32f10x_enet.c:2587
PHY_LINKED_STATUS
#define PHY_LINKED_STATUS
Definition: gd32f10x_enet.h:75
TXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:832
enet_ptp_feature_enable
void enet_ptp_feature_enable(uint32_t feature)
enable the PTP features
Definition: gd32f10x_enet.c:2616
ENET_DMA_CTL_FUF
#define ENET_DMA_CTL_FUF
Definition: gd32f10x_enet.h:403
ENET_JABBER_ENABLE
#define ENET_JABBER_ENABLE
Definition: gd32f10x_enet.h:896
ENET_DMA_BCTL_FPBL
#define ENET_DMA_BCTL_FPBL
Definition: gd32f10x_enet.h:361
enet_descriptors_chain_init
void enet_descriptors_chain_init(enet_dmadirection_enum direction)
initialize the DMA Tx/Rx descriptors's parameters in chain mode
Definition: gd32f10x_enet.c:647
ENET_FORWARD_ERRFRAMES_DISABLE
#define ENET_FORWARD_ERRFRAMES_DISABLE
Definition: gd32f10x_enet.h:1184
ENET_UNICAST_FILTER_PERFECT
#define ENET_UNICAST_FILTER_PERFECT
Definition: gd32f10x_enet.h:963
ENET_RXDP_32BEAT
#define ENET_RXDP_32BEAT
Definition: gd32f10x_enet.h:1117
TXDESC_COLLISION_COUNT
Definition: gd32f10x_enet.h:831
ENET_SET_MACADDRL
#define ENET_SET_MACADDRL(p)
Definition: gd32f10x_enet.h:530
ENET_MDC_HCLK_DIV62
#define ENET_MDC_HCLK_DIV62
Definition: gd32f10x_enet.h:969
enet_txfifo_flush
ErrStatus enet_txfifo_flush(void)
flush the ENET transmit FIFO, and wait until the flush operation completes
Definition: gd32f10x_enet.c:1810
enet_flowcontrol_feature_disable
void enet_flowcontrol_feature_disable(uint32_t feature)
disable ENET flow control feature
Definition: gd32f10x_enet.c:1734
ENET_PROMISCUOUS_DISABLE
#define ENET_PROMISCUOUS_DISABLE
Definition: gd32f10x_enet.h:951
DMA_MAXBURST_OPTION
Definition: gd32f10x_enet.h:746
enet_initpara_struct::flow_control
uint32_t flow_control
Definition: gd32f10x_enet.h:850
enet_flowcontrol_threshold_config
void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active)
configure the threshold of the flow control(deactive and active threshold)
Definition: gd32f10x_enet.c:1698
GET_RDES1_RB1S
#define GET_RDES1_RB1S(regval)
Definition: gd32f10x_enet.h:1223
enet_fliter_feature_disable
void enet_fliter_feature_disable(uint32_t feature)
disable ENET fliter feature
Definition: gd32f10x_enet.c:1612
GET_RDES1_RB2S
#define GET_RDES1_RB2S(regval)
Definition: gd32f10x_enet.h:1225
ENET_MDC_HCLK_DIV26
#define ENET_MDC_HCLK_DIV26
Definition: gd32f10x_enet.h:971
ENET_REG_VAL
#define ENET_REG_VAL(periph)
Definition: gd32f10x_enet.h:522
ENET_DMA_CTL_TSFD
#define ENET_DMA_CTL_TSFD
Definition: gd32f10x_enet.h:408
RXDESC_BUFFER_1_SIZE
Definition: gd32f10x_enet.h:834
enet_ptp_systime_struct::nanosecond
uint32_t nanosecond
Definition: gd32f10x_enet.h:872
enet_initpara_struct::store_forward_mode
uint32_t store_forward_mode
Definition: gd32f10x_enet.h:847
enet_flag_enum
enet_flag_enum
Definition: gd32f10x_enet.h:562
ENET_MAC_CFG_TEN
#define ENET_MAC_CFG_TEN
Definition: gd32f10x_enet.h:156
DMA_ARBITRATION_OPTION
Definition: gd32f10x_enet.h:747
enet_initpara_struct::dma_function
uint32_t dma_function
Definition: gd32f10x_enet.h:848
ENET_MAC_FCTL_PTM
#define ENET_MAC_FCTL_PTM
Definition: gd32f10x_enet.h:207
enet_pauseframe_config
void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold)
configure the pause frame parameters
Definition: gd32f10x_enet.c:1668
enet_interrupt_disable
void enet_interrupt_disable(enet_int_enum enet_int)
disable ENET MAC/MSC/DMA interrupt
Definition: gd32f10x_enet.c:1158
ENET_MAC_FRMF
#define ENET_MAC_FRMF
Definition: gd32f10x_enet.h:96
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
ENET_DMA_CTL_OSF
#define ENET_DMA_CTL_OSF
Definition: gd32f10x_enet.h:401
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
ENET_CHECKSUMOFFLOAD_DISABLE
#define ENET_CHECKSUMOFFLOAD_DISABLE
Definition: gd32f10x_enet.h:915
ENET_PTP_FINEMODE
Definition: gd32f10x_enet.h:1247
enet_ptp_normal_descriptors_chain_init
void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function ...
Definition: gd32f10x_enet.c:2120
RXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:836
ETH_DMARXDESC_SIZE
#define ETH_DMARXDESC_SIZE
Definition: gd32f10x_enet.h:1241
enet_software_reset
ErrStatus enet_software_reset(void)
reset all core internal registers located in CLK_TX and CLK_RX
Definition: gd32f10x_enet.c:562
_ENET_DELAY_
#define _ENET_DELAY_
Definition: gd32f10x_enet.h:1473
ENET_MODE_HALFDUPLEX
#define ENET_MODE_HALFDUPLEX
Definition: gd32f10x_enet.h:912
enet_ptp_feature_disable
void enet_ptp_feature_disable(uint32_t feature)
disable the PTP features
Definition: gd32f10x_enet.c:2630
ENET_FIXED_BURST_ENABLE
#define ENET_FIXED_BURST_ENABLE
Definition: gd32f10x_enet.h:1108
PHY_READ_TO
#define PHY_READ_TO
Definition: gd32f10x_enet.h:50
GET_DMA_MFBOCNT_MSFC
#define GET_DMA_MFBOCNT_MSFC(regval)
Definition: gd32f10x_enet.h:1196
enet_ptp_nanosecond_2_subsecond
uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
change nanosecond to subsecond
Definition: gd32f10x_enet.c:2600
ENET_MAC_HLH
#define ENET_MAC_HLH
Definition: gd32f10x_enet.h:97
enet_rx_enable
void enet_rx_enable(void)
ENET Rx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1274
enet_rx_disable
void enet_rx_disable(void)
ENET Rx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1286
ENET_DEST_FILTER_INVERSE_DISABLE
#define ENET_DEST_FILTER_INVERSE_DISABLE
Definition: gd32f10x_enet.h:947
ENET_MAC_INT_TMSTIM
Definition: gd32f10x_enet.h:633
enet_frame_receive
ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize)
handle current received frame data to application buffer
Definition: gd32f10x_enet.c:792
enet_ptp_systime_struct::second
uint32_t second
Definition: gd32f10x_enet.h:871
ENET_PAUSETIME_MINUS4
#define ENET_PAUSETIME_MINUS4
Definition: gd32f10x_enet.h:982
MAC_FCTL_MASK
#define MAC_FCTL_MASK
Definition: gd32f10x_enet.h:1236
ENET_DEACTIVE_THRESHOLD_512BYTES
#define ENET_DEACTIVE_THRESHOLD_512BYTES
Definition: gd32f10x_enet.h:1050
ENET_MAC_FCTL_PLTS
#define ENET_MAC_FCTL_PLTS
Definition: gd32f10x_enet.h:205
enet_interrupt_flag_get
FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag)
get ENET MAC/MSC/DMA interrupt flag
Definition: gd32f10x_enet.c:1205
ENET_MULTICAST_FILTER_PERFECT
#define ENET_MULTICAST_FILTER_PERFECT
Definition: gd32f10x_enet.h:955
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
ENET_MAC_FCTL_TFCEN
#define ENET_MAC_FCTL_TFCEN
Definition: gd32f10x_enet.h:202
ENET_ARBITRATION_RXTX_2_1
#define ENET_ARBITRATION_RXTX_2_1
Definition: gd32f10x_enet.h:1103
enet_initpara_struct::hashtable_low
uint32_t hashtable_low
Definition: gd32f10x_enet.h:852
ENET_MAC_PHY_CTL_PR
#define ENET_MAC_PHY_CTL_PR
Definition: gd32f10x_enet.h:194
MAC_PHY_CTL_PA
#define MAC_PHY_CTL_PA(regval)
Definition: gd32f10x_enet.h:975
ENET_SET_MACADDRH
#define ENET_SET_MACADDRH(p)
Definition: gd32f10x_enet.h:529
enet_ptp_normal_descriptors_ring_init
void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function ...
Definition: gd32f10x_enet.c:2199
ENET_BROADCASTFRAMES_ENABLE
#define ENET_BROADCASTFRAMES_ENABLE
Definition: gd32f10x_enet.h:943
PHY_CONFIGDELAY
#define PHY_CONFIGDELAY
Definition: gd32f10x_enet.h:55
ENET_PCFRM_PREVENT_ALL
#define ENET_PCFRM_PREVENT_ALL
Definition: gd32f10x_enet.h:929
enet_dmadirection_enum
enet_dmadirection_enum
Definition: gd32f10x_enet.h:799
ENET_RDES0_FRMT
#define ENET_RDES0_FRMT
Definition: gd32f10x_enet.h:491
enet_ptpframe_receive_normal_mode
ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[])
receive a packet data with timestamp values to application buffer, when the DMA is in normal mode ...
Definition: gd32f10x_enet.c:2281
ENET_DMA_CRDADDR
#define ENET_DMA_CRDADDR
Definition: gd32f10x_enet.h:149
ENET_MAC_RWFF
#define ENET_MAC_RWFF
Definition: gd32f10x_enet.h:104
ENET_PTP_TSADDEND
#define ENET_PTP_TSADDEND
Definition: gd32f10x_enet.h:135
STORE_OPTION
Definition: gd32f10x_enet.h:748
enet_msc_feature_enable
void enet_msc_feature_enable(uint32_t feature)
enable the MAC statistics counter features
Definition: gd32f10x_enet.c:2540
ENET_MAC_WUM_WUFFRPR
#define ENET_MAC_WUM_WUFFRPR
Definition: gd32f10x_enet.h:227
enet_dmaprocess_state_get
uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction)
get the dma transmit/receive process state
Definition: gd32f10x_enet.c:1756
ENET_DMA_STAT_RBU
#define ENET_DMA_STAT_RBU
Definition: gd32f10x_enet.h:384
ENET_AUTO_PADCRC_DROP
#define ENET_AUTO_PADCRC_DROP
Definition: gd32f10x_enet.h:922
ENET_PTP_TSCTL
#define ENET_PTP_TSCTL
Definition: gd32f10x_enet.h:129
ENET_RDES0_FDES
#define ENET_RDES0_FDES
Definition: gd32f10x_enet.h:495
enet_pauseframe_detect_config
void enet_pauseframe_detect_config(uint32_t detect)
configure the pause frame detect type
Definition: gd32f10x_enet.c:1649
dma_current_ptp_txdesc
enet_descriptors_struct * dma_current_ptp_txdesc
Definition: gd32f10x_enet.c:44
enet_fliter_feature_enable
void enet_fliter_feature_enable(uint32_t feature)
enable ENET fliter feature
Definition: gd32f10x_enet.c:1593
TIMER_OPTION
Definition: gd32f10x_enet.h:756
INTERFRAMEGAP_OPTION
Definition: gd32f10x_enet.h:757
PHY_SPEED_STATUS
#define PHY_SPEED_STATUS
Definition: gd32f10x_enet.h:84
ENET_ZERO_QUANTA_PAUSE
#define ENET_ZERO_QUANTA_PAUSE
Definition: gd32f10x_enet.h:989
ENET_INTERFRAMEGAP_96BIT
#define ENET_INTERFRAMEGAP_96BIT
Definition: gd32f10x_enet.h:884
ENET_AUTO_NEGOTIATION
Definition: gd32f10x_enet.h:763
ENET_DMA_BCTL_FB
#define ENET_DMA_BCTL_FB
Definition: gd32f10x_enet.h:358
ENET_MAC_ADDR1H_MB
#define ENET_MAC_ADDR1H_MB
Definition: gd32f10x_enet.h:249
ENET_MAC_FRMF_HPFLT
#define ENET_MAC_FRMF_HPFLT
Definition: gd32f10x_enet.h:181
ENET_TDES0_TTSEN
#define ENET_TDES0_TTSEN
Definition: gd32f10x_enet.h:467
ENET_DMA_BCTL_PGBL
#define ENET_DMA_BCTL_PGBL
Definition: gd32f10x_enet.h:356
ENET
#define ENET
Definition: gd32f10x_enet.h:92
ENET_PTP_TSUH
#define ENET_PTP_TSUH
Definition: gd32f10x_enet.h:133
enet_ptp_timestamp_update_config
void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time
Definition: gd32f10x_enet.c:2741
enet_missed_frame_counter_get
void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop)
get the number of missed frames during receiving
Definition: gd32f10x_enet.c:1906
VLAN_OPTION
Definition: gd32f10x_enet.h:750
enet_initpara_struct::forward_frame
uint32_t forward_frame
Definition: gd32f10x_enet.h:843
dma_current_ptp_rxdesc
enet_descriptors_struct * dma_current_ptp_rxdesc
Definition: gd32f10x_enet.c:45
enet_option_enum
enet_option_enum
Definition: gd32f10x_enet.h:742
enet_initpara_config
void enet_initpara_config(enet_option_enum option, uint32_t para)
configure the parameters which are usually less cared for initialization note – this function must b...
Definition: gd32f10x_enet.c:176
ENET_MAC_CFG_BOL
#define ENET_MAC_CFG_BOL
Definition: gd32f10x_enet.h:158
MAC_VLT_VLTI
#define MAC_VLT_VLTI(regval)
Definition: gd32f10x_enet.h:1008
enet_dma_feature_disable
void enet_dma_feature_disable(uint32_t feature)
disable DMA feature
Definition: gd32f10x_enet.c:2105
enet_flowcontrol_feature_enable
void enet_flowcontrol_feature_enable(uint32_t feature)
enable ENET flow control feature
Definition: gd32f10x_enet.c:1714
ENET_PGBL_32BEAT
#define ENET_PGBL_32BEAT
Definition: gd32f10x_enet.h:1093
ENET_MAC_CFG_APCD
#define ENET_MAC_CFG_APCD
Definition: gd32f10x_enet.h:159
ENET_SRC_FILTER_DISABLE
#define ENET_SRC_FILTER_DISABLE
Definition: gd32f10x_enet.h:939
ENET_MAC_WUM
#define ENET_MAC_WUM
Definition: gd32f10x_enet.h:105
ENET_DMA_BCTL_RXDP
#define ENET_DMA_BCTL_RXDP
Definition: gd32f10x_enet.h:359
enet_ptp_function_enum
enet_ptp_function_enum
Definition: gd32f10x_enet.h:1243
enet_tx_disable
void enet_tx_disable(void)
ENET Tx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1261
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
GET_DMA_MFBOCNT_MSFA
#define GET_DMA_MFBOCNT_MSFA(regval)
Definition: gd32f10x_enet.h:1198
ENET_VLANTAGCOMPARISON_16BIT
#define ENET_VLANTAGCOMPARISON_16BIT
Definition: gd32f10x_enet.h:1011
DMA_BCTL_DPSL
#define DMA_BCTL_DPSL(regval)
Definition: gd32f10x_enet.h:1084
ENET_ZERO_QUANTA_PAUSE_DISABLE
#define ENET_ZERO_QUANTA_PAUSE_DISABLE
Definition: gd32f10x_enet.h:988
ENET_PTP_TSL
#define ENET_PTP_TSL
Definition: gd32f10x_enet.h:132
enet_ptp_finecorrection_adjfreq
void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg)
adjust frequency in fine method by configure addend register
Definition: gd32f10x_enet.c:2832
enet_initpara_struct::timer_config
uint32_t timer_config
Definition: gd32f10x_enet.h:855
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
ENET_DMA_CTL_FTF
#define ENET_DMA_CTL_FTF
Definition: gd32f10x_enet.h:407
CK_AHB
Definition: gd32f10x_rcu.h:585
ENET_MAC_FCTL_RFCEN
#define ENET_MAC_FCTL_RFCEN
Definition: gd32f10x_enet.h:203
enet_wum_feature_enable
void enet_wum_feature_enable(uint32_t feature)
enable wakeup management features
Definition: gd32f10x_enet.c:2500
ENET_MAC_CFG_SPD
#define ENET_MAC_CFG_SPD
Definition: gd32f10x_enet.h:165
ENET_RDES0_DAV
#define ENET_RDES0_DAV
Definition: gd32f10x_enet.h:504
enet_flag_get
FlagStatus enet_flag_get(enet_flag_enum enet_flag)
get the ENET MAC/MSC/PTP/DMA status flag
Definition: gd32f10x_enet.c:1050
ENET_DMA_BCTL
#define ENET_DMA_BCTL
Definition: gd32f10x_enet.h:139
DMA_OPTION
Definition: gd32f10x_enet.h:749
enet_descstate_enum
enet_descstate_enum
Definition: gd32f10x_enet.h:829
enet_address_filter_config
void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type)
configure the MAC address filter
Definition: gd32f10x_enet.c:1375
enet_initpara_struct::option_enable
uint32_t option_enable
Definition: gd32f10x_enet.h:842
ENET_CHECKSUMOFFLOAD_ENABLE
#define ENET_CHECKSUMOFFLOAD_ENABLE
Definition: gd32f10x_enet.h:914
enet_msc_counters_reset
void enet_msc_counters_reset(void)
reset the MAC statistics counters
Definition: gd32f10x_enet.c:2525
ENET_DMA_RPEN
#define ENET_DMA_RPEN
Definition: gd32f10x_enet.h:141
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
ENET_MAC_CFG_WDD
#define ENET_MAC_CFG_WDD
Definition: gd32f10x_enet.h:169
ENET_DMA_BCTL_UIP
#define ENET_DMA_BCTL_UIP
Definition: gd32f10x_enet.h:360
ENET_MAC_FCTL_UPFDT
#define ENET_MAC_FCTL_UPFDT
Definition: gd32f10x_enet.h:204
PHY_REG_BSR
#define PHY_REG_BSR
Definition: gd32f10x_enet.h:59
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_RDES0_ERRS
#define ENET_RDES0_ERRS
Definition: gd32f10x_enet.h:501
ENET_MAC_FCTH_RFD
#define ENET_MAC_FCTH_RFD
Definition: gd32f10x_enet.h:211
ENET_DMA_CTL_DTCERFD
#define ENET_DMA_CTL_DTCERFD
Definition: gd32f10x_enet.h:411
enet_initpara_struct
Definition: gd32f10x_enet.h:840
ENET_DMA_BCTL_AA
#define ENET_DMA_BCTL_AA
Definition: gd32f10x_enet.h:362
enet_ptp_start
void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg)
configure and start PTP timestamp counter
Definition: gd32f10x_enet.c:2798
PHY_AUTONEGO_COMPLETE
#define PHY_AUTONEGO_COMPLETE
Definition: gd32f10x_enet.h:74
enet_initpara_struct::vlan_config
uint32_t vlan_config
Definition: gd32f10x_enet.h:849
enet_tx_enable
void enet_tx_enable(void)
ENET Tx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1248
enet_flag_clear
void enet_flag_clear(enet_flag_clear_enum enet_flag)
clear the ENET DMA status flag
Definition: gd32f10x_enet.c:1081
PHY_ADDRESS
#define PHY_ADDRESS
Definition: gd32f10x_enet.h:47
ENET_MAC_CFG_IGBS
#define ENET_MAC_CFG_IGBS
Definition: gd32f10x_enet.h:167
enet_enable
void enet_enable(void)
ENET Tx and Rx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:947
ENET_TDES0_TCHM
#define ENET_TDES0_TCHM
Definition: gd32f10x_enet.h:464
ENET_MAC_CFG_RTD
#define ENET_MAC_CFG_RTD
Definition: gd32f10x_enet.h:160
NULL
#define NULL
Definition: usbd_std.h:20
ENET_TDES0_TTMSS
#define ENET_TDES0_TTMSS
Definition: gd32f10x_enet.h:463
enet_ptp_system_time_get
void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct)
get the current system time
Definition: gd32f10x_enet.c:2771
enet_initpara_struct::dma_maxburst
uint32_t dma_maxburst
Definition: gd32f10x_enet.h:845
RXDESC_BUFFER_2_SIZE
Definition: gd32f10x_enet.h:835
ENET_PTP_ETH
#define ENET_PTP_ETH
Definition: gd32f10x_enet.h:136
ENET_MAC_CFG_CSD
#define ENET_MAC_CFG_CSD
Definition: gd32f10x_enet.h:166
ENET_PTP_TSH
#define ENET_PTP_TSH
Definition: gd32f10x_enet.h:131
ENET_TDES0_LSG
#define ENET_TDES0_LSG
Definition: gd32f10x_enet.h:471
enet_desc_flag_clear
void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag)
clear the bit flag of ENET DMA descriptor
Definition: gd32f10x_enet.c:2021
GET_PTP_TSL_STMSS
#define GET_PTP_TSL_STMSS(regval)
Definition: gd32f10x_enet.h:1070
enet_deinit
void enet_deinit(void)
deinitialize the ENET, and reset structure parameters for ENET initialization
Definition: gd32f10x_enet.c:69
enet_int_flag_enum
enet_int_flag_enum
Definition: gd32f10x_enet.h:661
ENET_PTP_SSINC
#define ENET_PTP_SSINC
Definition: gd32f10x_enet.h:130
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_RXTX_DIFFERENT_PGBL
#define ENET_RXTX_DIFFERENT_PGBL
Definition: gd32f10x_enet.h:1125
ENET_PTP_TSCTL_TMSSTI
#define ENET_PTP_TSCTL_TMSSTI
Definition: gd32f10x_enet.h:321
enet_ptp_subsecond_increment_config
void enet_ptp_subsecond_increment_config(uint32_t subsecond)
configure system time subsecond increment value
Definition: gd32f10x_enet.c:2713
ENET_MAC_PHY_CTL_CLR
#define ENET_MAC_PHY_CTL_CLR
Definition: gd32f10x_enet.h:193
PTP_TSUL_TMSUSS
#define PTP_TSUL_TMSUSS(regval)
Definition: gd32f10x_enet.h:1078
enet_disable
void enet_disable(void)
ENET Tx and Rx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:959
FORWARD_OPTION
Definition: gd32f10x_enet.h:744
ENET_MAC_ADDR1H_AFE
#define ENET_MAC_ADDR1H_AFE
Definition: gd32f10x_enet.h:251
ENET_DMA_STAT
#define ENET_DMA_STAT
Definition: gd32f10x_enet.h:144
ENET_RECEIVEOWN_ENABLE
#define ENET_RECEIVEOWN_ENABLE
Definition: gd32f10x_enet.h:905
MAC_FCTL_PTM
#define MAC_FCTL_PTM(regval)
Definition: gd32f10x_enet.h:1006
ENET_MAC_FRMF_MFD
#define ENET_MAC_FRMF_MFD
Definition: gd32f10x_enet.h:176
ENET_TDES0_DAV
#define ENET_TDES0_DAV
Definition: gd32f10x_enet.h:473
enet_desc_information_get
uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get)
get the Tx or Rx descriptor information
Definition: gd32f10x_enet.c:1868
ENET_RXBUF_SIZE
#define ENET_RXBUF_SIZE
Definition: gd32f10x_enet.h:33
ENET_TDES0_CM
#define ENET_TDES0_CM
Definition: gd32f10x_enet.h:466
ENET_SPEEDMODE_100M
#define ENET_SPEEDMODE_100M
Definition: gd32f10x_enet.h:903
ENET_PTP_ETL
#define ENET_PTP_ETL
Definition: gd32f10x_enet.h:137
ENET_CARRIERSENSE_ENABLE
#define ENET_CARRIERSENSE_ENABLE
Definition: gd32f10x_enet.h:899
ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE
#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE
Definition: gd32f10x_enet.h:1188
ENET_MAC_PHY_CTL_PB
#define ENET_MAC_PHY_CTL_PB
Definition: gd32f10x_enet.h:191
enet_dmaprocess_resume
void enet_dmaprocess_resume(enet_dmadirection_enum direction)
poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN re...
Definition: gd32f10x_enet.c:1773
enet_ptp_finecorrection_settime
void enet_ptp_finecorrection_settime(enet_ptp_systime_struct *systime_struct)
set system time in fine method
Definition: gd32f10x_enet.c:2884
ENET_MAC_VLT
#define ENET_MAC_VLT
Definition: gd32f10x_enet.h:103
ENET_RX_FLOWCONTROL_DISABLE
#define ENET_RX_FLOWCONTROL_DISABLE
Definition: gd32f10x_enet.h:995
enet_ptpframe_transmit_normal_mode
ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[])
send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal...
Definition: gd32f10x_enet.c:2372
ENET_FORWARD_UNDERSZ_GOODFRAMES
#define ENET_FORWARD_UNDERSZ_GOODFRAMES
Definition: gd32f10x_enet.h:1189
enet_rxprocess_check_recovery
void enet_rxprocess_check_recovery(void)
check and recover the Rx process
Definition: gd32f10x_enet.c:1788
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
ENET_TX_THRESHOLD_64BYTES
#define ENET_TX_THRESHOLD_64BYTES
Definition: gd32f10x_enet.h:1161
enet_registers_type_enum
enet_registers_type_enum
Definition: gd32f10x_enet.h:790
enet_chksumconf_enum
enet_chksumconf_enum
Definition: gd32f10x_enet.h:772
ENET_MAC_FCTH_RFA
#define ENET_MAC_FCTH_RFA
Definition: gd32f10x_enet.h:210
GET_PTP_TSL_STS
#define GET_PTP_TSL_STS(regval)
Definition: gd32f10x_enet.h:1075
ENET_MAC_CFG_REN
#define ENET_MAC_CFG_REN
Definition: gd32f10x_enet.h:155
enet_int_flag_clear_enum
enet_int_flag_clear_enum
Definition: gd32f10x_enet.h:699
ENET_MAC_CFG_DFC
#define ENET_MAC_CFG_DFC
Definition: gd32f10x_enet.h:157
enet_initpara_struct::framesfilter_mode
uint32_t framesfilter_mode
Definition: gd32f10x_enet.h:853
enet_interrupt_enable
void enet_interrupt_enable(enet_int_enum enet_int)
enable ENET MAC/MSC/DMA interrupt
Definition: gd32f10x_enet.c:1117
DMA_CTL_MASK
#define DMA_CTL_MASK
Definition: gd32f10x_enet.h:1237
ENET_LOOPBACKMODE_DISABLE
#define ENET_LOOPBACKMODE_DISABLE
Definition: gd32f10x_enet.h:909
ENET_ACTIVE_THRESHOLD_1536BYTES
#define ENET_ACTIVE_THRESHOLD_1536BYTES
Definition: gd32f10x_enet.h:1045
enet_mediamode_enum
enet_mediamode_enum
Definition: gd32f10x_enet.h:761
FILTER_OPTION
Definition: gd32f10x_enet.h:754
ENET_MAC_CFG_JBD
#define ENET_MAC_CFG_JBD
Definition: gd32f10x_enet.h:168
MAC_CFG_MASK
#define MAC_CFG_MASK
Definition: gd32f10x_enet.h:1235
dma_current_txdesc
enet_descriptors_struct * dma_current_txdesc
Definition: gd32f10x_enet.c:40
ENET_MAC_PHY_DATA
#define ENET_MAC_PHY_DATA
Definition: gd32f10x_enet.h:100
ENET_ADDRL_BASE
#define ENET_ADDRL_BASE
Definition: gd32f10x_enet.h:532
ENET_RDES0_LDES
#define ENET_RDES0_LDES
Definition: gd32f10x_enet.h:494
ENET_MAC_VLT_VLTI
#define ENET_MAC_VLT_VLTI
Definition: gd32f10x_enet.h:214
ENET_PTP_TSADDEND_TMSA
#define ENET_PTP_TSADDEND_TMSA
Definition: gd32f10x_enet.h:344
ENET_MAC_CFG_LBM
#define ENET_MAC_CFG_LBM
Definition: gd32f10x_enet.h:163
ENET_PTP_SYSTIME_UPDATE
Definition: gd32f10x_enet.h:1245
ENET_MAC_FRMF_HUF
#define ENET_MAC_FRMF_HUF
Definition: gd32f10x_enet.h:173
gd32f10x_enet.h
definitions for the ENET
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_bkp.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_bkp.h"
14
15 #define TAMPER_FLAG_SHIFT ((uint8_t)8U)
16
23 void bkp_deinit(void)
24 {
25 /* reset BKP domain register*/
26 rcu_bkp_reset_enable();
27 rcu_bkp_reset_disable();
28 }
29
38 void bkp_write_data(bkp_data_register_enum register_number, uint16_t data)
39 {
40 if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
41 BKP_DATA10_41(register_number - 1U) = data;
42 }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
43 BKP_DATA0_9(register_number - 1U) = data;
44 }else{
45 /* illegal parameters */
46 }
47 }
48
56 uint16_t bkp_read_data(bkp_data_register_enum register_number)
57 {
58 uint16_t data = 0U;
59
60 /* get the data from the BKP data register */
61 if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
62 data = BKP_DATA10_41(register_number - 1U);
63 }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
64 data = BKP_DATA0_9(register_number - 1U);
65 }else{
66 /* illegal parameters */
67 }
68 return data;
69 }
70
77 void bkp_rtc_calibration_output_enable(void)
78 {
79 BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
80 }
81
88 void bkp_rtc_calibration_output_disable(void)
89 {
90 BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
91 }
92
99 void bkp_rtc_signal_output_enable(void)
100 {
101 BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
102 }
103
110 void bkp_rtc_signal_output_disable(void)
111 {
112 BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
113 }
114
123 void bkp_rtc_output_select(uint16_t outputsel)
124 {
125 uint16_t ctl = 0U;
126
127 ctl = BKP_OCTL;
128 ctl &= (uint16_t)~BKP_OCTL_ROSEL;
129 ctl |= outputsel;
130 BKP_OCTL = ctl;
131 }
132
140 void bkp_rtc_calibration_value_set(uint8_t value)
141 {
142 uint16_t ctl;
143
144 ctl = BKP_OCTL;
145 ctl &= (uint16_t)OCTL_RCCV(0);
146 ctl |= (uint16_t)OCTL_RCCV(value);
147 BKP_OCTL = ctl;
148 }
149
156 void bkp_tamper_detection_enable(void)
157 {
158 BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN;
159 }
160
167 void bkp_tamper_detection_disable(void)
168 {
169 BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN;
170 }
171
180 void bkp_tamper_active_level_set(uint16_t level)
181 {
182 uint16_t ctl = 0U;
183
184 ctl = BKP_TPCTL;
185 ctl &= (uint16_t)~BKP_TPCTL_TPAL;
186 ctl |= level;
187 BKP_TPCTL = ctl;
188 }
189
196 void bkp_tamper_interrupt_enable(void)
197 {
198 BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE;
199 }
200
207 void bkp_tamper_interrupt_disable(void)
208 {
209 BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE;
210 }
211
219 FlagStatus bkp_flag_get(uint16_t flag)
220 {
221 if(RESET != (BKP_TPCS & flag)){
222 return SET;
223 }else{
224 return RESET;
225 }
226 }
227
235 void bkp_flag_clear(uint16_t flag)
236 {
237 BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT);
238 }
239
247 FlagStatus bkp_interrupt_flag_get(uint16_t flag)
248 {
249 if(RESET != (BKP_TPCS & flag)){
250 return SET;
251 }else{
252 return RESET;
253 }
254 }
255
263 void bkp_interrupt_flag_clear(uint16_t flag)
264 {
265 BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT);
266 }
267
BKP_OCTL
#define BKP_OCTL
Definition: gd32f10x_bkp.h:64
BKP_TPCTL
#define BKP_TPCTL
Definition: gd32f10x_bkp.h:65
OCTL_RCCV
#define OCTL_RCCV(regval)
Definition: gd32f10x_bkp.h:98
rcu_bkp_reset_enable
void rcu_bkp_reset_enable(void)
reset the BKP domain
Definition: gd32f10x_rcu.c:223
TAMPER_FLAG_SHIFT
#define TAMPER_FLAG_SHIFT
Definition: gd32f10x_bkp.c:15
bkp_rtc_output_select
void bkp_rtc_output_select(uint16_t outputsel)
select RTC output
Definition: gd32f10x_bkp.c:123
bkp_rtc_calibration_output_enable
void bkp_rtc_calibration_output_enable(void)
enable RTC clock calibration output
Definition: gd32f10x_bkp.c:77
BKP_DATA10_41
#define BKP_DATA10_41(number)
Definition: gd32f10x_bkp.h:92
BKP_TPCS_TPIE
#define BKP_TPCS_TPIE
Definition: gd32f10x_bkp.h:85
bkp_rtc_calibration_output_disable
void bkp_rtc_calibration_output_disable(void)
disable RTC clock calibration output
Definition: gd32f10x_bkp.c:88
bkp_tamper_interrupt_enable
void bkp_tamper_interrupt_enable(void)
enable tamper interrupt
Definition: gd32f10x_bkp.c:196
bkp_flag_clear
void bkp_flag_clear(uint16_t flag)
clear bkp flag state
Definition: gd32f10x_bkp.c:235
bkp_tamper_detection_enable
void bkp_tamper_detection_enable(void)
enable tamper detection
Definition: gd32f10x_bkp.c:156
bkp_tamper_interrupt_disable
void bkp_tamper_interrupt_disable(void)
disable tamper interrupt
Definition: gd32f10x_bkp.c:207
BKP_DATA0_9
#define BKP_DATA0_9(number)
Definition: gd32f10x_bkp.h:91
bkp_tamper_detection_disable
void bkp_tamper_detection_disable(void)
disable tamper detection
Definition: gd32f10x_bkp.c:167
BKP_DATA_9
Definition: gd32f10x_bkp.h:126
bkp_rtc_signal_output_enable
void bkp_rtc_signal_output_enable(void)
enable RTC alarm or second signal output
Definition: gd32f10x_bkp.c:99
BKP_TPCTL_TPAL
#define BKP_TPCTL_TPAL
Definition: gd32f10x_bkp.h:80
bkp_tamper_active_level_set
void bkp_tamper_active_level_set(uint16_t level)
set tamper pin active level
Definition: gd32f10x_bkp.c:180
bkp_data_register_enum
bkp_data_register_enum
Definition: gd32f10x_bkp.h:115
bkp_deinit
void bkp_deinit(void)
reset BKP registers
Definition: gd32f10x_bkp.c:23
BKP_OCTL_COEN
#define BKP_OCTL_COEN
Definition: gd32f10x_bkp.h:74
bkp_rtc_calibration_value_set
void bkp_rtc_calibration_value_set(uint8_t value)
set RTC clock calibration value
Definition: gd32f10x_bkp.c:140
bkp_read_data
uint16_t bkp_read_data(bkp_data_register_enum register_number)
read BKP data register
Definition: gd32f10x_bkp.c:56
BKP_DATA_41
Definition: gd32f10x_bkp.h:158
gd32f10x_bkp.h
definitions for the BKP
bkp_write_data
void bkp_write_data(bkp_data_register_enum register_number, uint16_t data)
write BKP data register
Definition: gd32f10x_bkp.c:38
bkp_rtc_signal_output_disable
void bkp_rtc_signal_output_disable(void)
disable RTC alarm or second signal output
Definition: gd32f10x_bkp.c:110
BKP_OCTL_ASOEN
#define BKP_OCTL_ASOEN
Definition: gd32f10x_bkp.h:75
rcu_bkp_reset_disable
void rcu_bkp_reset_disable(void)
disable the BKP domain reset
Definition: gd32f10x_rcu.c:234
BKP_DATA_10
Definition: gd32f10x_bkp.h:127
bkp_flag_get
FlagStatus bkp_flag_get(uint16_t flag)
get bkp flag state
Definition: gd32f10x_bkp.c:219
bkp_interrupt_flag_clear
void bkp_interrupt_flag_clear(uint16_t flag)
clear bkp interrupt flag state
Definition: gd32f10x_bkp.c:263
BKP_TPCTL_TPEN
#define BKP_TPCTL_TPEN
Definition: gd32f10x_bkp.h:79
BKP_TPCS
#define BKP_TPCS
Definition: gd32f10x_bkp.h:66
bkp_interrupt_flag_get
FlagStatus bkp_interrupt_flag_get(uint16_t flag)
get bkp interrupt flag state
Definition: gd32f10x_bkp.c:247
BKP_DATA_0
Definition: gd32f10x_bkp.h:117
BKP_OCTL_ROSEL
#define BKP_OCTL_ROSEL
Definition: gd32f10x_bkp.h:76
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_fmc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_fmc.h"
14
24 void fmc_wscnt_set(uint32_t wscnt)
25 {
26 uint32_t reg;
27
28 reg = FMC_WS;
29 /* set the wait state counter value */
30 reg &= ~FMC_WS_WSCNT;
31 FMC_WS = (reg | wscnt);
32 }
33
40 void fmc_unlock(void)
41 {
42 if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
43 /* write the FMC unlock key */
44 FMC_KEY0 = UNLOCK_KEY0;
45 FMC_KEY0 = UNLOCK_KEY1;
46 }
47 if(FMC_BANK0_SIZE < FMC_SIZE){
48 /* write the FMC unlock key */
49 if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){
50 FMC_KEY1 = UNLOCK_KEY0;
51 FMC_KEY1 = UNLOCK_KEY1;
52 }
53 }
54 }
55
65 void fmc_bank0_unlock(void)
66 {
67 if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
68 /* write the FMC unlock key */
69 FMC_KEY0 = UNLOCK_KEY0;
70 FMC_KEY0 = UNLOCK_KEY1;
71 }
72 }
73
81 void fmc_bank1_unlock(void)
82 {
83 if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){
84 /* write the FMC unlock key */
85 FMC_KEY1 = UNLOCK_KEY0;
86 FMC_KEY1 = UNLOCK_KEY1;
87 }
88 }
89
96 void fmc_lock(void)
97 {
98 /* set the LK bit */
99 FMC_CTL0 |= FMC_CTL0_LK;
100
101 if(FMC_BANK0_SIZE < FMC_SIZE){
102 /* set the LK bit */
103 FMC_CTL1 |= FMC_CTL1_LK;
104 }
105 }
106
116 void fmc_bank0_lock(void)
117 {
118 /* set the LK bit*/
119 FMC_CTL0 |= FMC_CTL0_LK;
120 }
121
129 void fmc_bank1_lock(void)
130 {
131 /* set the LK bit*/
132 FMC_CTL1 |= FMC_CTL1_LK;
133 }
134
141 fmc_state_enum fmc_page_erase(uint32_t page_address)
142 {
143 fmc_state_enum fmc_state;
144
145 if(FMC_BANK0_SIZE < FMC_SIZE){
146 if(FMC_BANK0_END_ADDRESS > page_address){
147 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
148 /* if the last operation is completed, start page erase */
149 if(FMC_READY == fmc_state){
150 FMC_CTL0 |= FMC_CTL0_PER;
151 FMC_ADDR0 = page_address;
152 FMC_CTL0 |= FMC_CTL0_START;
153 /* wait for the FMC ready */
154 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
155 /* reset the PER bit */
156 FMC_CTL0 &= ~FMC_CTL0_PER;
157 }
158 }else{
159 /* wait for the FMC ready */
160 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
161 /* if the last operation is completed, start page erase */
162 if(FMC_READY == fmc_state){
163 FMC_CTL1 |= FMC_CTL1_PER;
164 FMC_ADDR1 = page_address;
165 if(FMC_OBSTAT & FMC_OBSTAT_SPC){
166 FMC_ADDR0 = page_address;
167 }
168 FMC_CTL1 |= FMC_CTL1_START;
169 /* wait for the FMC ready */
170 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
171 /* reset the PER bit */
172 FMC_CTL1 &= ~FMC_CTL1_PER;
173 }
174 }
175 }else{
176 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
177 /* if the last operation is completed, start page erase */
178 if(FMC_READY == fmc_state){
179 FMC_CTL0 |= FMC_CTL0_PER;
180 FMC_ADDR0 = page_address;
181 FMC_CTL0 |= FMC_CTL0_START;
182 /* wait for the FMC ready */
183 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
184 /* reset the PER bit */
185 FMC_CTL0 &= ~FMC_CTL0_PER;
186 }
187 }
188 /* return the FMC state */
189 return fmc_state;
190 }
191
198 fmc_state_enum fmc_mass_erase(void)
199 {
200 fmc_state_enum fmc_state;
201 if(FMC_BANK0_SIZE < FMC_SIZE){
202 /* wait for the FMC ready */
203 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
204 if(FMC_READY == fmc_state){
205 /* start whole chip erase */
206 FMC_CTL0 |= FMC_CTL0_MER;
207 FMC_CTL0 |= FMC_CTL0_START;
208 /* wait for the FMC ready */
209 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
210 /* reset the MER bit */
211 FMC_CTL0 &= ~FMC_CTL0_MER;
212 }
213 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
214 if(FMC_READY == fmc_state){
215 /* start whole chip erase */
216 FMC_CTL1 |= FMC_CTL1_MER;
217 FMC_CTL1 |= FMC_CTL1_START;
218 /* wait for the FMC ready */
219 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
220 /* reset the MER bit */
221 FMC_CTL1 &= ~FMC_CTL1_MER;
222 }
223 }else{
224 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
225
226 if(FMC_READY == fmc_state){
227 /* start whole chip erase */
228 FMC_CTL0 |= FMC_CTL0_MER;
229 FMC_CTL0 |= FMC_CTL0_START;
230 /* wait for the FMC ready */
231 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
232 /* reset the MER bit */
233 FMC_CTL0 &= ~FMC_CTL0_MER;
234 }
235 }
236 /* return the FMC state */
237 return fmc_state;
238 }
239
246 fmc_state_enum fmc_bank0_erase(void)
247 {
248 fmc_state_enum fmc_state = FMC_READY;
249 /* wait for the FMC ready */
250 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
251
252 if(FMC_READY == fmc_state){
253 /* start FMC bank0 erase */
254 FMC_CTL0 |= FMC_CTL0_MER;
255 FMC_CTL0 |= FMC_CTL0_START;
256 /* wait for the FMC ready */
257 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
258 /* reset the MER bit */
259 FMC_CTL0 &= ~FMC_CTL0_MER;
260 }
261 /* return the fmc state */
262 return fmc_state;
263 }
264
271 fmc_state_enum fmc_bank1_erase(void)
272 {
273 fmc_state_enum fmc_state = FMC_READY;
274 /* wait for the FMC ready */
275 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
276
277 if(FMC_READY == fmc_state){
278 /* start FMC bank1 erase */
279 FMC_CTL1 |= FMC_CTL1_MER;
280 FMC_CTL1 |= FMC_CTL1_START;
281 /* wait for the FMC ready */
282 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
283 /* reset the MER bit */
284 FMC_CTL1 &= ~FMC_CTL1_MER;
285 }
286 /* return the fmc state */
287 return fmc_state;
288 }
289
297 fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
298 {
299 fmc_state_enum fmc_state = FMC_READY;
300 if(FMC_BANK0_SIZE < FMC_SIZE){
301 if(FMC_BANK0_END_ADDRESS > address){
302 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
303
304 if(FMC_READY == fmc_state){
305 /* set the PG bit to start program */
306 FMC_CTL0 |= FMC_CTL0_PG;
307 REG32(address) = data;
308 /* wait for the FMC ready */
309 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
310 /* reset the PG bit */
311 FMC_CTL0 &= ~FMC_CTL0_PG;
312 }
313 }else{
314 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
315
316 if(FMC_READY == fmc_state){
317 /* set the PG bit to start program */
318 FMC_CTL1 |= FMC_CTL1_PG;
319 REG32(address) = data;
320 /* wait for the FMC ready */
321 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
322 /* reset the PG bit */
323 FMC_CTL1 &= ~FMC_CTL1_PG;
324 }
325 }
326 }else{
327 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
328
329 if(FMC_READY == fmc_state){
330 /* set the PG bit to start program */
331 FMC_CTL0 |= FMC_CTL0_PG;
332 REG32(address) = data;
333 /* wait for the FMC ready */
334 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
335 /* reset the PG bit */
336 FMC_CTL0 &= ~FMC_CTL0_PG;
337 }
338 }
339 /* return the FMC state */
340 return fmc_state;
341 }
342
350 fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
351 {
352 fmc_state_enum fmc_state = FMC_READY;
353 if(FMC_BANK0_SIZE > FMC_SIZE){
354 if(FMC_BANK0_END_ADDRESS > address){
355 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
356
357 if(FMC_READY == fmc_state){
358 /* set the PG bit to start program */
359 FMC_CTL0 |= FMC_CTL0_PG;
360 REG16(address) = data;
361 /* wait for the FMC ready */
362 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
363 /* reset the PG bit */
364 FMC_CTL0 &= ~FMC_CTL0_PG;
365 }
366 }else{
367 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
368
369 if(FMC_READY == fmc_state){
370 /* set the PG bit to start program */
371 FMC_CTL1 |= FMC_CTL1_PG;
372 REG16(address) = data;
373 /* wait for the FMC ready */
374 fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
375 /* reset the PG bit */
376 FMC_CTL1 &= ~FMC_CTL1_PG;
377 }
378 }
379 }else{
380 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
381
382 if(FMC_READY == fmc_state){
383 /* set the PG bit to start program */
384 FMC_CTL0 |= FMC_CTL0_PG;
385 REG16(address) = data;
386 /* wait for the FMC ready */
387 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
388 /* reset the PG bit */
389 FMC_CTL0 &= ~FMC_CTL0_PG;
390 }
391 }
392 /* return the FMC state */
393 return fmc_state;
394 }
395
402 void ob_unlock(void)
403 {
404 if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
405 /* write the FMC key */
406 FMC_OBKEY = UNLOCK_KEY0;
407 FMC_OBKEY = UNLOCK_KEY1;
408 }
409
410 /* wait until OBWEN bit is set by hardware */
411 while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
412 }
413 }
414
421 void ob_lock(void)
422 {
423 /* reset the OBWEN bit */
424 FMC_CTL0 &= ~FMC_CTL0_OBWEN;
425 }
426
434 fmc_state_enum ob_erase(void)
435 {
436 uint16_t temp_spc = FMC_NSPC;
437
438 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
439
440 /* check the option byte security protection value */
441 if(RESET != ob_spc_get()){
442 temp_spc = FMC_USPC;
443 }
444
445 if(FMC_READY == fmc_state){
446
447 /* start erase the option byte */
448 FMC_CTL0 |= FMC_CTL0_OBER;
449 FMC_CTL0 |= FMC_CTL0_START;
450
451 /* wait for the FMC ready */
452 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
453
454 if(FMC_READY == fmc_state){
455 /* reset the OBER bit */
456 FMC_CTL0 &= ~FMC_CTL0_OBER;
457 /* set the OBPG bit */
458 FMC_CTL0 |= FMC_CTL0_OBPG;
459 /* no security protection */
460 OB_SPC = (uint16_t)temp_spc;
461 /* wait for the FMC ready */
462 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
463 if(FMC_TOERR != fmc_state){
464 /* reset the OBPG bit */
465 FMC_CTL0 &= ~FMC_CTL0_OBPG;
466 }
467 }else{
468 if(FMC_TOERR != fmc_state){
469 /* reset the OBPG bit */
470 FMC_CTL0 &= ~FMC_CTL0_OBPG;
471 }
472 }
473 }
474 /* return the FMC state */
475 return fmc_state;
476 }
477
486 fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
487 {
488 uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3;
489
490 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
491
492 ob_wp = (uint32_t)(~ob_wp);
493 temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0);
494 temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U);
495 temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U);
496 temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U);
497
498 if(FMC_READY == fmc_state){
499
500 /* set the OBPG bit*/
501 FMC_CTL0 |= FMC_CTL0_OBPG;
502
503 if(0xFFU != temp_wp0){
504 OB_WP0 = temp_wp0;
505
506 /* wait for the FMC ready */
507 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
508 }
509 if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){
510 OB_WP1 = temp_wp1;
511
512 /* wait for the FMC ready */
513 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
514 }
515 if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){
516 OB_WP2 = temp_wp2;
517
518 /* wait for the FMC ready */
519 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
520 }
521 if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){
522 OB_WP3 = temp_wp3;
523
524 /* wait for the FMC ready */
525 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
526 }
527 if(FMC_TOERR != fmc_state){
528 /* reset the OBPG bit */
529 FMC_CTL0 &= ~FMC_CTL0_OBPG;
530 }
531 }
532 /* return the FMC state */
533 return fmc_state;
534 }
535
544 fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
545 {
546 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
547
548 if(FMC_READY == fmc_state){
549 FMC_CTL0 |= FMC_CTL0_OBER;
550 FMC_CTL0 |= FMC_CTL0_START;
551
552 /* wait for the FMC ready */
553 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
554
555 if(FMC_READY == fmc_state){
556 /* reset the OBER bit */
557 FMC_CTL0 &= ~FMC_CTL0_OBER;
558
559 /* start the option byte program */
560 FMC_CTL0 |= FMC_CTL0_OBPG;
561
562 OB_SPC = (uint16_t)ob_spc;
563
564 /* wait for the FMC ready */
565 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
566
567 if(FMC_TOERR != fmc_state){
568 /* reset the OBPG bit */
569 FMC_CTL0 &= ~FMC_CTL0_OBPG;
570 }
571 }else{
572 if(FMC_TOERR != fmc_state){
573 /* reset the OBER bit */
574 FMC_CTL0 &= ~FMC_CTL0_OBER;
575 }
576 }
577 }
578 /* return the FMC state */
579 return fmc_state;
580 }
581
599 fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot)
600 {
601 fmc_state_enum fmc_state = FMC_READY;
602 uint8_t temp;
603
604 /* wait for the FMC ready */
605 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
606
607 if(FMC_READY == fmc_state){
608 /* set the OBPG bit*/
609 FMC_CTL0 |= FMC_CTL0_OBPG;
610
611 temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK);
612 OB_USER = (uint16_t)temp;
613
614 /* wait for the FMC ready */
615 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
616
617 if(FMC_TOERR != fmc_state){
618 /* reset the OBPG bit */
619 FMC_CTL0 &= ~FMC_CTL0_OBPG;
620 }
621 }
622 /* return the FMC state */
623 return fmc_state;
624 }
625
633 fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
634 {
635 fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
636
637 if(FMC_READY == fmc_state){
638 /* set the OBPG bit */
639 FMC_CTL0 |= FMC_CTL0_OBPG;
640 REG16(address) = data;
641
642 /* wait for the FMC ready */
643 fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
644
645 if(FMC_TOERR != fmc_state){
646 /* reset the OBPG bit */
647 FMC_CTL0 &= ~FMC_CTL0_OBPG;
648 }
649 }
650 /* return the FMC state */
651 return fmc_state;
652 }
653
660 uint8_t ob_user_get(void)
661 {
662 /* return the FMC user option byte value */
663 return (uint8_t)(FMC_OBSTAT >> 2U);
664 }
665
672 uint16_t ob_data_get(void)
673 {
674 return (uint16_t)(FMC_OBSTAT >> 10U);
675 }
676
683 uint32_t ob_write_protection_get(void)
684 {
685 /* return the FMC write protection option byte value */
686 return FMC_WP;
687 }
688
695 FlagStatus ob_spc_get(void)
696 {
697 FlagStatus spc_state = RESET;
698
699 if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){
700 spc_state = SET;
701 }else{
702 spc_state = RESET;
703 }
704 return spc_state;
705 }
706
717 void fmc_interrupt_enable(uint32_t interrupt)
718 {
719 FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt));
720 }
721
732 void fmc_interrupt_disable(uint32_t interrupt)
733 {
734 FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt));
735 }
736
753 FlagStatus fmc_flag_get(uint32_t flag)
754 {
755 if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){
756 return SET;
757 }else{
758 return RESET;
759 }
760 }
761
775 void fmc_flag_clear(uint32_t flag)
776 {
777 FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag));
778 }
779
793 FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
794 {
795 FlagStatus ret1 = RESET;
796 FlagStatus ret2 = RESET;
797
798 if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){
799 /* get the staus of interrupt flag */
800 ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
801 /* get the staus of interrupt enale bit */
802 ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
803 }else{
804 /* get the staus of interrupt flag */
805 ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
806 /* get the staus of interrupt enale bit */
807 ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag)));
808 }
809
810 if(ret1 && ret2){
811 return SET;
812 }else{
813 return RESET;
814 }
815 }
816
830 void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag)
831 {
832 FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag));
833 }
834
841 fmc_state_enum fmc_bank0_state_get(void)
842 {
843 fmc_state_enum fmc_state = FMC_READY;
844
845 if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){
846 fmc_state = FMC_BUSY;
847 }else{
848 if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){
849 fmc_state = FMC_WPERR;
850 }else{
851 if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){
852 fmc_state = FMC_PGERR;
853 }
854 }
855 }
856 /* return the FMC state */
857 return fmc_state;
858 }
859
866 fmc_state_enum fmc_bank1_state_get(void)
867 {
868 fmc_state_enum fmc_state = FMC_READY;
869
870 if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){
871 fmc_state = FMC_BUSY;
872 }else{
873 if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){
874 fmc_state = FMC_WPERR;
875 }else{
876 if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){
877 fmc_state = FMC_PGERR;
878 }
879 }
880 }
881
882 /* return the FMC state */
883 return fmc_state;
884 }
885
892 fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
893 {
894 fmc_state_enum fmc_state = FMC_BUSY;
895
896 /* wait for FMC ready */
897 do{
898 /* get FMC state */
899 fmc_state = fmc_bank0_state_get();
900 timeout--;
901 }while((FMC_BUSY == fmc_state) && (0x00U != timeout));
902
903 if(FMC_BUSY == fmc_state){
904 fmc_state = FMC_TOERR;
905 }
906 /* return the FMC state */
907 return fmc_state;
908 }
909
916 fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
917 {
918 fmc_state_enum fmc_state = FMC_BUSY;
919
920 /* wait for FMC ready */
921 do{
922 /* get FMC state */
923 fmc_state = fmc_bank1_state_get();
924 timeout--;
925 }while((FMC_BUSY == fmc_state) && (0x00U != timeout));
926
927 if(FMC_BUSY == fmc_state){
928 fmc_state = FMC_TOERR;
929 }
930 /* return the FMC state */
931 return fmc_state;
932 }
FMC_CTL0_LK
#define FMC_CTL0_LK
Definition: gd32f10x_fmc.h:68
FMC_BIT_POS0
#define FMC_BIT_POS0(val)
Definition: gd32f10x_fmc.h:119
ob_user_get
uint8_t ob_user_get(void)
get the FMC user option byte
Definition: gd32f10x_fmc.c:660
ob_write_protection_get
uint32_t ob_write_protection_get(void)
get the FMC option byte write protection
Definition: gd32f10x_fmc.c:683
FMC_REG_VALS
#define FMC_REG_VALS(offset)
Definition: gd32f10x_fmc.h:118
FMC_REG_OFFSET_GET
#define FMC_REG_OFFSET_GET(flag)
Definition: gd32f10x_fmc.h:121
fmc_bank1_state_get
fmc_state_enum fmc_bank1_state_get(void)
get the FMC bank1 state
Definition: gd32f10x_fmc.c:866
FMC_ADDR0
#define FMC_ADDR0
Definition: gd32f10x_fmc.h:28
fmc_bank0_lock
void fmc_bank0_lock(void)
lock the FMC bank0 operation this function can be used for all GD32F10X devices. for GD32F10x_MD and ...
Definition: gd32f10x_fmc.c:116
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f10x_fmc.h:175
OB_USER_MASK
#define OB_USER_MASK
Definition: gd32f10x_fmc.h:200
ob_unlock
void ob_unlock(void)
unlock the option byte operation
Definition: gd32f10x_fmc.c:402
FMC_WP
#define FMC_WP
Definition: gd32f10x_fmc.h:30
FMC_CTL0_PER
#define FMC_CTL0_PER
Definition: gd32f10x_fmc.h:63
OB_WP1_WP1
#define OB_WP1_WP1
Definition: gd32f10x_fmc.h:218
ob_erase
fmc_state_enum ob_erase(void)
erase the FMC option byte unlock the FMC_CTL0 and option byte before calling this function ...
Definition: gd32f10x_fmc.c:434
FMC_CTL0_OBER
#define FMC_CTL0_OBER
Definition: gd32f10x_fmc.h:66
FMC_BUSY
Definition: gd32f10x_fmc.h:134
FMC_WPERR
Definition: gd32f10x_fmc.h:136
FMC_CTL0_START
#define FMC_CTL0_START
Definition: gd32f10x_fmc.h:67
OB_WP0
#define OB_WP0
Definition: gd32f10x_fmc.h:40
FMC_STAT1
#define FMC_STAT1
Definition: gd32f10x_fmc.h:32
FMC_CTL0_MER
#define FMC_CTL0_MER
Definition: gd32f10x_fmc.h:64
fmc_word_program
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
program a word at the corresponding address
Definition: gd32f10x_fmc.c:297
fmc_interrupt_disable
void fmc_interrupt_disable(uint32_t interrupt)
disable FMC interrupt
Definition: gd32f10x_fmc.c:732
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f10x_fmc.h:262
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
OB_WP0_WP0
#define OB_WP0_WP0
Definition: gd32f10x_fmc.h:215
fmc_bank0_unlock
void fmc_bank0_unlock(void)
unlock the FMC bank0 operation this function can be used for all GD32F10x devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function.
Definition: gd32f10x_fmc.c:65
OB_SPC
#define OB_SPC
Definition: gd32f10x_fmc.h:38
ob_security_protection_config
fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
configure security protection
Definition: gd32f10x_fmc.c:544
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
FMC_OBKEY
#define FMC_OBKEY
Definition: gd32f10x_fmc.h:25
FMC_CTL1_START
#define FMC_CTL1_START
Definition: gd32f10x_fmc.h:98
FMC_KEY0
#define FMC_KEY0
Definition: gd32f10x_fmc.h:24
OB_WP3
#define OB_WP3
Definition: gd32f10x_fmc.h:43
FMC_BANK0_END_ADDRESS
#define FMC_BANK0_END_ADDRESS
Definition: gd32f10x_fmc.h:265
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f10x_fmc.h:176
OB_USER
#define OB_USER
Definition: gd32f10x_fmc.h:39
FMC_TOERR
Definition: gd32f10x_fmc.h:137
fmc_flag_get
FlagStatus fmc_flag_get(uint32_t flag)
check flag is set or not
Definition: gd32f10x_fmc.c:753
FMC_REG_VAL
#define FMC_REG_VAL(offset)
Definition: gd32f10x_fmc.h:115
FMC_NSPC
#define FMC_NSPC
Definition: gd32f10x_fmc.h:203
fmc_bank1_unlock
void fmc_bank1_unlock(void)
unlock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash m...
Definition: gd32f10x_fmc.c:81
FMC_WS_WSCNT
#define FMC_WS_WSCNT
Definition: gd32f10x_fmc.h:47
FMC_SIZE
#define FMC_SIZE
Definition: gd32f10x_fmc.h:267
FMC_BIT_POS
#define FMC_BIT_POS(val)
Definition: gd32f10x_fmc.h:116
FMC_STAT1_WPERR
#define FMC_STAT1_WPERR
Definition: gd32f10x_fmc.h:91
FMC_STAT0_WPERR
#define FMC_STAT0_WPERR
Definition: gd32f10x_fmc.h:58
FMC_ADDR1
#define FMC_ADDR1
Definition: gd32f10x_fmc.h:34
FMC_USPC
#define FMC_USPC
Definition: gd32f10x_fmc.h:204
fmc_interrupt_enable
void fmc_interrupt_enable(uint32_t interrupt)
enable FMC interrupt
Definition: gd32f10x_fmc.c:717
OB_WP3_WP3
#define OB_WP3_WP3
Definition: gd32f10x_fmc.h:224
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f10x_fmc.h:29
FMC_BIT_POS1
#define FMC_BIT_POS1(val)
Definition: gd32f10x_fmc.h:120
ob_spc_get
FlagStatus ob_spc_get(void)
get the FMC option byte security protection
Definition: gd32f10x_fmc.c:695
fmc_interrupt_flag_clear
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag)
clear FMC interrupt flag state
Definition: gd32f10x_fmc.c:830
ob_data_program
fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
program option bytes data
Definition: gd32f10x_fmc.c:633
OB_WP2_WP2
#define OB_WP2_WP2
Definition: gd32f10x_fmc.h:221
FMC_OBSTAT_SPC
#define FMC_OBSTAT_SPC
Definition: gd32f10x_fmc.h:78
FMC_CTL1_LK
#define FMC_CTL1_LK
Definition: gd32f10x_fmc.h:99
FMC_CTL0_OBWEN
#define FMC_CTL0_OBWEN
Definition: gd32f10x_fmc.h:69
gd32f10x_fmc.h
definitions for the FMC
fmc_page_erase
fmc_state_enum fmc_page_erase(uint32_t page_address)
erase page
Definition: gd32f10x_fmc.c:141
FMC_CTL1_MER
#define FMC_CTL1_MER
Definition: gd32f10x_fmc.h:97
FMC_STAT0
#define FMC_STAT0
Definition: gd32f10x_fmc.h:26
fmc_lock
void fmc_lock(void)
lock the main FMC operation
Definition: gd32f10x_fmc.c:96
OB_WP1
#define OB_WP1
Definition: gd32f10x_fmc.h:41
fmc_flag_clear
void fmc_flag_clear(uint32_t flag)
clear the FMC flag
Definition: gd32f10x_fmc.c:775
fmc_interrupt_flag_get
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
get FMC interrupt flag state
Definition: gd32f10x_fmc.c:793
OB_WP2
#define OB_WP2
Definition: gd32f10x_fmc.h:42
fmc_interrupt_flag_enum
fmc_interrupt_flag_enum
Definition: gd32f10x_fmc.h:164
fmc_mass_erase
fmc_state_enum fmc_mass_erase(void)
erase whole chip
Definition: gd32f10x_fmc.c:198
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_STAT0_PGERR
#define FMC_STAT0_PGERR
Definition: gd32f10x_fmc.h:57
FMC_STAT1_BUSY
#define FMC_STAT1_BUSY
Definition: gd32f10x_fmc.h:89
FMC_STAT1_PGERR
#define FMC_STAT1_PGERR
Definition: gd32f10x_fmc.h:90
FMC_CTL0_OBPG
#define FMC_CTL0_OBPG
Definition: gd32f10x_fmc.h:65
FMC_STAT0_REG_OFFSET
#define FMC_STAT0_REG_OFFSET
Definition: gd32f10x_fmc.h:124
FMC_CTL1
#define FMC_CTL1
Definition: gd32f10x_fmc.h:33
FMC_CTL0_PG
#define FMC_CTL0_PG
Definition: gd32f10x_fmc.h:62
FMC_CTL1_PG
#define FMC_CTL1_PG
Definition: gd32f10x_fmc.h:95
fmc_bank1_erase
fmc_state_enum fmc_bank1_erase(void)
erase bank1
Definition: gd32f10x_fmc.c:271
ob_data_get
uint16_t ob_data_get(void)
get OB_DATA in register FMC_OBSTAT
Definition: gd32f10x_fmc.c:672
fmc_bank0_erase
fmc_state_enum fmc_bank0_erase(void)
erase bank0
Definition: gd32f10x_fmc.c:246
FMC_BANK0_SIZE
#define FMC_BANK0_SIZE
Definition: gd32f10x_fmc.h:266
FMC_READY
Definition: gd32f10x_fmc.h:133
ob_user_write
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot)
program the FMC user option byte
Definition: gd32f10x_fmc.c:599
fmc_bank0_state_get
fmc_state_enum fmc_bank0_state_get(void)
get the FMC bank0 state
Definition: gd32f10x_fmc.c:841
fmc_wscnt_set
void fmc_wscnt_set(uint32_t wscnt)
set the wait state counter value
Definition: gd32f10x_fmc.c:24
fmc_bank1_lock
void fmc_bank1_lock(void)
lock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash mor...
Definition: gd32f10x_fmc.c:129
ob_write_protection_enable
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
enable write protection
Definition: gd32f10x_fmc.c:486
FMC_WS
#define FMC_WS
Definition: gd32f10x_fmc.h:23
FMC_CTL1_PER
#define FMC_CTL1_PER
Definition: gd32f10x_fmc.h:96
fmc_halfword_program
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
program a half word at the corresponding address
Definition: gd32f10x_fmc.c:350
FMC_STAT0_BUSY
#define FMC_STAT0_BUSY
Definition: gd32f10x_fmc.h:56
fmc_unlock
void fmc_unlock(void)
unlock the main FMC operation
Definition: gd32f10x_fmc.c:40
FMC_CTL0
#define FMC_CTL0
Definition: gd32f10x_fmc.h:27
FMC_PGERR
Definition: gd32f10x_fmc.h:135
ob_lock
void ob_lock(void)
lock the option byte operation
Definition: gd32f10x_fmc.c:421
FMC_KEY1
#define FMC_KEY1
Definition: gd32f10x_fmc.h:31
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_exmc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_EXMC_H
14 #define GD32F10X_EXMC_H
15
16 #include "gd32f10x.h"
17
18 /* EXMC definitions */
19 #define EXMC (EXMC_BASE)
21 /* registers definitions */
22 /* NOR/PSRAM */
23 #define EXMC_SNCTL0 REG32(EXMC + 0x00U)
24 #define EXMC_SNTCFG0 REG32(EXMC + 0x04U)
25 #define EXMC_SNWTCFG0 REG32(EXMC + 0x104U)
27 #define EXMC_SNCTL1 REG32(EXMC + 0x08U)
28 #define EXMC_SNTCFG1 REG32(EXMC + 0x0CU)
29 #define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU)
31 #define EXMC_SNCTL2 REG32(EXMC + 0x10U)
32 #define EXMC_SNTCFG2 REG32(EXMC + 0x14U)
33 #define EXMC_SNWTCFG2 REG32(EXMC + 0x114U)
35 #define EXMC_SNCTL3 REG32(EXMC + 0x18U)
36 #define EXMC_SNTCFG3 REG32(EXMC + 0x1CU)
37 #define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU)
39 /* NAND/PC card */
40 #define EXMC_NPCTL1 REG32(EXMC + 0x60U)
41 #define EXMC_NPINTEN1 REG32(EXMC + 0x64U)
42 #define EXMC_NPCTCFG1 REG32(EXMC + 0x68U)
43 #define EXMC_NPATCFG1 REG32(EXMC + 0x6CU)
44 #define EXMC_NECC1 REG32(EXMC + 0x74U)
46 #define EXMC_NPCTL2 REG32(EXMC + 0x80U)
47 #define EXMC_NPINTEN2 REG32(EXMC + 0x84U)
48 #define EXMC_NPCTCFG2 REG32(EXMC + 0x88U)
49 #define EXMC_NPATCFG2 REG32(EXMC + 0x8CU)
50 #define EXMC_NECC2 REG32(EXMC + 0x94U)
52 #define EXMC_NPCTL3 REG32(EXMC + 0xA0U)
53 #define EXMC_NPINTEN3 REG32(EXMC + 0xA4U)
54 #define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U)
55 #define EXMC_NPATCFG3 REG32(EXMC + 0xACU)
56 #define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U)
58 /* bits definitions */
59 /* NOR/PSRAM */
60 /* EXMC_SNCTLx,x=0..3 */
61 #define EXMC_SNCTL_NRBKEN BIT(0)
62 #define EXMC_SNCTL_NRMUX BIT(1)
63 #define EXMC_SNCTL_NRTP BITS(2,3)
64 #define EXMC_SNCTL_NRW BITS(4,5)
65 #define EXMC_SNCTL_NREN BIT(6)
66 #define EXMC_SNCTL_SBRSTEN BIT(8)
67 #define EXMC_SNCTL_NRWTPOL BIT(9)
68 #define EXMC_SNCTL_WRAPEN BIT(10)
69 #define EXMC_SNCTL_NRWTCFG BIT(11)
70 #define EXMC_SNCTL_WREN BIT(12)
71 #define EXMC_SNCTL_NRWTEN BIT(13)
72 #define EXMC_SNCTL_EXMODEN BIT(14)
73 #define EXMC_SNCTL_ASYNCWAIT BIT(15)
74 #define EXMC_SNCTL_SYNCWR BIT(19)
76 /* EXMC_SNTCFGx,x=0..3 */
77 #define EXMC_SNTCFG_ASET BITS(0,3)
78 #define EXMC_SNTCFG_AHLD BITS(4,7)
79 #define EXMC_SNTCFG_DSET BITS(8,15)
80 #define EXMC_SNTCFG_BUSLAT BITS(16,19)
81 #define EXMC_SNTCFG_CKDIV BITS(20,23)
82 #define EXMC_SNTCFG_DLAT BITS(24,27)
83 #define EXMC_SNTCFG_ASYNCMOD BITS(28,29)
85 /* EXMC_SNWTCFGx,x=0..3 */
86 #define EXMC_SNWTCFG_WASET BITS(0,3)
87 #define EXMC_SNWTCFG_WAHLD BITS(4,7)
88 #define EXMC_SNWTCFG_WDSET BITS(8,15)
89 #define EXMC_SNWTCFG_CKDIV BITS(20,23)
90 #define EXMC_SNWTCFG_DLAT BITS(24,27)
91 #define EXMC_SNWTCFG_WASYNCMOD BITS(28,29)
93 /* NAND/PC card */
94 /* EXMC_NPCTLx,x=1..3 */
95 #define EXMC_NPCTL_NDWTEN BIT(1)
96 #define EXMC_NPCTL_NDBKEN BIT(2)
97 #define EXMC_NPCTL_NDTP BIT(3)
98 #define EXMC_NPCTL_NDW BITS(4,5)
99 #define EXMC_NPCTL_ECCEN BIT(6)
100 #define EXMC_NPCTL_CTR BITS(9,12)
101 #define EXMC_NPCTL_ATR BITS(13,16)
102 #define EXMC_NPCTL_ECCSZ BITS(17,19)
104 /* EXMC_NPINTENx,x=1..3 */
105 #define EXMC_NPINTEN_INTRS BIT(0)
106 #define EXMC_NPINTEN_INTHS BIT(1)
107 #define EXMC_NPINTEN_INTFS BIT(2)
108 #define EXMC_NPINTEN_INTREN BIT(3)
109 #define EXMC_NPINTEN_INTHEN BIT(4)
110 #define EXMC_NPINTEN_INTFEN BIT(5)
111 #define EXMC_NPINTEN_FFEPT BIT(6)
113 /* EXMC_NPCTCFGx,x=1..3 */
114 #define EXMC_NPCTCFG_COMSET BITS(0,7)
115 #define EXMC_NPCTCFG_COMWAIT BITS(8,15)
116 #define EXMC_NPCTCFG_COMHLD BITS(16,23)
117 #define EXMC_NPCTCFG_COMHIZ BITS(24,31)
119 /* EXMC_NPATCFGx,x=1..3 */
120 #define EXMC_NPATCFG_ATTSET BITS(0,7)
121 #define EXMC_NPATCFG_ATTWAIT BITS(8,15)
122 #define EXMC_NPATCFG_ATTHLD BITS(16,23)
123 #define EXMC_NPATCFG_ATTHIZ BITS(24,31)
125 /* EXMC_PIOTCFG3 */
126 #define EXMC_PIOTCFG3_IOSET BITS(0,7)
127 #define EXMC_PIOTCFG3_IOWAIT BITS(8,15)
128 #define EXMC_PIOTCFG3_IOHLD BITS(16,23)
129 #define EXMC_PIOTCFG3_IOHIZ BITS(24,31)
131 /* EXMC_NECCx,x=1,2 */
132 #define EXMC_NECC_ECC BITS(0,31)
134 /* constants definitions */
135 /* EXMC NOR/SRAM timing initialize struct */
136 typedef struct
137 {
138 uint32_t asyn_access_mode;
139 uint32_t syn_data_latency;
140 uint32_t syn_clk_division;
141 uint32_t bus_latency;
142 uint32_t asyn_data_setuptime;
143 uint32_t asyn_address_holdtime;
144 uint32_t asyn_address_setuptime;
145 }exmc_norsram_timing_parameter_struct;
146
147 /* EXMC NOR/SRAM initialize struct */
148 typedef struct
149 {
150 uint32_t norsram_region;
151 uint32_t write_mode;
152 uint32_t extended_mode;
153 uint32_t asyn_wait;
154 uint32_t nwait_signal;
155 uint32_t memory_write;
156 uint32_t nwait_config;
157 uint32_t wrap_burst_mode;
158 uint32_t nwait_polarity;
159 uint32_t burst_mode;
160 uint32_t databus_width;
161 uint32_t memory_type;
162 uint32_t address_data_mux;
163 exmc_norsram_timing_parameter_struct* read_write_timing;
165 exmc_norsram_timing_parameter_struct* write_timing;
166 }exmc_norsram_parameter_struct;
167
168 /* EXMC NAND/PC card timing initialize struct */
169 typedef struct
170 {
171 uint32_t databus_hiztime;
172 uint32_t holdtime;
173 uint32_t waittime;
174 uint32_t setuptime;
175 }exmc_nand_pccard_timing_parameter_struct;
176
177 /* EXMC NAND initialize struct */
178 typedef struct
179 {
180 uint32_t nand_bank;
181 uint32_t ecc_size;
182 uint32_t atr_latency;
183 uint32_t ctr_latency;
184 uint32_t ecc_logic;
185 uint32_t databus_width;
186 uint32_t wait_feature;
187 exmc_nand_pccard_timing_parameter_struct* common_space_timing;
188 exmc_nand_pccard_timing_parameter_struct* attribute_space_timing;
189 }exmc_nand_parameter_struct;
190
191 /* EXMC PC card initialize struct */
192 typedef struct
193 {
194 uint32_t atr_latency;
195 uint32_t ctr_latency;
196 uint32_t wait_feature;
197 exmc_nand_pccard_timing_parameter_struct* common_space_timing;
198 exmc_nand_pccard_timing_parameter_struct* attribute_space_timing;
199 exmc_nand_pccard_timing_parameter_struct* io_space_timing;
200 }exmc_pccard_parameter_struct;;
201
202 /* EXMC register address */
203 #define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region))
204 #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region))
205 #define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region))
207 #define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank))
208 #define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank))
209 #define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank))
210 #define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank))
211 #define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank))
213 //#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
215 //#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */
216 //#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */
217 //#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */
218 //#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */
219 //#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */
220
221 /* NOR bank memory data bus width */
222 #define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
223 #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0)
224 #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1)
226 /* NOR bank memory type */
227 #define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
228 #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0)
229 #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1)
230 #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2)
232 /* asynchronous access mode */
233 #define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
234 #define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0)
235 #define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1)
236 #define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2)
237 #define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3)
239 /* data latency for NOR flash */
240 #define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
241 #define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0)
242 #define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1)
243 #define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2)
244 #define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3)
245 #define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4)
246 #define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5)
247 #define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6)
248 #define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7)
249 #define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8)
250 #define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9)
251 #define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10)
252 #define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11)
253 #define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12)
254 #define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13)
255 #define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14)
256 #define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15)
258 /* synchronous clock divide ratio */
259 #define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
260 #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0)
261 #define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1)
262 #define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2)
263 #define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3)
264 #define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4)
265 #define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5)
266 #define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6)
267 #define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7)
268 #define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8)
269 #define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9)
270 #define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10)
271 #define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11)
272 #define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12)
273 #define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13)
274 #define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14)
275 #define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15)
277 /* ECC size */
278 #define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
279 #define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */
280 #define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */
281 #define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */
282 #define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */
283 #define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */
284 #define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */
285
286 /* ALE to RE delay */
287 #define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
288 #define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
289 #define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
290 #define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
291 #define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
292 #define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
293 #define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
294 #define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
295 #define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
296 #define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
297 #define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
298 #define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
299 #define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
300 #define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
301 #define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
302 #define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
303 #define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
304
305 /* CLE to RE delay */
306 #define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
307 #define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
308 #define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
309 #define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
310 #define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
311 #define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
312 #define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
313 #define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
314 #define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
315 #define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
316 #define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
317 #define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
318 #define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
319 #define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
320 #define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
321 #define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
322 #define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
323
324 /* NAND bank memory data bus width */
325 #define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
326 #define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0)
327 #define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1)
329 /* EXMC NOR/SRAM bank region definition */
330 #define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U)
331 #define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U)
332 #define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U)
333 #define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U)
335 /* EXMC NOR/SRAM write mode */
336 #define EXMC_ASYN_WRITE ((uint32_t)0x00000000U)
337 #define EXMC_SYN_WRITE ((uint32_t)0x00080000U)
339 /* EXMC NWAIT signal configuration */
340 #define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U)
341 #define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U)
343 /* EXMC NWAIT signal polarity configuration */
344 #define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U)
345 #define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U)
347 /* EXMC NAND/PC card bank definition */
348 #define EXMC_BANK1_NAND ((uint32_t)0x00000001U)
349 #define EXMC_BANK2_NAND ((uint32_t)0x00000002U)
350 #define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U)
352 /* EXMC flag bits */
353 #define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS
354 #define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS
355 #define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS
356 #define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT
358 /* EXMC interrupt flag bits */
359 #define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN
360 #define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN
361 #define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN
363 /* function declarations */
364 /* deinitialize EXMC NOR/SRAM region */
365 void exmc_norsram_deinit(uint32_t norsram_region);
366 /* initialize EXMC NOR/SRAM region */
367 void exmc_norsram_init(exmc_norsram_parameter_struct* norsram_init_struct);
368 /* exmc_norsram_parameter_struct parameter initialize */
369 void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* norsram_init_struct);
370 /* EXMC NOR/SRAM bank enable */
371 void exmc_norsram_enable(uint32_t norsram_region);
372 /* EXMC NOR/SRAM bank disable */
373 void exmc_norsram_disable(uint32_t norsram_region);
374
375
376 /* deinitialize EXMC NAND bank */
377 void exmc_nand_deinit(uint32_t nand_bank);
378 /* initialize EXMC NAND bank */
379 void exmc_nand_init(exmc_nand_parameter_struct* nand_init_struct);
380 /* exmc_norsram_parameter_struct parameter initialize */
381 void exmc_nand_parameter_init(exmc_nand_parameter_struct* nand_init_struct);
382 /* EXMC NAND bank enable */
383 void exmc_nand_enable(uint32_t nand_bank);
384 /* EXMC NAND bank disable */
385 void exmc_nand_disable(uint32_t nand_bank);
386 /* enable or disable the EXMC NAND ECC function */
387 void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue);
388 /* get the EXMC ECC value */
389 uint32_t exmc_ecc_get(uint32_t nand_bank);
390
391 /* deinitialize EXMC PC card bank */
392 void exmc_pccard_deinit(void);
393 /* initialize EXMC PC card bank */
394 void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
395 /* exmc_pccard_parameter_struct parameter initialize */
396 void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
397 /* EXMC PC card bank enable */
398 void exmc_pccard_enable(void);
399 /* EXMC PC card bank disable */
400 void exmc_pccard_disable(void);
401
402 /* check EXMC flag is set or not */
403 FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag);
404 /* clear EXMC flag */
405 void exmc_flag_clear(uint32_t bank, uint32_t flag);
406 /* check EXMC flag is set or not */
407 FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source);
408 /* clear EXMC flag */
409 void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source);
410 /* enable EXMC interrupt */
411 void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source);
412 /* disable EXMC interrupt */
413 void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source);
414
415 #endif /* GD32F10X_EXMC_H */
exmc_nand_deinit
void exmc_nand_deinit(uint32_t nand_bank)
deinitialize EXMC NAND bank
Definition: gd32f10x_exmc.c:235
exmc_norsram_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:160
exmc_norsram_parameter_struct::extended_mode
uint32_t extended_mode
Definition: gd32f10x_exmc.h:152
exmc_norsram_init
void exmc_norsram_init(exmc_norsram_parameter_struct *norsram_init_struct)
initialize EXMC NOR/SRAM region
Definition: gd32f10x_exmc.c:109
exmc_norsram_timing_parameter_struct
Definition: gd32f10x_exmc.h:136
exmc_norsram_timing_parameter_struct::asyn_data_setuptime
uint32_t asyn_data_setuptime
Definition: gd32f10x_exmc.h:142
exmc_interrupt_flag_get
FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source)
check EXMC interrupt flag is set or not
Definition: gd32f10x_exmc.c:534
exmc_nand_parameter_init
void exmc_nand_parameter_init(exmc_nand_parameter_struct *nand_init_struct)
initialize the struct exmc_norsram_parameter_struct
Definition: gd32f10x_exmc.c:293
exmc_flag_get
FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag)
check EXMC flag is set or not
Definition: gd32f10x_exmc.c:485
exmc_pccard_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:195
exmc_nand_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:185
exmc_nand_pccard_timing_parameter_struct::waittime
uint32_t waittime
Definition: gd32f10x_exmc.h:173
exmc_norsram_parameter_struct::write_mode
uint32_t write_mode
Definition: gd32f10x_exmc.h:151
exmc_pccard_deinit
void exmc_pccard_deinit(void)
deinitialize EXMC PC card bank
Definition: gd32f10x_exmc.c:374
exmc_norsram_timing_parameter_struct::asyn_address_setuptime
uint32_t asyn_address_setuptime
Definition: gd32f10x_exmc.h:144
exmc_nand_pccard_timing_parameter_struct
Definition: gd32f10x_exmc.h:169
exmc_interrupt_disable
void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source)
disable EXMC interrupt
Definition: gd32f10x_exmc.c:604
exmc_nand_parameter_struct::ctr_latency
uint32_t ctr_latency
Definition: gd32f10x_exmc.h:183
exmc_pccard_init
void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct)
initialize EXMC PC card bank
Definition: gd32f10x_exmc.c:396
exmc_ecc_get
uint32_t exmc_ecc_get(uint32_t nand_bank)
get the EXMC ECC value
Definition: gd32f10x_exmc.c:363
exmc_norsram_parameter_struct::norsram_region
uint32_t norsram_region
Definition: gd32f10x_exmc.h:150
exmc_nand_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:187
exmc_norsram_timing_parameter_struct::syn_clk_division
uint32_t syn_clk_division
Definition: gd32f10x_exmc.h:140
exmc_interrupt_flag_clear
void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source)
clear EXMC interrupt flag
Definition: gd32f10x_exmc.c:566
exmc_norsram_parameter_struct::nwait_config
uint32_t nwait_config
Definition: gd32f10x_exmc.h:156
exmc_norsram_parameter_struct::write_timing
exmc_norsram_timing_parameter_struct * write_timing
Definition: gd32f10x_exmc.h:165
exmc_norsram_timing_parameter_struct::asyn_access_mode
uint32_t asyn_access_mode
Definition: gd32f10x_exmc.h:138
exmc_nand_parameter_struct
Definition: gd32f10x_exmc.h:178
exmc_nand_ecc_config
void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue)
enable or disable the EXMC NAND ECC function
Definition: gd32f10x_exmc.c:345
exmc_nand_pccard_timing_parameter_struct::databus_hiztime
uint32_t databus_hiztime
Definition: gd32f10x_exmc.h:171
exmc_norsram_disable
void exmc_norsram_disable(uint32_t norsram_region)
disable EXMC NOR/PSRAM bank region
Definition: gd32f10x_exmc.c:223
exmc_norsram_parameter_struct::read_write_timing
exmc_norsram_timing_parameter_struct * read_write_timing
Definition: gd32f10x_exmc.h:163
exmc_norsram_enable
void exmc_norsram_enable(uint32_t norsram_region)
enable EXMC NOR/PSRAM bank region
Definition: gd32f10x_exmc.c:211
exmc_norsram_parameter_struct::burst_mode
uint32_t burst_mode
Definition: gd32f10x_exmc.h:159
exmc_nand_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:188
exmc_norsram_parameter_struct::memory_type
uint32_t memory_type
Definition: gd32f10x_exmc.h:161
exmc_pccard_parameter_struct
Definition: gd32f10x_exmc.h:192
exmc_norsram_parameter_struct::asyn_wait
uint32_t asyn_wait
Definition: gd32f10x_exmc.h:153
exmc_pccard_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:196
exmc_norsram_parameter_struct
Definition: gd32f10x_exmc.h:148
exmc_nand_parameter_struct::wait_feature
uint32_t wait_feature
Definition: gd32f10x_exmc.h:186
exmc_norsram_parameter_struct::nwait_polarity
uint32_t nwait_polarity
Definition: gd32f10x_exmc.h:158
exmc_pccard_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:194
exmc_nand_parameter_struct::ecc_logic
uint32_t ecc_logic
Definition: gd32f10x_exmc.h:184
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
exmc_norsram_parameter_struct::nwait_signal
uint32_t nwait_signal
Definition: gd32f10x_exmc.h:154
exmc_nand_enable
void exmc_nand_enable(uint32_t nand_bank)
enable NAND bank
Definition: gd32f10x_exmc.c:320
exmc_norsram_parameter_init
void exmc_norsram_parameter_init(exmc_norsram_parameter_struct *norsram_init_struct)
initialize the struct exmc_norsram_parameter_struct
Definition: gd32f10x_exmc.c:170
exmc_pccard_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:197
exmc_pccard_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:198
exmc_nand_parameter_struct::ecc_size
uint32_t ecc_size
Definition: gd32f10x_exmc.h:181
exmc_pccard_parameter_struct::io_space_timing
exmc_nand_pccard_timing_parameter_struct * io_space_timing
Definition: gd32f10x_exmc.h:199
exmc_norsram_parameter_struct::wrap_burst_mode
uint32_t wrap_burst_mode
Definition: gd32f10x_exmc.h:157
exmc_norsram_parameter_struct::address_data_mux
uint32_t address_data_mux
Definition: gd32f10x_exmc.h:162
exmc_nand_parameter_struct::nand_bank
uint32_t nand_bank
Definition: gd32f10x_exmc.h:180
exmc_norsram_deinit
void exmc_norsram_deinit(uint32_t norsram_region)
deinitialize EXMC NOR/SRAM region
Definition: gd32f10x_exmc.c:75
exmc_pccard_disable
void exmc_pccard_disable(void)
disable PC Card Bank
Definition: gd32f10x_exmc.c:466
exmc_norsram_parameter_struct::memory_write
uint32_t memory_write
Definition: gd32f10x_exmc.h:155
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
exmc_nand_init
void exmc_nand_init(exmc_nand_parameter_struct *nand_init_struct)
initialize EXMC NAND bank
Definition: gd32f10x_exmc.c:259
exmc_nand_disable
void exmc_nand_disable(uint32_t nand_bank)
disable NAND bank
Definition: gd32f10x_exmc.c:332
exmc_norsram_timing_parameter_struct::asyn_address_holdtime
uint32_t asyn_address_holdtime
Definition: gd32f10x_exmc.h:143
exmc_norsram_timing_parameter_struct::bus_latency
uint32_t bus_latency
Definition: gd32f10x_exmc.h:141
exmc_pccard_enable
void exmc_pccard_enable(void)
enable PC Card Bank
Definition: gd32f10x_exmc.c:455
exmc_interrupt_enable
void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source)
enable EXMC interrupt
Definition: gd32f10x_exmc.c:585
exmc_nand_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:182
exmc_norsram_timing_parameter_struct::syn_data_latency
uint32_t syn_data_latency
Definition: gd32f10x_exmc.h:139
exmc_pccard_parameter_init
void exmc_pccard_parameter_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct)
initialize the struct exmc_pccard_parameter_struct
Definition: gd32f10x_exmc.c:429
exmc_flag_clear
void exmc_flag_clear(uint32_t bank, uint32_t flag)
clear EXMC flag
Definition: gd32f10x_exmc.c:515
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_regs.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usb_regs.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USB_REGS_H
14 #define USB_REGS_H
15
16 #include "usb_conf.h"
17
18 #define USBFS USBFS_BASE
20 /* registers location definitions */
21 #define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U))
22 #define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x))
23 #define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x))
24 #define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x))
25 #define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x))
26 #define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x))
27 #define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x))
28 #define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x))
29 #define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x))
30 #define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x))
31 #define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x))
32 #define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x))
33 #define LOCATE_FIFO(x) (((x) + 1U) << 12U)
35 /* registers definitions */
36 #define USB_GOTGCS REG32(((USBFS) + 0x0000U))
37 #define USB_GOTGINTF REG32(((USBFS) + 0x0004U))
38 #define USB_GAHBCS REG32(((USBFS) + 0x0008U))
39 #define USB_GUSBCS REG32(((USBFS) + 0x000CU))
40 #define USB_GRSTCTL REG32(((USBFS) + 0x0010U))
41 #define USB_GINTF REG32(((USBFS) + 0x0014U))
42 #define USB_GINTEN REG32(((USBFS) + 0x0018U))
43 #define USB_GRSTATR REG32(((USBFS) + 0x001CU))
44 #define USB_GRSTATP REG32(((USBFS) + 0x0020U))
45 #define USB_GRFLEN REG32(((USBFS) + 0x0024U))
46 #define USB_HNPTFLEN REG32(((USBFS) + 0x0028U))
47 #define USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U))
48 #define USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU))
49 #define USB_GCCFG REG32(((USBFS) + 0x0038U))
50 #define USB_CID REG32(((USBFS) + 0x003CU))
51 #define USB_HPTFLEN REG32(((USBFS) + 0x0100U))
52 #define USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x)))
54 #define USB_HCTL REG32(((USBFS) + 0x0400U))
55 #define USB_HFT REG32(((USBFS) + 0x0404U))
56 #define USB_HFINFR REG32(((USBFS) + 0x0408U))
57 #define USB_HPTFQSTAT REG32(((USBFS) + 0x0410U))
58 #define USB_HACHINT REG32(((USBFS) + 0x0414U))
59 #define USB_HACHINTEN REG32(((USBFS) + 0x0418U))
60 #define USB_HPCS REG32(((USBFS) + 0x0440U))
61 #define USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x)))
62 #define USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x)))
63 #define USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x)))
64 #define USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x)))
66 #define USB_DCFG REG32(((USBFS) + 0x0800U))
67 #define USB_DCTL REG32(((USBFS) + 0x0804U))
68 #define USB_DSTAT REG32(((USBFS) + 0x0808U))
69 #define USB_DIEPINTEN REG32(((USBFS) + 0x0810U))
70 #define USB_DOEPINTEN REG32(((USBFS) + 0x0814U))
71 #define USB_DAEPINT REG32(((USBFS) + 0x0818U))
72 #define USB_DAEPINTEN REG32(((USBFS) + 0x081CU))
73 #define USB_DVBUSDT REG32(((USBFS) + 0x0828U))
74 #define USB_DVBUSPT REG32(((USBFS) + 0x082CU))
75 #define USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U))
76 #define USB_DEP1INT REG32(((USBFS) + 0x0838U))
77 #define USB_DEP1INTEN REG32(((USBFS) + 0x083CU))
78 #define USB_DIEP1INTEN REG32(((USBFS) + 0x0844U))
79 #define USB_DOEP1INTEN REG32(((USBFS) + 0x0884U))
80 #define USB_DIEP0CTL REG32(((USBFS) + 0x0900U))
81 #define USB_DIEP0LEN REG32(((USBFS) + 0x0910U))
82 #define USB_DOEP0CTL REG32(((USBFS) + 0x0B00U))
83 #define USB_DOEP0LEN REG32(((USBFS) + 0x0B10U))
84 #define USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x)))
85 #define USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x)))
86 #define USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x)))
87 #define USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x)))
88 #define USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x)))
89 #define USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x)))
90 #define USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x)))
92 #define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U))
94 #define USB_FIFO(x) (&REG32(((USBFS) + LOCATE_FIFO(x))))
96 /* global OTG control and status register bits definitions */
97 #define GOTGCS_BSV BIT(19)
98 #define GOTGCS_ASV BIT(18)
99 #define GOTGCS_DI BIT(17)
100 #define GOTGCS_IDPS BIT(16)
101 #define GOTGCS_DHNPEN BIT(11)
102 #define GOTGCS_HHNPEN BIT(10)
103 #define GOTGCS_HNPREQ BIT(9)
104 #define GOTGCS_HNPS BIT(8)
105 #define GOTGCS_SRPREQ BIT(1)
106 #define GOTGCS_SRPS BIT(0)
108 /* global OTG interrupt flag register bits definitions */
109 #define GOTGINTF_DF BIT(19)
110 #define GOTGINTF_ADTO BIT(18)
111 #define GOTGINTF_HNPDET BIT(17)
112 #define GOTGINTF_HNPEND BIT(9)
113 #define GOTGINTF_SRPEND BIT(8)
114 #define GOTGINTF_SESEND BIT(2)
116 /* global AHB control and status register bits definitions */
117 #define GAHBCS_PTXFTH BIT(8)
118 #define GAHBCS_TXFTH BIT(7)
119 #define GAHBCS_GINTEN BIT(0)
121 /* global USB control and status register bits definitions */
122 #define GUSBCS_FDM BIT(30)
123 #define GUSBCS_FHM BIT(29)
124 #define GUSBCS_UTT BITS(10, 13)
125 #define GUSBCS_HNPCEN BIT(9)
126 #define GUSBCS_SRPCEN BIT(8)
127 #define GUSBCS_TOC BITS(0, 2)
129 /* global reset control register bits definitions */
130 #define GRSTCTL_TXFNUM BITS(6, 10)
131 #define GRSTCTL_TXFF BIT(5)
132 #define GRSTCTL_RXFF BIT(4)
133 #define GRSTCTL_HFCRST BIT(2)
134 #define GRSTCTL_HCSRST BIT(1)
135 #define GRSTCTL_CSRST BIT(0)
137 /* global interrupt flag register bits definitions */
138 #define GINTF_WKUPIF BIT(31)
139 #define GINTF_SESIF BIT(30)
140 #define GINTF_DISCIF BIT(29)
141 #define GINTF_IDPSC BIT(28)
142 #define GINTF_PTXFEIF BIT(26)
143 #define GINTF_HCIF BIT(25)
144 #define GINTF_HPIF BIT(24)
145 #define GINTF_PXNCIF BIT(21)
146 #define GINTF_ISOONCIF BIT(21)
147 #define GINTF_ISOINCIF BIT(20)
148 #define GINTF_OEPIF BIT(19)
149 #define GINTF_IEPIF BIT(18)
150 #define GINTF_EOPFIF BIT(15)
151 #define GINTF_ISOOPDIF BIT(14)
152 #define GINTF_ENUMF BIT(13)
153 #define GINTF_RST BIT(12)
154 #define GINTF_SP BIT(11)
155 #define GINTF_ESP BIT(10)
156 #define GINTF_GONAK BIT(7)
157 #define GINTF_GNPINAK BIT(6)
158 #define GINTF_NPTXFEIF BIT(5)
159 #define GINTF_RXFNEIF BIT(4)
160 #define GINTF_SOF BIT(3)
161 #define GINTF_OTGIF BIT(2)
162 #define GINTF_MFIF BIT(1)
163 #define GINTF_COPM BIT(0)
165 /* global interrupt enable register bits definitions */
166 #define GINTEN_WKUPIE BIT(31)
167 #define GINTEN_SESIE BIT(30)
168 #define GINTEN_DISCIE BIT(29)
169 #define GINTEN_IDPSCIE BIT(28)
170 #define GINTEN_PTXFEIE BIT(26)
171 #define GINTEN_HCIE BIT(25)
172 #define GINTEN_HPIE BIT(24)
173 #define GINTEN_PXNCIE BIT(21)
174 #define GINTEN_ISOONCIE BIT(21)
175 #define GINTEN_ISOINCIE BIT(20)
176 #define GINTEN_OEPIE BIT(19)
177 #define GINTEN_IEPIE BIT(18)
178 #define GINTEN_EOPFIE BIT(15)
179 #define GINTEN_ISOOPDIE BIT(14)
180 #define GINTEN_ENUMFIE BIT(13)
181 #define GINTEN_RSTIE BIT(12)
182 #define GINTEN_SPIE BIT(11)
183 #define GINTEN_ESPIE BIT(10)
184 #define GINTEN_GONAKIE BIT(7)
185 #define GINTEN_GNPINAKIE BIT(6)
186 #define GINTEN_NPTXFEIE BIT(5)
187 #define GINTEN_RXFNEIE BIT(4)
188 #define GINTEN_SOFIE BIT(3)
189 #define GINTEN_OTGIE BIT(2)
190 #define GINTEN_MFIE BIT(1)
192 /* global receive status read and pop register bits definitions */
193 #define GRSTATRP_RPCKST BITS(17, 20)
194 #define GRSTATRP_DPID BITS(15, 16)
195 #define GRSTATRP_BCOUNT BITS(4, 14)
196 #define GRSTATRP_CNUM BITS(0, 3)
197 #define GRSTATRP_EPNUM BITS(0, 3)
199 /* global receive FIFO length register bits definitions */
200 #define GRFLEN_RXFD BITS(0, 15)
202 /* host non-periodic transmit FIFO length register bits definitions */
203 #define HNPTFLEN_HNPTXFD BITS(16, 31)
204 #define HNPTFLEN_HNPTXRSAR BITS(0, 15)
206 /* IN endpoint 0 transmit FIFO length register bits definitions */
207 #define DIEP0TFLEN_IEP0TXFD BITS(16, 31)
208 #define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15)
210 /* host non-periodic transmit FIFO/queue status register bits definitions */
211 #define HNPTFQSTAT_NPTXRQTOP BITS(24, 30)
212 #define HNPTFQSTAT_NPTXRQS BITS(16, 23)
213 #define HNPTFQSTAT_NPTXFS BITS(0, 15)
214 #define HNPTFQSTAT_CNUM BITS(27, 30)
215 #define HNPTFQSTAT_EPNUM BITS(27, 30)
216 #define HNPTFQSTAT_TYPE BITS(25, 26)
217 #define HNPTFQSTAT_TMF BIT(24)
219 /* global core configuration register bits definitions */
220 #define GCCFG_VBUSIG BIT(21)
221 #define GCCFG_SOFOEN BIT(20)
222 #define GCCFG_VBUSBCEN BIT(19)
223 #define GCCFG_VBUSACEN BIT(18)
224 #define GCCFG_PWRON BIT(16)
226 /* core ID register bits definitions */
227 #define CID_CID BITS(0, 31)
229 /* host periodic transmit FIFO length register bits definitions */
230 #define HPTFLEN_HPTXFD BITS(16, 31)
231 #define HPTFLEN_HPTXFSAR BITS(0, 15)
233 /* device IN endpoint transmit FIFO length register bits definitions */
234 #define DIEPTFLEN_IEPTXFD BITS(16, 31)
235 #define DIEPTFLEN_IEPTXRSAR BITS(0, 15)
237 /* host control register bits definitions */
238 #define HCTL_CLKSEL BITS(0, 1)
240 /* host frame interval register bits definitions */
241 #define HFT_FRI BITS(0, 15)
243 /* host frame information remaining register bits definitions */
244 #define HFINFR_FRT BITS(16, 31)
245 #define HFINFR_FRNUM BITS(0, 15)
247 /* host periodic transmit FIFO/queue status register bits definitions */
248 #define HPTFQSTAT_PTXREQT BITS(24, 31)
249 #define HPTFQSTAT_PTXREQS BITS(16, 23)
250 #define HPTFQSTAT_PTXFS BITS(0, 15)
251 #define HPTFQSTAT_OEFRM BIT(31)
252 #define HPTFQSTAT_CNUM BITS(27, 30)
253 #define HPTFQSTAT_EPNUM BITS(27, 30)
254 #define HPTFQSTAT_TYPE BITS(25, 26)
255 #define HPTFQSTAT_TMF BIT(24)
257 /* host all channels interrupt register bits definitions */
258 #define HACHINT_HACHINT BITS(0, 7)
260 /* host all channels interrupt enable register bits definitions */
261 #define HACHINTEN_CINTEN BITS(0, 7)
263 /* host port control and status register bits definitions */
264 #define HPCS_PS BITS(17, 18)
265 #define HPCS_PP BIT(12)
266 #define HPCS_PLST BITS(10, 11)
267 #define HPCS_PRST BIT(8)
268 #define HPCS_PSP BIT(7)
269 #define HPCS_PREM BIT(6)
270 #define HPCS_PEDC BIT(3)
271 #define HPCS_PE BIT(2)
272 #define HPCS_PCD BIT(1)
273 #define HPCS_PCST BIT(0)
275 /* host channel-x control register bits definitions */
276 #define HCHCTL_CEN BIT(31)
277 #define HCHCTL_CDIS BIT(30)
278 #define HCHCTL_ODDFRM BIT(29)
279 #define HCHCTL_DAR BITS(22, 28)
280 #define HCHCTL_MPC BITS(20, 21)
281 #define HCHCTL_EPTYPE BITS(18, 19)
282 #define HCHCTL_LSD BIT(17)
283 #define HCHCTL_EPDIR BIT(15)
284 #define HCHCTL_EPNUM BITS(11, 14)
285 #define HCHCTL_MPL BITS(0, 10)
287 /* host channel-x interrupt flag register bits definitions */
288 #define HCHINTF_DTER BIT(10)
289 #define HCHINTF_REQOVR BIT(9)
290 #define HCHINTF_BBER BIT(8)
291 #define HCHINTF_USBER BIT(7)
292 #define HCHINTF_NYET BIT(6)
293 #define HCHINTF_ACK BIT(5)
294 #define HCHINTF_NAK BIT(4)
295 #define HCHINTF_STALL BIT(3)
296 #define HCHINTF_CH BIT(1)
297 #define HCHINTF_TF BIT(0)
299 /* host channel-x interrupt enable register bits definitions */
300 #define HCHINTEN_DTERIE BIT(10)
301 #define HCHINTEN_REQOVRIE BIT(9)
302 #define HCHINTEN_BBERIE BIT(8)
303 #define HCHINTEN_USBERIE BIT(7)
304 #define HCHINTEN_NYETIE BIT(6)
305 #define HCHINTEN_ACKIE BIT(5)
306 #define HCHINTEN_NAKIE BIT(4)
307 #define HCHINTEN_STALLIE BIT(3)
308 #define HCHINTEN_CHIE BIT(1)
309 #define HCHINTEN_TFIE BIT(0)
311 /* host channel-x transfer length register bits definitions */
312 #define HCHLEN_DPID BITS(29, 30)
313 #define HCHLEN_PCNT BITS(19, 28)
314 #define HCHLEN_TLEN BITS(0, 18)
316 /* host channel-x DMA address register bits definitions */
317 //#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
318
319 /* device control and status registers */
320 /* device configuration registers bits definitions */
321 #define DCFG_EOPFT BITS(11, 12)
322 #define DCFG_DAR BITS(4, 10)
323 #define DCFG_NZLSOH BIT(2)
324 #define DCFG_DS BITS(0, 1)
326 /* device control registers bits definitions */
327 #define DCTL_POIF BIT(11)
328 #define DCTL_CGONAK BIT(10)
329 #define DCTL_SGONAK BIT(9)
330 #define DCTL_CGINAK BIT(8)
331 #define DCTL_SGINAK BIT(7)
332 #define DCTL_GONS BIT(3)
333 #define DCTL_GINS BIT(2)
334 #define DCTL_SD BIT(1)
335 #define DCTL_RWKUP BIT(0)
337 /* device status registers bits definitions */
338 #define DSTAT_FNRSOF BITS(8, 21)
339 #define DSTAT_ES BITS(1, 2)
340 #define DSTAT_SPST BIT(0)
342 /* device IN endpoint common interrupt enable registers bits definitions */
343 #define DIEPINTEN_TXFEEN BIT(7)
344 #define DIEPINTEN_IEPNEEN BIT(6)
345 #define DIEPINTEN_EPTXFUDEN BIT(4)
346 #define DIEPINTEN_CITOEN BIT(3)
347 #define DIEPINTEN_EPDISEN BIT(1)
348 #define DIEPINTEN_TFEN BIT(0)
350 /* device OUT endpoint common interrupt enable registers bits definitions */
351 #define DOEPINTEN_BTBSTPEN BIT(6)
352 #define DOEPINTEN_EPRXFOVREN BIT(4)
353 #define DOEPINTEN_STPFEN BIT(3)
354 #define DOEPINTEN_EPDISEN BIT(1)
355 #define DOEPINTEN_TFEN BIT(0)
357 /* device all endpoints interrupt registers bits definitions */
358 #define DAEPINT_OEPITB BITS(16, 21)
359 #define DAEPINT_IEPITB BITS(0, 5)
361 /* device all endpoints interrupt enable registers bits definitions */
362 #define DAEPINTEN_OEPIE BITS(16, 21)
363 #define DAEPINTEN_IEPIE BITS(0, 3)
365 /* device Vbus discharge time registers bits definitions */
366 #define DVBUSDT_DVBUSDT BITS(0, 15)
368 /* device Vbus pulsing time registers bits definitions */
369 #define DVBUSPT_DVBUSPT BITS(0, 11)
371 /* device IN endpoint FIFO empty interrupt enable register bits definitions */
372 #define DIEPFEINTEN_IEPTXFEIE BITS(0, 3)
374 /* device endpoint 0 control register bits definitions */
375 #define DEP0CTL_EPEN BIT(31)
376 #define DEP0CTL_EPD BIT(30)
377 #define DEP0CTL_SNAK BIT(27)
378 #define DEP0CTL_CNAK BIT(26)
379 #define DIEP0CTL_TXFNUM BITS(22, 25)
380 #define DEP0CTL_STALL BIT(21)
381 #define DEP0CTL_EPTYPE BITS(18, 19)
382 #define DEP0CTL_NAKS BIT(17)
383 #define DEP0CTL_EPACT BIT(15)
384 #define DEP0CTL_MPL BITS(0, 1)
386 /* device endpoint x control register bits definitions */
387 #define DEPCTL_EPEN BIT(31)
388 #define DEPCTL_EPD BIT(30)
389 #define DEPCTL_SODDFRM BIT(29)
390 #define DEPCTL_SD1PID BIT(29)
391 #define DEPCTL_SEVNFRM BIT(28)
392 #define DEPCTL_SD0PID BIT(28)
393 #define DEPCTL_SNAK BIT(27)
394 #define DEPCTL_CNAK BIT(26)
395 #define DIEPCTL_TXFNUM BITS(22, 25)
396 #define DEPCTL_STALL BIT(21)
397 //#define DOEPCTL_SNOOP BIT(20)
398 #define DEPCTL_EPTYPE BITS(18, 19)
399 #define DEPCTL_NAKS BIT(17)
400 #define DEPCTL_EOFRM BIT(16)
401 #define DEPCTL_DPID BIT(16)
402 #define DEPCTL_EPACT BIT(15)
403 #define DEPCTL_MPL BITS(0, 10)
405 /* device IN endpoint-x interrupt flag register bits definitions */
406 #define DIEPINTF_TXFE BIT(7)
407 #define DIEPINTF_IEPNE BIT(6)
408 #define DIEPINTF_EPTXFUD BIT(4)
409 #define DIEPINTF_CITO BIT(3)
410 #define DIEPINTF_EPDIS BIT(1)
411 #define DIEPINTF_TF BIT(0)
413 /* device OUT endpoint-x interrupt flag register bits definitions */
414 #define DOEPINTF_BTBSTP BIT(6)
415 #define DOEPINTF_EPRXFOVR BIT(4)
416 #define DOEPINTF_STPF BIT(3)
417 #define DOEPINTF_EPDIS BIT(1)
418 #define DOEPINTF_TF BIT(0)
420 /* device IN endpoint 0 transfer length register bits definitions */
421 #define DIEP0LEN_PCNT BITS(19, 20)
422 #define DIEP0LEN_TLEN BITS(0, 6)
424 /* device OUT endpoint 0 transfer length register bits definitions */
425 #define DOEP0LEN_STPCNT BITS(29, 30)
426 #define DOEP0LEN_PCNT BIT(19)
427 #define DOEP0LEN_TLEN BITS(0, 6)
429 /* device OUT endpoint-x transfer length register bits definitions */
430 #define DOEPLEN_RXDPID BITS(29, 30)
431 #define DOEPLEN_STPCNT BITS(29, 30)
432 #define DIEPLEN_MCNT BITS(29, 30)
433 #define DEPLEN_PCNT BITS(19, 28)
434 #define DEPLEN_TLEN BITS(0, 18)
436 /* device IN endpoint-x transmit FIFO status register bits definitions */
437 #define DIEPTFSTAT_IEPTFS BITS(0, 15)
439 /* USB power and clock registers bits definition */
440 #define PWRCLKCTL_SHCLK BIT(1)
441 #define PWRCLKCTL_SUCLK BIT(0)
443 /* register options defines */
444 #define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U))
446 #define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U)
447 #define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U)
448 #define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U)
450 #define GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U))
452 #define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U)
453 #define TXFIFO_EMPTY GAHBCS_TFEL(1U)
455 #define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U))
457 #define DMA_INCR0 GAHBCS_DMAINCR(0U)
458 #define DMA_INCR1 GAHBCS_DMAINCR(1U)
459 #define DMA_INCR4 GAHBCS_DMAINCR(3U)
460 #define DMA_INCR8 GAHBCS_DMAINCR(5U)
461 #define DMA_INCR16 GAHBCS_DMAINCR(7U)
463 #define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U))
465 #define FRAME_INTERVAL_80 DCFG_PFRI(0U)
466 #define FRAME_INTERVAL_85 DCFG_PFRI(1U)
467 #define FRAME_INTERVAL_90 DCFG_PFRI(2U)
468 #define FRAME_INTERVAL_95 DCFG_PFRI(3U)
470 #define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U))
472 #define EP0MPL_64 DEP0_MPL(0U)
473 #define EP0MPL_32 DEP0_MPL(1U)
474 #define EP0MPL_16 DEP0_MPL(2U)
475 #define EP0MPL_8 DEP0_MPL(3U)
477 /* endpoints address */
478
479 /* first bit is direction(0 for Rx and 1 for Tx) */
480 #define EP0_OUT ((uint8_t)0x00U)
481 #define EP0_IN ((uint8_t)0x80U)
482 #define EP1_OUT ((uint8_t)0x01U)
483 #define EP1_IN ((uint8_t)0x81U)
484 #define EP2_OUT ((uint8_t)0x02U)
485 #define EP2_IN ((uint8_t)0x82U)
486 #define EP3_OUT ((uint8_t)0x03U)
487 #define EP3_IN ((uint8_t)0x83U)
489 /* enable global interrupt */
490 #define USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN)
491
492 /* disable global interrupt */
493 #define USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN)
494
495 /* get current operation mode */
496 #define USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM)
497
498 /* read global interrupt flag */
499 #define USB_CORE_INTR_READ(x) \
500 do { \
501 uint32_t global_intf = USB_GINTF; \
502 (x) = global_intf & USB_GINTEN; \
503 } while(0)
504
505 /* read global interrupt flag */
506 #define USB_DAOEP_INTR_READ(x) \
507 do { \
508 uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
509 uint32_t dev_all_ep_int = USB_DAEPINT; \
510 uint32_t out_ep_intb = DAEPINT_OEPITB; \
511 (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \
512 } while(0)
513
514 /* read out endpoint-x interrupt flag */
515 #define USB_DOEP_INTR_READ(x, EpID) \
516 do { \
517 uint32_t out_epintf = USB_DOEPxINTF(EpID); \
518 (x) = out_epintf & USB_DOEPINTEN; \
519 } while(0)
520
521 /* read all in endpoint interrupt flag */
522 #define USB_DAIEP_INTR_READ(x) \
523 do { \
524 uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
525 uint32_t dev_all_ep_int = USB_DAEPINT; \
526 uint32_t in_ep_intb = DAEPINT_IEPITB; \
527 (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \
528 } while(0)
529
530
531 /* read in endpoint-x interrupt flag */
532 #define USB_DIEP_INTR_READ(x, EpID) \
533 do { \
534 uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \
535 uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \
536 uint32_t dev_inep_inten = USB_DIEPINTEN; \
537 (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \
538 } while(0)
539
540 /* generate remote wakup signal */
541 #define USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP)
542
543 /* no remote wakup signal generate */
544 #define USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP)
545
546 /* generate soft disconnect */
547 #define USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD)
548
549 /* no soft disconnect generate */
550 #define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD)
551
552 /* set device address */
553 #define USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U)
554
555 /* check whether frame is even */
556 #define USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U))
557
558 /* read port status */
559 #define USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC))
560
561 /* usb clock initialize */
562 #define USB_FSLSCLOCK_INIT(ClockFreq) \
563 do { \
564 USB_HCTL &= ~HCTL_CLKSEL; \
565 USB_HCTL |= ClockFreq; \
566 } while(0)
567
568 /* get usb current speed */
569 #define USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17)
570
571 /* get usb current frame */
572 #define USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU)
573
574 #endif /* USB_REGS_H */
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_exmc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_exmc.h"
14
15 /* EXMC bank0 register reset value */
16 #define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DBU)
17 #define BANK0_SNCTL1_2_3_REGION_RESET ((uint32_t)0x000030D2U)
18 #define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)
19 #define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU)
20
21 /* EXMC bank1/2 register reset mask*/
22 #define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U)
23 #define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U)
24 #define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)
25 #define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)
26
27 /* EXMC bank3 register reset mask*/
28 #define BANK3_NPCTL_RESET ((uint32_t)0x00000018U)
29 #define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U)
30 #define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)
31 #define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)
32 #define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU)
33
34 /* EXMC register bit offset */
35 #define SNCTL_NRMUX_OFFSET ((uint32_t)1U)
36 #define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U)
37 #define SNCTL_WRAPEN_OFFSET ((uint32_t)10U)
38 #define SNCTL_WREN_OFFSET ((uint32_t)12U)
39 #define SNCTL_NRWTEN_OFFSET ((uint32_t)13U)
40 #define SNCTL_EXMODEN_OFFSET ((uint32_t)14U)
41 #define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)
42
43 #define SNTCFG_AHLD_OFFSET ((uint32_t)4U)
44 #define SNTCFG_DSET_OFFSET ((uint32_t)8U)
45 #define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)
46
47 #define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U)
48 #define SNWTCFG_WDSET_OFFSET ((uint32_t)8U)
49 #define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U)
50
51 #define NPCTL_NDWTEN_OFFSET ((uint32_t)1U)
52 #define NPCTL_ECCEN_OFFSET ((uint32_t)6U)
53
54 #define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U)
55 #define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U)
56 #define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U)
57
58 #define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U)
59 #define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U)
60 #define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U)
61
62 #define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U)
63 #define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U)
64 #define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U)
65
66 #define INTEN_INTS_OFFSET ((uint32_t)3U)
67
75 void exmc_norsram_deinit(uint32_t norsram_region)
76 {
77 /* reset the registers */
78 if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
79 EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
80 }else{
81 EXMC_SNCTL(norsram_region) = BANK0_SNCTL1_2_3_REGION_RESET;
82 }
83
84 EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET;
85 EXMC_SNWTCFG(norsram_region) = BANK0_SNWTCFG_RESET;
86 }
87
109 void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
110 {
111 uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U;
112
113 /* get the register value */
114 snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
115
116 /* clear relative bits */
117 snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN |
118 EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN |
119 EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR |
120 EXMC_SNCTL_NRMUX ));
121
122 snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
123 exmc_norsram_init_struct->memory_type |
124 exmc_norsram_init_struct->databus_width |
125 (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) |
126 exmc_norsram_init_struct->nwait_polarity |
127 (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) |
128 exmc_norsram_init_struct->nwait_config |
129 (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
130 (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
131 (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) |
132 (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) |
133 exmc_norsram_init_struct->write_mode;
134
135 sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
136 (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
137 (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
138 (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )|
139 exmc_norsram_init_struct->read_write_timing->syn_clk_division |
140 exmc_norsram_init_struct->read_write_timing->syn_data_latency |
141 exmc_norsram_init_struct->read_write_timing->asyn_access_mode;
142
143 /* nor flash access enable */
144 if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
145 snctl |= (uint32_t)EXMC_SNCTL_NREN;
146 }
147
148 /* extended mode configure */
149 if(ENABLE == exmc_norsram_init_struct->extended_mode){
150 snwtcfg = (uint32_t)(((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) |
151 (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD)|
152 (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNWTCFG_WDSET) |
153 exmc_norsram_init_struct->write_timing->asyn_access_mode);
154 }else{
155 snwtcfg = BANK0_SNWTCFG_RESET;
156 }
157
158 /* configure the registers */
159 EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
160 EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
161 EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg;
162 }
163
170 void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
171 {
172 /* configure the structure with default value */
173 exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
174 exmc_norsram_init_struct->address_data_mux = ENABLE;
175 exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
176 exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B;
177 exmc_norsram_init_struct->burst_mode = DISABLE;
178 exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
179 exmc_norsram_init_struct->wrap_burst_mode = DISABLE;
180 exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE;
181 exmc_norsram_init_struct->memory_write = ENABLE;
182 exmc_norsram_init_struct->nwait_signal = ENABLE;
183 exmc_norsram_init_struct->extended_mode = DISABLE;
184 exmc_norsram_init_struct->asyn_wait = DISABLE;
185 exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE;
186
187 /* read/write timing configure */
188 exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
189 exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
190 exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
191 exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
192 exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK;
193 exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK;
194 exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
195
196 /* write timing configure, when extended mode is used */
197 exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU;
198 exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU;
199 exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU;
200 exmc_norsram_init_struct->write_timing->bus_latency = 0xFU;
201 exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
202 }
203
211 void exmc_norsram_enable(uint32_t norsram_region)
212 {
213 EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
214 }
215
223 void exmc_norsram_disable(uint32_t norsram_region)
224 {
225 EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
226 }
227
235 void exmc_nand_deinit(uint32_t nand_bank)
236 {
237 /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */
238 EXMC_NPCTL(nand_bank) = BANK1_2_NPCTL_RESET;
239 EXMC_NPINTEN(nand_bank) = BANK1_2_NPINTEN_RESET;
240 EXMC_NPCTCFG(nand_bank) = BANK1_2_NPCTCFG_RESET;
241 EXMC_NPATCFG(nand_bank) = BANK1_2_NPATCFG_RESET;
242 }
243
259 void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct)
260 {
261 uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U;
262
263 npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)|
264 EXMC_NPCTL_NDTP |
265 exmc_nand_init_struct->databus_width |
266 (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)|
267 exmc_nand_init_struct->ecc_size |
268 exmc_nand_init_struct->ctr_latency |
269 exmc_nand_init_struct->atr_latency;
270
271 npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) |
272 (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
273 ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
274 (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
275
276 npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
277 (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
278 ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) |
279 (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
280
281 /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */
282 EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl;
283 EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg;
284 EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg;
285 }
286
293 void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct)
294 {
295 /* configure the structure with default value */
296 exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND;
297 exmc_nand_init_struct->wait_feature = DISABLE;
298 exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B;
299 exmc_nand_init_struct->ecc_logic = DISABLE;
300 exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES;
301 exmc_nand_init_struct->ctr_latency = 0x0U;
302 exmc_nand_init_struct->atr_latency = 0x0U;
303 exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU;
304 exmc_nand_init_struct->common_space_timing->waittime = 0xFCU;
305 exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU;
306 exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU;
307 exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU;
308 exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU;
309 exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU;
310 exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
311 }
312
320 void exmc_nand_enable(uint32_t nand_bank)
321 {
322 EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_NDBKEN;
323 }
324
332 void exmc_nand_disable(uint32_t nand_bank)
333 {
334 EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_NDBKEN;
335 }
336
345 void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue)
346 {
347 if (ENABLE == newvalue){
348 /* enable the selected NAND bank ECC function */
349 EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_ECCEN;
350 }else{
351 /* disable the selected NAND bank ECC function */
352 EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_ECCEN;
353 }
354 }
355
363 uint32_t exmc_ecc_get(uint32_t nand_bank)
364 {
365 return (EXMC_NECC(nand_bank));
366 }
367
374 void exmc_pccard_deinit(void)
375 {
376 /* EXMC_BANK3_PCCARD */
377 EXMC_NPCTL3 = BANK3_NPCTL_RESET;
378 EXMC_NPINTEN3 = BANK3_NPINTEN_RESET;
379 EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET;
380 EXMC_NPATCFG3 = BANK3_NPATCFG_RESET;
381 EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET;
382 }
383
396 void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct)
397 {
398 /* configure the EXMC bank3 PC card control register */
399 EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) |
400 EXMC_NAND_DATABUS_WIDTH_16B |
401 exmc_pccard_init_struct->ctr_latency |
402 exmc_pccard_init_struct->atr_latency ;
403
404 /* configure the EXMC bank3 PC card common space timing configuration register */
405 EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) |
406 (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
407 ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
408 (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
409
410 /* configure the EXMC bank3 PC card attribute space timing configuration register */
411 EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
412 (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
413 ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )|
414 (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
415
416 /* configure the EXMC bank3 PC card io space timing configuration register */
417 EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) |
418 (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) |
419 ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )|
420 ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ );
421 }
422
429 void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct)
430 {
431 /* configure the structure with default value */
432 exmc_pccard_init_struct->wait_feature = DISABLE;
433 exmc_pccard_init_struct->ctr_latency = 0x0U;
434 exmc_pccard_init_struct->atr_latency = 0x0U;
435 exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU;
436 exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU;
437 exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU;
438 exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU;
439 exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU;
440 exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU;
441 exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU;
442 exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
443 exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU;
444 exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU;
445 exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU;
446 exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU;
447 }
448
455 void exmc_pccard_enable(void)
456 {
457 EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN;
458 }
459
466 void exmc_pccard_disable(void)
467 {
468 EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN;
469 }
470
485 FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag)
486 {
487 uint32_t status = 0x00000000U;
488
489 /* NAND bank1,bank2 or PC card bank3 */
490 status = EXMC_NPINTEN(bank);
491
492 if ((status & flag) != (uint32_t)flag ){
493 /* flag is reset */
494 return RESET;
495 }else{
496 /* flag is set */
497 return SET;
498 }
499 }
500
515 void exmc_flag_clear(uint32_t bank, uint32_t flag)
516 {
517 /* NAND bank1,bank2 or PC card bank3 */
518 EXMC_NPINTEN(bank) &= ~flag;
519 }
520
534 FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source)
535 {
536 uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U;
537
538 /* NAND bank1,bank2 or PC card bank3 */
539 status = EXMC_NPINTEN(bank);
540 interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET));
541
542 interrupt_enable = (status & interrupt_source);
543
544 if ((interrupt_enable) && (interrupt_state)){
545 /* interrupt flag is set */
546 return SET;
547 }else{
548 /* interrupt flag is reset */
549 return RESET;
550 }
551 }
552
566 void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source)
567 {
568 /* NAND bank1,bank2 or PC card bank3 */
569 EXMC_NPINTEN(bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET);
570 }
571
585 void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source)
586 {
587 /* NAND bank1,bank2 or PC card bank3 */
588 EXMC_NPINTEN(bank) |= interrupt_source;
589 }
590
604 void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source)
605 {
606 /* NAND bank1,bank2 or PC card bank3 */
607 EXMC_NPINTEN(bank) &= ~interrupt_source;
608 }
EXMC_NPATCFG_ATTHLD
#define EXMC_NPATCFG_ATTHLD
Definition: gd32f10x_exmc.h:122
EXMC_MEMORY_TYPE_SRAM
#define EXMC_MEMORY_TYPE_SRAM
Definition: gd32f10x_exmc.h:228
exmc_norsram_parameter_struct::databus_width
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Definition: gd32f10x_exmc.h:160
exmc_norsram_parameter_struct::extended_mode
uint32_t extended_mode
Definition: gd32f10x_exmc.h:152
exmc_nand_disable
void exmc_nand_disable(uint32_t nand_bank)
disable NAND bank
Definition: gd32f10x_exmc.c:332
exmc_nand_parameter_init
void exmc_nand_parameter_init(exmc_nand_parameter_struct *exmc_nand_init_struct)
initialize the struct exmc_norsram_parameter_struct
Definition: gd32f10x_exmc.c:293
exmc_pccard_parameter_init
void exmc_pccard_parameter_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct)
initialize the struct exmc_pccard_parameter_struct
Definition: gd32f10x_exmc.c:429
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#define EXMC_NPCTL_NDTP
Definition: gd32f10x_exmc.h:97
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uint32_t asyn_data_setuptime
Definition: gd32f10x_exmc.h:142
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#define EXMC_SNCTL_ASYNCWAIT
Definition: gd32f10x_exmc.h:73
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#define BANK1_2_NPCTCFG_RESET
Definition: gd32f10x_exmc.c:24
exmc_interrupt_disable
void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source)
disable EXMC interrupt
Definition: gd32f10x_exmc.c:604
EXMC_SNWTCFG
#define EXMC_SNWTCFG(region)
Definition: gd32f10x_exmc.h:205
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#define EXMC_NPATCFG3
Definition: gd32f10x_exmc.h:55
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uint32_t ctr_latency
Definition: gd32f10x_exmc.h:195
EXMC_NPINTEN3
#define EXMC_NPINTEN3
Definition: gd32f10x_exmc.h:53
EXMC_SNWTCFG_WAHLD
#define EXMC_SNWTCFG_WAHLD
Definition: gd32f10x_exmc.h:87
NPATCFG_ATTHLD_OFFSET
#define NPATCFG_ATTHLD_OFFSET
Definition: gd32f10x_exmc.c:59
exmc_nand_parameter_struct::databus_width
uint32_t databus_width
Definition: gd32f10x_exmc.h:185
BANK3_PIOTCFG3_RESET
#define BANK3_PIOTCFG3_RESET
Definition: gd32f10x_exmc.c:32
EXMC_SNCTL_NRWTEN
#define EXMC_SNCTL_NRWTEN
Definition: gd32f10x_exmc.h:71
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uint32_t waittime
Definition: gd32f10x_exmc.h:173
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Definition: gd32f10x_exmc.h:151
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#define EXMC_NPATCFG(bank)
Definition: gd32f10x_exmc.h:210
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#define EXMC_SNCTL_SYNCWR
Definition: gd32f10x_exmc.h:74
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#define SNCTL_EXMODEN_OFFSET
Definition: gd32f10x_exmc.c:40
EXMC_PIOTCFG3_IOSET
#define EXMC_PIOTCFG3_IOSET
Definition: gd32f10x_exmc.h:126
BANK1_2_NPATCFG_RESET
#define BANK1_2_NPATCFG_RESET
Definition: gd32f10x_exmc.c:25
BANK3_NPATCFG_RESET
#define BANK3_NPATCFG_RESET
Definition: gd32f10x_exmc.c:31
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#define EXMC_SNCTL_NRBKEN
Definition: gd32f10x_exmc.h:61
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#define EXMC_NPCTCFG_COMSET
Definition: gd32f10x_exmc.h:114
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uint32_t asyn_address_setuptime
Definition: gd32f10x_exmc.h:144
EXMC_NECC
#define EXMC_NECC(bank)
Definition: gd32f10x_exmc.h:211
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uint32_t ctr_latency
Definition: gd32f10x_exmc.h:183
BANK0_SNCTL0_REGION_RESET
#define BANK0_SNCTL0_REGION_RESET
Definition: gd32f10x_exmc.c:16
BANK1_2_NPINTEN_RESET
#define BANK1_2_NPINTEN_RESET
Definition: gd32f10x_exmc.c:23
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#define EXMC_ASYN_WRITE
Definition: gd32f10x_exmc.h:336
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#define EXMC_NPATCFG_ATTWAIT
Definition: gd32f10x_exmc.h:121
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Definition: gd32f10x_exmc.h:150
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#define NPCTCFG_COMWAIT_OFFSET
Definition: gd32f10x_exmc.c:54
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Definition: gd32f10x_exmc.h:187
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#define EXMC_PIOTCFG3_IOHIZ
Definition: gd32f10x_exmc.h:129
exmc_ecc_get
uint32_t exmc_ecc_get(uint32_t nand_bank)
get the EXMC ECC value
Definition: gd32f10x_exmc.c:363
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#define EXMC_NPATCFG_ATTHIZ
Definition: gd32f10x_exmc.h:123
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Definition: gd32f10x_exmc.c:29
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Definition: gd32f10x_exmc.h:78
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Definition: gd32f10x_exmc.h:140
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Definition: gd32f10x_exmc.c:66
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Definition: gd32f10x_exmc.h:203
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Definition: gd32f10x_exmc.h:64
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Definition: gd32f10x_exmc.h:56
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Definition: gd32f10x_exmc.c:39
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Definition: gd32f10x_exmc.c:17
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Definition: gd32f10x_exmc.h:156
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Definition: gd32f10x_exmc.h:165
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Definition: gd32f10x_exmc.h:138
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Definition: gd32f10x_exmc.c:30
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Definition: gd32f10x_exmc.h:230
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#define PIOTCFG_IOHIZ_OFFSET
Definition: gd32f10x_exmc.c:64
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Definition: gd32f10x_exmc.h:178
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Definition: gd32f10x_exmc.h:171
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#define NPATCFG_ATTWAIT_OFFSET
Definition: gd32f10x_exmc.c:58
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exmc_norsram_timing_parameter_struct * read_write_timing
Definition: gd32f10x_exmc.h:163
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Definition: gd32f10x_exmc.h:52
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Definition: gd32f10x_exmc.h:204
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Definition: gd32f10x_exmc.h:159
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#define EXMC_NPCTCFG_COMWAIT
Definition: gd32f10x_exmc.h:115
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Definition: gd32f10x_exmc.h:88
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#define EXMC_BANK1_NAND
Definition: gd32f10x_exmc.h:348
exmc_norsram_enable
void exmc_norsram_enable(uint32_t norsram_region)
enable EXMC NOR/PSRAM bank region
Definition: gd32f10x_exmc.c:211
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#define EXMC_NPCTCFG_COMHLD
Definition: gd32f10x_exmc.h:116
exmc_interrupt_flag_get
FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source)
check EXMC interrupt flag is set or not
Definition: gd32f10x_exmc.c:534
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exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:188
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Definition: gd32f10x_exmc.h:161
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Definition: gd32f10x_exmc.c:38
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Definition: gd32f10x_exmc.h:66
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Definition: gd32f10x_exmc.h:192
exmc_norsram_parameter_struct::asyn_wait
uint32_t asyn_wait
Definition: gd32f10x_exmc.h:153
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#define SNCTL_NRMUX_OFFSET
Definition: gd32f10x_exmc.c:35
exmc_norsram_disable
void exmc_norsram_disable(uint32_t norsram_region)
disable EXMC NOR/PSRAM bank region
Definition: gd32f10x_exmc.c:223
exmc_norsram_parameter_init
void exmc_norsram_parameter_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
initialize the struct exmc_norsram_parameter_struct
Definition: gd32f10x_exmc.c:170
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uint32_t wait_feature
Definition: gd32f10x_exmc.h:196
exmc_norsram_parameter_struct
Definition: gd32f10x_exmc.h:148
EXMC_NAND_DATABUS_WIDTH_8B
#define EXMC_NAND_DATABUS_WIDTH_8B
Definition: gd32f10x_exmc.h:326
BANK0_SNWTCFG_RESET
#define BANK0_SNWTCFG_RESET
Definition: gd32f10x_exmc.c:19
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Definition: gd32f10x_exmc.h:186
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uint32_t nwait_polarity
Definition: gd32f10x_exmc.h:158
exmc_pccard_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:194
exmc_nand_parameter_struct::ecc_logic
uint32_t ecc_logic
Definition: gd32f10x_exmc.h:184
exmc_nand_init
void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct)
initialize EXMC NAND bank
Definition: gd32f10x_exmc.c:259
BANK1_2_NPCTL_RESET
#define BANK1_2_NPCTL_RESET
Definition: gd32f10x_exmc.c:22
exmc_nand_deinit
void exmc_nand_deinit(uint32_t nand_bank)
deinitialize EXMC NAND bank
Definition: gd32f10x_exmc.c:235
exmc_nand_ecc_config
void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue)
enable or disable the EXMC NAND ECC function
Definition: gd32f10x_exmc.c:345
EXMC_SNCTL_WRAPEN
#define EXMC_SNCTL_WRAPEN
Definition: gd32f10x_exmc.h:68
exmc_nand_pccard_timing_parameter_struct::setuptime
uint32_t setuptime
Definition: gd32f10x_exmc.h:174
EXMC_PIOTCFG3_IOHLD
#define EXMC_PIOTCFG3_IOHLD
Definition: gd32f10x_exmc.h:128
EXMC_NWAIT_POLARITY_LOW
#define EXMC_NWAIT_POLARITY_LOW
Definition: gd32f10x_exmc.h:344
BANK3_NPCTL_RESET
#define BANK3_NPCTL_RESET
Definition: gd32f10x_exmc.c:28
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uint32_t nwait_signal
Definition: gd32f10x_exmc.h:154
EXMC_SYN_CLOCK_RATIO_16_CLK
#define EXMC_SYN_CLOCK_RATIO_16_CLK
Definition: gd32f10x_exmc.h:275
SNCTL_SBRSTEN_OFFSET
#define SNCTL_SBRSTEN_OFFSET
Definition: gd32f10x_exmc.c:36
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#define BANK0_SNTCFG_RESET
Definition: gd32f10x_exmc.c:18
EXMC_SNCTL_EXMODEN
#define EXMC_SNCTL_EXMODEN
Definition: gd32f10x_exmc.h:72
exmc_flag_get
FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag)
check EXMC flag is set or not
Definition: gd32f10x_exmc.c:485
EXMC_NPCTCFG
#define EXMC_NPCTCFG(bank)
Definition: gd32f10x_exmc.h:209
exmc_pccard_parameter_struct::common_space_timing
exmc_nand_pccard_timing_parameter_struct * common_space_timing
Definition: gd32f10x_exmc.h:197
EXMC_SNTCFG_BUSLAT
#define EXMC_SNTCFG_BUSLAT
Definition: gd32f10x_exmc.h:80
EXMC_NPCTCFG3
#define EXMC_NPCTCFG3
Definition: gd32f10x_exmc.h:54
NPCTCFG_COMHLD_OFFSET
#define NPCTCFG_COMHLD_OFFSET
Definition: gd32f10x_exmc.c:55
exmc_nand_enable
void exmc_nand_enable(uint32_t nand_bank)
enable NAND bank
Definition: gd32f10x_exmc.c:320
exmc_pccard_parameter_struct::attribute_space_timing
exmc_nand_pccard_timing_parameter_struct * attribute_space_timing
Definition: gd32f10x_exmc.h:198
exmc_nand_parameter_struct::ecc_size
uint32_t ecc_size
Definition: gd32f10x_exmc.h:181
NPATCFG_ATTHIZ_OFFSET
#define NPATCFG_ATTHIZ_OFFSET
Definition: gd32f10x_exmc.c:60
EXMC_NPATCFG_ATTSET
#define EXMC_NPATCFG_ATTSET
Definition: gd32f10x_exmc.h:120
EXMC_SNWTCFG_WASET
#define EXMC_SNWTCFG_WASET
Definition: gd32f10x_exmc.h:86
exmc_interrupt_flag_clear
void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source)
clear EXMC interrupt flag
Definition: gd32f10x_exmc.c:566
exmc_pccard_deinit
void exmc_pccard_deinit(void)
deinitialize EXMC PC card bank
Definition: gd32f10x_exmc.c:374
SNTCFG_DSET_OFFSET
#define SNTCFG_DSET_OFFSET
Definition: gd32f10x_exmc.c:44
PIOTCFG_IOWAIT_OFFSET
#define PIOTCFG_IOWAIT_OFFSET
Definition: gd32f10x_exmc.c:62
SNCTL_ASYNCWAIT_OFFSET
#define SNCTL_ASYNCWAIT_OFFSET
Definition: gd32f10x_exmc.c:41
SNCTL_WRAPEN_OFFSET
#define SNCTL_WRAPEN_OFFSET
Definition: gd32f10x_exmc.c:37
EXMC_ACCESS_MODE_A
#define EXMC_ACCESS_MODE_A
Definition: gd32f10x_exmc.h:234
EXMC_SNCTL_WREN
#define EXMC_SNCTL_WREN
Definition: gd32f10x_exmc.h:70
exmc_pccard_parameter_struct::io_space_timing
exmc_nand_pccard_timing_parameter_struct * io_space_timing
Definition: gd32f10x_exmc.h:199
EXMC_BANK0_NORSRAM_REGION0
#define EXMC_BANK0_NORSRAM_REGION0
Definition: gd32f10x_exmc.h:330
exmc_norsram_deinit
void exmc_norsram_deinit(uint32_t norsram_region)
deinitialize EXMC NOR/SRAM region
Definition: gd32f10x_exmc.c:75
EXMC_SNCTL_NRWTPOL
#define EXMC_SNCTL_NRWTPOL
Definition: gd32f10x_exmc.h:67
EXMC_SNCTL_NREN
#define EXMC_SNCTL_NREN
Definition: gd32f10x_exmc.h:65
EXMC_SNCTL_NRTP
#define EXMC_SNCTL_NRTP
Definition: gd32f10x_exmc.h:63
exmc_norsram_parameter_struct::wrap_burst_mode
uint32_t wrap_burst_mode
Definition: gd32f10x_exmc.h:157
exmc_norsram_parameter_struct::address_data_mux
uint32_t address_data_mux
Definition: gd32f10x_exmc.h:162
exmc_nand_parameter_struct::nand_bank
uint32_t nand_bank
Definition: gd32f10x_exmc.h:180
SNTCFG_AHLD_OFFSET
#define SNTCFG_AHLD_OFFSET
Definition: gd32f10x_exmc.c:43
SNTCFG_BUSLAT_OFFSET
#define SNTCFG_BUSLAT_OFFSET
Definition: gd32f10x_exmc.c:45
exmc_norsram_init
void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
initialize EXMC NOR/SRAM region
Definition: gd32f10x_exmc.c:109
exmc_norsram_parameter_struct::memory_write
uint32_t memory_write
Definition: gd32f10x_exmc.h:155
PIOTCFG_IOHLD_OFFSET
#define PIOTCFG_IOHLD_OFFSET
Definition: gd32f10x_exmc.c:63
NPCTCFG_COMHIZ_OFFSET
#define NPCTCFG_COMHIZ_OFFSET
Definition: gd32f10x_exmc.c:56
EXMC_ECC_SIZE_256BYTES
#define EXMC_ECC_SIZE_256BYTES
Definition: gd32f10x_exmc.h:279
EXMC_DATALAT_17_CLK
#define EXMC_DATALAT_17_CLK
Definition: gd32f10x_exmc.h:256
exmc_nand_pccard_timing_parameter_struct::holdtime
uint32_t holdtime
Definition: gd32f10x_exmc.h:172
EXMC_NPCTCFG_COMHIZ
#define EXMC_NPCTCFG_COMHIZ
Definition: gd32f10x_exmc.h:117
exmc_pccard_disable
void exmc_pccard_disable(void)
disable PC Card Bank
Definition: gd32f10x_exmc.c:466
exmc_norsram_timing_parameter_struct::asyn_address_holdtime
uint32_t asyn_address_holdtime
Definition: gd32f10x_exmc.h:143
exmc_pccard_enable
void exmc_pccard_enable(void)
enable PC Card Bank
Definition: gd32f10x_exmc.c:455
exmc_interrupt_enable
void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source)
enable EXMC interrupt
Definition: gd32f10x_exmc.c:585
EXMC_SNTCFG_DSET
#define EXMC_SNTCFG_DSET
Definition: gd32f10x_exmc.h:79
EXMC_NWAIT_CONFIG_BEFORE
#define EXMC_NWAIT_CONFIG_BEFORE
Definition: gd32f10x_exmc.h:340
EXMC_NPCTL
#define EXMC_NPCTL(bank)
Definition: gd32f10x_exmc.h:207
EXMC_NPCTL_ECCEN
#define EXMC_NPCTL_ECCEN
Definition: gd32f10x_exmc.h:99
EXMC_PIOTCFG3_IOWAIT
#define EXMC_PIOTCFG3_IOWAIT
Definition: gd32f10x_exmc.h:127
exmc_norsram_timing_parameter_struct::bus_latency
uint32_t bus_latency
Definition: gd32f10x_exmc.h:141
EXMC_NOR_DATABUS_WIDTH_8B
#define EXMC_NOR_DATABUS_WIDTH_8B
Definition: gd32f10x_exmc.h:223
EXMC_SNTCFG_ASET
#define EXMC_SNTCFG_ASET
Definition: gd32f10x_exmc.h:77
EXMC_NPCTL_NDBKEN
#define EXMC_NPCTL_NDBKEN
Definition: gd32f10x_exmc.h:96
gd32f10x_exmc.h
definitions for the EXMC
EXMC_NAND_DATABUS_WIDTH_16B
#define EXMC_NAND_DATABUS_WIDTH_16B
Definition: gd32f10x_exmc.h:327
exmc_nand_parameter_struct::atr_latency
uint32_t atr_latency
Definition: gd32f10x_exmc.h:182
NPCTL_ECCEN_OFFSET
#define NPCTL_ECCEN_OFFSET
Definition: gd32f10x_exmc.c:52
exmc_flag_clear
void exmc_flag_clear(uint32_t bank, uint32_t flag)
clear EXMC flag
Definition: gd32f10x_exmc.c:515
EXMC_SNCTL_NRMUX
#define EXMC_SNCTL_NRMUX
Definition: gd32f10x_exmc.h:62
EXMC_SNCTL_NRWTCFG
#define EXMC_SNCTL_NRWTCFG
Definition: gd32f10x_exmc.h:69
EXMC_NPINTEN
#define EXMC_NPINTEN(bank)
Definition: gd32f10x_exmc.h:208
exmc_norsram_timing_parameter_struct::syn_data_latency
uint32_t syn_data_latency
Definition: gd32f10x_exmc.h:139
NPCTL_NDWTEN_OFFSET
#define NPCTL_NDWTEN_OFFSET
Definition: gd32f10x_exmc.c:51
exmc_pccard_init
void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct)
initialize EXMC PC card bank
Definition: gd32f10x_exmc.c:396
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_fwdgt.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_FWDGT_H
14 #define GD32F10X_FWDGT_H
15
16 #include "gd32f10x.h"
17
18 /* FWDGT definitions */
19 #define FWDGT FWDGT_BASE
21 /* registers definitions */
22 #define FWDGT_CTL REG32((FWDGT) + 0x00U)
23 #define FWDGT_PSC REG32((FWDGT) + 0x04U)
24 #define FWDGT_RLD REG32((FWDGT) + 0x08U)
25 #define FWDGT_STAT REG32((FWDGT) + 0x0CU)
27 /* bits definitions */
28 /* FWDGT_CTL */
29 #define FWDGT_CTL_CMD BITS(0,15)
31 /* FWDGT_PSC */
32 #define FWDGT_PSC_PSC BITS(0,2)
34 /* FWDGT_RLD */
35 #define FWDGT_RLD_RLD BITS(0,11)
37 /* FWDGT_STAT */
38 #define FWDGT_STAT_PUD BIT(0)
39 #define FWDGT_STAT_RUD BIT(1)
41 /* constants definitions */
42 /* psc register value */
43 #define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
44 #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0))
45 #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1))
46 #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2))
47 #define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3))
48 #define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4))
49 #define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5))
50 #define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6))
52 /* control value */
53 #define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U)
54 #define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U)
55 #define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU)
56 #define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU)
58 /* FWDGT timeout value */
59 #define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU)
60 #define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU)
62 /* FWDGT flag definitions */
63 #define FWDGT_FLAG_PUD FWDGT_STAT_PUD
64 #define FWDGT_FLAG_RUD FWDGT_STAT_RUD
66 /* function declarations */
67 /* disable write access to FWDGT_PSC and FWDGT_RLD */
68 void fwdgt_write_disable(void);
69 /* start the free watchdog timer counter */
70 void fwdgt_enable(void);
71
72 /* reload the counter of FWDGT */
73 void fwdgt_counter_reload(void);
74 /* configure counter reload value, and prescaler divider value */
75 ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
76
77 /* get flag state of FWDGT */
78 FlagStatus fwdgt_flag_get(uint16_t flag);
79
80 #endif /* GD32F10X_FWDGT_H */
fwdgt_write_disable
void fwdgt_write_disable(void)
disable write access to FWDGT_PSC and FWDGT_RLD
Definition: gd32f10x_fwdgt.c:26
fwdgt_enable
void fwdgt_enable(void)
start the free watchdog timer counter
Definition: gd32f10x_fwdgt.c:48
fwdgt_flag_get
FlagStatus fwdgt_flag_get(uint16_t flag)
get flag state of FWDGT
Definition: gd32f10x_fwdgt.c:110
fwdgt_config
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
configure counter reload value, and prescaler divider value
Definition: gd32f10x_fwdgt.c:68
fwdgt_counter_reload
void fwdgt_counter_reload(void)
reload the counter of FWDGT
Definition: gd32f10x_fwdgt.c:37
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_i2c.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_I2C_H
14 #define GD32F10X_I2C_H
15
16 #include "gd32f10x.h"
17
18 /* I2Cx(x=0,1) definitions */
19 #define I2C0 I2C_BASE
20 #define I2C1 (I2C_BASE+0x400U)
21
22 /* registers definitions */
23 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U)
24 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U)
25 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U)
26 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU)
27 #define I2C_DATA(i2cx) REG32((i2cx) + 0x10U)
28 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U)
29 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U)
30 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU)
31 #define I2C_RT(i2cx) REG32((i2cx) + 0x20U)
33 /* bits definitions */
34 /* I2Cx_CTL0 */
35 #define I2C_CTL0_I2CEN BIT(0)
36 #define I2C_CTL0_SMBEN BIT(1)
37 #define I2C_CTL0_SMBSEL BIT(3)
38 #define I2C_CTL0_ARPEN BIT(4)
39 #define I2C_CTL0_PECEN BIT(5)
40 #define I2C_CTL0_GCEN BIT(6)
41 #define I2C_CTL0_DISSTRC BIT(7)
42 #define I2C_CTL0_START BIT(8)
43 #define I2C_CTL0_STOP BIT(9)
44 #define I2C_CTL0_ACKEN BIT(10)
45 #define I2C_CTL0_POAP BIT(11)
46 #define I2C_CTL0_PECTRANS BIT(12)
47 #define I2C_CTL0_SALT BIT(13)
48 #define I2C_CTL0_SRESET BIT(15)
50 /* I2Cx_CTL1 */
51 #define I2C_CTL1_I2CCLK BITS(0,5)
52 #define I2C_CTL1_ERRIE BIT(8)
53 #define I2C_CTL1_EVIE BIT(9)
54 #define I2C_CTL1_BUFIE BIT(10)
55 #define I2C_CTL1_DMAON BIT(11)
56 #define I2C_CTL1_DMALST BIT(12)
58 /* I2Cx_SADDR0 */
59 #define I2C_SADDR0_ADDRESS0 BIT(0)
60 #define I2C_SADDR0_ADDRESS BITS(1,7)
61 #define I2C_SADDR0_ADDRESS_H BITS(8,9)
62 #define I2C_SADDR0_ADDFORMAT BIT(15)
64 /* I2Cx_SADDR1 */
65 #define I2C_SADDR1_DUADEN BIT(0)
66 #define I2C_SADDR1_ADDRESS2 BITS(1,7)
68 /* I2Cx_DATA */
69 #define I2C_DATA_TRB BITS(0,7)
71 /* I2Cx_STAT0 */
72 #define I2C_STAT0_SBSEND BIT(0)
73 #define I2C_STAT0_ADDSEND BIT(1)
74 #define I2C_STAT0_BTC BIT(2)
75 #define I2C_STAT0_ADD10SEND BIT(3)
76 #define I2C_STAT0_STPDET BIT(4)
77 #define I2C_STAT0_RBNE BIT(6)
78 #define I2C_STAT0_TBE BIT(7)
79 #define I2C_STAT0_BERR BIT(8)
80 #define I2C_STAT0_LOSTARB BIT(9)
81 #define I2C_STAT0_AERR BIT(10)
82 #define I2C_STAT0_OUERR BIT(11)
83 #define I2C_STAT0_PECERR BIT(12)
84 #define I2C_STAT0_SMBTO BIT(14)
85 #define I2C_STAT0_SMBALT BIT(15)
87 /* I2Cx_STAT1 */
88 #define I2C_STAT1_MASTER BIT(0)
89 #define I2C_STAT1_I2CBSY BIT(1)
90 #define I2C_STAT1_TRS BIT(2)
91 #define I2C_STAT1_RXGC BIT(4)
92 #define I2C_STAT1_DEFSMB BIT(5)
93 #define I2C_STAT1_HSTSMB BIT(6)
94 #define I2C_STAT1_DUMODF BIT(7)
95 #define I2C_STAT1_ECV BITS(8,15)
97 /* I2Cx_CKCFG */
98 #define I2C_CKCFG_CLKC BITS(0,11)
99 #define I2C_CKCFG_DTCY BIT(14)
100 #define I2C_CKCFG_FAST BIT(15)
102 /* I2Cx_RT */
103 #define I2C_RT_RISETIME BITS(0,5)
105 /* constants definitions */
106 /* SMBus/I2C mode switch and SMBus type selection */
107 #define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U)
108 #define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN
110 /* SMBus/I2C mode switch and SMBus type selection */
111 #define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U)
112 #define I2C_SMBUS_HOST I2C_CTL0_SMBSEL
113 /* I2C transfer direction */
114 #define I2C_RECEIVER ((uint32_t)0x00000001U)
115 #define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU)
117 /* whether or not to send an ACK */
118 #define I2C_ACK_DISABLE ((uint32_t)0x00000000U)
119 #define I2C_ACK_ENABLE ((uint32_t)0x00000001U)
121 /* I2C POAP position*/
122 #define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U)
123 #define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U)
125 /* I2C dual-address mode switch */
126 #define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U)
127 #define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U)
130 /* whether or not to stretch SCL low */
131 #define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U)
132 #define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC
134 /* whether or not to response to a general call */
135 #define I2C_GCEN_ENABLE I2C_CTL0_GCEN
136 #define I2C_GCEN_DISABLE ((uint32_t)0x00000000U)
138 /* software reset I2C */
139 #define I2C_SRESET_SET I2C_CTL0_SRESET
140 #define I2C_SRESET_RESET ((uint32_t)0x00000000U)
142 /* I2C DMA mode configure */
143 /* DMA mode switch */
144 #define I2C_DMA_ON I2C_CTL1_DMAON
145 #define I2C_DMA_OFF ((uint32_t)0x00000000U)
146 /* flag indicating DMA last transfer */
147 #define I2C_DMALST_ON I2C_CTL1_DMALST
148 #define I2C_DMALST_OFF ((uint32_t)0x00000000U)
150 /* I2C PEC configure */
151 /* PEC enable */
152 #define I2C_PEC_ENABLE I2C_CTL0_PECEN
153 #define I2C_PEC_DISABLE ((uint32_t)0x00000000U)
155 /* PEC transfer */
156 #define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS
157 #define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U)
159 /* I2C SMBus configure */
160 /* issue or not alert through SMBA pin */
161 #define I2C_SALTSEND_ENABLE I2C_CTL0_SALT
162 #define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U)
163 /* ARP protocol in SMBus switch */
164 #define I2C_ARP_ENABLE I2C_CTL0_ARPEN
165 #define I2C_ARP_DISABLE ((uint32_t)0x00000000U)
167 /* transmit I2C data */
168 #define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
169
170 /* receive I2C data */
171 #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
172
173 /* I2C flag definitions */
174 #define I2C_FLAG_SBSEND BIT(0)
175 #define I2C_FLAG_ADDSEND BIT(1)
176 #define I2C_FLAG_BTC BIT(2)
177 #define I2C_FLAG_ADD10SEND BIT(3)
178 #define I2C_FLAG_STPDET BIT(4)
179 #define I2C_FLAG_RBNE BIT(6)
180 #define I2C_FLAG_TBE BIT(7)
181 #define I2C_FLAG_BERR BIT(8)
182 #define I2C_FLAG_LOSTARB BIT(9)
183 #define I2C_FLAG_AERR BIT(10)
184 #define I2C_FLAG_OUERR BIT(11)
185 #define I2C_FLAG_PECERR BIT(12)
186 #define I2C_FLAG_SMBTO BIT(14)
187 #define I2C_FLAG_SMBALT BIT(15)
188 #define I2C_FLAG_MASTER (BIT(0)|BIT(31))
189 #define I2C_FLAG_I2CBSY (BIT(1)|BIT(31))
190 #define I2C_FLAG_TRS (BIT(2)|BIT(31))
191 #define I2C_FLAG_RXGC (BIT(4)|BIT(31))
192 #define I2C_FLAG_DEFSMB (BIT(5)|BIT(31))
193 #define I2C_FLAG_HSTSMB (BIT(6)|BIT(31))
194 #define I2C_FLAG_DUMOD (BIT(7)|BIT(31))
196 /* I2C interrupt flags */
197 #define I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND
198 #define I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND
199 #define I2C_INT_FLAG_BTC I2C_FLAG_BTC
200 #define I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND
201 #define I2C_INT_FLAG_STPDET I2C_FLAG_STPDET
202 #define I2C_INT_FLAG_RBNE I2C_FLAG_RBNE
203 #define I2C_INT_FLAG_TBE I2C_FLAG_TBE
204 #define I2C_INT_FLAG_BERR I2C_FLAG_BERR
205 #define I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB
206 #define I2C_INT_FLAG_AERR I2C_FLAG_AERR
207 #define I2C_INT_FLAG_OUERR I2C_FLAG_OUERR
208 #define I2C_INT_FLAG_PECERR I2C_FLAG_PECERR
209 #define I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO
210 #define I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT
212 /* I2C interrupt enable bit */
213 #define I2C_INT_ERR I2C_CTL1_ERRIE
214 #define I2C_INT_EV I2C_CTL1_EVIE
215 #define I2C_INT_BUF I2C_CTL1_BUFIE
217 /* I2C duty cycle in fast mode */
218 #define CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14))
219 #define I2C_DTCY_2 CKCFG_DTCY(0)
220 #define I2C_DTCY_16_9 CKCFG_DTCY(1)
222 /* address mode for the I2C slave */
223 #define SADDR0_ADDFORMAT(regval) (BIT(15) & ((uint32_t)(regval) << 15))
224 #define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0)
225 #define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1)
227 /* function declarations */
228 /* reset I2C */
229 void i2c_deinit(uint32_t i2c_periph);
230 /* configure I2C clock */
231 void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
232 /* configure I2C address */
233 void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
234 /* SMBus type selection */
235 void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
236 /* whether or not to send an ACK */
237 void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
238 /* configure I2C POAP position */
239 void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
240 /* master send slave address */
241 void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
242 /* dual-address mode switch */
243 void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr);
244
245 /* enable I2C */
246 void i2c_enable(uint32_t i2c_periph);
247 /* disable I2C */
248 void i2c_disable(uint32_t i2c_periph);
249 /* generate a START condition on I2C bus */
250 void i2c_start_on_bus(uint32_t i2c_periph);
251 /* generate a STOP condition on I2C bus */
252 void i2c_stop_on_bus(uint32_t i2c_periph);
253 /* I2C transmit data function */
254 void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
255 /* I2C receive data function */
256 uint8_t i2c_data_receive(uint32_t i2c_periph);
257 /* I2C DMA mode enable */
258 void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
259 /* flag indicating DMA last transfer */
260 void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast);
261 /* whether to stretch SCL low when data is not ready in slave mode */
262 void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara );
263 /* whether or not to response to a general call */
264 void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
265 /* software reset I2C */
266 void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
267
268 /* check I2C flag is set or not */
269 FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag);
270 /* clear I2C flag */
271 void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag);
272 /* enable I2C interrupt */
273 void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype);
274 /* disable I2C interrupt */
275 void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype);
276 /* check I2C interrupt flag */
277 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,uint32_t intflag);
278 /* clear I2C interrupt flag */
279 void i2c_interrupt_flag_clear(uint32_t i2c_periph,uint32_t intflag);
280
281 /* I2C PEC calculation on or off */
282 void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
283 /* I2C whether to transfer PEC value */
284 void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
285 /* packet error checking value */
286 uint8_t i2c_pec_value_get(uint32_t i2c_periph);
287 /* I2C issue alert through SMBA pin */
288 void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
289 /* I2C ARP protocol in SMBus switch */
290 void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
291
292 #endif /* GD32F10X_I2C_H */
i2c_dma_last_transfer_enable
void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast)
flag indicating DMA last transfer
Definition: gd32f10x_i2c.c:318
i2c_master_addressing
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
master send slave address
Definition: gd32f10x_i2c.c:195
i2c_interrupt_flag_get
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
check I2C interrupt flag
Definition: gd32f10x_i2c.c:513
i2c_start_on_bus
void i2c_start_on_bus(uint32_t i2c_periph)
generate a START condition on I2C bus
Definition: gd32f10x_i2c.c:251
i2c_stop_on_bus
void i2c_stop_on_bus(uint32_t i2c_periph)
generate a STOP condition on I2C bus
Definition: gd32f10x_i2c.c:262
i2c_disable
void i2c_disable(uint32_t i2c_periph)
disable I2C
Definition: gd32f10x_i2c.c:240
i2c_interrupt_enable
void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
enable I2C interrupt
Definition: gd32f10x_i2c.c:472
i2c_clock_config
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
I2C clock configure.
Definition: gd32f10x_i2c.c:51
i2c_dma_enable
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
enable I2C DMA mode
Definition: gd32f10x_i2c.c:299
i2c_interrupt_disable
void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
disable I2C interrupt
Definition: gd32f10x_i2c.c:487
i2c_stretch_scl_low_config
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
whether to stretch SCL low when data is not ready in slave mode
Definition: gd32f10x_i2c.c:337
i2c_flag_get
FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
check I2C flag is set or not
Definition: gd32f10x_i2c.c:413
i2c_dualaddr_enable
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr)
dual-address mode switch
Definition: gd32f10x_i2c.c:214
i2c_mode_addr_config
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
configure I2C address
Definition: gd32f10x_i2c.c:118
i2c_flag_clear
void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag)
clear I2C flag
Definition: gd32f10x_i2c.c:451
i2c_smbus_type_config
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
SMBus type selection.
Definition: gd32f10x_i2c.c:139
i2c_pec_enable
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
I2C PEC calculation on or off.
Definition: gd32f10x_i2c.c:589
i2c_data_transmit
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
I2C transmit data function.
Definition: gd32f10x_i2c.c:274
i2c_interrupt_flag_clear
void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag)
clear I2C interrupt flag
Definition: gd32f10x_i2c.c:569
i2c_ackpos_config
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
I2C POAP position configure.
Definition: gd32f10x_i2c.c:175
i2c_software_reset_config
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
software reset I2C
Definition: gd32f10x_i2c.c:375
i2c_smbus_arp_enable
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
enable or disable I2C ARP protocol in SMBus switch
Definition: gd32f10x_i2c.c:657
i2c_slave_response_to_gcall_config
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
whether or not to response to a general call
Definition: gd32f10x_i2c.c:356
i2c_pec_transfer_enable
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
I2C whether to transfer PEC value.
Definition: gd32f10x_i2c.c:608
i2c_smbus_issue_alert
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
I2C issue alert through SMBA pin.
Definition: gd32f10x_i2c.c:638
i2c_deinit
void i2c_deinit(uint32_t i2c_periph)
reset I2C
Definition: gd32f10x_i2c.c:25
i2c_enable
void i2c_enable(uint32_t i2c_periph)
enable I2C
Definition: gd32f10x_i2c.c:229
i2c_ack_config
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
whether or not to send an ACK
Definition: gd32f10x_i2c.c:157
i2c_pec_value_get
uint8_t i2c_pec_value_get(uint32_t i2c_periph)
get packet error checking value
Definition: gd32f10x_i2c.c:624
i2c_data_receive
uint8_t i2c_data_receive(uint32_t i2c_periph)
I2C receive data function.
Definition: gd32f10x_i2c.c:285
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_std.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
usbd_std.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBD_STD_H
14 #define USBD_STD_H
15
16 #include "usbd_core.h"
17 #include <wchar.h>
18
19 #ifndef NULL
20 #define NULL 0U
21 #endif
22
23 /* constants definitions */
24 #define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /* device qualifier descriptor length */
25 #define USB_CFG_DESC_LEN 0x09U /* configuration descriptor length */
26
27 #define USBD_LANGID_STR_IDX 0x00U /* language ID string index */
28 #define USBD_MFC_STR_IDX 0x01U /* manufacturer string index */
29 #define USBD_PRODUCT_STR_IDX 0x02U /* product string index */
30 #define USBD_SERIAL_STR_IDX 0x03U /* serial string index */
31 #define USBD_CONFIG_STR_IDX 0x04U /* configuration string index */
32 #define USBD_INTERFACE_STR_IDX 0x05U /* interface string index */
33
34 #define USB_STANDARD_REQ 0x00U /* standard request */
35 #define USB_CLASS_REQ 0x20U /* device class request */
36 #define USB_VENDOR_REQ 0x40U /* vendor request */
37 #define USB_REQ_MASK 0x60U /* request type mask */
38
39 #define USB_REQTYPE_DEVICE 0x00U /* request recipient is device */
40 #define USB_REQTYPE_INTERFACE 0x01U /* request recipient is interface */
41 #define USB_REQTYPE_ENDPOINT 0x02U /* request recipient is endpoint */
42 #define USB_REQ_RECIPIENT_MASK 0x1fU /* request recipient mask */
43
44 #define USBREQ_GET_STATUS 0x00U /* Get_Status standard requeset */
45 #define USBREQ_CLEAR_FEATURE 0x01U /* Clear_Feature standard requeset */
46 #define USBREQ_SET_FEATURE 0x03U /* Set_Feature standard requeset */
47 #define USBREQ_SET_ADDRESS 0x05U /* Set_Address standard requeset */
48 #define USBREQ_GET_DESCRIPTOR 0x06U /* Get_Descriptor standard requeset */
49 #define USBREQ_GET_CONFIGURATION 0x08U /* Get_Configuration standard requeset */
50 #define USBREQ_SET_CONFIGURATION 0x09U /* Set_Configuration standard requeset */
51 #define USBREQ_GET_INTERFACE 0x0AU /* Get_Interface standard requeset */
52 #define USBREQ_SET_INTERFACE 0x0BU /* Set_Interface standard requeset */
53
54 #define USB_DESCTYPE_DEVICE 0x01U /* device descriptor type */
55 #define USB_DESCTYPE_CONFIGURATION 0x02U /* configuration descriptor type */
56 #define USB_DESCTYPE_STRING 0x03U /* string descriptor type */
57 #define USB_DESCTYPE_INTERFACE 0x04U /* interface descriptor type */
58 #define USB_DESCTYPE_ENDPOINT 0x05U /* endpoint descriptor type */
59 #define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /* device qualifier descriptor type */
60 #define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /* other speed configuration descriptor type */
61 #define USB_DESCTYPE_BOS 0x0FU /* BOS descriptor type */
62
63 #define USB_STATUS_REMOTE_WAKEUP 2U /* USB is in remote wakeup status */
64 #define USB_STATUS_SELF_POWERED 1U /* USB is in self powered status */
65
66 #define USB_FEATURE_ENDP_HALT 0U /* USB has endpoint halt feature */
67 #define USB_FEATURE_REMOTE_WAKEUP 1U /* USB has endpoint remote wakeup feature */
68 #define USB_FEATURE_TEST_MODE 2U /* USB has endpoint test mode feature */
69
70 #define ENG_LANGID 0x0409U /* english language ID */
71 #define CHN_LANGID 0x0804U /* chinese language ID */
72
73 #define USB_EPTYPE_MASK 0x03U
74
75 #define USB_DEVICE_DESC_SIZE 0x12U
76
77 /* USB device exported macros */
78 #define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
79 (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
80
81 #define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU))
82 #define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))
83
84 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
85
86 #define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))
87
88 #define WIDE_STRING(string) _WIDE_STRING(string)
89 #define _WIDE_STRING(string) L##string
90
91 #define USBD_STRING_DESC(string) \
92 (void *)&(const struct { \
93 uint8_t _len; \
94 uint8_t _type; \
95 wchar_t _data[sizeof(string)]; \
96 }) { \
97 sizeof(WIDE_STRING(string)) + 2U - 2U, \
98 USB_DESCTYPE_STRING, \
99 WIDE_STRING(string) \
100 }
101
102 typedef struct
103 {
104 uint8_t bLength;
105 uint8_t bDescriptorType;
106 } usb_descriptor_header_struct;
107
108 typedef struct
109 {
110 usb_descriptor_header_struct Header;
112 uint16_t bcdUSB;
113 uint8_t bDeviceClass;
114 uint8_t bDeviceSubClass;
115 uint8_t bDeviceProtocol;
116 uint8_t bMaxPacketSize0;
117 uint16_t idVendor;
118 uint16_t idProduct;
119 uint16_t bcdDevice;
120 uint8_t iManufacturer;
121 uint8_t iProduct;
122 uint8_t iSerialNumber;
123 uint8_t bNumberConfigurations;
124 } usb_descriptor_device_struct;
125
126 #pragma pack(1)
127
128 typedef struct
129 {
130 usb_descriptor_header_struct Header;
132 uint16_t wTotalLength;
133 uint8_t bNumInterfaces;
134 uint8_t bConfigurationValue;
135 uint8_t iConfiguration;
136 uint8_t bmAttributes;
137 uint8_t bMaxPower;
138 } usb_descriptor_configuration_struct;
139
140 #pragma pack()
141
142 typedef struct
143 {
144 usb_descriptor_header_struct Header;
146 uint8_t bInterfaceNumber;
147 uint8_t bAlternateSetting;
148 uint8_t bNumEndpoints;
149 uint8_t bInterfaceClass;
150 uint8_t bInterfaceSubClass;
151 uint8_t bInterfaceProtocol;
152 uint8_t iInterface;
153 } usb_descriptor_interface_struct;
154
155 #pragma pack(1)
156
157 typedef struct
158 {
159 usb_descriptor_header_struct Header;
161 uint8_t bEndpointAddress;
162 uint8_t bmAttributes;
163 uint16_t wMaxPacketSize;
164 uint8_t bInterval;
165 } usb_descriptor_endpoint_struct;
166
167 typedef struct
168 {
169 usb_descriptor_header_struct Header;
170 uint16_t wLANGID;
171 }usb_descriptor_language_id_struct;
172
173 #pragma pack()
174
175 /* function declarations */
176 /* USB SETUP transaction processing */
177 uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev);
178 /* USB OUT transaction processing */
179 uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num);
180 /* USB IN transaction processing */
181 uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num);
182
183 /* handle USB standard device request */
184 uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
185 /* handle device class request */
186 uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
187 /* handle USB vendor request */
188 uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
189
190 /* decode setup data packet */
191 void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
192 /* handle USB enumeration error event */
193 void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
194
195 #endif /* USBD_STD_H */
usb_descriptor_interface_struct::bInterfaceProtocol
uint8_t bInterfaceProtocol
Definition: usbd_std.h:151
usb_descriptor_configuration_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:136
usbd_device_class_request
uint8_t usbd_device_class_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB device class request
Definition: usbd_std.c:235
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:162
usb_descriptor_device_struct::idProduct
uint16_t idProduct
Definition: usbd_std.h:118
usb_descriptor_interface_struct::iInterface
uint8_t iInterface
Definition: usbd_std.h:152
usb_descriptor_configuration_struct::wTotalLength
uint16_t wTotalLength
Definition: usbd_std.h:132
usb_descriptor_language_id_struct::wLANGID
uint16_t wLANGID
Definition: usbd_std.h:170
usb_descriptor_configuration_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:130
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usbd_std.h:148
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usbd_std.h:104
usb_descriptor_interface_struct
Definition: usbd_std.h:142
usb_device_req_struct
Definition: usbd_core.h:115
usbd_in_transaction
uint8_t usbd_in_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data in stage processing
Definition: usbd_std.c:155
usb_descriptor_header_struct
Definition: usbd_std.h:102
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usbd_std.h:161
usb_descriptor_device_struct
Definition: usbd_std.h:108
usb_descriptor_language_id_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:169
usb_descriptor_device_struct::bcdUSB
uint16_t bcdUSB
Definition: usbd_std.h:112
usb_descriptor_interface_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:144
usbd_core.h
usb_descriptor_interface_struct::bInterfaceClass
uint8_t bInterfaceClass
Definition: usbd_std.h:149
usbd_core_handle_struct
Definition: usbd_core.h:125
usb_descriptor_device_struct::bDeviceProtocol
uint8_t bDeviceProtocol
Definition: usbd_std.h:115
usb_descriptor_device_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:110
usb_descriptor_configuration_struct::bConfigurationValue
uint8_t bConfigurationValue
Definition: usbd_std.h:134
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
usb_descriptor_device_struct::bcdDevice
uint16_t bcdDevice
Definition: usbd_std.h:119
usbd_setup_transaction
uint8_t usbd_setup_transaction(usbd_core_handle_struct *pudev)
USB setup stage processing.
Definition: usbd_std.c:80
usb_descriptor_device_struct::bDeviceSubClass
uint8_t bDeviceSubClass
Definition: usbd_std.h:114
usb_descriptor_interface_struct::bInterfaceSubClass
uint8_t bInterfaceSubClass
Definition: usbd_std.h:150
usb_descriptor_device_struct::bNumberConfigurations
uint8_t bNumberConfigurations
Definition: usbd_std.h:123
usb_descriptor_interface_struct::bAlternateSetting
uint8_t bAlternateSetting
Definition: usbd_std.h:147
usbd_setup_request_parse
void usbd_setup_request_parse(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
decode setup data packet
Definition: usbd_std.c:812
usbd_enum_error
void usbd_enum_error(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB enumeration error event
Definition: usbd_std.c:832
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usbd_std.h:163
usb_descriptor_configuration_struct::bNumInterfaces
uint8_t bNumInterfaces
Definition: usbd_std.h:133
usb_descriptor_endpoint_struct::Header
usb_descriptor_header_struct Header
Definition: usbd_std.h:159
usb_descriptor_configuration_struct::iConfiguration
uint8_t iConfiguration
Definition: usbd_std.h:135
usb_descriptor_device_struct::idVendor
uint16_t idVendor
Definition: usbd_std.h:117
usbd_out_transaction
uint8_t usbd_out_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data out stage processing
Definition: usbd_std.c:113
usb_descriptor_interface_struct::bInterfaceNumber
uint8_t bInterfaceNumber
Definition: usbd_std.h:146
usbd_vendor_request
uint8_t usbd_vendor_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB vendor request
Definition: usbd_std.c:268
usb_descriptor_device_struct::iProduct
uint8_t iProduct
Definition: usbd_std.h:121
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usbd_std.h:105
usb_descriptor_device_struct::bDeviceClass
uint8_t bDeviceClass
Definition: usbd_std.h:113
usbd_standard_request
uint8_t usbd_standard_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB standard device request
Definition: usbd_std.c:220
usb_descriptor_language_id_struct
Definition: usbd_std.h:167
usb_descriptor_device_struct::bMaxPacketSize0
uint8_t bMaxPacketSize0
Definition: usbd_std.h:116
usb_descriptor_configuration_struct::bMaxPower
uint8_t bMaxPower
Definition: usbd_std.h:137
usb_descriptor_device_struct::iManufacturer
uint8_t iManufacturer
Definition: usbd_std.h:120
usb_descriptor_endpoint_struct::bInterval
uint8_t bInterval
Definition: usbd_std.h:164
usb_descriptor_device_struct::iSerialNumber
uint8_t iSerialNumber
Definition: usbd_std.h:122
usb_descriptor_configuration_struct
Definition: usbd_std.h:128
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_rcu.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_rcu.h"
14
15 /* define clock source */
16 #define SEL_IRC8M ((uint16_t)0U)
17 #define SEL_HXTAL ((uint16_t)1U)
18 #define SEL_PLL ((uint16_t)2U)
19
20 /* define startup timeout count */
21 #define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)
22 #define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)
23
30 void rcu_deinit(void)
31 {
32 /* enable IRC8M */
33 RCU_CTL |= RCU_CTL_IRC8MEN;
34 rcu_osci_stab_wait(RCU_IRC8M);
35
36 /* reset CFG0 register */
37 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
38 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
39 RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF |
40 RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2);
41 #elif defined(GD32F10X_CL)
42 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
43 RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
44 RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4);
45 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
46 /* reset CTL register */
47 RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
48 RCU_CTL &= ~RCU_CTL_HXTALBPS;
49 #ifdef GD32F10X_CL
50 RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN);
51 #endif /* GD32F10X_CL */
52
53 /* reset INT and CFG1 register */
54 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
55 RCU_INT = 0x009f0000U;
56 #elif defined(GD32F10X_CL)
57 RCU_INT = 0x00ff0000U;
58 RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF |
59 RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL);
60 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
61 }
62
93 void rcu_periph_clock_enable(rcu_periph_enum periph)
94 {
95 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
96 }
97
128 void rcu_periph_clock_disable(rcu_periph_enum periph)
129 {
130 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
131 }
132
142 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
143 {
144 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
145 }
146
156 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
157 {
158 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
159 }
160
184 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
185 {
186 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
187 }
188
212 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
213 {
214 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
215 }
216
223 void rcu_bkp_reset_enable(void)
224 {
225 RCU_BDCTL |= RCU_BDCTL_BKPRST;
226 }
227
234 void rcu_bkp_reset_disable(void)
235 {
236 RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
237 }
238
249 void rcu_system_clock_source_config(uint32_t ck_sys)
250 {
251 uint32_t reg;
252
253 reg = RCU_CFG0;
254 /* reset the SCS bits and set according to ck_sys */
255 reg &= ~RCU_CFG0_SCS;
256 RCU_CFG0 = (reg | ck_sys);
257 }
258
268 uint32_t rcu_system_clock_source_get(void)
269 {
270 return (RCU_CFG0 & RCU_CFG0_SCSS);
271 }
272
281 void rcu_ahb_clock_config(uint32_t ck_ahb)
282 {
283 uint32_t reg;
284
285 reg = RCU_CFG0;
286
287 /* reset the AHBPSC bits and set according to ck_ahb */
288 reg &= ~RCU_CFG0_AHBPSC;
289 RCU_CFG0 = (reg | ck_ahb);
290 }
291
304 void rcu_apb1_clock_config(uint32_t ck_apb1)
305 {
306 uint32_t reg;
307
308 reg = RCU_CFG0;
309
310 /* reset the APB1PSC and set according to ck_apb1 */
311 reg &= ~RCU_CFG0_APB1PSC;
312 RCU_CFG0 = (reg | ck_apb1);
313 }
314
327 void rcu_apb2_clock_config(uint32_t ck_apb2)
328 {
329 uint32_t reg;
330
331 reg = RCU_CFG0;
332
333 /* reset the APB2PSC and set according to ck_apb2 */
334 reg &= ~RCU_CFG0_APB2PSC;
335 RCU_CFG0 = (reg | ck_apb2);
336 }
337
354 void rcu_ckout0_config(uint32_t ckout0_src)
355 {
356 uint32_t reg;
357
358 reg = RCU_CFG0;
359
360 /* reset the CKOUT0SRC, set according to ckout0_src */
361 reg &= ~RCU_CFG0_CKOUT0SEL;
362 RCU_CFG0 = (reg | ckout0_src);
363 }
364
375 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
376 {
377 uint32_t reg = 0U;
378
379 reg = RCU_CFG0;
380
381 /* PLL clock source and multiplication factor configuration */
382 reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
383 reg |= (pll_src | pll_mul);
384
385 RCU_CFG0 = reg;
386 }
387
388 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
389
396 void rcu_predv0_config(uint32_t predv0_div)
397 {
398 uint32_t reg = 0U;
399
400 reg = RCU_CFG0;
401 /* reset PREDV0 bit */
402 reg &= ~RCU_CFG0_PREDV0;
403 if(RCU_PREDV0_DIV2 == predv0_div){
404 /* set the PREDV0 bit */
405 reg |= RCU_CFG0_PREDV0;
406 }
407
408 RCU_CFG0 = reg;
409 }
410 #elif defined(GD32F10X_CL)
411
421 void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div)
422 {
423 uint32_t reg = 0U;
424
425 reg = RCU_CFG1;
426 /* reset PREDV0SEL and PREDV0 bits */
427 reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0);
428 /* set the PREDV0SEL and PREDV0 division factor */
429 reg |= (predv0_source | predv0_div);
430
431 RCU_CFG1 = reg;
432 }
433
441 void rcu_predv1_config(uint32_t predv1_div)
442 {
443 uint32_t reg = 0U;
444
445 reg = RCU_CFG1;
446 /* reset the PREDV1 bits */
447 reg &= ~RCU_CFG1_PREDV1;
448 /* set the PREDV1 division factor */
449 reg |= predv1_div;
450
451 RCU_CFG1 = reg;
452 }
453
461 void rcu_pll1_config(uint32_t pll_mul)
462 {
463 RCU_CFG1 &= ~RCU_CFG1_PLL1MF;
464 RCU_CFG1 |= pll_mul;
465 }
466
474 void rcu_pll2_config(uint32_t pll_mul)
475 {
476 RCU_CFG1 &= ~RCU_CFG1_PLL2MF;
477 RCU_CFG1 |= pll_mul;
478 }
479 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
480
493 void rcu_adc_clock_config(uint32_t adc_psc)
494 {
495 uint32_t reg0;
496
497 /* reset the ADCPSC bits */
498 reg0 = RCU_CFG0;
499 reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC);
500
501 /* set the ADC prescaler factor */
502 switch(adc_psc){
503 case RCU_CKADC_CKAPB2_DIV2:
504 case RCU_CKADC_CKAPB2_DIV4:
505 case RCU_CKADC_CKAPB2_DIV6:
506 case RCU_CKADC_CKAPB2_DIV8:
507 reg0 |= (adc_psc << 14);
508 break;
509
510 case RCU_CKADC_CKAPB2_DIV12:
511 case RCU_CKADC_CKAPB2_DIV16:
512 adc_psc &= ~BIT(2);
513 reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2);
514 break;
515
516 default:
517 break;
518 }
519
520 /* set the register */
521 RCU_CFG0 = reg0;
522 }
523
534 void rcu_usb_clock_config(uint32_t usb_psc)
535 {
536 uint32_t reg;
537
538 reg = RCU_CFG0;
539
540 /* configure the USBD/USBFS prescaler factor */
541 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
542 reg &= ~RCU_CFG0_USBDPSC;
543 #elif defined(GD32F10X_CL)
544 reg &= ~RCU_CFG0_USBFSPSC;
545 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
546
547 RCU_CFG0 = (reg | usb_psc);
548 }
549
561 void rcu_rtc_clock_config(uint32_t rtc_clock_source)
562 {
563 uint32_t reg;
564
565 reg = RCU_BDCTL;
566 /* reset the RTCSRC bits and set according to rtc_clock_source */
567 reg &= ~RCU_BDCTL_RTCSRC;
568 RCU_BDCTL = (reg | rtc_clock_source);
569 }
570
571 #ifdef GD32F10X_CL
572
581 void rcu_i2s1_clock_config(uint32_t i2s_clock_source)
582 {
583 uint32_t reg;
584
585 reg = RCU_CFG1;
586 /* reset the I2S1SEL bit and set according to i2s_clock_source */
587 reg &= ~RCU_CFG1_I2S1SEL;
588 RCU_CFG1 = (reg | i2s_clock_source);
589 }
590
600 void rcu_i2s2_clock_config(uint32_t i2s_clock_source)
601 {
602 uint32_t reg;
603
604 reg = RCU_CFG1;
605 /* reset the I2S2SEL bit and set according to i2s_clock_source */
606 reg &= ~RCU_CFG1_I2S2SEL;
607 RCU_CFG1 = (reg | i2s_clock_source);
608 }
609 #endif /* GD32F10X_CL */
610
631 FlagStatus rcu_flag_get(rcu_flag_enum flag)
632 {
633 /* get the rcu flag */
634 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
635 return SET;
636 }else{
637 return RESET;
638 }
639 }
640
647 void rcu_all_reset_flag_clear(void)
648 {
649 RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
650 }
651
667 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
668 {
669 /* get the rcu interrupt flag */
670 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
671 return SET;
672 }else{
673 return RESET;
674 }
675 }
676
692 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
693 {
694 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
695 }
696
711 void rcu_interrupt_enable(rcu_int_enum stab_int)
712 {
713 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
714 }
715
730 void rcu_interrupt_disable(rcu_int_enum stab_int)
731 {
732 RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
733 }
734
749 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
750 {
751 uint32_t stb_cnt = 0U;
752 ErrStatus reval = ERROR;
753 FlagStatus osci_stat = RESET;
754
755 switch(osci){
756 /* wait HXTAL stable */
757 case RCU_HXTAL:
758 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
759 osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
760 stb_cnt++;
761 }
762
763 /* check whether flag is set or not */
764 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
765 reval = SUCCESS;
766 }
767 break;
768
769 /* wait LXTAL stable */
770 case RCU_LXTAL:
771 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
772 osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
773 stb_cnt++;
774 }
775
776 /* check whether flag is set or not */
777 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
778 reval = SUCCESS;
779 }
780 break;
781
782 /* wait IRC8M stable */
783 case RCU_IRC8M:
784 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
785 osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
786 stb_cnt++;
787 }
788
789 /* check whether flag is set or not */
790 if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
791 reval = SUCCESS;
792 }
793 break;
794
795 /* wait IRC40K stable */
796 case RCU_IRC40K:
797 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
798 osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
799 stb_cnt++;
800 }
801
802 /* check whether flag is set or not */
803 if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
804 reval = SUCCESS;
805 }
806 break;
807
808 /* wait PLL stable */
809 case RCU_PLL_CK:
810 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
811 osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
812 stb_cnt++;
813 }
814
815 /* check whether flag is set or not */
816 if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
817 reval = SUCCESS;
818 }
819 break;
820
821 #ifdef GD32F10X_CL
822 /* wait PLL1 stable */
823 case RCU_PLL1_CK:
824 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
825 osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
826 stb_cnt++;
827 }
828
829 /* check whether flag is set or not */
830 if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){
831 reval = SUCCESS;
832 }
833 break;
834 /* wait PLL2 stable */
835 case RCU_PLL2_CK:
836 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
837 osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
838 stb_cnt++;
839 }
840
841 /* check whether flag is set or not */
842 if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){
843 reval = SUCCESS;
844 }
845 break;
846 #endif /* GD32F10X_CL */
847
848 default:
849 break;
850 }
851
852 /* return value */
853 return reval;
854 }
855
870 void rcu_osci_on(rcu_osci_type_enum osci)
871 {
872 RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
873 }
874
889 void rcu_osci_off(rcu_osci_type_enum osci)
890 {
891 RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
892 }
893
903 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
904 {
905 uint32_t reg;
906
907 switch(osci){
908 /* enable HXTAL to bypass mode */
909 case RCU_HXTAL:
910 reg = RCU_CTL;
911 RCU_CTL &= ~RCU_CTL_HXTALEN;
912 RCU_CTL = (reg | RCU_CTL_HXTALBPS);
913 break;
914 /* enable LXTAL to bypass mode */
915 case RCU_LXTAL:
916 reg = RCU_BDCTL;
917 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
918 RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
919 break;
920 case RCU_IRC8M:
921 case RCU_IRC40K:
922 case RCU_PLL_CK:
923 #ifdef GD32F10X_CL
924 case RCU_PLL1_CK:
925 case RCU_PLL2_CK:
926 #endif /* GD32F10X_CL */
927 break;
928 default:
929 break;
930 }
931 }
932
942 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
943 {
944 uint32_t reg;
945
946 switch(osci){
947 /* disable HXTAL to bypass mode */
948 case RCU_HXTAL:
949 reg = RCU_CTL;
950 RCU_CTL &= ~RCU_CTL_HXTALEN;
951 RCU_CTL = (reg & ~RCU_CTL_HXTALBPS);
952 break;
953 /* disable LXTAL to bypass mode */
954 case RCU_LXTAL:
955 reg = RCU_BDCTL;
956 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
957 RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS);
958 break;
959 case RCU_IRC8M:
960 case RCU_IRC40K:
961 case RCU_PLL_CK:
962 #ifdef GD32F10X_CL
963 case RCU_PLL1_CK:
964 case RCU_PLL2_CK:
965 #endif /* GD32F10X_CL */
966 break;
967 default:
968 break;
969 }
970 }
971
979 void rcu_hxtal_clock_monitor_enable(void)
980 {
981 RCU_CTL |= RCU_CTL_CKMEN;
982 }
983
990 void rcu_hxtal_clock_monitor_disable(void)
991 {
992 RCU_CTL &= ~RCU_CTL_CKMEN;
993 }
994
1001 void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
1002 {
1003 uint32_t reg;
1004
1005 reg = RCU_CTL;
1006 /* reset the IRC8MADJ bits and set according to irc8m_adjval */
1007 reg &= ~RCU_CTL_IRC8MADJ;
1008 RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3));
1009 }
1010
1022 void rcu_deepsleep_voltage_set(uint32_t dsvol)
1023 {
1024 dsvol &= RCU_DSV_DSLPVS;
1025 RCU_DSV = dsvol;
1026 }
1027
1039 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
1040 {
1041 uint32_t sws, ck_freq = 0U;
1042 uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq;
1043 uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp;
1044 #ifdef GD32F10X_CL
1045 uint32_t predv0, predv1, pll1mf;
1046 #endif /* GD32F10X_CL */
1047
1048 /* exponent of AHB, APB1 and APB2 clock divider */
1049 uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
1050 uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
1051 uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
1052
1053 sws = GET_BITS(RCU_CFG0, 2, 3);
1054 switch(sws){
1055 /* IRC8M is selected as CK_SYS */
1056 case SEL_IRC8M:
1057 cksys_freq = IRC8M_VALUE;
1058 break;
1059 /* HXTAL is selected as CK_SYS */
1060 case SEL_HXTAL:
1061 cksys_freq = HXTAL_VALUE;
1062 break;
1063 /* PLL is selected as CK_SYS */
1064 case SEL_PLL:
1065 /* PLL clock source selection, HXTAL or IRC8M/2 */
1066 pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
1067
1068 if(RCU_PLLSRC_HXTAL == pllsel) {
1069 /* PLL clock source is HXTAL */
1070 ck_src = HXTAL_VALUE;
1071
1072 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
1073 predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0);
1074 /* PREDV0 input source clock divided by 2 */
1075 if(RCU_CFG0_PREDV0 == predv0sel){
1076 ck_src = HXTAL_VALUE/2U;
1077 }
1078 #elif defined(GD32F10X_CL)
1079 predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
1080 /* source clock use PLL1 */
1081 if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
1082 predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
1083 pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
1084 if(17U == pll1mf){
1085 pll1mf = 20U;
1086 }
1087 ck_src = (ck_src / predv1) * pll1mf;
1088 }
1089 predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
1090 ck_src /= predv0;
1091 #endif /* GD32F10X_HD and GD32F10X_XD */
1092 }else{
1093 /* PLL clock source is IRC8M/2 */
1094 ck_src = IRC8M_VALUE/2U;
1095 }
1096
1097 /* PLL multiplication factor */
1098 pllmf = GET_BITS(RCU_CFG0, 18, 21);
1099 if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
1100 pllmf |= 0x10U;
1101 }
1102 if(pllmf < 15U){
1103 pllmf += 2U;
1104 }else{
1105 pllmf += 1U;
1106 }
1107
1108 cksys_freq = ck_src * pllmf;
1109
1110 #ifdef GD32F10X_CL
1111 if(15U == pllmf){
1112 /* PLL source clock multiply by 6.5 */
1113 cksys_freq = ck_src * 6U + ck_src / 2U;
1114 }
1115 #endif /* GD32F10X_CL */
1116
1117 break;
1118 /* IRC8M is selected as CK_SYS */
1119 default:
1120 cksys_freq = IRC8M_VALUE;
1121 break;
1122 }
1123
1124 /* calculate AHB clock frequency */
1125 idx = GET_BITS(RCU_CFG0, 4, 7);
1126 clk_exp = ahb_exp[idx];
1127 ahb_freq = cksys_freq >> clk_exp;
1128
1129 /* calculate APB1 clock frequency */
1130 idx = GET_BITS(RCU_CFG0, 8, 10);
1131 clk_exp = apb1_exp[idx];
1132 apb1_freq = ahb_freq >> clk_exp;
1133
1134 /* calculate APB2 clock frequency */
1135 idx = GET_BITS(RCU_CFG0, 11, 13);
1136 clk_exp = apb2_exp[idx];
1137 apb2_freq = ahb_freq >> clk_exp;
1138
1139 /* return the clocks frequency */
1140 switch(clock){
1141 case CK_SYS:
1142 ck_freq = cksys_freq;
1143 break;
1144 case CK_AHB:
1145 ck_freq = ahb_freq;
1146 break;
1147 case CK_APB1:
1148 ck_freq = apb1_freq;
1149 break;
1150 case CK_APB2:
1151 ck_freq = apb2_freq;
1152 break;
1153 default:
1154 break;
1155 }
1156 return ck_freq;
1157 }
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f10x_rcu.h:90
RCU_FLAG_PLL1STB
Definition: gd32f10x_rcu.h:509
RCU_CKADC_CKAPB2_DIV8
#define RCU_CKADC_CKAPB2_DIV8
Definition: gd32f10x_rcu.h:635
RCU_INT
#define RCU_INT
Definition: gd32f10x_rcu.h:25
RCU_PLL_CK
Definition: gd32f10x_rcu.h:574
RCU_CKADC_CKAPB2_DIV2
#define RCU_CKADC_CKAPB2_DIV2
Definition: gd32f10x_rcu.h:632
RCU_HXTAL
Definition: gd32f10x_rcu.h:570
rcu_irc8m_adjust_value_set
void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
set the IRC8M adjust value
Definition: gd32f10x_rcu.c:1001
rcu_osci_on
void rcu_osci_on(rcu_osci_type_enum osci)
turn on the oscillator
Definition: gd32f10x_rcu.c:870
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
SEL_HXTAL
#define SEL_HXTAL
Definition: gd32f10x_rcu.c:17
rcu_pll_config
void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
configure the main PLL clock
Definition: gd32f10x_rcu.c:375
rcu_int_enum
rcu_int_enum
Definition: gd32f10x_rcu.h:554
RCU_CFG0_PREDV0
#define RCU_CFG0_PREDV0
Definition: gd32f10x_rcu.h:89
RCU_FLAG_HXTALSTB
Definition: gd32f10x_rcu.h:506
SEL_IRC8M
#define SEL_IRC8M
Definition: gd32f10x_rcu.c:16
rcu_i2s2_clock_config
void rcu_i2s2_clock_config(uint32_t i2s_clock_source)
configure the I2S2 clock source selection
Definition: gd32f10x_rcu.c:600
RCU_CFG0_SCSS
#define RCU_CFG0_SCSS
Definition: gd32f10x_rcu.h:83
RCU_CTL_PLLEN
#define RCU_CTL_PLLEN
Definition: gd32f10x_rcu.h:61
RCU_CTL
#define RCU_CTL
Definition: gd32f10x_rcu.h:23
rcu_flag_enum
rcu_flag_enum
Definition: gd32f10x_rcu.h:502
RCU_CFG0_CKOUT0SEL
#define RCU_CFG0_CKOUT0SEL
Definition: gd32f10x_rcu.h:92
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f10x_rcu.h:86
RCU_BDCTL_RTCSRC
#define RCU_BDCTL_RTCSRC
Definition: gd32f10x_rcu.h:288
RCU_CFG0_ADCPSC_2
#define RCU_CFG0_ADCPSC_2
Definition: gd32f10x_rcu.h:94
rcu_rtc_clock_config
void rcu_rtc_clock_config(uint32_t rtc_clock_source)
configure the RTC clock source selection
Definition: gd32f10x_rcu.c:561
rcu_osci_bypass_mode_enable
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
Definition: gd32f10x_rcu.c:903
rcu_interrupt_enable
void rcu_interrupt_enable(rcu_int_enum stab_int)
enable the stabilization interrupt
Definition: gd32f10x_rcu.c:711
rcu_ckout0_config
void rcu_ckout0_config(uint32_t ckout0_src)
configure the CK_OUT0 clock source
Definition: gd32f10x_rcu.c:354
rcu_bkp_reset_disable
void rcu_bkp_reset_disable(void)
disable the BKP domain reset
Definition: gd32f10x_rcu.c:234
rcu_all_reset_flag_clear
void rcu_all_reset_flag_clear(void)
clear all the reset flag
Definition: gd32f10x_rcu.c:647
RCU_CFG1_I2S1SEL
#define RCU_CFG1_I2S1SEL
Definition: gd32f10x_rcu.h:316
RCU_RSTSCK_RSTFC
#define RCU_RSTSCK_RSTFC
Definition: gd32f10x_rcu.h:295
RCU_CKADC_CKAPB2_DIV4
#define RCU_CKADC_CKAPB2_DIV4
Definition: gd32f10x_rcu.h:633
RCU_IRC8M
Definition: gd32f10x_rcu.h:572
rcu_osci_off
void rcu_osci_off(rcu_osci_type_enum osci)
turn off the oscillator
Definition: gd32f10x_rcu.c:889
rcu_interrupt_disable
void rcu_interrupt_disable(rcu_int_enum stab_int)
disable the stabilization interrupt
Definition: gd32f10x_rcu.c:730
RCU_CFG1_PLL2MF
#define RCU_CFG1_PLL2MF
Definition: gd32f10x_rcu.h:314
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f10x_rcu.h:290
RCU_FLAG_PLL2STB
Definition: gd32f10x_rcu.h:510
rcu_periph_sleep_enum
rcu_periph_sleep_enum
Definition: gd32f10x_rcu.h:428
OSC_STARTUP_TIMEOUT
#define OSC_STARTUP_TIMEOUT
Definition: gd32f10x_rcu.c:21
rcu_int_flag_enum
rcu_int_flag_enum
Definition: gd32f10x_rcu.h:524
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f10x_rcu.h:84
RCU_DSV
#define RCU_DSV
Definition: gd32f10x_rcu.h:33
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f10x_rcu.h:87
rcu_osci_type_enum
rcu_osci_type_enum
Definition: gd32f10x_rcu.h:568
rcu_osci_stab_wait
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
wait for oscillator stabilization flags is SET or oscillator startup is timeout
Definition: gd32f10x_rcu.c:749
RCU_PREDV0_DIV2
#define RCU_PREDV0_DIV2
Definition: gd32f10x_rcu.h:714
rcu_interrupt_flag_get
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
get the clock stabilization interrupt and ckm flags
Definition: gd32f10x_rcu.c:667
rcu_ahb_clock_config
void rcu_ahb_clock_config(uint32_t ck_ahb)
configure the AHB clock prescaler selection
Definition: gd32f10x_rcu.c:281
LXTAL_STARTUP_TIMEOUT
#define LXTAL_STARTUP_TIMEOUT
Definition: gd32f10x_rcu.c:22
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f10x_rcu.h:85
RCU_FLAG_LXTALSTB
Definition: gd32f10x_rcu.h:512
RCU_PLLSRC_HXTAL
#define RCU_PLLSRC_HXTAL
Definition: gd32f10x_rcu.h:641
RCU_FLAG_PLLSTB
Definition: gd32f10x_rcu.h:507
CK_SYS
Definition: gd32f10x_rcu.h:584
RCU_CTL_CKMEN
#define RCU_CTL_CKMEN
Definition: gd32f10x_rcu.h:60
RCU_CFG1_I2S2SEL
#define RCU_CFG1_I2S2SEL
Definition: gd32f10x_rcu.h:317
rcu_apb1_clock_config
void rcu_apb1_clock_config(uint32_t ck_apb1)
configure the APB1 clock prescaler selection
Definition: gd32f10x_rcu.c:304
RCU_PREDV0SRC_CKPLL1
#define RCU_PREDV0SRC_CKPLL1
Definition: gd32f10x_rcu.h:778
RCU_CFG1_PREDV0
#define RCU_CFG1_PREDV0
Definition: gd32f10x_rcu.h:311
RCU_CTL_IRC8MADJ
#define RCU_CTL_IRC8MADJ
Definition: gd32f10x_rcu.h:55
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f10x_rcu.h:326
RCU_PLL1_CK
Definition: gd32f10x_rcu.h:576
RCU_CFG1_PREDV1
#define RCU_CFG1_PREDV1
Definition: gd32f10x_rcu.h:312
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f10x_rcu.h:82
RCU_CFG0_USBDPSC
#define RCU_CFG0_USBDPSC
Definition: gd32f10x_rcu.h:91
RCU_CKADC_CKAPB2_DIV16
#define RCU_CKADC_CKAPB2_DIV16
Definition: gd32f10x_rcu.h:637
rcu_clock_freq_enum
rcu_clock_freq_enum
Definition: gd32f10x_rcu.h:582
rcu_osci_bypass_mode_disable
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
Definition: gd32f10x_rcu.c:942
RCU_DSV_DSLPVS
#define RCU_DSV_DSLPVS
Definition: gd32f10x_rcu.h:321
RCU_IRC40K
Definition: gd32f10x_rcu.h:573
rcu_bkp_reset_enable
void rcu_bkp_reset_enable(void)
reset the BKP domain
Definition: gd32f10x_rcu.c:223
rcu_hxtal_clock_monitor_disable
void rcu_hxtal_clock_monitor_disable(void)
disable the HXTAL clock monitor
Definition: gd32f10x_rcu.c:990
RCU_CFG1_PLL1MF
#define RCU_CFG1_PLL1MF
Definition: gd32f10x_rcu.h:313
rcu_hxtal_clock_monitor_enable
void rcu_hxtal_clock_monitor_enable(void)
enable the HXTAL clock monitor
Definition: gd32f10x_rcu.c:979
rcu_periph_clock_disable
void rcu_periph_clock_disable(rcu_periph_enum periph)
disable the peripherals clock
Definition: gd32f10x_rcu.c:128
gd32f10x_rcu.h
definitions for the RCU
CK_APB2
Definition: gd32f10x_rcu.h:587
rcu_i2s1_clock_config
void rcu_i2s1_clock_config(uint32_t i2s_clock_source)
configure the I2S1 clock source selection
Definition: gd32f10x_rcu.c:581
RCU_CKADC_CKAPB2_DIV12
#define RCU_CKADC_CKAPB2_DIV12
Definition: gd32f10x_rcu.h:636
rcu_flag_get
FlagStatus rcu_flag_get(rcu_flag_enum flag)
get the clock stabilization and periphral reset flags
Definition: gd32f10x_rcu.c:631
CK_AHB
Definition: gd32f10x_rcu.h:585
rcu_system_clock_source_get
uint32_t rcu_system_clock_source_get(void)
get the system clock source
Definition: gd32f10x_rcu.c:268
RCU_CTL_HXTALBPS
#define RCU_CTL_HXTALBPS
Definition: gd32f10x_rcu.h:59
RCU_FLAG_IRC8MSTB
Definition: gd32f10x_rcu.h:505
RCU_FLAG_IRC40KSTB
Definition: gd32f10x_rcu.h:513
RCU_CKADC_CKAPB2_DIV6
#define RCU_CKADC_CKAPB2_DIV6
Definition: gd32f10x_rcu.h:634
RCU_CFG0
#define RCU_CFG0
Definition: gd32f10x_rcu.h:24
rcu_periph_clock_sleep_disable
void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
disable the peripherals clock when sleep mode
Definition: gd32f10x_rcu.c:156
rcu_periph_clock_enable
void rcu_periph_clock_enable(rcu_periph_enum periph)
enable the peripherals clock
Definition: gd32f10x_rcu.c:93
rcu_deepsleep_voltage_set
void rcu_deepsleep_voltage_set(uint32_t dsvol)
deep-sleep mode voltage select
Definition: gd32f10x_rcu.c:1022
RCU_CTL_IRC8MEN
#define RCU_CTL_IRC8MEN
Definition: gd32f10x_rcu.h:53
rcu_int_flag_clear_enum
rcu_int_flag_clear_enum
Definition: gd32f10x_rcu.h:539
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f10x_rcu.h:88
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f10x_rcu.h:327
RCU_PLL2_CK
Definition: gd32f10x_rcu.h:577
SEL_PLL
#define SEL_PLL
Definition: gd32f10x_rcu.c:18
RCU_CFG0_PLLMF_4
#define RCU_CFG0_PLLMF_4
Definition: gd32f10x_rcu.h:93
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f10x_rcu.h:285
rcu_deinit
void rcu_deinit(void)
deinitialize the RCU
Definition: gd32f10x_rcu.c:30
CK_APB1
Definition: gd32f10x_rcu.h:586
rcu_system_clock_source_config
void rcu_system_clock_source_config(uint32_t ck_sys)
configure the system clock source
Definition: gd32f10x_rcu.c:249
RCU_CFG1_PREDV0SEL
#define RCU_CFG1_PREDV0SEL
Definition: gd32f10x_rcu.h:315
rcu_periph_clock_sleep_enable
void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
enable the peripherals clock when sleep mode
Definition: gd32f10x_rcu.c:142
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f10x_rcu.h:287
RCU_RSTSCK
#define RCU_RSTSCK
Definition: gd32f10x_rcu.h:32
rcu_adc_clock_config
void rcu_adc_clock_config(uint32_t adc_psc)
configure the ADC prescaler factor
Definition: gd32f10x_rcu.c:493
RCU_LXTAL
Definition: gd32f10x_rcu.h:571
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
rcu_usb_clock_config
void rcu_usb_clock_config(uint32_t usb_psc)
configure the USBD/USBFS prescaler factor
Definition: gd32f10x_rcu.c:534
rcu_periph_enum
rcu_periph_enum
Definition: gd32f10x_rcu.h:353
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f10x_rcu.h:31
rcu_predv0_config
void rcu_predv0_config(uint32_t predv0_div)
configure the PREDV0 division factor
Definition: gd32f10x_rcu.c:396
RCU_CTL_HXTALEN
#define RCU_CTL_HXTALEN
Definition: gd32f10x_rcu.h:57
rcu_interrupt_flag_clear
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
clear the interrupt flags
Definition: gd32f10x_rcu.c:692
rcu_periph_reset_enum
rcu_periph_reset_enum
Definition: gd32f10x_rcu.h:436
rcu_apb2_clock_config
void rcu_apb2_clock_config(uint32_t ck_apb2)
configure the APB2 clock prescaler selection
Definition: gd32f10x_rcu.c:327
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_fwdgt.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_fwdgt.h"
14
15 /* write value to FWDGT_CTL_CMD bit field */
16 #define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
17 /* write value to FWDGT_RLD_RLD bit field */
18 #define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
19
26 void fwdgt_write_disable(void)
27 {
28 FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
29 }
30
37 void fwdgt_counter_reload(void)
38 {
39 FWDGT_CTL = FWDGT_KEY_RELOAD;
40 }
41
48 void fwdgt_enable(void)
49 {
50 FWDGT_CTL = FWDGT_KEY_ENABLE;
51 }
52
53
68 ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
69 {
70 uint32_t timeout = FWDGT_PSC_TIMEOUT;
71 uint32_t flag_status = RESET;
72
73 /* enable write access to FWDGT_PSC,and FWDGT_RLD */
74 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
75 /* wait until the PUD flag to be reset */
76 do{
77 flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
78 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
79
80 if((uint32_t)RESET != flag_status){
81 return ERROR;
82 }
83 /* configure FWDGT */
84 FWDGT_PSC = (uint32_t)prescaler_div;
85
86 timeout = FWDGT_RLD_TIMEOUT;
87 /* wait until the RUD flag to be reset */
88 do{
89 flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
90 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
91
92 if((uint32_t)RESET != flag_status){
93 return ERROR;
94 }
95 FWDGT_RLD = RLD_RLD(reload_value);
96 /* reload the counter */
97 FWDGT_CTL = FWDGT_KEY_RELOAD;
98
99 return SUCCESS;
100 }
101
110 FlagStatus fwdgt_flag_get(uint16_t flag)
111 {
112 if(FWDGT_STAT & flag){
113 return SET;
114 }
115 return RESET;
116 }
FWDGT_STAT_PUD
#define FWDGT_STAT_PUD
Definition: gd32f10x_fwdgt.h:38
FWDGT_KEY_ENABLE
#define FWDGT_KEY_ENABLE
Definition: gd32f10x_fwdgt.h:56
fwdgt_enable
void fwdgt_enable(void)
start the free watchdog timer counter
Definition: gd32f10x_fwdgt.c:48
FWDGT_RLD_TIMEOUT
#define FWDGT_RLD_TIMEOUT
Definition: gd32f10x_fwdgt.h:60
RLD_RLD
#define RLD_RLD(regval)
Definition: gd32f10x_fwdgt.c:18
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f10x_fwdgt.h:25
fwdgt_counter_reload
void fwdgt_counter_reload(void)
reload the counter of FWDGT
Definition: gd32f10x_fwdgt.c:37
FWDGT_WRITEACCESS_ENABLE
#define FWDGT_WRITEACCESS_ENABLE
Definition: gd32f10x_fwdgt.h:53
FWDGT_RLD
#define FWDGT_RLD
Definition: gd32f10x_fwdgt.h:24
FWDGT_PSC_TIMEOUT
#define FWDGT_PSC_TIMEOUT
Definition: gd32f10x_fwdgt.h:59
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f10x_fwdgt.h:55
fwdgt_write_disable
void fwdgt_write_disable(void)
disable write access to FWDGT_PSC and FWDGT_RLD
Definition: gd32f10x_fwdgt.c:26
gd32f10x_fwdgt.h
definitions for the FWDGT
FWDGT_WRITEACCESS_DISABLE
#define FWDGT_WRITEACCESS_DISABLE
Definition: gd32f10x_fwdgt.h:54
fwdgt_config
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
configure counter reload value, and prescaler divider value
Definition: gd32f10x_fwdgt.c:68
FWDGT_STAT_RUD
#define FWDGT_STAT_RUD
Definition: gd32f10x_fwdgt.h:39
FWDGT_PSC
#define FWDGT_PSC
Definition: gd32f10x_fwdgt.h:23
fwdgt_flag_get
FlagStatus fwdgt_flag_get(uint16_t flag)
get flag state of FWDGT
Definition: gd32f10x_fwdgt.c:110
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f10x_fwdgt.h:22
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_ctrl.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usbh_ctrl.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBH_CTRL_H
14 #define USBH_CTRL_H
15
16 #include "usbh_core.h"
17 #include "usbh_usr.h"
18
19 #define CTRL_HANDLE_TABLE_SIZE 13U
21 extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE];
22 extern uint8_t ctrl_polling_handle_flag;
23
24 /* the enum of CTRL event */
25 typedef enum
26 {
27 CTRL_EVENT_IDLE = 0, /* the ctrl idle event */
28 CTRL_EVENT_SETUP, /* the ctrl setup event */
29 CTRL_EVENT_DATA, /* the ctrl data event */
30 CTRL_EVENT_STATUS, /* the ctrl status event */
31 CTRL_EVENT_COMPLETE, /* the ctrl complete event */
32 CTRL_EVENT_ERROR, /* the ctrl error event */
33 CTRL_EVENT_STALLED, /* the ctrl stalled event */
34 }ctrl_event_enum;
35
36 /* function declarations */
37 /* the polling function of control transfer state handle */
38 usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
39 /* send datas from the host channel */
40 usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len);
41 /* send the setup packet to the device */
42 usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num);
43 /* this function prepare a hc and start a transfer */
44 uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num);
45
46 #endif /* USBH_CTRL_H */
usbh_core.h
header file for usbh_core.c
ctrl_state_polling_fun
usbh_status_enum ctrl_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state
Definition: usbh_ctrl.c:73
CTRL_EVENT_ERROR
Definition: usbh_ctrl.h:32
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
usbh_host_struct
Definition: usbh_core.h:189
CTRL_EVENT_SETUP
Definition: usbh_ctrl.h:28
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:605
CTRL_EVENT_DATA
Definition: usbh_ctrl.h:29
usbh_ctltx_setup
usbh_status_enum usbh_ctltx_setup(usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
send the setup packet to the device
Definition: usbh_ctrl.c:587
usbh_xfer
usbh_status_enum usbh_xfer(usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len)
send datas from the host channel
Definition: usbh_ctrl.c:494
ctrl_event_enum
ctrl_event_enum
Definition: usbh_ctrl.h:25
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:17
usb_core_handle_struct
Definition: usb_core.h:201
CTRL_EVENT_STALLED
Definition: usbh_ctrl.h:33
CTRL_EVENT_COMPLETE
Definition: usbh_ctrl.h:31
CTRL_EVENT_IDLE
Definition: usbh_ctrl.h:27
CTRL_EVENT_STATUS
Definition: usbh_ctrl.h:30
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_pwr.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
usbd_pwr.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBD_PWR_H
14 #define USBD_PWR_H
15
16 #include "usbd_core.h"
17
18 /* function declarations */
19 /* USB wakeup first operation is to wakeup mcu */
20 void resume_mcu (void);
21 /* set USB device to suspend mode */
22 void usbd_suspend (void);
23 /* start to remote wakeup */
24 void usbd_remote_wakeup_active (void);
25
26 #endif /* USBD_PWR_H */
resume_mcu
void resume_mcu(void)
USB wakeup first operation is to wakeup mcu.
Definition: usbd_pwr.c:33
usbd_core.h
usbd_suspend
void usbd_suspend(void)
set USB device to suspend mode
Definition: usbd_pwr.c:91
usbd_remote_wakeup_active
void usbd_remote_wakeup_active(void)
start to remote wakeup
Definition: usbd_pwr.c:119
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbd_core.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usbd_core.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBD_CORE_H
14 #define USBD_CORE_H
15
16 #include "usbd_conf.h"
17 #include "usb_core.h"
18 #include "usbd_std.h"
19
20 /* device status */
21 #define USB_STATUS_DEFAULT 1U /* default status */
22 #define USB_STATUS_ADDRESSED 2U /* addressed status */
23 #define USB_STATUS_CONFIGURED 3U /* configured status */
24 #define USB_STATUS_SUSPENDED 4U /* suspended status */
25
26 /* function declarations */
27 /* initailizes the USB device-mode handler stack */
28 void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id);
29 /* endpoint initialization */
30 void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc);
31 /* endpoint deinitialize */
32 void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr);
33 /* endpoint prepare to receive data */
34 void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
35 /* endpoint prepare to transmit data */
36 void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len);
37 /* transmit data on the control channel */
38 usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
39 /* receive data on the control channel */
40 usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
41 /* transmit status on the control channel */
42 usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev);
43 /* receive status on the control channel */
44 usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev);
45 /* set an endpoint to STALL status */
46 void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
47 /* clear endpoint stalled status */
48 void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
49 /* flushes the FIFOs */
50 void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr);
51 /* get the received data length */
52 uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num);
53
54 #endif /* USBD_CORE_H */
usbd_ep_deinit
void usbd_ep_deinit(usbd_core_handle_struct *pudev, uint8_t ep_addr)
configure the endpoint when it is disabled
Definition: usbd_core.c:173
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
usbd_ep_clear_stall
void usbd_ep_clear_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status
Definition: usbd_core.c:297
usbd_std.h
usbd_init
void usbd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initailizes the USB device-mode handler stack
Definition: usbd_core.c:23
usbd_ep_init
void usbd_ep_init(usbd_core_handle_struct *pudev, void *pep_desc)
endpoint initialization
Definition: usbd_core.c:100
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:368
usbd_rxcount_get
uint16_t usbd_rxcount_get(usb_core_handle_struct *pudev, uint8_t ep_num)
get the received data length
Definition: usbd_core.c:474
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:351
usbd_ctlrx
usbd_status_enum usbd_ctlrx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
receive data on the control channel
Definition: usbd_core.c:334
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
usb_core.h
USB core driver header file.
usb_core_handle_struct
Definition: usb_core.h:201
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
usbd_ctltx
usbd_status_enum usbd_ctltx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel
Definition: usbd_core.c:313
usbd_ep_fifo_flush
void usbd_ep_fifo_flush(usb_core_handle_struct *pudev, uint8_t ep_addr)
flushes the FIFOs
Definition: usbd_core.c:458
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:87
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_hcs.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
usbh_hcs.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbh_hcs.h"
14
15 static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev);
16
28 uint8_t usbh_channel_open (usb_core_handle_struct *pudev,
29 uint8_t channel_num,
30 uint8_t dev_addr,
31 uint8_t dev_speed,
32 uint8_t ep_type,
33 uint16_t ep_mps)
34 {
35 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
36 uint16_t channel_info = puhc->info;
37
38 puhc->endp_id = (uint8_t)channel_info & 0x7FU;
39 puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7;
40 puhc->endp_type = ep_type;
41 puhc->endp_mps = ep_mps;
42 puhc->dev_addr = dev_addr;
43 puhc->dev_speed = dev_speed;
44
45 puhc->data_tg_in = 0U;
46 puhc->data_tg_out = 0U;
47
48 usb_hostchannel_init(pudev, channel_num);
49
50 return (uint8_t)HC_OK;
51 }
52
64 uint8_t usbh_channel_modify (usb_core_handle_struct *pudev,
65 uint8_t channel_num,
66 uint8_t dev_addr,
67 uint8_t dev_speed,
68 uint8_t ep_type,
69 uint16_t ep_mps)
70 {
71 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
72
73 if (0U != dev_addr) {
74 puhc->dev_addr = dev_addr;
75 }
76
77 if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) {
78 puhc->endp_mps = ep_mps;
79 }
80
81 if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) {
82 puhc->dev_speed = dev_speed;
83 }
84
85 usb_hostchannel_init(pudev, channel_num);
86
87 return (uint8_t)HC_OK;
88 }
89
97 uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr)
98 {
99 uint16_t hc_num = usbh_freechannel_get(pudev);
100
101 if ((uint16_t)HC_ERROR != hc_num) {
102 pudev->host.host_channel[hc_num].info = HC_USED | ep_addr;
103 }
104
105 return (uint8_t)hc_num;
106 }
107
115 uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index)
116 {
117 if (index < HC_MAX) {
118 pudev->host.host_channel[index].info &= HC_USED_MASK;
119 }
120
121 return USBH_OK;
122 }
123
130 uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev)
131 {
132 uint8_t index;
133
134 for (index = 2U; index < HC_MAX; index ++) {
135 pudev->host.host_channel[index].info = 0U;
136 }
137
138 return USBH_OK;
139 }
140
147 static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev)
148 {
149 uint8_t index = 0U;
150
151 for (index = 0U; index < HC_MAX; index++) {
152 if (0U == (pudev->host.host_channel[index].info & HC_USED)) {
153 return (uint16_t)index;
154 }
155 }
156
157 return HC_ERROR;
158 }
159
HC_USED
#define HC_USED
Definition: usbh_hcs.h:21
usb_hostchannel_struct::info
uint16_t info
Definition: usb_core.h:164
usbh_channel_modify
uint8_t usbh_channel_modify(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel
Definition: usbh_hcs.c:64
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:176
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:161
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:18
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:115
usb_hostchannel_struct
Definition: usb_core.h:155
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:175
usbh_channel_open
uint8_t usbh_channel_open(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel
Definition: usbh_hcs.c:28
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:163
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:157
usbh_hcs.h
header file for usbh_hcs.c
usb_core_handle_struct
Definition: usb_core.h:201
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:158
HC_ERROR
#define HC_ERROR
Definition: usbh_hcs.h:22
usbh_channel_alloc
uint8_t usbh_channel_alloc(usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe
Definition: usbh_hcs.c:97
HC_USED_MASK
#define HC_USED_MASK
Definition: usbh_hcs.h:23
USBH_OK
Definition: usbh_core.h:109
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:162
HC_OK
#define HC_OK
Definition: usbh_hcs.h:20
usbh_allchannel_dealloc
uint8_t usbh_allchannel_dealloc(usb_core_handle_struct *pudev)
free all usb host channel
Definition: usbh_hcs.c:130
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:160
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbd_core.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
usbd_core.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbd_core.h"
14 #include "usbd_std.h"
15
23 void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
24 {
25 /* select USB core */
26 usb_core_select (pudev, core_id);
27
28 pudev->dev.status = USB_STATUS_DEFAULT;
29
30 /* disable USB global interrupt */
31 USB_GLOBAL_INT_DISABLE();
32
33 /* init the core (common init.) */
34 usb_core_init(pudev);
35
36 /* force device mode*/
37 usb_mode_set(pudev, DEVICE_MODE);
38
39 /* set device disconnect */
40 USB_SOFT_DISCONNECT_ENABLE();
41
42 if ((void *)0 != pudev->mdelay) {
43 pudev->mdelay(3U);
44 }
45
46 /* init device */
47 usb_devcore_init(pudev);
48
49 /* set device Connect */
50 USB_SOFT_DISCONNECT_DISABLE();
51
52 if ((void *)0 != pudev->mdelay) {
53 pudev->mdelay(3U);
54 }
55
56 /* enable USB global interrupt */
57 USB_GLOBAL_INT_ENABLE();
58 }
59
67 void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc)
68 {
69 usb_ep_struct *ep;
70 usb_dir_enum ep_dir;
71
72 uint32_t devepinten = 0U;
73 uint32_t devepctl = 0U;
74
75 uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU;
76 uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK;
77 uint16_t ep_mps = ep_desc->wMaxPacketSize;
78
79 if (ep_desc->bEndpointAddress >> 7) {
80 ep = &pudev->dev.in_ep[ep_num];
81
82 devepinten |= 1U << ep_num;
83 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
84
85 ep_dir = USB_TX;
86 } else {
87 ep = &pudev->dev.out_ep[ep_num];
88
89 devepinten |= (1U << ep_num) << 16;
90 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
91
92 ep_dir = USB_RX;
93 }
94
95 /* if the endpoint is not active, need change the endpoint control register */
96 if (!(devepctl & DEPCTL_EPACT)) {
97 devepctl &= ~DEPCTL_MPL;
98 devepctl |= ep_mps;
99
100 devepctl &= ~DEPCTL_EPTYPE;
101 devepctl |= (uint32_t)ep_type << 18;
102
103 if (USB_TX == ep_dir) {
104 devepctl &= ~DIEPCTL_TXFNUM;
105 devepctl |= (uint32_t)ep_num << 22;
106 }
107
108 devepctl |= DEPCTL_SD0PID;
109 devepctl |= DEPCTL_EPACT;
110 }
111
112 if (USB_TX == ep_dir) {
113 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
114 } else if (USB_RX == ep_dir) {
115 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
116 } else {
117 /* no operation */
118 }
119
120 ep->endp_mps = ep_mps;
121 ep->endp_type = ep_type;
122
123 /* enable the interrupts for this endpoint */
124 USB_DAEPINTEN |= devepinten;
125 }
126
134 void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr)
135 {
136 uint32_t devepinten = 0U;
137 uint8_t ep_num = ep_addr & 0x7FU;
138
139 if (ep_addr >> 7) {
140 devepinten |= 1U << ep_num;
141
142 USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
143 } else {
144 devepinten |= (1U << ep_num) << 16U;
145
146 USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
147 }
148
149 /* disable the interrupts for this endpoint */
150 USB_DAEPINTEN &= ~devepinten;
151 }
152
162 void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
163 {
164 usb_ep_struct *ep;
165 uint8_t ep_num = ep_addr & 0x7FU;
166 uint32_t devepctl = 0U, devepxlen = 0U;
167
168 ep = &pudev->dev.out_ep[ep_num];
169
170 /* setup and start the Xfer */
171 ep->xfer_buff = pbuf;
172 ep->xfer_len = buf_len;
173 ep->xfer_count = 0U;
174
175 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
176 devepxlen = USB_DOEPxLEN((uint16_t)ep_num);
177
178 devepxlen &= ~DEPLEN_TLEN;
179 devepxlen &= ~DEPLEN_PCNT;
180
181 /* zero length packet */
182 if (0U == ep->xfer_len) {
183 /* set the transfer length to max packet size */
184 devepxlen |= ep->endp_mps;
185
186 /* set the transfer packet count to 1 */
187 devepxlen |= 1U << 19U;
188 } else {
189
190 if (0U == ep_num) {
191 /* set the transfer length to max packet size */
192 devepxlen |= ep->endp_mps;
193
194 /* set the transfer packet count to 1 */
195 devepxlen |= 1U << 19U;
196 } else {
197 /* configure the transfer size and packet count as follows:
198 * pktcnt = N
199 * xfersize = N * maxpacket
200 */
201 devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U;
202 devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps;
203 }
204 }
205
206 USB_DOEPxLEN((uint16_t)ep_num) = devepxlen;
207
208 if (USB_EPTYPE_ISOC == ep->endp_type) {
209 if (ep->endp_frame) {
210 devepctl |= DEPCTL_SODDFRM;
211 } else {
212 devepctl |= DEPCTL_SEVNFRM;
213 }
214 }
215
216 /* enable the endpoint and clear the NAK */
217 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
218
219 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
220 }
221
231 void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
232 {
233 usb_ep_struct *ep;
234 uint8_t ep_num = ep_addr & 0x7FU;
235 __IO uint32_t devepctl = 0U;
236 __IO uint32_t deveplen = 0U;
237
238 ep = &pudev->dev.in_ep[ep_num];
239
240 /* setup and start the transfer */
241 ep->xfer_buff = pbuf;
242 ep->xfer_len = buf_len;
243 ep->xfer_count = 0U;
244
245 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
246 deveplen = USB_DIEPxLEN((uint16_t)ep_num);
247
248 /* clear transfer length to 0 */
249 deveplen &= ~DEPLEN_TLEN;
250
251 /* clear transfer packet to 0 */
252 deveplen &= ~DEPLEN_PCNT;
253
254 /* zero length packet */
255 if (0U == ep->xfer_len) {
256 /* set transfer packet count to 1 */
257 deveplen |= 1U << 19U;
258 } else {
259 if (0U == ep_num) {
260 if (ep->xfer_len > ep->endp_mps) {
261 ep->xfer_len = ep->endp_mps;
262 }
263
264 deveplen |= 1U << 19U;
265 } else {
266 deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U;
267 }
268
269 /* configure the transfer size and packet count as follows:
270 * xfersize = N * maxpacket + short_packet
271 * pktcnt = N + (short_packet exist ? 1 : 0)
272 */
273 deveplen |= ep->xfer_len;
274
275 if (USB_EPTYPE_ISOC == ep->endp_type) {
276 deveplen |= DIEPLEN_MCNT & (1U << 29U);
277 }
278 }
279
280 USB_DIEPxLEN((uint16_t)ep_num) = deveplen;
281
282 if (USB_EPTYPE_ISOC == ep->endp_type) {
283 if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) {
284 devepctl |= DEPCTL_SODDFRM;
285 } else {
286 devepctl |= DEPCTL_SEVNFRM;
287 }
288 }
289
290 /* enable the endpoint and clear the NAK */
291 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
292
293 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
294
295 if (USB_EPTYPE_ISOC != ep->endp_type) {
296 /* enable the Tx FIFO empty interrupt for this endpoint */
297 if (ep->xfer_len > 0U) {
298 USB_DIEPFEINTEN |= 1U << ep_num;
299 }
300 } else {
301 usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len);
302 }
303 }
304
313 usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
314 {
315 usbd_status_enum ret = USBD_OK;
316
317 pudev->dev.sum_len = len;
318 pudev->dev.remain_len = len;
319 pudev->dev.ctl_status = USB_CTRL_DATA_IN;
320
321 usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len);
322
323 return ret;
324 }
325
334 usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
335 {
336 pudev->dev.sum_len = len;
337 pudev->dev.remain_len = len;
338 pudev->dev.ctl_status = USB_CTRL_DATA_OUT;
339
340 usbd_ep_rx (pudev, 0U, pbuf, len);
341
342 return USBD_OK;
343 }
344
351 usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev)
352 {
353 pudev->dev.ctl_status = USB_CTRL_STATUS_IN;
354
355 usbd_ep_tx (pudev, 0U, NULL, 0U);
356
357 usb_ep0_startout(pudev);
358
359 return USBD_OK;
360 }
361
368 usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev)
369 {
370 pudev->dev.ctl_status = USB_CTRL_STATUS_OUT;
371
372 usbd_ep_rx (pudev, 0U, NULL, 0U);
373
374 usb_ep0_startout(pudev);
375
376 return USBD_OK;
377 }
378
386 void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
387 {
388 uint8_t ep_num = ep_addr & 0x7FU;
389 __IO uint32_t devepctl = 0U;
390
391 if (ep_addr >> 7U) {
392 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
393
394 /* set the endpoint disable bit */
395 if (devepctl & DEPCTL_EPEN) {
396 devepctl |= DEPCTL_EPD;
397 }
398
399 /* set the endpoint stall bit */
400 devepctl |= DEPCTL_STALL;
401
402 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
403 } else {
404 /* set the endpoint stall bit */
405 USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL;
406 }
407 }
408
416 void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
417 {
418 usb_ep_struct *ep;
419 uint8_t ep_num = ep_addr & 0x7FU;
420 __IO uint32_t devepctl = 0U;
421
422 if(ep_addr >> 7){
423 ep = &pudev->dev.in_ep[ep_num];
424
425 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
426
427 /* clear the IN endpoint stall bits */
428 devepctl &= ~DEPCTL_STALL;
429
430 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
431 devepctl |= DEPCTL_SEVNFRM;
432 }
433
434 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
435 } else {
436 ep = &pudev->dev.out_ep[ep_num];
437
438 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
439
440 /* clear the OUT endpoint stall bits */
441 devepctl &= ~DEPCTL_STALL;
442
443 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
444 devepctl |= DEPCTL_SEVNFRM;
445 }
446
447 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
448 }
449 }
450
458 void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr)
459 {
460 if (ep_addr >> 7) {
461 usb_txfifo_flush(pudev, ep_addr & 0x7FU);
462 } else {
463 usb_rxfifo_flush(pudev);
464 }
465 }
466
474 uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num)
475 {
476 return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count;
477 }
usbd_ep_deinit
void usbd_ep_deinit(usbd_core_handle_struct *pudev, uint8_t ep_addr)
configure the endpoint when it is disabled
Definition: usbd_core.c:173
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:211
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:128
USB_CTRL_STATUS_OUT
Definition: usb_core.h:88
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usbd_std.h:162
USB_TX
Definition: usb_core.h:96
USB_CTRL_STATUS_IN
Definition: usb_core.h:87
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:268
DEPCTL_EPTYPE
#define DEPCTL_EPTYPE
Definition: usb_regs.h:398
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:53
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:238
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:109
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:72
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:387
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:55
USB_CTRL_DATA_IN
Definition: usb_core.h:85
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:82
usbd_ep_clear_stall
void usbd_ep_clear_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status
Definition: usbd_core.c:297
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usbd_std.h:161
USB_CTRL_DATA_OUT
Definition: usb_core.h:86
DIEPLEN_MCNT
#define DIEPLEN_MCNT
Definition: usb_regs.h:432
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:388
USB_DIEPxLEN
#define USB_DIEPxLEN(x)
Definition: usb_regs.h:88
usbd_ep_fifo_flush
void usbd_ep_fifo_flush(usb_core_handle_struct *pudev, uint8_t ep_addr)
flushes the FIFOs
Definition: usbd_core.c:458
usbd_ctltx
usbd_status_enum usbd_ctltx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel
Definition: usbd_core.c:313
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:102
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:108
usb_ep_struct::endp_frame
uint8_t endp_frame
Definition: usb_core.h:103
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:434
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:402
USB_RX
Definition: usb_core.h:95
usbd_init
void usbd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initailizes the USB device-mode handler stack
Definition: usbd_core.c:23
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:433
usb_ep_struct
Definition: usbd_core.h:102
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:68
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:21
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
usbd_rxcount_get
uint16_t usbd_rxcount_get(usb_core_handle_struct *pudev, uint8_t ep_num)
get the received data length
Definition: usbd_core.c:474
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:93
DSTAT_FNRSOF
#define DSTAT_FNRSOF
Definition: usb_regs.h:338
USB_SOFT_DISCONNECT_DISABLE
#define USB_SOFT_DISCONNECT_DISABLE()
Definition: usb_regs.h:550
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:351
USBD_OK
Definition: usbd_core.h:84
DEPCTL_MPL
#define DEPCTL_MPL
Definition: usb_regs.h:403
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:75
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:493
usb_core_handle_struct
Definition: usb_core.h:201
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usbd_std.h:163
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:396
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:89
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:490
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:368
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:394
NULL
#define NULL
Definition: usbd_std.h:20
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:170
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:391
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
DIEPCTL_TXFNUM
#define DIEPCTL_TXFNUM
Definition: usb_regs.h:395
USB_SOFT_DISCONNECT_ENABLE
#define USB_SOFT_DISCONNECT_ENABLE()
Definition: usb_regs.h:547
usbd_ep_init
void usbd_ep_init(usbd_core_handle_struct *pudev, void *ep_desc)
endpoint initialization
Definition: usbd_core.c:100
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:48
USB_EPTYPE_MASK
#define USB_EPTYPE_MASK
Definition: usbd_std.h:73
DEPCTL_SD0PID
#define DEPCTL_SD0PID
Definition: usb_regs.h:392
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:389
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:87
usbd_ctlrx
usbd_status_enum usbd_ctlrx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
receive data on the control channel
Definition: usbd_core.c:334
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:54
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbd_std.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
usbd_std.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbd_std.h"
14 #include "usb_core.h"
15
16 static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req);
17 static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req);
18 static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req);
19
20 static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req);
21
22 static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req);
23 static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req);
24 static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req);
25 static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req);
26 static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req);
27 static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req);
28 static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req);
29 static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req);
30 static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req);
31 static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req);
32 static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req);
33 static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req);
34
35 static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen);
36 static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen);
37 static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen);
38
39 static void (*StandardDeviceRequest[])(usb_core_handle_struct *pudev, usb_device_req_struct *req) =
40 {
41 usbd_getstatus,
42 usbd_clrfeature,
43 usbd_reserved,
44 usbd_setfeature,
45 usbd_reserved,
46 usbd_setaddress,
47 usbd_getdescriptor,
48 usbd_setdescriptor,
49 usbd_getconfig,
50 usbd_setconfig,
51 usbd_getinterface,
52 usbd_setinterface,
53 usbd_synchframe,
54 };
55
56 /* get standard descriptor handler */
57 static uint8_t* (*standard_descriptor_get[])(usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) =
58 {
59 usbd_device_descriptor_get,
60 usbd_configuration_descriptor_get,
61 usbd_string_descriptor_get
62 };
63
70 usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev)
71 {
72 usb_device_req_struct req;
73
74 usbd_setup_request_parse(pudev, &req);
75
76 switch (req.bmRequestType & USB_REQ_MASK) {
77 /* standard device request */
78 case USB_STANDARD_REQ:
79 usbd_standard_request(pudev, &req);
80 break;
81 /* device class request */
82 case USB_CLASS_REQ:
83 usbd_device_class_request(pudev, &req);
84 break;
85 /* vendor defined request */
86 case USB_VENDOR_REQ:
87 usbd_vendor_request(pudev, &req);
88 break;
89 default:
90 usbd_ep_stall(pudev, req.bmRequestType & 0x80U);
91 break;
92 }
93
94 return USBD_OK;
95 }
96
104 usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
105 {
106 usb_ep_struct *ep;
107
108 if (0U == endp_num) {
109 ep = &pudev->dev.out_ep[0];
110
111 if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) {
112 if (pudev->dev.remain_len > ep->endp_mps) {
113 pudev->dev.remain_len -= ep->endp_mps;
114
115 usbd_ep_rx (pudev,
116 0U,
117 ep->xfer_buff,
118 (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps));
119 } else {
120 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
121 pudev->dev.class_data_handler(pudev, USB_RX, 0U);
122 }
123
124 usbd_ctlstatus_tx(pudev);
125 }
126 }
127 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
128 pudev->dev.class_data_handler(pudev, USB_RX, endp_num);
129 } else {
130 /* no operation */
131 }
132
133 return USBD_OK;
134 }
135
143 usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
144 {
145 usb_ep_struct *ep;
146
147 if (0U == endp_num) {
148 ep = &pudev->dev.in_ep[0];
149
150 if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) {
151 if (pudev->dev.remain_len > ep->endp_mps) {
152 pudev->dev.remain_len -= ep->endp_mps;
153
154 usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len);
155
156 usbd_ep_rx (pudev, 0U, NULL, 0U);
157 } else {
158 /* last packet is MPS multiple, so send ZLP packet */
159 if ((pudev->dev.sum_len % ep->endp_mps == 0U) &&
160 (pudev->dev.sum_len >= ep->endp_mps) &&
161 (pudev->dev.sum_len < pudev->dev.ctl_len)) {
162 usbd_ep_tx (pudev, 0U, NULL, 0U);
163 pudev->dev.ctl_len = 0U;
164
165 usbd_ep_rx (pudev, 0U, NULL, 0U);
166 } else {
167 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
168 pudev->dev.class_data_handler(pudev, USB_TX, 0U);
169 }
170
171 usbd_ctlstatus_rx(pudev);
172 }
173 }
174 }
175 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
176 pudev->dev.class_data_handler(pudev, USB_TX, endp_num);
177 } else {
178 /* no operation */
179 }
180
181 return USBD_OK;
182 }
183
191 static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req)
192 {
193 /* call device request handle function */
194 (*StandardDeviceRequest[req->bRequest])(pudev, req);
195
196 return USBD_OK;
197 }
198
206 static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req)
207 {
208 usbd_status_enum ret = USBD_OK;
209
210 switch (pudev->dev.status) {
211 case USB_STATUS_CONFIGURED:
212 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
213 ret = (usbd_status_enum)(pudev->dev.class_req_handler(pudev, req));
214
215 if ((0U == req->wLength) && (USBD_OK == ret)) {
216 /* no data stage */
217 usbd_ctlstatus_tx(pudev);
218 }
219 } else {
220 usbd_enum_error(pudev, req);
221 }
222 break;
223
224 default:
225 usbd_enum_error(pudev, req);
226 break;
227 }
228
229 return ret;
230 }
231
239 static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req)
240 {
241 /* added by user... */
242
243 return USBD_OK;
244 }
245
253 static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req)
254 {
255 /* no operation... */
256 }
257
265 static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen)
266 {
267 *pLen = pudev->dev.dev_desc[0];
268
269 return pudev->dev.dev_desc;
270 }
271
279 static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen)
280 {
281 *pLen = pudev->dev.config_desc[2];
282
283 return pudev->dev.config_desc;
284 }
285
293 static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen)
294 {
295 uint8_t *desc = pudev->dev.strings[index];
296
297 *pLen = desc[0];
298
299 return desc;
300 }
301
309 static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req)
310 {
311 }
312
320 static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req)
321 {
322 uint8_t ep_addr = 0U;
323
324 switch (req->bmRequestType & USB_REQTYPE_MASK) {
325 case USB_REQTYPE_DEVICE:
326 switch (pudev->dev.status) {
327 case USB_STATUS_ADDRESSED:
328 case USB_STATUS_CONFIGURED:
329 if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
330 pudev->dev.remote_wakeup = 0U;
331 pudev->dev.class_req_handler(pudev, req);
332
333 usbd_ctlstatus_tx(pudev);
334 }
335 break;
336
337 default:
338 usbd_enum_error(pudev, req);
339 break;
340 }
341 break;
342 case USB_REQTYPE_INTERFACE:
343 switch (pudev->dev.status) {
344 case USB_STATUS_ADDRESSED:
345 usbd_enum_error(pudev, req);
346 break;
347 case USB_STATUS_CONFIGURED:
348 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
349 /* no operation */
350 } else {
351 usbd_enum_error(pudev, req);
352 }
353 break;
354 default:
355 break;
356 }
357 break;
358 case USB_REQTYPE_ENDPOINT:
359 ep_addr = LOWBYTE(req->wIndex);
360
361 switch (pudev->dev.status) {
362 case USB_STATUS_ADDRESSED:
363 if (IS_NOT_EP0(ep_addr)) {
364 usbd_ep_stall(pudev, ep_addr);
365 }
366 break;
367 case USB_STATUS_CONFIGURED:
368 if (USB_FEATURE_ENDP_HALT == req->wValue) {
369 if (IS_NOT_EP0(ep_addr)) {
370 usbd_ep_clear_stall(pudev, ep_addr);
371
372 pudev->dev.class_req_handler(pudev, req);
373 }
374 }
375 usbd_ctlstatus_tx(pudev);
376 break;
377 default:
378 break;
379 }
380 break;
381 default:
382 usbd_enum_error(pudev, req);
383 break;
384 }
385 }
386
394 static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req)
395 {
396 uint8_t ep_addr = 0U;
397 __IO uint32_t DctlrStatus;
398
399 switch (req->bmRequestType & USB_REQ_MASK) {
400 case USB_REQTYPE_DEVICE:
401 switch (pudev->dev.status) {
402 case USB_STATUS_ADDRESSED:
403 case USB_STATUS_CONFIGURED:
404 if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
405 pudev->dev.remote_wakeup = 1U;
406 pudev->dev.class_req_handler(pudev, req);
407
408 usbd_ctlstatus_tx(pudev);
409 } else if ((req->wValue == USB_FEATURE_TEST_MODE) &&
410 (0U == (req->wIndex & 0xFFU))) {
411 DctlrStatus = USB_DCTL;
412
413 usbd_ctlstatus_tx(pudev);
414 } else {
415 /* no operation */
416 }
417 break;
418 default:
419 break;
420 }
421 break;
422 case USB_REQTYPE_INTERFACE:
423 switch (pudev->dev.status) {
424 case USB_STATUS_ADDRESSED:
425 usbd_enum_error(pudev, req);
426 break;
427 case USB_STATUS_CONFIGURED:
428 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
429 /* no operation */
430 } else {
431 usbd_enum_error(pudev, req);
432 }
433 break;
434 default:
435 break;
436 }
437 break;
438 case USB_REQTYPE_ENDPOINT:
439 switch (pudev->dev.status) {
440 case USB_STATUS_ADDRESSED:
441 if (IS_NOT_EP0(ep_addr)) {
442 usbd_ep_stall(pudev, ep_addr);
443 }
444 break;
445 case USB_STATUS_CONFIGURED:
446 if (USB_FEATURE_ENDP_HALT == req->wValue) {
447 if (IS_NOT_EP0(ep_addr)) {
448 usbd_ep_stall(pudev, ep_addr);
449 }
450 }
451 pudev->dev.class_req_handler(pudev, req);
452
453 usbd_ctlstatus_tx(pudev);
454 break;
455 default:
456 break;
457 }
458 break;
459 default:
460 usbd_enum_error(pudev, req);
461 break;
462 }
463 }
464
472 static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req)
473 {
474 uint8_t DevAddr;
475
476 if ((0U == req->wIndex) && (0U == req->wLength)) {
477 DevAddr = (uint8_t)(req->wValue) & 0x7FU;
478
479 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
480 usbd_enum_error(pudev, req);
481 } else {
482 USB_SET_DEVADDR((uint32_t)DevAddr);
483
484 usbd_ctlstatus_tx(pudev);
485
486 if (0U != DevAddr) {
487 pudev->dev.status = USB_STATUS_ADDRESSED;
488 } else {
489 pudev->dev.status = USB_STATUS_DEFAULT;
490 }
491 }
492 } else {
493 usbd_enum_error(pudev, req);
494 }
495 }
496
504 static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req)
505 {
506 if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) {
507 uint8_t desc_index = (uint8_t)(req->wValue >> 8U);
508
509 if (desc_index <= 0x03U) {
510 uint16_t len;
511 uint8_t *pbuf;
512
513 /* call corresponding descriptor get function */
514 pbuf = standard_descriptor_get[desc_index - 1U](pudev, (uint8_t)(req->wValue) & 0xFFU, &len);
515
516 if ((0U != len) && (0U != req->wLength)) {
517 len = USB_MIN(len, req->wLength);
518
519 if ((1U == desc_index) && (64U == req->wLength)) {
520 len = 8U;
521 }
522
523 usbd_ctltx(pudev, pbuf, len);
524 }
525 } else {
526 usbd_enum_error(pudev, req);
527 }
528 } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQTYPE_MASK)) {
529 pudev->dev.class_req_handler(pudev, req);
530 } else {
531 /* no operation */
532 }
533 }
534
542 static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req)
543 {
544 /* no handle... */
545 }
546
554 static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req)
555 {
556 uint32_t USBD_default_config = 0U;
557
558 if (1U != req->wLength) {
559 usbd_enum_error(pudev, req);
560 } else {
561 switch (pudev->dev.status) {
562 case USB_STATUS_ADDRESSED:
563 usbd_ctltx(pudev, (uint8_t *)&USBD_default_config, 1U);
564 break;
565 case USB_STATUS_CONFIGURED:
566 usbd_ctltx(pudev, &pudev->dev.config_num, 1U);
567 break;
568 default:
569 usbd_enum_error(pudev, req);
570 break;
571 }
572 }
573 }
574
582 static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req)
583 {
584 static uint8_t cfgidx;
585
586 cfgidx = (uint8_t)(req->wValue);
587
588 if (cfgidx > USBD_CFG_MAX_NUM) {
589 usbd_enum_error(pudev, req);
590 } else {
591 switch (pudev->dev.status) {
592 case USB_STATUS_ADDRESSED:
593 if (cfgidx) {
594 pudev->dev.config_num = cfgidx;
595 pudev->dev.status = USB_STATUS_CONFIGURED;
596 pudev->dev.class_init(pudev, cfgidx);
597 }
598
599 usbd_ctlstatus_tx(pudev);
600 break;
601 case USB_STATUS_CONFIGURED:
602 if (0U == cfgidx) {
603 pudev->dev.status = USB_STATUS_ADDRESSED;
604 pudev->dev.config_num = cfgidx;
605 pudev->dev.class_deinit(pudev, cfgidx);
606 } else if (cfgidx != pudev->dev.config_num) {
607 /* clear old configuration */
608 pudev->dev.class_deinit(pudev, pudev->dev.config_num);
609
610 /* set new configuration */
611 pudev->dev.config_num = cfgidx;
612 pudev->dev.class_init(pudev, cfgidx);
613 } else {
614 /* no operation */
615 }
616
617 usbd_ctlstatus_tx(pudev);
618 break;
619 default:
620 usbd_enum_error(pudev, req);
621 break;
622 }
623 }
624 }
625
633 static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req)
634 {
635 pudev->dev.class_req_handler(pudev, req);
636 }
637
645 static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req)
646 {
647 pudev->dev.class_req_handler(pudev, req);
648 }
649
657 static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req)
658 {
659 /* no handle... */
660 }
661
669 static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req)
670 {
671 uint8_t *psetup = pudev->dev.setup_packet;
672
673 req->bmRequestType = *psetup;
674 req->bRequest = *(uint8_t *)(psetup + 1U);
675 req->wValue = SWAPBYTE (psetup + 2U);
676 req->wIndex = SWAPBYTE (psetup + 4U);
677 req->wLength = SWAPBYTE (psetup + 6U);
678
679 pudev->dev.ctl_len = req->wLength;
680 }
681
689 void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req)
690 {
691 usbd_ep_stall(pudev, 0x80U);
692 usbd_ep_stall(pudev, 0x00U);
693 usb_ep0_startout(pudev);
694 }
usbd_standard_request
uint8_t usbd_standard_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB standard device request
Definition: usbd_std.c:220
USB_REQTYPE_ENDPOINT
#define USB_REQTYPE_ENDPOINT
Definition: usbd_std.h:41
USB_TX
Definition: usb_core.h:96
usb_device_req_struct::wIndex
uint16_t wIndex
Definition: usbd_core.h:120
usb_device_req_struct::wLength
uint16_t wLength
Definition: usbd_core.h:121
USB_VENDOR_REQ
#define USB_VENDOR_REQ
Definition: usbd_std.h:36
USB_CLASS_REQ
#define USB_CLASS_REQ
Definition: usbd_std.h:35
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
usb_device_req_struct
Definition: usbd_core.h:115
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usbd_std.h:39
USB_CTRL_DATA_IN
Definition: usb_core.h:85
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
USB_CTRL_DATA_OUT
Definition: usb_core.h:86
usbd_ep_clear_stall
void usbd_ep_clear_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status
Definition: usbd_core.c:297
USB_REQTYPE_MASK
#define USB_REQTYPE_MASK
Definition: usb_std.h:40
USB_REQTYPE_INTERFACE
#define USB_REQTYPE_INTERFACE
Definition: usbd_std.h:40
USB_SET_DEVADDR
#define USB_SET_DEVADDR(DevAddr)
Definition: usb_regs.h:553
IS_NOT_EP0
#define IS_NOT_EP0(ep_addr)
Definition: usbd_std.h:86
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usbd_core.h:117
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:368
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:104
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
LOWBYTE
#define LOWBYTE(x)
Definition: usbd_std.h:81
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:351
USB_RX
Definition: usb_core.h:95
usb_ep_struct
Definition: usbd_core.h:102
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:21
usbd_device_class_request
uint8_t usbd_device_class_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB device class request
Definition: usbd_std.c:235
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
USB_FEATURE_REMOTE_WAKEUP
#define USB_FEATURE_REMOTE_WAKEUP
Definition: usbd_std.h:67
usb_core.h
USB core driver header file.
USB_FEATURE_TEST_MODE
#define USB_FEATURE_TEST_MODE
Definition: usbd_std.h:68
USBD_OK
Definition: usbd_core.h:84
USB_MIN
#define USB_MIN(a, b)
Definition: usbd_std.h:43
usb_core_handle_struct
Definition: usb_core.h:201
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
USB_STATUS_ADDRESSED
#define USB_STATUS_ADDRESSED
Definition: usbd_core.h:22
NULL
#define NULL
Definition: usbd_std.h:20
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:23
usbd_in_transaction
uint8_t usbd_in_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data in stage processing
Definition: usbd_std.c:155
usbd_enum_error
void usbd_enum_error(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB enumeration error event
Definition: usbd_std.c:832
USB_REQ_MASK
#define USB_REQ_MASK
Definition: usbd_std.h:37
usbd_out_transaction
uint8_t usbd_out_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data out stage processing
Definition: usbd_std.c:113
usb_device_req_struct::bRequest
uint8_t bRequest
Definition: usbd_core.h:118
usbd_ctltx
usbd_status_enum usbd_ctltx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel
Definition: usbd_core.c:313
usbd_vendor_request
uint8_t usbd_vendor_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB vendor request
Definition: usbd_std.c:268
USB_FEATURE_ENDP_HALT
#define USB_FEATURE_ENDP_HALT
Definition: usbd_std.h:66
usb_device_req_struct::wValue
uint16_t wValue
Definition: usbd_core.h:119
USB_DCTL
#define USB_DCTL
Definition: usb_regs.h:67
usbd_setup_request_parse
void usbd_setup_request_parse(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
decode setup data packet
Definition: usbd_std.c:812
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:107
usbd_setup_transaction
uint8_t usbd_setup_transaction(usbd_core_handle_struct *pudev)
USB setup stage processing.
Definition: usbd_std.c:80
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_adc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10x_ADC_H
14 #define GD32F10x_ADC_H
15
16 #include "gd32f10x.h"
17
18 /* ADC definitions */
19 #define ADC0 ADC_BASE
20 #define ADC1 (ADC_BASE + 0x400U)
21 #define ADC2 (ADC_BASE + 0x1800U)
22
23 /* registers definitions */
24 #define ADC_STAT(adcx) REG32((adcx) + 0x00U)
25 #define ADC_CTL0(adcx) REG32((adcx) + 0x04U)
26 #define ADC_CTL1(adcx) REG32((adcx) + 0x08U)
27 #define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU)
28 #define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U)
29 #define ADC_IOFF0(adcx) REG32((adcx) + 0x14U)
30 #define ADC_IOFF1(adcx) REG32((adcx) + 0x18U)
31 #define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU)
32 #define ADC_IOFF3(adcx) REG32((adcx) + 0x20U)
33 #define ADC_WDHT(adcx) REG32((adcx) + 0x24U)
34 #define ADC_WDLT(adcx) REG32((adcx) + 0x28U)
35 #define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU)
36 #define ADC_RSQ1(adcx) REG32((adcx) + 0x30U)
37 #define ADC_RSQ2(adcx) REG32((adcx) + 0x34U)
38 #define ADC_ISQ(adcx) REG32((adcx) + 0x38U)
39 #define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU)
40 #define ADC_IDATA1(adcx) REG32((adcx) + 0x40U)
41 #define ADC_IDATA2(adcx) REG32((adcx) + 0x44U)
42 #define ADC_IDATA3(adcx) REG32((adcx) + 0x48U)
43 #define ADC_RDATA(adcx) REG32((adcx) + 0x4CU)
45 /* bits definitions */
46 /* ADC_STAT */
47 #define ADC_STAT_WDE BIT(0)
48 #define ADC_STAT_EOC BIT(1)
49 #define ADC_STAT_EOIC BIT(2)
50 #define ADC_STAT_STIC BIT(3)
51 #define ADC_STAT_STRC BIT(4)
53 /* ADC_CTL0 */
54 #define ADC_CTL0_WDCHSEL BITS(0,4)
55 #define ADC_CTL0_EOCIE BIT(5)
56 #define ADC_CTL0_WDEIE BIT(6)
57 #define ADC_CTL0_EOICIE BIT(7)
58 #define ADC_CTL0_SM BIT(8)
59 #define ADC_CTL0_WDSC BIT(9)
60 #define ADC_CTL0_ICA BIT(10)
61 #define ADC_CTL0_DISRC BIT(11)
62 #define ADC_CTL0_DISIC BIT(12)
63 #define ADC_CTL0_DISNUM BITS(13,15)
64 #define ADC_CTL0_SYNCM BITS(16,19)
65 #define ADC_CTL0_IWDEN BIT(22)
66 #define ADC_CTL0_RWDEN BIT(23)
67 #define ADC_CTL0_DRES BITS(24,25)
69 /* ADC_CTL1 */
70 #define ADC_CTL1_ADCON BIT(0)
71 #define ADC_CTL1_CTN BIT(1)
72 #define ADC_CTL1_CLB BIT(2)
73 #define ADC_CTL1_RSTCLB BIT(3)
74 #define ADC_CTL1_DMA BIT(8)
75 #define ADC_CTL1_DAL BIT(11)
76 #define ADC_CTL1_ETSIC BITS(12,14)
77 #define ADC_CTL1_ETEIC BIT(15)
78 #define ADC_CTL1_ETSRC BITS(17,19)
79 #define ADC_CTL1_ETERC BIT(20)
80 #define ADC_CTL1_SWICST BIT(21)
81 #define ADC_CTL1_SWRCST BIT(22)
82 #define ADC_CTL1_TSVREN BIT(23)
84 /* ADC_SAMPTx x=0..1 */
85 #define ADC_SAMPTX_SPTN BITS(0,2)
87 /* ADC_IOFFx x=0..3 */
88 #define ADC_IOFFX_IOFF BITS(0,11)
90 /* ADC_WDHT */
91 #define ADC_WDHT_WDHT BITS(0,11)
93 /* ADC_WDLT */
94 #define ADC_WDLT_WDLT BITS(0,11)
96 /* ADC_RSQx */
97 #define ADC_RSQX_RSQN BITS(0,4)
98 #define ADC_RSQ0_RL BITS(20,23)
100 /* ADC_ISQ */
101 #define ADC_ISQ_ISQN BITS(0,4)
102 #define ADC_ISQ_IL BITS(20,21)
104 /* ADC_IDATAx x=0..3*/
105 #define ADC_IDATAX_IDATAN BITS(0,15)
107 /* ADC_RDATA */
108 #define ADC_RDATA_RDATA BITS(0,15)
109 #define ADC_RDATA_ADC1RDTR BITS(16,31)
112 /* constants definitions */
113 /* adc_stat register value */
114 #define ADC_FLAG_WDE ADC_STAT_WDE
115 #define ADC_FLAG_EOC ADC_STAT_EOC
116 #define ADC_FLAG_EOIC ADC_STAT_EOIC
117 #define ADC_FLAG_STIC ADC_STAT_STIC
118 #define ADC_FLAG_STRC ADC_STAT_STRC
120 /* adc_ctl0 register value */
121 #define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13))
123 #define ADC_SCAN_MODE ADC_CTL0_SM
125 #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA
127 #define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
128 #define ADC_MODE_FREE CTL0_SYNCM(0)
129 #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1)
130 #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2)
131 #define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3)
132 #define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4)
133 #define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5)
134 #define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6)
135 #define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7)
136 #define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8)
137 #define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9)
139 /* adc_ctl1 register value */
140 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
141 #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL
143 #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN
145 #define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
146 #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0)
147 #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1)
148 #define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2)
149 #define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3)
150 #define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4)
151 #define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5)
152 #define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6)
153 #define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6)
154 #define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7)
156 #define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0)
157 #define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1)
158 #define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2)
159 #define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3)
160 #define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4)
161 #define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5)
162 #define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6)
164 #define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12))
165 #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0)
166 #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1)
167 #define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2)
168 #define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3)
169 #define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4)
170 #define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5)
171 #define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6)
172 #define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6)
173 #define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7)
175 #define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0)
176 #define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1)
177 #define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2)
178 #define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3)
179 #define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4)
180 #define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5)
181 #define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6)
183 /* adc_samptx register value */
184 #define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
185 #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0)
186 #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1)
187 #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2)
188 #define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3)
189 #define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4)
190 #define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5)
191 #define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6)
192 #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7)
194 /* adc_ioffx register value */
195 #define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
197 /* adc_wdht register value */
198 #define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
200 /* adc_wdlt register value */
201 #define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
203 /* adc_rsqx register value */
204 #define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
206 /* adc_isq register value */
207 #define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
209 /* ADC channel group definitions */
210 #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U)
211 #define ADC_INSERTED_CHANNEL ((uint8_t)0x02U)
212 #define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U)
214 #define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U)
216 /* ADC inserted channel definitions */
217 #define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U)
218 #define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U)
219 #define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U)
220 #define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U)
222 /* ADC channel definitions */
223 #define ADC_CHANNEL_0 ((uint8_t)0x00U)
224 #define ADC_CHANNEL_1 ((uint8_t)0x01U)
225 #define ADC_CHANNEL_2 ((uint8_t)0x02U)
226 #define ADC_CHANNEL_3 ((uint8_t)0x03U)
227 #define ADC_CHANNEL_4 ((uint8_t)0x04U)
228 #define ADC_CHANNEL_5 ((uint8_t)0x05U)
229 #define ADC_CHANNEL_6 ((uint8_t)0x06U)
230 #define ADC_CHANNEL_7 ((uint8_t)0x07U)
231 #define ADC_CHANNEL_8 ((uint8_t)0x08U)
232 #define ADC_CHANNEL_9 ((uint8_t)0x09U)
233 #define ADC_CHANNEL_10 ((uint8_t)0x0AU)
234 #define ADC_CHANNEL_11 ((uint8_t)0x0BU)
235 #define ADC_CHANNEL_12 ((uint8_t)0x0CU)
236 #define ADC_CHANNEL_13 ((uint8_t)0x0DU)
237 #define ADC_CHANNEL_14 ((uint8_t)0x0EU)
238 #define ADC_CHANNEL_15 ((uint8_t)0x0FU)
239 #define ADC_CHANNEL_16 ((uint8_t)0x10U)
240 #define ADC_CHANNEL_17 ((uint8_t)0x11U)
242 /* ADC interrupt flag */
243 #define ADC_INT_WDE ADC_STAT_WDE
244 #define ADC_INT_EOC ADC_STAT_EOC
245 #define ADC_INT_EOIC ADC_STAT_EOIC
248 /* function declarations */
249 /* reset ADC */
250 void adc_deinit(uint32_t adc_periph);
251 /* enable ADC interface */
252 void adc_enable(uint32_t adc_periph);
253 /* disable ADC interface */
254 void adc_disable(uint32_t adc_periph);
255 /* ADC calibration and reset calibration */
256 void adc_calibration_enable(uint32_t adc_periph);
257 /* enable DMA request */
258 void adc_dma_mode_enable(uint32_t adc_periph);
259 /* disable DMA request */
260 void adc_dma_mode_disable(uint32_t adc_periph);
261 /* enable the temperature sensor and Vrefint channel */
262 void adc_tempsensor_vrefint_enable(void);
263 /* disable the temperature sensor and Vrefint channel */
264 void adc_tempsensor_vrefint_disable(void);
265
266 /* configure ADC discontinuous mode */
267 void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length);
268
269 /* configure the ADC mode */
270 void adc_mode_config(uint32_t mode);
271 /* enable or disable ADC special function */
272 void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue);
273 /* configure ADC data alignment */
274 void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment);
275 /* configure the length of regular channel group or inserted channel group */
276 void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length);
277 /* configure ADC regular channel */
278 void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
279 /* configure ADC inserted channel */
280 void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
281 /* configure ADC inserted channel offset */
282 void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset);
283 /* enable ADC external trigger */
284 void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
285 /* configure ADC external trigger source */
286 void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
287 /* enable ADC software trigger */
288 void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group);
289 /* get the bit state of ADCx software start conversion */
290 FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
291 /* get the bit state of ADCx software inserted channel start conversion */
292 FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
293
294 /* read ADC regular group data register */
295 uint16_t adc_regular_data_read(uint32_t adc_periph);
296 /* read ADC inserted group data register */
297 uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
298 /* read the last ADC0 and ADC1 conversion result data in sync mode */
299 uint32_t adc_sync_mode_convert_value_read(void);
300
301 /* get the ADC flag bits */
302 FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag);
303 /* clear the ADC flag bits */
304 void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag);
305 /* get the ADC interrupt bits */
306 FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt);
307 /* clear the ADC flag */
308 void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt);
309 /* enable ADC interrupt */
310 void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt);
311 /* disable ADC interrupt */
312 void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt);
313
314 /* configure ADC analog watchdog single channel */
315 void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
316 /* configure ADC analog watchdog group channel */
317 void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
318 /* disable ADC analog watchdog */
319 void adc_watchdog_disable(uint32_t adc_periph);
320 /* configure ADC analog watchdog threshold */
321 void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold);
322
323 #endif /* GD32F10x_ADC_H */
adc_watchdog_group_channel_enable
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
configure ADC analog watchdog group channel
Definition: gd32f10x_adc.c:817
adc_regular_data_read
uint16_t adc_regular_data_read(uint32_t adc_periph)
read ADC regular group data register
Definition: gd32f10x_adc.c:578
adc_external_trigger_config
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
enable ADC external trigger
Definition: gd32f10x_adc.c:435
adc_mode_config
void adc_mode_config(uint32_t mode)
configure the ADC sync mode
Definition: gd32f10x_adc.c:190
adc_interrupt_disable
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
disable ADC interrupt
Definition: gd32f10x_adc.c:772
adc_external_trigger_source_config
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
configure ADC external trigger source
Definition: gd32f10x_adc.c:501
adc_dma_mode_enable
void adc_dma_mode_enable(uint32_t adc_periph)
enable DMA request
Definition: gd32f10x_adc.c:98
adc_flag_get
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
get the ADC flag bits
Definition: gd32f10x_adc.c:646
adc_data_alignment_config
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
configure ADC data alignment
Definition: gd32f10x_adc.c:245
adc_inserted_data_read
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
read ADC inserted group data register
Definition: gd32f10x_adc.c:596
adc_inserted_software_startconv_flag_get
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
get the bit state of ADCx software inserted channel start conversion
Definition: gd32f10x_adc.c:561
adc_inserted_channel_config
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
configure ADC inserted channel
Definition: gd32f10x_adc.c:366
adc_calibration_enable
void adc_calibration_enable(uint32_t adc_periph)
ADC calibration and reset calibration.
Definition: gd32f10x_adc.c:77
adc_dma_mode_disable
void adc_dma_mode_disable(uint32_t adc_periph)
disable DMA request
Definition: gd32f10x_adc.c:110
adc_interrupt_flag_clear
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
clear the ADC flag
Definition: gd32f10x_adc.c:728
adc_discontinuous_mode_config
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
configure ADC discontinuous mode
Definition: gd32f10x_adc.c:153
adc_watchdog_disable
void adc_watchdog_disable(uint32_t adc_periph)
disable ADC analog watchdog
Definition: gd32f10x_adc.c:843
adc_inserted_channel_offset_config
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
configure ADC inserted channel offset
Definition: gd32f10x_adc.c:407
adc_regular_channel_config
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
configure ADC regular channel
Definition: gd32f10x_adc.c:307
adc_watchdog_single_channel_enable
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
configure ADC analog watchdog single channel
Definition: gd32f10x_adc.c:797
adc_tempsensor_vrefint_enable
void adc_tempsensor_vrefint_enable(void)
enable the temperature sensor and Vrefint channel
Definition: gd32f10x_adc.c:121
adc_enable
void adc_enable(uint32_t adc_periph)
enable ADC interface
Definition: gd32f10x_adc.c:51
adc_tempsensor_vrefint_disable
void adc_tempsensor_vrefint_disable(void)
disable the temperature sensor and Vrefint channel
Definition: gd32f10x_adc.c:133
adc_flag_clear
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
clear the ADC flag bits
Definition: gd32f10x_adc.c:669
adc_deinit
void adc_deinit(uint32_t adc_periph)
reset ADC
Definition: gd32f10x_adc.c:22
adc_interrupt_enable
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
enable ADC interrupt
Definition: gd32f10x_adc.c:745
adc_regular_software_startconv_flag_get
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
get the bit state of ADCx software start conversion
Definition: gd32f10x_adc.c:545
adc_sync_mode_convert_value_read
uint32_t adc_sync_mode_convert_value_read(void)
read the last ADC0 and ADC1 conversion result data in sync mode
Definition: gd32f10x_adc.c:626
adc_software_trigger_enable
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
enable ADC software trigger
Definition: gd32f10x_adc.c:528
adc_disable
void adc_disable(uint32_t adc_periph)
disable ADC interface
Definition: gd32f10x_adc.c:65
adc_watchdog_threshold_config
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
configure ADC analog watchdog threshold
Definition: gd32f10x_adc.c:857
adc_special_function_config
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
enable or disable ADC special function
Definition: gd32f10x_adc.c:209
adc_channel_length_config
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
configure the length of regular channel group or inserted channel group
Definition: gd32f10x_adc.c:268
adc_interrupt_flag_get
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
get the ADC interrupt bits
Definition: gd32f10x_adc.c:686
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_usart.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_USART_H
14 #define GD32F10X_USART_H
15
16 #include "gd32f10x.h"
17
18 /* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */
19 #define USART1 USART_BASE
20 #define USART2 (USART_BASE+0x00000400U)
21 #define UART3 (USART_BASE+0x00000800U)
22 #define UART4 (USART_BASE+0x00000C00U)
23 #define USART0 (USART_BASE+0x0000F400U)
25 /* registers definitions */
26 #define USART_STAT(usartx) REG32((usartx) + 0x00U)
27 #define USART_DATA(usartx) REG32((usartx) + 0x04U)
28 #define USART_BAUD(usartx) REG32((usartx) + 0x08U)
29 #define USART_CTL0(usartx) REG32((usartx) + 0x0CU)
30 #define USART_CTL1(usartx) REG32((usartx) + 0x10U)
31 #define USART_CTL2(usartx) REG32((usartx) + 0x14U)
32 #define USART_GP(usartx) REG32((usartx) + 0x18U)
34 /* bits definitions */
35 /* USARTx_STAT */
36 #define USART_STAT_PERR BIT(0)
37 #define USART_STAT_FERR BIT(1)
38 #define USART_STAT_NERR BIT(2)
39 #define USART_STAT_ORERR BIT(3)
40 #define USART_STAT_IDLEF BIT(4)
41 #define USART_STAT_RBNE BIT(5)
42 #define USART_STAT_TC BIT(6)
43 #define USART_STAT_TBE BIT(7)
44 #define USART_STAT_LBDF BIT(8)
45 #define USART_STAT_CTSF BIT(9)
47 /* USARTx_DATA */
48 #define USART_DATA_DATA BITS(0,8)
50 /* USARTx_BAUD */
51 #define USART_BAUD_FRADIV BITS(0,3)
52 #define USART_BAUD_INTDIV BITS(4,15)
54 /* USARTx_CTL0 */
55 #define USART_CTL0_SBKCMD BIT(0)
56 #define USART_CTL0_RWU BIT(1)
57 #define USART_CTL0_REN BIT(2)
58 #define USART_CTL0_TEN BIT(3)
59 #define USART_CTL0_IDLEIE BIT(4)
60 #define USART_CTL0_RBNEIE BIT(5)
61 #define USART_CTL0_TCIE BIT(6)
62 #define USART_CTL0_TBEIE BIT(7)
63 #define USART_CTL0_PERRIE BIT(8)
64 #define USART_CTL0_PM BIT(9)
65 #define USART_CTL0_PCEN BIT(10)
66 #define USART_CTL0_WM BIT(11)
67 #define USART_CTL0_WL BIT(12)
68 #define USART_CTL0_UEN BIT(13)
70 /* USARTx_CTL1 */
71 #define USART_CTL1_ADDR BITS(0,3)
72 #define USART_CTL1_LBLEN BIT(5)
73 #define USART_CTL1_LBDIE BIT(6)
74 #define USART_CTL1_CLEN BIT(8)
75 #define USART_CTL1_CPH BIT(9)
76 #define USART_CTL1_CPL BIT(10)
77 #define USART_CTL1_CKEN BIT(11)
78 #define USART_CTL1_STB BITS(12,13)
79 #define USART_CTL1_LMEN BIT(14)
81 /* USARTx_CTL2 */
82 #define USART_CTL2_ERRIE BIT(0)
83 #define USART_CTL2_IREN BIT(1)
84 #define USART_CTL2_IRLP BIT(2)
85 #define USART_CTL2_HDEN BIT(3)
86 #define USART_CTL2_NKEN BIT(4)
87 #define USART_CTL2_SCEN BIT(5)
88 #define USART_CTL2_DENR BIT(6)
89 #define USART_CTL2_DENT BIT(7)
90 #define USART_CTL2_RTSEN BIT(8)
91 #define USART_CTL2_CTSEN BIT(9)
92 #define USART_CTL2_CTSIE BIT(10)
94 /* USARTx_GP */
95 #define USART_GP_PSC BITS(0,7)
96 #define USART_GP_GUAT BITS(8,15)
98 /* constants definitions */
99 /* define the USART bit position and its register index offset */
100 #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
101 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
102 #define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
103 #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
104 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
105 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
106 #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
107
108 /* register offset */
109 #define USART_STAT_REG_OFFSET 0x00U
110 #define USART_CTL0_REG_OFFSET 0x0CU
111 #define USART_CTL1_REG_OFFSET 0x10U
112 #define USART_CTL2_REG_OFFSET 0x14U
114 /* USART flags */
115 typedef enum
116 {
117 /* flags in STAT register */
118 USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U),
119 USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U),
120 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U),
121 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U),
122 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U),
123 USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U),
124 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U),
125 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U),
126 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U),
127 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U),
128 }usart_flag_enum;
129
130 /* USART interrupt flags */
131 typedef enum
132 {
133 /* interrupt flags in CTL0 register */
134 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U),
135 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U),
136 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U),
137 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U),
138 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U),
139 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U),
140 /* interrupt flags in CTL1 register */
141 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U),
142 /* interrupt flags in CTL2 register */
143 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),
144 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U),
145 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U),
146 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U),
147 }usart_interrupt_flag_enum;
148
149 /* USART interrupt enable or disable */
150 typedef enum
151 {
152 /* interrupt in CTL0 register */
153 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),
154 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U),
155 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U),
156 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),
157 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),
158 /* interrupt in CTL1 register */
159 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U),
160 /* interrupt in CTL2 register */
161 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U),
162 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),
163 }usart_interrupt_enum;
164
165 /* USART receiver configure */
166 #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
167 #define USART_RECEIVE_ENABLE CTL0_REN(1)
168 #define USART_RECEIVE_DISABLE CTL0_REN(0)
170 /* USART transmitter configure */
171 #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
172 #define USART_TRANSMIT_ENABLE CTL0_TEN(1)
173 #define USART_TRANSMIT_DISABLE CTL0_TEN(0)
175 /* USART parity bits definitions */
176 #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
177 #define USART_PM_NONE CTL0_PM(0)
178 #define USART_PM_EVEN CTL0_PM(2)
179 #define USART_PM_ODD CTL0_PM(3)
181 /* USART wakeup method in mute mode */
182 #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
183 #define USART_WM_IDLE CTL0_WM(0)
184 #define USART_WM_ADDR CTL0_WM(1)
186 /* USART word length definitions */
187 #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
188 #define USART_WL_8BIT CTL0_WL(0)
189 #define USART_WL_9BIT CTL0_WL(1)
191 /* USART stop bits definitions */
192 #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
193 #define USART_STB_1BIT CTL1_STB(0)
194 #define USART_STB_0_5BIT CTL1_STB(1)
195 #define USART_STB_2BIT CTL1_STB(2)
196 #define USART_STB_1_5BIT CTL1_STB(3)
198 /* USART LIN break frame length */
199 #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
200 #define USART_LBLEN_10B CTL1_LBLEN(0)
201 #define USART_LBLEN_11B CTL1_LBLEN(1)
203 /* USART CK length */
204 #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
205 #define USART_CLEN_NONE CTL1_CLEN(0)
206 #define USART_CLEN_EN CTL1_CLEN(1)
208 /* USART clock phase */
209 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
210 #define USART_CPH_1CK CTL1_CPH(0)
211 #define USART_CPH_2CK CTL1_CPH(1)
213 /* USART clock polarity */
214 #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
215 #define USART_CPL_LOW CTL1_CPL(0)
216 #define USART_CPL_HIGH CTL1_CPL(1)
218 /* USART DMA request for receive configure */
219 #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
220 #define USART_DENR_ENABLE CLT2_DENR(1)
221 #define USART_DENR_DISABLE CLT2_DENR(0)
223 /* USART DMA request for transmission configure */
224 #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
225 #define USART_DENT_ENABLE CLT2_DENT(1)
226 #define USART_DENT_DISABLE CLT2_DENT(0)
228 /* USART RTS configure */
229 #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
230 #define USART_RTS_ENABLE CLT2_RTSEN(1)
231 #define USART_RTS_DISABLE CLT2_RTSEN(0)
233 /* USART CTS configure */
234 #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
235 #define USART_CTS_ENABLE CLT2_CTSEN(1)
236 #define USART_CTS_DISABLE CLT2_CTSEN(0)
238 /* USART IrDA low-power enable */
239 #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
240 #define USART_IRLP_LOW CTL2_IRLP(1)
241 #define USART_IRLP_NORMAL CTL2_IRLP(0)
243 /* function declarations */
244 /* initialization functions */
245 /* reset USART */
246 void usart_deinit(uint32_t usart_periph);
247 /* configure USART baud rate value */
248 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
249 /* configure USART parity function */
250 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
251 /* configure USART word length */
252 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
253 /* configure USART stop bit length */
254 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
255
256 /* USART normal mode communication */
257 /* enable USART */
258 void usart_enable(uint32_t usart_periph);
259 /* disable USART */
260 void usart_disable(uint32_t usart_periph);
261 /* configure USART transmitter */
262 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
263 /* configure USART receiver */
264 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
265 /* USART transmit data function */
266 void usart_data_transmit(uint32_t usart_periph, uint32_t data);
267 /* USART receive data function */
268 uint16_t usart_data_receive(uint32_t usart_periph);
269
270 /* multi-processor communication */
271 /* configure address of the USART */
272 void usart_address_config(uint32_t usart_periph, uint8_t addr);
273 /* enable mute mode */
274 void usart_mute_mode_enable(uint32_t usart_periph);
275 /* disable mute mode */
276 void usart_mute_mode_disable(uint32_t usart_periph);
277 /* configure wakeup method in mute mode */
278 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
279
280 /* LIN mode communication */
281 /* LIN mode enable */
282 void usart_lin_mode_enable(uint32_t usart_periph);
283 /* LIN mode disable */
284 void usart_lin_mode_disable(uint32_t usart_periph);
285 /* LIN break detection length */
286 void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen);
287 /* send break frame */
288 void usart_send_break(uint32_t usart_periph);
289
290 /* half-duplex communication */
291 /* half-duplex enable */
292 void usart_halfduplex_enable(uint32_t usart_periph);
293 /* half-duplex disable */
294 void usart_halfduplex_disable(uint32_t usart_periph);
295
296 /* synchronous communication */
297 /* clock enable */
298 void usart_synchronous_clock_enable(uint32_t usart_periph);
299 /* clock disable */
300 void usart_synchronous_clock_disable(uint32_t usart_periph);
301 /* configure usart synchronous mode parameters */
302 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
303
304 /* smartcard communication */
305 /* guard time value configure in smartcard mode */
306 void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut);
307 /* smartcard mode enable */
308 void usart_smartcard_mode_enable(uint32_t usart_periph);
309 /* smartcard mode disable */
310 void usart_smartcard_mode_disable(uint32_t usart_periph);
311 /* NACK enable in smartcard mode */
312 void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
313 /* NACK disable in smartcard mode */
314 void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
315
316 /* IrDA communication */
317 /* enable IrDA mode */
318 void usart_irda_mode_enable(uint32_t usart_periph);
319 /* disable IrDA mode */
320 void usart_irda_mode_disable(uint32_t usart_periph);
321 /* configure the peripheral clock prescaler */
322 void usart_prescaler_config(uint32_t usart_periph, uint8_t psc);
323 /* configure IrDA low-power */
324 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
325
326 /* hardware flow communication */
327 /* configure hardware flow control RTS */
328 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
329 /* configure hardware flow control CTS */
330 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
331
332 /* configure USART DMA for reception */
333 void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
334 /* configure USART DMA for transmission */
335 void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
336
337 /* flag functions */
338 /* get flag in STAT register */
339 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
340 /* clear flag in STAT register */
341 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
342
343 /* interrupt functions */
344 /* enable USART interrupt */
345 void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag);
346 /* disable USART interrupt */
347 void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag);
348 /* get USART interrupt and flag status */
349 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
350 /* clear interrupt flag in STAT register */
351 void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag);
352 #endif /* GD32F10X_USART_H */
usart_interrupt_flag_clear
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
clear USART interrupt flag in STAT register
Definition: gd32f10x_usart.c:708
usart_smartcard_mode_nack_disable
void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
disable NACK in smartcard mode
Definition: gd32f10x_usart.c:445
USART_INT_FLAG_LBD
Definition: gd32f10x_usart.h:141
USART_FLAG_CTSF
Definition: gd32f10x_usart.h:118
USART_CTL0_REG_OFFSET
#define USART_CTL0_REG_OFFSET
Definition: gd32f10x_usart.h:110
usart_interrupt_enable
void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag)
enable USART interrupt
Definition: gd32f10x_usart.c:639
usart_disable
void usart_disable(uint32_t usart_periph)
disable USART
Definition: gd32f10x_usart.c:156
usart_lin_mode_disable
void usart_lin_mode_disable(uint32_t usart_periph)
disable LIN mode
Definition: gd32f10x_usart.c:291
usart_interrupt_flag_enum
usart_interrupt_flag_enum
Definition: gd32f10x_usart.h:131
USART_INT_TC
Definition: gd32f10x_usart.h:155
USART_INT_FLAG_ERR_ORERR
Definition: gd32f10x_usart.h:144
usart_smartcard_mode_disable
void usart_smartcard_mode_disable(uint32_t usart_periph)
disable smartcard mode
Definition: gd32f10x_usart.c:423
usart_synchronous_clock_disable
void usart_synchronous_clock_disable(uint32_t usart_periph)
disable CK pin in synchronous mode
Definition: gd32f10x_usart.c:361
usart_hardware_flow_rts_config
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
configure hardware flow control RTS
Definition: gd32f10x_usart.c:509
usart_mute_mode_wakeup_config
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
configure wakeup method in mute mode
Definition: gd32f10x_usart.c:268
USART_INT_PERR
Definition: gd32f10x_usart.h:153
USART_FLAG_IDLEF
Definition: gd32f10x_usart.h:123
usart_send_break
void usart_send_break(uint32_t usart_periph)
send break frame
Definition: gd32f10x_usart.c:317
USART_FLAG_TBE
Definition: gd32f10x_usart.h:120
USART_INT_LBD
Definition: gd32f10x_usart.h:159
USART_REGIDX_BIT
#define USART_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_usart.h:100
usart_halfduplex_enable
void usart_halfduplex_enable(uint32_t usart_periph)
enable half duplex mode
Definition: gd32f10x_usart.c:328
usart_synchronous_clock_config
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
configure USART synchronous mode parameters
Definition: gd32f10x_usart.c:381
USART_INT_FLAG_ERR_NERR
Definition: gd32f10x_usart.h:145
usart_lin_break_dection_length_config
void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen)
configure lin break frame length
Definition: gd32f10x_usart.c:305
usart_irda_lowpower_config
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
configure IrDA low-power
Definition: gd32f10x_usart.c:494
USART_FLAG_TC
Definition: gd32f10x_usart.h:121
USART_FLAG_LBDF
Definition: gd32f10x_usart.h:119
usart_irda_mode_enable
void usart_irda_mode_enable(uint32_t usart_periph)
enable IrDA mode
Definition: gd32f10x_usart.c:456
usart_data_receive
uint16_t usart_data_receive(uint32_t usart_periph)
USART receive data function.
Definition: gd32f10x_usart.c:219
USART_INT_TBE
Definition: gd32f10x_usart.h:154
usart_mute_mode_enable
void usart_mute_mode_enable(uint32_t usart_periph)
receiver in mute mode
Definition: gd32f10x_usart.c:243
usart_deinit
void usart_deinit(uint32_t usart_periph)
reset USART/UART
Definition: gd32f10x_usart.c:21
USART_INT_ERR
Definition: gd32f10x_usart.h:162
USART_INT_FLAG_PERR
Definition: gd32f10x_usart.h:134
usart_baudrate_set
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
configure USART baud rate value
Definition: gd32f10x_usart.c:56
usart_flag_clear
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
clear flag in STAT register
Definition: gd32f10x_usart.c:619
USART_INT_FLAG_TBE
Definition: gd32f10x_usart.h:135
USART_INT_CTS
Definition: gd32f10x_usart.h:161
usart_data_transmit
void usart_data_transmit(uint32_t usart_periph, uint32_t data)
USART transmit data function.
Definition: gd32f10x_usart.c:208
USART_STAT_REG_OFFSET
#define USART_STAT_REG_OFFSET
Definition: gd32f10x_usart.h:109
USART_INT_FLAG_IDLE
Definition: gd32f10x_usart.h:139
USART_INT_FLAG_RBNE_ORERR
Definition: gd32f10x_usart.h:138
USART_INT_RBNE
Definition: gd32f10x_usart.h:156
usart_mute_mode_disable
void usart_mute_mode_disable(uint32_t usart_periph)
receiver in active mode
Definition: gd32f10x_usart.c:254
USART_CTL1_REG_OFFSET
#define USART_CTL1_REG_OFFSET
Definition: gd32f10x_usart.h:111
USART_FLAG_RBNE
Definition: gd32f10x_usart.h:122
usart_guard_time_config
void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut)
configure guard time value in smartcard mode
Definition: gd32f10x_usart.c:400
USART_CTL2_REG_OFFSET
#define USART_CTL2_REG_OFFSET
Definition: gd32f10x_usart.h:112
usart_address_config
void usart_address_config(uint32_t usart_periph, uint8_t addr)
configure the address of the USART in wake up by address match mode
Definition: gd32f10x_usart.c:231
USART_FLAG_ORERR
Definition: gd32f10x_usart.h:124
USART_FLAG_PERR
Definition: gd32f10x_usart.h:127
usart_interrupt_flag_get
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
get USART interrupt and flag status
Definition: gd32f10x_usart.c:682
USART_FLAG_NERR
Definition: gd32f10x_usart.h:125
usart_irda_mode_disable
void usart_irda_mode_disable(uint32_t usart_periph)
disable IrDA mode
Definition: gd32f10x_usart.c:467
USART_REGIDX_BIT2
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)
Definition: gd32f10x_usart.h:103
USART_INT_IDLE
Definition: gd32f10x_usart.h:157
usart_parity_config
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
configure USART parity
Definition: gd32f10x_usart.c:96
usart_stop_bit_set
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
configure USART stop bit length
Definition: gd32f10x_usart.c:132
usart_word_length_set
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
configure USART word length
Definition: gd32f10x_usart.c:113
usart_interrupt_enum
usart_interrupt_enum
Definition: gd32f10x_usart.h:150
usart_dma_transmit_config
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA transmission
Definition: gd32f10x_usart.c:569
usart_flag_enum
usart_flag_enum
Definition: gd32f10x_usart.h:115
usart_hardware_flow_cts_config
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
configure hardware flow control CTS
Definition: gd32f10x_usart.c:529
usart_synchronous_clock_enable
void usart_synchronous_clock_enable(uint32_t usart_periph)
enable CK pin in synchronous mode
Definition: gd32f10x_usart.c:350
usart_smartcard_mode_enable
void usart_smartcard_mode_enable(uint32_t usart_periph)
enable smartcard mode
Definition: gd32f10x_usart.c:412
usart_prescaler_config
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc)
configure the peripheral clock prescaler in USART IrDA low-power mode
Definition: gd32f10x_usart.c:479
usart_lin_mode_enable
void usart_lin_mode_enable(uint32_t usart_periph)
enable LIN mode
Definition: gd32f10x_usart.c:280
usart_receive_config
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
configure USART receiver
Definition: gd32f10x_usart.c:190
USART_INT_FLAG_ERR_FERR
Definition: gd32f10x_usart.h:146
USART_INT_FLAG_CTS
Definition: gd32f10x_usart.h:143
usart_smartcard_mode_nack_enable
void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
enable NACK in smartcard mode
Definition: gd32f10x_usart.c:434
usart_dma_receive_config
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA reception
Definition: gd32f10x_usart.c:549
USART_INT_FLAG_RBNE
Definition: gd32f10x_usart.h:137
USART_FLAG_FERR
Definition: gd32f10x_usart.h:126
usart_transmit_config
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
configure USART transmitter
Definition: gd32f10x_usart.c:170
usart_flag_get
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
get flag in STAT register
Definition: gd32f10x_usart.c:598
usart_halfduplex_disable
void usart_halfduplex_disable(uint32_t usart_periph)
disable half duplex mode
Definition: gd32f10x_usart.c:339
usart_interrupt_disable
void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag)
disable USART interrupt
Definition: gd32f10x_usart.c:659
usart_enable
void usart_enable(uint32_t usart_periph)
enable USART
Definition: gd32f10x_usart.c:145
USART_INT_FLAG_TC
Definition: gd32f10x_usart.h:136
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Source/usbd_core.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Source
usbd_core.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbd_core.h"
14 #include "usbd_std.h"
15
16 uint32_t g_interrupt_mask = 0U;
17 uint32_t g_free_buf_addr = ENDP_BUF_ADDR;
18
19 usbd_ep_buf_struct *pbuf_reg = (usbd_ep_buf_struct *)USBD_RAM;
20
27 void usbd_core_init (usbd_core_handle_struct *pudev)
28 {
29 /* disable remote wakeup feature */
30 pudev->remote_wakeup = 0U;
31
32 /* just reset the CLOSE bit */
33 USBD_REG_SET(USBD_CTL, CTL_SETRST);
34
35 /* may be need wait some time(tSTARTUP) ... */
36
37 /* clear SETRST bit in USBD_CTL register */
38 USBD_REG_SET(USBD_CTL, 0U);
39
40 /* clear all pending interrupts */
41 USBD_REG_SET(USBD_INTF, 0U);
42
43 /* set allocation buffer address */
44 USBD_REG_SET(USBD_BADDR, BUFFER_ADDRESS & 0xFFF8U);
45
46 g_interrupt_mask = IER_MASK;
47
48 #ifdef LPM_ENABLED
49 /* enable L1REQ interrupt */
50 USBD_REG_SET(USBD_LPMCS, LPMCS_LPMACK | LPMCS_LPMEN);
51 #endif /* LPM_ENABLED */
52
53 /* enable all interrupts mask bits */
54 USBD_REG_SET(USBD_CTL, g_interrupt_mask);
55 }
56
64 void user_buffer_free (uint8_t ep_num, uint8_t dir)
65 {
66 if (DBUF_EP_OUT == dir) {
67 USBD_SWBUF_RX_TOGGLE(ep_num);
68 } else if (DBUF_EP_IN == dir) {
69 USBD_SWBUF_TX_TOGGLE(ep_num);
70 } else {
71 /* no operation */
72 }
73 }
74
81 void usbd_core_deinit (void)
82 {
83 /* disable all interrupts and set USB reset */
84 USBD_REG_SET(USBD_CTL, CTL_SETRST);
85
86 /* clear all interrupt flags */
87 USBD_REG_SET(USBD_INTF, 0U);
88
89 /* close device */
90 USBD_REG_SET(USBD_CTL, CTL_SETRST | CTL_CLOSE);
91 }
92
100 void usbd_ep_init (usbd_core_handle_struct *pudev, void *ep_desc)
101 {
102 usb_ep_struct *ep;
103 uint8_t ep_num = ((usb_descriptor_endpoint_struct *)ep_desc)->bEndpointAddress & 0x0FU;
104 uint32_t reg_value = ((usb_descriptor_endpoint_struct *)ep_desc)->wMaxPacketSize;
105
106 if (((usb_descriptor_endpoint_struct *)ep_desc)->bEndpointAddress >> 7U) {
107 ep = &pudev->in_ep[ep_num];
108
109 ep->maxpacket = reg_value;
110
111 /* set the endpoint transmit buffer address */
112 (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr;
113
114 reg_value = (reg_value + 1U) & ~1U;
115
116 /* configure the endpoint status as NAK status */
117 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK);
118 } else {
119 ep = &pudev->out_ep[ep_num];
120
121 ep->maxpacket = reg_value;
122
123 /* set the endpoint receive buffer address */
124 (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr;
125
126 if (reg_value > 62U) {
127 reg_value = (reg_value + 31U) & ~31U;
128 (pbuf_reg + ep_num)->rx_count = ((reg_value << 5U) - 1U) | 0x8000U;
129 } else {
130 reg_value = (reg_value + 1U) & ~1U;
131 (pbuf_reg + ep_num)->rx_count = reg_value << 9U;
132 }
133
134 /* configure the endpoint status as NAK status */
135 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_NAK);
136 }
137
138 g_free_buf_addr += reg_value;
139
140 /* set the endpoint type */
141 switch (((usb_descriptor_endpoint_struct *)ep_desc)->bmAttributes & USB_EPTYPE_MASK) {
142 case ENDP_CONTROL:
143 reg_value = EP_CONTROL;
144 break;
145 case ENDP_BULK:
146 reg_value = EP_BULK;
147 break;
148 case ENDP_INT:
149 reg_value = EP_INTERRUPT;
150 break;
151 case ENDP_ISOC:
152 reg_value = EP_ISO;
153 break;
154 default:
155 break;
156 }
157
158 USBD_REG_SET(USBD_EPxCS(ep_num), reg_value | ep_num);
159
160 ep->stall = 0;
161 }
162
173 void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr)
174 {
175 uint8_t ep_num = ep_addr & 0x7F;
176
177 if (ep_addr >> 7) {
178 USBD_DTG_TX_CLEAR(ep_num);
179
180 /* configure the endpoint status as DISABLED */
181 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_DISABLED);
182 } else {
183 USBD_DTG_RX_CLEAR(ep_num);
184
185 /* configure the endpoint status as DISABLED */
186 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED);
187 }
188 }
189
202 void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
203 {
204 usb_ep_struct *ep;
205 uint8_t ep_num = ep_addr & 0x7FU;
206
207 ep = &pudev->out_ep[ep_num];
208
209 /* configure the transaction level parameters */
210 ep->trs_buf = pbuf;
211 ep->trs_len = buf_len;
212
213 /* enable endpoint to receive */
214 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID);
215 }
216
229 void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
230 {
231 __IO uint32_t len = 0U;
232 uint8_t ep_num = ep_addr & 0x7FU;
233 usb_ep_struct *ep = &pudev->in_ep[ep_num];
234
235 /* configure the transaction level parameters */
236 ep->trs_buf = pbuf;
237 ep->trs_len = buf_len;
238 ep->trs_count = 0U;
239
240 /* transmit length is more than one packet */
241 if (ep->trs_len > ep->maxpacket) {
242 len = ep->maxpacket;
243 } else {
244 len = ep->trs_len;
245 }
246
247 usbd_ep_data_write(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, (uint16_t)len);
248 (pbuf_reg + ep_num)->tx_count = (uint16_t)len;
249
250 /* enable endpoint to transmit */
251 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID);
252 }
253
264 void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr)
265 {
266 uint8_t ep_num = ep_addr & 0x7FU;
267 usb_ep_struct *ep;
268
269 if (ep_addr >> 7U) {
270 ep = &pudev->in_ep[ep_num];
271
272 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_STALL);
273 } else {
274 ep = &pudev->out_ep[ep_num];
275
276 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_STALL);
277 }
278
279 ep->stall = 1U;
280
281 if (0U == ep_num) {
282 /* control endpoint need to be stalled in two directions */
283 USBD_ENDP_RX_TX_STATUS_SET(ep_num, EPRX_STALL, EPTX_STALL);
284 }
285 }
286
297 void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr)
298 {
299 uint8_t ep_num = ep_addr & 0x7FU;
300 usb_ep_struct *ep;
301
302 if (ep_addr >> 7U) {
303 ep = &pudev->in_ep[ep_num];
304
305 /* clear endpoint data toggle bit */
306 USBD_DTG_TX_CLEAR(ep_num);
307
308 /* clear endpoint stall status */
309 USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID);
310 } else {
311 ep = &pudev->out_ep[ep_num];
312
313 /* clear endpoint data toggle bit */
314 USBD_DTG_RX_CLEAR(ep_num);
315
316 /* clear endpoint stall status */
317 USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID);
318 }
319
320 ep->stall = 0U;
321 }
322
333 uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr)
334 {
335 if (ep_addr >> 7U) {
336 return (uint8_t)USBD_ENDP_TX_STATUS_GET((ep_addr & 0x7FU));
337 } else {
338 return (uint8_t)USBD_ENDP_RX_STATUS_GET(ep_addr);
339 }
340 }
341
350 void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
351 {
352 uint32_t n;
353 uint32_t *write_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM));
354
355 for (n = 0U; n < (bytes + 1U) / 2U; n++) {
356 *write_addr++ = *((__packed uint16_t*)user_fifo);
357 user_fifo += 2U;
358 }
359 }
360
369 void usbd_ep_data_read(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
370 {
371 uint32_t n;
372 uint32_t *read_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM));
373
374 for (n = 0U; n < (bytes + 1U) / 2U; n++) {
375 *((__packed uint16_t*)user_fifo) = (uint16_t)*read_addr++;
376 user_fifo += 2U;
377 }
378 }
379
387 uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num)
388 {
389 return (uint16_t)pudev->out_ep[ep_num].trs_count;
390 }
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
usbd_ep_deinit
void usbd_ep_deinit(usbd_core_handle_struct *pudev, uint8_t ep_addr)
configure the endpoint when it is disabled
Definition: usbd_core.c:173
EP_ISO
#define EP_ISO
Definition: usbd_regs.h:105
EPRX_VALID
#define EPRX_VALID
Definition: usbd_regs.h:127
USBD_ENDP_TX_STATUS_SET
#define USBD_ENDP_TX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:209
USBD_ENDP_RX_STATUS_GET
#define USBD_ENDP_RX_STATUS_GET(ep_num)
Definition: usbd_regs.h:223
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
g_interrupt_mask
uint32_t g_interrupt_mask
Definition: usbd_core.c:16
usbd_core_init
void usbd_core_init(usbd_core_handle_struct *pudev)
device core register initialization
Definition: usbd_core.c:27
ENDP_INT
Definition: usbd_core.h:53
ENDP_ISOC
Definition: usbd_core.h:51
USBD_RAM
#define USBD_RAM
Definition: usbd_regs.h:20
CTL_SETRST
#define CTL_SETRST
Definition: usbd_regs.h:52
USBD_LPMCS
#define USBD_LPMCS
Definition: usbd_regs.h:34
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
EPRX_DISABLED
#define EPRX_DISABLED
Definition: usbd_regs.h:124
usbd_ep_clear_stall
void usbd_ep_clear_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status
Definition: usbd_core.c:297
LPMCS_LPMACK
#define LPMCS_LPMACK
Definition: usbd_regs.h:93
EPRX_NAK
#define EPRX_NAK
Definition: usbd_regs.h:126
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
usbd_ep_status_get
uint8_t usbd_ep_status_get(usbd_core_handle_struct *pudev, uint8_t ep_addr)
get the endpoint status
Definition: usbd_core.c:333
USBD_ENDP_RX_TX_STATUS_SET
#define USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx)
Definition: usbd_regs.h:226
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
EP_CONTROL
#define EP_CONTROL
Definition: usbd_regs.h:104
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usbd_rx_count_get
uint16_t usbd_rx_count_get(usbd_core_handle_struct *pudev, uint8_t ep_num)
get the received data length
Definition: usbd_core.c:387
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
DBUF_EP_IN
Definition: usbd_regs.h:164
usbd_core_handle_struct::remote_wakeup
uint8_t remote_wakeup
Definition: usbd_core.h:131
USBD_ENDP_RX_STATUS_SET
#define USBD_ENDP_RX_STATUS_SET(ep_num, state)
Definition: usbd_regs.h:215
usbd_core_handle_struct
Definition: usbd_core.h:125
USBD_BADDR
#define USBD_BADDR
Definition: usbd_regs.h:28
usb_ep_struct
Definition: usbd_core.h:102
usbd_ep_buf_struct
Definition: usbd_core.h:89
EP_BULK
#define EP_BULK
Definition: usbd_regs.h:103
ENDP_BULK
Definition: usbd_core.h:52
usbd_ep_data_read
void usbd_ep_data_read(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
read datas from USBRAM to user fifo
Definition: usbd_core.c:369
EPTX_VALID
#define EPTX_VALID
Definition: usbd_regs.h:118
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
ENDP_CONTROL
Definition: usbd_core.h:50
USBD_SWBUF_TX_TOGGLE
#define USBD_SWBUF_TX_TOGGLE(ep_num)
Definition: usbd_regs.h:268
usbd_ep_data_write
void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
write datas from user fifo to USBRAM
Definition: usbd_core.c:350
user_buffer_free
void user_buffer_free(uint8_t ep_num, uint8_t dir)
free buffer used from application by toggling the SW_BUF byte
Definition: usbd_core.c:64
CTL_CLOSE
#define CTL_CLOSE
Definition: usbd_regs.h:51
IER_MASK
#define IER_MASK
Definition: usbd_core.h:20
LPMCS_LPMEN
#define LPMCS_LPMEN
Definition: usbd_regs.h:94
EPTX_DISABLED
#define EPTX_DISABLED
Definition: usbd_regs.h:115
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
USBD_ENDP_TX_STATUS_GET
#define USBD_ENDP_TX_STATUS_GET(ep_num)
Definition: usbd_regs.h:222
EPTX_STALL
#define EPTX_STALL
Definition: usbd_regs.h:116
usb_ep_struct::stall
uint8_t stall
Definition: usbd_core.h:105
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
USBD_EPxCS
#define USBD_EPxCS(ep_id)
Definition: usbd_regs.h:31
USBD_SWBUF_RX_TOGGLE
#define USBD_SWBUF_RX_TOGGLE(ep_num)
Definition: usbd_regs.h:269
usbd_core_deinit
void usbd_core_deinit(void)
device core register configure when stop device
Definition: usbd_core.c:81
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
pbuf_reg
usbd_ep_buf_struct * pbuf_reg
Definition: usbd_core.c:19
DBUF_EP_OUT
Definition: usbd_regs.h:165
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
ENDP_BUF_ADDR
#define ENDP_BUF_ADDR
Definition: usbd_core.h:45
USBD_DTG_RX_CLEAR
#define USBD_DTG_RX_CLEAR(ep_num)
Definition: usbd_regs.h:249
EP_INTERRUPT
#define EP_INTERRUPT
Definition: usbd_regs.h:106
g_free_buf_addr
uint32_t g_free_buf_addr
Definition: usbd_core.c:17
usbd_ep_init
void usbd_ep_init(usbd_core_handle_struct *pudev, void *ep_desc)
endpoint initialization
Definition: usbd_core.c:100
EPRX_STALL
#define EPRX_STALL
Definition: usbd_regs.h:125
USB_EPTYPE_MASK
#define USB_EPTYPE_MASK
Definition: usbd_std.h:73
EPTX_NAK
#define EPTX_NAK
Definition: usbd_regs.h:117
USBD_DTG_TX_CLEAR
#define USBD_DTG_TX_CLEAR(ep_num)
Definition: usbd_regs.h:256
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_timer.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_TIMER_H
14 #define GD32F10X_TIMER_H
15
16 #include "gd32f10x.h"
17
18 /* TIMERx(x=0..13) definitions */
19 #define TIMER0 (TIMER_BASE + 0x00012C00U)
20 #define TIMER1 (TIMER_BASE + 0x00000000U)
21 #define TIMER2 (TIMER_BASE + 0x00000400U)
22 #define TIMER3 (TIMER_BASE + 0x00000800U)
23 #define TIMER4 (TIMER_BASE + 0x00000C00U)
24 #define TIMER5 (TIMER_BASE + 0x00001000U)
25 #define TIMER6 (TIMER_BASE + 0x00001400U)
26 #define TIMER7 (TIMER_BASE + 0x00013400U)
27 #define TIMER8 (TIMER_BASE + 0x00014C00U)
28 #define TIMER9 (TIMER_BASE + 0x00015000U)
29 #define TIMER10 (TIMER_BASE + 0x00015400U)
30 #define TIMER11 (TIMER_BASE + 0x00001800U)
31 #define TIMER12 (TIMER_BASE + 0x00001C00U)
32 #define TIMER13 (TIMER_BASE + 0x00002000U)
33
34 /* registers definitions */
35 #define TIMER_CTL0(timerx) REG32((timerx) + 0x00U)
36 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U)
37 #define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U)
38 #define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU)
39 #define TIMER_INTF(timerx) REG32((timerx) + 0x10U)
40 #define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U)
41 #define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U)
42 #define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU)
43 #define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U)
44 #define TIMER_CNT(timerx) REG32((timerx) + 0x24U)
45 #define TIMER_PSC(timerx) REG32((timerx) + 0x28U)
46 #define TIMER_CAR(timerx) REG32((timerx) + 0x2CU)
47 #define TIMER_CREP(timerx) REG32((timerx) + 0x30U)
48 #define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U)
49 #define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U)
50 #define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU)
51 #define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U)
52 #define TIMER_CCHP(timerx) REG32((timerx) + 0x44U)
53 #define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U)
54 #define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU)
56 /* bits definitions */
57 /* TIMER_CTL0 */
58 #define TIMER_CTL0_CEN BIT(0)
59 #define TIMER_CTL0_UPDIS BIT(1)
60 #define TIMER_CTL0_UPS BIT(2)
61 #define TIMER_CTL0_SPM BIT(3)
62 #define TIMER_CTL0_DIR BIT(4)
63 #define TIMER_CTL0_CAM BITS(5,6)
64 #define TIMER_CTL0_ARSE BIT(7)
65 #define TIMER_CTL0_CKDIV BITS(8,9)
67 /* TIMER_CTL1 */
68 #define TIMER_CTL1_CCSE BIT(0)
69 #define TIMER_CTL1_CCUC BIT(2)
70 #define TIMER_CTL1_DMAS BIT(3)
71 #define TIMER_CTL1_MMC BITS(4,6)
72 #define TIMER_CTL1_TI0S BIT(7)
73 #define TIMER_CTL1_ISO0 BIT(8)
74 #define TIMER_CTL1_ISO0N BIT(9)
75 #define TIMER_CTL1_ISO1 BIT(10)
76 #define TIMER_CTL1_ISO1N BIT(11)
77 #define TIMER_CTL1_ISO2 BIT(12)
78 #define TIMER_CTL1_ISO2N BIT(13)
79 #define TIMER_CTL1_ISO3 BIT(14)
81 /* TIMER_SMCFG */
82 #define TIMER_SMCFG_SMC BITS(0,2)
83 #define TIMER_SMCFG_TRGS BITS(4,6)
84 #define TIMER_SMCFG_MSM BIT(7)
85 #define TIMER_SMCFG_ETFC BITS(8,11)
86 #define TIMER_SMCFG_ETPSC BITS(12,13)
87 #define TIMER_SMCFG_SMC1 BIT(14)
88 #define TIMER_SMCFG_ETP BIT(15)
90 /* TIMER_DMAINTEN */
91 #define TIMER_DMAINTEN_UPIE BIT(0)
92 #define TIMER_DMAINTEN_CH0IE BIT(1)
93 #define TIMER_DMAINTEN_CH1IE BIT(2)
94 #define TIMER_DMAINTEN_CH2IE BIT(3)
95 #define TIMER_DMAINTEN_CH3IE BIT(4)
96 #define TIMER_DMAINTEN_CMTIE BIT(5)
97 #define TIMER_DMAINTEN_TRGIE BIT(6)
98 #define TIMER_DMAINTEN_BRKIE BIT(7)
99 #define TIMER_DMAINTEN_UPDEN BIT(8)
100 #define TIMER_DMAINTEN_CH0DEN BIT(9)
101 #define TIMER_DMAINTEN_CH1DEN BIT(10)
102 #define TIMER_DMAINTEN_CH2DEN BIT(11)
103 #define TIMER_DMAINTEN_CH3DEN BIT(12)
104 #define TIMER_DMAINTEN_CMTDEN BIT(13)
105 #define TIMER_DMAINTEN_TRGDEN BIT(14)
107 /* TIMER_INTF */
108 #define TIMER_INTF_UPIF BIT(0)
109 #define TIMER_INTF_CH0IF BIT(1)
110 #define TIMER_INTF_CH1IF BIT(2)
111 #define TIMER_INTF_CH2IF BIT(3)
112 #define TIMER_INTF_CH3IF BIT(4)
113 #define TIMER_INTF_CMTIF BIT(5)
114 #define TIMER_INTF_TRGIF BIT(6)
115 #define TIMER_INTF_BRKIF BIT(7)
116 #define TIMER_INTF_CH0OF BIT(9)
117 #define TIMER_INTF_CH1OF BIT(10)
118 #define TIMER_INTF_CH2OF BIT(11)
119 #define TIMER_INTF_CH3OF BIT(12)
121 /* TIMER_SWEVG */
122 #define TIMER_SWEVG_UPG BIT(0)
123 #define TIMER_SWEVG_CH0G BIT(1)
124 #define TIMER_SWEVG_CH1G BIT(2)
125 #define TIMER_SWEVG_CH2G BIT(3)
126 #define TIMER_SWEVG_CH3G BIT(4)
127 #define TIMER_SWEVG_CMTG BIT(5)
128 #define TIMER_SWEVG_TRGG BIT(6)
129 #define TIMER_SWEVG_BRKG BIT(7)
131 /* TIMER_CHCTL0 */
132 /* output compare mode */
133 #define TIMER_CHCTL0_CH0MS BITS(0,1)
134 #define TIMER_CHCTL0_CH0COMFEN BIT(2)
135 #define TIMER_CHCTL0_CH0COMSEN BIT(3)
136 #define TIMER_CHCTL0_CH0COMCTL BITS(4,6)
137 #define TIMER_CHCTL0_CH0COMCEN BIT(7)
138 #define TIMER_CHCTL0_CH1MS BITS(8,9)
139 #define TIMER_CHCTL0_CH1COMFEN BIT(10)
140 #define TIMER_CHCTL0_CH1COMSEN BIT(11)
141 #define TIMER_CHCTL0_CH1COMCTL BITS(12,14)
142 #define TIMER_CHCTL0_CH1COMCEN BIT(15)
143 /* input capture mode */
144 #define TIMER_CHCTL0_CH0CAPPSC BITS(2,3)
145 #define TIMER_CHCTL0_CH0CAPFLT BITS(4,7)
146 #define TIMER_CHCTL0_CH1CAPPSC BITS(10,11)
147 #define TIMER_CHCTL0_CH1CAPFLT BITS(12,15)
149 /* TIMER_CHCTL1 */
150 /* output compare mode */
151 #define TIMER_CHCTL1_CH2MS BITS(0,1)
152 #define TIMER_CHCTL1_CH2COMFEN BIT(2)
153 #define TIMER_CHCTL1_CH2COMSEN BIT(3)
154 #define TIMER_CHCTL1_CH2COMCTL BITS(4,6)
155 #define TIMER_CHCTL1_CH2COMCEN BIT(7)
156 #define TIMER_CHCTL1_CH3MS BITS(8,9)
157 #define TIMER_CHCTL1_CH3COMFEN BIT(10)
158 #define TIMER_CHCTL1_CH3COMSEN BIT(11)
159 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14)
160 #define TIMER_CHCTL1_CH3COMCEN BIT(15)
161 /* input capture mode */
162 #define TIMER_CHCTL1_CH2CAPPSC BITS(2,3)
163 #define TIMER_CHCTL1_CH2CAPFLT BITS(4,7)
164 #define TIMER_CHCTL1_CH3CAPPSC BITS(10,11)
165 #define TIMER_CHCTL1_CH3CAPFLT BITS(12,15)
167 /* TIMER_CHCTL2 */
168 #define TIMER_CHCTL2_CH0EN BIT(0)
169 #define TIMER_CHCTL2_CH0P BIT(1)
170 #define TIMER_CHCTL2_CH0NEN BIT(2)
171 #define TIMER_CHCTL2_CH0NP BIT(3)
172 #define TIMER_CHCTL2_CH1EN BIT(4)
173 #define TIMER_CHCTL2_CH1P BIT(5)
174 #define TIMER_CHCTL2_CH1NEN BIT(6)
175 #define TIMER_CHCTL2_CH1NP BIT(7)
176 #define TIMER_CHCTL2_CH2EN BIT(8)
177 #define TIMER_CHCTL2_CH2P BIT(9)
178 #define TIMER_CHCTL2_CH2NEN BIT(10)
179 #define TIMER_CHCTL2_CH2NP BIT(11)
180 #define TIMER_CHCTL2_CH3EN BIT(12)
181 #define TIMER_CHCTL2_CH3P BIT(13)
183 /* TIMER_CNT */
184 #define TIMER_CNT_CNT BITS(0,15)
186 /* TIMER_PSC */
187 #define TIMER_PSC_PSC BITS(0,15)
189 /* TIMER_CAR */
190 #define TIMER_CAR_CARL BITS(0,15)
192 /* TIMER_CREP */
193 #define TIMER_CREP_CREP BITS(0,7)
195 /* TIMER_CH0CV */
196 #define TIMER_CH0CV_CH0VAL BITS(0,15)
198 /* TIMER_CH1CV */
199 #define TIMER_CH1CV_CH1VAL BITS(0,15)
201 /* TIMER_CH2CV */
202 #define TIMER_CH2CV_CH2VAL BITS(0,15)
204 /* TIMER_CH3CV */
205 #define TIMER_CH3CV_CH3VAL BITS(0,15)
207 /* TIMER_CCHP */
208 #define TIMER_CCHP_DTCFG BITS(0,7)
209 #define TIMER_CCHP_PROT BITS(8,9)
210 #define TIMER_CCHP_IOS BIT(10)
211 #define TIMER_CCHP_ROS BIT(11)
212 #define TIMER_CCHP_BRKEN BIT(12)
213 #define TIMER_CCHP_BRKP BIT(13)
214 #define TIMER_CCHP_OAEN BIT(14)
215 #define TIMER_CCHP_POEN BIT(15)
217 /* TIMER_DMACFG */
218 #define TIMER_DMACFG_DMATA BITS(0,4)
219 #define TIMER_DMACFG_DMATC BITS(8,12)
221 /* TIMER_DMATB */
222 #define TIMER_DMATB_DMATB BITS(0,15)
224 /* constants definitions */
225 /* TIMER init parameter struct definitions*/
226 typedef struct
227 {
228 uint16_t prescaler;
229 uint16_t alignedmode;
230 uint16_t counterdirection;
231 uint32_t period;
232 uint16_t clockdivision;
233 uint8_t repetitioncounter;
234 }timer_parameter_struct;
235
236 /* break parameter struct definitions*/
237 typedef struct
238 {
239 uint16_t runoffstate;
240 uint32_t ideloffstate;
241 uint16_t deadtime;
242 uint16_t breakpolarity;
243 uint16_t outputautostate;
244 uint16_t protectmode;
245 uint16_t breakstate;
246 }timer_break_parameter_struct;
247
248 /* channel output parameter struct definitions */
249 typedef struct
250 {
251 uint32_t outputstate;
252 uint16_t outputnstate;
253 uint16_t ocpolarity;
254 uint16_t ocnpolarity;
255 uint16_t ocidlestate;
256 uint16_t ocnidlestate;
257 }timer_oc_parameter_struct;
258
259 /* channel input parameter struct definitions */
260 typedef struct
261 {
262 uint16_t icpolarity;
263 uint16_t icselection;
264 uint16_t icprescaler;
265 uint16_t icfilter;
266 }timer_ic_parameter_struct;
267
268 /* TIMER interrupt enable or disable */
269 #define TIMER_INT_UP TIMER_DMAINTEN_UPIE
270 #define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE
271 #define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE
272 #define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE
273 #define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE
274 #define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE
275 #define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE
276 #define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE
278 /* TIMER flag */
279 #define TIMER_FLAG_UP TIMER_INTF_UPIF
280 #define TIMER_FLAG_CH0 TIMER_INTF_CH0IF
281 #define TIMER_FLAG_CH1 TIMER_INTF_CH1IF
282 #define TIMER_FLAG_CH2 TIMER_INTF_CH2IF
283 #define TIMER_FLAG_CH3 TIMER_INTF_CH3IF
284 #define TIMER_FLAG_CMT TIMER_INTF_CMTIF
285 #define TIMER_FLAG_TRG TIMER_INTF_TRGIF
286 #define TIMER_FLAG_BRK TIMER_INTF_BRKIF
287 #define TIMER_FLAG_CH0O TIMER_INTF_CH0OF
288 #define TIMER_FLAG_CH1O TIMER_INTF_CH1OF
289 #define TIMER_FLAG_CH2O TIMER_INTF_CH2OF
290 #define TIMER_FLAG_CH3O TIMER_INTF_CH3OF
292 /* TIMER interrupt flag */
293 #define TIMER_INT_FLAG_UP TIMER_INTF_UPIF
294 #define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF
295 #define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF
296 #define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF
297 #define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF
298 #define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF
299 #define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF
300 #define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF
302 /* TIMER DMA source enable */
303 #define TIMER_DMA_UPD ((uint16_t)0x0100U)
304 #define TIMER_DMA_CH0D ((uint16_t)0x0200U)
305 #define TIMER_DMA_CH1D ((uint16_t)0x0400U)
306 #define TIMER_DMA_CH2D ((uint16_t)0x0800U)
307 #define TIMER_DMA_CH3D ((uint16_t)0x1000U)
308 #define TIMER_DMA_CMTD ((uint16_t)0x2000U)
309 #define TIMER_DMA_TRGD ((uint16_t)0x4000U)
311 /* channel DMA request source selection */
312 #define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U)
313 #define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U)
315 /* DMA access base address */
316 #define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
317 #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0)
318 #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1)
319 #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2)
320 #define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3)
321 #define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4)
322 #define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5)
323 #define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6)
324 #define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7)
325 #define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8)
326 #define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9)
327 #define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10)
328 #define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11)
329 #define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12)
330 #define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13)
331 #define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14)
332 #define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15)
333 #define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16)
334 #define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17)
335 #define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18)
336 #define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19)
338 /* DMA access burst length */
339 #define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
340 #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0)
341 #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1)
342 #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2)
343 #define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3)
344 #define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4)
345 #define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5)
346 #define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6)
347 #define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7)
348 #define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8)
349 #define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9)
350 #define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10)
351 #define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11)
352 #define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12)
353 #define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13)
354 #define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14)
355 #define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15)
356 #define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16)
357 #define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17)
359 /* TIMER software event generation source */
360 #define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U)
361 #define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U)
362 #define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U)
363 #define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U)
364 #define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U)
365 #define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U)
366 #define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U)
367 #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U)
369 /* center-aligned mode selection */
370 #define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
371 #define TIMER_COUNTER_EDGE CTL0_CAM(0)
372 #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1)
373 #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2)
374 #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3)
376 /* TIMER prescaler reload mode */
377 #define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U)
378 #define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U)
380 /* count direction */
381 #define TIMER_COUNTER_UP ((uint16_t)0x0000U)
382 #define TIMER_COUNTER_DOWN ((uint16_t)0x0010U)
384 /* specify division ratio between TIMER clock and dead-time and sampling clock */
385 #define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
386 #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0)
387 #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1)
388 #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2)
390 /* single pulse mode */
391 #define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U)
392 #define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U)
394 /* update source */
395 #define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U)
396 #define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U)
398 /* run mode off-state configure */
399 #define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U)
400 #define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U)
402 /* idle mode off-state configure */
403 #define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U)
404 #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U)
406 /* break input polarity */
407 #define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U)
408 #define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U)
410 /* output automatic enable */
411 #define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U)
412 #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U)
414 /* complementary register protect control */
415 #define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
416 #define TIMER_CCHP_PROT_OFF CCHP_PROT(0)
417 #define TIMER_CCHP_PROT_0 CCHP_PROT(1)
418 #define TIMER_CCHP_PROT_1 CCHP_PROT(2)
419 #define TIMER_CCHP_PROT_2 CCHP_PROT(3)
421 /* break input enable */
422 #define TIMER_BREAK_ENABLE ((uint16_t)0x1000U)
423 #define TIMER_BREAK_DISABLE ((uint16_t)0x0000U)
425 /* TIMER channel y(y=0,1,2,3) */
426 #define TIMER_CH_0 ((uint16_t)0x0000U)
427 #define TIMER_CH_1 ((uint16_t)0x0001U)
428 #define TIMER_CH_2 ((uint16_t)0x0002U)
429 #define TIMER_CH_3 ((uint16_t)0x0003U)
431 /* channel enable state */
432 #define TIMER_CCX_ENABLE ((uint32_t)0x00000001U)
433 #define TIMER_CCX_DISABLE ((uint32_t)0x00000000U)
435 /* channel complementary output enable state */
436 #define TIMER_CCXN_ENABLE ((uint16_t)0x0004U)
437 #define TIMER_CCXN_DISABLE ((uint16_t)0x0000U)
439 /* channel output polarity */
440 #define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U)
441 #define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U)
443 /* channel complementary output polarity */
444 #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U)
445 #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U)
447 /* idle state of channel output */
448 #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100)
449 #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000)
451 /* idle state of channel complementary output */
452 #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U)
453 #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U)
455 /* channel output compare mode */
456 #define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U)
457 #define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U)
458 #define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U)
459 #define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U)
460 #define TIMER_OC_MODE_LOW ((uint16_t)0x0040U)
461 #define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U)
462 #define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U)
463 #define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U)
465 /* channel output compare shadow enable */
466 #define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U)
467 #define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U)
469 /* channel output compare fast enable */
470 #define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004)
471 #define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000)
473 /* channel output compare clear enable */
474 #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U)
475 #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U)
477 /* channel control shadow register update control */
478 #define TIMER_UPDATECTL_CCU ((uint8_t)0x00U)
479 #define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U)
481 /* channel input capture polarity */
482 #define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U)
483 #define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U)
484 #define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU)
486 /* timer input capture selection */
487 #define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U)
488 #define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U)
489 #define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U)
491 /* channel input capture prescaler */
492 #define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U)
493 #define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U)
494 #define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U)
495 #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU)
497 /* trigger selection */
498 #define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
499 #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0)
500 #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1)
501 #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2)
502 #define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3)
503 #define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4)
504 #define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5)
505 #define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6)
506 #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7)
508 /* master mode control */
509 #define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
510 #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0)
511 #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1)
512 #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2)
513 #define TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3)
514 #define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4)
515 #define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5)
516 #define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6)
517 #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7)
519 /* slave mode control */
520 #define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
521 #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0)
522 #define TIMER_ENCODER_MODE0 SMCFG_SMC(1)
523 #define TIMER_ENCODER_MODE1 SMCFG_SMC(2)
524 #define TIMER_ENCODER_MODE2 SMCFG_SMC(3)
525 #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4)
526 #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5)
527 #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6)
528 #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7)
530 /* master slave mode selection */
531 #define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U)
532 #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U)
534 /* external trigger prescaler */
535 #define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
536 #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0)
537 #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1)
538 #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2)
539 #define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3)
541 /* external trigger polarity */
542 #define TIMER_ETP_FALLING TIMER_SMCFG_ETP
543 #define TIMER_ETP_RISING ((uint32_t)0x00000000U)
545 /* channel 0 trigger input selection */
546 #define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U)
547 #define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U)
549 /* function declarations */
550 /* TIMER timebase */
551 /* deinit a TIMER */
552 void timer_deinit(uint32_t timer_periph);
553 /* initialize TIMER counter */
554 void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
555 /* enable a TIMER */
556 void timer_enable(uint32_t timer_periph);
557 /* disable a TIMER */
558 void timer_disable(uint32_t timer_periph);
559 /* enable the auto reload shadow function */
560 void timer_auto_reload_shadow_enable(uint32_t timer_periph);
561 /* disable the auto reload shadow function */
562 void timer_auto_reload_shadow_disable(uint32_t timer_periph);
563 /* enable the update event */
564 void timer_update_event_enable(uint32_t timer_periph);
565 /* disable the update event */
566 void timer_update_event_disable(uint32_t timer_periph);
567 /* set TIMER counter alignment mode */
568 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
569 /* set TIMER counter up direction */
570 void timer_counter_up_direction(uint32_t timer_periph);
571 /* set TIMER counter down direction */
572 void timer_counter_down_direction(uint32_t timer_periph);
573 /* configure TIMER prescaler */
574 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload);
575 /* configure TIMER repetition register value */
576 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition);
577 /* configure TIMER autoreload register value */
578 void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload);
579 /* configure TIMER counter register value */
580 void timer_counter_value_config(uint32_t timer_periph, uint32_t counter);
581 /* read TIMER counter value */
582 uint32_t timer_counter_read(uint32_t timer_periph);
583 /* read TIMER prescaler value */
584 uint16_t timer_prescaler_read(uint32_t timer_periph);
585 /* configure TIMER single pulse mode */
586 void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode);
587 /* configure TIMER update source */
588 void timer_update_source_config(uint32_t timer_periph, uint8_t update);
589
590 /* TIMER interrupt and flag */
591 /* enable the TIMER interrupt */
592 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
593 /* disable the TIMER interrupt */
594 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
595 /* get timer interrupt flag */
596 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
597 /* clear TIMER interrupt flag */
598 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
599 /* get TIMER flags */
600 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
601 /* clear TIMER flags */
602 void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
603
604 /* timer DMA and event */
605 /* enable the TIMER DMA */
606 void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
607 /* disable the TIMER DMA */
608 void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
609 /* channel DMA request source selection */
610 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request);
611 /* configure the TIMER DMA transfer */
612 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth);
613 /* software generate events */
614 void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
615
616 /* timer channel complementary protection */
617 /* configure TIMER break function */
618 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
619 /* enable TIMER break function */
620 void timer_break_enable(uint32_t timer_periph);
621 /* disable TIMER break function */
622 void timer_break_disable(uint32_t timer_periph);
623 /* enable TIMER output automatic function */
624 void timer_automatic_output_enable(uint32_t timer_periph);
625 /* disable TIMER output automatic function */
626 void timer_automatic_output_disable(uint32_t timer_periph);
627 /* configure TIMER primary output function */
628 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
629 /* channel capture/compare control shadow register enable */
630 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
631 /* configure TIMER channel control shadow register update control */
632 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl);
633
634 /* TIMER channel output */
635 /* configure TIMER channel output function */
636 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara);
637 /* configure TIMER channel output compare mode */
638 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode);
639 /* configure TIMER channel output pulse value */
640 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse);
641 /* configure TIMER channel output shadow function */
642 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
643 /* configure TIMER channel output fast function */
644 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
645 /* configure TIMER channel output clear function */
646 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear);
647 /* configure TIMER channel output polarity */
648 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
649 /* configure TIMER channel complementary output polarity */
650 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
651 /* configure TIMER channel enable state */
652 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
653 /* configure TIMER channel complementary output enable state */
654 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
655
656 /* TIMER channel input */
657 /* configure TIMER input capture parameter */
658 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
659 /* configure TIMER channel input capture prescaler value */
660 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
661 /* read TIMER channel capture compare register value */
662 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
663 /* configure TIMER input pwm capture function */
664 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
665 /* configure TIMER hall sensor mode */
666 void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode);
667
668 /* TIMER master and slave */
669 /* select TIMER input trigger source */
670 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
671 /* select TIMER master mode output trigger source */
672 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
673 /* select TIMER slave mode */
674 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode);
675 /* configure TIMER master slave mode */
676 void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave);
677 /* configure TIMER external trigger input */
678 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter);
679 /* configure TIMER quadrature decoder mode */
680 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
681 /* configure TIMER internal clock mode */
682 void timer_internal_clock_config(uint32_t timer_periph);
683 /* configure TIMER the internal trigger as external clock input */
684 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
685 /* configure TIMER the external trigger as external clock input */
686 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter);
687 /* configure TIMER the external clock mode 0 */
688 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter);
689 /* configure TIMER the external clock mode 1 */
690 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter);
691 /* disable TIMER the external clock mode 1 */
692 void timer_external_clock_mode1_disable(uint32_t timer_periph);
693
694 #endif /* GD32F10X_TIMER_H */
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f10x_timer.c:1359
timer_break_config
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara)
configure TIMER break function
Definition: gd32f10x_timer.c:634
timer_auto_reload_shadow_disable
void timer_auto_reload_shadow_disable(uint32_t timer_periph)
disable the auto reload shadow function
Definition: gd32f10x_timer.c:185
timer_channel_complementary_output_state_config
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
configure TIMER channel complementary output enable state
Definition: gd32f10x_timer.c:1217
timer_autoreload_value_config
void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
configure TIMER autoreload register value
Definition: gd32f10x_timer.c:289
timer_counter_alignment
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
set TIMER counter alignment mode
Definition: gd32f10x_timer.c:223
timer_break_parameter_struct::deadtime
uint16_t deadtime
Definition: gd32f10x_timer.h:241
timer_break_enable
void timer_break_enable(uint32_t timer_periph)
enable TIMER break function
Definition: gd32f10x_timer.c:651
timer_enable
void timer_enable(uint32_t timer_periph)
enable a TIMER
Definition: gd32f10x_timer.c:152
timer_dma_enable
void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
enable the TIMER DMA
Definition: gd32f10x_timer.c:522
timer_channel_control_shadow_config
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
channel capture/compare control shadow register enable
Definition: gd32f10x_timer.c:712
timer_flag_clear
void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
clear TIMER flags
Definition: gd32f10x_timer.c:503
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f10x_timer.h:263
timer_automatic_output_disable
void timer_automatic_output_disable(uint32_t timer_periph)
disable TIMER output automatic function
Definition: gd32f10x_timer.c:684
timer_oc_parameter_struct::ocnidlestate
uint16_t ocnidlestate
Definition: gd32f10x_timer.h:256
timer_prescaler_config
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
configure TIMER prescaler
Definition: gd32f10x_timer.c:261
timer_channel_output_mode_config
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
configure TIMER channel output compare mode
Definition: gd32f10x_timer.c:898
timer_automatic_output_enable
void timer_automatic_output_enable(uint32_t timer_periph)
enable TIMER output automatic function
Definition: gd32f10x_timer.c:673
timer_dma_disable
void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
disable the TIMER DMA
Definition: gd32f10x_timer.c:541
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f10x_timer.c:1565
timer_channel_dma_request_source_select
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
channel DMA request source selection
Definition: gd32f10x_timer.c:555
timer_break_parameter_struct::ideloffstate
uint32_t ideloffstate
Definition: gd32f10x_timer.h:240
timer_update_source_config
void timer_update_source_config(uint32_t timer_periph, uint8_t update)
configure TIMER update source
Definition: gd32f10x_timer.c:360
timer_prescaler_read
uint16_t timer_prescaler_read(uint32_t timer_periph)
read TIMER prescaler value
Definition: gd32f10x_timer.c:325
timer_init
void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara)
initialize TIMER counter
Definition: gd32f10x_timer.c:114
timer_slave_mode_select
void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
select TIMER slave mode
Definition: gd32f10x_timer.c:1608
timer_channel_output_config
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
configure TIMER channel output function
Definition: gd32f10x_timer.c:758
timer_channel_output_state_config
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
configure TIMER channel enable state
Definition: gd32f10x_timer.c:1176
timer_master_slave_mode_config
void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave)
configure TIMER master slave mode
Definition: gd32f10x_timer.c:1624
timer_channel_output_polarity_config
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
configure TIMER channel output polarity
Definition: gd32f10x_timer.c:1098
timer_oc_parameter_struct::ocpolarity
uint16_t ocpolarity
Definition: gd32f10x_timer.h:253
timer_disable
void timer_disable(uint32_t timer_periph)
disable a TIMER
Definition: gd32f10x_timer.c:163
timer_update_event_disable
void timer_update_event_disable(uint32_t timer_periph)
disable the update event
Definition: gd32f10x_timer.c:207
timer_input_pwm_capture_config
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
configure TIMER input pwm capture function
Definition: gd32f10x_timer.c:1435
timer_channel_output_fast_config
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
configure TIMER channel output fast function
Definition: gd32f10x_timer.c:1014
timer_interrupt_flag_get
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
get timer interrupt flag
Definition: gd32f10x_timer.c:425
timer_event_software_generate
void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
software generate events
Definition: gd32f10x_timer.c:615
timer_update_event_enable
void timer_update_event_enable(uint32_t timer_periph)
enable the update event
Definition: gd32f10x_timer.c:196
timer_external_clock_mode1_disable
void timer_external_clock_mode1_disable(uint32_t timer_periph)
disable TIMER the external clock mode1
Definition: gd32f10x_timer.c:1833
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f10x_timer.h:264
timer_primary_output_config
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
configure TIMER primary output function
Definition: gd32f10x_timer.c:696
timer_external_clock_mode0_config
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode0
Definition: gd32f10x_timer.c:1791
timer_deinit
void timer_deinit(uint32_t timer_periph)
deinit a TIMER
Definition: gd32f10x_timer.c:21
timer_channel_output_clear_config
void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
configure TIMER channel output clear function
Definition: gd32f10x_timer.c:1056
timer_interrupt_enable
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
enable the TIMER interrupt
Definition: gd32f10x_timer.c:385
timer_single_pulse_mode_config
void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode)
configure TIMER single pulse mode
Definition: gd32f10x_timer.c:341
timer_parameter_struct::clockdivision
uint16_t clockdivision
Definition: gd32f10x_timer.h:232
timer_input_capture_config
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
configure TIMER input capture parameter
Definition: gd32f10x_timer.c:1256
timer_break_parameter_struct::outputautostate
uint16_t outputautostate
Definition: gd32f10x_timer.h:243
timer_channel_complementary_output_polarity_config
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
configure TIMER channel complementary output polarity
Definition: gd32f10x_timer.c:1139
timer_interrupt_flag_clear
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
clear TIMER interrupt flag
Definition: gd32f10x_timer.c:451
timer_counter_down_direction
void timer_counter_down_direction(uint32_t timer_periph)
set TIMER counter down direction
Definition: gd32f10x_timer.c:246
timer_external_trigger_as_external_clock_config
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
configure TIMER the external trigger as external clock input
Definition: gd32f10x_timer.c:1730
timer_auto_reload_shadow_enable
void timer_auto_reload_shadow_enable(uint32_t timer_periph)
enable the auto reload shadow function
Definition: gd32f10x_timer.c:174
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f10x_timer.h:262
timer_break_parameter_struct
Definition: gd32f10x_timer.h:237
timer_counter_up_direction
void timer_counter_up_direction(uint32_t timer_periph)
set TIMER counter up direction
Definition: gd32f10x_timer.c:235
timer_master_output_trigger_source_select
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
select TIMER master mode output trigger source
Definition: gd32f10x_timer.c:1586
timer_break_parameter_struct::runoffstate
uint16_t runoffstate
Definition: gd32f10x_timer.h:239
timer_channel_output_shadow_config
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
configure TIMER channel output shadow function
Definition: gd32f10x_timer.c:972
timer_oc_parameter_struct::outputstate
uint32_t outputstate
Definition: gd32f10x_timer.h:251
timer_oc_parameter_struct::ocidlestate
uint16_t ocidlestate
Definition: gd32f10x_timer.h:255
timer_channel_output_pulse_value_config
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
configure TIMER channel output pulse value
Definition: gd32f10x_timer.c:938
timer_break_parameter_struct::breakpolarity
uint16_t breakpolarity
Definition: gd32f10x_timer.h:242
timer_parameter_struct::repetitioncounter
uint8_t repetitioncounter
Definition: gd32f10x_timer.h:233
timer_break_parameter_struct::breakstate
uint16_t breakstate
Definition: gd32f10x_timer.h:245
timer_internal_trigger_as_external_clock_config
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
configure TIMER the internal trigger as external clock input
Definition: gd32f10x_timer.c:1709
timer_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f10x_timer.h:228
timer_oc_parameter_struct::ocnpolarity
uint16_t ocnpolarity
Definition: gd32f10x_timer.h:254
timer_parameter_struct
Definition: gd32f10x_timer.h:226
timer_repetition_value_config
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
configure TIMER repetition register value
Definition: gd32f10x_timer.c:277
timer_counter_value_config
void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
configure TIMER counter register value
Definition: gd32f10x_timer.c:301
timer_external_clock_mode1_config
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode1
Definition: gd32f10x_timer.c:1818
timer_channel_capture_value_register_read
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
read TIMER channel capture compare register value
Definition: gd32f10x_timer.c:1398
timer_flag_get
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
get TIMER flags
Definition: gd32f10x_timer.c:475
timer_counter_read
uint32_t timer_counter_read(uint32_t timer_periph)
read TIMER counter value
Definition: gd32f10x_timer.c:312
timer_channel_control_shadow_update_config
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
configure TIMER channel control shadow register update control
Definition: gd32f10x_timer.c:730
timer_parameter_struct::period
uint32_t period
Definition: gd32f10x_timer.h:231
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f10x_timer.c:1649
timer_dma_transfer_config
void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
configure the TIMER DMA transfer
Definition: gd32f10x_timer.c:594
timer_oc_parameter_struct
Definition: gd32f10x_timer.h:249
timer_break_parameter_struct::protectmode
uint16_t protectmode
Definition: gd32f10x_timer.h:244
timer_internal_clock_config
void timer_internal_clock_config(uint32_t timer_periph)
configure TIMER internal clock mode
Definition: gd32f10x_timer.c:1693
timer_break_disable
void timer_break_disable(uint32_t timer_periph)
disable TIMER break function
Definition: gd32f10x_timer.c:662
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f10x_timer.h:265
timer_hall_mode_config
void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode)
configure TIMER hall sensor mode
Definition: gd32f10x_timer.c:1540
timer_oc_parameter_struct::outputnstate
uint16_t outputnstate
Definition: gd32f10x_timer.h:252
timer_interrupt_disable
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
disable the TIMER interrupt
Definition: gd32f10x_timer.c:405
timer_quadrature_decoder_mode_config
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
configure TIMER quadrature decoder mode
Definition: gd32f10x_timer.c:1673
timer_ic_parameter_struct
Definition: gd32f10x_timer.h:260
timer_parameter_struct::alignedmode
uint16_t alignedmode
Definition: gd32f10x_timer.h:229
timer_parameter_struct::counterdirection
uint16_t counterdirection
Definition: gd32f10x_timer.h:230
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_wwdgt.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_wwdgt.h"
14
15 /* write value to WWDGT_CTL_CNT bit field */
16 #define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
17 /* write value to WWDGT_CFG_WIN bit field */
18 #define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
19
26 void wwdgt_deinit(void)
27 {
28 rcu_periph_reset_enable(RCU_WWDGTRST);
29 rcu_periph_reset_disable(RCU_WWDGTRST);
30 }
31
38 void wwdgt_counter_update(uint16_t counter_value)
39 {
40 uint32_t reg = 0U;
41
42 reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
43 reg |= CTL_CNT(counter_value);
44
45 WWDGT_CTL = reg;
46 }
47
54 void wwdgt_enable(void)
55 {
56 WWDGT_CTL |= WWDGT_CTL_WDGTEN;
57 }
58
71 void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
72 {
73 uint32_t reg_cfg = 0U, reg_ctl = 0U;
74
75 /* clear WIN and PSC bits, clear CNT bit */
76 reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
77 reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
78
79 /* configure WIN and PSC bits, configure CNT bit */
80 reg_cfg |= CFG_WIN(window);
81 reg_cfg |= prescaler;
82 reg_ctl |= CTL_CNT(counter);
83
84 WWDGT_CTL = reg_ctl;
85 WWDGT_CFG = reg_cfg;
86 }
87
94 void wwdgt_interrupt_enable(void)
95 {
96 WWDGT_CFG |= WWDGT_CFG_EWIE;
97 }
98
105 FlagStatus wwdgt_flag_get(void)
106 {
107 if(WWDGT_STAT & WWDGT_STAT_EWIF){
108 return SET;
109 }
110
111 return RESET;
112 }
113
120 void wwdgt_flag_clear(void)
121 {
122 WWDGT_STAT &= (~WWDGT_STAT_EWIF);
123 }
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f10x_wwdgt.h:37
wwdgt_deinit
void wwdgt_deinit(void)
reset the window watchdog timer configuration
Definition: gd32f10x_wwdgt.c:26
WWDGT_CFG_EWIE
#define WWDGT_CFG_EWIE
Definition: gd32f10x_wwdgt.h:34
gd32f10x_wwdgt.h
definitions for the WWDGT
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f10x_wwdgt.h:24
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f10x_wwdgt.h:28
wwdgt_interrupt_enable
void wwdgt_interrupt_enable(void)
enable early wakeup interrupt of WWDGT
Definition: gd32f10x_wwdgt.c:94
CFG_WIN
#define CFG_WIN(regval)
Definition: gd32f10x_wwdgt.c:18
wwdgt_enable
void wwdgt_enable(void)
start the window watchdog timer counter
Definition: gd32f10x_wwdgt.c:54
RCU_WWDGTRST
Definition: gd32f10x_rcu.h:456
WWDGT_CTL_WDGTEN
#define WWDGT_CTL_WDGTEN
Definition: gd32f10x_wwdgt.h:29
wwdgt_flag_get
FlagStatus wwdgt_flag_get(void)
check early wakeup interrupt state of WWDGT
Definition: gd32f10x_wwdgt.c:105
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f10x_wwdgt.h:23
WWDGT_CFG_PSC
#define WWDGT_CFG_PSC
Definition: gd32f10x_wwdgt.h:33
wwdgt_counter_update
void wwdgt_counter_update(uint16_t counter_value)
configure the window watchdog timer counter value
Definition: gd32f10x_wwdgt.c:38
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f10x_wwdgt.c:16
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f10x_wwdgt.h:22
WWDGT_CFG_WIN
#define WWDGT_CFG_WIN
Definition: gd32f10x_wwdgt.h:32
wwdgt_config
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
configure counter value, window value, and prescaler divider value
Definition: gd32f10x_wwdgt.c:71
wwdgt_flag_clear
void wwdgt_flag_clear(void)
clear early wakeup interrupt state of WWDGT
Definition: gd32f10x_wwdgt.c:120
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_int.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
usbd_int.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBD_INT_H
14 #define USBD_INT_H
15
16 #include "usbd_core.h"
17 #include "usbd_std.h"
18 #include "usbd_pwr.h"
19
20 extern usbd_core_handle_struct usb_device_dev;
21
22 typedef struct
23 {
24 uint8_t (*SOF) (usbd_core_handle_struct *pudev);
25 }usbd_int_cb_struct;
26
27 extern usbd_int_cb_struct *usbd_int_fops;
28
29 /* function declarations */
30 /* USB device interrupt service routine */
31 void usbd_isr (void);
32
33 #endif /* USBD_INT_H */
usbd_int_fops
usbd_int_cb_struct * usbd_int_fops
usbd_pwr.h
USB device power management functions prototype.
usbd_std.h
usbd_core.h
usbd_core_handle_struct
Definition: usbd_core.h:125
usbd_isr
void usbd_isr(void)
USB interrupt events service routine.
Definition: usbd_int.c:39
usbd_int_cb_struct
Definition: usbd_int.h:22
usb_device_dev
usbd_core_handle_struct usb_device_dev
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_int.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
usbh_int.c
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1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usb_core.h"
14 #include "usb_defines.h"
15 #include "usbh_int.h"
16
17 static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev);
18 static uint32_t usbh_intf_port (usb_core_handle_struct *pudev);
19 static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev);
20 static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num);
21 static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num);
22 static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev);
23 static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev);
24 static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev);
25 static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev);
26 static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev);
27
34 uint32_t usbh_isr (usb_core_handle_struct *pudev)
35 {
36 uint32_t retval = 0U;
37 __IO uint32_t int_flag = 0U;
38
39 /* check if host mode */
40 if (USB_CURRENT_MODE_GET() == HOST_MODE) {
41 USB_CORE_INTR_READ(int_flag);
42
43 if (!int_flag) {
44 return 0U;
45 }
46
47 /* start of frame interrupt handle */
48 if (int_flag & GINTF_SOF) {
49 retval |= usbh_intf_sof (pudev);
50 }
51
52 /* Rx FIFO non-empty interrupt handle */
53 if (int_flag & GINTF_RXFNEIF) {
54 retval |= usbh_intf_rxfifo_noempty (pudev);
55 }
56
57 /* Non-Periodic Tx FIFO empty interrupt hanlde */
58 if (int_flag & GINTF_NPTXFEIF) {
59 retval |= usbh_intf_nptxfifo_empty (pudev);
60 }
61
62 /* periodic Tx FIFO empty interrupt handle */
63 if (int_flag & GINTF_PTXFEIF) {
64 retval |= usbh_intf_ptxfifo_empty (pudev);
65 }
66
67 /* host channels interrupt handle */
68 if (int_flag & GINTF_HCIF) {
69 retval |= usbh_intf_hc (pudev);
70 }
71
72 /* host port interrupt handle */
73 if (int_flag & GINTF_HPIF) {
74 retval |= usbh_intf_port (pudev);
75 }
76
77 /* disconnect interrupt handle */
78 if (int_flag & GINTF_DISCIF) {
79 retval |= usbh_intf_disconnect (pudev);
80 }
81
82 /* isochronous IN transfer not complete interrupt handle */
83 if (int_flag & GINTF_ISOONCIF) {
84 retval |= usbh_intf_iso_incomplete_xfer (pudev);
85 }
86 }
87
88 return retval;
89 }
90
97 static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev)
98 {
99 usbh_hcd_int_fops->sof(pudev);
100
101 /* clear interrupt */
102 USB_GINTF = GINTF_SOF;
103
104 return 1U;
105 }
106
113 static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev)
114 {
115 uint8_t i = 0U;
116 uint32_t retval = 0U;
117
118 for (i = 0U; i < pudev->cfg.host_channel_num; i++) {
119 if ((USB_HACHINT & HACHINT_HACHINT) & ((uint32_t)1U << i)) {
120 if ((USB_HCHxCTL((uint16_t)i) & HCHCTL_EPDIR) >> 15U) {
121 retval |= usbh_intf_hc_in (pudev, i);
122 } else {
123 retval |= usbh_intf_hc_out (pudev, i);
124 }
125 }
126 }
127
128 return retval;
129 }
130
137 static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev)
138 {
139 usbh_hcd_int_fops->device_disconnected(pudev);
140
141 /* clear interrupt */
142 USB_GINTF = GINTF_DISCIF;
143
144 return 1U;
145 }
146
153 static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev)
154 {
155 uint8_t channel_num = 0U;
156 uint32_t dword_len = 0U, len = 0U;
157 usb_hostchannel_struct *puhc;
158
159 channel_num = (uint8_t)((USB_HNPTFQSTAT & HNPTFQSTAT_CNUM) >> 27U);
160 puhc = &pudev->host.host_channel[channel_num];
161 dword_len = (puhc->xfer_len + 3U) / 4U;
162
163 while (((USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) > dword_len) && (0U != puhc->xfer_len)) {
164 len = (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) * 4U;
165
166 if (len > puhc->xfer_len) {
167 /* last packet */
168 len = (uint16_t)puhc->xfer_len;
169
170 USB_GINTEN &= ~GINTF_NPTXFEIF;
171
172 }
173
174 dword_len = (puhc->xfer_len + 3U) / 4U;
175 usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len);
176
177 puhc->xfer_buff += len;
178 puhc->xfer_len -= len;
179 puhc->xfer_count += len;
180 }
181
182 return 1U;
183 }
184
191 static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev)
192 {
193 uint8_t channel_num = 0U;
194 uint32_t dword_len = 0U, len = 0U;
195 usb_hostchannel_struct *puhc;
196
197 channel_num = (uint8_t)((USB_HPTFQSTAT & HPTFQSTAT_CNUM) >> 27U);
198 puhc = &pudev->host.host_channel[channel_num];
199 dword_len = (puhc->xfer_len + 3U) / 4U;
200
201 while (((USB_HPTFQSTAT & HPTFQSTAT_PTXFS) > dword_len) && (0U != puhc->xfer_len)) {
202 len = (USB_HPTFQSTAT & HPTFQSTAT_PTXFS) * 4U;
203
204 if (len > puhc->xfer_len) {
205 len = puhc->xfer_len;
206
207 /* last packet */
208 USB_GINTEN &= ~GINTF_PTXFEIF;
209 }
210
211 dword_len = (puhc->xfer_len + 3U) / 4U;
212 usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len);
213
214 puhc->xfer_buff += len;
215 puhc->xfer_len -= len;
216 puhc->xfer_count += len;
217 }
218
219 return 1U;
220 }
221
228 static uint32_t usbh_intf_port (usb_core_handle_struct *pudev)
229 {
230 uint8_t port_speed = 0U;
231 uint8_t port_reset = 0U;
232 uint32_t retval = 0U;
233 __IO uint32_t hostportdup = USB_HPCS;
234
235 /* clear the interrupt bits in gintsts */
236 hostportdup &= ~HPCS_PE;
237 hostportdup &= ~HPCS_PCD;
238 hostportdup &= ~HPCS_PEDC;
239
240 /* port connect detected */
241 if (USB_HPCS & HPCS_PCD) {
242 hostportdup |= HPCS_PCD;
243 usbh_hcd_int_fops->device_connected(pudev);
244 retval |= 1U;
245 }
246
247 /* port enable changed */
248 if (USB_HPCS & HPCS_PEDC) {
249 hostportdup |= HPCS_PEDC;
250
251 if (USB_HPCS & HPCS_PE) {
252 port_speed = (uint8_t)((USB_HPCS & HPCS_PS) >> 17U);
253
254 if (HPRT_PRTSPD_LOW_SPEED == port_speed) {
255 USB_HFT = 6000U;
256
257 if (HCTLR_6_MHZ != (USB_HCTL & HCTL_CLKSEL)) {
258 if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) {
259 USB_FSLSCLOCK_INIT(HCTLR_6_MHZ);
260 }
261 port_reset = 1U;
262 }
263 } else if(HPRT_PRTSPD_FULL_SPEED == port_speed) {
264 USB_HFT = 48000U;
265
266 if (HCTLR_48_MHZ != (USB_HCTL & HCTL_CLKSEL)) {
267 if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) {
268 USB_FSLSCLOCK_INIT(HCTLR_48_MHZ);
269 }
270 port_reset = 1U;
271 }
272 } else {
273 /* for high speed device and others */
274 port_reset = 1U;
275 }
276 }
277 }
278
279 if (port_reset) {
280 usb_port_reset(pudev);
281 }
282
283 /* clear port interrupts */
284 USB_HPCS = hostportdup;
285
286 return retval;
287 }
288
296 static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num)
297 {
298 uint32_t channel_intr = USB_HCHxINTF((uint16_t)channel_num);
299 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
300
301 channel_intr &= USB_HCHxINTEN((uint16_t)channel_num);
302
303 if (channel_intr & HCHINTF_ACK) {
304 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK;
305 } else if (channel_intr & HCHINTF_REQOVR) {
306 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
307 usb_hostchannel_halt(pudev, channel_num);
308 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR;
309 } else if (channel_intr & HCHINTF_TF) {
310 puhc->err_count = 0U;
311 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
312 usb_hostchannel_halt(pudev, channel_num);
313 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF;
314 puhc->status = HC_XF;
315 } else if (channel_intr & HCHINTF_STALL) {
316 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
317 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL;
318 usb_hostchannel_halt(pudev, channel_num);
319 puhc->status = HC_STALL;
320 } else if (channel_intr & HCHINTF_NAK) {
321 puhc->err_count = 0U;
322 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
323 usb_hostchannel_halt(pudev, channel_num);
324 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
325 puhc->status = HC_NAK;
326 } else if (channel_intr & HCHINTF_USBER) {
327 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
328 usb_hostchannel_halt(pudev, channel_num);
329 puhc->status = HC_TRACERR;
330 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER;
331 } else if (channel_intr & HCHINTF_NYET) {
332 puhc->err_count = 0U;
333 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
334 usb_hostchannel_halt(pudev, channel_num);
335 puhc->status = HC_NYET;
336 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NYET;
337 } else if (channel_intr & HCHINTF_DTER) {
338 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
339 usb_hostchannel_halt(pudev, channel_num);
340 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
341 puhc->status= HC_DTGERR;
342 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER;
343 } else if (channel_intr & HCHINTF_CH) {
344 USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE;
345
346 switch (puhc->status) {
347 case HC_XF:
348 puhc->urb_state = URB_DONE;
349
350 if (USB_EPTYPE_BULK == ((USB_HCHxCTL((uint16_t)channel_num) & HCHCTL_EPTYPE) >> 18)) {
351 puhc->data_tg_out ^= 1U;
352 }
353 break;
354 case HC_NAK:
355 puhc->urb_state = URB_NOTREADY;
356 break;
357 case HC_NYET:
358 puhc->urb_state = URB_NOTREADY;
359 break;
360 case HC_STALL:
361 puhc->urb_state = URB_STALL;
362 break;
363 case HC_TRACERR:
364 puhc->urb_state = URB_ERROR;
365 break;
366 default:
367 break;
368 }
369
370 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH;
371 } else {
372 /* no operation */
373 }
374
375 return 1U;
376 }
377
385 static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num)
386 {
387 uint8_t endp_type = 0U;
388 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
389
390 uint32_t channle_intf = USB_HCHxINTF((uint16_t)channel_num);
391 __IO uint32_t channel_ctrl = USB_HCHxCTL((uint16_t)channel_num);
392
393 channle_intf &= USB_HCHxINTEN((uint16_t)channel_num);
394
395 endp_type = (uint8_t)((channel_ctrl & HCHCTL_EPTYPE) >> 18U);
396
397 if (channle_intf & HCHINTF_ACK) {
398 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK;
399 } else if (channle_intf & HCHINTF_STALL) {
400 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
401 puhc->status = HC_STALL;
402 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
403 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL;
404
405 /* NOTE: When there is a 'stall', reset also nak,
406 else, the pudev->host.status = HC_STALL
407 will be overwritten by 'nak' in code below */
408 channle_intf &= ~HCHINTF_NAK;
409
410 usb_hostchannel_halt(pudev, channel_num);
411 } else if (channle_intf & HCHINTF_DTER) {
412 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
413 usb_hostchannel_halt(pudev, channel_num);
414 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
415 puhc->status = HC_DTGERR;
416 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER;
417 } else {
418 /* no operation */
419 }
420
421 if (channle_intf & HCHINTF_REQOVR) {
422 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
423 usb_hostchannel_halt(pudev, channel_num);
424 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR;
425 } else if (channle_intf & HCHINTF_TF) {
426 puhc->status = HC_XF;
427 puhc->err_count = 0U;
428 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF;
429
430 if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) {
431 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
432 usb_hostchannel_halt(pudev, channel_num);
433 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
434 puhc->data_tg_in ^= 1U;
435 } else if (USB_EPTYPE_INTR == endp_type) {
436 channel_ctrl |= HCHCTL_ODDFRM;
437 USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl;
438 puhc->urb_state = URB_DONE;
439 } else {
440 /* no operation */
441 }
442 } else if (channle_intf & HCHINTF_CH) {
443 USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE;
444
445 switch (puhc->status) {
446 case HC_XF:
447 puhc->urb_state = URB_DONE;
448 break;
449 case HC_TRACERR:
450 case HC_DTGERR:
451 puhc->err_count = 0U;
452 puhc->urb_state = URB_ERROR;
453 break;
454 case HC_STALL:
455 puhc->urb_state = URB_STALL;
456 break;
457 default:
458 if (USB_EPTYPE_INTR == endp_type) {
459 puhc->data_tg_in ^= 1U;
460 }
461 break;
462 }
463
464 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH;
465 } else if (channle_intf & HCHINTF_USBER) {
466 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
467 puhc->status = HC_TRACERR;
468 usb_hostchannel_halt(pudev, channel_num);
469 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER;
470 } else if (channle_intf & HCHINTF_NAK) {
471 if (USB_EPTYPE_INTR == endp_type) {
472 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
473 usb_hostchannel_halt(pudev, channel_num);
474 }
475
476 puhc->status = HC_NAK;
477 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
478
479 if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) {
480 /* re-activate the channel */
481 channel_ctrl |= HCHCTL_CEN;
482 channel_ctrl &= ~HCHCTL_CDIS;
483 USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl;
484 }
485 } else {
486 /* no operation */
487 }
488
489 return 1U;
490 }
491
498 static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev)
499 {
500 uint32_t count = 0U;
501 __IO uint8_t channel_num = 0U;
502 __IO uint32_t rx_status = 0U;
503 uint32_t usbh_ch_ctl_reg = 0U;
504 usb_hostchannel_struct *puhc;
505
506 /* disable the Rx status queue level interrupt */
507 USB_GINTEN &= ~GINTF_RXFNEIF;
508
509 rx_status = USB_GRSTATP;
510 channel_num = (uint8_t)(rx_status & GRSTATRP_CNUM);
511 puhc = &pudev->host.host_channel[channel_num];
512
513 switch ((rx_status & GRSTATRP_RPCKST) >> 17) {
514 case GRSTATR_RPCKST_IN:
515 count = (rx_status & GRSTATRP_BCOUNT) >> 4;
516
517 /* read the data into the host buffer. */
518 if ((count > 0U) && (puhc->xfer_buff != (void *)0)) {
519 usb_fifo_read(puhc->xfer_buff, (uint16_t)count);
520
521 /* manage multiple Xfer */
522 puhc->xfer_buff += count;
523 puhc->xfer_count += count;
524
525 if (USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_PCNT) {
526 /* re-activate the channel when more packets are expected */
527 usbh_ch_ctl_reg = USB_HCHxCTL((uint16_t)channel_num);
528 usbh_ch_ctl_reg |= HCHCTL_CEN;
529 usbh_ch_ctl_reg &= ~HCHCTL_CDIS;
530 USB_HCHxCTL((uint16_t)channel_num) = usbh_ch_ctl_reg;
531 }
532 }
533 break;
534 case GRSTATR_RPCKST_IN_XFER_COMP:
535 case GRSTATR_RPCKST_DATA_TOGGLE_ERR:
536 case GRSTATR_RPCKST_CH_HALTED:
537 default:
538 break;
539 }
540
541 /* enable the Rx status queue level interrupt */
542 USB_GINTEN |= GINTF_RXFNEIF;
543
544 return 1U;
545 }
546
553 static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev)
554 {
555 __IO uint32_t gint_flag = 0U;
556
557 gint_flag = USB_HCHxCTL(0U);
558 USB_HCHxCTL(0U) = 0U;
559
560 gint_flag = 0U;
561
562 /* clear interrupt */
563 gint_flag |= GINTF_ISOONCIF;
564 USB_GINTF = gint_flag;
565
566 return 1U;
567 }
USB_CORE_INTR_READ
#define USB_CORE_INTR_READ(x)
Definition: usb_regs.h:499
HC_NYET
Definition: usb_core.h:41
HPCS_PS
#define HPCS_PS
Definition: usb_regs.h:264
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:49
HC_XF
Definition: usb_core.h:38
usb_fifo_read
void * usb_fifo_read(uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint
Definition: usb_core.c:105
URB_STALL
Definition: usb_core.h:55
HCHINTF_ACK
#define HCHINTF_ACK
Definition: usb_regs.h:293
USB_FSLSCLOCK_INIT
#define USB_FSLSCLOCK_INIT(ClockFreq)
Definition: usb_regs.h:562
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:173
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:159
HPRT_PRTSPD_LOW_SPEED
#define HPRT_PRTSPD_LOW_SPEED
Definition: usb_defines.h:76
HCHINTF_CH
#define HCHINTF_CH
Definition: usb_regs.h:296
HPCS_PE
#define HPCS_PE
Definition: usb_regs.h:271
usb_hostchannel_struct::status
hc_status_enum status
Definition: usb_core.h:172
HCHINTF_NAK
#define HCHINTF_NAK
Definition: usb_regs.h:294
HCHCTL_CDIS
#define HCHCTL_CDIS
Definition: usb_regs.h:277
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:166
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:176
HPTFQSTAT_CNUM
#define HPTFQSTAT_CNUM
Definition: usb_regs.h:252
HNPTFQSTAT_NPTXFS
#define HNPTFQSTAT_NPTXFS
Definition: usb_regs.h:213
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:55
usbh_isr
uint32_t usbh_isr(usb_core_handle_struct *pudev)
handle global host interrupt
Definition: usbh_int.c:34
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:42
USB_HFT
#define USB_HFT
Definition: usb_regs.h:55
HCHINTF_USBER
#define HCHINTF_USBER
Definition: usb_regs.h:291
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:82
HPCS_PEDC
#define HPCS_PEDC
Definition: usb_regs.h:270
USB_HNPTFQSTAT
#define USB_HNPTFQSTAT
Definition: usb_regs.h:48
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:41
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:52
USB_HCHxLEN
#define USB_HCHxLEN(x)
Definition: usb_regs.h:64
HNPTFQSTAT_CNUM
#define HNPTFQSTAT_CNUM
Definition: usb_regs.h:214
GRSTATRP_RPCKST
#define GRSTATRP_RPCKST
Definition: usb_regs.h:193
HCHCTL_EPTYPE
#define HCHCTL_EPTYPE
Definition: usb_regs.h:281
usbh_hcd_int_fops
usbh_hcd_int_cb_struct * usbh_hcd_int_fops
Definition: usbh_core.c:34
USB_HACHINT
#define USB_HACHINT
Definition: usb_regs.h:58
URB_NOTREADY
Definition: usb_core.h:53
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:64
HCHINTF_DTER
#define HCHINTF_DTER
Definition: usb_regs.h:288
usb_hostchannel_struct::err_count
uint32_t err_count
Definition: usb_core.h:170
usb_hostchannel_struct
Definition: usb_core.h:155
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:496
USB_HCHxINTF
#define USB_HCHxINTF(x)
Definition: usb_regs.h:62
HPCS_PCD
#define HPCS_PCD
Definition: usb_regs.h:272
HCHINTEN_CHIE
#define HCHINTEN_CHIE
Definition: usb_regs.h:308
USB_CORE_EMBEDDED_PHY
#define USB_CORE_EMBEDDED_PHY
Definition: usb_defines.h:36
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:175
GRSTATR_RPCKST_IN
#define GRSTATR_RPCKST_IN
Definition: usb_defines.h:43
HC_TRACERR
Definition: usb_core.h:43
USB_GRSTATP
#define USB_GRSTATP
Definition: usb_regs.h:44
GRSTATR_RPCKST_DATA_TOGGLE_ERR
#define GRSTATR_RPCKST_DATA_TOGGLE_ERR
Definition: usb_defines.h:45
HC_NAK
Definition: usb_core.h:40
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:167
GINTF_HCIF
#define GINTF_HCIF
Definition: usb_regs.h:143
usbh_int.h
USB host mode interrupt handler header file.
usb_core.h
USB core driver header file.
USB_HCHxINTEN
#define USB_HCHxINTEN(x)
Definition: usb_regs.h:63
HC_STALL
Definition: usb_core.h:42
USB_HPTFQSTAT
#define USB_HPTFQSTAT
Definition: usb_regs.h:57
HCHCTL_ODDFRM
#define HCHCTL_ODDFRM
Definition: usb_regs.h:278
HCHCTL_EPDIR
#define HCHCTL_EPDIR
Definition: usb_regs.h:283
HACHINT_HACHINT
#define HACHINT_HACHINT
Definition: usb_regs.h:258
HCHCTL_CEN
#define HCHCTL_CEN
Definition: usb_regs.h:276
usbh_hcd_int_cb_struct::device_connected
uint8_t(* device_connected)(usb_core_handle_struct *pudev)
Definition: usbh_int.h:21
USB_HCHxCTL
#define USB_HCHxCTL(x)
Definition: usb_regs.h:61
HCHINTF_TF
#define HCHINTF_TF
Definition: usb_regs.h:297
usb_core_handle_struct
Definition: usb_core.h:201
URB_ERROR
Definition: usb_core.h:54
usb_defines.h
USB core defines.
HPRT_PRTSPD_FULL_SPEED
#define HPRT_PRTSPD_FULL_SPEED
Definition: usb_defines.h:75
GINTF_HPIF
#define GINTF_HPIF
Definition: usb_regs.h:144
USB_HCTL
#define USB_HCTL
Definition: usb_regs.h:54
HCHINTF_REQOVR
#define HCHINTF_REQOVR
Definition: usb_regs.h:289
HCHLEN_PCNT
#define HCHLEN_PCNT
Definition: usb_regs.h:313
HCHINTF_STALL
#define HCHINTF_STALL
Definition: usb_regs.h:295
HC_DTGERR
Definition: usb_core.h:45
GRSTATRP_BCOUNT
#define GRSTATRP_BCOUNT
Definition: usb_regs.h:195
GRSTATR_RPCKST_CH_HALTED
#define GRSTATR_RPCKST_CH_HALTED
Definition: usb_defines.h:46
USB_HPCS
#define USB_HPCS
Definition: usb_regs.h:60
GINTF_NPTXFEIF
#define GINTF_NPTXFEIF
Definition: usb_regs.h:158
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:146
HPTFQSTAT_PTXFS
#define HPTFQSTAT_PTXFS
Definition: usb_regs.h:250
HCTL_CLKSEL
#define HCTL_CLKSEL
Definition: usb_regs.h:238
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:65
usbh_hcd_int_cb_struct::sof
uint8_t(* sof)(usb_core_handle_struct *pudev)
Definition: usbh_int.h:20
usbh_hcd_int_cb_struct::device_disconnected
uint8_t(* device_disconnected)(usb_core_handle_struct *pudev)
Definition: usbh_int.h:22
GINTF_PTXFEIF
#define GINTF_PTXFEIF
Definition: usb_regs.h:142
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:160
GRSTATR_RPCKST_IN_XFER_COMP
#define GRSTATR_RPCKST_IN_XFER_COMP
Definition: usb_defines.h:44
URB_DONE
Definition: usb_core.h:52
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:168
HCTLR_48_MHZ
#define HCTLR_48_MHZ
Definition: usb_defines.h:79
GINTF_DISCIF
#define GINTF_DISCIF
Definition: usb_regs.h:140
GRSTATRP_CNUM
#define GRSTATRP_CNUM
Definition: usb_regs.h:196
HCHINTF_NYET
#define HCHINTF_NYET
Definition: usb_regs.h:292
HCTLR_6_MHZ
#define HCTLR_6_MHZ
Definition: usb_defines.h:80
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:203
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:54
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Include/usbd_core.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Include
usbd_core.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBD_CORE_H
14 #define USBD_CORE_H
15
16 #include "usbd_conf.h"
17 #include "usbd_regs.h"
18
19 /* interrupt flag mask which decide what event should be handled by application */
20 #define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \
21 | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE)
22
23 #ifdef LPM_ENABLED
24 #undef IER_MASK
25
26 #define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \
27 | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE | CTL_L1REQIE)
28 #endif /* LPM_ENABLED */
29
30 /* USB device endpoint0 max packet size */
31 #define USBD_EP0_MAX_SIZE 64U
32
33 #define USBD_CONTRL_STATUS_TX() do \
34 { \
35 pbuf_reg->tx_count = 0U; \
36 USBD_ENDP_TX_STATUS_SET(EP0, EPTX_VALID); \
37 } while(0)
38
39 #define USBD_CONTRL_STATUS_RX() do \
40 { \
41 USBD_STATUS_OUT_SET(EP0); \
42 USBD_ENDP_RX_STATUS_SET(EP0, EPRX_VALID); \
43 } while(0)
44
45 #define ENDP_BUF_ADDR (sizeof(usbd_ep_buf_struct) * EP_COUNT)
46
47 /* USB device endpoint type */
48 typedef enum
49 {
50 ENDP_CONTROL = 0,
51 ENDP_ISOC,
52 ENDP_BULK,
53 ENDP_INT
54 }usbd_eptype_enum;
55
56 /* USB device endpoint kind */
57 typedef enum
58 {
59 ENDP_SNG_BUF = 0,
60 ENDP_DBL_BUF
61 }usbd_epkind_enum;
62
63 /* transfer direction */
64 typedef enum
65 {
66 USBD_RX = 0,
67 USBD_TX
68 }usbd_dir_enum;
69
70 /* USB device status */
71 typedef enum
72 {
73 USBD_UNCONNECTED = 0,
74 USBD_DEFAULT,
75 USBD_ADDRESSED,
76 USBD_CONFIGURED,
77 USBD_SUSPENDED,
78 USBD_CONNECTED
79 }usbd_run_status_enum;
80
81 /* USB device operation state */
82 typedef enum
83 {
84 USBD_OK = 0,
85 USBD_BUSY,
86 USBD_FAIL
87 }usbd_status_enum;
88
89 typedef struct
90 {
91 uint16_t tx_addr;
92 uint16_t reserved0;
93 uint16_t tx_count;
94 uint16_t reserved1;
95 uint16_t rx_addr;
96 uint16_t reserved2;
97 uint16_t rx_count;
98 uint16_t reserved3;
99 }usbd_ep_buf_struct;
100
101 /* USB endpoint structure */
102 typedef struct
103 {
104 /* basic parameters */
105 uint8_t stall;
106 uint32_t maxpacket;
108 /* transaction level parameters */
109 uint8_t *trs_buf;
110 uint32_t trs_len;
111 uint32_t trs_count;
112 }usb_ep_struct;
113
114 /* USB standard device request structure */
115 typedef struct
116 {
117 uint8_t bmRequestType;
118 uint8_t bRequest;
119 uint16_t wValue;
120 uint16_t wIndex;
121 uint16_t wLength;
122 }usb_device_req_struct;
123
124 /* USB core driver struct */
125 typedef struct
126 {
127 /* basic parameters */
128 uint8_t config_num;
129 uint8_t status;
130 uint8_t prev_status;
131 uint8_t remote_wakeup;
134 /* the parameters which needs in control transfer */
135 uint8_t setup_packet[8];
136 uint32_t ctl_count;
138 /* device endpoints */
139 usb_ep_struct in_ep[EP_COUNT];
140 usb_ep_struct out_ep[EP_COUNT];
142 #ifdef LPM_ENABLED
143 uint8_t *bos_desc;
144 #endif /* LPM_ENABLED */
145
146 uint8_t *dev_desc;
147 uint8_t *config_desc;
148 void* const *strings;
150 /* device class handler */
151 usbd_status_enum (*class_init) (void *pudev, uint8_t config_index);
152 usbd_status_enum (*class_deinit) (void *pudev, uint8_t config_index);
153 usbd_status_enum (*class_req_handler) (void *pudev, usb_device_req_struct *req);
154 usbd_status_enum (*class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num);
155 }usbd_core_handle_struct;
156
157 extern uint32_t g_free_buf_addr;
158 extern usbd_ep_buf_struct *pbuf_reg;
159
160 /* function declarations */
161 /* device core register initialization */
162 void usbd_core_init (usbd_core_handle_struct *pudev);
163 /* device core register configure when stop device */
164 void usbd_core_deinit (void);
165
166 /* free buffer used from application by toggling the SW_BUF byte */
167 void user_buffer_free (uint8_t ep_num, uint8_t dir);
168
169 /* endpoint initialization */
170 void usbd_ep_init (usbd_core_handle_struct *pudev, void *pep_desc);
171 /* configure the endpoint when it is disabled */
172 void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr);
173 /* endpoint prepare to transmit data */
174 void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
175 /* endpoint prepare to receive data */
176 void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
177 /* set an endpoint to STALL status */
178 void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr);
179 /* clear endpoint stalled status */
180 void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr);
181 /* write datas from user fifo to USBRAM */
182 void usbd_ep_data_write (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes);
183 /* read datas from USBRAM to user fifo */
184 void usbd_ep_data_read (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes);
185
186 /* get the endpoint status */
187 uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr);
188
189 /* get the received data length */
190 uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num);
191
192 #endif /* USBD_CORE_H */
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
usbd_core_handle_struct::dev_desc
uint8_t * dev_desc
Definition: usbd_core.h:146
usbd_ep_deinit
void usbd_ep_deinit(usbd_core_handle_struct *pudev, uint8_t ep_addr)
configure the endpoint when it is disabled
Definition: usbd_core.c:173
usbd_ep_data_read
void usbd_ep_data_read(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
read datas from USBRAM to user fifo
Definition: usbd_core.c:369
usb_device_req_struct::wIndex
uint16_t wIndex
Definition: usbd_core.h:120
USBD_ADDRESSED
Definition: usbd_core.h:75
usb_device_req_struct::wLength
uint16_t wLength
Definition: usbd_core.h:121
USBD_FAIL
Definition: usbd_core.h:86
usbd_core_init
void usbd_core_init(usbd_core_handle_struct *pudev)
device core register initialization
Definition: usbd_core.c:27
usbd_ep_buf_struct::rx_addr
uint16_t rx_addr
Definition: usbd_core.h:95
ENDP_INT
Definition: usbd_core.h:53
usbd_rx_count_get
uint16_t usbd_rx_count_get(usbd_core_handle_struct *pudev, uint8_t ep_num)
get the received data length
Definition: usbd_core.c:387
ENDP_ISOC
Definition: usbd_core.h:51
usbd_ep_data_write
void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
write datas from user fifo to USBRAM
Definition: usbd_core.c:350
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
usb_device_req_struct
Definition: usbd_core.h:115
usbd_dir_enum
usbd_dir_enum
Definition: usbd_core.h:64
usbd_core_handle_struct::strings
void *const * strings
Definition: usbd_core.h:148
usbd_core_handle_struct::ctl_count
uint32_t ctl_count
Definition: usbd_core.h:136
usbd_ep_buf_struct::tx_addr
uint16_t tx_addr
Definition: usbd_core.h:91
usbd_ep_clear_stall
void usbd_ep_clear_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status
Definition: usbd_core.c:297
usbd_ep_buf_struct::reserved0
uint16_t reserved0
Definition: usbd_core.h:92
USBD_DEFAULT
Definition: usbd_core.h:74
usbd_ep_init
void usbd_ep_init(usbd_core_handle_struct *pudev, void *pep_desc)
endpoint initialization
Definition: usbd_core.c:100
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usbd_core.h:117
USBD_UNCONNECTED
Definition: usbd_core.h:73
pbuf_reg
usbd_ep_buf_struct * pbuf_reg
Definition: usbd_core.c:19
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
usbd_core_handle_struct::config_num
uint8_t config_num
Definition: usbd_core.h:128
ENDP_SNG_BUF
Definition: usbd_core.h:59
usbd_core_handle_struct::remote_wakeup
uint8_t remote_wakeup
Definition: usbd_core.h:131
USBD_SUSPENDED
Definition: usbd_core.h:77
usbd_core_handle_struct
Definition: usbd_core.h:125
usbd_core_handle_struct::prev_status
uint8_t prev_status
Definition: usbd_core.h:130
usbd_ep_buf_struct::reserved2
uint16_t reserved2
Definition: usbd_core.h:96
usb_ep_struct
Definition: usbd_core.h:102
usbd_ep_buf_struct
Definition: usbd_core.h:89
usbd_ep_status_get
uint8_t usbd_ep_status_get(usbd_core_handle_struct *pudev, uint8_t ep_addr)
get the endpoint status
Definition: usbd_core.c:333
ENDP_BULK
Definition: usbd_core.h:52
usbd_core_deinit
void usbd_core_deinit(void)
device core register configure when stop device
Definition: usbd_core.c:81
ENDP_CONTROL
Definition: usbd_core.h:50
usbd_run_status_enum
usbd_run_status_enum
Definition: usbd_core.h:71
USBD_OK
Definition: usbd_core.h:84
usbd_ep_buf_struct::reserved1
uint16_t reserved1
Definition: usbd_core.h:94
USBD_CONNECTED
Definition: usbd_core.h:78
usbd_ep_buf_struct::tx_count
uint16_t tx_count
Definition: usbd_core.h:93
usb_ep_struct::stall
uint8_t stall
Definition: usbd_core.h:105
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
ENDP_DBL_BUF
Definition: usbd_core.h:60
USBD_CONFIGURED
Definition: usbd_core.h:76
USBD_RX
Definition: usbd_core.h:66
usb_device_req_struct::bRequest
uint8_t bRequest
Definition: usbd_core.h:118
user_buffer_free
void user_buffer_free(uint8_t ep_num, uint8_t dir)
free buffer used from application by toggling the SW_BUF byte
Definition: usbd_core.c:64
usbd_regs.h
USB device registers.
usbd_ep_buf_struct::reserved3
uint16_t reserved3
Definition: usbd_core.h:98
usbd_core_handle_struct::status
uint8_t status
Definition: usbd_core.h:129
usbd_ep_buf_struct::rx_count
uint16_t rx_count
Definition: usbd_core.h:97
usbd_eptype_enum
usbd_eptype_enum
Definition: usbd_core.h:48
g_free_buf_addr
uint32_t g_free_buf_addr
Definition: usbd_core.c:17
usb_device_req_struct::wValue
uint16_t wValue
Definition: usbd_core.h:119
usbd_core_handle_struct::config_desc
uint8_t * config_desc
Definition: usbd_core.h:147
USBD_TX
Definition: usbd_core.h:67
usbd_epkind_enum
usbd_epkind_enum
Definition: usbd_core.h:57
USBD_BUSY
Definition: usbd_core.h:85
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_ctrl.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
usbh_ctrl.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbh_core.h"
14 #include "usbh_std.h"
15 #include "usbh_ctrl.h"
16
17 uint8_t ctrl_polling_handle_flag = 0U;
18 uint8_t ctrl_setup_wait_flag = 0U;
19 uint8_t ctrl_data_wait_flag = 0U;
20 uint8_t ctrl_status_wait_flag = 0U;
21
22 static uint16_t timeout = 0U;
23
24 static void ctrl_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
25 static void ctrl_setup_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
26 static void ctrl_data_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
27 static void ctrl_status_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
28 static void ctrl_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
29 static void ctrl_stalled_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
30 static void ctrl_complete_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
31
32 /* the ctrl state handle function array */
33 void (*ctrl_state_handle[]) (usb_core_handle_struct *pudev,
34 usbh_host_struct *puhost,
35 usbh_state_handle_struct *pustate) =
36 {
37 ctrl_idle_handle,
38 ctrl_setup_handle,
39 ctrl_data_handle,
40 ctrl_status_handle,
41 ctrl_error_handle,
42 ctrl_stalled_handle,
43 ctrl_complete_handle,
44 };
45
46 /* the ctrl state handle table */
47 state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] =
48 {
49 /* the current state the current event the next state the event function */
50 {CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move },
51 {CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move },
52 {CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move },
53 {CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
54 {CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move },
55 {CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
56 {CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move },
57 {CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move },
58 {CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
59 {CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move },
60 {CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
61 {CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
62 {CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
63 };
64
73 usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev,
74 usbh_host_struct *puhost,
75 void *pustate)
76 {
77 usbh_status_enum exe_state = USBH_BUSY;
78 usbh_state_handle_struct *p_state;
79
80 p_state = (usbh_state_handle_struct *)pustate;
81
82 /* if first enter this function, begin the ctrl state */
83 if (0U == ctrl_polling_handle_flag) {
84 ctrl_polling_handle_flag = 1U;
85 scd_table_push(p_state);
86 scd_state_move(p_state, CTRL_IDLE);
87 }
88
89 /* base on the current state to handle the ctrl state */
90 scd_begin(p_state, CTRL_FSM_ID);
91 ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
92
93 /* determine the control transfer whether to complete */
94 switch (puhost->usbh_backup_state.ctrl_backup_state) {
95 case CTRL_COMPLETE:
96 ctrl_polling_handle_flag = 0U;
97 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
98 exe_state = USBH_OK;
99 break;
100 case CTRL_STALLED:
101 ctrl_polling_handle_flag = 0U;
102 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
103 exe_state = USBH_NOT_SUPPORTED;
104 break;
105 case CTRL_ERROR:
106 ctrl_polling_handle_flag = 0U;
107 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
108 exe_state = USBH_FAIL;
109 break;
110 default:
111 exe_state = USBH_BUSY;
112 break;
113 }
114
115 return exe_state;
116 }
117
126 static void ctrl_idle_handle (usb_core_handle_struct *pudev,
127 usbh_host_struct *puhost,
128 usbh_state_handle_struct *pustate)
129 {
130 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
131 scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state);
132 }
133
142 static void ctrl_setup_handle (usb_core_handle_struct *pudev,
143 usbh_host_struct *puhost,
144 usbh_state_handle_struct *pustate)
145 {
146 urb_state_enum urb_status = URB_IDLE;
147 puhost->usbh_backup_state.ctrl_backup_state = CTRL_SETUP;
148
149 if (0U == ctrl_setup_wait_flag) {
150 ctrl_setup_wait_flag = 1U;
151
152 /* send a setup packet */
153 usbh_ctltx_setup (pudev,
154 puhost->control.setup.data,
155 puhost->control.hc_out_num);
156 } else {
157 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num);
158
159 /* case setup packet sent successfully */
160 if (URB_DONE == urb_status) {
161 /* check if there is a data stage */
162 if (0U != puhost->control.setup.b.wLength) {
163 ctrl_setup_wait_flag = 0U;
164 timeout = DATA_STAGE_TIMEOUT;
165 scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_DATA, pustate->usbh_current_state);
166 /* no data stage */
167 } else {
168 timeout = NODATA_STAGE_TIMEOUT;
169 ctrl_setup_wait_flag = 0U;
170 scd_event_handle(pudev,
171 puhost,
172 pustate,
173 CTRL_EVENT_STATUS,
174 pustate->usbh_current_state);
175 }
176
177 /* set the delay timer to enable timeout for data stage completion */
178 puhost->control.timer = (uint16_t)USB_CURRENT_FRAME_GET();
179 } else if (URB_ERROR == urb_status) {
180 ctrl_setup_wait_flag = 0U;
181 scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_ERROR, pustate->usbh_current_state);
182 } else {
183 /* no operation */
184 }
185 }
186 }
187
196 static void ctrl_data_handle (usb_core_handle_struct *pudev,
197 usbh_host_struct *puhost,
198 usbh_state_handle_struct *pustate)
199 {
200 uint8_t direction;
201 urb_state_enum urb_status = URB_IDLE;
202 puhost->usbh_backup_state.ctrl_backup_state = CTRL_DATA;
203
204 direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK);
205
206 if (USB_DIR_IN == direction) {
207 if (0U == ctrl_data_wait_flag) {
208 ctrl_data_wait_flag = 1U;
209
210 /* issue an IN token */
211 usbh_xfer(pudev,
212 puhost->control.buff,
213 puhost->control.hc_in_num,
214 puhost->control.length);
215 } else {
216 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num);
217
218 /* check is data packet transfered successfully */
219 switch (urb_status) {
220 case URB_DONE:
221 ctrl_data_wait_flag = 0U;
222
223 scd_event_handle(pudev,
224 puhost,
225 pustate,
226 CTRL_EVENT_STATUS,
227 pustate->usbh_current_state);
228 break;
229 case URB_STALL:
230 ctrl_data_wait_flag = 0U;
231
232 scd_event_handle(pudev,
233 puhost,
234 pustate,
235 CTRL_EVENT_STALLED,
236 pustate->usbh_current_state);
237 break;
238 case URB_ERROR:
239 ctrl_data_wait_flag = 0U;
240
241 /* device error */
242 scd_event_handle(pudev,
243 puhost,
244 pustate,
245 CTRL_EVENT_ERROR,
246 pustate->usbh_current_state);
247 break;
248 default:
249 if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) {
250 ctrl_data_wait_flag = 0U;
251
252 /* timeout for IN transfer */
253 scd_event_handle(pudev,
254 puhost,
255 pustate,
256 CTRL_EVENT_ERROR,
257 pustate->usbh_current_state);
258 }
259 break;
260 }
261 }
262 } else {
263 if (0U == ctrl_data_wait_flag) {
264 ctrl_data_wait_flag = 1U;
265
266 /* start DATA out transfer (only one DATA packet)*/
267 pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out = 1U;
268
269 usbh_xfer(pudev,
270 puhost->control.buff,
271 puhost->control.hc_out_num,
272 puhost->control.length);
273 } else {
274 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num);
275
276 switch (urb_status) {
277 case URB_DONE:
278 ctrl_data_wait_flag = 0U;
279
280 /* if the setup pkt is sent successful, then change the state */
281 scd_event_handle(pudev,
282 puhost,
283 pustate,
284 CTRL_EVENT_STATUS,
285 pustate->usbh_current_state);
286 break;
287 case URB_STALL:
288 ctrl_data_wait_flag = 0U;
289
290 scd_event_handle(pudev,
291 puhost,
292 pustate,
293 CTRL_EVENT_STALLED,
294 pustate->usbh_current_state);
295 break;
296 case URB_NOTREADY:
297 /* nack received from device */
298 ctrl_data_wait_flag = 0U;
299 break;
300 case URB_ERROR:
301 ctrl_data_wait_flag = 0U;
302
303 /* device error */
304 scd_event_handle(pudev,
305 puhost,
306 pustate,
307 CTRL_EVENT_ERROR,
308 pustate->usbh_current_state);
309 break;
310 default:
311 break;
312 }
313 }
314 }
315 }
316
325 static void ctrl_status_handle (usb_core_handle_struct *pudev,
326 usbh_host_struct *puhost,
327 usbh_state_handle_struct *pustate)
328 {
329 uint8_t direction;
330 urb_state_enum urb_status = URB_IDLE;
331
332 puhost->usbh_backup_state.ctrl_backup_state = CTRL_STATUS;
333
334 /* get the transfer direction in the data state, but the transfer direction in the status state is opposite */
335 direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK);
336
337 if (USB_DIR_OUT == direction) {
338 /* handle status in */
339 if (0U == ctrl_status_wait_flag) {
340 ctrl_status_wait_flag = 1U;
341 usbh_xfer (pudev, 0U, puhost->control.hc_in_num, 0U);
342 } else {
343 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num);
344
345 switch (urb_status) {
346 case URB_DONE:
347 ctrl_status_wait_flag = 0U;
348
349 /* handle URB_DONE status */
350 scd_event_handle(pudev,
351 puhost,
352 pustate,
353 CTRL_EVENT_COMPLETE,
354 pustate->usbh_current_state);
355 break;
356 case URB_ERROR:
357 ctrl_status_wait_flag = 0U;
358
359 /* handle URB_STALL status*/
360 scd_event_handle(pudev,
361 puhost,
362 pustate,
363 CTRL_EVENT_ERROR,
364 pustate->usbh_current_state);
365 break;
366 case URB_STALL:
367 ctrl_status_wait_flag = 0U;
368
369 /* handle URB_STALL status */
370 scd_event_handle(pudev,
371 puhost,
372 pustate,
373 CTRL_EVENT_STALLED,
374 pustate->usbh_current_state);
375 break;
376 default:
377 if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) {
378 ctrl_status_wait_flag = 0U;
379
380 /* handle timeout */
381 scd_event_handle(pudev,
382 puhost,
383 pustate,
384 CTRL_EVENT_ERROR,
385 pustate->usbh_current_state);
386 }
387 break;
388 }
389 }
390 } else {
391 /* handle status out */
392 if (0U == ctrl_status_wait_flag) {
393 ctrl_status_wait_flag = 1U;
394 pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U;
395 usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U);
396 } else {
397 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num);
398
399 switch (urb_status) {
400 case URB_DONE:
401 ctrl_status_wait_flag = 0U;
402
403 /* handle URB_DONE status */
404 scd_event_handle(pudev,
405 puhost,
406 pustate,
407 CTRL_EVENT_COMPLETE,
408 pustate->usbh_current_state);
409 break;
410 case URB_NOTREADY:
411 /* handle URB_NOTREADY status */
412 ctrl_status_wait_flag = 0U;
413 break;
414 case URB_ERROR:
415 ctrl_status_wait_flag = 0U;
416
417 /* handle URB_ERROR status */
418 scd_event_handle(pudev,
419 puhost,
420 pustate,
421 CTRL_EVENT_ERROR,
422 pustate->usbh_current_state);
423 break;
424 default:
425 break;
426 }
427 }
428 }
429 }
430
439 static void ctrl_error_handle (usb_core_handle_struct *pudev,
440 usbh_host_struct *puhost,
441 usbh_state_handle_struct *pustate)
442 {
443 puhost->usbh_backup_state.ctrl_backup_state = CTRL_ERROR;
444
445 if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) {
446 /* do the transmission again, starting from SETUP Packet */
447 scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state);
448 } else {
449 scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state);
450 }
451 }
452
461 static void ctrl_stalled_handle (usb_core_handle_struct *pudev,
462 usbh_host_struct *puhost,
463 usbh_state_handle_struct *pustate)
464 {
465 puhost->usbh_backup_state.ctrl_backup_state = CTRL_STALLED;
466 scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state);
467 }
468
477 static void ctrl_complete_handle (usb_core_handle_struct *pudev,
478 usbh_host_struct *puhost,
479 usbh_state_handle_struct *pustate)
480 {
481 puhost->usbh_backup_state.ctrl_backup_state = CTRL_COMPLETE;
482 scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state);
483 }
484
494 usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev,
495 uint8_t *buf,
496 uint8_t hc_num,
497 uint16_t len)
498 {
499 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
500
501 puhc->xfer_buff = buf;
502 puhc->xfer_len = len;
503
504 switch (puhc->endp_type) {
505 case USB_EPTYPE_CTRL:
506 if (0U == puhc->endp_in) {
507 if (0U == len) {
508 /* for status out stage, length = 0, status out pid = 1 */
509 puhc->data_tg_out = 1U;
510 }
511
512 /* set the data toggle bit as per the flag */
513 if (0U == puhc->data_tg_out) {
514 /* put the pid 0 */
515 puhc->DPID = HC_PID_DATA0;
516 } else {
517 /* put the pid 1 */
518 puhc->DPID = HC_PID_DATA1;
519 }
520 } else {
521 puhc->DPID = HC_PID_DATA1;
522 }
523 break;
524
525 case USB_EPTYPE_ISOC:
526 puhc->DPID = HC_PID_DATA0;
527 break;
528
529 case USB_EPTYPE_BULK:
530 if (0U == puhc->endp_in) {
531 /* set the data toggle bit as per the flag */
532 if (0U == puhc->data_tg_out) {
533 /* put the pid 0 */
534 puhc->DPID = HC_PID_DATA0;
535 } else {
536 /* put the pid 1 */
537 puhc->DPID = HC_PID_DATA1;
538 }
539 } else {
540 if (0U == puhc->data_tg_in) {
541 puhc->DPID = HC_PID_DATA0;
542 } else {
543 puhc->DPID = HC_PID_DATA1;
544 }
545 }
546 break;
547
548 case USB_EPTYPE_INTR:
549 if (0U == puhc->endp_in) {
550 if (0U == puhc->data_tg_out) {
551 puhc->DPID = HC_PID_DATA0;
552 } else {
553 puhc->DPID = HC_PID_DATA1;
554 }
555
556 /* toggle data pid */
557 puhc->data_tg_out ^= 1U;
558 } else {
559 if (0U == puhc->data_tg_in) {
560 puhc->DPID = HC_PID_DATA0;
561 } else {
562 puhc->DPID = HC_PID_DATA1;
563 }
564
565 /* toggle data pid */
566 puhc->data_tg_in ^= 1U;
567 }
568 break;
569
570 default:
571 break;
572 }
573
574 hcd_submit_request (pudev, hc_num);
575
576 return USBH_OK;
577 }
578
587 usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
588 {
589 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
590
591 puhc->DPID = HC_PID_SETUP;
592 puhc->xfer_buff = buf;
593 puhc->xfer_len = USBH_SETUP_PACKET_SIZE;
594
595 return (usbh_status_enum)hcd_submit_request (pudev, hc_num);
596 }
597
605 uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num)
606 {
607 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
608
609 puhc->urb_state = URB_IDLE;
610 puhc->xfer_count = 0U;
611
612 return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num);
613 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:706
hcd_urb_state_get
urb_state_enum hcd_urb_state_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:430
usbh_core.h
header file for usbh_core.c
usbh_std.h
header file for usbh_std.c
URB_STALL
Definition: usb_core.h:55
usbh_xfer
usbh_status_enum usbh_xfer(usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len)
send datas from the host channel
Definition: usbh_ctrl.c:494
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:173
usbh_state_handle_struct
Definition: usbh_core.h:228
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:605
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:53
ctrl_state_handle
void(* ctrl_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_ctrl.c:33
CTRL_EVENT_ERROR
Definition: usbh_ctrl.h:32
backup_state_struct::ctrl_backup_state
ctrl_state_enum ctrl_backup_state
Definition: usbh_core.h:183
CTRL_IDLE
Definition: usbh_core.h:97
urb_state_enum
urb_state_enum
Definition: usb_core.h:49
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:166
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:176
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:114
CTRL_ERROR
Definition: usbh_core.h:101
usbh_ctrl_struct::timer
uint16_t timer
Definition: usbh_core.h:133
ctrl_status_wait_flag
uint8_t ctrl_status_wait_flag
Definition: usbh_ctrl.c:20
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:42
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:128
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:55
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:134
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:161
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:17
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:52
USBH_NOT_SUPPORTED
Definition: usbh_core.h:112
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
usbh_host_struct
Definition: usbh_core.h:189
HC_PID_DATA1
#define HC_PID_DATA1
Definition: usb_defines.h:71
CTRL_HANDLE_TABLE_SIZE
#define CTRL_HANDLE_TABLE_SIZE
Definition: usbh_ctrl.h:19
URB_IDLE
Definition: usb_core.h:51
NODATA_STAGE_TIMEOUT
#define NODATA_STAGE_TIMEOUT
Definition: usb_std.h:101
URB_NOTREADY
Definition: usb_core.h:53
usb_setup_union::data
uint8_t data[8]
Definition: usb_std.h:110
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:118
UP_STATE
#define UP_STATE
Definition: usbh_core.h:46
CTRL_EVENT_SETUP
Definition: usbh_ctrl.h:28
GO_TO_UP_STATE_EVENT
#define GO_TO_UP_STATE_EVENT
Definition: usbh_core.h:47
usbh_ctltx_setup
usbh_status_enum usbh_ctltx_setup(usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
send the setup packet to the device
Definition: usbh_ctrl.c:587
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:27
USBH_MAX_ERROR_COUNT
#define USBH_MAX_ERROR_COUNT
Definition: usbh_core.h:27
CTRL_STATUS
Definition: usbh_core.h:100
usb_hostchannel_struct
Definition: usb_core.h:155
USBH_SETUP_PACKET_SIZE
#define USBH_SETUP_PACKET_SIZE
Definition: usbh_std.h:23
usbh_ctrl.h
header file for usbh_ctrl.c
DATA_STAGE_TIMEOUT
#define DATA_STAGE_TIMEOUT
Definition: usb_std.h:100
usbh_ctrl_struct::error_count
uint8_t error_count
Definition: usbh_core.h:131
CTRL_STALLED
Definition: usbh_core.h:102
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:175
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
HC_PID_DATA0
#define HC_PID_DATA0
Definition: usb_defines.h:69
ctrl_data_wait_flag
uint8_t ctrl_data_wait_flag
Definition: usbh_ctrl.c:19
ctrl_state_polling_fun
usbh_status_enum ctrl_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state
Definition: usbh_ctrl.c:73
USB_CURRENT_FRAME_GET
#define USB_CURRENT_FRAME_GET()
Definition: usb_regs.h:572
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
state_table_struct
Definition: usbh_core.h:203
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:159
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:167
scd_event_handle
usbh_status_enum scd_event_handle(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle
Definition: usbh_core.c:577
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:191
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:623
CTRL_EVENT_DATA
Definition: usbh_ctrl.h:29
USB_DIR_IN
#define USB_DIR_IN
Definition: usb_std.h:28
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:132
usb_core_handle_struct
Definition: usb_core.h:201
URB_ERROR
Definition: usb_core.h:54
CTRL_EVENT_STALLED
Definition: usbh_ctrl.h:33
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:693
ctrl_setup_wait_flag
uint8_t ctrl_setup_wait_flag
Definition: usbh_ctrl.c:18
USBH_OK
Definition: usbh_core.h:109
CTRL_SETUP
Definition: usbh_core.h:98
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:162
CTRL_EVENT_COMPLETE
Definition: usbh_ctrl.h:31
USB_DIR_MASK
#define USB_DIR_MASK
Definition: usb_std.h:26
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
USBH_FAIL
Definition: usbh_core.h:111
URB_DONE
Definition: usb_core.h:52
CTRL_COMPLETE
Definition: usbh_core.h:103
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:168
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:129
USBH_BUSY
Definition: usbh_core.h:110
ctrl_handle_table
state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Definition: usbh_ctrl.c:47
CTRL_DATA
Definition: usbh_core.h:99
HC_PID_SETUP
#define HC_PID_SETUP
Definition: usb_defines.h:72
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:135
CTRL_EVENT_STATUS
Definition: usbh_ctrl.h:30
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:54
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h Source File

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gd32f10x_gpio.h
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1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10x_GPIO_H
14 #define GD32F10x_GPIO_H
15
16 #include "gd32f10x.h"
17
18 /* GPIOx(x=A,B,C,D,E,F,G) definitions */
19 #define GPIOA (GPIO_BASE + 0x00000000U)
20 #define GPIOB (GPIO_BASE + 0x00000400U)
21 #define GPIOC (GPIO_BASE + 0x00000800U)
22 #define GPIOD (GPIO_BASE + 0x00000C00U)
23 #define GPIOE (GPIO_BASE + 0x00001000U)
24 #define GPIOF (GPIO_BASE + 0x00001400U)
25 #define GPIOG (GPIO_BASE + 0x00001800U)
26
27 /* AFIO definitions */
28 #define AFIO AFIO_BASE
29
30 /* registers definitions */
31
32 /* GPIO registers definitions */
33 #define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U)
34 #define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U)
35 #define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U)
36 #define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU)
37 #define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U)
38 #define GPIO_BC(gpiox) REG32((gpiox) + 0x14U)
39 #define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U)
41 /* AFIO registers definitions */
42 #define AFIO_EC REG32(AFIO + 0x00U)
43 #define AFIO_PCF0 REG32(AFIO + 0x04U)
44 #define AFIO_EXTISS0 REG32(AFIO + 0x08U)
45 #define AFIO_EXTISS1 REG32(AFIO + 0x0CU)
46 #define AFIO_EXTISS2 REG32(AFIO + 0x10U)
47 #define AFIO_EXTISS3 REG32(AFIO + 0x14U)
48 #define AFIO_PCF1 REG32(AFIO + 0x1CU)
50 /* bits definitions */
51 /* GPIO_CTL0 */
52 #define GPIO_CTL0_MD0 BITS(0,1)
53 #define GPIO_CTL0_CTL0 BITS(2,3)
54 #define GPIO_CTL0_MD1 BITS(4,5)
55 #define GPIO_CTL0_CTL1 BITS(6,7)
56 #define GPIO_CTL0_MD2 BITS(8,9)
57 #define GPIO_CTL0_CTL2 BITS(10,11)
58 #define GPIO_CTL0_MD3 BITS(12,13)
59 #define GPIO_CTL0_CTL3 BITS(14,15)
60 #define GPIO_CTL0_MD4 BITS(16,17)
61 #define GPIO_CTL0_CTL4 BITS(18,19)
62 #define GPIO_CTL0_MD5 BITS(20,21)
63 #define GPIO_CTL0_CTL5 BITS(22,23)
64 #define GPIO_CTL0_MD6 BITS(24,25)
65 #define GPIO_CTL0_CTL6 BITS(26,27)
66 #define GPIO_CTL0_MD7 BITS(28,29)
67 #define GPIO_CTL0_CTL7 BITS(30,31)
69 /* GPIO_CTL1 */
70 #define GPIO_CTL1_MD8 BITS(0,1)
71 #define GPIO_CTL1_CTL8 BITS(2,3)
72 #define GPIO_CTL1_MD9 BITS(4,5)
73 #define GPIO_CTL1_CTL9 BITS(6,7)
74 #define GPIO_CTL1_MD10 BITS(8,9)
75 #define GPIO_CTL1_CTL10 BITS(10,11)
76 #define GPIO_CTL1_MD11 BITS(12,13)
77 #define GPIO_CTL1_CTL11 BITS(14,15)
78 #define GPIO_CTL1_MD12 BITS(16,17)
79 #define GPIO_CTL1_CTL12 BITS(18,19)
80 #define GPIO_CTL1_MD13 BITS(20,21)
81 #define GPIO_CTL1_CTL13 BITS(22,23)
82 #define GPIO_CTL1_MD14 BITS(24,25)
83 #define GPIO_CTL1_CTL14 BITS(26,27)
84 #define GPIO_CTL1_MD15 BITS(28,29)
85 #define GPIO_CTL1_CTL15 BITS(30,31)
87 /* GPIO_ISTAT */
88 #define GPIO_ISTAT_ISTAT0 BIT(0)
89 #define GPIO_ISTAT_ISTAT1 BIT(1)
90 #define GPIO_ISTAT_ISTAT2 BIT(2)
91 #define GPIO_ISTAT_ISTAT3 BIT(3)
92 #define GPIO_ISTAT_ISTAT4 BIT(4)
93 #define GPIO_ISTAT_ISTAT5 BIT(5)
94 #define GPIO_ISTAT_ISTAT6 BIT(6)
95 #define GPIO_ISTAT_ISTAT7 BIT(7)
96 #define GPIO_ISTAT_ISTAT8 BIT(8)
97 #define GPIO_ISTAT_ISTAT9 BIT(9)
98 #define GPIO_ISTAT_ISTAT10 BIT(10)
99 #define GPIO_ISTAT_ISTAT11 BIT(11)
100 #define GPIO_ISTAT_ISTAT12 BIT(12)
101 #define GPIO_ISTAT_ISTAT13 BIT(13)
102 #define GPIO_ISTAT_ISTAT14 BIT(14)
103 #define GPIO_ISTAT_ISTAT15 BIT(15)
105 /* GPIO_OCTL */
106 #define GPIO_OCTL_OCTL0 BIT(0)
107 #define GPIO_OCTL_OCTL1 BIT(1)
108 #define GPIO_OCTL_OCTL2 BIT(2)
109 #define GPIO_OCTL_OCTL3 BIT(3)
110 #define GPIO_OCTL_OCTL4 BIT(4)
111 #define GPIO_OCTL_OCTL5 BIT(5)
112 #define GPIO_OCTL_OCTL6 BIT(6)
113 #define GPIO_OCTL_OCTL7 BIT(7)
114 #define GPIO_OCTL_OCTL8 BIT(8)
115 #define GPIO_OCTL_OCTL9 BIT(9)
116 #define GPIO_OCTL_OCTL10 BIT(10)
117 #define GPIO_OCTL_OCTL11 BIT(11)
118 #define GPIO_OCTL_OCTL12 BIT(12)
119 #define GPIO_OCTL_OCTL13 BIT(13)
120 #define GPIO_OCTL_OCTL14 BIT(14)
121 #define GPIO_OCTL_OCTL15 BIT(15)
123 /* GPIO_BOP */
124 #define GPIO_BOP_BOP0 BIT(0)
125 #define GPIO_BOP_BOP1 BIT(1)
126 #define GPIO_BOP_BOP2 BIT(2)
127 #define GPIO_BOP_BOP3 BIT(3)
128 #define GPIO_BOP_BOP4 BIT(4)
129 #define GPIO_BOP_BOP5 BIT(5)
130 #define GPIO_BOP_BOP6 BIT(6)
131 #define GPIO_BOP_BOP7 BIT(7)
132 #define GPIO_BOP_BOP8 BIT(8)
133 #define GPIO_BOP_BOP9 BIT(9)
134 #define GPIO_BOP_BOP10 BIT(10)
135 #define GPIO_BOP_BOP11 BIT(11)
136 #define GPIO_BOP_BOP12 BIT(12)
137 #define GPIO_BOP_BOP13 BIT(13)
138 #define GPIO_BOP_BOP14 BIT(14)
139 #define GPIO_BOP_BOP15 BIT(15)
140 #define GPIO_BOP_CR0 BIT(16)
141 #define GPIO_BOP_CR1 BIT(17)
142 #define GPIO_BOP_CR2 BIT(18)
143 #define GPIO_BOP_CR3 BIT(19)
144 #define GPIO_BOP_CR4 BIT(20)
145 #define GPIO_BOP_CR5 BIT(21)
146 #define GPIO_BOP_CR6 BIT(22)
147 #define GPIO_BOP_CR7 BIT(23)
148 #define GPIO_BOP_CR8 BIT(24)
149 #define GPIO_BOP_CR9 BIT(25)
150 #define GPIO_BOP_CR10 BIT(26)
151 #define GPIO_BOP_CR11 BIT(27)
152 #define GPIO_BOP_CR12 BIT(28)
153 #define GPIO_BOP_CR13 BIT(29)
154 #define GPIO_BOP_CR14 BIT(30)
155 #define GPIO_BOP_CR15 BIT(31)
157 /* GPIO_BC */
158 #define GPIO_BC_CR0 BIT(0)
159 #define GPIO_BC_CR1 BIT(1)
160 #define GPIO_BC_CR2 BIT(2)
161 #define GPIO_BC_CR3 BIT(3)
162 #define GPIO_BC_CR4 BIT(4)
163 #define GPIO_BC_CR5 BIT(5)
164 #define GPIO_BC_CR6 BIT(6)
165 #define GPIO_BC_CR7 BIT(7)
166 #define GPIO_BC_CR8 BIT(8)
167 #define GPIO_BC_CR9 BIT(9)
168 #define GPIO_BC_CR10 BIT(10)
169 #define GPIO_BC_CR11 BIT(11)
170 #define GPIO_BC_CR12 BIT(12)
171 #define GPIO_BC_CR13 BIT(13)
172 #define GPIO_BC_CR14 BIT(14)
173 #define GPIO_BC_CR15 BIT(15)
175 /* GPIO_LOCK */
176 #define GPIO_LOCK_LK0 BIT(0)
177 #define GPIO_LOCK_LK1 BIT(1)
178 #define GPIO_LOCK_LK2 BIT(2)
179 #define GPIO_LOCK_LK3 BIT(3)
180 #define GPIO_LOCK_LK4 BIT(4)
181 #define GPIO_LOCK_LK5 BIT(5)
182 #define GPIO_LOCK_LK6 BIT(6)
183 #define GPIO_LOCK_LK7 BIT(7)
184 #define GPIO_LOCK_LK8 BIT(8)
185 #define GPIO_LOCK_LK9 BIT(9)
186 #define GPIO_LOCK_LK10 BIT(10)
187 #define GPIO_LOCK_LK11 BIT(11)
188 #define GPIO_LOCK_LK12 BIT(12)
189 #define GPIO_LOCK_LK13 BIT(13)
190 #define GPIO_LOCK_LK14 BIT(14)
191 #define GPIO_LOCK_LK15 BIT(15)
192 #define GPIO_LOCK_LKK BIT(16)
194 /* AFIO_EC */
195 #define AFIO_EC_PIN BITS(0,3)
196 #define AFIO_EC_PORT BITS(4,6)
197 #define AFIO_EC_EOE BIT(7)
199 /* AFIO_PCF0 */
200 #ifdef GD32F10X_CL
201 /* memory map and bit definitions for GD32F10X_CL devices */
202 #define AFIO_PCF0_SPI0_REMAP BIT(0)
203 #define AFIO_PCF0_I2C0_REMAP BIT(1)
204 #define AFIO_PCF0_USART0_REMAP BIT(2)
205 #define AFIO_PCF0_USART1_REMAP BIT(3)
206 #define AFIO_PCF0_USART2_REMAP BITS(4,5)
207 #define AFIO_PCF0_TIMER0_REMAP BITS(6,7)
208 #define AFIO_PCF0_TIMER1_REMAP BITS(8,9)
209 #define AFIO_PCF0_TIMER2_REMAP BITS(10,11)
210 #define AFIO_PCF0_TIMER3_REMAP BIT(12)
211 #define AFIO_PCF0_CAN0_REMAP BITS(13,14)
212 #define AFIO_PCF0_PD01_REMAP BIT(15)
213 #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16)
214 #define AFIO_PCF0_ENET_REMAP BIT(21)
215 #define AFIO_PCF0_CAN1_REMAP BIT(22)
216 #define AFIO_PCF0_ENET_PHY_SEL BIT(23)
217 #define AFIO_PCF0_SWJ_CFG BITS(24,26)
218 #define AFIO_PCF0_SPI2_REMAP BIT(28)
219 #define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29)
220 #define AFIO_PCF0_PTP_PPS_REMAP BIT(30)
222 #else
223 /* memory map and bit definitions for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices */
224 #define AFIO_PCF0_SPI0_REMAP BIT(0)
225 #define AFIO_PCF0_I2C0_REMAP BIT(1)
226 #define AFIO_PCF0_USART0_REMAP BIT(2)
227 #define AFIO_PCF0_USART1_REMAP BIT(3)
228 #define AFIO_PCF0_USART2_REMAP BITS(4,5)
229 #define AFIO_PCF0_TIMER0_REMAP BITS(6,7)
230 #define AFIO_PCF0_TIMER1_REMAP BITS(8,9)
231 #define AFIO_PCF0_TIMER2_REMAP BITS(10,11)
232 #define AFIO_PCF0_TIMER3_REMAP BIT(12)
233 #define AFIO_PCF0_CAN_REMAP BITS(13,14)
234 #define AFIO_PCF0_PD01_REMAP BIT(15)
235 #define AFIO_PCF0_TIMER4CH3_REMAP BIT(16)
236 #define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17)
237 #define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18)
238 #define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19)
239 #define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20)
240 #define AFIO_PCF0_SWJ_CFG BITS(24,26)
241 #endif /* GD32F10X_CL */
242
243 /* AFIO_EXTISS0 */
244 #define AFIO_EXTI0_SS BITS(0,3)
245 #define AFIO_EXTI1_SS BITS(4,7)
246 #define AFIO_EXTI2_SS BITS(8,11)
247 #define AFIO_EXTI3_SS BITS(12,15)
249 /* AFIO_EXTISS1 */
250 #define AFIO_EXTI4_SS BITS(0,3)
251 #define AFIO_EXTI5_SS BITS(4,7)
252 #define AFIO_EXTI6_SS BITS(8,11)
253 #define AFIO_EXTI7_SS BITS(12,15)
255 /* AFIO_EXTISS2 */
256 #define AFIO_EXTI8_SS BITS(0,3)
257 #define AFIO_EXTI9_SS BITS(4,7)
258 #define AFIO_EXTI10_SS BITS(8,11)
259 #define AFIO_EXTI11_SS BITS(12,15)
261 /* AFIO_EXTISS3 */
262 #define AFIO_EXTI12_SS BITS(0,3)
263 #define AFIO_EXTI13_SS BITS(4,7)
264 #define AFIO_EXTI14_SS BITS(8,11)
265 #define AFIO_EXTI15_SS BITS(12,15)
267 /* AFIO_PCF1 */
268 #define AFIO_PCF1_TIMER8_REMAP BIT(5)
269 #define AFIO_PCF1_TIMER9_REMAP BIT(6)
270 #define AFIO_PCF1_TIMER10_REMAP BIT(7)
271 #define AFIO_PCF1_TIMER12_REMAP BIT(8)
272 #define AFIO_PCF1_TIMER13_REMAP BIT(9)
273 #define AFIO_PCF1_FSMC_NADV BIT(10)
275 /* constants definitions */
276 typedef FlagStatus bit_status;
277
278 /* GPIO mode values set */
279 #define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n))))
280 #define GPIO_MODE_MASK(n) (0xFU << (4U * (n)))
281
282 /* GPIO mode definitions */
283 #define GPIO_MODE_AIN ((uint8_t)0x00U)
284 #define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U)
285 #define GPIO_MODE_IPD ((uint8_t)0x28U)
286 #define GPIO_MODE_IPU ((uint8_t)0x48U)
287 #define GPIO_MODE_OUT_OD ((uint8_t)0x14U)
288 #define GPIO_MODE_OUT_PP ((uint8_t)0x10U)
289 #define GPIO_MODE_AF_OD ((uint8_t)0x1CU)
290 #define GPIO_MODE_AF_PP ((uint8_t)0x18U)
292 /* GPIO output max speed value */
293 #define GPIO_OSPEED_10MHZ ((uint8_t)0x01U)
294 #define GPIO_OSPEED_2MHZ ((uint8_t)0x02U)
295 #define GPIO_OSPEED_50MHZ ((uint8_t)0x03U)
297 /* GPIO event output port definitions */
298 #define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U)
299 #define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U)
300 #define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U)
301 #define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U)
302 #define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U)
304 /* GPIO output port source definitions */
305 #define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U)
306 #define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U)
307 #define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U)
308 #define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U)
309 #define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U)
310 #define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U)
311 #define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U)
313 /* GPIO event output pin definitions */
314 #define GPIO_EVENT_PIN_0 ((uint8_t)0x00U)
315 #define GPIO_EVENT_PIN_1 ((uint8_t)0x01U)
316 #define GPIO_EVENT_PIN_2 ((uint8_t)0x02U)
317 #define GPIO_EVENT_PIN_3 ((uint8_t)0x03U)
318 #define GPIO_EVENT_PIN_4 ((uint8_t)0x04U)
319 #define GPIO_EVENT_PIN_5 ((uint8_t)0x05U)
320 #define GPIO_EVENT_PIN_6 ((uint8_t)0x06U)
321 #define GPIO_EVENT_PIN_7 ((uint8_t)0x07U)
322 #define GPIO_EVENT_PIN_8 ((uint8_t)0x08U)
323 #define GPIO_EVENT_PIN_9 ((uint8_t)0x09U)
324 #define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU)
325 #define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU)
326 #define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU)
327 #define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU)
328 #define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU)
329 #define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU)
331 /* GPIO output pin source definitions */
332 #define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U)
333 #define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U)
334 #define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U)
335 #define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U)
336 #define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U)
337 #define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U)
338 #define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U)
339 #define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U)
340 #define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U)
341 #define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U)
342 #define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU)
343 #define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU)
344 #define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU)
345 #define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU)
346 #define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU)
347 #define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU)
349 /* GPIO pin definitions */
350 #define GPIO_PIN_0 BIT(0)
351 #define GPIO_PIN_1 BIT(1)
352 #define GPIO_PIN_2 BIT(2)
353 #define GPIO_PIN_3 BIT(3)
354 #define GPIO_PIN_4 BIT(4)
355 #define GPIO_PIN_5 BIT(5)
356 #define GPIO_PIN_6 BIT(6)
357 #define GPIO_PIN_7 BIT(7)
358 #define GPIO_PIN_8 BIT(8)
359 #define GPIO_PIN_9 BIT(9)
360 #define GPIO_PIN_10 BIT(10)
361 #define GPIO_PIN_11 BIT(11)
362 #define GPIO_PIN_12 BIT(12)
363 #define GPIO_PIN_13 BIT(13)
364 #define GPIO_PIN_14 BIT(14)
365 #define GPIO_PIN_15 BIT(15)
366 #define GPIO_PIN_ALL BITS(0,15)
368 /* GPIO remap definitions */
369 #define GPIO_SPI0_REMAP ((uint32_t)0x00000001U)
370 #define GPIO_I2C0_REMAP ((uint32_t)0x00000002U)
371 #define GPIO_USART0_REMAP ((uint32_t)0x00000004U)
372 #define GPIO_USART1_REMAP ((uint32_t)0x00000008U)
373 #define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U)
374 #define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U)
375 #define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U)
376 #define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U)
377 #define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U)
378 #define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U)
379 #define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U)
380 #define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U)
381 #define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U)
382 #define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U)
383 #define GPIO_PD01_REMAP ((uint32_t)0x00008000U)
384 #if (defined(GD32F10X_MD) || (GD32F10X_HD) || defined(GD32F10X_XD))
385 #define GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U)
386 #define GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U)
387 #endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */
388 #if (defined(GD32F10X_CL) || defined(GD32F10X_HD))
389 #define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U)
390 #endif /* GD32F10X_CL||GD32F10X_HD */
391 #if (defined(GD32F10X_MD) || (GD32F10X_HD) || defined(GD32F10X_XD))
392 #define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U)
393 #define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U)
394 #define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U)
395 #define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U)
396 #endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */
397 #define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U)
398 #define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U)
399 #define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U)
400 #ifdef GD32F10X_CL
401 #define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U)
402 #define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U)
403 #define GPIO_ENET_REMAP ((uint32_t)0x00200020U)
404 #define GPIO_CAN1_REMAP ((uint32_t)0x00200040U)
405 #define GPIO_SPI2_REMAP ((uint32_t)0x00201100U)
406 #define GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00202000U)
407 #define GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U)
408 #endif /* GD32F10X_CL */
409 #ifdef GD32F10X_XD
410 #define GPIO_TIMER8_REMAP ((uint32_t)0x80000020U)
411 #define GPIO_TIMER9_REMAP ((uint32_t)0x80000040U)
412 #define GPIO_TIMER10_REMAP ((uint32_t)0x80000080U)
413 #define GPIO_TIMER12_REMAP ((uint32_t)0x80000100U)
414 #define GPIO_TIMER13_REMAP ((uint32_t)0x80000200U)
415 #define GPIO_FSMC_NADV_REMAP ((uint32_t)0x80000400U)
416 #endif /* GD32F10X_XD */
417
418 #ifdef GD32F10X_CL
419 /* ethernet MII or RMII PHY selection */
420 #define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U)
421 #define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL
422 #endif /* GD32F10X_CL */
423
424 /* function declarations */
425 /* reset GPIO port */
426 void gpio_deinit(uint32_t gpio_periph);
427 /* reset alternate function I/O(AFIO) */
428 void gpio_afio_deinit(void);
429 /* GPIO parameter initialization */
430 void gpio_init(uint32_t gpio_periph,uint32_t gpio_mode,uint32_t gpio_speed,uint32_t pin);
431
432 /* set GPIO pin bit */
433 void gpio_bit_set(uint32_t gpio_periph,uint32_t pin);
434 /* reset GPIO pin bit */
435 void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin);
436 /* write data to the specified GPIO pin */
437 void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value);
438 /* write data to the specified GPIO port */
439 void gpio_port_write(uint32_t gpio_periph,uint16_t data);
440
441 /* get GPIO pin input status */
442 FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin);
443 /* get GPIO port input status */
444 uint16_t gpio_input_port_get(uint32_t gpio_periph);
445 /* get GPIO pin output status */
446 FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin);
447 /* get GPIO port output status */
448 uint16_t gpio_output_port_get(uint32_t gpio_periph);
449
450 /* lock GPIO pin bit */
451 void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin);
452
453 /* configure GPIO pin event output */
454 void gpio_event_output_config(uint8_t gpio_outputport,uint8_t gpio_outputpin);
455 /* enable GPIO pin event output */
456 void gpio_event_output_enable(void);
457 /* disable GPIO pin event output */
458 void gpio_event_output_disable(void);
459
460 /* select GPIO pin exti sources */
461 void gpio_exti_source_select(uint8_t gpio_outputport,uint8_t gpio_outputpin);
462
463 #ifdef GD32F10X_CL
464 /* select ethernet MII or RMII PHY */
465 void gpio_ethernet_phy_select(uint32_t gpio_enetsel);
466 #endif /* GD32F10X_CL */
467
468 /* configure GPIO pin remap */
469 void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue);
470
471 #endif /* GD32F10x_GPIO_H */
gpio_deinit
void gpio_deinit(uint32_t gpio_periph)
reset GPIO port
Definition: gd32f10x_gpio.c:29
gpio_init
void gpio_init(uint32_t gpio_periph, uint32_t gpio_mode, uint32_t gpio_speed, uint32_t pin)
GPIO parameter initialization.
Definition: gd32f10x_gpio.c:104
gpio_output_port_get
uint16_t gpio_output_port_get(uint32_t gpio_periph)
get GPIO port output status
Definition: gd32f10x_gpio.c:273
bit_status
FlagStatus bit_status
Definition: gd32f10x_gpio.h:276
gpio_input_bit_get
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
get GPIO pin input status
Definition: gd32f10x_gpio.c:231
gpio_pin_remap_config
void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue)
configure GPIO pin remap
Definition: gd32f10x_gpio.c:449
gpio_ethernet_phy_select
void gpio_ethernet_phy_select(uint32_t gpio_enetsel)
select ethernet MII or RMII PHY
Definition: gd32f10x_gpio.c:394
gpio_bit_write
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
write data to the specified GPIO pin
Definition: gd32f10x_gpio.c:203
gpio_exti_source_select
void gpio_exti_source_select(uint8_t gpio_outputport, uint8_t gpio_outputpin)
select GPIO pin exti sources
Definition: gd32f10x_gpio.c:360
gpio_bit_reset
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
reset GPIO pin
Definition: gd32f10x_gpio.c:188
gpio_port_write
void gpio_port_write(uint32_t gpio_periph, uint16_t data)
write data to the specified GPIO port
Definition: gd32f10x_gpio.c:219
gpio_afio_deinit
void gpio_afio_deinit(void)
reset alternate function I/O(AFIO)
Definition: gd32f10x_gpio.c:78
gpio_event_output_disable
void gpio_event_output_disable(void)
disable GPIO pin event output
Definition: gd32f10x_gpio.c:341
gpio_bit_set
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
set GPIO pin
Definition: gd32f10x_gpio.c:176
gpio_output_bit_get
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
get GPIO pin output status
Definition: gd32f10x_gpio.c:258
gpio_event_output_config
void gpio_event_output_config(uint8_t gpio_outputport, uint8_t gpio_outputpin)
configure GPIO pin event output
Definition: gd32f10x_gpio.c:310
gpio_event_output_enable
void gpio_event_output_enable(void)
enable GPIO pin event output
Definition: gd32f10x_gpio.c:330
gpio_input_port_get
uint16_t gpio_input_port_get(uint32_t gpio_periph)
get GPIO port input status
Definition: gd32f10x_gpio.c:246
gpio_pin_lock
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
lock GPIO pin
Definition: gd32f10x_gpio.c:285
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_std.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usb_std.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USB_STD_H
14 #define USB_STD_H
15
16 #include "usb_conf.h"
17
18 #define USB_DEV_QUALIFIER_DESC_LEN 0x0AU
19 #define USB_DEV_DESC_LEN 0x12U
20 #define USB_CFG_DESC_LEN 0x09U
21 #define USB_IF_DESC_LEN 0x09U
22 #define USB_EP_DESC_LEN 0x07U
23 #define USB_OTG_DESC_LEN 0x03U
25 /* bit 7 of bmRequestType: data phase transfer direction */
26 #define USB_DIR_MASK 0x80U
27 #define USB_DIR_OUT 0x00U
28 #define USB_DIR_IN 0x80U
30 /* bit 6..5 of bmRequestType: request type */
31 #define USB_STANDARD_REQ 0x00U
32 #define USB_CLASS_REQ 0x20U
33 #define USB_VENDOR_REQ 0x40U
34 #define USB_REQ_MASK 0x60U
36 /* bit 4..0 of bmRequestType: recipient type */
37 #define USB_REQTYPE_DEVICE 0x00U
38 #define USB_REQTYPE_INTERFACE 0x01U
39 #define USB_REQTYPE_ENDPOINT 0x02U
40 #define USB_REQTYPE_MASK 0x03U
42 /* bRequest value */
43 #define USBREQ_GET_STATUS 0x00U
44 #define USBREQ_CLEAR_FEATURE 0x01U
45 #define USBREQ_SET_FEATURE 0x03U
46 #define USBREQ_SET_ADDRESS 0x05U
47 #define USBREQ_GET_DESCRIPTOR 0x06U
48 #define USBREQ_SET_DESCRIPTOR 0x07U
49 #define USBREQ_GET_CONFIGURATION 0x08U
50 #define USBREQ_SET_CONFIGURATION 0x09U
51 #define USBREQ_GET_INTERFACE 0x0AU
52 #define USBREQ_SET_INTERFACE 0x0BU
53 #define USBREQ_SYNCH_FRAME 0x0CU
55 /* descriptor types of usb specifications */
56 #define USB_DESCTYPE_DEVICE 0x01U
57 #define USB_DESCTYPE_CONFIGURATION 0x02U
58 #define USB_DESCTYPE_STRING 0x03U
59 #define USB_DESCTYPE_INTERFACE 0x04U
60 #define USB_DESCTYPE_ENDPOINT 0x05U
61 #define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U
62 #define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U
63 #define USB_DESCTYPE_INTERFACE_POWER 0x08U
65 #define USB_DESCTYPE_HID 0x21U
66 #define USB_DESCTYPE_HID_REPORT 0x22U
68 #define USB_DEVDESC_SIZE 18U
69 #define USB_CFGDESC_SIZE 9U
70 #define USB_INTDESC_SIZE 9U
71 #define USB_EPDESC_SIZE 7U
73 /* descriptor type and descriptor index */
74 /* use the following values when USB host need to get descriptor */
75 #define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U)
76 #define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U)
77 #define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U)
78 #define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)
79 #define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)
80 #define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U)
81 #define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U)
82 #define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U)
83 #define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U)
84 #define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U)
86 #define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
87 (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
88
89 /* supported classes */
90 #define USB_MSC_CLASS 0x08U
91 #define USB_HID_CLASS 0x03U
93 /* interface descriptor field values for hid boot protocol */
94 #define HID_BOOT_CODE 0x01U
95 #define HID_KEYBRD_BOOT_CODE 0x01U
96 #define HID_MOUSE_BOOT_CODE 0x02U
98 /* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec
99 standard request with no data stage timeout : 50ms */
100 #define DATA_STAGE_TIMEOUT 5000U
101 #define NODATA_STAGE_TIMEOUT 50U
103 #define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \
104 + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE))
106 #pragma pack(1)
107
108 typedef union
109 {
110 uint8_t data[8];
111
112 struct _setup_packet_struct
113 {
114 uint8_t bmRequestType;
115 uint8_t bRequest;
116 uint16_t wValue;
117 uint16_t wIndex;
118 uint16_t wLength;
119 } b;
120 }usb_setup_union;
121
122 typedef struct
123 {
124 uint8_t bLength;
125 uint8_t bDescriptorType;
126 } usb_descriptor_header_struct;
127
128 typedef struct
129 {
130 usb_descriptor_header_struct Header;
132 uint16_t bcdUSB;
133 uint8_t bDeviceClass;
134 uint8_t bDeviceSubClass;
135 uint8_t bDeviceProtocol;
136 uint8_t bMaxPacketSize0;
137 uint16_t idVendor;
138 uint16_t idProduct;
139 uint16_t bcdDevice;
140 uint8_t iManufacturer;
141 uint8_t iProduct;
142 uint8_t iSerialNumber;
143 uint8_t bNumberConfigurations;
144 } usb_descriptor_device_struct;
145
146 typedef struct
147 {
148 usb_descriptor_header_struct Header;
150 uint16_t wTotalLength;
151 uint8_t bNumInterfaces;
152 uint8_t bConfigurationValue;
153 uint8_t iConfiguration;
154 uint8_t bmAttributes;
155 uint8_t bMaxPower;
156 } usb_descriptor_configuration_struct;
157
158 typedef struct
159 {
160 usb_descriptor_header_struct Header;
162 uint8_t bInterfaceNumber;
163 uint8_t bAlternateSetting;
164 uint8_t bNumEndpoints;
165 uint8_t bInterfaceClass;
166 uint8_t bInterfaceSubClass;
167 uint8_t bInterfaceProtocol;
168 uint8_t iInterface;
169 } usb_descriptor_interface_struct;
170
171 typedef struct
172 {
173 usb_descriptor_header_struct Header;
175 uint8_t bEndpointAddress;
176 uint8_t bmAttributes;
177 uint16_t wMaxPacketSize;
178 uint8_t bInterval;
179 } usb_descriptor_endpoint_struct;
180
181 typedef struct
182 {
183 usb_descriptor_header_struct Header;
184 uint16_t wLANGID;
185 }usb_descriptor_language_id_struct;
186
187 #pragma pack()
188
189 #endif /* USB_STD_H */
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:117
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:114
usb_descriptor_interface_struct
Definition: usbd_std.h:142
usb_descriptor_header_struct
Definition: usbd_std.h:102
usb_descriptor_device_struct
Definition: usbd_std.h:108
usb_setup_union
Definition: usb_std.h:108
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:118
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:116
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:115
usb_setup_union::_setup_packet_struct
Definition: usb_std.h:112
usb_descriptor_language_id_struct
Definition: usbd_std.h:167
usb_descriptor_configuration_struct
Definition: usbd_std.h:128
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbh_std.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usbh_std.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBH_STD_H
14 #define USBH_STD_H
15
16 #include "usbh_core.h"
17 #include "usbh_usr.h"
18
19 /* standard feature selector for clear feature command */
20 #define FEATURE_SELECTOR_ENDPOINT 0x00U
21 #define FEATURE_SELECTOR_DEVICE 0x01U
22
23 #define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */
24 #define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */
25
26 extern uint8_t usbh_cfg_desc[512];
27 extern uint8_t enum_polling_handle_flag;
28 extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE];
29
30 typedef enum
31 {
32 ENUN_EVENT_IDLE = 0, /* the enum idle event */
33 ENUM_EVENT_SET_ADDR, /* the enum set address event */
34 ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */
35 ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */
36 ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */
37 ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */
38 ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */
39 ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */
40 ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */
41 ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */
42 }enum_event_enum;
43
44 /* function declarations */
45 /* the polling function of enumeration state */
46 usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
47 /* get descriptor in usb host enumeration stage */
48 void usbh_enum_desc_get (usb_core_handle_struct *pudev,
49 usbh_host_struct *puhost,
50 uint8_t *buf,
51 uint8_t req_type,
52 uint16_t value_idx,
53 uint16_t len);
54 /* set address in usb host enumeration stage */
55 void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address);
56 /* set configuration in usb host enumeration stage */
57 void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx);
58 /* parse the device descriptor */
59 void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len);
60 /* parse the configuration descriptor */
61 void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc,
62 usb_descriptor_interface_struct *itf_desc,
63 usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM],
64 uint8_t *buf,
65 uint16_t len);
66 /* parse the interface descriptor */
67 void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf);
68 /* parse the endpoint descriptor */
69 void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf);
70 /* parse the string descriptor */
71 void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len);
72 /* get the next descriptor header */
73 usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr);
74
75 #endif /* USBH_STD_H */
usbh_core.h
header file for usbh_core.c
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
Definition: usbh_std.h:39
usbh_enum_addr_set
void usbh_enum_addr_set(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address)
set address in usb host enumeration stage
Definition: usbh_std.c:560
enum_event_enum
enum_event_enum
Definition: usbh_std.h:30
usbh_enum_cfg_set
void usbh_enum_cfg_set(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx)
set configuration in usb host enumeration stage
Definition: usbh_std.c:583
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:20
usbh_cfg_desc
uint8_t usbh_cfg_desc[512]
Definition: usbh_std.c:19
ENUN_EVENT_DEV_CONFIGURED
Definition: usbh_std.h:41
ENUN_EVENT_SET_CONFIGURATION
Definition: usbh_std.h:40
usbh_device_desc_parse
void usbh_device_desc_parse(usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
parse the device descriptor
Definition: usbh_std.c:606
usb_descriptor_interface_struct
Definition: usbd_std.h:142
usb_descriptor_header_struct
Definition: usbd_std.h:102
usb_descriptor_device_struct
Definition: usbd_std.h:108
usbh_next_desc_get
usb_descriptor_header_struct * usbh_next_desc_get(uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header
Definition: usbh_std.c:796
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
usbh_host_struct
Definition: usbh_core.h:189
ENUN_EVENT_GET_PRODUCT_STRING_DESC
Definition: usbh_std.h:38
ENUN_EVENT_GET_CFG_DESC
Definition: usbh_std.h:35
ENUN_EVENT_GET_FULL_CFG_DESC
Definition: usbh_std.h:36
ENUN_EVENT_GET_MFC_STRING_DESC
Definition: usbh_std.h:37
usbh_endpoint_desc_parse
void usbh_endpoint_desc_parse(usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor
Definition: usbh_std.c:743
ENUN_EVENT_GET_FULL_DEV_DESC
Definition: usbh_std.h:34
usb_descriptor_endpoint_struct
Definition: usbd_std.h:157
usbh_interface_desc_parse
void usbh_interface_desc_parse(usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor
Definition: usbh_std.c:723
state_table_struct
Definition: usbh_core.h:203
ENUN_EVENT_IDLE
Definition: usbh_std.h:32
usb_core_handle_struct
Definition: usb_core.h:201
ENUM_EVENT_SET_ADDR
Definition: usbh_std.h:33
usbh_enum_desc_get
void usbh_enum_desc_get(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t *buf, uint8_t req_type, uint16_t value_idx, uint16_t len)
get descriptor in usb host enumeration stage
Definition: usbh_std.c:526
usbh_string_desc_parse
void usbh_string_desc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len)
parse the string descriptor
Definition: usbh_std.c:761
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:24
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:49
usbh_cfg_desc_parse
void usbh_cfg_desc_parse(usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], uint8_t *buf, uint16_t len)
parse the configuration descriptor
Definition: usbh_std.c:638
enum_state_polling_fun
usbh_status_enum enum_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state
Definition: usbh_std.c:72
usb_descriptor_configuration_struct
Definition: usbd_std.h:128
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_dac.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_DAC_H
14 #define GD32F10X_DAC_H
15
16 #include "gd32f10x.h"
17
18 /* DACx(x=0,1) definitions */
19 #define DAC DAC_BASE
20 #define DAC0 0U
21 #define DAC1 1U
22
23 /* registers definitions */
24 #define DAC_CTL REG32(DAC + 0x00U)
25 #define DAC_SWT REG32(DAC + 0x04U)
26 #define DAC0_R12DH REG32(DAC + 0x08U)
27 #define DAC0_L12DH REG32(DAC + 0x0CU)
28 #define DAC0_R8DH REG32(DAC + 0x10U)
29 #define DAC1_R12DH REG32(DAC + 0x14U)
30 #define DAC1_L12DH REG32(DAC + 0x18U)
31 #define DAC1_R8DH REG32(DAC + 0x1CU)
32 #define DACC_R12DH REG32(DAC + 0x20U)
33 #define DACC_L12DH REG32(DAC + 0x24U)
34 #define DACC_R8DH REG32(DAC + 0x28U)
35 #define DAC0_DO REG32(DAC + 0x2CU)
36 #define DAC1_DO REG32(DAC + 0x30U)
38 /* bits definitions */
39 /* DAC_CTL */
40 #define DAC_CTL_DEN0 BIT(0)
41 #define DAC_CTL_DBOFF0 BIT(1)
42 #define DAC_CTL_DTEN0 BIT(2)
43 #define DAC_CTL_DTSEL0 BITS(3,5)
44 #define DAC_CTL_DWM0 BITS(6,7)
45 #define DAC_CTL_DWBW0 BITS(8,11)
46 #define DAC_CTL_DDMAEN0 BIT(12)
47 #define DAC_CTL_DEN1 BIT(16)
48 #define DAC_CTL_DBOFF1 BIT(17)
49 #define DAC_CTL_DTEN1 BIT(18)
50 #define DAC_CTL_DTSEL1 BITS(19,21)
51 #define DAC_CTL_DWM1 BITS(22,23)
52 #define DAC_CTL_DWBW1 BITS(24,27)
53 #define DAC_CTL_DDMAEN1 BIT(28)
55 /* DAC_SWT */
56 #define DAC_SWT_SWTR0 BIT(0)
57 #define DAC_SWT_SWTR1 BIT(1)
59 /* DAC0_R12DH */
60 #define DAC0_R12DH_DAC0_DH BITS(0,11)
62 /* DAC0_L12DH */
63 #define DAC0_L12DH_DAC0_DH BITS(4,15)
65 /* DAC0_R8DH */
66 #define DAC0_R8DH_DAC0_DH BITS(0,7)
68 /* DAC1_R12DH */
69 #define DAC1_R12DH_DAC1_DH BITS(0,11)
71 /* DAC1_L12DH */
72 #define DAC1_L12DH_DAC1_DH BITS(4,15)
74 /* DAC1_R8DH */
75 #define DAC1_R8DH_DAC1_DH BITS(0,7)
77 /* DACC_R12DH */
78 #define DACC_R12DH_DAC0_DH BITS(0,11)
79 #define DACC_R12DH_DAC1_DH BITS(16,27)
81 /* DACC_L12DH */
82 #define DACC_L12DH_DAC0_DH BITS(4,15)
83 #define DACC_L12DH_DAC1_DH BITS(20,31)
85 /* DACC_R8DH */
86 #define DACC_R8DH_DAC0_DH BITS(0,7)
87 #define DACC_R8DH_DAC1_DH BITS(8,15)
89 /* DAC0_DO */
90 #define DAC0_DO_DAC0_DO BITS(0,11)
92 /* DAC1_DO */
93 #define DAC1_DO_DAC1_DO BITS(0,11)
95 /* constants definitions */
96 /* DAC trigger source */
97 #define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
98 #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0)
99 #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
100 #define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1)
101 #elif defined(GD32F10X_CL)
102 #define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1)
103 #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
104 #define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2)
105 #define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3)
106 #define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4)
107 #define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5)
108 #define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6)
109 #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7)
111 /* DAC noise wave mode */
112 #define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
113 #define DAC_WAVE_DISABLE CTL_DWM(0)
114 #define DAC_WAVE_MODE_LFSR CTL_DWM(1)
115 #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2)
117 /* DAC noise wave bit width */
118 #define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
119 #define DAC_WAVE_BIT_WIDTH_1 DWBW(0)
120 #define DAC_WAVE_BIT_WIDTH_2 DWBW(1)
121 #define DAC_WAVE_BIT_WIDTH_3 DWBW(2)
122 #define DAC_WAVE_BIT_WIDTH_4 DWBW(3)
123 #define DAC_WAVE_BIT_WIDTH_5 DWBW(4)
124 #define DAC_WAVE_BIT_WIDTH_6 DWBW(5)
125 #define DAC_WAVE_BIT_WIDTH_7 DWBW(6)
126 #define DAC_WAVE_BIT_WIDTH_8 DWBW(7)
127 #define DAC_WAVE_BIT_WIDTH_9 DWBW(8)
128 #define DAC_WAVE_BIT_WIDTH_10 DWBW(9)
129 #define DAC_WAVE_BIT_WIDTH_11 DWBW(10)
130 #define DAC_WAVE_BIT_WIDTH_12 DWBW(11)
132 /* unmask LFSR bits in DAC LFSR noise mode */
133 #define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1
134 #define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2
135 #define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3
136 #define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4
137 #define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5
138 #define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6
139 #define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7
140 #define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8
141 #define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9
142 #define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10
143 #define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11
144 #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12
146 /* triangle amplitude in DAC triangle noise mode */
147 #define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1
148 #define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2
149 #define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3
150 #define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4
151 #define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5
152 #define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6
153 #define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7
154 #define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8
155 #define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9
156 #define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10
157 #define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11
158 #define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12
160 /* DAC data alignment */
161 #define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
162 #define DAC_ALIGN_12B_R DATA_ALIGN(0)
163 #define DAC_ALIGN_12B_L DATA_ALIGN(1)
164 #define DAC_ALIGN_8B_R DATA_ALIGN(2)
166 /* function declarations */
167 /* deinitialize DAC */
168 void dac_deinit(void);
169 /* enable DAC */
170 void dac_enable(uint32_t dac_periph);
171 /* disable DAC */
172 void dac_disable(uint32_t dac_periph);
173 /* enable DAC DMA */
174 void dac_dma_enable(uint32_t dac_periph);
175 /* disable DAC DMA */
176 void dac_dma_disable(uint32_t dac_periph);
177 /* enable DAC output buffer */
178 void dac_output_buffer_enable(uint32_t dac_periph);
179 /* disable DAC output buffer */
180 void dac_output_buffer_disable(uint32_t dac_periph);
181 /* enable DAC trigger */
182 void dac_trigger_enable(uint32_t dac_periph);
183 /* disable DAC trigger */
184 void dac_trigger_disable(uint32_t dac_periph);
185 /* enable DAC software trigger */
186 void dac_software_trigger_enable(uint32_t dac_periph);
187 /* disable DAC software trigger */
188 void dac_software_trigger_disable(uint32_t dac_periph);
189
190 /* configure DAC trigger source */
191 void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
192 /* configure DAC wave mode */
193 void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
194 /* configure DAC wave bit width */
195 void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
196 /* configure DAC LFSR noise mode */
197 void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
198 /* configure DAC triangle noise mode */
199 void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
200 /* get the last data output value */
201 uint16_t dac_output_value_get(uint32_t dac_periph);
202
203 /* set DAC data holding register value */
204 void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
205 /* set DAC concurrent mode data holding register value */
206 void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1);
207
208 /* enable DAC concurrent mode */
209 void dac_concurrent_enable(void);
210 /* disable DAC concurrent mode */
211 void dac_concurrent_disable(void);
212 /* enable DAC concurrent software trigger */
213 void dac_concurrent_software_trigger_enable(void);
214 /* disable DAC concurrent software trigger */
215 void dac_concurrent_software_trigger_disable(void);
216 /* enable DAC concurrent buffer function */
217 void dac_concurrent_output_buffer_enable(void);
218 /* disable DAC concurrent buffer function */
219 void dac_concurrent_output_buffer_disable(void);
220
221 #endif /* GD32F10X_DAC_H */
dac_software_trigger_disable
void dac_software_trigger_disable(uint32_t dac_periph)
disable DAC software trigger
Definition: gd32f10x_dac.c:177
dac_concurrent_output_buffer_enable
void dac_concurrent_output_buffer_enable(void)
enable DAC concurrent buffer function
Definition: gd32f10x_dac.c:405
dac_output_buffer_enable
void dac_output_buffer_enable(uint32_t dac_periph)
enable DAC output buffer
Definition: gd32f10x_dac.c:98
dac_trigger_disable
void dac_trigger_disable(uint32_t dac_periph)
disable DAC trigger
Definition: gd32f10x_dac.c:146
dac_lfsr_noise_config
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
configure DAC LFSR noise mode
Definition: gd32f10x_dac.c:287
dac_deinit
void dac_deinit(void)
deinitialize DAC
Definition: gd32f10x_dac.c:21
dac_enable
void dac_enable(uint32_t dac_periph)
enable DAC
Definition: gd32f10x_dac.c:34
dac_concurrent_disable
void dac_concurrent_disable(void)
disable DAC concurrent mode
Definition: gd32f10x_dac.c:366
dac_trigger_enable
void dac_trigger_enable(uint32_t dac_periph)
enable DAC trigger
Definition: gd32f10x_dac.c:130
dac_dma_enable
void dac_dma_enable(uint32_t dac_periph)
enable DAC DMA function
Definition: gd32f10x_dac.c:66
dac_data_set
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
set the DAC specified data holding register value
Definition: gd32f10x_dac.c:437
dac_trigger_source_config
void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource)
set DAC trigger source
Definition: gd32f10x_dac.c:203
dac_concurrent_output_buffer_disable
void dac_concurrent_output_buffer_disable(void)
disable DAC concurrent buffer function
Definition: gd32f10x_dac.c:418
dac_concurrent_enable
void dac_concurrent_enable(void)
enable DAC concurrent mode
Definition: gd32f10x_dac.c:353
dac_concurrent_software_trigger_disable
void dac_concurrent_software_trigger_disable(void)
disable DAC concurrent software trigger function
Definition: gd32f10x_dac.c:392
dac_wave_bit_width_config
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
configure DAC wave bit width
Definition: gd32f10x_dac.c:256
dac_wave_mode_config
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
configure DAC wave mode
Definition: gd32f10x_dac.c:225
dac_software_trigger_enable
void dac_software_trigger_enable(uint32_t dac_periph)
enable DAC software trigger
Definition: gd32f10x_dac.c:161
dac_concurrent_software_trigger_enable
void dac_concurrent_software_trigger_enable(void)
enable DAC concurrent software trigger function
Definition: gd32f10x_dac.c:379
dac_output_buffer_disable
void dac_output_buffer_disable(uint32_t dac_periph)
disable DAC output buffer
Definition: gd32f10x_dac.c:114
dac_concurrent_data_set
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
set DAC concurrent mode data holding register value
Definition: gd32f10x_dac.c:487
dac_disable
void dac_disable(uint32_t dac_periph)
disable DAC
Definition: gd32f10x_dac.c:50
dac_triangle_noise_config
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
configure DAC triangle noise mode
Definition: gd32f10x_dac.c:318
dac_output_value_get
uint16_t dac_output_value_get(uint32_t dac_periph)
get DAC output value
Definition: gd32f10x_dac.c:336
dac_dma_disable
void dac_dma_disable(uint32_t dac_periph)
disable DAC DMA function
Definition: gd32f10x_dac.c:82
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_pmu.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_pmu.h"
14
21 void pmu_deinit(void)
22 {
23 /* reset PMU */
24 rcu_periph_reset_enable(RCU_PMURST);
25 rcu_periph_reset_disable(RCU_PMURST);
26 }
27
42 void pmu_lvd_select(uint32_t lvdt_n)
43 {
44 /* disable LVD */
45 PMU_CTL &= ~PMU_CTL_LVDEN;
46 /* clear LVDT bits */
47 PMU_CTL &= ~PMU_CTL_LVDT;
48 /* set LVDT bits according to lvdt_n */
49 PMU_CTL |= lvdt_n;
50 /* enable LVD */
51 PMU_CTL |= PMU_CTL_LVDEN;
52 }
53
60 void pmu_lvd_disable(void)
61 {
62 /* disable LVD */
63 PMU_CTL &= ~PMU_CTL_LVDEN;
64 }
65
74 void pmu_to_sleepmode(uint8_t sleepmodecmd)
75 {
76 /* clear sleepdeep bit of Cortex-M3 system control register */
77 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
78
79 /* select WFI or WFE command to enter sleep mode */
80 if(WFI_CMD == sleepmodecmd){
81 __WFI();
82 }else{
83 __WFE();
84 }
85 }
86
98 void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
99 {
100 /* clear stbmod and ldolp bits */
101 PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
102
103 /* set ldolp bit according to pmu_ldo */
104 PMU_CTL |= ldo;
105
106 /* set sleepdeep bit of Cortex-M3 system control register */
107 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
108
109 /* select WFI or WFE command to enter deepsleep mode */
110 if(WFI_CMD == deepsleepmodecmd){
111 __WFI();
112 }else{
113 __SEV();
114 __WFE();
115 __WFE();
116 }
117 /* reset sleepdeep bit of Cortex-M3 system control register */
118 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
119 }
120
129 void pmu_to_standbymode(uint8_t standbymodecmd)
130 {
131 /* set sleepdeep bit of Cortex-M3 system control register */
132 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
133
134 /* set stbmod bit */
135 PMU_CTL |= PMU_CTL_STBMOD;
136
137 /* reset wakeup flag */
138 PMU_CTL |= PMU_CTL_WURST;
139
140 /* select WFI or WFE command to enter standby mode */
141 if(WFI_CMD == standbymodecmd){
142 __WFI();
143 }else{
144 __WFE();
145 }
146 }
147
156 void pmu_flag_clear(uint32_t flag_reset)
157 {
158 switch(flag_reset){
159 case PMU_FLAG_RESET_WAKEUP:
160 /* reset wakeup flag */
161 PMU_CTL |= PMU_CTL_WURST;
162 break;
163 case PMU_FLAG_RESET_STANDBY:
164 /* reset standby flag */
165 PMU_CTL |= PMU_CTL_STBRST;
166 break;
167 default :
168 break;
169 }
170 }
171
181 FlagStatus pmu_flag_get(uint32_t flag)
182 {
183 if(PMU_CS & flag){
184 return SET;
185 }else{
186 return RESET;
187 }
188 }
189
196 void pmu_backup_write_enable(void)
197 {
198 PMU_CTL |= PMU_CTL_BKPWEN;
199 }
200
207 void pmu_backup_write_disable(void)
208 {
209 PMU_CTL &= ~PMU_CTL_BKPWEN;
210 }
211
218 void pmu_wakeup_pin_enable(void)
219 {
220 PMU_CS |= PMU_CS_WUPEN;
221 }
222
229 void pmu_wakeup_pin_disable(void)
230 {
231 PMU_CS &= ~PMU_CS_WUPEN;
232 }
PMU_FLAG_RESET_STANDBY
#define PMU_FLAG_RESET_STANDBY
Definition: gd32f10x_pmu.h:64
pmu_lvd_disable
void pmu_lvd_disable(void)
disable PMU lvd
Definition: gd32f10x_pmu.c:60
PMU_FLAG_RESET_WAKEUP
#define PMU_FLAG_RESET_WAKEUP
Definition: gd32f10x_pmu.h:63
pmu_wakeup_pin_enable
void pmu_wakeup_pin_enable(void)
enable wakeup pin
Definition: gd32f10x_pmu.c:218
pmu_deinit
void pmu_deinit(void)
reset PMU register
Definition: gd32f10x_pmu.c:21
WFI_CMD
#define WFI_CMD
Definition: gd32f10x_pmu.h:67
pmu_backup_write_disable
void pmu_backup_write_disable(void)
disable backup domain write
Definition: gd32f10x_pmu.c:207
pmu_flag_get
FlagStatus pmu_flag_get(uint32_t flag)
get flag state
Definition: gd32f10x_pmu.c:181
PMU_CS_WUPEN
#define PMU_CS_WUPEN
Definition: gd32f10x_pmu.h:39
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f10x_pmu.h:28
gd32f10x_pmu.h
definitions for the PMU
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f10x_pmu.h:33
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f10x_pmu.h:31
PMU_CTL_LVDT
#define PMU_CTL_LVDT
Definition: gd32f10x_pmu.h:32
pmu_to_sleepmode
void pmu_to_sleepmode(uint8_t sleepmodecmd)
PMU work at sleep mode.
Definition: gd32f10x_pmu.c:74
pmu_backup_write_enable
void pmu_backup_write_enable(void)
enable backup domain write
Definition: gd32f10x_pmu.c:196
pmu_to_standbymode
void pmu_to_standbymode(uint8_t standbymodecmd)
pmu work at standby mode
Definition: gd32f10x_pmu.c:129
PMU_CS
#define PMU_CS
Definition: gd32f10x_pmu.h:23
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f10x_pmu.h:29
pmu_flag_clear
void pmu_flag_clear(uint32_t flag_reset)
clear flag bit
Definition: gd32f10x_pmu.c:156
pmu_to_deepsleepmode
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode.
Definition: gd32f10x_pmu.c:98
pmu_wakeup_pin_disable
void pmu_wakeup_pin_disable(void)
disable wakeup pin
Definition: gd32f10x_pmu.c:229
RCU_PMURST
Definition: gd32f10x_rcu.h:473
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
PMU_CTL
#define PMU_CTL
Definition: gd32f10x_pmu.h:22
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
pmu_lvd_select
void pmu_lvd_select(uint32_t lvdt_n)
select low voltage detector threshold
Definition: gd32f10x_pmu.c:42
PMU_CTL_STBRST
#define PMU_CTL_STBRST
Definition: gd32f10x_pmu.h:30
PMU_CTL_LDOLP
#define PMU_CTL_LDOLP
Definition: gd32f10x_pmu.h:27
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_crc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_CRC_H
14 #define GD32F10X_CRC_H
15
16 #include "gd32f10x.h"
17
18 /* CRC definitions */
19 #define CRC CRC_BASE
20
21 /* registers definitions */
22 #define CRC_DATA REG32(CRC + 0x00U)
23 #define CRC_FDATA REG32(CRC + 0x04U)
24 #define CRC_CTL REG32(CRC + 0x08U)
26 /* bits definitions */
27 /* CRC_DATA */
28 #define CRC_DATA_DATA BITS(0,31)
30 /* CRC_FDATA */
31 #define CRC_FDATA_FDATA BITS(0,7)
33 /* CRC_CTL */
34 #define CRC_CTL_RST BIT(0)
37 /* function declarations */
38 /* deinit CRC calculation unit */
39 void crc_deinit(void);
40
41 /* reset data register to the value of initializaiton data register */
42 void crc_data_register_reset(void);
43 /* read the data register */
44 uint32_t crc_data_register_read(void);
45
46 /* read the free data register */
47 uint8_t crc_free_data_register_read(void);
48 /* write the free data register */
49 void crc_free_data_register_write(uint8_t free_data);
50
51 /* CRC calculate a 32-bit data */
52 uint32_t crc_single_data_calculate(uint32_t sdata);
53 /* CRC calculate a 32-bit data array */
54 uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
55
56 #endif /* GD32F10X_CRC_H */
crc_data_register_read
uint32_t crc_data_register_read(void)
read the data register
Definition: gd32f10x_crc.c:45
crc_data_register_reset
void crc_data_register_reset(void)
reset data register to the value of initializaiton data register
Definition: gd32f10x_crc.c:34
crc_block_data_calculate
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
CRC calculate a 32-bit data array.
Definition: gd32f10x_crc.c:95
crc_free_data_register_read
uint8_t crc_free_data_register_read(void)
read the free data register
Definition: gd32f10x_crc.c:58
crc_free_data_register_write
void crc_free_data_register_write(uint8_t free_data)
write the free data register
Definition: gd32f10x_crc.c:71
crc_deinit
void crc_deinit(void)
deinit CRC calculation unit
Definition: gd32f10x_crc.c:21
crc_single_data_calculate
uint32_t crc_single_data_calculate(uint32_t sdata)
CRC calculate a 32-bit data.
Definition: gd32f10x_crc.c:82
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Source/usbd_int.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Source
usbd_int.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbd_int.h"
14
15 extern uint32_t g_interrupt_mask;
16 extern __IO uint8_t g_suspend_enabled;
17 extern __IO uint8_t g_remote_wakeup_on;
18 extern __IO uint8_t g_ESOF_count;
19
20 #ifdef LPM_ENABLED
21 __IO uint32_t L1_remote_wakeup = 0U;
22 __IO uint32_t L1_resume = 0U;
23 __IO uint32_t besl = 0U;
24 #endif /* LPM_ENABLED */
25
26 static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev);
27 static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev);
28 static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev);
29 static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev);
30 static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev);
31 static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev);
32
39 void usbd_isr (void)
40 {
41 __IO uint16_t interrupt_flag = 0U;
42 __IO uint16_t ctlr = 0U;
43
44 interrupt_flag = USBD_REG_GET(USBD_INTF);
45
46 if (g_interrupt_mask & INTF_STIF & interrupt_flag) {
47 /* the endpoint successful transfer interrupt service */
48 usbd_intf_lpst(&usb_device_dev);
49 }
50
51 if (g_interrupt_mask & INTF_WKUPIF & interrupt_flag) {
52 /* clear wakeup interrupt flag in INTF */
53 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_WKUPIF);
54
55 /* USB wakeup interrupt handle */
56 usbd_intf_wakeup(&usb_device_dev);
57
58 #ifdef LPM_ENABLED
59 /* clear L1 remote wakeup flag */
60 L1_remote_wakeup = 0;
61 #endif /* LPM_ENABLED */
62 }
63
64 if (g_interrupt_mask & INTF_SPSIF & interrupt_flag) {
65 if(!(USBD_REG_GET(USBD_CTL) & CTL_RSREQ)) {
66 /* process library core layer suspend routine*/
67 usbd_intf_suspend(&usb_device_dev);
68
69 /* clear of suspend interrupt flag bit must be done after setting of CTLR_SETSPS */
70 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SPSIF);
71 }
72 }
73
74 if (g_interrupt_mask & INTF_SOFIF & interrupt_flag) {
75 /* clear SOF interrupt flag in INTF */
76 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SOFIF);
77
78 /* USB SOF interrupt handle */
79 usbd_intf_sof(&usb_device_dev);
80 }
81
82 if (g_interrupt_mask & INTF_ESOFIF & interrupt_flag) {
83 /* clear ESOF interrupt flag in INTF */
84 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_ESOFIF);
85
86 /* USB ESOF interrupt handle */
87 usbd_intf_esof(&usb_device_dev);
88 }
89
90 if (g_interrupt_mask & INTF_RSTIF & interrupt_flag) {
91 /* clear reset interrupt flag in INTF */
92 USBD_REG_SET(USBD_INTF, (uint16_t)CLR_RSTIF);
93
94 /* USB reset interrupt handle */
95 usbd_intf_reset(&usb_device_dev);
96 }
97
98 #ifdef LPM_ENABLED
99 if (g_interrupt_mask & INTF_L1REQ & interrupt_flag) {
100 /* clear L1 ST bit in LPM INTF */
101 USBD_REG_SET(USBD_INTF, CLR_L1REQ);
102
103 /* read BESL field from subendpoint0 register which coressponds to HIRD parameter in LPM spec */
104 besl = (USBD_REG_GET(USBD_LPMCS) & LPMCS_BLSTAT) >> 4;
105
106 /* read BREMOTEWAKE bit from subendpoint0 register which corresponding to bRemoteWake bit in LPM request */
107 L1_remote_wakeup = (USBD_REG_GET(USBD_LPMCS) & LPMCS_REMWK) >> 8;
108
109 /* process USB device core layer suspend routine */
110 /* enter USB model in suspend and system in low power mode (DEEP_SLEEP mode) */
111 usbd_intf_suspend(&usb_device_dev);
112 }
113 #endif /* LPM_ENABLED */
114 }
115
122 static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev)
123 {
124 uint8_t ep_num = 0U;
125
126 __IO uint16_t int_status = 0U;
127 __IO uint16_t ep_value = 0U;
128
129 usb_ep_struct *ep = NULL;
130
131 /* wait till interrupts are not pending */
132 while (0U != ((int_status = USBD_REG_GET(USBD_INTF)) & (uint16_t)INTF_STIF)) {
133 /* get endpoint number and the value of control and state register */
134 ep_num = (uint8_t)(int_status & INTF_EPNUM);
135 ep_value = USBD_REG_GET(USBD_EPxCS(ep_num));
136
137 if (0U == (int_status & INTF_DIR)) {
138 /* handle the in direction transaction */
139
140 ep = &(pudev->in_ep[ep_num]);
141
142 if (0U != (ep_value & EPxCS_TX_ST)) {
143 /* clear successful transmit interrupt flag */
144 USBD_ENDP_TX_STAT_CLEAR(ep_num);
145
146 /* just handle single buffer situation */
147 ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT;
148
149 /* maybe mutiple packets */
150 ep->trs_buf += ep->trs_count;
151
152 usbd_in_transaction(pudev, ep_num);
153 }
154 } else {
155 /* handle the out direction transaction */
156
157 uint16_t count = 0U;
158
159 ep = &(pudev->out_ep[ep_num]);
160
161 if (0U != (ep_value & EPxCS_RX_ST)) {
162 /* clear successful receive interrupt flag */
163 USBD_ENDP_RX_STAT_CLEAR(ep_num);
164
165 count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT;
166
167 if (0U != count) {
168 if (0U != (ep_value & EPxCS_SETUP)) {
169 /* handle setup packet */
170 usbd_ep_data_read(&(pudev->setup_packet[0]), pbuf_reg->rx_addr, count);
171
172 /* enter setup status */
173 usbd_setup_transaction(pudev);
174
175 return USBD_OK;
176 } else {
177 usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count);
178 }
179 }
180
181 /* maybe mutiple packets */
182 ep->trs_count += count;
183 ep->trs_buf += count;
184 ep->trs_len -= count;
185
186 if ((0U == ep->trs_len) || (count < ep->maxpacket)) {
187 /* enter data OUT status */
188 usbd_out_transaction(pudev, ep_num);
189
190 ep->trs_count = 0U;
191 } else {
192 usbd_ep_rx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len);
193 }
194 }
195 }
196 }
197
198 return USBD_OK;
199 }
200
207 static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev)
208 {
209 /* if necessary, user can add code here */
210 if (NULL != usbd_int_fops) {
211 usbd_int_fops->SOF(pudev);
212 }
213
214 return USBD_OK;
215 }
216
223 static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev)
224 {
225 /* control resume time by ESOFs */
226 if (g_ESOF_count > 0U) {
227 g_ESOF_count--;
228
229 if (0U == g_ESOF_count) {
230 if (1U == g_remote_wakeup_on) {
231 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_RSREQ);
232
233 g_remote_wakeup_on = 0U;
234 } else {
235 USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ);
236
237 g_ESOF_count = 3U;
238 g_remote_wakeup_on = 1U;
239 }
240 }
241 }
242
243 return USBD_OK;
244 }
245
252 static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev)
253 {
254 uint8_t i;
255
256 g_free_buf_addr = ENDP_BUF_ADDR;
257
258 /* configure endpoint 0 buffer */
259 pbuf_reg->tx_addr = (uint16_t)g_free_buf_addr;
260 g_free_buf_addr += USBD_EP0_MAX_SIZE;
261
262 pbuf_reg->rx_addr = (uint16_t)g_free_buf_addr;
263 g_free_buf_addr += USBD_EP0_MAX_SIZE;
264
265 /* configure endpoint 0 Rx count */
266 if (USBD_EP0_MAX_SIZE > 62U) {
267 pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE << 5U) - 1U) | 0x8000U;
268 } else {
269 pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE + 1U) & ~1U) << 9U;
270 }
271
272 pudev->in_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE;
273 pudev->out_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE;
274
275 /* set endpoints address */
276 for (i = 0U; i < EP_COUNT; i++)
277 {
278 _EP_ADDR_SET(i, i);
279 }
280
281 USBD_REG_SET(USBD_EPxCS(EP0), EP_CONTROL | EPRX_VALID | EPTX_NAK);
282
283 /* set device address as default address 0 */
284 USBD_REG_SET(USBD_DADDR, DADDR_USBEN);
285
286 pudev->status = USBD_DEFAULT;
287
288 return USBD_OK;
289 }
290
297 static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev)
298 {
299 /* store the device current status */
300 pudev->prev_status = pudev->status;
301
302 /* set device in suspended state */
303 pudev->status = USBD_SUSPENDED;
304
305 /* enter USB in suspend and mcu system in low power mode */
306 if (g_suspend_enabled) {
307 usbd_suspend();
308 } else {
309 /* if not possible then resume after xx ms */
310 g_ESOF_count = 3U;
311 }
312
313 return USBD_OK;
314 }
315
322 static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev)
323 {
324 /* restore the old status */
325 pudev->status = pudev->prev_status;
326
327 #ifdef LPM_ENABLED
328 if ((0U == g_remote_wakeup_on) && (0U == L1_resume)) {
329 resume_mcu();
330 } else if (1U == g_remote_wakeup_on) {
331 /* no operation */
332 } else {
333 L1_resume = 0U;
334 }
335 #else
336 if (0U == g_remote_wakeup_on) {
337 resume_mcu();
338 }
339 #endif /* LPM_ENABLED */
340
341 return USBD_OK;
342 }
resume_mcu
void resume_mcu(void)
USB wakeup first operation is to wakeup mcu.
Definition: usbd_pwr.c:33
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
EPRX_VALID
#define EPRX_VALID
Definition: usbd_regs.h:127
usbd_int_fops
usbd_int_cb_struct * usbd_int_fops
g_ESOF_count
__IO uint8_t g_ESOF_count
Definition: usbd_pwr.c:19
INTF_STIF
#define INTF_STIF
Definition: usbd_regs.h:55
usbd_ep_data_read
void usbd_ep_data_read(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes)
read datas from USBRAM to user fifo
Definition: usbd_core.c:369
DADDR_USBEN
#define DADDR_USBEN
Definition: usbd_regs.h:75
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
EPxCS_TX_ST
#define EPxCS_TX_ST
Definition: usbd_regs.h:85
usbd_ep_buf_struct::rx_addr
uint16_t rx_addr
Definition: usbd_core.h:95
EP0
#define EP0
Definition: usbd_regs.h:189
USBD_LPMCS
#define USBD_LPMCS
Definition: usbd_regs.h:34
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
usbd_in_transaction
uint8_t usbd_in_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data in stage processing
Definition: usbd_std.c:155
USBD_REG_GET
#define USBD_REG_GET(reg)
Definition: usbd_regs.h:204
INTF_L1REQ
#define INTF_L1REQ
Definition: usbd_regs.h:63
usbd_ep_buf_struct::tx_addr
uint16_t tx_addr
Definition: usbd_core.h:91
usbd_core_handle_struct::setup_packet
uint8_t setup_packet[8]
Definition: usbd_core.h:135
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
USBD_DEFAULT
Definition: usbd_core.h:74
LPMCS_BLSTAT
#define LPMCS_BLSTAT
Definition: usbd_regs.h:91
usbd_int_cb_struct::SOF
uint8_t(* SOF)(usbd_core_handle_struct *pudev)
Definition: usbd_int.h:24
USBD_CTL
#define USBD_CTL
Definition: usbd_regs.h:24
EP_CONTROL
#define EP_CONTROL
Definition: usbd_regs.h:104
pbuf_reg
usbd_ep_buf_struct * pbuf_reg
Definition: usbd_core.c:19
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
usbd_suspend
void usbd_suspend(void)
set USB device to suspend mode
Definition: usbd_pwr.c:91
CLR_SPSIF
#define CLR_SPSIF
Definition: usbd_regs.h:142
INTF_SOFIF
#define INTF_SOFIF
Definition: usbd_regs.h:61
INTF_EPNUM
#define INTF_EPNUM
Definition: usbd_regs.h:65
USBD_SUSPENDED
Definition: usbd_core.h:77
usbd_core_handle_struct
Definition: usbd_core.h:125
CLR_ESOFIF
#define CLR_ESOFIF
Definition: usbd_regs.h:145
usbd_core_handle_struct::prev_status
uint8_t prev_status
Definition: usbd_core.h:130
USBD_ENDP_RX_STAT_CLEAR
#define USBD_ENDP_RX_STAT_CLEAR(ep_num)
Definition: usbd_regs.h:241
usb_ep_struct
Definition: usbd_core.h:102
g_interrupt_mask
uint32_t g_interrupt_mask
Definition: usbd_core.c:16
usbd_setup_transaction
uint8_t usbd_setup_transaction(usbd_core_handle_struct *pudev)
USB setup stage processing.
Definition: usbd_std.c:80
g_remote_wakeup_on
__IO uint8_t g_remote_wakeup_on
Definition: usbd_pwr.c:21
CLR_SOFIF
#define CLR_SOFIF
Definition: usbd_regs.h:144
LPMCS_REMWK
#define LPMCS_REMWK
Definition: usbd_regs.h:92
CLR_L1REQ
#define CLR_L1REQ
Definition: usbd_regs.h:146
USBD_OK
Definition: usbd_core.h:84
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
INTF_RSTIF
#define INTF_RSTIF
Definition: usbd_regs.h:60
USBD_ENDP_TX_STAT_CLEAR
#define USBD_ENDP_TX_STAT_CLEAR(ep_num)
Definition: usbd_regs.h:242
INTF_ESOFIF
#define INTF_ESOFIF
Definition: usbd_regs.h:62
INTF_SPSIF
#define INTF_SPSIF
Definition: usbd_regs.h:59
EPRCNT_CNT
#define EPRCNT_CNT
Definition: usbd_regs.h:133
_EP_ADDR_SET
#define _EP_ADDR_SET(ep_num, addr)
Definition: usbd_regs.h:206
EPxCS_RX_ST
#define EPxCS_RX_ST
Definition: usbd_regs.h:79
USBD_DADDR
#define USBD_DADDR
Definition: usbd_regs.h:27
INTF_DIR
#define INTF_DIR
Definition: usbd_regs.h:64
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
USBD_EPxCS
#define USBD_EPxCS(ep_id)
Definition: usbd_regs.h:31
usbd_out_transaction
uint8_t usbd_out_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data out stage processing
Definition: usbd_std.c:113
NULL
#define NULL
Definition: usbd_std.h:20
USBD_INTF
#define USBD_INTF
Definition: usbd_regs.h:25
CTL_RSREQ
#define CTL_RSREQ
Definition: usbd_regs.h:48
INTF_WKUPIF
#define INTF_WKUPIF
Definition: usbd_regs.h:58
ENDP_BUF_ADDR
#define ENDP_BUF_ADDR
Definition: usbd_core.h:45
usbd_isr
void usbd_isr(void)
USB interrupt events service routine.
Definition: usbd_int.c:39
g_suspend_enabled
__IO uint8_t g_suspend_enabled
Definition: usbd_pwr.c:20
CLR_WKUPIF
#define CLR_WKUPIF
Definition: usbd_regs.h:141
usbd_core_handle_struct::status
uint8_t status
Definition: usbd_core.h:129
USBD_EP0_MAX_SIZE
#define USBD_EP0_MAX_SIZE
Definition: usbd_core.h:31
usbd_ep_buf_struct::rx_count
uint16_t rx_count
Definition: usbd_core.h:97
CLR_RSTIF
#define CLR_RSTIF
Definition: usbd_regs.h:143
g_free_buf_addr
uint32_t g_free_buf_addr
Definition: usbd_core.c:17
EPTX_NAK
#define EPTX_NAK
Definition: usbd_regs.h:117
EPTCNT_CNT
#define EPTCNT_CNT
Definition: usbd_regs.h:135
usb_device_dev
usbd_core_handle_struct usb_device_dev
EPxCS_SETUP
#define EPxCS_SETUP
Definition: usbd_regs.h:82
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_pmu.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_PMU_H
14 #define GD32F10X_PMU_H
15
16 #include "gd32f10x.h"
17
18 /* PMU definitions */
19 #define PMU PMU_BASE
21 /* registers definitions */
22 #define PMU_CTL REG32((PMU) + 0x00U)
23 #define PMU_CS REG32((PMU) + 0x04U)
25 /* bits definitions */
26 /* PMU_CTL */
27 #define PMU_CTL_LDOLP BIT(0)
28 #define PMU_CTL_STBMOD BIT(1)
29 #define PMU_CTL_WURST BIT(2)
30 #define PMU_CTL_STBRST BIT(3)
31 #define PMU_CTL_LVDEN BIT(4)
32 #define PMU_CTL_LVDT BITS(5,7)
33 #define PMU_CTL_BKPWEN BIT(8)
35 /* PMU_CS */
36 #define PMU_CS_WUF BIT(0)
37 #define PMU_CS_STBF BIT(1)
38 #define PMU_CS_LVDF BIT(2)
39 #define PMU_CS_WUPEN BIT(8)
41 /* constants definitions */
42 /* PMU low voltage detector threshold definitions */
43 #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5))
44 #define PMU_LVDT_0 CTL_LVDT(0)
45 #define PMU_LVDT_1 CTL_LVDT(1)
46 #define PMU_LVDT_2 CTL_LVDT(2)
47 #define PMU_LVDT_3 CTL_LVDT(3)
48 #define PMU_LVDT_4 CTL_LVDT(4)
49 #define PMU_LVDT_5 CTL_LVDT(5)
50 #define PMU_LVDT_6 CTL_LVDT(6)
51 #define PMU_LVDT_7 CTL_LVDT(7)
53 /* PMU flag definitions */
54 #define PMU_FLAG_WAKEUP PMU_CS_WUF
55 #define PMU_FLAG_STANDBY PMU_CS_STBF
56 #define PMU_FLAG_LVD PMU_CS_LVDF
58 /* PMU ldo definitions */
59 #define PMU_LDO_NORMAL ((uint32_t)0x00000000U)
60 #define PMU_LDO_LOWPOWER PMU_CTL_LDOLP
62 /* PMU flag reset definitions */
63 #define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U)
64 #define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U)
66 /* PMU command constants definitions */
67 #define WFI_CMD ((uint8_t)0x00U)
68 #define WFE_CMD ((uint8_t)0x01U)
70 /* function declarations */
71 /* reset PMU registers */
72 void pmu_deinit(void);
73
74 /* select low voltage detector threshold */
75 void pmu_lvd_select(uint32_t lvdt_n);
76 /* disable PMU lvd */
77 void pmu_lvd_disable(void);
78
79 /* set PMU mode */
80 /* PMU work at sleep mode */
81 void pmu_to_sleepmode(uint8_t sleepmodecmd);
82 /* PMU work at deepsleep mode */
83 void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
84 /* PMU work at standby mode */
85 void pmu_to_standbymode(uint8_t standbymodecmd);
86 /* enable PMU wakeup pin */
87 void pmu_wakeup_pin_enable(void);
88 /* disable PMU wakeup pin */
89 void pmu_wakeup_pin_disable(void);
90
91 /* backup related functions */
92 /* enable backup domain write */
93 void pmu_backup_write_enable(void);
94 /* disable backup domain write */
95 void pmu_backup_write_disable(void);
96
97 /* flag functions */
98 /* clear flag bit */
99 void pmu_flag_clear(uint32_t flag_reset);
100 /* get flag state */
101 FlagStatus pmu_flag_get(uint32_t flag);
102
103 #endif /* GD32F10X_PMU_H */
pmu_wakeup_pin_disable
void pmu_wakeup_pin_disable(void)
disable wakeup pin
Definition: gd32f10x_pmu.c:229
pmu_lvd_disable
void pmu_lvd_disable(void)
disable PMU lvd
Definition: gd32f10x_pmu.c:60
pmu_lvd_select
void pmu_lvd_select(uint32_t lvdt_n)
select low voltage detector threshold
Definition: gd32f10x_pmu.c:42
pmu_backup_write_disable
void pmu_backup_write_disable(void)
disable backup domain write
Definition: gd32f10x_pmu.c:207
pmu_flag_get
FlagStatus pmu_flag_get(uint32_t flag)
get flag state
Definition: gd32f10x_pmu.c:181
pmu_wakeup_pin_enable
void pmu_wakeup_pin_enable(void)
enable wakeup pin
Definition: gd32f10x_pmu.c:218
pmu_deinit
void pmu_deinit(void)
reset PMU register
Definition: gd32f10x_pmu.c:21
pmu_to_standbymode
void pmu_to_standbymode(uint8_t standbymodecmd)
pmu work at standby mode
Definition: gd32f10x_pmu.c:129
pmu_to_sleepmode
void pmu_to_sleepmode(uint8_t sleepmodecmd)
PMU work at sleep mode.
Definition: gd32f10x_pmu.c:74
pmu_flag_clear
void pmu_flag_clear(uint32_t flag_reset)
clear flag bit
Definition: gd32f10x_pmu.c:156
pmu_backup_write_enable
void pmu_backup_write_enable(void)
enable backup domain write
Definition: gd32f10x_pmu.c:196
pmu_to_deepsleepmode
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode.
Definition: gd32f10x_pmu.c:98
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_spi.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_spi.h"
14
15 #define SPI_INIT_MASK ((uint32_t)0x00003040U)
16 #define I2S_INIT_MASK ((uint32_t)0x0000F047U)
18 #define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */
19 #define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */
20 #define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */
21 #define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */
22
29 void spi_i2s_deinit(uint32_t spi_periph)
30 {
31 switch(spi_periph){
32 case SPI0:
33 /* reset SPI0 */
34 rcu_periph_reset_enable(RCU_SPI0RST);
35 rcu_periph_reset_disable(RCU_SPI0RST);
36 break;
37 case SPI1:
38 /* reset SPI1 and I2S1 */
39 rcu_periph_reset_enable(RCU_SPI1RST);
40 rcu_periph_reset_disable(RCU_SPI1RST);
41 break;
42 case SPI2:
43 /* reset SPI2 and I2S2 */
44 rcu_periph_reset_enable(RCU_SPI2RST);
45 rcu_periph_reset_disable(RCU_SPI2RST);
46 break;
47 default :
48 break;
49 }
50 }
51
69 void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
70 {
71 uint32_t reg = 0U;
72 reg = SPI_CTL0(spi_periph);
73 reg &= SPI_INIT_MASK;
74
75 /* select SPI as master or slave */
76 reg |= spi_struct->device_mode;
77 /* select SPI transfer mode */
78 reg |= spi_struct->trans_mode;
79 /* select SPI frame size */
80 reg |= spi_struct->frame_size;
81 /* select SPI NSS use hardware or software */
82 reg |= spi_struct->nss;
83 /* select SPI LSB or MSB */
84 reg |= spi_struct->endian;
85 /* select SPI polarity and phase */
86 reg |= spi_struct->clock_polarity_phase;
87 /* select SPI prescale to adjust transmit speed */
88 reg |= spi_struct->prescale;
89
90 /* write to SPI_CTL0 register */
91 SPI_CTL0(spi_periph) = (uint32_t)reg;
92
93 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
94 }
95
102 void spi_enable(uint32_t spi_periph)
103 {
104 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
105 }
106
113 void spi_disable(uint32_t spi_periph)
114 {
115 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
116 }
117
138 void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
139 {
140 uint32_t reg = 0U;
141 reg = SPI_I2SCTL(spi_periph);
142 reg &= I2S_INIT_MASK;
143
144 /* enable I2S mode */
145 reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
146 /* select I2S mode */
147 reg |= (uint32_t)mode;
148 /* select I2S standard */
149 reg |= (uint32_t)standard;
150 /* select I2S polarity */
151 reg |= (uint32_t)ckpl;
152
153 /* write to SPI_I2SCTL register */
154 SPI_I2SCTL(spi_periph) = (uint32_t)reg;
155 }
156
181 void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
182 {
183 uint32_t i2sdiv = 2U, i2sof = 0U;
184 uint32_t clks = 0U;
185 uint32_t i2sclock = 0U;
186
187 /* deinit SPI_I2SPSC register */
188 SPI_I2SPSC(spi_periph) = 0x0002U;
189
190 #ifdef GD32F10X_CL
191 /* get the I2S clock source */
192 if(((uint32_t)spi_periph) == SPI1){
193 /* I2S1 clock source selection */
194 clks = I2S1_CLOCK_SEL;
195 }else{
196 /* I2S2 clock source selection */
197 clks = I2S2_CLOCK_SEL;
198 }
199
200 if(0U != (RCU_CFG1 & clks)){
201 /* get RCU PLL2 clock multiplication factor */
202 clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U);
203
204 if((clks > 5U) && (clks < 15U)){
205 /* multiplier is between 8 and 14 */
206 clks += 2U;
207 }else{
208 if(15U == clks){
209 /* multiplier is 20 */
210 clks = 20U;
211 }
212 }
213
214 /* get the PREDV1 value */
215 i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U);
216 /* calculate i2sclock based on PLL2 and PREDV1 */
217 i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U);
218 }else{
219 /* get system clock */
220 i2sclock = rcu_clock_freq_get(CK_SYS);
221 }
222 #else
223 /* get system clock */
224 i2sclock = rcu_clock_freq_get(CK_SYS);
225 #endif /* GD32F10X_CL */
226
227 /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
228 if(I2S_MCKOUT_ENABLE == mckout){
229 clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
230 }else{
231 if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){
232 clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample);
233 }else{
234 clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample);
235 }
236 }
237
238 /* remove the floating point */
239 clks = (clks + 5U) / 10U;
240 i2sof = (clks & 0x00000001U);
241 i2sdiv = ((clks - i2sof) / 2U);
242 i2sof = (i2sof << 8U);
243
244 /* set the default values */
245 if((i2sdiv < 2U) || (i2sdiv > 255U)){
246 i2sdiv = 2U;
247 i2sof = 0U;
248 }
249
250 /* configure SPI_I2SPSC */
251 SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout);
252
253 /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
254 SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
255 /* configure data frame format */
256 SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat;
257 }
258
265 void i2s_enable(uint32_t spi_periph)
266 {
267 SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
268 }
269
276 void i2s_disable(uint32_t spi_periph)
277 {
278 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
279 }
280
287 void spi_nss_output_enable(uint32_t spi_periph)
288 {
289 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
290 }
291
298 void spi_nss_output_disable(uint32_t spi_periph)
299 {
300 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
301 }
302
309 void spi_nss_internal_high(uint32_t spi_periph)
310 {
311 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
312 }
313
320 void spi_nss_internal_low(uint32_t spi_periph)
321 {
322 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
323 }
324
334 void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
335 {
336 if(SPI_DMA_TRANSMIT == dma){
337 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
338 }else{
339 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
340 }
341 }
342
352 void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
353 {
354 if(SPI_DMA_TRANSMIT == dma){
355 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
356 }else{
357 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
358 }
359 }
360
370 void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
371 {
372 /* clear SPI_CTL0_FF16 bit */
373 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
374 /* confige SPI_CTL0_FF16 bit */
375 SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
376 }
377
385 void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
386 {
387 SPI_DATA(spi_periph) = (uint32_t)data;
388 }
389
396 uint16_t spi_i2s_data_receive(uint32_t spi_periph)
397 {
398 return ((uint16_t)SPI_DATA(spi_periph));
399 }
400
409 void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
410 {
411 if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
412 /* set the transmit only mode */
413 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
414 }else{
415 /* set the receive only mode */
416 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
417 }
418 }
419
431 void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
432 {
433 switch(interrupt){
434 /* SPI/I2S transmit buffer empty interrupt */
435 case SPI_I2S_INT_TBE:
436 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
437 break;
438 /* SPI/I2S receive buffer not empty interrupt */
439 case SPI_I2S_INT_RBNE:
440 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
441 break;
442 /* SPI/I2S error */
443 case SPI_I2S_INT_ERR:
444 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
445 break;
446 default:
447 break;
448 }
449 }
450
462 void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
463 {
464 switch(interrupt){
465 /* SPI/I2S transmit buffer empty interrupt */
466 case SPI_I2S_INT_TBE:
467 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
468 break;
469 /* SPI/I2S receive buffer not empty interrupt */
470 case SPI_I2S_INT_RBNE:
471 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
472 break;
473 /* SPI/I2S error */
474 case SPI_I2S_INT_ERR:
475 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
476 break;
477 default :
478 break;
479 }
480 }
481
495 FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
496 {
497 uint32_t reg1 = SPI_STAT(spi_periph);
498 uint32_t reg2 = SPI_CTL1(spi_periph);
499
500 switch(interrupt){
501 /* SPI/I2S transmit buffer empty interrupt */
502 case SPI_I2S_INT_FLAG_TBE:
503 reg1 = reg1 & SPI_STAT_TBE;
504 reg2 = reg2 & SPI_CTL1_TBEIE;
505 break;
506 /* SPI/I2S receive buffer not empty interrupt */
507 case SPI_I2S_INT_FLAG_RBNE:
508 reg1 = reg1 & SPI_STAT_RBNE;
509 reg2 = reg2 & SPI_CTL1_RBNEIE;
510 break;
511 /* SPI/I2S overrun interrupt */
512 case SPI_I2S_INT_FLAG_RXORERR:
513 reg1 = reg1 & SPI_STAT_RXORERR;
514 reg2 = reg2 & SPI_CTL1_ERRIE;
515 break;
516 /* SPI config error interrupt */
517 case SPI_INT_FLAG_CONFERR:
518 reg1 = reg1 & SPI_STAT_CONFERR;
519 reg2 = reg2 & SPI_CTL1_ERRIE;
520 break;
521 /* SPI CRC error interrupt */
522 case SPI_INT_FLAG_CRCERR:
523 reg1 = reg1 & SPI_STAT_CRCERR;
524 reg2 = reg2 & SPI_CTL1_ERRIE;
525 break;
526 /* I2S underrun error interrupt */
527 case I2S_INT_FLAG_TXURERR:
528 reg1 = reg1 & SPI_STAT_TXURERR;
529 reg2 = reg2 & SPI_CTL1_ERRIE;
530 break;
531 default :
532 break;
533 }
534 /*get SPI/I2S interrupt flag status */
535 if(reg1 && reg2){
536 return SET;
537 }else{
538 return RESET;
539 }
540 }
541
561 FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
562 {
563 if(SPI_STAT(spi_periph) & flag){
564 return SET;
565 }else{
566 return RESET;
567 }
568 }
569
576 void spi_crc_error_clear(uint32_t spi_periph)
577 {
578 SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
579 }
580
587 void spi_crc_on(uint32_t spi_periph)
588 {
589 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
590 }
591
598 void spi_crc_off(uint32_t spi_periph)
599 {
600 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
601 }
602
610 void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
611 {
612 /* set SPI CRC polynomial */
613 SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
614 }
615
622 uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
623 {
624 return ((uint16_t)SPI_CRCPOLY(spi_periph));
625 }
626
633 void spi_crc_next(uint32_t spi_periph)
634 {
635 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
636 }
637
647 uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
648 {
649 if(SPI_CRC_TX == crc){
650 return ((uint16_t)(SPI_TCRC(spi_periph)));
651 }else{
652 return ((uint16_t)(SPI_RCRC(spi_periph)));
653 }
654 }
spi_dma_disable
void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
disable SPI DMA send or receive
Definition: gd32f10x_spi.c:352
SPI_FLAG_CRCERR
#define SPI_FLAG_CRCERR
Definition: gd32f10x_spi.h:217
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f10x_spi.h:53
SPI_I2SCTL_I2SSEL
#define SPI_I2SCTL_I2SSEL
Definition: gd32f10x_spi.h:89
spi_i2s_interrupt_enable
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
enable SPI and I2S interrupt
Definition: gd32f10x_spi.c:431
i2s_enable
void i2s_enable(uint32_t spi_periph)
enable I2S
Definition: gd32f10x_spi.c:265
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f10x_spi.h:204
SPI_STAT_CONFERR
#define SPI_STAT_CONFERR
Definition: gd32f10x_spi.h:65
spi_parameter_struct::nss
uint32_t nss
Definition: gd32f10x_spi.h:103
SPI_STAT_TBE
#define SPI_STAT_TBE
Definition: gd32f10x_spi.h:61
spi_parameter_struct::device_mode
uint32_t device_mode
Definition: gd32f10x_spi.h:100
spi_nss_internal_high
void spi_nss_internal_high(uint32_t spi_periph)
SPI NSS pin high level in software mode.
Definition: gd32f10x_spi.c:309
SPI_INT_FLAG_CRCERR
#define SPI_INT_FLAG_CRCERR
Definition: gd32f10x_spi.h:211
spi_enable
void spi_enable(uint32_t spi_periph)
enable SPI
Definition: gd32f10x_spi.c:102
SPI_BIDIRECTIONAL_RECEIVE
#define SPI_BIDIRECTIONAL_RECEIVE
Definition: gd32f10x_spi.h:115
spi_crc_on
void spi_crc_on(uint32_t spi_periph)
turn on CRC function
Definition: gd32f10x_spi.c:587
spi_nss_output_enable
void spi_nss_output_enable(uint32_t spi_periph)
enable SPI NSS output
Definition: gd32f10x_spi.c:287
SPI1
#define SPI1
Definition: gd32f10x_spi.h:20
SPI_CTL0_FF16
#define SPI_CTL0_FF16
Definition: gd32f10x_spi.h:45
RCU_SPI1RST
Definition: gd32f10x_rcu.h:457
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f10x_spi.h:28
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f10x_spi.h:47
spi_i2s_data_receive
uint16_t spi_i2s_data_receive(uint32_t spi_periph)
SPI receive data.
Definition: gd32f10x_spi.c:396
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f10x_spi.h:55
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f10x_spi.h:203
spi_parameter_struct::frame_size
uint32_t frame_size
Definition: gd32f10x_spi.h:102
spi_i2s_data_frame_format_config
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
configure SPI/I2S data frame format
Definition: gd32f10x_spi.c:370
SPI_I2S_INT_FLAG_TBE
#define SPI_I2S_INT_FLAG_TBE
Definition: gd32f10x_spi.h:207
I2S_CLOCK_DIV_MASK
#define I2S_CLOCK_DIV_MASK
Definition: gd32f10x_spi.c:21
SPI_STAT_CRCERR
#define SPI_STAT_CRCERR
Definition: gd32f10x_spi.h:64
SPI_STAT_TXURERR
#define SPI_STAT_TXURERR
Definition: gd32f10x_spi.h:63
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f10x_spi.h:42
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f10x_spi.h:202
SPI0
#define SPI0
Definition: gd32f10x_spi.h:19
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f10x_spi.h:194
SPI2
#define SPI2
Definition: gd32f10x_spi.h:21
spi_disable
void spi_disable(uint32_t spi_periph)
disable SPI
Definition: gd32f10x_spi.c:113
SPI_CRC_TX
#define SPI_CRC_TX
Definition: gd32f10x_spi.h:198
spi_parameter_struct::trans_mode
uint32_t trans_mode
Definition: gd32f10x_spi.h:101
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f10x_spi.h:52
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f10x_spi.h:31
CK_SYS
Definition: gd32f10x_rcu.h:584
SPI_I2S_INT_FLAG_RBNE
#define SPI_I2S_INT_FLAG_RBNE
Definition: gd32f10x_spi.h:208
I2S2_CLOCK_SEL
#define I2S2_CLOCK_SEL
Definition: gd32f10x_spi.c:19
gd32f10x_spi.h
definitions for the SPI
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
i2s_init
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
initialize I2S parameter
Definition: gd32f10x_spi.c:138
spi_crc_get
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
get SPI CRC send value or receive value
Definition: gd32f10x_spi.c:647
SPI_CTL0_CRCNT
#define SPI_CTL0_CRCNT
Definition: gd32f10x_spi.h:46
spi_parameter_struct::endian
uint32_t endian
Definition: gd32f10x_spi.h:104
spi_crc_polynomial_set
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
set CRC polynomial
Definition: gd32f10x_spi.c:610
SPI_INIT_MASK
#define SPI_INIT_MASK
Definition: gd32f10x_spi.c:15
spi_parameter_struct
Definition: gd32f10x_spi.h:98
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f10x_spi.h:27
spi_crc_off
void spi_crc_off(uint32_t spi_periph)
turn off CRC function
Definition: gd32f10x_spi.c:598
RCU_SPI2RST
Definition: gd32f10x_rcu.h:458
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f10x_spi.h:40
spi_i2s_flag_get
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
get SPI and I2S flag status
Definition: gd32f10x_spi.c:561
I2S_INIT_MASK
#define I2S_INIT_MASK
Definition: gd32f10x_spi.c:16
i2s_disable
void i2s_disable(uint32_t spi_periph)
disable I2S
Definition: gd32f10x_spi.c:276
spi_bidirectional_transfer_config
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
configure SPI bidirectional transfer direction
Definition: gd32f10x_spi.c:409
spi_i2s_interrupt_flag_get
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
get SPI and I2S interrupt flag status
Definition: gd32f10x_spi.c:495
spi_i2s_data_transmit
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
SPI transmit data.
Definition: gd32f10x_spi.c:385
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
spi_nss_internal_low
void spi_nss_internal_low(uint32_t spi_periph)
SPI NSS pin low level in software mode.
Definition: gd32f10x_spi.c:320
RCU_SPI0RST
Definition: gd32f10x_rcu.h:488
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
SPI_I2SCTL_DTLEN
#define SPI_I2SCTL_DTLEN
Definition: gd32f10x_spi.h:83
SPI_RCRC
#define SPI_RCRC(spix)
Definition: gd32f10x_spi.h:29
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f10x_spi.h:25
SPI_I2S_INT_FLAG_RXORERR
#define SPI_I2S_INT_FLAG_RXORERR
Definition: gd32f10x_spi.h:209
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f10x_spi.h:24
I2S_CLOCK_MUL_MASK
#define I2S_CLOCK_MUL_MASK
Definition: gd32f10x_spi.c:20
spi_init
void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct)
initialize SPI parameter
Definition: gd32f10x_spi.c:69
spi_crc_polynomial_get
uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
get SPI CRC polynomial
Definition: gd32f10x_spi.c:622
spi_dma_enable
void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
enable SPI DMA send or receive
Definition: gd32f10x_spi.c:334
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f10x_spi.h:54
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f10x_spi.h:26
SPI_BIDIRECTIONAL_TRANSMIT
#define SPI_BIDIRECTIONAL_TRANSMIT
Definition: gd32f10x_spi.h:114
spi_crc_error_clear
void spi_crc_error_clear(uint32_t spi_periph)
clear SPI CRC error flag status
Definition: gd32f10x_spi.c:576
spi_parameter_struct::clock_polarity_phase
uint32_t clock_polarity_phase
Definition: gd32f10x_spi.h:105
I2S_MCKOUT_ENABLE
#define I2S_MCKOUT_ENABLE
Definition: gd32f10x_spi.h:172
SPI_I2SCTL_I2SEN
#define SPI_I2SCTL_I2SEN
Definition: gd32f10x_spi.h:88
I2S_INT_FLAG_TXURERR
#define I2S_INT_FLAG_TXURERR
Definition: gd32f10x_spi.h:212
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f10x_spi.h:56
I2S_FRAMEFORMAT_DT16B_CH16B
#define I2S_FRAMEFORMAT_DT16B_CH16B
Definition: gd32f10x_spi.h:165
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f10x_spi.h:57
SPI_TCRC
#define SPI_TCRC(spix)
Definition: gd32f10x_spi.h:30
SPI_INT_FLAG_CONFERR
#define SPI_INT_FLAG_CONFERR
Definition: gd32f10x_spi.h:210
spi_nss_output_disable
void spi_nss_output_disable(uint32_t spi_periph)
disable SPI NSS output
Definition: gd32f10x_spi.c:298
spi_i2s_interrupt_disable
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
disable SPI and I2S interrupt
Definition: gd32f10x_spi.c:462
spi_parameter_struct::prescale
uint32_t prescale
Definition: gd32f10x_spi.h:106
SPI_I2SPSC
#define SPI_I2SPSC(spix)
Definition: gd32f10x_spi.h:32
SPI_STAT_RXORERR
#define SPI_STAT_RXORERR
Definition: gd32f10x_spi.h:66
SPI_STAT_RBNE
#define SPI_STAT_RBNE
Definition: gd32f10x_spi.h:60
SPI_I2SCTL_CHLEN
#define SPI_I2SCTL_CHLEN
Definition: gd32f10x_spi.h:82
spi_crc_next
void spi_crc_next(uint32_t spi_periph)
SPI next data is CRC value.
Definition: gd32f10x_spi.c:633
spi_i2s_deinit
void spi_i2s_deinit(uint32_t spi_periph)
reset SPI and I2S
Definition: gd32f10x_spi.c:29
i2s_psc_config
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
configure I2S prescaler
Definition: gd32f10x_spi.c:181
I2S1_CLOCK_SEL
#define I2S1_CLOCK_SEL
Definition: gd32f10x_spi.c:18
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_enet.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10x_ENET_H
14 #define GD32F10x_ENET_H
15
16 #include "gd32f10x.h"
17 #include <stdlib.h>
18
19 #define IF_USE_EXTERNPHY_LIB 0
20 #if (1 == IF_USE_EXTERNPHY_LIB)
21 #include "phy.h"
22 #endif
23
24 #ifndef ENET_RXBUF_NUM
25 #define ENET_RXBUF_NUM 5U
26 #endif
27
28 #ifndef ENET_TXBUF_NUM
29 #define ENET_TXBUF_NUM 5U
30 #endif
31
32 #ifndef ENET_RXBUF_SIZE
33 #define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE
34 #endif
35
36 #ifndef ENET_TXBUF_SIZE
37 #define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE
38 #endif
39
40 /* #define USE_DELAY */
41
42 #ifndef _PHY_H_
43 #define DP83848 0
44 #define LAN8700 1
45 #define PHY_TYPE DP83848
46
47 #define PHY_ADDRESS ((uint16_t)1U)
49 /* PHY read write timeouts */
50 #define PHY_READ_TO ((uint32_t)0x0004FFFFU)
51 #define PHY_WRITE_TO ((uint32_t)0x0004FFFFU)
53 /* PHY delay */
54 #define PHY_RESETDELAY ((uint32_t)0x008FFFFFU)
55 #define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU)
57 /* PHY register address */
58 #define PHY_REG_BCR 0U
59 #define PHY_REG_BSR 1U
61 /* PHY basic control register */
62 #define PHY_RESET ((uint16_t)0x8000)
63 #define PHY_LOOPBACK ((uint16_t)0x4000)
64 #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100)
65 #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000)
66 #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100)
67 #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000)
68 #define PHY_AUTONEGOTIATION ((uint16_t)0x1000)
69 #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200)
70 #define PHY_POWERDOWN ((uint16_t)0x0800)
71 #define PHY_ISOLATE ((uint16_t)0x0400)
73 /* PHY basic status register */
74 #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020)
75 #define PHY_LINKED_STATUS ((uint16_t)0x0004)
76 #define PHY_JABBER_DETECTION ((uint16_t)0x0002)
78 #if(PHY_TYPE == LAN8700)
79 #define PHY_SR 31U
80 #define PHY_SPEED_STATUS ((uint16_t)0x0004)
81 #define PHY_DUPLEX_STATUS ((uint16_t)0x0010)
82 #elif(PHY_TYPE == DP83848)
83 #define PHY_SR 16U
84 #define PHY_SPEED_STATUS ((uint16_t)0x0002)
85 #define PHY_DUPLEX_STATUS ((uint16_t)0x0004)
86 #endif /* PHY_TYPE */
87
88 #endif /* _PHY_H_ */
89
90
91 /* ENET definitions */
92 #define ENET ENET_BASE
93
94 /* registers definitions */
95 #define ENET_MAC_CFG REG32((ENET) + 0x00U)
96 #define ENET_MAC_FRMF REG32((ENET) + 0x04U)
97 #define ENET_MAC_HLH REG32((ENET) + 0x08U)
98 #define ENET_MAC_HLL REG32((ENET) + 0x0CU)
99 #define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U)
100 #define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U)
101 #define ENET_MAC_FCTL REG32((ENET) + 0x18U)
102 #define ENET_MAC_FCTH REG32((ENET) + 0x1080U)
103 #define ENET_MAC_VLT REG32((ENET) + 0x1CU)
104 #define ENET_MAC_RWFF REG32((ENET) + 0x28U)
105 #define ENET_MAC_WUM REG32((ENET) + 0x2CU)
106 #define ENET_MAC_INTF REG32((ENET) + 0x38U)
107 #define ENET_MAC_INTMSK REG32((ENET) + 0x3CU)
108 #define ENET_MAC_ADDR0H REG32((ENET) + 0x40U)
109 #define ENET_MAC_ADDR0L REG32((ENET) + 0x44U)
110 #define ENET_MAC_ADDR1H REG32((ENET) + 0x48U)
111 #define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU)
112 #define ENET_MAC_ADDT2H REG32((ENET) + 0x50U)
113 #define ENET_MAC_ADDR2L REG32((ENET) + 0x54U)
114 #define ENET_MAC_ADDR3H REG32((ENET) + 0x58U)
115 #define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU)
117 #define ENET_MSC_CTL REG32((ENET) + 0x100U)
118 #define ENET_MSC_RINTF REG32((ENET) + 0x104U)
119 #define ENET_MSC_TINTF REG32((ENET) + 0x108U)
120 #define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU)
121 #define ENET_MSC_TINTMSK REG32((ENET) + 0x110U)
122 #define ENET_MSC_SCCNT REG32((ENET) + 0x14CU)
123 #define ENET_MSC_MSCCNT REG32((ENET) + 0x150U)
124 #define ENET_MSC_TGFCNT REG32((ENET) + 0x168U)
125 #define ENET_MSC_RFCECNT REG32((ENET) + 0x194U)
126 #define ENET_MSC_RFAECNT REG32((ENET) + 0x198U)
127 #define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U)
129 #define ENET_PTP_TSCTL REG32((ENET) + 0x700U)
130 #define ENET_PTP_SSINC REG32((ENET) + 0x704U)
131 #define ENET_PTP_TSH REG32((ENET) + 0x708U)
132 #define ENET_PTP_TSL REG32((ENET) + 0x70CU)
133 #define ENET_PTP_TSUH REG32((ENET) + 0x710U)
134 #define ENET_PTP_TSUL REG32((ENET) + 0x714U)
135 #define ENET_PTP_TSADDEND REG32((ENET) + 0x718U)
136 #define ENET_PTP_ETH REG32((ENET) + 0x71CU)
137 #define ENET_PTP_ETL REG32((ENET) + 0x720U)
139 #define ENET_DMA_BCTL REG32((ENET) + 0x1000U)
140 #define ENET_DMA_TPEN REG32((ENET) + 0x1004U)
141 #define ENET_DMA_RPEN REG32((ENET) + 0x1008U)
142 #define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU)
143 #define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U)
144 #define ENET_DMA_STAT REG32((ENET) + 0x1014U)
145 #define ENET_DMA_CTL REG32((ENET) + 0x1018U)
146 #define ENET_DMA_INTEN REG32((ENET) + 0x101CU)
147 #define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U)
148 #define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U)
149 #define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU)
150 #define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U)
151 #define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U)
153 /* bits definitions */
154 /* ENET_MAC_CFG */
155 #define ENET_MAC_CFG_REN BIT(2)
156 #define ENET_MAC_CFG_TEN BIT(3)
157 #define ENET_MAC_CFG_DFC BIT(4)
158 #define ENET_MAC_CFG_BOL BITS(5,6)
159 #define ENET_MAC_CFG_APCD BIT(7)
160 #define ENET_MAC_CFG_RTD BIT(9)
161 #define ENET_MAC_CFG_IPFCO BIT(10)
162 #define ENET_MAC_CFG_DPM BIT(11)
163 #define ENET_MAC_CFG_LBM BIT(12)
164 #define ENET_MAC_CFG_ROD BIT(13)
165 #define ENET_MAC_CFG_SPD BIT(14)
166 #define ENET_MAC_CFG_CSD BIT(16)
167 #define ENET_MAC_CFG_IGBS BITS(17,19)
168 #define ENET_MAC_CFG_JBD BIT(22)
169 #define ENET_MAC_CFG_WDD BIT(23)
171 /* ENET_MAC_FRMF */
172 #define ENET_MAC_FRMF_PM BIT(0)
173 #define ENET_MAC_FRMF_HUF BIT(1)
174 #define ENET_MAC_FRMF_HMF BIT(2)
175 #define ENET_MAC_FRMF_DAIFLT BIT(3)
176 #define ENET_MAC_FRMF_MFD BIT(4)
177 #define ENET_MAC_FRMF_BFRMD BIT(5)
178 #define ENET_MAC_FRMF_PCFRM BITS(6,7)
179 #define ENET_MAC_FRMF_SAIFLT BIT(8)
180 #define ENET_MAC_FRMF_SAFLT BIT(9)
181 #define ENET_MAC_FRMF_HPFLT BIT(10)
182 #define ENET_MAC_FRMF_FAR BIT(31)
184 /* ENET_MAC_HLH */
185 #define ENET_MAC_HLH_HLH BITS(0,31)
187 /* ENET_MAC_HLL */
188 #define ENET_MAC_HLL_HLL BITS(0,31)
190 /* ENET_MAC_PHY_CTL */
191 #define ENET_MAC_PHY_CTL_PB BIT(0)
192 #define ENET_MAC_PHY_CTL_PW BIT(1)
193 #define ENET_MAC_PHY_CTL_CLR BITS(2,4)
194 #define ENET_MAC_PHY_CTL_PR BITS(6,10)
195 #define ENET_MAC_PHY_CTL_PA BITS(11,15)
197 /* ENET_MAC_PHY_DATA */
198 #define ENET_MAC_PHY_DATA_PD BITS(0,15)
200 /* ENET_MAC_FCTL */
201 #define ENET_MAC_FCTL_FLCBBKPA BIT(0)
202 #define ENET_MAC_FCTL_TFCEN BIT(1)
203 #define ENET_MAC_FCTL_RFCEN BIT(2)
204 #define ENET_MAC_FCTL_UPFDT BIT(3)
205 #define ENET_MAC_FCTL_PLTS BITS(4,5)
206 #define ENET_MAC_FCTL_DZQP BIT(7)
207 #define ENET_MAC_FCTL_PTM BITS(16,31)
209 /* ENET_MAC_FCTH */
210 #define ENET_MAC_FCTH_RFA BITS(0,2)
211 #define ENET_MAC_FCTH_RFD BITS(4,6)
213 /* ENET_MAC_VLT */
214 #define ENET_MAC_VLT_VLTI BITS(0,15)
215 #define ENET_MAC_VLT_VLTC BIT(16)
217 /* ENET_MAC_RWFF */
218 #define ENET_MAC_RWFF_DATA BITS(0,31)
220 /* ENET_MAC_WUM */
221 #define ENET_MAC_WUM_PWD BIT(0)
222 #define ENET_MAC_WUM_MPEN BIT(1)
223 #define ENET_MAC_WUM_WFEN BIT(2)
224 #define ENET_MAC_WUM_MPKR BIT(5)
225 #define ENET_MAC_WUM_WUFR BIT(6)
226 #define ENET_MAC_WUM_GU BIT(9)
227 #define ENET_MAC_WUM_WUFFRPR BIT(31)
229 /* ENET_MAC_INTF */
230 #define ENET_MAC_INTF_WUM BIT(3)
231 #define ENET_MAC_INTF_MSC BIT(4)
232 #define ENET_MAC_INTF_MSCR BIT(5)
233 #define ENET_MAC_INTF_MSCT BIT(6)
234 #define ENET_MAC_INTF_TMST BIT(9)
236 /* ENET_MAC_INTMSK */
237 #define ENET_MAC_INTMSK_WUMIM BIT(3)
238 #define ENET_MAC_INTMSK_TMSTIM BIT(9)
240 /* ENET_MAC_ADDR0H */
241 #define ENET_MAC_ADDR0H_ADDR0H BITS(0,15)
242 #define ENET_MAC_ADDR0H_MO BIT(31)
244 /* ENET_MAC_ADDR0L */
245 #define ENET_MAC_ADDR0L_ADDR0L BITS(0,31)
247 /* ENET_MAC_ADDR1H */
248 #define ENET_MAC_ADDR1H_ADDR1H BITS(0,15)
249 #define ENET_MAC_ADDR1H_MB BITS(24,29)
250 #define ENET_MAC_ADDR1H_SAF BIT(30)
251 #define ENET_MAC_ADDR1H_AFE BIT(31)
253 /* ENET_MAC_ADDR1L */
254 #define ENET_MAC_ADDR1L_ADDR1L BITS(0,31)
256 /* ENET_MAC_ADDR2H */
257 #define ENET_MAC_ADDR2H_ADDR2H BITS(0,15)
258 #define ENET_MAC_ADDR2H_MB BITS(24,29)
259 #define ENET_MAC_ADDR2H_SAF BIT(30)
260 #define ENET_MAC_ADDR2H_AFE BIT(31)
262 /* ENET_MAC_ADDR2L */
263 #define ENET_MAC_ADDR2L_ADDR2L BITS(0,31)
265 /* ENET_MAC_ADDR3H */
266 #define ENET_MAC_ADDR3H_ADDR3H BITS(0,15)
267 #define ENET_MAC_ADDR3H_MB BITS(24,29)
268 #define ENET_MAC_ADDR3H_SAF BIT(30)
269 #define ENET_MAC_ADDR3H_AFE BIT(31)
271 /* ENET_MAC_ADDR3L */
272 #define ENET_MAC_ADDR3L_ADDR3L BITS(0,31)
274 /* ENET_MSC_CTL */
275 #define ENET_MSC_CTL_CTR BIT(0)
276 #define ENET_MSC_CTL_CTSR BIT(1)
277 #define ENET_MSC_CTL_RTOR BIT(2)
278 #define ENET_MSC_CTL_MCFZ BIT(3)
280 /* ENET_MSC_RINTF */
281 #define ENET_MSC_RINTF_RFCE BIT(5)
282 #define ENET_MSC_RINTF_RFAE BIT(6)
283 #define ENET_MSC_RINTF_RGUF BIT(17)
285 /* ENET_MSC_TINTF */
286 #define ENET_MSC_TINTF_TGFSC BIT(14)
287 #define ENET_MSC_TINTF_TGFMSC BIT(15)
288 #define ENET_MSC_TINTF_TGF BIT(21)
290 /* ENET_MSC_RINTMSK */
291 #define ENET_MSC_RINTMSK_RFCEIM BIT(5)
292 #define ENET_MSC_RINTMSK_RFAEIM BIT(6)
293 #define ENET_MSC_RINTMSK_RGUFIM BIT(17)
295 /* ENET_MSC_TINTMSK */
296 #define ENET_MSC_TINTMSK_TGFSCIM BIT(14)
297 #define ENET_MSC_TINTMSK_TGFMSCIM BIT(15)
298 #define ENET_MSC_TINTMSK_TGFIM BIT(21)
300 /* ENET_MSC_SCCNT */
301 #define ENET_MSC_SCCNT_SCC BITS(0,31)
303 /* ENET_MSC_MSCCNT */
304 #define ENET_MSC_MSCCNT_MSCC BITS(0,31)
306 /* ENET_MSC_TGFCNT */
307 #define ENET_MSC_TGFCNT_TGF BITS(0,31)
309 /* ENET_MSC_RFCECNT */
310 #define ENET_MSC_RFCECNT_RFCER BITS(0,31)
312 /* ENET_MSC_RFAECNT */
313 #define ENET_MSC_RFAECNT_RFAER BITS(0,31)
315 /* ENET_MSC_RGUFCNT */
316 #define ENET_MSC_RGUFCNT_RGUF BITS(0,31)
318 /* ENET_PTP_TSCTL */
319 #define ENET_PTP_TSCTL_TMSEN BIT(0)
320 #define ENET_PTP_TSCTL_TMSFCU BIT(1)
321 #define ENET_PTP_TSCTL_TMSSTI BIT(2)
322 #define ENET_PTP_TSCTL_TMSSTU BIT(3)
323 #define ENET_PTP_TSCTL_TMSITEN BIT(4)
324 #define ENET_PTP_TSCTL_TMSARU BIT(5)
326 /* ENET_PTP_SSINC */
327 #define ENET_PTP_SSINC_STMSSI BITS(0,7)
329 /* ENET_PTP_TSH */
330 #define ENET_PTP_TSH_STMS BITS(0,31)
332 /* ENET_PTP_TSL */
333 #define ENET_PTP_TSL_STMSS BITS(0,30)
334 #define ENET_PTP_TSL_STS BIT(31)
336 /* ENET_PTP_TSUH */
337 #define ENET_PTP_TSUH_TMSUS BITS(0,31)
339 /* ENET_PTP_TSUL */
340 #define ENET_PTP_TSUL_TMSUSS BITS(0,30)
341 #define ENET_PTP_TSUL_TMSUPNS BIT(31)
343 /* ENET_PTP_TSADDEND */
344 #define ENET_PTP_TSADDEND_TMSA BITS(0,31)
346 /* ENET_PTP_ETH */
347 #define ENET_PTP_ETH_ETSH BITS(0,31)
349 /* ENET_PTP_ETL */
350 #define ENET_PTP_ETL_ETSL BITS(0,31)
352 /* ENET_DMA_BCTL */
353 #define ENET_DMA_BCTL_SWR BIT(0)
354 #define ENET_DMA_BCTL_DAB BIT(1)
355 #define ENET_DMA_BCTL_DPSL BITS(2,6)
356 #define ENET_DMA_BCTL_PGBL BITS(8,13)
357 #define ENET_DMA_BCTL_RTPR BITS(14,15)
358 #define ENET_DMA_BCTL_FB BIT(16)
359 #define ENET_DMA_BCTL_RXDP BITS(17,22)
360 #define ENET_DMA_BCTL_UIP BIT(23)
361 #define ENET_DMA_BCTL_FPBL BIT(24)
362 #define ENET_DMA_BCTL_AA BIT(25)
364 /* ENET_DMA_TPEN */
365 #define ENET_DMA_TPEN_TPE BITS(0,31)
367 /* ENET_DMA_RPEN */
368 #define ENET_DMA_RPEN_RPE BITS(0,31)
370 /* ENET_DMA_RDTADDR */
371 #define ENET_DMA_RDTADDR_SRT BITS(0,31)
373 /* ENET_DMA_TDTADDR */
374 #define ENET_DMA_TDTADDR_STT BITS(0,31)
376 /* ENET_DMA_STAT */
377 #define ENET_DMA_STAT_TS BIT(0)
378 #define ENET_DMA_STAT_TPS BIT(1)
379 #define ENET_DMA_STAT_TBU BIT(2)
380 #define ENET_DMA_STAT_TJT BIT(3)
381 #define ENET_DMA_STAT_RO BIT(4)
382 #define ENET_DMA_STAT_TU BIT(5)
383 #define ENET_DMA_STAT_RS BIT(6)
384 #define ENET_DMA_STAT_RBU BIT(7)
385 #define ENET_DMA_STAT_RPS BIT(8)
386 #define ENET_DMA_STAT_RWT BIT(9)
387 #define ENET_DMA_STAT_ET BIT(10)
388 #define ENET_DMA_STAT_FBE BIT(13)
389 #define ENET_DMA_STAT_ER BIT(14)
390 #define ENET_DMA_STAT_AI BIT(15)
391 #define ENET_DMA_STAT_NI BIT(16)
392 #define ENET_DMA_STAT_RP BITS(17,19)
393 #define ENET_DMA_STAT_TP BITS(20,22)
394 #define ENET_DMA_STAT_EB BITS(23,25)
395 #define ENET_DMA_STAT_MSC BIT(27)
396 #define ENET_DMA_STAT_WUM BIT(28)
397 #define ENET_DMA_STAT_TST BIT(29)
399 /* ENET_DMA_CTL */
400 #define ENET_DMA_CTL_SRE BIT(1)
401 #define ENET_DMA_CTL_OSF BIT(2)
402 #define ENET_DMA_CTL_RTHC BITS(3,4)
403 #define ENET_DMA_CTL_FUF BIT(6)
404 #define ENET_DMA_CTL_FERF BIT(7)
405 #define ENET_DMA_CTL_STE BIT(13)
406 #define ENET_DMA_CTL_TTHC BITS(14,16)
407 #define ENET_DMA_CTL_FTF BIT(20)
408 #define ENET_DMA_CTL_TSFD BIT(21)
409 #define ENET_DMA_CTL_DAFRF BIT(24)
410 #define ENET_DMA_CTL_RSFD BIT(25)
411 #define ENET_DMA_CTL_DTCERFD BIT(26)
413 /* ENET_DMA_INTEN */
414 #define ENET_DMA_INTEN_TIE BIT(0)
415 #define ENET_DMA_INTEN_TPSIE BIT(1)
416 #define ENET_DMA_INTEN_TBUIE BIT(2)
417 #define ENET_DMA_INTEN_TJTIE BIT(3)
418 #define ENET_DMA_INTEN_ROIE BIT(4)
419 #define ENET_DMA_INTEN_TUIE BIT(5)
420 #define ENET_DMA_INTEN_RIE BIT(6)
421 #define ENET_DMA_INTEN_RBUIE BIT(7)
422 #define ENET_DMA_INTEN_RPSIE BIT(8)
423 #define ENET_DMA_INTEN_RWTIE BIT(9)
424 #define ENET_DMA_INTEN_ETIE BIT(10)
425 #define ENET_DMA_INTEN_FBEIE BIT(13)
426 #define ENET_DMA_INTEN_ERIE BIT(14)
427 #define ENET_DMA_INTEN_AIE BIT(15)
428 #define ENET_DMA_INTEN_NIE BIT(16)
430 /* ENET_DMA_MFBOCNT */
431 #define ENET_DMA_MFBOCNT_MSFC BITS(0,15)
432 #define ENET_DMA_MFBOCNT_OBMFC BIT(16) /* Overflow bit for missed frame counter */
433 #define ENET_DMA_MFBOCNT_MSFA BITS(17,27)
434 #define ENET_DMA_MFBOCNT_OBFOC BIT(28)
436 /* ENET_DMA_CTDADDR */
437 #define ENET_DMA_CTDADDR_TDAP BITS(0,31)
439 /* ENET_DMA_CRDADDR */
440 #define ENET_DMA_CRDADDR_RDAP BITS(0,31)
442 /* ENET_DMA_CTBADDR */
443 #define ENET_DMA_CTBADDR_TBAP BITS(0,31)
445 /* ENET_DMA_CRBADDR */
446 #define ENET_DMA_CRBADDR_RBAP BITS(0,31)
448 /* ENET DMA Tx descriptor TDES0 */
449 #define ENET_TDES0_DB BIT(0)
450 #define ENET_TDES0_UFE BIT(1)
451 #define ENET_TDES0_EXD BIT(2)
452 #define ENET_TDES0_COCNT BITS(3,6)
453 #define ENET_TDES0_VFRM BIT(7)
454 #define ENET_TDES0_ECO BIT(8)
455 #define ENET_TDES0_LCO BIT(9)
456 #define ENET_TDES0_NCA BIT(10)
457 #define ENET_TDES0_LCA BIT(11)
458 #define ENET_TDES0_IPPE BIT(12)
459 #define ENET_TDES0_FRMF BIT(13)
460 #define ENET_TDES0_JT BIT(14)
461 #define ENET_TDES0_ES BIT(15)
462 #define ENET_TDES0_IPHE BIT(16)
463 #define ENET_TDES0_TTMSS BIT(17)
464 #define ENET_TDES0_TCHM BIT(20)
465 #define ENET_TDES0_TERM BIT(21)
466 #define ENET_TDES0_CM BITS(22,23)
467 #define ENET_TDES0_TTSEN BIT(25)
468 #define ENET_TDES0_DPAD BIT(26)
469 #define ENET_TDES0_DCRC BIT(27)
470 #define ENET_TDES0_FSG BIT(28)
471 #define ENET_TDES0_LSG BIT(29)
472 #define ENET_TDES0_INTC BIT(30)
473 #define ENET_TDES0_DAV BIT(31)
475 /* ENET DMA Tx descriptor TDES1 */
476 #define ENET_TDES1_TB1S BITS(0,12)
477 #define ENET_TDES1_TB2S BITS(16,28)
479 /* ENET DMA Tx descriptor TDES2 */
480 #define ENET_TDES2_TB1AP BITS(0,31)
482 /* ENET DMA Tx descriptor TDES3 */
483 #define ENET_TDES3_TB2AP BITS(0,31)
485 /* ENET DMA Rx descriptor RDES0 */
486 #define ENET_RDES0_PCERR BIT(0)
487 #define ENET_RDES0_CERR BIT(1)
488 #define ENET_RDES0_DBERR BIT(2)
489 #define ENET_RDES0_RERR BIT(3)
490 #define ENET_RDES0_RWDT BIT(4)
491 #define ENET_RDES0_FRMT BIT(5)
492 #define ENET_RDES0_LCO BIT(6)
493 #define ENET_RDES0_IPHERR BIT(7)
494 #define ENET_RDES0_LDES BIT(8)
495 #define ENET_RDES0_FDES BIT(9)
496 #define ENET_RDES0_VTAG BIT(10)
497 #define ENET_RDES0_OERR BIT(11)
498 #define ENET_RDES0_LERR BIT(12)
499 #define ENET_RDES0_SAFF BIT(13)
500 #define ENET_RDES0_DERR BIT(14)
501 #define ENET_RDES0_ERRS BIT(15)
502 #define ENET_RDES0_FRML BITS(16,29)
503 #define ENET_RDES0_DAFF BIT(30)
504 #define ENET_RDES0_DAV BIT(31)
506 /* ENET DMA Rx descriptor RDES1 */
507 #define ENET_RDES1_RB1S BITS(0,12)
508 #define ENET_RDES1_RCHM BIT(14)
509 #define ENET_RDES1_RERM BIT(15)
510 #define ENET_RDES1_RB2S BITS(16,28)
511 #define ENET_RDES1_DINTC BIT(31)
513 /* ENET DMA Rx descriptor RDES2 */
514 #define ENET_RDES2_RB1AP BITS(0,31)
516 /* ENET DMA Rx descriptor RDES3 */
517 #define ENET_RDES3_RB2AP BITS(0,31)
519 /* constants definitions */
520 /* define bit position and its register index offset */
521 #define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
522 #define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6)))
523 #define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
524
525 /* ENET clock range judgement */
526 #define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m)))
527
528 /* define MAC address configuration and reference address */
529 #define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4])
530 #define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0])
531 #define ENET_ADDRH_BASE ((ENET) + 0x40U)
532 #define ENET_ADDRL_BASE ((ENET) + 0x44U)
533 #define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU))
534
535 /* register offset */
536 #define MAC_FCTL_REG_OFFSET 0x0018U
537 #define MAC_WUM_REG_OFFSET 0x002CU
538 #define MAC_INTF_REG_OFFSET 0x0038U
539 #define MAC_INTMSK_REG_OFFSET 0x003CU
541 #define MSC_RINTF_REG_OFFSET 0x0104U
542 #define MSC_TINTF_REG_OFFSET 0x0108U
543 #define MSC_RINTMSK_REG_OFFSET 0x010CU
544 #define MSC_TINTMSK_REG_OFFSET 0x0110U
545 #define MSC_SCCNT_REG_OFFSET 0x014CU
546 #define MSC_MSCCNT_REG_OFFSET 0x0150U
547 #define MSC_TGFCNT_REG_OFFSET 0x0168U
548 #define MSC_RFCECNT_REG_OFFSET 0x0194U
549 #define MSC_RFAECNT_REG_OFFSET 0x0198U
550 #define MSC_RGUFCNT_REG_OFFSET 0x01C4U
552 #define DMA_STAT_REG_OFFSET 0x1014U
553 #define DMA_INTEN_REG_OFFSET 0x101CU
554 #define DMA_TDTADDR_REG_OFFSET 0x1010U
555 #define DMA_CTDADDR_REG_OFFSET 0x1048U
556 #define DMA_CTBADDR_REG_OFFSET 0x1050U
557 #define DMA_RDTADDR_REG_OFFSET 0x100CU
558 #define DMA_CRDADDR_REG_OFFSET 0x104CU
559 #define DMA_CRBADDR_REG_OFFSET 0x1054U
561 /* ENET status flag get */
562 typedef enum
563 {
564 /* ENET_MAC_WUM register */
565 ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U),
566 ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U),
567 /* ENET_MAC_FCTL register */
568 ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U),
569 /* ENET_MAC_INTF register */
570 ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U),
571 ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U),
572 ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U),
573 ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U),
574 ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U),
575 /* ENET_MSC_RINTF register */
576 ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U),
577 ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U),
578 ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U),
579 /* ENET_MSC_TINTF register */
580 ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U),
581 ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U),
582 ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U),
583 /* ENET_DMA_STAT register */
584 ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
585 ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
586 ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
587 ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
588 ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
589 ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
590 ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
591 ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
592 ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
593 ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
594 ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
595 ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
596 ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
597 ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
598 ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
599 ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U),
600 ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U),
601 ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U),
602 ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U),
603 ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U),
604 ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U),
605 }enet_flag_enum;
606
607 /* ENET stutus flag clear */
608 typedef enum
609 {
610 /* ENET_DMA_STAT register */
611 ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
612 ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
613 ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
614 ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
615 ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
616 ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
617 ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
618 ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
619 ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
620 ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
621 ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
622 ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
623 ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
624 ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
625 ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
626 }enet_flag_clear_enum;
627
628 /* ENET interrupt enable/disable */
629 typedef enum
630 {
631 /* ENET_MAC_INTMSK register */
632 ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U),
633 ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U),
634 /* ENET_MSC_RINTMSK register */
635 ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U),
636 ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U),
637 ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U),
638 /* ENET_MSC_TINTMSK register */
639 ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U),
640 ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U),
641 ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U),
642 /* ENET_DMA_INTEN register */
643 ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U),
644 ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U),
645 ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U),
646 ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U),
647 ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U),
648 ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U),
649 ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U),
650 ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U),
651 ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U),
652 ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U),
653 ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U),
654 ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U),
655 ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U),
656 ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U),
657 ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U),
658 }enet_int_enum;
659
660 /* ENET interrupt flag get */
661 typedef enum
662 {
663 /* ENET_MAC_INTF register */
664 ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U),
665 ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U),
666 ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U),
667 ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U),
668 ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U),
669 /* ENET_MSC_RINTF register */
670 ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U),
671 ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U),
672 ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U),
673 /* ENET_MSC_TINTF register */
674 ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U),
675 ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U),
676 ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U),
677 /* ENET_DMA_STAT register */
678 ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
679 ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
680 ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
681 ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
682 ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
683 ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
684 ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
685 ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
686 ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
687 ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
688 ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
689 ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
690 ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
691 ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
692 ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
693 ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U),
694 ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U),
695 ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U),
696 }enet_int_flag_enum;
697
698 /* ENET interrupt flag clear */
699 typedef enum
700 {
701 /* ENET_DMA_STAT register */
702 ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
703 ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
704 ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
705 ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
706 ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
707 ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
708 ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
709 ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
710 ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
711 ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
712 ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
713 ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
714 ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
715 ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
716 ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
717 }enet_int_flag_clear_enum;
718
719 /* current RX/TX descriptor/buffer/descriptor table address get */
720 typedef enum
721 {
722 ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET,
723 ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET,
724 ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET,
725 ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET,
726 ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET,
727 ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET
728 }enet_desc_reg_enum;
729
730 /* MAC statistics counter get */
731 typedef enum
732 {
733 ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET,
734 ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET,
735 ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET,
736 ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET,
737 ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET,
738 ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET
739 }enet_msc_counter_enum;
740
741 /* function option, used for ENET initialization */
742 typedef enum
743 {
744 FORWARD_OPTION = BIT(0),
745 DMABUS_OPTION = BIT(1),
746 DMA_MAXBURST_OPTION = BIT(2),
747 DMA_ARBITRATION_OPTION = BIT(3),
748 STORE_OPTION = BIT(4),
749 DMA_OPTION = BIT(5),
750 VLAN_OPTION = BIT(6),
751 FLOWCTL_OPTION = BIT(7),
752 HASHH_OPTION = BIT(8),
753 HASHL_OPTION = BIT(9),
754 FILTER_OPTION = BIT(10),
755 HALFDUPLEX_OPTION = BIT(11),
756 TIMER_OPTION = BIT(12),
757 INTERFRAMEGAP_OPTION = BIT(13),
758 }enet_option_enum;
759
760 /* phy mode and mac loopback configurations */
761 typedef enum
762 {
763 ENET_AUTO_NEGOTIATION = 0x01u,
764 ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM),
765 ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD ,
766 ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM,
767 ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U,
768 ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM)
769 }enet_mediamode_enum;
770
771 /* IP frame checksum function */
772 typedef enum
773 {
774 ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U,
775 ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO,
776 ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD)
778 }enet_chksumconf_enum;
779
780 /* received frame filter function */
781 typedef enum
782 {
783 ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM,
784 ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR,
785 ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U,
786 ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD
787 }enet_frmrecept_enum;
788
789 /* register group value get */
790 typedef enum
791 {
792 ALL_MAC_REG = 0,
793 ALL_MSC_REG = 22,
794 ALL_PTP_REG = 33,
795 ALL_DMA_REG = 44,
796 }enet_registers_type_enum;
797
798 /* dma direction select */
799 typedef enum
800 {
801 ENET_DMA_TX = ENET_DMA_STAT_TP,
802 ENET_DMA_RX = ENET_DMA_STAT_RP
803 }enet_dmadirection_enum;
804
805 /* PHY operation direction select */
806 typedef enum
807 {
808 ENET_PHY_READ = (uint32_t)0x00000000,
809 ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW
810 }enet_phydirection_enum;
811
812 /* register operation direction select */
813 typedef enum
814 {
815 ENET_REG_READ,
816 ENET_REG_WRITE
817 }enet_regdirection_enum;
818
819 /* ENET MAC addresses */
820 typedef enum
821 {
822 ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000),
823 ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008),
824 ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010),
825 ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018)
826 }enet_macaddress_enum;
827
828 /* descriptor information */
829 typedef enum
830 {
831 TXDESC_COLLISION_COUNT,
832 TXDESC_BUFFER_1_ADDR,
833 RXDESC_FRAME_LENGTH,
834 RXDESC_BUFFER_1_SIZE,
835 RXDESC_BUFFER_2_SIZE,
836 RXDESC_BUFFER_1_ADDR
837 }enet_descstate_enum;
838
839 /* structure for initialization of the ENET */
840 typedef struct
841 {
842 uint32_t option_enable;
843 uint32_t forward_frame;
844 uint32_t dmabus_mode;
845 uint32_t dma_maxburst;
846 uint32_t dma_arbitration;
847 uint32_t store_forward_mode;
848 uint32_t dma_function;
849 uint32_t vlan_config;
850 uint32_t flow_control;
851 uint32_t hashtable_high;
852 uint32_t hashtable_low;
853 uint32_t framesfilter_mode;
854 uint32_t halfduplex_param;
855 uint32_t timer_config;
856 uint32_t interframegap;
857 }enet_initpara_struct;
858
859 /* structure for ENET DMA desciptors */
860 typedef struct
861 {
862 uint32_t status;
863 uint32_t control_buffer_size;
864 uint32_t buffer1_addr;
865 uint32_t buffer2_next_desc_addr;
866 } enet_descriptors_struct;
867
868 /* structure of PTP system time */
869 typedef struct
870 {
871 uint32_t second;
872 uint32_t nanosecond;
873 uint32_t sign;
874 }enet_ptp_systime_struct;
875
876 /* mac_cfg register value */
877 #define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5))
878 #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0)
879 #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1)
880 #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2)
881 #define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3)
883 #define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
884 #define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0)
885 #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1)
886 #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2)
887 #define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3)
888 #define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4)
889 #define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5)
890 #define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6)
891 #define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7)
893 #define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U)
894 #define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD
896 #define ENET_JABBER_ENABLE ((uint32_t)0x00000000U)
897 #define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD
899 #define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U)
900 #define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD
902 #define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U)
903 #define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD
905 #define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)
906 #define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD
908 #define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM
909 #define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)
911 #define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM
912 #define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U)
914 #define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO
915 #define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U)
917 #define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)
918 #define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD
920 #define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD
921 #define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U)
922 #define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD
924 #define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC
925 #define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U)
927 /* mac_frmf register value */
928 #define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
929 #define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0)
930 #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1)
931 #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2)
932 #define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3)
934 #define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR
935 #define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U)
937 #define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT
938 #define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT)
939 #define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U)
940 #define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT
941 #define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT
943 #define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U)
944 #define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD
946 #define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT
947 #define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U)
948 #define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT
950 #define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM
951 #define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U)
953 #define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT)
954 #define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF
955 #define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U)
956 #define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD
957 #define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD
958 #define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF
959 #define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT
961 #define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT)
962 #define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF
963 #define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U)
964 #define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF
966 /* mac_phy_ctl register value */
967 #define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
968 #define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0)
969 #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1)
970 #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2)
971 #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3)
973 #define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6))
975 #define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11))
977 /* mac_phy_data register value */
978 #define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
980 /* mac_fctl register value */
981 #define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
982 #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0)
983 #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1)
984 #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2)
985 #define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3)
987 #define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U)
988 #define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP
989 #define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP
991 #define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT
992 #define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U)
994 #define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN
995 #define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
996 #define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN
998 #define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN
999 #define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
1000 #define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN
1002 #define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA
1003 #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U)
1004 #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA
1006 #define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
1007 /* mac_vlt register value */
1008 #define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
1010 #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC
1011 #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
1013 /* mac_wum register value */
1014 #define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR
1015 #define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR
1016 #define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR
1017 #define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD
1018 #define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN
1019 #define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN
1020 #define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU
1022 /* mac_addr0h register value */
1023 #define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
1025 /* mac_addrxh register value, x = 1,2,3 */
1026 #define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
1028 #define ENET_ADDRESS_MASK_BYTE0 BIT(24)
1029 #define ENET_ADDRESS_MASK_BYTE1 BIT(25)
1030 #define ENET_ADDRESS_MASK_BYTE2 BIT(26)
1031 #define ENET_ADDRESS_MASK_BYTE3 BIT(27)
1032 #define ENET_ADDRESS_MASK_BYTE4 BIT(28)
1033 #define ENET_ADDRESS_MASK_BYTE5 BIT(29)
1035 #define ENET_ADDRESS_FILTER_SA BIT(30)
1036 #define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000)
1038 /* mac_fcth register value */
1039 #define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8)
1040 #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0)
1041 #define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1)
1042 #define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2)
1043 #define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3)
1044 #define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4)
1045 #define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5)
1046 #define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6)
1048 #define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8)
1049 #define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0)
1050 #define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1)
1051 #define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2)
1052 #define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3)
1053 #define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4)
1054 #define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5)
1055 #define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6)
1057 /* msc_ctl register value */
1058 #define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR
1059 #define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR
1060 #define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ
1062 /* ptp_tsctl register value */
1063 #define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN
1064 #define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN
1066 /* ptp_ssinc register value */
1067 #define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
1069 /* ptp_tsl register value */
1070 #define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30)
1072 #define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000)
1073 #define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS
1075 #define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U))
1077 /* ptp_tsul register value */
1078 #define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0))
1080 #define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000)
1081 #define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS
1083 /* dma_bctl register value */
1084 #define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2))
1085 #define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6)
1087 #define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
1088 #define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1)
1089 #define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2)
1090 #define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4)
1091 #define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8)
1092 #define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16)
1093 #define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32)
1094 #define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL)
1095 #define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL)
1096 #define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL)
1097 #define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL)
1098 #define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL)
1099 #define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL)
1101 #define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14))
1102 #define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0)
1103 #define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1)
1104 #define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2)
1105 #define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3)
1106 #define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB
1108 #define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB
1109 #define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000)
1111 #define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17))
1112 #define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1)
1113 #define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2)
1114 #define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4)
1115 #define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8)
1116 #define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16)
1117 #define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32)
1118 #define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL)
1119 #define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL)
1120 #define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL)
1121 #define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL)
1122 #define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL)
1123 #define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL)
1125 #define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP
1126 #define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000)
1128 #define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA
1129 #define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000)
1131 /* dma_stat register value */
1132 #define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19)
1133 #define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000)
1134 #define ENET_RX_STATE_FETCHING BIT(17)
1135 #define ENET_RX_STATE_WAITING (BIT(17)|BIT(18))
1136 #define ENET_RX_STATE_SUSPENDED BIT(19)
1137 #define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19))
1138 #define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP
1140 #define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22)
1141 #define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000)
1142 #define ENET_TX_STATE_FETCHING BIT(20)
1143 #define ENET_TX_STATE_WAITING BIT(21)
1144 #define ENET_TX_STATE_READING (BIT(20)|BIT(21))
1145 #define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22))
1146 #define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP
1148 #define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25)
1149 #define ENET_ERROR_TXDATA_TRANSFER BIT(23)
1150 #define ENET_ERROR_READ_TRANSFER BIT(24)
1151 #define ENET_ERROR_DESC_ACCESS BIT(25)
1153 /* dma_ctl register value */
1154 #define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3))
1155 #define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0)
1156 #define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1)
1157 #define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2)
1158 #define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3)
1160 #define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14))
1161 #define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0)
1162 #define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1)
1163 #define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2)
1164 #define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3)
1165 #define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4)
1166 #define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5)
1167 #define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6)
1168 #define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7)
1170 #define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD
1171 #define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000)
1173 #define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD
1174 #define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000)
1176 #define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000)
1177 #define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF
1178 #define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF
1180 #define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD
1181 #define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000)
1183 #define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2)
1184 #define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000)
1185 #define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2)
1187 #define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2)
1188 #define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000)
1189 #define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2)
1191 #define ENET_SECONDFRAME_OPT_ENABLE ((uint32_t)0x00000000)
1192 #define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000)
1193 #define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF
1195 /* dma_mfbocnt register value */
1196 #define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15)
1198 #define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27)
1200 /* dma tx descriptor tdes0 register value */
1201 #define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3))
1202 #define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6)
1204 #define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
1205 #define ENET_CHECKSUM_DISABLE TDES0_CM(0)
1206 #define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1)
1207 #define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2)
1208 #define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3)
1210 /* dma tx descriptor tdes1 register value */
1211 #define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0))
1213 #define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16))
1215 /* dma rx descriptor rdes0 register value */
1216 #define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16))
1217 #define GET_RDES0_FRML(regval) GET_BITS((regval),16,29)
1219 /* dma rx descriptor rdes1 register value */
1220 #define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U)
1221 #define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC
1223 #define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12)
1225 #define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28)
1227 /* dma rx descriptor rdes4 register value */
1228 #define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
1229 #define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2)
1231 #define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
1232 #define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11)
1234 /* ENET register mask value */
1235 #define MAC_CFG_MASK ((uint32_t)0xFD30810FU)
1236 #define MAC_FCTL_MASK ((uint32_t)0x0000FF41U)
1237 #define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U)
1238 #define DMA_BCTL_MASK ((uint32_t)0xF800007DU)
1240 #define ETH_DMATXDESC_SIZE 0x10U
1241 #define ETH_DMARXDESC_SIZE 0x10U
1243 typedef enum{
1244 ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI,
1245 ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU,
1246 ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU,
1247 ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)),
1248 ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU,
1249 }enet_ptp_function_enum;
1250
1251
1252 /* ENET remote wake-up frame register length */
1253 #define ETH_WAKEUP_REGISTER_LENGTH 8U
1255 /* ENET frame size */
1256 #define ENET_MAX_FRAME_SIZE 1524U
1258 /* ENET delay timeout */
1259 #define ENET_DELAY_TO ((uint32_t)0x0004FFFFU)
1260 #define ENET_RESET_TO ((uint32_t)0x000004FFU)
1262 /* function declarations */
1263 /* main function */
1264 /* deinitialize the ENET, and reset structure parameters for ENET initialization */
1265 void enet_deinit(void);
1266 /* configure the parameters which are usually less cared for initialization */
1267 void enet_initpara_config(enet_option_enum option, uint32_t para);
1268 /* initialize ENET peripheral with generally concerned parameters and the less cared parameters */
1269 ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept);
1270 /* reset all core internal registers located in CLK_TX and CLK_RX */
1271 ErrStatus enet_software_reset(void);
1272 /* check receive frame valid and return frame size */
1273 uint32_t enet_rxframe_size_get(void);
1274 /* initialize the dma tx/rx descriptors's parameters in chain mode */
1275 void enet_descriptors_chain_init(enet_dmadirection_enum direction);
1276 /* initialize the dma tx/rx descriptors's parameters in ring mode */
1277 void enet_descriptors_ring_init(enet_dmadirection_enum direction);
1278 /* handle current received frame data to application buffer */
1279 ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize);
1280 /* handle current received frame but without data copy to application buffer */
1281 #define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U)
1282 /* handle application buffer data to transmit it */
1283 ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length);
1284 /* handle current transmit frame but without data copy from application buffer */
1285 #define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len))
1286 /* configure the transmit IP frame checksum offload calculation and insertion */
1287 void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum);
1288 /* ENET Tx and Rx function enable (include MAC and DMA module) */
1289 void enet_enable(void);
1290 /* ENET Tx and Rx function disable (include MAC and DMA module) */
1291 void enet_disable(void);
1292 /* configure MAC address */
1293 void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]);
1294 /* get MAC address */
1295 void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]);
1296
1297 /* get the ENET MAC/MSC/PTP/DMA status flag */
1298 FlagStatus enet_flag_get(enet_flag_enum enet_flag);
1299 /* clear the ENET DMA status flag */
1300 void enet_flag_clear(enet_flag_clear_enum enet_flag);
1301 /* enable ENET MAC/MSC/DMA interrupt */
1302 void enet_interrupt_enable(enet_int_enum enet_int);
1303 /* disable ENET MAC/MSC/DMA interrupt */
1304 void enet_interrupt_disable(enet_int_enum enet_int);
1305 /* get ENET MAC/MSC/DMA interrupt flag */
1306 FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag);
1307 /* clear ENET DMA interrupt flag */
1308 void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear);
1309
1310 /* MAC function */
1311 /* ENET Tx function enable (include MAC and DMA module) */
1312 void enet_tx_enable(void);
1313 /* ENET Tx function disable (include MAC and DMA module) */
1314 void enet_tx_disable(void);
1315 /* ENET Rx function enable (include MAC and DMA module) */
1316 void enet_rx_enable(void);
1317 /* ENET Rx function disable (include MAC and DMA module) */
1318 void enet_rx_disable(void);
1319 /* put registers value into the application buffer */
1320 void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num);
1321 /* get the enet debug status from the debug register */
1322 uint32_t enet_debug_status_get(uint32_t mac_debug);
1323 /* enable the MAC address filter */
1324 void enet_address_filter_enable(enet_macaddress_enum mac_addr);
1325 /* disable the MAC address filter */
1326 void enet_address_filter_disable(enet_macaddress_enum mac_addr);
1327 /* configure the MAC address filter */
1328 void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type);
1329 /* PHY interface configuration (configure SMI clock and reset PHY chip) */
1330 ErrStatus enet_phy_config(void);
1331 /* write to/read from a PHY register */
1332 ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue);
1333 /* enable the loopback function of phy chip */
1334 ErrStatus enet_phyloopback_enable(void);
1335 /* disable the loopback function of phy chip */
1336 ErrStatus enet_phyloopback_disable(void);
1337 /* enable ENET forward feature */
1338 void enet_forward_feature_enable(uint32_t feature);
1339 /* disable ENET forward feature */
1340 void enet_forward_feature_disable(uint32_t feature);
1341 /* enable ENET fliter feature */
1342 void enet_fliter_feature_enable(uint32_t feature);
1343 /* disable ENET fliter feature */
1344 void enet_fliter_feature_disable(uint32_t feature);
1345
1346 /* flow control function */
1347 /* generate the pause frame, ENET will send pause frame after enable transmit flow control */
1348 ErrStatus enet_pauseframe_generate(void);
1349 /* configure the pause frame detect type */
1350 void enet_pauseframe_detect_config(uint32_t detect);
1351 /* configure the pause frame parameters */
1352 void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold);
1353 /* configure the threshold of the flow control(deactive and active threshold) */
1354 void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active);
1355 /* enable ENET flow control feature */
1356 void enet_flowcontrol_feature_enable(uint32_t feature);
1357 /* disable ENET flow control feature */
1358 void enet_flowcontrol_feature_disable(uint32_t feature);
1359
1360 /* DMA function */
1361 /* get the dma transmit/receive process state */
1362 uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction);
1363 /* poll the dma transmission/reception enable */
1364 void enet_dmaprocess_resume(enet_dmadirection_enum direction);
1365 /* check and recover the Rx process */
1366 void enet_rxprocess_check_recovery(void);
1367 /* flush the ENET transmit fifo, and wait until the flush operation completes */
1368 ErrStatus enet_txfifo_flush(void);
1369 /* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */
1370 uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get);
1371 /* get the Tx or Rx descriptor information */
1372 uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get);
1373 /* get the number of missed frames during receiving */
1374 void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop);
1375
1376 /* descriptor function */
1377 /* get the bit flag of ENET dma descriptor */
1378 FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag);
1379 /* set the bit flag of ENET dma tx descriptor */
1380 void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag);
1381 /* clear the bit flag of ENET dma tx descriptor */
1382 void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag);
1383 /* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */
1384 void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc);
1385 /* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */
1386 void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time);
1387 /* drop current receive frame */
1388 void enet_rxframe_drop(void);
1389 /* enable DMA feature */
1390 void enet_dma_feature_enable(uint32_t feature);
1391 /* disable DMA feature */
1392 void enet_dma_feature_disable(uint32_t feature);
1393
1394 /* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */
1395 void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab);
1396 /* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */
1397 void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab);
1398 /* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */
1399 ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]);
1400 /* handle current received frame but without data copy to application buffer in PTP normal mode */
1401 #define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr))
1402 /* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */
1403 ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]);
1404 /* handle current transmit frame but without data copy from application buffer in PTP normal mode */
1405 #define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr))
1406
1407 /* WUM function */
1408 /* wakeup frame filter register pointer reset */
1409 void enet_wum_filter_register_pointer_reset(void);
1410 /* set the remote wakeup frame registers */
1411 void enet_wum_filter_config(uint32_t pdata[]);
1412 /* enable wakeup management features */
1413 void enet_wum_feature_enable(uint32_t feature);
1414 /* disable wakeup management features */
1415 void enet_wum_feature_disable(uint32_t feature);
1416
1417 /* MSC function */
1418 /* reset the MAC statistics counters */
1419 void enet_msc_counters_reset(void);
1420 /* enable the MAC statistics counter features */
1421 void enet_msc_feature_enable(uint32_t feature);
1422 /* disable the MAC statistics counter features */
1423 void enet_msc_feature_disable(uint32_t feature);
1424 /* get MAC statistics counter */
1425 uint32_t enet_msc_counters_get(enet_msc_counter_enum counter);
1426
1427 /* PTP function */
1428 /* change subsecond to nanosecond */
1429 uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond);
1430 /* change nanosecond to subsecond */
1431 uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond);
1432 /* enable the PTP features */
1433 void enet_ptp_feature_enable(uint32_t feature);
1434 /* disable the PTP features */
1435 void enet_ptp_feature_disable(uint32_t feature);
1436 /* configure the PTP timestamp function */
1437 ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func);
1438 /* configure the PTP system time subsecond increment value */
1439 void enet_ptp_subsecond_increment_config(uint32_t subsecond);
1440 /* adjusting the PTP clock frequency only in fine update mode */
1441 void enet_ptp_timestamp_addend_config(uint32_t add);
1442 /* initializing or adding/subtracting to second of the PTP system time */
1443 void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond);
1444 /* configure the PTP expected target time */
1445 void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond);
1446 /* get the PTP current system time */
1447 void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct);
1448 /* configure the PPS output frequency */
1449 void enet_ptp_pps_output_frequency_config(uint32_t freq);
1450 /* configure and start PTP timestamp counter */
1451 void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg);
1452 /* adjust frequency in fine method by configure addend register */
1453 void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg);
1454 /* update system time in coarse method */
1455 void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct);
1456 /* set system time in fine method */
1457 void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct);
1458 /* get the ptp flag status */
1459 FlagStatus enet_ptp_flag_get(uint32_t flag);
1460
1461 /* internal function */
1462 /* reset the ENET initpara struct, call it before using enet_initpara_config() */
1463 void enet_initpara_reset(void);
1464 /* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */
1465 static void enet_default_init(void);
1466 #ifdef USE_DELAY
1467 /* user can provide more timing precise _ENET_DELAY_ function */
1468 #define _ENET_DELAY_ delay_ms
1469 #else
1470 /* insert a delay time */
1471 static void enet_delay(uint32_t ncount);
1472 /* default _ENET_DELAY_ function with less precise timing */
1473 #define _ENET_DELAY_ enet_delay
1474 #endif
1475
1476 #endif /* GD32F10X_ENET_H */
ALL_MAC_REG
Definition: gd32f10x_enet.h:792
enet_enable
void enet_enable(void)
ENET Tx and Rx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:947
ENET_MSC_FLAG_RFCE
Definition: gd32f10x_enet.h:576
HALFDUPLEX_OPTION
Definition: gd32f10x_enet.h:755
enet_ptp_timestamp_update_config
void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
initialize or add/subtract to second of the system time
Definition: gd32f10x_enet.c:2741
enet_missed_frame_counter_get
void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop)
get the number of missed frames during receiving
Definition: gd32f10x_enet.c:1906
enet_initpara_config
void enet_initpara_config(enet_option_enum option, uint32_t para)
configure the parameters which are usually less cared for initialization note – this function must b...
Definition: gd32f10x_enet.c:176
ENET_MSC_INT_TGFMSCIM
Definition: gd32f10x_enet.h:640
enet_phy_config
ErrStatus enet_phy_config(void)
PHY interface configuration (configure SMI clock and reset PHY chip)
Definition: gd32f10x_enet.c:1394
ENET_MAC_CFG_DPM
#define ENET_MAC_CFG_DPM
Definition: gd32f10x_enet.h:162
ENET_PTP_SYSTIME_INIT
Definition: gd32f10x_enet.h:1244
ENET_PTP_TSCTL_TMSSTU
#define ENET_PTP_TSCTL_TMSSTU
Definition: gd32f10x_enet.h:322
enet_registers_get
void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num)
put registers value into the application buffer
Definition: gd32f10x_enet.c:1304
ENET_DMA_FLAG_RS
Definition: gd32f10x_enet.h:590
ENET_DMA_FLAG_TPS_CLR
Definition: gd32f10x_enet.h:612
enet_initpara_reset
void enet_initpara_reset(void)
reset the ENET initpara struct, call it before using enet_initpara_config()
Definition: gd32f10x_enet.c:2925
ENET_DMA_FLAG_TS
Definition: gd32f10x_enet.h:584
ENET_DMA_INT_TBUIE
Definition: gd32f10x_enet.h:645
enet_rx_desc_delay_receive_complete_interrupt
void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time)
enet_ptp_feature_disable
void enet_ptp_feature_disable(uint32_t feature)
disable the PTP features
Definition: gd32f10x_enet.c:2630
ENET_MSC_INT_FLAG_TGFMSC
Definition: gd32f10x_enet.h:675
enet_disable
void enet_disable(void)
ENET Tx and Rx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:959
ENET_DMA_FLAG_RWT_CLR
Definition: gd32f10x_enet.h:620
enet_frame_receive
ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize)
handle current received frame data to application buffer
Definition: gd32f10x_enet.c:792
ENET_DMA_INT_FLAG_NI
Definition: gd32f10x_enet.h:692
DMABUS_OPTION
Definition: gd32f10x_enet.h:745
ENET_MSC_TX_TGFCNT
Definition: gd32f10x_enet.h:735
ENET_DMA_FLAG_AI_CLR
Definition: gd32f10x_enet.h:624
enet_ptp_finecorrection_adjfreq
void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg)
adjust frequency in fine method by configure addend register
Definition: gd32f10x_enet.c:2832
enet_phydirection_enum
enet_phydirection_enum
Definition: gd32f10x_enet.h:806
enet_desc_information_get
uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get)
get the Tx or Rx descriptor information
Definition: gd32f10x_enet.c:1868
HASHL_OPTION
Definition: gd32f10x_enet.h:753
ENET_DMA_FLAG_TST
Definition: gd32f10x_enet.h:604
ENET_MAC_INT_FLAG_MSCT
Definition: gd32f10x_enet.h:667
ENET_RX_CURRENT_DESC
Definition: gd32f10x_enet.h:723
enet_initpara_struct::dmabus_mode
uint32_t dmabus_mode
Definition: gd32f10x_enet.h:844
ENET_MSC_INT_FLAG_TGF
Definition: gd32f10x_enet.h:676
ENET_PTP_TSCTL_TMSARU
#define ENET_PTP_TSCTL_TMSARU
Definition: gd32f10x_enet.h:324
enet_descriptors_struct::control_buffer_size
uint32_t control_buffer_size
Definition: gd32f10x_enet.h:863
enet_ptp_finecorrection_settime
void enet_ptp_finecorrection_settime(enet_ptp_systime_struct *systime_struct)
set system time in fine method
Definition: gd32f10x_enet.c:2884
enet_msc_counter_enum
enet_msc_counter_enum
Definition: gd32f10x_enet.h:731
enet_msc_counters_reset
void enet_msc_counters_reset(void)
reset the MAC statistics counters
Definition: gd32f10x_enet.c:2525
enet_ptpframe_transmit_normal_mode
ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[])
send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal...
Definition: gd32f10x_enet.c:2372
ENET_MSC_FLAG_TGFMSC
Definition: gd32f10x_enet.h:581
ENET_DMA_INT_RWTIE
Definition: gd32f10x_enet.h:652
ENET_DMA_INT_FLAG_TJT_CLR
Definition: gd32f10x_enet.h:705
MSC_TINTMSK_REG_OFFSET
#define MSC_TINTMSK_REG_OFFSET
Definition: gd32f10x_enet.h:544
ENET_MSC_RX_RFCECNT
Definition: gd32f10x_enet.h:736
FLOWCTL_OPTION
Definition: gd32f10x_enet.h:751
DMA_INTEN_REG_OFFSET
#define DMA_INTEN_REG_OFFSET
Definition: gd32f10x_enet.h:553
ENET_RX_CURRENT_BUFFER
Definition: gd32f10x_enet.h:724
ENET_MSC_INT_RFCEIM
Definition: gd32f10x_enet.h:635
enet_msc_feature_enable
void enet_msc_feature_enable(uint32_t feature)
enable the MAC statistics counter features
Definition: gd32f10x_enet.c:2540
ENET_DMA_INT_TPSIE
Definition: gd32f10x_enet.h:644
enet_int_enum
enet_int_enum
Definition: gd32f10x_enet.h:629
ENET_DMA_INT_FLAG_ET_CLR
Definition: gd32f10x_enet.h:712
ENET_MAC_ADDRESS0
Definition: gd32f10x_enet.h:822
enet_tx_enable
void enet_tx_enable(void)
ENET Tx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1248
ENET_DMA_FLAG_RS_CLR
Definition: gd32f10x_enet.h:617
ENET_MSC_INT_FLAG_RFCE
Definition: gd32f10x_enet.h:670
enet_pauseframe_detect_config
void enet_pauseframe_detect_config(uint32_t detect)
configure the pause frame detect type
Definition: gd32f10x_enet.c:1649
enet_fliter_feature_enable
void enet_fliter_feature_enable(uint32_t feature)
enable ENET fliter feature
Definition: gd32f10x_enet.c:1593
ENET_MAC_FLAG_MSCR
Definition: gd32f10x_enet.h:572
ENET_DMA_INT_FLAG_TST
Definition: gd32f10x_enet.h:695
ENET_DMA_FLAG_RPS
Definition: gd32f10x_enet.h:592
ENET_DMA_FLAG_TPS
Definition: gd32f10x_enet.h:585
ENET_DMA_INT_TIE
Definition: gd32f10x_enet.h:643
ENET_DMA_INT_FLAG_RBU_CLR
Definition: gd32f10x_enet.h:709
DMA_CRBADDR_REG_OFFSET
#define DMA_CRBADDR_REG_OFFSET
Definition: gd32f10x_enet.h:559
DMA_CRDADDR_REG_OFFSET
#define DMA_CRDADDR_REG_OFFSET
Definition: gd32f10x_enet.h:558
enet_desc_reg_enum
enet_desc_reg_enum
Definition: gd32f10x_enet.h:720
ENET_MSC_FLAG_RFAE
Definition: gd32f10x_enet.h:577
ENET_DMA_TX
Definition: gd32f10x_enet.h:801
enet_pauseframe_config
void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold)
configure the pause frame parameters
Definition: gd32f10x_enet.c:1668
DMA_RDTADDR_REG_OFFSET
#define DMA_RDTADDR_REG_OFFSET
Definition: gd32f10x_enet.h:557
ENET_MAC_FLAG_TMST
Definition: gd32f10x_enet.h:574
ENET_DMA_INT_FLAG_RWT_CLR
Definition: gd32f10x_enet.h:711
enet_descriptors_struct
Definition: gd32f10x_enet.h:860
ENET_PHY_WRITE
Definition: gd32f10x_enet.h:809
ENET_MAC_ADDRESS2
Definition: gd32f10x_enet.h:824
ENET_BROADCAST_FRAMES_DROP
Definition: gd32f10x_enet.h:786
enet_initpara_struct::dma_arbitration
uint32_t dma_arbitration
Definition: gd32f10x_enet.h:846
ENET_MSC_INT_FLAG_RFAE
Definition: gd32f10x_enet.h:671
enet_initpara_struct::interframegap
uint32_t interframegap
Definition: gd32f10x_enet.h:856
enet_ptp_normal_descriptors_chain_init
void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function ...
Definition: gd32f10x_enet.c:2120
ENET_DMA_INT_FLAG_FBE
Definition: gd32f10x_enet.h:689
enet_dma_feature_disable
void enet_dma_feature_disable(uint32_t feature)
disable DMA feature
Definition: gd32f10x_enet.c:2105
ENET_RECEIVEALL
Definition: gd32f10x_enet.h:784
enet_ptp_systime_struct::sign
uint32_t sign
Definition: gd32f10x_enet.h:873
ENET_DMA_INT_FLAG_TBU_CLR
Definition: gd32f10x_enet.h:704
ENET_MSC_FLAG_TGF
Definition: gd32f10x_enet.h:582
enet_tx_disable
void enet_tx_disable(void)
ENET Tx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1261
ENET_MAC_FLAG_MPKR
Definition: gd32f10x_enet.h:565
ENET_DMA_STAT_RP
#define ENET_DMA_STAT_RP
Definition: gd32f10x_enet.h:392
enet_initpara_struct::hashtable_high
uint32_t hashtable_high
Definition: gd32f10x_enet.h:851
ENET_PTP_TSCTL_TMSFCU
#define ENET_PTP_TSCTL_TMSFCU
Definition: gd32f10x_enet.h:320
ENET_MAC_FRMF_BFRMD
#define ENET_MAC_FRMF_BFRMD
Definition: gd32f10x_enet.h:177
enet_macaddress_enum
enet_macaddress_enum
Definition: gd32f10x_enet.h:820
enet_forward_feature_disable
void enet_forward_feature_disable(uint32_t feature)
disable ENET forward feature
Definition: gd32f10x_enet.c:1568
enet_interrupt_flag_get
FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag)
get ENET MAC/MSC/DMA interrupt flag
Definition: gd32f10x_enet.c:1205
enet_initpara_struct::halfduplex_param
uint32_t halfduplex_param
Definition: gd32f10x_enet.h:854
ENET_DMA_FLAG_TBU_CLR
Definition: gd32f10x_enet.h:613
ENET_DMA_INT_FLAG_TPS_CLR
Definition: gd32f10x_enet.h:703
ENET_DMA_INT_NIE
Definition: gd32f10x_enet.h:657
ENET_MAC_FLAG_WUFR
Definition: gd32f10x_enet.h:566
enet_frmrecept_enum
enet_frmrecept_enum
Definition: gd32f10x_enet.h:781
enet_desc_flag_set
void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag)
set the bit flag of ENET DMA descriptor
Definition: gd32f10x_enet.c:1996
enet_flag_clear_enum
enet_flag_clear_enum
Definition: gd32f10x_enet.h:608
enet_flag_get
FlagStatus enet_flag_get(enet_flag_enum enet_flag)
get the ENET MAC/MSC/PTP/DMA status flag
Definition: gd32f10x_enet.c:1050
ENET_MAC_INT_FLAG_MSC
Definition: gd32f10x_enet.h:665
ENET_DMA_INT_ETIE
Definition: gd32f10x_enet.h:653
enet_ptp_pps_output_frequency_config
void enet_ptp_pps_output_frequency_config(uint32_t freq)
HASHH_OPTION
Definition: gd32f10x_enet.h:752
enet_dmaprocess_resume
void enet_dmaprocess_resume(enet_dmadirection_enum direction)
poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN re...
Definition: gd32f10x_enet.c:1773
ENET_DMA_FLAG_RO_CLR
Definition: gd32f10x_enet.h:615
ENET_DMA_FLAG_EB_TRANSFER_ERROR
Definition: gd32f10x_enet.h:600
ENET_LOOPBACKMODE
Definition: gd32f10x_enet.h:768
ENET_DMA_INT_FLAG_TPS
Definition: gd32f10x_enet.h:679
enet_debug_status_get
uint32_t enet_debug_status_get(uint32_t mac_debug)
enet_ptp_systime_struct
Definition: gd32f10x_enet.h:869
ENET_MSC_TX_SCCNT
Definition: gd32f10x_enet.h:733
enet_ptp_coarsecorrection_systime_update
void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct)
update system time in coarse method
Definition: gd32f10x_enet.c:2850
ENET_DMA_INT_FLAG_AI_CLR
Definition: gd32f10x_enet.h:715
ENET_MAC_PHY_CTL_PW
#define ENET_MAC_PHY_CTL_PW
Definition: gd32f10x_enet.h:192
ENET_DMA_INT_FLAG_TU
Definition: gd32f10x_enet.h:683
ENET_MAC_ADDRESS1
Definition: gd32f10x_enet.h:823
ENET_DMA_FLAG_TBU
Definition: gd32f10x_enet.h:586
RXDESC_FRAME_LENGTH
Definition: gd32f10x_enet.h:833
TXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:832
enet_ptp_timestamp_addend_config
void enet_ptp_timestamp_addend_config(uint32_t add)
adjusting the clock frequency only in fine update mode
Definition: gd32f10x_enet.c:2724
enet_dmaprocess_state_get
uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction)
get the dma transmit/receive process state
Definition: gd32f10x_enet.c:1756
enet_interrupt_enable
void enet_interrupt_enable(enet_int_enum enet_int)
enable ENET MAC/MSC/DMA interrupt
Definition: gd32f10x_enet.c:1117
TXDESC_COLLISION_COUNT
Definition: gd32f10x_enet.h:831
ENET_DMA_INT_RBUIE
Definition: gd32f10x_enet.h:650
ALL_DMA_REG
Definition: gd32f10x_enet.h:795
ENET_TX_CURRENT_DESC
Definition: gd32f10x_enet.h:726
enet_transmit_checksum_config
void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum)
configure the transmit IP frame checksum offload calculation and insertion
Definition: gd32f10x_enet.c:935
ENET_MAC_INT_FLAG_WUM
Definition: gd32f10x_enet.h:664
MAC_INTF_REG_OFFSET
#define MAC_INTF_REG_OFFSET
Definition: gd32f10x_enet.h:538
ALL_PTP_REG
Definition: gd32f10x_enet.h:794
ENET_DMA_FLAG_EB_ACCESS_ERROR
Definition: gd32f10x_enet.h:601
MSC_TGFCNT_REG_OFFSET
#define MSC_TGFCNT_REG_OFFSET
Definition: gd32f10x_enet.h:547
enet_wum_filter_register_pointer_reset
void enet_wum_filter_register_pointer_reset(void)
wakeup frame filter register pointer reset
Definition: gd32f10x_enet.c:2469
enet_ptp_system_time_get
void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct)
get the current system time
Definition: gd32f10x_enet.c:2771
DMA_MAXBURST_OPTION
Definition: gd32f10x_enet.h:746
ENET_AUTOCHECKSUM_DROP_FAILFRAMES
Definition: gd32f10x_enet.h:775
enet_desc_flag_clear
void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag)
clear the bit flag of ENET DMA descriptor
Definition: gd32f10x_enet.c:2021
enet_initpara_struct::flow_control
uint32_t flow_control
Definition: gd32f10x_enet.h:850
enet_deinit
void enet_deinit(void)
deinitialize the ENET, and reset structure parameters for ENET initialization
Definition: gd32f10x_enet.c:69
ENET_MAC_FRMF_FAR
#define ENET_MAC_FRMF_FAR
Definition: gd32f10x_enet.h:182
ENET_DMA_INT_FLAG_MSC
Definition: gd32f10x_enet.h:693
RXDESC_BUFFER_1_SIZE
Definition: gd32f10x_enet.h:834
enet_ptp_systime_struct::nanosecond
uint32_t nanosecond
Definition: gd32f10x_enet.h:872
ENET_100M_HALFDUPLEX
Definition: gd32f10x_enet.h:765
enet_initpara_struct::store_forward_mode
uint32_t store_forward_mode
Definition: gd32f10x_enet.h:847
ENET_DMA_FLAG_RO
Definition: gd32f10x_enet.h:588
enet_flag_enum
enet_flag_enum
Definition: gd32f10x_enet.h:562
ENET_DMA_INT_FLAG_ER_CLR
Definition: gd32f10x_enet.h:714
DMA_ARBITRATION_OPTION
Definition: gd32f10x_enet.h:747
enet_initpara_struct::dma_function
uint32_t dma_function
Definition: gd32f10x_enet.h:848
ENET_MAC_FLAG_MSCT
Definition: gd32f10x_enet.h:573
ENET_PTP_ADDEND_UPDATE
Definition: gd32f10x_enet.h:1246
MSC_RINTF_REG_OFFSET
#define MSC_RINTF_REG_OFFSET
Definition: gd32f10x_enet.h:541
enet_init
ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept)
initialize ENET peripheral with generally concerned parameters and the less cared parameters ...
Definition: gd32f10x_enet.c:280
ENET_PTP_FINEMODE
Definition: gd32f10x_enet.h:1247
RXDESC_BUFFER_1_ADDR
Definition: gd32f10x_enet.h:836
ENET_MSC_INT_TGFSCIM
Definition: gd32f10x_enet.h:639
MSC_RFAECNT_REG_OFFSET
#define MSC_RFAECNT_REG_OFFSET
Definition: gd32f10x_enet.h:549
ENET_TX_DESC_TABLE
Definition: gd32f10x_enet.h:725
enet_wum_feature_enable
void enet_wum_feature_enable(uint32_t feature)
enable wakeup management features
Definition: gd32f10x_enet.c:2500
ENET_REGIDX_BIT
#define ENET_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_enet.h:521
MAC_INTMSK_REG_OFFSET
#define MAC_INTMSK_REG_OFFSET
Definition: gd32f10x_enet.h:539
ENET_DMA_INT_FLAG_RS_CLR
Definition: gd32f10x_enet.h:708
enet_frame_transmit
ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length)
handle application buffer data to transmit it
Definition: gd32f10x_enet.c:864
ENET_MAC_INT_TMSTIM
Definition: gd32f10x_enet.h:633
enet_phy_write_read
ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
write to / read from a PHY register
Definition: gd32f10x_enet.c:1454
enet_ptp_systime_struct::second
uint32_t second
Definition: gd32f10x_enet.h:871
ENET_MSC_FLAG_RGUF
Definition: gd32f10x_enet.h:578
enet_rxprocess_check_recovery
void enet_rxprocess_check_recovery(void)
check and recover the Rx process
Definition: gd32f10x_enet.c:1788
ENET_DMA_FLAG_ER_CLR
Definition: gd32f10x_enet.h:623
MSC_RINTMSK_REG_OFFSET
#define MSC_RINTMSK_REG_OFFSET
Definition: gd32f10x_enet.h:543
enet_msc_feature_disable
void enet_msc_feature_disable(uint32_t feature)
disable the MAC statistics counter features
Definition: gd32f10x_enet.c:2554
ENET_DMA_FLAG_ET_CLR
Definition: gd32f10x_enet.h:621
enet_initpara_struct::hashtable_low
uint32_t hashtable_low
Definition: gd32f10x_enet.h:852
ENET_MAC_INT_FLAG_MSCR
Definition: gd32f10x_enet.h:666
ENET_MSC_INT_RFAEIM
Definition: gd32f10x_enet.h:636
enet_forward_feature_enable
void enet_forward_feature_enable(uint32_t feature)
enable ENET forward feature
Definition: gd32f10x_enet.c:1547
enet_ptp_start
void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg)
configure and start PTP timestamp counter
Definition: gd32f10x_enet.c:2798
ENET_DMA_FLAG_RBU
Definition: gd32f10x_enet.h:591
enet_mac_address_set
void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[])
configure MAC address
Definition: gd32f10x_enet.c:978
enet_dmadirection_enum
enet_dmadirection_enum
Definition: gd32f10x_enet.h:799
ENET_BROADCAST_FRAMES_PASS
Definition: gd32f10x_enet.h:785
ENET_DMA_INT_RPSIE
Definition: gd32f10x_enet.h:651
ENET_DMA_FLAG_FBE
Definition: gd32f10x_enet.h:595
enet_current_desc_address_get
uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get)
get the transmit/receive address of current descriptor, or current buffer, or descriptor table ...
Definition: gd32f10x_enet.c:1846
ENET_REG_READ
Definition: gd32f10x_enet.h:815
enet_rx_desc_immediate_receive_complete_interrupt
void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc)
when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set ...
Definition: gd32f10x_enet.c:2032
ENET_REG_WRITE
Definition: gd32f10x_enet.h:816
enet_ptp_subsecond_2_nanosecond
uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond)
change subsecond to nanosecond
Definition: gd32f10x_enet.c:2587
STORE_OPTION
Definition: gd32f10x_enet.h:748
ENET_DMA_FLAG_NI_CLR
Definition: gd32f10x_enet.h:625
ENET_DMA_INT_FLAG_TU_CLR
Definition: gd32f10x_enet.h:707
enet_phyloopback_disable
ErrStatus enet_phyloopback_disable(void)
disable the loopback function of PHY chip
Definition: gd32f10x_enet.c:1520
ENET_MSC_INT_FLAG_RGUF
Definition: gd32f10x_enet.h:672
TIMER_OPTION
Definition: gd32f10x_enet.h:756
INTERFRAMEGAP_OPTION
Definition: gd32f10x_enet.h:757
ALL_MSC_REG
Definition: gd32f10x_enet.h:793
ENET_DMA_INT_TJTIE
Definition: gd32f10x_enet.h:646
ENET_NO_AUTOCHECKSUM
Definition: gd32f10x_enet.h:774
enet_address_filter_disable
void enet_address_filter_disable(enet_macaddress_enum mac_addr)
disable the MAC address filter
Definition: gd32f10x_enet.c:1348
ENET_DMA_FLAG_ER
Definition: gd32f10x_enet.h:596
ENET_AUTO_NEGOTIATION
Definition: gd32f10x_enet.h:763
ENET_DMA_FLAG_NI
Definition: gd32f10x_enet.h:598
enet_address_filter_enable
void enet_address_filter_enable(enet_macaddress_enum mac_addr)
enable the MAC address filter
Definition: gd32f10x_enet.c:1333
ENET_DMA_FLAG_RBU_CLR
Definition: gd32f10x_enet.h:618
enet_ptp_subsecond_increment_config
void enet_ptp_subsecond_increment_config(uint32_t subsecond)
configure system time subsecond increment value
Definition: gd32f10x_enet.c:2713
ENET_DMA_INT_RIE
Definition: gd32f10x_enet.h:649
ENET_DMA_FLAG_WUM
Definition: gd32f10x_enet.h:603
VLAN_OPTION
Definition: gd32f10x_enet.h:750
enet_initpara_struct::forward_frame
uint32_t forward_frame
Definition: gd32f10x_enet.h:843
ENET_DMA_INT_TUIE
Definition: gd32f10x_enet.h:648
enet_option_enum
enet_option_enum
Definition: gd32f10x_enet.h:742
ENET_10M_HALFDUPLEX
Definition: gd32f10x_enet.h:767
ENET_MAC_FLAG_MSC
Definition: gd32f10x_enet.h:571
ENET_PROMISCUOUS_MODE
Definition: gd32f10x_enet.h:783
ENET_MSC_TX_MSCCNT
Definition: gd32f10x_enet.h:734
ENET_MAC_FLAG_WUM
Definition: gd32f10x_enet.h:570
enet_interrupt_flag_clear
void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear)
clear ENET DMA interrupt flag
Definition: gd32f10x_enet.c:1236
ENET_DMA_INT_FBEIE
Definition: gd32f10x_enet.h:654
enet_descriptors_ring_init
void enet_descriptors_ring_init(enet_dmadirection_enum direction)
initialize the DMA Tx/Rx descriptors's parameters in ring mode
Definition: gd32f10x_enet.c:719
ENET_DMA_INT_FLAG_WUM
Definition: gd32f10x_enet.h:694
ENET_DMA_INT_FLAG_ER
Definition: gd32f10x_enet.h:690
enet_rxframe_drop
void enet_rxframe_drop(void)
drop current receive frame
Definition: gd32f10x_enet.c:2043
ENET_DMA_FLAG_TJT_CLR
Definition: gd32f10x_enet.h:614
ENET_MAC_INT_FLAG_TMST
Definition: gd32f10x_enet.h:668
enet_ptp_function_enum
enet_ptp_function_enum
Definition: gd32f10x_enet.h:1243
MAC_WUM_REG_OFFSET
#define MAC_WUM_REG_OFFSET
Definition: gd32f10x_enet.h:537
enet_descriptors_struct::buffer2_next_desc_addr
uint32_t buffer2_next_desc_addr
Definition: gd32f10x_enet.h:865
DMA_STAT_REG_OFFSET
#define DMA_STAT_REG_OFFSET
Definition: gd32f10x_enet.h:552
enet_initpara_struct::timer_config
uint32_t timer_config
Definition: gd32f10x_enet.h:855
ENET_PTP_COARSEMODE
Definition: gd32f10x_enet.h:1248
MAC_FCTL_REG_OFFSET
#define MAC_FCTL_REG_OFFSET
Definition: gd32f10x_enet.h:536
ENET_DMA_INT_FLAG_RWT
Definition: gd32f10x_enet.h:687
ENET_DMA_INT_FLAG_AI
Definition: gd32f10x_enet.h:691
ENET_DMA_INT_FLAG_RBU
Definition: gd32f10x_enet.h:685
ENET_MSC_RX_RFAECNT
Definition: gd32f10x_enet.h:737
ENET_MSC_INT_TGFIM
Definition: gd32f10x_enet.h:641
ENET_MAC_CFG_SPD
#define ENET_MAC_CFG_SPD
Definition: gd32f10x_enet.h:165
enet_rxframe_size_get
uint32_t enet_rxframe_size_get(void)
check receive frame valid and return frame size
Definition: gd32f10x_enet.c:591
ENET_DMA_FLAG_ET
Definition: gd32f10x_enet.h:594
enet_phyloopback_enable
ErrStatus enet_phyloopback_enable(void)
enable the loopback function of PHY chip
Definition: gd32f10x_enet.c:1497
MSC_MSCCNT_REG_OFFSET
#define MSC_MSCCNT_REG_OFFSET
Definition: gd32f10x_enet.h:546
ENET_MAC_FLAG_FLOWCONTROL
Definition: gd32f10x_enet.h:568
DMA_OPTION
Definition: gd32f10x_enet.h:749
ENET_DMA_INT_FLAG_NI_CLR
Definition: gd32f10x_enet.h:716
enet_descstate_enum
enet_descstate_enum
Definition: gd32f10x_enet.h:829
enet_dma_feature_enable
void enet_dma_feature_enable(uint32_t feature)
enable DMA feature
Definition: gd32f10x_enet.c:2091
enet_initpara_struct::option_enable
uint32_t option_enable
Definition: gd32f10x_enet.h:842
enet_rx_disable
void enet_rx_disable(void)
ENET Rx function disable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1286
ENET_100M_FULLDUPLEX
Definition: gd32f10x_enet.h:764
enet_wum_filter_config
void enet_wum_filter_config(uint32_t pdata[])
set the remote wakeup frame registers
Definition: gd32f10x_enet.c:2480
ENET_DMA_FLAG_AI
Definition: gd32f10x_enet.h:597
ENET_MSC_INT_RGUFIM
Definition: gd32f10x_enet.h:637
DMA_TDTADDR_REG_OFFSET
#define DMA_TDTADDR_REG_OFFSET
Definition: gd32f10x_enet.h:554
ENET_TX_CURRENT_BUFFER
Definition: gd32f10x_enet.h:727
ENET_DMA_INT_ERIE
Definition: gd32f10x_enet.h:655
ENET_DMA_INT_FLAG_RPS_CLR
Definition: gd32f10x_enet.h:710
enet_descriptors_struct::status
uint32_t status
Definition: gd32f10x_enet.h:862
ENET_DMA_CTL_DTCERFD
#define ENET_DMA_CTL_DTCERFD
Definition: gd32f10x_enet.h:411
ENET_MAC_INT_WUMIM
Definition: gd32f10x_enet.h:632
MSC_RFCECNT_REG_OFFSET
#define MSC_RFCECNT_REG_OFFSET
Definition: gd32f10x_enet.h:548
ENET_10M_FULLDUPLEX
Definition: gd32f10x_enet.h:766
enet_initpara_struct
Definition: gd32f10x_enet.h:840
enet_ptp_normal_descriptors_ring_init
void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function ...
Definition: gd32f10x_enet.c:2199
enet_initpara_struct::vlan_config
uint32_t vlan_config
Definition: gd32f10x_enet.h:849
enet_descriptors_chain_init
void enet_descriptors_chain_init(enet_dmadirection_enum direction)
initialize the DMA Tx/Rx descriptors's parameters in chain mode
Definition: gd32f10x_enet.c:647
ENET_DMA_FLAG_RPS_CLR
Definition: gd32f10x_enet.h:619
ENET_DMA_INT_AIE
Definition: gd32f10x_enet.h:656
ENET_DMA_FLAG_EB_DMA_ERROR
Definition: gd32f10x_enet.h:599
ENET_DMA_FLAG_TS_CLR
Definition: gd32f10x_enet.h:611
enet_txfifo_flush
ErrStatus enet_txfifo_flush(void)
flush the ENET transmit FIFO, and wait until the flush operation completes
Definition: gd32f10x_enet.c:1810
enet_desc_flag_get
FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag)
get the bit flag of ENET DMA descriptor
Definition: gd32f10x_enet.c:1965
ENET_MAC_ADDRESS3
Definition: gd32f10x_enet.h:825
enet_ptpframe_receive_normal_mode
ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[])
receive a packet data with timestamp values to application buffer, when the DMA is in normal mode ...
Definition: gd32f10x_enet.c:2281
ENET_DMA_FLAG_FBE_CLR
Definition: gd32f10x_enet.h:622
enet_flowcontrol_feature_disable
void enet_flowcontrol_feature_disable(uint32_t feature)
disable ENET flow control feature
Definition: gd32f10x_enet.c:1734
ENET_MSC_INT_FLAG_TGFSC
Definition: gd32f10x_enet.h:674
ENET_DMA_INT_FLAG_RPS
Definition: gd32f10x_enet.h:686
enet_initpara_struct::dma_maxburst
uint32_t dma_maxburst
Definition: gd32f10x_enet.h:845
RXDESC_BUFFER_2_SIZE
Definition: gd32f10x_enet.h:835
ENET_DMA_FLAG_TU_CLR
Definition: gd32f10x_enet.h:616
ENET_DMA_INT_ROIE
Definition: gd32f10x_enet.h:647
DMA_CTDADDR_REG_OFFSET
#define DMA_CTDADDR_REG_OFFSET
Definition: gd32f10x_enet.h:555
ENET_MAC_CFG_IPFCO
#define ENET_MAC_CFG_IPFCO
Definition: gd32f10x_enet.h:161
ENET_MAC_FRMF_PM
#define ENET_MAC_FRMF_PM
Definition: gd32f10x_enet.h:172
enet_int_flag_enum
enet_int_flag_enum
Definition: gd32f10x_enet.h:661
enet_fliter_feature_disable
void enet_fliter_feature_disable(uint32_t feature)
disable ENET fliter feature
Definition: gd32f10x_enet.c:1612
enet_msc_counters_get
uint32_t enet_msc_counters_get(enet_msc_counter_enum counter)
get MAC statistics counter
Definition: gd32f10x_enet.c:2572
enet_descriptors_struct::buffer1_addr
uint32_t buffer1_addr
Definition: gd32f10x_enet.h:864
ENET_DMA_FLAG_TJT
Definition: gd32f10x_enet.h:587
ENET_PTP_TSCTL_TMSSTI
#define ENET_PTP_TSCTL_TMSSTI
Definition: gd32f10x_enet.h:321
ENET_DMA_FLAG_RWT
Definition: gd32f10x_enet.h:593
ENET_RX_DESC_TABLE
Definition: gd32f10x_enet.h:722
enet_interrupt_disable
void enet_interrupt_disable(enet_int_enum enet_int)
disable ENET MAC/MSC/DMA interrupt
Definition: gd32f10x_enet.c:1158
ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES
Definition: gd32f10x_enet.h:776
MSC_SCCNT_REG_OFFSET
#define MSC_SCCNT_REG_OFFSET
Definition: gd32f10x_enet.h:545
FORWARD_OPTION
Definition: gd32f10x_enet.h:744
enet_pauseframe_generate
ErrStatus enet_pauseframe_generate(void)
generate the pause frame, ENET will send pause frame after enable transmit flow control this function...
Definition: gd32f10x_enet.c:1624
enet_ptp_timestamp_function_config
ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
configure the PTP timestamp function
Definition: gd32f10x_enet.c:2647
enet_flowcontrol_feature_enable
void enet_flowcontrol_feature_enable(uint32_t feature)
enable ENET flow control feature
Definition: gd32f10x_enet.c:1714
DMA_CTBADDR_REG_OFFSET
#define DMA_CTBADDR_REG_OFFSET
Definition: gd32f10x_enet.h:556
enet_software_reset
ErrStatus enet_software_reset(void)
reset all core internal registers located in CLK_TX and CLK_RX
Definition: gd32f10x_enet.c:562
ENET_DMA_INT_FLAG_ET
Definition: gd32f10x_enet.h:688
ENET_DMA_INT_FLAG_TJT
Definition: gd32f10x_enet.h:681
enet_ptp_nanosecond_2_subsecond
uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
change nanosecond to subsecond
Definition: gd32f10x_enet.c:2600
enet_rx_enable
void enet_rx_enable(void)
ENET Rx function enable (include MAC and DMA module)
Definition: gd32f10x_enet.c:1274
enet_mac_address_get
void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[])
get MAC address
Definition: gd32f10x_enet.c:996
ENET_DMA_INT_FLAG_RS
Definition: gd32f10x_enet.h:684
ENET_DMA_RX
Definition: gd32f10x_enet.h:802
ENET_MSC_RX_RGUFCNT
Definition: gd32f10x_enet.h:738
ENET_DMA_INT_FLAG_RO_CLR
Definition: gd32f10x_enet.h:706
ENET_PHY_READ
Definition: gd32f10x_enet.h:808
enet_ptp_expected_time_config
void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond)
configure the expected target time
Definition: gd32f10x_enet.c:2754
enet_registers_type_enum
enet_registers_type_enum
Definition: gd32f10x_enet.h:790
ENET_DMA_INT_FLAG_TS
Definition: gd32f10x_enet.h:678
ENET_DMA_INT_FLAG_RO
Definition: gd32f10x_enet.h:682
enet_chksumconf_enum
enet_chksumconf_enum
Definition: gd32f10x_enet.h:772
enet_wum_feature_disable
void enet_wum_feature_disable(uint32_t feature)
disable wakeup management features
Definition: gd32f10x_enet.c:2514
enet_ptp_flag_get
FlagStatus enet_ptp_flag_get(uint32_t flag)
get the ptp flag status
Definition: gd32f10x_enet.c:2908
enet_int_flag_clear_enum
enet_int_flag_clear_enum
Definition: gd32f10x_enet.h:699
ENET_DMA_FLAG_MSC
Definition: gd32f10x_enet.h:602
enet_ptp_feature_enable
void enet_ptp_feature_enable(uint32_t feature)
enable the PTP features
Definition: gd32f10x_enet.c:2616
enet_initpara_struct::framesfilter_mode
uint32_t framesfilter_mode
Definition: gd32f10x_enet.h:853
enet_address_filter_config
void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type)
configure the MAC address filter
Definition: gd32f10x_enet.c:1375
ENET_MSC_FLAG_TGFSC
Definition: gd32f10x_enet.h:580
ENET_DMA_STAT_TP
#define ENET_DMA_STAT_TP
Definition: gd32f10x_enet.h:393
enet_mediamode_enum
enet_mediamode_enum
Definition: gd32f10x_enet.h:761
MSC_TINTF_REG_OFFSET
#define MSC_TINTF_REG_OFFSET
Definition: gd32f10x_enet.h:542
ENET_DMA_INT_FLAG_FBE_CLR
Definition: gd32f10x_enet.h:713
FILTER_OPTION
Definition: gd32f10x_enet.h:754
ENET_DMA_INT_FLAG_TS_CLR
Definition: gd32f10x_enet.h:702
ENET_DMA_INT_FLAG_TBU
Definition: gd32f10x_enet.h:680
ENET_DMA_FLAG_TU
Definition: gd32f10x_enet.h:589
ENET_MAC_CFG_LBM
#define ENET_MAC_CFG_LBM
Definition: gd32f10x_enet.h:163
MSC_RGUFCNT_REG_OFFSET
#define MSC_RGUFCNT_REG_OFFSET
Definition: gd32f10x_enet.h:550
enet_flag_clear
void enet_flag_clear(enet_flag_clear_enum enet_flag)
clear the ENET DMA status flag
Definition: gd32f10x_enet.c:1081
enet_flowcontrol_threshold_config
void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active)
configure the threshold of the flow control(deactive and active threshold)
Definition: gd32f10x_enet.c:1698
ENET_PTP_SYSTIME_UPDATE
Definition: gd32f10x_enet.h:1245
enet_regdirection_enum
enet_regdirection_enum
Definition: gd32f10x_enet.h:813
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usb_defines.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usb_defines.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USB_DEFINES_H
14 #define USB_DEFINES_H
15
16 #include "usb_conf.h"
17
18 #ifndef NULL
19 #define NULL (void *)0
20 #endif /* NULL */
21
22 #define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */
23 #define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */
24
25 #define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */
26 #define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */
27 #define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */
28 #define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */
29
30 #define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */
31 #define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */
32 #define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */
33 #define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */
34
35 #define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */
36 #define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */
37
38 #define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
39 #define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
40 #define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */
41 #define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */
42
43 #define GRSTATR_RPCKST_IN 2U /* IN data packet received */
44 #define GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */
45 #define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */
46 #define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */
47
48 #define DEVICE_MODE 0U /* USB core in device mode */
49 #define HOST_MODE 1U /* USB core in host mode */
50 #define OTG_MODE 2U /* USB core in OTG mode */
51
52 #define USB_EPTYPE_CTRL 0U /* USB control endpoint type */
53 #define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */
54 #define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */
55 #define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */
56 #define USB_EPTYPE_MASK 3U /* USB endpoint type mask */
57
58 #define RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */
59 #define RXSTAT_DATA_UPDT 2U /* OUT data packet received */
60 #define RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */
61 #define RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */
62 #define RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */
63
64 #define DPID_DATA0 0U /* device endpoint data PID is DATA0 */
65 #define DPID_DATA1 2U /* device endpoint data PID is DATA1 */
66 #define DPID_DATA2 1U /* device endpoint data PID is DATA2 */
67 #define DPID_MDATA 3U /* device endpoint data PID is MDATA */
68
69 #define HC_PID_DATA0 0U /* host channel data PID is DATA0 */
70 #define HC_PID_DATA2 1U /* host channel data PID is DATA2 */
71 #define HC_PID_DATA1 2U /* host channel data PID is DATA1 */
72 #define HC_PID_SETUP 3U /* host channel data PID is SETUP */
73
74 #define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */
75 #define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */
76 #define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */
77
78 #define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */
79 #define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */
80 #define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */
81
82 #define HCCHAR_CTRL 0U /* control channel type */
83 #define HCCHAR_ISOC 1U /* synchronous channel type */
84 #define HCCHAR_BULK 2U /* bulk channel type */
85 #define HCCHAR_INTR 3U /* interrupt channel type */
86
87 typedef enum
88 {
89 USB_HS_CORE_ID = 0,
90 USB_FS_CORE_ID = 1
91 }usb_core_id_enum;
92
93 typedef enum
94 {
95 USB_SPEED_UNKNOWN = 0,
96 USB_SPEED_LOW,
97 USB_SPEED_FULL,
98 USB_SPEED_HIGH
99 }usb_speed_enum;
100
101 #endif /* USB_DEFINES_H */
USB_HS_CORE_ID
Definition: usb_defines.h:89
USB_SPEED_FULL
Definition: usb_defines.h:97
usb_speed_enum
usb_speed_enum
Definition: usb_defines.h:93
USB_SPEED_UNKNOWN
Definition: usb_defines.h:95
USB_SPEED_HIGH
Definition: usb_defines.h:98
USB_SPEED_LOW
Definition: usb_defines.h:96
USB_FS_CORE_ID
Definition: usb_defines.h:90
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:87
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_misc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_misc.h"
14
26 void nvic_priority_group_set(uint32_t nvic_prigroup)
27 {
28 /* set the priority group value */
29 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
30 }
31
40 void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
41 uint8_t nvic_irq_sub_priority)
42 {
43 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
44 /* use the priority group value to get the temp_pre and the temp_sub */
45 if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
46 temp_pre=0U;
47 temp_sub=0x4U;
48 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
49 temp_pre=1U;
50 temp_sub=0x3U;
51 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
52 temp_pre=2U;
53 temp_sub=0x2U;
54 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
55 temp_pre=3U;
56 temp_sub=0x1U;
57 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
58 temp_pre=4U;
59 temp_sub=0x0U;
60 }else{
61 }
62 /* get the temp_priority to fill the NVIC->IP register */
63 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
64 temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
65 temp_priority = temp_priority << 0x04U;
66 NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
67 /* enable the selected IRQ */
68 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
69 }
70
77 void nvic_irq_disable(uint8_t nvic_irq)
78 {
79 /* disable the selected IRQ.*/
80 NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
81 }
82
92 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
93 {
94 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
95 }
96
108 void system_lowpower_set(uint8_t lowpower_mode)
109 {
110 SCB->SCR |= (uint32_t)lowpower_mode;
111 }
112
124 void system_lowpower_reset(uint8_t lowpower_mode)
125 {
126 SCB->SCR &= (~(uint32_t)lowpower_mode);
127 }
128
138 void systick_clksource_set(uint32_t systick_clksource)
139 {
140 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
141 /* set the systick clock source from HCLK */
142 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
143 }else{
144 /* set the systick clock source from HCLK/8 */
145 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
146 }
147 }
nvic_priority_group_set
void nvic_priority_group_set(uint32_t nvic_prigroup)
set the priority group
Definition: gd32f10x_misc.c:26
NVIC_PRIGROUP_PRE2_SUB2
#define NVIC_PRIGROUP_PRE2_SUB2
Definition: gd32f10x_misc.h:32
NVIC_VECTTAB_OFFSET_MASK
#define NVIC_VECTTAB_OFFSET_MASK
Definition: gd32f10x_misc.h:24
NVIC_AIRCR_VECTKEY_MASK
#define NVIC_AIRCR_VECTKEY_MASK
Definition: gd32f10x_misc.h:27
NVIC_PRIGROUP_PRE3_SUB1
#define NVIC_PRIGROUP_PRE3_SUB1
Definition: gd32f10x_misc.h:33
NVIC_PRIGROUP_PRE0_SUB4
#define NVIC_PRIGROUP_PRE0_SUB4
Definition: gd32f10x_misc.h:30
SYSTICK_CLKSOURCE_HCLK_DIV8
#define SYSTICK_CLKSOURCE_HCLK_DIV8
Definition: gd32f10x_misc.h:46
system_lowpower_reset
void system_lowpower_reset(uint8_t lowpower_mode)
reset the state of the low power mode
Definition: gd32f10x_misc.c:124
nvic_irq_enable
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority)
enable NVIC request
Definition: gd32f10x_misc.c:40
nvic_irq_disable
void nvic_irq_disable(uint8_t nvic_irq)
disable NVIC request
Definition: gd32f10x_misc.c:77
gd32f10x_misc.h
definitions for the MISC
system_lowpower_set
void system_lowpower_set(uint8_t lowpower_mode)
set the state of the low power mode
Definition: gd32f10x_misc.c:108
NVIC_PRIGROUP_PRE1_SUB3
#define NVIC_PRIGROUP_PRE1_SUB3
Definition: gd32f10x_misc.h:31
NVIC_PRIGROUP_PRE4_SUB0
#define NVIC_PRIGROUP_PRE4_SUB0
Definition: gd32f10x_misc.h:34
systick_clksource_set
void systick_clksource_set(uint32_t systick_clksource)
set the systick clock source
Definition: gd32f10x_misc.c:138
SYSTICK_CLKSOURCE_HCLK
#define SYSTICK_CLKSOURCE_HCLK
Definition: gd32f10x_misc.h:47
nvic_vector_table_set
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
set the NVIC vector table base address
Definition: gd32f10x_misc.c:92
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbd_driver/Source/usbd_std.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbd_driver
  • Source
usbd_std.c
Go to the documentation of this file.
1
7 /*
8 Copyright (C) 2017 GigaDevice
9
10 2014-12-26, V1.0.0, firmware for GD32F10x
11 2017-06-20, V2.0.0, firmware for GD32F10x
12 */
13
14 #include "usbd_std.h"
15
16 uint8_t g_device_address = 0U;
17
18 /* USB enumeration handle functions */
19 static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
20 static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
21 static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
22 static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
23 static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
24 static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
25 static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
26 static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
27 static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
28 static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
29 static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
30 static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req);
31
32 static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev,
33 uint8_t index,
34 uint16_t *pLen);
35
36 static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev,
37 uint8_t index,
38 uint16_t *pLen);
39
40 static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev,
41 uint8_t index,
42 uint16_t *pLen);
43
44 #ifdef LPM_ENABLED
45 static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen);
46 #endif /* LPM_ENABLED */
47
48 /* standard device request handler */
49 static void (*standard_device_request[])(usbd_core_handle_struct *pudev, usb_device_req_struct *req) =
50 {
51 usbd_getstatus,
52 usbd_clearfeature,
53 usbd_reserved,
54 usbd_setfeature,
55 usbd_reserved,
56 usbd_setaddress,
57 usbd_getdescriptor,
58 usbd_setdescriptor,
59 usbd_getconfiguration,
60 usbd_setconfiguration,
61 usbd_getinterface,
62 usbd_setinterface,
63 usbd_synchframe,
64 };
65
66 /* get standard descriptor handler */
67 static uint8_t* (*standard_descriptor_get[])(usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) =
68 {
69 usbd_device_descriptor_get,
70 usbd_configuration_descriptor_get,
71 usbd_string_descriptor_get
72 };
73
80 uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev)
81 {
82 usb_device_req_struct req;
83
84 usbd_setup_request_parse (pudev, &req);
85
86 switch (req.bmRequestType & USB_REQ_MASK) {
87 /* standard device request */
88 case USB_STANDARD_REQ:
89 usbd_standard_request(pudev, &req);
90 break;
91 /* device class request */
92 case USB_CLASS_REQ:
93 usbd_device_class_request(pudev, &req);
94 break;
95 /* vendor defined request */
96 case USB_VENDOR_REQ:
97 usbd_vendor_request(pudev, &req);
98 break;
99 default:
100 usbd_ep_stall(pudev, 0x00U);
101 break;
102 }
103 return USBD_OK;
104 }
105
113 uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num)
114 {
115 usb_ep_struct *ep = &pudev->out_ep[ep_num];
116
117 if (0U == ep_num) {
118 if (0U != pudev->ctl_count) {
119 if (ep->trs_len > ep->maxpacket) {
120 /* one data packet has been received, update trs_len */
121 ep->trs_len -= ep->maxpacket;
122
123 /* continue to receive remain data */
124 usbd_ep_rx(pudev, EP0_OUT, ep->trs_buf, (uint16_t)ep->trs_len);
125 } else {
126 if (USBD_CONFIGURED == pudev->status) {
127 /* device class handle */
128 pudev->class_data_handler(pudev, USBD_RX, EP0);
129 }
130
131 /* enter the control transaction status stage */
132 USBD_CONTRL_STATUS_TX();
133
134 pudev->ctl_count = 0U;
135 }
136 } else {
137 /* clear endpoint status_out status */
138 USBD_STATUS_OUT_CLEAR(EP0);
139 }
140 } else {
141 if (USBD_CONFIGURED == pudev->status) {
142 pudev->class_data_handler(pudev, USBD_RX, ep_num);
143 }
144 }
145 return USBD_OK;
146 }
147
155 uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num)
156 {
157 usb_ep_struct *ep = &pudev->in_ep[ep_num];
158
159 if (0U == ep_num) {
160 if (0U != pudev->ctl_count) {
161 if (ep->trs_len > ep->maxpacket) {
162 /* one data packet has been transmited, update trs_len */
163 ep->trs_len -= ep->maxpacket;
164
165 /* continue to transmit remain data */
166 usbd_ep_tx (pudev, EP0_IN, ep->trs_buf, (uint16_t)ep->trs_len);
167
168 usbd_ep_rx (pudev, 0, NULL, 0);
169 } else {
170 #ifndef USB_DFU
171 /* transmit length is maxpacket multiple, so send zero length packet */
172 if ((0U == (ep->trs_len % ep->maxpacket)) && (ep->trs_len < pudev->ctl_count)) {
173 usbd_ep_tx (pudev, EP0_IN, NULL, 0U);
174
175 pudev->ctl_count = 0U;
176
177 usbd_ep_rx (pudev, 0, NULL, 0);
178 } else
179 #endif /* USB_DFU */
180 {
181 ep->trs_len = 0U;
182
183 if (USBD_CONFIGURED == pudev->status) {
184 pudev->class_data_handler(pudev, USBD_TX, EP0);
185 }
186
187 USBD_CONTRL_STATUS_RX();
188
189 pudev->ctl_count = 0U;
190 }
191 }
192 } else {
193 if (0U != g_device_address) {
194 USBD_REG_SET(USBD_DADDR, DADDR_USBEN | g_device_address);
195 g_device_address = 0U;
196 }
197 }
198 } else {
199 ep->trs_len -= ep->trs_count;
200
201 if (0U == ep->trs_len) {
202 if (USBD_CONFIGURED == pudev->status) {
203 pudev->class_data_handler(pudev, USBD_TX, ep_num);
204 }
205 } else {
206 usbd_ep_tx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len);
207 }
208 }
209
210 return USBD_OK;
211 }
212
220 uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
221 {
222 /* call device request handle function */
223 (*standard_device_request[req->bRequest])(pudev, req);
224
225 return USBD_OK;
226 }
227
235 uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
236 {
237 usbd_status_enum ret;
238
239 switch (pudev->status) {
240 case USBD_CONFIGURED:
241 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
242 /* call device class handle function */
243 ret = (usbd_status_enum)(pudev->class_req_handler(pudev, req));
244
245 if ((0U == req->wLength) && (USBD_OK == ret)) {
246 /* no data stage */
247 USBD_CONTRL_STATUS_TX();
248 }
249 } else {
250 usbd_enum_error(pudev, req);
251 }
252 break;
253 default:
254 usbd_enum_error(pudev, req);
255 break;
256 }
257
258 return USBD_OK;
259 }
260
268 uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
269 {
270 /* added by user */
271
272 return USBD_OK;
273 }
274
282 static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
283 {
284 /* no operation */
285 }
286
287 #ifdef LPM_ENABLED
288
289 static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen)
290 {
291 *pLen = pudev->bos_desc[2] | ((uint16_t)pudev->bos_desc[3] << 8);
292
293 return pudev->bos_desc;
294 }
295
296 #endif /* LPM_ENABLED */
297
305 static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen)
306 {
307 *pLen = pudev->dev_desc[0];
308
309 return pudev->dev_desc;
310 }
311
319 static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen)
320 {
321 *pLen = pudev->config_desc[2];
322
323 return pudev->config_desc;
324 }
325
333 static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen)
334 {
335 uint8_t *desc = pudev->strings[index];
336
337 *pLen = desc[0];
338
339 return desc;
340 }
341
349 static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
350 {
351 uint8_t ep_addr;
352 uint16_t config_status = 0x0000U;
353 uint16_t endp_status = 0x0000U;
354
355 switch(req->bmRequestType & USB_REQ_RECIPIENT_MASK) {
356 case USB_REQTYPE_DEVICE:
357 switch (pudev->status) {
358 case USBD_ADDRESSED:
359 case USBD_CONFIGURED:
360
361 #ifdef USBD_SELF_POWERED
362 config_status = USB_STATUS_SELF_POWERED;
363 #endif /* USBD_SELF_POWERED */
364
365 if (pudev->remote_wakeup) {
366 config_status |= USB_STATUS_REMOTE_WAKEUP;
367 }
368
369 usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U);
370 break;
371 default:
372 break;
373 }
374 break;
375 case USB_REQTYPE_INTERFACE:
376 switch (pudev->status) {
377 case USBD_ADDRESSED:
378 usbd_enum_error(pudev, req);
379 break;
380 case USBD_CONFIGURED:
381 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
382 usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U);
383 } else {
384 usbd_enum_error(pudev, req);
385 }
386 break;
387 default:
388 break;
389 }
390 break;
391 case USB_REQTYPE_ENDPOINT:
392 /* get enndpoint address */
393 ep_addr = LOWBYTE(req->wIndex);
394
395 switch (pudev->status) {
396 case USBD_ADDRESSED:
397 if (IS_NOT_EP0(ep_addr)) {
398 usbd_enum_error(pudev, req);
399 }
400 break;
401 case USBD_CONFIGURED:
402 if ((ep_addr & 0x80U) == 0x80U) {
403 if(pudev->in_ep[ep_addr & 0x7FU].stall) {
404 endp_status = 0x0001U;
405 }
406 } else {
407 if (pudev->out_ep[ep_addr].stall) {
408 endp_status = 0x0001U;
409 }
410 }
411 usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&endp_status, 2U);
412 break;
413
414 default:
415 break;
416 }
417 break;
418 default:
419 usbd_enum_error(pudev, req);
420 break;
421 }
422 }
423
431 static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
432 {
433 uint8_t ep_addr = 0U;
434
435 switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) {
436 case USB_REQTYPE_DEVICE:
437 switch (pudev->status) {
438 case USBD_ADDRESSED:
439 case USBD_CONFIGURED:
440 /* clear device remote wakeup feature */
441 if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
442 pudev->remote_wakeup = 0U;
443 pudev->class_req_handler(pudev, req);
444 USBD_CONTRL_STATUS_TX();
445 } else if (USB_FEATURE_TEST_MODE == req->wValue) {
446 /* can not clear test_mode feature */
447 usbd_enum_error(pudev, req);
448 } else {
449 /* no operation */
450 }
451 break;
452 default:
453 break;
454 }
455 break;
456 case USB_REQTYPE_INTERFACE:
457 switch (pudev->status) {
458 case USBD_ADDRESSED:
459 usbd_enum_error (pudev, req);
460 break;
461 case USBD_CONFIGURED:
462 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
463 /* no operation */
464 } else {
465 usbd_enum_error(pudev, req);
466 }
467 break;
468 default:
469 break;
470 }
471 break;
472 case USB_REQTYPE_ENDPOINT:
473 /* get endpoint address */
474 ep_addr = LOWBYTE(req->wIndex);
475
476 switch (pudev->status) {
477 case USBD_ADDRESSED:
478 if (IS_NOT_EP0(ep_addr)) {
479 usbd_enum_error(pudev, req);
480 }
481 break;
482 case USBD_CONFIGURED:
483 /* clear endpoint halt feature */
484 if (USB_FEATURE_ENDP_HALT == req->wValue) {
485 if (IS_NOT_EP0(ep_addr)) {
486 usbd_ep_clear_stall(pudev, ep_addr);
487 }
488 }
489
490 pudev->class_req_handler(pudev, req);
491
492 USBD_CONTRL_STATUS_TX();
493 break;
494 default:
495 break;
496 }
497 break;
498 default:
499 usbd_enum_error(pudev, req);
500 break;
501 }
502 }
503
511 static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
512 {
513 uint8_t ep_addr = 0U;
514
515 switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) {
516 case USB_REQTYPE_DEVICE:
517 switch (pudev->status) {
518 case USBD_ADDRESSED:
519 case USBD_CONFIGURED:
520 /* set device remote wakeup feature */
521 if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
522 pudev->remote_wakeup = 1U;
523
524 USBD_CONTRL_STATUS_TX();
525 }
526 break;
527 default:
528 break;
529 }
530 break;
531 case USB_REQTYPE_INTERFACE:
532 switch (pudev->status) {
533 case USBD_ADDRESSED:
534 usbd_enum_error(pudev, req);
535 break;
536 case USBD_CONFIGURED:
537 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
538 /* no operation */
539 } else {
540 usbd_enum_error(pudev, req);
541 }
542 break;
543 default:
544 break;
545 }
546 break;
547 case USB_REQTYPE_ENDPOINT:
548 /* get endpoint address */
549 ep_addr = LOWBYTE(req->wIndex);
550
551 switch (pudev->status) {
552 case USBD_ADDRESSED:
553 if (IS_NOT_EP0(ep_addr)) {
554 usbd_enum_error(pudev, req);
555 }
556 break;
557 case USBD_CONFIGURED:
558 /* set endpoint halt feature */
559 if (USB_FEATURE_ENDP_HALT == req->wValue) {
560 if (IS_NOT_EP0(ep_addr)) {
561 usbd_ep_stall(pudev, ep_addr);
562 }
563 }
564 USBD_CONTRL_STATUS_TX();
565 break;
566 default:
567 break;
568 }
569 break;
570 default:
571 usbd_enum_error(pudev, req);
572 break;
573 }
574 }
575
583 static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
584 {
585 if ((0U == req->wIndex) && (0U == req->wLength)) {
586 g_device_address = (uint8_t)(req->wValue) & 0x7FU;
587
588 if (USBD_CONFIGURED == pudev->status) {
589 usbd_enum_error(pudev, req);
590 } else {
591 USBD_CONTRL_STATUS_TX();
592
593 if (0U != g_device_address) {
594 pudev->status = USBD_ADDRESSED;
595 } else {
596 pudev->status = USBD_DEFAULT;
597 }
598 }
599 } else {
600 usbd_enum_error(pudev, req);
601 }
602 }
603
611 static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
612 {
613 if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) {
614 uint8_t *pbuf = NULL;
615 uint8_t desc_index = (uint8_t)(req->wValue >> 8);
616 uint16_t len = 0U;
617
618 if (desc_index <= 0x03U) {
619 /* call corresponding descriptor get function */
620 pbuf = standard_descriptor_get[desc_index - 1U](pudev, (uint8_t)(req->wValue) & 0xFFU, &len);
621 }
622 #ifdef LPM_ENABLED
623 else if (USB_DESCTYPE_BOS == desc_index) {
624 pbuf = usbd_bos_descriptor_get(pudev, &len);
625 }
626 #endif /* LPM_ENABLED */
627 else {
628 usbd_enum_error(pudev, req);
629 }
630
631 if ((0U != len) && (0U != req->wLength)) {
632 len = MIN(len, req->wLength);
633
634 usbd_ep_tx (pudev, EP0_IN, pbuf, len);
635 }
636 } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) {
637 if (NULL != pudev->class_req_handler) {
638 /* get device class special descriptor */
639 pudev->class_req_handler(pudev, req);
640 }
641 } else {
642
643 }
644 }
645
653 static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
654 {
655 /* no handle */
656 }
657
665 static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
666 {
667 uint32_t usbd_default_config = 0U;
668
669 if (req->wLength != 1) {
670 usbd_enum_error(pudev, req);
671 } else {
672 switch (pudev->status) {
673 case USBD_ADDRESSED:
674 usbd_ep_tx (pudev, EP0_IN, (uint8_t *)&usbd_default_config, 1U);
675 break;
676 case USBD_CONFIGURED:
677 usbd_ep_tx (pudev, EP0_IN, &pudev->config_num, 1);
678 break;
679 default:
680 usbd_enum_error(pudev, req);
681 break;
682 }
683 }
684 }
685
693 static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
694 {
695 static uint8_t cfgidx;
696
697 cfgidx = (uint8_t)(req->wValue);
698
699 if (cfgidx > USBD_CFG_MAX_NUM) {
700 usbd_enum_error(pudev, req);
701 } else {
702 switch (pudev->status) {
703 case USBD_ADDRESSED:
704 if (cfgidx){
705 pudev->config_num = cfgidx;
706 pudev->status = USBD_CONFIGURED;
707 pudev->class_init(pudev, cfgidx);
708 USBD_CONTRL_STATUS_TX();
709 } else {
710 USBD_CONTRL_STATUS_TX();
711 }
712 break;
713 case USBD_CONFIGURED:
714 if (0U == cfgidx) {
715 pudev->status = USBD_ADDRESSED;
716 pudev->config_num = cfgidx;
717 pudev->class_deinit(pudev, cfgidx);
718 USBD_CONTRL_STATUS_TX();
719 } else if (cfgidx != pudev->config_num) {
720 /* clear old configuration */
721 pudev->class_deinit(pudev, pudev->config_num);
722
723 /* set new configuration */
724 pudev->config_num = cfgidx;
725 pudev->class_init(pudev, cfgidx);
726 USBD_CONTRL_STATUS_TX();
727 } else {
728 USBD_CONTRL_STATUS_TX();
729 }
730 break;
731 default:
732 break;
733 }
734 }
735 }
736
744 static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
745 {
746 switch (pudev->status) {
747 case USBD_ADDRESSED:
748 usbd_enum_error(pudev, req);
749 break;
750 case USBD_CONFIGURED:
751 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
752 if (NULL != pudev->class_req_handler) {
753 pudev->class_req_handler(pudev, req);
754 }
755 } else {
756 usbd_enum_error(pudev, req);
757 }
758 break;
759 default:
760 break;
761 }
762 }
763
771 static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
772 {
773 switch (pudev->status) {
774 case USBD_ADDRESSED:
775 usbd_enum_error(pudev, req);
776 break;
777 case USBD_CONFIGURED:
778 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
779 if (NULL != pudev->class_req_handler) {
780 pudev->class_req_handler(pudev, req);
781 }
782
783 USBD_CONTRL_STATUS_TX();
784 } else {
785 usbd_enum_error(pudev, req);
786 }
787 break;
788 default:
789 break;
790 }
791 }
792
800 static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
801 {
802 /* no handle */
803 }
804
812 void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
813 {
814 uint8_t *setup_data = pudev->setup_packet;
815
816 req->bmRequestType = *setup_data;
817 req->bRequest = *(uint8_t *)(setup_data + 1U);
818 req->wValue = SWAPBYTE (setup_data + 2U);
819 req->wIndex = SWAPBYTE (setup_data + 4U);
820 req->wLength = SWAPBYTE (setup_data + 6U);
821
822 pudev->ctl_count = req->wLength;
823 }
824
832 void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req)
833 {
834 usbd_ep_stall(pudev, EP0);
835 }
EP0_IN
#define EP0_IN
Definition: usbd_regs.h:172
usbd_standard_request
uint8_t usbd_standard_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB standard device request
Definition: usbd_std.c:220
usb_ep_struct::trs_buf
uint8_t * trs_buf
Definition: usbd_core.h:109
USB_REQTYPE_ENDPOINT
#define USB_REQTYPE_ENDPOINT
Definition: usbd_std.h:41
usbd_core_handle_struct::dev_desc
uint8_t * dev_desc
Definition: usbd_core.h:146
usb_device_req_struct::wIndex
uint16_t wIndex
Definition: usbd_core.h:120
DADDR_USBEN
#define DADDR_USBEN
Definition: usbd_regs.h:75
USBD_ADDRESSED
Definition: usbd_core.h:75
USBD_REG_SET
#define USBD_REG_SET(reg, regvalue)
Definition: usbd_regs.h:201
usb_device_req_struct::wLength
uint16_t wLength
Definition: usbd_core.h:121
USB_VENDOR_REQ
#define USB_VENDOR_REQ
Definition: usbd_std.h:36
MIN
#define MIN(a, b)
Definition: usbd_std.h:84
EP0
#define EP0
Definition: usbd_regs.h:189
USB_CLASS_REQ
#define USB_CLASS_REQ
Definition: usbd_std.h:35
usbd_ep_stall
void usbd_ep_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:264
usbd_ep_tx
void usbd_ep_tx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:229
usb_ep_struct::trs_len
uint32_t trs_len
Definition: usbd_core.h:110
usb_device_req_struct
Definition: usbd_core.h:115
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usbd_std.h:39
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usbd_std.h:78
usbd_core_handle_struct::strings
void *const * strings
Definition: usbd_core.h:148
USBD_CONTRL_STATUS_TX
#define USBD_CONTRL_STATUS_TX()
Definition: usbd_core.h:33
usbd_core_handle_struct::ctl_count
uint32_t ctl_count
Definition: usbd_core.h:136
usbd_ep_clear_stall
void usbd_ep_clear_stall(usbd_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status
Definition: usbd_core.c:297
usbd_core_handle_struct::class_init
usbd_status_enum(* class_init)(void *pudev, uint8_t config_index)
Definition: usbd_core.h:151
usbd_core_handle_struct::setup_packet
uint8_t setup_packet[8]
Definition: usbd_core.h:135
usbd_core_handle_struct::out_ep
usb_ep_struct out_ep[EP_COUNT]
Definition: usbd_core.h:140
USBD_DEFAULT
Definition: usbd_core.h:74
USB_REQTYPE_INTERFACE
#define USB_REQTYPE_INTERFACE
Definition: usbd_std.h:40
usbd_core_handle_struct::class_data_handler
usbd_status_enum(* class_data_handler)(void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num)
Definition: usbd_core.h:154
IS_NOT_EP0
#define IS_NOT_EP0(ep_addr)
Definition: usbd_std.h:86
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usbd_core.h:117
USB_DESCTYPE_BOS
#define USB_DESCTYPE_BOS
Definition: usbd_std.h:61
usbd_ep_rx
void usbd_ep_rx(usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:202
usb_ep_struct::maxpacket
uint32_t maxpacket
Definition: usbd_core.h:106
usbd_core_handle_struct::config_num
uint8_t config_num
Definition: usbd_core.h:128
LOWBYTE
#define LOWBYTE(x)
Definition: usbd_std.h:81
usbd_core_handle_struct::remote_wakeup
uint8_t remote_wakeup
Definition: usbd_core.h:131
usbd_core_handle_struct
Definition: usbd_core.h:125
usb_ep_struct
Definition: usbd_core.h:102
usbd_device_class_request
uint8_t usbd_device_class_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB device class request
Definition: usbd_std.c:235
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usbd_std.h:34
USB_FEATURE_REMOTE_WAKEUP
#define USB_FEATURE_REMOTE_WAKEUP
Definition: usbd_std.h:67
USB_FEATURE_TEST_MODE
#define USB_FEATURE_TEST_MODE
Definition: usbd_std.h:68
USBD_OK
Definition: usbd_core.h:84
usbd_core_handle_struct::in_ep
usb_ep_struct in_ep[EP_COUNT]
Definition: usbd_core.h:139
USBD_CONTRL_STATUS_RX
#define USBD_CONTRL_STATUS_RX()
Definition: usbd_core.h:39
usb_ep_struct::stall
uint8_t stall
Definition: usbd_core.h:105
USBD_DADDR
#define USBD_DADDR
Definition: usbd_regs.h:27
usbd_core_handle_struct::class_deinit
usbd_status_enum(* class_deinit)(void *pudev, uint8_t config_index)
Definition: usbd_core.h:152
usb_ep_struct::trs_count
uint32_t trs_count
Definition: usbd_core.h:111
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
NULL
#define NULL
Definition: usbd_std.h:20
USBD_CONFIGURED
Definition: usbd_core.h:76
usbd_in_transaction
uint8_t usbd_in_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data in stage processing
Definition: usbd_std.c:155
usbd_enum_error
void usbd_enum_error(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB enumeration error event
Definition: usbd_std.c:832
USBD_RX
Definition: usbd_core.h:66
USB_REQ_MASK
#define USB_REQ_MASK
Definition: usbd_std.h:37
usbd_out_transaction
uint8_t usbd_out_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data out stage processing
Definition: usbd_std.c:113
usb_device_req_struct::bRequest
uint8_t bRequest
Definition: usbd_core.h:118
usbd_core_handle_struct::class_req_handler
usbd_status_enum(* class_req_handler)(void *pudev, usb_device_req_struct *req)
Definition: usbd_core.h:153
g_device_address
uint8_t g_device_address
Definition: usbd_std.c:16
usbd_vendor_request
uint8_t usbd_vendor_request(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB vendor request
Definition: usbd_std.c:268
USB_FEATURE_ENDP_HALT
#define USB_FEATURE_ENDP_HALT
Definition: usbd_std.h:66
usbd_core_handle_struct::status
uint8_t status
Definition: usbd_core.h:129
USBD_STATUS_OUT_CLEAR
#define USBD_STATUS_OUT_CLEAR(ep_num)
Definition: usbd_regs.h:238
USB_STATUS_REMOTE_WAKEUP
#define USB_STATUS_REMOTE_WAKEUP
Definition: usbd_std.h:63
usb_device_req_struct::wValue
uint16_t wValue
Definition: usbd_core.h:119
USB_STATUS_SELF_POWERED
#define USB_STATUS_SELF_POWERED
Definition: usbd_std.h:64
usbd_core_handle_struct::config_desc
uint8_t * config_desc
Definition: usbd_core.h:147
usbd_setup_request_parse
void usbd_setup_request_parse(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
decode setup data packet
Definition: usbd_std.c:812
USBD_TX
Definition: usbd_core.h:67
EP0_OUT
#define EP0_OUT
Definition: usbd_regs.h:171
USB_REQ_RECIPIENT_MASK
#define USB_REQ_RECIPIENT_MASK
Definition: usbd_std.h:42
usbd_setup_transaction
uint8_t usbd_setup_transaction(usbd_core_handle_struct *pudev)
USB setup stage processing.
Definition: usbd_std.c:80
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_crc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_crc.h"
14
21 void crc_deinit(void)
22 {
23 CRC_DATA = (uint32_t)0xFFFFFFFFU;
24 CRC_FDATA = (uint32_t)0x00000000U;
25 CRC_CTL = (uint32_t)CRC_CTL_RST;
26 }
27
34 void crc_data_register_reset(void)
35 {
36 CRC_CTL |= (uint32_t)CRC_CTL_RST;
37 }
38
45 uint32_t crc_data_register_read(void)
46 {
47 uint32_t data;
48 data = CRC_DATA;
49 return (data);
50 }
51
58 uint8_t crc_free_data_register_read(void)
59 {
60 uint8_t fdata;
61 fdata = (uint8_t)CRC_FDATA;
62 return (fdata);
63 }
64
71 void crc_free_data_register_write(uint8_t free_data)
72 {
73 CRC_FDATA = (uint32_t)free_data;
74 }
75
82 uint32_t crc_single_data_calculate(uint32_t sdata)
83 {
84 CRC_DATA = sdata;
85 return (CRC_DATA);
86 }
87
95 uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
96 {
97 uint32_t index;
98 for(index = 0U; index < size; index++){
99 CRC_DATA = array[index];
100 }
101 return (CRC_DATA);
102 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f10x_crc.h:23
crc_data_register_reset
void crc_data_register_reset(void)
reset data register to the value of initializaiton data register
Definition: gd32f10x_crc.c:34
crc_data_register_read
uint32_t crc_data_register_read(void)
read the data register
Definition: gd32f10x_crc.c:45
crc_block_data_calculate
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
CRC calculate a 32-bit data array.
Definition: gd32f10x_crc.c:95
crc_free_data_register_write
void crc_free_data_register_write(uint8_t free_data)
write the free data register
Definition: gd32f10x_crc.c:71
gd32f10x_crc.h
definitions for the CRC
CRC_CTL
#define CRC_CTL
Definition: gd32f10x_crc.h:24
crc_free_data_register_read
uint8_t crc_free_data_register_read(void)
read the free data register
Definition: gd32f10x_crc.c:58
CRC_DATA
#define CRC_DATA
Definition: gd32f10x_crc.h:22
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f10x_crc.h:34
crc_single_data_calculate
uint32_t crc_single_data_calculate(uint32_t sdata)
CRC calculate a 32-bit data.
Definition: gd32f10x_crc.c:82
crc_deinit
void crc_deinit(void)
deinit CRC calculation unit
Definition: gd32f10x_crc.c:21
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_misc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_MISC_H
14 #define GD32F10X_MISC_H
15
16 #include "gd32f10x.h"
17
18 /* constants definitions */
19 /* set the RAM and FLASH base address */
20 #define NVIC_VECTTAB_RAM ((uint32_t)0x20000000)
21 #define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000)
23 /* set the NVIC vector table offset mask */
24 #define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)
25
26 /* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
27 #define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
28
29 /* priority group - define the pre-emption priority and the subpriority */
30 #define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700)
31 #define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600)
32 #define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500)
33 #define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400)
34 #define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300)
36 /* choose the method to enter or exit the lowpower mode */
37 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)
38 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04)
39 #define SCB_SCR_SEVONPEND ((uint8_t)0x10)
41 #define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
42 #define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
43 #define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
44
45 /* choose the systick clock source */
46 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU)
47 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
49 /* function declarations */
50 /* set the priority group */
51 void nvic_priority_group_set(uint32_t nvic_prigroup);
52
53 /* enable NVIC request */
54 void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
55 /* disable NVIC request */
56 void nvic_irq_disable(uint8_t nvic_irq);
57
58 /* set the NVIC vector table base address */
59 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
60
61 /* set the state of the low power mode */
62 void system_lowpower_set(uint8_t lowpower_mode);
63 /* reset the state of the low power mode */
64 void system_lowpower_reset(uint8_t lowpower_mode);
65
66 /* set the systick clock source */
67 void systick_clksource_set(uint32_t systick_clksource);
68
69 #endif /* GD32F10X_MISC_H */
nvic_irq_disable
void nvic_irq_disable(uint8_t nvic_irq)
disable NVIC request
Definition: gd32f10x_misc.c:77
systick_clksource_set
void systick_clksource_set(uint32_t systick_clksource)
set the systick clock source
Definition: gd32f10x_misc.c:138
system_lowpower_reset
void system_lowpower_reset(uint8_t lowpower_mode)
reset the state of the low power mode
Definition: gd32f10x_misc.c:124
nvic_irq_enable
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority)
enable NVIC request
Definition: gd32f10x_misc.c:40
nvic_vector_table_set
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
set the NVIC vector table base address
Definition: gd32f10x_misc.c:92
nvic_priority_group_set
void nvic_priority_group_set(uint32_t nvic_prigroup)
set the priority group
Definition: gd32f10x_misc.c:26
system_lowpower_set
void system_lowpower_set(uint8_t lowpower_mode)
set the state of the low power mode
Definition: gd32f10x_misc.c:108
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_rtc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_rtc.h"
14
24 void rtc_interrupt_enable(uint32_t interrupt)
25 {
26 RTC_INTEN |= interrupt;
27 }
28
38 void rtc_interrupt_disable(uint32_t interrupt)
39 {
40 RTC_INTEN &= ~interrupt;
41 }
42
49 void rtc_configuration_mode_enter(void)
50 {
51 RTC_CTL |= RTC_CTL_CMF;
52 }
53
60 void rtc_configuration_mode_exit(void)
61 {
62 RTC_CTL &= ~RTC_CTL_CMF;
63 }
64
71 void rtc_lwoff_wait(void)
72 {
73 /* loop until LWOFF flag is set */
74 while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){
75 }
76 }
77
84 void rtc_register_sync_wait(void)
85 {
86 /* clear RSYNF flag */
87 RTC_CTL &= ~RTC_CTL_RSYNF;
88 /* loop until RSYNF flag is set */
89 while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){
90 }
91 }
92
99 uint32_t rtc_counter_get(void)
100 {
101 uint32_t temp = 0x0U;
102 temp = RTC_CNTL;
103 temp |= (RTC_CNTH << 16);
104 return temp;
105 }
106
113 void rtc_counter_set(uint32_t cnt)
114 {
115 rtc_configuration_mode_enter();
116 /* set the RTC counter high bits */
117 RTC_CNTH = cnt >> 16;
118 /* set the RTC counter low bits */
119 RTC_CNTL = (cnt & RTC_LOW_VALUE);
120 rtc_configuration_mode_exit();
121 }
122
129 void rtc_prescaler_set(uint32_t psc)
130 {
131 rtc_configuration_mode_enter();
132 /* set the RTC prescaler high bits */
133 RTC_PSCH = (psc & RTC_HIGH_VALUE) >> 16;
134 /* set the RTC prescaler low bits */
135 RTC_PSCL = (psc & RTC_LOW_VALUE);
136 rtc_configuration_mode_exit();
137 }
138
145 void rtc_alarm_config(uint32_t alarm)
146 {
147 rtc_configuration_mode_enter();
148 /* set the alarm high bits */
149 RTC_ALRMH = alarm >> 16;
150 /* set the alarm low bits */
151 RTC_ALRML = (alarm & RTC_LOW_VALUE);
152 rtc_configuration_mode_exit();
153 }
154
161 uint32_t rtc_divider_get(void)
162 {
163 uint32_t temp = 0x00U;
164 temp = (RTC_DIVH & RTC_DIVH_DIV) << 16;
165 temp |= RTC_DIVL;
166 return temp;
167 }
168
180 FlagStatus rtc_flag_get(uint32_t flag)
181 {
182 if(RESET != (RTC_CTL & flag)){
183 return SET;
184 }else{
185 return RESET;
186 }
187 }
188
199 void rtc_flag_clear(uint32_t flag)
200 {
201 /* clear RTC flag */
202 RTC_CTL &= ~flag;
203 }
RTC_HIGH_VALUE
#define RTC_HIGH_VALUE
Definition: gd32f10x_rtc.h:57
gd32f10x_rtc.h
definitions for the RTC
RTC_CNTL
#define RTC_CNTL
Definition: gd32f10x_rtc.h:29
RTC_PSCL
#define RTC_PSCL
Definition: gd32f10x_rtc.h:25
RTC_INTEN
#define RTC_INTEN
Definition: gd32f10x_rtc.h:22
rtc_interrupt_enable
void rtc_interrupt_enable(uint32_t interrupt)
enable RTC interrupt
Definition: gd32f10x_rtc.c:24
rtc_prescaler_set
void rtc_prescaler_set(uint32_t psc)
set RTC prescaler value
Definition: gd32f10x_rtc.c:129
RTC_DIVL
#define RTC_DIVL
Definition: gd32f10x_rtc.h:27
RTC_PSCH
#define RTC_PSCH
Definition: gd32f10x_rtc.h:24
rtc_counter_get
uint32_t rtc_counter_get(void)
get RTC counter value
Definition: gd32f10x_rtc.c:99
rtc_register_sync_wait
void rtc_register_sync_wait(void)
wait RTC registers synchronized flag set
Definition: gd32f10x_rtc.c:84
rtc_configuration_mode_enter
void rtc_configuration_mode_enter(void)
enter RTC configuration mode
Definition: gd32f10x_rtc.c:49
RTC_DIVH_DIV
#define RTC_DIVH_DIV
Definition: gd32f10x_rtc.h:49
RTC_CTL_CMF
#define RTC_CTL_CMF
Definition: gd32f10x_rtc.h:44
RTC_CTL
#define RTC_CTL
Definition: gd32f10x_rtc.h:23
rtc_lwoff_wait
void rtc_lwoff_wait(void)
wait RTC last write operation finished flag set
Definition: gd32f10x_rtc.c:71
rtc_flag_clear
void rtc_flag_clear(uint32_t flag)
clear RTC flag status
Definition: gd32f10x_rtc.c:199
rtc_counter_set
void rtc_counter_set(uint32_t cnt)
set RTC counter value
Definition: gd32f10x_rtc.c:113
rtc_flag_get
FlagStatus rtc_flag_get(uint32_t flag)
get RTC flag status
Definition: gd32f10x_rtc.c:180
rtc_divider_get
uint32_t rtc_divider_get(void)
get RTC divider value
Definition: gd32f10x_rtc.c:161
RTC_LOW_VALUE
#define RTC_LOW_VALUE
Definition: gd32f10x_rtc.h:58
rtc_configuration_mode_exit
void rtc_configuration_mode_exit(void)
exit RTC configuration mode
Definition: gd32f10x_rtc.c:60
RTC_DIVH
#define RTC_DIVH
Definition: gd32f10x_rtc.h:26
RTC_CTL_RSYNF
#define RTC_CTL_RSYNF
Definition: gd32f10x_rtc.h:43
rtc_interrupt_disable
void rtc_interrupt_disable(uint32_t interrupt)
disable RTC interrupt
Definition: gd32f10x_rtc.c:38
rtc_alarm_config
void rtc_alarm_config(uint32_t alarm)
set RTC alarm value
Definition: gd32f10x_rtc.c:145
RTC_CTL_LWOFF
#define RTC_CTL_LWOFF
Definition: gd32f10x_rtc.h:45
RTC_ALRML
#define RTC_ALRML
Definition: gd32f10x_rtc.h:31
RTC_CNTH
#define RTC_CNTH
Definition: gd32f10x_rtc.h:28
RTC_ALRMH
#define RTC_ALRMH
Definition: gd32f10x_rtc.h:30
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_fmc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_FMC_H
14 #define GD32F10X_FMC_H
15
16 #include "gd32f10x.h"
17
18 /* FMC and option byte definition */
19 #define FMC FMC_BASE
20 #define OB OB_BASE
22 /* registers definitions */
23 #define FMC_WS REG32((FMC) + 0x00U)
24 #define FMC_KEY0 REG32((FMC) + 0x04U)
25 #define FMC_OBKEY REG32((FMC) + 0x08U)
26 #define FMC_STAT0 REG32((FMC) + 0x0CU)
27 #define FMC_CTL0 REG32((FMC) + 0x10U)
28 #define FMC_ADDR0 REG32((FMC) + 0x14U)
29 #define FMC_OBSTAT REG32((FMC) + 0x1CU)
30 #define FMC_WP REG32((FMC) + 0x20U)
31 #define FMC_KEY1 REG32((FMC) + 0x44U)
32 #define FMC_STAT1 REG32((FMC) + 0x4CU)
33 #define FMC_CTL1 REG32((FMC) + 0x50U)
34 #define FMC_ADDR1 REG32((FMC) + 0x54U)
35 #define FMC_WSEN REG32((FMC) + 0xFCU)
36 #define FMC_PID REG32((FMC) + 0x100U)
38 #define OB_SPC REG16((OB) + 0x00U)
39 #define OB_USER REG16((OB) + 0x02U)
40 #define OB_WP0 REG16((OB) + 0x08U)
41 #define OB_WP1 REG16((OB) + 0x0AU)
42 #define OB_WP2 REG16((OB) + 0x0CU)
43 #define OB_WP3 REG16((OB) + 0x0EU)
45 /* bits definitions */
46 /* FMC_WS */
47 #define FMC_WS_WSCNT BITS(0,2)
49 /* FMC_KEY0 */
50 #define FMC_KEY0_KEY BITS(0,31)
52 /* FMC_OBKEY */
53 #define FMC_OBKEY_OBKEY BITS(0,31)
55 /* FMC_STAT0 */
56 #define FMC_STAT0_BUSY BIT(0)
57 #define FMC_STAT0_PGERR BIT(2)
58 #define FMC_STAT0_WPERR BIT(4)
59 #define FMC_STAT0_ENDF BIT(5)
61 /* FMC_CTL0 */
62 #define FMC_CTL0_PG BIT(0)
63 #define FMC_CTL0_PER BIT(1)
64 #define FMC_CTL0_MER BIT(2)
65 #define FMC_CTL0_OBPG BIT(4)
66 #define FMC_CTL0_OBER BIT(5)
67 #define FMC_CTL0_START BIT(6)
68 #define FMC_CTL0_LK BIT(7)
69 #define FMC_CTL0_OBWEN BIT(9)
70 #define FMC_CTL0_ERRIE BIT(10)
71 #define FMC_CTL0_ENDIE BIT(12)
73 /* FMC_ADDR0 */
74 #define FMC_ADDR0_ADDR BITS(0,31)
76 /* FMC_OBSTAT */
77 #define FMC_OBSTAT_OBERR BIT(0)
78 #define FMC_OBSTAT_SPC BIT(1)
79 #define FMC_OBSTAT_USER BITS(2,9)
80 #define FMC_OBSTAT_DATA BITS(10,25)
82 /* FMC_WP */
83 #define FMC_WP_WP BITS(0,31)
85 /* FMC_KEY1 */
86 #define FMC_KEY1_KEY BITS(0,31)
88 /* FMC_STAT1 */
89 #define FMC_STAT1_BUSY BIT(0)
90 #define FMC_STAT1_PGERR BIT(2)
91 #define FMC_STAT1_WPERR BIT(4)
92 #define FMC_STAT1_ENDF BIT(5)
94 /* FMC_CTL1 */
95 #define FMC_CTL1_PG BIT(0)
96 #define FMC_CTL1_PER BIT(1)
97 #define FMC_CTL1_MER BIT(2)
98 #define FMC_CTL1_START BIT(6)
99 #define FMC_CTL1_LK BIT(7)
100 #define FMC_CTL1_ERRIE BIT(10)
101 #define FMC_CTL1_ENDIE BIT(12)
103 /* FMC_ADDR1 */
104 #define FMC_ADDR1_ADDR BITS(0,31)
106 /* FMC_WSEN */
107 #define FMC_WSEN_WSEN BIT(0)
109 /* FMC_PID */
110 #define FMC_PID_PID BITS(0,31)
112 /* constants definitions */
113 /* define the FMC bit position and its register index offset */
114 #define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
115 #define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6)))
116 #define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
117 #define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
118 #define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12)))
119 #define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
120 #define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
121 #define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
122
123 /* configuration register */
124 #define FMC_STAT0_REG_OFFSET 0x0CU
125 #define FMC_CTL0_REG_OFFSET 0x10U
126 #define FMC_STAT1_REG_OFFSET 0x4CU
127 #define FMC_CTL1_REG_OFFSET 0x50U
128 #define FMC_OBSTAT_REG_OFFSET 0x1CU
130 /* fmc state */
131 typedef enum
132 {
133 FMC_READY,
134 FMC_BUSY,
135 FMC_PGERR,
136 FMC_WPERR,
137 FMC_TOERR,
138 }fmc_state_enum;
139
140 /* FMC interrupt enable */
141 typedef enum
142 {
143 FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U),
144 FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U),
145 FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U),
146 FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U),
147 }fmc_int_enum;
148
149 /* FMC flags */
150 typedef enum
151 {
152 FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U),
153 FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U),
154 FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U),
155 FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U),
156 FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U),
157 FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U),
158 FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U),
159 FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U),
160 FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U),
161 }fmc_flag_enum;
162
163 /* FMC interrupt flags */
164 typedef enum
165 {
166 FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U),
167 FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U),
168 FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U),
169 FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U),
170 FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U),
171 FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U),
172 }fmc_interrupt_flag_enum;
173
174 /* unlock key */
175 #define UNLOCK_KEY0 ((uint32_t)0x45670123U)
176 #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU)
178 /* FMC wait state counter */
179 #define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval)))
180 #define WS_WSCNT_0 WS_WSCNT(0)
181 #define WS_WSCNT_1 WS_WSCNT(1)
182 #define WS_WSCNT_2 WS_WSCNT(2)
184 /* option bytes software/hardware free watch dog timer */
185 #define OB_FWDGT_SW ((uint8_t)0x01U)
186 #define OB_FWDGT_HW ((uint8_t)0x00U)
188 /* option bytes reset or not entering deep sleep mode */
189 #define OB_DEEPSLEEP_NRST ((uint8_t)0x02U)
190 #define OB_DEEPSLEEP_RST ((uint8_t)0x00U)
192 /* option bytes reset or not entering standby mode */
193 #define OB_STDBY_NRST ((uint8_t)0x04U)
194 #define OB_STDBY_RST ((uint8_t)0x00U)
196 /* option bytes boot bank value */
197 #define OB_BOOT_B0 ((uint8_t)0x08U)
198 #define OB_BOOT_B1 ((uint8_t)0x00U)
200 #define OB_USER_MASK ((uint8_t)0xF0U)
202 /* read protect configure */
203 #define FMC_NSPC ((uint8_t)0xA5U)
204 #define FMC_USPC ((uint8_t)0xBBU)
206 /* OB_SPC */
207 #define OB_SPC_SPC ((uint32_t)0x000000FFU)
208 #define OB_SPC_SPC_N ((uint32_t)0x0000FF00U)
210 /* OB_USER */
211 #define OB_USER_USER ((uint32_t)0x00FF0000U)
212 #define OB_USER_USER_N ((uint32_t)0xFF000000U)
214 /* OB_WP0 */
215 #define OB_WP0_WP0 ((uint32_t)0x000000FFU)
217 /* OB_WP1 */
218 #define OB_WP1_WP1 ((uint32_t)0x0000FF00U)
220 /* OB_WP2 */
221 #define OB_WP2_WP2 ((uint32_t)0x00FF0000U)
223 /* OB_WP3 */
224 #define OB_WP3_WP3 ((uint32_t)0xFF000000U)
226 /* option bytes write protection */
227 #define OB_WP_0 ((uint32_t)0x00000001U)
228 #define OB_WP_1 ((uint32_t)0x00000002U)
229 #define OB_WP_2 ((uint32_t)0x00000004U)
230 #define OB_WP_3 ((uint32_t)0x00000008U)
231 #define OB_WP_4 ((uint32_t)0x00000010U)
232 #define OB_WP_5 ((uint32_t)0x00000020U)
233 #define OB_WP_6 ((uint32_t)0x00000040U)
234 #define OB_WP_7 ((uint32_t)0x00000080U)
235 #define OB_WP_8 ((uint32_t)0x00000100U)
236 #define OB_WP_9 ((uint32_t)0x00000200U)
237 #define OB_WP_10 ((uint32_t)0x00000400U)
238 #define OB_WP_11 ((uint32_t)0x00000800U)
239 #define OB_WP_12 ((uint32_t)0x00001000U)
240 #define OB_WP_13 ((uint32_t)0x00002000U)
241 #define OB_WP_14 ((uint32_t)0x00004000U)
242 #define OB_WP_15 ((uint32_t)0x00008000U)
243 #define OB_WP_16 ((uint32_t)0x00010000U)
244 #define OB_WP_17 ((uint32_t)0x00020000U)
245 #define OB_WP_18 ((uint32_t)0x00040000U)
246 #define OB_WP_19 ((uint32_t)0x00080000U)
247 #define OB_WP_20 ((uint32_t)0x00100000U)
248 #define OB_WP_21 ((uint32_t)0x00200000U)
249 #define OB_WP_22 ((uint32_t)0x00400000U)
250 #define OB_WP_23 ((uint32_t)0x00800000U)
251 #define OB_WP_24 ((uint32_t)0x01000000U)
252 #define OB_WP_25 ((uint32_t)0x02000000U)
253 #define OB_WP_26 ((uint32_t)0x04000000U)
254 #define OB_WP_27 ((uint32_t)0x08000000U)
255 #define OB_WP_28 ((uint32_t)0x10000000U)
256 #define OB_WP_29 ((uint32_t)0x20000000U)
257 #define OB_WP_30 ((uint32_t)0x40000000U)
258 #define OB_WP_31 ((uint32_t)0x80000000U)
259 #define OB_WP_ALL ((uint32_t)0xFFFFFFFFU)
261 /* FMC timeout */
262 #define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U)
264 /* FMC BANK address */
265 #define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU)
266 #define FMC_BANK0_SIZE ((uint32_t)0x00000200U)
267 #define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U)
269 /* function declarations */
270 /* FMC main memory programming functions */
271 /* set the FMC wait state counter */
272 void fmc_wscnt_set(uint32_t wscnt);
273 /* unlock the main FMC operation */
274 void fmc_unlock(void);
275 /* unlock the FMC bank0 operation */
276 void fmc_bank0_unlock(void);
277 /* unlock the FMC bank1 operation */
278 void fmc_bank1_unlock(void);
279 /* lock the main FMC operation */
280 void fmc_lock(void);
281 /* lock the bank0 FMC operation */
282 void fmc_bank0_lock(void);
283 /* lock the bank1 FMC operation */
284 void fmc_bank1_lock(void);
285 /* FMC erase page */
286 fmc_state_enum fmc_page_erase(uint32_t page_address);
287 /* FMC erase whole chip */
288 fmc_state_enum fmc_mass_erase(void);
289 /* FMC erase whole bank0 */
290 fmc_state_enum fmc_bank0_erase(void);
291 /* FMC erase whole bank1 */
292 fmc_state_enum fmc_bank1_erase(void);
293 /* FMC program a word at the corresponding address */
294 fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
295 /* FMC program a half word at the corresponding address */
296 fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
297
298 /* FMC option bytes programming functions */
299 /* unlock the option byte operation */
300 void ob_unlock(void);
301 /* lock the option byte operation */
302 void ob_lock(void);
303 /* erase the option byte */
304 fmc_state_enum ob_erase(void);
305 /* enable write protect */
306 fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
307 /* configure the option byte security protection */
308 fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
309 /* write the FMC option byte */
310 fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
311 /* program option bytes data */
312 fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
313 /* get the FMC option byte user */
314 uint8_t ob_user_get(void);
315 /* get OB_DATA in register FMC_OBSTAT */
316 uint16_t ob_data_get(void);
317 /* get the FMC option byte write protection */
318 uint32_t ob_write_protection_get(void);
319 /* get option byte security protection code value */
320 FlagStatus ob_spc_get(void);
321
322 /* FMC interrupts and flags management functions */
323 /* enable FMC interrupt */
324 void fmc_interrupt_enable(uint32_t interrupt);
325 /* disable FMC interrupt */
326 void fmc_interrupt_disable(uint32_t interrupt);
327 /* check flag is set or not */
328 FlagStatus fmc_flag_get(uint32_t flag);
329 /* clear the FMC flag */
330 void fmc_flag_clear(uint32_t flag);
331 /* get FMC interrupt flag state */
332 FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
333 /* clear FMC interrupt flag state */
334 void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
335 /* return the FMC bank0 state */
336 fmc_state_enum fmc_bank0_state_get(void);
337 /* return the FMC bank1 state */
338 fmc_state_enum fmc_bank1_state_get(void);
339 /* check FMC bank0 ready or not */
340 fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout);
341 /* check FMC bank1 ready or not */
342 fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout);
343
344 #endif /* GD32F10X_FMC_H */
ob_user_write
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot)
program the FMC user option byte
Definition: gd32f10x_fmc.c:599
FMC_INT_BANK0_END
Definition: gd32f10x_fmc.h:143
FMC_STAT1_REG_OFFSET
#define FMC_STAT1_REG_OFFSET
Definition: gd32f10x_fmc.h:126
ob_data_program
fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
program option bytes data
Definition: gd32f10x_fmc.c:633
FMC_INT_BANK0_ERR
Definition: gd32f10x_fmc.h:144
FMC_FLAG_BANK1_WPERR
Definition: gd32f10x_fmc.h:159
ob_data_get
uint16_t ob_data_get(void)
get OB_DATA in register FMC_OBSTAT
Definition: gd32f10x_fmc.c:672
ob_security_protection_config
fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
configure security protection
Definition: gd32f10x_fmc.c:544
fmc_int_enum
fmc_int_enum
Definition: gd32f10x_fmc.h:141
ob_user_get
uint8_t ob_user_get(void)
get the FMC user option byte
Definition: gd32f10x_fmc.c:660
FMC_FLAG_BANK0_PGERR
Definition: gd32f10x_fmc.h:153
ob_unlock
void ob_unlock(void)
unlock the option byte operation
Definition: gd32f10x_fmc.c:402
FMC_BUSY
Definition: gd32f10x_fmc.h:134
FMC_WPERR
Definition: gd32f10x_fmc.h:136
fmc_interrupt_disable
void fmc_interrupt_disable(uint32_t interrupt)
disable FMC interrupt
Definition: gd32f10x_fmc.c:732
FMC_INT_BANK1_END
Definition: gd32f10x_fmc.h:145
fmc_bank0_unlock
void fmc_bank0_unlock(void)
unlock the FMC bank0 operation this function can be used for all GD32F10x devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function.
Definition: gd32f10x_fmc.c:65
fmc_mass_erase
fmc_state_enum fmc_mass_erase(void)
erase whole chip
Definition: gd32f10x_fmc.c:198
fmc_bank0_lock
void fmc_bank0_lock(void)
lock the FMC bank0 operation this function can be used for all GD32F10X devices. for GD32F10x_MD and ...
Definition: gd32f10x_fmc.c:116
fmc_state_enum
fmc_state_enum
Definition: gd32f10x_fmc.h:131
fmc_page_erase
fmc_state_enum fmc_page_erase(uint32_t page_address)
erase page
Definition: gd32f10x_fmc.c:141
FMC_OBSTAT_REG_OFFSET
#define FMC_OBSTAT_REG_OFFSET
Definition: gd32f10x_fmc.h:128
FMC_INT_FLAG_BANK0_END
Definition: gd32f10x_fmc.h:168
ob_spc_get
FlagStatus ob_spc_get(void)
get the FMC option byte security protection
Definition: gd32f10x_fmc.c:695
FMC_INT_FLAG_BANK1_PGERR
Definition: gd32f10x_fmc.h:169
FMC_TOERR
Definition: gd32f10x_fmc.h:137
ob_write_protection_enable
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
enable write protection
Definition: gd32f10x_fmc.c:486
fmc_flag_clear
void fmc_flag_clear(uint32_t flag)
clear the FMC flag
Definition: gd32f10x_fmc.c:775
FMC_INT_FLAG_BANK1_WPERR
Definition: gd32f10x_fmc.h:170
fmc_bank0_ready_wait
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
check whether FMC bank0 is ready or not
Definition: gd32f10x_fmc.c:892
FMC_INT_FLAG_BANK0_PGERR
Definition: gd32f10x_fmc.h:166
fmc_bank1_ready_wait
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
check whether FMC bank1 is ready or not
Definition: gd32f10x_fmc.c:916
fmc_flag_enum
fmc_flag_enum
Definition: gd32f10x_fmc.h:150
FMC_FLAG_BANK1_PGERR
Definition: gd32f10x_fmc.h:158
fmc_bank1_lock
void fmc_bank1_lock(void)
lock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash mor...
Definition: gd32f10x_fmc.c:129
FMC_FLAG_BANK1_END
Definition: gd32f10x_fmc.h:160
ob_erase
fmc_state_enum ob_erase(void)
erase the FMC option byte unlock the FMC_CTL0 and option byte before calling this function ...
Definition: gd32f10x_fmc.c:434
FMC_CTL0_REG_OFFSET
#define FMC_CTL0_REG_OFFSET
Definition: gd32f10x_fmc.h:125
FMC_FLAG_BANK0_END
Definition: gd32f10x_fmc.h:155
fmc_flag_get
FlagStatus fmc_flag_get(uint32_t flag)
check flag is set or not
Definition: gd32f10x_fmc.c:753
fmc_word_program
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
program a word at the corresponding address
Definition: gd32f10x_fmc.c:297
FMC_REGIDX_BIT
#define FMC_REGIDX_BIT(regidx, bitpos)
Definition: gd32f10x_fmc.h:114
fmc_interrupt_flag_enum
fmc_interrupt_flag_enum
Definition: gd32f10x_fmc.h:164
fmc_bank0_state_get
fmc_state_enum fmc_bank0_state_get(void)
get the FMC bank0 state
Definition: gd32f10x_fmc.c:841
FMC_INT_BANK1_ERR
Definition: gd32f10x_fmc.h:146
fmc_wscnt_set
void fmc_wscnt_set(uint32_t wscnt)
set the wait state counter value
Definition: gd32f10x_fmc.c:24
FMC_CTL1_REG_OFFSET
#define FMC_CTL1_REG_OFFSET
Definition: gd32f10x_fmc.h:127
fmc_interrupt_enable
void fmc_interrupt_enable(uint32_t interrupt)
enable FMC interrupt
Definition: gd32f10x_fmc.c:717
fmc_bank1_erase
fmc_state_enum fmc_bank1_erase(void)
erase bank1
Definition: gd32f10x_fmc.c:271
FMC_STAT0_REG_OFFSET
#define FMC_STAT0_REG_OFFSET
Definition: gd32f10x_fmc.h:124
FMC_REGIDX_BITS
#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1)
Definition: gd32f10x_fmc.h:117
FMC_READY
Definition: gd32f10x_fmc.h:133
FMC_FLAG_BANK0_WPERR
Definition: gd32f10x_fmc.h:154
fmc_bank0_erase
fmc_state_enum fmc_bank0_erase(void)
erase bank0
Definition: gd32f10x_fmc.c:246
FMC_FLAG_BANK0_BUSY
Definition: gd32f10x_fmc.h:152
fmc_bank1_unlock
void fmc_bank1_unlock(void)
unlock the FMC bank1 operation this function can be used for GD32F10x_XD and GD32F10x_CL with flash m...
Definition: gd32f10x_fmc.c:81
fmc_halfword_program
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
program a half word at the corresponding address
Definition: gd32f10x_fmc.c:350
fmc_lock
void fmc_lock(void)
lock the main FMC operation
Definition: gd32f10x_fmc.c:96
FMC_FLAG_BANK1_BUSY
Definition: gd32f10x_fmc.h:157
FMC_FLAG_OBERR
Definition: gd32f10x_fmc.h:156
FMC_INT_FLAG_BANK1_END
Definition: gd32f10x_fmc.h:171
fmc_interrupt_flag_get
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
get FMC interrupt flag state
Definition: gd32f10x_fmc.c:793
fmc_interrupt_flag_clear
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag)
clear FMC interrupt flag state
Definition: gd32f10x_fmc.c:830
ob_write_protection_get
uint32_t ob_write_protection_get(void)
get the FMC option byte write protection
Definition: gd32f10x_fmc.c:683
ob_lock
void ob_lock(void)
lock the option byte operation
Definition: gd32f10x_fmc.c:421
fmc_unlock
void fmc_unlock(void)
unlock the main FMC operation
Definition: gd32f10x_fmc.c:40
FMC_INT_FLAG_BANK0_WPERR
Definition: gd32f10x_fmc.h:167
fmc_bank1_state_get
fmc_state_enum fmc_bank1_state_get(void)
get the FMC bank1 state
Definition: gd32f10x_fmc.c:866
FMC_PGERR
Definition: gd32f10x_fmc.h:135
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usb_core.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
usb_core.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usb_core.h"
14
15 static void usb_commonint_enable (usb_core_handle_struct *pudev);
16 static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev);
17
24 static void usb_commonint_enable (usb_core_handle_struct *pudev)
25 {
26 #ifndef USE_OTG_MODE
27
28 /* clear any pending USB interrupts */
29 USB_GOTGINTF = 0xFFFFFFFFU;
30
31 #endif /* USE_OTG_MODE */
32
33 USB_GINTF = 0xBFFFFFFF;
34
35 /* enable the usb wakeup and suspend interrupts */
36 USB_GINTEN = GINTEN_WKUPIE | GINTEN_SPIE;
37
38 #ifdef USE_OTG_MODE
39
40 /* enable the OTG interrupts, session interrrupts and connector ID pin interrupt */
41 USB_GINTEN |= GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE;
42
43 #endif /* USE_OTG_MODE */
44 }
45
52 static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev)
53 {
54 uint32_t count = 0U;
55
56 /* enable core soft reset */
57 USB_GRSTCTL |= GRSTCTL_CSRST;
58
59 /* wait for the core to be soft reset */
60 do {
61 if (++count > 200000U) {
62 break;
63 }
64 } while (1U == (USB_GRSTCTL & GRSTCTL_CSRST));
65
66 /* wait for addtional 3 PHY clocks */
67 if (NULL != pudev->udelay) {
68 pudev->udelay(3U);
69 }
70
71 return USB_OK;
72 }
73
82 usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len)
83 {
84 uint32_t count32b = 0U, i = 0U;
85 __IO uint32_t *fifo = USB_FIFO(chep_num);
86
87 count32b = (len + 3U) / 4U;
88
89 for (i = 0U; i < count32b; i++) {
90 *fifo = *((__packed uint32_t *)src);
91
92 src += 4U;
93 }
94
95 return USB_OK;
96 }
97
105 void *usb_fifo_read (uint8_t *dest, uint16_t len)
106 {
107 uint32_t i = 0U;
108 uint32_t count32b = (len + 3U) / 4U;
109
110 __IO uint32_t *fifo = USB_FIFO(0U);
111
112 for (i = 0U; i < count32b; i++) {
113 *(__packed uint32_t *)dest = *fifo;
114
115 dest += 4U;
116 }
117
118 return ((void *)dest);
119 }
120
128 usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
129 {
130 /* at startup the core is in FS mode */
131 pudev->cfg.core_speed = USB_CORE_SPEED_FULL;
132 pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE;
133
134 /* initialize the core parameters */
135 if (USB_FS_CORE_ID == core_id) {
136
137 pudev->cfg.core_id = USB_FS_CORE_ID;
138
139 /* set the host channel numbers */
140 pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT;
141
142 /* set the device endpoint numbers */
143 pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT;
144
145 /* fifo size is in terms of DWORD */
146 pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN;
147
148 /* OTG_FS core use embedded physical layer */
149 pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY;
150
151 #ifdef USBFS_SOF_OUTPUT_ENABLED
152 pudev->cfg.sof_output = 1U;
153 #endif /* USBFS_SOF_OUTPUT_ENABLED */
154
155 #ifdef USBFS_LOW_PWR_MGMT_SUPPORT
156 pudev->cfg.low_power = 1U;
157 #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */
158 }
159
160 return USB_OK;
161 }
162
170 usb_status_enum usb_core_init (usb_core_handle_struct *pudev)
171 {
172 /* soft reset the core */
173 usb_core_reset(pudev);
174
175 /* active the transceiver and enable vbus sensing */
176 USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN;
177
178 /* set Tx FIFO empty level to half empty mode */
179 USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF;
180
181 #ifndef VBUS_SENSING_ENABLED
182 USB_GCCFG |= GCCFG_VBUSIG;
183 #endif /* VBUS_SENSING_ENABLED */
184
185 if(pudev->cfg.sof_output){
186 USB_GCCFG |= GCCFG_SOFOEN;
187 }
188
189 if (NULL != pudev->mdelay) {
190 pudev->mdelay(20U);
191 }
192
193
194 #ifdef USE_OTG_MODE
195 /* enable OTG features */
196 USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP;
197 USB_OTG_EnableCommonInt(pudev);
198
199 #endif /* USE_OTG_MODE */
200
201 return USB_OK;
202 }
203
211 usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num)
212 {
213 uint32_t count = 0U;
214
215 USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF;
216
217 /* wait for Tx FIFO flush bit is set */
218 do {
219 if (++count > 200000U) {
220 break;
221 }
222 } while (USB_GRSTCTL & GRSTCTL_TXFF);
223
224 /* wait for 3 PHY clocks */
225 if (NULL != pudev->udelay) {
226 pudev->udelay(3U);
227 }
228
229 return USB_OK;
230 }
231
238 usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev)
239 {
240 uint32_t count = 0U;
241
242 USB_GRSTCTL = GRSTCTL_RXFF;
243
244 /* wait for Rx FIFO flush bit is set */
245 do {
246 if (++count > 200000U) {
247 break;
248 }
249 } while (USB_GRSTCTL & GRSTCTL_RXFF);
250
251 /* wait for 3 PHY clocks */
252 if (NULL != pudev->udelay) {
253 pudev->udelay(3U);
254 }
255
256 return USB_OK;
257 }
258
268 usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode)
269 {
270 if (HOST_MODE == mode) {
271 USB_GUSBCS &= ~GUSBCS_FDM;
272 USB_GUSBCS |= GUSBCS_FHM;
273 } else if (DEVICE_MODE == mode) {
274 USB_GUSBCS &= ~GUSBCS_FHM;
275 USB_GUSBCS |= GUSBCS_FDM;
276 } else {
277 /* no operation */
278 }
279
280 if (NULL != pudev->mdelay) {
281 pudev->mdelay(50U);
282 }
283
284 return USB_OK;
285 }
286
287 #ifdef USE_HOST_MODE
288
295 usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev)
296 {
297 uint32_t i = 0U;
298 __IO uint32_t nptxfifolen = 0U;
299 __IO uint32_t ptxfifolen = 0U;
300
301 #ifdef USE_OTG_MODE
302 __IO uint32_t otgctl = 0;
303 #endif /* USE_OTG_MODE */
304
305 /* restart the PHY clock */
306 USB_PWRCLKCTL = 0U;
307
308 /* initialize host configuration register */
309 if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) {
310 USB_FSLSCLOCK_INIT(HCTLR_30_60_MHZ);
311 } else {
312 USB_FSLSCLOCK_INIT(HCTLR_48_MHZ);
313 }
314
315 /* reset USB port */
316 usb_port_reset(pudev);
317
318 /* configure data FIFO sizes */
319 if (USB_FS_CORE_ID == pudev->cfg.core_id) {
320 /* set Rx FIFO size */
321 USB_GRFLEN = USBFS_RX_FIFO_SIZE;
322
323 /* set non-periodic Tx FIFO size and address */
324 nptxfifolen &= ~HNPTFLEN_HNPTXRSAR;
325 nptxfifolen |= USBFS_RX_FIFO_SIZE;
326 nptxfifolen &= ~HNPTFLEN_HNPTXFD;
327 nptxfifolen |= USBFS_HTX_NPFIFO_SIZE << 16;
328 USB_HNPTFLEN = nptxfifolen;
329
330 /* set periodic Tx FIFO size and address */
331 ptxfifolen &= ~HPTFLEN_HPTXFSAR;
332 ptxfifolen |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE;
333 ptxfifolen &= ~HPTFLEN_HPTXFD;
334 ptxfifolen |= USBFS_HTX_PFIFO_SIZE << 16;
335 USB_HPTFLEN = ptxfifolen;
336 }
337
338 #ifdef USE_OTG_MODE
339
340 /* clear Host Set HNP Enable bit in the USB OTG Control Register */
341 otgctl |= GOTGCS_HHNPEN;
342 USB_GOTGCS &= ~otgctl;
343 USB_GOTGCS |= 0;
344
345 #endif /* USE_OTG_MODE */
346
347 /* make sure the FIFOs are flushed */
348
349 /* flush all Tx FIFOs in device or host mode */
350 usb_txfifo_flush(pudev, 0x10U);
351
352 /* flush the entire Rx FIFO */
353 usb_rxfifo_flush(pudev);
354
355 /* clear all pending host channel interrupts */
356 USB_HACHINTEN &= ~HACHINTEN_CINTEN;
357
358 for (i = 0U; i < pudev->cfg.host_channel_num; i++) {
359 USB_HCHxINTEN(i) = 0U;
360 USB_HCHxINTF(i) = 0xFFFFFFFFU;
361 }
362
363 #ifndef USE_OTG_MODE
364 usb_vbus_drive(pudev, 1U);
365 #endif /* USE_OTG_MODE */
366
367 usb_hostint_enable(pudev);
368
369 return USB_OK;
370 }
371
379 void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state)
380 {
381 __IO uint32_t host_port = 0U;
382
383 /* enable or disable the external charge pump */
384 if ((void *)0 != pudev->host.vbus_drive) {
385 pudev->host.vbus_drive(pudev, state);
386 }
387
388 /* turn on the host port power. */
389 host_port = USB_PORT_READ();
390
391 if ((0U == (host_port & HPCS_PP)) && (1U == state)) {
392 host_port |= HPCS_PP;
393 } else if ((1U == (host_port & HPCS_PP)) && (0U == state)) {
394 host_port &= ~HPCS_PP;
395 } else {
396 /* no operation */
397 }
398
399 USB_HPCS = host_port;
400
401 if (NULL != pudev->mdelay) {
402 pudev->mdelay(200U);
403 }
404 }
405
412 usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev)
413 {
414 uint32_t gintf = 0U;
415
416 /* disable all interrupts */
417 USB_GINTEN = 0U;
418
419 /* clear any pending interrupts */
420 USB_GINTF = 0xFFFFFFFFU;
421
422 /* enable the common interrupts */
423 usb_commonint_enable(pudev);
424
425 gintf |= GINTF_RXFNEIF;
426
427 /* enable host_mode-related interrupts */
428 gintf |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF | GINTF_SOF | GINTF_ISOONCIF;
429
430 USB_GINTEN &= ~gintf;
431 USB_GINTEN |= gintf;
432
433 return USB_OK;
434 }
435
442 uint32_t usb_port_reset (usb_core_handle_struct *pudev)
443 {
444 __IO uint32_t hpcs;
445
446 hpcs = USB_PORT_READ();
447
448 hpcs |= HPCS_PRST;
449
450 USB_HPCS = hpcs;
451
452 if (NULL != pudev->mdelay) {
453 pudev->mdelay(100U);
454 }
455
456 hpcs &= ~HPCS_PRST;
457
458 USB_HPCS = hpcs;
459
460 if (NULL != pudev->mdelay) {
461 pudev->mdelay(20U);
462 }
463
464 return USB_OK;
465 }
466
474 usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num)
475 {
476 uint8_t is_low_speed = 0U;
477 __IO uint32_t chinten = 0U;
478 __IO uint32_t chctl = 0U;
479
480 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
481
482 /* clear old interrupt conditions for this host channel */
483 USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU;
484
485 /* enable channel interrupts required for this transfer */
486 switch (puhc->endp_type) {
487 case USB_EPTYPE_CTRL:
488 case USB_EPTYPE_BULK:
489 chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \
490 | HCHINTEN_DTERIE | HCHINTEN_NAKIE;
491
492 if (puhc->endp_in) {
493 chinten |= HCHINTEN_BBERIE;
494 } else {
495 chinten |= HCHINTEN_NYETIE;
496 }
497 break;
498
499 case USB_EPTYPE_INTR:
500 chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \
501 | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE;
502
503 if (puhc->endp_in) {
504 chinten |= HCHINTEN_BBERIE;
505 }
506 break;
507
508 case USB_EPTYPE_ISOC:
509 chinten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE;
510
511 if (puhc->endp_in) {
512 chinten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE;
513 }
514 break;
515
516 default:
517 break;
518 }
519
520 USB_HCHxINTEN((uint16_t)hc_num) = chinten;
521
522 /* enable the top level host channel interrupt */
523 USB_HACHINTEN |= 1U << hc_num;
524
525 /* make sure host channel interrupts are enabled */
526 USB_GINTEN |= GINTEN_HCIE;
527
528 /* program the hcctlr register */
529 chctl = 0U;
530
531 if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) {
532 is_low_speed = 1U;
533 }
534
535 chctl |= (uint32_t)puhc->dev_addr << 22U;
536 chctl |= (uint32_t)puhc->endp_type << 18U;
537 chctl |= (uint32_t)puhc->endp_id << 11U;
538 chctl |= (uint32_t)puhc->endp_in << 15U;
539 chctl |= (uint32_t)is_low_speed << 17U;
540 chctl |= puhc->endp_mps;
541
542 if (HCCHAR_INTR == puhc->endp_type) {
543 chctl |= HCHCTL_ODDFRM;
544 }
545
546 USB_HCHxCTL((uint16_t)hc_num) = chctl;
547
548 return USB_OK;
549 }
550
558 usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num)
559 {
560 uint16_t dword_len = 0U;
561 uint16_t packet_num = 0U;
562
563 __IO uint32_t chxlen = 0U;
564 __IO uint32_t chctl = 0U;
565
566 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
567
568 /* compute the expected number of packets associated to the transfer */
569 if (puhc->xfer_len > 0U) {
570 packet_num = ((uint16_t)puhc->xfer_len + puhc->endp_mps - 1U) / puhc->endp_mps;
571
572 if (packet_num > HC_MAX_PACKET_COUNT) {
573 packet_num = HC_MAX_PACKET_COUNT;
574 puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps);
575 }
576 } else {
577 packet_num = 1U;
578 }
579
580 if (puhc->endp_in) {
581 puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps);
582 }
583
584 /* initialize the host channel length register */
585 chxlen &= ~HCHLEN_TLEN;
586 chxlen |= puhc->xfer_len;
587 chxlen &= ~HCHLEN_PCNT;
588 chxlen |= (uint32_t)packet_num << 19;
589 chxlen &= ~HCHLEN_DPID;
590 chxlen |= (uint32_t)(puhc->DPID) << 29;
591 USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)chxlen;
592
593 /* set host channel enable */
594 chctl = USB_HCHxCTL((uint16_t)hc_num);
595
596 if (1 == USB_EVEN_FRAME()) {
597 chctl |= HCHCTL_ODDFRM;
598 } else {
599 chctl &= ~HCHCTL_ODDFRM;
600 }
601
602 chctl |= HCHCTL_CEN;
603 chctl &= ~HCHCTL_CDIS;
604 USB_HCHxCTL((uint16_t)hc_num) = chctl;
605
606 if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) {
607 dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U;
608
609 switch (puhc->endp_type) {
610 /* non-periodic transfer */
611 case USB_EPTYPE_CTRL:
612 case USB_EPTYPE_BULK:
613 /* check if there is enough space in fifo space */
614 if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) {
615 /* need to process data in non-periodic transfer fifo empty interrupt */
616 USB_GINTEN |= GINTEN_NPTXFEIE;
617 }
618 break;
619
620 /* periodic transfer */
621 case USB_EPTYPE_INTR:
622 case USB_EPTYPE_ISOC:
623 /* check if there is enough space in FIFO space */
624 if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) {
625 /* need to process data in periodic transfer fifo empty interrupt */
626 USB_GINTEN |= GINTEN_PTXFEIE;
627 }
628 break;
629
630 default:
631 break;
632 }
633
634 /* write packet into the Tx FIFO. */
635 usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len);
636 }
637
638 return USB_OK;
639 }
640
648 usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num)
649 {
650 uint8_t endp_type = 0U;
651 __IO uint32_t chctl = USB_HCHxCTL((uint16_t)hc_num);
652
653 chctl |= HCHCTL_CEN | HCHCTL_CDIS;
654
655 endp_type = (uint8_t)((chctl & HCHCTL_EPTYPE) >> 18U);
656
657 /* check for space in the request queue to issue the halt. */
658 if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) {
659 if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) {
660 chctl &= ~HCHCTL_CEN;
661 }
662 } else {
663 if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) {
664 chctl &= ~HCHCTL_CEN;
665 }
666 }
667
668 USB_HCHxCTL((uint16_t)hc_num) = chctl;
669
670 return USB_OK;
671 }
672
679 void usb_host_stop(usb_core_handle_struct *pudev)
680 {
681 uint32_t i;
682
683 /* disable all host channel interrupt */
684 USB_HACHINTEN = 0U;
685 USB_HACHINT = 0xFFFFFFFFU;
686
687 /* flush out any leftover queued requests */
688 for (i = 0U; i < pudev->cfg.host_channel_num; i++) {
689 USB_HCHxCTL(i) |= HCHCTL_CEN | HCHCTL_CDIS | HCHCTL_EPDIR;
690 }
691
692 /* flush the FIFO */
693 usb_rxfifo_flush(pudev);
694 usb_txfifo_flush(pudev, 0x10U);
695 }
696
697 #endif /* USE_HOST_MODE */
698
699
700 #ifdef USE_DEVICE_MODE
701
702 /* USB endpoint Tx FIFO size */
703 static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] =
704 {
705 (uint16_t)TX0_FIFO_FS_SIZE,
706 (uint16_t)TX1_FIFO_FS_SIZE,
707 (uint16_t)TX2_FIFO_FS_SIZE,
708 (uint16_t)TX3_FIFO_FS_SIZE
709 };
710
711 static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev);
712
719 usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev)
720 {
721 uint32_t i, ram_address = 0U;
722 __IO uint32_t devinep0intf = USB_DIEP0TFLEN;
723 __IO uint32_t devinepintf = 0U;
724
725 /* restart the Phy Clock (Maybe don't need to...) */
726 USB_PWRCLKCTL = 0U;
727
728 /* config periodic frmae interval to default */
729 USB_DCFG &= ~DCFG_EOPFT;
730 USB_DCFG |= FRAME_INTERVAL_80;
731
732 if (USB_FS_CORE_ID == pudev->cfg.core_id) {
733 /* set full speed PHY */
734 USB_DCFG &= ~DCFG_DS;
735 USB_DCFG |= USB_SPEED_INP_FULL;
736
737 /* set Rx FIFO size */
738 USB_GRFLEN &= ~GRFLEN_RXFD;
739 USB_GRFLEN |= (uint32_t)RX_FIFO_FS_SIZE;
740
741 /* set endpoint 0 Tx FIFO length and RAM address */
742 devinep0intf &= ~DIEP0TFLEN_IEP0TXFD;
743 devinep0intf |= (uint32_t)TX0_FIFO_FS_SIZE << 16;
744 devinep0intf &= ~DIEP0TFLEN_IEP0TXRSAR;
745 devinep0intf |= (uint32_t)RX_FIFO_FS_SIZE;
746
747 USB_DIEP0TFLEN = devinep0intf;
748
749 ram_address = (uint32_t)RX_FIFO_FS_SIZE;
750
751 /* set endpoint 1 to 3's Tx FIFO length and RAM address */
752 for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) {
753 ram_address += USBFS_TX_FIFO_SIZE[i - 1U];
754
755 devinepintf &= ~DIEPTFLEN_IEPTXFD;
756 devinepintf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U;
757 devinepintf &= ~DIEPTFLEN_IEPTXRSAR;
758 devinepintf |= ram_address;
759
760 USB_DIEPxTFLEN(i) = devinepintf;
761 }
762 }
763
764 /* make sure all FIFOs are flushed */
765
766 /* flush all Tx FIFOs */
767 usb_txfifo_flush(pudev, 0x10U);
768
769 /* flush entire Rx FIFO */
770 usb_rxfifo_flush(pudev);
771
772 /* clear all pending device interrupts */
773 USB_DIEPINTEN = 0U;
774 USB_DOEPINTEN = 0U;
775 USB_DAEPINT = 0xFFFFFFFFU;
776 USB_DAEPINTEN = 0U;
777
778 /* configure all IN/OUT endpoints */
779 for (i = 0U; i < pudev->cfg.dev_endp_num; i++) {
780 if (USB_DIEPxCTL(i) & DEPCTL_EPEN) {
781 USB_DIEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK;
782 } else {
783 USB_DIEPxCTL(i) = 0U;
784 }
785
786 if (USB_DOEPxCTL(i) & DEPCTL_EPEN) {
787 USB_DOEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK;
788 } else {
789 USB_DOEPxCTL(i) = 0U;
790 }
791
792 /* set IN/OUT endpoint transfer length to 0 */
793 USB_DIEPxLEN(i) = 0U;
794 USB_DOEPxLEN(i) = 0U;
795
796 /* clear all pending IN/OUT endpoints interrupts */
797 USB_DIEPxINTF(i) = 0xFFU;
798 USB_DOEPxINTF(i) = 0xFFU;
799 }
800
801 usb_devint_enable(pudev);
802
803 return USB_OK;
804 }
805
812 static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev)
813 {
814 uint32_t int_mask = 0U;
815
816 /* disable all interrupts */
817 USB_GINTEN = 0U;
818
819 /* clear any pending interrupts */
820 USB_GINTF = 0xBFFFFFFFU;
821
822 /* enable the common interrupts */
823 usb_commonint_enable(pudev);
824
825 int_mask = GINTEN_RXFNEIE;
826
827 /* enable device_mode-related interrupts */
828 int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \
829 | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE \
830 | GINTEN_ISOINCIE;
831
832 #ifdef VBUS_SENSING_ENABLED
833 int_mask |= GINTEN_SESIE | GINTEN_OTGIE;
834 #endif /* VBUS_SENSING_ENABLED */
835
836 USB_GINTEN &= ~int_mask;
837 USB_GINTEN |= int_mask;
838
839 return USB_OK;
840 }
841
848 void usb_ep0_startout(usb_core_handle_struct *pudev)
849 {
850 __IO uint32_t ep0len = 0U;
851
852 /* set OUT endpoint 0 receive length to 24 bytes */
853 ep0len &= ~DOEP0LEN_TLEN;
854 ep0len |= 8U * 3U;
855
856 /* set OUT endpoint 0 receive length to 1 packet */
857 ep0len &= ~DOEP0LEN_PCNT;
858 ep0len |= 1U << 19;
859
860 /* set SETUP packet count to 3 */
861 ep0len &= ~DOEP0LEN_STPCNT;
862 ep0len |= 3U << 29;
863
864 USB_DOEPxLEN(0U) = ep0len;
865 }
866
873 void usb_remotewakeup_active(usb_core_handle_struct *pudev)
874 {
875 __IO uint32_t power_clock;
876
877 if (pudev->dev.remote_wakeup) {
878 if (1U == (USB_DSTAT & DSTAT_SPST)) {
879 if (pudev->cfg.low_power) {
880 /* ungate USB core clock */
881 power_clock = USB_PWRCLKCTL;
882 power_clock &= ~PWRCLKCTL_SHCLK;
883 power_clock &= ~PWRCLKCTL_SUCLK;
884
885 USB_PWRCLKCTL = power_clock;
886 }
887
888 /* active remote wakeup signaling */
889 USB_DCTL |= DCTL_RWKUP;
890
891 if (pudev->mdelay != (void *)0) {
892 pudev->mdelay(5U);
893 }
894
895 USB_DCTL &= ~DCTL_RWKUP;
896 }
897 }
898 }
899
906 void usb_clock_ungate(usb_core_handle_struct *pudev)
907 {
908 if (pudev->cfg.low_power) {
909 __IO uint32_t power_clock;
910
911 if (1U == (USB_DSTAT & DSTAT_SPST)) {
912 /* un-gate USB core clock */
913 power_clock = USB_PWRCLKCTL;
914 power_clock &= ~PWRCLKCTL_SHCLK;
915 power_clock &= ~PWRCLKCTL_SUCLK;
916
917 USB_PWRCLKCTL = power_clock;
918 }
919 }
920 }
921
928 void usb_device_stop (usb_core_handle_struct *pudev)
929 {
930 uint32_t i;
931
932 pudev->dev.status = 1U;
933
934 for (i = 0U; i < pudev->cfg.dev_endp_num; i++) {
935 USB_DIEPxINTF(i) = 0xFFU;
936 USB_DOEPxINTF(i) = 0xFFU;
937 }
938
939 USB_DIEPINTEN = 0U;
940 USB_DOEPINTEN = 0U;
941 USB_DAEPINTEN = 0U;
942 USB_DAEPINT = 0xFFFFFFFFU;
943
944 /* flush the FIFO */
945 usb_rxfifo_flush(pudev);
946 usb_txfifo_flush(pudev, 0x10U);
947 }
948 #endif /* USE_DEVICE_MODE */
HCHLEN_DPID
#define HCHLEN_DPID
Definition: usb_regs.h:312
HCHINTEN_BBERIE
#define HCHINTEN_BBERIE
Definition: usb_regs.h:302
USB_DIEPxTFLEN
#define USB_DIEPxTFLEN(x)
Definition: usb_regs.h:52
USB_DIEP0TFLEN
#define USB_DIEP0TFLEN
Definition: usb_regs.h:47
GINTEN_OTGIE
#define GINTEN_OTGIE
Definition: usb_regs.h:189
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:49
DOEP0LEN_TLEN
#define DOEP0LEN_TLEN
Definition: usb_regs.h:427
USBFS_MAX_PACKET_SIZE
#define USBFS_MAX_PACKET_SIZE
Definition: usb_defines.h:25
GRFLEN_RXFD
#define GRFLEN_RXFD
Definition: usb_regs.h:200
GINTEN_ISOINCIE
#define GINTEN_ISOINCIE
Definition: usb_regs.h:175
USB_DOEPINTEN
#define USB_DOEPINTEN
Definition: usb_regs.h:70
USB_DIEPxINTF
#define USB_DIEPxINTF(x)
Definition: usb_regs.h:86
USB_FSLSCLOCK_INIT
#define USB_FSLSCLOCK_INIT(ClockFreq)
Definition: usb_regs.h:562
USB_HNPTFLEN
#define USB_HNPTFLEN
Definition: usb_regs.h:46
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:159
HPRT_PRTSPD_LOW_SPEED
#define HPRT_PRTSPD_LOW_SPEED
Definition: usb_defines.h:76
USB_GCCFG
#define USB_GCCFG
Definition: usb_regs.h:49
GINTEN_NPTXFEIE
#define GINTEN_NPTXFEIE
Definition: usb_regs.h:186
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:53
DIEP0TFLEN_IEP0TXFD
#define DIEP0TFLEN_IEP0TXFD
Definition: usb_regs.h:207
DOEP0LEN_STPCNT
#define DOEP0LEN_STPCNT
Definition: usb_regs.h:425
HPCS_PP
#define HPCS_PP
Definition: usb_regs.h:265
HCHCTL_CDIS
#define HCHCTL_CDIS
Definition: usb_regs.h:277
FRAME_INTERVAL_80
#define FRAME_INTERVAL_80
Definition: usb_regs.h:465
GINTEN_RSTIE
#define GINTEN_RSTIE
Definition: usb_regs.h:181
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:166
GINTEN_ISOONCIE
#define GINTEN_ISOONCIE
Definition: usb_regs.h:174
DEPCTL_SNAK
#define DEPCTL_SNAK
Definition: usb_regs.h:393
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:72
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:66
USB_DIEPINTEN
#define USB_DIEPINTEN
Definition: usb_regs.h:69
HCHINTEN_STALLIE
#define HCHINTEN_STALLIE
Definition: usb_regs.h:307
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:69
GAHBCS_TXFTH
#define GAHBCS_TXFTH
Definition: usb_regs.h:118
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:387
HNPTFQSTAT_NPTXFS
#define HNPTFQSTAT_NPTXFS
Definition: usb_regs.h:213
GCCFG_VBUSBCEN
#define GCCFG_VBUSBCEN
Definition: usb_regs.h:222
HC_MAX_PACKET_COUNT
#define HC_MAX_PACKET_COUNT
Definition: usb_core.h:22
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:55
DIEP0TFLEN_IEP0TXRSAR
#define DIEP0TFLEN_IEP0TXRSAR
Definition: usb_regs.h:208
USBFS_MAX_HOST_CHANNELCOUNT
#define USBFS_MAX_HOST_CHANNELCOUNT
Definition: usb_defines.h:26
HCHINTEN_TFIE
#define HCHINTEN_TFIE
Definition: usb_regs.h:309
HCHINTEN_DTERIE
#define HCHINTEN_DTERIE
Definition: usb_regs.h:300
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:39
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:42
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:217
HCCHAR_INTR
#define HCCHAR_INTR
Definition: usb_defines.h:85
GRSTCTL_CSRST
#define GRSTCTL_CSRST
Definition: usb_regs.h:135
GUSBCS_FDM
#define GUSBCS_FDM
Definition: usb_regs.h:122
GCCFG_PWRON
#define GCCFG_PWRON
Definition: usb_regs.h:224
USB_OK
Definition: usb_core.h:30
USB_HNPTFQSTAT
#define USB_HNPTFQSTAT
Definition: usb_regs.h:48
USB_EVEN_FRAME
#define USB_EVEN_FRAME()
Definition: usb_regs.h:556
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:41
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:161
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:52
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:388
USB_DIEPxLEN
#define USB_DIEPxLEN(x)
Definition: usb_regs.h:88
HCHINTEN_NAKIE
#define HCHINTEN_NAKIE
Definition: usb_regs.h:306
TXFIFO_EMPTY_HALF
#define TXFIFO_EMPTY_HALF
Definition: usb_regs.h:452
USB_GRFLEN
#define USB_GRFLEN
Definition: usb_regs.h:45
USB_HCHxLEN
#define USB_HCHxLEN(x)
Definition: usb_regs.h:64
DCTL_RWKUP
#define DCTL_RWKUP
Definition: usb_regs.h:335
USB_GOTGCS
#define USB_GOTGCS
Definition: usb_regs.h:36
HCHCTL_EPTYPE
#define HCHCTL_EPTYPE
Definition: usb_regs.h:281
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:211
USB_PWRCLKCTL
#define USB_PWRCLKCTL
Definition: usb_regs.h:92
HPCS_PRST
#define HPCS_PRST
Definition: usb_regs.h:267
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
USB_HACHINT
#define USB_HACHINT
Definition: usb_regs.h:58
HPTFLEN_HPTXFSAR
#define HPTFLEN_HPTXFSAR
Definition: usb_regs.h:231
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:82
GCCFG_SOFOEN
#define GCCFG_SOFOEN
Definition: usb_regs.h:221
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:64
USB_DOEPxINTF
#define USB_DOEPxINTF(x)
Definition: usb_regs.h:87
GINTEN_IEPIE
#define GINTEN_IEPIE
Definition: usb_regs.h:177
USB_CORE_ULPI_PHY
#define USB_CORE_ULPI_PHY
Definition: usb_defines.h:35
DIEPTFLEN_IEPTXFD
#define DIEPTFLEN_IEPTXFD
Definition: usb_regs.h:234
USB_SPEED_INP_FULL
#define USB_SPEED_INP_FULL
Definition: usb_regs.h:448
GINTEN_OEPIE
#define GINTEN_OEPIE
Definition: usb_regs.h:176
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:84
USB_CORE_SPEED_FULL
#define USB_CORE_SPEED_FULL
Definition: usb_defines.h:23
usb_hostchannel_struct
Definition: usb_core.h:155
HCCHAR_CTRL
#define HCCHAR_CTRL
Definition: usb_defines.h:82
HCCHAR_BULK
#define HCCHAR_BULK
Definition: usb_defines.h:84
GINTEN_SOFIE
#define GINTEN_SOFIE
Definition: usb_regs.h:188
USB_HCHxINTF
#define USB_HCHxINTF(x)
Definition: usb_regs.h:62
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:67
GINTEN_SESIE
#define GINTEN_SESIE
Definition: usb_regs.h:167
USB_CORE_EMBEDDED_PHY
#define USB_CORE_EMBEDDED_PHY
Definition: usb_defines.h:36
GRSTCTL_TXFF
#define GRSTCTL_TXFF
Definition: usb_regs.h:131
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:163
GUSBCS_FHM
#define GUSBCS_FHM
Definition: usb_regs.h:123
USB_DAEPINT
#define USB_DAEPINT
Definition: usb_regs.h:71
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:68
HCHINTEN_NYETIE
#define HCHINTEN_NYETIE
Definition: usb_regs.h:304
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:63
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:68
GCCFG_VBUSACEN
#define GCCFG_VBUSACEN
Definition: usb_regs.h:223
GINTEN_ENUMFIE
#define GINTEN_ENUMFIE
Definition: usb_regs.h:180
DOEP0LEN_PCNT
#define DOEP0LEN_PCNT
Definition: usb_regs.h:426
usb_fifo_read
void * usb_fifo_read(uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint
Definition: usb_core.c:105
HACHINTEN_CINTEN
#define HACHINTEN_CINTEN
Definition: usb_regs.h:261
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:159
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:268
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:167
GINTF_HCIF
#define GINTF_HCIF
Definition: usb_regs.h:143
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:94
usb_core.h
USB core driver header file.
USB_HCHxINTEN
#define USB_HCHxINTEN(x)
Definition: usb_regs.h:63
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:85
USB_GOTGINTF
#define USB_GOTGINTF
Definition: usb_regs.h:37
DSTAT_SPST
#define DSTAT_SPST
Definition: usb_regs.h:340
GRSTCTL_RXFF
#define GRSTCTL_RXFF
Definition: usb_regs.h:132
USB_HPTFQSTAT
#define USB_HPTFQSTAT
Definition: usb_regs.h:57
HCHCTL_ODDFRM
#define HCHCTL_ODDFRM
Definition: usb_regs.h:278
HPTFLEN_HPTXFD
#define HPTFLEN_HPTXFD
Definition: usb_regs.h:230
GINTEN_WKUPIE
#define GINTEN_WKUPIE
Definition: usb_regs.h:166
HCHCTL_EPDIR
#define HCHCTL_EPDIR
Definition: usb_regs.h:283
usb_status_enum
usb_status_enum
Definition: usb_core.h:28
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:157
HCHCTL_CEN
#define HCHCTL_CEN
Definition: usb_regs.h:276
HNPTFLEN_HNPTXRSAR
#define HNPTFLEN_HNPTXRSAR
Definition: usb_regs.h:204
USB_HCHxCTL
#define USB_HCHxCTL(x)
Definition: usb_regs.h:61
GCCFG_VBUSIG
#define GCCFG_VBUSIG
Definition: usb_regs.h:220
USB_FS_CORE_ID
Definition: usb_defines.h:90
HCHINTEN_USBERIE
#define HCHINTEN_USBERIE
Definition: usb_regs.h:303
usb_core_handle_struct
Definition: usb_core.h:201
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:158
DIEPTFLEN_IEPTXRSAR
#define DIEPTFLEN_IEPTXRSAR
Definition: usb_regs.h:235
USB_HACHINTEN
#define USB_HACHINTEN
Definition: usb_regs.h:59
USBFS_MAX_FIFO_WORDLEN
#define USBFS_MAX_FIFO_WORDLEN
Definition: usb_defines.h:28
USBFS_MAX_DEV_EPCOUNT
#define USBFS_MAX_DEV_EPCOUNT
Definition: usb_defines.h:27
HNPTFLEN_HNPTXFD
#define HNPTFLEN_HNPTXFD
Definition: usb_regs.h:203
GINTEN_PTXFEIE
#define GINTEN_PTXFEIE
Definition: usb_regs.h:170
GINTF_HPIF
#define GINTF_HPIF
Definition: usb_regs.h:144
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:89
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:40
HCHLEN_PCNT
#define HCHLEN_PCNT
Definition: usb_regs.h:313
usb_core_cfgs_struct::max_fifo_size
uint16_t max_fifo_size
Definition: usb_core.h:70
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:162
NULL
#define NULL
Definition: usbd_std.h:20
usb_core_cfgs_struct::core_id
uint8_t core_id
Definition: usb_core.h:62
PWRCLKCTL_SUCLK
#define PWRCLKCTL_SUCLK
Definition: usb_regs.h:441
USB_HPCS
#define USB_HPCS
Definition: usb_regs.h:60
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:238
GINTEN_RXFNEIE
#define GINTEN_RXFNEIE
Definition: usb_regs.h:187
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:146
USB_HPTFLEN
#define USB_HPTFLEN
Definition: usb_regs.h:51
HPTFQSTAT_PTXFS
#define HPTFQSTAT_PTXFS
Definition: usb_regs.h:250
USB_DCFG
#define USB_DCFG
Definition: usb_regs.h:66
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:170
USB_PORT_READ
#define USB_PORT_READ()
Definition: usb_regs.h:559
GINTEN_HCIE
#define GINTEN_HCIE
Definition: usb_regs.h:171
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:65
USB_GAHBCS
#define USB_GAHBCS
Definition: usb_regs.h:38
HCTLR_30_60_MHZ
#define HCTLR_30_60_MHZ
Definition: usb_defines.h:78
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:128
GINTEN_SPIE
#define GINTEN_SPIE
Definition: usb_regs.h:182
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:160
DCFG_DS
#define DCFG_DS
Definition: usb_regs.h:324
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:48
HCHLEN_TLEN
#define HCHLEN_TLEN
Definition: usb_regs.h:314
HCTLR_48_MHZ
#define HCTLR_48_MHZ
Definition: usb_defines.h:79
DCFG_EOPFT
#define DCFG_EOPFT
Definition: usb_regs.h:321
GINTF_DISCIF
#define GINTF_DISCIF
Definition: usb_regs.h:140
USB_DCTL
#define USB_DCTL
Definition: usb_regs.h:67
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:87
HCHINTEN_REQOVRIE
#define HCHINTEN_REQOVRIE
Definition: usb_regs.h:301
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:203
HCHINTEN_ACKIE
#define HCHINTEN_ACKIE
Definition: usb_regs.h:305
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:54
PWRCLKCTL_SHCLK
#define PWRCLKCTL_SHCLK
Definition: usb_regs.h:440
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:160
GOTGCS_HHNPEN
#define GOTGCS_HHNPEN
Definition: usb_regs.h:102
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Source/usbh_core.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Source
usbh_core.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "usbh_hcs.h"
14 #include "usbh_core.h"
15 #include "usbh_int.h"
16 #include "stdio.h"
17 #include "usbh_std.h"
18 #include "usbh_ctrl.h"
19 #include "usb_core.h"
20
21 extern class_polling_fun_cb_struct class_polling_cb;
22
23 uint8_t usbh_sof (usb_core_handle_struct *pudev);
24 uint8_t usbh_connected (usb_core_handle_struct *pudev);
25 uint8_t usbh_disconnected (usb_core_handle_struct *pudev);
26
27 usbh_hcd_int_cb_struct usbh_hcd_int_cb =
28 {
29 usbh_sof,
30 usbh_connected,
31 usbh_disconnected,
32 };
33
34 usbh_hcd_int_cb_struct *usbh_hcd_int_fops = &usbh_hcd_int_cb;
35 extern usbh_state_handle_struct usbh_state_core;
36
37 static void host_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
38 static void host_dev_attached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
39 static void host_dev_detached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
40 static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
41 static void host_enum_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
42 static void host_class_request_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
43 static void host_class_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
44 static void host_user_input_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
45 static void host_suspended_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
46 static void host_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
47
48 static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
49 static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
50
51 /* the host state handle function array */
52 void (*host_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) =
53 {
54 host_idle_handle,
55 host_dev_attached_handle,
56 host_dev_detached_handle,
57 host_detect_dev_speed_handle,
58 host_enum_handle,
59 host_class_request_handle,
60 host_class_handle,
61 host_user_input_handle,
62 host_suspended_handle,
63 host_error_handle,
64 };
65
66 /* the host state handle table */
67 state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE] =
68 {
69 /* the current state the current event the next state the event function */
70 {HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move },
71 {HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move },
72 {HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move },
73 {HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move },
74 {HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move },
75 {HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move },
76 {HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move },
77 {HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move },
78 {HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move },
79 };
80
89 usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev,
90 usbh_host_struct *puhost,
91 void *pustate)
92 {
93 usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate;
94
95 scd_begin(p_state, HOST_FSM_ID);
96
97 if (-1 == p_state->usbh_current_state_stack_top) {
98 uint8_t cur_state = p_state->usbh_current_state;
99
100 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) {
101 if (HOST_DEV_DETACHED != cur_state) {
102 p_state->usbh_current_state = HOST_DEV_DETACHED;
103 cur_state = HOST_DEV_DETACHED;
104 }
105 }
106
107 host_state_handle[cur_state](pudev, puhost, p_state);
108 } else {
109 uint8_t stack0_state = p_state->stack[0].state;
110
111 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) {
112 if (HOST_DEV_DETACHED != stack0_state) {
113 p_state->stack[0].state = HOST_DEV_DETACHED;
114 stack0_state = HOST_DEV_DETACHED;
115 p_state->usbh_current_state = HOST_DEV_DETACHED;
116 }
117 }
118
119 host_state_handle[stack0_state](pudev, puhost, p_state);
120 }
121
122 return USBH_OK;
123 }
124
133 static void host_idle_handle (usb_core_handle_struct *pudev,
134 usbh_host_struct *puhost,
135 usbh_state_handle_struct *pustate)
136 {
137 if (hcd_is_device_connected(pudev)) {
138 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ATTACHED, pustate->usbh_current_state);
139
140 if ((void *)0 != pudev->mdelay) {
141 pudev->mdelay(100U);
142 }
143 }
144 }
145
154 static void host_dev_attached_handle (usb_core_handle_struct *pudev,
155 usbh_host_struct *puhost,
156 usbh_state_handle_struct *pustate)
157 {
158 puhost->usr_cb->device_connected();
159 puhost->control.hc_out_num = usbh_channel_alloc(pudev, 0x00U);
160 puhost->control.hc_in_num = usbh_channel_alloc(pudev, 0x80U);
161
162 /* reset usb device */
163 if (0U == usb_port_reset(pudev)) {
164 puhost->usr_cb->device_reset();
165
166 /* wait for USB USBH_ISR_PrtEnDisableChange()
167 * host is now ready to start the enumeration
168 */
169 puhost->device.speed = (uint8_t)USB_CURRENT_SPEED_GET();
170 puhost->usr_cb->device_speed_detected(puhost->device.speed);
171
172 /* open IN control pipes */
173 usbh_channel_open (pudev,
174 puhost->control.hc_in_num,
175 puhost->device.address,
176 puhost->device.speed,
177 USB_EPTYPE_CTRL,
178 (uint16_t)puhost->control.ep0_size);
179
180 /* open OUT control pipes */
181 usbh_channel_open (pudev,
182 puhost->control.hc_out_num,
183 puhost->device.address,
184 puhost->device.speed,
185 USB_EPTYPE_CTRL,
186 (uint16_t)puhost->control.ep0_size);
187
188 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ENUM, pustate->usbh_current_state);
189 }
190 }
191
200 static void host_enum_handle (usb_core_handle_struct *pudev,
201 usbh_host_struct *puhost,
202 usbh_state_handle_struct *pustate)
203 {
204 if (USBH_OK == enum_state_polling_fun(pudev, puhost, pustate)) {
205 puhost->usr_cb->enumeration_finish();
206 scd_event_handle(pudev,
207 puhost,
208 pustate,
209 HOST_EVENT_USER_INPUT,
210 pustate->usbh_current_state);
211 }
212 }
213
222 static void host_user_input_handle (usb_core_handle_struct *pudev,
223 usbh_host_struct *puhost,
224 usbh_state_handle_struct *pustate)
225 {
226 if (USBH_USER_RESP_OK == puhost->usr_cb->user_input()) {
227 if (USBH_OK == (puhost->class_init(pudev, puhost))) {
228 scd_event_handle(pudev,
229 puhost,
230 pustate,
231 HOST_EVENT_CLASS_REQ,
232 pustate->usbh_current_state);
233 }
234 }
235 }
236
245 static void host_class_request_handle (usb_core_handle_struct *pudev,
246 usbh_host_struct *puhost,
247 usbh_state_handle_struct *pustate)
248 {
249 if (USBH_OK == class_req_state_polling_fun(pudev, puhost, pustate)) {
250 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_CLASS, pustate->usbh_current_state);
251 }
252 }
253
262 static void host_class_handle (usb_core_handle_struct *pudev,
263 usbh_host_struct *puhost,
264 usbh_state_handle_struct *pustate)
265 {
266 class_state_polling_fun(pudev, puhost, pustate);
267 }
268
277 static void host_suspended_handle (usb_core_handle_struct *pudev,
278 usbh_host_struct *puhost,
279 usbh_state_handle_struct *pustate)
280 {
281 /* no operation */
282 }
283
292 static void host_error_handle (usb_core_handle_struct *pudev,
293 usbh_host_struct *puhost,
294 usbh_state_handle_struct *pustate)
295 {
296 /* re-initilaize host for new enumeration */
297 usbh_deinit (pudev, puhost,&usbh_state_core);
298 puhost->usr_cb->deinit();
299 puhost->class_deinit(pudev, &puhost->device);
300 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state);
301 }
302
311 static void host_dev_detached_handle (usb_core_handle_struct *pudev,
312 usbh_host_struct *puhost,
313 usbh_state_handle_struct *pustate)
314 {
315 /* manage user disconnect operations*/
316 puhost->usr_cb->device_disconnected();
317
318 /* re-initilaize host for new enumeration */
319 usbh_deinit(pudev, puhost,&usbh_state_core);
320 puhost->usr_cb->deinit();
321 puhost->class_deinit(pudev, &puhost->device);
322 usbh_allchannel_dealloc(pudev);
323 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state);
324 }
325
334 static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev,
335 usbh_host_struct *puhost,
336 usbh_state_handle_struct *pustate)
337 {
338 /* no operation */
339 }
340
347 uint8_t usbh_connected (usb_core_handle_struct *pudev)
348 {
349 pudev->host.connect_status = 1U;
350
351 return 0U;
352 }
353
360 uint8_t usbh_disconnected (usb_core_handle_struct *pudev)
361 {
362 pudev->host.connect_status = 0U;
363
364 return 0U;
365 }
366
373 uint8_t usbh_sof (usb_core_handle_struct *pudev)
374 {
375 /* this callback could be used to implement a scheduler process */
376 return 0U;
377 }
378
386 uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
387 {
388 pudev->host.connect_status = 0U;
389
390 pudev->host.host_channel[0].endp_mps = 8U;
391
392 usb_core_select(pudev, core_id);
393
394 #ifndef DUAL_ROLE_MODE_ENABLED
395
396 USB_GLOBAL_INT_DISABLE();
397
398 usb_core_init(pudev);
399
400 /* force host mode*/
401 usb_mode_set(pudev, HOST_MODE);
402
403 usb_hostcore_init(pudev);
404
405 USB_GLOBAL_INT_ENABLE();
406
407 #endif
408
409 return 0U;
410 }
411
418 uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
419 {
420 return (uint32_t)(pudev->host.connect_status);
421 }
422
430 urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num)
431 {
432 return pudev->host.host_channel[channel_num].urb_state;
433 }
434
442 uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num)
443 {
444 return pudev->host.host_channel[channel_num].xfer_count;
445 }
446
454 usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev,
455 usbh_host_struct *puhost,
456 usbh_state_handle_struct* pustate)
457 {
458 /* software init */
459
460 puhost->control.ep0_size = USB_MAX_EP0_SIZE;
461
462 puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT;
463 puhost->device.speed = HPRT_PRTSPD_FULL_SPEED;
464
465 usbh_channel_free(pudev, puhost->control.hc_in_num);
466 usbh_channel_free(pudev, puhost->control.hc_out_num);
467
468 scd_init(pustate);
469 scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE);
470 scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE);
471 scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE);
472
473 scd_begin(pustate,HOST_FSM_ID);
474 scd_state_move(pustate, HOST_IDLE);
475
476 return USBH_OK;
477 }
478
485 void scd_init(usbh_state_handle_struct* pustate)
486 {
487 /* init the state core */
488 pustate->usbh_current_state = 0U;
489 pustate->usbh_current_state_table = NULL;
490 pustate->usbh_current_state_table_size = 0U;
491
492 pustate->usbh_current_state_stack_top = -1;
493 pustate->stack->state = 0U;
494 pustate->stack->table_size = 0U;
495 pustate->stack->table = NULL;
496
497 pustate->usbh_regist_state_table_num = 0U;
498 pustate->usbh_regist_state_table->table = NULL;
499 pustate->usbh_regist_state_table->table_size = 0U;
500 pustate->usbh_regist_state_table->id = 0U;
501
502 /* init the control and the enumeration polling handle flag */
503 ctrl_polling_handle_flag = 0U;
504 enum_polling_handle_flag = 0U;
505 }
506
516 void scd_table_regist (usbh_state_handle_struct* pustate,
517 state_table_struct* pstate_table,
518 uint8_t table_id,
519 uint8_t current_table_size)
520 {
521 usbh_state_regist_table_struct *cur_state_reg_table;
522
523 cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num];
524
525 cur_state_reg_table->id = table_id;
526 cur_state_reg_table->table = pstate_table;
527 cur_state_reg_table->table_size = current_table_size;
528
529 pustate->usbh_regist_state_table_num++;
530 }
531
539 void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id)
540 {
541 uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num;
542 usbh_state_regist_table_struct *cur_state_reg_table;
543
544 for (i = 0U; i < table_num; i++) {
545 cur_state_reg_table = &pustate->usbh_regist_state_table[i];
546
547 if (table_id == cur_state_reg_table->id) {
548 pustate->usbh_current_state_table = cur_state_reg_table->table;
549 pustate->usbh_current_state_table_size = cur_state_reg_table->table_size;
550 break;
551 }
552 }
553 }
554
562 void scd_state_move(usbh_state_handle_struct* pustate, uint8_t state)
563 {
564 pustate->usbh_current_state = state;
565 }
566
577 usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev,
578 usbh_host_struct *puhost,
579 usbh_state_handle_struct* pustate,
580 uint8_t event,
581 uint8_t state)
582 {
583 uint8_t i = 0U;
584 ACT_FUN event_act_fun = NULL;
585 state_table_struct *backup_state_t = pustate->usbh_current_state_table;
586 state_table_struct *executive_state_table = pustate->usbh_current_state_table;
587
588 /* look up the table to find the action function */
589 for (i = 0U; i < pustate->usbh_current_state_table_size; i++) {
590 if (state == executive_state_table->cur_state) {
591 if (event == executive_state_table->cur_event) {
592 state = executive_state_table->next_state;
593 event_act_fun = executive_state_table->event_action_fun;
594 break;
595 } else {
596 executive_state_table++;
597 }
598 } else {
599 executive_state_table++;
600 }
601 }
602
603 pustate->usbh_current_state_table = backup_state_t;
604
605 /* if the action function is not NULL, execute the action function */
606 if (event_act_fun) {
607 if (event_act_fun == &only_state_move) {
608 pustate->usbh_current_state = state;
609 } else {
610 return event_act_fun(pudev, puhost, pustate);
611 }
612 }
613
614 return USBH_BUSY;
615 }
616
623 void scd_table_push(usbh_state_handle_struct* pustate)
624 {
625 usbh_state_stack_struct *top_state_element;
626
627 if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) {
628 pustate->usbh_current_state_stack_top++;
629
630 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
631
632 /* put the current state table into the state stack */
633 top_state_element->state = pustate->usbh_current_state;
634 top_state_element->table = pustate->usbh_current_state_table;
635 top_state_element->table_size = pustate->usbh_current_state_table_size;
636 }
637 }
638
645 void scd_table_pop (usbh_state_handle_struct* pustate)
646 {
647 usbh_state_stack_struct *top_state_element;
648
649 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
650
651 if (pustate->usbh_current_state_stack_top > -1) {
652 /* get the current state table from the state stack */
653 pustate->usbh_current_state = top_state_element->state;
654 pustate->usbh_current_state_table = top_state_element->table;
655 pustate->usbh_current_state_table_size = top_state_element->table_size;
656 pustate->usbh_current_state_stack_top--;
657 }
658 }
667 static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
668 {
669 return class_polling_cb.class_req_polling(pudev, puhost, pustate);
670 }
671
680 static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
681 {
682 return class_polling_cb.class_polling(pudev, puhost, pustate);
683 }
684
693 usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
694 {
695 return USBH_OK;
696 }
697
706 usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
707 {
708 scd_table_pop((usbh_state_handle_struct *)pustate);
709
710 return USBH_OK;
711 }
usbh_hcd_int_fops
usbh_hcd_int_cb_struct * usbh_hcd_int_fops
Definition: usbh_core.c:34
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:230
HOST_EVENT_IDLE
Definition: usbh_core.h:76
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:128
usbh_core.h
header file for usbh_core.c
usbh_std.h
header file for usbh_std.c
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:49
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:268
usbh_state_handle_struct
Definition: usbh_core.h:228
HOST_EVENT_CLASS_REQ
Definition: usbh_core.h:72
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:20
hcd_is_device_connected
uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
check if the device is connected.
Definition: usbh_core.c:418
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:40
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:214
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:115
host_handle_table
state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE]
Definition: usbh_core.c:67
HOST_EVENT_CLASS
Definition: usbh_core.h:73
state_table_struct::event_action_fun
ACT_FUN event_action_fun
Definition: usbh_core.h:208
urb_state_enum
urb_state_enum
Definition: usb_core.h:49
usbh_user_callback_struct::user_input
usbh_user_status_enum(* user_input)(void)
Definition: usbh_core.h:171
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:42
HOST_EVENT_ENUM
Definition: usbh_core.h:70
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:128
scd_event_handle
usbh_status_enum scd_event_handle(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle
Definition: usbh_core.c:577
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:232
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:623
HOST_CLASS
Definition: usbh_core.h:60
HOST_ERROR
Definition: usbh_core.h:63
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:562
HOST_DEV_DETACHED
Definition: usbh_core.h:56
usbh_user_callback_struct::device_connected
void(* device_connected)(void)
Definition: usbh_core.h:154
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:52
usbh_host_struct::class_deinit
void(* class_deinit)(usb_core_handle_struct *pudev, void *phost)
Definition: usbh_core.h:196
HOST_EVENT_ERROR
Definition: usbh_core.h:74
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:107
scd_table_regist
void scd_table_regist(usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist
Definition: usbh_core.c:516
usbh_host_struct
Definition: usbh_core.h:189
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:130
usbh_connected
uint8_t usbh_connected(usb_core_handle_struct *pudev)
usb connect callback function from the interrupt.
Definition: usbh_core.c:347
HOST_DEV_ATTACHED
Definition: usbh_core.h:55
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:539
scd_init
void scd_init(usbh_state_handle_struct *pustate)
state core driver init
Definition: usbh_core.c:485
CTRL_HANDLE_TABLE_SIZE
#define CTRL_HANDLE_TABLE_SIZE
Definition: usbh_ctrl.h:19
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:237
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:218
usbh_host_struct::usr_cb
usbh_user_callback_struct * usr_cb
Definition: usbh_core.h:194
usbh_user_callback_struct::enumeration_finish
void(* enumeration_finish)(void)
Definition: usbh_core.h:170
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:238
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:224
usbh_device_struct::speed
uint8_t speed
Definition: usbh_core.h:142
hcd_init
uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize the host portion of the driver.
Definition: usbh_core.c:386
usbh_ctrl.h
header file for usbh_ctrl.c
hcd_urb_state_get
urb_state_enum hcd_urb_state_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:430
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:222
state_table_struct::next_state
uint8_t next_state
Definition: usbh_core.h:207
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:39
HOST_ENUMERATION
Definition: usbh_core.h:58
usbh_deinit
usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
de-initialize host
Definition: usbh_core.c:454
scd_table_pop
void scd_table_pop(usbh_state_handle_struct *pustate)
state core driver table pop
Definition: usbh_core.c:645
usbh_hcd_int_cb
usbh_hcd_int_cb_struct usbh_hcd_int_cb
Definition: usbh_core.c:27
hcd_xfer_count_get
uint32_t hcd_xfer_count_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:442
USBH_USER_RESP_OK
Definition: usbh_core.h:122
usbh_state_stack_struct
Definition: usbh_core.h:212
state_table_struct
Definition: usbh_core.h:203
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:234
usbh_int.h
USB host mode interrupt handler header file.
usb_core.h
USB core driver header file.
state_table_struct::cur_state
uint8_t cur_state
Definition: usbh_core.h:205
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:215
ACT_FUN
usbh_status_enum(* ACT_FUN)(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
Definition: usbh_core.h:200
usbh_user_callback_struct::device_disconnected
void(* device_disconnected)(void)
Definition: usbh_core.h:156
usbh_hcs.h
header file for usbh_hcs.c
usbh_sof
uint8_t usbh_sof(usb_core_handle_struct *pudev)
usb sof callback function from the interrupt.
Definition: usbh_core.c:373
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:141
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:17
host_state_handle
void(* host_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_core.c:52
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:223
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:493
usb_core_handle_struct
Definition: usb_core.h:201
HOST_EVENT_ATTACHED
Definition: usbh_core.h:69
usbh_state_core
usbh_state_handle_struct usbh_state_core
ctrl_handle_table
state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Definition: usbh_ctrl.c:47
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:235
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:231
HPRT_PRTSPD_FULL_SPEED
#define HPRT_PRTSPD_FULL_SPEED
Definition: usb_defines.h:75
USB_MAX_EP0_SIZE
#define USB_MAX_EP0_SIZE
Definition: usb_core.h:20
usbh_host_struct::class_init
usbh_status_enum(* class_init)(usb_core_handle_struct *pudev, void *phost)
Definition: usbh_core.h:195
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:216
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:193
USBH_OK
Definition: usbh_core.h:109
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:490
NULL
#define NULL
Definition: usbd_std.h:20
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:706
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:170
usbh_user_callback_struct::deinit
void(* deinit)(void)
Definition: usbh_core.h:153
class_polling_cb
class_polling_fun_cb_struct class_polling_cb
HOST_CLASS_REQUEST
Definition: usbh_core.h:59
usbh_hcd_int_cb_struct
Definition: usbh_int.h:18
usbh_allchannel_dealloc
uint8_t usbh_allchannel_dealloc(usb_core_handle_struct *pudev)
free all usb host channel
Definition: usbh_hcs.c:130
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:192
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:24
host_state_polling_fun
usbh_status_enum host_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of HOST state
Definition: usbh_core.c:89
MAX_USBH_STATE_STACK_DEEP
#define MAX_USBH_STATE_STACK_DEEP
Definition: usbh_core.h:36
usbh_user_callback_struct::device_reset
void(* device_reset)(void)
Definition: usbh_core.h:155
HOST_USER_INPUT
Definition: usbh_core.h:61
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:49
usbh_state_regist_table_struct
Definition: usbh_core.h:220
USB_CURRENT_SPEED_GET
#define USB_CURRENT_SPEED_GET()
Definition: usb_regs.h:569
HOST_IDLE
Definition: usbh_core.h:54
usbh_disconnected
uint8_t usbh_disconnected(usb_core_handle_struct *pudev)
usb disconnect callback function from the interrupt.
Definition: usbh_core.c:360
USBH_DEVICE_ADDRESS_DEFAULT
#define USBH_DEVICE_ADDRESS_DEFAULT
Definition: usbh_core.h:25
usbh_user_callback_struct::device_speed_detected
void(* device_speed_detected)(uint8_t device_speed)
Definition: usbh_core.h:158
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:129
HOST_HANDLE_TABLE_SIZE
#define HOST_HANDLE_TABLE_SIZE
Definition: usbh_core.h:49
usbh_channel_open
uint8_t usbh_channel_open(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel
Definition: usbh_hcs.c:28
usbh_channel_alloc
uint8_t usbh_channel_alloc(usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe
Definition: usbh_hcs.c:97
enum_state_polling_fun
usbh_status_enum enum_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state
Definition: usbh_std.c:72
USBH_BUSY
Definition: usbh_core.h:110
state_table_struct::cur_event
uint8_t cur_event
Definition: usbh_core.h:206
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:87
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:693
HOST_EVENT_USER_INPUT
Definition: usbh_core.h:71
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_exti.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_EXTI_H
14 #define GD32F10X_EXTI_H
15
16 #include "gd32f10x.h"
17
18 /* EXTI definitions */
19 #define EXTI EXTI_BASE
20
21 /* registers definitions */
22 #define EXTI_INTEN REG32(EXTI + 0x00U)
23 #define EXTI_EVEN REG32(EXTI + 0x04U)
24 #define EXTI_RTEN REG32(EXTI + 0x08U)
25 #define EXTI_FTEN REG32(EXTI + 0x0CU)
26 #define EXTI_SWIEV REG32(EXTI + 0x10U)
27 #define EXTI_PD REG32(EXTI + 0x14U)
29 /* bits definitions */
30 /* EXTI_INTEN */
31 #define EXTI_INTEN_INTEN0 BIT(0)
32 #define EXTI_INTEN_INTEN1 BIT(1)
33 #define EXTI_INTEN_INTEN2 BIT(2)
34 #define EXTI_INTEN_INTEN3 BIT(3)
35 #define EXTI_INTEN_INTEN4 BIT(4)
36 #define EXTI_INTEN_INTEN5 BIT(5)
37 #define EXTI_INTEN_INTEN6 BIT(6)
38 #define EXTI_INTEN_INTEN7 BIT(7)
39 #define EXTI_INTEN_INTEN8 BIT(8)
40 #define EXTI_INTEN_INTEN9 BIT(9)
41 #define EXTI_INTEN_INTEN10 BIT(10)
42 #define EXTI_INTEN_INTEN11 BIT(11)
43 #define EXTI_INTEN_INTEN12 BIT(12)
44 #define EXTI_INTEN_INTEN13 BIT(13)
45 #define EXTI_INTEN_INTEN14 BIT(14)
46 #define EXTI_INTEN_INTEN15 BIT(15)
47 #define EXTI_INTEN_INTEN16 BIT(16)
48 #define EXTI_INTEN_INTEN17 BIT(17)
49 #define EXTI_INTEN_INTEN18 BIT(18)
50 #define EXTI_INTEN_INTEN19 BIT(19)
52 /* EXTI_EVEN */
53 #define EXTI_EVEN_EVEN0 BIT(0)
54 #define EXTI_EVEN_EVEN1 BIT(1)
55 #define EXTI_EVEN_EVEN2 BIT(2)
56 #define EXTI_EVEN_EVEN3 BIT(3)
57 #define EXTI_EVEN_EVEN4 BIT(4)
58 #define EXTI_EVEN_EVEN5 BIT(5)
59 #define EXTI_EVEN_EVEN6 BIT(6)
60 #define EXTI_EVEN_EVEN7 BIT(7)
61 #define EXTI_EVEN_EVEN8 BIT(8)
62 #define EXTI_EVEN_EVEN9 BIT(9)
63 #define EXTI_EVEN_EVEN10 BIT(10)
64 #define EXTI_EVEN_EVEN11 BIT(11)
65 #define EXTI_EVEN_EVEN12 BIT(12)
66 #define EXTI_EVEN_EVEN13 BIT(13)
67 #define EXTI_EVEN_EVEN14 BIT(14)
68 #define EXTI_EVEN_EVEN15 BIT(15)
69 #define EXTI_EVEN_EVEN16 BIT(16)
70 #define EXTI_EVEN_EVEN17 BIT(17)
71 #define EXTI_EVEN_EVEN18 BIT(18)
72 #define EXTI_EVEN_EVEN19 BIT(19)
74 /* EXTI_RTEN */
75 #define EXTI_RTEN_RTEN0 BIT(0)
76 #define EXTI_RTEN_RTEN1 BIT(1)
77 #define EXTI_RTEN_RTEN2 BIT(2)
78 #define EXTI_RTEN_RTEN3 BIT(3)
79 #define EXTI_RTEN_RTEN4 BIT(4)
80 #define EXTI_RTEN_RTEN5 BIT(5)
81 #define EXTI_RTEN_RTEN6 BIT(6)
82 #define EXTI_RTEN_RTEN7 BIT(7)
83 #define EXTI_RTEN_RTEN8 BIT(8)
84 #define EXTI_RTEN_RTEN9 BIT(9)
85 #define EXTI_RTEN_RTEN10 BIT(10)
86 #define EXTI_RTEN_RTEN11 BIT(11)
87 #define EXTI_RTEN_RTEN12 BIT(12)
88 #define EXTI_RTEN_RTEN13 BIT(13)
89 #define EXTI_RTEN_RTEN14 BIT(14)
90 #define EXTI_RTEN_RTEN15 BIT(15)
91 #define EXTI_RTEN_RTEN16 BIT(16)
92 #define EXTI_RTEN_RTEN17 BIT(17)
93 #define EXTI_RTEN_RTEN18 BIT(18)
94 #define EXTI_RTEN_RTEN19 BIT(19)
96 /* EXTI_FTEN */
97 #define EXTI_FTEN_FTEN0 BIT(0)
98 #define EXTI_FTEN_FTEN1 BIT(1)
99 #define EXTI_FTEN_FTEN2 BIT(2)
100 #define EXTI_FTEN_FTEN3 BIT(3)
101 #define EXTI_FTEN_FTEN4 BIT(4)
102 #define EXTI_FTEN_FTEN5 BIT(5)
103 #define EXTI_FTEN_FTEN6 BIT(6)
104 #define EXTI_FTEN_FTEN7 BIT(7)
105 #define EXTI_FTEN_FTEN8 BIT(8)
106 #define EXTI_FTEN_FTEN9 BIT(9)
107 #define EXTI_FTEN_FTEN10 BIT(10)
108 #define EXTI_FTEN_FTEN11 BIT(11)
109 #define EXTI_FTEN_FTEN12 BIT(12)
110 #define EXTI_FTEN_FTEN13 BIT(13)
111 #define EXTI_FTEN_FTEN14 BIT(14)
112 #define EXTI_FTEN_FTEN15 BIT(15)
113 #define EXTI_FTEN_FTEN16 BIT(16)
114 #define EXTI_FTEN_FTEN17 BIT(17)
115 #define EXTI_FTEN_FTEN18 BIT(18)
116 #define EXTI_FTEN_FTEN19 BIT(19)
118 /* EXTI_SWIEV */
119 #define EXTI_SWIEV_SWIEV0 BIT(0)
120 #define EXTI_SWIEV_SWIEV1 BIT(1)
121 #define EXTI_SWIEV_SWIEV2 BIT(2)
122 #define EXTI_SWIEV_SWIEV3 BIT(3)
123 #define EXTI_SWIEV_SWIEV4 BIT(4)
124 #define EXTI_SWIEV_SWIEV5 BIT(5)
125 #define EXTI_SWIEV_SWIEV6 BIT(6)
126 #define EXTI_SWIEV_SWIEV7 BIT(7)
127 #define EXTI_SWIEV_SWIEV8 BIT(8)
128 #define EXTI_SWIEV_SWIEV9 BIT(9)
129 #define EXTI_SWIEV_SWIEV10 BIT(10)
130 #define EXTI_SWIEV_SWIEV11 BIT(11)
131 #define EXTI_SWIEV_SWIEV12 BIT(12)
132 #define EXTI_SWIEV_SWIEV13 BIT(13)
133 #define EXTI_SWIEV_SWIEV14 BIT(14)
134 #define EXTI_SWIEV_SWIEV15 BIT(15)
135 #define EXTI_SWIEV_SWIEV16 BIT(16)
136 #define EXTI_SWIEV_SWIEV17 BIT(17)
137 #define EXTI_SWIEV_SWIEV18 BIT(18)
138 #define EXTI_SWIEV_SWIEV19 BIT(19)
140 /* EXTI_PD */
141 #define EXTI_PD_PD0 BIT(0)
142 #define EXTI_PD_PD1 BIT(1)
143 #define EXTI_PD_PD2 BIT(2)
144 #define EXTI_PD_PD3 BIT(3)
145 #define EXTI_PD_PD4 BIT(4)
146 #define EXTI_PD_PD5 BIT(5)
147 #define EXTI_PD_PD6 BIT(6)
148 #define EXTI_PD_PD7 BIT(7)
149 #define EXTI_PD_PD8 BIT(8)
150 #define EXTI_PD_PD9 BIT(9)
151 #define EXTI_PD_PD10 BIT(10)
152 #define EXTI_PD_PD11 BIT(11)
153 #define EXTI_PD_PD12 BIT(12)
154 #define EXTI_PD_PD13 BIT(13)
155 #define EXTI_PD_PD14 BIT(14)
156 #define EXTI_PD_PD15 BIT(15)
157 #define EXTI_PD_PD16 BIT(16)
158 #define EXTI_PD_PD17 BIT(17)
159 #define EXTI_PD_PD18 BIT(18)
160 #define EXTI_PD_PD19 BIT(19)
162 /* constants definitions */
163 /* EXTI line number */
164 typedef enum
165 {
166 EXTI_0 = BIT(0),
167 EXTI_1 = BIT(1),
168 EXTI_2 = BIT(2),
169 EXTI_3 = BIT(3),
170 EXTI_4 = BIT(4),
171 EXTI_5 = BIT(5),
172 EXTI_6 = BIT(6),
173 EXTI_7 = BIT(7),
174 EXTI_8 = BIT(8),
175 EXTI_9 = BIT(9),
176 EXTI_10 = BIT(10),
177 EXTI_11 = BIT(11),
178 EXTI_12 = BIT(12),
179 EXTI_13 = BIT(13),
180 EXTI_14 = BIT(14),
181 EXTI_15 = BIT(15),
182 EXTI_16 = BIT(16),
183 EXTI_17 = BIT(17),
184 EXTI_18 = BIT(18),
185 EXTI_19 = BIT(19),
186 }exti_line_enum;
187
188 /* external interrupt and event */
189 typedef enum
190 {
191 EXTI_INTERRUPT = 0,
192 EXTI_EVENT
193 }exti_mode_enum;
194
195 /* interrupt trigger mode */
196 typedef enum
197 {
198 EXTI_TRIG_RISING = 0,
199 EXTI_TRIG_FALLING,
200 EXTI_TRIG_BOTH
201 }exti_trig_type_enum;
202
203 /* function declarations */
204 /* deinitialize the EXTI */
205 void exti_deinit(void);
206 /* enable the configuration of EXTI initialize */
207 void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
208 /* enable the interrupts from EXTI line x */
209 void exti_interrupt_enable(exti_line_enum linex);
210 /* enable the events from EXTI line x */
211 void exti_event_enable(exti_line_enum linex);
212 /* disable the interrupts from EXTI line x */
213 void exti_interrupt_disable(exti_line_enum linex);
214 /* disable the events from EXTI line x */
215 void exti_event_disable(exti_line_enum linex);
216
217 /* get EXTI lines pending flag */
218 FlagStatus exti_flag_get(exti_line_enum linex);
219 /* clear EXTI lines pending flag */
220 void exti_flag_clear(exti_line_enum linex);
221 /* get EXTI lines flag when the interrupt flag is set */
222 FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
223 /* clear EXTI lines pending flag */
224 void exti_interrupt_flag_clear(exti_line_enum linex);
225 /* enable the EXTI software interrupt event */
226 void exti_software_interrupt_enable(exti_line_enum linex);
227 /* disable the EXTI software interrupt event */
228 void exti_software_interrupt_disable(exti_line_enum linex);
229
230 #endif /* GD32F10X_EXTI_H */
EXTI_2
Definition: gd32f10x_exti.h:168
EXTI_INTERRUPT
Definition: gd32f10x_exti.h:191
EXTI_10
Definition: gd32f10x_exti.h:176
EXTI_19
Definition: gd32f10x_exti.h:185
exti_interrupt_flag_clear
void exti_interrupt_flag_clear(exti_line_enum linex)
clear EXTI lines pending flag
Definition: gd32f10x_exti.c:199
EXTI_16
Definition: gd32f10x_exti.h:182
EXTI_6
Definition: gd32f10x_exti.h:172
exti_mode_enum
exti_mode_enum
Definition: gd32f10x_exti.h:189
EXTI_5
Definition: gd32f10x_exti.h:171
EXTI_15
Definition: gd32f10x_exti.h:181
EXTI_4
Definition: gd32f10x_exti.h:170
exti_line_enum
exti_line_enum
Definition: gd32f10x_exti.h:164
EXTI_TRIG_FALLING
Definition: gd32f10x_exti.h:199
EXTI_11
Definition: gd32f10x_exti.h:177
EXTI_TRIG_BOTH
Definition: gd32f10x_exti.h:200
exti_event_enable
void exti_event_enable(exti_line_enum linex)
enable the events from EXTI line x
Definition: gd32f10x_exti.c:108
EXTI_TRIG_RISING
Definition: gd32f10x_exti.h:198
EXTI_9
Definition: gd32f10x_exti.h:175
EXTI_18
Definition: gd32f10x_exti.h:184
exti_event_disable
void exti_event_disable(exti_line_enum linex)
disable the events from EXTI line x
Definition: gd32f10x_exti.c:134
EXTI_8
Definition: gd32f10x_exti.h:174
EXTI_3
Definition: gd32f10x_exti.h:169
EXTI_0
Definition: gd32f10x_exti.h:166
EXTI_14
Definition: gd32f10x_exti.h:180
exti_flag_clear
void exti_flag_clear(exti_line_enum linex)
clear EXTI lines pending flag
Definition: gd32f10x_exti.c:164
EXTI_7
Definition: gd32f10x_exti.h:173
EXTI_13
Definition: gd32f10x_exti.h:179
EXTI_17
Definition: gd32f10x_exti.h:183
exti_interrupt_flag_get
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
get EXTI lines flag when the interrupt flag is set
Definition: gd32f10x_exti.c:177
EXTI_12
Definition: gd32f10x_exti.h:178
EXTI_1
Definition: gd32f10x_exti.h:167
exti_interrupt_enable
void exti_interrupt_enable(exti_line_enum linex)
enable the interrupts from EXTI line x
Definition: gd32f10x_exti.c:95
exti_software_interrupt_enable
void exti_software_interrupt_enable(exti_line_enum linex)
enable EXTI software interrupt event
Definition: gd32f10x_exti.c:212
exti_init
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
initialize the EXTI
Definition: gd32f10x_exti.c:48
exti_trig_type_enum
exti_trig_type_enum
Definition: gd32f10x_exti.h:196
exti_interrupt_disable
void exti_interrupt_disable(exti_line_enum linex)
disable the interrupt from EXTI line x
Definition: gd32f10x_exti.c:121
EXTI_EVENT
Definition: gd32f10x_exti.h:192
exti_software_interrupt_disable
void exti_software_interrupt_disable(exti_line_enum linex)
disable EXTI software interrupt event
Definition: gd32f10x_exti.c:225
exti_flag_get
FlagStatus exti_flag_get(exti_line_enum linex)
get EXTI lines flag
Definition: gd32f10x_exti.c:147
exti_deinit
void exti_deinit(void)
deinitialize the EXTI
Definition: gd32f10x_exti.c:21
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_i2c.c
Go to the documentation of this file.
1
7 /*
8 Copyright (C) 2017 GigaDevice
9
10 2014-12-26, V1.0.0, firmware for GD32F10x
11 2017-06-20, V2.0.0, firmware for GD32F10x
12 */
13
14 #include "gd32f10x_i2c.h"
15
16 #define I2CCLK_MAX 0x3FU
17 #define I2C_FLAG_MASK 0x0000FFFFU
25 void i2c_deinit(uint32_t i2c_periph)
26 {
27 switch(i2c_periph){
28 case I2C0:
29 rcu_periph_reset_enable(RCU_I2C0RST);
30 rcu_periph_reset_disable(RCU_I2C0RST);
31 break;
32 case I2C1:
33 rcu_periph_reset_enable(RCU_I2C1RST);
34 rcu_periph_reset_disable(RCU_I2C1RST);
35 break;
36 default:
37 break;
38 }
39 }
40
51 void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
52 {
53 uint32_t pclk1,clkc,freq,risetime;
54 uint32_t temp;
55
56 pclk1 = rcu_clock_freq_get(CK_APB1);
57 /* I2C peripheral clock frequency */
58 freq = (uint32_t)(pclk1/1000000U);
59 if(freq >= I2CCLK_MAX){
60 freq = I2CCLK_MAX;
61 }
62 temp = I2C_CTL1(i2c_periph);
63 temp &= ~I2C_CTL1_I2CCLK;
64 temp |= freq;
65
66 I2C_CTL1(i2c_periph) = temp;
67
68 if(100000U >= clkspeed){
69 /* the maximum SCL rise time is 1000ns in standard mode */
70 risetime = (uint32_t)((pclk1/1000000U)+1U);
71 if(risetime >= I2CCLK_MAX){
72 I2C_RT(i2c_periph) = I2CCLK_MAX;
73 }else{
74 I2C_RT(i2c_periph) = risetime;
75 }
76 clkc = (uint32_t)(pclk1/(clkspeed*2U));
77 if(clkc < 0x04U){
78 /* the CLKC in standard mode minmum value is 4 */
79 clkc = 0x04U;
80 }
81 I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
82
83 }else if(400000U >= clkspeed){
84 /* the maximum SCL rise time is 300ns in fast mode */
85 I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
86 if(I2C_DTCY_2 == dutycyc){
87 /* I2C duty cycle is 2 */
88 clkc = (uint32_t)(pclk1/(clkspeed*3U));
89 I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
90 }else{
91 /* I2C duty cycle is 16/9 */
92 clkc = (uint32_t)(pclk1/(clkspeed*25U));
93 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
94 }
95 if(0U == (clkc & I2C_CKCFG_CLKC)){
96 /* the CLKC in fast mode minmum value is 1 */
97 clkc |= 0x0001U;
98 }
99 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
100 I2C_CKCFG(i2c_periph) |= clkc;
101 }else{
102 }
103 }
104
118 void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
119 {
120 /* SMBus/I2C mode selected */
121 uint32_t ctl = 0U;
122 ctl = I2C_CTL0(i2c_periph);
123 ctl &= ~(I2C_CTL0_SMBEN);
124 ctl |= mode;
125 I2C_CTL0(i2c_periph) = ctl;
126 /* configure address */
127 I2C_SADDR0(i2c_periph) = (addformat | addr);
128 }
129
139 void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
140 {
141 if(I2C_SMBUS_HOST == type){
142 I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
143 }else{
144 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
145 }
146 }
147
157 void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
158 {
159 if(I2C_ACK_ENABLE == ack){
160 I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
161 }else{
162 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
163 }
164 }
165
175 void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
176 {
177 /* configure I2C POAP position */
178 if(I2C_ACKPOS_NEXT == pos){
179 I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
180 }else{
181 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
182 }
183 }
184
195 void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
196 {
197 if(I2C_TRANSMITTER == trandirection){
198 addr = addr & I2C_TRANSMITTER;
199 }else{
200 addr = addr | I2C_RECEIVER;
201 }
202 I2C_DATA(i2c_periph) = addr;
203 }
204
214 void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr)
215 {
216 if(I2C_DUADEN_ENABLE == dualaddr){
217 I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
218 }else{
219 I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
220 }
221 }
222
229 void i2c_enable(uint32_t i2c_periph)
230 {
231 I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
232 }
233
240 void i2c_disable(uint32_t i2c_periph)
241 {
242 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
243 }
244
251 void i2c_start_on_bus(uint32_t i2c_periph)
252 {
253 I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
254 }
255
262 void i2c_stop_on_bus(uint32_t i2c_periph)
263 {
264 I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
265 }
266
274 void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
275 {
276 I2C_DATA(i2c_periph) = DATA_TRANS(data);
277 }
278
285 uint8_t i2c_data_receive(uint32_t i2c_periph)
286 {
287 return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
288 }
289
299 void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
300 {
301 /* configure I2C DMA function */
302 uint32_t ctl = 0U;
303 ctl = I2C_CTL1(i2c_periph);
304 ctl &= ~(I2C_CTL1_DMAON);
305 ctl |= dmastate;
306 I2C_CTL1(i2c_periph) = ctl;
307 }
308
318 void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast)
319 {
320 /* configure DMA last transfer */
321 uint32_t ctl = 0U;
322 ctl = I2C_CTL1(i2c_periph);
323 ctl &= ~(I2C_CTL1_DMALST);
324 ctl |= dmalast;
325 I2C_CTL1(i2c_periph) = ctl;
326 }
327
337 void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
338 {
339 /* configure I2C SCL strerching enable or disable */
340 uint32_t ctl = 0U;
341 ctl = I2C_CTL0(i2c_periph);
342 ctl &= ~(I2C_CTL0_DISSTRC);
343 ctl |= stretchpara;
344 I2C_CTL0(i2c_periph) = ctl;
345 }
346
356 void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
357 {
358 /* configure slave response to a general call enable or disable */
359 uint32_t ctl = 0U;
360 ctl = I2C_CTL0(i2c_periph);
361 ctl &= ~(I2C_CTL0_GCEN);
362 ctl |= gcallpara;
363 I2C_CTL0(i2c_periph) = ctl;
364 }
365
375 void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
376 {
377 /* modify CTL0 and configure software reset I2C state */
378 uint32_t ctl = 0U;
379 ctl = I2C_CTL0(i2c_periph);
380 ctl &= ~(I2C_CTL0_SRESET);
381 ctl |= sreset;
382 I2C_CTL0(i2c_periph) = ctl;
383 }
384
413 FlagStatus i2c_flag_get(uint32_t i2c_periph,uint32_t flag )
414 {
415 uint32_t reg = 0U;
416 FlagStatus reval = RESET;
417 /* get the flag in which register */
418 reg = (BIT(31) & flag);
419 if((BIT(31) == reg)){
420 if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){
421 reval = SET;
422 }else{
423 reval = RESET;
424 }
425 }else{
426 if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){
427 reval = SET;
428 }else{
429 reval = RESET;
430 }
431 }
432 /* return the flag status */
433 return reval;
434 }
435
451 void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag)
452 {
453 if(I2C_FLAG_ADDSEND == flag){
454 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
455 I2C_STAT0(i2c_periph);
456 I2C_STAT1(i2c_periph);
457 }else{
458 I2C_STAT0(i2c_periph) &= ~(flag);
459 }
460 }
461
472 void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
473 {
474 I2C_CTL1(i2c_periph) |= (inttype);
475 }
476
487 void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
488 {
489 I2C_CTL1(i2c_periph) &= ~(inttype);
490 }
491
513 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
514 {
515 uint32_t evie, errie, bufie;
516
517 evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE;
518 errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE;
519 /* check I2C event interrupt enable bit */
520 if((intflag&0x00ffU) && evie){
521 if(intflag&0x001fU){
522 /* check I2C event flags except TBE and RBNE */
523 if(intflag & I2C_STAT0(i2c_periph)){
524 return SET;
525 }else{
526 return RESET;
527 }
528 }else{
529 /* check I2C event flags TBE and RBNE */
530 bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
531 if(bufie){
532 if(intflag & I2C_STAT0(i2c_periph)){
533 return SET;
534 }else{
535 return RESET;
536 }
537 }else{
538 return RESET;
539 }
540 }
541 /* check I2C error interrupt enable bit */
542 }else if((intflag&0xff00U) && errie){
543 /* check I2C error flags */
544 if(intflag & I2C_STAT0(i2c_periph)){
545 return SET;
546 }else{
547 return RESET;
548 }
549 }else{
550 return RESET;
551 }
552 }
553
569 void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag)
570 {
571 if(I2C_INT_FLAG_ADDSEND == intflag){
572 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
573 I2C_STAT0(i2c_periph);
574 I2C_STAT1(i2c_periph);
575 }else{
576 I2C_STAT0(i2c_periph) &= ~(intflag);
577 }
578 }
579
589 void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
590 {
591 /* on/off PEC calculation */
592 uint32_t ctl = 0U;
593 ctl = I2C_CTL0(i2c_periph);
594 ctl &= ~(I2C_CTL0_PECEN);
595 ctl |= pecstate;
596 I2C_CTL0(i2c_periph) = ctl;
597 }
598
608 void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
609 {
610 /* whether to transfer PEC */
611 uint32_t ctl = 0U;
612 ctl = I2C_CTL0(i2c_periph);
613 ctl &= ~(I2C_CTL0_PECTRANS);
614 ctl |= pecpara;
615 I2C_CTL0(i2c_periph) = ctl;
616 }
617
624 uint8_t i2c_pec_value_get(uint32_t i2c_periph)
625 {
626 return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>8);
627 }
628
638 void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
639 {
640 /* issue alert through SMBA pin configure*/
641 uint32_t ctl = 0U;
642 ctl = I2C_CTL0(i2c_periph);
643 ctl &= ~(I2C_CTL0_SALT);
644 ctl |= smbuspara;
645 I2C_CTL0(i2c_periph) = ctl;
646 }
647
657 void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
658 {
659 /* enable or disable I2C ARP protocol*/
660 uint32_t ctl = 0U;
661 ctl = I2C_CTL0(i2c_periph);
662 ctl &= ~(I2C_CTL0_ARPEN);
663 ctl |= arpstate;
664 I2C_CTL0(i2c_periph) = ctl;
665 }
I2C_CTL1_DMAON
#define I2C_CTL1_DMAON
Definition: gd32f10x_i2c.h:55
i2c_dma_enable
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
enable I2C DMA mode
Definition: gd32f10x_i2c.c:299
RCU_I2C0RST
Definition: gd32f10x_rcu.h:463
i2c_interrupt_enable
void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
enable I2C interrupt
Definition: gd32f10x_i2c.c:472
DATA_TRANS
#define DATA_TRANS(regval)
Definition: gd32f10x_i2c.h:168
I2C_DTCY_2
#define I2C_DTCY_2
Definition: gd32f10x_i2c.h:219
i2c_enable
void i2c_enable(uint32_t i2c_periph)
enable I2C
Definition: gd32f10x_i2c.c:229
I2C_CKCFG_DTCY
#define I2C_CKCFG_DTCY
Definition: gd32f10x_i2c.h:99
I2C_CTL0_STOP
#define I2C_CTL0_STOP
Definition: gd32f10x_i2c.h:43
i2c_dualaddr_enable
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr)
dual-address mode switch
Definition: gd32f10x_i2c.c:214
i2c_stop_on_bus
void i2c_stop_on_bus(uint32_t i2c_periph)
generate a STOP condition on I2C bus
Definition: gd32f10x_i2c.c:262
RCU_I2C1RST
Definition: gd32f10x_rcu.h:464
i2c_pec_transfer_enable
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
I2C whether to transfer PEC value.
Definition: gd32f10x_i2c.c:608
I2C_ACKPOS_NEXT
#define I2C_ACKPOS_NEXT
Definition: gd32f10x_i2c.h:122
i2c_interrupt_flag_get
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
check I2C interrupt flag
Definition: gd32f10x_i2c.c:513
I2C_CTL0_SMBEN
#define I2C_CTL0_SMBEN
Definition: gd32f10x_i2c.h:36
i2c_master_addressing
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
master send slave address
Definition: gd32f10x_i2c.c:195
i2c_start_on_bus
void i2c_start_on_bus(uint32_t i2c_periph)
generate a START condition on I2C bus
Definition: gd32f10x_i2c.c:251
i2c_slave_response_to_gcall_config
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
whether or not to response to a general call
Definition: gd32f10x_i2c.c:356
I2C_CTL0_START
#define I2C_CTL0_START
Definition: gd32f10x_i2c.h:42
gd32f10x_i2c.h
definitions for the I2C
I2C_CTL1_ERRIE
#define I2C_CTL1_ERRIE
Definition: gd32f10x_i2c.h:52
I2C_RECEIVER
#define I2C_RECEIVER
Definition: gd32f10x_i2c.h:114
I2C_SMBUS_HOST
#define I2C_SMBUS_HOST
Definition: gd32f10x_i2c.h:112
I2C_CTL0_DISSTRC
#define I2C_CTL0_DISSTRC
Definition: gd32f10x_i2c.h:41
i2c_data_transmit
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
I2C transmit data function.
Definition: gd32f10x_i2c.c:274
I2C_SADDR0
#define I2C_SADDR0(i2cx)
Definition: gd32f10x_i2c.h:25
I2C_CKCFG_FAST
#define I2C_CKCFG_FAST
Definition: gd32f10x_i2c.h:100
i2c_smbus_type_config
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
SMBus type selection.
Definition: gd32f10x_i2c.c:139
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f10x_i2c.h:29
i2c_interrupt_flag_clear
void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag)
clear I2C interrupt flag
Definition: gd32f10x_i2c.c:569
I2C_FLAG_ADDSEND
#define I2C_FLAG_ADDSEND
Definition: gd32f10x_i2c.h:175
I2C_CTL0_ACKEN
#define I2C_CTL0_ACKEN
Definition: gd32f10x_i2c.h:44
i2c_interrupt_disable
void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
disable I2C interrupt
Definition: gd32f10x_i2c.c:487
i2c_stretch_scl_low_config
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
whether to stretch SCL low when data is not ready in slave mode
Definition: gd32f10x_i2c.c:337
I2C_CTL0_ARPEN
#define I2C_CTL0_ARPEN
Definition: gd32f10x_i2c.h:38
i2c_flag_get
FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
check I2C flag is set or not
Definition: gd32f10x_i2c.c:413
i2c_mode_addr_config
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
configure I2C address
Definition: gd32f10x_i2c.c:118
i2c_dma_last_transfer_enable
void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast)
flag indicating DMA last transfer
Definition: gd32f10x_i2c.c:318
I2C_CTL0_SALT
#define I2C_CTL0_SALT
Definition: gd32f10x_i2c.h:47
I2C_CTL1_BUFIE
#define I2C_CTL1_BUFIE
Definition: gd32f10x_i2c.h:54
I2C_INT_FLAG_ADDSEND
#define I2C_INT_FLAG_ADDSEND
Definition: gd32f10x_i2c.h:198
I2C_STAT1_ECV
#define I2C_STAT1_ECV
Definition: gd32f10x_i2c.h:95
I2C_CKCFG_CLKC
#define I2C_CKCFG_CLKC
Definition: gd32f10x_i2c.h:98
i2c_flag_clear
void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag)
clear I2C flag
Definition: gd32f10x_i2c.c:451
I2C1
#define I2C1
Definition: gd32f10x_i2c.h:20
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f10x_i2c.h:27
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f10x_rcu.c:1039
I2C0
#define I2C0
Definition: gd32f10x_i2c.h:19
I2C_SADDR1_DUADEN
#define I2C_SADDR1_DUADEN
Definition: gd32f10x_i2c.h:65
i2c_pec_enable
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
I2C PEC calculation on or off.
Definition: gd32f10x_i2c.c:589
i2c_software_reset_config
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
software reset I2C
Definition: gd32f10x_i2c.c:375
I2C_CTL0_SMBSEL
#define I2C_CTL0_SMBSEL
Definition: gd32f10x_i2c.h:37
I2C_ACK_ENABLE
#define I2C_ACK_ENABLE
Definition: gd32f10x_i2c.h:119
DATA_RECV
#define DATA_RECV(regval)
Definition: gd32f10x_i2c.h:171
I2C_CTL1_EVIE
#define I2C_CTL1_EVIE
Definition: gd32f10x_i2c.h:53
I2C_RT
#define I2C_RT(i2cx)
Definition: gd32f10x_i2c.h:31
I2C_SADDR1
#define I2C_SADDR1(i2cx)
Definition: gd32f10x_i2c.h:26
i2c_smbus_issue_alert
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
I2C issue alert through SMBA pin.
Definition: gd32f10x_i2c.c:638
I2C_CTL0_GCEN
#define I2C_CTL0_GCEN
Definition: gd32f10x_i2c.h:40
I2C_CTL0_SRESET
#define I2C_CTL0_SRESET
Definition: gd32f10x_i2c.h:48
i2c_clock_config
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
I2C clock configure.
Definition: gd32f10x_i2c.c:51
I2C_CTL1_I2CCLK
#define I2C_CTL1_I2CCLK
Definition: gd32f10x_i2c.h:51
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
I2C_CKCFG
#define I2C_CKCFG(i2cx)
Definition: gd32f10x_i2c.h:30
I2C_DUADEN_ENABLE
#define I2C_DUADEN_ENABLE
Definition: gd32f10x_i2c.h:127
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f10x_i2c.h:24
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
I2C_TRANSMITTER
#define I2C_TRANSMITTER
Definition: gd32f10x_i2c.h:115
i2c_smbus_arp_enable
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
enable or disable I2C ARP protocol in SMBus switch
Definition: gd32f10x_i2c.c:657
i2c_disable
void i2c_disable(uint32_t i2c_periph)
disable I2C
Definition: gd32f10x_i2c.c:240
i2c_ackpos_config
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
I2C POAP position configure.
Definition: gd32f10x_i2c.c:175
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: gd32f10x_i2c.c:17
I2C_CTL0_PECTRANS
#define I2C_CTL0_PECTRANS
Definition: gd32f10x_i2c.h:46
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f10x_i2c.h:23
I2CCLK_MAX
#define I2CCLK_MAX
Definition: gd32f10x_i2c.c:16
i2c_data_receive
uint8_t i2c_data_receive(uint32_t i2c_periph)
I2C receive data function.
Definition: gd32f10x_i2c.c:285
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f10x_i2c.h:35
CK_APB1
Definition: gd32f10x_rcu.h:586
I2C_CTL0_PECEN
#define I2C_CTL0_PECEN
Definition: gd32f10x_i2c.h:39
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f10x_i2c.h:28
i2c_pec_value_get
uint8_t i2c_pec_value_get(uint32_t i2c_periph)
get packet error checking value
Definition: gd32f10x_i2c.c:624
I2C_CTL0_POAP
#define I2C_CTL0_POAP
Definition: gd32f10x_i2c.h:45
I2C_CTL1_DMALST
#define I2C_CTL1_DMALST
Definition: gd32f10x_i2c.h:56
i2c_ack_config
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
whether or not to send an ACK
Definition: gd32f10x_i2c.c:157
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_wwdgt.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_WWDGT_H
14 #define GD32F10X_WWDGT_H
15
16 #include "gd32f10x.h"
17
18 /* WWDGT definitions */
19 #define WWDGT WWDGT_BASE
21 /* registers definitions */
22 #define WWDGT_CTL REG32((WWDGT) + 0x00U)
23 #define WWDGT_CFG REG32((WWDGT) + 0x04U)
24 #define WWDGT_STAT REG32((WWDGT) + 0x08U)
26 /* bits definitions */
27 /* WWDGT_CTL */
28 #define WWDGT_CTL_CNT BITS(0,6)
29 #define WWDGT_CTL_WDGTEN BIT(7)
31 /* WWDGT_CFG */
32 #define WWDGT_CFG_WIN BITS(0,6)
33 #define WWDGT_CFG_PSC BITS(7,8)
34 #define WWDGT_CFG_EWIE BIT(9)
36 /* WWDGT_STAT */
37 #define WWDGT_STAT_EWIF BIT(0)
39 /* constants definitions */
40 #define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7))
41 #define WWDGT_CFG_PSC_DIV1 CFG_PSC(0)
42 #define WWDGT_CFG_PSC_DIV2 CFG_PSC(1)
43 #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2)
44 #define WWDGT_CFG_PSC_DIV8 CFG_PSC(3)
46 /* function declarations */
47 /* reset the window watchdog timer configuration */
48 void wwdgt_deinit(void);
49 /* start the window watchdog timer counter */
50 void wwdgt_enable(void);
51
52 /* configure the window watchdog timer counter value */
53 void wwdgt_counter_update(uint16_t counter_value);
54 /* configure counter value, window value, and prescaler divider value */
55 void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
56
57 /* enable early wakeup interrupt of WWDGT */
58 void wwdgt_interrupt_enable(void);
59 /* check early wakeup interrupt state of WWDGT */
60 FlagStatus wwdgt_flag_get(void);
61 /* clear early wakeup interrupt state of WWDGT */
62 void wwdgt_flag_clear(void);
63
64 #endif /* GD32F10X_WWDGT_H */
wwdgt_flag_get
FlagStatus wwdgt_flag_get(void)
check early wakeup interrupt state of WWDGT
Definition: gd32f10x_wwdgt.c:105
wwdgt_deinit
void wwdgt_deinit(void)
reset the window watchdog timer configuration
Definition: gd32f10x_wwdgt.c:26
wwdgt_interrupt_enable
void wwdgt_interrupt_enable(void)
enable early wakeup interrupt of WWDGT
Definition: gd32f10x_wwdgt.c:94
wwdgt_counter_update
void wwdgt_counter_update(uint16_t counter_value)
configure the window watchdog timer counter value
Definition: gd32f10x_wwdgt.c:38
wwdgt_config
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
configure counter value, window value, and prescaler divider value
Definition: gd32f10x_wwdgt.c:71
wwdgt_flag_clear
void wwdgt_flag_clear(void)
clear early wakeup interrupt state of WWDGT
Definition: gd32f10x_wwdgt.c:120
wwdgt_enable
void wwdgt_enable(void)
start the window watchdog timer counter
Definition: gd32f10x_wwdgt.c:54
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_dac.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_dac.h"
14
21 void dac_deinit(void)
22 {
23 rcu_periph_reset_enable(RCU_DACRST);
24 rcu_periph_reset_disable(RCU_DACRST);
25 }
26
34 void dac_enable(uint32_t dac_periph)
35 {
36 if(DAC0 == dac_periph){
37 DAC_CTL |= DAC_CTL_DEN0;
38 }else{
39 DAC_CTL |= DAC_CTL_DEN1;
40 }
41 }
42
50 void dac_disable(uint32_t dac_periph)
51 {
52 if(DAC0 == dac_periph){
53 DAC_CTL &= ~DAC_CTL_DEN0;
54 }else{
55 DAC_CTL &= ~DAC_CTL_DEN1;
56 }
57 }
58
66 void dac_dma_enable(uint32_t dac_periph)
67 {
68 if(DAC0 == dac_periph){
69 DAC_CTL |= DAC_CTL_DDMAEN0;
70 }else{
71 DAC_CTL |= DAC_CTL_DDMAEN1;
72 }
73 }
74
82 void dac_dma_disable(uint32_t dac_periph)
83 {
84 if(DAC0 == dac_periph){
85 DAC_CTL &= ~DAC_CTL_DDMAEN0;
86 }else{
87 DAC_CTL &= ~DAC_CTL_DDMAEN1;
88 }
89 }
90
98 void dac_output_buffer_enable(uint32_t dac_periph)
99 {
100 if(DAC0 == dac_periph){
101 DAC_CTL &= ~DAC_CTL_DBOFF0;
102 }else{
103 DAC_CTL &= ~DAC_CTL_DBOFF1;
104 }
105 }
106
114 void dac_output_buffer_disable(uint32_t dac_periph)
115 {
116 if(DAC0 == dac_periph){
117 DAC_CTL |= DAC_CTL_DBOFF0;
118 }else{
119 DAC_CTL |= DAC_CTL_DBOFF1;
120 }
121 }
122
130 void dac_trigger_enable(uint32_t dac_periph)
131 {
132 if(DAC0 == dac_periph){
133 DAC_CTL |= DAC_CTL_DTEN0;
134 }else{
135 DAC_CTL |= DAC_CTL_DTEN1;
136 }
137 }
138
146 void dac_trigger_disable(uint32_t dac_periph)
147 {
148 if(DAC0 == dac_periph){
149 DAC_CTL &= ~DAC_CTL_DTEN0;
150 }else{
151 DAC_CTL &= ~DAC_CTL_DTEN1;
152 }
153 }
154
161 void dac_software_trigger_enable(uint32_t dac_periph)
162 {
163 if(DAC0 == dac_periph){
164 DAC_SWT |= DAC_SWT_SWTR0;
165 }else{
166 DAC_SWT |= DAC_SWT_SWTR1;
167 }
168 }
169
177 void dac_software_trigger_disable(uint32_t dac_periph)
178 {
179 if(DAC0 == dac_periph){
180 DAC_SWT &= ~DAC_SWT_SWTR0;
181 }else{
182 DAC_SWT &= ~DAC_SWT_SWTR1;
183 }
184 }
185
203 void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource)
204 {
205 if(DAC0 == dac_periph){
206 DAC_CTL &= ~DAC_CTL_DTSEL0;
207 DAC_CTL |= triggersource;
208 }else{
209 DAC_CTL &= ~DAC_CTL_DTSEL1;
210 DAC_CTL |= (triggersource << 16);
211 }
212 }
213
225 void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
226 {
227 if(DAC0 == dac_periph){
228 DAC_CTL &= ~DAC_CTL_DWM0;
229 DAC_CTL |= wave_mode;
230 }else{
231 DAC_CTL &= ~DAC_CTL_DWM1;
232 DAC_CTL |= wave_mode << 16;
233 }
234 }
235
256 void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
257 {
258 if(DAC0 == dac_periph){
259 DAC_CTL &= ~DAC_CTL_DWBW0;
260 DAC_CTL |= bit_width;
261 }else{
262 DAC_CTL &= ~DAC_CTL_DWBW1;
263 DAC_CTL |= bit_width << 16;
264 }
265 }
266
287 void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
288 {
289 if(DAC0 == dac_periph){
290 DAC_CTL &= ~DAC_CTL_DWBW0;
291 DAC_CTL |= unmask_bits;
292 }else{
293 DAC_CTL &= ~DAC_CTL_DWBW1;
294 DAC_CTL |= unmask_bits << 16;
295 }
296 }
297
318 void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
319 {
320 if(DAC0 == dac_periph){
321 DAC_CTL &= ~DAC_CTL_DWBW0;
322 DAC_CTL |= amplitude;
323 }else{
324 DAC_CTL &= ~DAC_CTL_DWBW1;
325 DAC_CTL |= amplitude << 16;
326 }
327 }
328
336 uint16_t dac_output_value_get(uint32_t dac_periph)
337 {
338 uint16_t data = 0U;
339 if(DAC0 == dac_periph){
340 data = (uint16_t)DAC0_DO;
341 }else{
342 data = (uint16_t)DAC1_DO;
343 }
344 return data;
345 }
346
353 void dac_concurrent_enable(void)
354 {
355 uint32_t ctl = 0U;
356 ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
357 DAC_CTL |= (ctl);
358 }
359
366 void dac_concurrent_disable(void)
367 {
368 uint32_t ctl = 0U;
369 ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
370 DAC_CTL &= (~ctl);
371 }
372
379 void dac_concurrent_software_trigger_enable(void)
380 {
381 uint32_t swt = 0U;
382 swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
383 DAC_SWT |= (swt);
384 }
385
392 void dac_concurrent_software_trigger_disable(void)
393 {
394 uint32_t swt = 0U;
395 swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
396 DAC_SWT &= (~swt);
397 }
398
405 void dac_concurrent_output_buffer_enable(void)
406 {
407 uint32_t ctl = 0U;
408 ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
409 DAC_CTL &= (~ctl);
410 }
411
418 void dac_concurrent_output_buffer_disable(void)
419 {
420 uint32_t ctl = 0U;
421 ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
422 DAC_CTL |= (ctl);
423 }
424
437 void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
438 {
439 if(DAC0 == dac_periph){
440 switch(dac_align){
441 /* data right 12b alignment */
442 case DAC_ALIGN_12B_R:
443 DAC0_R12DH = data;
444 break;
445 /* data left 12b alignment */
446 case DAC_ALIGN_12B_L:
447 DAC0_L12DH = data;
448 break;
449 /* data right 8b alignment */
450 case DAC_ALIGN_8B_R:
451 DAC0_R8DH = data;
452 break;
453 default:
454 break;
455 }
456 }else{
457 switch(dac_align){
458 /* data right 12b alignment */
459 case DAC_ALIGN_12B_R:
460 DAC1_R12DH = data;
461 break;
462 /* data left 12b alignment */
463 case DAC_ALIGN_12B_L:
464 DAC1_L12DH = data;
465 break;
466 /* data right 8b alignment */
467 case DAC_ALIGN_8B_R:
468 DAC1_R8DH = data;
469 break;
470 default:
471 break;
472 }
473 }
474 }
475
487 void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
488 {
489 uint32_t data = 0U;
490 switch(dac_align){
491 /* data right 12b alignment */
492 case DAC_ALIGN_12B_R:
493 data = ((uint32_t)data1 << 16) | data0;
494 DACC_R12DH = data;
495 break;
496 /* data left 12b alignment */
497 case DAC_ALIGN_12B_L:
498 data = ((uint32_t)data1 << 16) | data0;
499 DACC_L12DH = data;
500 break;
501 /* data right 8b alignment */
502 case DAC_ALIGN_8B_R:
503 data = ((uint32_t)data1 << 8) | data0;
504 DACC_R8DH = data;
505 break;
506 default:
507 break;
508 }
509 }
dac_trigger_disable
void dac_trigger_disable(uint32_t dac_periph)
disable DAC trigger
Definition: gd32f10x_dac.c:146
DACC_L12DH
#define DACC_L12DH
Definition: gd32f10x_dac.h:33
dac_concurrent_output_buffer_disable
void dac_concurrent_output_buffer_disable(void)
disable DAC concurrent buffer function
Definition: gd32f10x_dac.c:418
DAC_CTL_DBOFF1
#define DAC_CTL_DBOFF1
Definition: gd32f10x_dac.h:48
DACC_R12DH
#define DACC_R12DH
Definition: gd32f10x_dac.h:32
dac_disable
void dac_disable(uint32_t dac_periph)
disable DAC
Definition: gd32f10x_dac.c:50
DAC_CTL_DTEN0
#define DAC_CTL_DTEN0
Definition: gd32f10x_dac.h:42
dac_output_value_get
uint16_t dac_output_value_get(uint32_t dac_periph)
get DAC output value
Definition: gd32f10x_dac.c:336
DAC0_DO
#define DAC0_DO
Definition: gd32f10x_dac.h:35
DAC_CTL_DTSEL1
#define DAC_CTL_DTSEL1
Definition: gd32f10x_dac.h:50
DACC_R8DH
#define DACC_R8DH
Definition: gd32f10x_dac.h:34
DAC_ALIGN_12B_R
#define DAC_ALIGN_12B_R
Definition: gd32f10x_dac.h:162
dac_concurrent_output_buffer_enable
void dac_concurrent_output_buffer_enable(void)
enable DAC concurrent buffer function
Definition: gd32f10x_dac.c:405
DAC1_DO
#define DAC1_DO
Definition: gd32f10x_dac.h:36
DAC1_R8DH
#define DAC1_R8DH
Definition: gd32f10x_dac.h:31
DAC_CTL_DEN1
#define DAC_CTL_DEN1
Definition: gd32f10x_dac.h:47
dac_output_buffer_enable
void dac_output_buffer_enable(uint32_t dac_periph)
enable DAC output buffer
Definition: gd32f10x_dac.c:98
dac_wave_bit_width_config
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
configure DAC wave bit width
Definition: gd32f10x_dac.c:256
DAC_CTL_DWM1
#define DAC_CTL_DWM1
Definition: gd32f10x_dac.h:51
dac_output_buffer_disable
void dac_output_buffer_disable(uint32_t dac_periph)
disable DAC output buffer
Definition: gd32f10x_dac.c:114
dac_trigger_enable
void dac_trigger_enable(uint32_t dac_periph)
enable DAC trigger
Definition: gd32f10x_dac.c:130
DAC_CTL_DWM0
#define DAC_CTL_DWM0
Definition: gd32f10x_dac.h:44
DAC_ALIGN_12B_L
#define DAC_ALIGN_12B_L
Definition: gd32f10x_dac.h:163
DAC_ALIGN_8B_R
#define DAC_ALIGN_8B_R
Definition: gd32f10x_dac.h:164
dac_deinit
void dac_deinit(void)
deinitialize DAC
Definition: gd32f10x_dac.c:21
DAC_SWT
#define DAC_SWT
Definition: gd32f10x_dac.h:25
DAC0_R8DH
#define DAC0_R8DH
Definition: gd32f10x_dac.h:28
DAC_SWT_SWTR0
#define DAC_SWT_SWTR0
Definition: gd32f10x_dac.h:56
dac_software_trigger_enable
void dac_software_trigger_enable(uint32_t dac_periph)
enable DAC software trigger
Definition: gd32f10x_dac.c:161
dac_concurrent_software_trigger_enable
void dac_concurrent_software_trigger_enable(void)
enable DAC concurrent software trigger function
Definition: gd32f10x_dac.c:379
dac_data_set
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
set the DAC specified data holding register value
Definition: gd32f10x_dac.c:437
dac_lfsr_noise_config
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
configure DAC LFSR noise mode
Definition: gd32f10x_dac.c:287
RCU_DACRST
Definition: gd32f10x_rcu.h:474
dac_concurrent_data_set
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
set DAC concurrent mode data holding register value
Definition: gd32f10x_dac.c:487
DAC_CTL_DDMAEN0
#define DAC_CTL_DDMAEN0
Definition: gd32f10x_dac.h:46
dac_dma_disable
void dac_dma_disable(uint32_t dac_periph)
disable DAC DMA function
Definition: gd32f10x_dac.c:82
dac_enable
void dac_enable(uint32_t dac_periph)
enable DAC
Definition: gd32f10x_dac.c:34
dac_trigger_source_config
void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource)
set DAC trigger source
Definition: gd32f10x_dac.c:203
gd32f10x_dac.h
definitions for the DAC
dac_wave_mode_config
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
configure DAC wave mode
Definition: gd32f10x_dac.c:225
DAC_CTL_DTSEL0
#define DAC_CTL_DTSEL0
Definition: gd32f10x_dac.h:43
dac_software_trigger_disable
void dac_software_trigger_disable(uint32_t dac_periph)
disable DAC software trigger
Definition: gd32f10x_dac.c:177
DAC_CTL_DWBW1
#define DAC_CTL_DWBW1
Definition: gd32f10x_dac.h:52
dac_triangle_noise_config
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
configure DAC triangle noise mode
Definition: gd32f10x_dac.c:318
DAC0_L12DH
#define DAC0_L12DH
Definition: gd32f10x_dac.h:27
dac_concurrent_software_trigger_disable
void dac_concurrent_software_trigger_disable(void)
disable DAC concurrent software trigger function
Definition: gd32f10x_dac.c:392
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
dac_dma_enable
void dac_dma_enable(uint32_t dac_periph)
enable DAC DMA function
Definition: gd32f10x_dac.c:66
dac_concurrent_enable
void dac_concurrent_enable(void)
enable DAC concurrent mode
Definition: gd32f10x_dac.c:353
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
DAC1_R12DH
#define DAC1_R12DH
Definition: gd32f10x_dac.h:29
DAC_CTL_DEN0
#define DAC_CTL_DEN0
Definition: gd32f10x_dac.h:40
DAC0_R12DH
#define DAC0_R12DH
Definition: gd32f10x_dac.h:26
DAC_CTL
#define DAC_CTL
Definition: gd32f10x_dac.h:24
DAC_CTL_DDMAEN1
#define DAC_CTL_DDMAEN1
Definition: gd32f10x_dac.h:53
DAC_CTL_DBOFF0
#define DAC_CTL_DBOFF0
Definition: gd32f10x_dac.h:41
dac_concurrent_disable
void dac_concurrent_disable(void)
disable DAC concurrent mode
Definition: gd32f10x_dac.c:366
DAC1_L12DH
#define DAC1_L12DH
Definition: gd32f10x_dac.h:30
DAC_CTL_DWBW0
#define DAC_CTL_DWBW0
Definition: gd32f10x_dac.h:45
DAC0
#define DAC0
Definition: gd32f10x_dac.h:20
DAC_SWT_SWTR1
#define DAC_SWT_SWTR1
Definition: gd32f10x_dac.h:57
DAC_CTL_DTEN1
#define DAC_CTL_DTEN1
Definition: gd32f10x_dac.h:49
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Include
gd32f10x_bkp.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef GD32F10X_BKP_H
14 #define GD32F10X_BKP_H
15
16 #include "gd32f10x.h"
17
18 /* BKP definitions */
19 #define BKP BKP_BASE
21 /* registers definitions */
22 #define BKP_DATA0 REG16((BKP) + 0x04U)
23 #define BKP_DATA1 REG16((BKP) + 0x08U)
24 #define BKP_DATA2 REG16((BKP) + 0x0CU)
25 #define BKP_DATA3 REG16((BKP) + 0x10U)
26 #define BKP_DATA4 REG16((BKP) + 0x14U)
27 #define BKP_DATA5 REG16((BKP) + 0x18U)
28 #define BKP_DATA6 REG16((BKP) + 0x1CU)
29 #define BKP_DATA7 REG16((BKP) + 0x20U)
30 #define BKP_DATA8 REG16((BKP) + 0x24U)
31 #define BKP_DATA9 REG16((BKP) + 0x28U)
32 #define BKP_DATA10 REG16((BKP) + 0x40U)
33 #define BKP_DATA11 REG16((BKP) + 0x44U)
34 #define BKP_DATA12 REG16((BKP) + 0x48U)
35 #define BKP_DATA13 REG16((BKP) + 0x4CU)
36 #define BKP_DATA14 REG16((BKP) + 0x50U)
37 #define BKP_DATA15 REG16((BKP) + 0x54U)
38 #define BKP_DATA16 REG16((BKP) + 0x58U)
39 #define BKP_DATA17 REG16((BKP) + 0x5CU)
40 #define BKP_DATA18 REG16((BKP) + 0x60U)
41 #define BKP_DATA19 REG16((BKP) + 0x64U)
42 #define BKP_DATA20 REG16((BKP) + 0x68U)
43 #define BKP_DATA21 REG16((BKP) + 0x6CU)
44 #define BKP_DATA22 REG16((BKP) + 0x70U)
45 #define BKP_DATA23 REG16((BKP) + 0x74U)
46 #define BKP_DATA24 REG16((BKP) + 0x78U)
47 #define BKP_DATA25 REG16((BKP) + 0x7CU)
48 #define BKP_DATA26 REG16((BKP) + 0x80U)
49 #define BKP_DATA27 REG16((BKP) + 0x84U)
50 #define BKP_DATA28 REG16((BKP) + 0x88U)
51 #define BKP_DATA29 REG16((BKP) + 0x8CU)
52 #define BKP_DATA30 REG16((BKP) + 0x90U)
53 #define BKP_DATA31 REG16((BKP) + 0x94U)
54 #define BKP_DATA32 REG16((BKP) + 0x98U)
55 #define BKP_DATA33 REG16((BKP) + 0x9CU)
56 #define BKP_DATA34 REG16((BKP) + 0xA0U)
57 #define BKP_DATA35 REG16((BKP) + 0xA4U)
58 #define BKP_DATA36 REG16((BKP) + 0xA8U)
59 #define BKP_DATA37 REG16((BKP) + 0xACU)
60 #define BKP_DATA38 REG16((BKP) + 0xB0U)
61 #define BKP_DATA39 REG16((BKP) + 0xB4U)
62 #define BKP_DATA40 REG16((BKP) + 0xB8U)
63 #define BKP_DATA41 REG16((BKP) + 0xBCU)
64 #define BKP_OCTL REG16((BKP) + 0x2CU)
65 #define BKP_TPCTL REG16((BKP) + 0x30U)
66 #define BKP_TPCS REG16((BKP) + 0x34U)
68 /* bits definitions */
69 /* BKP_DATA */
70 #define BKP_DATA BITS(0,15)
72 /* BKP_OCTL */
73 #define BKP_OCTL_RCCV BITS(0,6)
74 #define BKP_OCTL_COEN BIT(7)
75 #define BKP_OCTL_ASOEN BIT(8)
76 #define BKP_OCTL_ROSEL BIT(9)
78 /* BKP_TPCTL */
79 #define BKP_TPCTL_TPEN BIT(0)
80 #define BKP_TPCTL_TPAL BIT(1)
82 /* BKP_TPCS */
83 #define BKP_TPCS_TER BIT(0)
84 #define BKP_TPCS_TIR BIT(1)
85 #define BKP_TPCS_TPIE BIT(2)
86 #define BKP_TPCS_TEF BIT(8)
87 #define BKP_TPCS_TIF BIT(9)
89 /* constants definitions */
90 /* BKP register */
91 #define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U)
92 #define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
93
94 /* get data of BKP data register */
95 #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15)
96
97 /* RTC clock calibration value */
98 #define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
99
100 /* RTC output selection */
101 #define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U)
102 #define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U)
104 /* tamper pin active level */
105 #define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U)
106 #define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U)
108 /* tamper flag */
109 #define BKP_FLAG_TAMPER BKP_TPCS_TEF
111 /* tamper interrupt flag */
112 #define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF
114 /* BKP data register number */
115 typedef enum
116 {
117 BKP_DATA_0 = 1,
118 BKP_DATA_1,
119 BKP_DATA_2,
120 BKP_DATA_3,
121 BKP_DATA_4,
122 BKP_DATA_5,
123 BKP_DATA_6,
124 BKP_DATA_7,
125 BKP_DATA_8,
126 BKP_DATA_9,
127 BKP_DATA_10,
128 BKP_DATA_11,
129 BKP_DATA_12,
130 BKP_DATA_13,
131 BKP_DATA_14,
132 BKP_DATA_15,
133 BKP_DATA_16,
134 BKP_DATA_17,
135 BKP_DATA_18,
136 BKP_DATA_19,
137 BKP_DATA_20,
138 BKP_DATA_21,
139 BKP_DATA_22,
140 BKP_DATA_23,
141 BKP_DATA_24,
142 BKP_DATA_25,
143 BKP_DATA_26,
144 BKP_DATA_27,
145 BKP_DATA_28,
146 BKP_DATA_29,
147 BKP_DATA_30,
148 BKP_DATA_31,
149 BKP_DATA_32,
150 BKP_DATA_33,
151 BKP_DATA_34,
152 BKP_DATA_35,
153 BKP_DATA_36,
154 BKP_DATA_37,
155 BKP_DATA_38,
156 BKP_DATA_39,
157 BKP_DATA_40,
158 BKP_DATA_41,
159 }bkp_data_register_enum;
160
161 /* function declarations */
162 /* reset BKP registers */
163 void bkp_deinit(void);
164 /* write BKP data register */
165 void bkp_write_data(bkp_data_register_enum register_number, uint16_t data);
166 /* read BKP data register */
167 uint16_t bkp_read_data(bkp_data_register_enum register_number);
168
169 /* RTC related functions */
170 /* enable RTC clock calibration output */
171 void bkp_rtc_calibration_output_enable(void);
172 /* disable RTC clock calibration output */
173 void bkp_rtc_calibration_output_disable(void);
174 /* enable RTC alarm or second signal output */
175 void bkp_rtc_signal_output_enable(void);
176 /* disable RTC alarm or second signal output */
177 void bkp_rtc_signal_output_disable(void);
178 /* RTC output selection */
179 void bkp_rtc_output_select(uint16_t outputsel);
180 /* set RTC clock calibration value */
181 void bkp_rtc_calibration_value_set(uint8_t value);
182
183 /* tamper pin related functions */
184 /* enable tamper pin detection */
185 void bkp_tamper_detection_enable(void);
186 /* disable tamper pin detection */
187 void bkp_tamper_detection_disable(void);
188 /* set tamper pin active level */
189 void bkp_tamper_active_level_set(uint16_t level);
190 /* enable tamper pin interrupt */
191 void bkp_tamper_interrupt_enable(void);
192 /* disable tamper pin interrupt */
193 void bkp_tamper_interrupt_disable(void);
194
195 /* flag functions */
196 /* get BKP flag state */
197 FlagStatus bkp_flag_get(uint16_t flag);
198 /* clear BKP flag state */
199 void bkp_flag_clear(uint16_t flag);
200 /* get BKP interrupt flag state */
201 FlagStatus bkp_interrupt_flag_get(uint16_t flag);
202 /* clear BKP interrupt flag state */
203 void bkp_interrupt_flag_clear(uint16_t flag);
204
205 #endif /* GD32F10X_BKP_H */
BKP_DATA_33
Definition: gd32f10x_bkp.h:150
BKP_DATA_22
Definition: gd32f10x_bkp.h:139
bkp_rtc_signal_output_disable
void bkp_rtc_signal_output_disable(void)
disable RTC alarm or second signal output
Definition: gd32f10x_bkp.c:110
BKP_DATA_29
Definition: gd32f10x_bkp.h:146
bkp_rtc_output_select
void bkp_rtc_output_select(uint16_t outputsel)
select RTC output
Definition: gd32f10x_bkp.c:123
BKP_DATA_5
Definition: gd32f10x_bkp.h:122
BKP_DATA_36
Definition: gd32f10x_bkp.h:153
BKP_DATA_30
Definition: gd32f10x_bkp.h:147
BKP_DATA_4
Definition: gd32f10x_bkp.h:121
BKP_DATA_17
Definition: gd32f10x_bkp.h:134
BKP_DATA_24
Definition: gd32f10x_bkp.h:141
BKP_DATA_8
Definition: gd32f10x_bkp.h:125
BKP_DATA_1
Definition: gd32f10x_bkp.h:118
BKP_DATA_13
Definition: gd32f10x_bkp.h:130
bkp_rtc_calibration_value_set
void bkp_rtc_calibration_value_set(uint8_t value)
set RTC clock calibration value
Definition: gd32f10x_bkp.c:140
BKP_DATA_19
Definition: gd32f10x_bkp.h:136
bkp_tamper_detection_disable
void bkp_tamper_detection_disable(void)
disable tamper detection
Definition: gd32f10x_bkp.c:167
BKP_DATA_34
Definition: gd32f10x_bkp.h:151
BKP_DATA_6
Definition: gd32f10x_bkp.h:123
BKP_DATA_20
Definition: gd32f10x_bkp.h:137
BKP_DATA_9
Definition: gd32f10x_bkp.h:126
bkp_tamper_interrupt_enable
void bkp_tamper_interrupt_enable(void)
enable tamper interrupt
Definition: gd32f10x_bkp.c:196
BKP_DATA_35
Definition: gd32f10x_bkp.h:152
BKP_DATA_37
Definition: gd32f10x_bkp.h:154
BKP_DATA_27
Definition: gd32f10x_bkp.h:144
BKP_DATA_2
Definition: gd32f10x_bkp.h:119
BKP_DATA_12
Definition: gd32f10x_bkp.h:129
bkp_tamper_interrupt_disable
void bkp_tamper_interrupt_disable(void)
disable tamper interrupt
Definition: gd32f10x_bkp.c:207
BKP_DATA_32
Definition: gd32f10x_bkp.h:149
bkp_rtc_calibration_output_enable
void bkp_rtc_calibration_output_enable(void)
enable RTC clock calibration output
Definition: gd32f10x_bkp.c:77
BKP_DATA_40
Definition: gd32f10x_bkp.h:157
bkp_data_register_enum
bkp_data_register_enum
Definition: gd32f10x_bkp.h:115
bkp_rtc_signal_output_enable
void bkp_rtc_signal_output_enable(void)
enable RTC alarm or second signal output
Definition: gd32f10x_bkp.c:99
BKP_DATA_31
Definition: gd32f10x_bkp.h:148
BKP_DATA_38
Definition: gd32f10x_bkp.h:155
bkp_deinit
void bkp_deinit(void)
reset BKP registers
Definition: gd32f10x_bkp.c:23
BKP_DATA_26
Definition: gd32f10x_bkp.h:143
bkp_read_data
uint16_t bkp_read_data(bkp_data_register_enum register_number)
read BKP data register
Definition: gd32f10x_bkp.c:56
BKP_DATA_25
Definition: gd32f10x_bkp.h:142
BKP_DATA_14
Definition: gd32f10x_bkp.h:131
BKP_DATA_41
Definition: gd32f10x_bkp.h:158
BKP_DATA_11
Definition: gd32f10x_bkp.h:128
bkp_rtc_calibration_output_disable
void bkp_rtc_calibration_output_disable(void)
disable RTC clock calibration output
Definition: gd32f10x_bkp.c:88
BKP_DATA_23
Definition: gd32f10x_bkp.h:140
bkp_write_data
void bkp_write_data(bkp_data_register_enum register_number, uint16_t data)
write BKP data register
Definition: gd32f10x_bkp.c:38
bkp_flag_clear
void bkp_flag_clear(uint16_t flag)
clear bkp flag state
Definition: gd32f10x_bkp.c:235
bkp_flag_get
FlagStatus bkp_flag_get(uint16_t flag)
get bkp flag state
Definition: gd32f10x_bkp.c:219
BKP_DATA_15
Definition: gd32f10x_bkp.h:132
bkp_tamper_active_level_set
void bkp_tamper_active_level_set(uint16_t level)
set tamper pin active level
Definition: gd32f10x_bkp.c:180
BKP_DATA_21
Definition: gd32f10x_bkp.h:138
BKP_DATA_3
Definition: gd32f10x_bkp.h:120
bkp_interrupt_flag_clear
void bkp_interrupt_flag_clear(uint16_t flag)
clear bkp interrupt flag state
Definition: gd32f10x_bkp.c:263
BKP_DATA_18
Definition: gd32f10x_bkp.h:135
BKP_DATA_28
Definition: gd32f10x_bkp.h:145
bkp_interrupt_flag_get
FlagStatus bkp_interrupt_flag_get(uint16_t flag)
get bkp interrupt flag state
Definition: gd32f10x_bkp.c:247
BKP_DATA_7
Definition: gd32f10x_bkp.h:124
BKP_DATA_10
Definition: gd32f10x_bkp.h:127
BKP_DATA_39
Definition: gd32f10x_bkp.h:156
bkp_tamper_detection_enable
void bkp_tamper_detection_enable(void)
enable tamper detection
Definition: gd32f10x_bkp.c:156
BKP_DATA_16
Definition: gd32f10x_bkp.h:133
BKP_DATA_0
Definition: gd32f10x_bkp.h:117
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_usbfs_driver/Include/usbd_std.h Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_usbfs_driver
  • Include
usbd_std.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #ifndef USBD_STD_H
14 #define USBD_STD_H
15
16 #include "usb_std.h"
17 #include "usbd_core.h"
18 #include "usbd_conf.h"
19 #include <wchar.h>
20
21 #define USBD_LANGID_STR_IDX 0x00U
22 #define USBD_MFC_STR_IDX 0x01U
23 #define USBD_PRODUCT_STR_IDX 0x02U
24 #define USBD_SERIAL_STR_IDX 0x03U
25 #define USBD_CONFIG_STR_IDX 0x04U
26 #define USBD_INTERFACE_STR_IDX 0x05U
28 #define USB_STATUS_REMOTE_WAKEUP 0x02U
29 #define USB_STATUS_SELF_POWERED 0x01U
31 #define USB_FEATURE_ENDP_HALT 0x00U
32 #define USB_FEATURE_REMOTE_WAKEUP 0x01U
33 #define USB_FEATURE_TEST_MODE 0x02U
35 #define ENG_LANGID 0x0409U
36 #define CHN_LANGID 0x0804U
38 #define USB_DEVICE_DESC_SIZE 0x12U
40 #define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU))
41 #define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))
43 #define USB_MIN(a, b) (((a) < (b)) ? (a) : (b))
45 #define WIDE_STRING(string) _WIDE_STRING(string)
46 #define _WIDE_STRING(string) L##string
47
48 #define USBD_STRING_DESC(string) \
49 (uint8_t *)&(struct { \
50 uint8_t _len; \
51 uint8_t _type; \
52 wchar_t _data[sizeof(string)]; \
53 }) { \
54 sizeof(WIDE_STRING(string)) + 2U - 2U, \
55 USB_DESCTYPE_STRING, \
56 WIDE_STRING(string) \
57 }
58
59 #define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))
60
61 /* function declarations */
62 /* USB device setup transaction*/
63 usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev);
64 /* USB device out transaction*/
65 usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
66 /* USB device in transaction*/
67 usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
68 /* USB device enum error handle*/
69 void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req);
70
71 #endif /* USBD_STD_H */
usb_device_req_struct
Definition: usbd_core.h:115
usbd_in_transaction
uint8_t usbd_in_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data in stage processing
Definition: usbd_std.c:155
usbd_core.h
usbd_setup_transaction
uint8_t usbd_setup_transaction(usbd_core_handle_struct *pudev)
USB setup stage processing.
Definition: usbd_std.c:80
usb_core_handle_struct
Definition: usb_core.h:201
usbd_enum_error
void usbd_enum_error(usbd_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB enumeration error event
Definition: usbd_std.c:832
usbd_status_enum
usbd_status_enum
Definition: usbd_core.h:82
usbd_out_transaction
uint8_t usbd_out_transaction(usbd_core_handle_struct *pudev, uint8_t ep_num)
data out stage processing
Definition: usbd_std.c:113
usb_std.h
USB 2.0 standard defines.
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_adc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_adc.h"
14
22 void adc_deinit(uint32_t adc_periph)
23 {
24 switch(adc_periph){
25 case ADC0:
26 rcu_periph_reset_enable(RCU_ADC0RST);
27 rcu_periph_reset_disable(RCU_ADC0RST);
28 break;
29 case ADC1:
30 rcu_periph_reset_enable(RCU_ADC1RST);
31 rcu_periph_reset_disable(RCU_ADC1RST);
32 break;
33 #ifndef GD32F10X_CL
34 case ADC2:
35 rcu_periph_reset_enable(RCU_ADC2RST);
36 rcu_periph_reset_disable(RCU_ADC2RST);
37 break;
38 #endif /* GD32F10X_CL */
39 default:
40 break;
41 }
42 }
43
51 void adc_enable(uint32_t adc_periph)
52 {
53 if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
54 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
55 }
56 }
57
65 void adc_disable(uint32_t adc_periph)
66 {
67 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
68 }
69
77 void adc_calibration_enable(uint32_t adc_periph)
78 {
79 /* reset the selected ADC1 calibration registers */
80 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
81 /* check the RSTCLB bit state */
82 while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
83 }
84 /* enable ADC calibration process */
85 ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
86 /* check the CLB bit state */
87 while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
88 }
89 }
90
98 void adc_dma_mode_enable(uint32_t adc_periph)
99 {
100 ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
101 }
102
110 void adc_dma_mode_disable(uint32_t adc_periph)
111 {
112 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
113 }
114
121 void adc_tempsensor_vrefint_enable(void)
122 {
123 /* enable the temperature sensor and Vrefint channel */
124 ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
125 }
126
133 void adc_tempsensor_vrefint_disable(void)
134 {
135 /* disable the temperature sensor and Vrefint channel */
136 ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
137 }
138
153 void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
154 {
155 ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC ));
156 switch(adc_channel_group){
157 case ADC_REGULAR_CHANNEL:
158 /* config the number of conversions in discontinuous mode */
159 ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
160 ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U));
161
162 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
163 break;
164 case ADC_INSERTED_CHANNEL:
165 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
166 break;
167 case ADC_CHANNEL_DISCON_DISABLE:
168 default:
169 break;
170 }
171 }
172
190 void adc_mode_config(uint32_t mode)
191 {
192 ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
193 ADC_CTL0(ADC0) |= mode;
194 }
195
209 void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue)
210 {
211 if(newvalue){
212 if(0U != (function & ADC_SCAN_MODE)){
213 ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
214 }
215 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
216 ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
217 }
218 if(0U != (function & ADC_CONTINUOUS_MODE)){
219 ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
220 }
221 }else{
222 if(0U != (function & ADC_SCAN_MODE)){
223 ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
224 }
225 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
226 ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
227 }
228 if(0U != (function & ADC_CONTINUOUS_MODE)){
229 ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
230 }
231 }
232 }
233
245 void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment)
246 {
247 if(ADC_DATAALIGN_RIGHT != data_alignment){
248 ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
249 }else{
250 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
251 }
252 }
253
268 void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
269 {
270 switch(adc_channel_group){
271 case ADC_REGULAR_CHANNEL:
272 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
273 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U));
274
275 break;
276 case ADC_INSERTED_CHANNEL:
277 ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
278 ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-1U));
279
280 break;
281 default:
282 break;
283 }
284 }
285
307 void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time)
308 {
309 uint32_t rsq,sampt;
310
311 /* ADC regular sequence config */
312 if(rank < 6U){
313 rsq = ADC_RSQ2(adc_periph);
314 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
315 rsq |= ((uint32_t)adc_channel << (5U*rank));
316 ADC_RSQ2(adc_periph) = rsq;
317 }else if(rank < 12U){
318 rsq = ADC_RSQ1(adc_periph);
319 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
320 rsq |= ((uint32_t)adc_channel << (5U*(rank-6U)));
321 ADC_RSQ1(adc_periph) = rsq;
322 }else if(rank < 16U){
323 rsq = ADC_RSQ0(adc_periph);
324 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
325 rsq |= ((uint32_t)adc_channel << (5U*(rank-12U)));
326 ADC_RSQ0(adc_periph) = rsq;
327 }else{
328 }
329
330 /* ADC sampling time config */
331 if(adc_channel < 10U){
332 sampt = ADC_SAMPT1(adc_periph);
333 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
334 sampt |= (uint32_t)(sample_time << (3U*adc_channel));
335 ADC_SAMPT1(adc_periph) = sampt;
336 }else if(adc_channel < 18U){
337 sampt = ADC_SAMPT0(adc_periph);
338 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
339 sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U)));
340 ADC_SAMPT0(adc_periph) = sampt;
341 }else{
342 }
343 }
344
366 void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time)
367 {
368 uint8_t inserted_length;
369 uint32_t isq,sampt;
370
371 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
372
373 isq = ADC_ISQ(adc_periph);
374 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U-(inserted_length-rank)*5U)));
375 isq |= ((uint32_t)adc_channel << (15U-(inserted_length-rank)*5U));
376 ADC_ISQ(adc_periph) = isq;
377
378 /* ADC sampling time config */
379 if(adc_channel < 10U){
380 sampt = ADC_SAMPT1(adc_periph);
381 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
382 sampt |= (uint32_t) sample_time << (3U*adc_channel);
383 ADC_SAMPT1(adc_periph) = sampt;
384 }else if(adc_channel < 18U){
385 sampt = ADC_SAMPT0(adc_periph);
386 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
387 sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U)));
388 ADC_SAMPT0(adc_periph) = sampt;
389 }else{
390 }
391 }
392
407 void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset)
408 {
409 uint8_t inserted_length;
410 uint32_t num = 0U;
411
412 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
413 num = 3U - (inserted_length - inserted_channel);
414
415 if(num <= 3U){
416 /* calculate the offset of the register */
417 num = num * 4U;
418 /* config the offset of the selected channels */
419 REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
420 }
421 }
422
435 void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
436 {
437 if(newvalue){
438 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
439 ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
440 }
441 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
442 ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
443 }
444 }else{
445 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
446 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
447 }
448 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
449 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
450 }
451 }
452 }
453
501 void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
502 {
503 switch(adc_channel_group){
504 case ADC_REGULAR_CHANNEL:
505 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
506 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
507 break;
508 case ADC_INSERTED_CHANNEL:
509 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
510 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
511 break;
512 default:
513 break;
514 }
515 }
516
528 void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group)
529 {
530 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
531 ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
532 }
533 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
534 ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
535 }
536 }
537
545 FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
546 {
547 FlagStatus reval = RESET;
548 if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){
549 reval = SET;
550 }
551 return reval;
552 }
553
561 FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
562 {
563 FlagStatus reval = RESET;
564 if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){
565 reval = SET;
566 }
567 return reval;
568 }
569
578 uint16_t adc_regular_data_read(uint32_t adc_periph)
579 {
580 return (uint16_t)(ADC_RDATA(adc_periph));
581 }
582
596 uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel)
597 {
598 uint32_t idata;
599 /* read the data of the selected channel */
600 switch(inserted_channel){
601 case ADC_INSERTED_CHANNEL_0:
602 idata = ADC_IDATA0(adc_periph);
603 break;
604 case ADC_INSERTED_CHANNEL_1:
605 idata = ADC_IDATA1(adc_periph);
606 break;
607 case ADC_INSERTED_CHANNEL_2:
608 idata = ADC_IDATA2(adc_periph);
609 break;
610 case ADC_INSERTED_CHANNEL_3:
611 idata = ADC_IDATA3(adc_periph);
612 break;
613 default:
614 idata = 0U;
615 break;
616 }
617 return (uint16_t)idata;
618 }
619
626 uint32_t adc_sync_mode_convert_value_read(void)
627 {
628 /* return conversion value */
629 return ADC_RDATA(ADC0);
630 }
631
646 FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag)
647 {
648 FlagStatus reval = RESET;
649 if(ADC_STAT(adc_periph) & adc_flag){
650 reval = SET;
651 }
652 return reval;
653 }
654
669 void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag)
670 {
671 ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
672 }
673
686 FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt)
687 {
688 FlagStatus interrupt_flag = RESET;
689 uint32_t state;
690 /* check the interrupt bits */
691 switch(adc_interrupt){
692 case ADC_INT_WDE:
693 state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
694 if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
695 interrupt_flag = SET;
696 }
697 break;
698 case ADC_INT_EOC:
699 state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
700 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
701 interrupt_flag = SET;
702 }
703 break;
704 case ADC_INT_EOIC:
705 state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
706 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
707 interrupt_flag = SET;
708 }
709 break;
710 default:
711 break;
712 }
713 return interrupt_flag;
714 }
715
728 void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt)
729 {
730 ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
731 }
732
745 void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt)
746 {
747 if(0U != (adc_interrupt & ADC_INT_WDE)){
748 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
749 }
750
751 if(0U != (adc_interrupt & ADC_INT_EOC)){
752 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
753 }
754
755 if(0U != (adc_interrupt & ADC_INT_EOIC)){
756 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
757 }
758 }
759
772 void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
773 {
774 if(0U != (adc_interrupt & ADC_INT_WDE)){
775 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
776 }
777
778 if(0U != (adc_interrupt & ADC_INT_EOC)){
779 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
780 }
781
782 if(0U != (adc_interrupt & ADC_INT_EOIC)){
783 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
784 }
785 }
786
797 void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
798 {
799 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
800
801 ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
802 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
803 }
804
817 void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
818 {
819 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
820 /* select the group */
821 switch(adc_channel_group){
822 case ADC_REGULAR_CHANNEL:
823 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
824 break;
825 case ADC_INSERTED_CHANNEL:
826 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
827 break;
828 case ADC_REGULAR_INSERTED_CHANNEL:
829 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
830 break;
831 default:
832 break;
833 }
834 }
835
843 void adc_watchdog_disable(uint32_t adc_periph)
844 {
845 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
846 }
847
857 void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold)
858 {
859 ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
860 ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
861 }
ADC_CONTINUOUS_MODE
#define ADC_CONTINUOUS_MODE
Definition: gd32f10x_adc.h:143
adc_interrupt_flag_get
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
get the ADC interrupt bits
Definition: gd32f10x_adc.c:686
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f10x_adc.h:82
adc_inserted_channel_offset_config
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
configure ADC inserted channel offset
Definition: gd32f10x_adc.c:407
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f10x_adc.h:59
gd32f10x_adc.h
definitions for the ADC
ADC_INSERTED_CHANNEL_1
#define ADC_INSERTED_CHANNEL_1
Definition: gd32f10x_adc.h:218
adc_inserted_data_read
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
read ADC inserted group data register
Definition: gd32f10x_adc.c:596
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f10x_adc.h:57
ADC_CTL0_DISIC
#define ADC_CTL0_DISIC
Definition: gd32f10x_adc.h:62
adc_calibration_enable
void adc_calibration_enable(uint32_t adc_periph)
ADC calibration and reset calibration.
Definition: gd32f10x_adc.c:77
adc_external_trigger_source_config
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
configure ADC external trigger source
Definition: gd32f10x_adc.c:501
RSQ0_RL
#define RSQ0_RL(regval)
Definition: gd32f10x_adc.h:204
adc_external_trigger_config
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
enable ADC external trigger
Definition: gd32f10x_adc.c:435
ADC_CTL1_ETSIC
#define ADC_CTL1_ETSIC
Definition: gd32f10x_adc.h:76
ADC_RSQ0_RL
#define ADC_RSQ0_RL
Definition: gd32f10x_adc.h:98
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f10x_adc.h:65
ADC_CTL1
#define ADC_CTL1(adcx)
Definition: gd32f10x_adc.h:26
ADC_ISQ_IL
#define ADC_ISQ_IL
Definition: gd32f10x_adc.h:102
ADC1
#define ADC1
Definition: gd32f10x_adc.h:20
ADC_SAMPT0
#define ADC_SAMPT0(adcx)
Definition: gd32f10x_adc.h:27
adc_dma_mode_disable
void adc_dma_mode_disable(uint32_t adc_periph)
disable DMA request
Definition: gd32f10x_adc.c:110
RCU_ADC0RST
Definition: gd32f10x_rcu.h:485
ADC_IDATA0
#define ADC_IDATA0(adcx)
Definition: gd32f10x_adc.h:39
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:211
adc_interrupt_disable
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
disable ADC interrupt
Definition: gd32f10x_adc.c:772
adc_software_trigger_enable
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
enable ADC software trigger
Definition: gd32f10x_adc.c:528
adc_disable
void adc_disable(uint32_t adc_periph)
disable ADC interface
Definition: gd32f10x_adc.c:65
adc_watchdog_disable
void adc_watchdog_disable(uint32_t adc_periph)
disable ADC analog watchdog
Definition: gd32f10x_adc.c:843
adc_tempsensor_vrefint_enable
void adc_tempsensor_vrefint_enable(void)
enable the temperature sensor and Vrefint channel
Definition: gd32f10x_adc.c:121
ADC_ISQ
#define ADC_ISQ(adcx)
Definition: gd32f10x_adc.h:38
ADC_STAT_EOC
#define ADC_STAT_EOC
Definition: gd32f10x_adc.h:48
adc_flag_clear
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
clear the ADC flag bits
Definition: gd32f10x_adc.c:669
adc_watchdog_single_channel_enable
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
configure ADC analog watchdog single channel
Definition: gd32f10x_adc.c:797
adc_enable
void adc_enable(uint32_t adc_periph)
enable ADC interface
Definition: gd32f10x_adc.c:51
adc_flag_get
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
get the ADC flag bits
Definition: gd32f10x_adc.c:646
ADC_CTL0_DISRC
#define ADC_CTL0_DISRC
Definition: gd32f10x_adc.h:61
ISQ_IL
#define ISQ_IL(regval)
Definition: gd32f10x_adc.h:207
ADC_SAMPT1
#define ADC_SAMPT1(adcx)
Definition: gd32f10x_adc.h:28
ADC_INSERTED_CHANNEL_AUTO
#define ADC_INSERTED_CHANNEL_AUTO
Definition: gd32f10x_adc.h:125
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f10x_adc.h:70
ADC_STAT_EOIC
#define ADC_STAT_EOIC
Definition: gd32f10x_adc.h:49
ADC_STAT
#define ADC_STAT(adcx)
Definition: gd32f10x_adc.h:24
ADC_WDLT
#define ADC_WDLT(adcx)
Definition: gd32f10x_adc.h:34
adc_inserted_channel_config
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
configure ADC inserted channel
Definition: gd32f10x_adc.c:366
ADC_RSQ2
#define ADC_RSQ2(adcx)
Definition: gd32f10x_adc.h:37
ADC_CTL1_SWRCST
#define ADC_CTL1_SWRCST
Definition: gd32f10x_adc.h:81
adc_regular_channel_config
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
configure ADC regular channel
Definition: gd32f10x_adc.c:307
ADC_CTL0_DISNUM
#define ADC_CTL0_DISNUM
Definition: gd32f10x_adc.h:63
ADC_RDATA
#define ADC_RDATA(adcx)
Definition: gd32f10x_adc.h:43
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f10x_adc.h:54
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f10x_adc.h:245
adc_data_alignment_config
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
configure ADC data alignment
Definition: gd32f10x_adc.c:245
adc_regular_software_startconv_flag_get
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
get the bit state of ADCx software start conversion
Definition: gd32f10x_adc.c:545
ADC_CTL1_SWICST
#define ADC_CTL1_SWICST
Definition: gd32f10x_adc.h:80
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f10x_adc.h:85
ADC_STAT_WDE
#define ADC_STAT_WDE
Definition: gd32f10x_adc.h:47
ADC_CTL1_DAL
#define ADC_CTL1_DAL
Definition: gd32f10x_adc.h:75
ADC_SCAN_MODE
#define ADC_SCAN_MODE
Definition: gd32f10x_adc.h:123
adc_special_function_config
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
enable or disable ADC special function
Definition: gd32f10x_adc.c:209
ADC_IDATA1
#define ADC_IDATA1(adcx)
Definition: gd32f10x_adc.h:40
adc_regular_data_read
uint16_t adc_regular_data_read(uint32_t adc_periph)
read ADC regular group data register
Definition: gd32f10x_adc.c:578
adc_interrupt_flag_clear
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
clear the ADC flag
Definition: gd32f10x_adc.c:728
ADC_CTL1_RSTCLB
#define ADC_CTL1_RSTCLB
Definition: gd32f10x_adc.h:73
ADC_CTL0_SYNCM
#define ADC_CTL0_SYNCM
Definition: gd32f10x_adc.h:64
adc_interrupt_enable
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
enable ADC interrupt
Definition: gd32f10x_adc.c:745
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
ADC_RSQ0
#define ADC_RSQ0(adcx)
Definition: gd32f10x_adc.h:35
adc_dma_mode_enable
void adc_dma_mode_enable(uint32_t adc_periph)
enable DMA request
Definition: gd32f10x_adc.c:98
adc_tempsensor_vrefint_disable
void adc_tempsensor_vrefint_disable(void)
disable the temperature sensor and Vrefint channel
Definition: gd32f10x_adc.c:133
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f10x_adc.h:244
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
adc_channel_length_config
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
configure the length of regular channel group or inserted channel group
Definition: gd32f10x_adc.c:268
ADC_CTL0
#define ADC_CTL0(adcx)
Definition: gd32f10x_adc.h:25
ADC_RSQ1
#define ADC_RSQ1(adcx)
Definition: gd32f10x_adc.h:36
adc_sync_mode_convert_value_read
uint32_t adc_sync_mode_convert_value_read(void)
read the last ADC0 and ADC1 conversion result data in sync mode
Definition: gd32f10x_adc.c:626
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f10x_adc.h:243
adc_inserted_software_startconv_flag_get
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
get the bit state of ADCx software inserted channel start conversion
Definition: gd32f10x_adc.c:561
ADC_INSERTED_CHANNEL_2
#define ADC_INSERTED_CHANNEL_2
Definition: gd32f10x_adc.h:219
adc_watchdog_threshold_config
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
configure ADC analog watchdog threshold
Definition: gd32f10x_adc.c:857
WDLT_WDLT
#define WDLT_WDLT(regval)
Definition: gd32f10x_adc.h:201
ADC_CTL1_CLB
#define ADC_CTL1_CLB
Definition: gd32f10x_adc.h:72
ADC_REGULAR_INSERTED_CHANNEL
#define ADC_REGULAR_INSERTED_CHANNEL
Definition: gd32f10x_adc.h:212
ADC_CTL1_ETEIC
#define ADC_CTL1_ETEIC
Definition: gd32f10x_adc.h:77
ADC_CHANNEL_DISCON_DISABLE
#define ADC_CHANNEL_DISCON_DISABLE
Definition: gd32f10x_adc.h:214
adc_discontinuous_mode_config
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
configure ADC discontinuous mode
Definition: gd32f10x_adc.c:153
CTL0_DISNUM
#define CTL0_DISNUM(regval)
Definition: gd32f10x_adc.h:121
adc_deinit
void adc_deinit(uint32_t adc_periph)
reset ADC
Definition: gd32f10x_adc.c:22
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f10x_adc.h:66
ADC_ISQ_ISQN
#define ADC_ISQ_ISQN
Definition: gd32f10x_adc.h:101
ADC_DATAALIGN_RIGHT
#define ADC_DATAALIGN_RIGHT
Definition: gd32f10x_adc.h:140
ADC_WDHT
#define ADC_WDHT(adcx)
Definition: gd32f10x_adc.h:33
ADC_CTL1_ETSRC
#define ADC_CTL1_ETSRC
Definition: gd32f10x_adc.h:78
ADC_IDATA2
#define ADC_IDATA2(adcx)
Definition: gd32f10x_adc.h:41
RCU_ADC1RST
Definition: gd32f10x_rcu.h:486
adc_watchdog_group_channel_enable
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
configure ADC analog watchdog group channel
Definition: gd32f10x_adc.c:817
ADC_INSERTED_CHANNEL_3
#define ADC_INSERTED_CHANNEL_3
Definition: gd32f10x_adc.h:220
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f10x_adc.h:210
ADC_RSQX_RSQN
#define ADC_RSQX_RSQN
Definition: gd32f10x_adc.h:97
WDHT_WDHT
#define WDHT_WDHT(regval)
Definition: gd32f10x_adc.h:198
ADC_IDATA3
#define ADC_IDATA3(adcx)
Definition: gd32f10x_adc.h:42
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f10x_adc.h:55
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f10x_adc.h:56
ADC_INSERTED_CHANNEL_0
#define ADC_INSERTED_CHANNEL_0
Definition: gd32f10x_adc.h:217
ADC_CTL1_ETERC
#define ADC_CTL1_ETERC
Definition: gd32f10x_adc.h:79
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f10x_adc.h:74
adc_mode_config
void adc_mode_config(uint32_t mode)
configure the ADC sync mode
Definition: gd32f10x_adc.c:190
IOFFX_IOFF
#define IOFFX_IOFF(regval)
Definition: gd32f10x_adc.h:195
ADC2
#define ADC2
Definition: gd32f10x_adc.h:21
ADC0
#define ADC0
Definition: gd32f10x_adc.h:19
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_exti.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_exti.h"
14
21 void exti_deinit(void)
22 {
23 /* reset the value of all the EXTI registers */
24 EXTI_INTEN = (uint32_t)0x00000000U;
25 EXTI_EVEN = (uint32_t)0x00000000U;
26 EXTI_RTEN = (uint32_t)0x00000000U;
27 EXTI_FTEN = (uint32_t)0x00000000U;
28 EXTI_SWIEV = (uint32_t)0x00000000U;
29 }
30
48 void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
49 {
50 /* reset the EXTI line x */
51 EXTI_INTEN &= ~(uint32_t)linex;
52 EXTI_EVEN &= ~(uint32_t)linex;
53 EXTI_RTEN &= ~(uint32_t)linex;
54 EXTI_FTEN &= ~(uint32_t)linex;
55
56 /* set the EXTI mode and enable the interrupts or events from EXTI line x */
57 switch(mode){
58 case EXTI_INTERRUPT:
59 EXTI_INTEN |= (uint32_t)linex;
60 break;
61 case EXTI_EVENT:
62 EXTI_EVEN |= (uint32_t)linex;
63 break;
64 default:
65 break;
66 }
67
68 /* set the EXTI trigger type */
69 switch(trig_type){
70 case EXTI_TRIG_RISING:
71 EXTI_RTEN |= (uint32_t)linex;
72 EXTI_FTEN &= ~(uint32_t)linex;
73 break;
74 case EXTI_TRIG_FALLING:
75 EXTI_RTEN &= ~(uint32_t)linex;
76 EXTI_FTEN |= (uint32_t)linex;
77 break;
78 case EXTI_TRIG_BOTH:
79 EXTI_RTEN |= (uint32_t)linex;
80 EXTI_FTEN |= (uint32_t)linex;
81 break;
82 default:
83 break;
84 }
85 }
86
95 void exti_interrupt_enable(exti_line_enum linex)
96 {
97 EXTI_INTEN |= (uint32_t)linex;
98 }
99
108 void exti_event_enable(exti_line_enum linex)
109 {
110 EXTI_EVEN |= (uint32_t)linex;
111 }
112
121 void exti_interrupt_disable(exti_line_enum linex)
122 {
123 EXTI_INTEN &= ~(uint32_t)linex;
124 }
125
134 void exti_event_disable(exti_line_enum linex)
135 {
136 EXTI_EVEN &= ~(uint32_t)linex;
137 }
138
147 FlagStatus exti_flag_get(exti_line_enum linex)
148 {
149 if(RESET != (EXTI_PD & (uint32_t)linex)){
150 return SET;
151 }else{
152 return RESET;
153 }
154 }
155
164 void exti_flag_clear(exti_line_enum linex)
165 {
166 EXTI_PD = (uint32_t)linex;
167 }
168
177 FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
178 {
179 uint32_t flag_left, flag_right;
180
181 flag_left = EXTI_PD & (uint32_t)linex;
182 flag_right = EXTI_INTEN & (uint32_t)linex;
183
184 if((RESET != flag_left) && (RESET != flag_right)){
185 return SET;
186 }else{
187 return RESET;
188 }
189 }
190
199 void exti_interrupt_flag_clear(exti_line_enum linex)
200 {
201 EXTI_PD = (uint32_t)linex;
202 }
203
212 void exti_software_interrupt_enable(exti_line_enum linex)
213 {
214 EXTI_SWIEV |= (uint32_t)linex;
215 }
216
225 void exti_software_interrupt_disable(exti_line_enum linex)
226 {
227 EXTI_SWIEV &= ~(uint32_t)linex;
228 }
exti_software_interrupt_disable
void exti_software_interrupt_disable(exti_line_enum linex)
disable EXTI software interrupt event
Definition: gd32f10x_exti.c:225
exti_interrupt_flag_clear
void exti_interrupt_flag_clear(exti_line_enum linex)
clear EXTI lines pending flag
Definition: gd32f10x_exti.c:199
exti_interrupt_enable
void exti_interrupt_enable(exti_line_enum linex)
enable the interrupts from EXTI line x
Definition: gd32f10x_exti.c:95
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f10x_exti.h:25
EXTI_INTERRUPT
Definition: gd32f10x_exti.h:191
exti_event_disable
void exti_event_disable(exti_line_enum linex)
disable the events from EXTI line x
Definition: gd32f10x_exti.c:134
exti_deinit
void exti_deinit(void)
deinitialize the EXTI
Definition: gd32f10x_exti.c:21
exti_flag_clear
void exti_flag_clear(exti_line_enum linex)
clear EXTI lines pending flag
Definition: gd32f10x_exti.c:164
exti_interrupt_disable
void exti_interrupt_disable(exti_line_enum linex)
disable the interrupt from EXTI line x
Definition: gd32f10x_exti.c:121
exti_mode_enum
exti_mode_enum
Definition: gd32f10x_exti.h:189
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f10x_exti.h:22
exti_line_enum
exti_line_enum
Definition: gd32f10x_exti.h:164
EXTI_TRIG_FALLING
Definition: gd32f10x_exti.h:199
exti_software_interrupt_enable
void exti_software_interrupt_enable(exti_line_enum linex)
enable EXTI software interrupt event
Definition: gd32f10x_exti.c:212
EXTI_TRIG_BOTH
Definition: gd32f10x_exti.h:200
EXTI_TRIG_RISING
Definition: gd32f10x_exti.h:198
exti_event_enable
void exti_event_enable(exti_line_enum linex)
enable the events from EXTI line x
Definition: gd32f10x_exti.c:108
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f10x_exti.h:23
gd32f10x_exti.h
definitions for the EXTI
EXTI_PD
#define EXTI_PD
Definition: gd32f10x_exti.h:27
exti_init
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
initialize the EXTI
Definition: gd32f10x_exti.c:48
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f10x_exti.h:26
exti_trig_type_enum
exti_trig_type_enum
Definition: gd32f10x_exti.h:196
EXTI_EVENT
Definition: gd32f10x_exti.h:192
exti_interrupt_flag_get
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
get EXTI lines flag when the interrupt flag is set
Definition: gd32f10x_exti.c:177
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f10x_exti.h:24
exti_flag_get
FlagStatus exti_flag_get(exti_line_enum linex)
get EXTI lines flag
Definition: gd32f10x_exti.c:147
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_can.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_can.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_can.h"
14
22 void can_deinit(uint32_t can_periph)
23 {
24 #ifdef GD32F10x_CL
25 if(CAN0 == can_periph){
26 rcu_periph_reset_enable(RCU_CAN0RST);
27 rcu_periph_reset_disable(RCU_CAN0RST);
28 }else{
29 rcu_periph_reset_enable(RCU_CAN1RST);
30 rcu_periph_reset_disable(RCU_CAN1RST);
31 }
32 #else
33 if(CAN0 == can_periph){
34 rcu_periph_reset_enable(RCU_CAN0RST);
35 rcu_periph_reset_disable(RCU_CAN0RST);
36 }
37 #endif
38 }
39
59 ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init)
60 {
61 uint32_t timeout = CAN_TIMEOUT;
62 ErrStatus flag = ERROR;
63
64 /* disable sleep mode */
65 CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
66 /* enable initialize mode */
67 CAN_CTL(can_periph) |= CAN_CTL_IWMOD;
68 /* wait ACK */
69 while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){
70 timeout--;
71 }
72 /* check initialize working success */
73 if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
74 flag = ERROR;
75 }else{
76 /* set the bit timing register */
77 CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \
78 BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \
79 BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
80 BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
81 BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
82 /* time trigger communication mode */
83 if(ENABLE == can_parameter_init->time_triggered){
84 CAN_CTL(can_periph) |= CAN_CTL_TTC;
85 }else{
86 CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
87 }
88 /* automatic bus-off managment */
89 if(ENABLE == can_parameter_init->auto_bus_off_recovery){
90 CAN_CTL(can_periph) |= CAN_CTL_ABOR;
91 }else{
92 CAN_CTL(can_periph) &= ~CAN_CTL_ABOR;
93 }
94 /* automatic wakeup mode */
95 if(ENABLE == can_parameter_init->auto_wake_up){
96 CAN_CTL(can_periph) |= CAN_CTL_AWU;
97 }else{
98 CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
99 }
100 /* automatic retransmission mode */
101 if(ENABLE == can_parameter_init->auto_retrans){
102 CAN_CTL(can_periph) |= CAN_CTL_ARD;
103 }else{
104 CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
105 }
106 /* receive fifo overwrite mode */
107 if(ENABLE == can_parameter_init->rec_fifo_overwrite){
108 CAN_CTL(can_periph) |= CAN_CTL_RFOD;
109 }else{
110 CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
111 }
112 /* transmit fifo order */
113 if(ENABLE == can_parameter_init->trans_fifo_order){
114 CAN_CTL(can_periph) |= CAN_CTL_TFO;
115 }else{
116 CAN_CTL(can_periph) &= ~CAN_CTL_TFO;
117 }
118 /* disable initialize mode */
119 CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD;
120 timeout = CAN_TIMEOUT;
121 /* wait the ACK */
122 while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){
123 timeout--;
124 }
125 /* check exit initialize mode */
126 if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){
127 flag = SUCCESS;
128 }
129 }
130 return flag;
131 }
132
148 void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
149 {
150 uint32_t val = 0U;
151
152 val = ((uint32_t)1) << (can_filter_parameter_init->filter_number);
153 /* filter lock disable */
154 CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
155 /* disable filter */
156 CAN_FW(CAN0) &= ~(uint32_t)val;
157
158 /* filter 16 bits */
159 if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){
160 /* set filter 16 bits */
161 CAN_FSCFG(CAN0) &= ~(uint32_t)val;
162 /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */
163 CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
164 FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \
165 FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
166 /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */
167 CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
168 FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \
169 FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS);
170 }
171 /* filter 32 bits */
172 if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){
173 /* set filter 32 bits */
174 CAN_FSCFG(CAN0) |= (uint32_t)val;
175 /* 32 bits list or first 32 bits list */
176 CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
177 FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) |
178 FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
179 /* 32 bits mask or second 32 bits list */
180 CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
181 FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) |
182 FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS);
183 }
184
185 /* filter mode */
186 if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){
187 /* mask mode */
188 CAN_FMCFG(CAN0) &= ~(uint32_t)val;
189 }else{
190 /* list mode */
191 CAN_FMCFG(CAN0) |= (uint32_t)val;
192 }
193
194 /* filter FIFO */
195 if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){
196 /* FIFO0 */
197 CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
198 }else{
199 /* FIFO1 */
200 CAN_FAFIFO(CAN0) |= (uint32_t)val;
201 }
202
203 /* filter working */
204 if(ENABLE == can_filter_parameter_init->filter_enable){
205
206 CAN_FW(CAN0) |= (uint32_t)val;
207 }
208
209 /* filter lock enable */
210 CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
211 }
212
220 void can1_filter_start_bank(uint8_t start_bank)
221 {
222 /* filter lock disable */
223 CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
224 /* set CAN1 filter start number */
225 CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F;
226 CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank);
227 /* filter lock enaable */
228 CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
229 }
230
238 void can_debug_freeze_enable(uint32_t can_periph)
239 {
240 CAN_CTL(can_periph) |= CAN_CTL_DFZ;
241 #ifdef GD32F10x_CL
242 if(CAN0 == can_periph){
243 dbg_periph_enable(DBG_CAN0_HOLD);
244 }else{
245 dbg_periph_enable(DBG_CAN1_HOLD);
246 }
247 #else
248 if(CAN0 == can_periph){
249 dbg_periph_enable(DBG_CAN0_HOLD);
250 }
251 #endif
252 }
253
261 void can_debug_freeze_disable(uint32_t can_periph)
262 {
263 CAN_CTL(can_periph) |= CAN_CTL_DFZ;
264 #ifdef GD32F10x_CL
265 if(CAN0 == can_periph){
266 dbg_periph_disable(DBG_CAN0_HOLD);
267 }else{
268 dbg_periph_disable(DBG_CAN1_HOLD);
269 }
270 #else
271 if(CAN0 == can_periph){
272 dbg_periph_enable(DBG_CAN0_HOLD);
273 }
274 #endif
275 }
276
284 void can_time_trigger_mode_enable(uint32_t can_periph)
285 {
286 uint8_t mailbox_number;
287
288 /* enable the tcc mode */
289 CAN_CTL(can_periph) |= CAN_CTL_TTC;
290 /* enable time stamp */
291 for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){
292 CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN;
293 }
294 }
295
303 void can_time_trigger_mode_disable(uint32_t can_periph)
304 {
305 uint8_t mailbox_number;
306
307 /* disable the TCC mode */
308 CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
309 /* reset TSEN bits */
310 for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){
311 CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN;
312 }
313 }
314
329 uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message)
330 {
331 uint8_t mailbox_number = CAN_MAILBOX0;
332
333 /* select one empty mailbox */
334 if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){
335 mailbox_number = CAN_MAILBOX0;
336 }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){
337 mailbox_number = CAN_MAILBOX1;
338 }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){
339 mailbox_number = CAN_MAILBOX2;
340 }else{
341 mailbox_number = CAN_NOMAILBOX;
342 }
343 if(CAN_NOMAILBOX == mailbox_number){
344 return CAN_NOMAILBOX;
345 }
346
347 CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN;
348 if(CAN_FF_STANDARD == transmit_message->tx_ff){
349 /* set transmit mailbox standard identifier */
350 CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \
351 transmit_message->tx_ft);
352 }else{
353 /* set transmit mailbox extended identifier */
354 CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \
355 transmit_message->tx_ff | \
356 transmit_message->tx_ft);
357 }
358 /* set the data length */
359 CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC);
360 CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
361 /* set the data */
362 CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \
363 TMDATA0_DB2(transmit_message->tx_data[2]) | \
364 TMDATA0_DB1(transmit_message->tx_data[1]) | \
365 TMDATA0_DB0(transmit_message->tx_data[0]);
366 CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \
367 TMDATA1_DB6(transmit_message->tx_data[6]) | \
368 TMDATA1_DB5(transmit_message->tx_data[5]) | \
369 TMDATA1_DB4(transmit_message->tx_data[4]);
370 /* enable transmission */
371 CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN;
372
373 return mailbox_number;
374 }
375
385 can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number)
386 {
387 can_transmit_state_enum state = CAN_TRANSMIT_FAILED;
388 uint32_t val = 0U;
389
390 switch(mailbox_number){
391 case CAN_MAILBOX0:
392 val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0);
393 break;
394 case CAN_MAILBOX1:
395 val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1);
396 break;
397 case CAN_MAILBOX2:
398 val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2);
399 break;
400 default:
401 val = CAN_TRANSMIT_FAILED;
402 break;
403 }
404 switch(val){
405 /* transmit pending */
406 case (CAN_STATE_PENDING):
407 state = CAN_TRANSMIT_PENDING;
408 break;
409 /* transmit succeeded */
410 case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0):
411 state = CAN_TRANSMIT_OK;
412 break;
413 case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1):
414 state = CAN_TRANSMIT_OK;
415 break;
416 case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2):
417 state = CAN_TRANSMIT_OK;
418 break;
419 default:
420 state = CAN_TRANSMIT_FAILED;
421 break;
422 }
423 return state;
424 }
425
436 void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
437 {
438 if(CAN_MAILBOX0 == mailbox_number){
439 CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
440 }else if(CAN_MAILBOX1 == mailbox_number){
441 CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
442 }else if(CAN_MAILBOX2 == mailbox_number){
443 CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
444 }else{
445 /* illegal parameter*/
446 }
447 }
448
465 void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message)
466 {
467 /* get the frame format */
468 receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number));
469 if(CAN_FF_STANDARD == receive_message->rx_ff){
470 /* get standard identifier */
471 receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number)));
472 }else{
473 /* get extended identifier */
474 receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number)));
475 }
476
477 /* get frame type */
478 receive_message -> rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number));
479 /* get recevie data length */
480 receive_message -> rx_dlen = (uint8_t)(RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number)));
481 /* filtering index */
482 receive_message -> rx_fi = (uint8_t)(RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number)));
483
484 /* receive data */
485 receive_message -> rx_data[0] = (uint8_t)(RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number)));
486 receive_message -> rx_data[1] = (uint8_t)(RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number)));
487 receive_message -> rx_data[2] = (uint8_t)(RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number)));
488 receive_message -> rx_data[3] = (uint8_t)(RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number)));
489 receive_message -> rx_data[4] = (uint8_t)(RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number)));
490 receive_message -> rx_data[5] = (uint8_t)(RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number)));
491 receive_message -> rx_data[6] = (uint8_t)(RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number)));
492 receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number)));
493
494 /* release FIFO */
495 if(CAN_FIFO0 == fifo_number){
496 CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
497 }else{
498 CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
499 }
500 }
501
510 void can_fifo_release(uint32_t can_periph, uint8_t fifo_number)
511 {
512 if(CAN_FIFO0 == fifo_number){
513 CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
514 }else if(CAN_FIFO1 == fifo_number){
515 CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
516 }else{
517 /* illegal parameter */
518 }
519 }
520
530 uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
531 {
532 uint8_t val = 0U;
533
534 if(CAN_FIFO0 == fifo_number){
535 val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK);
536 }else if(CAN_FIFO1 == fifo_number){
537 val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK);
538 }else{
539 /* illegal parameter */
540 }
541 return val;
542 }
543
555 ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
556 {
557 ErrStatus flag = ERROR;
558 /* timeout for IWS or also for SLPWS bits */
559 uint32_t timeout = CAN_TIMEOUT;
560
561 if(CAN_MODE_INITIALIZE == working_mode){
562 /* disable sleep mode */
563 CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD);
564 /* set initialize mode */
565 CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD;
566 /* wait the acknowledge */
567 while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
568 timeout--;
569 }
570 if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
571 flag = ERROR;
572 }else{
573 flag = SUCCESS;
574 }
575 }else if(CAN_MODE_NORMAL == working_mode){
576 /* enter normal mode */
577 CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD);
578 /* wait the acknowledge */
579 while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){
580 timeout--;
581 }
582 if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){
583 flag = ERROR;
584 }else{
585 flag = SUCCESS;
586 }
587 }else if(CAN_MODE_SLEEP == working_mode){
588 /* disable initialize mode */
589 CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD);
590 /* set sleep mode */
591 CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD;
592 /* wait the acknowledge */
593 while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){
594 timeout--;
595 }
596 if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
597 flag = ERROR;
598 }else{
599 flag = SUCCESS;
600 }
601 }else{
602 flag = ERROR;
603 }
604 return flag;
605 }
606
614 ErrStatus can_wakeup(uint32_t can_periph)
615 {
616 ErrStatus flag = ERROR;
617 uint32_t timeout = CAN_TIMEOUT;
618
619 /* wakeup */
620 CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
621
622 while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){
623 timeout--;
624 }
625 if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
626 flag = ERROR;
627 }else{
628 flag = SUCCESS;
629 }
630 return flag;
631 }
632
640 can_error_enum can_error_get(uint32_t can_periph)
641 {
642 can_error_enum error;
643 error = CAN_ERROR_NONE;
644
645 /* get error type */
646 error = (can_error_enum)((CAN_ERR(can_periph) & CAN_ERR_ERRN) >> 4U);
647 return error;
648 }
649
657 uint8_t can_receive_error_number_get(uint32_t can_periph)
658 {
659 uint8_t val;
660
661 val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_RECNT) >> 24U);
662 return val;
663 }
664
672 uint8_t can_transmit_error_number_get(uint32_t can_periph)
673 {
674 uint8_t val;
675
676 val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_TECNT) >> 16U);
677 return val;
678 }
679
702 void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
703 {
704 CAN_INTEN(can_periph) |= interrupt;
705 }
706
729 void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
730 {
731 CAN_INTEN(can_periph) &= ~interrupt;
732 }
733
756 FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
757 {
758 if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){
759 return SET;
760 }else{
761 return RESET;
762 }
763 }
764
784 void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
785 {
786 CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag));
787 }
788
808 FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag)
809 {
810 FlagStatus ret1 = RESET;
811 FlagStatus ret2 = RESET;
812
813 /* get the staus of interrupt flag */
814 ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)));
815 /* get the staus of interrupt enale bit */
816 ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)));
817 if(ret1 && ret2){
818 return SET;
819 }else{
820 return RESET;
821 }
822 }
823
843 void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag)
844 {
845 CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag));
846 }
FCTL_HBC1F
#define FCTL_HBC1F(regval)
Definition: gd32f10x_can.h:443
RFIFOMDATA0_DB0
#define RFIFOMDATA0_DB0(regval)
Definition: gd32f10x_can.h:488
CAN_RFIFOMDATA0
#define CAN_RFIFOMDATA0(canx, bank)
Definition: gd32f10x_can.h:126
BT_BS2
#define BT_BS2(regval)
Definition: gd32f10x_can.h:428
can_transmit_states
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number)
get CAN transmit state
Definition: gd32f10x_can.c:385
CAN_TMDATA0
#define CAN_TMDATA0(canx, bank)
Definition: gd32f10x_can.h:116
can_deinit
void can_deinit(uint32_t can_periph)
deinitialize CAN
Definition: gd32f10x_can.c:22
can_init
ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init)
initialize CAN
Definition: gd32f10x_can.c:59
can_error_enum
can_error_enum
Definition: gd32f10x_can.h:400
can_transmission_stop
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
stop CAN transmission
Definition: gd32f10x_can.c:436
CAN_TSTAT_MTFNERR1
#define CAN_TSTAT_MTFNERR1
Definition: gd32f10x_can.h:160
can_fifo_release
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number)
release FIFO0
Definition: gd32f10x_can.c:510
CAN_ERR
#define CAN_ERR(canx)
Definition: gd32f10x_can.h:29
can_parameter_struct::auto_wake_up
ControlStatus auto_wake_up
Definition: gd32f10x_can.h:355
CAN_RFIFO1_RFD1
#define CAN_RFIFO1_RFD1
Definition: gd32f10x_can.h:187
can_transmit_state_enum
can_transmit_state_enum
Definition: gd32f10x_can.h:413
can_filter_parameter_struct::filter_list_high
uint16_t filter_list_high
Definition: gd32f10x_can.h:388
CAN_ERR_TECNT
#define CAN_ERR_TECNT
Definition: gd32f10x_can.h:210
CAN_FCTL_HBC1F
#define CAN_FCTL_HBC1F
Definition: gd32f10x_can.h:270
CAN_TSTAT
#define CAN_TSTAT(canx)
Definition: gd32f10x_can.h:25
RFIFOMDATA1_DB6
#define RFIFOMDATA1_DB6(regval)
Definition: gd32f10x_can.h:506
CAN_TSTAT_MST1
#define CAN_TSTAT_MST1
Definition: gd32f10x_can.h:163
TMDATA0_DB3
#define TMDATA0_DB3(regval)
Definition: gd32f10x_can.h:461
CAN_TMI
#define CAN_TMI(canx, bank)
Definition: gd32f10x_can.h:114
can_interrupt_flag_enum
can_interrupt_flag_enum
Definition: gd32f10x_can.h:328
can_receive_message_struct::rx_ff
uint8_t rx_ff
Definition: gd32f10x_can.h:378
can_interrupt_disable
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
disable CAN interrupt
Definition: gd32f10x_can.c:729
DBG_CAN0_HOLD
Definition: gd32f10x_dbg.h:73
dbg_periph_enable
void dbg_periph_enable(dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:68
can_flag_clear
void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
clear CAN flag state
Definition: gd32f10x_can.c:784
CAN_TSTAT_MTF1
#define CAN_TSTAT_MTF1
Definition: gd32f10x_can.h:159
RCU_CAN0RST
Definition: gd32f10x_rcu.h:468
can_trasnmit_message_struct::tx_dlen
uint8_t tx_dlen
Definition: gd32f10x_can.h:369
RFIFOMI_SFID
#define RFIFOMI_SFID(regval)
Definition: gd32f10x_can.h:479
can_filter_parameter_struct::filter_list_low
uint16_t filter_list_low
Definition: gd32f10x_can.h:389
can_error_get
can_error_enum can_error_get(uint32_t can_periph)
get CAN error type
Definition: gd32f10x_can.c:640
can_debug_freeze_disable
void can_debug_freeze_disable(uint32_t can_periph)
disable CAN debug freeze
Definition: gd32f10x_can.c:261
can_filter_parameter_struct::filter_mode
uint16_t filter_mode
Definition: gd32f10x_can.h:394
can_trasnmit_message_struct
Definition: gd32f10x_can.h:363
TMDATA1_DB5
#define TMDATA1_DB5(regval)
Definition: gd32f10x_can.h:467
CAN_RFIF_RFL_MASK
#define CAN_RFIF_RFL_MASK
Definition: gd32f10x_can.h:579
CAN_RFIFOMDATA1
#define CAN_RFIFOMDATA1(canx, bank)
Definition: gd32f10x_can.h:127
FDATA_MASK_HIGH
#define FDATA_MASK_HIGH(regval)
Definition: gd32f10x_can.h:437
RFIFOMP_FI
#define RFIFOMP_FI(regval)
Definition: gd32f10x_can.h:485
CAN_FILTERBITS_32BIT
#define CAN_FILTERBITS_32BIT
Definition: gd32f10x_can.h:591
CAN_FSCFG
#define CAN_FSCFG(canx)
Definition: gd32f10x_can.h:53
CAN_FILTER_MASK_16BITS
#define CAN_FILTER_MASK_16BITS
Definition: gd32f10x_can.h:598
can_parameter_struct::time_segment_1
uint8_t time_segment_1
Definition: gd32f10x_can.h:351
TMDATA0_DB0
#define TMDATA0_DB0(regval)
Definition: gd32f10x_can.h:452
can_interrupt_flag_get
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag)
get CAN interrupt flag state
Definition: gd32f10x_can.c:808
CAN_FCTL
#define CAN_FCTL(canx)
Definition: gd32f10x_can.h:51
CAN_MODE_NORMAL
#define CAN_MODE_NORMAL
Definition: gd32f10x_can.h:586
dbg_periph_disable
void dbg_periph_disable(dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode
Definition: gd32f10x_dbg.c:85
CAN_RFIFO1
#define CAN_RFIFO1(canx)
Definition: gd32f10x_can.h:27
BT_BAUDPSC
#define BT_BAUDPSC(regval)
Definition: gd32f10x_can.h:422
CAN_REG_VALS
#define CAN_REG_VALS(canx, offset)
Definition: gd32f10x_can.h:294
can_parameter_struct
Definition: gd32f10x_can.h:347
CAN_CTL_IWMOD
#define CAN_CTL_IWMOD
Definition: gd32f10x_can.h:131
can_working_mode_set
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
set CAN working mode
Definition: gd32f10x_can.c:555
CAN_TRANSMIT_FAILED
Definition: gd32f10x_can.h:415
can_filter_init
void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init)
initialize CAN filter
Definition: gd32f10x_can.c:148
CAN_CTL_DFZ
#define CAN_CTL_DFZ
Definition: gd32f10x_can.h:140
CAN_FW
#define CAN_FW(canx)
Definition: gd32f10x_can.h:55
BT_MODE
#define BT_MODE(regval)
Definition: gd32f10x_can.h:434
RFIFOMI_EFID
#define RFIFOMI_EFID(regval)
Definition: gd32f10x_can.h:476
can_trasnmit_message_struct::tx_sfid
uint32_t tx_sfid
Definition: gd32f10x_can.h:365
gd32f10x_can.h
definitions for the CAN
CAN_STAT
#define CAN_STAT(canx)
Definition: gd32f10x_can.h:24
CAN_TSTAT_TME2
#define CAN_TSTAT_TME2
Definition: gd32f10x_can.h:172
CAN_ERROR_NONE
Definition: gd32f10x_can.h:402
can_filter_parameter_struct::filter_mask_low
uint16_t filter_mask_low
Definition: gd32f10x_can.h:391
CAN0
#define CAN0
Definition: gd32f10x_can.h:19
can_trasnmit_message_struct::tx_ff
uint8_t tx_ff
Definition: gd32f10x_can.h:367
can_filter_parameter_struct::filter_number
uint16_t filter_number
Definition: gd32f10x_can.h:393
CAN_MODE_SLEEP
#define CAN_MODE_SLEEP
Definition: gd32f10x_can.h:587
CAN_BIT_POS1
#define CAN_BIT_POS1(val)
Definition: gd32f10x_can.h:296
CAN_RFIFO0
#define CAN_RFIFO0(canx)
Definition: gd32f10x_can.h:26
CAN_CTL_ABOR
#define CAN_CTL_ABOR
Definition: gd32f10x_can.h:137
RFIFOMDATA0_DB1
#define RFIFOMDATA0_DB1(regval)
Definition: gd32f10x_can.h:491
BT_BS1
#define BT_BS1(regval)
Definition: gd32f10x_can.h:425
CAN_ERR_ERRN
#define CAN_ERR_ERRN
Definition: gd32f10x_can.h:209
CAN_CTL_RFOD
#define CAN_CTL_RFOD
Definition: gd32f10x_can.h:134
CAN_TSTAT_TME1
#define CAN_TSTAT_TME1
Definition: gd32f10x_can.h:171
can_time_trigger_mode_disable
void can_time_trigger_mode_disable(uint32_t can_periph)
disable CAN time trigger mode
Definition: gd32f10x_can.c:303
can_receive_error_number_get
uint8_t can_receive_error_number_get(uint32_t can_periph)
get CAN receive error number
Definition: gd32f10x_can.c:657
CAN_BIT_POS
#define CAN_BIT_POS(val)
Definition: gd32f10x_can.h:291
RFIFOMDATA1_DB4
#define RFIFOMDATA1_DB4(regval)
Definition: gd32f10x_can.h:500
can_parameter_struct::auto_bus_off_recovery
ControlStatus auto_bus_off_recovery
Definition: gd32f10x_can.h:354
CAN_FIFO1
#define CAN_FIFO1
Definition: gd32f10x_can.h:576
CAN_MODE_INITIALIZE
#define CAN_MODE_INITIALIZE
Definition: gd32f10x_can.h:585
can_parameter_struct::resync_jump_width
uint8_t resync_jump_width
Definition: gd32f10x_can.h:350
can_message_receive
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message)
CAN receive message.
Definition: gd32f10x_can.c:465
can_parameter_struct::rec_fifo_overwrite
ControlStatus rec_fifo_overwrite
Definition: gd32f10x_can.h:357
can_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f10x_can.h:359
can_trasnmit_message_struct::tx_efid
uint32_t tx_efid
Definition: gd32f10x_can.h:366
CAN_FCTL_FLD
#define CAN_FCTL_FLD
Definition: gd32f10x_can.h:269
CAN_TMP_DLENC
#define CAN_TMP_DLENC
Definition: gd32f10x_can.h:229
CAN_CTL_ARD
#define CAN_CTL_ARD
Definition: gd32f10x_can.h:135
TMDATA0_DB1
#define TMDATA0_DB1(regval)
Definition: gd32f10x_can.h:455
CAN_INTEN
#define CAN_INTEN(canx)
Definition: gd32f10x_can.h:28
CAN_CTL_SLPWMOD
#define CAN_CTL_SLPWMOD
Definition: gd32f10x_can.h:132
RFIFOMDATA1_DB5
#define RFIFOMDATA1_DB5(regval)
Definition: gd32f10x_can.h:503
CAN_TSTAT_MTF0
#define CAN_TSTAT_MTF0
Definition: gd32f10x_can.h:154
CAN_TIMEOUT
#define CAN_TIMEOUT
Definition: gd32f10x_can.h:605
CAN_FMCFG
#define CAN_FMCFG(canx)
Definition: gd32f10x_can.h:52
can_transmit_error_number_get
uint8_t can_transmit_error_number_get(uint32_t can_periph)
get CAN transmit error number
Definition: gd32f10x_can.c:672
can_parameter_struct::time_triggered
ControlStatus time_triggered
Definition: gd32f10x_can.h:353
TMDATA1_DB6
#define TMDATA1_DB6(regval)
Definition: gd32f10x_can.h:470
CAN_RFIFOMI
#define CAN_RFIFOMI(canx, bank)
Definition: gd32f10x_can.h:124
CAN_REG_VAL
#define CAN_REG_VAL(canx, offset)
Definition: gd32f10x_can.h:290
CAN_RFIFO0_RFD0
#define CAN_RFIFO0_RFD0
Definition: gd32f10x_can.h:181
can_filter_parameter_struct::filter_mask_high
uint16_t filter_mask_high
Definition: gd32f10x_can.h:390
can_trasnmit_message_struct::tx_data
uint8_t tx_data[8]
Definition: gd32f10x_can.h:370
CAN_RFIFOMI_FF
#define CAN_RFIFOMI_FF
Definition: gd32f10x_can.h:247
CAN_CTL
#define CAN_CTL(canx)
Definition: gd32f10x_can.h:23
CAN_CTL_AWU
#define CAN_CTL_AWU
Definition: gd32f10x_can.h:136
CAN_TSTAT_MST0
#define CAN_TSTAT_MST0
Definition: gd32f10x_can.h:158
CAN_NOMAILBOX
#define CAN_NOMAILBOX
Definition: gd32f10x_can.h:568
CAN_STAT_IWS
#define CAN_STAT_IWS
Definition: gd32f10x_can.h:143
can_receive_message_length_get
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
CAN receive message length.
Definition: gd32f10x_can.c:530
can_message_transmit
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message)
transmit CAN message
Definition: gd32f10x_can.c:329
can_flag_enum
can_flag_enum
Definition: gd32f10x_can.h:306
CAN_TMDATA1
#define CAN_TMDATA1(canx, bank)
Definition: gd32f10x_can.h:117
CAN_TRANSMIT_PENDING
Definition: gd32f10x_can.h:417
BT_SJW
#define BT_SJW(regval)
Definition: gd32f10x_can.h:431
CAN_TSTAT_TME0
#define CAN_TSTAT_TME0
Definition: gd32f10x_can.h:170
CAN_BIT_POS0
#define CAN_BIT_POS0(val)
Definition: gd32f10x_can.h:295
CAN_TSTAT_MTF2
#define CAN_TSTAT_MTF2
Definition: gd32f10x_can.h:164
RFIFOMDATA1_DB7
#define RFIFOMDATA1_DB7(regval)
Definition: gd32f10x_can.h:509
CAN_FAFIFO
#define CAN_FAFIFO(canx)
Definition: gd32f10x_can.h:54
CAN_FF_STANDARD
#define CAN_FF_STANDARD
Definition: gd32f10x_can.h:571
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
CAN_TMP
#define CAN_TMP(canx, bank)
Definition: gd32f10x_can.h:115
CAN_CTL_TFO
#define CAN_CTL_TFO
Definition: gd32f10x_can.h:133
can_flag_get
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
get CAN flag state
Definition: gd32f10x_can.c:756
CAN_FDATA0
#define CAN_FDATA0(canx, bank)
Definition: gd32f10x_can.h:120
can_debug_freeze_enable
void can_debug_freeze_enable(uint32_t can_periph)
enable CAN debug freeze
Definition: gd32f10x_can.c:238
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
CAN_MAILBOX0
#define CAN_MAILBOX0
Definition: gd32f10x_can.h:565
FDATA_MASK_LOW
#define FDATA_MASK_LOW(regval)
Definition: gd32f10x_can.h:440
can_filter_parameter_struct::filter_bits
uint16_t filter_bits
Definition: gd32f10x_can.h:395
can_parameter_struct::trans_fifo_order
ControlStatus trans_fifo_order
Definition: gd32f10x_can.h:358
CAN_TRANSMIT_OK
Definition: gd32f10x_can.h:416
CAN_CTL_TTC
#define CAN_CTL_TTC
Definition: gd32f10x_can.h:138
can1_filter_start_bank
void can1_filter_start_bank(uint8_t start_bank)
set CAN1 fliter start bank number
Definition: gd32f10x_can.c:220
CAN_MAILBOX2
#define CAN_MAILBOX2
Definition: gd32f10x_can.h:567
CAN_TMP_TSEN
#define CAN_TMP_TSEN
Definition: gd32f10x_can.h:230
can_parameter_struct::time_segment_2
uint8_t time_segment_2
Definition: gd32f10x_can.h:352
CAN_MAILBOX1
#define CAN_MAILBOX1
Definition: gd32f10x_can.h:566
can_filter_parameter_struct::filter_enable
ControlStatus filter_enable
Definition: gd32f10x_can.h:396
CAN_TSTAT_MST2
#define CAN_TSTAT_MST2
Definition: gd32f10x_can.h:168
CAN_FDATA1
#define CAN_FDATA1(canx, bank)
Definition: gd32f10x_can.h:121
CAN_FILTERMODE_MASK
#define CAN_FILTERMODE_MASK
Definition: gd32f10x_can.h:594
CAN_TSTAT_MTFNERR0
#define CAN_TSTAT_MTFNERR0
Definition: gd32f10x_can.h:155
can_filter_parameter_struct
Definition: gd32f10x_can.h:386
TMDATA1_DB7
#define TMDATA1_DB7(regval)
Definition: gd32f10x_can.h:473
RFIFOMDATA0_DB2
#define RFIFOMDATA0_DB2(regval)
Definition: gd32f10x_can.h:494
can_time_trigger_mode_enable
void can_time_trigger_mode_enable(uint32_t can_periph)
enable CAN time trigger mode
Definition: gd32f10x_can.c:284
CAN_RFIFOMI_FT
#define CAN_RFIFOMI_FT
Definition: gd32f10x_can.h:246
can_parameter_struct::auto_retrans
ControlStatus auto_retrans
Definition: gd32f10x_can.h:356
RFIFOMP_DLENC
#define RFIFOMP_DLENC(regval)
Definition: gd32f10x_can.h:482
can_wakeup
ErrStatus can_wakeup(uint32_t can_periph)
wake up CAN
Definition: gd32f10x_can.c:614
RCU_CAN1RST
Definition: gd32f10x_rcu.h:470
CAN_RFIFOMP
#define CAN_RFIFOMP(canx, bank)
Definition: gd32f10x_can.h:125
RFIFOMDATA0_DB3
#define RFIFOMDATA0_DB3(regval)
Definition: gd32f10x_can.h:497
CAN_STATE_PENDING
#define CAN_STATE_PENDING
Definition: gd32f10x_can.h:522
CAN_FILTERBITS_16BIT
#define CAN_FILTERBITS_16BIT
Definition: gd32f10x_can.h:590
can_interrupt_flag_clear
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag)
clear CAN interrupt flag state
Definition: gd32f10x_can.c:843
can_filter_parameter_struct::filter_fifo_number
uint16_t filter_fifo_number
Definition: gd32f10x_can.h:392
can_receive_message_struct
Definition: gd32f10x_can.h:374
TMDATA0_DB2
#define TMDATA0_DB2(regval)
Definition: gd32f10x_can.h:458
TMDATA1_DB4
#define TMDATA1_DB4(regval)
Definition: gd32f10x_can.h:464
TMI_SFID
#define TMI_SFID(regval)
Definition: gd32f10x_can.h:449
CAN_TSTAT_MTFNERR2
#define CAN_TSTAT_MTFNERR2
Definition: gd32f10x_can.h:165
CAN_BT
#define CAN_BT(canx)
Definition: gd32f10x_can.h:30
CAN_STAT_SLPWS
#define CAN_STAT_SLPWS
Definition: gd32f10x_can.h:144
CAN_FIFO0
#define CAN_FIFO0
Definition: gd32f10x_can.h:575
TMI_EFID
#define TMI_EFID(regval)
Definition: gd32f10x_can.h:446
can_parameter_struct::working_mode
uint8_t working_mode
Definition: gd32f10x_can.h:349
can_interrupt_enable
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
enable CAN interrupt
Definition: gd32f10x_can.c:702
CAN_TMI_TEN
#define CAN_TMI_TEN
Definition: gd32f10x_can.h:222
CAN_ERR_RECNT
#define CAN_ERR_RECNT
Definition: gd32f10x_can.h:211
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1


GD32F10x_Firmware_Library: E:/GD32F10x_Firmware_Library_V2.0.0/Firmware/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c Source File

  • E:
  • GD32F10x_Firmware_Library_V2.0.0
  • Firmware
  • GD32F10x_standard_peripheral
  • Source
gd32f10x_gpio.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2014-12-26, V1.0.0, firmware for GD32F10x
10 2017-06-20, V2.0.0, firmware for GD32F10x
11 */
12
13 #include "gd32f10x_gpio.h"
14
15 #define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U)
16 #define LSB_16BIT_MASK ((uint16_t)0xFFFFU)
17 #define PCF_POSITION_MASK ((uint32_t)0x000F0000U)
18 #define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU)
19 #define PCF_LOCATION1_MASK ((uint32_t)0x00200000U)
20 #define PCF_LOCATION2_MASK ((uint32_t)0x00100000U)
21 #define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U)
29 void gpio_deinit(uint32_t gpio_periph)
30 {
31 switch(gpio_periph){
32 case GPIOA:
33 /* reset GPIOA */
34 rcu_periph_reset_enable(RCU_GPIOARST);
35 rcu_periph_reset_disable(RCU_GPIOARST);
36 break;
37 case GPIOB:
38 /* reset GPIOB */
39 rcu_periph_reset_enable(RCU_GPIOBRST);
40 rcu_periph_reset_disable(RCU_GPIOBRST);
41 break;
42 case GPIOC:
43 /* reset GPIOC */
44 rcu_periph_reset_enable(RCU_GPIOCRST);
45 rcu_periph_reset_disable(RCU_GPIOCRST);
46 break;
47 case GPIOD:
48 /* reset GPIOD */
49 rcu_periph_reset_enable(RCU_GPIODRST);
50 rcu_periph_reset_disable(RCU_GPIODRST);
51 break;
52 case GPIOE:
53 /* reset GPIOE */
54 rcu_periph_reset_enable(RCU_GPIOERST);
55 rcu_periph_reset_disable(RCU_GPIOERST);
56 break;
57 case GPIOF:
58 /* reset GPIOF */
59 rcu_periph_reset_enable(RCU_GPIOFRST);
60 rcu_periph_reset_disable(RCU_GPIOFRST);
61 break;
62 case GPIOG:
63 /* reset GPIOG */
64 rcu_periph_reset_enable(RCU_GPIOGRST);
65 rcu_periph_reset_disable(RCU_GPIOGRST);
66 break;
67 default:
68 break;
69 }
70 }
71
78 void gpio_afio_deinit(void)
79 {
80 rcu_periph_reset_enable(RCU_AFRST);
81 rcu_periph_reset_disable(RCU_AFRST);
82 }
83
104 void gpio_init(uint32_t gpio_periph,uint32_t gpio_mode,uint32_t gpio_speed,uint32_t pin)
105 {
106 uint16_t i;
107 uint32_t temp_mode = 0U;
108 uint32_t reg = 0U;
109
110 /* GPIO mode configuration */
111 temp_mode = (uint32_t)(gpio_mode & ((uint32_t)0x0FU));
112
113 /* GPIO speed configuration */
114 if(((uint32_t)0x00U) != ((uint32_t)gpio_mode & ((uint32_t)0x10U))){
115 /* output mode max speed:10MHz,2MHz,50MHz */
116 temp_mode |= (uint32_t)gpio_speed;
117 }
118
119 /* configure the eight low port pins with GPIO_CTL0 */
120 for(i = 0U;i < 8U;i++){
121 if((1U << i) & pin){
122 reg = GPIO_CTL0(gpio_periph);
123
124 /* clear the specified pin mode bits */
125 reg &= ~GPIO_MODE_MASK(i);
126 /* set the specified pin mode bits */
127 reg |= GPIO_MODE_SET(i, temp_mode);
128
129 /* set IPD or IPU */
130 if(GPIO_MODE_IPD == gpio_mode){
131 /* reset the corresponding OCTL bit */
132 GPIO_BC(gpio_periph) = (uint32_t)pin;
133 }else{
134 /* set the corresponding OCTL bit */
135 if(GPIO_MODE_IPU == gpio_mode){
136 GPIO_BOP(gpio_periph) = (uint32_t)pin;
137 }
138 }
139 /* set GPIO_CTL0 register */
140 GPIO_CTL0(gpio_periph) = reg;
141 }
142 }
143 /* configure the eight high port pins with GPIO_CTL1 */
144 for(i = 8U;i < 16U;i++){
145 if((1U << i) & pin){
146 reg = GPIO_CTL1(gpio_periph);
147
148 /* clear the specified pin mode bits */
149 reg &= ~GPIO_MODE_MASK(i - 8U);
150 /* set the specified pin mode bits */
151 reg |= GPIO_MODE_SET(i - 8U, temp_mode);
152
153 /* set IPD or IPU */
154 if(GPIO_MODE_IPD == gpio_mode){
155 /* reset the corresponding OCTL bit */
156 GPIO_BC(gpio_periph) = (uint32_t)pin;
157 }else{
158 /* set the corresponding OCTL bit */
159 if(GPIO_MODE_IPU == gpio_mode){
160 GPIO_BOP(gpio_periph) = (uint32_t)pin;
161 }
162 }
163 /* set GPIO_CTL1 register */
164 GPIO_CTL1(gpio_periph) = reg;
165 }
166 }
167 }
168
176 void gpio_bit_set(uint32_t gpio_periph,uint32_t pin)
177 {
178 GPIO_BOP(gpio_periph) = (uint32_t)pin;
179 }
180
188 void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin)
189 {
190 GPIO_BC(gpio_periph) = (uint32_t)pin;
191 }
192
203 void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value)
204 {
205 if(RESET != bit_value){
206 GPIO_BOP(gpio_periph) = (uint32_t)pin;
207 }else{
208 GPIO_BC(gpio_periph) = (uint32_t)pin;
209 }
210 }
211
219 void gpio_port_write(uint32_t gpio_periph,uint16_t data)
220 {
221 GPIO_OCTL(gpio_periph) = (uint32_t)data;
222 }
223
231 FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin)
232 {
233 if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
234 return SET;
235 }else{
236 return RESET;
237 }
238 }
239
246 uint16_t gpio_input_port_get(uint32_t gpio_periph)
247 {
248 return (uint16_t)(GPIO_ISTAT(gpio_periph));
249 }
250
258 FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin)
259 {
260 if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){
261 return SET;
262 }else{
263 return RESET;
264 }
265 }
266
273 uint16_t gpio_output_port_get(uint32_t gpio_periph)
274 {
275 return ((uint16_t)GPIO_OCTL(gpio_periph));
276 }
277
285 void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin)
286 {
287 uint32_t lock = 0x00010000U;
288 lock |= pin;
289
290 /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */
291 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
292 GPIO_LOCK(gpio_periph) = (uint32_t)pin;
293 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
294 lock = GPIO_LOCK(gpio_periph);
295 lock = GPIO_LOCK(gpio_periph);
296 }
297
310 void gpio_event_output_config(uint8_t gpio_outputport,uint8_t gpio_outputpin)
311 {
312 uint32_t reg = 0U;
313 reg = AFIO_EC;
314
315 /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */
316 reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN));
317
318 reg |= (uint32_t)((uint32_t)gpio_outputport << 0x04U);
319 reg |= (uint32_t)gpio_outputpin;
320
321 AFIO_EC = reg;
322 }
323
330 void gpio_event_output_enable(void)
331 {
332 AFIO_EC |= AFIO_EC_EOE;
333 }
334
341 void gpio_event_output_disable(void)
342 {
343 AFIO_EC &= (uint32_t)(~AFIO_EC_EOE);
344 }
345
360 void gpio_exti_source_select(uint8_t gpio_outputport,uint8_t gpio_outputpin)
361 {
362 uint32_t source = 0U;
363 source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U));
364
365 /* select EXTI sources */
366 if(GPIO_PIN_SOURCE_4 > gpio_outputpin){
367 /* select EXTI0/EXTI1/EXTI2/EXTI3 */
368 AFIO_EXTISS0 &= ~source;
369 AFIO_EXTISS0 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
370 }else if(GPIO_PIN_SOURCE_8 > gpio_outputpin){
371 /* select EXTI4/EXTI5/EXTI6/EXTI7 */
372 AFIO_EXTISS1 &= ~source;
373 AFIO_EXTISS1 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
374 }else if(GPIO_PIN_SOURCE_12 > gpio_outputpin){
375 /* select EXTI8/EXTI9/EXTI10/EXTI11 */
376 AFIO_EXTISS2 &= ~source;
377 AFIO_EXTISS2 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
378 }else{
379 /* select EXTI12/EXTI13/EXTI14/EXTI15 */
380 AFIO_EXTISS3 &= ~source;
381 AFIO_EXTISS3 |= (((uint32_t)gpio_outputport) << (AFIO_EXTI_SOURCE_FIELDS * (gpio_outputpin & (uint8_t)0x03U)));
382 }
383 }
384
385 #ifdef GD32F10X_CL
386
394 void gpio_ethernet_phy_select(uint32_t gpio_enetsel)
395 {
396 /* clear AFIO_PCF0_ENET_PHY_SEL bit */
397 AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL);
398
399 /* select MII or RMII PHY */
400 AFIO_PCF0 |= (uint32_t)gpio_enetsel;
401 }
402 #endif
403
449 void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue)
450 {
451 uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;
452
453 if(((uint32_t)0x80000000U) == (gpio_remap & 0x80000000U)){
454 /* get AFIO_PCF1 regiter value */
455 temp_reg = AFIO_PCF1;
456 }else{
457 /* get AFIO_PCF0 regiter value */
458 temp_reg = AFIO_PCF0;
459 }
460
461 temp_mask = (gpio_remap & PCF_POSITION_MASK) >> 0x10U;
462 remap1 = gpio_remap & LSB_16BIT_MASK;
463
464 /* judge pin remap type */
465 if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){
466 temp_reg &= PCF_SWJCFG_MASK;
467 AFIO_PCF0 &= PCF_SWJCFG_MASK;
468 }else if(PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)){
469 remap2 = ((uint32_t)0x03U) << temp_mask;
470 temp_reg &= ~remap2;
471 temp_reg |= ~PCF_SWJCFG_MASK;
472 }else{
473 temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U)*0x10U));
474 temp_reg |= ~PCF_SWJCFG_MASK;
475 }
476
477 /* set pin remap value */
478 if(DISABLE != newvalue){
479 temp_reg |= (remap1 << ((gpio_remap >> 0x15U)*0x10U));
480 }
481
482 if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){
483 /* set AFIO_PCF1 regiter value */
484 AFIO_PCF1 = temp_reg;
485 }else{
486 /* set AFIO_PCF0 regiter value */
487 AFIO_PCF0 = temp_reg;
488 }
489 }
gpio_exti_source_select
void gpio_exti_source_select(uint8_t gpio_outputport, uint8_t gpio_outputpin)
select GPIO pin exti sources
Definition: gd32f10x_gpio.c:360
gpio_pin_lock
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
lock GPIO pin
Definition: gd32f10x_gpio.c:285
AFIO_PCF1_FIELDS
#define AFIO_PCF1_FIELDS
Definition: gd32f10x_gpio.c:21
GPIO_MODE_IPU
#define GPIO_MODE_IPU
Definition: gd32f10x_gpio.h:286
AFIO_PCF1
#define AFIO_PCF1
Definition: gd32f10x_gpio.h:48
RCU_GPIOGRST
Definition: gd32f10x_rcu.h:484
bit_status
FlagStatus bit_status
Definition: gd32f10x_gpio.h:276
gpio_afio_deinit
void gpio_afio_deinit(void)
reset alternate function I/O(AFIO)
Definition: gd32f10x_gpio.c:78
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f10x_gpio.h:35
gpio_output_port_get
uint16_t gpio_output_port_get(uint32_t gpio_periph)
get GPIO port output status
Definition: gd32f10x_gpio.c:273
gpio_output_bit_get
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
get GPIO pin output status
Definition: gd32f10x_gpio.c:258
RCU_GPIOBRST
Definition: gd32f10x_rcu.h:479
AFIO_EXTISS1
#define AFIO_EXTISS1
Definition: gd32f10x_gpio.h:45
gpio_event_output_config
void gpio_event_output_config(uint8_t gpio_outputport, uint8_t gpio_outputpin)
configure GPIO pin event output
Definition: gd32f10x_gpio.c:310
GPIOD
#define GPIOD
Definition: gd32f10x_gpio.h:22
LSB_16BIT_MASK
#define LSB_16BIT_MASK
Definition: gd32f10x_gpio.c:16
AFIO_PCF0_ENET_PHY_SEL
#define AFIO_PCF0_ENET_PHY_SEL
Definition: gd32f10x_gpio.h:216
AFIO_EC_EOE
#define AFIO_EC_EOE
Definition: gd32f10x_gpio.h:197
PCF_SWJCFG_MASK
#define PCF_SWJCFG_MASK
Definition: gd32f10x_gpio.c:18
gpio_bit_set
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
set GPIO pin
Definition: gd32f10x_gpio.c:176
gpio_event_output_enable
void gpio_event_output_enable(void)
enable GPIO pin event output
Definition: gd32f10x_gpio.c:330
RCU_GPIOFRST
Definition: gd32f10x_rcu.h:483
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f10x_gpio.h:36
gpio_port_write
void gpio_port_write(uint32_t gpio_periph, uint16_t data)
write data to the specified GPIO port
Definition: gd32f10x_gpio.c:219
gpio_input_port_get
uint16_t gpio_input_port_get(uint32_t gpio_periph)
get GPIO port input status
Definition: gd32f10x_gpio.c:246
RCU_AFRST
Definition: gd32f10x_rcu.h:477
GPIOA
#define GPIOA
Definition: gd32f10x_gpio.h:19
gd32f10x_gpio.h
definitions for the GPIO
RCU_GPIODRST
Definition: gd32f10x_rcu.h:481
gpio_event_output_disable
void gpio_event_output_disable(void)
disable GPIO pin event output
Definition: gd32f10x_gpio.c:341
GPIO_PIN_SOURCE_8
#define GPIO_PIN_SOURCE_8
Definition: gd32f10x_gpio.h:340
GPIO_PIN_SOURCE_4
#define GPIO_PIN_SOURCE_4
Definition: gd32f10x_gpio.h:336
GPIO_LOCK
#define GPIO_LOCK(gpiox)
Definition: gd32f10x_gpio.h:39
GPIO_MODE_IPD
#define GPIO_MODE_IPD
Definition: gd32f10x_gpio.h:285
gpio_bit_reset
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
reset GPIO pin
Definition: gd32f10x_gpio.c:188
GPIOF
#define GPIOF
Definition: gd32f10x_gpio.h:24
RCU_GPIOARST
Definition: gd32f10x_rcu.h:478
PCF_LOCATION1_MASK
#define PCF_LOCATION1_MASK
Definition: gd32f10x_gpio.c:19
GPIO_CTL1
#define GPIO_CTL1(gpiox)
Definition: gd32f10x_gpio.h:34
AFIO_EC_PIN
#define AFIO_EC_PIN
Definition: gd32f10x_gpio.h:195
GPIOB
#define GPIOB
Definition: gd32f10x_gpio.h:20
AFIO_EXTISS3
#define AFIO_EXTISS3
Definition: gd32f10x_gpio.h:47
GPIO_MODE_SET
#define GPIO_MODE_SET(n, mode)
Definition: gd32f10x_gpio.h:279
PCF_LOCATION2_MASK
#define PCF_LOCATION2_MASK
Definition: gd32f10x_gpio.c:20
GPIOG
#define GPIOG
Definition: gd32f10x_gpio.h:25
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f10x_rcu.c:184
GPIO_MODE_MASK
#define GPIO_MODE_MASK(n)
Definition: gd32f10x_gpio.h:280
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f10x_gpio.h:37
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f10x_rcu.c:212
GPIO_PIN_SOURCE_12
#define GPIO_PIN_SOURCE_12
Definition: gd32f10x_gpio.h:344
AFIO_EXTISS0
#define AFIO_EXTISS0
Definition: gd32f10x_gpio.h:44
RCU_GPIOCRST
Definition: gd32f10x_rcu.h:480
GPIOE
#define GPIOE
Definition: gd32f10x_gpio.h:23
gpio_pin_remap_config
void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue)
configure GPIO pin remap
Definition: gd32f10x_gpio.c:449
AFIO_EXTISS2
#define AFIO_EXTISS2
Definition: gd32f10x_gpio.h:46
gpio_init
void gpio_init(uint32_t gpio_periph, uint32_t gpio_mode, uint32_t gpio_speed, uint32_t pin)
GPIO parameter initialization.
Definition: gd32f10x_gpio.c:104
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f10x_gpio.h:38
AFIO_PCF0
#define AFIO_PCF0
Definition: gd32f10x_gpio.h:43
gpio_input_bit_get
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
get GPIO pin input status
Definition: gd32f10x_gpio.c:231
gpio_ethernet_phy_select
void gpio_ethernet_phy_select(uint32_t gpio_enetsel)
select ethernet MII or RMII PHY
Definition: gd32f10x_gpio.c:394
RCU_GPIOERST
Definition: gd32f10x_rcu.h:482
gpio_bit_write
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
write data to the specified GPIO pin
Definition: gd32f10x_gpio.c:203
GPIOC
#define GPIOC
Definition: gd32f10x_gpio.h:21
AFIO_EC
#define AFIO_EC
Definition: gd32f10x_gpio.h:42
AFIO_EXTI_SOURCE_FIELDS
#define AFIO_EXTI_SOURCE_FIELDS
Definition: gd32f10x_gpio.c:15
GPIO_CTL0
#define GPIO_CTL0(gpiox)
Definition: gd32f10x_gpio.h:33
PCF_POSITION_MASK
#define PCF_POSITION_MASK
Definition: gd32f10x_gpio.c:17
AFIO_EC_PORT
#define AFIO_EC_PORT
Definition: gd32f10x_gpio.h:196
Generated on Tue Jul 18 2017 09:24:14 for GD32F10x_Firmware_Library by doxygen 1.8.9.1