uart.c 12 KB

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  1. #include "uart.h"
  2. #include "os/co_task.h"
  3. #include "libs/crc16.h"
  4. #include "libs/logger.h"
  5. #include "libs/utils.h"
  6. #define SHARK_UART_BAUDRATE 921600
  7. #define SHARK_UART0_com USART2
  8. #define SHARK_UART0_tx_port GPIOB
  9. #define SHARK_UART0_tx_pin GPIO_PIN_10
  10. #define SHARK_UART0_rx_port GPIOB
  11. #define SHARK_UART0_rx_pin GPIO_PIN_11
  12. #define SHARK_UART0_irq USART2_IRQn
  13. #define SHARK_UART0_clk RCU_USART2
  14. #define SHARK_UART0_tx_gpio_clk RCU_GPIOB
  15. #define SHARK_UART0_rx_gpio_clk RCU_GPIOB
  16. #define SHARK_UART0_tx_dma DMA0
  17. #define SHARK_UART0_tx_dma_ch DMA_CH1
  18. #define SHARK_UART0_tx_dma_clk RCU_DMA0
  19. #define SHARK_UART0_rx_dma DMA0
  20. #define SHARK_UART0_rx_dma_ch DMA_CH2
  21. #define SHARK_UART0_rx_dma_clk RCU_DMA0
  22. // ================================================================================
  23. #define ENABLE_RX_DMA 1
  24. static u8 shark_uart0_tx_cache[SHARK_UART_TX_MEM_SIZE];
  25. static u8 shark_uart0_rx_cache[SHARK_UART_RX_MEM_SIZE];
  26. static shark_uart_t _shark_uart[1];
  27. ///static bool uart_no_data = false;
  28. #if ENABLE_RX_DMA==1
  29. #define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(SHARK_UART0_rx_dma, uart->rx_dma_ch))
  30. #else
  31. #define update_dma_w_pos(uart){}
  32. #endif
  33. // ================================================================================
  34. static uart_enum_t _uart_index(uint32_t com){
  35. return SHARK_UART0;
  36. }
  37. static bool shark_uart_on_rx_frame(shark_uart_t *uart)
  38. {
  39. u16 crc0 = decode_u16(uart->rx_frame + uart->rx_length);
  40. u16 crc1 = crc16_get(uart->rx_frame, uart->rx_length);
  41. if (crc0 != crc1) {
  42. return false;
  43. }
  44. //protocol_recv_frame(_uart_index(uart->uart_com), (char *)uart->rx_frame, uart->rx_length);
  45. return true;
  46. }
  47. static void shark_uart_rx(shark_uart_t *uart){
  48. while(1) {
  49. u8 data;
  50. update_dma_w_pos(uart);
  51. if (circle_get_one_data(&uart->rx_queue, &data) != 1) {
  52. break;
  53. }
  54. switch(data){
  55. case CH_START:
  56. uart->rx_length = 0;
  57. uart->escape = false;
  58. uart->start = true;
  59. break;
  60. case CH_END:
  61. if (uart->rx_length > 2 && uart->rx_length != 0xFFFF){
  62. uart->rx_length -= 2; //skip crc
  63. shark_uart_on_rx_frame(uart);
  64. }
  65. uart->rx_length = 0xFFFF;
  66. uart->start = false;
  67. break;
  68. case CH_ESC:
  69. uart->escape = true;
  70. break;
  71. default:
  72. if (uart->escape) {
  73. uart->escape = false;
  74. switch (data) {
  75. case CH_ESC_START:
  76. data = CH_START;
  77. break;
  78. case CH_ESC_END:
  79. data = CH_END;
  80. break;
  81. case CH_ESC_ESC:
  82. data = CH_ESC;
  83. break;
  84. default:
  85. data = 0xFF;
  86. }
  87. }
  88. if (uart->rx_length < sizeof(uart->rx_frame)) {
  89. uart->rx_frame[uart->rx_length] = data;
  90. uart->rx_length++;
  91. } else {
  92. uart->rx_length = 0xFFFF;
  93. }
  94. }
  95. }
  96. }
  97. static void shark_uart_dma_tx(shark_uart_t *uart)
  98. {
  99. u32 value = DMA_CHCTL(SHARK_UART0_tx_dma, uart->tx_dma_ch);
  100. if (value & DMA_CHXCTL_CHEN) {
  101. if (SET != dma_flag_get(SHARK_UART0_tx_dma, uart->tx_dma_ch, DMA_FLAG_FTF)) {
  102. return;
  103. }
  104. byte_queue_skip(&uart->tx_queue, uart->tx_length);
  105. DMA_CHCTL(SHARK_UART0_tx_dma, uart->tx_dma_ch) = value & (~DMA_CHXCTL_CHEN);
  106. }
  107. uart->tx_length = byte_queue_peek(&uart->tx_queue);
  108. if (uart->tx_length > 0) {
  109. DMA_CHCNT(SHARK_UART0_tx_dma, uart->tx_dma_ch) = uart->tx_length;
  110. DMA_CHMADDR(SHARK_UART0_tx_dma, uart->tx_dma_ch) = (u32) byte_queue_head(&uart->tx_queue);
  111. dma_flag_clear(SHARK_UART0_tx_dma, uart->tx_dma_ch, DMA_FLAG_FTF);
  112. DMA_CHCTL(SHARK_UART0_tx_dma, uart->tx_dma_ch) = value | DMA_CHXCTL_CHEN;
  113. }
  114. }
  115. static void shark_uart_write(shark_uart_t *uart, const u8 *buff, u16 size)
  116. {
  117. while (size > 0) {
  118. u16 length = byte_queue_write(&uart->tx_queue, buff, size);
  119. if (length == size) {
  120. shark_uart_dma_tx(uart);
  121. break;
  122. }
  123. shark_uart_dma_tx(uart);
  124. buff += length;
  125. size -= length;
  126. co_task_schedule();
  127. }
  128. }
  129. static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
  130. {
  131. shark_uart_write(uart, &value, 1);
  132. }
  133. void shark_uart_write_log(char *buffer){
  134. int len = strlen(buffer);
  135. shark_uart_t *uart = (_shark_uart+SHARK_UART0);
  136. if (len > byte_queue_get_free(&uart->tx_queue)){
  137. return;
  138. }
  139. byte_queue_write(&uart->tx_queue, (const u8 *)buffer, len);
  140. shark_uart_dma_tx(uart);
  141. }
  142. static void shark_uart_tx_dma_init(shark_uart_t *uart){
  143. dma_parameter_struct dma_init_struct;
  144. rcu_periph_clock_enable(SHARK_UART0_tx_dma_clk);
  145. dma_deinit(SHARK_UART0_tx_dma, uart->tx_dma_ch);
  146. dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
  147. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  148. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  149. dma_init_struct.periph_addr = (u32) &USART_DATA(uart->uart_com);
  150. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  151. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  152. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  153. dma_init(SHARK_UART0_tx_dma, uart->tx_dma_ch, &dma_init_struct);
  154. dma_circulation_disable(SHARK_UART0_tx_dma, uart->tx_dma_ch);
  155. dma_memory_to_memory_disable(SHARK_UART0_tx_dma, uart->tx_dma_ch);
  156. usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
  157. #if 0
  158. if (uart->tx_dma_ch == DMA_CH1) {
  159. nvic_irq_enable(DMA_Channel1_2_IRQn ,4, 0);
  160. }else {
  161. nvic_irq_enable(DMA_Channel3_4_IRQn ,4, 0);
  162. }
  163. dma_interrupt_enable(uart->tx_dma_ch, DMA_INT_FTF);
  164. #endif
  165. }
  166. #if ENABLE_RX_DMA==1
  167. static void shark_uart_rx_dma_init(shark_uart_t *uart){
  168. dma_parameter_struct dma_init_struct;
  169. rcu_periph_clock_enable(SHARK_UART0_rx_dma_clk);
  170. dma_deinit(SHARK_UART0_rx_dma, uart->rx_dma_ch);
  171. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  172. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  173. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
  174. dma_init_struct.memory_addr = (u32)uart->rx_queue.buffer;
  175. dma_init_struct.number = uart->rx_queue.buffer_len;
  176. dma_init_struct.periph_addr = (u32) &USART_DATA(uart->uart_com);
  177. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  178. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
  179. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  180. dma_init(SHARK_UART0_rx_dma, uart->rx_dma_ch, &dma_init_struct);
  181. dma_circulation_enable(SHARK_UART0_rx_dma, uart->rx_dma_ch);
  182. dma_memory_to_memory_disable(SHARK_UART0_rx_dma, uart->rx_dma_ch);
  183. dma_channel_enable(SHARK_UART0_rx_dma, uart->rx_dma_ch);
  184. usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
  185. }
  186. #endif
  187. static void shark_uart_pin_init(shark_uart_t *uart){
  188. rcu_periph_clock_enable(SHARK_UART0_clk);
  189. rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
  190. rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
  191. rcu_periph_clock_enable(RCU_AF);
  192. gpio_init(SHARK_UART0_tx_port, GPIO_MODE_AF_PP,GPIO_OSPEED_50MHZ,SHARK_UART0_tx_pin);
  193. gpio_init(SHARK_UART0_rx_port, GPIO_MODE_IN_FLOATING,GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
  194. }
  195. static void shark_uart_pin_deinit(shark_uart_t *uart){
  196. if (_uart_index(uart->uart_com) == SHARK_UART0) {
  197. gpio_init(SHARK_UART0_tx_port, GPIO_MODE_IN_FLOATING,GPIO_OSPEED_50MHZ,SHARK_UART0_tx_pin);
  198. gpio_init(SHARK_UART0_rx_port, GPIO_MODE_IN_FLOATING,GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
  199. }
  200. }
  201. static void shark_uart_device_init(shark_uart_t *uart){
  202. usart_deinit(uart->uart_com);
  203. usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
  204. usart_word_length_set(uart->uart_com, USART_WL_8BIT);
  205. usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
  206. usart_parity_config(uart->uart_com, USART_PM_NONE);
  207. usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
  208. usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
  209. usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
  210. usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
  211. #if ENABLE_RX_DMA==0
  212. usart_lin_mode_disable(uart->uart_com);
  213. usart_receiver_timeout_disable(uart->uart_com);
  214. usart_interrupt_enable(uart->uart_com,USART_INT_RBNE);
  215. #endif
  216. }
  217. static void shark_uart_task(void *args)
  218. {
  219. shark_uart_t *uart = (shark_uart_t *)args;
  220. while(1) {
  221. if(uart->uart_com != 0) {
  222. shark_uart_rx(uart);
  223. shark_uart_dma_tx(uart);
  224. }
  225. co_task_yield();
  226. }
  227. }
  228. void shark_uart_flush(void){
  229. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  230. if (uart->uart_com != 0) {
  231. while(!byte_queue_empty(&uart->tx_queue)) {
  232. shark_uart_dma_tx(uart);
  233. }
  234. }
  235. }
  236. #if 0
  237. void DMA_Channel1_2_IRQHandler(void){
  238. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  239. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  240. shark_uart_dma_tx(uart);
  241. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  242. }
  243. }
  244. void DMA_Channel3_4_IRQHandler(void){
  245. shark_uart_t *uart = _shark_uart + SHARK_UART1;
  246. if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
  247. shark_uart_dma_tx(uart);
  248. dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
  249. }
  250. }
  251. #endif
  252. static u8 *tx_cache_addr(uart_enum_t uart_no){
  253. return shark_uart0_tx_cache;
  254. }
  255. static u8 *rx_cache_addr(uart_enum_t uart_no){
  256. return shark_uart0_rx_cache;
  257. }
  258. void shark_uart_deinit(uart_enum_t uart_no){
  259. shark_uart_t *uart = _shark_uart + uart_no;
  260. if (uart->uart_com != 0) {
  261. usart_disable(uart->uart_com);
  262. usart_deinit(uart->uart_com);
  263. rcu_periph_clock_disable(SHARK_UART0_clk);
  264. dma_channel_disable(SHARK_UART0_rx_dma, uart->rx_dma_ch);
  265. dma_channel_disable(SHARK_UART0_tx_dma, uart->tx_dma_ch);
  266. rcu_periph_clock_disable(SHARK_UART0_tx_dma_clk);
  267. rcu_periph_clock_disable(SHARK_UART0_rx_dma_clk);
  268. shark_uart_pin_deinit(uart);
  269. }
  270. #if ENABLE_RX_DMA==0
  271. nvic_irq_disable(SHARK_UART0_irq);
  272. #endif
  273. }
  274. bool shark_uart_timeout(void){
  275. #if UART_NUM==2
  276. return (_shark_uart[0].uart_no_data && _shark_uart[1].uart_no_data)?TRUE:FALSE;
  277. #else
  278. return (_shark_uart[0].uart_no_data)?TRUE:FALSE;
  279. #endif
  280. }
  281. void shark_uart_init(uart_enum_t uart_no)
  282. {
  283. shark_uart_t *uart = _shark_uart + uart_no;
  284. uart->escape = false;
  285. uart->rx_length = 0;
  286. uart->tx_length = 0;
  287. uart->uart_com = SHARK_UART0_com;
  288. circle_buffer_init(&uart->rx_queue, rx_cache_addr(uart_no), SHARK_UART_RX_MEM_SIZE);
  289. byte_queue_init(&uart->tx_queue,tx_cache_addr(uart_no), SHARK_UART_TX_MEM_SIZE);
  290. uart->rx_dma_ch = SHARK_UART0_rx_dma_ch;
  291. uart->tx_dma_ch = SHARK_UART0_tx_dma_ch;
  292. shark_uart_pin_init(uart);
  293. shark_uart_device_init(uart);
  294. #if ENABLE_RX_DMA==1
  295. shark_uart_rx_dma_init(uart);
  296. #endif
  297. shark_uart_tx_dma_init(uart);
  298. usart_enable(uart->uart_com);
  299. co_task_create(shark_uart_task, uart, 256);
  300. #if ENABLE_RX_DMA==0
  301. nvic_irq_enable(SHARK_UART0_irq, 3, 0);
  302. #endif
  303. uart->uart_no_data = false;
  304. }
  305. #if ENABLE_RX_DMA==0
  306. void USART3_IRQHandler(void){
  307. if(usart_flag_get(USART0, USART_FLAG_RBNE) == SET){
  308. shark_uart_t *uart = _shark_uart + SHARK_UART0;
  309. u8 c = usart_data_receive(USART0);
  310. circle_put_one_data(&uart->rx_queue, c);
  311. }
  312. }
  313. #endif
  314. static void shark_uart_write_byte_esc(shark_uart_t *uart, u8 value)
  315. {
  316. switch (value) {
  317. case CH_START:
  318. shark_uart_write_byte(uart, CH_ESC);
  319. value = CH_ESC_START;
  320. break;
  321. case CH_END:
  322. shark_uart_write_byte(uart, CH_ESC);
  323. value = CH_ESC_END;
  324. break;
  325. case CH_ESC:
  326. shark_uart_write_byte(uart, CH_ESC);
  327. value = CH_ESC_ESC;
  328. break;
  329. }
  330. shark_uart_write_byte(uart, value);
  331. }
  332. static void shark_uart_write_esc(shark_uart_t *uart, const u8 *buff, u16 length)
  333. {
  334. const u8 *buff_end;
  335. for (buff_end = buff + length; buff < buff_end; buff++) {
  336. shark_uart_write_byte_esc(uart, *buff);
  337. }
  338. }
  339. static void shark_uart_tx_start(shark_uart_t *uart)
  340. {
  341. shark_uart_write_byte(uart, CH_START);
  342. uart->tx_crc16 = 0;
  343. }
  344. static void shark_uart_tx_continue(shark_uart_t *uart, const void *buff, u16 length)
  345. {
  346. shark_uart_write_esc(uart, (const u8 *) buff, length);
  347. uart->tx_crc16 = crc16_update(uart->tx_crc16, (const u8 *) buff, length);
  348. }
  349. static void shark_uart_tx_end(shark_uart_t *uart)
  350. {
  351. shark_uart_write_esc(uart, (u8 *)&uart->tx_crc16, sizeof(uart->tx_crc16));
  352. shark_uart_write_byte(uart, CH_END);
  353. }
  354. void shark_uart_write_frame(uart_enum_t uart_no, uint8_t *bytes, int len){
  355. shark_uart_t *uart = _shark_uart + uart_no;
  356. shark_uart_tx_start(uart);
  357. shark_uart_tx_continue(uart, bytes, len);
  358. shark_uart_tx_end(uart);
  359. }
  360. void shark_uart_frame_start(uart_enum_t uart_no, uint8_t *bytes, int len){
  361. shark_uart_t *uart = _shark_uart + uart_no;
  362. shark_uart_tx_start(uart);
  363. shark_uart_tx_continue(uart, bytes, len);
  364. }
  365. void shark_uart_frame_continue(uart_enum_t uart_no, uint8_t *bytes, int len){
  366. shark_uart_t *uart = _shark_uart + uart_no;
  367. shark_uart_tx_continue(uart, bytes, len);
  368. }
  369. void shark_uart_frame_end(uart_enum_t uart_no){
  370. shark_uart_tx_end(_shark_uart + uart_no);
  371. }
  372. void shark_uart_write_bytes(uart_enum_t uart_no, u8 *buff, u16 size){
  373. shark_uart_write(_shark_uart + uart_no, buff, size);
  374. }
  375. int fputc(int c, FILE *fp){
  376. shark_uart_write_byte(_shark_uart+SHARK_UART0, (u8)c);
  377. return 1;
  378. }