MC100/Applications/bsp/adc.c

#include "bsp/bsp.h"
#include "bsp/adc.h"
#include "libs/utils.h"
#include "os/os_task.h"
#include "libs/logger.h"
#include "math/fast_math.h"

#define REG_CHAN_DMA 1

#ifdef REG_CHAN_DMA
#ifndef MC100_HW_V1
#define ADC01_NUM 7
#define ADC2_NUM 0
#else
#define ADC01_NUM (8)
#define ADC2_NUM 4
#endif
#define REG_CHAN_NUM (ADC01_NUM + ADC2_NUM)
s16 adc_buffer[REG_CHAN_NUM];
float vref_adc = 1408.0f;
float vref_5v_adc = 2047.0f;

#define VREF_ADC_DATA 1509.0F //1498, 1.21/3.3*4095

static void adc01_dma_init(void)
{
    dma_parameter_struct dma_init_struct;
    rcu_periph_clock_enable(RCU_DMA0);

    dma_deinit(DMA0, DMA_CH0);
    dma_init_struct.direction    = DMA_PERIPHERAL_TO_MEMORY;
    dma_init_struct.memory_addr  = (uint32_t)adc_buffer;
    dma_init_struct.memory_inc   = DMA_MEMORY_INCREASE_ENABLE;
    dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
    dma_init_struct.number       = ADC01_NUM;
    dma_init_struct.periph_addr  = (uint32_t)(&ADC_RDATA(ADC0));
    dma_init_struct.periph_inc   = DMA_PERIPH_INCREASE_DISABLE;
    dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
    dma_init_struct.priority     = DMA_PRIORITY_ULTRA_HIGH;
    dma_init(DMA0, DMA_CH0, &dma_init_struct);
    dma_circulation_enable(DMA0, DMA_CH0);
    dma_memory_to_memory_disable(DMA0, DMA_CH0);

    dma_channel_enable(DMA0, DMA_CH0);
}

#ifdef MC100_HW_V1
static void adc2_dma_init(void)
{
    dma_parameter_struct dma_init_struct;
    rcu_periph_clock_enable(RCU_DMA1);

    dma_deinit(DMA1, DMA_CH4);
    dma_init_struct.direction    = DMA_PERIPHERAL_TO_MEMORY;
    dma_init_struct.memory_addr  = (uint32_t)(adc_buffer + ADC01_NUM);
    dma_init_struct.memory_inc   = DMA_MEMORY_INCREASE_ENABLE;
    dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
    dma_init_struct.number       = ADC2_NUM;
    dma_init_struct.periph_addr  = (uint32_t)(&ADC_RDATA(ADC2));
    dma_init_struct.periph_inc   = DMA_PERIPH_INCREASE_DISABLE;
    dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
    dma_init_struct.priority     = DMA_PRIORITY_ULTRA_HIGH;
    dma_init(DMA1, DMA_CH4, &dma_init_struct);
    dma_circulation_enable(DMA1, DMA_CH4);
    dma_memory_to_memory_disable(DMA1, DMA_CH4);

    dma_channel_enable(DMA1, DMA_CH4);
}
#endif

#endif

static void adc0_init(void){
    /* config ADC clock */
    rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV4); //APB2 clk 120M, adc clk 30M

	rcu_periph_clock_enable(RCU_ADC0);

	adc_deinit(ADC0);
	
	adc_mode_config(ADC_DAUL_INSERTED_PARALLEL);

    adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
    adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE);

    /* configure ADC data alignment */
    adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT);
	
    /* configure ADC inserted channel length */
    adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 1);

    //adc_inserted_channel_config(ADC0, 0, U_PHASE_I_CHAN, ADC_SAMPLE_TIME);
#ifdef U_PHASE_I_CHAN
	adc_update_insert_sample_time(ADC0, U_PHASE_I_CHAN, ADC_SAMPLE_TIME);
#endif
#ifdef V_PHASE_I_CHAN	
	adc_update_insert_sample_time(ADC0, V_PHASE_I_CHAN, ADC_SAMPLE_TIME);
#endif
#ifdef W_PHASE_I_CHAN	
	adc_update_insert_sample_time(ADC0, W_PHASE_I_CHAN, ADC_SAMPLE_TIME);
#endif

#ifdef CONFIG_HW_MUTISAMPLE
	adc_oversample_mode_config(ADC0, ADC_OVERSAMPLING_ALL_CONVERT, CONFIG_HW_MUTISAMPLE_SHIFT, CONFIG_HW_MUTISAMPLE);
	adc_oversample_mode_enable(ADC0);
#endif
    /* configure ADC inserted channel trigger */
    adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC_TRIGGER_PHASE);

    /* ADC external trigger enable */
    adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE);

#ifdef REG_CHAN_DMA
    /* configure ADC regular channel */
    adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, ADC01_NUM);
#ifndef MC100_HW_V1
    adc_regular_channel_config(ADC0, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
    adc_regular_channel_config(ADC0, 1, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 2, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 3, V_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 4, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 5, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 6, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
#else
	adc_regular_channel_config(ADC0, 0, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 1, MOS_TEMP1_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 2, VBUS_I_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 3, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 4, V_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 5, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 6, ADC_CHANNEL_10, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC0, 7, ADC_CHANNEL_17, ADC_REGCHAN_SAMPLE_TIME);
	adc_tempsensor_vrefint_enable();
	adc_buffer[7] = VREF_ADC_DATA; //1.21/3.3*4095
#endif
#endif
    /* configure ADC regular channel trigger */
    adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
    adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE);
#ifdef REG_CHAN_DMA
	adc_dma_mode_enable(ADC0);
#endif
    /* enable ADC interface */
    adc_enable(ADC0);

	delay_ms(1);
    /* ADC calibration and reset calibration */
    adc_calibration_enable(ADC0);

	nvic_irq_enable(ADC0_1_IRQn, ADC_IRQ_PRIORITY, 0);

	adc_disable_ext_trigger();
#ifdef REG_CHAN_DMA
	adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL);
#endif
}

static void adc1_init(void){

	rcu_periph_clock_enable(RCU_ADC1);
	adc_deinit(ADC1);

	adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
	adc_special_function_config(ADC1, ADC_SCAN_MODE, ENABLE);

    /* configure ADC data alignment */
    adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT);
	
    /* configure ADC inserted channel length */
    adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 1);

    /* configure ADC inserted channel */
#ifdef U_PHASE_I_CHAN
	adc_update_insert_sample_time(ADC1, U_PHASE_I_CHAN, ADC_SAMPLE_TIME);
#endif
#ifdef V_PHASE_I_CHAN	
	adc_update_insert_sample_time(ADC1, V_PHASE_I_CHAN, ADC_SAMPLE_TIME);
#endif
#ifdef W_PHASE_I_CHAN	
	adc_update_insert_sample_time(ADC1, W_PHASE_I_CHAN, ADC_SAMPLE_TIME);
#endif

#ifdef CONFIG_HW_MUTISAMPLE
	adc_oversample_mode_config(ADC1, ADC_OVERSAMPLING_ALL_CONVERT, CONFIG_HW_MUTISAMPLE_SHIFT, CONFIG_HW_MUTISAMPLE);
	adc_oversample_mode_enable(ADC1);
#endif

    /* ADC external trigger enable */
	adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL, ADC_TRIGGER_NONE);
    adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE);

    /* enable ADC interface */
    adc_enable(ADC1);
	delay_ms(1);
    /* ADC calibration and reset calibration */
    adc_calibration_enable(ADC1);
    /* ADC software trigger enable */
    adc_software_trigger_enable(ADC1, ADC_INSERTED_CHANNEL);	
}

#ifdef MC100_HW_V1
static void adc2_init(void){

	rcu_periph_clock_enable(RCU_ADC2);

	adc_deinit(ADC2);
	
    adc_special_function_config(ADC2, ADC_CONTINUOUS_MODE, ENABLE);
    adc_special_function_config(ADC2, ADC_SCAN_MODE, ENABLE);

    /* configure ADC data alignment */
    adc_data_alignment_config(ADC2, ADC_DATAALIGN_RIGHT);
#ifdef CONFIG_HW_MUTISAMPLE
	adc_oversample_mode_config(ADC2, ADC_OVERSAMPLING_ALL_CONVERT, CONFIG_HW_MUTISAMPLE_SHIFT, CONFIG_HW_MUTISAMPLE);
	adc_oversample_mode_enable(ADC2);
#endif

#ifdef REG_CHAN_DMA
    /* configure ADC regular channel */
    adc_channel_length_config(ADC2, ADC_REGULAR_CHANNEL, ADC2_NUM);
    adc_regular_channel_config(ADC2, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC2, 1, ACC_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
    adc_regular_channel_config(ADC2, 2, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
	adc_regular_channel_config(ADC2, 3, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
#endif
    /* configure ADC regular channel trigger */
    adc_external_trigger_source_config(ADC2, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
    adc_external_trigger_config(ADC2, ADC_REGULAR_CHANNEL, ENABLE);
#ifdef REG_CHAN_DMA
	adc_dma_mode_enable(ADC2);
#endif
    /* enable ADC interface */
    adc_enable(ADC2);

	delay_ms(1);
    /* ADC calibration and reset calibration */
    adc_calibration_enable(ADC2);

#ifdef REG_CHAN_DMA
	adc_software_trigger_enable(ADC2, ADC_REGULAR_CHANNEL);
#endif
}
#endif

static void adc_gpio_init(void) {

	rcu_periph_clock_enable(RCU_AF);
		/* configure ADC pin, current sampling -- ADC_IN1(PA1) ADC_IN12(PC2) ADC_IN13(PC3) */
#ifdef U_PHASE_ADC_GROUP
		rcu_periph_clock_enable(U_PHASE_ADC_RCU);
		gpio_init(U_PHASE_ADC_GROUP, U_PHASE_ADC_MODE, GPIO_OSPEED_50MHZ, U_PHASE_ADC_PIN);
#endif
#ifdef V_PHASE_ADC_GROUP
		rcu_periph_clock_enable(V_PHASE_ADC_RCU);
		gpio_init(V_PHASE_ADC_GROUP, V_PHASE_ADC_MODE, GPIO_OSPEED_50MHZ, V_PHASE_ADC_PIN);
#endif
#ifdef W_PHASE_ADC_GROUP
		rcu_periph_clock_enable(W_PHASE_ADC_RCU);
		gpio_init(W_PHASE_ADC_GROUP, W_PHASE_ADC_MODE, GPIO_OSPEED_50MHZ, W_PHASE_ADC_PIN);
#endif

#ifdef VBUS_V_ADC_GROUP
	rcu_periph_clock_enable(VBUS_V_ADC_RCU);
	/* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
	gpio_init(VBUS_V_ADC_GROUP, VBUS_V_ADC_MODE, GPIO_OSPEED_50MHZ, VBUS_V_ADC_PIN);
#endif

#ifdef VBUS_I_ADC_GROUP
	rcu_periph_clock_enable(VBUS_I_ADC_RCU);
	/* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
	gpio_init(VBUS_I_ADC_GROUP, VBUS_I_ADC_MODE, GPIO_OSPEED_50MHZ, VBUS_I_ADC_PIN);
#endif


#ifdef ACC_V_ADC_GROUP
	rcu_periph_clock_enable(ACC_V_ADC_RCU);
	/* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
	gpio_init(ACC_V_ADC_GROUP, ACC_V_ADC_MODE, GPIO_OSPEED_50MHZ, ACC_V_ADC_PIN);
#endif

#ifdef THROTTLE_V_ADC_GROUP
	rcu_periph_clock_enable(THROTTLE_V_ADC_RCU);
	/* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
	gpio_init(THROTTLE_V_ADC_GROUP, THROTTLE_V_ADC_MODE, GPIO_OSPEED_50MHZ, THROTTLE_V_ADC_PIN);
#endif

#ifdef TEMP_V_ADC_GROUP
	rcu_periph_clock_enable(TEMP_V_ADC_GROUP);
	/* configure ADC pin, temperature sampling -- ADC_IN11(PC1) */
	gpio_init(TEMP_V_ADC_GROUP, TEMP_V_ADC_MODE, GPIO_OSPEED_50MHZ, TEMP_V_ADC_PIN);
#endif


#ifdef U_VOL_ADC_GROUP
	rcu_periph_clock_enable(U_VOL_ADC_RCU);
	gpio_init(U_VOL_ADC_GROUP, U_VOL_ADC_MODE, GPIO_OSPEED_50MHZ, U_VOL_ADC_PIN);
#endif
#ifdef V_VOL_ADC_GROUP
	rcu_periph_clock_enable(V_VOL_ADC_RCU);
	gpio_init(V_VOL_ADC_GROUP, V_VOL_ADC_MODE, GPIO_OSPEED_50MHZ, V_VOL_ADC_PIN);
#endif
#ifdef W_VOL_ADC_GROUP
	rcu_periph_clock_enable(W_VOL_ADC_RCU);
	gpio_init(W_VOL_ADC_GROUP, W_VOL_ADC_MODE, GPIO_OSPEED_50MHZ, W_VOL_ADC_PIN);
#endif
#ifdef MOS_TEMP_ADC_CHAN
	rcu_periph_clock_enable(MOS_TEMP_ADC_RCU);
	gpio_init(MOS_TEMP_ADC_CHAN, MOS_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOS_TEMP_ADC_PIN);
#endif
#ifdef MOS_TEMP1_ADC_CHAN
	rcu_periph_clock_enable(MOS_TEMP1_ADC_RCU);
	gpio_init(MOS_TEMP1_ADC_CHAN, MOS_TEMP1_ADC_MODE, GPIO_OSPEED_50MHZ, MOS_TEMP1_ADC_PIN);
#endif

#ifdef MOTOR_TEMP_ADC_CHAN
	rcu_periph_clock_enable(MOTOR_TEMP_ADC_RCU);
	gpio_init(MOTOR_TEMP_ADC_CHAN, MOTOR_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOTOR_TEMP_ADC_PIN);
#endif

}

void adc_init(void) {
	adc_gpio_init();
#ifdef REG_CHAN_DMA	
	adc01_dma_init();
#ifdef MC100_HW_V1
	adc2_dma_init();
#endif
#endif
	adc0_init();
	adc1_init();
#ifdef MC100_HW_V1
	adc2_init();
#endif
	adc_current_sample_config(0);
}

void adc_set_vref_calc(float v) {
	vref_adc = v;
}

void adc_set_5vref_calc(float v) {
	vref_5v_adc = v;
}

#define VREF_COMP_LFP_CEOF (0.01F)
static float vref_compestion_filter = 1.0f;
#define VREF_COMPESTION() (vref_adc/(float)adc_buffer[7])
void adc_3v3ref_filter(void) {
	float value = VREF_COMPESTION();
	LowPass_Filter(vref_compestion_filter, value, VREF_COMP_LFP_CEOF);
}

float adc_vref_compesion(void) {
	return vref_compestion_filter;
}

static float vref_5v_compestion_filter = 1.0f;
#define VREF_5V_COMPESTION() (vref_5v_adc/(float)adc_buffer[1])
void adc_5vref_filter(void) {
	float value = VREF_5V_COMPESTION();
	LowPass_Filter(vref_5v_compestion_filter, value, VREF_COMP_LFP_CEOF);
}

float adc_5vref_compesion(void) {
	return vref_5v_compestion_filter;
}

void adc_vref_filter(void) {
	adc_3v3ref_filter();
	adc_5vref_filter();
}

u16 adc_get_vbus(void) {
#ifdef MC100_HW_V1
	return (float)adc_buffer[ADC01_NUM + 0] * VREF_COMPESTION();
#else
	return adc_buffer[0];
#endif
}

u16 adc_get_acc(void) {
#ifdef MC100_HW_V1
	return (float)adc_buffer[ADC01_NUM + 1] * VREF_COMPESTION();
#else
	return adc_get_vbus();
#endif
}

u16 adc_get_ibus(void) {
#ifdef MC100_HW_V1
	return (float)adc_buffer[2] * VREF_5V_COMPESTION();
#else
	return 0;
#endif
}

u16 adc_get_throttle(void) {
#ifdef MC100_HW_V1
	return adc_buffer[ADC01_NUM + 2] * VREF_COMPESTION();
#else
	return adc_buffer[1];
#endif
}

void adc_get_uvw_phaseV(u16 *uvw) {
	int offset = 0;
#ifdef MC100_HW_V1
	offset = 1;
#endif
	uvw[0] = adc_buffer[2 + offset];
	uvw[1] = adc_buffer[3 + offset];
	uvw[2] = adc_buffer[4 + offset];
}

u16 adc_get_mos_temp(void) {
#ifdef MC100_HW_V1
	return adc_buffer[0];
#else
	return adc_buffer[5];
#endif
}

u16 adc_get_mos_temp2(void) {
#ifdef MC100_HW_V1
	return adc_buffer[1];
#else
	return adc_get_mos_temp();
#endif
}


u16 adc_get_motor_temp(void) {
#ifdef MC100_HW_V1
	return adc_buffer[ADC01_NUM + 3];
#else
	return adc_buffer[6];
#endif
}

u16 adc_get_vref(void) {
	return adc_buffer[7];
}

u16 adc_get_5v_ref(void) {
	return adc_buffer[1];
}

void adc_start_convert(void) {
	int drop = 2;
    /* clear the ADC flag */
    adc_flag_clear(ADC0, ADC_FLAG_EOIC);
    adc_flag_clear(ADC1, ADC_FLAG_EOIC);

	adc_enable_ext_trigger();
	while(drop-- > 0) {
		while (adc_flag_get(ADC0, ADC_FLAG_EOIC) == RESET);
		adc_flag_clear(ADC0, ADC_FLAG_EOIC);
	}
    /* enable ADC interrupt */

	adc_interrupt_enable(ADC0, ADC_INT_EOIC);

	adc_update_ext_trigger(ADC_TRIGGER_PHASE);
}

void adc_stop_convert(void) {
	adc_disable_ext_trigger();
    /* disable ADC interrupt */

	adc_interrupt_disable(ADC0, ADC_INT_EOIC);

    /* clear the ADC flag */
    adc_flag_clear(ADC0, ADC_FLAG_EOIC);
	adc_flag_clear(ADC1, ADC_FLAG_EOIC);
}


s32 adc_sample_regular_channel(int channel, int times) {
#ifndef REG_CHAN_DMA
	u32 adc_device = ADC0;
	int value = 0;
	int count = 0;
	int min = 0xFFFFF;
	int max = -0xFFFFF;
	u64 start_time;
	adc_channel_length_config(adc_device, ADC_REGULAR_CHANNEL, 1);
	adc_regular_channel_config(adc_device, 0, channel, ADC_REGCHAN_SAMPLE_TIME);
	while(count < times){
restart:		
		start_time = shark_get_mseconds();
		adc_software_trigger_enable(adc_device, ADC_REGULAR_CHANNEL);
    	while(SET != adc_flag_get(adc_device, ADC_FLAG_EOC)){
			if (shark_get_mseconds() - start_time >= 2){
				goto restart;
			}
		};
    	int one = adc_regular_data_read(adc_device);
		adc_flag_clear(adc_device, ADC_FLAG_EOC);		
		value += (one & 0xFFF);
		count ++;
		if (one > max){
			max = one;
		}
		if (one < min) {
			min = one;
		}
	}
	if (times <= 2) {
		return value/times;
	}
	return (value - min - max)/(times-2);
#else
	return 0;
#endif
}