MC100/Applications/bsp/adc.h

#ifndef _ADC_H__
#define _ADC_H__
#include "bsp/bsp.h"
#include "os/os_types.h"

/*
inserted ADC 由timer0 ch3触发，
注意：adc所有外部触发都是下降沿触发 
*/

#ifdef GD32_FOC_DEMO
#define U_PHASE_I_CHAN  ADC_CHANNEL_1
#define V_PHASE_I_CHAN  ADC_CHANNEL_12
#define W_PHASE_I_CHAN  ADC_CHANNEL_13

#define MOTOR_TEMP_CHAN ADC_CHANNEL_11
#define VBUS_V_CHAN 	ADC_CHANNEL_0
#define THROTTLE_CHAN   ADC_CHANNEL_2 
#else
#define MOTOR_TEMP_CHAN ADC_CHANNEL_0
#define THROTTLE_CHAN ADC_CHANNEL_1 //转把信号
#define VBUS_V_CHAN 	ADC_CHANNEL_2
#define W_PHASE_V_CHAN  ADC_CHANNEL_3
#define V_PHASE_V_CHAN  ADC_CHANNEL_4
#define U_PHASE_V_CHAN  ADC_CHANNEL_5
#define W_PHASE_I_CHAN  ADC_CHANNEL_6
#define V_PHASE_I_CHAN  ADC_CHANNEL_7
#define U_PHASE_I_CHAN  ADC_CHANNEL_8
#define VBUS_I_CHAN     ADC_CHANNEL_9
#endif
#define ISQ2_OFFSET 10
#define ISO3_OFFSET 15
#define IL_OFFSET   20

#define ADC_SAMPLE_TIME ADC_SAMPLETIME_7POINT5
#define ADC_TRIGGER_PHASE ADC0_1_EXTTRIG_INSERTED_T0_CH3
#define ADC_TRIGGER_PHASE2 ADC0_1_EXTTRIG_INSERTED_T1_CH0
#define ADC_TRIGGER_NONE  ADC0_1_2_EXTTRIG_INSERTED_NONE
#define ADC_TRIGGER_VBUS ADC0_1_EXTTRIG_INSERTED_T1_CH0


#define PHASE_AB 0
#define PHASE_AC 1
#define PHASE_BC 2

//#define ADC_RANK_CHANNEL(c1, c2, l) ((c1)<<ISQ2_OFFSET | (c2)<<ISO3_OFFSET | (l)<<IL_OFFSET)
#define ADC_RANK_CHANNEL(c)  ((c)<<ISO3_OFFSET | (0)<<IL_OFFSET) 
#define ADC_CALI_RANK_CHANEL(c)  ((c)<<ISO3_OFFSET | (0)<<IL_OFFSET) 

#if 0
static u32 adc0_rank_channels[6] = {
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),//1, B, BC
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),//2, A, AC 
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),//3, C, CA
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),//4, B, BA
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),//5, A, AB
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),//6, C, CB
};
static u32 adc1_rank_channels[6] = {
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),//1, C
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),//2, C
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),//3, A
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),//4, A
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),//5, B
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),//5, B
};


static u32 volatile * adc_phase_reg1[6] = {
	&ADC_IDATA0(ADC0),//1, B
	&ADC_IDATA0(ADC0),//2, A
	&ADC_IDATA0(ADC1),//3, A
	&ADC_IDATA0(ADC0),//4, B
	&ADC_IDATA0(ADC1),//5, B 
	&ADC_IDATA0(ADC1),//6, B
};
static u32 volatile * adc_phase_reg2[6] = {
	&ADC_IDATA0(ADC1),//1, C
	&ADC_IDATA0(ADC1),//2, C
	&ADC_IDATA0(ADC0),//3, C
	&ADC_IDATA0(ADC1),//4, A
	&ADC_IDATA0(ADC0),//5, A
	&ADC_IDATA0(ADC0),//6, C
};

static void __inline adc_phase_current_read(u8 sector, s32 *v1, s32 *v2) {
#if SHUNT_NUM==THREE_SHUNTS_SAMPLE	
	*v1 = (s32)(*adc_phase_reg1[sector]) ;
	*v2 = (s32)(*adc_phase_reg2[sector]) ;
#else
	*v1 =  (ADC_IDATA0(ADC0) & 0xFFF);
	*v2 =  (ADC_IDATA0(ADC1) & 0xFFF);
#endif
}

static void __inline adc_current_sample_config(u8 sector) {
#if SHUNT_NUM==THREE_SHUNTS_SAMPLE
	ADC_ISQ(ADC0) = adc0_rank_channels[sector];
	ADC_ISQ(ADC1) = adc1_rank_channels[sector];
#endif	
}
#else
static u32 adc0_rank_channels[3] = {
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),//0, A, AB
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),//1, A, AC
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),//2, B, BC
};
static u32 adc1_rank_channels[3] = {
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),//0, B
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),//1, C
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),//2, C
};


static u32 volatile * adc_phase_reg1[3] = {
	&ADC_IDATA0(ADC0),//0, A
	&ADC_IDATA0(ADC0),//1, A
	&ADC_IDATA0(ADC0),//2, B
};
static u32 volatile * adc_phase_reg2[3] = {
	&ADC_IDATA0(ADC1),//0, B
	&ADC_IDATA0(ADC1),//1, C
	&ADC_IDATA0(ADC1),//2, C
};

static void __inline adc_phase_current_read(u8 phases, s32 *v1, s32 *v2) {
#if SHUNT_NUM==THREE_SHUNTS_SAMPLE	
	*v1 = (s32)(*adc_phase_reg1[phases]) ;
	*v2 = (s32)(*adc_phase_reg2[phases]) ;
#else
	*v1 =  (ADC_IDATA0(ADC0) & 0xFFF);
	*v2 =  (ADC_IDATA0(ADC1) & 0xFFF);
#endif
}

static void __inline adc_current_sample_config(u8 phases) {
#if SHUNT_NUM==THREE_SHUNTS_SAMPLE
	ADC_ISQ(ADC0) = adc0_rank_channels[phases];
	ADC_ISQ(ADC1) = adc1_rank_channels[phases];
#endif
}
#endif

static void __inline adc_disable_ext_trigger(void) {   
	ADC_CTL1(ADC0) &= ~ADC_CTL1_ETEIC;
#if SHUNT_NUM==ONE_SHUNT_SAMPLE
	ADC_CTL1(ADC1) &= ~ADC_CTL1_ETEIC;
#endif
}

static void __inline adc_enable_ext_trigger(void) {	
	ADC_CTL1(ADC0) |= ADC_CTL1_ETEIC;
#if SHUNT_NUM==ONE_SHUNT_SAMPLE	
	ADC_CTL1(ADC1) |= ADC_CTL1_ETEIC;
#endif
}

/* insert len fixed to 2(IL=1), ISQ2 >> ISQ3*/
static __inline__ void adc_update_insert_sample_rank(u32 adc, u8 channel) {
    ADC_ISQ(adc) = ADC_RANK_CHANNEL(channel);
}

static __inline__ void adc_update_insert_sample_time(u32 adc, uint8_t adc_channel , uint32_t sample_time)
{
    uint32_t sampt;
    /* ADC sampling time config */  
    if(adc_channel < 10U){
        sampt = ADC_SAMPT1(adc);
        sampt &= ~((u32)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
        sampt |= (u32) sample_time << (3U*adc_channel);
        ADC_SAMPT1(adc) = sampt;
    }else if(adc_channel < 18U){
        sampt = ADC_SAMPT0(adc);
        sampt &= ~((u32)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
        sampt |= ((u32)sample_time << (3U*(adc_channel-10U)));
        ADC_SAMPT0(adc) = sampt;
    }
}

static __inline__ bool adc_eoic_interrupt(void)
{
#if SHUNT_NUM==THREE_SHUNTS_SAMPLE
	if (ADC_STAT(ADC0) & ADC_STAT_EOIC){
		return true;
	}
#endif
#if SHUNT_NUM==ONE_SHUNT_SAMPLE
	if (ADC_STAT(ADC1) & ADC_STAT_EOIC){
		return true;
	}
#endif
	return false;
}

static __inline__ void adc_clear_irq_flags(void) {
#if SHUNT_NUM==THREE_SHUNTS_SAMPLE
	ADC_STAT(ADC0) &= ~((u32) ADC_INT_FLAG_EOIC);
	ADC_STAT(ADC1) &= ~((u32) ADC_INT_FLAG_EOIC);
#else
	ADC_STAT(ADC0) &= ~((u32) ADC_INT_FLAG_EOIC);
	ADC_STAT(ADC1) &= ~((u32) ADC_INT_FLAG_EOIC);
#endif
}


static __inline void adc_update_ext_trigger(u32 trigger) {
	adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, trigger);
}

void adc_init(void);
s32 adc_sample_regular_channel(int chan, int times);
void adc_start_convert(void);
void adc_stop_convert(void);

#endif /* _ADC_H__ */