adc.c 18 KB

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  1. #include "bsp/bsp.h"
  2. #include "bsp/adc.h"
  3. #include "libs/utils.h"
  4. #include "os/os_task.h"
  5. #include "libs/logger.h"
  6. #include "math/fast_math.h"
  7. #define REG_CHAN_DMA 1
  8. #ifdef REG_CHAN_DMA
  9. #ifndef CONFIG_BOARD_MCXXX
  10. #define ADC01_NUM 7
  11. #define ADC2_NUM 0
  12. #define VBUS_V_BUFF_IDX 0
  13. #define THROTTLE_BUFF_IDX 1
  14. #define U_VOL_BUFF_IDX 2
  15. #define V_VOL_BUFF_IDX 3
  16. #define W_VOL_BUFF_IDX 4
  17. #define MOS_TEMP_BUFF_IDX 5
  18. #define MOTOR_TEMP_BUFF_IDX 6
  19. #elif (CONFIG_HW_VERSION==2)
  20. #define ADC01_NUM (8)
  21. #define ADC2_NUM 4
  22. #define MOS_TEMP_BUFF_IDX 0
  23. #define VREF5v_BUFF_IDX 1
  24. #define VBUS_I_BUFF_IDX 2
  25. #define U_VOL_BUFF_IDX 3
  26. #define V_VOL_BUFF_IDX 4
  27. #define W_VOL_BUFF_IDX 5
  28. #define VREF_BUFF_IDX 7
  29. #define VBUS_V_BUFF_IDX 8
  30. #define ACC_V_BUFF_IDX 9
  31. #define THROTTLE_BUFF_IDX 10
  32. #define MOTOR_TEMP_BUFF_IDX 11
  33. #elif (CONFIG_HW_VERSION==3)
  34. #define ADC01_NUM (12)
  35. #define ADC2_NUM 5
  36. #define MOS_TEMP_BUFF_IDX 0
  37. #define MOTOR_TEMP_BUFF_IDX 1
  38. #define THROTTLE_BUFF_IDX 2
  39. #define THROTTLE2_BUFF_IDX 3
  40. #define THROTTLE_5V_BUFF_IDX 5
  41. #define THROTTLE2_5V_BUFF_IDX 6
  42. #define U_VOL_BUFF_IDX 7
  43. #define VREF_BUFF_IDX 9
  44. #define VREF5v_BUFF_IDX 11
  45. #define VBUS_V_BUFF_IDX 12
  46. #define ACC_V_BUFF_IDX 13
  47. #define VBUS_I_BUFF_IDX 14
  48. #define V_VOL_BUFF_IDX 15
  49. #define W_VOL_BUFF_IDX 16
  50. #endif
  51. #define REG_CHAN_NUM (ADC01_NUM + ADC2_NUM)
  52. s16 adc_buffer[REG_CHAN_NUM];
  53. float vref_adc = 1408.0f;
  54. float vref_5v_adc = 2047.0f;
  55. #define VREF_ADC_DATA 1509.0F //1498, 1.21/3.3*4095
  56. static void adc01_dma_init(void)
  57. {
  58. dma_parameter_struct dma_init_struct;
  59. rcu_periph_clock_enable(RCU_DMA0);
  60. dma_deinit(DMA0, DMA_CH0);
  61. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  62. dma_init_struct.memory_addr = (uint32_t)adc_buffer;
  63. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  64. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
  65. dma_init_struct.number = ADC01_NUM;
  66. dma_init_struct.periph_addr = (uint32_t)(&ADC_RDATA(ADC0));
  67. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  68. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
  69. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  70. dma_init(DMA0, DMA_CH0, &dma_init_struct);
  71. dma_circulation_enable(DMA0, DMA_CH0);
  72. dma_memory_to_memory_disable(DMA0, DMA_CH0);
  73. dma_channel_enable(DMA0, DMA_CH0);
  74. }
  75. #ifdef CONFIG_BOARD_MCXXX
  76. static void adc2_dma_init(void)
  77. {
  78. dma_parameter_struct dma_init_struct;
  79. rcu_periph_clock_enable(RCU_DMA1);
  80. dma_deinit(DMA1, DMA_CH4);
  81. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  82. dma_init_struct.memory_addr = (uint32_t)(adc_buffer + ADC01_NUM);
  83. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  84. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
  85. dma_init_struct.number = ADC2_NUM;
  86. dma_init_struct.periph_addr = (uint32_t)(&ADC_RDATA(ADC2));
  87. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  88. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
  89. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  90. dma_init(DMA1, DMA_CH4, &dma_init_struct);
  91. dma_circulation_enable(DMA1, DMA_CH4);
  92. dma_memory_to_memory_disable(DMA1, DMA_CH4);
  93. dma_channel_enable(DMA1, DMA_CH4);
  94. }
  95. #endif
  96. #endif
  97. static void adc0_init(void){
  98. /* config ADC clock */
  99. rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV4); //APB2 clk 120M, adc clk 30M
  100. rcu_periph_clock_enable(RCU_ADC0);
  101. adc_deinit(ADC0);
  102. adc_mode_config(ADC_DAUL_INSERTED_PARALLEL);
  103. adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
  104. adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE);
  105. /* configure ADC data alignment */
  106. adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT);
  107. /* configure ADC inserted channel length */
  108. adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 1);
  109. //adc_inserted_channel_config(ADC0, 0, U_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  110. #ifdef U_PHASE_I_CHAN
  111. adc_update_insert_sample_time(ADC0, U_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  112. #endif
  113. #ifdef V_PHASE_I_CHAN
  114. adc_update_insert_sample_time(ADC0, V_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  115. #endif
  116. #ifdef W_PHASE_I_CHAN
  117. adc_update_insert_sample_time(ADC0, W_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  118. #endif
  119. #ifdef CONFIG_HW_MUTISAMPLE
  120. adc_oversample_mode_config(ADC0, ADC_OVERSAMPLING_ALL_CONVERT, CONFIG_HW_MUTISAMPLE_SHIFT, CONFIG_HW_MUTISAMPLE);
  121. adc_oversample_mode_enable(ADC0);
  122. #endif
  123. /* configure ADC inserted channel trigger */
  124. adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC_TRIGGER_PHASE);
  125. /* ADC external trigger enable */
  126. adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE);
  127. #ifdef REG_CHAN_DMA
  128. /* configure ADC regular channel */
  129. adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, ADC01_NUM);
  130. #ifndef CONFIG_BOARD_MCXXX
  131. adc_regular_channel_config(ADC0, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  132. adc_regular_channel_config(ADC0, 1, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  133. adc_regular_channel_config(ADC0, 2, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  134. adc_regular_channel_config(ADC0, 3, V_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  135. adc_regular_channel_config(ADC0, 4, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  136. adc_regular_channel_config(ADC0, 5, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  137. adc_regular_channel_config(ADC0, 6, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  138. #elif (CONFIG_HW_VERSION==2)
  139. adc_regular_channel_config(ADC0, 0, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  140. adc_regular_channel_config(ADC0, 1, MOS_TEMP1_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  141. adc_regular_channel_config(ADC0, 2, VBUS_I_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  142. adc_regular_channel_config(ADC0, 3, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  143. adc_regular_channel_config(ADC0, 4, V_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  144. adc_regular_channel_config(ADC0, 5, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  145. adc_regular_channel_config(ADC0, 6, ADC_CHANNEL_10, ADC_REGCHAN_SAMPLE_TIME);
  146. adc_regular_channel_config(ADC0, 7, ADC_CHANNEL_17, ADC_REGCHAN_SAMPLE_TIME);
  147. adc_tempsensor_vrefint_enable();
  148. adc_buffer[VREF_BUFF_IDX] = VREF_ADC_DATA; //1.21/3.3*4095
  149. #elif (CONFIG_HW_VERSION==3)
  150. adc_regular_channel_config(ADC0, 0, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  151. adc_regular_channel_config(ADC0, 1, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  152. adc_regular_channel_config(ADC0, 2, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  153. adc_regular_channel_config(ADC0, 3, THROTTLE2_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  154. adc_regular_channel_config(ADC0, 4, ZERO_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME); //insert zero vol
  155. adc_regular_channel_config(ADC0, 5, THROTTLE_5V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  156. adc_regular_channel_config(ADC0, 6, THROTTLE2_5V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  157. adc_regular_channel_config(ADC0, 7, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  158. adc_regular_channel_config(ADC0, 8, ZERO_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME); //insert zero vol
  159. adc_regular_channel_config(ADC0, 9, ADC_CHANNEL_17, ADC_REGCHAN_SAMPLE_TIME); //mcu内部vref
  160. adc_regular_channel_config(ADC0, 10, ZERO_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME); //insert zero vol
  161. adc_regular_channel_config(ADC0, 11, DC5V_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  162. adc_tempsensor_vrefint_enable();
  163. adc_buffer[VREF_BUFF_IDX] = VREF_ADC_DATA; //1.21/3.3*4095
  164. #endif
  165. #endif
  166. /* configure ADC regular channel trigger */
  167. adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
  168. adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE);
  169. #ifdef REG_CHAN_DMA
  170. adc_dma_mode_enable(ADC0);
  171. #endif
  172. /* enable ADC interface */
  173. adc_enable(ADC0);
  174. delay_ms(1);
  175. /* ADC calibration and reset calibration */
  176. adc_calibration_enable(ADC0);
  177. nvic_irq_enable(ADC0_1_IRQn, ADC_IRQ_PRIORITY, 0);
  178. adc_disable_ext_trigger();
  179. #ifdef REG_CHAN_DMA
  180. adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL);
  181. #endif
  182. }
  183. static void adc1_init(void){
  184. rcu_periph_clock_enable(RCU_ADC1);
  185. adc_deinit(ADC1);
  186. adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
  187. adc_special_function_config(ADC1, ADC_SCAN_MODE, ENABLE);
  188. /* configure ADC data alignment */
  189. adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT);
  190. /* configure ADC inserted channel length */
  191. adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 1);
  192. /* configure ADC inserted channel */
  193. #ifdef U_PHASE_I_CHAN
  194. adc_update_insert_sample_time(ADC1, U_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  195. #endif
  196. #ifdef V_PHASE_I_CHAN
  197. adc_update_insert_sample_time(ADC1, V_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  198. #endif
  199. #ifdef W_PHASE_I_CHAN
  200. adc_update_insert_sample_time(ADC1, W_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  201. #endif
  202. #ifdef CONFIG_HW_MUTISAMPLE
  203. adc_oversample_mode_config(ADC1, ADC_OVERSAMPLING_ALL_CONVERT, CONFIG_HW_MUTISAMPLE_SHIFT, CONFIG_HW_MUTISAMPLE);
  204. adc_oversample_mode_enable(ADC1);
  205. #endif
  206. /* ADC external trigger enable */
  207. adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL, ADC_TRIGGER_NONE);
  208. adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE);
  209. /* enable ADC interface */
  210. adc_enable(ADC1);
  211. delay_ms(1);
  212. /* ADC calibration and reset calibration */
  213. adc_calibration_enable(ADC1);
  214. /* ADC software trigger enable */
  215. adc_software_trigger_enable(ADC1, ADC_INSERTED_CHANNEL);
  216. }
  217. #ifdef CONFIG_BOARD_MCXXX
  218. static void adc2_init(void){
  219. rcu_periph_clock_enable(RCU_ADC2);
  220. adc_deinit(ADC2);
  221. adc_special_function_config(ADC2, ADC_CONTINUOUS_MODE, ENABLE);
  222. adc_special_function_config(ADC2, ADC_SCAN_MODE, ENABLE);
  223. /* configure ADC data alignment */
  224. adc_data_alignment_config(ADC2, ADC_DATAALIGN_RIGHT);
  225. #ifdef CONFIG_HW_MUTISAMPLE
  226. adc_oversample_mode_config(ADC2, ADC_OVERSAMPLING_ALL_CONVERT, CONFIG_HW_MUTISAMPLE_SHIFT, CONFIG_HW_MUTISAMPLE);
  227. adc_oversample_mode_enable(ADC2);
  228. #endif
  229. #ifdef REG_CHAN_DMA
  230. /* configure ADC regular channel */
  231. adc_channel_length_config(ADC2, ADC_REGULAR_CHANNEL, ADC2_NUM);
  232. #if (CONFIG_HW_VERSION==2)
  233. adc_regular_channel_config(ADC2, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  234. adc_regular_channel_config(ADC2, 1, ACC_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  235. adc_regular_channel_config(ADC2, 2, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  236. adc_regular_channel_config(ADC2, 3, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  237. #elif (CONFIG_HW_VERSION==3)
  238. adc_regular_channel_config(ADC2, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  239. adc_regular_channel_config(ADC2, 1, ACC_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  240. adc_regular_channel_config(ADC2, 2, VBUS_I_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  241. adc_regular_channel_config(ADC2, 3, V_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  242. adc_regular_channel_config(ADC2, 4, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  243. #endif
  244. #endif
  245. /* configure ADC regular channel trigger */
  246. adc_external_trigger_source_config(ADC2, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
  247. adc_external_trigger_config(ADC2, ADC_REGULAR_CHANNEL, ENABLE);
  248. #ifdef REG_CHAN_DMA
  249. adc_dma_mode_enable(ADC2);
  250. #endif
  251. /* enable ADC interface */
  252. adc_enable(ADC2);
  253. delay_ms(1);
  254. /* ADC calibration and reset calibration */
  255. adc_calibration_enable(ADC2);
  256. #ifdef REG_CHAN_DMA
  257. adc_software_trigger_enable(ADC2, ADC_REGULAR_CHANNEL);
  258. #endif
  259. }
  260. #endif
  261. static void adc_gpio_init(void) {
  262. rcu_periph_clock_enable(RCU_AF);
  263. /* configure ADC pin, current sampling -- ADC_IN1(PA1) ADC_IN12(PC2) ADC_IN13(PC3) */
  264. #ifdef U_PHASE_ADC_GROUP
  265. rcu_periph_clock_enable(U_PHASE_ADC_RCU);
  266. gpio_init(U_PHASE_ADC_GROUP, U_PHASE_ADC_MODE, GPIO_OSPEED_50MHZ, U_PHASE_ADC_PIN);
  267. #endif
  268. #ifdef V_PHASE_ADC_GROUP
  269. rcu_periph_clock_enable(V_PHASE_ADC_RCU);
  270. gpio_init(V_PHASE_ADC_GROUP, V_PHASE_ADC_MODE, GPIO_OSPEED_50MHZ, V_PHASE_ADC_PIN);
  271. #endif
  272. #ifdef W_PHASE_ADC_GROUP
  273. rcu_periph_clock_enable(W_PHASE_ADC_RCU);
  274. gpio_init(W_PHASE_ADC_GROUP, W_PHASE_ADC_MODE, GPIO_OSPEED_50MHZ, W_PHASE_ADC_PIN);
  275. #endif
  276. #ifdef VBUS_V_ADC_GROUP
  277. rcu_periph_clock_enable(VBUS_V_ADC_RCU);
  278. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  279. gpio_init(VBUS_V_ADC_GROUP, VBUS_V_ADC_MODE, GPIO_OSPEED_50MHZ, VBUS_V_ADC_PIN);
  280. #endif
  281. #ifdef VBUS_I_ADC_GROUP
  282. rcu_periph_clock_enable(VBUS_I_ADC_RCU);
  283. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  284. gpio_init(VBUS_I_ADC_GROUP, VBUS_I_ADC_MODE, GPIO_OSPEED_50MHZ, VBUS_I_ADC_PIN);
  285. #endif
  286. #ifdef ACC_V_ADC_GROUP
  287. rcu_periph_clock_enable(ACC_V_ADC_RCU);
  288. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  289. gpio_init(ACC_V_ADC_GROUP, ACC_V_ADC_MODE, GPIO_OSPEED_50MHZ, ACC_V_ADC_PIN);
  290. #endif
  291. #ifdef THROTTLE_V_ADC_GROUP
  292. rcu_periph_clock_enable(THROTTLE_V_ADC_RCU);
  293. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  294. gpio_init(THROTTLE_V_ADC_GROUP, THROTTLE_V_ADC_MODE, GPIO_OSPEED_50MHZ, THROTTLE_V_ADC_PIN);
  295. #endif
  296. #ifdef THROTTLE2_V_ADC_GROUP
  297. rcu_periph_clock_enable(THROTTLE2_V_ADC_RCU);
  298. gpio_init(THROTTLE2_V_ADC_GROUP, THROTTLE2_V_ADC_MODE, GPIO_OSPEED_50MHZ, THROTTLE2_V_ADC_PIN);
  299. #endif
  300. #ifdef THROTTLE_5V_ADC_GROUP
  301. rcu_periph_clock_enable(THROTTLE_5V_ADC_RCU);
  302. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  303. gpio_init(THROTTLE_5V_ADC_GROUP, THROTTLE_5V_ADC_MODE, GPIO_OSPEED_50MHZ, THROTTLE_5V_ADC_PIN);
  304. #endif
  305. #ifdef THROTTLE2_5V_ADC_GROUP
  306. rcu_periph_clock_enable(THROTTLE2_5V_ADC_RCU);
  307. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  308. gpio_init(THROTTLE2_5V_ADC_GROUP, THROTTLE2_5V_ADC_MODE, GPIO_OSPEED_50MHZ, THROTTLE2_5V_ADC_PIN);
  309. #endif
  310. #ifdef U_VOL_ADC_GROUP
  311. rcu_periph_clock_enable(U_VOL_ADC_RCU);
  312. gpio_init(U_VOL_ADC_GROUP, U_VOL_ADC_MODE, GPIO_OSPEED_50MHZ, U_VOL_ADC_PIN);
  313. #endif
  314. #ifdef V_VOL_ADC_GROUP
  315. rcu_periph_clock_enable(V_VOL_ADC_RCU);
  316. gpio_init(V_VOL_ADC_GROUP, V_VOL_ADC_MODE, GPIO_OSPEED_50MHZ, V_VOL_ADC_PIN);
  317. #endif
  318. #ifdef W_VOL_ADC_GROUP
  319. rcu_periph_clock_enable(W_VOL_ADC_RCU);
  320. gpio_init(W_VOL_ADC_GROUP, W_VOL_ADC_MODE, GPIO_OSPEED_50MHZ, W_VOL_ADC_PIN);
  321. #endif
  322. #ifdef MOS_TEMP_ADC_GROUP
  323. rcu_periph_clock_enable(MOS_TEMP_ADC_RCU);
  324. gpio_init(MOS_TEMP_ADC_GROUP, MOS_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOS_TEMP_ADC_PIN);
  325. #endif
  326. #ifdef MOS_TEMP1_ADC_GROUP
  327. rcu_periph_clock_enable(MOS_TEMP1_ADC_RCU);
  328. gpio_init(MOS_TEMP1_ADC_GROUP, MOS_TEMP1_ADC_MODE, GPIO_OSPEED_50MHZ, MOS_TEMP1_ADC_PIN);
  329. #endif
  330. #ifdef MOTOR_TEMP_ADC_GROUP
  331. rcu_periph_clock_enable(MOTOR_TEMP_ADC_RCU);
  332. gpio_init(MOTOR_TEMP_ADC_GROUP, MOTOR_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOTOR_TEMP_ADC_PIN);
  333. #endif
  334. #ifdef ZERO_ADC_GROUP
  335. rcu_periph_clock_enable(ZERO_ADC_RCU);
  336. gpio_init(ZERO_ADC_GROUP, ZERO_ADC_MODE, GPIO_OSPEED_50MHZ, ZERO_ADC_PIN);
  337. #endif
  338. }
  339. void adc_init(void) {
  340. adc_gpio_init();
  341. #ifdef REG_CHAN_DMA
  342. adc01_dma_init();
  343. #ifdef CONFIG_BOARD_MCXXX
  344. adc2_dma_init();
  345. #endif
  346. #endif
  347. adc0_init();
  348. adc1_init();
  349. #ifdef CONFIG_BOARD_MCXXX
  350. adc2_init();
  351. #endif
  352. adc_current_sample_config(0);
  353. }
  354. void adc_set_vref_calc(float v) {
  355. vref_adc = v;
  356. }
  357. void adc_set_5vref_calc(float v) {
  358. vref_5v_adc = v;
  359. }
  360. #define VREF_COMP_LFP_CEOF (0.0001F)
  361. static float vref_compestion_filter = 1.0f;
  362. #define VREF_3V3_COMPESTION() (vref_adc/(float)adc_buffer[VREF_BUFF_IDX])
  363. void adc_3v3ref_filter(void) {
  364. float value = VREF_3V3_COMPESTION();
  365. LowPass_Filter(vref_compestion_filter, value, VREF_COMP_LFP_CEOF);
  366. }
  367. float adc_vref_compesion(void) {
  368. return vref_compestion_filter;
  369. }
  370. static float vref_5v_compestion_filter = 1.0f;
  371. #define VREF_5V_COMPESTION() (vref_5v_adc/(float)adc_buffer[VREF5v_BUFF_IDX])
  372. void adc_5vref_filter(void) {
  373. float value = VREF_5V_COMPESTION();
  374. LowPass_Filter(vref_5v_compestion_filter, value, VREF_COMP_LFP_CEOF);
  375. }
  376. float adc_5vref_compesion(void) {
  377. return vref_5v_compestion_filter;
  378. }
  379. void adc_vref_filter(void) {
  380. adc_3v3ref_filter();
  381. adc_5vref_filter();
  382. }
  383. u16 adc_get_vbus(void) {
  384. return (float)adc_buffer[VBUS_V_BUFF_IDX] * VREF_3V3_COMPESTION();
  385. }
  386. u16 adc_get_acc(void) {
  387. #ifdef CONFIG_BOARD_MCXXX
  388. return (float)adc_buffer[ACC_V_BUFF_IDX] * VREF_3V3_COMPESTION();
  389. #else
  390. return adc_get_vbus();
  391. #endif
  392. }
  393. u16 adc_get_ibus(void) {
  394. #ifdef CONFIG_BOARD_MCXXX
  395. return (float)adc_buffer[VBUS_I_BUFF_IDX] * VREF_5V_COMPESTION();
  396. #else
  397. return 0;
  398. #endif
  399. }
  400. u16 adc_get_throttle(void) {
  401. return adc_buffer[THROTTLE_BUFF_IDX] * VREF_3V3_COMPESTION();
  402. }
  403. u16 adc_get_throttle2(void) {
  404. #ifdef THROTTLE2_BUFF_IDX
  405. return adc_buffer[THROTTLE2_BUFF_IDX] * VREF_3V3_COMPESTION();
  406. #else
  407. return adc_get_throttle();
  408. #endif
  409. }
  410. u16 adc_get_thro_5v(void) {
  411. #ifdef THROTTLE_5V_BUFF_IDX
  412. return adc_buffer[THROTTLE_5V_BUFF_IDX] * VREF_3V3_COMPESTION();
  413. #else
  414. return 0;
  415. #endif
  416. }
  417. u16 adc_get_thro2_5v(void) {
  418. #ifdef THROTTLE2_5V_BUFF_IDX
  419. return adc_buffer[THROTTLE2_5V_BUFF_IDX] * VREF_3V3_COMPESTION();
  420. #else
  421. return 0;
  422. #endif
  423. }
  424. void adc_get_uvw_phaseV(u16 *uvw) {
  425. uvw[0] = adc_buffer[U_VOL_BUFF_IDX];
  426. uvw[1] = adc_buffer[V_VOL_BUFF_IDX];
  427. uvw[2] = adc_buffer[W_VOL_BUFF_IDX];
  428. }
  429. u16 adc_get_mos_temp(void) {
  430. return adc_buffer[MOS_TEMP_BUFF_IDX];
  431. }
  432. u16 adc_get_motor_temp(void) {
  433. return adc_buffer[MOTOR_TEMP_BUFF_IDX];
  434. }
  435. u16 adc_get_vref(void) {
  436. #ifdef CONFIG_BOARD_MCXXX
  437. return adc_buffer[VREF_BUFF_IDX];
  438. #else
  439. return 0;
  440. #endif
  441. }
  442. u16 adc_get_5v_ref(void) {
  443. #ifdef CONFIG_BOARD_MCXXX
  444. return adc_buffer[VREF5v_BUFF_IDX];
  445. #else
  446. return 0;
  447. #endif
  448. }
  449. void adc_start_convert(void) {
  450. int drop = 2;
  451. /* clear the ADC flag */
  452. adc_flag_clear(ADC0, ADC_FLAG_EOIC);
  453. adc_flag_clear(ADC1, ADC_FLAG_EOIC);
  454. adc_enable_ext_trigger();
  455. while(drop-- > 0) {
  456. while (adc_flag_get(ADC0, ADC_FLAG_EOIC) == RESET);
  457. adc_flag_clear(ADC0, ADC_FLAG_EOIC);
  458. }
  459. /* enable ADC interrupt */
  460. adc_interrupt_enable(ADC0, ADC_INT_EOIC);
  461. adc_update_ext_trigger(ADC_TRIGGER_PHASE);
  462. }
  463. void adc_stop_convert(void) {
  464. adc_disable_ext_trigger();
  465. /* disable ADC interrupt */
  466. adc_interrupt_disable(ADC0, ADC_INT_EOIC);
  467. /* clear the ADC flag */
  468. adc_flag_clear(ADC0, ADC_FLAG_EOIC);
  469. adc_flag_clear(ADC1, ADC_FLAG_EOIC);
  470. }
  471. s32 adc_sample_regular_channel(int channel, int times) {
  472. #ifndef REG_CHAN_DMA
  473. u32 adc_device = ADC0;
  474. int value = 0;
  475. int count = 0;
  476. int min = 0xFFFFF;
  477. int max = -0xFFFFF;
  478. u64 start_time;
  479. adc_channel_length_config(adc_device, ADC_REGULAR_CHANNEL, 1);
  480. adc_regular_channel_config(adc_device, 0, channel, ADC_REGCHAN_SAMPLE_TIME);
  481. while(count < times){
  482. restart:
  483. start_time = shark_get_mseconds();
  484. adc_software_trigger_enable(adc_device, ADC_REGULAR_CHANNEL);
  485. while(SET != adc_flag_get(adc_device, ADC_FLAG_EOC)){
  486. if (shark_get_mseconds() - start_time >= 2){
  487. goto restart;
  488. }
  489. };
  490. int one = adc_regular_data_read(adc_device);
  491. adc_flag_clear(adc_device, ADC_FLAG_EOC);
  492. value += (one & 0xFFF);
  493. count ++;
  494. if (one > max){
  495. max = one;
  496. }
  497. if (one < min) {
  498. min = one;
  499. }
  500. }
  501. if (times <= 2) {
  502. return value/times;
  503. }
  504. return (value - min - max)/(times-2);
  505. #else
  506. return 0;
  507. #endif
  508. }