MC100/Applications/bsp/n32/pwm.h

#ifndef _PWM_H__
#define _PWM_H__
#include "bsp/bsp.h"
#include "os/os_types.h"

#define TIMER_CHCTL2_CH0EN               BIT(0)              /*!< channel 0 capture/compare function enable */
#define TIMER_CHCTL2_CH0P                BIT(1)              /*!< channel 0 capture/compare function polarity */
#define TIMER_CHCTL2_CH0NEN              BIT(2)              /*!< channel 0 complementary output enable */
#define TIMER_CHCTL2_CH0NP               BIT(3)              /*!< channel 0 complementary output polarity */
#define TIMER_CHCTL2_CH1EN               BIT(4)              /*!< channel 1 capture/compare function enable  */
#define TIMER_CHCTL2_CH1P                BIT(5)              /*!< channel 1 capture/compare function polarity */
#define TIMER_CHCTL2_CH1NEN              BIT(6)              /*!< channel 1 complementary output enable */
#define TIMER_CHCTL2_CH1NP               BIT(7)              /*!< channel 1 complementary output polarity */
#define TIMER_CHCTL2_CH2EN               BIT(8)              /*!< channel 2 capture/compare function enable  */
#define TIMER_CHCTL2_CH2P                BIT(9)              /*!< channel 2 capture/compare function polarity */
#define TIMER_CHCTL2_CH2NEN              BIT(10)             /*!< channel 2 complementary output enable */
#define TIMER_CHCTL2_CH2NP               BIT(11)             /*!< channel 2 complementary output polarity */

#define TIMxCCER_MASK_CH012        ((uint16_t)  (TIMER_CHCTL2_CH0EN|TIMER_CHCTL2_CH0NEN|\
                                                 TIMER_CHCTL2_CH1EN|TIMER_CHCTL2_CH1NEN|\
                                                 TIMER_CHCTL2_CH2EN|TIMER_CHCTL2_CH2NEN))

#define pwm_enable_channel() {TIMER_CHCTL2(pwm_timer) |= TIMxCCER_MASK_CH012;}
#define pwm_disable_channel() {TIMER_CHCTL2(pwm_timer) &= ~TIMxCCER_MASK_CH012;}


#define ch0_update_duty(duty) 	TIMER_CH0CV(pwm_timer) = (uint32_t)duty
#define ch1_update_duty(duty) 	TIMER_CH1CV(pwm_timer) = (uint32_t)duty
#define ch2_update_duty(duty) 	TIMER_CH2CV(pwm_timer) = (uint32_t)duty
#define update_adc_trigger(time) TIMER_CH3CV(pwm_timer) = (uint32_t)time

#ifdef CONFIG_PWM_UV_SWAP
#define pwm_update_duty(dutyA, dutyB, dutyC) \
	do {\
		ch0_update_duty(dutyC);\
		ch1_update_duty(dutyB);\
		ch2_update_duty(dutyA);\
	}while(0)

#else
#define pwm_update_duty(dutyA, dutyB, dutyC) \
	do {\
		ch0_update_duty(dutyA);\
		ch1_update_duty(dutyB);\
		ch2_update_duty(dutyC);\
	}while(0)

#endif

#define pwm_update_2smaples(samp1, sampl2) \
	do { \
		TIMER_CH3CV(pwm_timer) = (uint32_t)samp1; \
	}while(0)


#define pwm_wait_and_clear_updata() \
	do { \
		while ( TIM_GetFlagStatus(pwm_timer, TIM_FLAG_UPDATE) == RESET ); \
		TIM_ClearFlag(pwm_timer, TIM_FLAG_UPDATE); \
	}while(0)

#define pwm_change_t3_mode(m) \
	do { \
		if (((TIMER_CHCTL1(pwm_timer) >> 8)) != m) { \
			TIMER_CHCTL1(pwm_timer) &= (~(uint32_t)TIM_CCMOD2_OC4MD); \
        	TIMER_CHCTL1(pwm_timer) |= (m << 8); \
		} \
	}while(0)

#define pwm_brake_enable(n) \
	do { \
		if (n) { \
			nvic_irq_enable(PWM_BRK_IRQ, EBREAK_IRQ_PRIORITY, 0); \
		}else { \
			nvic_irq_disable(PWM_BRK_IRQ); \
		} \
	}while(0)

#define pwm_up_enable(n) \
	do { \
		if (n) { \
			TIM_ClearFlag(pwm_timer, TIM_FLAG_UPDATE); \
			TIM_ConfigInt(pwm_timer, TIM_INT_UPDATE, ENABLE); \
		}else { \
			TIM_ConfigInt(pwm_timer, TIM_INT_UPDATE, DISABLE); \
			TIM_ClrIntPendingBit(pwm_timer, TIM_INT_UPDATE); \
		} \
	}while(0)

#define get_deadtime() (TIMER_CCHP(pwm_timer) & 0xFF)

void pwm_3phase_init(void);
void pwm_3phase_sides(bool hon, bool lon);
void pwm_start(void);
void pwm_stop(void);
void pwm_turn_on_low_side(void);
void pwm_enable_output(bool enable);
void pwm_update_sample(u32 samp1, u32 samp2, u8 sector);

#endif  /*_PWM_H__*/