pwm.c 8.5 KB

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  1. #include "bsp/bsp.h"
  2. #include "bsp/bsp_driver.h"
  3. #include "os/os_task.h"
  4. #include "libs/logger.h"
  5. /*
  6. 以下主要是在某一相电路无法采集的时候,需要对这相的pwm挖坑处理
  7. timer 分配:
  8. timer0 -> ch0-2 互补pwm
  9. ch4 event, update event 触发DMA(ch3,4)实现CCR的自更新
  10. timer1 -> 触发ADC采样,GD32不支持多channel 或方式触发输出,通过timer1的 ch0 compara 配置 TRGO触发ADC,但是需要在一个PWM周期内触发2次(单电阻)
  11. timer0 master --> timer1 slave/master 确保timer0,1同步开始,同频同相位
  12. DMA 分配:
  13. DMA0 ch4 -> timer0 update event
  14. ch3 -> timer0 chan3 CC event
  15. ch1 -> timer1 update event,需要更新CCR
  16. */
  17. static void _init_pwm_timer(bool);
  18. static void _pwm_gpio_config(void);
  19. #ifndef PWM_BRAKE_GROUP
  20. static void _gpio_brakein_irq_enable(void);
  21. #endif
  22. u16 timer_update_buffer[6] = {0};
  23. void pwm_3phase_init(void){
  24. _pwm_gpio_config();
  25. _init_pwm_timer(true);
  26. }
  27. void pwm_3phase_sides(bool hon, bool lon) {
  28. if (hon && lon) {
  29. return;
  30. }
  31. TIM_DeInit(pwm_timer);
  32. rcu_apb2_periph_clock_enable(PWM_TIM_CLK);
  33. gpio_init(PWM_U_P_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_U_P_PIN);
  34. gpio_init(PWM_V_P_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_V_P_PIN);
  35. gpio_init(PWM_W_P_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_W_P_PIN);
  36. gpio_init(PWM_U_N_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_U_N_PIN);
  37. gpio_init(PWM_V_N_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_V_N_PIN);
  38. gpio_init(PWM_W_N_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_W_N_PIN);
  39. sys_debug("pwm_3phase_sides\n");
  40. /* 开上桥或者下桥之前先关闭下桥或者上桥 */
  41. if (hon) {
  42. _pwm_gpio_config();
  43. _init_pwm_timer(false);
  44. delay_us(10);
  45. pwm_start();
  46. pwm_update_duty(FOC_PWM_Half_Period-200, FOC_PWM_Half_Period-200, FOC_PWM_Half_Period-200);
  47. }else if (lon) {
  48. gpio_bit_write(PWM_U_P_GROUP, PWM_U_P_PIN, RESET);
  49. gpio_bit_write(PWM_V_P_GROUP, PWM_V_P_PIN, RESET);
  50. gpio_bit_write(PWM_W_P_GROUP, PWM_W_P_PIN, RESET);
  51. delay_us(10);
  52. gpio_bit_write(PWM_U_N_GROUP, PWM_U_N_PIN, SET);
  53. gpio_bit_write(PWM_V_N_GROUP, PWM_V_N_PIN, SET);
  54. gpio_bit_write(PWM_W_N_GROUP, PWM_W_N_PIN, SET);
  55. }else {
  56. #if 0
  57. gpio_bit_write(PWM_U_P_GROUP, PWM_U_P_PIN, RESET);
  58. gpio_bit_write(PWM_V_P_GROUP, PWM_V_P_PIN, RESET);
  59. gpio_bit_write(PWM_W_P_GROUP, PWM_W_P_PIN, RESET);
  60. gpio_bit_write(PWM_U_N_GROUP, PWM_U_N_PIN, RESET);
  61. gpio_bit_write(PWM_V_N_GROUP, PWM_V_N_PIN, RESET);
  62. gpio_bit_write(PWM_W_N_GROUP, PWM_W_N_PIN, RESET);
  63. #else
  64. pwm_3phase_init();
  65. #endif
  66. }
  67. }
  68. static void _pwm_gpio_config(void)
  69. {
  70. rcu_apb2_periph_clock_enable(PWM_U_P_RCU);
  71. rcu_apb2_periph_clock_enable(PWM_V_P_RCU);
  72. rcu_apb2_periph_clock_enable(PWM_W_P_RCU);
  73. rcu_apb2_periph_clock_enable(PWM_U_N_RCU);
  74. rcu_apb2_periph_clock_enable(PWM_V_N_RCU);
  75. rcu_apb2_periph_clock_enable(PWM_W_N_RCU);
  76. rcu_apb2_periph_clock_enable(RCU_AF);
  77. /*configure PA8 PA9 PA10(TIMER0 CH0 CH1 CH2) as alternate function*/
  78. gpio_init(PWM_U_P_GROUP,PWM_U_P_MODE,GPIO_OSPEED_50MHZ,PWM_U_P_PIN);
  79. gpio_init(PWM_V_P_GROUP,PWM_V_P_MODE,GPIO_OSPEED_50MHZ,PWM_V_P_PIN);
  80. gpio_init(PWM_W_P_GROUP,PWM_W_P_MODE,GPIO_OSPEED_50MHZ,PWM_W_P_PIN);
  81. /*configure PB13 PB14 PB15(TIMER0 CH0N CH1N CH2N) as alternate function*/
  82. gpio_init(PWM_U_N_GROUP,PWM_U_N_MODE,GPIO_OSPEED_50MHZ,PWM_U_N_PIN);
  83. gpio_init(PWM_V_N_GROUP,PWM_V_N_MODE,GPIO_OSPEED_50MHZ,PWM_V_N_PIN);
  84. gpio_init(PWM_W_N_GROUP,PWM_W_N_MODE,GPIO_OSPEED_50MHZ,PWM_W_N_PIN);
  85. /*configure BRAKE IN*/
  86. #ifdef PWM_BRAKE_GROUP
  87. /* TIMER0 BKIN */
  88. rcu_apb2_periph_clock_enable(PWM_BRAKE_RCU);
  89. gpio_init(PWM_BRAKE_GROUP, PWM_BRAKE_MODE, GPIO_OSPEED_50MHZ, PWM_BRAKE_PIN);
  90. #endif
  91. }
  92. static u8 _dead_time(u16 t) {
  93. if (t < 128) {
  94. return (u8 )t;
  95. }else if (t <= (64 + 63) * 2) { //11 1111
  96. return ((((u8)2<<6) + (t-64)/2));
  97. }else if (t <= (32 + 31) * 8) {
  98. return (((u8)3 << 6) + (t - 32)/8);
  99. }else {
  100. if ((t-32)/16 > 63) {
  101. return 0xFF;
  102. }
  103. return (((u8)7<<3) + (t - 32)/16);
  104. }
  105. }
  106. static void _init_pwm_timer(bool enable_brk) {
  107. TIM_TimeBaseInitType TIM1_TimeBaseStructure;
  108. OCInitType TIM1_OCInitStructure;
  109. TIM_BDTRInitType TIM1_BDTRInitStructure;
  110. TIM_Module *TIMx = pwm_timer;
  111. u32 half_period = FOC_PWM_Half_Period;
  112. rcu_apb2_periph_clock_enable(PWM_TIM_CLK);
  113. TIM_DeInit(TIMx);
  114. TIM_InitTimBaseStruct(&TIM1_TimeBaseStructure);
  115. TIM1_TimeBaseStructure.Prescaler = 0;
  116. TIM1_TimeBaseStructure.CntMode = TIM_CNT_MODE_CENTER_ALIGN1;// 01: \,irq flag only counter down
  117. TIM1_TimeBaseStructure.Period = half_period;
  118. TIM1_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
  119. TIM1_TimeBaseStructure.RepetCnt = 1;
  120. TIM_InitTimeBase(TIMx, &TIM1_TimeBaseStructure);
  121. //Channel 1, 2,3 in PWM mode
  122. TIM_InitOcStruct(&TIM1_OCInitStructure);
  123. TIM1_OCInitStructure.OcMode = TIM_OCMODE_PWM1;//Pos logic(when '<' is active,when '>' is inactive)
  124. TIM1_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
  125. TIM1_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_ENABLE;
  126. TIM1_OCInitStructure.Pulse = (half_period>>1);
  127. TIM1_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH;
  128. TIM1_OCInitStructure.OcNPolarity = TIM_OCN_POLARITY_HIGH;
  129. TIM1_OCInitStructure.OcIdleState = TIM_OC_IDLE_STATE_RESET;
  130. TIM1_OCInitStructure.OcNIdleState = TIM_OC_IDLE_STATE_RESET;
  131. TIM_InitOc1(TIMx, &TIM1_OCInitStructure);
  132. TIM_InitOc2(TIMx, &TIM1_OCInitStructure);
  133. TIM_InitOc3(TIMx, &TIM1_OCInitStructure);
  134. //Channel 4 Configuration in OC
  135. TIM1_OCInitStructure.OcMode = TIM_OCMODE_PWM2;
  136. TIM1_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
  137. TIM1_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_DISABLE;
  138. TIM1_OCInitStructure.Pulse = half_period - 1;//3400;
  139. TIM_InitOc4(TIMx, &TIM1_OCInitStructure);
  140. //Enables the TIM1 Preload on CC1,CC2,CC3,CC4 Register
  141. TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
  142. TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
  143. TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
  144. //Automatic Output enable, Break, dead time and lock configuration
  145. TIM1_BDTRInitStructure.OssrState = TIM_OSSR_STATE_DISABLE;
  146. TIM1_BDTRInitStructure.OssiState = TIM_OSSI_STATE_DISABLE;
  147. TIM1_BDTRInitStructure.LockLevel = TIM_LOCK_LEVEL_OFF;
  148. TIM1_BDTRInitStructure.DeadTime = _dead_time(NS_2_TCLK(PWM_DEAD_TIME_NS));
  149. TIM1_BDTRInitStructure.Break = enable_brk?TIM_BREAK_IN_ENABLE:TIM_BREAK_IN_DISABLE;
  150. TIM1_BDTRInitStructure.BreakPolarity = TIM_BREAK_POLARITY_LOW;
  151. TIM1_BDTRInitStructure.AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE;
  152. TIM1_BDTRInitStructure.IomBreakEn = true;
  153. TIM_ConfigBkdt(TIMx, &TIM1_BDTRInitStructure);
  154. pwm_enable_channel();
  155. TIM_ClearFlag(TIMx,TIM_FLAG_UPDATE);
  156. TIM_ConfigInt(TIMx, TIM_INT_UPDATE, DISABLE);
  157. nvic_irq_enable(PWM_UP_IRQ, TIMER_UP_IRQ_PRIORITY, 0);
  158. TIM_ClearFlag(TIMx,TIM_FLAG_BREAK);
  159. TIM_ConfigInt(TIMx, TIM_INT_BREAK, ENABLE);
  160. nvic_irq_enable(PWM_BRK_IRQ, EBREAK_IRQ_PRIORITY, 0);
  161. //TIM1 counter enable
  162. TIM_Enable(TIMx, ENABLE);
  163. }
  164. void pwm_start(void){
  165. pwm_update_duty(FOC_PWM_Half_Period/2, FOC_PWM_Half_Period/2, FOC_PWM_Half_Period/2);
  166. pwm_update_2smaples(FOC_PWM_Half_Period-1, FOC_PWM_Half_Period + 1);
  167. /* wait for a new PWM period to flush last HF task */
  168. TIM_ClearFlag(pwm_timer, TIM_FLAG_UPDATE);
  169. TIM_GenerateEvent(pwm_timer, TIM_EVT_SRC_UPDATE);
  170. while ( TIM_GetFlagStatus(pwm_timer, TIM_FLAG_UPDATE) == RESET ){}
  171. /* Clear Update Flag */
  172. TIM_ClearFlag(pwm_timer, TIM_FLAG_UPDATE);
  173. TIM_EnableCtrlPwmOutputs(pwm_timer,ENABLE);
  174. }
  175. void pwm_stop(void){
  176. TIM_EnableCtrlPwmOutputs(pwm_timer,DISABLE);
  177. TIM_ConfigInt(pwm_timer, TIM_INT_UPDATE, DISABLE);
  178. /* wait for a new PWM period to flush last HF task */
  179. TIM_ClearFlag(pwm_timer, TIM_FLAG_UPDATE);
  180. while ( TIM_GetFlagStatus(pwm_timer, TIM_FLAG_UPDATE) == RESET ){}
  181. /* Clear Update Flag */
  182. TIM_ClearFlag(pwm_timer, TIM_FLAG_UPDATE);
  183. }
  184. void pwm_enable_output(bool enable) {
  185. if (enable) {
  186. TIM_EnableCtrlPwmOutputs(pwm_timer,ENABLE);
  187. }else {
  188. TIM_EnableCtrlPwmOutputs(pwm_timer,DISABLE);
  189. }
  190. }
  191. /*open low side of the mosfet*/
  192. void pwm_turn_on_low_side(void)
  193. {
  194. pwm_update_duty(0, 0, 0);
  195. pwm_update_2smaples(FOC_PWM_Half_Period-1, FOC_PWM_Half_Period + 1);
  196. TIM_ClearFlag(pwm_timer,TIM_FLAG_UPDATE);
  197. TIM_GenerateEvent(pwm_timer, TIM_EVT_SRC_UPDATE);
  198. while (TIM_GetFlagStatus(pwm_timer, TIM_FLAG_UPDATE) == RESET );
  199. /* Main PWM Output Enable */
  200. TIM_EnableCtrlPwmOutputs(pwm_timer, ENABLE);
  201. }
  202. void pwm_update_sample(u32 samp1, u32 samp2, u8 sector) {
  203. if (samp1 < FOC_PWM_Half_Period) {
  204. TIMER_CH3CV(pwm_timer) = samp1;
  205. pwm_change_t3_mode(TIM_OCMODE_PWM2);
  206. }else {
  207. TIMER_CH3CV(pwm_timer) = samp2;
  208. pwm_change_t3_mode(TIM_OCMODE_PWM1);
  209. }
  210. adc_current_sample_config(sector);
  211. }