adc.c 18 KB

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  1. #include "bsp/bsp_driver.h"
  2. #include "libs/utils.h"
  3. #include "os/os_task.h"
  4. #include "libs/logger.h"
  5. #include "math/fast_math.h"
  6. #define REG_CHAN_DMA 1
  7. #ifdef REG_CHAN_DMA
  8. #ifndef CONFIG_BOARD_MCXXX
  9. #define ADC01_NUM 7
  10. #define ADC2_NUM 0
  11. #define VBUS_V_BUFF_IDX 0
  12. #define THROTTLE_BUFF_IDX 1
  13. #define U_VOL_BUFF_IDX 2
  14. #define V_VOL_BUFF_IDX 3
  15. #define W_VOL_BUFF_IDX 4
  16. #define MOS_TEMP_BUFF_IDX 5
  17. #define MOTOR_TEMP_BUFF_IDX 6
  18. #elif (CONFIG_HW_VERSION==2)
  19. #define ADC01_NUM (8)
  20. #define ADC2_NUM 4
  21. #define MOS_TEMP_BUFF_IDX 0
  22. #define VREF5v_BUFF_IDX 1
  23. #define VBUS_I_BUFF_IDX 2
  24. #define U_VOL_BUFF_IDX 3
  25. #define V_VOL_BUFF_IDX 4
  26. #define W_VOL_BUFF_IDX 5
  27. #define VREF_BUFF_IDX 7
  28. #define VBUS_V_BUFF_IDX 8
  29. #define ACC_V_BUFF_IDX 9
  30. #define THROTTLE_BUFF_IDX 10
  31. #define MOTOR_TEMP_BUFF_IDX 11
  32. #elif (CONFIG_HW_VERSION==3)
  33. #define ADC01_NUM (12)
  34. #define ADC2_NUM 5
  35. #define MOS_TEMP_BUFF_IDX 0
  36. #define MOTOR_TEMP_BUFF_IDX 1
  37. #define THROTTLE_BUFF_IDX 2
  38. #define THROTTLE2_BUFF_IDX 3
  39. #define THROTTLE_5V_BUFF_IDX 5
  40. #define THROTTLE2_5V_BUFF_IDX 6
  41. #define U_VOL_BUFF_IDX 7
  42. #define VREF_BUFF_IDX 9
  43. #define VREF5v_BUFF_IDX 11
  44. #define VBUS_V_BUFF_IDX 12
  45. #define ACC_V_BUFF_IDX 13
  46. #define VBUS_I_BUFF_IDX 14
  47. #define V_VOL_BUFF_IDX 15
  48. #define W_VOL_BUFF_IDX 16
  49. #endif
  50. #define REG_CHAN_NUM (ADC01_NUM + ADC2_NUM)
  51. s16 adc_buffer[REG_CHAN_NUM];
  52. float vref_adc = 1408.0f;
  53. float vref_5v_adc = 2047.0f;
  54. #define VREF_ADC_DATA 1509.0F //1498, 1.21/3.3*4095
  55. static void adc01_dma_init(void)
  56. {
  57. dma_parameter_struct dma_init_struct;
  58. rcu_periph_clock_enable(RCU_DMA0);
  59. dma_deinit(DMA0, DMA_CH0);
  60. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  61. dma_init_struct.memory_addr = (uint32_t)adc_buffer;
  62. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  63. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
  64. dma_init_struct.number = ADC01_NUM;
  65. dma_init_struct.periph_addr = (uint32_t)(&ADC_RDATA(ADC0));
  66. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  67. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
  68. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  69. dma_init(DMA0, DMA_CH0, &dma_init_struct);
  70. dma_circulation_enable(DMA0, DMA_CH0);
  71. dma_memory_to_memory_disable(DMA0, DMA_CH0);
  72. dma_channel_enable(DMA0, DMA_CH0);
  73. }
  74. #ifdef CONFIG_BOARD_MCXXX
  75. static void adc2_dma_init(void)
  76. {
  77. dma_parameter_struct dma_init_struct;
  78. rcu_periph_clock_enable(RCU_DMA1);
  79. dma_deinit(DMA1, DMA_CH4);
  80. dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
  81. dma_init_struct.memory_addr = (uint32_t)(adc_buffer + ADC01_NUM);
  82. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  83. dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
  84. dma_init_struct.number = ADC2_NUM;
  85. dma_init_struct.periph_addr = (uint32_t)(&ADC_RDATA(ADC2));
  86. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  87. dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
  88. dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
  89. dma_init(DMA1, DMA_CH4, &dma_init_struct);
  90. dma_circulation_enable(DMA1, DMA_CH4);
  91. dma_memory_to_memory_disable(DMA1, DMA_CH4);
  92. dma_channel_enable(DMA1, DMA_CH4);
  93. }
  94. #endif
  95. #endif
  96. static void adc0_init(void){
  97. /* config ADC clock */
  98. rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV4); //APB2 clk 120M, adc clk 30M
  99. rcu_periph_clock_enable(RCU_ADC0);
  100. adc_deinit(ADC0);
  101. adc_mode_config(ADC_DAUL_INSERTED_PARALLEL);
  102. adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
  103. adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE);
  104. /* configure ADC data alignment */
  105. adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT);
  106. /* configure ADC inserted channel length */
  107. adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 1);
  108. //adc_inserted_channel_config(ADC0, 0, U_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  109. #ifdef U_PHASE_I_CHAN
  110. adc_update_insert_sample_time(ADC0, U_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  111. #endif
  112. #ifdef V_PHASE_I_CHAN
  113. adc_update_insert_sample_time(ADC0, V_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  114. #endif
  115. #ifdef W_PHASE_I_CHAN
  116. adc_update_insert_sample_time(ADC0, W_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  117. #endif
  118. #ifdef CONFIG_HW_MUTISAMPLE
  119. adc_oversample_mode_config(ADC0, ADC_OVERSAMPLING_ALL_CONVERT, CONFIG_HW_MUTISAMPLE_SHIFT, CONFIG_HW_MUTISAMPLE);
  120. adc_oversample_mode_enable(ADC0);
  121. #endif
  122. /* configure ADC inserted channel trigger */
  123. adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC_TRIGGER_PHASE);
  124. /* ADC external trigger enable */
  125. adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE);
  126. #ifdef REG_CHAN_DMA
  127. /* configure ADC regular channel */
  128. adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, ADC01_NUM);
  129. #ifndef CONFIG_BOARD_MCXXX
  130. adc_regular_channel_config(ADC0, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  131. adc_regular_channel_config(ADC0, 1, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  132. adc_regular_channel_config(ADC0, 2, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  133. adc_regular_channel_config(ADC0, 3, V_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  134. adc_regular_channel_config(ADC0, 4, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  135. adc_regular_channel_config(ADC0, 5, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  136. adc_regular_channel_config(ADC0, 6, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  137. #elif (CONFIG_HW_VERSION==2)
  138. adc_regular_channel_config(ADC0, 0, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  139. adc_regular_channel_config(ADC0, 1, MOS_TEMP1_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  140. adc_regular_channel_config(ADC0, 2, VBUS_I_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  141. adc_regular_channel_config(ADC0, 3, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  142. adc_regular_channel_config(ADC0, 4, V_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  143. adc_regular_channel_config(ADC0, 5, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  144. adc_regular_channel_config(ADC0, 6, ADC_CHANNEL_10, ADC_REGCHAN_SAMPLE_TIME);
  145. adc_regular_channel_config(ADC0, 7, ADC_CHANNEL_17, ADC_REGCHAN_SAMPLE_TIME);
  146. adc_tempsensor_vrefint_enable();
  147. adc_buffer[VREF_BUFF_IDX] = VREF_ADC_DATA; //1.21/3.3*4095
  148. #elif (CONFIG_HW_VERSION==3)
  149. adc_regular_channel_config(ADC0, 0, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  150. adc_regular_channel_config(ADC0, 1, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  151. adc_regular_channel_config(ADC0, 2, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  152. adc_regular_channel_config(ADC0, 3, THROTTLE2_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  153. adc_regular_channel_config(ADC0, 4, ZERO_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME); //insert zero vol
  154. adc_regular_channel_config(ADC0, 5, THROTTLE_5V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  155. adc_regular_channel_config(ADC0, 6, THROTTLE2_5V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  156. adc_regular_channel_config(ADC0, 7, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  157. adc_regular_channel_config(ADC0, 8, ZERO_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME); //insert zero vol
  158. adc_regular_channel_config(ADC0, 9, ADC_CHANNEL_17, ADC_REGCHAN_SAMPLE_TIME); //mcu内部vref
  159. adc_regular_channel_config(ADC0, 10, ZERO_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME); //insert zero vol
  160. adc_regular_channel_config(ADC0, 11, DC5V_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  161. adc_tempsensor_vrefint_enable();
  162. adc_buffer[VREF_BUFF_IDX] = VREF_ADC_DATA; //1.21/3.3*4095
  163. #endif
  164. #endif
  165. /* configure ADC regular channel trigger */
  166. adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
  167. adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE);
  168. #ifdef REG_CHAN_DMA
  169. adc_dma_mode_enable(ADC0);
  170. #endif
  171. /* enable ADC interface */
  172. adc_enable(ADC0);
  173. delay_ms(1);
  174. /* ADC calibration and reset calibration */
  175. adc_calibration_enable(ADC0);
  176. nvic_irq_enable(ADC0_1_IRQn, ADC_IRQ_PRIORITY, 0);
  177. adc_disable_ext_trigger();
  178. #ifdef REG_CHAN_DMA
  179. adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL);
  180. #endif
  181. }
  182. static void adc1_init(void){
  183. rcu_periph_clock_enable(RCU_ADC1);
  184. adc_deinit(ADC1);
  185. adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
  186. adc_special_function_config(ADC1, ADC_SCAN_MODE, ENABLE);
  187. /* configure ADC data alignment */
  188. adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT);
  189. /* configure ADC inserted channel length */
  190. adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 1);
  191. /* configure ADC inserted channel */
  192. #ifdef U_PHASE_I_CHAN
  193. adc_update_insert_sample_time(ADC1, U_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  194. #endif
  195. #ifdef V_PHASE_I_CHAN
  196. adc_update_insert_sample_time(ADC1, V_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  197. #endif
  198. #ifdef W_PHASE_I_CHAN
  199. adc_update_insert_sample_time(ADC1, W_PHASE_I_CHAN, ADC_SAMPLE_TIME);
  200. #endif
  201. #ifdef CONFIG_HW_MUTISAMPLE
  202. adc_oversample_mode_config(ADC1, ADC_OVERSAMPLING_ALL_CONVERT, CONFIG_HW_MUTISAMPLE_SHIFT, CONFIG_HW_MUTISAMPLE);
  203. adc_oversample_mode_enable(ADC1);
  204. #endif
  205. /* ADC external trigger enable */
  206. adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL, ADC_TRIGGER_NONE);
  207. adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE);
  208. /* enable ADC interface */
  209. adc_enable(ADC1);
  210. delay_ms(1);
  211. /* ADC calibration and reset calibration */
  212. adc_calibration_enable(ADC1);
  213. /* ADC software trigger enable */
  214. adc_software_trigger_enable(ADC1, ADC_INSERTED_CHANNEL);
  215. }
  216. #ifdef CONFIG_BOARD_MCXXX
  217. static void adc2_init(void){
  218. rcu_periph_clock_enable(RCU_ADC2);
  219. adc_deinit(ADC2);
  220. adc_special_function_config(ADC2, ADC_CONTINUOUS_MODE, ENABLE);
  221. adc_special_function_config(ADC2, ADC_SCAN_MODE, ENABLE);
  222. /* configure ADC data alignment */
  223. adc_data_alignment_config(ADC2, ADC_DATAALIGN_RIGHT);
  224. #ifdef CONFIG_HW_MUTISAMPLE
  225. adc_oversample_mode_config(ADC2, ADC_OVERSAMPLING_ALL_CONVERT, CONFIG_HW_MUTISAMPLE_SHIFT, CONFIG_HW_MUTISAMPLE);
  226. adc_oversample_mode_enable(ADC2);
  227. #endif
  228. #ifdef REG_CHAN_DMA
  229. /* configure ADC regular channel */
  230. adc_channel_length_config(ADC2, ADC_REGULAR_CHANNEL, ADC2_NUM);
  231. #if (CONFIG_HW_VERSION==2)
  232. adc_regular_channel_config(ADC2, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  233. adc_regular_channel_config(ADC2, 1, ACC_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  234. adc_regular_channel_config(ADC2, 2, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  235. adc_regular_channel_config(ADC2, 3, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  236. #elif (CONFIG_HW_VERSION==3)
  237. adc_regular_channel_config(ADC2, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  238. adc_regular_channel_config(ADC2, 1, ACC_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  239. adc_regular_channel_config(ADC2, 2, VBUS_I_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  240. adc_regular_channel_config(ADC2, 3, V_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  241. adc_regular_channel_config(ADC2, 4, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
  242. #endif
  243. #endif
  244. /* configure ADC regular channel trigger */
  245. adc_external_trigger_source_config(ADC2, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
  246. adc_external_trigger_config(ADC2, ADC_REGULAR_CHANNEL, ENABLE);
  247. #ifdef REG_CHAN_DMA
  248. adc_dma_mode_enable(ADC2);
  249. #endif
  250. /* enable ADC interface */
  251. adc_enable(ADC2);
  252. delay_ms(1);
  253. /* ADC calibration and reset calibration */
  254. adc_calibration_enable(ADC2);
  255. #ifdef REG_CHAN_DMA
  256. adc_software_trigger_enable(ADC2, ADC_REGULAR_CHANNEL);
  257. #endif
  258. }
  259. #endif
  260. static void adc_gpio_init(void) {
  261. rcu_periph_clock_enable(RCU_AF);
  262. /* configure ADC pin, current sampling -- ADC_IN1(PA1) ADC_IN12(PC2) ADC_IN13(PC3) */
  263. #ifdef U_PHASE_ADC_GROUP
  264. rcu_periph_clock_enable(U_PHASE_ADC_RCU);
  265. gpio_init(U_PHASE_ADC_GROUP, U_PHASE_ADC_MODE, GPIO_OSPEED_50MHZ, U_PHASE_ADC_PIN);
  266. #endif
  267. #ifdef V_PHASE_ADC_GROUP
  268. rcu_periph_clock_enable(V_PHASE_ADC_RCU);
  269. gpio_init(V_PHASE_ADC_GROUP, V_PHASE_ADC_MODE, GPIO_OSPEED_50MHZ, V_PHASE_ADC_PIN);
  270. #endif
  271. #ifdef W_PHASE_ADC_GROUP
  272. rcu_periph_clock_enable(W_PHASE_ADC_RCU);
  273. gpio_init(W_PHASE_ADC_GROUP, W_PHASE_ADC_MODE, GPIO_OSPEED_50MHZ, W_PHASE_ADC_PIN);
  274. #endif
  275. #ifdef VBUS_V_ADC_GROUP
  276. rcu_periph_clock_enable(VBUS_V_ADC_RCU);
  277. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  278. gpio_init(VBUS_V_ADC_GROUP, VBUS_V_ADC_MODE, GPIO_OSPEED_50MHZ, VBUS_V_ADC_PIN);
  279. #endif
  280. #ifdef VBUS_I_ADC_GROUP
  281. rcu_periph_clock_enable(VBUS_I_ADC_RCU);
  282. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  283. gpio_init(VBUS_I_ADC_GROUP, VBUS_I_ADC_MODE, GPIO_OSPEED_50MHZ, VBUS_I_ADC_PIN);
  284. #endif
  285. #ifdef ACC_V_ADC_GROUP
  286. rcu_periph_clock_enable(ACC_V_ADC_RCU);
  287. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  288. gpio_init(ACC_V_ADC_GROUP, ACC_V_ADC_MODE, GPIO_OSPEED_50MHZ, ACC_V_ADC_PIN);
  289. #endif
  290. #ifdef THROTTLE_V_ADC_GROUP
  291. rcu_periph_clock_enable(THROTTLE_V_ADC_RCU);
  292. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  293. gpio_init(THROTTLE_V_ADC_GROUP, THROTTLE_V_ADC_MODE, GPIO_OSPEED_50MHZ, THROTTLE_V_ADC_PIN);
  294. #endif
  295. #ifdef THROTTLE2_V_ADC_GROUP
  296. rcu_periph_clock_enable(THROTTLE2_V_ADC_RCU);
  297. gpio_init(THROTTLE2_V_ADC_GROUP, THROTTLE2_V_ADC_MODE, GPIO_OSPEED_50MHZ, THROTTLE2_V_ADC_PIN);
  298. #endif
  299. #ifdef THROTTLE_5V_ADC_GROUP
  300. rcu_periph_clock_enable(THROTTLE_5V_ADC_RCU);
  301. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  302. gpio_init(THROTTLE_5V_ADC_GROUP, THROTTLE_5V_ADC_MODE, GPIO_OSPEED_50MHZ, THROTTLE_5V_ADC_PIN);
  303. #endif
  304. #ifdef THROTTLE2_5V_ADC_GROUP
  305. rcu_periph_clock_enable(THROTTLE2_5V_ADC_RCU);
  306. /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
  307. gpio_init(THROTTLE2_5V_ADC_GROUP, THROTTLE2_5V_ADC_MODE, GPIO_OSPEED_50MHZ, THROTTLE2_5V_ADC_PIN);
  308. #endif
  309. #ifdef U_VOL_ADC_GROUP
  310. rcu_periph_clock_enable(U_VOL_ADC_RCU);
  311. gpio_init(U_VOL_ADC_GROUP, U_VOL_ADC_MODE, GPIO_OSPEED_50MHZ, U_VOL_ADC_PIN);
  312. #endif
  313. #ifdef V_VOL_ADC_GROUP
  314. rcu_periph_clock_enable(V_VOL_ADC_RCU);
  315. gpio_init(V_VOL_ADC_GROUP, V_VOL_ADC_MODE, GPIO_OSPEED_50MHZ, V_VOL_ADC_PIN);
  316. #endif
  317. #ifdef W_VOL_ADC_GROUP
  318. rcu_periph_clock_enable(W_VOL_ADC_RCU);
  319. gpio_init(W_VOL_ADC_GROUP, W_VOL_ADC_MODE, GPIO_OSPEED_50MHZ, W_VOL_ADC_PIN);
  320. #endif
  321. #ifdef MOS_TEMP_ADC_GROUP
  322. rcu_periph_clock_enable(MOS_TEMP_ADC_RCU);
  323. gpio_init(MOS_TEMP_ADC_GROUP, MOS_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOS_TEMP_ADC_PIN);
  324. #endif
  325. #ifdef MOS_TEMP1_ADC_GROUP
  326. rcu_periph_clock_enable(MOS_TEMP1_ADC_RCU);
  327. gpio_init(MOS_TEMP1_ADC_GROUP, MOS_TEMP1_ADC_MODE, GPIO_OSPEED_50MHZ, MOS_TEMP1_ADC_PIN);
  328. #endif
  329. #ifdef MOTOR_TEMP_ADC_GROUP
  330. rcu_periph_clock_enable(MOTOR_TEMP_ADC_RCU);
  331. gpio_init(MOTOR_TEMP_ADC_GROUP, MOTOR_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOTOR_TEMP_ADC_PIN);
  332. #endif
  333. #ifdef ZERO_ADC_GROUP
  334. rcu_periph_clock_enable(ZERO_ADC_RCU);
  335. gpio_init(ZERO_ADC_GROUP, ZERO_ADC_MODE, GPIO_OSPEED_50MHZ, ZERO_ADC_PIN);
  336. #endif
  337. }
  338. void adc_init(void) {
  339. adc_gpio_init();
  340. #ifdef REG_CHAN_DMA
  341. adc01_dma_init();
  342. #ifdef CONFIG_BOARD_MCXXX
  343. adc2_dma_init();
  344. #endif
  345. #endif
  346. adc0_init();
  347. adc1_init();
  348. #ifdef CONFIG_BOARD_MCXXX
  349. adc2_init();
  350. #endif
  351. adc_current_sample_config(0);
  352. }
  353. void adc_set_vref_calc(float v) {
  354. vref_adc = v;
  355. }
  356. void adc_set_5vref_calc(float v) {
  357. vref_5v_adc = v;
  358. }
  359. #define VREF_COMP_LFP_CEOF (0.0001F)
  360. static float vref_compestion_filter = 1.0f;
  361. #define VREF_3V3_COMPESTION() (vref_adc/(float)adc_buffer[VREF_BUFF_IDX])
  362. void adc_3v3ref_filter(void) {
  363. float value = VREF_3V3_COMPESTION();
  364. LowPass_Filter(vref_compestion_filter, value, VREF_COMP_LFP_CEOF);
  365. }
  366. float adc_vref_compesion(void) {
  367. return vref_compestion_filter;
  368. }
  369. static float vref_5v_compestion_filter = 1.0f;
  370. #define VREF_5V_COMPESTION() (vref_5v_adc/(float)adc_buffer[VREF5v_BUFF_IDX])
  371. void adc_5vref_filter(void) {
  372. float value = VREF_5V_COMPESTION();
  373. LowPass_Filter(vref_5v_compestion_filter, value, VREF_COMP_LFP_CEOF);
  374. }
  375. float adc_5vref_compesion(void) {
  376. return vref_5v_compestion_filter;
  377. }
  378. void adc_vref_filter(void) {
  379. adc_3v3ref_filter();
  380. adc_5vref_filter();
  381. }
  382. u16 adc_get_vbus(void) {
  383. return (float)adc_buffer[VBUS_V_BUFF_IDX] * VREF_3V3_COMPESTION();
  384. }
  385. u16 adc_get_acc(void) {
  386. #ifdef CONFIG_BOARD_MCXXX
  387. return (float)adc_buffer[ACC_V_BUFF_IDX] * VREF_3V3_COMPESTION();
  388. #else
  389. return adc_get_vbus();
  390. #endif
  391. }
  392. u16 adc_get_ibus(void) {
  393. #ifdef CONFIG_BOARD_MCXXX
  394. return (float)adc_buffer[VBUS_I_BUFF_IDX] * VREF_5V_COMPESTION();
  395. #else
  396. return 0;
  397. #endif
  398. }
  399. u16 adc_get_throttle(void) {
  400. return adc_buffer[THROTTLE_BUFF_IDX] * VREF_3V3_COMPESTION();
  401. }
  402. u16 adc_get_throttle2(void) {
  403. #ifdef THROTTLE2_BUFF_IDX
  404. return adc_buffer[THROTTLE2_BUFF_IDX] * VREF_3V3_COMPESTION();
  405. #else
  406. return adc_get_throttle();
  407. #endif
  408. }
  409. u16 adc_get_thro_5v(void) {
  410. #ifdef THROTTLE_5V_BUFF_IDX
  411. return adc_buffer[THROTTLE_5V_BUFF_IDX] * VREF_3V3_COMPESTION();
  412. #else
  413. return 0;
  414. #endif
  415. }
  416. u16 adc_get_thro2_5v(void) {
  417. #ifdef THROTTLE2_5V_BUFF_IDX
  418. return adc_buffer[THROTTLE2_5V_BUFF_IDX] * VREF_3V3_COMPESTION();
  419. #else
  420. return 0;
  421. #endif
  422. }
  423. void adc_get_uvw_phaseV(u16 *uvw) {
  424. uvw[0] = adc_buffer[U_VOL_BUFF_IDX];
  425. uvw[1] = adc_buffer[V_VOL_BUFF_IDX];
  426. uvw[2] = adc_buffer[W_VOL_BUFF_IDX];
  427. }
  428. u16 adc_get_mos_temp(void) {
  429. return adc_buffer[MOS_TEMP_BUFF_IDX];
  430. }
  431. u16 adc_get_motor_temp(void) {
  432. return adc_buffer[MOTOR_TEMP_BUFF_IDX];
  433. }
  434. u16 adc_get_vref(void) {
  435. #ifdef CONFIG_BOARD_MCXXX
  436. return adc_buffer[VREF_BUFF_IDX];
  437. #else
  438. return 0;
  439. #endif
  440. }
  441. u16 adc_get_5v_ref(void) {
  442. #ifdef CONFIG_BOARD_MCXXX
  443. return adc_buffer[VREF5v_BUFF_IDX];
  444. #else
  445. return 0;
  446. #endif
  447. }
  448. void adc_start_convert(void) {
  449. int drop = 2;
  450. /* clear the ADC flag */
  451. adc_flag_clear(ADC0, ADC_FLAG_EOIC);
  452. adc_flag_clear(ADC1, ADC_FLAG_EOIC);
  453. adc_enable_ext_trigger();
  454. while(drop-- > 0) {
  455. while (adc_flag_get(ADC0, ADC_FLAG_EOIC) == RESET);
  456. adc_flag_clear(ADC0, ADC_FLAG_EOIC);
  457. }
  458. /* enable ADC interrupt */
  459. adc_interrupt_enable(ADC0, ADC_INT_EOIC);
  460. adc_update_ext_trigger(ADC_TRIGGER_PHASE);
  461. }
  462. void adc_stop_convert(void) {
  463. adc_disable_ext_trigger();
  464. /* disable ADC interrupt */
  465. adc_interrupt_disable(ADC0, ADC_INT_EOIC);
  466. /* clear the ADC flag */
  467. adc_flag_clear(ADC0, ADC_FLAG_EOIC);
  468. adc_flag_clear(ADC1, ADC_FLAG_EOIC);
  469. }
  470. s32 adc_sample_regular_channel(int channel, int times) {
  471. #ifndef REG_CHAN_DMA
  472. u32 adc_device = ADC0;
  473. int value = 0;
  474. int count = 0;
  475. int min = 0xFFFFF;
  476. int max = -0xFFFFF;
  477. u64 start_time;
  478. adc_channel_length_config(adc_device, ADC_REGULAR_CHANNEL, 1);
  479. adc_regular_channel_config(adc_device, 0, channel, ADC_REGCHAN_SAMPLE_TIME);
  480. while(count < times){
  481. restart:
  482. start_time = shark_get_mseconds();
  483. adc_software_trigger_enable(adc_device, ADC_REGULAR_CHANNEL);
  484. while(SET != adc_flag_get(adc_device, ADC_FLAG_EOC)){
  485. if (shark_get_mseconds() - start_time >= 2){
  486. goto restart;
  487. }
  488. };
  489. int one = adc_regular_data_read(adc_device);
  490. adc_flag_clear(adc_device, ADC_FLAG_EOC);
  491. value += (one & 0xFFF);
  492. count ++;
  493. if (one > max){
  494. max = one;
  495. }
  496. if (one < min) {
  497. min = one;
  498. }
  499. }
  500. if (times <= 2) {
  501. return value/times;
  502. }
  503. return (value - min - max)/(times-2);
  504. #else
  505. return 0;
  506. #endif
  507. }