MC100/Simulink/PMSM_Controller_ert_rtw/PMSM_Controller.c

/*
 * File: PMSM_Controller.c
 *
 * Code generated for Simulink model 'PMSM_Controller'.
 *
 * Model version                  : 1.1235
 * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
 * C/C++ source code generated on : Wed Apr  6 15:47:34 2022
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: ARM Compatible->ARM Cortex-M
 * Code generation objectives:
 *    1. Execution efficiency
 *    2. RAM efficiency
 * Validation result: Not run
 */

#include "PMSM_Controller.h"

/* Named constants for Chart: '<S3>/Control_Mode_Manager' */
#define IN_ACTIVE                      ((uint8_T)1U)
#define IN_NO_ACTIVE_CHILD             ((uint8_T)0U)
#define IN_OPEN                        ((uint8_T)2U)
#define IN_SPEED_MODE                  ((uint8_T)1U)
#define IN_TORQUE_MODE                 ((uint8_T)2U)
#define OPEN_MODE                      ((uint8_T)0U)
#define SPD_MODE                       ((uint8_T)1U)
#define TRQ_MODE                       ((uint8_T)2U)
#ifndef UCHAR_MAX
#include <limits.h>
#endif

#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) )
#error Code was generated for compiler with different sized uchar/char. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif

#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) )
#error Code was generated for compiler with different sized ushort/short. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif

#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) )
#error Code was generated for compiler with different sized uint/int. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif

#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) )
#error Code was generated for compiler with different sized ulong/long. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif

/* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */
static uint16_T plook_u16s16_evencka(int16_T u, int16_T bp0, uint16_T bpSpace,
  uint32_T maxIndex);
static uint8_T plook_u8u16_evencka(uint16_T u, uint16_T bp0, uint16_T bpSpace,
  uint32_T maxIndex);
static void Counter_Init(DW_Counter *localDW, uint16_T rtp_z_cntInit);
static uint16_T Counter(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst,
  DW_Counter *localDW);
static boolean_T either_edge(boolean_T rtu_u, DW_either_edge *localDW);
static void Debounce_Filter_Init(DW_Debounce_Filter *localDW);
static void Debounce_Filter(boolean_T rtu_u, uint16_T rtu_tAcv, uint16_T
  rtu_tDeacv, boolean_T *rty_y, DW_Debounce_Filter *localDW);
static void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T
  rty_y[2], DW_Low_Pass_Filter *localDW);
static void PI_iq(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I, int16_T rtu_Kb,
                  int16_T rtu_satMax, int16_T rtu_satMin, int16_T
                  rtu_ext_limProt, int16_T *rty_pi_out, DW_PI_iq *localDW);
static void PI_id(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I, int16_T rtu_Kb,
                  int16_T rtu_satMax, int16_T rtu_satMin, int16_T
                  rtu_ext_limProt, int16_T *rty_pi_out, DW_PI_id *localDW);
static void pi_speed_Init(DW_pi_speed *localDW);
static int16_T pi_speed(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I, int16_T
  rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_ext_limProt,
  uint8_T rtu_reset, const ConstB_pi_speed *localC, DW_pi_speed *localDW,
  ZCE_pi_speed *localZCE);
static uint16_T plook_u16s16_evencka(int16_T u, int16_T bp0, uint16_T bpSpace,
  uint32_T maxIndex)
{
  uint16_T bpIndex;

  /* Prelookup - Index only
     Index Search method: 'even'
     Extrapolation method: 'Clip'
     Use previous index: 'off'
     Use last breakpoint for index at or above upper limit: 'on'
     Remove protection against out-of-range input in generated code: 'off'
   */
  if (u <= bp0) {
    bpIndex = 0U;
  } else {
    bpIndex = (uint16_T)((uint32_T)(uint16_T)(u - bp0) / bpSpace);
    if (bpIndex < maxIndex) {
    } else {
      bpIndex = (uint16_T)maxIndex;
    }
  }

  return bpIndex;
}

static uint8_T plook_u8u16_evencka(uint16_T u, uint16_T bp0, uint16_T bpSpace,
  uint32_T maxIndex)
{
  uint16_T fbpIndex;
  uint8_T bpIndex;

  /* Prelookup - Index only
     Index Search method: 'even'
     Extrapolation method: 'Clip'
     Use previous index: 'off'
     Use last breakpoint for index at or above upper limit: 'on'
     Remove protection against out-of-range input in generated code: 'off'
   */
  if (u <= bp0) {
    bpIndex = 0U;
  } else {
    fbpIndex = (uint16_T)((uint32_T)(uint16_T)((uint32_T)u - bp0) / bpSpace);
    if (fbpIndex < maxIndex) {
      bpIndex = (uint8_T)fbpIndex;
    } else {
      bpIndex = (uint8_T)maxIndex;
    }
  }

  return bpIndex;
}

/*
 * System initialize for atomic system:
 *    '<S39>/Counter'
 *    '<S38>/Counter'
 */
static void Counter_Init(DW_Counter *localDW, uint16_T rtp_z_cntInit)
{
  /* InitializeConditions for UnitDelay: '<S44>/UnitDelay' */
  localDW->UnitDelay_DSTATE = rtp_z_cntInit;
}

/*
 * Output and update for atomic system:
 *    '<S39>/Counter'
 *    '<S38>/Counter'
 */
static uint16_T Counter(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst,
  DW_Counter *localDW)
{
  uint16_T rty_cnt_0;
  uint16_T rtu_rst_0;

  /* Switch: '<S44>/Switch1' incorporates:
   *  Constant: '<S44>/Constant23'
   *  UnitDelay: '<S44>/UnitDelay'
   */
  if (rtu_rst) {
    rtu_rst_0 = 0U;
  } else {
    rtu_rst_0 = localDW->UnitDelay_DSTATE;
  }

  /* End of Switch: '<S44>/Switch1' */

  /* Sum: '<S43>/Sum1' */
  rty_cnt_0 = (uint16_T)((uint32_T)rtu_inc + rtu_rst_0);

  /* MinMax: '<S43>/MinMax' */
  if (rty_cnt_0 < rtu_max) {
    /* Update for UnitDelay: '<S44>/UnitDelay' */
    localDW->UnitDelay_DSTATE = rty_cnt_0;
  } else {
    /* Update for UnitDelay: '<S44>/UnitDelay' */
    localDW->UnitDelay_DSTATE = rtu_max;
  }

  /* End of MinMax: '<S43>/MinMax' */
  return rty_cnt_0;
}

/*
 * Output and update for atomic system:
 *    '<S35>/either_edge'
 *    '<S34>/either_edge'
 */
static boolean_T either_edge(boolean_T rtu_u, DW_either_edge *localDW)
{
  boolean_T rty_y_0;

  /* RelationalOperator: '<S40>/Relational Operator' incorporates:
   *  UnitDelay: '<S40>/UnitDelay'
   */
  rty_y_0 = (rtu_u != localDW->UnitDelay_DSTATE);

  /* Update for UnitDelay: '<S40>/UnitDelay' */
  localDW->UnitDelay_DSTATE = rtu_u;
  return rty_y_0;
}

/* System initialize for atomic system: '<S34>/Debounce_Filter' */
static void Debounce_Filter_Init(DW_Debounce_Filter *localDW)
{
  /* SystemInitialize for IfAction SubSystem: '<S35>/Qualification' */
  /* SystemInitialize for Atomic SubSystem: '<S39>/Counter' */
  Counter_Init(&localDW->Counter_f, 0);

  /* End of SystemInitialize for SubSystem: '<S39>/Counter' */
  /* End of SystemInitialize for SubSystem: '<S35>/Qualification' */

  /* SystemInitialize for IfAction SubSystem: '<S35>/Dequalification' */
  /* SystemInitialize for Atomic SubSystem: '<S38>/Counter' */
  Counter_Init(&localDW->Counter_d, 0);

  /* End of SystemInitialize for SubSystem: '<S38>/Counter' */
  /* End of SystemInitialize for SubSystem: '<S35>/Dequalification' */
}

/* Output and update for atomic system: '<S34>/Debounce_Filter' */
static void Debounce_Filter(boolean_T rtu_u, uint16_T rtu_tAcv, uint16_T
  rtu_tDeacv, boolean_T *rty_y, DW_Debounce_Filter *localDW)
{
  uint16_T rtb_Sum1_n;
  boolean_T rtb_RelationalOperator_e;

  /* Outputs for Atomic SubSystem: '<S35>/either_edge' */
  rtb_RelationalOperator_e = either_edge(rtu_u, &localDW->either_edge_j);

  /* End of Outputs for SubSystem: '<S35>/either_edge' */

  /* If: '<S35>/If2' incorporates:
   *  Constant: '<S38>/Constant6'
   *  Constant: '<S39>/Constant6'
   *  Inport: '<S37>/yPrev'
   *  Logic: '<S35>/Logical Operator1'
   *  Logic: '<S35>/Logical Operator2'
   *  Logic: '<S35>/Logical Operator3'
   *  Logic: '<S35>/Logical Operator4'
   *  UnitDelay: '<S35>/UnitDelay'
   */
  if (rtu_u && (!localDW->UnitDelay_DSTATE)) {
    /* Outputs for IfAction SubSystem: '<S35>/Qualification' incorporates:
     *  ActionPort: '<S39>/Action Port'
     */
    /* Outputs for Atomic SubSystem: '<S39>/Counter' */
    rtb_Sum1_n = Counter(1, rtu_tAcv, rtb_RelationalOperator_e,
                         &localDW->Counter_f);

    /* End of Outputs for SubSystem: '<S39>/Counter' */

    /* Switch: '<S39>/Switch2' incorporates:
     *  Constant: '<S39>/Constant6'
     *  RelationalOperator: '<S39>/Relational Operator2'
     */
    *rty_y = ((rtb_Sum1_n > rtu_tAcv) || localDW->UnitDelay_DSTATE);

    /* End of Outputs for SubSystem: '<S35>/Qualification' */
  } else if ((!rtu_u) && localDW->UnitDelay_DSTATE) {
    /* Outputs for IfAction SubSystem: '<S35>/Dequalification' incorporates:
     *  ActionPort: '<S38>/Action Port'
     */
    /* Outputs for Atomic SubSystem: '<S38>/Counter' */
    rtb_Sum1_n = Counter(1, rtu_tDeacv, rtb_RelationalOperator_e,
                         &localDW->Counter_d);

    /* End of Outputs for SubSystem: '<S38>/Counter' */

    /* Switch: '<S38>/Switch2' incorporates:
     *  Constant: '<S38>/Constant6'
     *  RelationalOperator: '<S38>/Relational Operator2'
     */
    *rty_y = ((rtb_Sum1_n <= rtu_tDeacv) && localDW->UnitDelay_DSTATE);

    /* End of Outputs for SubSystem: '<S35>/Dequalification' */
  } else {
    /* Outputs for IfAction SubSystem: '<S35>/Default' incorporates:
     *  ActionPort: '<S37>/Action Port'
     */
    *rty_y = localDW->UnitDelay_DSTATE;

    /* End of Outputs for SubSystem: '<S35>/Default' */
  }

  /* End of If: '<S35>/If2' */

  /* Update for UnitDelay: '<S35>/UnitDelay' */
  localDW->UnitDelay_DSTATE = *rty_y;
}

/* Output and update for atomic system: '<S45>/Low_Pass_Filter' */
static void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T
  rty_y[2], DW_Low_Pass_Filter *localDW)
{
  int32_T tmp;

  /* Sum: '<S54>/Sum2' incorporates:
   *  UnitDelay: '<S54>/UnitDelay1'
   */
  tmp = rtu_u[0] - localDW->UnitDelay1_DSTATE[0];
  if (tmp > 32767) {
    tmp = 32767;
  } else {
    if (tmp < -32768) {
      tmp = -32768;
    }
  }

  /* Product: '<S54>/Divide3' incorporates:
   *  Sum: '<S54>/Sum2'
   */
  rty_y[0] = (int16_T)((rtu_coef * tmp) >> 16);

  /* Sum: '<S54>/Sum3' incorporates:
   *  UnitDelay: '<S54>/UnitDelay1'
   */
  rty_y[0] += localDW->UnitDelay1_DSTATE[0];

  /* Update for UnitDelay: '<S54>/UnitDelay1' incorporates:
   *  Sum: '<S54>/Sum3'
   */
  localDW->UnitDelay1_DSTATE[0] = rty_y[0];

  /* Sum: '<S54>/Sum2' incorporates:
   *  UnitDelay: '<S54>/UnitDelay1'
   */
  tmp = rtu_u[1] - localDW->UnitDelay1_DSTATE[1];
  if (tmp > 32767) {
    tmp = 32767;
  } else {
    if (tmp < -32768) {
      tmp = -32768;
    }
  }

  /* Product: '<S54>/Divide3' incorporates:
   *  Sum: '<S54>/Sum2'
   */
  rty_y[1] = (int16_T)((rtu_coef * tmp) >> 16);

  /* Sum: '<S54>/Sum3' incorporates:
   *  UnitDelay: '<S54>/UnitDelay1'
   */
  rty_y[1] += localDW->UnitDelay1_DSTATE[1];

  /* Update for UnitDelay: '<S54>/UnitDelay1' incorporates:
   *  Sum: '<S54>/Sum3'
   */
  localDW->UnitDelay1_DSTATE[1] = rty_y[1];
}

/* Output and update for atomic system: '<S58>/PI_iq' */
static void PI_iq(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I, int16_T rtu_Kb,
                  int16_T rtu_satMax, int16_T rtu_satMin, int16_T
                  rtu_ext_limProt, int16_T *rty_pi_out, DW_PI_iq *localDW)
{
  int64_T tmp;
  int32_T rtb_Divide4_k;
  int32_T rtb_Sum1_hy;

  /* Product: '<S63>/Divide4' */
  rtb_Divide4_k = (rtu_err * rtu_P) >> 6;

  /* Product: '<S63>/Divide1' incorporates:
   *  Product: '<S63>/Divide4'
   */
  tmp = ((int64_T)rtb_Divide4_k * rtu_I) >> 10;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Sum: '<S63>/Sum2' incorporates:
   *  Product: '<S63>/Divide1'
   *  UnitDelay: '<S63>/UnitDelay'
   */
  tmp = (((int64_T)rtu_ext_limProt << 4) + (int32_T)tmp) +
    localDW->UnitDelay_DSTATE;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Sum: '<S65>/Sum1' incorporates:
   *  Sum: '<S63>/Sum2'
   *  UnitDelay: '<S65>/UnitDelay'
   */
  rtb_Sum1_hy = (int32_T)tmp + localDW->UnitDelay_DSTATE_i;

  /* Sum: '<S63>/Sum6' incorporates:
   *  Product: '<S63>/Divide4'
   *  Sum: '<S65>/Sum1'
   */
  tmp = (int64_T)rtb_Divide4_k + rtb_Sum1_hy;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Switch: '<S66>/Switch2' incorporates:
   *  RelationalOperator: '<S66>/LowerRelop1'
   *  RelationalOperator: '<S66>/UpperRelop'
   *  Sum: '<S63>/Sum6'
   *  Switch: '<S66>/Switch'
   */
  if ((int32_T)tmp > (rtu_satMax << 4)) {
    *rty_pi_out = rtu_satMax;
  } else if ((int32_T)tmp < (rtu_satMin << 4)) {
    /* Switch: '<S66>/Switch' */
    *rty_pi_out = rtu_satMin;
  } else {
    *rty_pi_out = (int16_T)((int32_T)tmp >> 4);
  }

  /* End of Switch: '<S66>/Switch2' */

  /* Update for UnitDelay: '<S63>/UnitDelay' incorporates:
   *  Product: '<S63>/Divide2'
   *  Sum: '<S63>/Sum3'
   *  Sum: '<S63>/Sum6'
   */
  localDW->UnitDelay_DSTATE = (int32_T)(((int64_T)((*rty_pi_out << 4) - (int32_T)
    tmp) * rtu_Kb) >> 10);

  /* Update for UnitDelay: '<S65>/UnitDelay' incorporates:
   *  Sum: '<S65>/Sum1'
   */
  localDW->UnitDelay_DSTATE_i = rtb_Sum1_hy;
}

/* Output and update for atomic system: '<S57>/PI_id' */
static void PI_id(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I, int16_T rtu_Kb,
                  int16_T rtu_satMax, int16_T rtu_satMin, int16_T
                  rtu_ext_limProt, int16_T *rty_pi_out, DW_PI_id *localDW)
{
  int64_T tmp;
  int32_T rtb_Divide4_e;
  int32_T rtb_Sum1_l;

  /* Product: '<S59>/Divide4' */
  rtb_Divide4_e = (rtu_err * rtu_P) >> 6;

  /* Product: '<S59>/Divide1' incorporates:
   *  Product: '<S59>/Divide4'
   */
  tmp = ((int64_T)rtb_Divide4_e * rtu_I) >> 10;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Sum: '<S59>/Sum2' incorporates:
   *  Product: '<S59>/Divide1'
   *  UnitDelay: '<S59>/UnitDelay'
   */
  tmp = (((int64_T)rtu_ext_limProt << 3) + (int32_T)tmp) +
    localDW->UnitDelay_DSTATE;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Sum: '<S61>/Sum1' incorporates:
   *  Sum: '<S59>/Sum2'
   *  UnitDelay: '<S61>/UnitDelay'
   */
  rtb_Sum1_l = (int32_T)tmp + localDW->UnitDelay_DSTATE_p;

  /* Sum: '<S59>/Sum6' incorporates:
   *  Product: '<S59>/Divide4'
   *  Sum: '<S61>/Sum1'
   */
  tmp = (int64_T)rtb_Divide4_e + rtb_Sum1_l;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Switch: '<S62>/Switch2' incorporates:
   *  RelationalOperator: '<S62>/LowerRelop1'
   *  RelationalOperator: '<S62>/UpperRelop'
   *  Sum: '<S59>/Sum6'
   *  Switch: '<S62>/Switch'
   */
  if ((int32_T)tmp > (rtu_satMax << 4)) {
    *rty_pi_out = rtu_satMax;
  } else if ((int32_T)tmp < (rtu_satMin << 4)) {
    /* Switch: '<S62>/Switch' */
    *rty_pi_out = rtu_satMin;
  } else {
    *rty_pi_out = (int16_T)((int32_T)tmp >> 4);
  }

  /* End of Switch: '<S62>/Switch2' */

  /* Update for UnitDelay: '<S59>/UnitDelay' incorporates:
   *  Product: '<S59>/Divide2'
   *  Sum: '<S59>/Sum3'
   *  Sum: '<S59>/Sum6'
   */
  localDW->UnitDelay_DSTATE = (int32_T)(((int64_T)((*rty_pi_out << 4) - (int32_T)
    tmp) * rtu_Kb) >> 10);

  /* Update for UnitDelay: '<S61>/UnitDelay' incorporates:
   *  Sum: '<S61>/Sum1'
   */
  localDW->UnitDelay_DSTATE_p = rtb_Sum1_l;
}

/* System initialize for atomic system: '<S77>/pi_speed' */
static void pi_speed_Init(DW_pi_speed *localDW)
{
  /* InitializeConditions for Delay: '<S81>/Resettable Delay' */
  localDW->icLoad = 1U;
}

/* Output and update for atomic system: '<S77>/pi_speed' */
static int16_T pi_speed(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I, int16_T
  rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_ext_limProt,
  uint8_T rtu_reset, const ConstB_pi_speed *localC, DW_pi_speed *localDW,
  ZCE_pi_speed *localZCE)
{
  int16_T rty_pi_out_0;
  int64_T tmp;
  int32_T rtb_Divide4_hl;
  int32_T rtb_Sum1_b1;

  /* Product: '<S80>/Divide4' */
  rtb_Divide4_hl = (rtu_err * rtu_P) >> 2;

  /* Delay: '<S81>/Resettable Delay' incorporates:
   *  DataTypeConversion: '<S81>/Data Type Conversion2'
   */
  if ((rtu_reset > 0) && (localZCE->ResettableDelay_Reset_ZCE != POS_ZCSIG)) {
    localDW->icLoad = 1U;
  }

  localZCE->ResettableDelay_Reset_ZCE = (ZCSigState)(rtu_reset > 0);
  if (localDW->icLoad != 0) {
    localDW->ResettableDelay_DSTATE = localC->DataTypeConversion2;
  }

  /* Product: '<S80>/Divide1' incorporates:
   *  Product: '<S80>/Divide4'
   */
  tmp = ((int64_T)rtb_Divide4_hl * rtu_I) >> 10;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Sum: '<S80>/Sum2' incorporates:
   *  Product: '<S80>/Divide1'
   *  UnitDelay: '<S80>/UnitDelay'
   */
  tmp = (((int64_T)(int32_T)tmp + rtu_ext_limProt) + ((int64_T)
          localDW->UnitDelay_DSTATE << 2)) >> 2;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Sum: '<S81>/Sum1' incorporates:
   *  Delay: '<S81>/Resettable Delay'
   *  Sum: '<S80>/Sum2'
   */
  rtb_Sum1_b1 = (int32_T)tmp + localDW->ResettableDelay_DSTATE;

  /* Sum: '<S80>/Sum6' incorporates:
   *  DataTypeConversion: '<S81>/Data Type Conversion1'
   *  Product: '<S80>/Divide4'
   *  Sum: '<S81>/Sum1'
   */
  tmp = ((int64_T)(rtb_Sum1_b1 >> 2) << 4) + rtb_Divide4_hl;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Switch: '<S82>/Switch2' incorporates:
   *  RelationalOperator: '<S82>/LowerRelop1'
   *  RelationalOperator: '<S82>/UpperRelop'
   *  Sum: '<S80>/Sum6'
   *  Switch: '<S82>/Switch'
   */
  if ((int32_T)tmp > (rtu_satMax << 4)) {
    rty_pi_out_0 = rtu_satMax;
  } else if ((int32_T)tmp < (rtu_satMin << 4)) {
    /* Switch: '<S82>/Switch' */
    rty_pi_out_0 = rtu_satMin;
  } else {
    rty_pi_out_0 = (int16_T)((int32_T)tmp >> 4);
  }

  /* End of Switch: '<S82>/Switch2' */

  /* Update for UnitDelay: '<S80>/UnitDelay' incorporates:
   *  Product: '<S80>/Divide2'
   *  Sum: '<S80>/Sum3'
   *  Sum: '<S80>/Sum6'
   */
  localDW->UnitDelay_DSTATE = (int32_T)(((int64_T)((rty_pi_out_0 << 4) -
    (int32_T)tmp) * rtu_Kb) >> 12);

  /* Update for Delay: '<S81>/Resettable Delay' incorporates:
   *  Sum: '<S81>/Sum1'
   */
  localDW->icLoad = 0U;
  localDW->ResettableDelay_DSTATE = rtb_Sum1_b1;
  return rty_pi_out_0;
}

/* Model step function */
void PMSM_Controller_step(RT_MODEL *const rtM)
{
  DW *rtDW = rtM->dwork;
  PrevZCX *rtPrevZCX = rtM->prevZCSigState;
  ExtU *rtU = (ExtU *) rtM->inputs;
  ExtY *rtY = (ExtY *) rtM->outputs;
  int32_T rtb_Divide;
  int32_T rtb_Gain1;
  int32_T rtb_MultiportSwitch_idx_0;
  int32_T rtb_MultiportSwitch_idx_1;
  uint32_T tmp;
  int16_T rtb_DataTypeConversion[2];
  int16_T rtb_TmpSignalConversionAtLow_Pa[2];
  int16_T rtb_Abs5;
  int16_T rtb_Abs5_h;
  int16_T rtb_Divide1_fi;
  int16_T rtb_Gain4;
  int16_T rtb_Max;
  int16_T rtb_Sign;
  int16_T rtb_Switch2_ip;
  int16_T rtb_Switch3_c;
  int16_T rtb_Switch_b;
  int16_T rtb_Switch_oi;
  uint16_T rtb_LogicalOperator3;
  int8_T UnitDelay3;
  int8_T rtb_Sum2;
  int8_T rtb_Sum2_tmp;
  uint8_T rtb_Add_cr;
  uint8_T rtb_DataTypeConversion1_c;
  uint8_T rtb_Switch2_fu;
  uint8_T rtb_UnitDelay;
  uint8_T rtb_z_ctrlMod;
  boolean_T rtb_LogicalOperator2;
  boolean_T rtb_LogicalOperator4;
  boolean_T rtb_LogicalOperator_p;
  boolean_T rtb_RelationalOperator4_f;
  boolean_T rtb_n_commDeacv;

  /* Outputs for Atomic SubSystem: '<Root>/PMSM_Controller' */
  /* Logic: '<S7>/Edge_Detect' incorporates:
   *  Delay: '<S7>/Delay'
   *  Delay: '<S7>/Delay1'
   *  Delay: '<S7>/Delay2'
   *  Inport: '<Root>/hall_a'
   *  Inport: '<Root>/hall_b'
   *  Inport: '<Root>/hall_c'
   */
  rtb_LogicalOperator_p = (boolean_T)((rtU->hall_a != 0) ^ (rtDW->Delay_DSTATE
    != 0) ^ (rtU->hall_b != 0) ^ (rtDW->Delay1_DSTATE != 0) ^ (rtU->hall_c != 0))
    ^ (rtDW->Delay2_DSTATE != 0);

  /* Sum: '<S9>/Add' incorporates:
   *  Gain: '<S9>/Gain'
   *  Gain: '<S9>/Gain1'
   *  Inport: '<Root>/hall_a'
   *  Inport: '<Root>/hall_b'
   *  Inport: '<Root>/hall_c'
   */
  rtb_Add_cr = (uint8_T)((uint32_T)(uint8_T)((uint32_T)(uint8_T)(rtU->hall_c <<
    2) + (uint8_T)(rtU->hall_b << 1)) + rtU->hall_a);

  /* If: '<S2>/If2' incorporates:
   *  If: '<S10>/If2'
   *  Inport: '<S15>/z_counterRawPrev'
   *  UnitDelay: '<S10>/UnitDelay3'
   */
  if (rtb_LogicalOperator_p) {
    /* Outputs for IfAction SubSystem: '<S2>/Direction_Detection' incorporates:
     *  ActionPort: '<S6>/Action Port'
     */
    /* UnitDelay: '<S6>/UnitDelay3' */
    UnitDelay3 = rtDW->Switch2_i;

    /* End of Outputs for SubSystem: '<S2>/Direction_Detection' */

    /* Selector: '<S9>/Selector' incorporates:
     *  Constant: '<S9>/vec_hallToPos'
     */
    rtb_Sum2_tmp = rtConstP.vec_hallToPos_Value[rtb_Add_cr];

    /* Outputs for IfAction SubSystem: '<S2>/Direction_Detection' incorporates:
     *  ActionPort: '<S6>/Action Port'
     */
    /* Sum: '<S6>/Sum2' incorporates:
     *  Constant: '<S9>/vec_hallToPos'
     *  Selector: '<S9>/Selector'
     *  UnitDelay: '<S6>/UnitDelay2'
     */
    rtb_Sum2 = (int8_T)(rtb_Sum2_tmp - rtDW->UnitDelay2_DSTATE_j);

    /* Switch: '<S6>/Switch2' incorporates:
     *  Constant: '<S6>/Constant20'
     *  Constant: '<S6>/Constant8'
     *  Logic: '<S6>/Logical Operator3'
     *  RelationalOperator: '<S6>/Relational Operator1'
     *  RelationalOperator: '<S6>/Relational Operator6'
     */
    if ((rtb_Sum2 == 1) || (rtb_Sum2 == -5)) {
      /* Switch: '<S6>/Switch2' incorporates:
       *  Constant: '<S6>/Constant24'
       */
      rtDW->Switch2_i = 1;
    } else {
      /* Switch: '<S6>/Switch2' incorporates:
       *  Constant: '<S6>/Constant23'
       */
      rtDW->Switch2_i = -1;
    }

    /* End of Switch: '<S6>/Switch2' */

    /* Update for UnitDelay: '<S6>/UnitDelay2' */
    rtDW->UnitDelay2_DSTATE_j = rtb_Sum2_tmp;

    /* End of Outputs for SubSystem: '<S2>/Direction_Detection' */

    /* Outputs for IfAction SubSystem: '<S10>/Raw_Motor_Speed_Estimation' incorporates:
     *  ActionPort: '<S15>/Action Port'
     */
    /* RelationalOperator: '<S15>/Relational Operator4' */
    rtb_RelationalOperator4_f = (rtDW->Switch2_i != UnitDelay3);
    rtDW->z_counterRawPrev = rtDW->UnitDelay3_DSTATE;

    /* Switch: '<S15>/Switch3' incorporates:
     *  Constant: '<S15>/Constant4'
     *  Inport: '<S15>/z_counterRawPrev'
     *  Logic: '<S15>/Logical Operator1'
     *  Switch: '<S15>/Switch2'
     *  UnitDelay: '<S10>/UnitDelay3'
     *  UnitDelay: '<S15>/UnitDelay1'
     */
    if (rtb_RelationalOperator4_f && rtDW->UnitDelay1_DSTATE_i) {
      rtb_Switch3_c = 0;
    } else if (rtb_RelationalOperator4_f) {
      /* Switch: '<S15>/Switch3' incorporates:
       *  Switch: '<S15>/Switch2'
       *  UnitDelay: '<S10>/UnitDelay4'
       */
      rtb_Switch3_c = rtDW->UnitDelay4_DSTATE;
    } else {
      /* Product: '<S15>/Divide13' incorporates:
       *  Sum: '<S15>/Sum13'
       *  Switch: '<S15>/Switch2'
       *  UnitDelay: '<S15>/UnitDelay2'
       *  UnitDelay: '<S15>/UnitDelay3'
       *  UnitDelay: '<S15>/UnitDelay5'
       */
      tmp = 8000000U / (((rtDW->UnitDelay2_DSTATE + rtDW->UnitDelay3_DSTATE_l) +
                         rtDW->UnitDelay5_DSTATE) + rtDW->z_counterRawPrev);
      if (tmp > 32767U) {
        tmp = 32767U;
      }

      /* Switch: '<S15>/Switch3' incorporates:
       *  Product: '<S15>/Divide13'
       *  Switch: '<S15>/Switch2'
       */
      rtb_Switch3_c = (int16_T)tmp;
    }

    /* End of Switch: '<S15>/Switch3' */

    /* Product: '<S15>/Divide11' incorporates:
     *  Switch: '<S15>/Switch3'
     */
    rtDW->Divide11 = (int16_T)(rtb_Switch3_c * rtDW->Switch2_i);

    /* Update for UnitDelay: '<S15>/UnitDelay1' */
    rtDW->UnitDelay1_DSTATE_i = rtb_RelationalOperator4_f;

    /* Update for UnitDelay: '<S15>/UnitDelay2' incorporates:
     *  UnitDelay: '<S15>/UnitDelay3'
     */
    rtDW->UnitDelay2_DSTATE = rtDW->UnitDelay3_DSTATE_l;

    /* Update for UnitDelay: '<S15>/UnitDelay3' incorporates:
     *  UnitDelay: '<S15>/UnitDelay5'
     */
    rtDW->UnitDelay3_DSTATE_l = rtDW->UnitDelay5_DSTATE;

    /* Update for UnitDelay: '<S15>/UnitDelay5' */
    rtDW->UnitDelay5_DSTATE = rtDW->z_counterRawPrev;

    /* End of Outputs for SubSystem: '<S10>/Raw_Motor_Speed_Estimation' */
  }

  /* End of If: '<S2>/If2' */

  /* Switch: '<S8>/Switch3' incorporates:
   *  Constant: '<S8>/Constant16'
   *  Constant: '<S8>/Constant2'
   *  Constant: '<S9>/vec_hallToPos'
   *  RelationalOperator: '<S8>/Relational Operator7'
   *  Selector: '<S9>/Selector'
   *  Sum: '<S8>/Sum1'
   */
  if (rtDW->Switch2_i == 1) {
    rtb_Sum2 = rtConstP.vec_hallToPos_Value[rtb_Add_cr];
  } else {
    rtb_Sum2 = (int8_T)(rtConstP.vec_hallToPos_Value[rtb_Add_cr] + 1);
  }

  /* End of Switch: '<S8>/Switch3' */

  /* MinMax: '<S8>/MinMax' incorporates:
   *  Inport: '<Root>/hw_count'
   */
  if (rtU->hw_count < rtDW->z_counterRawPrev) {
    tmp = rtU->hw_count;
  } else {
    tmp = rtDW->z_counterRawPrev;
  }

  /* End of MinMax: '<S8>/MinMax' */

  /* Sum: '<S8>/Sum3' incorporates:
   *  Product: '<S8>/Divide1'
   *  Product: '<S8>/Divide3'
   */
  rtb_Switch3_c = (int16_T)(((int16_T)((int16_T)(((uint64_T)tmp << 14) /
    rtDW->z_counterRawPrev) * rtDW->Switch2_i) + (rtb_Sum2 << 14)) >> 2);

  /* MinMax: '<S8>/MinMax1' incorporates:
   *  Constant: '<S8>/Constant1'
   *  Sum: '<S8>/Sum3'
   *  Switch: '<S8>/Switch2'
   */
  if (rtb_Switch3_c <= 0) {
    rtb_Switch3_c = 0;
  }

  /* End of MinMax: '<S8>/MinMax1' */

  /* Sum: '<S11>/Add2' incorporates:
   *  Constant: '<S11>/Constant2'
   *  Product: '<S8>/Divide2'
   */
  rtb_Switch3_c = (int16_T)((((15 * rtb_Switch3_c) >> 4) + 3840) >> 2);

  /* If: '<S11>/If' incorporates:
   *  Constant: '<S11>/Constant3'
   *  DataTypeConversion: '<S11>/Data Type Conversion'
   *  Inport: '<S12>/In1'
   *  Merge: '<S11>/Merge'
   *  Sum: '<S11>/Add'
   *  Sum: '<S11>/Add2'
   */
  if ((int16_T)(rtb_Switch3_c >> 4) >= 360) {
    /* Outputs for IfAction SubSystem: '<S11>/If Action Subsystem' incorporates:
     *  ActionPort: '<S12>/Action Port'
     */
    rtb_Switch3_c = (int16_T)(rtb_Switch3_c - 5760);

    /* End of Outputs for SubSystem: '<S11>/If Action Subsystem' */
  }

  /* End of If: '<S11>/If' */

  /* Switch: '<S10>/Switch2' incorporates:
   *  Constant: '<S10>/Constant4'
   *  Inport: '<Root>/hw_count'
   *  Product: '<S15>/Divide11'
   *  RelationalOperator: '<S10>/Relational Operator2'
   */
  if (rtU->hw_count >= 400000U) {
    rtb_Switch2_ip = 0;
  } else {
    rtb_Switch2_ip = rtDW->Divide11;
  }

  /* End of Switch: '<S10>/Switch2' */

  /* Abs: '<S10>/Abs5' incorporates:
   *  Switch: '<S10>/Switch2'
   */
  if (rtb_Switch2_ip < 0) {
    rtb_Abs5 = (int16_T)-rtb_Switch2_ip;
  } else {
    rtb_Abs5 = rtb_Switch2_ip;
  }

  /* End of Abs: '<S10>/Abs5' */

  /* If: '<S10>/If1' */
  if (rtb_LogicalOperator_p) {
    /* Outputs for IfAction SubSystem: '<S10>/Subsystem' incorporates:
     *  ActionPort: '<S16>/Action Port'
     */
    /* Relay: '<S16>/n_commDeacv' incorporates:
     *  Abs: '<S10>/Abs5'
     */
    rtDW->n_commDeacv_Mode = ((rtb_Abs5 >= 120) || ((rtb_Abs5 > 60) &&
      rtDW->n_commDeacv_Mode));

    /* RelationalOperator: '<S18>/Compare' incorporates:
     *  Constant: '<S18>/Constant'
     *  Relay: '<S16>/n_commDeacv'
     *  Sum: '<S16>/Sum13'
     *  UnitDelay: '<S16>/UnitDelay2'
     *  UnitDelay: '<S16>/UnitDelay3'
     *  UnitDelay: '<S16>/UnitDelay5'
     */
    rtDW->Compare = ((uint16_T)((uint32_T)(uint16_T)((uint32_T)(uint16_T)
      ((uint32_T)rtDW->UnitDelay2_DSTATE_f + rtDW->UnitDelay3_DSTATE_lh) +
      rtDW->UnitDelay5_DSTATE_f) + rtDW->n_commDeacv_Mode) >= 4);

    /* Update for UnitDelay: '<S16>/UnitDelay2' incorporates:
     *  UnitDelay: '<S16>/UnitDelay3'
     */
    rtDW->UnitDelay2_DSTATE_f = rtDW->UnitDelay3_DSTATE_lh;

    /* Update for UnitDelay: '<S16>/UnitDelay3' incorporates:
     *  UnitDelay: '<S16>/UnitDelay5'
     */
    rtDW->UnitDelay3_DSTATE_lh = rtDW->UnitDelay5_DSTATE_f;

    /* Update for UnitDelay: '<S16>/UnitDelay5' incorporates:
     *  Logic: '<S16>/Logical Operator3'
     *  Relay: '<S16>/n_commDeacv'
     */
    rtDW->UnitDelay5_DSTATE_f = rtDW->n_commDeacv_Mode;

    /* End of Outputs for SubSystem: '<S10>/Subsystem' */
  }

  /* End of If: '<S10>/If1' */

  /* Switch: '<S2>/Switch' incorporates:
   *  Inport: '<Root>/b_hall_calibrate'
   *  Inport: '<Root>/open_theta'
   *  Merge: '<S11>/Merge'
   */
  if (rtU->b_hall_calibrate) {
    rtb_Switch_b = (int16_T)(rtU->open_theta << 4);
  } else {
    rtb_Switch_b = rtb_Switch3_c;
  }

  /* End of Switch: '<S2>/Switch' */

  /* Abs: '<S3>/Abs2' incorporates:
   *  Switch: '<S10>/Switch2'
   */
  if (rtb_Switch2_ip < 0) {
    rtb_LogicalOperator3 = (uint16_T)((uint32_T)-rtb_Switch2_ip >> 2);
  } else {
    rtb_LogicalOperator3 = (uint16_T)((uint32_T)rtb_Switch2_ip >> 2);
  }

  /* End of Abs: '<S3>/Abs2' */

  /* UnitDelay: '<S34>/UnitDelay' */
  rtb_UnitDelay = rtDW->UnitDelay_DSTATE_j;

  /* Outport: '<Root>/VqPrev' incorporates:
   *  UnitDelay: '<S5>/UnitDelay2'
   */
  rtY->VqPrev = rtDW->UnitDelay2_DSTATE_p;

  /* Switch: '<S34>/Switch3' incorporates:
   *  Abs: '<S10>/Abs5'
   *  Abs: '<S34>/Abs4'
   *  Constant: '<S34>/CTRL_COMM4'
   *  Inport: '<Root>/b_motEna'
   *  Logic: '<S34>/Logical Operator1'
   *  RelationalOperator: '<S10>/Relational Operator9'
   *  RelationalOperator: '<S34>/Relational Operator7'
   *  S-Function (sfix_bitop): '<S34>/Bitwise Operator1'
   *  UnitDelay: '<S5>/UnitDelay2'
   */
  if ((rtb_UnitDelay & 4U) != 0U) {
    rtb_LogicalOperator_p = true;
  } else {
    if (rtDW->UnitDelay2_DSTATE_p < 0) {
      /* Abs: '<S34>/Abs4' incorporates:
       *  UnitDelay: '<S5>/UnitDelay2'
       */
      rtb_Divide1_fi = (int16_T)-rtDW->UnitDelay2_DSTATE_p;
    } else {
      /* Abs: '<S34>/Abs4' incorporates:
       *  UnitDelay: '<S5>/UnitDelay2'
       */
      rtb_Divide1_fi = rtDW->UnitDelay2_DSTATE_p;
    }

    rtb_LogicalOperator_p = (rtU->b_motEna && (rtb_Abs5 < 12) && (rtb_Divide1_fi
      > 960));
  }

  /* End of Switch: '<S34>/Switch3' */

  /* Sum: '<S34>/Sum' incorporates:
   *  Constant: '<S34>/CTRL_COMM'
   *  Constant: '<S34>/CTRL_COMM1'
   *  DataTypeConversion: '<S34>/Data Type Conversion3'
   *  Gain: '<S34>/g_Hb'
   *  Gain: '<S34>/g_Hb1'
   *  RelationalOperator: '<S34>/Relational Operator1'
   *  RelationalOperator: '<S34>/Relational Operator3'
   */
  rtb_DataTypeConversion1_c = (uint8_T)(((uint32_T)((rtb_Add_cr == 7) << 1) +
    (rtb_Add_cr == 0)) + (rtb_LogicalOperator_p << 2));

  /* Outputs for Atomic SubSystem: '<S34>/Debounce_Filter' */
  /* RelationalOperator: '<S34>/Relational Operator2' incorporates:
   *  Constant: '<S34>/CTRL_COMM2'
   *  Constant: '<S34>/t_errDequal'
   *  Constant: '<S34>/t_errQual'
   */
  Debounce_Filter(rtb_DataTypeConversion1_c != 0, 1600, 12000,
                  &rtb_RelationalOperator4_f, &rtDW->Debounce_Filter_i);

  /* End of Outputs for SubSystem: '<S34>/Debounce_Filter' */

  /* Logic: '<S21>/Logical Operator12' incorporates:
   *  Inport: '<Root>/b_motEna'
   *  Logic: '<S21>/Logical Operator7'
   */
  rtb_n_commDeacv = ((!rtb_RelationalOperator4_f) && rtU->b_motEna);

  /* Logic: '<S21>/Logical Operator4' incorporates:
   *  Constant: '<S21>/constant8'
   *  Inport: '<Root>/b_hall_calibrate'
   *  Inport: '<Root>/n_ctrlModReq'
   *  Logic: '<S21>/Logical Operator11'
   *  Logic: '<S21>/Logical Operator8'
   *  RelationalOperator: '<S21>/Relational Operator10'
   */
  rtb_LogicalOperator4 = (rtU->b_hall_calibrate || (!rtDW->Compare) ||
    (!rtb_n_commDeacv) || (rtU->n_ctrlModReq == 0));

  /* Relay: '<S21>/n_SpeedCtrl' */
  rtDW->n_SpeedCtrl_Mode = ((rtb_LogicalOperator3 >= 300) ||
    ((rtb_LogicalOperator3 > 200) && rtDW->n_SpeedCtrl_Mode));
  rtb_LogicalOperator_p = rtDW->n_SpeedCtrl_Mode;

  /* Logic: '<S21>/Logical Operator10' incorporates:
   *  Inport: '<Root>/b_cruiseEna'
   */
  rtb_LogicalOperator_p = (rtb_LogicalOperator_p && rtU->b_cruiseEna);

  /* Logic: '<S21>/Logical Operator2' incorporates:
   *  Constant: '<S21>/constant'
   *  Inport: '<Root>/n_ctrlModReq'
   *  Logic: '<S21>/Logical Operator5'
   *  RelationalOperator: '<S21>/Relational Operator4'
   */
  rtb_LogicalOperator2 = ((rtU->n_ctrlModReq == 2) && (!rtb_LogicalOperator_p));

  /* Logic: '<S21>/Logical Operator1' incorporates:
   *  Constant: '<S21>/constant1'
   *  Inport: '<Root>/n_ctrlModReq'
   *  RelationalOperator: '<S21>/Relational Operator1'
   */
  rtb_LogicalOperator_p = ((rtU->n_ctrlModReq == 1) || rtb_LogicalOperator_p);

  /* Chart: '<S3>/Control_Mode_Manager' incorporates:
   *  Logic: '<S21>/Logical Operator3'
   *  Logic: '<S21>/Logical Operator6'
   *  Logic: '<S21>/Logical Operator9'
   */
  if (rtDW->is_active_c5_PMSM_Controller == 0U) {
    rtDW->is_active_c5_PMSM_Controller = 1U;
    rtDW->is_c5_PMSM_Controller = IN_OPEN;
    rtb_z_ctrlMod = OPEN_MODE;
  } else if (rtDW->is_c5_PMSM_Controller == 1) {
    if (rtb_LogicalOperator4) {
      rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD;
      rtDW->is_c5_PMSM_Controller = IN_OPEN;
      rtb_z_ctrlMod = OPEN_MODE;
    } else if (rtDW->is_ACTIVE == 1) {
      rtb_z_ctrlMod = SPD_MODE;
      if (!rtb_LogicalOperator_p) {
        if (rtb_LogicalOperator2) {
          rtDW->is_ACTIVE = IN_TORQUE_MODE;
          rtb_z_ctrlMod = TRQ_MODE;
        } else {
          rtDW->is_ACTIVE = IN_SPEED_MODE;
        }
      }
    } else {
      /* case IN_TORQUE_MODE: */
      rtb_z_ctrlMod = TRQ_MODE;
      if (!rtb_LogicalOperator2) {
        rtDW->is_ACTIVE = IN_SPEED_MODE;
        rtb_z_ctrlMod = SPD_MODE;
      }
    }
  } else {
    /* case IN_OPEN: */
    rtb_z_ctrlMod = OPEN_MODE;
    if ((!rtb_LogicalOperator4) && (rtb_LogicalOperator2 ||
         rtb_LogicalOperator_p)) {
      rtDW->is_c5_PMSM_Controller = IN_ACTIVE;
      if (rtb_LogicalOperator2) {
        rtDW->is_ACTIVE = IN_TORQUE_MODE;
        rtb_z_ctrlMod = TRQ_MODE;
      } else {
        rtDW->is_ACTIVE = IN_SPEED_MODE;
        rtb_z_ctrlMod = SPD_MODE;
      }
    }
  }

  /* End of Chart: '<S3>/Control_Mode_Manager' */

  /* Switch: '<S22>/Switch' incorporates:
   *  Constant: '<S22>/Constant3'
   *  Inport: '<Root>/input_target'
   */
  if (rtU->input_target > 60) {
    /* Switch: '<S22>/Switch1' incorporates:
     *  Constant: '<S22>/Constant1'
     *  DataTypeConversion: '<S22>/Data Type Conversion'
     *  Switch: '<S22>/Switch'
     */
    if (rtb_n_commDeacv) {
      rtb_Switch_oi = rtU->input_target;
    } else {
      rtb_Switch_oi = 0;
    }

    /* End of Switch: '<S22>/Switch1' */
  } else {
    rtb_Switch_oi = 0;
  }

  /* End of Switch: '<S22>/Switch' */

  /* Switch: '<S22>/Switch3' incorporates:
   *  Constant: '<S22>/Constant4'
   *  DataTypeConversion: '<S22>/Data Type Conversion2'
   *  Inport: '<Root>/vq_open_target'
   */
  if (rtb_n_commDeacv) {
    rtb_Abs5_h = rtU->vq_open_target;
  } else {
    rtb_Abs5_h = 0;
  }

  /* End of Switch: '<S22>/Switch3' */

  /* If: '<S23>/If' incorporates:
   *  Inport: '<Root>/b_hall_calibrate'
   *  Inport: '<S27>/vq_in'
   *  Switch: '<S22>/Switch3'
   */
  if (rtU->b_hall_calibrate) {
    /* Switch: '<S22>/Switch2' incorporates:
     *  Constant: '<S22>/Constant2'
     *  DataTypeConversion: '<S22>/Data Type Conversion1'
     *  Inport: '<Root>/vd_open_target'
     *  Inport: '<S27>/vd_in'
     */
    if (rtb_n_commDeacv) {
      /* Outputs for IfAction SubSystem: '<S23>/If Action Subsystem' incorporates:
       *  ActionPort: '<S27>/Action Port'
       */
      rtDW->Merge[0] = rtU->vd_open_target;

      /* End of Outputs for SubSystem: '<S23>/If Action Subsystem' */
    } else {
      /* Outputs for IfAction SubSystem: '<S23>/If Action Subsystem' incorporates:
       *  ActionPort: '<S27>/Action Port'
       */
      rtDW->Merge[0] = 0;

      /* End of Outputs for SubSystem: '<S23>/If Action Subsystem' */
    }

    /* End of Switch: '<S22>/Switch2' */

    /* Outputs for IfAction SubSystem: '<S23>/If Action Subsystem' incorporates:
     *  ActionPort: '<S27>/Action Port'
     */
    rtDW->Merge[1] = rtb_Abs5_h;

    /* End of Outputs for SubSystem: '<S23>/If Action Subsystem' */
  } else if (rtb_z_ctrlMod == 0) {
    /* Outputs for IfAction SubSystem: '<S23>/open_mode' incorporates:
     *  ActionPort: '<S28>/Action Port'
     */
    /* RelationalOperator: '<S28>/Equal1' incorporates:
     *  Switch: '<S22>/Switch3'
     *  UnitDelay: '<S28>/Unit Delay'
     */
    rtb_LogicalOperator_p = (rtDW->UnitDelay_DSTATE != rtb_Abs5_h);

    /* If: '<S30>/If' */
    if (rtb_LogicalOperator_p) {
      /* Outputs for IfAction SubSystem: '<S30>/Subsystem' incorporates:
       *  ActionPort: '<S32>/Action Port'
       */
      /* Sum: '<S32>/Add' incorporates:
       *  Signum: '<S32>/Sign'
       *  Switch: '<S22>/Switch3'
       *  UnitDelay: '<S5>/UnitDelay2'
       */
      rtb_Sign = (int16_T)((rtb_Abs5_h - rtDW->UnitDelay2_DSTATE_p) >> 2);

      /* Signum: '<S32>/Sign' */
      if (rtb_Sign < 0) {
        rtb_Sign = -1;
      } else {
        rtb_Sign = (int16_T)(rtb_Sign > 0);
      }

      /* End of Signum: '<S32>/Sign' */

      /* Product: '<S32>/Divide' incorporates:
       *  Constant: '<S28>/Constant5'
       */
      rtDW->Divide = (int16_T)(rtb_Sign * 6);

      /* Switch: '<S32>/Switch' incorporates:
       *  Switch: '<S32>/Switch1'
       */
      if (rtb_Sign > 0) {
        /* Switch: '<S32>/Switch' incorporates:
         *  Switch: '<S22>/Switch3'
         */
        rtDW->Switch = rtb_Abs5_h;

        /* Switch: '<S32>/Switch1' incorporates:
         *  UnitDelay: '<S5>/UnitDelay2'
         */
        rtDW->Switch1 = rtDW->UnitDelay2_DSTATE_p;
      } else {
        /* Switch: '<S32>/Switch' incorporates:
         *  UnitDelay: '<S5>/UnitDelay2'
         */
        rtDW->Switch = rtDW->UnitDelay2_DSTATE_p;

        /* Switch: '<S32>/Switch1' incorporates:
         *  Switch: '<S22>/Switch3'
         */
        rtDW->Switch1 = rtb_Abs5_h;
      }

      /* End of Switch: '<S32>/Switch' */
      /* End of Outputs for SubSystem: '<S30>/Subsystem' */

      /* Switch: '<S33>/Switch1' incorporates:
       *  UnitDelay: '<S5>/UnitDelay2'
       */
      rtb_Sign = rtDW->UnitDelay2_DSTATE_p;
    } else {
      /* Switch: '<S33>/Switch1' incorporates:
       *  UnitDelay: '<S33>/UnitDelay'
       */
      rtb_Sign = rtDW->UnitDelay_DSTATE_d;
    }

    /* End of If: '<S30>/If' */

    /* Sum: '<S30>/Add2' incorporates:
     *  Product: '<S32>/Divide'
     */
    rtb_Gain1 = ((rtb_Sign << 1) + rtDW->Divide) >> 1;
    if (rtb_Gain1 > 32767) {
      rtb_Gain1 = 32767;
    } else {
      if (rtb_Gain1 < -32768) {
        rtb_Gain1 = -32768;
      }
    }

    /* Switch: '<S28>/Switch' incorporates:
     *  Switch: '<S22>/Switch'
     */
    if (rtb_Switch_oi > 0) {
      /* Switch: '<S31>/Switch2' incorporates:
       *  RelationalOperator: '<S31>/LowerRelop1'
       *  RelationalOperator: '<S31>/UpperRelop'
       *  Sum: '<S30>/Add2'
       *  Switch: '<S31>/Switch'
       *  Switch: '<S32>/Switch'
       *  Switch: '<S32>/Switch1'
       */
      if ((int16_T)rtb_Gain1 > rtDW->Switch) {
        /* Merge: '<S23>/Merge' incorporates:
         *  Switch: '<S28>/Switch'
         */
        rtDW->Merge[1] = rtDW->Switch;
      } else if ((int16_T)rtb_Gain1 < rtDW->Switch1) {
        /* Merge: '<S23>/Merge' incorporates:
         *  Switch: '<S28>/Switch'
         *  Switch: '<S31>/Switch'
         *  Switch: '<S32>/Switch1'
         */
        rtDW->Merge[1] = rtDW->Switch1;
      } else {
        /* Merge: '<S23>/Merge' incorporates:
         *  Switch: '<S28>/Switch'
         */
        rtDW->Merge[1] = (int16_T)rtb_Gain1;
      }

      /* End of Switch: '<S31>/Switch2' */
    } else {
      /* Merge: '<S23>/Merge' incorporates:
       *  Constant: '<S28>/Constant1'
       */
      rtDW->Merge[1] = 0;
    }

    /* End of Switch: '<S28>/Switch' */

    /* Merge: '<S23>/Merge' incorporates:
     *  Constant: '<S28>/Constant3'
     *  SignalConversion generated from: '<S28>/open_voltage'
     */
    rtDW->Merge[0] = 0;

    /* Update for UnitDelay: '<S28>/Unit Delay' incorporates:
     *  Switch: '<S22>/Switch3'
     */
    rtDW->UnitDelay_DSTATE = rtb_Abs5_h;

    /* Switch: '<S33>/Switch2' */
    if (rtb_LogicalOperator_p) {
      /* Update for UnitDelay: '<S33>/UnitDelay' incorporates:
       *  UnitDelay: '<S5>/UnitDelay2'
       */
      rtDW->UnitDelay_DSTATE_d = rtDW->UnitDelay2_DSTATE_p;
    } else {
      /* Update for UnitDelay: '<S33>/UnitDelay' incorporates:
       *  Sum: '<S30>/Add2'
       */
      rtDW->UnitDelay_DSTATE_d = (int16_T)rtb_Gain1;
    }

    /* End of Switch: '<S33>/Switch2' */
    /* End of Outputs for SubSystem: '<S23>/open_mode' */
  } else {
    /* Outputs for IfAction SubSystem: '<S23>/torque_mode' incorporates:
     *  ActionPort: '<S29>/Action Port'
     */
    /* Product: '<S29>/Divide1' incorporates:
     *  Inport: '<Root>/i_dc_limit'
     *  Inport: '<Root>/speed_limit'
     *  Product: '<S29>/Divide4'
     *  Switch: '<S22>/Switch'
     */
    rtb_Gain1 = ((uint16_T)((rtU->i_dc_limit << 8) / rtU->speed_limit) *
                 rtb_Switch_oi) >> 8;
    if (rtb_Gain1 > 32767) {
      rtb_Gain1 = 32767;
    } else {
      if (rtb_Gain1 < -32768) {
        rtb_Gain1 = -32768;
      }
    }

    /* Product: '<S29>/Divide1' */
    rtDW->Divide1 = (int16_T)rtb_Gain1;

    /* End of Outputs for SubSystem: '<S23>/torque_mode' */
  }

  /* End of If: '<S23>/If' */

  /* Outputs for Atomic SubSystem: '<S34>/either_edge' */
  rtb_LogicalOperator_p = either_edge(rtb_RelationalOperator4_f,
    &rtDW->either_edge_f);

  /* End of Outputs for SubSystem: '<S34>/either_edge' */

  /* Switch: '<S34>/Switch1' */
  if (rtb_LogicalOperator_p) {
    rtb_UnitDelay = rtb_DataTypeConversion1_c;
  }

  /* End of Switch: '<S34>/Switch1' */

  /* Gain: '<S51>/Multiply' incorporates:
   *  DataTypeConversion: '<S54>/Data Type Conversion'
   *  Inport: '<Root>/adc_a'
   *  Inport: '<Root>/adc_b'
   */
  rtb_Gain1 = (12351 * rtU->adc_a) >> 11;
  if (rtb_Gain1 > 32767) {
    rtb_Gain1 = 32767;
  } else {
    if (rtb_Gain1 < -32768) {
      rtb_Gain1 = -32768;
    }
  }

  rtb_DataTypeConversion[0] = (int16_T)rtb_Gain1;
  rtb_MultiportSwitch_idx_0 = (12351 * rtU->adc_b) >> 11;
  if (rtb_MultiportSwitch_idx_0 > 32767) {
    rtb_MultiportSwitch_idx_0 = 32767;
  } else {
    if (rtb_MultiportSwitch_idx_0 < -32768) {
      rtb_MultiportSwitch_idx_0 = -32768;
    }
  }

  rtb_DataTypeConversion[1] = (int16_T)rtb_MultiportSwitch_idx_0;

  /* Sum: '<S45>/Add' incorporates:
   *  Gain: '<S51>/Multiply'
   */
  rtb_MultiportSwitch_idx_1 = (int16_T)rtb_Gain1 + (int16_T)
    rtb_MultiportSwitch_idx_0;
  if (rtb_MultiportSwitch_idx_1 > 32767) {
    rtb_MultiportSwitch_idx_1 = 32767;
  } else {
    if (rtb_MultiportSwitch_idx_1 < -32768) {
      rtb_MultiportSwitch_idx_1 = -32768;
    }
  }

  /* Sum: '<S45>/Add1' incorporates:
   *  Sum: '<S45>/Add'
   */
  rtb_Divide = -rtb_MultiportSwitch_idx_1;
  if (-rtb_MultiportSwitch_idx_1 > 32767) {
    rtb_Divide = 32767;
  }

  /* Sum: '<S53>/Add3' incorporates:
   *  Gain: '<S51>/Multiply'
   *  Sum: '<S45>/Add1'
   */
  rtb_MultiportSwitch_idx_1 = (int16_T)rtb_MultiportSwitch_idx_0 + (int16_T)
    rtb_Divide;
  if (rtb_MultiportSwitch_idx_1 > 32767) {
    rtb_MultiportSwitch_idx_1 = 32767;
  } else {
    if (rtb_MultiportSwitch_idx_1 < -32768) {
      rtb_MultiportSwitch_idx_1 = -32768;
    }
  }

  /* Sum: '<S53>/Add' incorporates:
   *  Gain: '<S51>/Multiply'
   *  Sum: '<S53>/Add3'
   */
  rtb_Gain1 = (((int16_T)rtb_Gain1 << 1) - rtb_MultiportSwitch_idx_1) >> 1;
  if (rtb_Gain1 > 32767) {
    rtb_Gain1 = 32767;
  } else {
    if (rtb_Gain1 < -32768) {
      rtb_Gain1 = -32768;
    }
  }

  /* Gain: '<S53>/Gain1' incorporates:
   *  Product: '<S55>/Divide1'
   *  Sum: '<S53>/Add'
   */
  rtb_Divide1_fi = (int16_T)((21845 * rtb_Gain1) >> 15);

  /* Gain: '<S53>/Gain2' incorporates:
   *  Gain: '<S51>/Multiply'
   *  Sum: '<S45>/Add1'
   *  Sum: '<S53>/Add2'
   */
  rtb_Gain1 = ((((int16_T)rtb_MultiportSwitch_idx_0 - (int16_T)rtb_Divide) >> 1)
               * 18919) >> 14;
  if (rtb_Gain1 > 32767) {
    rtb_Gain1 = 32767;
  } else {
    if (rtb_Gain1 < -32768) {
      rtb_Gain1 = -32768;
    }
  }

  /* PreLookup: '<S56>/a_elecAngle_XA' incorporates:
   *  Switch: '<S2>/Switch'
   */
  rtb_LogicalOperator3 = plook_u16s16_evencka(rtb_Switch_b, 0, 4U, 1440U);

  /* Interpolation_n-D: '<S56>/r_cos_M1' */
  rtb_Sign = rtConstP.r_cos_M1_Table[rtb_LogicalOperator3];

  /* Interpolation_n-D: '<S56>/r_sin_M1' incorporates:
   *  Product: '<S67>/Divide4'
   */
  rtb_Abs5_h = rtConstP.r_sin_M1_Table[rtb_LogicalOperator3];

  /* Sum: '<S55>/Sum1' incorporates:
   *  Gain: '<S53>/Gain2'
   *  Interpolation_n-D: '<S56>/r_cos_M1'
   *  Interpolation_n-D: '<S56>/r_sin_M1'
   *  Product: '<S55>/Divide1'
   *  Product: '<S55>/Divide2'
   *  Product: '<S55>/Divide3'
   */
  rtb_MultiportSwitch_idx_0 = (int16_T)((rtb_Divide1_fi *
    rtConstP.r_cos_M1_Table[rtb_LogicalOperator3]) >> 14) + (int16_T)(((int16_T)
    rtb_Gain1 * rtConstP.r_sin_M1_Table[rtb_LogicalOperator3]) >> 14);
  if (rtb_MultiportSwitch_idx_0 > 32767) {
    rtb_MultiportSwitch_idx_0 = 32767;
  } else {
    if (rtb_MultiportSwitch_idx_0 < -32768) {
      rtb_MultiportSwitch_idx_0 = -32768;
    }
  }

  /* SignalConversion generated from: '<S45>/Low_Pass_Filter' incorporates:
   *  Sum: '<S55>/Sum1'
   */
  rtb_TmpSignalConversionAtLow_Pa[0] = (int16_T)rtb_MultiportSwitch_idx_0;

  /* Sum: '<S55>/Sum6' incorporates:
   *  Gain: '<S53>/Gain2'
   *  Interpolation_n-D: '<S56>/r_cos_M1'
   *  Interpolation_n-D: '<S56>/r_sin_M1'
   *  Product: '<S55>/Divide1'
   *  Product: '<S55>/Divide4'
   */
  rtb_Gain1 = (int16_T)(((int16_T)rtb_Gain1 *
    rtConstP.r_cos_M1_Table[rtb_LogicalOperator3]) >> 14) - (int16_T)
    ((rtb_Divide1_fi * rtConstP.r_sin_M1_Table[rtb_LogicalOperator3]) >> 14);
  if (rtb_Gain1 > 32767) {
    rtb_Gain1 = 32767;
  } else {
    if (rtb_Gain1 < -32768) {
      rtb_Gain1 = -32768;
    }
  }

  /* SignalConversion generated from: '<S45>/Low_Pass_Filter' incorporates:
   *  Sum: '<S55>/Sum6'
   */
  rtb_TmpSignalConversionAtLow_Pa[1] = (int16_T)rtb_Gain1;

  /* Outputs for Atomic SubSystem: '<S45>/Low_Pass_Filter' */
  /* Constant: '<S45>/Constant' */
  Low_Pass_Filter(rtb_TmpSignalConversionAtLow_Pa, 26214, rtb_DataTypeConversion,
                  &rtDW->Low_Pass_Filter_d);

  /* End of Outputs for SubSystem: '<S45>/Low_Pass_Filter' */

  /* Outport: '<Root>/VdPrev' incorporates:
   *  UnitDelay: '<S5>/UnitDelay1'
   */
  rtY->VdPrev = rtDW->UnitDelay1_DSTATE;

  /* Abs: '<S46>/Abs5' incorporates:
   *  UnitDelay: '<S5>/UnitDelay1'
   */
  if (rtDW->UnitDelay1_DSTATE < 0) {
    rtb_Divide1_fi = (int16_T)-rtDW->UnitDelay1_DSTATE;
  } else {
    rtb_Divide1_fi = rtDW->UnitDelay1_DSTATE;
  }

  /* End of Abs: '<S46>/Abs5' */

  /* PreLookup: '<S46>/Vq_max_XA' */
  rtb_LogicalOperator3 = plook_u16s16_evencka(rtb_Divide1_fi, 0, 64U, 45U);

  /* Interpolation_n-D: '<S46>/iq_maxSca_M1' incorporates:
   *  Inport: '<Root>/i_dc_limit'
   *  Product: '<S24>/Divide3'
   *  Product: '<S46>/Divide4'
   */
  rtb_Gain1 = rtDW->Divide3 << 16;
  rtb_Gain1 = (rtb_Gain1 == MIN_int32_T) && (rtU->i_dc_limit == -1) ?
    MAX_int32_T : rtb_Gain1 / rtU->i_dc_limit;
  if (rtb_Gain1 < 0) {
    rtb_Gain1 = 0;
  } else {
    if (rtb_Gain1 > 65535) {
      rtb_Gain1 = 65535;
    }
  }

  /* Product: '<S46>/Divide1' incorporates:
   *  Inport: '<Root>/i_dc_limit'
   *  Interpolation_n-D: '<S46>/iq_maxSca_M1'
   *  PreLookup: '<S46>/iq_maxSca_XA'
   *  Product: '<S46>/Divide4'
   */
  rtb_Divide1_fi = (int16_T)((rtConstP.iq_maxSca_M1_Table[plook_u8u16_evencka
    ((uint16_T)rtb_Gain1, 0U, 1311U, 49U)] * rtU->i_dc_limit) >> 16);

  /* Switch: '<S52>/Switch2' */
  rtb_Switch2_fu = (uint8_T)(rtb_z_ctrlMod != 0);

  /* Delay: '<S84>/Delay' */
  rtb_RelationalOperator4_f = rtDW->Delay_DSTATE_n[0];

  /* DataTypeConversion: '<S52>/Data Type Conversion1' incorporates:
   *  Delay: '<S84>/Delay'
   *  Logic: '<S52>/Logical Operator'
   *  Logic: '<S84>/Logical Operator'
   *  UnitDelay: '<S84>/Unit Delay'
   */
  rtb_DataTypeConversion1_c = (uint8_T)((rtb_Switch2_fu != 0) && ((boolean_T)
    (rtDW->UnitDelay_DSTATE_f ^ rtDW->Delay_DSTATE_n[0])));

  /* If: '<S50>/If' incorporates:
   *  Constant: '<S77>/Constant1'
   *  Constant: '<S77>/Constant11'
   *  Constant: '<S77>/Constant2'
   *  Constant: '<S77>/Constant4'
   *  Gain: '<S46>/Gain1'
   *  Product: '<S46>/Divide1'
   *  Sum: '<S77>/Add2'
   *  Switch: '<S10>/Switch2'
   *  Switch: '<S82>/Switch2'
   */
  if ((rtb_DataTypeConversion1_c > 0) && (rtb_z_ctrlMod == 1)) {
    /* Outputs for IfAction SubSystem: '<S50>/speed_mode' incorporates:
     *  ActionPort: '<S77>/Action Port'
     */
    /* Switch: '<S79>/Switch2' incorporates:
     *  Inport: '<Root>/speed_limit'
     *  RelationalOperator: '<S79>/LowerRelop1'
     *  RelationalOperator: '<S79>/UpperRelop'
     *  Switch: '<S22>/Switch'
     *  Switch: '<S79>/Switch'
     *  Switch: '<S82>/Switch2'
     */
    if (rtb_Switch_oi > rtU->speed_limit) {
      rtb_Switch_oi = rtU->speed_limit;
    } else {
      if (rtb_Switch_oi < 0) {
        /* Switch: '<S79>/Switch' incorporates:
         *  Constant: '<S77>/Constant5'
         *  Switch: '<S82>/Switch2'
         */
        rtb_Switch_oi = 0;
      }
    }

    /* End of Switch: '<S79>/Switch2' */

    /* Outputs for Atomic SubSystem: '<S77>/pi_speed' */
    rtb_Switch_oi = pi_speed((int16_T)(rtb_Switch_oi - rtb_Switch2_ip), 3174, 10,
      20, rtb_Divide1_fi, (int16_T)-rtb_Divide1_fi, 0, rtb_Switch2_fu,
      &rtConstB.pi_speed_g, &rtDW->pi_speed_g, &rtPrevZCX->pi_speed_g);

    /* End of Outputs for SubSystem: '<S77>/pi_speed' */

    /* Merge: '<S50>/Merge' incorporates:
     *  Constant: '<S77>/Constant1'
     *  Constant: '<S77>/Constant11'
     *  Constant: '<S77>/Constant2'
     *  Constant: '<S77>/Constant4'
     *  Gain: '<S46>/Gain1'
     *  Product: '<S46>/Divide1'
     *  SignalConversion generated from: '<S77>/iq_target'
     *  Sum: '<S77>/Add2'
     *  Switch: '<S10>/Switch2'
     *  Switch: '<S82>/Switch2'
     */
    rtDW->Merge_b = rtb_Switch_oi;

    /* End of Outputs for SubSystem: '<S50>/speed_mode' */
  } else {
    if ((rtb_DataTypeConversion1_c > 0) && (rtb_z_ctrlMod == 2)) {
      /* Outputs for IfAction SubSystem: '<S50>/torque_mode' incorporates:
       *  ActionPort: '<S78>/Action Port'
       */
      /* Product: '<S78>/Divide' incorporates:
       *  Constant: '<S78>/Constant2'
       *  Sum: '<S78>/Sum2'
       *  Switch: '<S10>/Switch2'
       *  Switch: '<S22>/Switch'
       */
      rtb_Gain1 = ((int16_T)(rtb_Switch_oi - rtb_Switch2_ip) * 819) >> 6;
      if (rtb_Gain1 > 32767) {
        rtb_Gain1 = 32767;
      } else {
        if (rtb_Gain1 < -32768) {
          rtb_Gain1 = -32768;
        }
      }

      /* Product: '<S78>/Divide1' incorporates:
       *  Sum: '<S78>/Sum3'
       *  Switch: '<S10>/Switch2'
       *  Switch: '<S22>/Switch'
       */
      rtb_MultiportSwitch_idx_0 = ((int16_T)(rtb_Switch2_ip - rtb_Switch_oi) *
        -51) >> 5;
      if (rtb_MultiportSwitch_idx_0 > 32767) {
        rtb_MultiportSwitch_idx_0 = 32767;
      } else {
        if (rtb_MultiportSwitch_idx_0 < -32768) {
          rtb_MultiportSwitch_idx_0 = -32768;
        }
      }

      rtb_Switch_oi = (int16_T)rtb_MultiportSwitch_idx_0;

      /* End of Product: '<S78>/Divide1' */

      /* MinMax: '<S78>/Max' incorporates:
       *  Product: '<S78>/Divide'
       *  Product: '<S78>/Divide1'
       */
      if ((int16_T)rtb_Gain1 > rtb_Switch_oi) {
        rtb_Max = (int16_T)rtb_Gain1;
      } else {
        rtb_Max = rtb_Switch_oi;
      }

      /* End of MinMax: '<S78>/Max' */

      /* MinMax: '<S78>/Max3' incorporates:
       *  MinMax: '<S78>/Max'
       *  Product: '<S46>/Divide1'
       *  Switch: '<S83>/Switch2'
       */
      if (rtb_Divide1_fi < rtb_Max) {
        rtb_Max = rtb_Divide1_fi;
      }

      /* End of MinMax: '<S78>/Max3' */

      /* Switch: '<S83>/Switch2' incorporates:
       *  Product: '<S29>/Divide1'
       *  RelationalOperator: '<S83>/LowerRelop1'
       */
      if (rtDW->Divide1 <= rtb_Max) {
        /* MinMax: '<S78>/Max1' incorporates:
         *  Product: '<S78>/Divide'
         *  Product: '<S78>/Divide1'
         */
        if ((int16_T)rtb_Gain1 < rtb_Switch_oi) {
          rtb_Switch_oi = (int16_T)rtb_Gain1;
        }

        /* End of MinMax: '<S78>/Max1' */

        /* MinMax: '<S78>/Max2' incorporates:
         *  Gain: '<S46>/Gain1'
         *  MinMax: '<S78>/Max1'
         *  Product: '<S46>/Divide1'
         */
        if (rtb_Switch_oi <= (int16_T)-rtb_Divide1_fi) {
          rtb_Switch_oi = (int16_T)-rtb_Divide1_fi;
        }

        /* End of MinMax: '<S78>/Max2' */

        /* Switch: '<S83>/Switch' incorporates:
         *  MinMax: '<S78>/Max2'
         *  RelationalOperator: '<S83>/UpperRelop'
         */
        if (rtDW->Divide1 < rtb_Switch_oi) {
          rtb_Max = rtb_Switch_oi;
        } else {
          rtb_Max = rtDW->Divide1;
        }

        /* End of Switch: '<S83>/Switch' */
      }

      /* End of Switch: '<S83>/Switch2' */

      /* Merge: '<S50>/Merge' incorporates:
       *  SignalConversion generated from: '<S78>/torque_iq'
       *  Switch: '<S83>/Switch2'
       */
      rtDW->Merge_b = rtb_Max;

      /* End of Outputs for SubSystem: '<S50>/torque_mode' */
    }
  }

  /* End of If: '<S50>/If' */

  /* If: '<S47>/If' incorporates:
   *  Constant: '<S47>/Constant3'
   *  Constant: '<S57>/Constant3'
   *  Constant: '<S57>/Constant4'
   *  Constant: '<S57>/Constant6'
   *  Constant: '<S57>/Constant9'
   *  Constant: '<S58>/Constant1'
   *  Constant: '<S58>/Constant7'
   *  Constant: '<S58>/Constant8'
   *  Gain: '<S46>/Gain3'
   *  Gain: '<S46>/Gain5'
   *  If: '<S47>/If1'
   *  Inport: '<Root>/vbus_voltage'
   *  Interpolation_n-D: '<S46>/Vq_max_M1'
   *  Sum: '<S57>/Add'
   *  Sum: '<S58>/Add1'
   *  Switch: '<S60>/Switch2'
   *  Switch: '<S64>/Switch2'
   */
  if (rtb_Switch2_fu == 1) {
    /* Outputs for IfAction SubSystem: '<S47>/iq_ctrl' incorporates:
     *  ActionPort: '<S58>/Action Port'
     */
    /* Switch: '<S64>/Switch2' incorporates:
     *  Merge: '<S50>/Merge'
     *  Product: '<S46>/Divide1'
     *  RelationalOperator: '<S64>/LowerRelop1'
     */
    if (rtDW->Merge_b <= rtb_Divide1_fi) {
      /* Switch: '<S64>/Switch' incorporates:
       *  Gain: '<S46>/Gain1'
       *  RelationalOperator: '<S64>/UpperRelop'
       *  Switch: '<S64>/Switch2'
       */
      if (rtDW->Merge_b < (int16_T)-rtb_Divide1_fi) {
        rtb_Divide1_fi = (int16_T)-rtb_Divide1_fi;
      } else {
        rtb_Divide1_fi = rtDW->Merge_b;
      }

      /* End of Switch: '<S64>/Switch' */
    }

    /* End of Switch: '<S64>/Switch2' */

    /* Outputs for Atomic SubSystem: '<S58>/PI_iq' */
    PI_iq((int16_T)(rtb_Divide1_fi - rtb_DataTypeConversion[1]), 4096, 51, 1024,
          rtConstP.Vq_max_M1_Table[rtb_LogicalOperator3], (int16_T)
          -rtConstP.Vq_max_M1_Table[rtb_LogicalOperator3], 0, &rtDW->Switch2_m,
          &rtDW->PI_iq_g);

    /* End of Outputs for SubSystem: '<S58>/PI_iq' */
    /* End of Outputs for SubSystem: '<S47>/iq_ctrl' */

    /* Outputs for IfAction SubSystem: '<S47>/id_ctrl' incorporates:
     *  ActionPort: '<S57>/Action Port'
     */
    /* Switch: '<S60>/Switch2' incorporates:
     *  Constant: '<S47>/Constant3'
     *  Constant: '<S58>/Constant1'
     *  Constant: '<S58>/Constant7'
     *  Constant: '<S58>/Constant8'
     *  Gain: '<S46>/Gain4'
     *  Gain: '<S46>/Gain5'
     *  Inport: '<Root>/i_dc_limit'
     *  Interpolation_n-D: '<S46>/Vq_max_M1'
     *  Product: '<S24>/Divide3'
     *  RelationalOperator: '<S60>/LowerRelop1'
     *  RelationalOperator: '<S60>/UpperRelop'
     *  Sum: '<S58>/Add1'
     *  Switch: '<S60>/Switch'
     *  Switch: '<S64>/Switch2'
     */
    if (rtDW->Divide3 > rtU->i_dc_limit) {
      rtb_Switch_oi = rtU->i_dc_limit;
    } else if (rtDW->Divide3 < (int16_T)-rtU->i_dc_limit) {
      /* Switch: '<S60>/Switch' incorporates:
       *  Gain: '<S46>/Gain4'
       *  Switch: '<S60>/Switch2'
       */
      rtb_Switch_oi = (int16_T)-rtU->i_dc_limit;
    } else {
      rtb_Switch_oi = rtDW->Divide3;
    }

    /* End of Switch: '<S60>/Switch2' */

    /* Outputs for Atomic SubSystem: '<S57>/PI_id' */
    PI_id((int16_T)(rtb_Switch_oi - rtb_DataTypeConversion[0]), 4096, 51, 1024,
          rtU->vbus_voltage, (int16_T)-rtU->vbus_voltage, 0, &rtDW->Switch2,
          &rtDW->PI_id_b);

    /* End of Outputs for SubSystem: '<S57>/PI_id' */
    /* End of Outputs for SubSystem: '<S47>/id_ctrl' */
  }

  /* End of If: '<S47>/If' */

  /* Switch: '<S5>/Switch1' incorporates:
   *  Switch: '<S5>/Switch'
   *  Switch: '<S62>/Switch2'
   *  Switch: '<S66>/Switch2'
   */
  if (rtb_z_ctrlMod != 0) {
    rtb_Switch_oi = rtDW->Switch2_m;
    rtb_Divide1_fi = rtDW->Switch2;
  } else {
    rtb_Switch_oi = rtDW->Merge[1];
    rtb_Divide1_fi = rtDW->Merge[0];
  }

  /* End of Switch: '<S5>/Switch1' */

  /* Sum: '<S48>/Sum1' incorporates:
   *  Interpolation_n-D: '<S56>/r_cos_M1'
   *  Product: '<S48>/Divide2'
   *  Product: '<S48>/Divide3'
   *  Product: '<S67>/Divide4'
   *  Switch: '<S5>/Switch'
   *  Switch: '<S5>/Switch1'
   */
  rtb_Gain1 = (int16_T)((rtb_Divide1_fi * rtb_Abs5_h) >> 14) + (int16_T)
    ((rtb_Switch_oi * rtb_Sign) >> 14);
  if (rtb_Gain1 > 32767) {
    rtb_Gain1 = 32767;
  } else {
    if (rtb_Gain1 < -32768) {
      rtb_Gain1 = -32768;
    }
  }

  /* Sum: '<S48>/Sum6' incorporates:
   *  Interpolation_n-D: '<S56>/r_cos_M1'
   *  Product: '<S48>/Divide1'
   *  Product: '<S48>/Divide4'
   *  Product: '<S67>/Divide4'
   *  Switch: '<S5>/Switch'
   *  Switch: '<S5>/Switch1'
   */
  rtb_MultiportSwitch_idx_0 = (int16_T)((rtb_Divide1_fi * rtb_Sign) >> 14) -
    (int16_T)((rtb_Switch_oi * rtb_Abs5_h) >> 14);
  if (rtb_MultiportSwitch_idx_0 > 32767) {
    rtb_MultiportSwitch_idx_0 = 32767;
  } else {
    if (rtb_MultiportSwitch_idx_0 < -32768) {
      rtb_MultiportSwitch_idx_0 = -32768;
    }
  }

  /* Product: '<S67>/Divide3' incorporates:
   *  Constant: '<S67>/Constant1'
   *  Product: '<S67>/Divide'
   *  Sum: '<S48>/Sum6'
   */
  rtb_Sign = (int16_T)((3547 * (int16_T)rtb_MultiportSwitch_idx_0) >> 12);

  /* Product: '<S67>/Divide2' incorporates:
   *  Constant: '<S67>/Constant'
   *  Sum: '<S48>/Sum1'
   */
  rtb_Max = (int16_T)((3547 * (int16_T)rtb_Gain1) >> 12);

  /* Product: '<S67>/Divide4' incorporates:
   *  Constant: '<S67>/Constant2'
   *  Product: '<S67>/Divide2'
   */
  rtb_Abs5_h = (int16_T)((2365 * rtb_Max) >> 12);

  /* Sum: '<S67>/Add' incorporates:
   *  Product: '<S67>/Divide'
   *  Product: '<S67>/Divide4'
   */
  rtb_Gain4 = (int16_T)((rtb_Sign + rtb_Abs5_h) >> 1);

  /* Sum: '<S67>/Add1' incorporates:
   *  Product: '<S67>/Divide'
   *  Product: '<S67>/Divide4'
   */
  rtb_Abs5_h = (int16_T)((rtb_Abs5_h - rtb_Sign) >> 1);

  /* Product: '<S67>/Divide7' incorporates:
   *  Constant: '<S67>/Constant3'
   *  Sum: '<S48>/Sum1'
   */
  rtb_Sign = (int16_T)((2365 * (int16_T)rtb_Gain1) >> 12);

  /* MATLAB Function: '<S67>/sector_select' incorporates:
   *  Product: '<S67>/Divide7'
   *  Sum: '<S48>/Sum1'
   *  Sum: '<S48>/Sum6'
   */
  if ((int16_T)rtb_Gain1 >= 0) {
    if ((int16_T)rtb_MultiportSwitch_idx_0 >= 0) {
      if (rtb_Sign > (int16_T)rtb_MultiportSwitch_idx_0) {
        /* DataTypeConversion: '<S67>/Data Type Conversion' */
        rtb_DataTypeConversion1_c = 2U;
      } else {
        /* DataTypeConversion: '<S67>/Data Type Conversion' */
        rtb_DataTypeConversion1_c = 1U;
      }
    } else if (-rtb_Sign > (int16_T)rtb_MultiportSwitch_idx_0) {
      /* DataTypeConversion: '<S67>/Data Type Conversion' */
      rtb_DataTypeConversion1_c = 3U;
    } else {
      /* DataTypeConversion: '<S67>/Data Type Conversion' */
      rtb_DataTypeConversion1_c = 2U;
    }
  } else if ((int16_T)rtb_MultiportSwitch_idx_0 >= 0) {
    if (-rtb_Sign > (int16_T)rtb_MultiportSwitch_idx_0) {
      /* DataTypeConversion: '<S67>/Data Type Conversion' */
      rtb_DataTypeConversion1_c = 5U;
    } else {
      /* DataTypeConversion: '<S67>/Data Type Conversion' */
      rtb_DataTypeConversion1_c = 6U;
    }
  } else if (rtb_Sign > (int16_T)rtb_MultiportSwitch_idx_0) {
    /* DataTypeConversion: '<S67>/Data Type Conversion' */
    rtb_DataTypeConversion1_c = 4U;
  } else {
    /* DataTypeConversion: '<S67>/Data Type Conversion' */
    rtb_DataTypeConversion1_c = 5U;
  }

  /* End of MATLAB Function: '<S67>/sector_select' */

  /* Product: '<S67>/Divide' incorporates:
   *  Inport: '<Root>/vbus_voltage'
   */
  rtb_Sign = (int16_T)(24576000 / rtU->vbus_voltage);

  /* Product: '<S67>/Divide1' incorporates:
   *  Product: '<S67>/Divide'
   *  Product: '<S67>/Divide2'
   *  Product: '<S67>/Divide8'
   */
  rtb_Max = (int16_T)((((2365 * rtb_Max) >> 13) * rtb_Sign) >> 10);

  /* Product: '<S67>/Divide5' incorporates:
   *  Product: '<S67>/Divide'
   *  Sum: '<S67>/Add'
   */
  rtb_Gain4 = (int16_T)((rtb_Gain4 * rtb_Sign) >> 11);

  /* Product: '<S67>/Divide6' incorporates:
   *  Product: '<S67>/Divide'
   *  Sum: '<S67>/Add1'
   */
  rtb_Abs5_h = (int16_T)((rtb_Abs5_h * rtb_Sign) >> 11);

  /* MultiPortSwitch: '<S69>/Multiport Switch' incorporates:
   *  DataTypeConversion: '<S67>/Data Type Conversion1'
   *  Gain: '<S71>/Gain'
   *  Gain: '<S74>/Gain'
   *  Gain: '<S75>/Gain1'
   *  Product: '<S71>/Divide2'
   *  Product: '<S72>/Divide2'
   *  Product: '<S73>/Divide2'
   *  Product: '<S74>/Divide2'
   *  Product: '<S75>/Divide2'
   *  Product: '<S76>/Divide2'
   *  Sum: '<S71>/Add3'
   *  Sum: '<S72>/Add3'
   *  Sum: '<S73>/Add3'
   *  Sum: '<S74>/Add3'
   *  Sum: '<S75>/Add3'
   *  Sum: '<S76>/Add3'
   */
  switch (rtb_DataTypeConversion1_c) {
   case 1:
    /* Product: '<S71>/Divide' incorporates:
     *  Gain: '<S71>/Gain'
     *  Sum: '<S71>/Add'
     *  Sum: '<S71>/Add1'
     */
    rtb_Gain1 = (6000 - (rtb_Max - rtb_Abs5_h)) >> 2;

    /* Sum: '<S71>/Add2' incorporates:
     *  Product: '<S71>/Divide1'
     */
    rtb_Divide = (rtb_Max >> 1) + rtb_Gain1;
    rtb_MultiportSwitch_idx_0 = (-rtb_Abs5_h >> 1) + rtb_Divide;
    rtb_MultiportSwitch_idx_1 = rtb_Divide;
    break;

   case 2:
    /* Product: '<S72>/Divide' incorporates:
     *  Sum: '<S72>/Add'
     *  Sum: '<S72>/Add1'
     */
    rtb_Sign = (int16_T)((int16_T)(6000 - (int16_T)(rtb_Abs5_h + rtb_Gain4)) >>
                         2);

    /* Sum: '<S72>/Add2' incorporates:
     *  Product: '<S72>/Divide1'
     */
    rtb_Max = (int16_T)((rtb_Gain4 >> 1) + rtb_Sign);
    rtb_MultiportSwitch_idx_0 = rtb_Max;
    rtb_MultiportSwitch_idx_1 = (int16_T)((rtb_Abs5_h >> 1) + rtb_Max);
    rtb_Gain1 = rtb_Sign;
    break;

   case 3:
    /* Product: '<S73>/Divide' incorporates:
     *  Gain: '<S73>/Gain'
     *  Sum: '<S73>/Add'
     *  Sum: '<S73>/Add1'
     */
    rtb_Divide = (6000 - (rtb_Max - rtb_Gain4)) >> 2;

    /* Sum: '<S73>/Add2' incorporates:
     *  Gain: '<S73>/Gain'
     *  Product: '<S73>/Divide1'
     */
    rtb_Gain1 = (-rtb_Gain4 >> 1) + rtb_Divide;
    rtb_MultiportSwitch_idx_0 = rtb_Divide;
    rtb_MultiportSwitch_idx_1 = (rtb_Max >> 1) + rtb_Gain1;
    break;

   case 4:
    /* Product: '<S74>/Divide' incorporates:
     *  Gain: '<S74>/Gain'
     *  Sum: '<S74>/Add'
     *  Sum: '<S74>/Add1'
     */
    rtb_Gain1 = (6000 - (rtb_Abs5_h - rtb_Max)) >> 2;

    /* Sum: '<S74>/Add2' incorporates:
     *  Product: '<S74>/Divide1'
     */
    rtb_Divide = (rtb_Abs5_h >> 1) + rtb_Gain1;
    rtb_MultiportSwitch_idx_0 = rtb_Gain1;
    rtb_MultiportSwitch_idx_1 = rtb_Divide;
    rtb_Gain1 = (-rtb_Max >> 1) + rtb_Divide;
    break;

   case 5:
    /* Product: '<S75>/Divide' incorporates:
     *  Gain: '<S75>/Gain'
     *  Gain: '<S75>/Gain1'
     *  Sum: '<S75>/Add1'
     */
    rtb_Gain1 = (6000 - (-rtb_Abs5_h - rtb_Gain4)) >> 2;

    /* Sum: '<S75>/Add2' incorporates:
     *  Gain: '<S75>/Gain'
     *  Product: '<S75>/Divide1'
     */
    rtb_Divide = (-rtb_Abs5_h >> 1) + rtb_Gain1;
    rtb_MultiportSwitch_idx_0 = rtb_Divide;
    rtb_MultiportSwitch_idx_1 = rtb_Gain1;
    rtb_Gain1 = (-rtb_Gain4 >> 1) + rtb_Divide;
    break;

   default:
    /* Product: '<S76>/Divide' incorporates:
     *  Gain: '<S76>/Gain1'
     *  Sum: '<S76>/Add'
     *  Sum: '<S76>/Add1'
     */
    rtb_Divide = (6000 - (rtb_Gain4 - rtb_Max)) >> 2;

    /* Sum: '<S76>/Add2' incorporates:
     *  Gain: '<S76>/Gain1'
     *  Product: '<S76>/Divide1'
     */
    rtb_Gain1 = (-rtb_Max >> 1) + rtb_Divide;
    rtb_MultiportSwitch_idx_0 = (rtb_Gain4 >> 1) + rtb_Gain1;
    rtb_MultiportSwitch_idx_1 = rtb_Divide;
    break;
  }

  /* End of MultiPortSwitch: '<S69>/Multiport Switch' */

  /* Update for Delay: '<S7>/Delay' incorporates:
   *  Inport: '<Root>/hall_a'
   */
  rtDW->Delay_DSTATE = rtU->hall_a;

  /* Update for Delay: '<S7>/Delay1' incorporates:
   *  Inport: '<Root>/hall_b'
   */
  rtDW->Delay1_DSTATE = rtU->hall_b;

  /* Update for Delay: '<S7>/Delay2' incorporates:
   *  Inport: '<Root>/hall_c'
   */
  rtDW->Delay2_DSTATE = rtU->hall_c;

  /* Update for UnitDelay: '<S10>/UnitDelay3' incorporates:
   *  Inport: '<Root>/hw_count'
   */
  rtDW->UnitDelay3_DSTATE = rtU->hw_count;

  /* Update for UnitDelay: '<S10>/UnitDelay4' incorporates:
   *  Abs: '<S10>/Abs5'
   */
  rtDW->UnitDelay4_DSTATE = rtb_Abs5;

  /* Update for UnitDelay: '<S34>/UnitDelay' */
  rtDW->UnitDelay_DSTATE_j = rtb_UnitDelay;

  /* Update for UnitDelay: '<S5>/UnitDelay2' incorporates:
   *  Switch: '<S5>/Switch1'
   */
  rtDW->UnitDelay2_DSTATE_p = rtb_Switch_oi;

  /* Update for UnitDelay: '<S5>/UnitDelay1' incorporates:
   *  Switch: '<S5>/Switch'
   */
  rtDW->UnitDelay1_DSTATE = rtb_Divide1_fi;

  /* Update for UnitDelay: '<S84>/Unit Delay' incorporates:
   *  Delay: '<S84>/Delay'
   */
  rtDW->UnitDelay_DSTATE_f = rtDW->Delay_DSTATE_n[0];

  /* Update for Delay: '<S84>/Delay' incorporates:
   *  Logic: '<S84>/Logical Operator1'
   */
  for (rtb_Divide = 0; rtb_Divide < 19; rtb_Divide++) {
    rtDW->Delay_DSTATE_n[rtb_Divide] = rtDW->Delay_DSTATE_n[rtb_Divide + 1];
  }

  rtDW->Delay_DSTATE_n[19] = !rtb_RelationalOperator4_f;

  /* End of Update for Delay: '<S84>/Delay' */

  /* Switch: '<S68>/Switch2' incorporates:
   *  RelationalOperator: '<S68>/LowerRelop1'
   *  RelationalOperator: '<S68>/UpperRelop'
   *  Switch: '<S68>/Switch'
   */
  if (rtb_MultiportSwitch_idx_0 > 3000) {
    /* Outport: '<Root>/PWM' incorporates:
     *  Constant: '<S67>/Constant6'
     */
    rtY->PWM[0] = 3000U;
  } else if (rtb_MultiportSwitch_idx_0 < 0) {
    /* Switch: '<S68>/Switch' incorporates:
     *  Constant: '<S67>/Constant5'
     *  Outport: '<Root>/PWM'
     */
    rtY->PWM[0] = 0U;
  } else {
    /* Outport: '<Root>/PWM' */
    rtY->PWM[0] = (uint16_T)rtb_MultiportSwitch_idx_0;
  }

  if (rtb_MultiportSwitch_idx_1 > 3000) {
    /* Outport: '<Root>/PWM' incorporates:
     *  Constant: '<S67>/Constant6'
     */
    rtY->PWM[1] = 3000U;
  } else if (rtb_MultiportSwitch_idx_1 < 0) {
    /* Switch: '<S68>/Switch' incorporates:
     *  Constant: '<S67>/Constant5'
     *  Outport: '<Root>/PWM'
     */
    rtY->PWM[1] = 0U;
  } else {
    /* Outport: '<Root>/PWM' */
    rtY->PWM[1] = (uint16_T)rtb_MultiportSwitch_idx_1;
  }

  if (rtb_Gain1 > 3000) {
    /* Outport: '<Root>/PWM' incorporates:
     *  Constant: '<S67>/Constant6'
     */
    rtY->PWM[2] = 3000U;
  } else if (rtb_Gain1 < 0) {
    /* Switch: '<S68>/Switch' incorporates:
     *  Constant: '<S67>/Constant5'
     *  Outport: '<Root>/PWM'
     */
    rtY->PWM[2] = 0U;
  } else {
    /* Outport: '<Root>/PWM' */
    rtY->PWM[2] = (uint16_T)rtb_Gain1;
  }

  /* End of Switch: '<S68>/Switch2' */
  /* End of Outputs for SubSystem: '<Root>/PMSM_Controller' */

  /* Outport: '<Root>/sector' */
  rtY->sector = rtb_DataTypeConversion1_c;

  /* Outport: '<Root>/n_MotError' */
  rtY->n_MotError = rtb_UnitDelay;

  /* Outport: '<Root>/iq' */
  rtY->iq = rtb_DataTypeConversion[1];

  /* Outport: '<Root>/id' */
  rtY->id = rtb_DataTypeConversion[0];

  /* Outport: '<Root>/angle' incorporates:
   *  Switch: '<S2>/Switch'
   */
  rtY->angle = rtb_Switch_b;

  /* Outport: '<Root>/rpm' incorporates:
   *  Switch: '<S10>/Switch2'
   */
  rtY->rpm = rtb_Switch2_ip;

  /* Outport: '<Root>/hall_angle' incorporates:
   *  Merge: '<S11>/Merge'
   */
  rtY->hall_angle = rtb_Switch3_c;

  /* Outport: '<Root>/hall_state' */
  rtY->hall_state = rtb_Add_cr;

  /* Outport: '<Root>/running_mode' */
  rtY->running_mode = rtb_z_ctrlMod;
}

/* Model initialize function */
void PMSM_Controller_initialize(RT_MODEL *const rtM)
{
  DW *rtDW = rtM->dwork;
  PrevZCX *rtPrevZCX = rtM->prevZCSigState;

  {
    int32_T i;
    rtPrevZCX->pi_speed_g.ResettableDelay_Reset_ZCE = POS_ZCSIG;

    /* SystemInitialize for Atomic SubSystem: '<Root>/PMSM_Controller' */
    /* InitializeConditions for Delay: '<S84>/Delay' */
    for (i = 0; i < 20; i++) {
      rtDW->Delay_DSTATE_n[i] = true;
    }

    /* End of InitializeConditions for Delay: '<S84>/Delay' */

    /* SystemInitialize for IfAction SubSystem: '<S10>/Raw_Motor_Speed_Estimation' */
    /* SystemInitialize for Outport: '<S15>/z_counter' incorporates:
     *  Inport: '<S15>/z_counterRawPrev'
     */
    rtDW->z_counterRawPrev = 200000U;

    /* End of SystemInitialize for SubSystem: '<S10>/Raw_Motor_Speed_Estimation' */

    /* SystemInitialize for Atomic SubSystem: '<S34>/Debounce_Filter' */
    Debounce_Filter_Init(&rtDW->Debounce_Filter_i);

    /* End of SystemInitialize for SubSystem: '<S34>/Debounce_Filter' */

    /* SystemInitialize for IfAction SubSystem: '<S50>/speed_mode' */
    /* SystemInitialize for Atomic SubSystem: '<S77>/pi_speed' */
    pi_speed_Init(&rtDW->pi_speed_g);

    /* End of SystemInitialize for SubSystem: '<S77>/pi_speed' */
    /* End of SystemInitialize for SubSystem: '<S50>/speed_mode' */
    /* End of SystemInitialize for SubSystem: '<Root>/PMSM_Controller' */
  }
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */