MC100/Applications/bsp/adc.h

#ifndef _ADC_H__
#define _ADC_H__
#include "bsp/bsp.h"
#include "os/os_type.h"

/*
inserted ADC 由timer0 ch3触发，
注意：adc所有外部触发都是下降沿触发 
*/
#define MOTOR_TEMP_CHAN ADC_CHANNEL_0
#define HANDLERBAR_CHAN ADC_CHANNEL_1 //转把信号
#define VBUS_V_CHAN 	ADC_CHANNEL_2
#define W_PHASE_V_CHAN  ADC_CHANNEL_3
#define V_PHASE_V_CHAN  ADC_CHANNEL_4
#define U_PHASE_V_CHAN  ADC_CHANNEL_5
#define W_PHASE_I_CHAN  ADC_CHANNEL_6
#define V_PHASE_I_CHAN  ADC_CHANNEL_7
#define U_PHASE_I_CHAN  ADC_CHANNEL_8
#define VBUS_I_CHAN     ADC_CHANNEL_9
#define ISQ2_OFFSET 10
#define ISO3_OFFSET 15
#define IL_OFFSET   20

#define ADC_SAMPLE_TIME ADC_SAMPLETIME_7POINT5
#define ADC_TRIGGER_PHASE ADC0_1_EXTTRIG_INSERTED_T0_CH3
#define ADC_TRIGGER_NONE  ADC0_1_2_EXTTRIG_INSERTED_NONE
#define ADC_TRIGGER_VBUS ADC0_1_EXTTRIG_INSERTED_T1_CH0

//#define ADC_RANK_CHANNEL(c1, c2, l) ((c1)<<ISQ2_OFFSET | (c2)<<ISO3_OFFSET | (l)<<IL_OFFSET)
#define ADC_RANK_CHANNEL(c)  ((c)<<ISO3_OFFSET | (0)<<IL_OFFSET) 
#define ADC_CALI_RANK_CHANEL(c)  ((c)<<ISO3_OFFSET | (0)<<IL_OFFSET) 
static u32 adc0_rank_channels[6] = {
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),//1, UW, AC
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),//2, VW, BC
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),//3, VU, BA
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),//4, WU, CA
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),//5, WV, CB
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),//6, UV, AB
};
static u32 adc1_rank_channels[6] = {
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN),
};


static u32 volatile * adc_phase_reg1[6] = {
	&ADC_IDATA0(ADC0),//1, U
	&ADC_IDATA0(ADC0),//2, V
	&ADC_IDATA0(ADC0),//3, V
	&ADC_IDATA0(ADC0),//4, U
	&ADC_IDATA0(ADC0),//5, V 
	&ADC_IDATA0(ADC0),//6, V
};
static u32 volatile * adc_phase_reg2[6] = {
	&ADC_IDATA0(ADC1),//1, W
	&ADC_IDATA0(ADC1),//2, W
	&ADC_IDATA0(ADC1),//3, U
	&ADC_IDATA0(ADC1),//4, W
	&ADC_IDATA0(ADC1),//5, W
	&ADC_IDATA0(ADC1),//6, U
};

static void __inline adc_phase_current_read(u8 sector, s32 *v1, s32 *v2) {
	*v1 = (s32)(*adc_phase_reg1[sector]) ;
	*v2 = (s32)(*adc_phase_reg2[sector]) ;
}


static void __inline adc_current_sample_config(u8 sector) {
	ADC_ISQ(ADC0) = adc0_rank_channels[sector];
	ADC_ISQ(ADC1) = adc1_rank_channels[sector];
}


static void __inline adc_disable_ext_trigger(void) {   
	ADC_CTL1(ADC0) &= ~ADC_CTL1_ETEIC;
	//ADC_CTL1(ADC1) &= ~ADC_CTL1_ETEIC;
}

static void __inline adc_enable_ext_trigger(void) {	
	ADC_CTL1(ADC0) |= ADC_CTL1_ETEIC;
	//ADC_CTL1(ADC1) |= ADC_CTL1_ETEIC;
}

static bool __inline adc_is_trigged_vbus(void) {
	if ((ADC_CTL1(ADC1) & ADC_TRIGGER_VBUS) == ADC_TRIGGER_VBUS) {
		return true;
	}
	return false;
}

/* insert len fixed to 2(IL=1), ISQ2 >> ISQ3*/
static __inline__ void adc_update_insert_sample_rank(u32 adc, u8 channel) {
    ADC_ISQ(adc) = ADC_RANK_CHANNEL(channel);
}

static __inline__ void adc_update_insert_sample_time(u32 adc, uint8_t adc_channel , uint32_t sample_time)
{
    uint32_t sampt;
    /* ADC sampling time config */  
    if(adc_channel < 10U){
        sampt = ADC_SAMPT1(adc);
        sampt &= ~((u32)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
        sampt |= (u32) sample_time << (3U*adc_channel);
        ADC_SAMPT1(adc) = sampt;
    }else if(adc_channel < 18U){
        sampt = ADC_SAMPT0(adc);
        sampt &= ~((u32)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
        sampt |= ((u32)sample_time << (3U*(adc_channel-10U)));
        ADC_SAMPT0(adc) = sampt;
    }
}

static __inline__ bool adc_eoic_interrupt(void)
{
#if 0
	if (ADC_STAT(ADC0) & ADC_STAT_EOIC){
		return true;
	}
	if (ADC_STAT(ADC1) & ADC_STAT_EOIC){
		return true;
	}
#else
	if (ADC_STAT(ADC0) & ADC_STAT_EOIC){
		return true;
	}
#endif


	return false;
}

static __inline__ void adc_clear_irq_flags(void) {
	ADC_STAT(ADC0) &= ~((u32) ADC_INT_FLAG_EOIC);
}


void adc_init(void);
s32 adc_sample_regular_channel(int chan, int times);
void adc_start_insert_convert(void);
void adc_stop_insert_convert(void);

#endif /* _ADC_H__ */