pwm.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301
  1. #include "bsp/bsp.h"
  2. #include "bsp/pwm.h"
  3. #include "bsp/adc.h"
  4. #include "os/os_task.h"
  5. #include "libs/logger.h"
  6. /*
  7. 以下主要是在某一相电路无法采集的时候,需要对这相的pwm挖坑处理
  8. timer 分配:
  9. timer0 -> ch0-2 互补pwm
  10. ch4 event, update event 触发DMA(ch3,4)实现CCR的自更新
  11. timer1 -> 触发ADC采样,GD32不支持多channel 或方式触发输出,通过timer1的 ch0 compara 配置 TRGO触发ADC,但是需要在一个PWM周期内触发2次(单电阻)
  12. timer0 master --> timer1 slave/master 确保timer0,1同步开始,同频同相位
  13. DMA 分配:
  14. DMA0 ch4 -> timer0 update event
  15. ch3 -> timer0 chan3 CC event
  16. ch1 -> timer1 update event,需要更新CCR
  17. */
  18. static void _init_pwm_timer(bool);
  19. static void _pwm_gpio_config(void);
  20. #ifndef PWM_BRAKE_GROUP
  21. static void _gpio_brakein_irq_enable(void);
  22. #endif
  23. u16 timer_update_buffer[6] = {0};
  24. static rcu_periph_enum _rcu_clk(u32 timer) {
  25. if (timer == TIMER0) {
  26. return RCU_TIMER0;
  27. }
  28. if (timer == TIMER1) {
  29. return RCU_TIMER1;
  30. }
  31. if (timer == TIMER2) {
  32. return RCU_TIMER2;
  33. }
  34. return RCU_TIMER2;
  35. }
  36. void pwm_3phase_init(void){
  37. _pwm_gpio_config();
  38. _init_pwm_timer(true);
  39. }
  40. void pwm_3phase_sides(bool hon, bool lon) {
  41. if (hon && lon) {
  42. return;
  43. }
  44. timer_deinit(pwm_timer);
  45. rcu_periph_clock_enable(_rcu_clk(pwm_timer));
  46. gpio_init(PWM_U_P_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_U_P_PIN);
  47. gpio_init(PWM_V_P_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_V_P_PIN);
  48. gpio_init(PWM_W_P_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_W_P_PIN);
  49. gpio_init(PWM_U_N_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_U_N_PIN);
  50. gpio_init(PWM_V_N_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_V_N_PIN);
  51. gpio_init(PWM_W_N_GROUP,GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,PWM_W_N_PIN);
  52. sys_debug("pwm_3phase_sides\n");
  53. /* 开上桥或者下桥之前先关闭下桥或者上桥 */
  54. if (hon) {
  55. _pwm_gpio_config();
  56. _init_pwm_timer(false);
  57. delay_us(10);
  58. pwm_start();
  59. pwm_update_duty(FOC_PWM_Half_Period-200, FOC_PWM_Half_Period-200, FOC_PWM_Half_Period-200);
  60. }else if (lon) {
  61. gpio_bit_write(PWM_U_P_GROUP, PWM_U_P_PIN, RESET);
  62. gpio_bit_write(PWM_V_P_GROUP, PWM_V_P_PIN, RESET);
  63. gpio_bit_write(PWM_W_P_GROUP, PWM_W_P_PIN, RESET);
  64. delay_us(10);
  65. gpio_bit_write(PWM_U_N_GROUP, PWM_U_N_PIN, SET);
  66. gpio_bit_write(PWM_V_N_GROUP, PWM_V_N_PIN, SET);
  67. gpio_bit_write(PWM_W_N_GROUP, PWM_W_N_PIN, SET);
  68. }else {
  69. #if 0
  70. gpio_bit_write(PWM_U_P_GROUP, PWM_U_P_PIN, RESET);
  71. gpio_bit_write(PWM_V_P_GROUP, PWM_V_P_PIN, RESET);
  72. gpio_bit_write(PWM_W_P_GROUP, PWM_W_P_PIN, RESET);
  73. gpio_bit_write(PWM_U_N_GROUP, PWM_U_N_PIN, RESET);
  74. gpio_bit_write(PWM_V_N_GROUP, PWM_V_N_PIN, RESET);
  75. gpio_bit_write(PWM_W_N_GROUP, PWM_W_N_PIN, RESET);
  76. #else
  77. pwm_3phase_init();
  78. #endif
  79. }
  80. }
  81. static void _pwm_gpio_config(void)
  82. {
  83. rcu_periph_clock_enable(PWM_U_P_RCU);
  84. rcu_periph_clock_enable(PWM_V_P_RCU);
  85. rcu_periph_clock_enable(PWM_W_P_RCU);
  86. rcu_periph_clock_enable(PWM_U_N_RCU);
  87. rcu_periph_clock_enable(PWM_V_N_RCU);
  88. rcu_periph_clock_enable(PWM_W_N_RCU);
  89. rcu_periph_clock_enable(RCU_AF);
  90. /*configure PA8 PA9 PA10(TIMER0 CH0 CH1 CH2) as alternate function*/
  91. gpio_init(PWM_U_P_GROUP,PWM_U_P_MODE,GPIO_OSPEED_50MHZ,PWM_U_P_PIN);
  92. gpio_init(PWM_V_P_GROUP,PWM_V_P_MODE,GPIO_OSPEED_50MHZ,PWM_V_P_PIN);
  93. gpio_init(PWM_W_P_GROUP,PWM_W_P_MODE,GPIO_OSPEED_50MHZ,PWM_W_P_PIN);
  94. /*configure PB13 PB14 PB15(TIMER0 CH0N CH1N CH2N) as alternate function*/
  95. gpio_init(PWM_U_N_GROUP,PWM_U_N_MODE,GPIO_OSPEED_50MHZ,PWM_U_N_PIN);
  96. gpio_init(PWM_V_N_GROUP,PWM_V_N_MODE,GPIO_OSPEED_50MHZ,PWM_V_N_PIN);
  97. gpio_init(PWM_W_N_GROUP,PWM_W_N_MODE,GPIO_OSPEED_50MHZ,PWM_W_N_PIN);
  98. /*configure BRAKE IN*/
  99. #ifdef PWM_BRAKE_GROUP
  100. /* TIMER0 BKIN */
  101. rcu_periph_clock_enable(PWM_BRAKE_RCU);
  102. gpio_init(PWM_BRAKE_GROUP, PWM_BRAKE_MODE, GPIO_OSPEED_50MHZ, PWM_BRAKE_PIN);
  103. #endif
  104. }
  105. static u8 _dead_time(u16 t) {
  106. if (t < 128) {
  107. return (u8 )t;
  108. }else if (t <= (64 + 63) * 2) { //11 1111
  109. return ((((u8)2<<6) + (t-64)/2));
  110. }else if (t <= (32 + 31) * 8) {
  111. return (((u8)3 << 6) + (t - 32)/8);
  112. }else {
  113. if ((t-32)/16 > 63) {
  114. return 0xFF;
  115. }
  116. return (((u8)7<<3) + (t - 32)/16);
  117. }
  118. }
  119. static void _init_pwm_timer(bool enable_brk) {
  120. timer_oc_parameter_struct timer_ocintpara;
  121. timer_parameter_struct timer_initpara;
  122. u32 timer = pwm_timer;
  123. u32 half_period = FOC_PWM_Half_Period;
  124. rcu_periph_clock_enable(_rcu_clk(timer));
  125. timer_deinit(timer);
  126. /* TIMER0 configuration */
  127. memset(&timer_initpara, 0, sizeof(timer_initpara));
  128. memset(&timer_ocintpara, 0, sizeof(timer_ocintpara));
  129. timer_initpara.prescaler = 0;
  130. timer_initpara.alignedmode = TIMER_COUNTER_CENTER_UP;
  131. timer_initpara.counterdirection = TIMER_COUNTER_UP;
  132. timer_initpara.period = half_period;
  133. timer_initpara.clockdivision = TIMER_CKDIV_DIV1;
  134. timer_initpara.repetitioncounter = 1;
  135. timer_init(timer,&timer_initpara);
  136. /* auto-reload preload enable */
  137. timer_auto_reload_shadow_enable(timer);
  138. /* CH1,CH2 and CH3 configuration in PWM mode */
  139. timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
  140. timer_ocintpara.outputnstate = TIMER_CCXN_ENABLE;
  141. timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
  142. timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH;
  143. timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW;
  144. timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
  145. timer_channel_output_config(timer,TIMER_CH_0,&timer_ocintpara);
  146. timer_channel_output_pulse_value_config(timer,TIMER_CH_0,half_period/2);
  147. timer_channel_output_mode_config(timer,TIMER_CH_0,PWM_MODE);
  148. timer_channel_output_shadow_config(timer,TIMER_CH_0,TIMER_OC_SHADOW_ENABLE);
  149. timer_channel_output_config(timer,TIMER_CH_1,&timer_ocintpara);
  150. timer_channel_output_pulse_value_config(timer,TIMER_CH_1,half_period/2);
  151. timer_channel_output_mode_config(timer,TIMER_CH_1,PWM_MODE);
  152. timer_channel_output_shadow_config(timer,TIMER_CH_1,TIMER_OC_SHADOW_ENABLE);
  153. timer_channel_output_config(timer,TIMER_CH_2,&timer_ocintpara);
  154. timer_channel_output_pulse_value_config(timer,TIMER_CH_2,half_period/2);
  155. timer_channel_output_mode_config(timer,TIMER_CH_2,PWM_MODE);
  156. timer_channel_output_shadow_config(timer,TIMER_CH_2,TIMER_OC_SHADOW_ENABLE);
  157. timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
  158. timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE;
  159. timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
  160. timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH;
  161. timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW;
  162. timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
  163. /* chan3 trigger adc O3CPRE is alwary active high, adc trigger is rising */
  164. timer_channel_output_config(timer,TIMER_CH_3,&timer_ocintpara);
  165. timer_channel_output_pulse_value_config(timer,TIMER_CH_3,half_period-5);
  166. timer_channel_output_mode_config(timer,TIMER_CH_3,TIMER_OC_MODE_PWM1);
  167. timer_channel_output_shadow_config(timer,TIMER_CH_3,TIMER_OC_SHADOW_ENABLE);
  168. #ifdef PWM_BRAKE_GROUP
  169. timer_break_parameter_struct timer_breakpara;
  170. timer_breakpara.runoffstate = TIMER_ROS_STATE_DISABLE;
  171. timer_breakpara.ideloffstate = TIMER_ROS_STATE_DISABLE;
  172. timer_breakpara.protectmode = TIMER_CCHP_PROT_OFF;
  173. timer_breakpara.deadtime = _dead_time(NS_2_TCLK(PWM_DEAD_TIME_NS));
  174. timer_breakpara.breakstate = enable_brk?TIMER_BREAK_ENABLE:TIMER_BREAK_DISABLE;
  175. timer_breakpara.breakpolarity = TIMER_BREAK_POLARITY_LOW;
  176. timer_breakpara.outputautostate = TIMER_OUTAUTO_DISABLE;
  177. timer_break_config(timer,&timer_breakpara);
  178. timer_interrupt_enable(timer, TIMER_INT_BRK);
  179. timer_interrupt_flag_clear(timer, TIMER_INT_FLAG_BRK);
  180. nvic_irq_enable(TIMER0_BRK_IRQn, EBREAK_IRQ_PRIORITY, 0);
  181. #else
  182. _gpio_brakein_irq_enable();
  183. #endif
  184. timer_master_slave_mode_config(timer,TIMER_MASTER_SLAVE_MODE_DISABLE);
  185. pwm_enable_channel();
  186. timer_interrupt_disable(timer, TIMER_INT_UP);
  187. timer_interrupt_flag_clear(timer, TIMER_INT_FLAG_UP);
  188. nvic_irq_enable(TIMER0_UP_IRQn, TIMER_UP_IRQ_PRIORITY, 0);
  189. timer_enable(timer);
  190. #ifdef GD32_FOC_DEMO
  191. /* IR2136S enable */
  192. gpio_ir2136_enable(true);
  193. #endif
  194. }
  195. #ifndef PWM_BRAKE_GROUP
  196. static void _gpio_brakein_irq_enable(void){
  197. #ifndef GD32_FOC_DEMO
  198. gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOB, GPIO_PIN_SOURCE_4);
  199. exti_init(EXTI_4, EXTI_INTERRUPT, EXTI_TRIG_BOTH);
  200. nvic_irq_enable(EXTI4_IRQn, EBREAK_IRQ_PRIORITY, 0U);
  201. exti_interrupt_flag_clear(EXTI_4);
  202. exti_interrupt_enable(EXTI_4);
  203. gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOB, GPIO_PIN_SOURCE_5);
  204. exti_init(EXTI_5, EXTI_INTERRUPT, EXTI_TRIG_BOTH);
  205. nvic_irq_enable(EXTI5_9_IRQn, EBREAK_IRQ_PRIORITY, 0U);
  206. exti_interrupt_flag_clear(EXTI_5);
  207. exti_interrupt_enable(EXTI_5);
  208. #endif
  209. }
  210. #endif
  211. void pwm_start(void){
  212. pwm_update_duty(FOC_PWM_Half_Period/2, FOC_PWM_Half_Period/2, FOC_PWM_Half_Period/2);
  213. pwm_update_2smaples(FOC_PWM_Half_Period-1, FOC_PWM_Half_Period + 1);
  214. /* wait for a new PWM period to flush last HF task */
  215. timer_flag_clear(pwm_timer, TIMER_FLAG_UP);
  216. timer_event_software_generate(pwm_timer, TIMER_EVENT_SRC_UPG);
  217. while ( timer_flag_get(pwm_timer, TIMER_FLAG_UP) == RESET ){}
  218. /* Clear Update Flag */
  219. timer_flag_clear(pwm_timer, TIMER_FLAG_UP);
  220. timer_primary_output_config(pwm_timer,ENABLE);
  221. }
  222. void pwm_stop(void){
  223. timer_primary_output_config(pwm_timer,DISABLE);
  224. timer_interrupt_disable(pwm_timer, TIMER_INT_UP);
  225. /* wait for a new PWM period to flush last HF task */
  226. timer_flag_clear(pwm_timer, TIMER_FLAG_UP);
  227. while ( timer_flag_get(pwm_timer, TIMER_FLAG_UP) == RESET ){}
  228. /* Clear Update Flag */
  229. timer_flag_clear(pwm_timer, TIMER_FLAG_UP);
  230. }
  231. void pwm_enable_output(bool enable) {
  232. if (enable) {
  233. timer_primary_output_config(pwm_timer,ENABLE);
  234. }else {
  235. timer_primary_output_config(pwm_timer,DISABLE);
  236. }
  237. }
  238. /*open low side of the mosfet*/
  239. void pwm_turn_on_low_side(void)
  240. {
  241. pwm_update_duty(0, 0, 0);
  242. pwm_update_2smaples(FOC_PWM_Half_Period-1, FOC_PWM_Half_Period + 1);
  243. timer_flag_clear(pwm_timer,TIMER_FLAG_UP);
  244. timer_event_software_generate(pwm_timer, TIMER_EVENT_SRC_UPG);
  245. while (timer_flag_get(pwm_timer,TIMER_FLAG_UP) == RESET );
  246. /* Main PWM Output Enable */
  247. timer_primary_output_config(pwm_timer, ENABLE);
  248. }
  249. void pwm_update_sample(u32 samp1, u32 samp2, u8 sector) {
  250. if (samp1 < FOC_PWM_Half_Period) {
  251. TIMER_CH3CV(pwm_timer) = samp1;
  252. pwm_change_t3_mode(TIMER_OC_MODE_PWM1);
  253. }else {
  254. TIMER_CH3CV(pwm_timer) = samp2;
  255. pwm_change_t3_mode(TIMER_OC_MODE_PWM0);
  256. }
  257. adc_current_sample_config(sector);
  258. }