/*
 * File: PMSM_Controller.c
 *
 * Code generated for Simulink model 'PMSM_Controller'.
 *
 * Model version                  : 1.1529
 * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
 * C/C++ source code generated on : Tue Aug  2 19:43:20 2022
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: ARM Compatible->ARM Cortex-M
 * Code generation objectives:
 *    1. Execution efficiency
 *    2. RAM efficiency
 * Validation result: Not run
 */

#include "PMSM_Controller.h"

/* Named constants for Chart: '<S36>/Control_Mode_Manager' */
#define IN_ACTIVE                      ((uint8_T)1U)
#define IN_NO_ACTIVE_CHILD             ((uint8_T)0U)
#define IN_OPEN                        ((uint8_T)2U)
#define IN_SPEED_MODE                  ((uint8_T)1U)
#define IN_TORQUE_MODE                 ((uint8_T)2U)
#define OPEN_MODE                      ((uint8_T)0U)
#define SPD_MODE                       ((uint8_T)1U)
#define TRQ_MODE                       ((uint8_T)2U)
#ifndef UCHAR_MAX
#include <limits.h>
#endif

#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) )
#error Code was generated for compiler with different sized uchar/char. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif

#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) )
#error Code was generated for compiler with different sized ushort/short. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif

#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) )
#error Code was generated for compiler with different sized uint/int. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif

#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) )
#error Code was generated for compiler with different sized ulong/long. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif

/* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */
extern int16_T rt_sqrt_Us32En6_Ys16En5_Is64En10_f_s(int32_T u);
extern int16_T rt_sqrt_Us32En10_Ys16En5_Is32En10_s_s(int32_T u);
extern uint16_T rt_sqrt_Uu16En14_Yu16En14_Iu32En28_s_s(uint16_T u);
static uint16_T plook_u16s16_evencka(int16_T u, int16_T bp0, uint16_T bpSpace,
  uint32_T maxIndex);
static int32_T div_nde_s32_floor(int32_T numerator, int32_T denominator);
static void wrapper(uint32_T rtu_In1, uint32_T rtu_In2, uint32_T *rty_Out1);
static void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T
  rty_y[2], DW_Low_Pass_Filter *localDW);
static void PI_backCalc_fixdt_Init(DW_PI_backCalc_fixdt *localDW);
static int32_T PI_backCalc_fixdt(int32_T rtu_err, int16_T rtu_P, int16_T rtu_I,
  int16_T rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_init,
  uint8_T rtu_reset, DW_PI_backCalc_fixdt *localDW, ZCE_PI_backCalc_fixdt
  *localZCE);
static void PI_backCalc_fixdt_g_Init(DW_PI_backCalc_fixdt_j *localDW);
static int32_T PI_backCalc_fixdt_i(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I,
  int16_T rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_init,
  uint8_T rtu_reset, DW_PI_backCalc_fixdt_j *localDW, ZCE_PI_backCalc_fixdt_n
  *localZCE);
static void RateInit(int16_T rtu_initVal, int16_T rtu_target, int16_T rtu_step,
                     int16_T *rty_s_step, int16_T *rty_High, int16_T *rty_Low);
static void RateInit_a(int16_T rtu_initVal, int16_T rtu_target, int16_T rtu_step,
  int16_T *rty_s_step, int16_T *rty_High, int16_T *rty_Low);
static uint16_T plook_u16s16_evencka(int16_T u, int16_T bp0, uint16_T bpSpace,
  uint32_T maxIndex)
{
  uint16_T bpIndex;

  /* Prelookup - Index only
     Index Search method: 'even'
     Extrapolation method: 'Clip'
     Use previous index: 'off'
     Use last breakpoint for index at or above upper limit: 'on'
     Remove protection against out-of-range input in generated code: 'off'
   */
  if (u <= bp0) {
    bpIndex = 0U;
  } else {
    bpIndex = (uint16_T)((uint32_T)(uint16_T)(u - bp0) / bpSpace);
    if (bpIndex < maxIndex) {
    } else {
      bpIndex = (uint16_T)maxIndex;
    }
  }

  return bpIndex;
}

static int32_T div_nde_s32_floor(int32_T numerator, int32_T denominator)
{
  return (((numerator < 0) != (denominator < 0)) && (numerator % denominator !=
           0) ? -1 : 0) + numerator / denominator;
}

/*
 * Output and update for action system:
 *    '<S21>/wrapper'
 *    '<S31>/wrapper'
 */
static void wrapper(uint32_T rtu_In1, uint32_T rtu_In2, uint32_T *rty_Out1)
{
  /* Sum: '<S24>/Add1' incorporates:
   *  Sum: '<S24>/Add'
   *  Sum: '<S24>/Subtract'
   */
  *rty_Out1 = rtu_In1 - rtu_In2;
}

/*
 * Output and update for atomic system:
 *    '<S39>/Low_Pass_Filter'
 *    '<S68>/Low_Pass_Filter'
 */
static void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T
  rty_y[2], DW_Low_Pass_Filter *localDW)
{
  int32_T rtb_Sum3_i;

  /* Sum: '<S47>/Sum2' incorporates:
   *  UnitDelay: '<S47>/UnitDelay1'
   */
  rtb_Sum3_i = rtu_u[0] - (localDW->UnitDelay1_DSTATE[0] >> 16);
  if (rtb_Sum3_i > 32767) {
    rtb_Sum3_i = 32767;
  } else {
    if (rtb_Sum3_i < -32768) {
      rtb_Sum3_i = -32768;
    }
  }

  /* Sum: '<S47>/Sum3' incorporates:
   *  Product: '<S47>/Divide3'
   *  Sum: '<S47>/Sum2'
   *  UnitDelay: '<S47>/UnitDelay1'
   */
  rtb_Sum3_i = rtu_coef * rtb_Sum3_i + localDW->UnitDelay1_DSTATE[0];

  /* DataTypeConversion: '<S47>/Data Type Conversion' */
  rty_y[0] = (int16_T)(rtb_Sum3_i >> 16);

  /* Update for UnitDelay: '<S47>/UnitDelay1' */
  localDW->UnitDelay1_DSTATE[0] = rtb_Sum3_i;

  /* Sum: '<S47>/Sum2' incorporates:
   *  UnitDelay: '<S47>/UnitDelay1'
   */
  rtb_Sum3_i = rtu_u[1] - (localDW->UnitDelay1_DSTATE[1] >> 16);
  if (rtb_Sum3_i > 32767) {
    rtb_Sum3_i = 32767;
  } else {
    if (rtb_Sum3_i < -32768) {
      rtb_Sum3_i = -32768;
    }
  }

  /* Sum: '<S47>/Sum3' incorporates:
   *  Product: '<S47>/Divide3'
   *  Sum: '<S47>/Sum2'
   *  UnitDelay: '<S47>/UnitDelay1'
   */
  rtb_Sum3_i = rtu_coef * rtb_Sum3_i + localDW->UnitDelay1_DSTATE[1];

  /* DataTypeConversion: '<S47>/Data Type Conversion' */
  rty_y[1] = (int16_T)(rtb_Sum3_i >> 16);

  /* Update for UnitDelay: '<S47>/UnitDelay1' */
  localDW->UnitDelay1_DSTATE[1] = rtb_Sum3_i;
}

/* System initialize for atomic system: '<S79>/PI_Speed' */
static void PI_backCalc_fixdt_Init(DW_PI_backCalc_fixdt *localDW)
{
  /* InitializeConditions for Delay: '<S82>/Resettable Delay' */
  localDW->icLoad = 1U;
}

/* Output and update for atomic system: '<S79>/PI_Speed' */
static int32_T PI_backCalc_fixdt(int32_T rtu_err, int16_T rtu_P, int16_T rtu_I,
  int16_T rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_init,
  uint8_T rtu_reset, DW_PI_backCalc_fixdt *localDW, ZCE_PI_backCalc_fixdt
  *localZCE)
{
  int32_T rty_pi_out_0;
  int64_T tmp;
  int64_T tmp_0;

  /* Product: '<S81>/Divide4' */
  tmp_0 = (int64_T)rtu_err * rtu_P;
  if (tmp_0 > 2147483647LL) {
    tmp_0 = 2147483647LL;
  } else {
    if (tmp_0 < -2147483648LL) {
      tmp_0 = -2147483648LL;
    }
  }

  /* Delay: '<S82>/Resettable Delay' incorporates:
   *  DataTypeConversion: '<S82>/Data Type Conversion2'
   */
  if ((rtu_reset > 0) && (localZCE->ResettableDelay_Reset_ZCE_fm != POS_ZCSIG))
  {
    localDW->icLoad = 1U;
  }

  localZCE->ResettableDelay_Reset_ZCE_fm = (ZCSigState)(rtu_reset > 0);
  if (localDW->icLoad != 0) {
    localDW->ResettableDelay_DSTATE = rtu_init << 7;
  }

  /* Product: '<S81>/Divide1' incorporates:
   *  Product: '<S81>/Divide4'
   */
  tmp = ((int64_T)(int32_T)tmp_0 * rtu_I) >> 14;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Sum: '<S81>/Sum2' incorporates:
   *  Product: '<S81>/Divide1'
   *  UnitDelay: '<S81>/UnitDelay'
   */
  tmp = (int64_T)(int32_T)tmp + localDW->UnitDelay_DSTATE;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Sum: '<S82>/Sum1' incorporates:
   *  Delay: '<S82>/Resettable Delay'
   *  Sum: '<S81>/Sum2'
   */
  tmp = (((int64_T)localDW->ResettableDelay_DSTATE << 2) + (int32_T)tmp) >> 2;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* Sum: '<S81>/Sum6' incorporates:
   *  DataTypeConversion: '<S82>/Data Type Conversion1'
   *  Product: '<S81>/Divide4'
   *  Sum: '<S82>/Sum1'
   */
  tmp_0 = (int64_T)((int32_T)tmp << 2) + (int32_T)tmp_0;
  if (tmp_0 > 2147483647LL) {
    tmp_0 = 2147483647LL;
  } else {
    if (tmp_0 < -2147483648LL) {
      tmp_0 = -2147483648LL;
    }
  }

  /* RelationalOperator: '<S83>/LowerRelop1' incorporates:
   *  Switch: '<S83>/Switch2'
   */
  rty_pi_out_0 = rtu_satMax << 9;

  /* Switch: '<S83>/Switch2' incorporates:
   *  RelationalOperator: '<S83>/LowerRelop1'
   *  Sum: '<S81>/Sum6'
   */
  if ((int32_T)tmp_0 <= rty_pi_out_0) {
    /* RelationalOperator: '<S83>/UpperRelop' incorporates:
     *  Switch: '<S83>/Switch'
     */
    rty_pi_out_0 = rtu_satMin << 9;

    /* Switch: '<S83>/Switch' incorporates:
     *  RelationalOperator: '<S83>/UpperRelop'
     */
    if ((int32_T)tmp_0 >= rty_pi_out_0) {
      rty_pi_out_0 = (int32_T)tmp_0;
    }
  }

  /* Update for UnitDelay: '<S81>/UnitDelay' incorporates:
   *  Product: '<S81>/Divide2'
   *  Sum: '<S81>/Sum3'
   *  Sum: '<S81>/Sum6'
   */
  localDW->UnitDelay_DSTATE = (int32_T)(((int64_T)(rty_pi_out_0 - (int32_T)tmp_0)
    * rtu_Kb) >> 14);

  /* Update for Delay: '<S82>/Resettable Delay' incorporates:
   *  Sum: '<S82>/Sum1'
   */
  localDW->icLoad = 0U;
  localDW->ResettableDelay_DSTATE = (int32_T)tmp;
  return rty_pi_out_0;
}

/*
 * System initialize for atomic system:
 *    '<S85>/PI_backCalc_fixdt'
 *    '<S85>/PI_backCalc_fixdt1'
 */
static void PI_backCalc_fixdt_g_Init(DW_PI_backCalc_fixdt_j *localDW)
{
  /* InitializeConditions for Delay: '<S92>/Resettable Delay' */
  localDW->icLoad = 1U;
}

/*
 * Output and update for atomic system:
 *    '<S85>/PI_backCalc_fixdt'
 *    '<S85>/PI_backCalc_fixdt1'
 */
static int32_T PI_backCalc_fixdt_i(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I,
  int16_T rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_init,
  uint8_T rtu_reset, DW_PI_backCalc_fixdt_j *localDW, ZCE_PI_backCalc_fixdt_n
  *localZCE)
{
  int32_T rty_pi_out_0;
  int64_T tmp;
  int64_T tmp_0;
  int32_T rtb_Divide4_px;

  /* Product: '<S90>/Divide4' */
  rtb_Divide4_px = (rtu_err * rtu_P) >> 1;

  /* Delay: '<S92>/Resettable Delay' incorporates:
   *  DataTypeConversion: '<S92>/Data Type Conversion2'
   */
  if ((rtu_reset > 0) && (localZCE->ResettableDelay_Reset_ZCE != POS_ZCSIG)) {
    localDW->icLoad = 1U;
  }

  localZCE->ResettableDelay_Reset_ZCE = (ZCSigState)(rtu_reset > 0);
  if (localDW->icLoad != 0) {
    localDW->ResettableDelay_DSTATE = rtu_init << 7;
  }

  /* Product: '<S90>/Divide1' incorporates:
   *  Product: '<S90>/Divide4'
   */
  tmp_0 = ((int64_T)rtb_Divide4_px * rtu_I) >> 14;
  if (tmp_0 > 2147483647LL) {
    tmp_0 = 2147483647LL;
  } else {
    if (tmp_0 < -2147483648LL) {
      tmp_0 = -2147483648LL;
    }
  }

  /* Sum: '<S90>/Sum2' incorporates:
   *  Product: '<S90>/Divide1'
   *  UnitDelay: '<S90>/UnitDelay'
   */
  tmp_0 = (int64_T)(int32_T)tmp_0 + localDW->UnitDelay_DSTATE;
  if (tmp_0 > 2147483647LL) {
    tmp_0 = 2147483647LL;
  } else {
    if (tmp_0 < -2147483648LL) {
      tmp_0 = -2147483648LL;
    }
  }

  /* Sum: '<S92>/Sum1' incorporates:
   *  Delay: '<S92>/Resettable Delay'
   *  Sum: '<S90>/Sum2'
   */
  tmp_0 = (((int64_T)localDW->ResettableDelay_DSTATE << 2) + (int32_T)tmp_0) >>
    2;
  if (tmp_0 > 2147483647LL) {
    tmp_0 = 2147483647LL;
  } else {
    if (tmp_0 < -2147483648LL) {
      tmp_0 = -2147483648LL;
    }
  }

  /* Sum: '<S90>/Sum6' incorporates:
   *  DataTypeConversion: '<S92>/Data Type Conversion1'
   *  Product: '<S90>/Divide4'
   *  Sum: '<S92>/Sum1'
   */
  tmp = (int64_T)((int32_T)tmp_0 << 2) + rtb_Divide4_px;
  if (tmp > 2147483647LL) {
    tmp = 2147483647LL;
  } else {
    if (tmp < -2147483648LL) {
      tmp = -2147483648LL;
    }
  }

  /* RelationalOperator: '<S93>/LowerRelop1' incorporates:
   *  Switch: '<S93>/Switch2'
   */
  rty_pi_out_0 = rtu_satMax << 9;

  /* Switch: '<S93>/Switch2' incorporates:
   *  RelationalOperator: '<S93>/LowerRelop1'
   *  Sum: '<S90>/Sum6'
   */
  if ((int32_T)tmp <= rty_pi_out_0) {
    /* RelationalOperator: '<S93>/UpperRelop' incorporates:
     *  Switch: '<S93>/Switch'
     */
    rty_pi_out_0 = rtu_satMin << 9;

    /* Switch: '<S93>/Switch' incorporates:
     *  RelationalOperator: '<S93>/UpperRelop'
     */
    if ((int32_T)tmp >= rty_pi_out_0) {
      rty_pi_out_0 = (int32_T)tmp;
    }
  }

  /* Update for UnitDelay: '<S90>/UnitDelay' incorporates:
   *  Product: '<S90>/Divide2'
   *  Sum: '<S90>/Sum3'
   *  Sum: '<S90>/Sum6'
   */
  localDW->UnitDelay_DSTATE = (int32_T)(((int64_T)(rty_pi_out_0 - (int32_T)tmp) *
    rtu_Kb) >> 14);

  /* Update for Delay: '<S92>/Resettable Delay' incorporates:
   *  Sum: '<S92>/Sum1'
   */
  localDW->icLoad = 0U;
  localDW->ResettableDelay_DSTATE = (int32_T)tmp_0;
  return rty_pi_out_0;
}

/*
 * Output and update for action system:
 *    '<S98>/RateInit'
 *    '<S105>/RateInit'
 */
static void RateInit(int16_T rtu_initVal, int16_T rtu_target, int16_T rtu_step,
                     int16_T *rty_s_step, int16_T *rty_High, int16_T *rty_Low)
{
  int16_T rtb_Add_c;

  /* Sum: '<S99>/Add' */
  rtb_Add_c = (int16_T)((rtu_target - rtu_initVal) >> 1);

  /* Signum: '<S99>/Sign' incorporates:
   *  Sum: '<S99>/Add'
   */
  if (rtb_Add_c < 0) {
    rtb_Add_c = -1;
  } else {
    rtb_Add_c = (int16_T)(rtb_Add_c > 0);
  }

  /* End of Signum: '<S99>/Sign' */

  /* Product: '<S99>/Divide' */
  *rty_s_step = (int16_T)(rtu_step * rtb_Add_c);

  /* MinMax: '<S99>/Max' */
  if (rtu_target > rtu_initVal) {
    *rty_High = rtu_target;
  } else {
    *rty_High = rtu_initVal;
  }

  /* End of MinMax: '<S99>/Max' */

  /* MinMax: '<S99>/Max1' */
  if (rtu_initVal < rtu_target) {
    *rty_Low = rtu_initVal;
  } else {
    *rty_Low = rtu_target;
  }

  /* End of MinMax: '<S99>/Max1' */
}

/*
 * Output and update for action system:
 *    '<S113>/RateInit'
 *    '<S115>/RateInit'
 */
static void RateInit_a(int16_T rtu_initVal, int16_T rtu_target, int16_T rtu_step,
  int16_T *rty_s_step, int16_T *rty_High, int16_T *rty_Low)
{
  int16_T rtb_Add_pn;

  /* Sum: '<S116>/Add' */
  rtb_Add_pn = (int16_T)((rtu_target - rtu_initVal) >> 1);

  /* Signum: '<S116>/Sign' incorporates:
   *  Sum: '<S116>/Add'
   */
  if (rtb_Add_pn < 0) {
    rtb_Add_pn = -1;
  } else {
    rtb_Add_pn = (int16_T)(rtb_Add_pn > 0);
  }

  /* End of Signum: '<S116>/Sign' */

  /* Product: '<S116>/Divide' */
  *rty_s_step = (int16_T)(rtu_step * rtb_Add_pn);

  /* MinMax: '<S116>/Max' */
  if (rtu_target > rtu_initVal) {
    *rty_High = rtu_target;
  } else {
    *rty_High = rtu_initVal;
  }

  /* End of MinMax: '<S116>/Max' */

  /* MinMax: '<S116>/Max1' */
  if (rtu_initVal < rtu_target) {
    *rty_Low = rtu_initVal;
  } else {
    *rty_Low = rtu_target;
  }

  /* End of MinMax: '<S116>/Max1' */
}

int16_T rt_sqrt_Us32En6_Ys16En5_Is64En10_f_s(int32_T u)
{
  int64_T tmp03_u;
  int32_T iBit;
  int16_T shiftMask;
  int16_T tmp01_y;
  int16_T y;

  /* Fixed-Point Sqrt Computation by the bisection method. */
  if (u > 0) {
    y = 0;
    shiftMask = 16384;
    tmp03_u = (int64_T)u << 4;
    for (iBit = 0; iBit < 15; iBit++) {
      tmp01_y = (int16_T)(y | shiftMask);
      if (tmp01_y * tmp01_y <= tmp03_u) {
        y = tmp01_y;
      }

      shiftMask = (int16_T)((uint32_T)shiftMask >> 1U);
    }
  } else {
    y = 0;
  }

  return y;
}

int16_T rt_sqrt_Us32En10_Ys16En5_Is32En10_s_s(int32_T u)
{
  int32_T iBit;
  int16_T shiftMask;
  int16_T tmp01_y;
  int16_T y;

  /* Fixed-Point Sqrt Computation by the bisection method. */
  if (u > 0) {
    y = 0;
    shiftMask = 16384;
    for (iBit = 0; iBit < 15; iBit++) {
      tmp01_y = (int16_T)(y | shiftMask);
      if (tmp01_y * tmp01_y <= u) {
        y = tmp01_y;
      }

      shiftMask = (int16_T)((uint32_T)shiftMask >> 1U);
    }
  } else {
    y = 0;
  }

  return y;
}

uint16_T rt_sqrt_Uu16En14_Yu16En14_Iu32En28_s_s(uint16_T u)
{
  int32_T iBit;
  uint32_T tmp03_u;
  uint16_T shiftMask;
  uint16_T tmp01_y;
  uint16_T y;

  /* Fixed-Point Sqrt Computation by the bisection method. */
  if (u > 0) {
    y = 0U;
    shiftMask = 32768U;
    tmp03_u = (uint32_T)u << 14;
    for (iBit = 0; iBit < 16; iBit++) {
      tmp01_y = (uint16_T)(y | shiftMask);
      if ((uint32_T)tmp01_y * tmp01_y <= tmp03_u) {
        y = tmp01_y;
      }

      shiftMask = (uint16_T)((uint32_T)shiftMask >> 1U);
    }
  } else {
    y = 0U;
  }

  return y;
}

/* Model step function */
void PMSM_Controller_step(RT_MODEL *const rtM)
{
  DW *rtDW = rtM->dwork;
  PrevZCX *rtPrevZCX = rtM->prevZCSigState;
  ExtU *rtU = (ExtU *) rtM->inputs;
  ExtY *rtY = (ExtY *) rtM->outputs;
  int64_T tmp_2;
  uint64_T tmp_0;
  uint64_T tmp_1;
  int32_T rtb_Divide_e_idx_1;
  int32_T rtb_Divide_e_idx_2;
  int32_T rtb_Gain_b;
  int32_T rtb_Gain_h;
  int32_T rtb_Gain_ib;
  int32_T rtb_MathFunction2_n;
  int32_T rtb_RelationalOperator4_b;
  int32_T rtb_Switch2_au;
  int32_T rtb_Switch3;
  int32_T tmp;
  uint32_T rtb_Merge;
  uint32_T rtb_Rem1;
  uint32_T rtb_Switch1;
  int16_T rtb_TmpSignalConversionAtLow_Pass_FilterInport1[2];
  int16_T rtb_UnitDelay1_ko[2];
  int16_T rtb_Add2_lk;
  int16_T rtb_Divide1_oy;
  int16_T rtb_Divide3_k;
  int16_T rtb_Gain_a;
  int16_T rtb_Sum1_ak;
  int16_T rtb_Sum6;
  int16_T rtb_Switch2_pl;
  int16_T rtb_r_cos_M1;
  uint16_T rtb_Divide_d;
  uint16_T rtb_Sum1_p;
  int8_T rtb_Sum2;
  uint8_T rtb_Add_h;
  uint8_T rtb_DataTypeConversion_e;
  uint8_T rtb_Sum_d;
  uint8_T rtb_UnitDelay_n;
  uint8_T rtb_dz_cntTrnsDet;
  boolean_T rtb_Edge_Detect;
  boolean_T rtb_LogicalOperator1_g;
  boolean_T rtb_LogicalOperator2_c;
  boolean_T rtb_LogicalOperator4_f;
  boolean_T rtb_RelationalOperator;
  boolean_T rtb_RelationalOperator4_d;
  boolean_T rtb_UnitDelay_c;

  /* Outputs for Atomic SubSystem: '<Root>/PMSM_Controller' */
  /* Product: '<S43>/Divide' incorporates:
   *  Constant: '<S43>/Constant'
   *  Inport: '<Root>/adc_Phase'
   */
  rtb_Divide_e_idx_1 = rtU->adc_Phase[1] * rtP.f_adc_curr_ceof;
  rtb_Divide_e_idx_2 = rtU->adc_Phase[2] * rtP.f_adc_curr_ceof;

  /* Gain: '<S46>/Gain' incorporates:
   *  Constant: '<S43>/Constant'
   *  Inport: '<Root>/adc_Phase'
   *  Product: '<S43>/Divide'
   */
  rtb_RelationalOperator4_b = (rtU->adc_Phase[0] * rtP.f_adc_curr_ceof) >> 8;
  if (rtb_RelationalOperator4_b > 32767) {
    rtb_RelationalOperator4_b = 32767;
  } else {
    if (rtb_RelationalOperator4_b < -32768) {
      rtb_RelationalOperator4_b = -32768;
    }
  }

  /* Sum: '<S46>/Add3' */
  tmp_2 = ((int64_T)rtb_Divide_e_idx_1 + rtb_Divide_e_idx_2) >> 8;
  if (tmp_2 > 32767LL) {
    tmp_2 = 32767LL;
  } else {
    if (tmp_2 < -32768LL) {
      tmp_2 = -32768LL;
    }
  }

  /* Sum: '<S46>/Add' incorporates:
   *  Gain: '<S46>/Gain'
   *  Sum: '<S46>/Add3'
   */
  rtb_RelationalOperator4_b = ((rtb_RelationalOperator4_b << 1) - (int16_T)tmp_2)
    >> 1;
  if (rtb_RelationalOperator4_b > 32767) {
    rtb_RelationalOperator4_b = 32767;
  } else {
    if (rtb_RelationalOperator4_b < -32768) {
      rtb_RelationalOperator4_b = -32768;
    }
  }

  /* Gain: '<S46>/Gain1' incorporates:
   *  Product: '<S48>/Divide1'
   *  Sum: '<S46>/Add'
   */
  rtb_Divide1_oy = (int16_T)((21845 * rtb_RelationalOperator4_b) >> 16);

  /* Logic: '<S17>/Edge_Detect' incorporates:
   *  Delay: '<S17>/Delay'
   *  Delay: '<S17>/Delay1'
   *  Delay: '<S17>/Delay2'
   *  Inport: '<Root>/hall_abc'
   */
  rtb_Edge_Detect = (boolean_T)((rtU->hall_abc[0] != 0) ^ (rtDW->Delay_DSTATE_p
    != 0) ^ (rtU->hall_abc[1] != 0) ^ (rtDW->Delay1_DSTATE != 0) ^
    (rtU->hall_abc[2] != 0)) ^ (rtDW->Delay2_DSTATE != 0);

  /* Sum: '<S19>/Add' incorporates:
   *  Gain: '<S19>/Gain'
   *  Gain: '<S19>/Gain1'
   *  Inport: '<Root>/hall_abc'
   */
  rtb_Add_h = (uint8_T)((uint32_T)(uint8_T)((uint32_T)(uint8_T)(rtU->hall_abc[2]
    << 2) + (uint8_T)(rtU->hall_abc[1] << 1)) + rtU->hall_abc[0]);

  /* If: '<S3>/If2' incorporates:
   *  Inport: '<Root>/sys_ticks'
   *  Inport: '<S16>/i_count'
   */
  if (rtb_Edge_Detect) {
    /* Outputs for IfAction SubSystem: '<S3>/Direction_Detection' incorporates:
     *  ActionPort: '<S16>/Action Port'
     */
    /* UnitDelay: '<S16>/UnitDelay3' */
    rtDW->UnitDelay3 = rtDW->Switch2_o;

    /* Sum: '<S16>/Sum2' incorporates:
     *  Constant: '<S19>/vec_hallToPos'
     *  Selector: '<S19>/Selector'
     *  UnitDelay: '<S16>/UnitDelay2'
     */
    rtb_Sum2 = (int8_T)(rtConstP.vec_hallToPos_Value[rtb_Add_h] -
                        rtDW->UnitDelay2_DSTATE_i);

    /* Switch: '<S16>/Switch2' incorporates:
     *  Constant: '<S16>/Constant20'
     *  Constant: '<S16>/Constant8'
     *  Logic: '<S16>/Logical Operator3'
     *  RelationalOperator: '<S16>/Relational Operator1'
     *  RelationalOperator: '<S16>/Relational Operator6'
     */
    if ((rtb_Sum2 == 1) || (rtb_Sum2 == -5)) {
      /* Switch: '<S16>/Switch2' incorporates:
       *  Constant: '<S16>/Constant24'
       */
      rtDW->Switch2_o = 1;
    } else {
      /* Switch: '<S16>/Switch2' incorporates:
       *  Constant: '<S16>/Constant23'
       */
      rtDW->Switch2_o = -1;
    }

    /* End of Switch: '<S16>/Switch2' */
    rtDW->i_count = rtU->sys_ticks;

    /* Update for UnitDelay: '<S16>/UnitDelay2' incorporates:
     *  Constant: '<S19>/vec_hallToPos'
     *  Inport: '<Root>/sys_ticks'
     *  Inport: '<S16>/i_count'
     *  Selector: '<S19>/Selector'
     */
    rtDW->UnitDelay2_DSTATE_i = rtConstP.vec_hallToPos_Value[rtb_Add_h];

    /* End of Outputs for SubSystem: '<S3>/Direction_Detection' */
  }

  /* End of If: '<S3>/If2' */

  /* If: '<S21>/If' incorporates:
   *  Inport: '<Root>/sys_ticks'
   */
  if (rtU->sys_ticks >= rtDW->i_count) {
    /* Outputs for IfAction SubSystem: '<S21>/normal' incorporates:
     *  ActionPort: '<S23>/Action Port'
     */
    /* Sum: '<S23>/Subtract' */
    rtb_Rem1 = rtU->sys_ticks - rtDW->i_count;

    /* End of Outputs for SubSystem: '<S21>/normal' */
  } else {
    /* Outputs for IfAction SubSystem: '<S21>/wrapper' incorporates:
     *  ActionPort: '<S24>/Action Port'
     */
    wrapper(rtU->sys_ticks, rtDW->i_count, &rtb_Rem1);

    /* End of Outputs for SubSystem: '<S21>/wrapper' */
  }

  /* End of If: '<S21>/If' */

  /* If: '<S20>/If2' */
  if (rtb_Edge_Detect) {
    /* Outputs for IfAction SubSystem: '<S20>/Raw_Motor_Speed_Estimation' incorporates:
     *  ActionPort: '<S29>/Action Port'
     */
    /* If: '<S31>/If' incorporates:
     *  UnitDelay: '<S29>/Unit Delay'
     */
    if (rtDW->i_count >= rtDW->UnitDelay_DSTATE) {
      /* Outputs for IfAction SubSystem: '<S31>/normal' incorporates:
       *  ActionPort: '<S32>/Action Port'
       */
      /* Sum: '<S32>/Subtract' */
      rtb_Merge = rtDW->i_count - rtDW->UnitDelay_DSTATE;

      /* End of Outputs for SubSystem: '<S31>/normal' */
    } else {
      /* Outputs for IfAction SubSystem: '<S31>/wrapper' incorporates:
       *  ActionPort: '<S33>/Action Port'
       */
      wrapper(rtDW->i_count, rtDW->UnitDelay_DSTATE, &rtb_Merge);

      /* End of Outputs for SubSystem: '<S31>/wrapper' */
    }

    /* End of If: '<S31>/If' */

    /* Sum: '<S29>/Sum13' incorporates:
     *  UnitDelay: '<S29>/UnitDelay2'
     *  UnitDelay: '<S29>/UnitDelay3'
     *  UnitDelay: '<S29>/UnitDelay5'
     */
    tmp_1 = (((uint64_T)rtDW->UnitDelay2_DSTATE + rtDW->UnitDelay3_DSTATE) +
             rtDW->UnitDelay5_DSTATE) + rtb_Merge;
    if (tmp_1 > 4294967295ULL) {
      tmp_1 = 4294967295ULL;
    }

    /* Switch: '<S29>/Switch1' incorporates:
     *  Constant: '<S29>/cf_speedCoef'
     *  Constant: '<S29>/polePairs'
     *  Product: '<S29>/Divide'
     *  Product: '<S29>/Divide13'
     *  Product: '<S29>/Divide14'
     *  UnitDelay: '<S29>/Unit Delay1'
     */
    if (rtDW->UnitDelay1_DSTATE_k != 0) {
      rtb_Switch1 = (uint32_T)(((uint64_T)(10000000U / rtP.n_polePairs) << 4) /
        rtb_Merge);
    } else {
      /* Product: '<S29>/Divide13' incorporates:
       *  Constant: '<S29>/cf_speedCoef'
       *  Constant: '<S29>/polePairs'
       *  Gain: '<S29>/g_Ha'
       *  Product: '<S29>/Divide'
       *  Sum: '<S29>/Sum13'
       */
      tmp_0 = ((uint64_T)((10000000U / rtP.n_polePairs) << 2) << 4) / (uint32_T)
        tmp_1;
      if (tmp_0 > 4294967295ULL) {
        tmp_0 = 4294967295ULL;
      }

      rtb_Switch1 = (uint32_T)tmp_0;
    }

    /* End of Switch: '<S29>/Switch1' */

    /* Sum: '<S29>/Sum7' incorporates:
     *  Switch: '<S29>/Switch1'
     *  UnitDelay: '<S29>/UnitDelay4'
     */
    rtb_Switch3 = ((int32_T)(rtb_Switch1 >> 1) - (int32_T)
                   (rtDW->UnitDelay4_DSTATE_o >> 1)) >> 3;

    /* Abs: '<S29>/Abs2' */
    if (rtb_Switch3 < 0) {
      rtb_Switch3 = -rtb_Switch3;
    }

    /* End of Abs: '<S29>/Abs2' */

    /* Relay: '<S29>/dz_cntTrnsDet' */
    rtDW->dz_cntTrnsDet_Mode = ((rtb_Switch3 >= 140) || ((rtb_Switch3 > 100) &&
      rtDW->dz_cntTrnsDet_Mode));

    /* RelationalOperator: '<S29>/Relational Operator4' */
    rtb_RelationalOperator4_d = (rtDW->Switch2_o != rtDW->UnitDelay3);

    /* Switch: '<S29>/Switch3' incorporates:
     *  Constant: '<S29>/Constant4'
     *  Logic: '<S29>/Logical Operator1'
     *  Switch: '<S29>/Switch1'
     *  Switch: '<S29>/Switch2'
     *  UnitDelay: '<S29>/UnitDelay1'
     */
    if (rtb_RelationalOperator4_d && rtDW->UnitDelay1_DSTATE_m) {
      rtb_RelationalOperator4_b = 0;
    } else if (rtb_RelationalOperator4_d) {
      /* Switch: '<S29>/Switch2' incorporates:
       *  UnitDelay: '<S20>/UnitDelay4'
       */
      rtb_RelationalOperator4_b = (int32_T)rtDW->UnitDelay4_DSTATE;
    } else {
      rtb_RelationalOperator4_b = (int32_T)rtb_Switch1;
    }

    /* End of Switch: '<S29>/Switch3' */

    /* Product: '<S29>/Divide11' */
    rtDW->Divide11 = rtb_RelationalOperator4_b * rtDW->Switch2_o;

    /* Switch: '<S29>/Switch4' incorporates:
     *  UnitDelay: '<S29>/Unit Delay1'
     */
    if (rtDW->UnitDelay1_DSTATE_k != 0) {
      /* Switch: '<S29>/Switch4' incorporates:
       *  Product: '<S29>/Divide2'
       */
      rtDW->Switch4 = 62914560U / rtb_Merge;
    } else {
      /* Switch: '<S29>/Switch4' incorporates:
       *  Product: '<S29>/Divide1'
       *  Sum: '<S29>/Sum13'
       */
      rtDW->Switch4 = 251658240U / (uint32_T)tmp_1;
    }

    /* End of Switch: '<S29>/Switch4' */

    /* SignalConversion generated from: '<S29>/delta_count' */
    rtDW->OutportBufferFordelta_count = rtb_Merge;

    /* Update for UnitDelay: '<S29>/Unit Delay' */
    rtDW->UnitDelay_DSTATE = rtDW->i_count;

    /* Update for UnitDelay: '<S29>/UnitDelay2' incorporates:
     *  UnitDelay: '<S29>/UnitDelay3'
     */
    rtDW->UnitDelay2_DSTATE = rtDW->UnitDelay3_DSTATE;

    /* Update for UnitDelay: '<S29>/UnitDelay3' incorporates:
     *  UnitDelay: '<S29>/UnitDelay5'
     */
    rtDW->UnitDelay3_DSTATE = rtDW->UnitDelay5_DSTATE;

    /* Update for UnitDelay: '<S29>/UnitDelay5' */
    rtDW->UnitDelay5_DSTATE = rtb_Merge;

    /* Update for UnitDelay: '<S29>/Unit Delay1' incorporates:
     *  Relay: '<S29>/dz_cntTrnsDet'
     */
    rtDW->UnitDelay1_DSTATE_k = rtDW->dz_cntTrnsDet_Mode;

    /* Update for UnitDelay: '<S29>/UnitDelay4' incorporates:
     *  Switch: '<S29>/Switch1'
     */
    rtDW->UnitDelay4_DSTATE_o = rtb_Switch1;

    /* Update for UnitDelay: '<S29>/UnitDelay1' */
    rtDW->UnitDelay1_DSTATE_m = rtb_RelationalOperator4_d;

    /* End of Outputs for SubSystem: '<S20>/Raw_Motor_Speed_Estimation' */
  }

  /* End of If: '<S20>/If2' */

  /* Switch: '<S18>/Switch3' incorporates:
   *  Constant: '<S18>/Constant16'
   *  Constant: '<S18>/Constant2'
   *  Constant: '<S19>/vec_hallToPos'
   *  RelationalOperator: '<S18>/Relational Operator7'
   *  Selector: '<S19>/Selector'
   *  Sum: '<S18>/Sum1'
   */
  if (rtDW->Switch2_o == 1) {
    rtb_Sum2 = rtConstP.vec_hallToPos_Value[rtb_Add_h];
  } else {
    rtb_Sum2 = (int8_T)(rtConstP.vec_hallToPos_Value[rtb_Add_h] + 1);
  }

  /* End of Switch: '<S18>/Switch3' */

  /* Sum: '<S18>/Sum3' incorporates:
   *  Gain: '<S18>/Gain'
   *  Interpolation_n-D: '<S49>/r_cos_M1'
   *  Product: '<S18>/Divide1'
   *  Product: '<S18>/Divide3'
   *  Switch: '<S29>/Switch4'
   */
  rtb_r_cos_M1 = (int16_T)(((int16_T)((int16_T)(((int32_T)((2290649225ULL *
    rtDW->Switch4) >> 37) * (int32_T)rtb_Rem1) >> 6) * rtDW->Switch2_o) +
    (rtb_Sum2 << 14)) >> 2);

  /* MinMax: '<S18>/Max' incorporates:
   *  Constant: '<S18>/a_elecAngle2'
   *  Interpolation_n-D: '<S49>/r_cos_M1'
   */
  if (rtb_r_cos_M1 <= 0) {
    rtb_r_cos_M1 = 0;
  }

  /* End of MinMax: '<S18>/Max' */

  /* Sum: '<S22>/Add2' incorporates:
   *  Constant: '<S22>/Constant2'
   *  Product: '<S18>/Divide2'
   */
  rtb_Add2_lk = (int16_T)((((15 * rtb_r_cos_M1) >> 4) + (rtP.i_hall_offset << 2))
    >> 2);

  /* DataTypeConversion: '<S22>/Data Type Conversion' incorporates:
   *  Sum: '<S22>/Add2'
   */
  rtb_r_cos_M1 = (int16_T)(rtb_Add2_lk >> 4);

  /* If: '<S22>/If' incorporates:
   *  Constant: '<S22>/Constant1'
   *  Constant: '<S22>/Constant3'
   *  Inport: '<S25>/In1'
   *  Inport: '<S26>/In1'
   *  Inport: '<S27>/In1'
   *  Interpolation_n-D: '<S49>/r_cos_M1'
   *  Sum: '<S22>/Add'
   *  Sum: '<S22>/Add1'
   *  Sum: '<S22>/Add2'
   */
  if (rtb_r_cos_M1 >= 360) {
    /* Outputs for IfAction SubSystem: '<S22>/If Action Subsystem' incorporates:
     *  ActionPort: '<S25>/Action Port'
     */
    rtb_r_cos_M1 = (int16_T)(rtb_Add2_lk - 5760);

    /* End of Outputs for SubSystem: '<S22>/If Action Subsystem' */
  } else if (rtb_r_cos_M1 < 0) {
    /* Outputs for IfAction SubSystem: '<S22>/If Action Subsystem2' incorporates:
     *  ActionPort: '<S27>/Action Port'
     */
    rtb_r_cos_M1 = (int16_T)(rtb_Add2_lk + 5760);

    /* End of Outputs for SubSystem: '<S22>/If Action Subsystem2' */
  } else {
    /* Outputs for IfAction SubSystem: '<S22>/If Action Subsystem1' incorporates:
     *  ActionPort: '<S26>/Action Port'
     */
    rtb_r_cos_M1 = rtb_Add2_lk;

    /* End of Outputs for SubSystem: '<S22>/If Action Subsystem1' */
  }

  /* End of If: '<S22>/If' */

  /* Switch: '<S1>/Switch' incorporates:
   *  Inport: '<Root>/set_Angle'
   */
  if (rtU->set_Angle <= 5760) {
    rtb_r_cos_M1 = rtU->set_Angle;
  }

  /* End of Switch: '<S1>/Switch' */

  /* PreLookup: '<S49>/a_elecAngle_XA' incorporates:
   *  Switch: '<S1>/Switch'
   */
  rtb_Divide_d = plook_u16s16_evencka(rtb_r_cos_M1, 0, 16U, 360U);

  /* Sum: '<S46>/Add2' */
  tmp_2 = ((int64_T)rtb_Divide_e_idx_1 - rtb_Divide_e_idx_2) >> 9;
  if (tmp_2 > 32767LL) {
    tmp_2 = 32767LL;
  } else {
    if (tmp_2 < -32768LL) {
      tmp_2 = -32768LL;
    }
  }

  /* Gain: '<S46>/Gain2' incorporates:
   *  Sum: '<S46>/Add2'
   *  Sum: '<S48>/Sum6'
   */
  rtb_Add2_lk = (int16_T)((18919 * (int16_T)tmp_2) >> 15);

  /* Sum: '<S48>/Sum1' incorporates:
   *  Interpolation_n-D: '<S49>/r_cos_M1'
   *  Interpolation_n-D: '<S49>/r_sin_M1'
   *  Product: '<S48>/Divide1'
   *  Product: '<S48>/Divide2'
   *  Product: '<S48>/Divide3'
   *  Sum: '<S48>/Sum6'
   */
  rtb_RelationalOperator4_b = ((rtb_Divide1_oy * rtConstP.pooled13[rtb_Divide_d])
    >> 14) + (int16_T)((rtb_Add2_lk * rtConstP.pooled12[rtb_Divide_d]) >> 14);
  if (rtb_RelationalOperator4_b > 32767) {
    rtb_RelationalOperator4_b = 32767;
  } else {
    if (rtb_RelationalOperator4_b < -32768) {
      rtb_RelationalOperator4_b = -32768;
    }
  }

  /* SignalConversion generated from: '<S39>/Low_Pass_Filter' incorporates:
   *  Sum: '<S48>/Sum1'
   */
  rtb_TmpSignalConversionAtLow_Pass_FilterInport1[0] = (int16_T)
    rtb_RelationalOperator4_b;

  /* Sum: '<S48>/Sum6' incorporates:
   *  Interpolation_n-D: '<S49>/r_cos_M1'
   *  Interpolation_n-D: '<S49>/r_sin_M1'
   *  Product: '<S48>/Divide1'
   *  Product: '<S48>/Divide4'
   */
  rtb_RelationalOperator4_b = (int16_T)((rtb_Add2_lk *
    rtConstP.pooled13[rtb_Divide_d]) >> 14) - ((rtb_Divide1_oy *
    rtConstP.pooled12[rtb_Divide_d]) >> 14);
  if (rtb_RelationalOperator4_b > 32767) {
    rtb_RelationalOperator4_b = 32767;
  } else {
    if (rtb_RelationalOperator4_b < -32768) {
      rtb_RelationalOperator4_b = -32768;
    }
  }

  /* SignalConversion generated from: '<S39>/Low_Pass_Filter' incorporates:
   *  Sum: '<S48>/Sum6'
   */
  rtb_TmpSignalConversionAtLow_Pass_FilterInport1[1] = (int16_T)
    rtb_RelationalOperator4_b;

  /* Outputs for Atomic SubSystem: '<S39>/Low_Pass_Filter' */
  /* Constant: '<S39>/Constant' incorporates:
   *  Outport: '<Root>/f_Idq'
   */
  Low_Pass_Filter(rtb_TmpSignalConversionAtLow_Pass_FilterInport1, rtP.f_lpf_idq,
                  rtY->f_Idq, &rtDW->Low_Pass_Filter_l);

  /* End of Outputs for SubSystem: '<S39>/Low_Pass_Filter' */

  /* UnitDelay: '<S5>/UnitDelay' */
  rtb_UnitDelay_n = rtDW->UnitDelay_DSTATE_p;

  /* Switch: '<S20>/Switch2' incorporates:
   *  Constant: '<S20>/Constant4'
   *  Constant: '<S20>/z_maxCntRst'
   *  Gain: '<S20>/Gain'
   *  Product: '<S29>/Divide11'
   *  RelationalOperator: '<S20>/Relational Operator2'
   */
  if (rtDW->OutportBufferFordelta_count >= 2000000U) {
    rtb_Switch3 = 0;
  } else {
    rtb_Switch3 = rtDW->Divide11;
  }

  /* End of Switch: '<S20>/Switch2' */

  /* Abs: '<S20>/Abs5' incorporates:
   *  Switch: '<S20>/Switch2'
   */
  if (rtb_Switch3 < 0) {
    rtb_Rem1 = (uint32_T)-rtb_Switch3;
  } else {
    rtb_Rem1 = (uint32_T)rtb_Switch3;
  }

  /* End of Abs: '<S20>/Abs5' */

  /* Outport: '<Root>/f_Vdq' incorporates:
   *  UnitDelay: '<S1>/Unit Delay'
   */
  rtY->f_Vdq[0] = rtDW->UnitDelay_DSTATE_k[0];
  rtY->f_Vdq[1] = rtDW->UnitDelay_DSTATE_k[1];

  /* Switch: '<S5>/Switch3' incorporates:
   *  Abs: '<S20>/Abs5'
   *  Abs: '<S5>/Abs4'
   *  Constant: '<S5>/CTRL_COMM4'
   *  Inport: '<Root>/b_motEna'
   *  Logic: '<S5>/Logical Operator1'
   *  RelationalOperator: '<S20>/Relational Operator9'
   *  RelationalOperator: '<S5>/Relational Operator7'
   *  S-Function (sfix_bitop): '<S5>/Bitwise Operator1'
   *  UnitDelay: '<S1>/Unit Delay'
   */
  if ((rtb_UnitDelay_n & 4U) != 0U) {
    rtb_UnitDelay_c = true;
  } else {
    if (rtDW->UnitDelay_DSTATE_k[1] < 0) {
      /* Abs: '<S5>/Abs4' incorporates:
       *  UnitDelay: '<S1>/Unit Delay'
       */
      rtb_Switch2_pl = (int16_T)-rtDW->UnitDelay_DSTATE_k[1];
    } else {
      /* Abs: '<S5>/Abs4' incorporates:
       *  UnitDelay: '<S1>/Unit Delay'
       */
      rtb_Switch2_pl = rtDW->UnitDelay_DSTATE_k[1];
    }

    rtb_UnitDelay_c = (rtU->b_motEna && (rtb_Rem1 < 48U) && (rtb_Switch2_pl >
      9920));
  }

  /* End of Switch: '<S5>/Switch3' */

  /* Sum: '<S5>/Sum' incorporates:
   *  Constant: '<S5>/CTRL_COMM'
   *  Constant: '<S5>/CTRL_COMM1'
   *  DataTypeConversion: '<S5>/Data Type Conversion3'
   *  Gain: '<S5>/g_Hb'
   *  Gain: '<S5>/g_Hb1'
   *  RelationalOperator: '<S5>/Relational Operator1'
   *  RelationalOperator: '<S5>/Relational Operator3'
   */
  rtb_Sum_d = (uint8_T)(((uint32_T)((rtb_Add_h == 7) << 1) + (rtb_Add_h == 0)) +
                        (rtb_UnitDelay_c << 2));

  /* RelationalOperator: '<S5>/Relational Operator2' incorporates:
   *  Constant: '<S5>/CTRL_COMM2'
   */
  rtb_RelationalOperator4_d = (rtb_Sum_d != 0);

  /* RelationalOperator: '<S10>/Relational Operator' incorporates:
   *  UnitDelay: '<S10>/UnitDelay'
   */
  rtb_RelationalOperator = (rtb_RelationalOperator4_d !=
    rtDW->UnitDelay_DSTATE_oy);

  /* If: '<S6>/If2' incorporates:
   *  Inport: '<S8>/yPrev'
   *  Logic: '<S6>/Logical Operator1'
   *  Logic: '<S6>/Logical Operator2'
   *  Logic: '<S6>/Logical Operator3'
   *  Logic: '<S6>/Logical Operator4'
   *  UnitDelay: '<S6>/UnitDelay'
   */
  if (rtb_RelationalOperator4_d && (!rtDW->UnitDelay_DSTATE_gv)) {
    /* Outputs for IfAction SubSystem: '<S6>/Qualification' incorporates:
     *  ActionPort: '<S11>/Action Port'
     */
    /* Switch: '<S15>/Switch1' incorporates:
     *  Constant: '<S15>/Constant23'
     *  UnitDelay: '<S15>/UnitDelay'
     */
    if (rtb_RelationalOperator) {
      rtb_Sum1_p = 0U;
    } else {
      rtb_Sum1_p = rtDW->UnitDelay_DSTATE_m;
    }

    /* End of Switch: '<S15>/Switch1' */

    /* Switch: '<S11>/Switch2' incorporates:
     *  Constant: '<S11>/Constant6'
     *  Constant: '<S5>/t_errQual'
     *  RelationalOperator: '<S11>/Relational Operator2'
     *  Sum: '<S14>/Sum1'
     */
    rtb_RelationalOperator = (((uint16_T)(rtb_Sum1_p + 1U) > 1600) ||
      rtDW->UnitDelay_DSTATE_gv);

    /* MinMax: '<S14>/MinMax' incorporates:
     *  Constant: '<S11>/Constant6'
     *  Sum: '<S14>/Sum1'
     */
    if ((uint16_T)(rtb_Sum1_p + 1U) < 1600) {
      /* Update for UnitDelay: '<S15>/UnitDelay' */
      rtDW->UnitDelay_DSTATE_m = (uint16_T)(rtb_Sum1_p + 1U);
    } else {
      /* Update for UnitDelay: '<S15>/UnitDelay' */
      rtDW->UnitDelay_DSTATE_m = 1600U;
    }

    /* End of MinMax: '<S14>/MinMax' */
    /* End of Outputs for SubSystem: '<S6>/Qualification' */
  } else if ((!rtb_RelationalOperator4_d) && rtDW->UnitDelay_DSTATE_gv) {
    /* Outputs for IfAction SubSystem: '<S6>/Dequalification' incorporates:
     *  ActionPort: '<S9>/Action Port'
     */
    /* Switch: '<S13>/Switch1' incorporates:
     *  Constant: '<S13>/Constant23'
     *  UnitDelay: '<S13>/UnitDelay'
     */
    if (rtb_RelationalOperator) {
      rtb_Sum1_p = 0U;
    } else {
      rtb_Sum1_p = rtDW->UnitDelay_DSTATE_i;
    }

    /* End of Switch: '<S13>/Switch1' */

    /* Switch: '<S9>/Switch2' incorporates:
     *  Constant: '<S5>/t_errDequal'
     *  Constant: '<S9>/Constant6'
     *  RelationalOperator: '<S9>/Relational Operator2'
     *  Sum: '<S12>/Sum1'
     */
    rtb_RelationalOperator = (((uint16_T)(rtb_Sum1_p + 1U) <= 12000) &&
      rtDW->UnitDelay_DSTATE_gv);

    /* MinMax: '<S12>/MinMax' incorporates:
     *  Constant: '<S9>/Constant6'
     *  Sum: '<S12>/Sum1'
     */
    if ((uint16_T)(rtb_Sum1_p + 1U) < 12000) {
      /* Update for UnitDelay: '<S13>/UnitDelay' */
      rtDW->UnitDelay_DSTATE_i = (uint16_T)(rtb_Sum1_p + 1U);
    } else {
      /* Update for UnitDelay: '<S13>/UnitDelay' */
      rtDW->UnitDelay_DSTATE_i = 12000U;
    }

    /* End of MinMax: '<S12>/MinMax' */
    /* End of Outputs for SubSystem: '<S6>/Dequalification' */
  } else {
    /* Outputs for IfAction SubSystem: '<S6>/Default' incorporates:
     *  ActionPort: '<S8>/Action Port'
     */
    rtb_RelationalOperator = rtDW->UnitDelay_DSTATE_gv;

    /* End of Outputs for SubSystem: '<S6>/Default' */
  }

  /* End of If: '<S6>/If2' */

  /* Logic: '<S1>/Logical Operator1' incorporates:
   *  Inport: '<Root>/b_motEna'
   *  Logic: '<S1>/Logical Operator'
   */
  rtb_LogicalOperator1_g = ((!rtb_RelationalOperator) && rtU->b_motEna);

  /* Logic: '<S36>/Logical Operator4' incorporates:
   *  Constant: '<S36>/constant8'
   *  Inport: '<Root>/n_ctrlMod'
   *  Logic: '<S36>/Logical Operator11'
   *  RelationalOperator: '<S36>/Relational Operator10'
   */
  rtb_LogicalOperator4_f = ((!rtb_LogicalOperator1_g) || (rtU->n_ctrlMod == 0));

  /* Abs: '<S36>/Abs' incorporates:
   *  Gain: '<S53>/Gain'
   *  Switch: '<S20>/Switch2'
   */
  if (rtb_Switch3 < 0) {
    rtb_Gain_b = -rtb_Switch3;
  } else {
    rtb_Gain_b = rtb_Switch3;
  }

  /* End of Abs: '<S36>/Abs' */

  /* Relay: '<S36>/n_SpeedCtrl' incorporates:
   *  Gain: '<S53>/Gain'
   */
  rtDW->n_SpeedCtrl_Mode = ((rtb_Gain_b >= 4800) || ((rtb_Gain_b > 3200) &&
    rtDW->n_SpeedCtrl_Mode));

  /* Logic: '<S36>/Logical Operator10' incorporates:
   *  Inport: '<Root>/b_cruiseEna'
   *  Relay: '<S36>/n_SpeedCtrl'
   */
  rtb_UnitDelay_c = (rtDW->n_SpeedCtrl_Mode && rtU->b_cruiseEna);

  /* Logic: '<S36>/Logical Operator2' incorporates:
   *  Constant: '<S36>/constant'
   *  Inport: '<Root>/n_ctrlMod'
   *  Logic: '<S36>/Logical Operator5'
   *  RelationalOperator: '<S36>/Relational Operator4'
   */
  rtb_LogicalOperator2_c = ((rtU->n_ctrlMod == 2) && (!rtb_UnitDelay_c));

  /* Logic: '<S36>/Logical Operator1' incorporates:
   *  Constant: '<S36>/constant1'
   *  Inport: '<Root>/n_ctrlMod'
   *  RelationalOperator: '<S36>/Relational Operator1'
   */
  rtb_UnitDelay_c = ((rtU->n_ctrlMod == 1) || rtb_UnitDelay_c);

  /* Chart: '<S36>/Control_Mode_Manager' incorporates:
   *  Logic: '<S36>/Logical Operator3'
   *  Logic: '<S36>/Logical Operator6'
   *  Logic: '<S36>/Logical Operator9'
   */
  if (rtDW->is_active_c11_PMSM_Controller == 0U) {
    rtDW->is_active_c11_PMSM_Controller = 1U;
    rtDW->is_c11_PMSM_Controller = IN_OPEN;
    rtb_dz_cntTrnsDet = OPEN_MODE;
  } else if (rtDW->is_c11_PMSM_Controller == 1) {
    if (rtb_LogicalOperator4_f) {
      rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD;
      rtDW->is_c11_PMSM_Controller = IN_OPEN;
      rtb_dz_cntTrnsDet = OPEN_MODE;
    } else if (rtDW->is_ACTIVE == 1) {
      rtb_dz_cntTrnsDet = SPD_MODE;
      if (!rtb_UnitDelay_c) {
        if (rtb_LogicalOperator2_c) {
          rtDW->is_ACTIVE = IN_TORQUE_MODE;
          rtb_dz_cntTrnsDet = TRQ_MODE;
        } else {
          rtDW->is_ACTIVE = IN_SPEED_MODE;
        }
      }
    } else {
      /* case IN_TORQUE_MODE: */
      rtb_dz_cntTrnsDet = TRQ_MODE;
      if (!rtb_LogicalOperator2_c) {
        rtDW->is_ACTIVE = IN_SPEED_MODE;
        rtb_dz_cntTrnsDet = SPD_MODE;
      }
    }
  } else {
    /* case IN_OPEN: */
    rtb_dz_cntTrnsDet = OPEN_MODE;
    if ((!rtb_LogicalOperator4_f) && (rtb_LogicalOperator2_c || rtb_UnitDelay_c))
    {
      rtDW->is_c11_PMSM_Controller = IN_ACTIVE;
      if (rtb_LogicalOperator2_c) {
        rtDW->is_ACTIVE = IN_TORQUE_MODE;
        rtb_dz_cntTrnsDet = TRQ_MODE;
      } else {
        rtDW->is_ACTIVE = IN_SPEED_MODE;
        rtb_dz_cntTrnsDet = SPD_MODE;
      }
    }
  }

  /* End of Chart: '<S36>/Control_Mode_Manager' */

  /* UnitDelay: '<S35>/UnitDelay1' */
  rtb_UnitDelay1_ko[0] = rtDW->UnitDelay1_DSTATE_o[0];
  rtb_UnitDelay1_ko[1] = rtDW->UnitDelay1_DSTATE_o[1];

  /* Switch: '<S50>/Switch2' incorporates:
   *  Inport: '<Root>/spd_Limit'
   *  Inport: '<Root>/spd_Target'
   *  RelationalOperator: '<S50>/LowerRelop1'
   *  RelationalOperator: '<S50>/UpperRelop'
   *  Switch: '<S50>/Switch'
   */
  if (rtU->spd_Target > rtU->spd_Limit) {
    rtb_Switch2_au = rtU->spd_Limit;
  } else if (rtU->spd_Target < 0) {
    /* Switch: '<S50>/Switch' incorporates:
     *  Constant: '<S40>/Constant'
     *  Switch: '<S50>/Switch2'
     */
    rtb_Switch2_au = 0;
  } else {
    rtb_Switch2_au = rtU->spd_Target;
  }

  /* End of Switch: '<S50>/Switch2' */

  /* Switch: '<S51>/Switch2' incorporates:
   *  Inport: '<Root>/idq_Limit'
   *  Inport: '<Root>/idq_Target'
   *  RelationalOperator: '<S51>/LowerRelop1'
   */
  if (rtU->idq_Target > rtU->idq_Limit) {
    rtb_Divide1_oy = rtU->idq_Limit;
  } else {
    /* Gain: '<S40>/Gain' */
    rtb_Gain_ib = -32768 * rtU->idq_Limit;

    /* Switch: '<S51>/Switch' incorporates:
     *  Gain: '<S40>/Gain'
     *  RelationalOperator: '<S51>/UpperRelop'
     *  Switch: '<S51>/Switch2'
     */
    if ((rtU->idq_Target << 15) < rtb_Gain_ib) {
      rtb_Divide1_oy = (int16_T)(rtb_Gain_ib >> 15);
    } else {
      rtb_Divide1_oy = rtU->idq_Target;
    }

    /* End of Switch: '<S51>/Switch' */
  }

  /* End of Switch: '<S51>/Switch2' */

  /* Sum: '<S38>/Sum3' incorporates:
   *  UnitDelay: '<S38>/UnitDelay1'
   */
  rtb_Merge = rtDW->UnitDelay1_DSTATE + /*MW:OvSatOk*/ 1U;
  if (rtDW->UnitDelay1_DSTATE + 1U < 1U) {
    rtb_Merge = MAX_uint32_T;
  }

  /* If: '<S37>/If' incorporates:
   *  Constant: '<S34>/Constant2'
   *  Logic: '<S37>/Logical Operator'
   *  Math: '<S34>/Rem1'
   *  RelationalOperator: '<S34>/Equal1'
   *  RelationalOperator: '<S37>/Equal'
   *  Sum: '<S38>/Sum3'
   */
  if ((rtb_dz_cntTrnsDet == 0) && (rtb_Merge % 200U == 0U)) {
    /* Outputs for IfAction SubSystem: '<S37>/open_mode' incorporates:
     *  ActionPort: '<S111>/Action Port'
     */
    /* RelationalOperator: '<S112>/Relational Operator' incorporates:
     *  Inport: '<Root>/vdq_Target'
     *  UnitDelay: '<S112>/UnitDelay'
     */
    rtb_UnitDelay_c = (rtU->vdq_Target[0] != rtDW->UnitDelay_DSTATE_lz);

    /* If: '<S113>/If' incorporates:
     *  Constant: '<S111>/Constant1'
     *  Inport: '<Root>/vdq_Target'
     *  UnitDelay: '<S4>/Unit Delay'
     */
    if (rtb_UnitDelay_c) {
      /* Outputs for IfAction SubSystem: '<S113>/RateInit' incorporates:
       *  ActionPort: '<S116>/Action Port'
       */
      RateInit_a(rtDW->UnitDelay_DSTATE_e[0], rtU->vdq_Target[0],
                 rtP.dz_OpenStepVol, &rtDW->Divide_o, &rtDW->Max_l,
                 &rtDW->Max1_j);

      /* End of Outputs for SubSystem: '<S113>/RateInit' */

      /* Switch: '<S119>/Switch1' incorporates:
       *  Constant: '<S111>/Constant1'
       *  Inport: '<Root>/vdq_Target'
       *  UnitDelay: '<S4>/Unit Delay'
       */
      rtb_Sum6 = rtDW->UnitDelay_DSTATE_e[0];
    } else {
      /* Switch: '<S119>/Switch1' incorporates:
       *  UnitDelay: '<S119>/UnitDelay'
       */
      rtb_Sum6 = rtDW->UnitDelay_DSTATE_j;
    }

    /* End of If: '<S113>/If' */

    /* Switch: '<S113>/Switch' incorporates:
     *  Constant: '<S113>/Constant'
     *  Inport: '<Root>/vdq_Target'
     *  Product: '<S116>/Divide'
     *  RelationalOperator: '<S113>/Equal'
     *  UnitDelay: '<S113>/Unit Delay'
     */
    if (rtU->vdq_Target[0] != rtDW->UnitDelay_DSTATE_h) {
      rtb_Switch2_pl = rtDW->Divide_o;
    } else {
      rtb_Switch2_pl = 0;
    }

    /* End of Switch: '<S113>/Switch' */

    /* Sum: '<S118>/Add2' */
    rtb_RelationalOperator4_b = ((rtb_Sum6 << 2) + rtb_Switch2_pl) >> 2;
    if (rtb_RelationalOperator4_b > 32767) {
      rtb_RelationalOperator4_b = 32767;
    } else {
      if (rtb_RelationalOperator4_b < -32768) {
        rtb_RelationalOperator4_b = -32768;
      }
    }

    /* Switch: '<S117>/Switch2' incorporates:
     *  MinMax: '<S116>/Max'
     *  MinMax: '<S116>/Max1'
     *  RelationalOperator: '<S117>/LowerRelop1'
     *  RelationalOperator: '<S117>/UpperRelop'
     *  Sum: '<S118>/Add2'
     *  Switch: '<S117>/Switch'
     */
    if ((int16_T)rtb_RelationalOperator4_b > rtDW->Max_l) {
      rtb_Add2_lk = rtDW->Max_l;
    } else if ((int16_T)rtb_RelationalOperator4_b < rtDW->Max1_j) {
      /* Switch: '<S117>/Switch' incorporates:
       *  MinMax: '<S116>/Max1'
       *  Switch: '<S117>/Switch2'
       */
      rtb_Add2_lk = rtDW->Max1_j;
    } else {
      rtb_Add2_lk = (int16_T)rtb_RelationalOperator4_b;
    }

    /* End of Switch: '<S117>/Switch2' */

    /* RelationalOperator: '<S114>/Relational Operator' incorporates:
     *  Inport: '<Root>/vdq_Target'
     *  UnitDelay: '<S114>/UnitDelay'
     */
    rtb_LogicalOperator4_f = (rtU->vdq_Target[1] != rtDW->UnitDelay_DSTATE_n);

    /* If: '<S115>/If' incorporates:
     *  Constant: '<S111>/Constant5'
     *  Inport: '<Root>/vdq_Target'
     *  UnitDelay: '<S4>/Unit Delay'
     */
    if (rtb_LogicalOperator4_f) {
      /* Outputs for IfAction SubSystem: '<S115>/RateInit' incorporates:
       *  ActionPort: '<S120>/Action Port'
       */
      RateInit_a(rtDW->UnitDelay_DSTATE_e[1], rtU->vdq_Target[1],
                 rtP.dz_OpenStepVol, &rtDW->Divide, &rtDW->Max, &rtDW->Max1);

      /* End of Outputs for SubSystem: '<S115>/RateInit' */

      /* Switch: '<S123>/Switch1' incorporates:
       *  Constant: '<S111>/Constant5'
       *  Inport: '<Root>/vdq_Target'
       *  UnitDelay: '<S4>/Unit Delay'
       */
      rtb_Sum6 = rtDW->UnitDelay_DSTATE_e[1];
    } else {
      /* Switch: '<S123>/Switch1' incorporates:
       *  UnitDelay: '<S123>/UnitDelay'
       */
      rtb_Sum6 = rtDW->UnitDelay_DSTATE_ox;
    }

    /* End of If: '<S115>/If' */

    /* Switch: '<S115>/Switch' incorporates:
     *  Constant: '<S115>/Constant'
     *  Inport: '<Root>/vdq_Target'
     *  Product: '<S120>/Divide'
     *  RelationalOperator: '<S115>/Equal'
     *  UnitDelay: '<S115>/Unit Delay'
     */
    if (rtU->vdq_Target[1] != rtDW->UnitDelay_DSTATE_gt) {
      rtb_Switch2_pl = rtDW->Divide;
    } else {
      rtb_Switch2_pl = 0;
    }

    /* End of Switch: '<S115>/Switch' */

    /* Sum: '<S122>/Add2' */
    rtb_Divide_e_idx_1 = ((rtb_Sum6 << 2) + rtb_Switch2_pl) >> 2;
    if (rtb_Divide_e_idx_1 > 32767) {
      rtb_Divide_e_idx_1 = 32767;
    } else {
      if (rtb_Divide_e_idx_1 < -32768) {
        rtb_Divide_e_idx_1 = -32768;
      }
    }

    /* Switch: '<S121>/Switch2' incorporates:
     *  MinMax: '<S120>/Max'
     *  MinMax: '<S120>/Max1'
     *  RelationalOperator: '<S121>/LowerRelop1'
     *  RelationalOperator: '<S121>/UpperRelop'
     *  Sum: '<S122>/Add2'
     *  Switch: '<S121>/Switch'
     */
    if ((int16_T)rtb_Divide_e_idx_1 > rtDW->Max) {
      rtb_Switch2_pl = rtDW->Max;
    } else if ((int16_T)rtb_Divide_e_idx_1 < rtDW->Max1) {
      /* Switch: '<S121>/Switch' incorporates:
       *  MinMax: '<S120>/Max1'
       *  Switch: '<S121>/Switch2'
       */
      rtb_Switch2_pl = rtDW->Max1;
    } else {
      rtb_Switch2_pl = (int16_T)rtb_Divide_e_idx_1;
    }

    /* End of Switch: '<S121>/Switch2' */

    /* Switch: '<S111>/Switch' */
    if (rtb_LogicalOperator1_g) {
      /* Switch: '<S111>/Switch' */
      rtDW->Switch[0] = rtb_Add2_lk;
      rtDW->Switch[1] = rtb_Switch2_pl;
    } else {
      /* Switch: '<S111>/Switch' incorporates:
       *  Constant: '<S111>/Constant2'
       */
      rtDW->Switch[0] = 0;
      rtDW->Switch[1] = 0;
    }

    /* End of Switch: '<S111>/Switch' */

    /* Update for UnitDelay: '<S112>/UnitDelay' incorporates:
     *  Inport: '<Root>/vdq_Target'
     */
    rtDW->UnitDelay_DSTATE_lz = rtU->vdq_Target[0];

    /* Switch: '<S119>/Switch2' */
    if (rtb_UnitDelay_c) {
      /* Update for UnitDelay: '<S119>/UnitDelay' incorporates:
       *  UnitDelay: '<S4>/Unit Delay'
       */
      rtDW->UnitDelay_DSTATE_j = rtDW->UnitDelay_DSTATE_e[0];
    } else {
      /* Update for UnitDelay: '<S119>/UnitDelay' incorporates:
       *  Sum: '<S118>/Add2'
       */
      rtDW->UnitDelay_DSTATE_j = (int16_T)rtb_RelationalOperator4_b;
    }

    /* End of Switch: '<S119>/Switch2' */

    /* Update for UnitDelay: '<S113>/Unit Delay' incorporates:
     *  Switch: '<S117>/Switch2'
     */
    rtDW->UnitDelay_DSTATE_h = rtb_Add2_lk;

    /* Update for UnitDelay: '<S114>/UnitDelay' incorporates:
     *  Inport: '<Root>/vdq_Target'
     */
    rtDW->UnitDelay_DSTATE_n = rtU->vdq_Target[1];

    /* Switch: '<S123>/Switch2' */
    if (rtb_LogicalOperator4_f) {
      /* Update for UnitDelay: '<S123>/UnitDelay' incorporates:
       *  UnitDelay: '<S4>/Unit Delay'
       */
      rtDW->UnitDelay_DSTATE_ox = rtDW->UnitDelay_DSTATE_e[1];
    } else {
      /* Update for UnitDelay: '<S123>/UnitDelay' incorporates:
       *  Sum: '<S122>/Add2'
       */
      rtDW->UnitDelay_DSTATE_ox = (int16_T)rtb_Divide_e_idx_1;
    }

    /* End of Switch: '<S123>/Switch2' */

    /* Update for UnitDelay: '<S115>/Unit Delay' incorporates:
     *  Switch: '<S121>/Switch2'
     */
    rtDW->UnitDelay_DSTATE_gt = rtb_Switch2_pl;

    /* End of Outputs for SubSystem: '<S37>/open_mode' */
  }

  /* End of If: '<S37>/If' */

  /* If: '<S44>/If' incorporates:
   *  Constant: '<S34>/Constant1'
   *  Constant: '<S68>/Constant'
   *  Logic: '<S63>/Logical Operator'
   *  Math: '<S34>/Rem'
   *  RelationalOperator: '<S34>/Equal'
   *  Sum: '<S38>/Sum3'
   *  Switch: '<S63>/Switch2'
   */
  rtb_Sum2 = -1;
  if ((rtb_dz_cntTrnsDet != 0) && (rtb_Merge % 40U == 0U)) {
    rtb_Sum2 = 0;

    /* Outputs for IfAction SubSystem: '<S44>/Do_Calc' incorporates:
     *  ActionPort: '<S62>/Action Port'
     */
    /* Outputs for Atomic SubSystem: '<S68>/Low_Pass_Filter' */
    Low_Pass_Filter(rtb_UnitDelay1_ko, rtP.f_lpf_vdq,
                    rtb_TmpSignalConversionAtLow_Pass_FilterInport1,
                    &rtDW->Low_Pass_Filter_e);

    /* End of Outputs for SubSystem: '<S68>/Low_Pass_Filter' */

    /* DataTypeConversion: '<S62>/Data Type Conversion' incorporates:
     *  Constant: '<S68>/Constant'
     *  RelationalOperator: '<S62>/Equal'
     *  UnitDelay: '<S62>/Unit Delay'
     */
    rtb_DataTypeConversion_e = (uint8_T)(rtDW->UnitDelay_DSTATE_lv !=
      rtb_dz_cntTrnsDet);

    /* If: '<S65>/If' incorporates:
     *  Constant: '<S79>/Constant1'
     *  Constant: '<S79>/Constant11'
     *  Constant: '<S79>/Constant4'
     *  Gain: '<S62>/Gain'
     *  Sum: '<S79>/Sum1'
     *  Switch: '<S20>/Switch2'
     *  Switch: '<S50>/Switch2'
     *  UnitDelay: '<S62>/Unit Delay1'
     */
    if (rtb_dz_cntTrnsDet == 1) {
      rtDW->If_ActiveSubsystem_k = 0;

      /* Outputs for IfAction SubSystem: '<S65>/speed_mode' incorporates:
       *  ActionPort: '<S79>/Action Port'
       */
      /* MinMax: '<S79>/Min' incorporates:
       *  Constant: '<S79>/Constant6'
       *  UnitDelay: '<S79>/Unit Delay'
       */
      if (rtP.i_dqMax < rtDW->UnitDelay_DSTATE_di) {
        rtb_Switch2_pl = rtP.i_dqMax;
      } else {
        rtb_Switch2_pl = rtDW->UnitDelay_DSTATE_di;
      }

      /* End of MinMax: '<S79>/Min' */

      /* MinMax: '<S79>/Min1' incorporates:
       *  Constant: '<S79>/Constant6'
       *  Gain: '<S79>/Gain'
       *  Gain: '<S79>/Gain1'
       *  UnitDelay: '<S79>/Unit Delay'
       */
      if ((int16_T)-rtDW->UnitDelay_DSTATE_di > (int16_T)-rtP.i_dqMax) {
        rtb_Gain_a = (int16_T)-rtDW->UnitDelay_DSTATE_di;
      } else {
        rtb_Gain_a = (int16_T)-rtP.i_dqMax;
      }

      /* End of MinMax: '<S79>/Min1' */

      /* Outputs for Atomic SubSystem: '<S79>/PI_Speed' */
      rtb_Gain_h = PI_backCalc_fixdt(rtb_Switch2_au - rtb_Switch3, rtP.cf_nKp,
        rtP.cf_nKi, rtP.cf_nKb, rtb_Switch2_pl, rtb_Gain_a, (int16_T)
        ((rtP.cf_lastIqGain * rtDW->UnitDelay1_DSTATE_jp) >> 15),
        rtb_DataTypeConversion_e, &rtDW->PI_Speed, &rtPrevZCX->PI_Speed);

      /* End of Outputs for SubSystem: '<S79>/PI_Speed' */

      /* Merge: '<S65>/Merge' incorporates:
       *  Constant: '<S79>/Constant1'
       *  Constant: '<S79>/Constant11'
       *  Constant: '<S79>/Constant4'
       *  DataTypeConversion: '<S79>/Data Type Conversion'
       *  Gain: '<S62>/Gain'
       *  Sum: '<S79>/Sum1'
       *  Switch: '<S20>/Switch2'
       *  Switch: '<S50>/Switch2'
       *  Switch: '<S83>/Switch2'
       *  UnitDelay: '<S62>/Unit Delay1'
       */
      rtDW->Merge = (int16_T)(rtb_Gain_h >> 9);

      /* End of Outputs for SubSystem: '<S65>/speed_mode' */
    } else {
      rtDW->If_ActiveSubsystem_k = 1;

      /* Outputs for IfAction SubSystem: '<S65>/torque_mode' incorporates:
       *  ActionPort: '<S80>/Action Port'
       */
      /* Delay: '<S80>/Delay' incorporates:
       *  Switch: '<S51>/Switch2'
       */
      if (rtDW->icLoad_i != 0) {
        rtDW->Delay_DSTATE = rtb_Divide1_oy;
      }

      /* Switch: '<S84>/Switch2' incorporates:
       *  Delay: '<S80>/Delay'
       *  RelationalOperator: '<S84>/LowerRelop1'
       *  Switch: '<S51>/Switch2'
       */
      if (rtb_Divide1_oy > rtDW->Delay_DSTATE) {
        /* Merge: '<S65>/Merge' */
        rtDW->Merge = rtDW->Delay_DSTATE;
      } else {
        /* Gain: '<S80>/Gain' */
        rtb_Gain_h = -32768 * rtDW->Delay_DSTATE;

        /* Switch: '<S84>/Switch' incorporates:
         *  Gain: '<S80>/Gain'
         *  RelationalOperator: '<S84>/UpperRelop'
         */
        if ((rtb_Divide1_oy << 15) < rtb_Gain_h) {
          /* Merge: '<S65>/Merge' */
          rtDW->Merge = (int16_T)(rtb_Gain_h >> 15);
        } else {
          /* Merge: '<S65>/Merge' */
          rtDW->Merge = rtb_Divide1_oy;
        }

        /* End of Switch: '<S84>/Switch' */
      }

      /* End of Switch: '<S84>/Switch2' */
      /* End of Outputs for SubSystem: '<S65>/torque_mode' */
    }

    /* End of If: '<S65>/If' */

    /* Outputs for IfAction SubSystem: '<S67>/MTPA_Calc' incorporates:
     *  ActionPort: '<S72>/Action Port'
     */
    /* If: '<S67>/If' incorporates:
     *  Constant: '<S72>/Constant3'
     *  Merge: '<S67>/Merge'
     *  Switch: '<S72>/Switch'
     */
    rtDW->Merge_i[0] = 0;
    rtDW->Merge_i[1] = rtDW->Merge;

    /* End of Outputs for SubSystem: '<S67>/MTPA_Calc' */

    /* Sum: '<S66>/Sum' incorporates:
     *  Constant: '<S66>/Constant3'
     *  UnitDelay: '<S66>/Unit Delay1'
     */
    rtb_RelationalOperator4_b = (rtP.V_modulation - rtDW->UnitDelay1_DSTATE_pl) >>
      1;
    if (rtb_RelationalOperator4_b < -32768) {
      rtb_RelationalOperator4_b = -32768;
    }

    /* Delay: '<S70>/Resettable Delay' incorporates:
     *  Constant: '<S66>/Constant4'
     *  DataTypeConversion: '<S70>/Data Type Conversion2'
     */
    if ((rtb_DataTypeConversion_e > 0) &&
        (rtPrevZCX->ResettableDelay_Reset_ZCE_f != 1)) {
      rtDW->icLoad = 1U;
    }

    rtPrevZCX->ResettableDelay_Reset_ZCE_f = (ZCSigState)
      (rtb_DataTypeConversion_e > 0);
    if (rtDW->icLoad != 0) {
      rtDW->ResettableDelay_DSTATE = 0;
    }

    /* Signum: '<S66>/Sign' incorporates:
     *  Sum: '<S66>/Sum'
     */
    if ((int16_T)rtb_RelationalOperator4_b < 0) {
      rtb_Switch2_pl = -1;
    } else {
      rtb_Switch2_pl = (int16_T)((int16_T)rtb_RelationalOperator4_b > 0);
    }

    /* End of Signum: '<S66>/Sign' */

    /* Sum: '<S70>/Sum1' incorporates:
     *  Constant: '<S66>/Constant2'
     *  Constant: '<S66>/Constant5'
     *  Delay: '<S70>/Resettable Delay'
     *  Product: '<S69>/Divide'
     *  Product: '<S69>/Divide1'
     *  Sum: '<S69>/Add'
     *  UnitDelay: '<S69>/Unit Delay'
     */
    rtb_Gain_h = (((((rtP.cf_Fw_Kb * rtDW->UnitDelay_DSTATE_l) << 6) >> 12) +
                   rtb_Switch2_pl * rtP.cf_Fw_Ki) >> 4) +
      rtDW->ResettableDelay_DSTATE;

    /* Switch: '<S71>/Switch2' incorporates:
     *  Constant: '<S69>/Constant6'
     *  RelationalOperator: '<S71>/LowerRelop1'
     *  Sum: '<S70>/Sum1'
     */
    if (rtb_Gain_h > 0) {
      rtb_Divide_e_idx_2 = 0;
    } else {
      /* Gain: '<S66>/Gain1' */
      rtb_Switch2_au = -32768 * rtDW->Merge_i[1];

      /* MinMax: '<S66>/Max' incorporates:
       *  Constant: '<S66>/Constant6'
       *  Gain: '<S66>/Gain1'
       */
      rtb_RelationalOperator4_b = rtP.id_fieldWeakMax << 15;
      if (rtb_Switch2_au <= rtb_RelationalOperator4_b) {
        rtb_Switch2_au = rtb_RelationalOperator4_b;
      }

      /* End of MinMax: '<S66>/Max' */

      /* Switch: '<S71>/Switch' incorporates:
       *  MinMax: '<S66>/Max'
       *  RelationalOperator: '<S71>/UpperRelop'
       *  Switch: '<S71>/Switch2'
       */
      if (((int64_T)rtb_Gain_h << 14) < rtb_Switch2_au) {
        rtb_Divide_e_idx_2 = rtb_Switch2_au >> 14;
      } else {
        rtb_Divide_e_idx_2 = rtb_Gain_h;
      }

      /* End of Switch: '<S71>/Switch' */
    }

    /* End of Switch: '<S71>/Switch2' */

    /* Sum: '<S66>/Sum1' incorporates:
     *  Product: '<S68>/Divide1'
     *  Switch: '<S71>/Switch2'
     */
    rtb_Gain_a = (int16_T)((rtb_Divide_e_idx_2 >> 1) + rtDW->Merge_i[0]);

    /* Sum: '<S66>/Sum of Elements' */
    rtb_Switch2_au = 1;
    rtb_Gain_ib = 0;

    /* Math: '<S66>/Math Function2' incorporates:
     *  Math: '<S78>/Math Function2'
     *  Product: '<S68>/Divide1'
     */
    rtb_RelationalOperator4_b = rtb_Gain_a * rtb_Gain_a;

    /* Sqrt: '<S66>/Sqrt' incorporates:
     *  Math: '<S66>/Math Function1'
     *  Math: '<S66>/Math Function2'
     *  Merge: '<S67>/Merge'
     *  Sum: '<S66>/Sum of Elements'
     *  Sum: '<S66>/Sum2'
     */
    rtb_Switch2_pl = rt_sqrt_Us32En6_Ys16En5_Is64En10_f_s((((rtDW->Merge_i[0] *
      rtDW->Merge_i[0] + rtDW->Merge_i[1] * rtDW->Merge_i[1]) >> 1) -
      (rtb_RelationalOperator4_b >> 1)) >> 3);

    /* Sum: '<S68>/Add' incorporates:
     *  Inport: '<Root>/iDC_Limit'
     *  Inport: '<Root>/vDC'
     *  Math: '<S78>/Math Function2'
     *  Product: '<S40>/Divide'
     *  Product: '<S68>/Divide'
     *  Switch: '<S66>/Switch'
     */
    rtb_MathFunction2_n = rtU->iDC_Limit * rtU->vDC - rtb_Gain_a *
      rtb_TmpSignalConversionAtLow_Pass_FilterInport1[0];

    /* Product: '<S68>/Divide3' incorporates:
     *  Constant: '<S68>/Constant5'
     *  Gain: '<S68>/Gain'
     *  Math: '<S78>/Math Function2'
     */
    rtb_Divide_e_idx_1 = rtb_MathFunction2_n / (rtP.i_dqMax << 1);
    if (rtb_Divide_e_idx_1 > 32767) {
      rtb_Divide_e_idx_1 = 32767;
    } else {
      if (rtb_Divide_e_idx_1 < -32768) {
        rtb_Divide_e_idx_1 = -32768;
      }
    }

    /* MinMax: '<S68>/Min2' incorporates:
     *  Product: '<S68>/Divide3'
     */
    if (rtb_TmpSignalConversionAtLow_Pass_FilterInport1[1] > (int16_T)
        rtb_Divide_e_idx_1) {
      rtb_Add2_lk = rtb_TmpSignalConversionAtLow_Pass_FilterInport1[1];
    } else {
      rtb_Add2_lk = (int16_T)rtb_Divide_e_idx_1;
    }

    /* End of MinMax: '<S68>/Min2' */

    /* Product: '<S68>/Divide1' incorporates:
     *  Math: '<S78>/Math Function2'
     */
    rtb_Divide_e_idx_1 = rtb_MathFunction2_n / rtb_Add2_lk;
    if (rtb_Divide_e_idx_1 > 32767) {
      rtb_Divide_e_idx_1 = 32767;
    } else {
      if (rtb_Divide_e_idx_1 < -32768) {
        rtb_Divide_e_idx_1 = -32768;
      }
    }

    /* Signum: '<S68>/Sign' incorporates:
     *  Sqrt: '<S66>/Sqrt'
     */
    if (rtb_Switch2_pl < 0) {
      rtb_Divide1_oy = -1;
    } else {
      rtb_Divide1_oy = (int16_T)(rtb_Switch2_pl > 0);
    }

    /* End of Signum: '<S68>/Sign' */

    /* Product: '<S68>/Divide2' incorporates:
     *  Product: '<S68>/Divide1'
     */
    rtb_Add2_lk = (int16_T)((int16_T)rtb_Divide_e_idx_1 * rtb_Divide1_oy);

    /* Switch: '<S77>/Switch2' incorporates:
     *  Constant: '<S68>/Constant2'
     *  Constant: '<S68>/Constant3'
     *  Gain: '<S68>/Gain1'
     *  Product: '<S68>/Divide2'
     *  RelationalOperator: '<S77>/LowerRelop1'
     *  RelationalOperator: '<S77>/UpperRelop'
     *  Switch: '<S77>/Switch'
     */
    if (rtb_Add2_lk > rtP.i_dqMax) {
      rtb_Add2_lk = rtP.i_dqMax;
    } else {
      if (rtb_Add2_lk < (int16_T)-rtP.i_dqMax) {
        /* Switch: '<S77>/Switch' incorporates:
         *  Constant: '<S68>/Constant2'
         *  Gain: '<S68>/Gain1'
         *  Switch: '<S77>/Switch2'
         */
        rtb_Add2_lk = (int16_T)-rtP.i_dqMax;
      }
    }

    /* End of Switch: '<S77>/Switch2' */

    /* Switch: '<S68>/Switch' incorporates:
     *  MinMax: '<S68>/Min1'
     *  Sqrt: '<S66>/Sqrt'
     *  Switch: '<S77>/Switch2'
     */
    if (rtb_Divide1_oy > 0) {
      /* MinMax: '<S68>/Min' incorporates:
       *  Sqrt: '<S66>/Sqrt'
       *  Switch: '<S77>/Switch2'
       */
      if (rtb_Add2_lk < rtb_Switch2_pl) {
        /* Switch: '<S68>/Switch' */
        rtDW->Switch_p = rtb_Add2_lk;
      } else {
        /* Switch: '<S68>/Switch' */
        rtDW->Switch_p = rtb_Switch2_pl;
      }

      /* End of MinMax: '<S68>/Min' */
    } else if (rtb_Add2_lk > rtb_Switch2_pl) {
      /* MinMax: '<S68>/Min1' incorporates:
       *  Switch: '<S68>/Switch'
       *  Switch: '<S77>/Switch2'
       */
      rtDW->Switch_p = rtb_Add2_lk;
    } else {
      /* Switch: '<S68>/Switch' incorporates:
       *  Sqrt: '<S66>/Sqrt'
       */
      rtDW->Switch_p = rtb_Switch2_pl;
    }

    /* End of Switch: '<S68>/Switch' */

    /* Switch: '<S76>/Switch2' incorporates:
     *  Constant: '<S68>/Constant1'
     *  Constant: '<S68>/Constant2'
     *  Gain: '<S68>/Gain1'
     *  RelationalOperator: '<S76>/LowerRelop1'
     *  RelationalOperator: '<S76>/UpperRelop'
     *  Switch: '<S66>/Switch'
     *  Switch: '<S76>/Switch'
     */
    if (rtb_Gain_a > rtP.i_dqMax) {
      /* Switch: '<S76>/Switch2' */
      rtDW->Switch2 = rtP.i_dqMax;
    } else if (rtb_Gain_a < (int16_T)-rtP.i_dqMax) {
      /* Switch: '<S76>/Switch' incorporates:
       *  Constant: '<S68>/Constant2'
       *  Gain: '<S68>/Gain1'
       *  Switch: '<S76>/Switch2'
       */
      rtDW->Switch2 = (int16_T)-rtP.i_dqMax;
    } else {
      /* Switch: '<S76>/Switch2' */
      rtDW->Switch2 = rtb_Gain_a;
    }

    /* End of Switch: '<S76>/Switch2' */

    /* Sqrt: '<S78>/Sqrt1' incorporates:
     *  Math: '<S78>/Math Function3'
     *  Product: '<S68>/Divide1'
     *  Sum: '<S78>/Add'
     */
    rtb_Gain_a = rt_sqrt_Us32En10_Ys16En5_Is32En10_s_s(rtb_RelationalOperator4_b
      + (int16_T)rtb_Divide_e_idx_1 * (int16_T)rtb_Divide_e_idx_1);

    /* Sum: '<S69>/Sum' incorporates:
     *  Sum: '<S70>/Sum1'
     *  Switch: '<S71>/Switch2'
     */
    rtb_MathFunction2_n = rtb_Divide_e_idx_2 - rtb_Gain_h;

    /* End of Outputs for SubSystem: '<S44>/Do_Calc' */
  }

  /* RelationalOperator: '<S96>/Relational Operator' incorporates:
   *  Switch: '<S76>/Switch2'
   *  UnitDelay: '<S96>/UnitDelay'
   */
  rtb_LogicalOperator1_g = (rtDW->Switch2 != rtDW->UnitDelay_DSTATE_l5);

  /* Sum: '<S87>/Add' incorporates:
   *  Product: '<S52>/Divide1'
   *  Switch: '<S76>/Switch2'
   *  UnitDelay: '<S87>/Unit Delay1'
   */
  rtb_Switch2_pl = (int16_T)(rtDW->Switch2 - rtDW->UnitDelay1_DSTATE_j);

  /* Abs: '<S87>/Abs' incorporates:
   *  Product: '<S52>/Divide1'
   */
  if (rtb_Switch2_pl < 0) {
    rtb_Switch2_pl = (int16_T)-rtb_Switch2_pl;
  }

  /* End of Abs: '<S87>/Abs' */

  /* Outputs for Enabled SubSystem: '<S87>/Enabled Subsystem' incorporates:
   *  EnablePort: '<S97>/Enable'
   */
  /* If: '<S98>/If' incorporates:
   *  Gain: '<S87>/Gain'
   *  Product: '<S52>/Divide1'
   *  UnitDelay: '<S87>/Unit Delay1'
   */
  if (rtb_LogicalOperator1_g) {
    /* Outputs for IfAction SubSystem: '<S98>/RateInit' incorporates:
     *  ActionPort: '<S99>/Action Port'
     */
    RateInit(rtDW->UnitDelay1_DSTATE_j, rtDW->Switch2, (int16_T)((13107 *
               rtb_Switch2_pl) >> 13), &rtDW->Divide_d, &rtDW->Max_i,
             &rtDW->Max1_e);

    /* End of Outputs for SubSystem: '<S98>/RateInit' */

    /* Switch: '<S102>/Switch1' incorporates:
     *  Gain: '<S87>/Gain'
     *  Product: '<S52>/Divide1'
     *  UnitDelay: '<S87>/Unit Delay1'
     */
    rtb_Add2_lk = rtDW->UnitDelay1_DSTATE_j;
  } else {
    /* Switch: '<S102>/Switch1' incorporates:
     *  UnitDelay: '<S102>/UnitDelay'
     */
    rtb_Add2_lk = rtDW->UnitDelay_DSTATE_g;
  }

  /* End of If: '<S98>/If' */
  /* End of Outputs for SubSystem: '<S87>/Enabled Subsystem' */

  /* Switch: '<S98>/Switch' incorporates:
   *  Constant: '<S98>/Constant'
   *  Product: '<S99>/Divide'
   *  RelationalOperator: '<S98>/Equal'
   *  Switch: '<S76>/Switch2'
   *  UnitDelay: '<S98>/Unit Delay'
   */
  if (rtDW->Switch2 != rtDW->UnitDelay_DSTATE_b) {
    rtb_Switch2_pl = rtDW->Divide_d;
  } else {
    rtb_Switch2_pl = 0;
  }

  /* End of Switch: '<S98>/Switch' */

  /* Sum: '<S101>/Add2' */
  rtb_RelationalOperator4_b = ((rtb_Add2_lk << 5) + rtb_Switch2_pl) >> 5;
  if (rtb_RelationalOperator4_b > 32767) {
    rtb_RelationalOperator4_b = 32767;
  } else {
    if (rtb_RelationalOperator4_b < -32768) {
      rtb_RelationalOperator4_b = -32768;
    }
  }

  /* Switch: '<S100>/Switch2' incorporates:
   *  MinMax: '<S99>/Max'
   *  MinMax: '<S99>/Max1'
   *  RelationalOperator: '<S100>/LowerRelop1'
   *  RelationalOperator: '<S100>/UpperRelop'
   *  Sum: '<S101>/Add2'
   *  Switch: '<S100>/Switch'
   */
  if ((int16_T)rtb_RelationalOperator4_b > rtDW->Max_i) {
    rtb_Add2_lk = rtDW->Max_i;
  } else if ((int16_T)rtb_RelationalOperator4_b < rtDW->Max1_e) {
    /* Switch: '<S100>/Switch' incorporates:
     *  MinMax: '<S99>/Max1'
     *  Switch: '<S100>/Switch2'
     */
    rtb_Add2_lk = rtDW->Max1_e;
  } else {
    rtb_Add2_lk = (int16_T)rtb_RelationalOperator4_b;
  }

  /* End of Switch: '<S100>/Switch2' */

  /* RelationalOperator: '<S103>/Relational Operator' incorporates:
   *  Switch: '<S68>/Switch'
   *  UnitDelay: '<S103>/UnitDelay'
   */
  rtb_UnitDelay_c = (rtDW->Switch_p != rtDW->UnitDelay_DSTATE_er);

  /* Sum: '<S88>/Add' incorporates:
   *  Product: '<S52>/Divide1'
   *  Switch: '<S68>/Switch'
   *  UnitDelay: '<S88>/Unit Delay1'
   */
  rtb_Switch2_pl = (int16_T)(rtDW->Switch_p - rtDW->UnitDelay1_DSTATE_p);

  /* Abs: '<S88>/Abs' incorporates:
   *  Product: '<S52>/Divide1'
   */
  if (rtb_Switch2_pl < 0) {
    rtb_Switch2_pl = (int16_T)-rtb_Switch2_pl;
  }

  /* End of Abs: '<S88>/Abs' */

  /* Outputs for Enabled SubSystem: '<S88>/Enabled Subsystem' incorporates:
   *  EnablePort: '<S104>/Enable'
   */
  /* If: '<S105>/If' incorporates:
   *  Gain: '<S88>/Gain'
   *  Product: '<S52>/Divide1'
   *  UnitDelay: '<S88>/Unit Delay1'
   */
  if (rtb_UnitDelay_c) {
    /* Outputs for IfAction SubSystem: '<S105>/RateInit' incorporates:
     *  ActionPort: '<S106>/Action Port'
     */
    RateInit(rtDW->UnitDelay1_DSTATE_p, rtDW->Switch_p, (int16_T)((13107 *
               rtb_Switch2_pl) >> 13), &rtDW->Divide_g, &rtDW->Max_p,
             &rtDW->Max1_i);

    /* End of Outputs for SubSystem: '<S105>/RateInit' */

    /* Switch: '<S109>/Switch1' incorporates:
     *  Gain: '<S88>/Gain'
     *  Product: '<S52>/Divide1'
     *  UnitDelay: '<S88>/Unit Delay1'
     */
    rtb_Sum6 = rtDW->UnitDelay1_DSTATE_p;
  } else {
    /* Switch: '<S109>/Switch1' incorporates:
     *  UnitDelay: '<S109>/UnitDelay'
     */
    rtb_Sum6 = rtDW->UnitDelay_DSTATE_o;
  }

  /* End of If: '<S105>/If' */
  /* End of Outputs for SubSystem: '<S88>/Enabled Subsystem' */

  /* Switch: '<S105>/Switch' incorporates:
   *  Constant: '<S105>/Constant'
   *  Product: '<S106>/Divide'
   *  RelationalOperator: '<S105>/Equal'
   *  Switch: '<S68>/Switch'
   *  UnitDelay: '<S105>/Unit Delay'
   */
  if (rtDW->Switch_p != rtDW->UnitDelay_DSTATE_d) {
    rtb_Switch2_pl = rtDW->Divide_g;
  } else {
    rtb_Switch2_pl = 0;
  }

  /* End of Switch: '<S105>/Switch' */

  /* Sum: '<S108>/Add2' */
  rtb_Divide_e_idx_1 = ((rtb_Sum6 << 5) + rtb_Switch2_pl) >> 5;
  if (rtb_Divide_e_idx_1 > 32767) {
    rtb_Divide_e_idx_1 = 32767;
  } else {
    if (rtb_Divide_e_idx_1 < -32768) {
      rtb_Divide_e_idx_1 = -32768;
    }
  }

  /* Switch: '<S107>/Switch2' incorporates:
   *  MinMax: '<S106>/Max'
   *  MinMax: '<S106>/Max1'
   *  RelationalOperator: '<S107>/LowerRelop1'
   *  RelationalOperator: '<S107>/UpperRelop'
   *  Sum: '<S108>/Add2'
   *  Switch: '<S107>/Switch'
   */
  if ((int16_T)rtb_Divide_e_idx_1 > rtDW->Max_p) {
    rtb_Divide1_oy = rtDW->Max_p;
  } else if ((int16_T)rtb_Divide_e_idx_1 < rtDW->Max1_i) {
    /* Switch: '<S107>/Switch' incorporates:
     *  MinMax: '<S106>/Max1'
     *  Switch: '<S107>/Switch2'
     */
    rtb_Divide1_oy = rtDW->Max1_i;
  } else {
    rtb_Divide1_oy = (int16_T)rtb_Divide_e_idx_1;
  }

  /* End of Switch: '<S107>/Switch2' */

  /* DataTypeConversion: '<S45>/Data Type Conversion' incorporates:
   *  Logic: '<S45>/Logical Operator'
   *  RelationalOperator: '<S45>/Equal'
   *  UnitDelay: '<S45>/Unit Delay'
   */
  rtb_DataTypeConversion_e = (uint8_T)((rtb_dz_cntTrnsDet != 0) &&
    (rtDW->UnitDelay_DSTATE_h3 != rtb_dz_cntTrnsDet));

  /* If: '<S45>/If1' incorporates:
   *  Constant: '<S85>/Constant1'
   *  Constant: '<S85>/Constant3'
   *  Constant: '<S85>/Constant4'
   *  Constant: '<S85>/Constant6'
   *  Constant: '<S85>/Constant7'
   *  Constant: '<S85>/Constant8'
   *  Gain: '<S85>/Gain1'
   *  Gain: '<S85>/Gain2'
   *  Inport: '<S86>/In1'
   *  Merge: '<S45>/Merge'
   *  Outport: '<Root>/f_Idq'
   *  Product: '<S85>/Divide'
   *  Sum: '<S85>/Sum'
   *  Sum: '<S85>/Sum1'
   *  Switch: '<S100>/Switch2'
   *  Switch: '<S107>/Switch2'
   *  Switch: '<S111>/Switch'
   *  UnitDelay: '<S35>/UnitDelay1'
   */
  if (rtb_dz_cntTrnsDet != 0) {
    /* Outputs for IfAction SubSystem: '<S45>/CurrentLoop' incorporates:
     *  ActionPort: '<S85>/Action Port'
     */
    /* Product: '<S85>/Divide' incorporates:
     *  Constant: '<S85>/Constant2'
     *  Inport: '<Root>/vDC'
     */
    rtb_Switch2_pl = (int16_T)((rtU->vDC * rtP.V_modulation) >> 14);

    /* Outputs for Atomic SubSystem: '<S85>/PI_backCalc_fixdt' */
    rtb_Switch2_au = PI_backCalc_fixdt_i((int16_T)(rtb_Add2_lk - rtY->f_Idq[0]),
      rtP.cf_idKp, rtP.cf_idKi, rtP.cf_idKb, rtb_Switch2_pl, (int16_T)
      -rtb_Switch2_pl, rtDW->UnitDelay1_DSTATE_o[0], rtb_DataTypeConversion_e,
      &rtDW->PI_backCalc_fixdt_ig, &rtPrevZCX->PI_backCalc_fixdt_ig);

    /* End of Outputs for SubSystem: '<S85>/PI_backCalc_fixdt' */

    /* Outputs for Atomic SubSystem: '<S85>/PI_backCalc_fixdt1' */
    rtb_Gain_ib = PI_backCalc_fixdt_i((int16_T)(rtb_Divide1_oy - rtY->f_Idq[1]),
      rtP.cf_iqKp, rtP.cf_iqKi, rtP.cf_iqKb, rtb_Switch2_pl, (int16_T)
      -rtb_Switch2_pl, rtDW->UnitDelay1_DSTATE_o[1], rtb_DataTypeConversion_e,
      &rtDW->PI_backCalc_fixdt1, &rtPrevZCX->PI_backCalc_fixdt1);

    /* End of Outputs for SubSystem: '<S85>/PI_backCalc_fixdt1' */

    /* Sum: '<S85>/Sum2' incorporates:
     *  Constant: '<S85>/Constant1'
     *  Constant: '<S85>/Constant3'
     *  Constant: '<S85>/Constant4'
     *  Constant: '<S85>/Constant6'
     *  Constant: '<S85>/Constant7'
     *  Constant: '<S85>/Constant8'
     *  DataTypeConversion: '<S85>/Data Type Conversion'
     *  DataTypeConversion: '<S85>/Data Type Conversion1'
     *  Gain: '<S85>/Gain1'
     *  Gain: '<S85>/Gain2'
     *  Merge: '<S45>/Merge'
     *  Outport: '<Root>/f_Idq'
     *  Product: '<S85>/Divide'
     *  Sum: '<S85>/Sum'
     *  Sum: '<S85>/Sum1'
     *  Switch: '<S100>/Switch2'
     *  Switch: '<S107>/Switch2'
     *  Switch: '<S93>/Switch2'
     *  Switch: '<S95>/Switch2'
     *  UnitDelay: '<S35>/UnitDelay1'
     */
    rtb_TmpSignalConversionAtLow_Pass_FilterInport1[0] = (int16_T)
      (rtb_Switch2_au >> 9);
    rtb_TmpSignalConversionAtLow_Pass_FilterInport1[1] = (int16_T)(rtb_Gain_ib >>
      9);

    /* End of Outputs for SubSystem: '<S45>/CurrentLoop' */
  } else {
    /* Outputs for IfAction SubSystem: '<S45>/OpenLoop' incorporates:
     *  ActionPort: '<S86>/Action Port'
     */
    rtb_TmpSignalConversionAtLow_Pass_FilterInport1[0] = rtDW->Switch[0];
    rtb_TmpSignalConversionAtLow_Pass_FilterInport1[1] = rtDW->Switch[1];

    /* End of Outputs for SubSystem: '<S45>/OpenLoop' */
  }

  /* End of If: '<S45>/If1' */

  /* Product: '<S42>/Divide2' incorporates:
   *  Constant: '<S42>/Constant'
   *  Inport: '<Root>/vDC'
   *  Product: '<S52>/Divide1'
   */
  rtb_Switch2_pl = (int16_T)div_nde_s32_floor(rtU->vDC << 14, rtP.V_modulation);

  /* Sum: '<S42>/Sum of Elements' incorporates:
   *  Math: '<S42>/Math Function'
   *  Merge: '<S45>/Merge'
   */
  tmp_2 = (int64_T)((rtb_TmpSignalConversionAtLow_Pass_FilterInport1[0] *
                     rtb_TmpSignalConversionAtLow_Pass_FilterInport1[0]) >> 4) +
    ((rtb_TmpSignalConversionAtLow_Pass_FilterInport1[1] *
      rtb_TmpSignalConversionAtLow_Pass_FilterInport1[1]) >> 4);
  if (tmp_2 > 2147483647LL) {
    tmp_2 = 2147483647LL;
  } else {
    if (tmp_2 < -2147483648LL) {
      tmp_2 = -2147483648LL;
    }
  }

  /* Product: '<S42>/Divide' incorporates:
   *  Math: '<S42>/Math Function1'
   *  Product: '<S52>/Divide1'
   *  Sum: '<S42>/Sum of Elements'
   */
  tmp_2 = ((int64_T)(int32_T)tmp_2 << 14) / ((rtb_Switch2_pl * rtb_Switch2_pl) >>
    4);
  if (tmp_2 < 0LL) {
    tmp_2 = 0LL;
  } else {
    if (tmp_2 > 65535LL) {
      tmp_2 = 65535LL;
    }
  }

  /* Sqrt: '<S42>/Sqrt' incorporates:
   *  Product: '<S42>/Divide'
   */
  rtb_Sum1_p = rt_sqrt_Uu16En14_Yu16En14_Iu32En28_s_s((uint16_T)tmp_2);

  /* Switch: '<S42>/Switch' incorporates:
   *  Merge: '<S45>/Merge'
   *  Sqrt: '<S42>/Sqrt'
   */
  if (rtb_Sum1_p > 16384) {
    /* Switch: '<S42>/Switch' incorporates:
     *  Merge: '<S45>/Merge'
     *  MultiPortSwitch: '<S42>/Multiport Switch'
     *  Product: '<S42>/Divide1'
     */
    rtb_UnitDelay1_ko[0] = (int16_T)
      ((rtb_TmpSignalConversionAtLow_Pass_FilterInport1[0] << 14) / rtb_Sum1_p);
    rtb_UnitDelay1_ko[1] = (int16_T)
      ((rtb_TmpSignalConversionAtLow_Pass_FilterInport1[1] << 14) / rtb_Sum1_p);
  } else {
    rtb_UnitDelay1_ko[0] = rtb_TmpSignalConversionAtLow_Pass_FilterInport1[0];
    rtb_UnitDelay1_ko[1] = rtb_TmpSignalConversionAtLow_Pass_FilterInport1[1];
  }

  /* End of Switch: '<S42>/Switch' */

  /* Sum: '<S52>/Sum1' incorporates:
   *  Interpolation_n-D: '<S49>/r_cos_M1'
   *  Interpolation_n-D: '<S49>/r_sin_M1'
   *  Product: '<S52>/Divide2'
   *  Product: '<S52>/Divide3'
   */
  rtb_Divide_e_idx_2 = (int16_T)((rtb_UnitDelay1_ko[0] *
    rtConstP.pooled12[rtb_Divide_d]) >> 14) + (int16_T)((rtb_UnitDelay1_ko[1] *
    rtConstP.pooled13[rtb_Divide_d]) >> 14);
  if (rtb_Divide_e_idx_2 > 32767) {
    rtb_Divide_e_idx_2 = 32767;
  } else {
    if (rtb_Divide_e_idx_2 < -32768) {
      rtb_Divide_e_idx_2 = -32768;
    }
  }

  /* Sum: '<S52>/Sum6' incorporates:
   *  Interpolation_n-D: '<S49>/r_cos_M1'
   *  Interpolation_n-D: '<S49>/r_sin_M1'
   *  Product: '<S52>/Divide1'
   *  Product: '<S52>/Divide4'
   */
  tmp = (int16_T)((rtb_UnitDelay1_ko[0] * rtConstP.pooled13[rtb_Divide_d]) >> 14)
    - (int16_T)((rtb_UnitDelay1_ko[1] * rtConstP.pooled12[rtb_Divide_d]) >> 14);
  if (tmp > 32767) {
    tmp = 32767;
  } else {
    if (tmp < -32768) {
      tmp = -32768;
    }
  }

  /* Product: '<S53>/Divide7' incorporates:
   *  Constant: '<S53>/Constant3'
   *  Sum: '<S52>/Sum1'
   */
  rtb_Switch2_pl = (int16_T)((2365 * (int16_T)rtb_Divide_e_idx_2) >> 11);

  /* MATLAB Function: '<S53>/sector_select' incorporates:
   *  Product: '<S53>/Divide7'
   *  Sum: '<S52>/Sum1'
   *  Sum: '<S52>/Sum6'
   */
  if ((int16_T)rtb_Divide_e_idx_2 >= 0) {
    if ((int16_T)tmp >= 0) {
      if (rtb_Switch2_pl > ((int16_T)tmp << 1)) {
        /* DataTypeConversion: '<S53>/Data Type Conversion' */
        rtb_DataTypeConversion_e = 2U;
      } else {
        /* DataTypeConversion: '<S53>/Data Type Conversion' */
        rtb_DataTypeConversion_e = 1U;
      }
    } else {
      rtb_Gain_b = -rtb_Switch2_pl;
      if (-rtb_Switch2_pl > 32767) {
        rtb_Gain_b = 32767;
      }

      if (rtb_Gain_b > ((int16_T)tmp << 1)) {
        /* DataTypeConversion: '<S53>/Data Type Conversion' */
        rtb_DataTypeConversion_e = 3U;
      } else {
        /* DataTypeConversion: '<S53>/Data Type Conversion' */
        rtb_DataTypeConversion_e = 2U;
      }
    }
  } else if ((int16_T)tmp >= 0) {
    rtb_Gain_b = -rtb_Switch2_pl;
    if (-rtb_Switch2_pl > 32767) {
      rtb_Gain_b = 32767;
    }

    if (rtb_Gain_b > ((int16_T)tmp << 1)) {
      /* DataTypeConversion: '<S53>/Data Type Conversion' */
      rtb_DataTypeConversion_e = 5U;
    } else {
      /* DataTypeConversion: '<S53>/Data Type Conversion' */
      rtb_DataTypeConversion_e = 6U;
    }
  } else if (rtb_Switch2_pl > ((int16_T)tmp << 1)) {
    /* DataTypeConversion: '<S53>/Data Type Conversion' */
    rtb_DataTypeConversion_e = 4U;
  } else {
    /* DataTypeConversion: '<S53>/Data Type Conversion' */
    rtb_DataTypeConversion_e = 5U;
  }

  /* End of MATLAB Function: '<S53>/sector_select' */

  /* Gain: '<S53>/Gain' incorporates:
   *  Inport: '<Root>/vDC'
   */
  rtb_Gain_b = 18919 * rtU->vDC;

  /* Product: '<S53>/Divide' incorporates:
   *  Gain: '<S53>/Gain'
   *  Sum: '<S52>/Sum6'
   */
  rtb_Sum6 = (int16_T)(((int64_T)(int16_T)tmp << 26) / rtb_Gain_b);

  /* Product: '<S53>/Divide1' incorporates:
   *  Gain: '<S53>/Gain'
   *  Sum: '<S52>/Sum1'
   */
  rtb_Sum1_ak = (int16_T)(((int64_T)(int16_T)rtb_Divide_e_idx_2 << 26) /
    rtb_Gain_b);

  /* MultiPortSwitch: '<S54>/Multiport Switch' incorporates:
   *  DataTypeConversion: '<S53>/Data Type Conversion1'
   */
  switch (rtb_DataTypeConversion_e) {
   case 1:
    /* Product: '<S56>/Divide3' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide1'
     *  Product: '<S56>/Divide2'
     */
    rtb_Divide3_k = (int16_T)(((int16_T)((rtb_Sum1_ak * 9459) >> 13) * (int16_T)
      rtP.i_pwm_count) >> 12);

    /* Product: '<S56>/Divide1' incorporates:
     *  Constant: '<S53>/Constant1'
     *  Constant: '<S56>/Constant'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide'
     *  Product: '<S53>/Divide1'
     *  Product: '<S56>/Divide'
     *  Sum: '<S56>/Add'
     */
    rtb_Sum1_ak = (int16_T)(((int16_T)(rtb_Sum6 - ((rtb_Sum1_ak * 9459) >> 14)) *
      (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S56>/Divide4' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Sum: '<S56>/Add1'
     *  Sum: '<S56>/Add2'
     */
    rtb_Switch2_pl = (int16_T)((int16_T)((int16_T)((int16_T)rtP.i_pwm_count -
      rtb_Sum1_ak) - rtb_Divide3_k) >> 1);

    /* Sum: '<S56>/Add3' */
    rtb_Sum6 = (int16_T)(rtb_Switch2_pl + rtb_Divide3_k);

    /* Outport: '<Root>/n_Duty' incorporates:
     *  Sum: '<S56>/Add4'
     */
    rtY->n_Duty[0] = (int16_T)(rtb_Sum6 + rtb_Sum1_ak);
    rtY->n_Duty[1] = rtb_Sum6;
    rtY->n_Duty[2] = rtb_Switch2_pl;
    break;

   case 2:
    /* Product: '<S57>/Divide1' incorporates:
     *  Constant: '<S53>/Constant1'
     *  Constant: '<S57>/Constant'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide'
     *  Product: '<S53>/Divide1'
     *  Product: '<S57>/Divide'
     *  Sum: '<S57>/Add'
     */
    rtb_Divide3_k = (int16_T)(((int16_T)(((rtb_Sum1_ak * 9459) >> 14) + rtb_Sum6)
      * (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S57>/Divide3' incorporates:
     *  Constant: '<S53>/Constant1'
     *  Constant: '<S57>/Constant'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide'
     *  Product: '<S53>/Divide1'
     *  Product: '<S57>/Divide2'
     *  Sum: '<S57>/Add5'
     */
    rtb_Sum1_ak = (int16_T)(((int16_T)(((rtb_Sum1_ak * 9459) >> 14) - rtb_Sum6) *
      (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S57>/Divide4' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Sum: '<S57>/Add1'
     *  Sum: '<S57>/Add2'
     */
    rtb_Switch2_pl = (int16_T)((int16_T)((int16_T)((int16_T)rtP.i_pwm_count -
      rtb_Sum1_ak) - rtb_Divide3_k) >> 1);

    /* Sum: '<S57>/Add3' */
    rtb_Sum6 = (int16_T)(rtb_Switch2_pl + rtb_Divide3_k);

    /* Outport: '<Root>/n_Duty' incorporates:
     *  Sum: '<S57>/Add4'
     */
    rtY->n_Duty[0] = rtb_Sum6;
    rtY->n_Duty[1] = (int16_T)(rtb_Sum6 + rtb_Sum1_ak);
    rtY->n_Duty[2] = rtb_Switch2_pl;
    break;

   case 3:
    /* Product: '<S58>/Divide1' incorporates:
     *  Constant: '<S53>/Constant1'
     *  Constant: '<S58>/Constant'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide'
     *  Product: '<S53>/Divide1'
     *  Product: '<S58>/Divide'
     *  Sum: '<S58>/Add'
     */
    rtb_Sum6 = (int16_T)(((int16_T)(-rtb_Sum6 - ((rtb_Sum1_ak * 9459) >> 14)) *
                          (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S58>/Divide3' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide1'
     *  Product: '<S58>/Divide2'
     */
    rtb_Sum1_ak = (int16_T)(((int16_T)((rtb_Sum1_ak * 9459) >> 13) * (int16_T)
      rtP.i_pwm_count) >> 12);

    /* Product: '<S58>/Divide4' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Sum: '<S58>/Add1'
     *  Sum: '<S58>/Add2'
     */
    rtb_Switch2_pl = (int16_T)((int16_T)((int16_T)((int16_T)rtP.i_pwm_count -
      rtb_Sum1_ak) - rtb_Sum6) >> 1);

    /* Sum: '<S58>/Add3' */
    rtb_Sum6 += rtb_Switch2_pl;

    /* Outport: '<Root>/n_Duty' incorporates:
     *  Sum: '<S58>/Add4'
     */
    rtY->n_Duty[0] = rtb_Switch2_pl;
    rtY->n_Duty[1] = (int16_T)(rtb_Sum6 + rtb_Sum1_ak);
    rtY->n_Duty[2] = rtb_Sum6;
    break;

   case 4:
    /* Product: '<S59>/Divide1' incorporates:
     *  Constant: '<S53>/Constant1'
     *  Constant: '<S59>/Constant'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide'
     *  Product: '<S53>/Divide1'
     *  Product: '<S59>/Divide'
     *  Sum: '<S59>/Add'
     */
    rtb_Sum6 = (int16_T)(((int16_T)(((rtb_Sum1_ak * 9459) >> 14) - rtb_Sum6) *
                          (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S59>/Divide3' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide1'
     *  Product: '<S59>/Divide2'
     *  Sum: '<S59>/Add5'
     */
    rtb_Sum1_ak = (int16_T)(((int16_T)(-((int16_T)((rtb_Sum1_ak * 9459) >> 13) <<
      2) >> 2) * (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S59>/Divide4' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Sum: '<S59>/Add1'
     *  Sum: '<S59>/Add2'
     */
    rtb_Switch2_pl = (int16_T)((int16_T)((int16_T)((int16_T)rtP.i_pwm_count -
      rtb_Sum1_ak) - rtb_Sum6) >> 1);

    /* Sum: '<S59>/Add3' */
    rtb_Sum6 += rtb_Switch2_pl;

    /* Outport: '<Root>/n_Duty' incorporates:
     *  Sum: '<S59>/Add4'
     */
    rtY->n_Duty[0] = rtb_Switch2_pl;
    rtY->n_Duty[1] = rtb_Sum6;
    rtY->n_Duty[2] = (int16_T)(rtb_Sum6 + rtb_Sum1_ak);
    break;

   case 5:
    /* Product: '<S60>/Divide3' incorporates:
     *  Constant: '<S53>/Constant1'
     *  Constant: '<S60>/Constant'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide'
     *  Product: '<S53>/Divide1'
     *  Product: '<S60>/Divide2'
     *  Sum: '<S60>/Add5'
     */
    rtb_Divide3_k = (int16_T)(((int16_T)(rtb_Sum6 - ((rtb_Sum1_ak * 9459) >> 14))
      * (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S60>/Divide1' incorporates:
     *  Constant: '<S53>/Constant1'
     *  Constant: '<S60>/Constant'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide'
     *  Product: '<S53>/Divide1'
     *  Product: '<S60>/Divide'
     *  Sum: '<S60>/Add'
     */
    rtb_Sum1_ak = (int16_T)(((int16_T)(-rtb_Sum6 - ((rtb_Sum1_ak * 9459) >> 14))
      * (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S60>/Divide4' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Sum: '<S60>/Add1'
     *  Sum: '<S60>/Add2'
     */
    rtb_Switch2_pl = (int16_T)((int16_T)((int16_T)((int16_T)rtP.i_pwm_count -
      rtb_Sum1_ak) - rtb_Divide3_k) >> 1);

    /* Sum: '<S60>/Add3' */
    rtb_Sum6 = (int16_T)(rtb_Switch2_pl + rtb_Divide3_k);

    /* Outport: '<Root>/n_Duty' incorporates:
     *  Sum: '<S60>/Add4'
     */
    rtY->n_Duty[0] = rtb_Sum6;
    rtY->n_Duty[1] = rtb_Switch2_pl;
    rtY->n_Duty[2] = (int16_T)(rtb_Sum6 + rtb_Sum1_ak);
    break;

   default:
    /* Product: '<S61>/Divide3' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide1'
     *  Product: '<S61>/Divide2'
     *  Sum: '<S61>/Add5'
     */
    rtb_Divide3_k = (int16_T)(((int16_T)(-((int16_T)((rtb_Sum1_ak * 9459) >> 13)
      << 2) >> 2) * (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S61>/Divide1' incorporates:
     *  Constant: '<S53>/Constant1'
     *  Constant: '<S61>/Constant'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Product: '<S53>/Divide'
     *  Product: '<S53>/Divide1'
     *  Product: '<S61>/Divide'
     *  Sum: '<S61>/Add'
     */
    rtb_Sum1_ak = (int16_T)(((int16_T)(((rtb_Sum1_ak * 9459) >> 14) + rtb_Sum6) *
      (int16_T)rtP.i_pwm_count) >> 12);

    /* Product: '<S61>/Divide4' incorporates:
     *  Constant: '<S53>/Constant1'
     *  DataTypeConversion: '<S53>/Data Type Conversion2'
     *  Sum: '<S61>/Add1'
     *  Sum: '<S61>/Add2'
     */
    rtb_Switch2_pl = (int16_T)((int16_T)((int16_T)((int16_T)rtP.i_pwm_count -
      rtb_Sum1_ak) - rtb_Divide3_k) >> 1);

    /* Sum: '<S61>/Add3' */
    rtb_Sum6 = (int16_T)(rtb_Switch2_pl + rtb_Divide3_k);

    /* Outport: '<Root>/n_Duty' incorporates:
     *  Sum: '<S61>/Add4'
     */
    rtY->n_Duty[0] = (int16_T)(rtb_Sum6 + rtb_Sum1_ak);
    rtY->n_Duty[1] = rtb_Switch2_pl;
    rtY->n_Duty[2] = rtb_Sum6;
    break;
  }

  /* End of MultiPortSwitch: '<S54>/Multiport Switch' */

  /* Switch: '<S109>/Switch2' */
  if (rtb_UnitDelay_c) {
    /* Update for UnitDelay: '<S109>/UnitDelay' incorporates:
     *  UnitDelay: '<S88>/Unit Delay1'
     */
    rtDW->UnitDelay_DSTATE_o = rtDW->UnitDelay1_DSTATE_p;
  } else {
    /* Update for UnitDelay: '<S109>/UnitDelay' incorporates:
     *  Sum: '<S108>/Add2'
     */
    rtDW->UnitDelay_DSTATE_o = (int16_T)rtb_Divide_e_idx_1;
  }

  /* End of Switch: '<S109>/Switch2' */

  /* Switch: '<S102>/Switch2' */
  if (rtb_LogicalOperator1_g) {
    /* Update for UnitDelay: '<S102>/UnitDelay' incorporates:
     *  UnitDelay: '<S87>/Unit Delay1'
     */
    rtDW->UnitDelay_DSTATE_g = rtDW->UnitDelay1_DSTATE_j;
  } else {
    /* Update for UnitDelay: '<S102>/UnitDelay' incorporates:
     *  Sum: '<S101>/Add2'
     */
    rtDW->UnitDelay_DSTATE_g = (int16_T)rtb_RelationalOperator4_b;
  }

  /* End of Switch: '<S102>/Switch2' */

  /* Switch: '<S5>/Switch1' incorporates:
   *  RelationalOperator: '<S7>/Relational Operator'
   *  UnitDelay: '<S7>/UnitDelay'
   */
  if (rtb_RelationalOperator != rtDW->UnitDelay_DSTATE_f) {
    rtb_UnitDelay_n = rtb_Sum_d;
  }

  /* End of Switch: '<S5>/Switch1' */

  /* If: '<S20>/If1' */
  if (rtb_Edge_Detect) {
    /* Outputs for IfAction SubSystem: '<S20>/AdvCtrlDetect' incorporates:
     *  ActionPort: '<S28>/Action Port'
     */
    /* Relay: '<S28>/n_commDeacv' incorporates:
     *  Abs: '<S20>/Abs5'
     */
    rtDW->n_commDeacv_Mode = ((rtb_Rem1 >= 480U) || ((rtb_Rem1 > 240U) &&
      rtDW->n_commDeacv_Mode));

    /* Outport: '<Root>/b_advCtrl' incorporates:
     *  Constant: '<S30>/Constant'
     *  RelationalOperator: '<S30>/Compare'
     *  Relay: '<S28>/n_commDeacv'
     *  Sum: '<S28>/Sum13'
     *  UnitDelay: '<S28>/UnitDelay2'
     *  UnitDelay: '<S28>/UnitDelay3'
     *  UnitDelay: '<S28>/UnitDelay5'
     */
    rtY->b_advCtrl = ((uint16_T)((uint32_T)(uint16_T)((uint32_T)(uint16_T)
      ((uint32_T)rtDW->UnitDelay2_DSTATE_o + rtDW->UnitDelay3_DSTATE_p) +
      rtDW->UnitDelay5_DSTATE_m) + rtDW->n_commDeacv_Mode) >= 4);

    /* Update for UnitDelay: '<S28>/UnitDelay2' incorporates:
     *  UnitDelay: '<S28>/UnitDelay3'
     */
    rtDW->UnitDelay2_DSTATE_o = rtDW->UnitDelay3_DSTATE_p;

    /* Update for UnitDelay: '<S28>/UnitDelay3' incorporates:
     *  UnitDelay: '<S28>/UnitDelay5'
     */
    rtDW->UnitDelay3_DSTATE_p = rtDW->UnitDelay5_DSTATE_m;

    /* Update for UnitDelay: '<S28>/UnitDelay5' incorporates:
     *  Logic: '<S28>/Logical Operator3'
     *  Relay: '<S28>/n_commDeacv'
     */
    rtDW->UnitDelay5_DSTATE_m = rtDW->n_commDeacv_Mode;

    /* End of Outputs for SubSystem: '<S20>/AdvCtrlDetect' */
  }

  /* End of If: '<S20>/If1' */

  /* Update for Delay: '<S17>/Delay' incorporates:
   *  Inport: '<Root>/hall_abc'
   */
  rtDW->Delay_DSTATE_p = rtU->hall_abc[0];

  /* Update for Delay: '<S17>/Delay1' incorporates:
   *  Inport: '<Root>/hall_abc'
   */
  rtDW->Delay1_DSTATE = rtU->hall_abc[1];

  /* Update for Delay: '<S17>/Delay2' incorporates:
   *  Inport: '<Root>/hall_abc'
   */
  rtDW->Delay2_DSTATE = rtU->hall_abc[2];

  /* Update for UnitDelay: '<S20>/UnitDelay4' incorporates:
   *  Abs: '<S20>/Abs5'
   */
  rtDW->UnitDelay4_DSTATE = rtb_Rem1;

  /* Update for UnitDelay: '<S5>/UnitDelay' */
  rtDW->UnitDelay_DSTATE_p = rtb_UnitDelay_n;

  /* Update for UnitDelay: '<S6>/UnitDelay' */
  rtDW->UnitDelay_DSTATE_gv = rtb_RelationalOperator;

  /* Update for UnitDelay: '<S10>/UnitDelay' */
  rtDW->UnitDelay_DSTATE_oy = rtb_RelationalOperator4_d;

  /* Update for UnitDelay: '<S38>/UnitDelay1' incorporates:
   *  Sum: '<S38>/Sum3'
   */
  rtDW->UnitDelay1_DSTATE = rtb_Merge;

  /* Update for UnitDelay: '<S1>/Unit Delay' incorporates:
   *  Switch: '<S42>/Switch'
   */
  rtDW->UnitDelay_DSTATE_k[0] = rtb_UnitDelay1_ko[0];

  /* Update for UnitDelay: '<S35>/UnitDelay1' incorporates:
   *  Switch: '<S42>/Switch'
   *  UnitDelay: '<S1>/Unit Delay'
   */
  rtDW->UnitDelay1_DSTATE_o[0] = rtb_UnitDelay1_ko[0];

  /* Update for UnitDelay: '<S4>/Unit Delay' incorporates:
   *  Switch: '<S42>/Switch'
   *  UnitDelay: '<S1>/Unit Delay'
   */
  rtDW->UnitDelay_DSTATE_e[0] = rtb_UnitDelay1_ko[0];

  /* Update for UnitDelay: '<S1>/Unit Delay' incorporates:
   *  Switch: '<S42>/Switch'
   */
  rtDW->UnitDelay_DSTATE_k[1] = rtb_UnitDelay1_ko[1];

  /* Update for UnitDelay: '<S35>/UnitDelay1' incorporates:
   *  Switch: '<S42>/Switch'
   *  UnitDelay: '<S1>/Unit Delay'
   */
  rtDW->UnitDelay1_DSTATE_o[1] = rtb_UnitDelay1_ko[1];

  /* Update for UnitDelay: '<S4>/Unit Delay' incorporates:
   *  Switch: '<S42>/Switch'
   *  UnitDelay: '<S1>/Unit Delay'
   */
  rtDW->UnitDelay_DSTATE_e[1] = rtb_UnitDelay1_ko[1];

  /* If: '<S44>/If' */
  if (rtb_Sum2 == 0) {
    /* Update for IfAction SubSystem: '<S44>/Do_Calc' incorporates:
     *  ActionPort: '<S62>/Action Port'
     */
    /* Update for UnitDelay: '<S62>/Unit Delay' */
    rtDW->UnitDelay_DSTATE_lv = rtb_dz_cntTrnsDet;

    /* Update for UnitDelay: '<S62>/Unit Delay1' incorporates:
     *  Merge: '<S65>/Merge'
     */
    rtDW->UnitDelay1_DSTATE_jp = rtDW->Merge;

    /* Update for If: '<S65>/If' */
    switch (rtDW->If_ActiveSubsystem_k) {
     case 0:
      /* Update for IfAction SubSystem: '<S65>/speed_mode' incorporates:
       *  ActionPort: '<S79>/Action Port'
       */
      /* Update for UnitDelay: '<S79>/Unit Delay' incorporates:
       *  Sqrt: '<S78>/Sqrt1'
       */
      rtDW->UnitDelay_DSTATE_di = rtb_Gain_a;

      /* End of Update for SubSystem: '<S65>/speed_mode' */
      break;

     case 1:
      /* Update for IfAction SubSystem: '<S65>/torque_mode' incorporates:
       *  ActionPort: '<S80>/Action Port'
       */
      /* Update for Delay: '<S80>/Delay' incorporates:
       *  Sqrt: '<S78>/Sqrt1'
       */
      rtDW->icLoad_i = 0U;
      rtDW->Delay_DSTATE = rtb_Gain_a;

      /* End of Update for SubSystem: '<S65>/torque_mode' */
      break;
    }

    /* End of Update for If: '<S65>/If' */

    /* Update for UnitDelay: '<S66>/Unit Delay1' incorporates:
     *  Sqrt: '<S42>/Sqrt'
     */
    rtDW->UnitDelay1_DSTATE_pl = rtb_Sum1_p;

    /* Update for UnitDelay: '<S69>/Unit Delay' incorporates:
     *  Sum: '<S69>/Sum'
     */
    rtDW->UnitDelay_DSTATE_l = rtb_MathFunction2_n;

    /* Update for Delay: '<S70>/Resettable Delay' incorporates:
     *  Sum: '<S70>/Sum1'
     */
    rtDW->icLoad = 0U;
    rtDW->ResettableDelay_DSTATE = rtb_Gain_h;

    /* End of Update for SubSystem: '<S44>/Do_Calc' */
  }

  /* Update for UnitDelay: '<S96>/UnitDelay' incorporates:
   *  Switch: '<S76>/Switch2'
   */
  rtDW->UnitDelay_DSTATE_l5 = rtDW->Switch2;

  /* Update for UnitDelay: '<S87>/Unit Delay1' incorporates:
   *  Switch: '<S100>/Switch2'
   */
  rtDW->UnitDelay1_DSTATE_j = rtb_Add2_lk;

  /* Update for UnitDelay: '<S98>/Unit Delay' incorporates:
   *  Switch: '<S100>/Switch2'
   */
  rtDW->UnitDelay_DSTATE_b = rtb_Add2_lk;

  /* Update for UnitDelay: '<S103>/UnitDelay' incorporates:
   *  Switch: '<S68>/Switch'
   */
  rtDW->UnitDelay_DSTATE_er = rtDW->Switch_p;

  /* Update for UnitDelay: '<S88>/Unit Delay1' incorporates:
   *  Switch: '<S107>/Switch2'
   */
  rtDW->UnitDelay1_DSTATE_p = rtb_Divide1_oy;

  /* Update for UnitDelay: '<S105>/Unit Delay' incorporates:
   *  Switch: '<S107>/Switch2'
   */
  rtDW->UnitDelay_DSTATE_d = rtb_Divide1_oy;

  /* Update for UnitDelay: '<S45>/Unit Delay' */
  rtDW->UnitDelay_DSTATE_h3 = rtb_dz_cntTrnsDet;

  /* Update for UnitDelay: '<S7>/UnitDelay' */
  rtDW->UnitDelay_DSTATE_f = rtb_RelationalOperator;

  /* End of Outputs for SubSystem: '<Root>/PMSM_Controller' */

  /* Outport: '<Root>/n_Sector' */
  rtY->n_Sector = rtb_DataTypeConversion_e;

  /* Outport: '<Root>/n_MotError' */
  rtY->n_MotError = rtb_UnitDelay_n;

  /* Outport: '<Root>/f_MotAngle' incorporates:
   *  Switch: '<S1>/Switch'
   */
  rtY->f_MotAngle = rtb_r_cos_M1;

  /* Outport: '<Root>/f_MotRPM' incorporates:
   *  Switch: '<S20>/Switch2'
   */
  rtY->f_MotRPM = rtb_Switch3;

  /* Outport: '<Root>/n_hallStat' */
  rtY->n_hallStat = rtb_Add_h;

  /* Outport: '<Root>/n_FocMode' */
  rtY->n_FocMode = rtb_dz_cntTrnsDet;
}

/* Model initialize function */
void PMSM_Controller_initialize(RT_MODEL *const rtM)
{
  DW *rtDW = rtM->dwork;
  PrevZCX *rtPrevZCX = rtM->prevZCSigState;
  rtPrevZCX->ResettableDelay_Reset_ZCE_f = POS_ZCSIG;
  rtPrevZCX->PI_backCalc_fixdt1.ResettableDelay_Reset_ZCE = POS_ZCSIG;
  rtPrevZCX->PI_backCalc_fixdt_ig.ResettableDelay_Reset_ZCE = POS_ZCSIG;
  rtPrevZCX->PI_Speed.ResettableDelay_Reset_ZCE_fm = POS_ZCSIG;

  /* SystemInitialize for Atomic SubSystem: '<Root>/PMSM_Controller' */
  /* SystemInitialize for IfAction SubSystem: '<S20>/Raw_Motor_Speed_Estimation' */
  /* InitializeConditions for UnitDelay: '<S29>/UnitDelay2' */
  rtDW->UnitDelay2_DSTATE = 1000000U;

  /* SystemInitialize for SignalConversion generated from: '<S29>/delta_count' incorporates:
   *  Outport: '<S29>/delta_count'
   */
  rtDW->OutportBufferFordelta_count = 1000000U;

  /* End of SystemInitialize for SubSystem: '<S20>/Raw_Motor_Speed_Estimation' */

  /* SystemInitialize for IfAction SubSystem: '<S44>/Do_Calc' */
  /* Start for If: '<S65>/If' */
  rtDW->If_ActiveSubsystem_k = -1;

  /* InitializeConditions for Delay: '<S70>/Resettable Delay' */
  rtDW->icLoad = 1U;

  /* SystemInitialize for IfAction SubSystem: '<S65>/speed_mode' */
  /* SystemInitialize for Atomic SubSystem: '<S79>/PI_Speed' */
  PI_backCalc_fixdt_Init(&rtDW->PI_Speed);

  /* End of SystemInitialize for SubSystem: '<S79>/PI_Speed' */
  /* End of SystemInitialize for SubSystem: '<S65>/speed_mode' */

  /* SystemInitialize for IfAction SubSystem: '<S65>/torque_mode' */
  /* InitializeConditions for Delay: '<S80>/Delay' */
  rtDW->icLoad_i = 1U;

  /* End of SystemInitialize for SubSystem: '<S65>/torque_mode' */
  /* End of SystemInitialize for SubSystem: '<S44>/Do_Calc' */

  /* SystemInitialize for IfAction SubSystem: '<S45>/CurrentLoop' */
  /* SystemInitialize for Atomic SubSystem: '<S85>/PI_backCalc_fixdt' */
  PI_backCalc_fixdt_g_Init(&rtDW->PI_backCalc_fixdt_ig);

  /* End of SystemInitialize for SubSystem: '<S85>/PI_backCalc_fixdt' */

  /* SystemInitialize for Atomic SubSystem: '<S85>/PI_backCalc_fixdt1' */
  PI_backCalc_fixdt_g_Init(&rtDW->PI_backCalc_fixdt1);

  /* End of SystemInitialize for SubSystem: '<S85>/PI_backCalc_fixdt1' */
  /* End of SystemInitialize for SubSystem: '<S45>/CurrentLoop' */
  /* End of SystemInitialize for SubSystem: '<Root>/PMSM_Controller' */
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */