#ifndef _ADC_H__
#define _ADC_H__
#include "bsp/bsp.h"
#include "libs/os.h"

/*
inserted ADC 由timer0 ch3触发，
注意：adc所有外部触发都是下降沿触发 
*/
#define MOTOR_TEMP_CHAN ADC_CHANNEL_0
#define HANDLERBAR_CHAN ADC_CHANNEL_1 //转把信号
#define VBUS_V_CHAN 	ADC_CHANNEL_2
#define W_PHASE_V_CHAN  ADC_CHANNEL_3
#define V_PHASE_V_CHAN  ADC_CHANNEL_4
#define U_PHASE_V_CHAN  ADC_CHANNEL_5
#define W_PHASE_I_CHAN  ADC_CHANNEL_6
#define V_PHASE_I_CHAN  ADC_CHANNEL_7
#define U_PHASE_I_CHAN  ADC_CHANNEL_8
#define VBUS_I_CHAN     ADC_CHANNEL_9
#define ISQ2_OFFSET 10
#define ISO3_OFFSET 15
#define IL_OFFSET   20

#define ADC_RANK_CHANNEL(c1, c2) ((c1)<<ISQ2_OFFSET | (c2)<<ISO3_OFFSET | 1<<IL_OFFSET)

static u32 adc_rank_channels[6] = {
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN, U_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN, V_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN, V_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(V_PHASE_I_CHAN, W_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(U_PHASE_I_CHAN, W_PHASE_I_CHAN),
	ADC_RANK_CHANNEL(W_PHASE_I_CHAN, U_PHASE_I_CHAN),
};


#define PHASE_I_ADC ADC1
static u32 volatile * adc_phase_reg1[6] = {
	&ADC_IDATA2(PHASE_I_ADC),
	&ADC_IDATA3(PHASE_I_ADC),
	&ADC_IDATA2(PHASE_I_ADC),
	&ADC_IDATA3(PHASE_I_ADC),
	&ADC_IDATA2(PHASE_I_ADC),
	&ADC_IDATA3(PHASE_I_ADC),
};
static u32 volatile * adc_phase_reg2[6] = {
	&ADC_IDATA3(PHASE_I_ADC),
	&ADC_IDATA2(PHASE_I_ADC),
	&ADC_IDATA3(PHASE_I_ADC),
	&ADC_IDATA2(PHASE_I_ADC),
	&ADC_IDATA3(PHASE_I_ADC),
	&ADC_IDATA2(PHASE_I_ADC),
};
#define VBUS_I_ADC ADC0
static u32 volatile * adc_vbus_reg1[6] = {
	&ADC_IDATA2(VBUS_I_ADC),
	&ADC_IDATA3(VBUS_I_ADC),
	&ADC_IDATA2(VBUS_I_ADC),
	&ADC_IDATA3(VBUS_I_ADC),
	&ADC_IDATA2(VBUS_I_ADC),
	&ADC_IDATA3(VBUS_I_ADC),
};
static u32 volatile * adc_vbus_reg2[6] = {
	&ADC_IDATA3(VBUS_I_ADC),
	&ADC_IDATA2(VBUS_I_ADC),
	&ADC_IDATA3(VBUS_I_ADC),
	&ADC_IDATA2(VBUS_I_ADC),
	&ADC_IDATA3(VBUS_I_ADC),
	&ADC_IDATA2(VBUS_I_ADC),
};

void __inline adc_phase_current_read(u8 sector, u32 *v1, u32 *v2) {
	*v1 = (*adc_phase_reg1[sector]) << 4;
	*v2 = (*adc_phase_reg2[sector]) << 4;
}

u32 __inline adc_phase_read_1(u8 sector) {
	return (*adc_phase_reg1[sector]) << 4;
}

void __inline adc_vbus_current_read(u8 sector, u32 *v1, u32 *v2) {
	*v1 = (*adc_vbus_reg1[sector]) << 4;
	*v2 = (*adc_vbus_reg2[sector]) << 4;
}

u32 __inline adc_vbus_read_1(u8 sector) {
	return (*adc_vbus_reg1[sector]) << 4;
}


void __inline adc_phase_inserted_config(u8 sector) {
	ADC_ISQ(ADC1) = adc_rank_channels[sector];
}

#define ADC_TRIGGER_PHASE ADC0_1_EXTTRIG_INSERTED_T0_CH3
#define ADC_TRIGGER_VBUS ADC0_1_EXTTRIG_INSERTED_T1_CH0


void __inline adc_config_trigger(u32 trigger) {
	ADC_CTL1(ADC0) &= ~((uint32_t)ADC_CTL1_ETSIC);
	ADC_CTL1(ADC0) |= (uint32_t)trigger;
	ADC_CTL1(ADC1) &= ~((uint32_t)ADC_CTL1_ETSIC);
	ADC_CTL1(ADC1) |= (uint32_t)trigger;
}

bool __inline adc_is_trigged_vbus(void) {
	if (ADC_CTL1(ADC0) & ADC_TRIGGER_VBUS == ADC_TRIGGER_VBUS) {
		return true;
	}
	return false;
}

/* insert len fixed to 2(IL=1), ISQ2 >> ISQ3*/
static __inline__ void adc1_update_insert_sample_rank(u8 channel1, u8 channel2) {
    u32 isq;
        
    isq = ADC_ISQ(ADC1);
    isq &= 0xFFF0000;
    isq |= (channel1 << 10) | (channel2 << 15);
    ADC_ISQ(ADC1) = isq;
}

static __inline__ void adc1_update_insert_sample_time(uint8_t adc_channel , uint32_t sample_time)
{
    uint32_t sampt;
    /* ADC sampling time config */  
    if(adc_channel < 10U){
        sampt = ADC_SAMPT1(ADC1);
        sampt &= ~((u32)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
        sampt |= (u32) sample_time << (3U*adc_channel);
        ADC_SAMPT1(ADC1) = sampt;
    }else if(adc_channel < 18U){
        sampt = ADC_SAMPT0(ADC1);
        sampt &= ~((u32)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
        sampt |= ((u32)sample_time << (3U*(adc_channel-10U)));
        ADC_SAMPT0(ADC1) = sampt;
    }
}


void adc_init(void);
s32 adc_sample_regular_channel(int chan, int times);
void adc_start_insert_convert(void);

#endif /* _ADC_H__ */