/* * File: Subsystem.c * * Code generated for Simulink model 'Subsystem'. * * Model version : 1.2 * Simulink Coder version : 9.4 (R2020b) 29-Jul-2020 * C/C++ source code generated on : Fri Oct 14 20:06:32 2022 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex-M * Code generation objectives: * 1. Execution efficiency * 2. RAM efficiency * Validation result: Not run */ #include "Subsystem.h" /* Block signals and states (default storage) */ DW rtDW; /* External inputs (root inport signals with default storage) */ ExtU rtU; /* External outputs (root outports fed by signals with default storage) */ ExtY rtY; /* Model step function */ void Subsystem_step(void) { real_T rtb_DiscreteTimeIntegrator; /* Outputs for Atomic SubSystem: '/Subsystem' */ /* DiscreteIntegrator: '/Discrete-Time Integrator' */ rtb_DiscreteTimeIntegrator = rtDW.DiscreteTimeIntegrator_DSTATE; /* Outport: '/target' incorporates: * DiscreteIntegrator: '/Discrete-Time Integrator1' */ rtY.target = rtDW.DiscreteTimeIntegrator1_DSTATE; /* Update for DiscreteIntegrator: '/Discrete-Time Integrator' incorporates: * DiscreteIntegrator: '/Discrete-Time Integrator1' * Gain: '/Gain' * Gain: '/Gain1' * Inport: '/in' * Inport: '/time' * Math: '/Math Function' * Product: '/Product' * Product: '/Product1' * Sum: '/Sum' * Sum: '/Sum1' */ rtDW.DiscreteTimeIntegrator_DSTATE += ((rtDW.DiscreteTimeIntegrator1_DSTATE - rtU.in) * -(rtU.time * rtU.time) + -2.0 * rtU.time * rtDW.DiscreteTimeIntegrator_DSTATE) * 6.25E-5; /* Update for DiscreteIntegrator: '/Discrete-Time Integrator1' */ rtDW.DiscreteTimeIntegrator1_DSTATE += 6.25E-5 * rtb_DiscreteTimeIntegrator; /* End of Outputs for SubSystem: '/Subsystem' */ /* Outport: '/diff' */ rtY.diff = rtb_DiscreteTimeIntegrator; } /* Model initialize function */ void Subsystem_initialize(void) { /* (no initialization code required) */ } /* * File trailer for generated code. * * [EOF] */