/*

 * File: PMSM_Controller.c

 *

 * Code generated for Simulink model 'PMSM_Controller'.

 *

 * Model version                  : 1.1245

 * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020

 * C/C++ source code generated on : Thu Apr  7 15:23:34 2022

 *

 * Target selection: ert.tlc

 * Embedded hardware selection: ARM Compatible->ARM Cortex-M

 * Code generation objectives:

 *    1. Execution efficiency

 *    2. RAM efficiency

 * Validation result: Not run

 */



#include "PMSM_Controller.h"



/* Named constants for Chart: '<S4>/Control_Mode_Manager' */

#define IN_ACTIVE                      ((uint8_T)1U)

#define IN_NO_ACTIVE_CHILD             ((uint8_T)0U)

#define IN_OPEN                        ((uint8_T)2U)

#define IN_SPEED_MODE                  ((uint8_T)1U)

#define IN_TORQUE_MODE                 ((uint8_T)2U)

#define OPEN_MODE                      ((uint8_T)0U)

#define SPD_MODE                       ((uint8_T)1U)

#define TRQ_MODE                       ((uint8_T)2U)

#ifndef UCHAR_MAX

#include <limits.h>

#endif



#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) )

#error Code was generated for compiler with different sized uchar/char. \

Consider adjusting Test hardware word size settings on the \

Hardware Implementation pane to match your compiler word sizes as \

defined in limits.h of the compiler. Alternatively, you can \

select the Test hardware is the same as production hardware option and \

select the Enable portable word sizes option on the Code Generation > \

Verification pane for ERT based targets, which will disable the \

preprocessor word size checks.

#endif



#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) )

#error Code was generated for compiler with different sized ushort/short. \

Consider adjusting Test hardware word size settings on the \

Hardware Implementation pane to match your compiler word sizes as \

defined in limits.h of the compiler. Alternatively, you can \

select the Test hardware is the same as production hardware option and \

select the Enable portable word sizes option on the Code Generation > \

Verification pane for ERT based targets, which will disable the \

preprocessor word size checks.

#endif



#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) )

#error Code was generated for compiler with different sized uint/int. \

Consider adjusting Test hardware word size settings on the \

Hardware Implementation pane to match your compiler word sizes as \

defined in limits.h of the compiler. Alternatively, you can \

select the Test hardware is the same as production hardware option and \

select the Enable portable word sizes option on the Code Generation > \

Verification pane for ERT based targets, which will disable the \

preprocessor word size checks.

#endif



#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) )

#error Code was generated for compiler with different sized ulong/long. \

Consider adjusting Test hardware word size settings on the \

Hardware Implementation pane to match your compiler word sizes as \

defined in limits.h of the compiler. Alternatively, you can \

select the Test hardware is the same as production hardware option and \

select the Enable portable word sizes option on the Code Generation > \

Verification pane for ERT based targets, which will disable the \

preprocessor word size checks.

#endif



/* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */

static uint16_T plook_u16s16_evencka(int16_T u, int16_T bp0, uint16_T bpSpace,

  uint32_T maxIndex);

static uint8_T plook_u8u16_evencka(uint16_T u, uint16_T bp0, uint16_T bpSpace,

  uint32_T maxIndex);

static void Counter_Init(DW_Counter *localDW, uint16_T rtp_z_cntInit);

static uint16_T Counter(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst,

  DW_Counter *localDW);

static boolean_T either_edge(boolean_T rtu_u, DW_either_edge *localDW);

static void Debounce_Filter_Init(DW_Debounce_Filter *localDW);

static void Debounce_Filter(boolean_T rtu_u, uint16_T rtu_tAcv, uint16_T

  rtu_tDeacv, boolean_T *rty_y, DW_Debounce_Filter *localDW);

static void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T

  rty_y[2], DW_Low_Pass_Filter *localDW);

static void PI_backCalc_fixdt_Init(DW_PI_backCalc_fixdt *localDW);

static void PI_backCalc_fixdt(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I,

  int16_T rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T

  rtu_ext_limProt, uint8_T rtu_reset, int16_T *rty_pi_out, const

  ConstB_PI_backCalc_fixdt *localC, DW_PI_backCalc_fixdt *localDW,

  ZCE_PI_backCalc_fixdt *localZCE);

static void pi_speed_Init(DW_pi_speed *localDW);

static int16_T pi_speed(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I, int16_T

  rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_ext_limProt,

  uint8_T rtu_reset, const ConstB_pi_speed *localC, DW_pi_speed *localDW,

  ZCE_pi_speed *localZCE);

static uint16_T plook_u16s16_evencka(int16_T u, int16_T bp0, uint16_T bpSpace,

  uint32_T maxIndex)

{

  uint16_T bpIndex;



  /* Prelookup - Index only

     Index Search method: 'even'

     Extrapolation method: 'Clip'

     Use previous index: 'off'

     Use last breakpoint for index at or above upper limit: 'on'

     Remove protection against out-of-range input in generated code: 'off'

   */

  if (u <= bp0) {

    bpIndex = 0U;

  } else {

    bpIndex = (uint16_T)((uint32_T)(uint16_T)(u - bp0) / bpSpace);

    if (bpIndex < maxIndex) {

    } else {

      bpIndex = (uint16_T)maxIndex;

    }

  }



  return bpIndex;

}



static uint8_T plook_u8u16_evencka(uint16_T u, uint16_T bp0, uint16_T bpSpace,

  uint32_T maxIndex)

{

  uint16_T fbpIndex;

  uint8_T bpIndex;



  /* Prelookup - Index only

     Index Search method: 'even'

     Extrapolation method: 'Clip'

     Use previous index: 'off'

     Use last breakpoint for index at or above upper limit: 'on'

     Remove protection against out-of-range input in generated code: 'off'

   */

  if (u <= bp0) {

    bpIndex = 0U;

  } else {

    fbpIndex = (uint16_T)((uint32_T)(uint16_T)((uint32_T)u - bp0) / bpSpace);

    if (fbpIndex < maxIndex) {

      bpIndex = (uint8_T)fbpIndex;

    } else {

      bpIndex = (uint8_T)maxIndex;

    }

  }



  return bpIndex;

}



/*

 * System initialize for atomic system:

 *    '<S41>/Counter'

 *    '<S40>/Counter'

 */

static void Counter_Init(DW_Counter *localDW, uint16_T rtp_z_cntInit)

{

  /* InitializeConditions for UnitDelay: '<S46>/UnitDelay' */

  localDW->UnitDelay_DSTATE = rtp_z_cntInit;

}



/*

 * Output and update for atomic system:

 *    '<S41>/Counter'

 *    '<S40>/Counter'

 */

static uint16_T Counter(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst,

  DW_Counter *localDW)

{

  uint16_T rty_cnt_0;

  uint16_T rtu_rst_0;



  /* Switch: '<S46>/Switch1' incorporates:

   *  Constant: '<S46>/Constant23'

   *  UnitDelay: '<S46>/UnitDelay'

   */

  if (rtu_rst) {

    rtu_rst_0 = 0U;

  } else {

    rtu_rst_0 = localDW->UnitDelay_DSTATE;

  }



  /* End of Switch: '<S46>/Switch1' */



  /* Sum: '<S45>/Sum1' */

  rty_cnt_0 = (uint16_T)((uint32_T)rtu_inc + rtu_rst_0);



  /* MinMax: '<S45>/MinMax' */

  if (rty_cnt_0 < rtu_max) {

    /* Update for UnitDelay: '<S46>/UnitDelay' */

    localDW->UnitDelay_DSTATE = rty_cnt_0;

  } else {

    /* Update for UnitDelay: '<S46>/UnitDelay' */

    localDW->UnitDelay_DSTATE = rtu_max;

  }



  /* End of MinMax: '<S45>/MinMax' */

  return rty_cnt_0;

}



/*

 * Output and update for atomic system:

 *    '<S37>/either_edge'

 *    '<S36>/either_edge'

 */

static boolean_T either_edge(boolean_T rtu_u, DW_either_edge *localDW)

{

  boolean_T rty_y_0;



  /* RelationalOperator: '<S42>/Relational Operator' incorporates:

   *  UnitDelay: '<S42>/UnitDelay'

   */

  rty_y_0 = (rtu_u != localDW->UnitDelay_DSTATE);



  /* Update for UnitDelay: '<S42>/UnitDelay' */

  localDW->UnitDelay_DSTATE = rtu_u;

  return rty_y_0;

}



/* System initialize for atomic system: '<S36>/Debounce_Filter' */

static void Debounce_Filter_Init(DW_Debounce_Filter *localDW)

{

  /* SystemInitialize for IfAction SubSystem: '<S37>/Qualification' */

  /* SystemInitialize for Atomic SubSystem: '<S41>/Counter' */

  Counter_Init(&localDW->Counter_f, 0);



  /* End of SystemInitialize for SubSystem: '<S41>/Counter' */

  /* End of SystemInitialize for SubSystem: '<S37>/Qualification' */



  /* SystemInitialize for IfAction SubSystem: '<S37>/Dequalification' */

  /* SystemInitialize for Atomic SubSystem: '<S40>/Counter' */

  Counter_Init(&localDW->Counter_d, 0);



  /* End of SystemInitialize for SubSystem: '<S40>/Counter' */

  /* End of SystemInitialize for SubSystem: '<S37>/Dequalification' */

}



/* Output and update for atomic system: '<S36>/Debounce_Filter' */

static void Debounce_Filter(boolean_T rtu_u, uint16_T rtu_tAcv, uint16_T

  rtu_tDeacv, boolean_T *rty_y, DW_Debounce_Filter *localDW)

{

  uint16_T rtb_Sum1_n;

  boolean_T rtb_RelationalOperator_e;



  /* Outputs for Atomic SubSystem: '<S37>/either_edge' */

  rtb_RelationalOperator_e = either_edge(rtu_u, &localDW->either_edge_j);



  /* End of Outputs for SubSystem: '<S37>/either_edge' */



  /* If: '<S37>/If2' incorporates:

   *  Constant: '<S40>/Constant6'

   *  Constant: '<S41>/Constant6'

   *  Inport: '<S39>/yPrev'

   *  Logic: '<S37>/Logical Operator1'

   *  Logic: '<S37>/Logical Operator2'

   *  Logic: '<S37>/Logical Operator3'

   *  Logic: '<S37>/Logical Operator4'

   *  UnitDelay: '<S37>/UnitDelay'

   */

  if (rtu_u && (!localDW->UnitDelay_DSTATE)) {

    /* Outputs for IfAction SubSystem: '<S37>/Qualification' incorporates:

     *  ActionPort: '<S41>/Action Port'

     */

    /* Outputs for Atomic SubSystem: '<S41>/Counter' */

    rtb_Sum1_n = Counter(1, rtu_tAcv, rtb_RelationalOperator_e,

                         &localDW->Counter_f);



    /* End of Outputs for SubSystem: '<S41>/Counter' */



    /* Switch: '<S41>/Switch2' incorporates:

     *  Constant: '<S41>/Constant6'

     *  RelationalOperator: '<S41>/Relational Operator2'

     */

    *rty_y = ((rtb_Sum1_n > rtu_tAcv) || localDW->UnitDelay_DSTATE);



    /* End of Outputs for SubSystem: '<S37>/Qualification' */

  } else if ((!rtu_u) && localDW->UnitDelay_DSTATE) {

    /* Outputs for IfAction SubSystem: '<S37>/Dequalification' incorporates:

     *  ActionPort: '<S40>/Action Port'

     */

    /* Outputs for Atomic SubSystem: '<S40>/Counter' */

    rtb_Sum1_n = Counter(1, rtu_tDeacv, rtb_RelationalOperator_e,

                         &localDW->Counter_d);



    /* End of Outputs for SubSystem: '<S40>/Counter' */



    /* Switch: '<S40>/Switch2' incorporates:

     *  Constant: '<S40>/Constant6'

     *  RelationalOperator: '<S40>/Relational Operator2'

     */

    *rty_y = ((rtb_Sum1_n <= rtu_tDeacv) && localDW->UnitDelay_DSTATE);



    /* End of Outputs for SubSystem: '<S37>/Dequalification' */

  } else {

    /* Outputs for IfAction SubSystem: '<S37>/Default' incorporates:

     *  ActionPort: '<S39>/Action Port'

     */

    *rty_y = localDW->UnitDelay_DSTATE;



    /* End of Outputs for SubSystem: '<S37>/Default' */

  }



  /* End of If: '<S37>/If2' */



  /* Update for UnitDelay: '<S37>/UnitDelay' */

  localDW->UnitDelay_DSTATE = *rty_y;

}



/* Output and update for atomic system: '<S47>/Low_Pass_Filter' */

static void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T

  rty_y[2], DW_Low_Pass_Filter *localDW)

{

  int32_T tmp;



  /* Sum: '<S56>/Sum2' incorporates:

   *  UnitDelay: '<S56>/UnitDelay1'

   */

  tmp = rtu_u[0] - localDW->UnitDelay1_DSTATE[0];

  if (tmp > 32767) {

    tmp = 32767;

  } else {

    if (tmp < -32768) {

      tmp = -32768;

    }

  }



  /* Product: '<S56>/Divide3' incorporates:

   *  Sum: '<S56>/Sum2'

   */

  rty_y[0] = (int16_T)((rtu_coef * tmp) >> 16);



  /* Sum: '<S56>/Sum3' incorporates:

   *  UnitDelay: '<S56>/UnitDelay1'

   */

  rty_y[0] += localDW->UnitDelay1_DSTATE[0];



  /* Update for UnitDelay: '<S56>/UnitDelay1' incorporates:

   *  Sum: '<S56>/Sum3'

   */

  localDW->UnitDelay1_DSTATE[0] = rty_y[0];



  /* Sum: '<S56>/Sum2' incorporates:

   *  UnitDelay: '<S56>/UnitDelay1'

   */

  tmp = rtu_u[1] - localDW->UnitDelay1_DSTATE[1];

  if (tmp > 32767) {

    tmp = 32767;

  } else {

    if (tmp < -32768) {

      tmp = -32768;

    }

  }



  /* Product: '<S56>/Divide3' incorporates:

   *  Sum: '<S56>/Sum2'

   */

  rty_y[1] = (int16_T)((rtu_coef * tmp) >> 16);



  /* Sum: '<S56>/Sum3' incorporates:

   *  UnitDelay: '<S56>/UnitDelay1'

   */

  rty_y[1] += localDW->UnitDelay1_DSTATE[1];



  /* Update for UnitDelay: '<S56>/UnitDelay1' incorporates:

   *  Sum: '<S56>/Sum3'

   */

  localDW->UnitDelay1_DSTATE[1] = rty_y[1];

}



/*

 * System initialize for atomic system:

 *    '<S60>/PI_iq'

 *    '<S59>/PI_id'

 */

static void PI_backCalc_fixdt_Init(DW_PI_backCalc_fixdt *localDW)

{

  /* InitializeConditions for Delay: '<S67>/Resettable Delay' */

  localDW->icLoad = 1U;

}



/*

 * Output and update for atomic system:

 *    '<S60>/PI_iq'

 *    '<S59>/PI_id'

 */

static void PI_backCalc_fixdt(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I,

  int16_T rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T

  rtu_ext_limProt, uint8_T rtu_reset, int16_T *rty_pi_out, const

  ConstB_PI_backCalc_fixdt *localC, DW_PI_backCalc_fixdt *localDW,

  ZCE_PI_backCalc_fixdt *localZCE)

{

  int64_T tmp;

  int32_T rtb_Divide4_h;

  int32_T rtb_Sum1_j;



  /* Product: '<S65>/Divide4' */

  rtb_Divide4_h = (rtu_err * rtu_P) >> 6;



  /* Delay: '<S67>/Resettable Delay' incorporates:

   *  DataTypeConversion: '<S67>/Data Type Conversion2'

   */

  if ((rtu_reset > 0) && (localZCE->ResettableDelay_Reset_ZCE_p != POS_ZCSIG)) {

    localDW->icLoad = 1U;

  }



  localZCE->ResettableDelay_Reset_ZCE_p = (ZCSigState)(rtu_reset > 0);

  if (localDW->icLoad != 0) {

    localDW->ResettableDelay_DSTATE = localC->DataTypeConversion2;

  }



  /* Product: '<S65>/Divide1' incorporates:

   *  Product: '<S65>/Divide4'

   */

  tmp = ((int64_T)rtb_Divide4_h * rtu_I) >> 10;

  if (tmp > 2147483647LL) {

    tmp = 2147483647LL;

  } else {

    if (tmp < -2147483648LL) {

      tmp = -2147483648LL;

    }

  }



  /* Sum: '<S65>/Sum2' incorporates:

   *  Product: '<S65>/Divide1'

   *  UnitDelay: '<S65>/UnitDelay'

   */

  tmp = (((int64_T)rtu_ext_limProt << 3) + (int32_T)tmp) +

    localDW->UnitDelay_DSTATE;

  if (tmp > 2147483647LL) {

    tmp = 2147483647LL;

  } else {

    if (tmp < -2147483648LL) {

      tmp = -2147483648LL;

    }

  }



  /* Sum: '<S67>/Sum1' incorporates:

   *  Delay: '<S67>/Resettable Delay'

   *  Sum: '<S65>/Sum2'

   */

  rtb_Sum1_j = ((int32_T)tmp >> 2) + localDW->ResettableDelay_DSTATE;



  /* Sum: '<S65>/Sum6' incorporates:

   *  DataTypeConversion: '<S67>/Data Type Conversion1'

   *  Product: '<S65>/Divide4'

   *  Sum: '<S67>/Sum1'

   */

  tmp = ((int64_T)(rtb_Sum1_j >> 2) << 4) + rtb_Divide4_h;

  if (tmp > 2147483647LL) {

    tmp = 2147483647LL;

  } else {

    if (tmp < -2147483648LL) {

      tmp = -2147483648LL;

    }

  }



  /* Switch: '<S68>/Switch2' incorporates:

   *  RelationalOperator: '<S68>/LowerRelop1'

   *  RelationalOperator: '<S68>/UpperRelop'

   *  Sum: '<S65>/Sum6'

   *  Switch: '<S68>/Switch'

   */

  if ((int32_T)tmp > (rtu_satMax << 4)) {

    *rty_pi_out = rtu_satMax;

  } else if ((int32_T)tmp < (rtu_satMin << 4)) {

    /* Switch: '<S68>/Switch' */

    *rty_pi_out = rtu_satMin;

  } else {

    *rty_pi_out = (int16_T)((int32_T)tmp >> 4);

  }



  /* End of Switch: '<S68>/Switch2' */



  /* Update for UnitDelay: '<S65>/UnitDelay' incorporates:

   *  Product: '<S65>/Divide2'

   *  Sum: '<S65>/Sum3'

   *  Sum: '<S65>/Sum6'

   */

  localDW->UnitDelay_DSTATE = (int32_T)(((int64_T)((*rty_pi_out << 4) - (int32_T)

    tmp) * rtu_Kb) >> 10);



  /* Update for Delay: '<S67>/Resettable Delay' incorporates:

   *  Sum: '<S67>/Sum1'

   */

  localDW->icLoad = 0U;

  localDW->ResettableDelay_DSTATE = rtb_Sum1_j;

}



/* System initialize for atomic system: '<S79>/pi_speed' */

static void pi_speed_Init(DW_pi_speed *localDW)

{

  /* InitializeConditions for Delay: '<S83>/Resettable Delay' */

  localDW->icLoad = 1U;

}



/* Output and update for atomic system: '<S79>/pi_speed' */

static int16_T pi_speed(int16_T rtu_err, int16_T rtu_P, int16_T rtu_I, int16_T

  rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_ext_limProt,

  uint8_T rtu_reset, const ConstB_pi_speed *localC, DW_pi_speed *localDW,

  ZCE_pi_speed *localZCE)

{

  int16_T rty_pi_out_0;

  int64_T tmp;

  int32_T rtb_Divide4_jw;

  int32_T rtb_Sum1_d;



  /* Product: '<S82>/Divide4' */

  rtb_Divide4_jw = (rtu_err * rtu_P) >> 2;



  /* Delay: '<S83>/Resettable Delay' incorporates:

   *  DataTypeConversion: '<S83>/Data Type Conversion2'

   */

  if ((rtu_reset > 0) && (localZCE->ResettableDelay_Reset_ZCE != POS_ZCSIG)) {

    localDW->icLoad = 1U;

  }



  localZCE->ResettableDelay_Reset_ZCE = (ZCSigState)(rtu_reset > 0);

  if (localDW->icLoad != 0) {

    localDW->ResettableDelay_DSTATE = localC->DataTypeConversion2;

  }



  /* Product: '<S82>/Divide1' incorporates:

   *  Product: '<S82>/Divide4'

   */

  tmp = ((int64_T)rtb_Divide4_jw * rtu_I) >> 10;

  if (tmp > 2147483647LL) {

    tmp = 2147483647LL;

  } else {

    if (tmp < -2147483648LL) {

      tmp = -2147483648LL;

    }

  }



  /* Sum: '<S82>/Sum2' incorporates:

   *  Product: '<S82>/Divide1'

   *  UnitDelay: '<S82>/UnitDelay'

   */

  tmp = (((int64_T)(int32_T)tmp + rtu_ext_limProt) + ((int64_T)

          localDW->UnitDelay_DSTATE << 2)) >> 2;

  if (tmp > 2147483647LL) {

    tmp = 2147483647LL;

  } else {

    if (tmp < -2147483648LL) {

      tmp = -2147483648LL;

    }

  }



  /* Sum: '<S83>/Sum1' incorporates:

   *  Delay: '<S83>/Resettable Delay'

   *  Sum: '<S82>/Sum2'

   */

  rtb_Sum1_d = (int32_T)tmp + localDW->ResettableDelay_DSTATE;



  /* Sum: '<S82>/Sum6' incorporates:

   *  DataTypeConversion: '<S83>/Data Type Conversion1'

   *  Product: '<S82>/Divide4'

   *  Sum: '<S83>/Sum1'

   */

  tmp = ((int64_T)(rtb_Sum1_d >> 2) << 4) + rtb_Divide4_jw;

  if (tmp > 2147483647LL) {

    tmp = 2147483647LL;

  } else {

    if (tmp < -2147483648LL) {

      tmp = -2147483648LL;

    }

  }



  /* Switch: '<S84>/Switch2' incorporates:

   *  RelationalOperator: '<S84>/LowerRelop1'

   *  RelationalOperator: '<S84>/UpperRelop'

   *  Sum: '<S82>/Sum6'

   *  Switch: '<S84>/Switch'

   */

  if ((int32_T)tmp > (rtu_satMax << 4)) {

    rty_pi_out_0 = rtu_satMax;

  } else if ((int32_T)tmp < (rtu_satMin << 4)) {

    /* Switch: '<S84>/Switch' */

    rty_pi_out_0 = rtu_satMin;

  } else {

    rty_pi_out_0 = (int16_T)((int32_T)tmp >> 4);

  }



  /* End of Switch: '<S84>/Switch2' */



  /* Update for UnitDelay: '<S82>/UnitDelay' incorporates:

   *  Product: '<S82>/Divide2'

   *  Sum: '<S82>/Sum3'

   *  Sum: '<S82>/Sum6'

   */

  localDW->UnitDelay_DSTATE = (int32_T)(((int64_T)((rty_pi_out_0 << 4) -

    (int32_T)tmp) * rtu_Kb) >> 12);



  /* Update for Delay: '<S83>/Resettable Delay' incorporates:

   *  Sum: '<S83>/Sum1'

   */

  localDW->icLoad = 0U;

  localDW->ResettableDelay_DSTATE = rtb_Sum1_d;

  return rty_pi_out_0;

}



/* Model step function */

void PMSM_Controller_step(RT_MODEL *const rtM)

{

  DW *rtDW = rtM->dwork;

  PrevZCX *rtPrevZCX = rtM->prevZCSigState;

  ExtU *rtU = (ExtU *) rtM->inputs;

  ExtY *rtY = (ExtY *) rtM->outputs;

  int32_T rtb_Add2_l;

  int32_T rtb_Divide;

  int32_T rtb_Gain1;

  int32_T rtb_MultiportSwitch_idx_0;

  uint32_T qY;

  uint32_T tmp;

  int16_T rtb_DataTypeConversion[2];

  int16_T rtb_TmpSignalConversionAtLow_Pa[2];

  int16_T rtb_Abs5;

  int16_T rtb_Abs5_h;

  int16_T rtb_Divide1_fi;

  int16_T rtb_Gain4;

  int16_T rtb_Max;

  int16_T rtb_Sign;

  int16_T rtb_Switch2_ip;

  int16_T rtb_Switch3_c;

  int16_T rtb_Switch_b;

  int16_T rtb_Switch_oi;

  uint16_T rtb_LogicalOperator3;

  int8_T UnitDelay3;

  int8_T rtb_Sum2;

  int8_T rtb_Sum2_tmp;

  uint8_T rtb_Add_cr;

  uint8_T rtb_DataTypeConversion1_c;

  uint8_T rtb_DataTypeConversion_m;

  uint8_T rtb_Switch2_fu;

  uint8_T rtb_UnitDelay;

  uint8_T rtb_z_ctrlMod;

  boolean_T rtb_Equal_k;

  boolean_T rtb_LogicalOperator;

  boolean_T rtb_LogicalOperator2;

  boolean_T rtb_LogicalOperator4;

  boolean_T rtb_RelationalOperator4_f;

  boolean_T rtb_n_commDeacv;



  /* Outputs for Atomic SubSystem: '<Root>/PMSM_Controller' */

  /* Sum: '<S7>/Sum3' incorporates:

   *  UnitDelay: '<S7>/UnitDelay1'

   */

  qY = rtDW->UnitDelay1_DSTATE + /*MW:OvSatOk*/ 1U;

  if (rtDW->UnitDelay1_DSTATE + 1U < 1U) {

    qY = MAX_uint32_T;

  }



  /* RelationalOperator: '<S2>/Equal' incorporates:

   *  Constant: '<S2>/Constant1'

   *  Math: '<S2>/Rem'

   *  Sum: '<S7>/Sum3'

   */

  rtb_Equal_k = (qY % 20U == 0U);



  /* Logic: '<S9>/Edge_Detect' incorporates:

   *  Delay: '<S9>/Delay'

   *  Delay: '<S9>/Delay1'

   *  Delay: '<S9>/Delay2'

   *  Inport: '<Root>/hall_a'

   *  Inport: '<Root>/hall_b'

   *  Inport: '<Root>/hall_c'

   */

  rtb_LogicalOperator = (boolean_T)((rtU->hall_a != 0) ^ (rtDW->Delay_DSTATE !=

    0) ^ (rtU->hall_b != 0) ^ (rtDW->Delay1_DSTATE != 0) ^ (rtU->hall_c != 0)) ^

    (rtDW->Delay2_DSTATE != 0);



  /* Sum: '<S11>/Add' incorporates:

   *  Gain: '<S11>/Gain'

   *  Gain: '<S11>/Gain1'

   *  Inport: '<Root>/hall_a'

   *  Inport: '<Root>/hall_b'

   *  Inport: '<Root>/hall_c'

   */

  rtb_Add_cr = (uint8_T)((uint32_T)(uint8_T)((uint32_T)(uint8_T)(rtU->hall_c <<

    2) + (uint8_T)(rtU->hall_b << 1)) + rtU->hall_a);



  /* If: '<S3>/If2' incorporates:

   *  If: '<S12>/If2'

   *  Inport: '<S17>/z_counterRawPrev'

   *  UnitDelay: '<S12>/UnitDelay3'

   */

  if (rtb_LogicalOperator) {

    /* Outputs for IfAction SubSystem: '<S3>/Direction_Detection' incorporates:

     *  ActionPort: '<S8>/Action Port'

     */

    /* UnitDelay: '<S8>/UnitDelay3' */

    UnitDelay3 = rtDW->Switch2_i;



    /* End of Outputs for SubSystem: '<S3>/Direction_Detection' */



    /* Selector: '<S11>/Selector' incorporates:

     *  Constant: '<S11>/vec_hallToPos'

     */

    rtb_Sum2_tmp = rtConstP.vec_hallToPos_Value[rtb_Add_cr];



    /* Outputs for IfAction SubSystem: '<S3>/Direction_Detection' incorporates:

     *  ActionPort: '<S8>/Action Port'

     */

    /* Sum: '<S8>/Sum2' incorporates:

     *  Constant: '<S11>/vec_hallToPos'

     *  Selector: '<S11>/Selector'

     *  UnitDelay: '<S8>/UnitDelay2'

     */

    rtb_Sum2 = (int8_T)(rtb_Sum2_tmp - rtDW->UnitDelay2_DSTATE_j);



    /* Switch: '<S8>/Switch2' incorporates:

     *  Constant: '<S8>/Constant20'

     *  Constant: '<S8>/Constant8'

     *  Logic: '<S8>/Logical Operator3'

     *  RelationalOperator: '<S8>/Relational Operator1'

     *  RelationalOperator: '<S8>/Relational Operator6'

     */

    if ((rtb_Sum2 == 1) || (rtb_Sum2 == -5)) {

      /* Switch: '<S8>/Switch2' incorporates:

       *  Constant: '<S8>/Constant24'

       */

      rtDW->Switch2_i = 1;

    } else {

      /* Switch: '<S8>/Switch2' incorporates:

       *  Constant: '<S8>/Constant23'

       */

      rtDW->Switch2_i = -1;

    }



    /* End of Switch: '<S8>/Switch2' */



    /* Update for UnitDelay: '<S8>/UnitDelay2' */

    rtDW->UnitDelay2_DSTATE_j = rtb_Sum2_tmp;



    /* End of Outputs for SubSystem: '<S3>/Direction_Detection' */



    /* Outputs for IfAction SubSystem: '<S12>/Raw_Motor_Speed_Estimation' incorporates:

     *  ActionPort: '<S17>/Action Port'

     */

    /* RelationalOperator: '<S17>/Relational Operator4' */

    rtb_RelationalOperator4_f = (rtDW->Switch2_i != UnitDelay3);

    rtDW->z_counterRawPrev = rtDW->UnitDelay3_DSTATE;



    /* Switch: '<S17>/Switch3' incorporates:

     *  Constant: '<S17>/Constant4'

     *  Inport: '<S17>/z_counterRawPrev'

     *  Logic: '<S17>/Logical Operator1'

     *  Switch: '<S17>/Switch2'

     *  UnitDelay: '<S12>/UnitDelay3'

     *  UnitDelay: '<S17>/UnitDelay1'

     */

    if (rtb_RelationalOperator4_f && rtDW->UnitDelay1_DSTATE_i) {

      rtb_Switch3_c = 0;

    } else if (rtb_RelationalOperator4_f) {

      /* Switch: '<S17>/Switch3' incorporates:

       *  Switch: '<S17>/Switch2'

       *  UnitDelay: '<S12>/UnitDelay4'

       */

      rtb_Switch3_c = rtDW->UnitDelay4_DSTATE;

    } else {

      /* Product: '<S17>/Divide13' incorporates:

       *  Sum: '<S17>/Sum13'

       *  Switch: '<S17>/Switch2'

       *  UnitDelay: '<S17>/UnitDelay2'

       *  UnitDelay: '<S17>/UnitDelay3'

       *  UnitDelay: '<S17>/UnitDelay5'

       */

      tmp = 8000000U / (((rtDW->UnitDelay2_DSTATE + rtDW->UnitDelay3_DSTATE_l) +

                         rtDW->UnitDelay5_DSTATE) + rtDW->z_counterRawPrev);

      if (tmp > 32767U) {

        tmp = 32767U;

      }



      /* Switch: '<S17>/Switch3' incorporates:

       *  Product: '<S17>/Divide13'

       *  Switch: '<S17>/Switch2'

       */

      rtb_Switch3_c = (int16_T)tmp;

    }



    /* End of Switch: '<S17>/Switch3' */



    /* Product: '<S17>/Divide11' incorporates:

     *  Switch: '<S17>/Switch3'

     */

    rtDW->Divide11 = (int16_T)(rtb_Switch3_c * rtDW->Switch2_i);



    /* Update for UnitDelay: '<S17>/UnitDelay1' */

    rtDW->UnitDelay1_DSTATE_i = rtb_RelationalOperator4_f;



    /* Update for UnitDelay: '<S17>/UnitDelay2' incorporates:

     *  UnitDelay: '<S17>/UnitDelay3'

     */

    rtDW->UnitDelay2_DSTATE = rtDW->UnitDelay3_DSTATE_l;



    /* Update for UnitDelay: '<S17>/UnitDelay3' incorporates:

     *  UnitDelay: '<S17>/UnitDelay5'

     */

    rtDW->UnitDelay3_DSTATE_l = rtDW->UnitDelay5_DSTATE;



    /* Update for UnitDelay: '<S17>/UnitDelay5' */

    rtDW->UnitDelay5_DSTATE = rtDW->z_counterRawPrev;



    /* End of Outputs for SubSystem: '<S12>/Raw_Motor_Speed_Estimation' */

  }



  /* End of If: '<S3>/If2' */



  /* Switch: '<S10>/Switch3' incorporates:

   *  Constant: '<S10>/Constant16'

   *  Constant: '<S10>/Constant2'

   *  Constant: '<S11>/vec_hallToPos'

   *  RelationalOperator: '<S10>/Relational Operator7'

   *  Selector: '<S11>/Selector'

   *  Sum: '<S10>/Sum1'

   */

  if (rtDW->Switch2_i == 1) {

    rtb_Sum2 = rtConstP.vec_hallToPos_Value[rtb_Add_cr];

  } else {

    rtb_Sum2 = (int8_T)(rtConstP.vec_hallToPos_Value[rtb_Add_cr] + 1);

  }



  /* End of Switch: '<S10>/Switch3' */



  /* MinMax: '<S10>/MinMax' incorporates:

   *  Inport: '<Root>/hw_count'

   */

  if (rtU->hw_count < rtDW->z_counterRawPrev) {

    tmp = rtU->hw_count;

  } else {

    tmp = rtDW->z_counterRawPrev;

  }



  /* End of MinMax: '<S10>/MinMax' */



  /* Sum: '<S10>/Sum3' incorporates:

   *  Product: '<S10>/Divide1'

   *  Product: '<S10>/Divide3'

   */

  rtb_Switch3_c = (int16_T)(((int16_T)((int16_T)(((uint64_T)tmp << 14) /

    rtDW->z_counterRawPrev) * rtDW->Switch2_i) + (rtb_Sum2 << 14)) >> 2);



  /* MinMax: '<S10>/MinMax1' incorporates:

   *  Constant: '<S10>/Constant1'

   *  Sum: '<S10>/Sum3'

   *  Switch: '<S10>/Switch2'

   */

  if (rtb_Switch3_c <= 0) {

    rtb_Switch3_c = 0;

  }



  /* End of MinMax: '<S10>/MinMax1' */



  /* Sum: '<S13>/Add2' incorporates:

   *  Constant: '<S13>/Constant2'

   *  Product: '<S10>/Divide2'

   */

  rtb_Switch3_c = (int16_T)((((15 * rtb_Switch3_c) >> 4) + 3840) >> 2);



  /* If: '<S13>/If' incorporates:

   *  Constant: '<S13>/Constant3'

   *  DataTypeConversion: '<S13>/Data Type Conversion'

   *  Inport: '<S14>/In1'

   *  Merge: '<S13>/Merge'

   *  Sum: '<S13>/Add'

   *  Sum: '<S13>/Add2'

   */

  if ((int16_T)(rtb_Switch3_c >> 4) >= 360) {

    /* Outputs for IfAction SubSystem: '<S13>/If Action Subsystem' incorporates:

     *  ActionPort: '<S14>/Action Port'

     */

    rtb_Switch3_c = (int16_T)(rtb_Switch3_c - 5760);



    /* End of Outputs for SubSystem: '<S13>/If Action Subsystem' */

  }



  /* End of If: '<S13>/If' */



  /* Switch: '<S12>/Switch2' incorporates:

   *  Constant: '<S12>/Constant4'

   *  Inport: '<Root>/hw_count'

   *  Product: '<S17>/Divide11'

   *  RelationalOperator: '<S12>/Relational Operator2'

   */

  if (rtU->hw_count >= 400000U) {

    rtb_Switch2_ip = 0;

  } else {

    rtb_Switch2_ip = rtDW->Divide11;

  }



  /* End of Switch: '<S12>/Switch2' */



  /* Abs: '<S12>/Abs5' incorporates:

   *  Switch: '<S12>/Switch2'

   */

  if (rtb_Switch2_ip < 0) {

    rtb_Abs5 = (int16_T)-rtb_Switch2_ip;

  } else {

    rtb_Abs5 = rtb_Switch2_ip;

  }



  /* End of Abs: '<S12>/Abs5' */



  /* If: '<S12>/If1' */

  if (rtb_LogicalOperator) {

    /* Outputs for IfAction SubSystem: '<S12>/Subsystem' incorporates:

     *  ActionPort: '<S18>/Action Port'

     */

    /* Relay: '<S18>/n_commDeacv' incorporates:

     *  Abs: '<S12>/Abs5'

     */

    rtDW->n_commDeacv_Mode = ((rtb_Abs5 >= 120) || ((rtb_Abs5 > 60) &&

      rtDW->n_commDeacv_Mode));



    /* RelationalOperator: '<S20>/Compare' incorporates:

     *  Constant: '<S20>/Constant'

     *  Relay: '<S18>/n_commDeacv'

     *  Sum: '<S18>/Sum13'

     *  UnitDelay: '<S18>/UnitDelay2'

     *  UnitDelay: '<S18>/UnitDelay3'

     *  UnitDelay: '<S18>/UnitDelay5'

     */

    rtDW->Compare = ((uint16_T)((uint32_T)(uint16_T)((uint32_T)(uint16_T)

      ((uint32_T)rtDW->UnitDelay2_DSTATE_f + rtDW->UnitDelay3_DSTATE_lh) +

      rtDW->UnitDelay5_DSTATE_f) + rtDW->n_commDeacv_Mode) >= 4);



    /* Update for UnitDelay: '<S18>/UnitDelay2' incorporates:

     *  UnitDelay: '<S18>/UnitDelay3'

     */

    rtDW->UnitDelay2_DSTATE_f = rtDW->UnitDelay3_DSTATE_lh;



    /* Update for UnitDelay: '<S18>/UnitDelay3' incorporates:

     *  UnitDelay: '<S18>/UnitDelay5'

     */

    rtDW->UnitDelay3_DSTATE_lh = rtDW->UnitDelay5_DSTATE_f;



    /* Update for UnitDelay: '<S18>/UnitDelay5' incorporates:

     *  Logic: '<S18>/Logical Operator3'

     *  Relay: '<S18>/n_commDeacv'

     */

    rtDW->UnitDelay5_DSTATE_f = rtDW->n_commDeacv_Mode;



    /* End of Outputs for SubSystem: '<S12>/Subsystem' */

  }



  /* End of If: '<S12>/If1' */



  /* Switch: '<S3>/Switch' incorporates:

   *  Inport: '<Root>/b_hall_calibrate'

   *  Inport: '<Root>/open_theta'

   *  Merge: '<S13>/Merge'

   */

  if (rtU->b_hall_calibrate) {

    rtb_Switch_b = (int16_T)(rtU->open_theta << 4);

  } else {

    rtb_Switch_b = rtb_Switch3_c;

  }



  /* End of Switch: '<S3>/Switch' */



  /* Abs: '<S4>/Abs2' incorporates:

   *  Switch: '<S12>/Switch2'

   */

  if (rtb_Switch2_ip < 0) {

    rtb_LogicalOperator3 = (uint16_T)((uint32_T)-rtb_Switch2_ip >> 2);

  } else {

    rtb_LogicalOperator3 = (uint16_T)((uint32_T)rtb_Switch2_ip >> 2);

  }



  /* End of Abs: '<S4>/Abs2' */



  /* UnitDelay: '<S36>/UnitDelay' */

  rtb_UnitDelay = rtDW->UnitDelay_DSTATE_j;



  /* Outport: '<Root>/VqPrev' incorporates:

   *  UnitDelay: '<S6>/UnitDelay2'

   */

  rtY->VqPrev = rtDW->UnitDelay2_DSTATE_p;



  /* Switch: '<S36>/Switch3' incorporates:

   *  Abs: '<S12>/Abs5'

   *  Abs: '<S36>/Abs4'

   *  Constant: '<S36>/CTRL_COMM4'

   *  Inport: '<Root>/b_motEna'

   *  Logic: '<S36>/Logical Operator1'

   *  RelationalOperator: '<S12>/Relational Operator9'

   *  RelationalOperator: '<S36>/Relational Operator7'

   *  S-Function (sfix_bitop): '<S36>/Bitwise Operator1'

   *  UnitDelay: '<S6>/UnitDelay2'

   */

  if ((rtb_UnitDelay & 4U) != 0U) {

    rtb_LogicalOperator = true;

  } else {

    if (rtDW->UnitDelay2_DSTATE_p < 0) {

      /* Abs: '<S36>/Abs4' incorporates:

       *  UnitDelay: '<S6>/UnitDelay2'

       */

      rtb_Divide1_fi = (int16_T)-rtDW->UnitDelay2_DSTATE_p;

    } else {

      /* Abs: '<S36>/Abs4' incorporates:

       *  UnitDelay: '<S6>/UnitDelay2'

       */

      rtb_Divide1_fi = rtDW->UnitDelay2_DSTATE_p;

    }



    rtb_LogicalOperator = (rtU->b_motEna && (rtb_Abs5 < 12) && (rtb_Divide1_fi >

      960));

  }



  /* End of Switch: '<S36>/Switch3' */



  /* Sum: '<S36>/Sum' incorporates:

   *  Constant: '<S36>/CTRL_COMM'

   *  Constant: '<S36>/CTRL_COMM1'

   *  DataTypeConversion: '<S36>/Data Type Conversion3'

   *  Gain: '<S36>/g_Hb'

   *  Gain: '<S36>/g_Hb1'

   *  RelationalOperator: '<S36>/Relational Operator1'

   *  RelationalOperator: '<S36>/Relational Operator3'

   */

  rtb_DataTypeConversion1_c = (uint8_T)(((uint32_T)((rtb_Add_cr == 7) << 1) +

    (rtb_Add_cr == 0)) + (rtb_LogicalOperator << 2));



  /* Outputs for Atomic SubSystem: '<S36>/Debounce_Filter' */

  /* RelationalOperator: '<S36>/Relational Operator2' incorporates:

   *  Constant: '<S36>/CTRL_COMM2'

   *  Constant: '<S36>/t_errDequal'

   *  Constant: '<S36>/t_errQual'

   */

  Debounce_Filter(rtb_DataTypeConversion1_c != 0, 1600, 12000,

                  &rtb_RelationalOperator4_f, &rtDW->Debounce_Filter_i);



  /* End of Outputs for SubSystem: '<S36>/Debounce_Filter' */



  /* Logic: '<S23>/Logical Operator12' incorporates:

   *  Inport: '<Root>/b_motEna'

   *  Logic: '<S23>/Logical Operator7'

   */

  rtb_n_commDeacv = ((!rtb_RelationalOperator4_f) && rtU->b_motEna);



  /* Logic: '<S23>/Logical Operator4' incorporates:

   *  Constant: '<S23>/constant8'

   *  Inport: '<Root>/b_hall_calibrate'

   *  Inport: '<Root>/n_ctrlModReq'

   *  Logic: '<S23>/Logical Operator11'

   *  Logic: '<S23>/Logical Operator8'

   *  RelationalOperator: '<S23>/Relational Operator10'

   */

  rtb_LogicalOperator4 = (rtU->b_hall_calibrate || (!rtDW->Compare) ||

    (!rtb_n_commDeacv) || (rtU->n_ctrlModReq == 0));



  /* Relay: '<S23>/n_SpeedCtrl' */

  rtDW->n_SpeedCtrl_Mode = ((rtb_LogicalOperator3 >= 300) ||

    ((rtb_LogicalOperator3 > 200) && rtDW->n_SpeedCtrl_Mode));

  rtb_LogicalOperator = rtDW->n_SpeedCtrl_Mode;



  /* Logic: '<S23>/Logical Operator10' incorporates:

   *  Inport: '<Root>/b_cruiseEna'

   */

  rtb_LogicalOperator = (rtb_LogicalOperator && rtU->b_cruiseEna);



  /* Logic: '<S23>/Logical Operator2' incorporates:

   *  Constant: '<S23>/constant'

   *  Inport: '<Root>/n_ctrlModReq'

   *  Logic: '<S23>/Logical Operator5'

   *  RelationalOperator: '<S23>/Relational Operator4'

   */

  rtb_LogicalOperator2 = ((rtU->n_ctrlModReq == 2) && (!rtb_LogicalOperator));



  /* Logic: '<S23>/Logical Operator1' incorporates:

   *  Constant: '<S23>/constant1'

   *  Inport: '<Root>/n_ctrlModReq'

   *  RelationalOperator: '<S23>/Relational Operator1'

   */

  rtb_LogicalOperator = ((rtU->n_ctrlModReq == 1) || rtb_LogicalOperator);



  /* Chart: '<S4>/Control_Mode_Manager' incorporates:

   *  Logic: '<S23>/Logical Operator3'

   *  Logic: '<S23>/Logical Operator6'

   *  Logic: '<S23>/Logical Operator9'

   */

  if (rtDW->is_active_c5_PMSM_Controller == 0U) {

    rtDW->is_active_c5_PMSM_Controller = 1U;

    rtDW->is_c5_PMSM_Controller = IN_OPEN;

    rtb_z_ctrlMod = OPEN_MODE;

  } else if (rtDW->is_c5_PMSM_Controller == 1) {

    if (rtb_LogicalOperator4) {

      rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD;

      rtDW->is_c5_PMSM_Controller = IN_OPEN;

      rtb_z_ctrlMod = OPEN_MODE;

    } else if (rtDW->is_ACTIVE == 1) {

      rtb_z_ctrlMod = SPD_MODE;

      if (!rtb_LogicalOperator) {

        if (rtb_LogicalOperator2) {

          rtDW->is_ACTIVE = IN_TORQUE_MODE;

          rtb_z_ctrlMod = TRQ_MODE;

        } else {

          rtDW->is_ACTIVE = IN_SPEED_MODE;

        }

      }

    } else {

      /* case IN_TORQUE_MODE: */

      rtb_z_ctrlMod = TRQ_MODE;

      if (!rtb_LogicalOperator2) {

        rtDW->is_ACTIVE = IN_SPEED_MODE;

        rtb_z_ctrlMod = SPD_MODE;

      }

    }

  } else {

    /* case IN_OPEN: */

    rtb_z_ctrlMod = OPEN_MODE;

    if ((!rtb_LogicalOperator4) && (rtb_LogicalOperator2 || rtb_LogicalOperator))

    {

      rtDW->is_c5_PMSM_Controller = IN_ACTIVE;

      if (rtb_LogicalOperator2) {

        rtDW->is_ACTIVE = IN_TORQUE_MODE;

        rtb_z_ctrlMod = TRQ_MODE;

      } else {

        rtDW->is_ACTIVE = IN_SPEED_MODE;

        rtb_z_ctrlMod = SPD_MODE;

      }

    }

  }



  /* End of Chart: '<S4>/Control_Mode_Manager' */



  /* Switch: '<S24>/Switch' incorporates:

   *  Constant: '<S24>/Constant3'

   *  Inport: '<Root>/input_target'

   */

  if (rtU->input_target > 60) {

    /* Switch: '<S24>/Switch1' incorporates:

     *  Constant: '<S24>/Constant1'

     *  DataTypeConversion: '<S24>/Data Type Conversion'

     *  Switch: '<S24>/Switch'

     */

    if (rtb_n_commDeacv) {

      rtb_Switch_oi = rtU->input_target;

    } else {

      rtb_Switch_oi = 0;

    }



    /* End of Switch: '<S24>/Switch1' */

  } else {

    rtb_Switch_oi = 0;

  }



  /* End of Switch: '<S24>/Switch' */



  /* Switch: '<S24>/Switch3' incorporates:

   *  Constant: '<S24>/Constant4'

   *  DataTypeConversion: '<S24>/Data Type Conversion2'

   *  Inport: '<Root>/vq_open_target'

   */

  if (rtb_n_commDeacv) {

    rtb_Abs5_h = rtU->vq_open_target;

  } else {

    rtb_Abs5_h = 0;

  }



  /* End of Switch: '<S24>/Switch3' */



  /* If: '<S25>/If' incorporates:

   *  DataTypeConversion: '<S25>/Data Type Conversion1'

   *  Inport: '<Root>/b_hall_calibrate'

   *  Inport: '<S29>/vq_in'

   *  Switch: '<S24>/Switch3'

   */

  if (rtU->b_hall_calibrate) {

    /* Switch: '<S24>/Switch2' incorporates:

     *  Constant: '<S24>/Constant2'

     *  DataTypeConversion: '<S24>/Data Type Conversion1'

     *  Inport: '<Root>/vd_open_target'

     *  Inport: '<S29>/vd_in'

     */

    if (rtb_n_commDeacv) {

      /* Outputs for IfAction SubSystem: '<S25>/If Action Subsystem' incorporates:

       *  ActionPort: '<S29>/Action Port'

       */

      rtDW->Merge[0] = rtU->vd_open_target;



      /* End of Outputs for SubSystem: '<S25>/If Action Subsystem' */

    } else {

      /* Outputs for IfAction SubSystem: '<S25>/If Action Subsystem' incorporates:

       *  ActionPort: '<S29>/Action Port'

       */

      rtDW->Merge[0] = 0;



      /* End of Outputs for SubSystem: '<S25>/If Action Subsystem' */

    }



    /* End of Switch: '<S24>/Switch2' */



    /* Outputs for IfAction SubSystem: '<S25>/If Action Subsystem' incorporates:

     *  ActionPort: '<S29>/Action Port'

     */

    rtDW->Merge[1] = rtb_Abs5_h;



    /* End of Outputs for SubSystem: '<S25>/If Action Subsystem' */

  } else if ((rtb_z_ctrlMod == 0) && rtb_Equal_k) {

    /* Outputs for IfAction SubSystem: '<S25>/open_mode' incorporates:

     *  ActionPort: '<S30>/Action Port'

     */

    /* RelationalOperator: '<S30>/Equal1' incorporates:

     *  Switch: '<S24>/Switch3'

     *  UnitDelay: '<S30>/Unit Delay'

     */

    rtb_LogicalOperator = (rtDW->UnitDelay_DSTATE != rtb_Abs5_h);



    /* If: '<S32>/If' */

    if (rtb_LogicalOperator) {

      /* Outputs for IfAction SubSystem: '<S32>/Subsystem' incorporates:

       *  ActionPort: '<S34>/Action Port'

       */

      /* Sum: '<S34>/Add' incorporates:

       *  Signum: '<S34>/Sign'

       *  Switch: '<S24>/Switch3'

       *  UnitDelay: '<S6>/UnitDelay2'

       */

      rtb_Sign = (int16_T)((rtb_Abs5_h - rtDW->UnitDelay2_DSTATE_p) >> 2);



      /* Signum: '<S34>/Sign' */

      if (rtb_Sign < 0) {

        rtb_Sign = -1;

      } else {

        rtb_Sign = (int16_T)(rtb_Sign > 0);

      }



      /* End of Signum: '<S34>/Sign' */



      /* Product: '<S34>/Divide' incorporates:

       *  Constant: '<S30>/Constant5'

       */

      rtDW->Divide = (int16_T)(rtb_Sign * 6);



      /* Switch: '<S34>/Switch' incorporates:

       *  Switch: '<S34>/Switch1'

       */

      if (rtb_Sign > 0) {

        /* Switch: '<S34>/Switch' incorporates:

         *  Switch: '<S24>/Switch3'

         */

        rtDW->Switch = rtb_Abs5_h;



        /* Switch: '<S34>/Switch1' incorporates:

         *  UnitDelay: '<S6>/UnitDelay2'

         */

        rtDW->Switch1 = rtDW->UnitDelay2_DSTATE_p;

      } else {

        /* Switch: '<S34>/Switch' incorporates:

         *  UnitDelay: '<S6>/UnitDelay2'

         */

        rtDW->Switch = rtDW->UnitDelay2_DSTATE_p;



        /* Switch: '<S34>/Switch1' incorporates:

         *  Switch: '<S24>/Switch3'

         */

        rtDW->Switch1 = rtb_Abs5_h;

      }



      /* End of Switch: '<S34>/Switch' */

      /* End of Outputs for SubSystem: '<S32>/Subsystem' */



      /* Switch: '<S35>/Switch1' incorporates:

       *  UnitDelay: '<S6>/UnitDelay2'

       */

      rtb_Sign = rtDW->UnitDelay2_DSTATE_p;

    } else {

      /* Switch: '<S35>/Switch1' incorporates:

       *  UnitDelay: '<S35>/UnitDelay'

       */

      rtb_Sign = rtDW->UnitDelay_DSTATE_d;

    }



    /* End of If: '<S32>/If' */



    /* Sum: '<S32>/Add2' incorporates:

     *  Product: '<S34>/Divide'

     */

    rtb_Divide = ((rtb_Sign << 1) + rtDW->Divide) >> 1;

    if (rtb_Divide > 32767) {

      rtb_Divide = 32767;

    } else {

      if (rtb_Divide < -32768) {

        rtb_Divide = -32768;

      }

    }



    /* Switch: '<S30>/Switch' incorporates:

     *  Switch: '<S24>/Switch'

     */

    if (rtb_Switch_oi > 0) {

      /* Switch: '<S33>/Switch2' incorporates:

       *  RelationalOperator: '<S33>/LowerRelop1'

       *  RelationalOperator: '<S33>/UpperRelop'

       *  Sum: '<S32>/Add2'

       *  Switch: '<S33>/Switch'

       *  Switch: '<S34>/Switch'

       *  Switch: '<S34>/Switch1'

       */

      if ((int16_T)rtb_Divide > rtDW->Switch) {

        /* Merge: '<S25>/Merge' incorporates:

         *  Switch: '<S30>/Switch'

         */

        rtDW->Merge[1] = rtDW->Switch;

      } else if ((int16_T)rtb_Divide < rtDW->Switch1) {

        /* Merge: '<S25>/Merge' incorporates:

         *  Switch: '<S30>/Switch'

         *  Switch: '<S33>/Switch'

         *  Switch: '<S34>/Switch1'

         */

        rtDW->Merge[1] = rtDW->Switch1;

      } else {

        /* Merge: '<S25>/Merge' incorporates:

         *  Switch: '<S30>/Switch'

         */

        rtDW->Merge[1] = (int16_T)rtb_Divide;

      }



      /* End of Switch: '<S33>/Switch2' */

    } else {

      /* Merge: '<S25>/Merge' incorporates:

       *  Constant: '<S30>/Constant1'

       */

      rtDW->Merge[1] = 0;

    }



    /* End of Switch: '<S30>/Switch' */



    /* Merge: '<S25>/Merge' incorporates:

     *  Constant: '<S30>/Constant3'

     *  SignalConversion generated from: '<S30>/open_voltage'

     */

    rtDW->Merge[0] = 0;



    /* Update for UnitDelay: '<S30>/Unit Delay' incorporates:

     *  Switch: '<S24>/Switch3'

     */

    rtDW->UnitDelay_DSTATE = rtb_Abs5_h;



    /* Switch: '<S35>/Switch2' */

    if (rtb_LogicalOperator) {

      /* Update for UnitDelay: '<S35>/UnitDelay' incorporates:

       *  UnitDelay: '<S6>/UnitDelay2'

       */

      rtDW->UnitDelay_DSTATE_d = rtDW->UnitDelay2_DSTATE_p;

    } else {

      /* Update for UnitDelay: '<S35>/UnitDelay' incorporates:

       *  Sum: '<S32>/Add2'

       */

      rtDW->UnitDelay_DSTATE_d = (int16_T)rtb_Divide;

    }



    /* End of Switch: '<S35>/Switch2' */

    /* End of Outputs for SubSystem: '<S25>/open_mode' */

  } else {

    if (rtb_z_ctrlMod == 2) {

      /* Outputs for IfAction SubSystem: '<S25>/torque_mode' incorporates:

       *  ActionPort: '<S31>/Action Port'

       */

      /* Product: '<S31>/Divide1' incorporates:

       *  Inport: '<Root>/i_dc_limit'

       *  Inport: '<Root>/speed_limit'

       *  Product: '<S31>/Divide4'

       *  Switch: '<S24>/Switch'

       */

      rtb_Divide = ((uint16_T)((rtU->i_dc_limit << 8) / rtU->speed_limit) *

                    rtb_Switch_oi) >> 8;

      if (rtb_Divide > 32767) {

        rtb_Divide = 32767;

      } else {

        if (rtb_Divide < -32768) {

          rtb_Divide = -32768;

        }

      }



      /* Product: '<S31>/Divide1' */

      rtDW->Divide1 = (int16_T)rtb_Divide;



      /* End of Outputs for SubSystem: '<S25>/torque_mode' */

    }

  }



  /* End of If: '<S25>/If' */



  /* Outputs for Atomic SubSystem: '<S36>/either_edge' */

  rtb_LogicalOperator = either_edge(rtb_RelationalOperator4_f,

    &rtDW->either_edge_f);



  /* End of Outputs for SubSystem: '<S36>/either_edge' */



  /* Switch: '<S36>/Switch1' */

  if (rtb_LogicalOperator) {

    rtb_UnitDelay = rtb_DataTypeConversion1_c;

  }



  /* End of Switch: '<S36>/Switch1' */



  /* Gain: '<S53>/Multiply' incorporates:

   *  DataTypeConversion: '<S56>/Data Type Conversion'

   *  Inport: '<Root>/adc_a'

   *  Inport: '<Root>/adc_b'

   */

  rtb_Divide = (12351 * rtU->adc_a) >> 11;

  if (rtb_Divide > 32767) {

    rtb_Divide = 32767;

  } else {

    if (rtb_Divide < -32768) {

      rtb_Divide = -32768;

    }

  }



  rtb_DataTypeConversion[0] = (int16_T)rtb_Divide;

  rtb_Gain1 = (12351 * rtU->adc_b) >> 11;

  if (rtb_Gain1 > 32767) {

    rtb_Gain1 = 32767;

  } else {

    if (rtb_Gain1 < -32768) {

      rtb_Gain1 = -32768;

    }

  }



  rtb_DataTypeConversion[1] = (int16_T)rtb_Gain1;



  /* Sum: '<S47>/Add' incorporates:

   *  Gain: '<S53>/Multiply'

   */

  rtb_MultiportSwitch_idx_0 = (int16_T)rtb_Divide + (int16_T)rtb_Gain1;

  if (rtb_MultiportSwitch_idx_0 > 32767) {

    rtb_MultiportSwitch_idx_0 = 32767;

  } else {

    if (rtb_MultiportSwitch_idx_0 < -32768) {

      rtb_MultiportSwitch_idx_0 = -32768;

    }

  }



  /* Sum: '<S47>/Add1' incorporates:

   *  Sum: '<S47>/Add'

   */

  rtb_Add2_l = -rtb_MultiportSwitch_idx_0;

  if (-rtb_MultiportSwitch_idx_0 > 32767) {

    rtb_Add2_l = 32767;

  }



  /* Sum: '<S55>/Add3' incorporates:

   *  Gain: '<S53>/Multiply'

   *  Sum: '<S47>/Add1'

   */

  rtb_MultiportSwitch_idx_0 = (int16_T)rtb_Gain1 + (int16_T)rtb_Add2_l;

  if (rtb_MultiportSwitch_idx_0 > 32767) {

    rtb_MultiportSwitch_idx_0 = 32767;

  } else {

    if (rtb_MultiportSwitch_idx_0 < -32768) {

      rtb_MultiportSwitch_idx_0 = -32768;

    }

  }



  /* Sum: '<S55>/Add' incorporates:

   *  Gain: '<S53>/Multiply'

   *  Sum: '<S55>/Add3'

   */

  rtb_Divide = (((int16_T)rtb_Divide << 1) - rtb_MultiportSwitch_idx_0) >> 1;

  if (rtb_Divide > 32767) {

    rtb_Divide = 32767;

  } else {

    if (rtb_Divide < -32768) {

      rtb_Divide = -32768;

    }

  }



  /* Gain: '<S55>/Gain1' incorporates:

   *  Product: '<S57>/Divide1'

   *  Sum: '<S55>/Add'

   */

  rtb_Divide1_fi = (int16_T)((21845 * rtb_Divide) >> 15);



  /* Gain: '<S55>/Gain2' incorporates:

   *  Gain: '<S53>/Multiply'

   *  Sum: '<S47>/Add1'

   *  Sum: '<S55>/Add2'

   */

  rtb_Divide = ((((int16_T)rtb_Gain1 - (int16_T)rtb_Add2_l) >> 1) * 18919) >> 14;

  if (rtb_Divide > 32767) {

    rtb_Divide = 32767;

  } else {

    if (rtb_Divide < -32768) {

      rtb_Divide = -32768;

    }

  }



  /* PreLookup: '<S58>/a_elecAngle_XA' incorporates:

   *  Switch: '<S3>/Switch'

   */

  rtb_LogicalOperator3 = plook_u16s16_evencka(rtb_Switch_b, 0, 4U, 1440U);



  /* Interpolation_n-D: '<S58>/r_cos_M1' */

  rtb_Sign = rtConstP.r_cos_M1_Table[rtb_LogicalOperator3];



  /* Interpolation_n-D: '<S58>/r_sin_M1' incorporates:

   *  Product: '<S69>/Divide4'

   */

  rtb_Abs5_h = rtConstP.r_sin_M1_Table[rtb_LogicalOperator3];



  /* Sum: '<S57>/Sum1' incorporates:

   *  Gain: '<S55>/Gain2'

   *  Interpolation_n-D: '<S58>/r_cos_M1'

   *  Interpolation_n-D: '<S58>/r_sin_M1'

   *  Product: '<S57>/Divide1'

   *  Product: '<S57>/Divide2'

   *  Product: '<S57>/Divide3'

   */

  rtb_Gain1 = (int16_T)((rtb_Divide1_fi *

    rtConstP.r_cos_M1_Table[rtb_LogicalOperator3]) >> 14) + (int16_T)(((int16_T)

    rtb_Divide * rtConstP.r_sin_M1_Table[rtb_LogicalOperator3]) >> 14);

  if (rtb_Gain1 > 32767) {

    rtb_Gain1 = 32767;

  } else {

    if (rtb_Gain1 < -32768) {

      rtb_Gain1 = -32768;

    }

  }



  /* SignalConversion generated from: '<S47>/Low_Pass_Filter' incorporates:

   *  Sum: '<S57>/Sum1'

   */

  rtb_TmpSignalConversionAtLow_Pa[0] = (int16_T)rtb_Gain1;



  /* Sum: '<S57>/Sum6' incorporates:

   *  Gain: '<S55>/Gain2'

   *  Interpolation_n-D: '<S58>/r_cos_M1'

   *  Interpolation_n-D: '<S58>/r_sin_M1'

   *  Product: '<S57>/Divide1'

   *  Product: '<S57>/Divide4'

   */

  rtb_Divide = (int16_T)(((int16_T)rtb_Divide *

    rtConstP.r_cos_M1_Table[rtb_LogicalOperator3]) >> 14) - (int16_T)

    ((rtb_Divide1_fi * rtConstP.r_sin_M1_Table[rtb_LogicalOperator3]) >> 14);

  if (rtb_Divide > 32767) {

    rtb_Divide = 32767;

  } else {

    if (rtb_Divide < -32768) {

      rtb_Divide = -32768;

    }

  }



  /* SignalConversion generated from: '<S47>/Low_Pass_Filter' incorporates:

   *  Sum: '<S57>/Sum6'

   */

  rtb_TmpSignalConversionAtLow_Pa[1] = (int16_T)rtb_Divide;



  /* Outputs for Atomic SubSystem: '<S47>/Low_Pass_Filter' */

  /* Constant: '<S47>/Constant' */

  Low_Pass_Filter(rtb_TmpSignalConversionAtLow_Pa, 26214, rtb_DataTypeConversion,

                  &rtDW->Low_Pass_Filter_d);



  /* End of Outputs for SubSystem: '<S47>/Low_Pass_Filter' */



  /* Outport: '<Root>/VdPrev' incorporates:

   *  UnitDelay: '<S6>/UnitDelay1'

   */

  rtY->VdPrev = rtDW->UnitDelay1_DSTATE_f;



  /* Abs: '<S48>/Abs5' incorporates:

   *  UnitDelay: '<S6>/UnitDelay1'

   */

  if (rtDW->UnitDelay1_DSTATE_f < 0) {

    rtb_Divide1_fi = (int16_T)-rtDW->UnitDelay1_DSTATE_f;

  } else {

    rtb_Divide1_fi = rtDW->UnitDelay1_DSTATE_f;

  }



  /* End of Abs: '<S48>/Abs5' */



  /* PreLookup: '<S48>/Vq_max_XA' */

  rtb_LogicalOperator3 = plook_u16s16_evencka(rtb_Divide1_fi, 0, 64U, 45U);



  /* Interpolation_n-D: '<S48>/iq_maxSca_M1' incorporates:

   *  Inport: '<Root>/i_dc_limit'

   *  Product: '<S26>/Divide3'

   *  Product: '<S48>/Divide4'

   */

  rtb_Divide = rtDW->Divide3 << 16;

  rtb_Divide = (rtb_Divide == MIN_int32_T) && (rtU->i_dc_limit == -1) ?

    MAX_int32_T : rtb_Divide / rtU->i_dc_limit;

  if (rtb_Divide < 0) {

    rtb_Divide = 0;

  } else {

    if (rtb_Divide > 65535) {

      rtb_Divide = 65535;

    }

  }



  /* Product: '<S48>/Divide1' incorporates:

   *  Inport: '<Root>/i_dc_limit'

   *  Interpolation_n-D: '<S48>/iq_maxSca_M1'

   *  PreLookup: '<S48>/iq_maxSca_XA'

   *  Product: '<S48>/Divide4'

   */

  rtb_Divide1_fi = (int16_T)((rtConstP.iq_maxSca_M1_Table[plook_u8u16_evencka

    ((uint16_T)rtb_Divide, 0U, 1311U, 49U)] * rtU->i_dc_limit) >> 16);



  /* Switch: '<S54>/Switch2' */

  rtb_Switch2_fu = (uint8_T)(rtb_z_ctrlMod != 0);



  /* DataTypeConversion: '<S49>/Data Type Conversion' incorporates:

   *  Logic: '<S49>/Logical Operator'

   *  RelationalOperator: '<S49>/Equal'

   *  UnitDelay: '<S49>/Unit Delay'

   */

  rtb_DataTypeConversion_m = (uint8_T)((rtb_Switch2_fu != 0) &&

    (rtDW->UnitDelay_DSTATE_b != rtb_Switch2_fu));



  /* DataTypeConversion: '<S54>/Data Type Conversion1' incorporates:

   *  Logic: '<S54>/Logical Operator'

   */

  rtb_DataTypeConversion1_c = (uint8_T)((rtb_Switch2_fu != 0) && rtb_Equal_k);



  /* If: '<S52>/If' incorporates:

   *  Constant: '<S79>/Constant1'

   *  Constant: '<S79>/Constant11'

   *  Constant: '<S79>/Constant2'

   *  Constant: '<S79>/Constant4'

   *  Gain: '<S48>/Gain1'

   *  Product: '<S48>/Divide1'

   *  Sum: '<S79>/Add2'

   *  Switch: '<S12>/Switch2'

   *  Switch: '<S84>/Switch2'

   */

  if ((rtb_DataTypeConversion1_c > 0) && (rtb_z_ctrlMod == 1)) {

    /* Outputs for IfAction SubSystem: '<S52>/speed_mode' incorporates:

     *  ActionPort: '<S79>/Action Port'

     */

    /* Switch: '<S81>/Switch2' incorporates:

     *  Inport: '<Root>/speed_limit'

     *  RelationalOperator: '<S81>/LowerRelop1'

     *  RelationalOperator: '<S81>/UpperRelop'

     *  Switch: '<S24>/Switch'

     *  Switch: '<S81>/Switch'

     *  Switch: '<S84>/Switch2'

     */

    if (rtb_Switch_oi > rtU->speed_limit) {

      rtb_Switch_oi = rtU->speed_limit;

    } else {

      if (rtb_Switch_oi < 0) {

        /* Switch: '<S81>/Switch' incorporates:

         *  Constant: '<S79>/Constant5'

         *  Switch: '<S84>/Switch2'

         */

        rtb_Switch_oi = 0;

      }

    }



    /* End of Switch: '<S81>/Switch2' */



    /* Outputs for Atomic SubSystem: '<S79>/pi_speed' */

    rtb_Switch_oi = pi_speed((int16_T)(rtb_Switch_oi - rtb_Switch2_ip), 3174, 10,

      20, rtb_Divide1_fi, (int16_T)-rtb_Divide1_fi, 0, rtb_Switch2_fu,

      &rtConstB.pi_speed_g, &rtDW->pi_speed_g, &rtPrevZCX->pi_speed_g);



    /* End of Outputs for SubSystem: '<S79>/pi_speed' */



    /* Merge: '<S52>/Merge' incorporates:

     *  Constant: '<S79>/Constant1'

     *  Constant: '<S79>/Constant11'

     *  Constant: '<S79>/Constant2'

     *  Constant: '<S79>/Constant4'

     *  Gain: '<S48>/Gain1'

     *  Product: '<S48>/Divide1'

     *  SignalConversion generated from: '<S79>/iq_target'

     *  Sum: '<S79>/Add2'

     *  Switch: '<S12>/Switch2'

     *  Switch: '<S84>/Switch2'

     */

    rtDW->Merge_b = rtb_Switch_oi;



    /* End of Outputs for SubSystem: '<S52>/speed_mode' */

  } else {

    if ((rtb_DataTypeConversion1_c > 0) && (rtb_z_ctrlMod == 2)) {

      /* Outputs for IfAction SubSystem: '<S52>/torque_mode' incorporates:

       *  ActionPort: '<S80>/Action Port'

       */

      /* Product: '<S80>/Divide' incorporates:

       *  Constant: '<S80>/Constant2'

       *  Sum: '<S80>/Sum2'

       *  Switch: '<S12>/Switch2'

       *  Switch: '<S24>/Switch'

       */

      rtb_Divide = ((int16_T)(rtb_Switch_oi - rtb_Switch2_ip) * 819) >> 6;

      if (rtb_Divide > 32767) {

        rtb_Divide = 32767;

      } else {

        if (rtb_Divide < -32768) {

          rtb_Divide = -32768;

        }

      }



      /* Product: '<S80>/Divide1' incorporates:

       *  Sum: '<S80>/Sum3'

       *  Switch: '<S12>/Switch2'

       *  Switch: '<S24>/Switch'

       */

      rtb_Gain1 = ((int16_T)(rtb_Switch2_ip - rtb_Switch_oi) * -51) >> 5;

      if (rtb_Gain1 > 32767) {

        rtb_Gain1 = 32767;

      } else {

        if (rtb_Gain1 < -32768) {

          rtb_Gain1 = -32768;

        }

      }



      rtb_Switch_oi = (int16_T)rtb_Gain1;



      /* End of Product: '<S80>/Divide1' */



      /* MinMax: '<S80>/Max' incorporates:

       *  Product: '<S80>/Divide'

       *  Product: '<S80>/Divide1'

       */

      if ((int16_T)rtb_Divide > rtb_Switch_oi) {

        rtb_Max = (int16_T)rtb_Divide;

      } else {

        rtb_Max = rtb_Switch_oi;

      }



      /* End of MinMax: '<S80>/Max' */



      /* MinMax: '<S80>/Max3' incorporates:

       *  MinMax: '<S80>/Max'

       *  Product: '<S48>/Divide1'

       *  Switch: '<S85>/Switch2'

       */

      if (rtb_Divide1_fi < rtb_Max) {

        rtb_Max = rtb_Divide1_fi;

      }



      /* End of MinMax: '<S80>/Max3' */



      /* Switch: '<S85>/Switch2' incorporates:

       *  Product: '<S31>/Divide1'

       *  RelationalOperator: '<S85>/LowerRelop1'

       */

      if (rtDW->Divide1 <= rtb_Max) {

        /* MinMax: '<S80>/Max1' incorporates:

         *  Product: '<S80>/Divide'

         *  Product: '<S80>/Divide1'

         */

        if ((int16_T)rtb_Divide < rtb_Switch_oi) {

          rtb_Switch_oi = (int16_T)rtb_Divide;

        }



        /* End of MinMax: '<S80>/Max1' */



        /* MinMax: '<S80>/Max2' incorporates:

         *  Gain: '<S48>/Gain1'

         *  MinMax: '<S80>/Max1'

         *  Product: '<S48>/Divide1'

         */

        if (rtb_Switch_oi <= (int16_T)-rtb_Divide1_fi) {

          rtb_Switch_oi = (int16_T)-rtb_Divide1_fi;

        }



        /* End of MinMax: '<S80>/Max2' */



        /* Switch: '<S85>/Switch' incorporates:

         *  MinMax: '<S80>/Max2'

         *  RelationalOperator: '<S85>/UpperRelop'

         */

        if (rtDW->Divide1 < rtb_Switch_oi) {

          rtb_Max = rtb_Switch_oi;

        } else {

          rtb_Max = rtDW->Divide1;

        }



        /* End of Switch: '<S85>/Switch' */

      }



      /* End of Switch: '<S85>/Switch2' */



      /* Merge: '<S52>/Merge' incorporates:

       *  SignalConversion generated from: '<S80>/torque_iq'

       *  Switch: '<S85>/Switch2'

       */

      rtDW->Merge_b = rtb_Max;



      /* End of Outputs for SubSystem: '<S52>/torque_mode' */

    }

  }



  /* End of If: '<S52>/If' */



  /* If: '<S49>/If' incorporates:

   *  Constant: '<S59>/Constant3'

   *  Constant: '<S59>/Constant4'

   *  Constant: '<S59>/Constant6'

   *  Constant: '<S59>/Constant9'

   *  Constant: '<S60>/Constant1'

   *  Constant: '<S60>/Constant7'

   *  Constant: '<S60>/Constant8'

   *  Constant: '<S60>/Constant9'

   *  Gain: '<S48>/Gain3'

   *  Gain: '<S48>/Gain5'

   *  If: '<S49>/If1'

   *  Inport: '<Root>/vbus_voltage'

   *  Interpolation_n-D: '<S48>/Vq_max_M1'

   *  Sum: '<S59>/Add'

   *  Sum: '<S60>/Add1'

   *  Switch: '<S62>/Switch2'

   *  Switch: '<S66>/Switch2'

   */

  if (rtb_Switch2_fu == 1) {

    /* Outputs for IfAction SubSystem: '<S49>/iq_ctrl' incorporates:

     *  ActionPort: '<S60>/Action Port'

     */

    /* Switch: '<S66>/Switch2' incorporates:

     *  Merge: '<S52>/Merge'

     *  Product: '<S48>/Divide1'

     *  RelationalOperator: '<S66>/LowerRelop1'

     */

    if (rtDW->Merge_b <= rtb_Divide1_fi) {

      /* Switch: '<S66>/Switch' incorporates:

       *  Gain: '<S48>/Gain1'

       *  RelationalOperator: '<S66>/UpperRelop'

       *  Switch: '<S66>/Switch2'

       */

      if (rtDW->Merge_b < (int16_T)-rtb_Divide1_fi) {

        rtb_Divide1_fi = (int16_T)-rtb_Divide1_fi;

      } else {

        rtb_Divide1_fi = rtDW->Merge_b;

      }



      /* End of Switch: '<S66>/Switch' */

    }



    /* End of Switch: '<S66>/Switch2' */



    /* Outputs for Atomic SubSystem: '<S60>/PI_iq' */

    PI_backCalc_fixdt((int16_T)(rtb_Divide1_fi - rtb_DataTypeConversion[1]),

                      4096, 51, 1024,

                      rtConstP.Vq_max_M1_Table[rtb_LogicalOperator3], (int16_T)

                      -rtConstP.Vq_max_M1_Table[rtb_LogicalOperator3], 0,

                      rtb_DataTypeConversion_m, &rtDW->Switch2_d,

                      &rtConstB.PI_iq, &rtDW->PI_iq, &rtPrevZCX->PI_iq);



    /* End of Outputs for SubSystem: '<S60>/PI_iq' */

    /* End of Outputs for SubSystem: '<S49>/iq_ctrl' */



    /* Outputs for IfAction SubSystem: '<S49>/id_ctrl' incorporates:

     *  ActionPort: '<S59>/Action Port'

     */

    /* Switch: '<S62>/Switch2' incorporates:

     *  Constant: '<S60>/Constant1'

     *  Constant: '<S60>/Constant7'

     *  Constant: '<S60>/Constant8'

     *  Constant: '<S60>/Constant9'

     *  Gain: '<S48>/Gain4'

     *  Gain: '<S48>/Gain5'

     *  Inport: '<Root>/i_dc_limit'

     *  Interpolation_n-D: '<S48>/Vq_max_M1'

     *  Product: '<S26>/Divide3'

     *  RelationalOperator: '<S62>/LowerRelop1'

     *  RelationalOperator: '<S62>/UpperRelop'

     *  Sum: '<S60>/Add1'

     *  Switch: '<S62>/Switch'

     *  Switch: '<S66>/Switch2'

     */

    if (rtDW->Divide3 > rtU->i_dc_limit) {

      rtb_Switch_oi = rtU->i_dc_limit;

    } else if (rtDW->Divide3 < (int16_T)-rtU->i_dc_limit) {

      /* Switch: '<S62>/Switch' incorporates:

       *  Gain: '<S48>/Gain4'

       *  Switch: '<S62>/Switch2'

       */

      rtb_Switch_oi = (int16_T)-rtU->i_dc_limit;

    } else {

      rtb_Switch_oi = rtDW->Divide3;

    }



    /* End of Switch: '<S62>/Switch2' */



    /* Outputs for Atomic SubSystem: '<S59>/PI_id' */

    PI_backCalc_fixdt((int16_T)(rtb_Switch_oi - rtb_DataTypeConversion[0]), 4096,

                      51, 1024, rtU->vbus_voltage, (int16_T)-rtU->vbus_voltage,

                      0, rtb_DataTypeConversion_m, &rtDW->Switch2,

                      &rtConstB.PI_id, &rtDW->PI_id, &rtPrevZCX->PI_id);



    /* End of Outputs for SubSystem: '<S59>/PI_id' */

    /* End of Outputs for SubSystem: '<S49>/id_ctrl' */

  }



  /* End of If: '<S49>/If' */



  /* Switch: '<S6>/Switch1' incorporates:

   *  Switch: '<S64>/Switch2'

   *  Switch: '<S68>/Switch2'

   *  Switch: '<S6>/Switch'

   */

  if (rtb_z_ctrlMod != 0) {

    rtb_Switch_oi = rtDW->Switch2_d;

    rtb_Divide1_fi = rtDW->Switch2;

  } else {

    rtb_Switch_oi = rtDW->Merge[1];

    rtb_Divide1_fi = rtDW->Merge[0];

  }



  /* End of Switch: '<S6>/Switch1' */



  /* Sum: '<S50>/Sum1' incorporates:

   *  Interpolation_n-D: '<S58>/r_cos_M1'

   *  Product: '<S50>/Divide2'

   *  Product: '<S50>/Divide3'

   *  Product: '<S69>/Divide4'

   *  Switch: '<S6>/Switch'

   *  Switch: '<S6>/Switch1'

   */

  rtb_Divide = (int16_T)((rtb_Divide1_fi * rtb_Abs5_h) >> 14) + (int16_T)

    ((rtb_Switch_oi * rtb_Sign) >> 14);

  if (rtb_Divide > 32767) {

    rtb_Divide = 32767;

  } else {

    if (rtb_Divide < -32768) {

      rtb_Divide = -32768;

    }

  }



  /* Sum: '<S50>/Sum6' incorporates:

   *  Interpolation_n-D: '<S58>/r_cos_M1'

   *  Product: '<S50>/Divide1'

   *  Product: '<S50>/Divide4'

   *  Product: '<S69>/Divide4'

   *  Switch: '<S6>/Switch'

   *  Switch: '<S6>/Switch1'

   */

  rtb_Gain1 = (int16_T)((rtb_Divide1_fi * rtb_Sign) >> 14) - (int16_T)

    ((rtb_Switch_oi * rtb_Abs5_h) >> 14);

  if (rtb_Gain1 > 32767) {

    rtb_Gain1 = 32767;

  } else {

    if (rtb_Gain1 < -32768) {

      rtb_Gain1 = -32768;

    }

  }



  /* Product: '<S69>/Divide3' incorporates:

   *  Constant: '<S69>/Constant1'

   *  Product: '<S69>/Divide'

   *  Sum: '<S50>/Sum6'

   */

  rtb_Sign = (int16_T)((3547 * (int16_T)rtb_Gain1) >> 12);



  /* Product: '<S69>/Divide2' incorporates:

   *  Constant: '<S69>/Constant'

   *  Sum: '<S50>/Sum1'

   */

  rtb_Max = (int16_T)((3547 * (int16_T)rtb_Divide) >> 12);



  /* Product: '<S69>/Divide4' incorporates:

   *  Constant: '<S69>/Constant2'

   *  Product: '<S69>/Divide2'

   */

  rtb_Abs5_h = (int16_T)((2365 * rtb_Max) >> 12);



  /* Sum: '<S69>/Add' incorporates:

   *  Product: '<S69>/Divide'

   *  Product: '<S69>/Divide4'

   */

  rtb_Gain4 = (int16_T)((rtb_Sign + rtb_Abs5_h) >> 1);



  /* Sum: '<S69>/Add1' incorporates:

   *  Product: '<S69>/Divide'

   *  Product: '<S69>/Divide4'

   */

  rtb_Abs5_h = (int16_T)((rtb_Abs5_h - rtb_Sign) >> 1);



  /* Product: '<S69>/Divide7' incorporates:

   *  Constant: '<S69>/Constant3'

   *  Sum: '<S50>/Sum1'

   */

  rtb_Sign = (int16_T)((2365 * (int16_T)rtb_Divide) >> 12);



  /* MATLAB Function: '<S69>/sector_select' incorporates:

   *  Product: '<S69>/Divide7'

   *  Sum: '<S50>/Sum1'

   *  Sum: '<S50>/Sum6'

   */

  if ((int16_T)rtb_Divide >= 0) {

    if ((int16_T)rtb_Gain1 >= 0) {

      if (rtb_Sign > (int16_T)rtb_Gain1) {

        /* DataTypeConversion: '<S69>/Data Type Conversion' */

        rtb_DataTypeConversion1_c = 2U;

      } else {

        /* DataTypeConversion: '<S69>/Data Type Conversion' */

        rtb_DataTypeConversion1_c = 1U;

      }

    } else if (-rtb_Sign > (int16_T)rtb_Gain1) {

      /* DataTypeConversion: '<S69>/Data Type Conversion' */

      rtb_DataTypeConversion1_c = 3U;

    } else {

      /* DataTypeConversion: '<S69>/Data Type Conversion' */

      rtb_DataTypeConversion1_c = 2U;

    }

  } else if ((int16_T)rtb_Gain1 >= 0) {

    if (-rtb_Sign > (int16_T)rtb_Gain1) {

      /* DataTypeConversion: '<S69>/Data Type Conversion' */

      rtb_DataTypeConversion1_c = 5U;

    } else {

      /* DataTypeConversion: '<S69>/Data Type Conversion' */

      rtb_DataTypeConversion1_c = 6U;

    }

  } else if (rtb_Sign > (int16_T)rtb_Gain1) {

    /* DataTypeConversion: '<S69>/Data Type Conversion' */

    rtb_DataTypeConversion1_c = 4U;

  } else {

    /* DataTypeConversion: '<S69>/Data Type Conversion' */

    rtb_DataTypeConversion1_c = 5U;

  }



  /* End of MATLAB Function: '<S69>/sector_select' */



  /* Product: '<S69>/Divide' incorporates:

   *  Inport: '<Root>/vbus_voltage'

   */

  rtb_Sign = (int16_T)(24576000 / rtU->vbus_voltage);



  /* Product: '<S69>/Divide1' incorporates:

   *  Product: '<S69>/Divide'

   *  Product: '<S69>/Divide2'

   *  Product: '<S69>/Divide8'

   */

  rtb_Max = (int16_T)((((2365 * rtb_Max) >> 13) * rtb_Sign) >> 10);



  /* Product: '<S69>/Divide5' incorporates:

   *  Product: '<S69>/Divide'

   *  Sum: '<S69>/Add'

   */

  rtb_Gain4 = (int16_T)((rtb_Gain4 * rtb_Sign) >> 11);



  /* Product: '<S69>/Divide6' incorporates:

   *  Product: '<S69>/Divide'

   *  Sum: '<S69>/Add1'

   */

  rtb_Abs5_h = (int16_T)((rtb_Abs5_h * rtb_Sign) >> 11);



  /* MultiPortSwitch: '<S71>/Multiport Switch' incorporates:

   *  DataTypeConversion: '<S69>/Data Type Conversion1'

   *  Gain: '<S73>/Gain'

   *  Gain: '<S76>/Gain'

   *  Gain: '<S77>/Gain1'

   *  Product: '<S73>/Divide2'

   *  Product: '<S74>/Divide2'

   *  Product: '<S75>/Divide2'

   *  Product: '<S76>/Divide2'

   *  Product: '<S77>/Divide2'

   *  Product: '<S78>/Divide2'

   *  Sum: '<S73>/Add3'

   *  Sum: '<S74>/Add3'

   *  Sum: '<S75>/Add3'

   *  Sum: '<S76>/Add3'

   *  Sum: '<S77>/Add3'

   *  Sum: '<S78>/Add3'

   */

  switch (rtb_DataTypeConversion1_c) {

   case 1:

    /* Product: '<S73>/Divide' incorporates:

     *  Gain: '<S73>/Gain'

     *  Sum: '<S73>/Add'

     *  Sum: '<S73>/Add1'

     */

    rtb_Gain1 = (6000 - (rtb_Max - rtb_Abs5_h)) >> 2;



    /* Sum: '<S73>/Add2' incorporates:

     *  Product: '<S73>/Divide1'

     */

    rtb_Add2_l = (rtb_Max >> 1) + rtb_Gain1;

    rtb_MultiportSwitch_idx_0 = (-rtb_Abs5_h >> 1) + rtb_Add2_l;

    rtb_Divide = rtb_Add2_l;

    break;



   case 2:

    /* Product: '<S74>/Divide' incorporates:

     *  Sum: '<S74>/Add'

     *  Sum: '<S74>/Add1'

     */

    rtb_Sign = (int16_T)((int16_T)(6000 - (int16_T)(rtb_Abs5_h + rtb_Gain4)) >>

                         2);



    /* Sum: '<S74>/Add2' incorporates:

     *  Product: '<S74>/Divide1'

     */

    rtb_Max = (int16_T)((rtb_Gain4 >> 1) + rtb_Sign);

    rtb_MultiportSwitch_idx_0 = rtb_Max;

    rtb_Divide = (int16_T)((rtb_Abs5_h >> 1) + rtb_Max);

    rtb_Gain1 = rtb_Sign;

    break;



   case 3:

    /* Product: '<S75>/Divide' incorporates:

     *  Gain: '<S75>/Gain'

     *  Sum: '<S75>/Add'

     *  Sum: '<S75>/Add1'

     */

    rtb_Divide = (6000 - (rtb_Max - rtb_Gain4)) >> 2;



    /* Sum: '<S75>/Add2' incorporates:

     *  Gain: '<S75>/Gain'

     *  Product: '<S75>/Divide1'

     */

    rtb_Gain1 = (-rtb_Gain4 >> 1) + rtb_Divide;

    rtb_MultiportSwitch_idx_0 = rtb_Divide;

    rtb_Divide = (rtb_Max >> 1) + rtb_Gain1;

    break;



   case 4:

    /* Product: '<S76>/Divide' incorporates:

     *  Gain: '<S76>/Gain'

     *  Sum: '<S76>/Add'

     *  Sum: '<S76>/Add1'

     */

    rtb_Gain1 = (6000 - (rtb_Abs5_h - rtb_Max)) >> 2;



    /* Sum: '<S76>/Add2' incorporates:

     *  Product: '<S76>/Divide1'

     */

    rtb_Add2_l = (rtb_Abs5_h >> 1) + rtb_Gain1;

    rtb_MultiportSwitch_idx_0 = rtb_Gain1;

    rtb_Divide = rtb_Add2_l;

    rtb_Gain1 = (-rtb_Max >> 1) + rtb_Add2_l;

    break;



   case 5:

    /* Product: '<S77>/Divide' incorporates:

     *  Gain: '<S77>/Gain'

     *  Gain: '<S77>/Gain1'

     *  Sum: '<S77>/Add1'

     */

    rtb_Gain1 = (6000 - (-rtb_Abs5_h - rtb_Gain4)) >> 2;



    /* Sum: '<S77>/Add2' incorporates:

     *  Gain: '<S77>/Gain'

     *  Product: '<S77>/Divide1'

     */

    rtb_Add2_l = (-rtb_Abs5_h >> 1) + rtb_Gain1;

    rtb_MultiportSwitch_idx_0 = rtb_Add2_l;

    rtb_Divide = rtb_Gain1;

    rtb_Gain1 = (-rtb_Gain4 >> 1) + rtb_Add2_l;

    break;



   default:

    /* Product: '<S78>/Divide' incorporates:

     *  Gain: '<S78>/Gain1'

     *  Sum: '<S78>/Add'

     *  Sum: '<S78>/Add1'

     */

    rtb_Divide = (6000 - (rtb_Gain4 - rtb_Max)) >> 2;



    /* Sum: '<S78>/Add2' incorporates:

     *  Gain: '<S78>/Gain1'

     *  Product: '<S78>/Divide1'

     */

    rtb_Gain1 = (-rtb_Max >> 1) + rtb_Divide;

    rtb_MultiportSwitch_idx_0 = (rtb_Gain4 >> 1) + rtb_Gain1;

    break;

  }



  /* End of MultiPortSwitch: '<S71>/Multiport Switch' */



  /* Update for UnitDelay: '<S7>/UnitDelay1' incorporates:

   *  Sum: '<S7>/Sum3'

   */

  rtDW->UnitDelay1_DSTATE = qY;



  /* Update for Delay: '<S9>/Delay' incorporates:

   *  Inport: '<Root>/hall_a'

   */

  rtDW->Delay_DSTATE = rtU->hall_a;



  /* Update for Delay: '<S9>/Delay1' incorporates:

   *  Inport: '<Root>/hall_b'

   */

  rtDW->Delay1_DSTATE = rtU->hall_b;



  /* Update for Delay: '<S9>/Delay2' incorporates:

   *  Inport: '<Root>/hall_c'

   */

  rtDW->Delay2_DSTATE = rtU->hall_c;



  /* Update for UnitDelay: '<S12>/UnitDelay3' incorporates:

   *  Inport: '<Root>/hw_count'

   */

  rtDW->UnitDelay3_DSTATE = rtU->hw_count;



  /* Update for UnitDelay: '<S12>/UnitDelay4' incorporates:

   *  Abs: '<S12>/Abs5'

   */

  rtDW->UnitDelay4_DSTATE = rtb_Abs5;



  /* Update for UnitDelay: '<S36>/UnitDelay' */

  rtDW->UnitDelay_DSTATE_j = rtb_UnitDelay;



  /* Update for UnitDelay: '<S6>/UnitDelay2' incorporates:

   *  Switch: '<S6>/Switch1'

   */

  rtDW->UnitDelay2_DSTATE_p = rtb_Switch_oi;



  /* Update for UnitDelay: '<S6>/UnitDelay1' incorporates:

   *  Switch: '<S6>/Switch'

   */

  rtDW->UnitDelay1_DSTATE_f = rtb_Divide1_fi;



  /* Update for UnitDelay: '<S49>/Unit Delay' */

  rtDW->UnitDelay_DSTATE_b = rtb_Switch2_fu;



  /* Switch: '<S70>/Switch2' incorporates:

   *  RelationalOperator: '<S70>/LowerRelop1'

   *  RelationalOperator: '<S70>/UpperRelop'

   *  Switch: '<S70>/Switch'

   */

  if (rtb_MultiportSwitch_idx_0 > 3000) {

    /* Outport: '<Root>/PWM' incorporates:

     *  Constant: '<S69>/Constant6'

     */

    rtY->PWM[0] = 3000U;

  } else if (rtb_MultiportSwitch_idx_0 < 0) {

    /* Switch: '<S70>/Switch' incorporates:

     *  Constant: '<S69>/Constant5'

     *  Outport: '<Root>/PWM'

     */

    rtY->PWM[0] = 0U;

  } else {

    /* Outport: '<Root>/PWM' */

    rtY->PWM[0] = (uint16_T)rtb_MultiportSwitch_idx_0;

  }



  if (rtb_Divide > 3000) {

    /* Outport: '<Root>/PWM' incorporates:

     *  Constant: '<S69>/Constant6'

     */

    rtY->PWM[1] = 3000U;

  } else if (rtb_Divide < 0) {

    /* Switch: '<S70>/Switch' incorporates:

     *  Constant: '<S69>/Constant5'

     *  Outport: '<Root>/PWM'

     */

    rtY->PWM[1] = 0U;

  } else {

    /* Outport: '<Root>/PWM' */

    rtY->PWM[1] = (uint16_T)rtb_Divide;

  }



  if (rtb_Gain1 > 3000) {

    /* Outport: '<Root>/PWM' incorporates:

     *  Constant: '<S69>/Constant6'

     */

    rtY->PWM[2] = 3000U;

  } else if (rtb_Gain1 < 0) {

    /* Switch: '<S70>/Switch' incorporates:

     *  Constant: '<S69>/Constant5'

     *  Outport: '<Root>/PWM'

     */

    rtY->PWM[2] = 0U;

  } else {

    /* Outport: '<Root>/PWM' */

    rtY->PWM[2] = (uint16_T)rtb_Gain1;

  }



  /* End of Switch: '<S70>/Switch2' */

  /* End of Outputs for SubSystem: '<Root>/PMSM_Controller' */



  /* Outport: '<Root>/sector' */

  rtY->sector = rtb_DataTypeConversion1_c;



  /* Outport: '<Root>/n_MotError' */

  rtY->n_MotError = rtb_UnitDelay;



  /* Outport: '<Root>/iq' */

  rtY->iq = rtb_DataTypeConversion[1];



  /* Outport: '<Root>/id' */

  rtY->id = rtb_DataTypeConversion[0];



  /* Outport: '<Root>/angle' incorporates:

   *  Switch: '<S3>/Switch'

   */

  rtY->angle = rtb_Switch_b;



  /* Outport: '<Root>/rpm' incorporates:

   *  Switch: '<S12>/Switch2'

   */

  rtY->rpm = rtb_Switch2_ip;



  /* Outport: '<Root>/hall_angle' incorporates:

   *  Merge: '<S13>/Merge'

   */

  rtY->hall_angle = rtb_Switch3_c;



  /* Outport: '<Root>/hall_state' */

  rtY->hall_state = rtb_Add_cr;



  /* Outport: '<Root>/running_mode' */

  rtY->running_mode = rtb_z_ctrlMod;

}



/* Model initialize function */

void PMSM_Controller_initialize(RT_MODEL *const rtM)

{

  DW *rtDW = rtM->dwork;

  PrevZCX *rtPrevZCX = rtM->prevZCSigState;

  rtPrevZCX->pi_speed_g.ResettableDelay_Reset_ZCE = POS_ZCSIG;

  rtPrevZCX->PI_id.ResettableDelay_Reset_ZCE_p = POS_ZCSIG;

  rtPrevZCX->PI_iq.ResettableDelay_Reset_ZCE_p = POS_ZCSIG;



  /* SystemInitialize for Atomic SubSystem: '<Root>/PMSM_Controller' */

  /* SystemInitialize for IfAction SubSystem: '<S12>/Raw_Motor_Speed_Estimation' */

  /* SystemInitialize for Outport: '<S17>/z_counter' incorporates:

   *  Inport: '<S17>/z_counterRawPrev'

   */

  rtDW->z_counterRawPrev = 200000U;



  /* End of SystemInitialize for SubSystem: '<S12>/Raw_Motor_Speed_Estimation' */



  /* SystemInitialize for Atomic SubSystem: '<S36>/Debounce_Filter' */

  Debounce_Filter_Init(&rtDW->Debounce_Filter_i);



  /* End of SystemInitialize for SubSystem: '<S36>/Debounce_Filter' */



  /* SystemInitialize for IfAction SubSystem: '<S52>/speed_mode' */

  /* SystemInitialize for Atomic SubSystem: '<S79>/pi_speed' */

  pi_speed_Init(&rtDW->pi_speed_g);



  /* End of SystemInitialize for SubSystem: '<S79>/pi_speed' */

  /* End of SystemInitialize for SubSystem: '<S52>/speed_mode' */



  /* SystemInitialize for IfAction SubSystem: '<S49>/iq_ctrl' */

  /* SystemInitialize for Atomic SubSystem: '<S60>/PI_iq' */

  PI_backCalc_fixdt_Init(&rtDW->PI_iq);



  /* End of SystemInitialize for SubSystem: '<S60>/PI_iq' */

  /* End of SystemInitialize for SubSystem: '<S49>/iq_ctrl' */



  /* SystemInitialize for IfAction SubSystem: '<S49>/id_ctrl' */

  /* SystemInitialize for Atomic SubSystem: '<S59>/PI_id' */

  PI_backCalc_fixdt_Init(&rtDW->PI_id);



  /* End of SystemInitialize for SubSystem: '<S59>/PI_id' */

  /* End of SystemInitialize for SubSystem: '<S49>/id_ctrl' */

  /* End of SystemInitialize for SubSystem: '<Root>/PMSM_Controller' */

}



/*

 * File trailer for generated code.

 *

 * [EOF]

 */