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@@ -7,9 +7,10 @@
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inserted ADC 由timer0 ch3触发,
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注意:adc所有外部触发都是下降沿触发
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*/
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-
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+#define ISQ0_OFFSET 0
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+#define ISQ1_OFFSET 5
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#define ISQ2_OFFSET 10
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-#define ISO3_OFFSET 15
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+#define ISQ3_OFFSET 15
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#define IL_OFFSET 20
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#define ADC_SAMPLE_TIME ADC_SAMPLETIME_7POINT5
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@@ -22,9 +23,8 @@ inserted ADC 由timer0 ch3触发,
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#define PHASE_AC 1
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#define PHASE_BC 2
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-//#define ADC_RANK_CHANNEL(c1, c2, l) ((c1)<<ISQ2_OFFSET | (c2)<<ISO3_OFFSET | (l)<<IL_OFFSET)
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-#define ADC_RANK_CHANNEL(c) ((c)<<ISO3_OFFSET | (0)<<IL_OFFSET)
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-#define ADC_CALI_RANK_CHANEL(c) ((c)<<ISO3_OFFSET | (0)<<IL_OFFSET)
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+#define ADC_RANK_CHANNEL(c) ((c)<<ISQ3_OFFSET | (0)<<IL_OFFSET)
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+#define ADC_INS_RANK_4_CHANS(c1,c2,c3,c4) (((c1)<<ISQ0_OFFSET) | ((c2)<<ISQ1_OFFSET) | ((c3)<<ISQ2_OFFSET) | ((c4)<<ISQ3_OFFSET) | ((3)<<IL_OFFSET))
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#ifndef HIGH_SIDE_CURRENT_SENSOR
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static u32 adc0_rank_channels[3] = {
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@@ -51,10 +51,41 @@ static u32 volatile * adc_phase_reg2[3] = {
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&ADC_IDATA0(ADC1),//2, C
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};
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#endif
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+#ifdef CONFIG_SW_MUTISAMPLE
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+static s32 __inline _adc_avg(s32 *v) {
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+ s32 max_v = 0;
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+ s32 min_v = 4096*32;
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+ s32 total_v = 0;
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+ for (int i = 0; i < 4; i++) {
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+ if (v[i] > max_v) {
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+ max_v = v[i];
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+ }else if (v[i] < min_v) {
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+ min_v = v[i];
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+ }
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+ total_v += v[i];
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+ }
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+ total_v -= (max_v + min_v);
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+ return (total_v>>1);
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+
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+}
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+#endif
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static void __inline adc_phase_current_read(u8 phases, s32 *v1, s32 *v2) {
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-#ifdef HIGH_SIDE_CURRENT_SENSOR
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+#ifdef CONFIG_HW_MUTISAMPLE
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*v1 = ADC_IDATA0(ADC0);
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*v2 = ADC_IDATA0(ADC1);
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+#elif defined (CONFIG_SW_MUTISAMPLE)
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+ s32 v[4];
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+ v[0] = ADC_IDATA0(ADC0);
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+ v[1] = ADC_IDATA1(ADC0);
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+ v[2] = ADC_IDATA2(ADC0);
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+ v[3] = ADC_IDATA3(ADC0);
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+ *v1 = _adc_avg(v);
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+
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+ v[0] = ADC_IDATA0(ADC1);
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+ v[1] = ADC_IDATA1(ADC1);
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+ v[2] = ADC_IDATA2(ADC1);
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+ v[3] = ADC_IDATA3(ADC1);
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+ *v2 = _adc_avg(v);
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#else
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*v1 = (s32)(*adc_phase_reg1[phases]) ;
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*v2 = (s32)(*adc_phase_reg2[phases]) ;
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@@ -63,9 +94,12 @@ static void __inline adc_phase_current_read(u8 phases, s32 *v1, s32 *v2) {
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static void __inline adc_current_sample_config(u8 phases) {
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-#ifdef HIGH_SIDE_CURRENT_SENSOR
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+#ifdef CONFIG_HW_MUTISAMPLE
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ADC_ISQ(ADC0) = ADC_RANK_CHANNEL(V_PHASE_I_CHAN);
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ADC_ISQ(ADC1) = ADC_RANK_CHANNEL(W_PHASE_I_CHAN);
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+#elif defined (CONFIG_SW_MUTISAMPLE)
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+ ADC_ISQ(ADC0) = ADC_INS_RANK_4_CHANS(V_PHASE_I_CHAN, V_PHASE_I_CHAN, V_PHASE_I_CHAN, V_PHASE_I_CHAN);
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+ ADC_ISQ(ADC1) = ADC_INS_RANK_4_CHANS(W_PHASE_I_CHAN, W_PHASE_I_CHAN, W_PHASE_I_CHAN, W_PHASE_I_CHAN);
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#else
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ADC_ISQ(ADC0) = adc0_rank_channels[phases];
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ADC_ISQ(ADC1) = adc1_rank_channels[phases];
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