|
@@ -7,10 +7,17 @@
|
|
|
#define REG_CHAN_DMA 1
|
|
#define REG_CHAN_DMA 1
|
|
|
|
|
|
|
|
#ifdef REG_CHAN_DMA
|
|
#ifdef REG_CHAN_DMA
|
|
|
-#define REG_CHAN_NUM 7
|
|
|
|
|
-s16 adc_buffer[REG_CHAN_NUM] = {0, 0, 0, 0, 0, 0, 0};
|
|
|
|
|
|
|
+#ifndef MC100_HW_V1
|
|
|
|
|
+#define ADC01_NUM 7
|
|
|
|
|
+#define ADC2_NUM 0
|
|
|
|
|
+#else
|
|
|
|
|
+#define ADC01_NUM 5
|
|
|
|
|
+#define ADC2_NUM 4
|
|
|
|
|
+#endif
|
|
|
|
|
+#define REG_CHAN_NUM (ADC01_NUM + ADC2_NUM)
|
|
|
|
|
+s16 adc_buffer[REG_CHAN_NUM];
|
|
|
|
|
|
|
|
-static void adc_dma_init(void)
|
|
|
|
|
|
|
+static void adc01_dma_init(void)
|
|
|
{
|
|
{
|
|
|
dma_parameter_struct dma_init_struct;
|
|
dma_parameter_struct dma_init_struct;
|
|
|
rcu_periph_clock_enable(RCU_DMA0);
|
|
rcu_periph_clock_enable(RCU_DMA0);
|
|
@@ -20,7 +27,7 @@ static void adc_dma_init(void)
|
|
|
dma_init_struct.memory_addr = (uint32_t)adc_buffer;
|
|
dma_init_struct.memory_addr = (uint32_t)adc_buffer;
|
|
|
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
|
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
|
|
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
|
|
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
|
|
|
- dma_init_struct.number = REG_CHAN_NUM;
|
|
|
|
|
|
|
+ dma_init_struct.number = ADC01_NUM;
|
|
|
dma_init_struct.periph_addr = (uint32_t)(&ADC_RDATA(ADC0));
|
|
dma_init_struct.periph_addr = (uint32_t)(&ADC_RDATA(ADC0));
|
|
|
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
|
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
|
|
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
|
|
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
|
|
@@ -29,12 +36,33 @@ static void adc_dma_init(void)
|
|
|
dma_circulation_enable(DMA0, DMA_CH0);
|
|
dma_circulation_enable(DMA0, DMA_CH0);
|
|
|
dma_memory_to_memory_disable(DMA0, DMA_CH0);
|
|
dma_memory_to_memory_disable(DMA0, DMA_CH0);
|
|
|
|
|
|
|
|
- /* enable the full transfer interrupt */
|
|
|
|
|
- dma_interrupt_flag_clear(DMA0, DMA_CH0, DMA_INT_FLAG_FTF);
|
|
|
|
|
- dma_interrupt_enable(DMA0, DMA_CH0, DMA_INT_FTF);
|
|
|
|
|
-
|
|
|
|
|
dma_channel_enable(DMA0, DMA_CH0);
|
|
dma_channel_enable(DMA0, DMA_CH0);
|
|
|
}
|
|
}
|
|
|
|
|
+
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+static void adc2_dma_init(void)
|
|
|
|
|
+{
|
|
|
|
|
+ dma_parameter_struct dma_init_struct;
|
|
|
|
|
+ rcu_periph_clock_enable(RCU_DMA1);
|
|
|
|
|
+
|
|
|
|
|
+ dma_deinit(DMA1, DMA_CH4);
|
|
|
|
|
+ dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
|
|
|
|
|
+ dma_init_struct.memory_addr = (uint32_t)(adc_buffer + ADC01_NUM);
|
|
|
|
|
+ dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
|
|
|
|
+ dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
|
|
|
|
|
+ dma_init_struct.number = ADC2_NUM;
|
|
|
|
|
+ dma_init_struct.periph_addr = (uint32_t)(&ADC_RDATA(ADC2));
|
|
|
|
|
+ dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
|
|
|
|
+ dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
|
|
|
|
|
+ dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
|
|
|
|
+ dma_init(DMA1, DMA_CH4, &dma_init_struct);
|
|
|
|
|
+ dma_circulation_enable(DMA1, DMA_CH4);
|
|
|
|
|
+ dma_memory_to_memory_disable(DMA1, DMA_CH4);
|
|
|
|
|
+
|
|
|
|
|
+ dma_channel_enable(DMA1, DMA_CH4);
|
|
|
|
|
+}
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
#endif
|
|
#endif
|
|
|
|
|
|
|
|
static void adc0_init(void){
|
|
static void adc0_init(void){
|
|
@@ -79,7 +107,8 @@ static void adc0_init(void){
|
|
|
|
|
|
|
|
#ifdef REG_CHAN_DMA
|
|
#ifdef REG_CHAN_DMA
|
|
|
/* configure ADC regular channel */
|
|
/* configure ADC regular channel */
|
|
|
- adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, REG_CHAN_NUM);
|
|
|
|
|
|
|
+ adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, ADC01_NUM);
|
|
|
|
|
+#ifndef MC100_HW_V1
|
|
|
adc_regular_channel_config(ADC0, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
adc_regular_channel_config(ADC0, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
adc_regular_channel_config(ADC0, 1, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
adc_regular_channel_config(ADC0, 1, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
adc_regular_channel_config(ADC0, 2, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
adc_regular_channel_config(ADC0, 2, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
@@ -87,6 +116,13 @@ static void adc0_init(void){
|
|
|
adc_regular_channel_config(ADC0, 4, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
adc_regular_channel_config(ADC0, 4, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
adc_regular_channel_config(ADC0, 5, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
adc_regular_channel_config(ADC0, 5, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
adc_regular_channel_config(ADC0, 6, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
adc_regular_channel_config(ADC0, 6, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+#else
|
|
|
|
|
+ adc_regular_channel_config(ADC0, 0, MOS_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+ adc_regular_channel_config(ADC0, 1, MOS_TEMP1_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+ adc_regular_channel_config(ADC0, 2, U_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+ adc_regular_channel_config(ADC0, 3, V_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+ adc_regular_channel_config(ADC0, 4, W_VOL_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+#endif
|
|
|
#endif
|
|
#endif
|
|
|
/* configure ADC regular channel trigger */
|
|
/* configure ADC regular channel trigger */
|
|
|
adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
|
|
adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
|
|
@@ -148,6 +184,51 @@ static void adc1_init(void){
|
|
|
adc_software_trigger_enable(ADC1, ADC_INSERTED_CHANNEL);
|
|
adc_software_trigger_enable(ADC1, ADC_INSERTED_CHANNEL);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+static void adc2_init(void){
|
|
|
|
|
+ /* config ADC clock */
|
|
|
|
|
+ rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV4); //APB2 clk 120M, adc clk 30M
|
|
|
|
|
+
|
|
|
|
|
+ rcu_periph_clock_enable(RCU_ADC2);
|
|
|
|
|
+
|
|
|
|
|
+ adc_deinit(ADC2);
|
|
|
|
|
+
|
|
|
|
|
+ adc_special_function_config(ADC2, ADC_CONTINUOUS_MODE, ENABLE);
|
|
|
|
|
+ adc_special_function_config(ADC2, ADC_SCAN_MODE, ENABLE);
|
|
|
|
|
+
|
|
|
|
|
+ /* configure ADC data alignment */
|
|
|
|
|
+ adc_data_alignment_config(ADC2, ADC_DATAALIGN_RIGHT);
|
|
|
|
|
+
|
|
|
|
|
+ adc_oversample_mode_config(ADC2, ADC_OVERSAMPLING_ALL_CONVERT, ADC_OVERSAMPLING_SHIFT_1B, ADC_OVERSAMPLING_RATIO_MUL2);
|
|
|
|
|
+ adc_oversample_mode_enable(ADC2);
|
|
|
|
|
+
|
|
|
|
|
+#ifdef REG_CHAN_DMA
|
|
|
|
|
+ /* configure ADC regular channel */
|
|
|
|
|
+ adc_channel_length_config(ADC2, ADC_REGULAR_CHANNEL, ADC2_NUM);
|
|
|
|
|
+ adc_regular_channel_config(ADC2, 0, VBUS_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+ adc_regular_channel_config(ADC2, 1, ACC_V_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+ adc_regular_channel_config(ADC2, 2, THROTTLE_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+ adc_regular_channel_config(ADC2, 3, MOTOR_TEMP_ADC_CHAN, ADC_REGCHAN_SAMPLE_TIME);
|
|
|
|
|
+#endif
|
|
|
|
|
+ /* configure ADC regular channel trigger */
|
|
|
|
|
+ adc_external_trigger_source_config(ADC2, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
|
|
|
|
|
+ adc_external_trigger_config(ADC2, ADC_REGULAR_CHANNEL, ENABLE);
|
|
|
|
|
+#ifdef REG_CHAN_DMA
|
|
|
|
|
+ adc_dma_mode_enable(ADC2);
|
|
|
|
|
+#endif
|
|
|
|
|
+ /* enable ADC interface */
|
|
|
|
|
+ adc_enable(ADC2);
|
|
|
|
|
+
|
|
|
|
|
+ delay_ms(1);
|
|
|
|
|
+ /* ADC calibration and reset calibration */
|
|
|
|
|
+ adc_calibration_enable(ADC2);
|
|
|
|
|
+
|
|
|
|
|
+#ifdef REG_CHAN_DMA
|
|
|
|
|
+ adc_software_trigger_enable(ADC2, ADC_REGULAR_CHANNEL);
|
|
|
|
|
+#endif
|
|
|
|
|
+}
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
static void adc_gpio_init(void) {
|
|
static void adc_gpio_init(void) {
|
|
|
|
|
|
|
|
rcu_periph_clock_enable(RCU_AF);
|
|
rcu_periph_clock_enable(RCU_AF);
|
|
@@ -170,6 +251,12 @@ static void adc_gpio_init(void) {
|
|
|
/* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
|
|
/* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
|
|
|
gpio_init(VBUS_V_ADC_GROUP, VBUS_V_ADC_MODE, GPIO_OSPEED_50MHZ, VBUS_V_ADC_PIN);
|
|
gpio_init(VBUS_V_ADC_GROUP, VBUS_V_ADC_MODE, GPIO_OSPEED_50MHZ, VBUS_V_ADC_PIN);
|
|
|
#endif
|
|
#endif
|
|
|
|
|
+#ifdef ACC_V_ADC_GROUP
|
|
|
|
|
+ rcu_periph_clock_enable(ACC_V_ADC_RCU);
|
|
|
|
|
+ /* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
|
|
|
|
|
+ gpio_init(ACC_V_ADC_GROUP, ACC_V_ADC_MODE, GPIO_OSPEED_50MHZ, ACC_V_ADC_PIN);
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
#ifdef THROTTLE_V_ADC_GROUP
|
|
#ifdef THROTTLE_V_ADC_GROUP
|
|
|
rcu_periph_clock_enable(THROTTLE_V_ADC_RCU);
|
|
rcu_periph_clock_enable(THROTTLE_V_ADC_RCU);
|
|
|
/* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
|
|
/* configure ADC pin, bus voltage sampling -- ADC_IN0(PA0) */
|
|
@@ -199,6 +286,11 @@ static void adc_gpio_init(void) {
|
|
|
rcu_periph_clock_enable(MOS_TEMP_ADC_RCU);
|
|
rcu_periph_clock_enable(MOS_TEMP_ADC_RCU);
|
|
|
gpio_init(MOS_TEMP_ADC_CHAN, MOS_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOS_TEMP_ADC_PIN);
|
|
gpio_init(MOS_TEMP_ADC_CHAN, MOS_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOS_TEMP_ADC_PIN);
|
|
|
#endif
|
|
#endif
|
|
|
|
|
+#ifdef MOS_TEMP1_ADC_CHAN
|
|
|
|
|
+ rcu_periph_clock_enable(MOS_TEMP1_ADC_RCU);
|
|
|
|
|
+ gpio_init(MOS_TEMP1_ADC_CHAN, MOS_TEMP1_ADC_MODE, GPIO_OSPEED_50MHZ, MOS_TEMP1_ADC_PIN);
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
#ifdef MOTOR_TEMP_ADC_CHAN
|
|
#ifdef MOTOR_TEMP_ADC_CHAN
|
|
|
rcu_periph_clock_enable(MOTOR_TEMP_ADC_RCU);
|
|
rcu_periph_clock_enable(MOTOR_TEMP_ADC_RCU);
|
|
|
gpio_init(MOTOR_TEMP_ADC_CHAN, MOTOR_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOTOR_TEMP_ADC_PIN);
|
|
gpio_init(MOTOR_TEMP_ADC_CHAN, MOTOR_TEMP_ADC_MODE, GPIO_OSPEED_50MHZ, MOTOR_TEMP_ADC_PIN);
|
|
@@ -209,19 +301,42 @@ static void adc_gpio_init(void) {
|
|
|
void adc_init(void) {
|
|
void adc_init(void) {
|
|
|
adc_gpio_init();
|
|
adc_gpio_init();
|
|
|
#ifdef REG_CHAN_DMA
|
|
#ifdef REG_CHAN_DMA
|
|
|
- adc_dma_init();
|
|
|
|
|
|
|
+ adc01_dma_init();
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+ adc2_dma_init();
|
|
|
|
|
+#endif
|
|
|
#endif
|
|
#endif
|
|
|
adc0_init();
|
|
adc0_init();
|
|
|
adc1_init();
|
|
adc1_init();
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+ adc2_init();
|
|
|
|
|
+#endif
|
|
|
adc_current_sample_config(0);
|
|
adc_current_sample_config(0);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
u16 adc_get_vbus(void) {
|
|
u16 adc_get_vbus(void) {
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+ return adc_buffer[ADC01_NUM + 0];
|
|
|
|
|
+#else
|
|
|
return adc_buffer[0];
|
|
return adc_buffer[0];
|
|
|
|
|
+#endif
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
+u16 adc_get_acc(void) {
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+ return adc_buffer[ADC01_NUM + 1];
|
|
|
|
|
+#else
|
|
|
|
|
+ return adc_get_vbus();
|
|
|
|
|
+#endif
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
u16 adc_get_throttle(void) {
|
|
u16 adc_get_throttle(void) {
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+ return adc_buffer[ADC01_NUM + 2];
|
|
|
|
|
+#else
|
|
|
return adc_buffer[1];
|
|
return adc_buffer[1];
|
|
|
|
|
+#endif
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
void adc_get_uvw_phaseV(u16 *uvw) {
|
|
void adc_get_uvw_phaseV(u16 *uvw) {
|
|
@@ -231,11 +346,28 @@ void adc_get_uvw_phaseV(u16 *uvw) {
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
u16 adc_get_mos_temp(void) {
|
|
u16 adc_get_mos_temp(void) {
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+ return adc_buffer[0];
|
|
|
|
|
+#else
|
|
|
return adc_buffer[5];
|
|
return adc_buffer[5];
|
|
|
|
|
+#endif
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
+u16 adc_get_mos_temp2(void) {
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+ return adc_buffer[1];
|
|
|
|
|
+#else
|
|
|
|
|
+ return adc_get_mos_temp();
|
|
|
|
|
+#endif
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
u16 adc_get_motor_temp(void) {
|
|
u16 adc_get_motor_temp(void) {
|
|
|
|
|
+#ifdef MC100_HW_V1
|
|
|
|
|
+ return adc_buffer[ADC01_NUM + 3];
|
|
|
|
|
+#else
|
|
|
return adc_buffer[6];
|
|
return adc_buffer[6];
|
|
|
|
|
+#endif
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
void adc_start_convert(void) {
|
|
void adc_start_convert(void) {
|