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@@ -45,7 +45,7 @@ void pwm_3phase_sides(bool hon, bool lon) {
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if (hon && lon) {
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return;
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}
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- tmr_reset(pwm_timer);
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+ tmr_reset(MOS_PWM_TIMER);
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crm_periph_clock_enable(PWM_CRM_CLK, TRUE);
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pwm_gpio_init(PWM_U_P_GROUP,GPIO_MODE_OUTPUT,GPIO_OUTPUT_PUSH_PULL,GPIO_PULL_NONE, PWM_U_P_PIN);
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pwm_gpio_init(PWM_V_P_GROUP,GPIO_MODE_OUTPUT,GPIO_OUTPUT_PUSH_PULL,GPIO_PULL_NONE,PWM_V_P_PIN);
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@@ -133,18 +133,18 @@ static void _init_pwm_timer(bool enable_brk) {
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tmr_output_config_type tmr_output_struct;
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tmr_brkdt_config_type tmr_brkdt_config_struct;
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- tmr_reset(pwm_timer);
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+ tmr_reset(MOS_PWM_TIMER);
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crm_periph_clock_enable(PWM_CRM_CLK, TRUE);
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- tmr_repetition_counter_set(pwm_timer, 1); /* the pwm cycle isr in underflow (high-side pwm on) */
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- tmr_base_init(pwm_timer, FOC_PWM_Half_Period, 0);
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- tmr_cnt_dir_set(pwm_timer, TMR_COUNT_TWO_WAY_1); /* output compare interrupt flags are set only count-down */
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+ tmr_repetition_counter_set(MOS_PWM_TIMER, 1); /* the pwm cycle isr in underflow (high-side pwm on) */
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+ tmr_base_init(MOS_PWM_TIMER, FOC_PWM_Half_Period, 0);
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+ tmr_cnt_dir_set(MOS_PWM_TIMER, TMR_COUNT_TWO_WAY_1); /* output compare interrupt flags are set only count-down */
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/* set dead time clock */
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- tmr_clock_source_div_set(pwm_timer, TMR_CLOCK_DIV1);
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+ tmr_clock_source_div_set(MOS_PWM_TIMER, TMR_CLOCK_DIV1);
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/* channel 1,2,3,1C,2C,3C configuration in output mode */
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- tmr_channel_value_set(pwm_timer, TMR_SELECT_CHANNEL_1, FOC_PWM_Half_Period/2);
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- tmr_channel_value_set(pwm_timer, TMR_SELECT_CHANNEL_2, FOC_PWM_Half_Period/2);
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- tmr_channel_value_set(pwm_timer, TMR_SELECT_CHANNEL_3, FOC_PWM_Half_Period/2);
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+ tmr_channel_value_set(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_1, FOC_PWM_Half_Period/2);
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+ tmr_channel_value_set(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_2, FOC_PWM_Half_Period/2);
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+ tmr_channel_value_set(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_3, FOC_PWM_Half_Period/2);
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tmr_output_default_para_init(&tmr_output_struct);
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tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
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@@ -156,18 +156,18 @@ static void _init_pwm_timer(bool enable_brk) {
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tmr_output_struct.occ_idle_state = FALSE;
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/* channel 1, 2, 3 */
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- tmr_output_channel_config(pwm_timer, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
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- tmr_output_channel_config(pwm_timer, TMR_SELECT_CHANNEL_2, &tmr_output_struct);
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- tmr_output_channel_config(pwm_timer, TMR_SELECT_CHANNEL_3, &tmr_output_struct);
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+ tmr_output_channel_config(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
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+ tmr_output_channel_config(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_2, &tmr_output_struct);
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+ tmr_output_channel_config(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_3, &tmr_output_struct);
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- tmr_output_channel_buffer_enable(pwm_timer, TMR_SELECT_CHANNEL_1, TRUE);
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- tmr_output_channel_buffer_enable(pwm_timer, TMR_SELECT_CHANNEL_2, TRUE);
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- tmr_output_channel_buffer_enable(pwm_timer, TMR_SELECT_CHANNEL_3, TRUE);
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+ tmr_output_channel_buffer_enable(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_1, TRUE);
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+ tmr_output_channel_buffer_enable(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_2, TRUE);
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+ tmr_output_channel_buffer_enable(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_3, TRUE);
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tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
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- tmr_output_channel_config(pwm_timer, TMR_SELECT_CHANNEL_4, &tmr_output_struct);
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- tmr_channel_value_set(pwm_timer, TMR_SELECT_CHANNEL_4, FOC_PWM_Half_Period-1);
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- tmr_output_channel_buffer_enable(pwm_timer, TMR_SELECT_CHANNEL_4, TRUE);
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+ tmr_output_channel_config(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_4, &tmr_output_struct);
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+ tmr_channel_value_set(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_4, FOC_PWM_Half_Period-1);
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+ tmr_output_channel_buffer_enable(MOS_PWM_TIMER, TMR_SELECT_CHANNEL_4, TRUE);
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#ifdef PWM_BRAKE_GROUP
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/* automatic output enable, break, dead time and lock configuration */
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tmr_brkdt_default_para_init(&tmr_brkdt_config_struct);
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@@ -178,25 +178,25 @@ static void _init_pwm_timer(bool enable_brk) {
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tmr_brkdt_config_struct.fcsoen_state = FALSE;
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tmr_brkdt_config_struct.brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW;
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tmr_brkdt_config_struct.wp_level = TMR_WP_OFF;
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- tmr_brkdt_config(pwm_timer, &tmr_brkdt_config_struct);
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+ tmr_brkdt_config(MOS_PWM_TIMER, &tmr_brkdt_config_struct);
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#endif
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- tmr_primary_mode_select(pwm_timer, TMR_PRIMARY_SEL_OVERFLOW);
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+ tmr_primary_mode_select(MOS_PWM_TIMER, TMR_PRIMARY_SEL_OVERFLOW);
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- tmr_flag_clear(pwm_timer, TMR_OVF_FLAG | TMR_BRK_FLAG | TMR_C4_INT);
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- tmr_interrupt_enable(pwm_timer, TMR_OVF_INT, TRUE);
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- tmr_interrupt_enable(pwm_timer, TMR_BRK_INT, TRUE);
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+ tmr_flag_clear(MOS_PWM_TIMER, TMR_OVF_FLAG | TMR_BRK_FLAG | TMR_C4_INT);
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+ tmr_interrupt_enable(MOS_PWM_TIMER, TMR_OVF_INT, TRUE);
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+ tmr_interrupt_enable(MOS_PWM_TIMER, TMR_BRK_INT, TRUE);
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/* disable single pulse mode */
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- tmr_one_cycle_mode_enable(pwm_timer, FALSE);
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+ tmr_one_cycle_mode_enable(MOS_PWM_TIMER, FALSE);
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/* pwm timer output enable */
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- tmr_output_enable(pwm_timer, FALSE);
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+ tmr_output_enable(MOS_PWM_TIMER, FALSE);
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nvic_irq_enable(TMR1_BRK_TMR9_IRQn, EBREAK_IRQ_PRIORITY, 0);
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nvic_irq_enable(TMR1_OVF_TMR10_IRQn, TIMER_UP_IRQ_PRIORITY, 0);
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/* enable pwm timer */
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- tmr_counter_enable(pwm_timer, TRUE);
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+ tmr_counter_enable(MOS_PWM_TIMER, TRUE);
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}
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@@ -204,32 +204,32 @@ void pwm_start(void){
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pwm_update_duty(FOC_PWM_Half_Period/2, FOC_PWM_Half_Period/2, FOC_PWM_Half_Period/2);
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pwm_update_2smaples(FOC_PWM_Half_Period-1, FOC_PWM_Half_Period + 1);
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/* wait for a new PWM period to flush last HF task */
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- tmr_flag_clear(pwm_timer, TMR_OVF_FLAG);
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+ tmr_flag_clear(MOS_PWM_TIMER, TMR_OVF_FLAG);
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- tmr_event_sw_trigger(pwm_timer, TMR_OVERFLOW_SWTRIG);
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- while ( tmr_flag_get(pwm_timer, TMR_OVF_FLAG) == RESET ){}
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+ tmr_event_sw_trigger(MOS_PWM_TIMER, TMR_OVERFLOW_SWTRIG);
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+ while ( tmr_flag_get(MOS_PWM_TIMER, TMR_OVF_FLAG) == RESET ){}
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/* Clear Update Flag */
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- tmr_flag_clear(pwm_timer, TMR_OVF_FLAG);
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+ tmr_flag_clear(MOS_PWM_TIMER, TMR_OVF_FLAG);
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- tmr_output_enable(pwm_timer, TRUE);
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+ tmr_output_enable(MOS_PWM_TIMER, TRUE);
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}
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void pwm_stop(void){
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- tmr_output_enable(pwm_timer, FALSE);
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+ tmr_output_enable(MOS_PWM_TIMER, FALSE);
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- tmr_interrupt_enable(pwm_timer, TMR_OVF_INT, FALSE);
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+ tmr_interrupt_enable(MOS_PWM_TIMER, TMR_OVF_INT, FALSE);
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/* wait for a new PWM period to flush last HF task */
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- tmr_flag_clear(pwm_timer, TMR_OVF_FLAG);
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- while ( tmr_flag_get(pwm_timer, TMR_OVF_FLAG) == RESET ){}
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+ tmr_flag_clear(MOS_PWM_TIMER, TMR_OVF_FLAG);
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+ while ( tmr_flag_get(MOS_PWM_TIMER, TMR_OVF_FLAG) == RESET ){}
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/* Clear Update Flag */
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- tmr_flag_clear(pwm_timer, TMR_OVF_FLAG);
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+ tmr_flag_clear(MOS_PWM_TIMER, TMR_OVF_FLAG);
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}
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void pwm_enable_output(bool enable) {
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if (enable) {
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- tmr_output_enable(pwm_timer,TRUE);
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+ tmr_output_enable(MOS_PWM_TIMER,TRUE);
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}else {
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- tmr_output_enable(pwm_timer,FALSE);
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+ tmr_output_enable(MOS_PWM_TIMER,FALSE);
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}
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}
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@@ -238,11 +238,11 @@ void pwm_turn_on_low_side(void)
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{
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pwm_update_duty(0, 0, 0);
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pwm_update_2smaples(FOC_PWM_Half_Period-1, FOC_PWM_Half_Period + 1);
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- tmr_flag_clear(pwm_timer, TMR_OVF_FLAG);
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- tmr_event_sw_trigger(pwm_timer, TMR_OVERFLOW_SWTRIG);
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- while ( tmr_flag_get(pwm_timer, TMR_OVF_FLAG) == RESET ){}
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+ tmr_flag_clear(MOS_PWM_TIMER, TMR_OVF_FLAG);
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+ tmr_event_sw_trigger(MOS_PWM_TIMER, TMR_OVERFLOW_SWTRIG);
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+ while ( tmr_flag_get(MOS_PWM_TIMER, TMR_OVF_FLAG) == RESET ){}
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/* Main PWM Output Enable */
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- tmr_output_enable(pwm_timer,TRUE);
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+ tmr_output_enable(MOS_PWM_TIMER,TRUE);
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}
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void pwm_update_sample(u32 samp1, u32 samp2, u8 sector) {
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