add AT32 driver & cmsis

Signed-off-by: huhui <huhui@sharkgulf.com>

Librarys/AT32F41x_Drivers/inc/at32f413_acc.h

@@ -0,0 +1,200 @@
+/**
+  **************************************************************************
+  * @file     at32f413_acc.h
+  * @brief    at32f413 acc header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_ACC_H
+#define __AT32F413_ACC_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup ACC
+  * @{
+  */
+
+/** @defgroup ACC_exported_constants
+  * @{
+  */
+
+#define ACC_CAL_HICKCAL                  ((uint16_t)0x0000) /*!< acc hick calibration */
+#define ACC_CAL_HICKTRIM                 ((uint16_t)0x0002) /*!< acc hick trim */
+
+#define ACC_RSLOST_FLAG                  ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
+#define ACC_CALRDY_FLAG                  ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
+
+#define ACC_CALRDYIEN_INT                ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
+#define ACC_EIEN_INT                     ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
+
+/**
+  * @}
+  */
+
+/** @defgroup ACC_exported_types
+  * @{
+  */
+
+/**
+  * @brief type define acc register all
+  */
+typedef struct
+{
+
+  /**
+    * @brief acc sts register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t sts;
+    struct
+    {
+      __IO uint32_t calrdy               : 1; /* [0] */
+      __IO uint32_t rslost               : 1; /* [1] */
+      __IO uint32_t reserved1            : 30;/* [31:2] */
+    } sts_bit;
+  };
+
+  /**
+    * @brief acc ctrl1 register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t ctrl1;
+    struct
+    {
+      __IO uint32_t calon                : 1; /* [0] */
+      __IO uint32_t entrim               : 1; /* [1] */
+      __IO uint32_t reserved1            : 2; /* [3:2] */
+      __IO uint32_t eien                 : 1; /* [4] */
+      __IO uint32_t calrdyien            : 1; /* [5] */
+      __IO uint32_t reserved2            : 2; /* [7:6] */
+      __IO uint32_t step                 : 4; /* [11:8] */
+      __IO uint32_t reserved3            : 20;/* [31:12] */
+    } ctrl1_bit;
+  };
+
+   /**
+    * @brief acc ctrl2 register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t ctrl2;
+    struct
+    {
+      __IO uint32_t hickcal              : 8; /* [7:0] */
+      __IO uint32_t hicktrim             : 6; /* [13:8] */
+      __IO uint32_t reserved1            : 18;/* [31:14] */
+    } ctrl2_bit;
+  };
+
+  /**
+  * @brief acc acc_c1 register, offset:0x0C
+  */
+  union
+  {
+    __IO uint32_t c1;
+    struct
+    {
+      __IO uint32_t c1                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } c1_bit;
+  };
+
+  /**
+  * @brief acc acc_c2 register, offset:0x10
+  */
+  union
+  {
+    __IO uint32_t c2;
+    struct
+    {
+      __IO uint32_t c2                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } c2_bit;
+  };
+
+  /**
+  * @brief acc acc_c3 register, offset:0x14
+  */
+  union
+  {
+    __IO uint32_t c3;
+    struct
+    {
+      __IO uint32_t c3                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } c3_bit;
+  };
+} acc_type;
+
+/**
+  * @}
+  */
+
+#define ACC                             ((acc_type *) ACC_BASE)
+
+/** @defgroup ACC_exported_functions
+  * @{
+  */
+
+void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
+void acc_step_set(uint8_t step_value);
+void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
+uint8_t acc_hicktrim_get(void);
+uint8_t acc_hickcal_get(void);
+void acc_write_c1(uint16_t acc_c1_value);
+void acc_write_c2(uint16_t acc_c2_value);
+void acc_write_c3(uint16_t acc_c3_value);
+uint16_t acc_read_c1(void);
+uint16_t acc_read_c2(void);
+uint16_t acc_read_c3(void);
+flag_status acc_flag_get(uint16_t acc_flag);
+void acc_flag_clear(uint16_t acc_flag);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_adc.h

@@ -0,0 +1,615 @@
+/**
+  **************************************************************************
+  * @file     at32f413_adc.h
+  * @brief    at32f413 adc header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_ADC_H
+#define __AT32F413_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_interrupts_definition
+  * @brief adc interrupt
+  * @{
+  */
+
+#define ADC_CCE_INT                      ((uint32_t)0x00000020) /*!< channels conversion end interrupt */
+#define ADC_VMOR_INT                     ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
+#define ADC_PCCE_INT                     ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition
+  * @brief adc flag
+  * @{
+  */
+
+#define ADC_VMOR_FLAG                    ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
+#define ADC_CCE_FLAG                     ((uint8_t)0x02) /*!< channels conversion end flag */
+#define ADC_PCCE_FLAG                    ((uint8_t)0x04) /*!< preempt channels conversion end flag */
+#define ADC_PCCS_FLAG                    ((uint8_t)0x08) /*!< preempt channel conversion start flag */
+#define ADC_OCCS_FLAG                    ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_exported_types
+  * @{
+  */
+
+/**
+  * @brief adc combine mode type(these options are reserved in adc2)
+  */
+typedef enum
+{
+  ADC_INDEPENDENT_MODE                      = 0x00, /*!< independent mode */
+  ADC_ORDINARY_SMLT_PREEMPT_SMLT_MODE       = 0x01, /*!< combined ordinary simultaneous + preempt simultaneous mode */
+  ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_MODE = 0x02, /*!< combined ordinary simultaneous + preempt interleaved trigger mode */
+  ADC_ORDINARY_SHORTSHIFT_PREEMPT_SMLT_MODE = 0x03, /*!< combined ordinary short shifting + preempt simultaneous mode */
+  ADC_ORDINARY_LONGSHIFT_PREEMPT_SMLT_MODE  = 0x04, /*!< combined ordinary long shifting + preempt simultaneous mode */
+  ADC_PREEMPT_SMLT_ONLY_MODE                = 0x05, /*!< preempt simultaneous mode only */
+  ADC_ORDINARY_SMLT_ONLY_MODE               = 0x06, /*!< ordinary simultaneous mode only */
+  ADC_ORDINARY_SHORTSHIFT_ONLY_MODE         = 0x07, /*!< ordinary short shifting mode only */
+  ADC_ORDINARY_LONGSHIFT_ONLY_MODE          = 0x08, /*!< slow interleaved mode only */
+  ADC_PREEMPT_INTERLTRIG_ONLY_MODE          = 0x09  /*!< alternate trigger mode only */
+} adc_combine_mode_type;
+
+/**
+  * @brief adc data align type
+  */
+typedef enum
+{
+  ADC_RIGHT_ALIGNMENT                    = 0x00, /*!< data right alignment */
+  ADC_LEFT_ALIGNMENT                     = 0x01  /*!< data left alignment */
+} adc_data_align_type;
+
+/**
+  * @brief adc channel select type
+  */
+typedef enum
+{
+  ADC_CHANNEL_0                          = 0x00, /*!< adc channel 0 */
+  ADC_CHANNEL_1                          = 0x01, /*!< adc channel 1 */
+  ADC_CHANNEL_2                          = 0x02, /*!< adc channel 2 */
+  ADC_CHANNEL_3                          = 0x03, /*!< adc channel 3 */
+  ADC_CHANNEL_4                          = 0x04, /*!< adc channel 4 */
+  ADC_CHANNEL_5                          = 0x05, /*!< adc channel 5 */
+  ADC_CHANNEL_6                          = 0x06, /*!< adc channel 6 */
+  ADC_CHANNEL_7                          = 0x07, /*!< adc channel 7 */
+  ADC_CHANNEL_8                          = 0x08, /*!< adc channel 8 */
+  ADC_CHANNEL_9                          = 0x09, /*!< adc channel 9 */
+  ADC_CHANNEL_10                         = 0x0A, /*!< adc channel 10 */
+  ADC_CHANNEL_11                         = 0x0B, /*!< adc channel 11 */
+  ADC_CHANNEL_12                         = 0x0C, /*!< adc channel 12 */
+  ADC_CHANNEL_13                         = 0x0D, /*!< adc channel 13 */
+  ADC_CHANNEL_14                         = 0x0E, /*!< adc channel 14 */
+  ADC_CHANNEL_15                         = 0x0F, /*!< adc channel 15 */
+  ADC_CHANNEL_16                         = 0x10, /*!< adc channel 16 */
+  ADC_CHANNEL_17                         = 0x11  /*!< adc channel 17 */
+} adc_channel_select_type;
+
+/**
+  * @brief adc sampletime select type
+  */
+typedef enum
+{
+  ADC_SAMPLETIME_1_5                     = 0x00, /*!< adc sample time 1.5 cycle */
+  ADC_SAMPLETIME_7_5                     = 0x01, /*!< adc sample time 7.5 cycle */
+  ADC_SAMPLETIME_13_5                    = 0x02, /*!< adc sample time 13.5 cycle */
+  ADC_SAMPLETIME_28_5                    = 0x03, /*!< adc sample time 28.5 cycle */
+  ADC_SAMPLETIME_41_5                    = 0x04, /*!< adc sample time 41.5 cycle */
+  ADC_SAMPLETIME_55_5                    = 0x05, /*!< adc sample time 55.5 cycle */
+  ADC_SAMPLETIME_71_5                    = 0x06, /*!< adc sample time 71.5 cycle */
+  ADC_SAMPLETIME_239_5                   = 0x07  /*!< adc sample time 239.5 cycle */
+} adc_sampletime_select_type;
+
+/**
+  * @brief adc ordinary group trigger event select type
+  */
+typedef enum
+{
+  /*adc1 and adc2 ordinary trigger event*/
+  ADC12_ORDINARY_TRIG_TMR1CH1            = 0x00, /*!< timer1 ch1 event as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_TMR1CH2            = 0x01, /*!< timer1 ch2 event as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_TMR1CH3            = 0x02, /*!< timer1 ch3 event as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_TMR2CH2            = 0x03, /*!< timer2 ch2 event as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_TMR3TRGOUT         = 0x04, /*!< timer3 trgout event as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_TMR4CH4            = 0x05, /*!< timer4 ch4 event as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_EXINT11_TMR8TRGOUT = 0x06, /*!< exint line11/timer8 trgout event as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_SOFTWARE           = 0x07, /*!< software(OCSWTRG) control bit as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_TMR1TRGOUT         = 0x0D, /*!< timer1 trgout event as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_TMR8CH1            = 0x0E, /*!< timer8 ch1 event as trigger source of adc1/adc2 ordinary sequence */
+  ADC12_ORDINARY_TRIG_TMR8CH2            = 0x0F, /*!< timer8 ch2 event as trigger source of adc1/adc2 ordinary sequence */
+} adc_ordinary_trig_select_type;
+
+/**
+  * @brief adc preempt group trigger event select type
+  */
+typedef enum
+{
+  /*adc1 and adc2 preempt trigger event*/
+  ADC12_PREEMPT_TRIG_TMR1TRGOUT          = 0x00, /*!< timer1 trgout event as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_TMR1CH4             = 0x01, /*!< timer1 ch4 event as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_TMR2TRGOUT          = 0x02, /*!< timer2 trgout event as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_TMR2CH1             = 0x03, /*!< timer2 ch1 event as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_TMR3CH4             = 0x04, /*!< timer3 ch4 event as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_TMR4TRGOUT          = 0x05, /*!< timer4 trgout event as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_EXINT15_TMR8CH4     = 0x06, /*!< exint line15/timer8 ch4 event as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_SOFTWARE            = 0x07, /*!< software(PCSWTRG) control bit as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_TMR1CH1             = 0x0D, /*!< timer1 ch1 event as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_TMR8CH1             = 0x0E, /*!< timer8 ch1 event as trigger source of adc1/adc2 preempt sequence */
+  ADC12_PREEMPT_TRIG_TMR8TRGOUT          = 0x0F, /*!< timer8 trgout event as trigger source of adc1/adc2 preempt sequence */
+} adc_preempt_trig_select_type;
+
+/**
+  * @brief adc preempt channel type
+  */
+typedef enum
+{
+  ADC_PREEMPT_CHANNEL_1                  = 0x00, /*!< adc preempt channel 1 */
+  ADC_PREEMPT_CHANNEL_2                  = 0x01, /*!< adc preempt channel 2 */
+  ADC_PREEMPT_CHANNEL_3                  = 0x02, /*!< adc preempt channel 3 */
+  ADC_PREEMPT_CHANNEL_4                  = 0x03  /*!< adc preempt channel 4 */
+} adc_preempt_channel_type;
+
+/**
+  * @brief adc voltage_monitoring type
+  */
+typedef enum
+{
+  ADC_VMONITOR_SINGLE_ORDINARY           = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
+  ADC_VMONITOR_SINGLE_PREEMPT            = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
+  ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT   = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
+  ADC_VMONITOR_ALL_ORDINARY              = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
+  ADC_VMONITOR_ALL_PREEMPT               = 0x00400000, /*!< voltage_monitoring on all preempt channel */
+  ADC_VMONITOR_ALL_ORDINARY_PREEMPT      = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
+  ADC_VMONITOR_NONE                      = 0x00000000  /*!< no channel guarded by the voltage_monitoring */
+} adc_voltage_monitoring_type;
+
+/**
+  * @brief adc base config type
+  */
+typedef struct
+{
+  confirm_state                          sequence_mode;           /*!< adc sequence mode */
+  confirm_state                          repeat_mode;             /*!< adc repeat mode */
+  adc_data_align_type                    data_align;              /*!< adc data alignment */
+  uint8_t                                ordinary_channel_length; /*!< adc ordinary channel sequence length*/
+} adc_base_config_type;
+
+/**
+  * @brief type define adc register all
+  */
+typedef struct
+{
+
+  /**
+    * @brief adc sts register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t sts;
+    struct
+    {
+      __IO uint32_t vmor                 : 1; /* [0] */
+      __IO uint32_t cce                  : 1; /* [1] */
+      __IO uint32_t pcce                 : 1; /* [2] */
+      __IO uint32_t pccs                 : 1; /* [3] */
+      __IO uint32_t occs                 : 1; /* [4] */
+      __IO uint32_t reserved1            : 27;/* [31:5] */
+    } sts_bit;
+  };
+
+  /**
+    * @brief adc ctrl1 register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t ctrl1;
+    struct
+    {
+      __IO uint32_t vmcsel               : 5; /* [4:0] */
+      __IO uint32_t cceien               : 1; /* [5] */
+      __IO uint32_t vmorien              : 1; /* [6] */
+      __IO uint32_t pcceien              : 1; /* [7] */
+      __IO uint32_t sqen                 : 1; /* [8] */
+      __IO uint32_t vmsgen               : 1; /* [9] */
+      __IO uint32_t pcautoen             : 1; /* [10] */
+      __IO uint32_t ocpen                : 1; /* [11] */
+      __IO uint32_t pcpen                : 1; /* [12] */
+      __IO uint32_t ocpcnt               : 3; /* [15:13] */
+      __IO uint32_t mssel                : 4; /* [19:16] */
+      __IO uint32_t reserved1            : 2; /* [21:20] */
+      __IO uint32_t pcvmen               : 1; /* [22] */
+      __IO uint32_t ocvmen               : 1; /* [23] */
+      __IO uint32_t reserved2            : 8; /* [31:24] */
+    } ctrl1_bit;
+  };
+
+   /**
+    * @brief adc ctrl2 register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t ctrl2;
+    struct
+    {
+      __IO uint32_t adcen                : 1; /* [0] */
+      __IO uint32_t rpen                 : 1; /* [1] */
+      __IO uint32_t adcal                : 1; /* [2] */
+      __IO uint32_t adcalinit            : 1; /* [3] */
+      __IO uint32_t reserved1            : 4; /* [7:4] */
+      __IO uint32_t ocdmaen              : 1; /* [8] */
+      __IO uint32_t reserved2            : 2; /* [10:9] */
+      __IO uint32_t dtalign              : 1; /* [11] */
+      __IO uint32_t pctesel_l            : 3; /* [14:12] */
+      __IO uint32_t pcten                : 1; /* [15] */
+      __IO uint32_t reserved3            : 1; /* [16] */
+      __IO uint32_t octesel_l            : 3; /* [19:17] */
+      __IO uint32_t octen                : 1; /* [20] */
+      __IO uint32_t pcswtrg              : 1; /* [21] */
+      __IO uint32_t ocswtrg              : 1; /* [22] */
+      __IO uint32_t itsrven              : 1; /* [23] */
+      __IO uint32_t pctesel_h            : 1; /* [24] */
+      __IO uint32_t octesel_h            : 1; /* [25] */
+      __IO uint32_t reserved4            : 6; /* [31:26] */
+    } ctrl2_bit;
+  };
+
+  /**
+  * @brief adc spt1 register, offset:0x0C
+  */
+  union
+  {
+    __IO uint32_t spt1;
+    struct
+    {
+      __IO uint32_t cspt10               : 3; /* [2:0] */
+      __IO uint32_t cspt11               : 3; /* [5:3] */
+      __IO uint32_t cspt12               : 3; /* [8:6] */
+      __IO uint32_t cspt13               : 3; /* [11:9] */
+      __IO uint32_t cspt14               : 3; /* [14:12] */
+      __IO uint32_t cspt15               : 3; /* [17:15] */
+      __IO uint32_t cspt16               : 3; /* [20:18] */
+      __IO uint32_t cspt17               : 3; /* [23:21] */
+      __IO uint32_t reserved1            : 8;/* [31:24] */
+    } spt1_bit;
+  };
+
+  /**
+  * @brief adc spt2 register, offset:0x10
+  */
+  union
+  {
+    __IO uint32_t spt2;
+    struct
+    {
+      __IO uint32_t cspt0                : 3;/* [2:0] */
+      __IO uint32_t cspt1                : 3;/* [5:3] */
+      __IO uint32_t cspt2                : 3;/* [8:6] */
+      __IO uint32_t cspt3                : 3;/* [11:9] */
+      __IO uint32_t cspt4                : 3;/* [14:12] */
+      __IO uint32_t cspt5                : 3;/* [17:15] */
+      __IO uint32_t cspt6                : 3;/* [20:18] */
+      __IO uint32_t cspt7                : 3;/* [23:21] */
+      __IO uint32_t cspt8                : 3;/* [26:24] */
+      __IO uint32_t cspt9                : 3;/* [29:27] */
+      __IO uint32_t reserved1            : 2;/* [31:30] */
+    } spt2_bit;
+  };
+
+  /**
+  * @brief adc pcdto1 register, offset:0x14
+  */
+  union
+  {
+    __IO uint32_t pcdto1;
+    struct
+    {
+      __IO uint32_t pcdto1               : 12; /* [11:0] */
+      __IO uint32_t reserved1            : 20; /* [31:12] */
+    } pcdto1_bit;
+  };
+
+  /**
+  * @brief adc pcdto2 register, offset:0x18
+  */
+  union
+  {
+    __IO uint32_t pcdto2;
+    struct
+    {
+      __IO uint32_t pcdto2               : 12; /* [11:0] */
+      __IO uint32_t reserved1            : 20; /* [31:12] */
+    } pcdto2_bit;
+  };
+
+  /**
+  * @brief adc pcdto3 register, offset:0x1C
+  */
+  union
+  {
+    __IO uint32_t pcdto3;
+    struct
+    {
+      __IO uint32_t pcdto3               : 12; /* [11:0] */
+      __IO uint32_t reserved1            : 20; /* [31:12] */
+    } pcdto3_bit;
+  };
+
+  /**
+  * @brief adc pcdto4 register, offset:0x20
+  */
+  union
+  {
+    __IO uint32_t pcdto4;
+    struct
+    {
+      __IO uint32_t pcdto4               : 12; /* [11:0] */
+      __IO uint32_t reserved1            : 20; /* [31:12] */
+    } pcdto4_bit;
+  };
+
+  /**
+  * @brief adc vmhb register, offset:0x24
+  */
+  union
+  {
+    __IO uint32_t vmhb;
+    struct
+    {
+      __IO uint32_t vmhb                 : 12; /* [11:0] */
+      __IO uint32_t reserved1            : 20; /* [31:12] */
+    } vmhb_bit;
+  };
+
+  /**
+  * @brief adc vmlb register, offset:0x28
+  */
+  union
+  {
+    __IO uint32_t vmlb;
+    struct
+    {
+      __IO uint32_t vmlb                 : 12; /* [11:0] */
+      __IO uint32_t reserved1            : 20; /* [31:12] */
+    } vmlb_bit;
+  };
+
+  /**
+  * @brief adc osq1 register, offset:0x2C
+  */
+  union
+  {
+    __IO uint32_t osq1;
+    struct
+    {
+      __IO uint32_t osn13                : 5; /* [4:0] */
+      __IO uint32_t osn14                : 5; /* [9:5] */
+      __IO uint32_t osn15                : 5; /* [14:10] */
+      __IO uint32_t osn16                : 5; /* [19:15] */
+      __IO uint32_t oclen                : 4; /* [23:20] */
+      __IO uint32_t reserved1            : 8; /* [31:24] */
+    } osq1_bit;
+  };
+
+  /**
+  * @brief adc osq2 register, offset:0x30
+  */
+  union
+  {
+    __IO uint32_t osq2;
+    struct
+    {
+      __IO uint32_t osn7                 : 5; /* [4:0] */
+      __IO uint32_t osn8                 : 5; /* [9:5] */
+      __IO uint32_t osn9                 : 5; /* [14:10] */
+      __IO uint32_t osn10                : 5; /* [19:15] */
+      __IO uint32_t osn11                : 5; /* [24:20] */
+      __IO uint32_t osn12                : 5; /* [29:25] */
+      __IO uint32_t reserved1            : 2; /* [31:30] */
+    } osq2_bit;
+  };
+
+  /**
+  * @brief adc osq3 register, offset:0x34
+  */
+  union
+  {
+    __IO uint32_t osq3;
+    struct
+    {
+      __IO uint32_t osn1                 : 5; /* [4:0] */
+      __IO uint32_t osn2                 : 5; /* [9:5] */
+      __IO uint32_t osn3                 : 5; /* [14:10] */
+      __IO uint32_t osn4                 : 5; /* [19:15] */
+      __IO uint32_t osn5                 : 5; /* [24:20] */
+      __IO uint32_t osn6                 : 5; /* [29:25] */
+      __IO uint32_t reserved1            : 2; /* [31:30] */
+    } osq3_bit;
+  };
+
+  /**
+  * @brief adc psq register, offset:0x38
+  */
+  union
+  {
+    __IO uint32_t psq;
+    struct
+    {
+      __IO uint32_t psn1                 : 5; /* [4:0] */
+      __IO uint32_t psn2                 : 5; /* [9:5] */
+      __IO uint32_t psn3                 : 5; /* [14:10] */
+      __IO uint32_t psn4                 : 5; /* [19:15] */
+      __IO uint32_t pclen                : 2; /* [21:20] */
+      __IO uint32_t reserved1            : 10;/* [31:22] */
+    } psq_bit;
+  };
+
+  /**
+  * @brief adc pdt1 register, offset:0x3C
+  */
+  union
+  {
+    __IO uint32_t pdt1;
+    struct
+    {
+      __IO uint32_t pdt1                 : 16; /* [15:0] */
+      __IO uint32_t reserved1            : 16; /* [31:16] */
+    } pdt1_bit;
+  };
+
+  /**
+  * @brief adc pdt2 register, offset:0x40
+  */
+  union
+  {
+    __IO uint32_t pdt2;
+    struct
+    {
+      __IO uint32_t pdt2                 : 16; /* [15:0] */
+      __IO uint32_t reserved1            : 16; /* [31:16] */
+    } pdt2_bit;
+  };
+
+  /**
+  * @brief adc pdt3 register, offset:0x44
+  */
+  union
+  {
+    __IO uint32_t pdt3;
+    struct
+    {
+      __IO uint32_t pdt3                 : 16; /* [15:0] */
+      __IO uint32_t reserved1            : 16; /* [31:16] */
+    } pdt3_bit;
+  };
+
+  /**
+  * @brief adc pdt4 register, offset:0x48
+  */
+  union
+  {
+    __IO uint32_t pdt4;
+    struct
+    {
+      __IO uint32_t pdt4                 : 16; /* [15:0] */
+      __IO uint32_t reserved1            : 16; /* [31:16] */
+    } pdt4_bit;
+  };
+
+  /**
+  * @brief adc odt register, offset:0x4C
+  */
+  union
+  {
+    __IO uint32_t odt;
+    struct
+    {
+      __IO uint32_t odt                  : 16; /* [15:0] */
+      __IO uint32_t adc2odt              : 16; /* [31:16] */
+    } odt_bit;
+  };
+
+} adc_type;
+
+/**
+  * @}
+  */
+
+#define ADC1                             ((adc_type *) ADC1_BASE)
+#define ADC2                             ((adc_type *) ADC2_BASE)
+
+/** @defgroup ADC_exported_functions
+  * @{
+  */
+
+void adc_reset(adc_type *adc_x);
+void adc_enable(adc_type *adc_x, confirm_state new_state);
+void adc_combine_mode_select(adc_combine_mode_type combine_mode);
+void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
+void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
+void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
+void adc_calibration_init(adc_type *adc_x);
+flag_status adc_calibration_init_status_get(adc_type *adc_x);
+void adc_calibration_start(adc_type *adc_x);
+flag_status adc_calibration_status_get(adc_type *adc_x);
+void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
+void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
+void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
+void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
+void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
+void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
+void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state);
+void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state);
+void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
+void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
+void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_tempersensor_vintrv_enable(confirm_state new_state);
+void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
+flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
+void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
+flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
+uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
+uint32_t adc_combine_ordinary_conversion_data_get(void);
+uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
+flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
+void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_bpr.h

@@ -0,0 +1,787 @@
+/**
+  **************************************************************************
+  * @file     at32f413_bpr.h
+  * @brief    at32f413 bpr header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_BPR_H
+#define __AT32F413_BPR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup BPR
+  * @{
+  */
+
+/** @defgroup BPR_flags_definition
+  * @brief bpr flag
+  * @{
+  */
+
+#define BPR_TAMPER_INTERRUPT_FLAG        ((uint32_t)0x00000001) /*!< bpr tamper interrupt flag */
+#define BPR_TAMPER_EVENT_FLAG            ((uint32_t)0x00000002) /*!< bpr tamper event flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup BPR_exported_types
+  * @{
+  */
+
+/**
+  * @brief battery powered register data type
+  */
+typedef enum
+{
+  BPR_DATA1                              = 0x04, /*!< bpr data register 1 */
+  BPR_DATA2                              = 0x08, /*!< bpr data register 2 */
+  BPR_DATA3                              = 0x0C, /*!< bpr data register 3 */
+  BPR_DATA4                              = 0x10, /*!< bpr data register 4 */
+  BPR_DATA5                              = 0x14, /*!< bpr data register 5 */
+  BPR_DATA6                              = 0x18, /*!< bpr data register 6 */
+  BPR_DATA7                              = 0x1C, /*!< bpr data register 7 */
+  BPR_DATA8                              = 0x20, /*!< bpr data register 8 */
+  BPR_DATA9                              = 0x24, /*!< bpr data register 9 */
+  BPR_DATA10                             = 0x28, /*!< bpr data register 10 */
+  BPR_DATA11                             = 0x40, /*!< bpr data register 11 */
+  BPR_DATA12                             = 0x44, /*!< bpr data register 12 */
+  BPR_DATA13                             = 0x48, /*!< bpr data register 13 */
+  BPR_DATA14                             = 0x4C, /*!< bpr data register 14 */
+  BPR_DATA15                             = 0x50, /*!< bpr data register 15 */
+  BPR_DATA16                             = 0x54, /*!< bpr data register 16 */
+  BPR_DATA17                             = 0x58, /*!< bpr data register 17 */
+  BPR_DATA18                             = 0x5C, /*!< bpr data register 18 */
+  BPR_DATA19                             = 0x60, /*!< bpr data register 19 */
+  BPR_DATA20                             = 0x64, /*!< bpr data register 20 */
+  BPR_DATA21                             = 0x68, /*!< bpr data register 21 */
+  BPR_DATA22                             = 0x6C, /*!< bpr data register 22 */
+  BPR_DATA23                             = 0x70, /*!< bpr data register 23 */
+  BPR_DATA24                             = 0x74, /*!< bpr data register 24 */
+  BPR_DATA25                             = 0x78, /*!< bpr data register 25 */
+  BPR_DATA26                             = 0x7C, /*!< bpr data register 26 */
+  BPR_DATA27                             = 0x80, /*!< bpr data register 27 */
+  BPR_DATA28                             = 0x84, /*!< bpr data register 28 */
+  BPR_DATA29                             = 0x88, /*!< bpr data register 29 */
+  BPR_DATA30                             = 0x8C, /*!< bpr data register 30 */
+  BPR_DATA31                             = 0x90, /*!< bpr data register 31 */
+  BPR_DATA32                             = 0x94, /*!< bpr data register 32 */
+  BPR_DATA33                             = 0x98, /*!< bpr data register 33 */
+  BPR_DATA34                             = 0x9C, /*!< bpr data register 34 */
+  BPR_DATA35                             = 0xA0, /*!< bpr data register 35 */
+  BPR_DATA36                             = 0xA4, /*!< bpr data register 36 */
+  BPR_DATA37                             = 0xA8, /*!< bpr data register 37 */
+  BPR_DATA38                             = 0xAC, /*!< bpr data register 38 */
+  BPR_DATA39                             = 0xB0, /*!< bpr data register 39 */
+  BPR_DATA40                             = 0xB4, /*!< bpr data register 40 */
+  BPR_DATA41                             = 0xB8, /*!< bpr data register 41 */
+  BPR_DATA42                             = 0xBC  /*!< bpr data register 42 */
+} bpr_data_type;
+
+/**
+  * @brief bpr rtc output type
+  */
+typedef enum
+{
+  BPR_RTC_OUTPUT_NONE                    = 0x000, /*!< output disable */
+  BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE        = 0x080, /*!< output clock before calibration */
+  BPR_RTC_OUTPUT_ALARM                   = 0x100, /*!< output alarm event with pluse mode */
+  BPR_RTC_OUTPUT_SECOND                  = 0x300, /*!< output second event with pluse mode */
+  BPR_RTC_OUTPUT_CLOCK_CAL_AFTER         = 0x480, /*!< output clock after calibration */
+  BPR_RTC_OUTPUT_ALARM_TOGGLE            = 0x900, /*!< output alarm event with toggle mode */
+  BPR_RTC_OUTPUT_SECOND_TOGGLE           = 0xB00  /*!< output second event with toggle mode */
+} bpr_rtc_output_type;
+
+/**
+  * @brief tamper pin active level type
+  */
+typedef enum
+{
+  BPR_TAMPER_PIN_ACTIVE_HIGH             = 0x00, /*!< tamper pin input active level is high */
+  BPR_TAMPER_PIN_ACTIVE_LOW              = 0x01  /*!< tamper pin input active level is low */
+} bpr_tamper_pin_active_level_type;
+
+/**
+  * @brief type define bpr register all
+  */
+typedef struct
+{
+  /**
+    * @brief reserved, offset:0x00
+    */
+  __IO uint32_t reserved1;
+
+  /**
+    * @brief bpr dt1 register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t dt1;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt1_bit;
+  };
+
+  /**
+    * @brief bpr dt2 register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t dt2;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt2_bit;
+  };
+
+  /**
+    * @brief bpr dt3 register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t dt3;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt3_bit;
+  };
+
+  /**
+    * @brief bpr dt4 register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t dt4;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt4_bit;
+  };
+
+  /**
+    * @brief bpr dt5 register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t dt5;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt5_bit;
+  };
+
+  /**
+    * @brief bpr dt6 register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t dt6;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt6_bit;
+  };
+
+  /**
+    * @brief bpr dt7 register, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t dt7;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt7_bit;
+  };
+
+  /**
+    * @brief bpr dt8 register, offset:0x20
+    */
+  union
+  {
+    __IO uint32_t dt8;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt8_bit;
+  };
+
+  /**
+    * @brief bpr dt9 register, offset:0x24
+    */
+  union
+  {
+    __IO uint32_t dt9;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt9_bit;
+  };
+
+  /**
+    * @brief bpr dt10 register, offset:0x28
+    */
+  union
+  {
+    __IO uint32_t dt10;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt10_bit;
+  };
+
+  /**
+    * @brief bpr rtccal register, offset:0x2C
+    */
+  union
+  {
+    __IO uint32_t rtccal;
+    struct
+    {
+      __IO uint32_t calval               : 7; /* [6:0] */
+      __IO uint32_t calout               : 1; /* [7] */
+      __IO uint32_t outen                : 1; /* [8] */
+      __IO uint32_t outsel               : 1; /* [9] */
+      __IO uint32_t ccos                 : 1; /* [10] */
+      __IO uint32_t outm                 : 1; /* [11] */
+      __IO uint32_t reserved1            : 20;/* [31:12] */
+    } rtccal_bit;
+  };
+
+  /**
+    * @brief bpr ctrl register, offset:0x30
+    */
+  union
+  {
+    __IO uint32_t ctrl;
+    struct
+    {
+      __IO uint32_t tpen                 : 1; /* [0] */
+      __IO uint32_t tpp                  : 1; /* [1] */
+      __IO uint32_t reserved1            : 30;/* [31:2] */
+    } ctrl_bit;
+  };
+
+  /**
+    * @brief bpr ctrlsts register, offset:0x34
+    */
+  union
+  {
+    __IO uint32_t ctrlsts;
+    struct
+    {
+      __IO uint32_t tpefclr              : 1;/* [0] */
+      __IO uint32_t tpifclr              : 1;/* [1] */
+      __IO uint32_t tpien                : 1;/* [2] */
+      __IO uint32_t reserved1            : 5;/* [7:3] */
+      __IO uint32_t tpef                 : 1;/* [8] */
+      __IO uint32_t tpif                 : 1;/* [9] */
+      __IO uint32_t reserved2            : 22;/* [31:10] */
+    } ctrlsts_bit;
+  };
+
+  /**
+    * @brief reserved, offset:0x38
+    */
+  __IO uint32_t reserved2;
+
+  /**
+    * @brief reserved, offset:0x3C
+    */
+  __IO uint32_t reserved3;
+
+  /**
+    * @brief bpr dt11 register, offset:0x40
+    */
+  union
+  {
+    __IO uint32_t dt11;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt11_bit;
+  };
+
+  /**
+    * @brief bpr dt12 register, offset:0x44
+    */
+  union
+  {
+    __IO uint32_t dt12;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt12_bit;
+  };
+
+  /**
+    * @brief bpr dt13 register, offset:0x48
+    */
+  union
+  {
+    __IO uint32_t dt13;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt13_bit;
+  };
+
+  /**
+    * @brief bpr dt14 register, offset:0x4C
+    */
+  union
+  {
+    __IO uint32_t dt14;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt14_bit;
+  };
+
+  /**
+    * @brief bpr dt15 register, offset:0x50
+    */
+  union
+  {
+    __IO uint32_t dt15;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt15_bit;
+  };
+
+  /**
+    * @brief bpr dt16 register, offset:0x54
+    */
+  union
+  {
+    __IO uint32_t dt16;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt16_bit;
+  };
+
+  /**
+    * @brief bpr dt17 register, offset:0x58
+    */
+  union
+  {
+    __IO uint32_t dt17;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt17_bit;
+  };
+
+  /**
+    * @brief bpr dt18 register, offset:0x5C
+    */
+  union
+  {
+    __IO uint32_t dt18;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt18_bit;
+  };
+
+  /**
+    * @brief bpr dt19 register, offset:0x60
+    */
+  union
+  {
+    __IO uint32_t dt19;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt19_bit;
+  };
+
+  /**
+    * @brief bpr dt20 register, offset:0x64
+    */
+  union
+  {
+    __IO uint32_t dt20;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt20_bit;
+  };
+
+  /**
+    * @brief bpr dt21 register, offset:0x68
+    */
+  union
+  {
+    __IO uint32_t dt21;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt21_bit;
+  };
+
+  /**
+    * @brief bpr dt22 register, offset:6C
+    */
+  union
+  {
+    __IO uint32_t dt22;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt22_bit;
+  };
+
+  /**
+    * @brief bpr dt23 register, offset:0x70
+    */
+  union
+  {
+    __IO uint32_t dt23;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt23_bit;
+  };
+
+  /**
+    * @brief bpr dt24 register, offset:0x74
+    */
+  union
+  {
+    __IO uint32_t dt24;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt24_bit;
+  };
+
+  /**
+    * @brief bpr dt25 register, offset:0x78
+    */
+  union
+  {
+    __IO uint32_t dt25;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt25_bit;
+  };
+
+  /**
+    * @brief bpr dt26 register, offset:0x7C
+    */
+  union
+  {
+    __IO uint32_t dt26;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt26_bit;
+  };
+
+  /**
+    * @brief bpr dt27 register, offset:0x80
+    */
+  union
+  {
+    __IO uint32_t dt27;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt27_bit;
+  };
+
+  /**
+    * @brief bpr dt28 register, offset:0x84
+    */
+  union
+  {
+    __IO uint32_t dt28;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt28_bit;
+  };
+
+  /**
+    * @brief bpr dt29 register, offset:0x88
+    */
+  union
+  {
+    __IO uint32_t dt29;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt29_bit;
+  };
+
+  /**
+    * @brief bpr dt30 register, offset:0x8C
+    */
+  union
+  {
+    __IO uint32_t dt30;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt30_bit;
+  };
+
+  /**
+    * @brief bpr dt31 register, offset:0x90
+    */
+  union
+  {
+    __IO uint32_t dt31;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt31_bit;
+  };
+
+  /**
+    * @brief bpr dt32 register, offset:0x94
+    */
+  union
+  {
+    __IO uint32_t dt32;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt32_bit;
+  };
+
+  /**
+    * @brief bpr dt33 register, offset:0x98
+    */
+  union
+  {
+    __IO uint32_t dt33;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt33_bit;
+  };
+
+  /**
+    * @brief bpr dt34 register, offset:0x9C
+    */
+  union
+  {
+    __IO uint32_t dt34;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt34_bit;
+  };
+
+  /**
+    * @brief bpr dt35 register, offset:0xA0
+    */
+  union
+  {
+    __IO uint32_t dt35;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt35_bit;
+  };
+
+  /**
+    * @brief bpr dt36 register, offset:0xA4
+    */
+  union
+  {
+    __IO uint32_t dt36;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt36_bit;
+  };
+
+  /**
+    * @brief bpr dt37 register, offset:0xA8
+    */
+  union
+  {
+    __IO uint32_t dt37;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt37_bit;
+  };
+
+  /**
+    * @brief bpr dt38 register, offset:0xAC
+    */
+  union
+  {
+    __IO uint32_t dt38;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt38_bit;
+  };
+
+  /**
+    * @brief bpr dt39 register, offset:0xB0
+    */
+  union
+  {
+    __IO uint32_t dt39;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt39_bit;
+  };
+
+  /**
+    * @brief bpr dt40 register, offset:0xB4
+    */
+  union
+  {
+    __IO uint32_t dt40;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt40_bit;
+  };
+
+  /**
+    * @brief bpr dt41 register, offset:0xB8
+    */
+  union
+  {
+    __IO uint32_t dt41;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt41_bit;
+  };
+
+  /**
+    * @brief bpr dt42 register, offset:0xBC
+    */
+  union
+  {
+    __IO uint32_t dt42;
+    struct
+    {
+      __IO uint32_t dt                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } dt42_bit;
+  };
+} bpr_type;
+
+/**
+  * @}
+  */
+
+#define BPR                              ((bpr_type *) BPR_BASE)
+
+/** @defgroup BPR_exported_functions
+  * @{
+  */
+
+void bpr_reset(void);
+flag_status bpr_flag_get(uint32_t flag);
+void bpr_flag_clear(uint32_t flag);
+void bpr_interrupt_enable(confirm_state new_state);
+uint16_t bpr_data_read(bpr_data_type bpr_data);
+void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value);
+void bpr_rtc_output_select(bpr_rtc_output_type output_source);
+void bpr_rtc_clock_calibration_value_set(uint8_t calibration_value);
+void bpr_tamper_pin_enable(confirm_state new_state);
+void bpr_tamper_pin_active_level_set(bpr_tamper_pin_active_level_type active_level);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_can.h

@@ -0,0 +1,987 @@
+/**
+  **************************************************************************
+  * @file     at32f413_can.h
+  * @brief    at32f413 can header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_CAN_H
+#define __AT32F413_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+
+/** @defgroup CAN_timeout_count
+  * @{
+  */
+
+#define FZC_TIMEOUT                      ((uint32_t)0x0000FFFF) /*!< time out for fzc bit */
+#define DZC_TIMEOUT                      ((uint32_t)0x0000FFFF) /*!< time out for dzc bit */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags_definition
+  * @brief can flag
+  * @{
+  */
+
+#define CAN_EAF_FLAG                     ((uint32_t)0x01) /*!< error active flag */
+#define CAN_EPF_FLAG                     ((uint32_t)0x02) /*!< error passive flag */
+#define CAN_BOF_FLAG                     ((uint32_t)0x03) /*!< bus-off flag */
+#define CAN_ETR_FLAG                     ((uint32_t)0x04) /*!< error type record flag */
+#define CAN_EOIF_FLAG                    ((uint32_t)0x05) /*!< error occur interrupt flag */
+#define CAN_TM0TCF_FLAG                  ((uint32_t)0x06) /*!< transmit mailbox 0 transmission completed flag */
+#define CAN_TM1TCF_FLAG                  ((uint32_t)0x07) /*!< transmit mailbox 1 transmission completed flag */
+#define CAN_TM2TCF_FLAG                  ((uint32_t)0x08) /*!< transmit mailbox 2 transmission completed flag */
+#define CAN_RF0MN_FLAG                   ((uint32_t)0x09) /*!< receive fifo 0 message num flag */
+#define CAN_RF0FF_FLAG                   ((uint32_t)0x0A) /*!< receive fifo 0 full flag */
+#define CAN_RF0OF_FLAG                   ((uint32_t)0x0B) /*!< receive fifo 0 overflow flag */
+#define CAN_RF1MN_FLAG                   ((uint32_t)0x0C) /*!< receive fifo 1 message num flag */
+#define CAN_RF1FF_FLAG                   ((uint32_t)0x0D) /*!< receive fifo 1 full flag */
+#define CAN_RF1OF_FLAG                   ((uint32_t)0x0E) /*!< receive fifo 1 overflow flag */
+#define CAN_QDZIF_FLAG                   ((uint32_t)0x0F) /*!< quit doze mode interrupt flag */
+#define CAN_EDZC_FLAG                    ((uint32_t)0x10) /*!< enter doze mode confirm flag */
+#define CAN_TMEF_FLAG                    ((uint32_t)0x11) /*!< transmit mailbox empty flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_interrupts_definition
+  * @brief can interrupt
+  * @{
+  */
+
+#define CAN_TCIEN_INT                    ((uint32_t)0x00000001) /*!< transmission complete interrupt */
+#define CAN_RF0MIEN_INT                  ((uint32_t)0x00000002) /*!< receive fifo 0 message interrupt */
+#define CAN_RF0FIEN_INT                  ((uint32_t)0x00000004) /*!< receive fifo 0 full interrupt */
+#define CAN_RF0OIEN_INT                  ((uint32_t)0x00000008) /*!< receive fifo 0 overflow interrupt */
+#define CAN_RF1MIEN_INT                  ((uint32_t)0x00000010) /*!< receive fifo 1 message interrupt */
+#define CAN_RF1FIEN_INT                  ((uint32_t)0x00000020) /*!< receive fifo 1 full interrupt */
+#define CAN_RF1OIEN_INT                  ((uint32_t)0x00000040) /*!< receive fifo 1 overflow interrupt */
+#define CAN_EAIEN_INT                    ((uint32_t)0x00000100) /*!< error active interrupt */
+#define CAN_EPIEN_INT                    ((uint32_t)0x00000200) /*!< error passive interrupt */
+#define CAN_BOIEN_INT                    ((uint32_t)0x00000400) /*!< bus-off interrupt */
+#define CAN_ETRIEN_INT                   ((uint32_t)0x00000800) /*!< error type record interrupt */
+#define CAN_EOIEN_INT                    ((uint32_t)0x00008000) /*!< error occur interrupt */
+#define CAN_QDZIEN_INT                   ((uint32_t)0x00010000) /*!< quit doze mode interrupt */
+#define CAN_EDZIEN_INT                   ((uint32_t)0x00020000) /*!< enter doze mode confirm interrupt */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  can flag clear operation macro definition val
+  */
+#define CAN_MSTS_EOIF_VAL                ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
+#define CAN_MSTS_QDZIF_VAL               ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
+#define CAN_MSTS_EDZIF_VAL               ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
+#define CAN_TSTS_TM0TCF_VAL              ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
+#define CAN_TSTS_TM1TCF_VAL              ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
+#define CAN_TSTS_TM2TCF_VAL              ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
+#define CAN_TSTS_TM0CT_VAL               ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
+#define CAN_TSTS_TM1CT_VAL               ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
+#define CAN_TSTS_TM2CT_VAL               ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
+#define CAN_RF0_RF0FF_VAL                ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
+#define CAN_RF0_RF0OF_VAL                ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
+#define CAN_RF0_RF0R_VAL                 ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
+#define CAN_RF1_RF1FF_VAL                ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
+#define CAN_RF1_RF1OF_VAL                ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
+#define CAN_RF1_RF1R_VAL                 ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
+
+/** @defgroup CAN_exported_types
+  * @{
+  */
+
+/**
+  * @brief  can filter fifo
+  */
+typedef enum
+{
+  CAN_FILTER_FIFO0                       = 0x00, /*!< filter fifo 0 assignment for filter x */
+  CAN_FILTER_FIFO1                       = 0x01  /*!< filter fifo 1 assignment for filter x */
+} can_filter_fifo_type;
+
+/**
+  * @brief  can filter mode
+  */
+typedef enum
+{
+  CAN_FILTER_MODE_ID_MASK                = 0x00, /*!< identifier mask mode */
+  CAN_FILTER_MODE_ID_LIST                = 0x01  /*!< identifier list mode */
+} can_filter_mode_type;
+
+/**
+  * @brief  can filter bit width select
+  */
+typedef enum
+{
+  CAN_FILTER_16BIT                       = 0x00, /*!< two 16-bit filters */
+  CAN_FILTER_32BIT                       = 0x01  /*!< one 32-bit filter */
+} can_filter_bit_width_type;
+
+/**
+  * @brief  can mode
+  */
+typedef enum
+{
+  CAN_MODE_COMMUNICATE                   = 0x00, /*!< communication mode */
+  CAN_MODE_LOOPBACK                      = 0x01, /*!< loopback mode */
+  CAN_MODE_LISTENONLY                    = 0x02, /*!< listen-only mode */
+  CAN_MODE_LISTENONLY_LOOPBACK           = 0x03  /*!< loopback combined with listen-only mode */
+} can_mode_type;
+
+/**
+  * @brief  can operating mode
+  */
+typedef enum
+{
+  CAN_OPERATINGMODE_FREEZE               = 0x00, /*!< freeze mode */
+  CAN_OPERATINGMODE_DOZE                 = 0x01, /*!< doze mode */
+  CAN_OPERATINGMODE_COMMUNICATE          = 0x02  /*!< communication mode */
+} can_operating_mode_type;
+
+/**
+  * @brief  can resynchronization adjust width
+  */
+typedef enum
+{
+  CAN_RSAW_1TQ                           = 0x00, /*!< 1 time quantum */
+  CAN_RSAW_2TQ                           = 0x01, /*!< 2 time quantum */
+  CAN_RSAW_3TQ                           = 0x02, /*!< 3 time quantum */
+  CAN_RSAW_4TQ                           = 0x03  /*!< 4 time quantum */
+} can_rsaw_type;
+
+/**
+  * @brief  can bit time segment 1
+  */
+typedef enum
+{
+  CAN_BTS1_1TQ                           = 0x00, /*!< 1 time quantum */
+  CAN_BTS1_2TQ                           = 0x01, /*!< 2 time quantum */
+  CAN_BTS1_3TQ                           = 0x02, /*!< 3 time quantum */
+  CAN_BTS1_4TQ                           = 0x03, /*!< 4 time quantum */
+  CAN_BTS1_5TQ                           = 0x04, /*!< 5 time quantum */
+  CAN_BTS1_6TQ                           = 0x05, /*!< 6 time quantum */
+  CAN_BTS1_7TQ                           = 0x06, /*!< 7 time quantum */
+  CAN_BTS1_8TQ                           = 0x07, /*!< 8 time quantum */
+  CAN_BTS1_9TQ                           = 0x08, /*!< 9 time quantum */
+  CAN_BTS1_10TQ                          = 0x09, /*!< 10 time quantum */
+  CAN_BTS1_11TQ                          = 0x0A, /*!< 11 time quantum */
+  CAN_BTS1_12TQ                          = 0x0B, /*!< 12 time quantum */
+  CAN_BTS1_13TQ                          = 0x0C, /*!< 13 time quantum */
+  CAN_BTS1_14TQ                          = 0x0D, /*!< 14 time quantum */
+  CAN_BTS1_15TQ                          = 0x0E, /*!< 15 time quantum */
+  CAN_BTS1_16TQ                          = 0x0F  /*!< 16 time quantum */
+} can_bts1_type;
+
+/**
+  * @brief  can bit time segment 2
+  */
+typedef enum
+{
+  CAN_BTS2_1TQ                           = 0x00, /*!< 1 time quantum */
+  CAN_BTS2_2TQ                           = 0x01, /*!< 2 time quantum */
+  CAN_BTS2_3TQ                           = 0x02, /*!< 3 time quantum */
+  CAN_BTS2_4TQ                           = 0x03, /*!< 4 time quantum */
+  CAN_BTS2_5TQ                           = 0x04, /*!< 5 time quantum */
+  CAN_BTS2_6TQ                           = 0x05, /*!< 6 time quantum */
+  CAN_BTS2_7TQ                           = 0x06, /*!< 7 time quantum */
+  CAN_BTS2_8TQ                           = 0x07  /*!< 8 time quantum */
+} can_bts2_type;
+
+/**
+  * @brief  can identifier type
+  */
+typedef enum
+{
+  CAN_ID_STANDARD                        = 0x00, /*!< standard Id */
+  CAN_ID_EXTENDED                        = 0x01  /*!< extended Id */
+} can_identifier_type;
+
+/**
+  * @brief  can transmission frame type
+  */
+typedef enum
+{
+  CAN_TFT_DATA                           = 0x00, /*!< data frame */
+  CAN_TFT_REMOTE                         = 0x01  /*!< remote frame */
+} can_trans_frame_type;
+
+/**
+  * @brief  can tx mailboxes
+  */
+typedef enum
+{
+  CAN_TX_MAILBOX0                        = 0x00, /*!< can tx mailbox 0 */
+  CAN_TX_MAILBOX1                        = 0x01, /*!< can tx mailbox 1 */
+  CAN_TX_MAILBOX2                        = 0x02  /*!< can tx mailbox 2 */
+} can_tx_mailbox_num_type;
+
+/**
+  * @brief  can receive fifo
+  */
+typedef enum
+{
+  CAN_RX_FIFO0                           = 0x00, /*!< can fifo 0 used to receive */
+  CAN_RX_FIFO1                           = 0x01  /*!< can fifo 1 used to receive */
+} can_rx_fifo_num_type;
+
+/**
+  * @brief  can transmit status
+  */
+typedef enum
+{
+  CAN_TX_STATUS_FAILED                   = 0x00, /*!< can transmission failed */
+  CAN_TX_STATUS_SUCCESSFUL               = 0x01, /*!< can transmission successful */
+  CAN_TX_STATUS_PENDING                  = 0x02, /*!< can transmission pending */
+  CAN_TX_STATUS_NO_EMPTY                 = 0x04  /*!< can transmission no empty mailbox */
+} can_transmit_status_type;
+
+/**
+  * @brief  can enter doze mode status
+  */
+typedef enum
+{
+  CAN_ENTER_DOZE_FAILED                  = 0x00, /*!< can enter the doze mode failed */
+  CAN_ENTER_DOZE_SUCCESSFUL              = 0x01  /*!< can enter the doze mode successful */
+} can_enter_doze_status_type;
+
+/**
+  * @brief  can quit doze mode status
+  */
+typedef enum
+{
+  CAN_QUIT_DOZE_FAILED                   = 0x00, /*!< can quit doze mode failed */
+  CAN_QUIT_DOZE_SUCCESSFUL               = 0x01  /*!< can quit doze mode successful */
+} can_quit_doze_status_type;
+
+/**
+  * @brief  can message discarding rule select when overflow
+  */
+typedef enum
+{
+  CAN_DISCARDING_FIRST_RECEIVED          = 0x00, /*!< can discarding the first received message */
+  CAN_DISCARDING_LAST_RECEIVED           = 0x01  /*!< can discarding the last received message */
+} can_msg_discarding_rule_type;
+
+/**
+  * @brief  can multiple message sending sequence rule
+  */
+typedef enum
+{
+  CAN_SENDING_BY_ID                      = 0x00, /*!< can sending the minimum id message first*/
+  CAN_SENDING_BY_REQUEST                 = 0x01  /*!< can sending the first request message first */
+} can_msg_sending_rule_type;
+
+/**
+  * @brief  can error type record
+  */
+typedef enum
+{
+  CAN_ERRORRECORD_NOERR                  = 0x00, /*!< no error */
+  CAN_ERRORRECORD_STUFFERR               = 0x01, /*!< stuff error */
+  CAN_ERRORRECORD_FORMERR                = 0x02, /*!< form error */
+  CAN_ERRORRECORD_ACKERR                 = 0x03, /*!< acknowledgment error */
+  CAN_ERRORRECORD_BITRECESSIVEERR        = 0x04, /*!< bit recessive error */
+  CAN_ERRORRECORD_BITDOMINANTERR         = 0x05, /*!< bit dominant error */
+  CAN_ERRORRECORD_CRCERR                 = 0x06, /*!< crc error */
+  CAN_ERRORRECORD_SOFTWARESETERR         = 0x07  /*!< software set error */
+} can_error_record_type;
+
+/**
+  * @brief  can init structure definition
+  */
+typedef struct
+{
+  can_mode_type mode_selection;          /*!< specifies the can mode.*/
+
+  confirm_state ttc_enable;              /*!< time triggered communication mode enable */
+
+  confirm_state aebo_enable;             /*!< automatic exit bus-off enable */
+
+  confirm_state aed_enable;              /*!< automatic exit doze mode enable */
+
+  confirm_state prsf_enable;             /*!< prohibit retransmission when sending fails enable */
+
+  can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
+
+  can_msg_sending_rule_type mmssr_selection;     /*!< multiple message sending sequence rule */
+
+} can_base_type;
+
+/**
+  * @brief  can baudrate structure definition
+  */
+typedef struct
+{
+  uint16_t baudrate_div;                  /*!< baudrate division,this parameter can be 0x001~0x1000.*/
+
+  can_rsaw_type rsaw_size;                /*!< resynchronization adjust width */
+
+  can_bts1_type bts1_size;                /*!< bit time segment 1 */
+
+  can_bts2_type bts2_size;                /*!< bit time segment 2 */
+
+} can_baudrate_type;
+
+/**
+  * @brief  can filter init structure definition
+  */
+typedef struct
+{
+  confirm_state filter_activate_enable;  /*!< enable or disable the filter activate.*/
+
+  can_filter_mode_type filter_mode;      /*!< config the filter mode mask or list.*/
+
+  can_filter_fifo_type filter_fifo;      /*!< config the fifo which will be assigned to the filter. */
+
+  uint8_t filter_number;                 /*!< config the filter number, parameter ranges from 0 to 13. */
+
+  can_filter_bit_width_type filter_bit;  /*!< config the filter bit width 16bit or 32bit.*/
+
+  uint16_t filter_id_high;               /*!< config the filter identification, for 32-bit configuration
+                                              it's high 16 bits, for 16-bit configuration it's first. */
+
+  uint16_t filter_id_low;                /*!< config the filter identification, for 32-bit configuration
+                                              it's low 16 bits, for 16-bit configuration it's second. */
+
+  uint16_t filter_mask_high;             /*!< config the filter mask or identification, according to the filtering mode,
+                                              for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
+
+  uint16_t filter_mask_low;              /*!< config the filter mask or identification, according to the filtering mode,
+                                              for 32-bit configuration it's low 16 bits, for 16-bit configuration it's second. */
+} can_filter_init_type;
+
+/**
+  * @brief  can tx message structure definition
+  */
+typedef struct
+{
+  uint32_t standard_id;                  /*!< specifies the 11 bits standard identifier.
+                                              this parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t extended_id;                  /*!< specifies the 29 bits extended identifier.
+                                              this parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  can_identifier_type id_type;           /*!< specifies identifier type for the transmit message.*/
+
+  can_trans_frame_type frame_type;       /*!< specifies frame type for the transmit message.*/
+
+  uint8_t dlc;                           /*!< specifies frame data length that will be transmitted.
+                                              this parameter can be a value between 0 to 8 */
+
+  uint8_t data[8];                       /*!< contains the transmit data. it ranges from 0 to 0xFF. */
+
+} can_tx_message_type;
+
+/**
+  * @brief  can rx message structure definition
+  */
+typedef struct
+{
+    uint32_t standard_id;                /*!< specifies the 11 bits standard identifier
+                                              this parameter can be a value between 0 to 0x7FF. */
+
+    uint32_t extended_id;                /*!< specifies the 29 bits extended identifier.
+                                              this parameter can be a value between 0 to 0x1FFFFFFF. */
+
+    can_identifier_type id_type;         /*!< specifies identifier type for the receive message.*/
+
+    can_trans_frame_type frame_type;     /*!< specifies frame type for the receive message.*/
+
+    uint8_t dlc;                         /*!< specifies the frame data length that will be received.
+                                              this parameter can be a value between 0 to 8 */
+
+    uint8_t data[8];                     /*!< contains the receive data. it ranges from 0 to 0xFF.*/
+
+    uint8_t filter_index;                /*!< specifies the message stored in which filter
+                                              this parameter can be a value between 0 to 0xFF */
+} can_rx_message_type;
+
+/**
+  * @brief can controller area network tx mailbox
+  */
+typedef struct
+{
+  /**
+    * @brief can tmi register
+    */
+  union
+  {
+    __IO uint32_t tmi;
+    struct
+    {
+      __IO uint32_t tmsr                 : 1; /* [0] */
+      __IO uint32_t tmfrsel              : 1; /* [1] */
+      __IO uint32_t tmidsel              : 1; /* [2] */
+      __IO uint32_t tmeid                : 18;/* [20:3] */
+      __IO uint32_t tmsid                : 11;/* [31:21] */
+    } tmi_bit;
+  };
+
+  /**
+    * @brief can tmc register
+    */
+  union
+  {
+    __IO uint32_t tmc;
+    struct
+    {
+      __IO uint32_t tmdtbl               : 4; /* [3:0] */
+      __IO uint32_t reserved1            : 4; /* [7:4] */
+      __IO uint32_t tmtsten              : 1; /* [8] */
+      __IO uint32_t reserved2            : 7; /* [15:9] */
+      __IO uint32_t tmts                 : 16;/* [31:16] */
+    } tmc_bit;
+  };
+
+  /**
+    * @brief can tmdtl register
+    */
+  union
+  {
+    __IO uint32_t tmdtl;
+    struct
+    {
+      __IO uint32_t tmdt0                : 8; /* [7:0] */
+      __IO uint32_t tmdt1                : 8; /* [15:8] */
+      __IO uint32_t tmdt2                : 8; /* [23:16] */
+      __IO uint32_t tmdt3                : 8; /* [31:24] */
+    } tmdtl_bit;
+  };
+
+  /**
+    * @brief can tmdth register
+    */
+  union
+  {
+    __IO uint32_t tmdth;
+    struct
+    {
+      __IO uint32_t tmdt4                : 8; /* [7:0] */
+      __IO uint32_t tmdt5                : 8; /* [15:8] */
+      __IO uint32_t tmdt6                : 8; /* [23:16] */
+      __IO uint32_t tmdt7                : 8; /* [31:24] */
+    } tmdth_bit;
+  };
+} can_tx_mailbox_type;
+
+/**
+  * @brief can controller area network fifo mailbox
+  */
+typedef struct
+{
+  /**
+    * @brief can rfi register
+    */
+  union
+  {
+    __IO uint32_t rfi;
+    struct
+    {
+      __IO uint32_t reserved1            : 1; /* [0] */
+      __IO uint32_t rffri                : 1; /* [1] */
+      __IO uint32_t rfidi                : 1; /* [2] */
+      __IO uint32_t rfeid                : 18;/* [20:3] */
+      __IO uint32_t rfsid                : 11;/* [31:21] */
+    } rfi_bit;
+  };
+
+  /**
+    * @brief can rfc register
+    */
+  union
+  {
+    __IO uint32_t rfc;
+    struct
+    {
+      __IO uint32_t rfdtl                : 4; /* [3:0] */
+      __IO uint32_t reserved1            : 4; /* [7:4] */
+      __IO uint32_t rffmn                : 8; /* [15:8] */
+      __IO uint32_t rfts                 : 16;/* [31:16] */
+    } rfc_bit;
+  };
+
+  /**
+    * @brief can rfdtl register
+    */
+  union
+  {
+    __IO uint32_t rfdtl;
+    struct
+    {
+      __IO uint32_t rfdt0                : 8; /* [7:0] */
+      __IO uint32_t rfdt1                : 8; /* [15:8] */
+      __IO uint32_t rfdt2                : 8; /* [23:16] */
+      __IO uint32_t rfdt3                : 8; /* [31:24] */
+    } rfdtl_bit;
+  };
+
+  /**
+    * @brief can rfdth register
+    */
+  union
+  {
+    __IO uint32_t rfdth;
+    struct
+    {
+      __IO uint32_t rfdt4                : 8; /* [7:0] */
+      __IO uint32_t rfdt5                : 8; /* [15:8] */
+      __IO uint32_t rfdt6                : 8; /* [23:16] */
+      __IO uint32_t rfdt7                : 8; /* [31:24] */
+    } rfdth_bit;
+  };
+} can_fifo_mailbox_type;
+
+/**
+  * @brief can controller area network filter bit register
+  */
+typedef struct
+{
+  __IO uint32_t ffdb1;
+  __IO uint32_t ffdb2;
+} can_filter_register_type;
+
+/**
+  * @brief type define can register all
+  */
+typedef struct
+{
+
+  /**
+    * @brief can mctrl register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t mctrl;
+    struct
+    {
+      __IO uint32_t fzen                 : 1; /* [0] */
+      __IO uint32_t dzen                 : 1; /* [1] */
+      __IO uint32_t mmssr                : 1; /* [2] */
+      __IO uint32_t mdrsel               : 1; /* [3] */
+      __IO uint32_t prsfen               : 1; /* [4] */
+      __IO uint32_t aeden                : 1; /* [5] */
+      __IO uint32_t aeboen               : 1; /* [6] */
+      __IO uint32_t ttcen                : 1; /* [7] */
+      __IO uint32_t reserved1            : 7; /* [14:8] */
+      __IO uint32_t sprst                : 1; /* [15] */
+      __IO uint32_t ptd                  : 1; /* [16] */
+      __IO uint32_t reserved2            : 15;/*[31:17] */
+    } mctrl_bit;
+  };
+
+  /**
+    * @brief can msts register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t msts;
+    struct
+    {
+      __IO uint32_t fzc                  : 1; /* [0] */
+      __IO uint32_t dzc                  : 1; /* [1] */
+      __IO uint32_t eoif                 : 1; /* [2] */
+      __IO uint32_t qdzif                : 1; /* [3] */
+      __IO uint32_t edzif                : 1; /* [4] */
+      __IO uint32_t reserved1            : 3; /* [7:5] */
+      __IO uint32_t cuss                 : 1; /* [8] */
+      __IO uint32_t curs                 : 1; /* [9] */
+      __IO uint32_t lsamprx              : 1; /* [10] */
+      __IO uint32_t realrx               : 1; /* [11] */
+      __IO uint32_t reserved2            : 20;/*[31:12] */
+    } msts_bit;
+  };
+
+   /**
+     * @brief can tsts register, offset:0x08
+     */
+  union
+  {
+    __IO uint32_t tsts;
+    struct
+    {
+      __IO uint32_t tm0tcf               : 1; /* [0] */
+      __IO uint32_t tm0tsf               : 1; /* [1] */
+      __IO uint32_t tm0alf               : 1; /* [2] */
+      __IO uint32_t tm0tef               : 1; /* [3] */
+      __IO uint32_t reserved1            : 3; /* [6:4] */
+      __IO uint32_t tm0ct                : 1; /* [7] */
+      __IO uint32_t tm1tcf               : 1; /* [8] */
+      __IO uint32_t tm1tsf               : 1; /* [9] */
+      __IO uint32_t tm1alf               : 1; /* [10] */
+      __IO uint32_t tm1tef               : 1; /* [11] */
+      __IO uint32_t reserved2            : 3; /* [14:12] */
+      __IO uint32_t tm1ct                : 1; /* [15] */
+      __IO uint32_t tm2tcf               : 1; /* [16] */
+      __IO uint32_t tm2tsf               : 1; /* [17] */
+      __IO uint32_t tm2alf               : 1; /* [18] */
+      __IO uint32_t tm2tef               : 1; /* [19] */
+      __IO uint32_t reserved3            : 3; /* [22:20] */
+      __IO uint32_t tm2ct                : 1; /* [23] */
+      __IO uint32_t tmnr                 : 2; /* [25:24] */
+      __IO uint32_t tm0ef                : 1; /* [26] */
+      __IO uint32_t tm1ef                : 1; /* [27] */
+      __IO uint32_t tm2ef                : 1; /* [28] */
+      __IO uint32_t tm0lpf               : 1; /* [29] */
+      __IO uint32_t tm1lpf               : 1; /* [30] */
+      __IO uint32_t tm2lpf               : 1; /* [31] */
+    } tsts_bit;
+  };
+
+  /**
+    * @brief can rf0 register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t rf0;
+    struct
+    {
+      __IO uint32_t rf0mn                : 2; /* [1:0] */
+      __IO uint32_t reserved1            : 1; /* [2] */
+      __IO uint32_t rf0ff                : 1; /* [3] */
+      __IO uint32_t rf0of                : 1; /* [4] */
+      __IO uint32_t rf0r                 : 1; /* [5] */
+      __IO uint32_t reserved2            : 26;/* [31:6] */
+    } rf0_bit;
+  };
+
+  /**
+    * @brief can rf1 register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t rf1;
+    struct
+    {
+      __IO uint32_t rf1mn                : 2; /* [1:0] */
+      __IO uint32_t reserved1            : 1; /* [2] */
+      __IO uint32_t rf1ff                : 1; /* [3] */
+      __IO uint32_t rf1of                : 1; /* [4] */
+      __IO uint32_t rf1r                 : 1; /* [5] */
+      __IO uint32_t reserved2            : 26;/* [31:6] */
+    } rf1_bit;
+  };
+
+  /**
+    * @brief can inten register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t inten;
+    struct
+    {
+      __IO uint32_t tcien               : 1; /* [0] */
+      __IO uint32_t rf0mien              : 1; /* [1] */
+      __IO uint32_t rf0fien              : 1; /* [2] */
+      __IO uint32_t rf0oien              : 1; /* [3] */
+      __IO uint32_t rf1mien              : 1; /* [4] */
+      __IO uint32_t rf1fien              : 1; /* [5] */
+      __IO uint32_t rf1oien              : 1; /* [6] */
+      __IO uint32_t reserved1            : 1; /* [7] */
+      __IO uint32_t eaien                : 1; /* [8] */
+      __IO uint32_t epien                : 1; /* [9] */
+      __IO uint32_t boien                : 1; /* [10] */
+      __IO uint32_t etrien               : 1; /* [11] */
+      __IO uint32_t reserved2            : 3; /* [14:12] */
+      __IO uint32_t eoien                : 1; /* [15] */
+      __IO uint32_t qdzien               : 1; /* [16] */
+      __IO uint32_t edzien               : 1; /* [17] */
+      __IO uint32_t reserved3            : 14;/* [31:18] */
+    } inten_bit;
+  };
+
+  /**
+    * @brief can ests register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t ests;
+    struct
+    {
+      __IO uint32_t eaf                  : 1; /* [0] */
+      __IO uint32_t epf                  : 1; /* [1] */
+      __IO uint32_t bof                  : 1; /* [2] */
+      __IO uint32_t reserved1            : 1; /* [3] */
+      __IO uint32_t etr                  : 3; /* [6:4] */
+      __IO uint32_t reserved2            : 9; /* [15:7] */
+      __IO uint32_t tec                  : 8; /* [23:16] */
+      __IO uint32_t rec                  : 8; /* [31:24] */
+    } ests_bit;
+  };
+
+  /**
+    * @brief can btmg register, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t btmg;
+    struct
+    {
+      __IO uint32_t brdiv                : 12;/* [11:0] */
+      __IO uint32_t reserved1            : 4; /* [15:12] */
+      __IO uint32_t bts1                 : 4; /* [19:16] */
+      __IO uint32_t bts2                 : 3; /* [22:20] */
+      __IO uint32_t reserved2            : 1; /* [23] */
+      __IO uint32_t rsaw                 : 2; /* [25:24] */
+      __IO uint32_t reserved3            : 4; /* [29:26] */
+      __IO uint32_t lben                 : 1; /* [30] */
+      __IO uint32_t loen                 : 1; /* [31] */
+    } btmg_bit;
+  };
+
+  /**
+    * @brief can reserved register, offset:0x20~0x17C
+    */
+  __IO uint32_t reserved1[88];
+
+  /**
+    * @brief can controller area network tx mailbox register, offset:0x180~0x1AC
+    */
+  can_tx_mailbox_type tx_mailbox[3];
+
+  /**
+    * @brief can controller area network fifo mailbox register, offset:0x1B0~0x1CC
+    */
+  can_fifo_mailbox_type fifo_mailbox[2];
+
+  /**
+    * @brief can reserved register, offset:0x1D0~0x1FC
+    */
+  __IO uint32_t reserved2[12];
+
+  /**
+    * @brief can fctrl register, offset:0x200
+    */
+  union
+  {
+    __IO uint32_t fctrl;
+    struct
+    {
+      __IO uint32_t fcs                  : 1; /* [0] */
+      __IO uint32_t reserved1            : 31;/* [31:1] */
+    } fctrl_bit;
+  };
+
+  /**
+    * @brief can fmcfg register, offset:0x204
+    */
+  union
+  {
+    __IO uint32_t fmcfg;
+    struct
+    {
+      __IO uint32_t fmsel0               : 1; /* [0] */
+      __IO uint32_t fmsel1               : 1; /* [1] */
+      __IO uint32_t fmsel2               : 1; /* [2] */
+      __IO uint32_t fmsel3               : 1; /* [3] */
+      __IO uint32_t fmsel4               : 1; /* [4] */
+      __IO uint32_t fmsel5               : 1; /* [5] */
+      __IO uint32_t fmsel6               : 1; /* [6] */
+      __IO uint32_t fmsel7               : 1; /* [7] */
+      __IO uint32_t fmsel8               : 1; /* [8] */
+      __IO uint32_t fmsel9               : 1; /* [9] */
+      __IO uint32_t fmsel10              : 1; /* [10] */
+      __IO uint32_t fmsel11              : 1; /* [11] */
+      __IO uint32_t fmsel12              : 1; /* [12] */
+      __IO uint32_t fmsel13              : 1; /* [13] */
+      __IO uint32_t reserved1            : 18;/* [31:14] */
+    } fmcfg_bit;
+  };
+
+  /**
+    * @brief can reserved register, offset:0x208
+    */
+  __IO uint32_t reserved3;
+
+  /**
+    * @brief can fbwcfg register, offset:0x20C
+    */
+  union
+  {
+    __IO uint32_t fbwcfg;
+    struct
+    {
+      __IO uint32_t fbwsel0              : 1; /* [0] */
+      __IO uint32_t fbwsel1              : 1; /* [1] */
+      __IO uint32_t fbwsel2              : 1; /* [2] */
+      __IO uint32_t fbwsel3              : 1; /* [3] */
+      __IO uint32_t fbwsel4              : 1; /* [4] */
+      __IO uint32_t fbwsel5              : 1; /* [5] */
+      __IO uint32_t fbwsel6              : 1; /* [6] */
+      __IO uint32_t fbwsel7              : 1; /* [7] */
+      __IO uint32_t fbwsel8              : 1; /* [8] */
+      __IO uint32_t fbwsel9              : 1; /* [9] */
+      __IO uint32_t fbwsel10             : 1; /* [10] */
+      __IO uint32_t fbwsel11             : 1; /* [11] */
+      __IO uint32_t fbwsel12             : 1; /* [12] */
+      __IO uint32_t fbwsel13             : 1; /* [13] */
+      __IO uint32_t reserved1            : 18;/* [31:14] */
+    } fbwcfg_bit;
+  };
+
+  /**
+    * @brief can reserved register, offset:0x210
+    */
+  __IO uint32_t reserved4;
+
+  /**
+    * @brief can frf register, offset:0x214
+    */
+  union
+  {
+    __IO uint32_t frf;
+    struct
+    {
+      __IO uint32_t frfsel0              : 1; /* [0] */
+      __IO uint32_t frfsel1              : 1; /* [1] */
+      __IO uint32_t frfsel2              : 1; /* [2] */
+      __IO uint32_t frfsel3              : 1; /* [3] */
+      __IO uint32_t frfsel4              : 1; /* [4] */
+      __IO uint32_t frfsel5              : 1; /* [5] */
+      __IO uint32_t frfsel6              : 1; /* [6] */
+      __IO uint32_t frfsel7              : 1; /* [7] */
+      __IO uint32_t frfsel8              : 1; /* [8] */
+      __IO uint32_t frfsel9              : 1; /* [9] */
+      __IO uint32_t frfsel10             : 1; /* [10] */
+      __IO uint32_t frfsel11             : 1; /* [11] */
+      __IO uint32_t frfsel12             : 1; /* [12] */
+      __IO uint32_t frfsel13             : 1; /* [13] */
+      __IO uint32_t reserved1            : 18;/* [31:14] */
+    } frf_bit;
+  };
+
+  /**
+    * @brief can reserved register, offset:0x218
+    */
+  __IO uint32_t reserved5;
+
+  /**
+    * @brief can facfg register, offset:0x21C
+    */
+  union
+  {
+    __IO uint32_t facfg;
+    struct
+    {
+      __IO uint32_t faen0                : 1; /* [0] */
+      __IO uint32_t faen1                : 1; /* [1] */
+      __IO uint32_t faen2                : 1; /* [2] */
+      __IO uint32_t faen3                : 1; /* [3] */
+      __IO uint32_t faen4                : 1; /* [4] */
+      __IO uint32_t faen5                : 1; /* [5] */
+      __IO uint32_t faen6                : 1; /* [6] */
+      __IO uint32_t faen7                : 1; /* [7] */
+      __IO uint32_t faen8                : 1; /* [8] */
+      __IO uint32_t faen9                : 1; /* [9] */
+      __IO uint32_t faen10               : 1; /* [10] */
+      __IO uint32_t faen11               : 1; /* [11] */
+      __IO uint32_t faen12               : 1; /* [12] */
+      __IO uint32_t faen13               : 1; /* [13] */
+      __IO uint32_t reserved1            : 18;/* [31:14] */
+    } facfg_bit;
+  };
+
+  /**
+    * @brief can reserved register, offset:0x220~0x23C
+    */
+  __IO uint32_t reserved6[8];
+
+  /**
+    * @brief can ffb register, offset:0x240~0x2AC
+    */
+  can_filter_register_type ffb[14];
+} can_type;
+
+/**
+  * @}
+  */
+
+#define CAN1                             ((can_type *) CAN1_BASE)
+#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \
+    defined (AT32F413Kx)
+#define CAN2                             ((can_type *) CAN2_BASE)
+#endif
+
+/** @defgroup CAN_exported_functions
+  * @{
+  */
+
+void can_reset(can_type* can_x);
+void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
+error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);
+void can_default_para_init(can_base_type* can_base_struct);
+error_status can_base_init(can_type* can_x, can_base_type* can_base_struct);
+void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct);
+void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct);
+void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state);
+void can_ttc_mode_enable(can_type* can_x, confirm_state new_state);
+uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct);
+can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
+void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
+void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct);
+void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number);
+uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number);
+error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode);
+can_enter_doze_status_type can_doze_mode_enter(can_type* can_x);
+can_quit_doze_status_type can_doze_mode_exit(can_type* can_x);
+can_error_record_type can_error_type_record_get(can_type* can_x);
+uint8_t can_receive_error_counter_get(can_type* can_x);
+uint8_t can_transmit_error_counter_get(can_type* can_x);
+void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
+flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
+void can_flag_clear(can_type* can_x, uint32_t can_flag);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_crc.h

@@ -0,0 +1,170 @@
+/**
+  **************************************************************************
+  * @file     at32f413_crc.h
+  * @brief    at32f413 crc header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_CRC_H
+#define __AT32F413_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup  CRC
+  * @{
+  */
+
+/** @defgroup CRC_exported_types
+  * @{
+  */
+
+/**
+  * @brief crc reverse input data
+  */
+typedef enum
+{
+  CRC_REVERSE_INPUT_NO_AFFECTE           = 0x00, /*!< input data no reverse */
+  CRC_REVERSE_INPUT_BY_BYTE              = 0x01, /*!< input data reverse by byte */
+  CRC_REVERSE_INPUT_BY_HALFWORD          = 0x02, /*!< input data reverse by half word */
+  CRC_REVERSE_INPUT_BY_WORD              = 0x03  /*!< input data reverse by word */
+} crc_reverse_input_type;
+
+/**
+  * @brief crc reverse output data
+  */
+typedef enum
+{
+  CRC_REVERSE_OUTPUT_NO_AFFECTE          = 0x00, /*!< output data no reverse */
+  CRC_REVERSE_OUTPUT_DATA                = 0x01  /*!< output data reverse by word */
+} crc_reverse_output_type;
+
+/**
+ * @brief type define crc register all
+ */
+typedef struct
+{
+  /**
+    * @brief crc dt register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t dt;
+    struct
+    {
+      __IO uint32_t dt                   : 32; /* [31:0] */
+    } dt_bit;
+  };
+
+  /**
+    * @brief crc cdt register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t cdt;
+    struct
+    {
+      __IO uint32_t cdt                  : 8 ; /* [7:0] */
+      __IO uint32_t reserved1            : 24 ;/* [31:8] */
+    } cdt_bit;
+  };
+
+  /**
+    * @brief crc ctrl register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t ctrl;
+    struct
+    {
+      __IO uint32_t rst                  : 1 ; /* [0] */
+      __IO uint32_t reserved1            : 4 ; /* [4:1] */
+      __IO uint32_t revid                : 2 ; /* [6:5] */
+      __IO uint32_t revod                : 1 ; /* [7] */
+      __IO uint32_t reserved2            : 24 ;/* [31:8] */
+    } ctrl_bit;
+  };
+
+  /**
+    * @brief crm reserved1 register, offset:0x0C
+    */
+  __IO uint32_t reserved1;
+
+  /**
+    * @brief crc idt register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t idt;
+    struct
+    {
+      __IO uint32_t idt                  : 32; /* [31:0] */
+    } idt_bit;
+  };
+
+} crc_type;
+
+/**
+  * @}
+  */
+
+#define CRC                              ((crc_type *) CRC_BASE)
+
+/** @defgroup CRC_exported_functions
+  * @{
+  */
+
+void crc_data_reset(void);
+uint32_t crc_one_word_calculate(uint32_t data);
+uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
+uint32_t crc_data_get(void);
+void crc_common_data_set(uint8_t cdt_value);
+uint8_t crc_common_data_get(void);
+void crc_init_data_set(uint32_t value);
+void crc_reverse_input_data_set(crc_reverse_input_type value);
+void crc_reverse_output_data_set(crc_reverse_output_type value);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_crm.h

@@ -0,0 +1,899 @@
+/**
+  **************************************************************************
+  * @file     at32f413_crm.h
+  * @brief    at32f413 crm header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_CRM_H
+#define __AT32F413_CRM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup CRM
+  * @{
+  */
+
+#define CRM_REG(value)                   PERIPH_REG(CRM_BASE, value)
+#define CRM_REG_BIT(value)               PERIPH_REG_BIT(value)
+
+/** @defgroup CRM_flags_definition
+  * @brief crm flag
+  * @{
+  */
+
+#define CRM_HICK_STABLE_FLAG             MAKE_VALUE(0x00, 1)  /*!< high speed internal clock stable flag */
+#define CRM_HEXT_STABLE_FLAG             MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
+#define CRM_PLL_STABLE_FLAG              MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
+#define CRM_LEXT_STABLE_FLAG             MAKE_VALUE(0x20, 1)  /*!< low speed external crystal stable flag */
+#define CRM_LICK_STABLE_FLAG             MAKE_VALUE(0x24, 1)  /*!< low speed internal clock stable flag */
+#define CRM_ALL_RESET_FLAG               MAKE_VALUE(0x24, 24) /*!< all reset flag */
+#define CRM_NRST_RESET_FLAG              MAKE_VALUE(0x24, 26) /*!< nrst pin reset flag */
+#define CRM_POR_RESET_FLAG               MAKE_VALUE(0x24, 27) /*!< power on reset flag */
+#define CRM_SW_RESET_FLAG                MAKE_VALUE(0x24, 28) /*!< software reset flag */
+#define CRM_WDT_RESET_FLAG               MAKE_VALUE(0x24, 29) /*!< watchdog timer reset flag */
+#define CRM_WWDT_RESET_FLAG              MAKE_VALUE(0x24, 30) /*!< window watchdog timer reset flag */
+#define CRM_LOWPOWER_RESET_FLAG          MAKE_VALUE(0x24, 31) /*!< low-power reset flag */
+#define CRM_LICK_READY_INT_FLAG          MAKE_VALUE(0x08, 0)  /*!< low speed internal clock stable interrupt ready flag */
+#define CRM_LEXT_READY_INT_FLAG          MAKE_VALUE(0x08, 1)  /*!< low speed external crystal stable interrupt ready flag */
+#define CRM_HICK_READY_INT_FLAG          MAKE_VALUE(0x08, 2)  /*!< high speed internal clock stable interrupt ready flag */
+#define CRM_HEXT_READY_INT_FLAG          MAKE_VALUE(0x08, 3)  /*!< high speed external crystal stable interrupt ready flag */
+#define CRM_PLL_READY_INT_FLAG           MAKE_VALUE(0x08, 4)  /*!< phase locking loop stable interrupt ready flag */
+#define CRM_CLOCK_FAILURE_INT_FLAG       MAKE_VALUE(0x08, 7)  /*!< clock failure interrupt ready flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRM_interrupts_definition
+  * @brief crm interrupt
+  * @{
+  */
+
+#define CRM_LICK_STABLE_INT              ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
+#define CRM_LEXT_STABLE_INT              ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
+#define CRM_HICK_STABLE_INT              ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
+#define CRM_HEXT_STABLE_INT              ((uint32_t)0x00000800) /*!< high speed external crystal stable interrupt */
+#define CRM_PLL_STABLE_INT               ((uint32_t)0x00001000) /*!< phase locking loop stable interrupt */
+#define CRM_CLOCK_FAILURE_INT            ((uint32_t)0x00800000) /*!< clock failure interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRM_exported_types
+  * @{
+  */
+
+/**
+  * @brief crm periph clock
+  */
+typedef enum
+{
+  /* ahb periph */
+  CRM_DMA1_PERIPH_CLOCK                  = MAKE_VALUE(0x14, 0),  /*!< dma1 periph clock */
+  CRM_DMA2_PERIPH_CLOCK                  = MAKE_VALUE(0x14, 1),  /*!< dma2 periph clock */
+  CRM_CRC_PERIPH_CLOCK                   = MAKE_VALUE(0x14, 6),  /*!< crc periph clock */
+  CRM_SDIO1_PERIPH_CLOCK                 = MAKE_VALUE(0x14, 10), /*!< sdio1 periph clock */
+  /* apb2 periph */
+  CRM_IOMUX_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 0),  /*!< iomux periph clock */
+  CRM_GPIOA_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 2),  /*!< gpioa periph clock */
+  CRM_GPIOB_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 3),  /*!< gpiob periph clock */
+  CRM_GPIOC_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 4),  /*!< gpioc periph clock */
+  CRM_GPIOD_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 5),  /*!< gpiod periph clock */
+  CRM_GPIOF_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 7),  /*!< gpiof periph clock */
+  CRM_ADC1_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 9),  /*!< adc1 periph clock */
+  CRM_ADC2_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 10), /*!< adc2 periph clock */
+  CRM_TMR1_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 11), /*!< tmr1 periph clock */
+  CRM_SPI1_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 12), /*!< spi1 periph clock */
+  CRM_TMR8_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 13), /*!< tmr8 periph clock */
+  CRM_USART1_PERIPH_CLOCK                = MAKE_VALUE(0x18, 14), /*!< usart1 periph clock */
+  CRM_TMR9_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 19), /*!< tmr9 periph clock */
+  CRM_TMR10_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 20), /*!< tmr10 periph clock */
+  CRM_TMR11_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 21), /*!< tmr11 periph clock */
+  CRM_ACC_PERIPH_CLOCK                   = MAKE_VALUE(0x18, 22), /*!< acc periph clock */
+  /* apb1 periph */
+  CRM_TMR2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 0),  /*!< tmr2 periph clock */
+  CRM_TMR3_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 1),  /*!< tmr3 periph clock */
+  CRM_TMR4_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 2),  /*!< tmr4 periph clock */
+  CRM_TMR5_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 3),  /*!< tmr5 periph clock */
+  CRM_WWDT_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 11), /*!< wwdt periph clock */
+  CRM_SPI2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 14), /*!< spi2 periph clock */
+  CRM_USART2_PERIPH_CLOCK                = MAKE_VALUE(0x1C, 17), /*!< usart2 periph clock */
+  CRM_USART3_PERIPH_CLOCK                = MAKE_VALUE(0x1C, 18), /*!< usart3 periph clock */
+  CRM_UART4_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 19), /*!< uart4 periph clock */
+  CRM_UART5_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 20), /*!< uart5 periph clock */
+  CRM_I2C1_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */
+  CRM_I2C2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */
+  CRM_USB_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 23), /*!< usb periph clock */
+  CRM_CAN1_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */
+  CRM_BPR_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 27), /*!< bpr periph clock */
+  CRM_PWC_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */
+  CRM_CAN2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 31), /*!< can2 periph clock */
+
+} crm_periph_clock_type;
+
+/**
+  * @brief crm periph reset
+  */
+typedef enum
+{
+  /* apb2 periph */
+  CRM_IOMUX_PERIPH_RESET                 = MAKE_VALUE(0x0C, 0),  /*!< iomux periph reset */
+  CRM_EXINT_PERIPH_RESET                 = MAKE_VALUE(0x0C, 1),  /*!< exint periph reset */
+  CRM_GPIOA_PERIPH_RESET                 = MAKE_VALUE(0x0C, 2),  /*!< gpioa periph reset */
+  CRM_GPIOB_PERIPH_RESET                 = MAKE_VALUE(0x0C, 3),  /*!< gpiob periph reset */
+  CRM_GPIOC_PERIPH_RESET                 = MAKE_VALUE(0x0C, 4),  /*!< gpioc periph reset */
+  CRM_GPIOD_PERIPH_RESET                 = MAKE_VALUE(0x0C, 5),  /*!< gpiod periph reset */
+  CRM_GPIOF_PERIPH_RESET                 = MAKE_VALUE(0x0C, 7),  /*!< gpiof periph reset */
+  CRM_ADC1_PERIPH_RESET                  = MAKE_VALUE(0x0C, 9),  /*!< adc1 periph reset */
+  CRM_ADC2_PERIPH_RESET                  = MAKE_VALUE(0x0C, 10), /*!< adc2 periph reset */
+  CRM_TMR1_PERIPH_RESET                  = MAKE_VALUE(0x0C, 11), /*!< tmr1 periph reset */
+  CRM_SPI1_PERIPH_RESET                  = MAKE_VALUE(0x0C, 12), /*!< spi2 periph reset */
+  CRM_TMR8_PERIPH_RESET                  = MAKE_VALUE(0x0C, 13), /*!< tmr8 periph reset */
+  CRM_USART1_PERIPH_RESET                = MAKE_VALUE(0x0C, 14), /*!< usart1 periph reset */
+  CRM_TMR9_PERIPH_RESET                  = MAKE_VALUE(0x0C, 19), /*!< tmr9 periph reset */
+  CRM_TMR10_PERIPH_RESET                 = MAKE_VALUE(0x0C, 20), /*!< tmr10 periph reset */
+  CRM_TMR11_PERIPH_RESET                 = MAKE_VALUE(0x0C, 21), /*!< tmr11 periph reset */
+  CRM_ACC_PERIPH_RESET                   = MAKE_VALUE(0x0C, 22), /*!< acc periph reset */
+  /* apb1 periph */
+  CRM_TMR2_PERIPH_RESET                  = MAKE_VALUE(0x10, 0),  /*!< tmr2 periph reset */
+  CRM_TMR3_PERIPH_RESET                  = MAKE_VALUE(0x10, 1),  /*!< tmr3 periph reset */
+  CRM_TMR4_PERIPH_RESET                  = MAKE_VALUE(0x10, 2),  /*!< tmr4 periph reset */
+  CRM_TMR5_PERIPH_RESET                  = MAKE_VALUE(0x10, 3),  /*!< tmr5 periph reset */
+  CRM_WWDT_PERIPH_RESET                  = MAKE_VALUE(0x10, 11), /*!< wwdt periph reset */
+  CRM_SPI2_PERIPH_RESET                  = MAKE_VALUE(0x10, 14), /*!< spi2 periph reset */
+  CRM_USART2_PERIPH_RESET                = MAKE_VALUE(0x10, 17), /*!< usart2 periph reset */
+  CRM_USART3_PERIPH_RESET                = MAKE_VALUE(0x10, 18), /*!< usart3 periph reset */
+  CRM_UART4_PERIPH_RESET                 = MAKE_VALUE(0x10, 19), /*!< uart4 periph reset */
+  CRM_UART5_PERIPH_RESET                 = MAKE_VALUE(0x10, 20), /*!< uart5 periph reset */
+  CRM_I2C1_PERIPH_RESET                  = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */
+  CRM_I2C2_PERIPH_RESET                  = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */
+  CRM_USB_PERIPH_RESET                   = MAKE_VALUE(0x10, 23), /*!< usb periph reset */
+  CRM_CAN1_PERIPH_RESET                  = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */
+  CRM_BPR_PERIPH_RESET                   = MAKE_VALUE(0x10, 27), /*!< bpr periph reset */
+  CRM_PWC_PERIPH_RESET                   = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */
+  CRM_CAN2_PERIPH_RESET                  = MAKE_VALUE(0x10, 31), /*!< can2 periph reset */
+
+} crm_periph_reset_type;
+
+/**
+  * @brief crm periph clock in sleep mode
+  */
+typedef enum
+{
+  /* ahb periph */
+  CRM_SRAM_PERIPH_CLOCK_SLEEP_MODE       = MAKE_VALUE(0x14, 2), /*!< sram sleep mode periph clock */
+  CRM_FLASH_PERIPH_CLOCK_SLEEP_MODE      = MAKE_VALUE(0x14, 4)  /*!< flash sleep mode periph clock */
+} crm_periph_clock_sleepmd_type;
+
+/**
+  * @brief crm pll mult_x
+  */
+typedef enum
+{
+  CRM_PLL_MULT_2                         = 0,  /*!< pll multiplication factor 2 */
+  CRM_PLL_MULT_3                         = 1,  /*!< pll multiplication factor 3 */
+  CRM_PLL_MULT_4                         = 2,  /*!< pll multiplication factor 4 */
+  CRM_PLL_MULT_5                         = 3,  /*!< pll multiplication factor 5 */
+  CRM_PLL_MULT_6                         = 4,  /*!< pll multiplication factor 6 */
+  CRM_PLL_MULT_7                         = 5,  /*!< pll multiplication factor 7 */
+  CRM_PLL_MULT_8                         = 6,  /*!< pll multiplication factor 8 */
+  CRM_PLL_MULT_9                         = 7,  /*!< pll multiplication factor 9 */
+  CRM_PLL_MULT_10                        = 8,  /*!< pll multiplication factor 10 */
+  CRM_PLL_MULT_11                        = 9,  /*!< pll multiplication factor 11 */
+  CRM_PLL_MULT_12                        = 10, /*!< pll multiplication factor 12 */
+  CRM_PLL_MULT_13                        = 11, /*!< pll multiplication factor 13 */
+  CRM_PLL_MULT_14                        = 12, /*!< pll multiplication factor 14 */
+  CRM_PLL_MULT_15                        = 13, /*!< pll multiplication factor 15 */
+  CRM_PLL_MULT_16                        = 15, /*!< pll multiplication factor 16 */
+  CRM_PLL_MULT_17                        = 16, /*!< pll multiplication factor 17 */
+  CRM_PLL_MULT_18                        = 17, /*!< pll multiplication factor 18 */
+  CRM_PLL_MULT_19                        = 18, /*!< pll multiplication factor 19 */
+  CRM_PLL_MULT_20                        = 19, /*!< pll multiplication factor 20 */
+  CRM_PLL_MULT_21                        = 20, /*!< pll multiplication factor 21 */
+  CRM_PLL_MULT_22                        = 21, /*!< pll multiplication factor 22 */
+  CRM_PLL_MULT_23                        = 22, /*!< pll multiplication factor 23 */
+  CRM_PLL_MULT_24                        = 23, /*!< pll multiplication factor 24 */
+  CRM_PLL_MULT_25                        = 24, /*!< pll multiplication factor 25 */
+  CRM_PLL_MULT_26                        = 25, /*!< pll multiplication factor 26 */
+  CRM_PLL_MULT_27                        = 26, /*!< pll multiplication factor 27 */
+  CRM_PLL_MULT_28                        = 27, /*!< pll multiplication factor 28 */
+  CRM_PLL_MULT_29                        = 28, /*!< pll multiplication factor 29 */
+  CRM_PLL_MULT_30                        = 29, /*!< pll multiplication factor 30 */
+  CRM_PLL_MULT_31                        = 30, /*!< pll multiplication factor 31 */
+  CRM_PLL_MULT_32                        = 31, /*!< pll multiplication factor 32 */
+  CRM_PLL_MULT_33                        = 32, /*!< pll multiplication factor 33 */
+  CRM_PLL_MULT_34                        = 33, /*!< pll multiplication factor 34 */
+  CRM_PLL_MULT_35                        = 34, /*!< pll multiplication factor 35 */
+  CRM_PLL_MULT_36                        = 35, /*!< pll multiplication factor 36 */
+  CRM_PLL_MULT_37                        = 36, /*!< pll multiplication factor 37 */
+  CRM_PLL_MULT_38                        = 37, /*!< pll multiplication factor 38 */
+  CRM_PLL_MULT_39                        = 38, /*!< pll multiplication factor 39 */
+  CRM_PLL_MULT_40                        = 39, /*!< pll multiplication factor 40 */
+  CRM_PLL_MULT_41                        = 40, /*!< pll multiplication factor 41 */
+  CRM_PLL_MULT_42                        = 41, /*!< pll multiplication factor 42 */
+  CRM_PLL_MULT_43                        = 42, /*!< pll multiplication factor 43 */
+  CRM_PLL_MULT_44                        = 43, /*!< pll multiplication factor 44 */
+  CRM_PLL_MULT_45                        = 44, /*!< pll multiplication factor 45 */
+  CRM_PLL_MULT_46                        = 45, /*!< pll multiplication factor 46 */
+  CRM_PLL_MULT_47                        = 46, /*!< pll multiplication factor 47 */
+  CRM_PLL_MULT_48                        = 47, /*!< pll multiplication factor 48 */
+  CRM_PLL_MULT_49                        = 48, /*!< pll multiplication factor 49 */
+  CRM_PLL_MULT_50                        = 49, /*!< pll multiplication factor 50 */
+  CRM_PLL_MULT_51                        = 50, /*!< pll multiplication factor 51 */
+  CRM_PLL_MULT_52                        = 51, /*!< pll multiplication factor 52 */
+  CRM_PLL_MULT_53                        = 52, /*!< pll multiplication factor 53 */
+  CRM_PLL_MULT_54                        = 53, /*!< pll multiplication factor 54 */
+  CRM_PLL_MULT_55                        = 54, /*!< pll multiplication factor 55 */
+  CRM_PLL_MULT_56                        = 55, /*!< pll multiplication factor 56 */
+  CRM_PLL_MULT_57                        = 56, /*!< pll multiplication factor 57 */
+  CRM_PLL_MULT_58                        = 57, /*!< pll multiplication factor 58 */
+  CRM_PLL_MULT_59                        = 58, /*!< pll multiplication factor 59 */
+  CRM_PLL_MULT_60                        = 59, /*!< pll multiplication factor 60 */
+  CRM_PLL_MULT_61                        = 60, /*!< pll multiplication factor 61 */
+  CRM_PLL_MULT_62                        = 61, /*!< pll multiplication factor 62 */
+  CRM_PLL_MULT_63                        = 62, /*!< pll multiplication factor 63 */
+  CRM_PLL_MULT_64                        = 63  /*!< pll multiplication factor 64 */
+} crm_pll_mult_type;
+
+/**
+  * @brief crm pll clock source
+  */
+typedef enum
+{
+  CRM_PLL_SOURCE_HICK                    = 0x00, /*!< high speed internal clock as pll reference clock source */
+  CRM_PLL_SOURCE_HEXT                    = 0x01, /*!< high speed external crystal as pll reference clock source */
+  CRM_PLL_SOURCE_HEXT_DIV                = 0x02  /*!< high speed external crystal div as pll reference clock source */
+} crm_pll_clock_source_type;
+
+/**
+  * @brief crm pll clock output range
+  */
+typedef enum
+{
+  CRM_PLL_OUTPUT_RANGE_LE72MHZ           = 0x00, /*!< pll clock output range less than or equal to 72mhz */
+  CRM_PLL_OUTPUT_RANGE_GT72MHZ           = 0x01  /*!< pll clock output range greater than 72mhz */
+} crm_pll_output_range_type;
+
+/**
+  * @brief crm clock source
+  */
+typedef enum
+{
+  CRM_CLOCK_SOURCE_HICK                  = 0x00, /*!< high speed internal clock */
+  CRM_CLOCK_SOURCE_HEXT                  = 0x01, /*!< high speed external crystal */
+  CRM_CLOCK_SOURCE_PLL                   = 0x02, /*!< phase locking loop */
+  CRM_CLOCK_SOURCE_LEXT                  = 0x03, /*!< low speed external crystal */
+  CRM_CLOCK_SOURCE_LICK                  = 0x04  /*!< low speed internal clock */
+} crm_clock_source_type;
+
+/**
+  * @brief crm ahb division
+  */
+typedef enum
+{
+  CRM_AHB_DIV_1                          = 0x00, /*!< sclk div1 to ahbclk */
+  CRM_AHB_DIV_2                          = 0x08, /*!< sclk div2 to ahbclk */
+  CRM_AHB_DIV_4                          = 0x09, /*!< sclk div4 to ahbclk */
+  CRM_AHB_DIV_8                          = 0x0A, /*!< sclk div8 to ahbclk */
+  CRM_AHB_DIV_16                         = 0x0B, /*!< sclk div16 to ahbclk */
+  CRM_AHB_DIV_64                         = 0x0C, /*!< sclk div64 to ahbclk */
+  CRM_AHB_DIV_128                        = 0x0D, /*!< sclk div128 to ahbclk */
+  CRM_AHB_DIV_256                        = 0x0E, /*!< sclk div256 to ahbclk */
+  CRM_AHB_DIV_512                        = 0x0F  /*!< sclk div512 to ahbclk */
+} crm_ahb_div_type;
+
+/**
+  * @brief crm apb1 division
+  */
+typedef enum
+{
+  CRM_APB1_DIV_1                         = 0x00, /*!< ahbclk div1 to apb1clk */
+  CRM_APB1_DIV_2                         = 0x04, /*!< ahbclk div2 to apb1clk */
+  CRM_APB1_DIV_4                         = 0x05, /*!< ahbclk div4 to apb1clk */
+  CRM_APB1_DIV_8                         = 0x06, /*!< ahbclk div8 to apb1clk */
+  CRM_APB1_DIV_16                        = 0x07  /*!< ahbclk div16 to apb1clk */
+} crm_apb1_div_type;
+
+/**
+  * @brief crm apb2 division
+  */
+typedef enum
+{
+  CRM_APB2_DIV_1                         = 0x00, /*!< ahbclk div1 to apb2clk */
+  CRM_APB2_DIV_2                         = 0x04, /*!< ahbclk div2 to apb2clk */
+  CRM_APB2_DIV_4                         = 0x05, /*!< ahbclk div4 to apb2clk */
+  CRM_APB2_DIV_8                         = 0x06, /*!< ahbclk div8 to apb2clk */
+  CRM_APB2_DIV_16                        = 0x07  /*!< ahbclk div16 to apb2clk */
+} crm_apb2_div_type;
+
+/**
+  * @brief crm adc division
+  */
+typedef enum
+{
+  CRM_ADC_DIV_2                          = 0x00, /*!< apb2clk div2 to adcclk */
+  CRM_ADC_DIV_4                          = 0x01, /*!< apb2clk div4 to adcclk */
+  CRM_ADC_DIV_6                          = 0x02, /*!< apb2clk div6 to adcclk */
+  CRM_ADC_DIV_8                          = 0x03, /*!< apb2clk div8 to adcclk */
+  CRM_ADC_DIV_12                         = 0x05, /*!< apb2clk div12 to adcclk */
+  CRM_ADC_DIV_16                         = 0x07  /*!< apb2clk div16 to adcclk */
+} crm_adc_div_type;
+
+/**
+  * @brief crm usb division
+  */
+typedef enum
+{
+  CRM_USB_DIV_1_5                        = 0x00, /*!< pllclk div1.5 to usbclk */
+  CRM_USB_DIV_1                          = 0x01, /*!< pllclk div1 to usbclk */
+  CRM_USB_DIV_2_5                        = 0x02, /*!< pllclk div2.5 to usbclk */
+  CRM_USB_DIV_2                          = 0x03, /*!< pllclk div2 to usbclk */
+  CRM_USB_DIV_3_5                        = 0x04, /*!< pllclk div3.5 to usbclk */
+  CRM_USB_DIV_3                          = 0x05, /*!< pllclk div3 to usbclk */
+  CRM_USB_DIV_4                          = 0x06  /*!< pllclk div4 to usbclk */
+} crm_usb_div_type;
+
+/**
+  * @brief crm rtc clock
+  */
+typedef enum
+{
+  CRM_RTC_CLOCK_NOCLK                    = 0x00, /*!< no clock as rtc clock source */
+  CRM_RTC_CLOCK_LEXT                     = 0x01, /*!< low speed external crystal as rtc clock source */
+  CRM_RTC_CLOCK_LICK                     = 0x02, /*!< low speed internal clock as rtc clock source */
+  CRM_RTC_CLOCK_HEXT_DIV                 = 0x03  /*!< high speed external crystal div as rtc clock source */
+} crm_rtc_clock_type;
+
+/**
+  * @brief crm hick 48mhz division
+  */
+typedef enum
+{
+  CRM_HICK48_DIV6                        = 0x00, /*!< high speed internal clock (48 mhz) div6 */
+  CRM_HICK48_NODIV                       = 0x01  /*!< high speed internal clock (48 mhz) no div */
+} crm_hick_div_6_type;
+
+/**
+  * @brief crm sclk select
+  */
+typedef enum
+{
+  CRM_SCLK_HICK                          = 0x00, /*!< select high speed internal clock as sclk */
+  CRM_SCLK_HEXT                          = 0x01, /*!< select high speed external crystal as sclk */
+  CRM_SCLK_PLL                           = 0x02  /*!< select phase locking loop clock as sclk */
+} crm_sclk_type;
+
+/**
+  * @brief crm clkout select
+  */
+typedef enum
+{
+  CRM_CLKOUT_NOCLK                       = 0x00, /*!< output no clock to clkout pin */
+  CRM_CLKOUT_LICK                        = 0x02, /*!< output low speed internal clock to clkout pin */
+  CRM_CLKOUT_LEXT                        = 0x03, /*!< output low speed external crystal to clkout pin */
+  CRM_CLKOUT_SCLK                        = 0x04, /*!< output system clock to clkout pin */
+  CRM_CLKOUT_HICK                        = 0x05, /*!< output high speed internal clock to clkout pin */
+  CRM_CLKOUT_HEXT                        = 0x06, /*!< output high speed external crystal to clkout pin */
+  CRM_CLKOUT_PLL_DIV_2                   = 0x07, /*!< output phase locking loop clock div2 to clkout pin */
+  CRM_CLKOUT_PLL_DIV_4                   = 0x0C, /*!< output phase locking loop clock div4 to clkout pin */
+  CRM_CLKOUT_USB                         = 0x0D, /*!< output usbclk to clkout pin */
+  CRM_CLKOUT_ADC                         = 0x0E  /*!< output adcclk to clkout pin */
+} crm_clkout_select_type;
+
+/**
+  * @brief crm clkout division
+  */
+typedef enum
+{
+  CRM_CLKOUT_DIV_1                       = 0x00, /*!< clkout div1 */
+  CRM_CLKOUT_DIV_2                       = 0x08, /*!< clkout div2 */
+  CRM_CLKOUT_DIV_4                       = 0x09, /*!< clkout div4 */
+  CRM_CLKOUT_DIV_8                       = 0x0A, /*!< clkout div8 */
+  CRM_CLKOUT_DIV_16                      = 0x0B, /*!< clkout div16 */
+  CRM_CLKOUT_DIV_64                      = 0x0C, /*!< clkout div64 */
+  CRM_CLKOUT_DIV_128                     = 0x0D, /*!< clkout div128 */
+  CRM_CLKOUT_DIV_256                     = 0x0E, /*!< clkout div256 */
+  CRM_CLKOUT_DIV_512                     = 0x0F  /*!< clkout div512 */
+} crm_clkout_div_type;
+
+/**
+  * @brief crm auto step mode
+  */
+typedef enum
+{
+  CRM_AUTO_STEP_MODE_DISABLE             = 0x00, /*!< disable auto step mode */
+  CRM_AUTO_STEP_MODE_ENABLE              = 0x03  /*!< enable auto step mode */
+} crm_auto_step_mode_type;
+
+/**
+  * @brief crm usbdev interrupt remap
+  */
+typedef enum
+{
+  CRM_USB_INT19_INT20                    = 0x00, /*!< usb high and low priority irq numer use 19 and 20 */
+  CRM_USB_INT73_INT74                    = 0x01  /*!< usb high and low priority irq numer use 73 and 74 */
+} crm_usb_int_map_type;
+
+/**
+  * @brief crm usb 48 mhz clock source select
+  */
+typedef enum
+{
+  CRM_USB_CLOCK_SOURCE_PLL               = 0x00, /*!< select phase locking loop clock as usb clock source */
+  CRM_USB_CLOCK_SOURCE_HICK              = 0x01  /*!< select high speed internal clock as usb clock source */
+} crm_usb_clock_source_type;
+
+/**
+  * @brief crm hick as system clock frequency select
+  */
+typedef enum
+{
+  CRM_HICK_SCLK_8MHZ                     = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
+  CRM_HICK_SCLK_48MHZ                    = 0x01  /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
+} crm_hick_sclk_frequency_type;
+
+/**
+  * @brief crm clocks freqency structure
+  */
+typedef struct
+{
+  uint32_t sclk_freq; /*!< system clock frequency */
+  uint32_t ahb_freq;  /*!< ahb bus clock frequency */
+  uint32_t apb2_freq; /*!< apb2 bus clock frequency */
+  uint32_t apb1_freq; /*!< apb1 bus clock frequency */
+  uint32_t adc_freq;  /*!< adc clock frequency */
+} crm_clocks_freq_type;
+
+/**
+  * @brief type define crm register all
+  */
+typedef struct
+{
+  /**
+    * @brief crm ctrl register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t ctrl;
+    struct
+    {
+      __IO uint32_t hicken               : 1; /* [0] */
+      __IO uint32_t hickstbl             : 1; /* [1] */
+      __IO uint32_t hicktrim             : 6; /* [7:2] */
+      __IO uint32_t hickcal              : 8; /* [15:8] */
+      __IO uint32_t hexten               : 1; /* [16] */
+      __IO uint32_t hextstbl             : 1; /* [17] */
+      __IO uint32_t hextbyps             : 1; /* [18] */
+      __IO uint32_t cfden                : 1; /* [19] */
+      __IO uint32_t reserved1            : 4; /* [23:20] */
+      __IO uint32_t pllen                : 1; /* [24] */
+      __IO uint32_t pllstbl              : 1; /* [25] */
+      __IO uint32_t reserved2            : 6; /* [31:26] */
+    } ctrl_bit;
+  };
+
+  /**
+    * @brief crm cfg register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t cfg;
+    struct
+    {
+      __IO uint32_t sclksel              : 2; /* [1:0] */
+      __IO uint32_t sclksts              : 2; /* [3:2] */
+      __IO uint32_t ahbdiv               : 4; /* [7:4] */
+      __IO uint32_t apb1div              : 3; /* [10:8] */
+      __IO uint32_t apb2div              : 3; /* [13:11] */
+      __IO uint32_t adcdiv_l             : 2; /* [15:14] */
+      __IO uint32_t pllrcs               : 1; /* [16] */
+      __IO uint32_t pllhextdiv           : 1; /* [17] */
+      __IO uint32_t pllmult_l            : 4; /* [21:18] */
+      __IO uint32_t usbdiv_l             : 2; /* [23:22] */
+      __IO uint32_t clkout_sel           : 3; /* [26:24] */
+      __IO uint32_t usbdiv_h             : 1; /* [27] */
+      __IO uint32_t adcdiv_h             : 1; /* [28] */
+      __IO uint32_t pllmult_h            : 2; /* [30:29] */
+      __IO uint32_t pllrange             : 1; /* [31] */
+    } cfg_bit;
+  };
+
+  /**
+    * @brief crm clkint register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t clkint;
+    struct
+    {
+      __IO uint32_t lickstblf            : 1; /* [0] */
+      __IO uint32_t lextstblf            : 1; /* [1] */
+      __IO uint32_t hickstblf            : 1; /* [2] */
+      __IO uint32_t hextstblf            : 1; /* [3] */
+      __IO uint32_t pllstblf             : 1; /* [4] */
+      __IO uint32_t reserved1            : 2; /* [6:5] */
+      __IO uint32_t cfdf                 : 1; /* [7] */
+      __IO uint32_t lickstblien          : 1; /* [8] */
+      __IO uint32_t lextstblien          : 1; /* [9] */
+      __IO uint32_t hickstblien          : 1; /* [10] */
+      __IO uint32_t hextstblien          : 1; /* [11] */
+      __IO uint32_t pllstblien           : 1; /* [12] */
+      __IO uint32_t reserved2            : 3; /* [15:13] */
+      __IO uint32_t lickstblfc           : 1; /* [16] */
+      __IO uint32_t lextstblfc           : 1; /* [17] */
+      __IO uint32_t hickstblfc           : 1; /* [18] */
+      __IO uint32_t hextstblfc           : 1; /* [19] */
+      __IO uint32_t pllstblfc            : 1; /* [20] */
+      __IO uint32_t reserved3            : 2; /* [22:21] */
+      __IO uint32_t cfdfc                : 1; /* [23] */
+      __IO uint32_t reserved4            : 8; /* [31:24] */
+    } clkint_bit;
+  };
+
+  /**
+    * @brief crm apb2rst register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t apb2rst;
+    struct
+    {
+      __IO uint32_t iomuxrst             : 1; /* [0] */
+      __IO uint32_t exintrst             : 1; /* [1] */
+      __IO uint32_t gpioarst             : 1; /* [2] */
+      __IO uint32_t gpiobrst             : 1; /* [3] */
+      __IO uint32_t gpiocrst             : 1; /* [4] */
+      __IO uint32_t gpiodrst             : 1; /* [5] */
+      __IO uint32_t reserved1            : 1; /* [6] */
+      __IO uint32_t gpioerst             : 1; /* [7] */
+      __IO uint32_t reserved2            : 1; /* [8] */
+      __IO uint32_t adc1rst              : 1; /* [9] */
+      __IO uint32_t adc2rst              : 1; /* [10] */
+      __IO uint32_t tmr1rst              : 1; /* [11] */
+      __IO uint32_t spi1rst              : 1; /* [12] */
+      __IO uint32_t tmr8rst              : 1; /* [13] */
+      __IO uint32_t usart1rst            : 1; /* [14] */
+      __IO uint32_t reserved3            : 4; /* [18:15] */
+      __IO uint32_t tmr9rst              : 1; /* [19] */
+      __IO uint32_t tmr10rst             : 1; /* [20] */
+      __IO uint32_t tmr11rst             : 1; /* [21] */
+      __IO uint32_t accrst               : 1; /* [22] */
+      __IO uint32_t reserved4            : 9; /* [31:23] */
+    } apb2rst_bit;
+  };
+
+  /**
+    * @brief crm apb1rst register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t apb1rst;
+    struct
+    {
+      __IO uint32_t tmr2rst              : 1; /* [0] */
+      __IO uint32_t tmr3rst              : 1; /* [1] */
+      __IO uint32_t tmr4rst              : 1; /* [2] */
+      __IO uint32_t tmr5rst              : 1; /* [3] */
+      __IO uint32_t reserved1            : 7; /* [10:4] */
+      __IO uint32_t wwdtrst              : 1; /* [11] */
+      __IO uint32_t reserved2            : 2; /* [13:12] */
+      __IO uint32_t spi2rst              : 1; /* [14] */
+      __IO uint32_t reserved3            : 2; /* [16:15] */
+      __IO uint32_t usart2rst            : 1; /* [17] */
+      __IO uint32_t usart3rst            : 1; /* [18] */
+      __IO uint32_t uart4rst             : 1; /* [19] */
+      __IO uint32_t uart5rst             : 1; /* [20] */
+      __IO uint32_t i2c1rst              : 1; /* [21] */
+      __IO uint32_t i2c2rst              : 1; /* [22] */
+      __IO uint32_t usbrst               : 1; /* [23] */
+      __IO uint32_t reserved4            : 1; /* [24] */
+      __IO uint32_t can1rst              : 1; /* [25] */
+      __IO uint32_t reserved5            : 1; /* [26] */
+      __IO uint32_t bprrst               : 1; /* [27] */
+      __IO uint32_t pwcrst               : 1; /* [28] */
+      __IO uint32_t reserved6            : 2; /* [31:30] */
+      __IO uint32_t can2rst              : 1; /* [31] */
+    } apb1rst_bit;
+  };
+
+  /**
+    * @brief crm ahben register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t ahben;
+    struct
+    {
+      __IO uint32_t dma1en               : 1; /* [0] */
+      __IO uint32_t dma2en               : 1; /* [1] */
+      __IO uint32_t sramen               : 1; /* [2] */
+      __IO uint32_t reserved1            : 1; /* [3] */
+      __IO uint32_t flashen              : 1; /* [4] */
+      __IO uint32_t reserved2            : 1; /* [5] */
+      __IO uint32_t crcen                : 1; /* [6] */
+      __IO uint32_t reserved3            : 3; /* [9:7] */
+      __IO uint32_t sdio1en              : 1; /* [10] */
+      __IO uint32_t reserved5            : 21;/* [31:11] */
+    } ahben_bit;
+  };
+
+  /**
+    * @brief crm apb2en register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t apb2en;
+    struct
+    {
+      __IO uint32_t iomuxen              : 1; /* [0] */
+      __IO uint32_t reserved1            : 1; /* [1] */
+      __IO uint32_t gpioaen              : 1; /* [2] */
+      __IO uint32_t gpioben              : 1; /* [3] */
+      __IO uint32_t gpiocen              : 1; /* [4] */
+      __IO uint32_t gpioden              : 1; /* [5] */
+      __IO uint32_t reserved2            : 1; /* [6] */
+      __IO uint32_t gpiofen              : 1; /* [7] */
+      __IO uint32_t reserved3            : 1; /* [8] */
+      __IO uint32_t adc1en               : 1; /* [9] */
+      __IO uint32_t adc2en               : 1; /* [10] */
+      __IO uint32_t tmr1en               : 1; /* [11] */
+      __IO uint32_t spi1en               : 1; /* [12] */
+      __IO uint32_t tmr8en               : 1; /* [13] */
+      __IO uint32_t usart1en             : 1; /* [14] */
+      __IO uint32_t reserved4            : 4; /* [18:15] */
+      __IO uint32_t tmr9en               : 1; /* [19] */
+      __IO uint32_t tmr10en              : 1; /* [20] */
+      __IO uint32_t tmr11en              : 1; /* [21] */
+      __IO uint32_t accen                : 1; /* [22] */
+      __IO uint32_t reserved5            : 9; /* [31:23] */
+    } apb2en_bit;
+  };
+
+  /**
+    * @brief crm apb1en register, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t apb1en;
+    struct
+    {
+      __IO uint32_t tmr2en               : 1; /* [0] */
+      __IO uint32_t tmr3en               : 1; /* [1] */
+      __IO uint32_t tmr4en               : 1; /* [2] */
+      __IO uint32_t tmr5en               : 1; /* [3] */
+      __IO uint32_t reserved1            : 7; /* [10:4] */
+      __IO uint32_t wwdten               : 1; /* [11] */
+      __IO uint32_t reserved2            : 2; /* [13:12] */
+      __IO uint32_t spi2en               : 1; /* [14] */
+      __IO uint32_t reserved3            : 2; /* [16:15] */
+      __IO uint32_t usart2en             : 1; /* [17] */
+      __IO uint32_t usart3en             : 1; /* [18] */
+      __IO uint32_t uart4en              : 1; /* [19] */
+      __IO uint32_t uart5en              : 1; /* [20] */
+      __IO uint32_t i2c1en               : 1; /* [21] */
+      __IO uint32_t i2c2en               : 1; /* [22] */
+      __IO uint32_t usben                : 1; /* [23] */
+      __IO uint32_t reserved4            : 1; /* [24] */
+      __IO uint32_t can1en               : 1; /* [25] */
+      __IO uint32_t reserved5            : 1; /* [26] */
+      __IO uint32_t bpren                : 1; /* [27] */
+      __IO uint32_t pwcen                : 1; /* [28] */
+      __IO uint32_t reserved6            : 2; /* [30:29] */
+      __IO uint32_t can2en               : 1; /* [31] */
+    } apb1en_bit;
+  };
+
+  /**
+    * @brief crm bpdc register, offset:0x20
+    */
+  union
+  {
+    __IO uint32_t bpdc;
+    struct
+    {
+      __IO uint32_t lexten               : 1; /* [0] */
+      __IO uint32_t lextstbl             : 1; /* [1] */
+      __IO uint32_t lextbyps             : 1; /* [2] */
+      __IO uint32_t reserved1            : 5; /* [7:3] */
+      __IO uint32_t rtcsel               : 2; /* [9:8] */
+      __IO uint32_t reserved2            : 5; /* [14:10] */
+      __IO uint32_t rtcen                : 1; /* [15] */
+      __IO uint32_t bpdrst               : 1; /* [16] */
+      __IO uint32_t reserved3            : 15;/* [31:17] */
+    } bpdc_bit;
+  };
+
+  /**
+    * @brief crm ctrlsts register, offset:0x24
+    */
+  union
+  {
+    __IO uint32_t ctrlsts;
+    struct
+    {
+      __IO uint32_t licken               : 1; /* [0] */
+      __IO uint32_t lickstbl             : 1; /* [1] */
+      __IO uint32_t reserved1            : 22;/* [23:2] */
+      __IO uint32_t rstfc                : 1; /* [24] */
+      __IO uint32_t reserved2            : 1; /* [25] */
+      __IO uint32_t nrstf                : 1; /* [26] */
+      __IO uint32_t porrstf              : 1; /* [27] */
+      __IO uint32_t swrstf               : 1; /* [28] */
+      __IO uint32_t wdtrstf              : 1; /* [29] */
+      __IO uint32_t wwdtrstf             : 1; /* [30] */
+      __IO uint32_t lprstf               : 1; /* [31] */
+    } ctrlsts_bit;
+  };
+
+  /**
+    * @brief crm reserved1 register, offset:0x28~0x2C
+    */
+  __IO uint32_t reserved1[2];
+
+  /**
+    * @brief crm misc1 register, offset:0x30
+    */
+  union
+  {
+    __IO uint32_t misc1;
+    struct
+    {
+      __IO uint32_t hickcal_key          : 8; /* [7:0] */
+      __IO uint32_t reserved1            : 8; /* [15:8] */
+      __IO uint32_t clkout_sel           : 1; /* [16] */
+      __IO uint32_t reserved2            : 7; /* [23:17] */
+      __IO uint32_t usbbufs              : 1; /* [24] */
+      __IO uint32_t hickdiv              : 1; /* [25] */
+      __IO uint32_t reserved3            : 2; /* [27:26] */
+      __IO uint32_t clkoutdiv            : 4; /* [31:28] */
+    } misc1_bit;
+  };
+
+  /**
+    * @brief crm reserved2 register, offset:0x4C~0x34
+    */
+  __IO uint32_t reserved2[7];
+
+  /**
+    * @brief crm misc2 register, offset:0x50
+    */
+  union
+  {
+    __IO uint32_t misc2;
+    struct
+    {
+      __IO uint32_t reserved1            : 16;/* [15:0] */
+      __IO uint32_t clk_to_tmr           : 1; /* [16] */
+      __IO uint32_t reserved2            : 15;/* [31:17] */
+    } misc2_bit;
+  };
+
+  /**
+    * @brief crm misc3 register, offset:0x54
+    */
+  union
+  {
+    __IO uint32_t misc3;
+    struct
+    {
+      __IO uint32_t reserved1            : 4; /* [3:0] */
+      __IO uint32_t auto_step_en         : 2; /* [5:4] */
+      __IO uint32_t reserved2            : 2; /* [7:6] */
+      __IO uint32_t hick_to_usb          : 1; /* [8] */
+      __IO uint32_t hick_to_sclk         : 1; /* [9] */
+      __IO uint32_t reserved3            : 22;/* [31:10] */
+    } misc3_bit;
+  };
+
+  /**
+    * @brief crm reserved3 register, offset:0x58
+    */
+  __IO uint32_t reserved3;
+
+  /**
+    * @brief crm intmap register, offset:0x5C
+    */
+  union
+  {
+    __IO uint32_t intmap;
+    struct
+    {
+      __IO uint32_t usbintmap            : 1; /* [0] */
+      __IO uint32_t reserved1            : 31;/* [31:1] */
+    } intmap_bit;
+  };
+
+} crm_type;
+
+/**
+  * @}
+  */
+
+#define CRM                              ((crm_type *) CRM_BASE)
+
+/** @defgroup CRM_exported_functions
+  * @{
+  */
+
+void crm_reset(void);
+void crm_lext_bypass(confirm_state new_state);
+void crm_hext_bypass(confirm_state new_state);
+flag_status crm_flag_get(uint32_t flag);
+error_status crm_hext_stable_wait(void);
+void crm_hick_clock_trimming_set(uint8_t trim_value);
+void crm_hick_clock_calibration_set(uint8_t cali_value);
+void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
+void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
+void crm_periph_sleep_mode_clock_enable(crm_periph_clock_sleepmd_type value, confirm_state new_state);
+void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
+void crm_flag_clear(uint32_t flag);
+void crm_rtc_clock_select(crm_rtc_clock_type value);
+void crm_rtc_clock_enable(confirm_state new_state);
+void crm_ahb_div_set(crm_ahb_div_type value);
+void crm_apb1_div_set(crm_apb1_div_type value);
+void crm_apb2_div_set(crm_apb2_div_type value);
+void crm_adc_clock_div_set(crm_adc_div_type div_value);
+void crm_usb_clock_div_set(crm_usb_div_type div_value);
+void crm_clock_failure_detection_enable(confirm_state new_state);
+void crm_battery_powered_domain_reset(confirm_state new_state);
+void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value, crm_pll_output_range_type pll_range);
+void crm_sysclk_switch(crm_sclk_type value);
+crm_sclk_type crm_sysclk_switch_status_get(void);
+void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
+void crm_clock_out_set(crm_clkout_select_type clkout);
+void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
+void crm_auto_step_mode_enable(confirm_state new_state);
+void crm_usb_interrupt_remapping_set(crm_usb_int_map_type int_remap);
+void crm_hick_divider_select(crm_hick_div_6_type value);
+void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
+void crm_usb_clock_source_select(crm_usb_clock_source_type value);
+void crm_clkout_to_tmr10_enable(confirm_state new_state);
+void crm_clkout_div_set(crm_clkout_div_type clkout_div);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_debug.h

@@ -0,0 +1,159 @@
+/**
+  **************************************************************************
+  * @file     at32f413_debug.h
+  * @brief    at32f413 debug header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_DEBUG_H
+#define __AT32F413_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup DEBUG
+  * @{
+  */
+
+/** @defgroup DEBUG_mode_definition
+  * @{
+  */
+
+#define DEBUG_SLEEP                      0x00000001 /*!< debug sleep mode */
+#define DEBUG_DEEPSLEEP                  0x00000002 /*!< debug deepsleep mode */
+#define DEBUG_STANDBY                    0x00000004 /*!< debug standby mode */
+#define DEBUG_WDT_PAUSE                  0x00000100 /*!< debug watchdog timer pause */
+#define DEBUG_WWDT_PAUSE                 0x00000200 /*!< debug window watchdog timer pause */
+#define DEBUG_TMR1_PAUSE                 0x00000400 /*!< debug timer1 pause */
+#define DEBUG_TMR2_PAUSE                 0x00000800 /*!< debug timer2 pause */
+#define DEBUG_TMR3_PAUSE                 0x00001000 /*!< debug timer3 pause */
+#define DEBUG_TMR4_PAUSE                 0x00002000 /*!< debug timer4 pause */
+#define DEBUG_CAN1_PAUSE                 0x00004000 /*!< debug can1 pause */
+#define DEBUG_I2C1_SMBUS_TIMEOUT         0x00008000 /*!< debug i2c1 smbus timeout */
+#define DEBUG_I2C2_SMBUS_TIMEOUT         0x00010000 /*!< debug i2c2 smbus timeout */
+#define DEBUG_TMR8_PAUSE                 0x00020000 /*!< debug timer8 pause */
+#define DEBUG_TMR5_PAUSE                 0x00040000 /*!< debug timer5 pause */
+#define DEBUG_CAN2_PAUSE                 0x00200000 /*!< debug can2 pause */
+#define DEBUG_TMR9_PAUSE                 0x10000000 /*!< debug timer9 pause */
+#define DEBUG_TMR10_PAUSE                0x20000000 /*!< debug timer10 pause */
+#define DEBUG_TMR11_PAUSE                0x40000000 /*!< debug timer11 pause */
+
+/**
+  * @}
+  */
+
+/** @defgroup DEBUG_exported_types
+  * @{
+  */
+
+/**
+  * @brief type define debug register all
+  */
+typedef struct
+{
+  /**
+    * @brief debug idcode register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t pid;
+    struct
+    {
+      __IO uint32_t pid                  : 32;/* [31:0] */
+    } idcode_bit;
+  };
+
+  /**
+    * @brief debug ctrl register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t ctrl;
+    struct
+    {
+      __IO uint32_t sleep_debug          : 1;/* [0] */
+      __IO uint32_t deepsleep_debug      : 1;/* [1] */
+      __IO uint32_t standby_debug        : 1;/* [2] */
+      __IO uint32_t reserved1            : 2;/* [4:3] */
+      __IO uint32_t trace_ioen           : 1;/* [5] */
+      __IO uint32_t trace_mode           : 2;/* [7:6] */
+      __IO uint32_t wdt_pause            : 1;/* [8] */
+      __IO uint32_t wwdt_pause           : 1;/* [9] */
+      __IO uint32_t tmr1_pause           : 1;/* [10] */
+      __IO uint32_t tmr2_pause           : 1;/* [11] */
+      __IO uint32_t tmr3_pause           : 1;/* [12] */
+      __IO uint32_t tmr4_pause           : 1;/* [13] */
+      __IO uint32_t can1_pause           : 1;/* [14] */
+      __IO uint32_t i2c1_smbus_timeout   : 1;/* [15] */
+      __IO uint32_t i2c2_smbus_timeout   : 1;/* [16] */
+      __IO uint32_t tmr8_pause           : 1;/* [17] */
+      __IO uint32_t tmr5_pause           : 1;/* [18] */
+      __IO uint32_t reserved2            : 2;/* [20:19] */
+      __IO uint32_t can2_pause           : 1;/* [21] */
+      __IO uint32_t reserved3            : 6;/* [27:22] */
+      __IO uint32_t tmr9_pause           : 1;/* [28] */
+      __IO uint32_t tmr10_pause          : 1;/* [29] */
+      __IO uint32_t tmr11_pause          : 1;/* [30] */
+      __IO uint32_t reserved4            : 1;/* [31] */
+    } ctrl_bit;
+  };
+
+} debug_type;
+
+/**
+  * @}
+  */
+
+#define DEBUGMCU                         ((debug_type *) DEBUG_BASE)
+
+/** @defgroup DEBUG_exported_functions
+  * @{
+  */
+
+uint32_t debug_device_id_get(void);
+void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_def.h

@@ -0,0 +1,69 @@
+/**
+  **************************************************************************
+  * @file     at32f413_def.h
+  * @brief    at32f413 macros header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_DEF_H
+#define __AT32F413_DEF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* gnu compiler */
+#if defined (__GNUC__)
+  #ifndef ALIGNED_HEAD
+    #define ALIGNED_HEAD
+  #endif
+  #ifndef ALIGNED_TAIL
+    #define ALIGNED_TAIL                 __attribute__ ((aligned (4)))
+  #endif
+#endif
+
+/* arm compiler */
+#if defined (__CC_ARM)
+  #ifndef ALIGNED_HEAD
+    #define ALIGNED_HEAD                 __align(4)
+  #endif
+  #ifndef ALIGNED_TAIL
+    #define ALIGNED_TAIL
+  #endif
+#endif
+
+/* iar compiler */
+#if defined (__ICCARM__)
+  #ifndef ALIGNED_HEAD
+    #define ALIGNED_HEAD
+  #endif
+  #ifndef ALIGNED_TAIL
+    #define ALIGNED_TAIL
+  #endif
+#endif
+
+#define UNUSED(x)                        (void)x /* to avoid gcc/g++ warnings */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_dma.h

@@ -0,0 +1,527 @@
+/**
+  **************************************************************************
+  * @file     at32f413_dma.h
+  * @brief    at32f413 dma header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_DMA_H
+#define __AT32F413_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/** @defgroup DMA_interrupts_definition
+  * @brief dma interrupt
+  * @{
+  */
+
+#define DMA_FDT_INT                      ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
+#define DMA_HDT_INT                      ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
+#define DMA_DTERR_INT                    ((uint32_t)0x00000008) /*!< dma errorr interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flexible_channel
+  * @{
+  */
+
+#define FLEX_CHANNEL1                    ((uint8_t)0x01) /*!< dma flexible channel1 */
+#define FLEX_CHANNEL2                    ((uint8_t)0x02) /*!< dma flexible channel2 */
+#define FLEX_CHANNEL3                    ((uint8_t)0x03) /*!< dma flexible channel3 */
+#define FLEX_CHANNEL4                    ((uint8_t)0x04) /*!< dma flexible channel4 */
+#define FLEX_CHANNEL5                    ((uint8_t)0x05) /*!< dma flexible channel5 */
+#define FLEX_CHANNEL6                    ((uint8_t)0x06) /*!< dma flexible channel6 */
+#define FLEX_CHANNEL7                    ((uint8_t)0x07) /*!< dma flexible channel7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flags_definition
+  * @brief dma flag
+  * @{
+  */
+
+#define DMA1_GL1_FLAG                    ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
+#define DMA1_FDT1_FLAG                   ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
+#define DMA1_HDT1_FLAG                   ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
+#define DMA1_DTERR1_FLAG                 ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
+#define DMA1_GL2_FLAG                    ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
+#define DMA1_FDT2_FLAG                   ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
+#define DMA1_HDT2_FLAG                   ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
+#define DMA1_DTERR2_FLAG                 ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
+#define DMA1_GL3_FLAG                    ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
+#define DMA1_FDT3_FLAG                   ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
+#define DMA1_HDT3_FLAG                   ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
+#define DMA1_DTERR3_FLAG                 ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
+#define DMA1_GL4_FLAG                    ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
+#define DMA1_FDT4_FLAG                   ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
+#define DMA1_HDT4_FLAG                   ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
+#define DMA1_DTERR4_FLAG                 ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
+#define DMA1_GL5_FLAG                    ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
+#define DMA1_FDT5_FLAG                   ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
+#define DMA1_HDT5_FLAG                   ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
+#define DMA1_DTERR5_FLAG                 ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
+#define DMA1_GL6_FLAG                    ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
+#define DMA1_FDT6_FLAG                   ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
+#define DMA1_HDT6_FLAG                   ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
+#define DMA1_DTERR6_FLAG                 ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
+#define DMA1_GL7_FLAG                    ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
+#define DMA1_FDT7_FLAG                   ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
+#define DMA1_HDT7_FLAG                   ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
+#define DMA1_DTERR7_FLAG                 ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
+
+#define DMA2_GL1_FLAG                    ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
+#define DMA2_FDT1_FLAG                   ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
+#define DMA2_HDT1_FLAG                   ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
+#define DMA2_DTERR1_FLAG                 ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
+#define DMA2_GL2_FLAG                    ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
+#define DMA2_FDT2_FLAG                   ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
+#define DMA2_HDT2_FLAG                   ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
+#define DMA2_DTERR2_FLAG                 ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
+#define DMA2_GL3_FLAG                    ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
+#define DMA2_FDT3_FLAG                   ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
+#define DMA2_HDT3_FLAG                   ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
+#define DMA2_DTERR3_FLAG                 ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
+#define DMA2_GL4_FLAG                    ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
+#define DMA2_FDT4_FLAG                   ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
+#define DMA2_HDT4_FLAG                   ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
+#define DMA2_DTERR4_FLAG                 ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
+#define DMA2_GL5_FLAG                    ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
+#define DMA2_FDT5_FLAG                   ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
+#define DMA2_HDT5_FLAG                   ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
+#define DMA2_DTERR5_FLAG                 ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
+#define DMA2_GL6_FLAG                    ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
+#define DMA2_FDT6_FLAG                   ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
+#define DMA2_HDT6_FLAG                   ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
+#define DMA2_DTERR6_FLAG                 ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
+#define DMA2_GL7_FLAG                    ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
+#define DMA2_FDT7_FLAG                   ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
+#define DMA2_HDT7_FLAG                   ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
+#define DMA2_DTERR7_FLAG                 ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_exported_types
+  * @{
+  */
+
+/**
+  * @brief dma flexible request type
+  */
+typedef enum
+{
+  DMA_FLEXIBLE_ADC1                      = 0x01, /*!< adc1 flexible request id */
+  DMA_FLEXIBLE_SPI1_RX                   = 0x09, /*!< spi1_rx flexible request id */
+  DMA_FLEXIBLE_SPI1_TX                   = 0x0A, /*!< spi1_tx flexible request id */
+  DMA_FLEXIBLE_SPI2_RX                   = 0x0B, /*!< spi2_rx flexible request id */
+  DMA_FLEXIBLE_SPI2_TX                   = 0x0C, /*!< spi2_tx flexible request id */
+  DMA_FLEXIBLE_UART1_RX                  = 0x19, /*!< uart1_rx flexible request id */
+  DMA_FLEXIBLE_UART1_TX                  = 0x1A, /*!< uart1_tx flexible request id */
+  DMA_FLEXIBLE_UART2_RX                  = 0x1B, /*!< uart2_rx flexible request id */
+  DMA_FLEXIBLE_UART2_TX                  = 0x1C, /*!< uart2_tx flexible request id */
+  DMA_FLEXIBLE_UART3_RX                  = 0x1D, /*!< uart3_rx flexible request id */
+  DMA_FLEXIBLE_UART3_TX                  = 0x1E, /*!< uart3_tx flexible request id */
+  DMA_FLEXIBLE_UART4_RX                  = 0x1F, /*!< uart4_rx flexible request id */
+  DMA_FLEXIBLE_UART4_TX                  = 0x20, /*!< uart4_tx flexible request id */
+  DMA_FLEXIBLE_UART5_RX                  = 0x21, /*!< uart5_rx flexible request id */
+  DMA_FLEXIBLE_UART5_TX                  = 0x22, /*!< uart5_tx flexible request id */
+  DMA_FLEXIBLE_I2C1_RX                   = 0x29, /*!< i2c1_rx flexible request id */
+  DMA_FLEXIBLE_I2C1_TX                   = 0x2A, /*!< i2c1_tx flexible request id */
+  DMA_FLEXIBLE_I2C2_RX                   = 0x2B, /*!< i2c2_rx flexible request id */
+  DMA_FLEXIBLE_I2C2_TX                   = 0x2C, /*!< i2c2_tx flexible request id */
+  DMA_FLEXIBLE_SDIO1                     = 0x31, /*!< sdio1 flexible request id */
+  DMA_FLEXIBLE_TMR1_TRIG                 = 0x35, /*!< tmr1_trig flexible request id */
+  DMA_FLEXIBLE_TMR1_HALL                 = 0x36, /*!< tmr1_hall flexible request id */
+  DMA_FLEXIBLE_TMR1_OVERFLOW             = 0x37, /*!< tmr1_overflow flexible request id */
+  DMA_FLEXIBLE_TMR1_CH1                  = 0x38, /*!< tmr1_ch1 flexible request id */
+  DMA_FLEXIBLE_TMR1_CH2                  = 0x39, /*!< tmr1_ch2 flexible request id */
+  DMA_FLEXIBLE_TMR1_CH3                  = 0x3A, /*!< tmr1_ch3 flexible request id */
+  DMA_FLEXIBLE_TMR1_CH4                  = 0x3B, /*!< tmr1_ch4 flexible request id */
+  DMA_FLEXIBLE_TMR2_TRIG                 = 0x3D, /*!< tmr2_trig flexible request id */
+  DMA_FLEXIBLE_TMR2_OVERFLOW             = 0x3F, /*!< tmr2_overflow flexible request id */
+  DMA_FLEXIBLE_TMR2_CH1                  = 0x40, /*!< tmr2_ch1 flexible request id */
+  DMA_FLEXIBLE_TMR2_CH2                  = 0x41, /*!< tmr2_ch2 flexible request id */
+  DMA_FLEXIBLE_TMR2_CH3                  = 0x42, /*!< tmr2_ch3 flexible request id */
+  DMA_FLEXIBLE_TMR2_CH4                  = 0x43, /*!< tmr2_ch4 flexible request id */
+  DMA_FLEXIBLE_TMR3_TRIG                 = 0x45, /*!< tmr3_trig flexible request id */
+  DMA_FLEXIBLE_TMR3_OVERFLOW             = 0x47, /*!< tmr3_overflow flexible request id */
+  DMA_FLEXIBLE_TMR3_CH1                  = 0x48, /*!< tmr3_ch1 flexible request id */
+  DMA_FLEXIBLE_TMR3_CH2                  = 0x49, /*!< tmr3_ch2 flexible request id */
+  DMA_FLEXIBLE_TMR3_CH3                  = 0x4A, /*!< tmr3_ch3 flexible request id */
+  DMA_FLEXIBLE_TMR3_CH4                  = 0x4B, /*!< tmr3_ch4 flexible request id */
+  DMA_FLEXIBLE_TMR4_TRIG                 = 0x4D, /*!< tmr4_trig flexible request id */
+  DMA_FLEXIBLE_TMR4_OVERFLOW             = 0x4F, /*!< tmr4_overflow flexible request id */
+  DMA_FLEXIBLE_TMR4_CH1                  = 0x50, /*!< tmr4_ch1 flexible request id */
+  DMA_FLEXIBLE_TMR4_CH2                  = 0x51, /*!< tmr4_ch2 flexible request id */
+  DMA_FLEXIBLE_TMR4_CH3                  = 0x52, /*!< tmr4_ch3 flexible request id */
+  DMA_FLEXIBLE_TMR4_CH4                  = 0x53, /*!< tmr4_ch4 flexible request id */
+  DMA_FLEXIBLE_TMR5_TRIG                 = 0x55, /*!< tmr5_trig flexible request id */
+  DMA_FLEXIBLE_TMR5_OVERFLOW             = 0x57, /*!< tmr5_overflow flexible request id */
+  DMA_FLEXIBLE_TMR5_CH1                  = 0x58, /*!< tmr5_ch1 flexible request id */
+  DMA_FLEXIBLE_TMR5_CH2                  = 0x59, /*!< tmr5_ch2 flexible request id */
+  DMA_FLEXIBLE_TMR5_CH3                  = 0x5A, /*!< tmr5_ch3 flexible request id */
+  DMA_FLEXIBLE_TMR5_CH4                  = 0x5B, /*!< tmr5_ch4 flexible request id */
+  DMA_FLEXIBLE_TMR8_TRIG                 = 0x6D, /*!< tmr8_trig flexible request id */
+  DMA_FLEXIBLE_TMR8_HALL                 = 0x6E, /*!< tmr8_hall flexible request id */
+  DMA_FLEXIBLE_TMR8_OVERFLOW             = 0x6F, /*!< tmr8_overflow flexible request id */
+  DMA_FLEXIBLE_TMR8_CH1                  = 0x70, /*!< tmr8_ch1 flexible request id */
+  DMA_FLEXIBLE_TMR8_CH2                  = 0x71, /*!< tmr8_ch2 flexible request id */
+  DMA_FLEXIBLE_TMR8_CH3                  = 0x72, /*!< tmr8_ch3 flexible request id */
+  DMA_FLEXIBLE_TMR8_CH4                  = 0x73, /*!< tmr8_ch4 flexible request id */
+} dma_flexible_request_type;
+
+/**
+  * @brief dma direction type
+  */
+typedef enum
+{
+  DMA_DIR_PERIPHERAL_TO_MEMORY           = 0x0000, /*!< dma data transfer direction:peripheral to memory */
+  DMA_DIR_MEMORY_TO_PERIPHERAL           = 0x0010, /*!< dma data transfer direction:memory to peripheral */
+  DMA_DIR_MEMORY_TO_MEMORY               = 0x4000  /*!< dma data transfer direction:memory to memory */
+} dma_dir_type;
+
+/**
+  * @brief dma peripheral incremented type
+  */
+typedef enum
+{
+  DMA_PERIPHERAL_INC_DISABLE             = 0x00, /*!< dma peripheral increment mode disable */
+  DMA_PERIPHERAL_INC_ENABLE              = 0x01  /*!< dma peripheral increment mode enable */
+} dma_peripheral_inc_type;
+
+/**
+  * @brief dma memory incremented type
+  */
+typedef enum
+{
+  DMA_MEMORY_INC_DISABLE                 = 0x00, /*!< dma memory increment mode disable */
+  DMA_MEMORY_INC_ENABLE                  = 0x01  /*!< dma memory increment mode enable */
+} dma_memory_inc_type;
+
+/**
+  * @brief dma peripheral data size type
+  */
+typedef enum
+{
+  DMA_PERIPHERAL_DATA_WIDTH_BYTE         = 0x00, /*!< dma peripheral databus width 8bit */
+  DMA_PERIPHERAL_DATA_WIDTH_HALFWORD     = 0x01, /*!< dma peripheral databus width 16bit */
+  DMA_PERIPHERAL_DATA_WIDTH_WORD         = 0x02  /*!< dma peripheral databus width 32bit */
+} dma_peripheral_data_size_type;
+
+/**
+  * @brief dma memory data size type
+  */
+typedef enum
+{
+  DMA_MEMORY_DATA_WIDTH_BYTE             = 0x00, /*!< dma memory databus width 8bit */
+  DMA_MEMORY_DATA_WIDTH_HALFWORD         = 0x01, /*!< dma memory databus width 16bit */
+  DMA_MEMORY_DATA_WIDTH_WORD             = 0x02  /*!< dma memory databus width 32bit */
+} dma_memory_data_size_type;
+
+/**
+  * @brief dma priority level type
+  */
+typedef enum
+{
+  DMA_PRIORITY_LOW                       = 0x00, /*!< dma channel priority: low */
+  DMA_PRIORITY_MEDIUM                    = 0x01, /*!< dma channel priority: mediue */
+  DMA_PRIORITY_HIGH                      = 0x02, /*!< dma channel priority: high */
+  DMA_PRIORITY_VERY_HIGH                 = 0x03  /*!< dma channel priority: very high */
+} dma_priority_level_type;
+
+/**
+  * @brief dma init type
+  */
+typedef struct
+{
+  uint32_t                               peripheral_base_addr;    /*!< base addrress for peripheral */
+  uint32_t                               memory_base_addr;        /*!< base addrress for memory */
+  dma_dir_type                           direction;               /*!< dma transmit direction, peripheral as source or as destnation  */
+  uint16_t                               buffer_size;             /*!< counter to transfer */
+  confirm_state                          peripheral_inc_enable;   /*!< periphera address increment after one transmit */
+  confirm_state                          memory_inc_enable;       /*!< memory address increment after one transmit */
+  dma_peripheral_data_size_type          peripheral_data_width;   /*!< peripheral data width for transmit */
+  dma_memory_data_size_type              memory_data_width;       /*!< memory data width for transmit */
+  confirm_state                          loop_mode_enable;        /*!< when circular mode enable, buffer size will reload if count to 0 */
+  dma_priority_level_type                priority;                /*!< dma priority can choose from very high, high, dedium or low */
+} dma_init_type;
+
+/**
+  * @brief type define dma register
+  */
+typedef struct
+{
+  /**
+    * @brief dma sts register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t sts;
+    struct
+    {
+      __IO uint32_t gf1                  : 1; /* [0] */
+      __IO uint32_t fdtf1                : 1; /* [1] */
+      __IO uint32_t hdtf1                : 1; /* [2] */
+      __IO uint32_t dterrf1              : 1; /* [3] */
+      __IO uint32_t gf2                  : 1; /* [4] */
+      __IO uint32_t fdtf2                : 1; /* [5] */
+      __IO uint32_t hdtf2                : 1; /* [6] */
+      __IO uint32_t dterrf2              : 1; /* [7] */
+      __IO uint32_t gf3                  : 1; /* [8] */
+      __IO uint32_t fdtf3                : 1; /* [9] */
+      __IO uint32_t hdtf3                : 1; /* [10] */
+      __IO uint32_t dterrf3              : 1; /* [11] */
+      __IO uint32_t gf4                  : 1; /* [12] */
+      __IO uint32_t fdtf4                : 1; /* [13] */
+      __IO uint32_t hdtf4                : 1; /* [14] */
+      __IO uint32_t dterrf4              : 1; /* [15] */
+      __IO uint32_t gf5                  : 1; /* [16] */
+      __IO uint32_t fdtf5                : 1; /* [17] */
+      __IO uint32_t hdtf5                : 1; /* [18] */
+      __IO uint32_t dterrf5              : 1; /* [19] */
+      __IO uint32_t gf6                  : 1; /* [20] */
+      __IO uint32_t fdtf6                : 1; /* [21] */
+      __IO uint32_t hdtf6                : 1; /* [22] */
+      __IO uint32_t dterrf6              : 1; /* [23] */
+      __IO uint32_t gf7                  : 1; /* [24] */
+      __IO uint32_t fdtf7                : 1; /* [25] */
+      __IO uint32_t hdtf7                : 1; /* [26] */
+      __IO uint32_t dterrf7              : 1; /* [27] */
+      __IO uint32_t reserved1            : 4; /* [31:28] */
+    } sts_bit;
+  };
+
+  /**
+    * @brief dma clr register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t clr;
+    struct
+    {
+      __IO uint32_t gfc1                 : 1; /* [0] */
+      __IO uint32_t fdtfc1               : 1; /* [1] */
+      __IO uint32_t hdtfc1               : 1; /* [2] */
+      __IO uint32_t dterrfc1             : 1; /* [3] */
+      __IO uint32_t gfc2                 : 1; /* [4] */
+      __IO uint32_t fdtfc2               : 1; /* [5] */
+      __IO uint32_t hdtfc2               : 1; /* [6] */
+      __IO uint32_t dterrfc2             : 1; /* [7] */
+      __IO uint32_t gfc3                 : 1; /* [8] */
+      __IO uint32_t fdtfc3               : 1; /* [9] */
+      __IO uint32_t hdtfc3               : 1; /* [10] */
+      __IO uint32_t dterrfc3             : 1; /* [11] */
+      __IO uint32_t gfc4                 : 1; /* [12] */
+      __IO uint32_t fdtfc4               : 1; /* [13] */
+      __IO uint32_t hdtfc4               : 1; /* [14] */
+      __IO uint32_t dterrfc4             : 1; /* [15] */
+      __IO uint32_t gfc5                 : 1; /* [16] */
+      __IO uint32_t fdtfc5               : 1; /* [17] */
+      __IO uint32_t hdtfc5               : 1; /* [18] */
+      __IO uint32_t dterrfc5             : 1; /* [19] */
+      __IO uint32_t gfc6                 : 1; /* [20] */
+      __IO uint32_t fdtfc6               : 1; /* [21] */
+      __IO uint32_t hdtfc6               : 1; /* [22] */
+      __IO uint32_t dterrfc6             : 1; /* [23] */
+      __IO uint32_t gfc7                 : 1; /* [24] */
+      __IO uint32_t fdtfc7               : 1; /* [25] */
+      __IO uint32_t hdtfc7               : 1; /* [26] */
+      __IO uint32_t dterrfc7             : 1; /* [27] */
+      __IO uint32_t reserved1            : 4; /* [31:28] */
+    } clr_bit;
+  };
+  /**
+    * @brief reserved, offset:0x08~0x9C
+    */
+  __IO uint32_t reserved1[38];
+  /**
+    * @brief dma src_sel0 register, offset:0xA0
+    */
+  union
+  {
+    __IO uint32_t src_sel0;
+    struct
+    {
+      __IO uint32_t ch1_src              : 8; /* [7:0] */
+      __IO uint32_t ch2_src              : 8; /* [15:8] */
+      __IO uint32_t ch3_src              : 8; /* [23:16] */
+      __IO uint32_t ch4_src              : 8; /* [31:24] */
+    } src_sel0_bit;
+  };
+
+  /**
+    * @brief dma src_sel1 register, offset:0xA4
+    */
+  union
+  {
+    __IO uint32_t src_sel1;
+    struct
+    {
+      __IO uint32_t ch5_src              : 8; /* [7:0] */
+      __IO uint32_t ch6_src              : 8; /* [15:8] */
+      __IO uint32_t ch7_src              : 8; /* [23:16] */
+      __IO uint32_t dma_flex_en          : 1; /* [24] */
+      __IO uint32_t reserved1            : 7; /* [31:25] */
+    } src_sel1_bit;
+  };
+} dma_type;
+
+/**
+  * @brief type define dma channel register all
+  */
+typedef struct
+{
+  /**
+    * @brief dma ctrl register, offset:0x08+20*(x-1) x=1...7
+    */
+  union
+  {
+    __IO uint32_t ctrl;
+    struct
+    {
+      __IO uint32_t chen                 : 1; /* [0] */
+      __IO uint32_t fdtien               : 1; /* [1] */
+      __IO uint32_t hdtien               : 1; /* [2] */
+      __IO uint32_t dterrien             : 1; /* [3] */
+      __IO uint32_t dtd                  : 1; /* [4] */
+      __IO uint32_t lm                   : 1; /* [5] */
+      __IO uint32_t pincm                : 1; /* [6] */
+      __IO uint32_t mincm                : 1; /* [7] */
+      __IO uint32_t pwidth               : 2; /* [9:8] */
+      __IO uint32_t mwidth               : 2; /* [11:10] */
+      __IO uint32_t chpl                 : 2; /* [13:12] */
+      __IO uint32_t m2m                  : 1; /* [14] */
+      __IO uint32_t reserved1            : 17;/* [31:15] */
+    } ctrl_bit;
+  };
+
+  /**
+    * @brief dma dtcnt register, offset:0x0C+20*(x-1) x=1...7
+    */
+  union
+  {
+    __IO uint32_t dtcnt;
+    struct
+    {
+      __IO uint32_t cnt                  : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } dtcnt_bit;
+  };
+
+  /**
+    * @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
+    */
+  union
+  {
+    __IO uint32_t paddr;
+    struct
+    {
+      __IO uint32_t paddr                : 32;/* [31:0] */
+    } paddr_bit;
+  };
+
+  /**
+    * @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
+    */
+  union
+  {
+    __IO uint32_t maddr;
+    struct
+    {
+      __IO uint32_t maddr                : 32;/* [31:0] */
+    } maddr_bit;
+  };
+} dma_channel_type;
+
+/**
+  * @}
+  */
+
+#define DMA1                             ((dma_type *) DMA1_BASE)
+#define DMA1_CHANNEL1                    ((dma_channel_type *) DMA1_CHANNEL1_BASE)
+#define DMA1_CHANNEL2                    ((dma_channel_type *) DMA1_CHANNEL2_BASE)
+#define DMA1_CHANNEL3                    ((dma_channel_type *) DMA1_CHANNEL3_BASE)
+#define DMA1_CHANNEL4                    ((dma_channel_type *) DMA1_CHANNEL4_BASE)
+#define DMA1_CHANNEL5                    ((dma_channel_type *) DMA1_CHANNEL5_BASE)
+#define DMA1_CHANNEL6                    ((dma_channel_type *) DMA1_CHANNEL6_BASE)
+#define DMA1_CHANNEL7                    ((dma_channel_type *) DMA1_CHANNEL7_BASE)
+
+#define DMA2                             ((dma_type *) DMA2_BASE)
+#define DMA2_CHANNEL1                    ((dma_channel_type *) DMA2_CHANNEL1_BASE)
+#define DMA2_CHANNEL2                    ((dma_channel_type *) DMA2_CHANNEL2_BASE)
+#define DMA2_CHANNEL3                    ((dma_channel_type *) DMA2_CHANNEL3_BASE)
+#define DMA2_CHANNEL4                    ((dma_channel_type *) DMA2_CHANNEL4_BASE)
+#define DMA2_CHANNEL5                    ((dma_channel_type *) DMA2_CHANNEL5_BASE)
+#define DMA2_CHANNEL6                    ((dma_channel_type *) DMA2_CHANNEL6_BASE)
+#define DMA2_CHANNEL7                    ((dma_channel_type *) DMA2_CHANNEL7_BASE)
+
+/** @defgroup DMA_exported_functions
+  * @{
+  */
+
+void dma_reset(dma_channel_type* dmax_channely);
+void dma_default_para_init(dma_init_type* dma_init_struct);
+void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);
+void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
+void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request);
+void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number);
+uint16_t dma_data_number_get(dma_channel_type* dmax_channely);
+void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state);
+flag_status dma_flag_get(uint32_t dmax_flag);
+void dma_flag_clear(uint32_t dmax_flag);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_exint.h

@@ -0,0 +1,227 @@
+/**
+  **************************************************************************
+  * @file     at32f413_exint.h
+  * @brief    at32f413 exint header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_EXINT_H
+#define __AT32F413_EXINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup EXINT
+  * @{
+  */
+
+/** @defgroup EXINT_lines
+  * @{
+  */
+
+#define EXINT_LINE_NONE                  ((uint32_t)0x000000)
+#define EXINT_LINE_0                     ((uint32_t)0x000001) /*!< external interrupt line 0 */
+#define EXINT_LINE_1                     ((uint32_t)0x000002) /*!< external interrupt line 1 */
+#define EXINT_LINE_2                     ((uint32_t)0x000004) /*!< external interrupt line 2 */
+#define EXINT_LINE_3                     ((uint32_t)0x000008) /*!< external interrupt line 3 */
+#define EXINT_LINE_4                     ((uint32_t)0x000010) /*!< external interrupt line 4 */
+#define EXINT_LINE_5                     ((uint32_t)0x000020) /*!< external interrupt line 5 */
+#define EXINT_LINE_6                     ((uint32_t)0x000040) /*!< external interrupt line 6 */
+#define EXINT_LINE_7                     ((uint32_t)0x000080) /*!< external interrupt line 7 */
+#define EXINT_LINE_8                     ((uint32_t)0x000100) /*!< external interrupt line 8 */
+#define EXINT_LINE_9                     ((uint32_t)0x000200) /*!< external interrupt line 9 */
+#define EXINT_LINE_10                    ((uint32_t)0x000400) /*!< external interrupt line 10 */
+#define EXINT_LINE_11                    ((uint32_t)0x000800) /*!< external interrupt line 11 */
+#define EXINT_LINE_12                    ((uint32_t)0x001000) /*!< external interrupt line 12 */
+#define EXINT_LINE_13                    ((uint32_t)0x002000) /*!< external interrupt line 13 */
+#define EXINT_LINE_14                    ((uint32_t)0x004000) /*!< external interrupt line 14 */
+#define EXINT_LINE_15                    ((uint32_t)0x008000) /*!< external interrupt line 15 */
+#define EXINT_LINE_16                    ((uint32_t)0x010000) /*!< external interrupt line 16 connected to the pvm output */
+#define EXINT_LINE_17                    ((uint32_t)0x020000) /*!< external interrupt line 17 connected to the rtc alarm event */
+#define EXINT_LINE_18                    ((uint32_t)0x040000) /*!< external interrupt line 18 connected to the usb fs wakeup from suspend event */
+/**
+  * @}
+  */
+
+/** @defgroup EXINT_exported_types
+  * @{
+  */
+
+/**
+  * @brief exint line mode type
+  */
+typedef enum
+{
+  EXINT_LINE_INTERRUPUT                  = 0x00, /*!< external interrupt line interrupt mode */
+  EXINT_LINE_EVENT                       = 0x01  /*!< external interrupt line event mode */
+} exint_line_mode_type;
+
+/**
+  * @brief exint polarity configuration type
+  */
+typedef enum
+{
+  EXINT_TRIGGER_RISING_EDGE              = 0x00, /*!< external interrupt line rising trigger mode */
+  EXINT_TRIGGER_FALLING_EDGE             = 0x01, /*!< external interrupt line falling trigger mode */
+  EXINT_TRIGGER_BOTH_EDGE                = 0x02  /*!< external interrupt line both rising and falling trigger mode */
+} exint_polarity_config_type;
+
+/**
+  * @brief exint init type
+  */
+typedef struct
+{
+  exint_line_mode_type                   line_mode;     /*!< choose mode event or interrupt mode */
+  uint32_t                               line_select;   /*!< select the exint line, availiable for single line or multiple lines */
+  exint_polarity_config_type             line_polarity; /*!< select the tregger polarity, with rising edge, falling edge or both edge */
+  confirm_state                          line_enable;   /*!< enable or disable exint */
+} exint_init_type;
+
+/**
+  * @brief type define exint register all
+  */
+typedef struct
+{
+
+  /**
+    * @brief exint inten register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t inten;
+    struct
+    {
+      __IO uint32_t intenx               : 23;/* [22:0] */
+      __IO uint32_t reserved1            : 9;/* [31:23] */
+    } inten_bit;
+  };
+
+  /**
+    * @brief exint evten register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t evten;
+    struct
+    {
+      __IO uint32_t evtenx               : 23;/* [22:0] */
+      __IO uint32_t reserved1            : 9;/* [31:23] */
+    } evten_bit;
+  };
+
+  /**
+    * @brief exint polcfg1 register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t polcfg1;
+    struct
+    {
+      __IO uint32_t rpx                  : 23;/* [22:0] */
+      __IO uint32_t reserved1            : 9;/* [31:23] */
+    } polcfg1_bit;
+  };
+
+  /**
+    * @brief exint polcfg2 register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t polcfg2;
+    struct
+    {
+      __IO uint32_t fpx                  : 23;/* [22:0] */
+      __IO uint32_t reserved1            : 9;/* [31:23] */
+    } polcfg2_bit;
+  };
+
+  /**
+    * @brief exint swtrg register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t swtrg;
+    struct
+    {
+      __IO uint32_t swtx                 : 23;/* [22:0] */
+      __IO uint32_t reserved1            : 9;/* [31:23] */
+    } swtrg_bit;
+  };
+
+  /**
+    * @brief exint intsts register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t intsts;
+    struct
+    {
+      __IO uint32_t linex                : 23;/* [22:0] */
+      __IO uint32_t reserved1            : 9;/* [31:23] */
+    } intsts_bit;
+  };
+} exint_type;
+
+/**
+  * @}
+  */
+
+#define EXINT                             ((exint_type *) EXINT_BASE)
+
+/** @defgroup EXINT_exported_functions
+  * @{
+  */
+
+void exint_reset(void);
+void exint_default_para_init(exint_init_type *exint_struct);
+void exint_init(exint_init_type *exint_struct);
+void exint_flag_clear(uint32_t exint_line);
+flag_status exint_flag_get(uint32_t exint_line);
+void exint_software_interrupt_event_generate(uint32_t exint_line);
+void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
+void exint_event_enable(uint32_t exint_line, confirm_state new_state);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_flash.h

@@ -0,0 +1,621 @@
+/**
+  **************************************************************************
+  * @file     at32f413_flash.h
+  * @brief    at32f413 flash header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_FLASH_H
+#define __AT32F413_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/** @defgroup FLASH_unlock_keys
+  * @brief flash unlock keys
+  * @{
+  */
+
+#define FLASH_UNLOCK_KEY1                ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */
+#define FLASH_UNLOCK_KEY2                ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */
+#define FAP_RELIEVE_KEY                  ((uint16_t)0x00A5)     /*!< flash fap relieve key val */
+#define SLIB_UNLOCK_KEY                  ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_spim_address
+  * @brief flash spim address
+  * @{
+  */
+#define FLASH_SPIM_START_ADDR            ((uint32_t)0x08400000) /*!< flash start address of spim */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_flags
+  * @brief flash flag
+  * @{
+  */
+
+#define FLASH_OBF_FLAG                   ((uint32_t)0x00000001)   /*!< flash bank1 operate busy flag */
+#define FLASH_ODF_FLAG                   ((uint32_t)0x00000020)   /*!< flash bank1 operate done flag */
+#define FLASH_PRGMERR_FLAG               ((uint32_t)0x00000004)   /*!< flash bank1 program error flag */
+#define FLASH_EPPERR_FLAG                ((uint32_t)0x00000010)   /*!< flash bank1 erase/program protection error flag */
+#define FLASH_SPIM_OBF_FLAG              ((uint32_t)0x20000001)   /*!< flash spim operate busy flag */
+#define FLASH_SPIM_ODF_FLAG              ((uint32_t)0x20000020)   /*!< flash spim operate done flag */
+#define FLASH_SPIM_PRGMERR_FLAG          ((uint32_t)0x20000004)   /*!< flash spim program error flag */
+#define FLASH_SPIM_EPPERR_FLAG           ((uint32_t)0x20000010)   /*!< flash spim erase/program protection error flag */
+#define FLASH_USDERR_FLAG                ((uint32_t)0x40000001)   /*!< flash user system data error flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_interrupts
+  * @brief flash interrupts
+  * @{
+  */
+
+#define FLASH_ERR_INT                    ((uint32_t)0x00000001) /*!< flash bank1 error interrupt */
+#define FLASH_ODF_INT                    ((uint32_t)0x00000002) /*!< flash bank1 operate done interrupt */
+#define FLASH_SPIM_ERR_INT               ((uint32_t)0x00000010) /*!< flash spim error interrupt */
+#define FLASH_SPIM_ODF_INT               ((uint32_t)0x00000020) /*!< flash spim operate done interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_slib_mask
+  * @brief flash slib mask
+  * @{
+  */
+
+#define FLASH_SLIB_START_SECTOR          ((uint32_t)0x000007FF) /*!< flash slib start sector */
+#define FLASH_SLIB_DATA_START_SECTOR     ((uint32_t)0x003FF800) /*!< flash slib d-bus area start sector */
+#define FLASH_SLIB_END_SECTOR            ((uint32_t)0xFFC00000) /*!< flash slib end sector */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_user_system_data
+  * @brief flash user system data
+  * @{
+  */
+
+#define USD_WDT_ATO_DISABLE              ((uint16_t)0x0001) /*!< wdt auto start disabled  */
+#define USD_WDT_ATO_ENABLE               ((uint16_t)0x0000) /*!< wdt auto start enabled */
+
+#define USD_DEPSLP_NO_RST                ((uint16_t)0x0002) /*!< no reset generated when entering in deepsleep */
+#define USD_DEPSLP_RST                   ((uint16_t)0x0000) /*!< reset generated when entering in deepsleep */
+
+#define USD_STDBY_NO_RST                 ((uint16_t)0x0004) /*!< no reset generated when entering in standby */
+#define USD_STDBY_RST                    ((uint16_t)0x0000) /*!< reset generated when entering in standby */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_timeout_definition
+  * @brief flash timeout definition
+  * @{
+  */
+
+#define ERASE_TIMEOUT                    ((uint32_t)0x40000000) /*!< internal flash erase operation timeout */
+#define PROGRAMMING_TIMEOUT              ((uint32_t)0x00100000) /*!< internal flash program operation timeout */
+#define SPIM_ERASE_TIMEOUT               ((uint32_t)0xFFFFFFFF) /*!< spim erase operation timeout */
+#define SPIM_PROGRAMMING_TIMEOUT         ((uint32_t)0x00100000) /*!< spim program operation timeout */
+#define OPERATION_TIMEOUT                ((uint32_t)0x10000000) /*!< flash common operation timeout */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_exported_types
+  * @{
+  */
+
+/**
+  * @brief  flash status type
+  */
+typedef enum
+{
+  FLASH_OPERATE_BUSY                     = 0x00, /*!< flash status is operate busy */
+  FLASH_PROGRAM_ERROR                    = 0x01, /*!< flash status is program error */
+  FLASH_EPP_ERROR                        = 0x02, /*!< flash status is epp error */
+  FLASH_OPERATE_DONE                     = 0x03, /*!< flash status is operate done */
+  FLASH_OPERATE_TIMEOUT                  = 0x04  /*!< flash status is operate timeout */
+} flash_status_type;
+
+/**
+  * @brief  flash spim model type
+  */
+typedef enum
+{
+  FLASH_SPIM_MODEL1                      = 0x01, /*!< spim model 1 */
+  FLASH_SPIM_MODEL2                      = 0x02, /*!< spim model 2 */
+} flash_spim_model_type;
+
+/**
+  * @brief type define flash register all
+  */
+typedef struct
+{
+  /**
+    * @brief flash psr register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t psr;
+    struct
+    {
+      __IO uint32_t reserved1            : 32; /* [31:0] */
+    } psr_bit;
+  };
+
+  /**
+    * @brief flash unlock register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t unlock;
+    struct
+    {
+      __IO uint32_t ukval                : 32;/* [31:0] */
+    } unlock_bit;
+  };
+
+  /**
+    * @brief flash usd unlock register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t usd_unlock;
+    struct
+    {
+      __IO uint32_t usd_ukval            : 32;/* [31:0] */
+    } usd_unlock_bit;
+  };
+
+  /**
+    * @brief flash sts register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t sts;
+    struct
+    {
+      __IO uint32_t obf                  : 1; /* [0] */
+      __IO uint32_t reserved1            : 1; /* [1] */
+      __IO uint32_t prgmerr              : 1; /* [2] */
+      __IO uint32_t reserved2            : 1; /* [3] */
+      __IO uint32_t epperr               : 1; /* [4] */
+      __IO uint32_t odf                  : 1; /* [5] */
+      __IO uint32_t reserved3            : 26;/* [31:6] */
+    } sts_bit;
+  };
+
+  /**
+    * @brief flash ctrl register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t ctrl;
+    struct
+    {
+      __IO uint32_t fprgm                : 1; /* [0] */
+      __IO uint32_t secers               : 1; /* [1] */
+      __IO uint32_t bankers              : 1; /* [2] */
+      __IO uint32_t reserved1            : 1; /* [3] */
+      __IO uint32_t usdprgm              : 1; /* [4] */
+      __IO uint32_t usders               : 1; /* [5] */
+      __IO uint32_t erstr                : 1; /* [6] */
+      __IO uint32_t oplk                 : 1; /* [7] */
+      __IO uint32_t reserved2            : 1; /* [8] */
+      __IO uint32_t usdulks              : 1; /* [9] */
+      __IO uint32_t errie                : 1; /* [10] */
+      __IO uint32_t reserved3            : 1; /* [11] */
+      __IO uint32_t odfie                : 1; /* [12] */
+      __IO uint32_t reserved4            : 19;/* [31:13] */
+    } ctrl_bit;
+  };
+
+  /**
+    * @brief flash addr register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t addr;
+    struct
+    {
+      __IO uint32_t fa                   : 32;/* [31:0] */
+    } addr_bit;
+  };
+
+  /**
+    * @brief flash reserved1 register, offset:0x18
+    */
+  __IO uint32_t reserved1;
+
+  /**
+    * @brief flash usd register, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t usd;
+    struct
+    {
+      __IO uint32_t usderr               : 1; /* [0] */
+      __IO uint32_t fap                  : 1; /* [1] */
+      __IO uint32_t wdt_ato_en           : 1; /* [2] */
+      __IO uint32_t depslp_rst           : 1; /* [3] */
+      __IO uint32_t stdby_rst            : 1; /* [4] */
+      __IO uint32_t reserved1            : 5; /* [9:5] */
+      __IO uint32_t user_d0              : 8; /* [17:10] */
+      __IO uint32_t user_d1              : 8; /* [25:18] */
+      __IO uint32_t reserved2            : 6; /* [31:26] */
+    } usd_bit;
+  };
+
+  /**
+    * @brief flash epps register, offset:0x20
+    */
+  union
+  {
+    __IO uint32_t epps;
+    struct
+    {
+      __IO uint32_t epps                 : 32;/* [31:0] */
+    } epps_bit;
+  };
+
+  /**
+    * @brief flash reserved2 register, offset:0x80~0x24
+    */
+  __IO uint32_t reserved2[24];
+
+  /**
+    * @brief flash unlock3 register, offset:0x84
+    */
+  union
+  {
+    __IO uint32_t unlock3;
+    struct
+    {
+      __IO uint32_t ukval                : 32;/* [31:0] */
+    } unlock3_bit;
+  };
+
+  /**
+    * @brief flash select register, offset:0x88
+    */
+  union
+  {
+    __IO uint32_t select;
+    struct
+    {
+      __IO uint32_t select               : 32;/* [31:0] */
+    } select_bit;
+  };
+
+  /**
+    * @brief flash sts3 register, offset:0x8C
+    */
+  union
+  {
+    __IO uint32_t sts3;
+    struct
+    {
+      __IO uint32_t obf                  : 1; /* [0] */
+      __IO uint32_t reserved1            : 1; /* [1] */
+      __IO uint32_t prgmerr              : 1; /* [2] */
+      __IO uint32_t reserved2            : 1; /* [3] */
+      __IO uint32_t epperr               : 1; /* [4] */
+      __IO uint32_t odf                  : 1; /* [5] */
+      __IO uint32_t reserved3            : 26;/* [31:6] */
+    } sts3_bit;
+  };
+
+  /**
+    * @brief flash ctrl3 register, offset:0x90
+    */
+  union
+  {
+    __IO uint32_t ctrl3;
+    struct
+    {
+      __IO uint32_t fprgm                : 1; /* [0] */
+      __IO uint32_t secers               : 1; /* [1] */
+      __IO uint32_t chpers               : 1; /* [2] */
+      __IO uint32_t reserved1            : 3; /* [5:3] */
+      __IO uint32_t erstr                : 1; /* [6] */
+      __IO uint32_t oplk                 : 1; /* [7] */
+      __IO uint32_t reserved2            : 2; /* [9:8] */
+      __IO uint32_t errie                : 1; /* [10] */
+      __IO uint32_t reserved3            : 1; /* [11] */
+      __IO uint32_t odfie                : 1; /* [12] */
+      __IO uint32_t reserved4            : 19;/* [31:13] */
+    } ctrl3_bit;
+  };
+
+  /**
+    * @brief flash addr3 register, offset:0x94
+    */
+  union
+  {
+    __IO uint32_t addr3;
+    struct
+    {
+      __IO uint32_t fa                   : 32;/* [31:0] */
+    } addr3_bit;
+  };
+
+  /**
+    * @brief flash da register, offset:0x98
+    */
+  union
+  {
+    __IO uint32_t da;
+    struct
+    {
+      __IO uint32_t fda                  : 32;/* [31:0] */
+    } da_bit;
+  };
+
+  /**
+    * @brief flash reserved5 register, offset:0xC8~0x9C
+    */
+  __IO uint32_t reserved5[12];
+
+  /**
+    * @brief flash slib_sts0 register, offset:0xCC
+    */
+  union
+  {
+    __IO uint32_t slib_sts0;
+    struct
+    {
+      __IO uint32_t reserved1            : 3; /* [2:0] */
+      __IO uint32_t slib_enf             : 1; /* [3] */
+      __IO uint32_t reserved2            : 28;/* [31:4] */
+    } slib_sts0_bit;
+  };
+
+  /**
+    * @brief flash slib_sts1 register, offset:0xD0
+    */
+  union
+  {
+    __IO uint32_t slib_sts1;
+    struct
+    {
+      __IO uint32_t slib_ss              : 11;/* [10:0] */
+      __IO uint32_t slib_dat_ss          : 11;/* [21:11] */
+      __IO uint32_t slib_es              : 10;/* [31:22] */
+    } slib_sts1_bit;
+  };
+
+  /**
+    * @brief flash slib_pwd_clr register, offset:0xD4
+    */
+  union
+  {
+    __IO uint32_t slib_pwd_clr;
+    struct
+    {
+      __IO uint32_t slib_pclr_val        : 32;/* [31:0] */
+    } slib_pwd_clr_bit;
+  };
+
+  /**
+    * @brief flash slib_misc_sts register, offset:0xD8
+    */
+  union
+  {
+    __IO uint32_t slib_misc_sts;
+    struct
+    {
+      __IO uint32_t slib_pwd_err         : 1; /* [0] */
+      __IO uint32_t slib_pwd_ok          : 1; /* [1] */
+      __IO uint32_t slib_ulkf            : 1; /* [2] */
+      __IO uint32_t reserved1            : 13;/* [15:3] */
+      __IO uint32_t slib_rcnt            : 9; /* [24:16] */
+      __IO uint32_t reserved2            : 7; /* [31:25] */
+    } slib_misc_sts_bit;
+  };
+
+  /**
+    * @brief flash slib_set_pwd register, offset:0xDC
+    */
+  union
+  {
+    __IO uint32_t slib_set_pwd;
+    struct
+    {
+      __IO uint32_t slib_pset_val        : 32;/* [31:0] */
+    } slib_set_pwd_bit;
+  };
+
+  /**
+    * @brief flash slib_set_range register, offset:0xE0
+    */
+  union
+  {
+    __IO uint32_t slib_set_range;
+    struct
+    {
+      __IO uint32_t slib_ss_set          : 11;/* [10:0] */
+      __IO uint32_t slib_dss_set         : 11;/* [21:11] */
+      __IO uint32_t slib_es_set          : 10;/* [31:22] */
+    } slib_set_range_bit;
+  };
+
+  /**
+    * @brief flash reserved6 register, offset:0xEC~0xE4
+    */
+  __IO uint32_t reserved6[3];
+
+  /**
+    * @brief flash slib_unlock register, offset:0xF0
+    */
+  union
+  {
+    __IO uint32_t slib_unlock;
+    struct
+    {
+      __IO uint32_t slib_ukval           : 32;/* [31:0] */
+    } slib_unlock_bit;
+  };
+
+  /**
+    * @brief flash crc_ctrl register, offset:0xF4
+    */
+  union
+  {
+    __IO uint32_t crc_ctrl;
+    struct
+    {
+      __IO uint32_t crc_ss               : 12;/* [11:0] */
+      __IO uint32_t crc_sn               : 12;/* [23:12] */
+      __IO uint32_t reserved1            : 7; /* [30:24] */
+      __IO uint32_t crc_strt             : 1; /* [31] */
+    } crc_ctrl_bit;
+  };
+
+  /**
+    * @brief flash crc_chkr register, offset:0xF8
+    */
+  union
+  {
+    __IO uint32_t crc_chkr;
+    struct
+    {
+      __IO uint32_t crc_chkr             : 32;/* [31:0] */
+    } crc_chkr_bit;
+  };
+
+} flash_type;
+
+/**
+  * @brief user system data
+  */
+typedef struct
+{
+  __IO uint16_t fap;
+  __IO uint16_t ssb;
+  __IO uint16_t data0;
+  __IO uint16_t data1;
+  __IO uint16_t epp0;
+  __IO uint16_t epp1;
+  __IO uint16_t epp2;
+  __IO uint16_t epp3;
+  __IO uint16_t eopb0;
+  __IO uint16_t reserved;
+  __IO uint16_t data2;
+  __IO uint16_t data3;
+  __IO uint16_t data4;
+  __IO uint16_t data5;
+  __IO uint16_t data6;
+  __IO uint16_t data7;
+  __IO uint16_t ext_flash_key[8];
+} usd_type;
+
+/**
+  * @}
+  */
+
+#define FLASH                            ((flash_type *) FLASH_REG_BASE)
+#define USD                              ((usd_type *) USD_BASE)
+
+/** @defgroup FLASH_exported_functions
+  * @{
+  */
+
+flag_status flash_flag_get(uint32_t flash_flag);
+void flash_flag_clear(uint32_t flash_flag);
+flash_status_type flash_operation_status_get(void);
+flash_status_type flash_spim_operation_status_get(void);
+flash_status_type flash_operation_wait_for(uint32_t time_out);
+flash_status_type flash_spim_operation_wait_for(uint32_t time_out);
+void flash_unlock(void);
+void flash_spim_unlock(void);
+void flash_lock(void);
+void flash_spim_lock(void);
+flash_status_type flash_sector_erase(uint32_t sector_address);
+flash_status_type flash_internal_all_erase(void);
+flash_status_type flash_spim_all_erase(void);
+flash_status_type flash_user_system_data_erase(void);
+flash_status_type flash_word_program(uint32_t address, uint32_t data);
+flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
+flash_status_type flash_byte_program(uint32_t address, uint8_t data);
+flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
+flash_status_type flash_epp_set(uint32_t *sector_bits);
+void flash_epp_status_get(uint32_t *sector_bits);
+flash_status_type flash_fap_enable(confirm_state new_state);
+flag_status flash_fap_status_get(void);
+flash_status_type flash_ssb_set(uint8_t usd_ssb);
+uint8_t flash_ssb_status_get(void);
+void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
+void flash_spim_model_select(flash_spim_model_type mode);
+void flash_spim_encryption_range_set(uint32_t decode_address);
+flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector);
+error_status flash_slib_disable(uint32_t pwd);
+uint32_t flash_slib_remaining_count_get(void);
+flag_status flash_slib_state_get(void);
+uint16_t flash_slib_start_sector_get(void);
+uint16_t flash_slib_datastart_sector_get(void);
+uint16_t flash_slib_end_sector_get(void);
+uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_gpio.h

@@ -0,0 +1,791 @@
+/**
+  **************************************************************************
+  * @file     at32f413_gpio.h
+  * @brief    at32f413 gpio header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_GPIO_H
+#define __AT32F413_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/** @defgroup GPIO_pins_number_definition
+  * @{
+  */
+
+#define GPIO_PINS_0                      0x0001 /*!< gpio pins number 0 */
+#define GPIO_PINS_1                      0x0002 /*!< gpio pins number 1 */
+#define GPIO_PINS_2                      0x0004 /*!< gpio pins number 2 */
+#define GPIO_PINS_3                      0x0008 /*!< gpio pins number 3 */
+#define GPIO_PINS_4                      0x0010 /*!< gpio pins number 4 */
+#define GPIO_PINS_5                      0x0020 /*!< gpio pins number 5 */
+#define GPIO_PINS_6                      0x0040 /*!< gpio pins number 6 */
+#define GPIO_PINS_7                      0x0080 /*!< gpio pins number 7 */
+#define GPIO_PINS_8                      0x0100 /*!< gpio pins number 8 */
+#define GPIO_PINS_9                      0x0200 /*!< gpio pins number 9 */
+#define GPIO_PINS_10                     0x0400 /*!< gpio pins number 10 */
+#define GPIO_PINS_11                     0x0800 /*!< gpio pins number 11 */
+#define GPIO_PINS_12                     0x1000 /*!< gpio pins number 12 */
+#define GPIO_PINS_13                     0x2000 /*!< gpio pins number 13 */
+#define GPIO_PINS_14                     0x4000 /*!< gpio pins number 14 */
+#define GPIO_PINS_15                     0x8000 /*!< gpio pins number 15 */
+#define GPIO_PINS_ALL                    0xFFFF /*!< gpio all pins */
+
+/**
+  * @}
+  */
+
+#define IOMUX_MAKE_VALUE(reg_offset, bit_addr ,bit_num, bit_val) \
+        (uint32_t)(((reg_offset) << 24) | ((bit_addr) << 16) | ((bit_num) << 8) | (bit_val))
+
+/** @defgroup IOMUX_map_definition
+  * @brief iomux map definitions
+  * @{
+  */
+
+#define SPI1_MUX_01                      SPI1_GMUX_0001    /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb0) */
+#define I2C1_MUX                         I2C1_GMUX_0001    /*!< i2c1_scl(pb8),      i2c1_sda(pb9) */
+#define USART1_MUX                       USART1_GMUX_0001  /*!< usart1_tx(pb6),     usart1_rx(pb7) */
+#define USART3_MUX_01                    USART3_GMUX_0001  /*!< usart3_tx(pc10),    usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
+#define TMR1_MUX_01                      TMR1_GMUX_0001    /*!< tmr1_ext(pa12),     tmr1_ch1(pa8),   tmr1_ch2(pa9),   tmr1_ch3(pa10),   tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
+#define TMR2_MUX_01                      TMR2_GMUX_001     /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3),   tmr2_ch3(pa2),   tmr2_ch4(pa3) */
+#define TMR2_MUX_10                      TMR2_GMUX_010     /*!< tmr2_ch1_ext(pa0),  tmr2_ch2(pa1),   tmr2_ch3(pb10),  tmr2_ch4(pb11) */
+#define TMR2_MUX_11                      TMR2_GMUX_011     /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3),   tmr2_ch3(pb10),  tmr2_ch4(pb11) */
+#define TMR3_MUX_10                      TMR3_GMUX_0010    /*!< tmr3_ch1(pb4),      tmr3_ch2(pb5),   tmr3_ch3(pb0),   tmr3_ch4(pb1) */
+#define TMR3_MUX_11                      TMR3_GMUX_0011    /*!< tmr3_ch1(pc6),      tmr3_ch2(pc7),   tmr3_ch3(pc8),   tmr3_ch4(pc9) */
+#define CAN_MUX_10                       CAN1_GMUX_0010    /*!< can_rx(pb8),        can_tx(pb9) */
+#define PD01_MUX                         PD01_GMUX         /*!< pd0/pd1 mapping on osc_in/osc_out */
+#define TMR5CH4_MUX                      TMR5CH4_GMUX      /*!< lick connected to tmr5_ch4 input capture for calibration */
+#define ADC1_ETP_MUX                     ADC1_ETP_GMUX     /*!< adc1 external trigger preempted conversion muxing */
+#define ADC1_ETO_MUX                     ADC1_ETO_GMUX     /*!< adc1 external trigger ordinary conversion muxing */
+#define ADC2_ETP_MUX                     ADC2_ETP_GMUX     /*!< adc2 external trigger preempted conversion muxing */
+#define ADC2_ETO_MUX                     ADC2_ETO_GMUX     /*!< adc2 external trigger ordinary conversion muxing */
+#define SWJTAG_CONF_001                  SWJTAG_GMUX_001   /*!< full swj enabled  (jtag-dp  +  sw-dp)  but without jtrst */
+#define SWJTAG_CONF_010                  SWJTAG_GMUX_010   /*!< jtag-dp disabled and sw-dp enabled */
+#define SWJTAG_CONF_100                  SWJTAG_GMUX_100   /*!< full swj disabled  (jtag-dp  +  sw-dp) */
+
+/**
+  * @}
+  */
+
+/** @defgroup IOMUX_map2_definition
+  * @brief iomux map2 definitions
+  * @{
+  */
+
+#define EXT_SPIM_EN_MUX                  EXT_SPIM_GMUX_1000 /*!< enable external spi-flash interface */
+
+/**
+  * @}
+  */
+
+/** @defgroup IOMUX_map3_definition
+  * @brief iomux map3 definitions
+  * @{
+  */
+
+#define TMR9_GMUX                        IOMUX_MAKE_VALUE(0x20, 0, 4, 0x02) /*!< tmr9_ch1(pb14),  tmr9_ch2(pb15) */
+#define TMR10_GMUX                       IOMUX_MAKE_VALUE(0x20, 4, 4, 0x02) /*!< tmr10_ch1(pa6) */
+#define TMR11_GMUX                       IOMUX_MAKE_VALUE(0x20, 8, 4, 0x02) /*!< tmr11_ch1(pa7) */
+
+/**
+  * @}
+  */
+
+/** @defgroup IOMUX_map4_definition
+  * @brief iomux map4 definitions
+  * @{
+  */
+
+#define TMR1_GMUX_0001                   IOMUX_MAKE_VALUE(0x24, 0, 4, 0x01)  /*!< tmr1_ext(pa12), tmr1_ch1(pa8), tmr1_ch2(pa9), tmr1_ch3(pa10), tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
+#define TMR2_GMUX_001                    IOMUX_MAKE_VALUE(0x24, 4, 3, 0x01)  /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pa2),  tmr2_ch4(pa3) */
+#define TMR2_GMUX_010                    IOMUX_MAKE_VALUE(0x24, 4, 3, 0x02)  /*!< tmr2_ch1_ext(pa0),  tmr2_ch2(pa1), tmr2_ch3(pb10), tmr2_ch4(pb11) */
+#define TMR2_GMUX_011                    IOMUX_MAKE_VALUE(0x24, 4, 3, 0x03)  /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pb10), tmr2_ch4(pb11) */
+#define TMR2ITR1_GMUX                    IOMUX_MAKE_VALUE(0x24, 7, 1, 0x01)  /*!< usbdev sof as input to tmr2_int.1 */
+#define TMR3_GMUX_0010                   IOMUX_MAKE_VALUE(0x24, 8, 4, 0x02)  /*!< tmr3_ch1(pb4),  tmr3_ch2(pb5),  tmr3_ch3(pb0),  tmr3_ch4(pb1) */
+#define TMR3_GMUX_0011                   IOMUX_MAKE_VALUE(0x24, 8, 4, 0x03)  /*!< tmr3_ch1(pc6),  tmr3_ch2(pc7),  tmr3_ch3(pc8),  tmr3_ch4(pc9) */
+#define TMR5_GMUX_001                    IOMUX_MAKE_VALUE(0x24, 16, 3, 0x01) /*!< tmr5_ch1(pf4),  tmr5_ch2(pf5) */
+#define TMR5CH4_GMUX                     IOMUX_MAKE_VALUE(0x24, 19, 1, 0x01) /*!< lick connected to tmr5_ch4 input capture for calibration */
+
+/**
+  * @}
+  */
+
+/** @defgroup IOMUX_map5_definition
+  * @brief iomux map5 definitions
+  * @{
+  */
+
+#define I2C1_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 4, 4, 0x01)  /*!< i2c1_scl(pb8), i2c1_sda(pb9) */
+#define I2C1_GMUX_0011                   IOMUX_MAKE_VALUE(0x28, 4, 4, 0x03)  /*!< i2c1_scl(pf6), i2c1_sda(pf7) */
+#define I2C2_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 8, 4, 0x01)  /*!< i2c2_scl(pf6), i2c2_sda(pf7) */
+#define I2C2_GMUX_0010                   IOMUX_MAKE_VALUE(0x28, 8, 4, 0x01)  /*!< i2c2_scl(pa8), i2c2_sda(pc9) */
+#define I2C2_GMUX_0011                   IOMUX_MAKE_VALUE(0x28, 8, 4, 0x01)  /*!< i2c2_scl(pa8), i2c2_sda(pb4) */
+#define SPI1_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 16, 4, 0x01) /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
+#define SPI2_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 20, 4, 0x01) /*!< spi2_cs/i2s2_ws(pa15), spi2_sck/i2s2_ck(pb3), spi2_miso(pb4), spi2_mosi/i2s2_sd(pb5), i2s2_mck(pc7) */
+
+/**
+  * @}
+  */
+
+/** @defgroup IOMUX_map6_definition
+  * @brief iomux map6 definitions
+  * @{
+  */
+
+#define CAN1_GMUX_0010                   IOMUX_MAKE_VALUE(0x2C, 0, 4, 0x02)  /*!< can_rx(pb8),   can_tx(pb9) */
+#define CAN2_GMUX_0001                   IOMUX_MAKE_VALUE(0x2C, 4, 4, 0x01)  /*!< can2_rx(pb5),  can2_tx(pb6) */
+#define SDIO1_GMUX_0100                  IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x04)  /*!< sdio1_ck(pc4), sdio1_cmd(pc5), sdio1_d0(pc0), sdio1_d1(pc1), sdio1_d2(pc2), sdio1_d3(pc3), sdio1_d4(pa4), sdio1_d5(pa5), sdio1_d6(pa6), sdio1_d7(pa7) */
+#define SDIO1_GMUX_0101                  IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x05)  /*!< sdio1_ck(pc4), sdio1_cmd(pc5), sdio1_d0(pa4), sdio1_d1(pa5), sdio1_d2(pa6), sdio1_d3(pa7) */
+#define SDIO1_GMUX_0110                  IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x06)  /*!< sdio1_ck(pa2), sdio1_cmd(pa3), sdio1_d0(pc0), sdio1_d1(pc1), sdio1_d2(pc2), sdio1_d3(pc3), sdio1_d4(pa4), sdio1_d5(pa5), sdio1_d6(pa6), sdio1_d7(pa7) */
+#define SDIO1_GMUX_0111                  IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x07)  /*!< sdio1_ck(pa2), sdio1_cmd(pa3), sdio1_d0(pa4), sdio1_d1(pa5), sdio1_d2(pa6), sdio1_d3(pa7) */
+#define USART1_GMUX_0001                 IOMUX_MAKE_VALUE(0x2C, 16, 4, 0x01) /*!< usart1_tx(pb6),  usart1_rx(pb7) */
+#define USART3_GMUX_0001                 IOMUX_MAKE_VALUE(0x2C, 24, 4, 0x01) /*!< usart3_tx(pc10), usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
+#define UART4_GMUX_0001                  IOMUX_MAKE_VALUE(0x2C, 28, 4, 0x01) /*!< uart4_tx(pf4),   uart4_rx(pf5) */
+
+/**
+  * @}
+  */
+
+/** @defgroup IOMUX_map7_definition
+  * @brief iomux map7 definitions
+  * @{
+  */
+
+#define EXT_SPIM_GMUX_1000               IOMUX_MAKE_VALUE(0x30, 0, 4, 0x08)  /*!< spim_sck(pb1), spim_cs(pa8), spim_io0(pa11), spim_io1(pa12), spim_io2(pb7), spim_sio3(pb6) */
+#define EXT_SPIM_GMUX_1001               IOMUX_MAKE_VALUE(0x30, 0, 4, 0x09)  /*!< spim_sck(pb1), spim_cs(pa8), spim_io0(pb10), spim_io1(pb11), spim_io2(pb7), spim_sio3(pb6) */
+#define ADC1_ETP_GMUX                    IOMUX_MAKE_VALUE(0x30, 4, 1, 0x01)  /*!< adc1 external trigger preempted conversion muxing */
+#define ADC1_ETO_GMUX                    IOMUX_MAKE_VALUE(0x30, 5, 1, 0x01)  /*!< adc1 external trigger ordinary conversion muxing */
+#define ADC2_ETP_GMUX                    IOMUX_MAKE_VALUE(0x30, 8, 1, 0x01)  /*!< adc2 external trigger preempted conversion muxing */
+#define ADC2_ETO_GMUX                    IOMUX_MAKE_VALUE(0x30, 9, 1, 0x01)  /*!< adc2 external trigger ordinary conversion muxing */
+#define SWJTAG_GMUX_001                  IOMUX_MAKE_VALUE(0x30, 16, 3, 0x01) /*!< full swj enabled  (jtag-dp  +  sw-dp)  but without jtrst */
+#define SWJTAG_GMUX_010                  IOMUX_MAKE_VALUE(0x30, 16, 3, 0x02) /*!< jtag-dp disabled and sw-dp enabled */
+#define SWJTAG_GMUX_100                  IOMUX_MAKE_VALUE(0x30, 16, 3, 0x04) /*!< full swj disabled  (jtag-dp  +  sw-dp) */
+#define PD01_GMUX                        IOMUX_MAKE_VALUE(0x30, 20, 1, 0x01) /*!< pd0/pd1 mapping on osc_in/osc_out */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_exported_types
+  * @{
+  */
+
+/**
+  * @brief gpio mode select
+  */
+typedef enum
+{
+  GPIO_MODE_INPUT                        = 0x00, /*!< gpio input mode */
+  GPIO_MODE_OUTPUT                       = 0x10, /*!< gpio output mode */
+  GPIO_MODE_MUX                          = 0x08, /*!< gpio mux function mode */
+  GPIO_MODE_ANALOG                       = 0x03  /*!< gpio analog in/out mode */
+} gpio_mode_type;
+
+/**
+  * @brief gpio output drive strength select
+  */
+typedef enum
+{
+  GPIO_DRIVE_STRENGTH_STRONGER           = 0x01, /*!< stronger sourcing/sinking strength */
+  GPIO_DRIVE_STRENGTH_MODERATE           = 0x02, /*!< moderate sourcing/sinking strength */
+  GPIO_DRIVE_STRENGTH_MAXIMUM            = 0x03  /*!< maximum sourcing/sinking strength */
+} gpio_drive_type;
+
+/**
+  * @brief gpio output type
+  */
+typedef enum
+{
+  GPIO_OUTPUT_PUSH_PULL                  = 0x00, /*!< output push-pull */
+  GPIO_OUTPUT_OPEN_DRAIN                 = 0x04  /*!< output open-drain */
+} gpio_output_type;
+
+/**
+  * @brief gpio pull type
+  */
+typedef enum
+{
+  GPIO_PULL_NONE                         = 0x0004, /*!< floating for input, no pull for output */
+  GPIO_PULL_UP                           = 0x0018, /*!< pull-up */
+  GPIO_PULL_DOWN                         = 0x0028  /*!< pull-down */
+} gpio_pull_type;
+
+/**
+  * @brief gpio pins source type
+  */
+typedef enum
+{
+  GPIO_PINS_SOURCE0                      = 0x00, /*!< gpio pins source number 0 */
+  GPIO_PINS_SOURCE1                      = 0x01, /*!< gpio pins source number 1 */
+  GPIO_PINS_SOURCE2                      = 0x02, /*!< gpio pins source number 2 */
+  GPIO_PINS_SOURCE3                      = 0x03, /*!< gpio pins source number 3 */
+  GPIO_PINS_SOURCE4                      = 0x04, /*!< gpio pins source number 4 */
+  GPIO_PINS_SOURCE5                      = 0x05, /*!< gpio pins source number 5 */
+  GPIO_PINS_SOURCE6                      = 0x06, /*!< gpio pins source number 6 */
+  GPIO_PINS_SOURCE7                      = 0x07, /*!< gpio pins source number 7 */
+  GPIO_PINS_SOURCE8                      = 0x08, /*!< gpio pins source number 8 */
+  GPIO_PINS_SOURCE9                      = 0x09, /*!< gpio pins source number 9 */
+  GPIO_PINS_SOURCE10                     = 0x0A, /*!< gpio pins source number 10 */
+  GPIO_PINS_SOURCE11                     = 0x0B, /*!< gpio pins source number 11 */
+  GPIO_PINS_SOURCE12                     = 0x0C, /*!< gpio pins source number 12 */
+  GPIO_PINS_SOURCE13                     = 0x0D, /*!< gpio pins source number 13 */
+  GPIO_PINS_SOURCE14                     = 0x0E, /*!< gpio pins source number 14 */
+  GPIO_PINS_SOURCE15                     = 0x0F  /*!< gpio pins source number 15 */
+} gpio_pins_source_type;
+
+/**
+  * @brief gpio port source type
+  */
+typedef enum
+{
+  GPIO_PORT_SOURCE_GPIOA                 = 0x00, /*!< gpio port source gpioa */
+  GPIO_PORT_SOURCE_GPIOB                 = 0x01, /*!< gpio port source gpiob */
+  GPIO_PORT_SOURCE_GPIOC                 = 0x02, /*!< gpio port source gpioc */
+  GPIO_PORT_SOURCE_GPIOD                 = 0x03, /*!< gpio port source gpiod */
+  GPIO_PORT_SOURCE_GPIOF                 = 0x05, /*!< gpio port source gpiof */
+} gpio_port_source_type;
+
+/**
+  * @brief gpio init type
+  */
+typedef struct
+{
+  uint32_t                               gpio_pins;           /*!< pins number selection */
+  gpio_output_type                       gpio_out_type;       /*!< output type selection */
+  gpio_pull_type                         gpio_pull;           /*!< pull type selection */
+  gpio_mode_type                         gpio_mode;           /*!< mode selection */
+  gpio_drive_type                        gpio_drive_strength; /*!< drive strength selection */
+} gpio_init_type;
+
+/**
+  * @brief type define gpio register all
+  */
+typedef struct
+{
+  /**
+    * @brief gpio cfglr register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t cfglr;
+    struct
+    {
+      __IO uint32_t iomc0                : 2; /* [1:0] */
+      __IO uint32_t iofc0                : 2; /* [3:2] */
+      __IO uint32_t iomc1                : 2; /* [5:4] */
+      __IO uint32_t iofc1                : 2; /* [7:6] */
+      __IO uint32_t iomc2                : 2; /* [9:8] */
+      __IO uint32_t iofc2                : 2; /* [11:10] */
+      __IO uint32_t iomc3                : 2; /* [13:12] */
+      __IO uint32_t iofc3                : 2; /* [15:14] */
+      __IO uint32_t iomc4                : 2; /* [17:16] */
+      __IO uint32_t iofc4                : 2; /* [19:18] */
+      __IO uint32_t iomc5                : 2; /* [21:20] */
+      __IO uint32_t iofc5                : 2; /* [23:22] */
+      __IO uint32_t iomc6                : 2; /* [25:24] */
+      __IO uint32_t iofc6                : 2; /* [27:26] */
+      __IO uint32_t iomc7                : 2; /* [29:28] */
+      __IO uint32_t iofc7                : 2; /* [31:30] */
+    } cfglr_bit;
+  };
+
+  /**
+    * @brief gpio cfghr register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t cfghr;
+    struct
+    {
+      __IO uint32_t iomc8                : 2; /* [1:0] */
+      __IO uint32_t iofc8                : 2; /* [3:2] */
+      __IO uint32_t iomc9                : 2; /* [5:4] */
+      __IO uint32_t iofc9                : 2; /* [7:6] */
+      __IO uint32_t iomc10               : 2; /* [9:8] */
+      __IO uint32_t iofc10               : 2; /* [11:10] */
+      __IO uint32_t iomc11               : 2; /* [13:12] */
+      __IO uint32_t iofc11               : 2; /* [15:14] */
+      __IO uint32_t iomc12               : 2; /* [17:16] */
+      __IO uint32_t iofc12               : 2; /* [19:18] */
+      __IO uint32_t iomc13               : 2; /* [21:20] */
+      __IO uint32_t iofc13               : 2; /* [23:22] */
+      __IO uint32_t iomc14               : 2; /* [25:24] */
+      __IO uint32_t iofc14               : 2; /* [27:26] */
+      __IO uint32_t iomc15               : 2; /* [29:28] */
+      __IO uint32_t iofc15               : 2; /* [31:30] */
+    } cfghr_bit;
+  };
+
+  /**
+    * @brief gpio idt register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t idt;
+    struct
+    {
+      __IO uint32_t idt0                 : 1; /* [0] */
+      __IO uint32_t idt1                 : 1; /* [1] */
+      __IO uint32_t idt2                 : 1; /* [2] */
+      __IO uint32_t idt3                 : 1; /* [3] */
+      __IO uint32_t idt4                 : 1; /* [4] */
+      __IO uint32_t idt5                 : 1; /* [5] */
+      __IO uint32_t idt6                 : 1; /* [6] */
+      __IO uint32_t idt7                 : 1; /* [7] */
+      __IO uint32_t idt8                 : 1; /* [8] */
+      __IO uint32_t idt9                 : 1; /* [9] */
+      __IO uint32_t idt10                : 1; /* [10] */
+      __IO uint32_t idt11                : 1; /* [11] */
+      __IO uint32_t idt12                : 1; /* [12] */
+      __IO uint32_t idt13                : 1; /* [13] */
+      __IO uint32_t idt14                : 1; /* [14] */
+      __IO uint32_t idt15                : 1; /* [15] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } idt_bit;
+  };
+
+  /**
+    * @brief gpio odt register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t odt;
+    struct
+    {
+      __IO uint32_t odt0                 : 1; /* [0] */
+      __IO uint32_t odt1                 : 1; /* [1] */
+      __IO uint32_t odt2                 : 1; /* [2] */
+      __IO uint32_t odt3                 : 1; /* [3] */
+      __IO uint32_t odt4                 : 1; /* [4] */
+      __IO uint32_t odt5                 : 1; /* [5] */
+      __IO uint32_t odt6                 : 1; /* [6] */
+      __IO uint32_t odt7                 : 1; /* [7] */
+      __IO uint32_t odt8                 : 1; /* [8] */
+      __IO uint32_t odt9                 : 1; /* [9] */
+      __IO uint32_t odt10                : 1; /* [10] */
+      __IO uint32_t odt11                : 1; /* [11] */
+      __IO uint32_t odt12                : 1; /* [12] */
+      __IO uint32_t odt13                : 1; /* [13] */
+      __IO uint32_t odt14                : 1; /* [14] */
+      __IO uint32_t odt15                : 1; /* [15] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } odt_bit;
+  };
+
+  /**
+    * @brief gpio scr register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t scr;
+    struct
+    {
+      __IO uint32_t iosb0                : 1; /* [0] */
+      __IO uint32_t iosb1                : 1; /* [1] */
+      __IO uint32_t iosb2                : 1; /* [2] */
+      __IO uint32_t iosb3                : 1; /* [3] */
+      __IO uint32_t iosb4                : 1; /* [4] */
+      __IO uint32_t iosb5                : 1; /* [5] */
+      __IO uint32_t iosb6                : 1; /* [6] */
+      __IO uint32_t iosb7                : 1; /* [7] */
+      __IO uint32_t iosb8                : 1; /* [8] */
+      __IO uint32_t iosb9                : 1; /* [9] */
+      __IO uint32_t iosb10               : 1; /* [10] */
+      __IO uint32_t iosb11               : 1; /* [11] */
+      __IO uint32_t iosb12               : 1; /* [12] */
+      __IO uint32_t iosb13               : 1; /* [13] */
+      __IO uint32_t iosb14               : 1; /* [14] */
+      __IO uint32_t iosb15               : 1; /* [15] */
+      __IO uint32_t iocb0                : 1; /* [16] */
+      __IO uint32_t iocb1                : 1; /* [17] */
+      __IO uint32_t iocb2                : 1; /* [18] */
+      __IO uint32_t iocb3                : 1; /* [19] */
+      __IO uint32_t iocb4                : 1; /* [20] */
+      __IO uint32_t iocb5                : 1; /* [21] */
+      __IO uint32_t iocb6                : 1; /* [22] */
+      __IO uint32_t iocb7                : 1; /* [23] */
+      __IO uint32_t iocb8                : 1; /* [24] */
+      __IO uint32_t iocb9                : 1; /* [25] */
+      __IO uint32_t iocb10               : 1; /* [26] */
+      __IO uint32_t iocb11               : 1; /* [27] */
+      __IO uint32_t iocb12               : 1; /* [28] */
+      __IO uint32_t iocb13               : 1; /* [29] */
+      __IO uint32_t iocb14               : 1; /* [30] */
+      __IO uint32_t iocb15               : 1; /* [31] */
+    } scr_bit;
+  };
+
+  /**
+    * @brief gpio clr register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t clr;
+    struct
+    {
+      __IO uint32_t iocb0                : 1; /* [0] */
+      __IO uint32_t iocb1                : 1; /* [1] */
+      __IO uint32_t iocb2                : 1; /* [2] */
+      __IO uint32_t iocb3                : 1; /* [3] */
+      __IO uint32_t iocb4                : 1; /* [4] */
+      __IO uint32_t iocb5                : 1; /* [5] */
+      __IO uint32_t iocb6                : 1; /* [6] */
+      __IO uint32_t iocb7                : 1; /* [7] */
+      __IO uint32_t iocb8                : 1; /* [8] */
+      __IO uint32_t iocb9                : 1; /* [9] */
+      __IO uint32_t iocb10               : 1; /* [10] */
+      __IO uint32_t iocb11               : 1; /* [11] */
+      __IO uint32_t iocb12               : 1; /* [12] */
+      __IO uint32_t iocb13               : 1; /* [13] */
+      __IO uint32_t iocb14               : 1; /* [14] */
+      __IO uint32_t iocb15               : 1; /* [15] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } clr_bit;
+  };
+
+  /**
+    * @brief gpio wpr register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t wpr;
+    struct
+    {
+      __IO uint32_t wpen0                : 1; /* [0] */
+      __IO uint32_t wpen1                : 1; /* [1] */
+      __IO uint32_t wpen2                : 1; /* [2] */
+      __IO uint32_t wpen3                : 1; /* [3] */
+      __IO uint32_t wpen4                : 1; /* [4] */
+      __IO uint32_t wpen5                : 1; /* [5] */
+      __IO uint32_t wpen6                : 1; /* [6] */
+      __IO uint32_t wpen7                : 1; /* [7] */
+      __IO uint32_t wpen8                : 1; /* [8] */
+      __IO uint32_t wpen9                : 1; /* [9] */
+      __IO uint32_t wpen10               : 1; /* [10] */
+      __IO uint32_t wpen11               : 1; /* [11] */
+      __IO uint32_t wpen12               : 1; /* [12] */
+      __IO uint32_t wpen13               : 1; /* [13] */
+      __IO uint32_t wpen14               : 1; /* [14] */
+      __IO uint32_t wpen15               : 1; /* [15] */
+      __IO uint32_t wpseq                : 1; /* [16] */
+      __IO uint32_t reserved1            : 15;/* [31:17] */
+    } wpr_bit;
+  };
+
+} gpio_type;
+
+/**
+  * @brief type define iomux register all
+  */
+typedef struct
+{
+  /**
+    * @brief mux event control register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t evtout;
+    struct
+    {
+      __IO uint32_t selpin               : 4; /* [3:0] */
+      __IO uint32_t selport              : 3; /* [6:4] */
+      __IO uint32_t evoen                : 1; /* [7]   */
+      __IO uint32_t reserved1            : 24;/* [31:8] */
+    } evtout_bit;
+  };
+
+  /**
+    * @brief iomux remap register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t remap;
+    struct
+    {
+      __IO uint32_t spi1_mux_l           : 1; /* [0] */
+      __IO uint32_t i2c1_mux             : 1; /* [1] */
+      __IO uint32_t usart1_mux           : 1; /* [2] */
+      __IO uint32_t reserved1            : 1; /* [3] */
+      __IO uint32_t usart3_mux           : 2; /* [5:4] */
+      __IO uint32_t tmr1_mux             : 2; /* [7:6] */
+      __IO uint32_t tmr2_mux             : 2; /* [9:8] */
+      __IO uint32_t tmr3_mux             : 2; /* [11:10] */
+      __IO uint32_t reserved2            : 1; /* [12] */
+      __IO uint32_t can_mux              : 2; /* [14:13] */
+      __IO uint32_t pd01_mux             : 1; /* [15] */
+      __IO uint32_t tmr5ch4_mux          : 1; /* [16] */
+      __IO uint32_t adc1_extrgpre_mux    : 1; /* [17] */
+      __IO uint32_t adc1_extrgord_mux    : 1; /* [18] */
+      __IO uint32_t adc2_extrgpre_mux    : 1; /* [19] */
+      __IO uint32_t adc2_extrgord_mux    : 1; /* [20] */
+      __IO uint32_t reserved3            : 3; /* [23:21] */
+      __IO uint32_t swjtag_conf          : 3; /* [26:24] */
+      __IO uint32_t reserved4            : 4; /* [30:27] */
+      __IO uint32_t spi1_mux_h           : 1; /* [31] */
+    } remap_bit;
+  };
+
+  /**
+    * @brief mux external interrupt configuration register 1, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t exintc1;
+    struct
+    {
+      __IO uint32_t exint0              : 4; /* [3:0] */
+      __IO uint32_t exint1              : 4; /* [7:4] */
+      __IO uint32_t exint2              : 4; /* [11:8] */
+      __IO uint32_t exint3              : 4; /* [15:12] */
+      __IO uint32_t reserved1           : 16;/* [31:16] */
+    } exintc1_bit;
+  };
+
+  /**
+    * @brief mux external interrupt configuration register 2, offset:0x0c
+    */
+  union
+  {
+    __IO uint32_t exintc2;
+    struct
+    {
+      __IO uint32_t exint4              : 4; /* [3:0] */
+      __IO uint32_t exint5              : 4; /* [7:4] */
+      __IO uint32_t exint6              : 4; /* [11:8] */
+      __IO uint32_t exint7              : 4; /* [15:12] */
+      __IO uint32_t reserved1           : 16;/* [31:16] */
+    } exintc2_bit;
+  };
+
+  /**
+    * @brief mux external interrupt configuration register 3, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t exintc3;
+    struct
+    {
+      __IO uint32_t exint8              : 4; /* [3:0] */
+      __IO uint32_t exint9              : 4; /* [7:4] */
+      __IO uint32_t exint10             : 4; /* [11:8] */
+      __IO uint32_t exint11             : 4; /* [15:12] */
+      __IO uint32_t reserved1           : 16;/* [31:16] */
+    } exintc3_bit;
+  };
+
+  /**
+    * @brief mux external interrupt configuration register 4, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t exintc4;
+    struct
+    {
+      __IO uint32_t exint12             : 4; /* [3:0] */
+      __IO uint32_t exint13             : 4; /* [7:4] */
+      __IO uint32_t exint14             : 4; /* [11:8] */
+      __IO uint32_t exint15             : 4; /* [15:12] */
+      __IO uint32_t reserved1           : 16;/* [31:16] */
+    } exintc4_bit;
+  };
+
+  /**
+    * @brief iomux reserved1 register, offset:0x18
+    */
+  __IO uint32_t reserved1;
+
+  /**
+    * @brief iomux remap register 2, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t remap2;
+    struct
+    {
+      __IO uint32_t reserved1            : 21;/* [20:0] */
+      __IO uint32_t ext_spim_en_mux      : 1; /* [21] */
+      __IO uint32_t reserved2            : 10;/* [31:22] */
+    } remap2_bit;
+  };
+
+  /**
+    * @brief iomux remap register 3, offset:0x20
+    */
+  union
+  {
+    __IO uint32_t remap3;
+    struct
+    {
+      __IO uint32_t tmr9_gmux            : 4; /* [3:0] */
+      __IO uint32_t tmr10_gmux           : 4; /* [7:4] */
+      __IO uint32_t tmr11_gmux           : 4; /* [11:8] */
+      __IO uint32_t reserved1            : 20;/* [31:12] */
+    } remap3_bit;
+  };
+
+  /**
+    * @brief iomux remap register 4, offset:0x24
+    */
+  union
+  {
+    __IO uint32_t remap4;
+    struct
+    {
+      __IO uint32_t tmr1_gmux            : 4; /* [3:0] */
+      __IO uint32_t tmr2_gmux            : 3; /* [6:4] */
+      __IO uint32_t tmr2itr1_gmux        : 1; /* [7] */
+      __IO uint32_t tmr3_gmux            : 4; /* [11:8] */
+      __IO uint32_t reserved1            : 4; /* [15:12] */
+      __IO uint32_t tmr5_gmux            : 3; /* [18:16] */
+      __IO uint32_t tmr5ch4_gmux         : 1; /* [19] */
+      __IO uint32_t reserved2            : 12;/* [31:20] */
+    } remap4_bit;
+  };
+
+  /**
+    * @brief iomux remap register 5, offset:0x28
+    */
+  union
+  {
+    __IO uint32_t remap5;
+    struct
+    {
+      __IO uint32_t reserved1            : 4; /* [3:0] */
+      __IO uint32_t i2c1_gmux            : 4; /* [7:4] */
+      __IO uint32_t i2c2_gmux            : 4; /* [11:8] */
+      __IO uint32_t reserved2            : 4; /* [15:12] */
+      __IO uint32_t spi1_gmux            : 4; /* [19:16] */
+      __IO uint32_t spi2_gmux            : 4; /* [23:20] */
+      __IO uint32_t reserved3            : 8; /* [31:24] */
+    } remap5_bit;
+  };
+
+  /**
+    * @brief iomux remap register 6, offset:0x2C
+    */
+  union
+  {
+    __IO uint32_t remap6;
+    struct
+    {
+      __IO uint32_t can1_gmux            : 4; /* [3:0] */
+      __IO uint32_t can2_gmux            : 4; /* [7:4] */
+      __IO uint32_t sdio1_gmux           : 4; /* [11:8] */
+      __IO uint32_t reserved1            : 4; /* [15:12] */
+      __IO uint32_t usart1_gmux          : 4; /* [19:16] */
+      __IO uint32_t reserved2            : 4; /* [23:20] */
+      __IO uint32_t usart3_gmux          : 4; /* [27:24] */
+      __IO uint32_t uart4_gmux           : 4; /* [31:28] */
+    } remap6_bit;
+  };
+
+  /**
+    * @brief iomux remap register 7, offset:0x30
+    */
+  union
+  {
+    __IO uint32_t remap7;
+    struct
+    {
+      __IO uint32_t ext_spim_gmux        : 3; /* [2:0] */
+      __IO uint32_t ext_spim_gen         : 1; /* [3] */
+      __IO uint32_t adc1_etp_gmux        : 1; /* [4] */
+      __IO uint32_t adc1_eto_gmux        : 1; /* [5] */
+      __IO uint32_t reserved1            : 2; /* [7:6] */
+      __IO uint32_t adc2_etp_gmux        : 1; /* [8] */
+      __IO uint32_t adc2_eto_gmux        : 1; /* [9] */
+      __IO uint32_t reserved2            : 6; /* [15:10] */
+      __IO uint32_t swjtag_gmux          : 3; /* [18:16] */
+      __IO uint32_t reserved3            : 1; /* [19] */
+      __IO uint32_t pd01_gmux            : 1; /* [20] */
+      __IO uint32_t reserved4            : 11;/* [31:21] */
+
+    } remap7_bit;
+  };
+
+} iomux_type;
+
+/**
+  * @}
+  */
+
+#define GPIOA                            ((gpio_type *) GPIOA_BASE)
+#define GPIOB                            ((gpio_type *) GPIOB_BASE)
+#define GPIOC                            ((gpio_type *) GPIOC_BASE)
+#define GPIOD                            ((gpio_type *) GPIOD_BASE)
+#define GPIOF                            ((gpio_type *) GPIOF_BASE)
+#define IOMUX                            ((iomux_type *) IOMUX_BASE)
+
+/** @defgroup GPIO_exported_functions
+  * @{
+  */
+
+void gpio_reset(gpio_type *gpio_x);
+void gpio_iomux_reset(void);
+void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
+void gpio_default_para_init(gpio_init_type *gpio_init_struct);
+flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
+uint16_t gpio_input_data_read(gpio_type *gpio_x);
+flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
+uint16_t gpio_output_data_read(gpio_type *gpio_x);
+void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
+void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
+void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
+void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
+void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
+void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
+void gpio_event_output_enable(confirm_state new_state);
+void gpio_pin_remap_config(uint32_t gpio_remap, confirm_state new_state);
+void gpio_exint_line_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_i2c.h

@@ -0,0 +1,399 @@
+/**
+  **************************************************************************
+  * @file     at32f413_i2c.h
+  * @brief    at32f413 i2c header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_I2C_H
+#define __AT32F413_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/** @defgroup I2C_sts1_flags_definition
+  * @brief  i2c sts1 flag
+  * @{
+  */
+
+#define I2C_STARTF_FLAG                  ((uint32_t)0x00000001) /*!< i2c start condition generation complete flag */
+#define I2C_ADDR7F_FLAG                  ((uint32_t)0x00000002) /*!< i2c 0~7 bit address match flag */
+#define I2C_TDC_FLAG                     ((uint32_t)0x00000004) /*!< i2c transmit data complete flag */
+#define I2C_ADDRHF_FLAG                  ((uint32_t)0x00000008) /*!< i2c master 9~8 bit address header match flag */
+#define I2C_STOPF_FLAG                   ((uint32_t)0x00000010) /*!< i2c stop condition generation complete flag */
+#define I2C_RDBF_FLAG                    ((uint32_t)0x00000040) /*!< i2c receive data buffer full flag */
+#define I2C_TDBE_FLAG                    ((uint32_t)0x00000080) /*!< i2c transmit data buffer empty flag */
+#define I2C_BUSERR_FLAG                  ((uint32_t)0x00000100) /*!< i2c bus error flag */
+#define I2C_ARLOST_FLAG                  ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
+#define I2C_ACKFAIL_FLAG                 ((uint32_t)0x00000400) /*!< i2c acknowledge failure flag */
+#define I2C_OUF_FLAG                     ((uint32_t)0x00000800) /*!< i2c overflow or underflow flag */
+#define I2C_PECERR_FLAG                  ((uint32_t)0x00001000) /*!< i2c pec receive error flag */
+#define I2C_TMOUT_FLAG                   ((uint32_t)0x00004000) /*!< i2c smbus timeout flag */
+#define I2C_ALERTF_FLAG                  ((uint32_t)0x00008000) /*!< i2c smbus alert flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_sts2_flags_definition
+  * @brief  i2c sts2 flag
+  * @{
+  */
+
+#define I2C_TRMODE_FLAG                  ((uint32_t)0x10010000) /*!< i2c transmission mode */
+#define I2C_BUSYF_FLAG                   ((uint32_t)0x10020000) /*!< i2c bus busy flag transmission mode */
+#define I2C_DIRF_FLAG                    ((uint32_t)0x10040000) /*!< i2c transmission direction flag */
+#define I2C_GCADDRF_FLAG                 ((uint32_t)0x10100000) /*!< i2c general call address received flag */
+#define I2C_DEVADDRF_FLAG                ((uint32_t)0x10200000) /*!< i2c smbus device address received flag */
+#define I2C_HOSTADDRF_FLAG               ((uint32_t)0x10400000) /*!< i2c smbus host address received flag */
+#define I2C_ADDR2_FLAG                   ((uint32_t)0x10800000) /*!< i2c own address 2 received flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_interrupts_definition
+  * @brief i2c interrupt
+  * @{
+  */
+
+#define I2C_DATA_INT                     ((uint16_t)0x0400) /*!< i2c data transmission interrupt */
+#define I2C_EVT_INT                      ((uint16_t)0x0200) /*!< i2c event interrupt */
+#define I2C_ERR_INT                      ((uint16_t)0x0100) /*!< i2c error interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_exported_types
+  * @{
+  */
+
+/**
+  * @brief i2c master receiving mode acknowledge control
+  */
+typedef enum
+{
+  I2C_MASTER_ACK_CURRENT                 = 0x00, /*!< acken bit acts on the current byte */
+  I2C_MASTER_ACK_NEXT                    = 0x01  /*!< acken bit acts on the next byte */
+} i2c_master_ack_type;
+
+/**
+  * @brief i2c pec position set
+  */
+typedef enum
+{
+  I2C_PEC_POSITION_CURRENT               = 0x00, /*!< the current byte is pec */
+  I2C_PEC_POSITION_NEXT                  = 0x01  /*!< the next byte is pec */
+} i2c_pec_position_type;
+
+
+/**
+  * @brief i2c smbus alert pin set
+  */
+typedef enum
+{
+  I2C_SMBUS_ALERT_HIGH                   = 0x00, /*!< smbus alert pin set high */
+  I2C_SMBUS_ALERT_LOW                    = 0x01  /*!< smbus alert pin set low */
+} i2c_smbus_alert_set_type;
+
+/**
+  * @brief i2c smbus mode set
+  */
+typedef enum
+{
+  I2C_SMBUS_MODE_DEVICE                  = 0x00, /*!< smbus device mode */
+  I2C_SMBUS_MODE_HOST                    = 0x01  /*!< smbus host mode */
+} i2c_smbus_mode_set_type;
+
+
+/**
+  * @brief i2c fast mode duty cycle
+  */
+typedef enum
+{
+  I2C_FSMODE_DUTY_2_1                    = 0x00, /*!< duty cycle is 2:1 in fast mode */
+  I2C_FSMODE_DUTY_16_9                   = 0x01  /*!< duty cycle is 16:9 in fast mode */
+} i2c_fsmode_duty_cycle_type;
+
+/**
+  * @brief i2c address mode
+  */
+typedef enum
+{
+  I2C_ADDRESS_MODE_7BIT                  = 0x00, /*!< 7bit address mode */
+  I2C_ADDRESS_MODE_10BIT                 = 0x01  /*!< 10bit address mode */
+} i2c_address_mode_type;
+
+/**
+  * @brief i2c address direction
+  */
+typedef enum
+{
+  I2C_DIRECTION_TRANSMIT                 = 0x00, /*!< transmit mode */
+  I2C_DIRECTION_RECEIVE                  = 0x01  /*!< receive mode */
+} i2c_direction_type;
+
+/**
+  * @brief type define i2c register all
+  */
+typedef struct
+{
+  /**
+    * @brief i2c ctrl1 register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t ctrl1;
+    struct
+    {
+      __IO uint32_t i2cen                : 1; /* [0] */
+      __IO uint32_t permode              : 1; /* [1] */
+      __IO uint32_t reserved1            : 1; /* [2] */
+      __IO uint32_t smbmode              : 1; /* [3] */
+      __IO uint32_t arpen                : 1; /* [4] */
+      __IO uint32_t pecen                : 1; /* [5] */
+      __IO uint32_t gcaen                : 1; /* [6] */
+      __IO uint32_t stretch              : 1; /* [7] */
+      __IO uint32_t genstart             : 1; /* [8] */
+      __IO uint32_t genstop              : 1; /* [9] */
+      __IO uint32_t acken                : 1; /* [10] */
+      __IO uint32_t mackctrl             : 1; /* [11] */
+      __IO uint32_t pecten               : 1; /* [12] */
+      __IO uint32_t smbalert             : 1; /* [13] */
+      __IO uint32_t reserved2            : 1; /* [14] */
+      __IO uint32_t reset                : 1; /* [15] */
+      __IO uint32_t reserved3            : 16;/* [31:16] */
+    } ctrl1_bit;
+  };
+
+  /**
+    * @brief i2c ctrl2 register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t ctrl2;
+    struct
+    {
+      __IO uint32_t clkfreq              : 8; /* [7:0] */
+      __IO uint32_t errien               : 1; /* [8] */
+      __IO uint32_t evtien               : 1; /* [9] */
+      __IO uint32_t dataien              : 1; /* [10] */
+      __IO uint32_t dmaen                : 1; /* [11] */
+      __IO uint32_t dmaend               : 1; /* [12] */
+      __IO uint32_t reserved1            : 19;/* [31:13] */
+    } ctrl2_bit;
+  };
+
+  /**
+    * @brief i2c oaddr1 register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t oaddr1;
+    struct
+    {
+      __IO uint32_t addr1                : 10;/* [9:0] */
+      __IO uint32_t reserved1            : 5; /* [14:10] */
+      __IO uint32_t addr1mode            : 1; /* [15] */
+      __IO uint32_t reserved2            : 16;/* [31:16] */
+    } oaddr1_bit;
+  };
+
+  /**
+    * @brief i2c oaddr2 register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t oaddr2;
+    struct
+    {
+      __IO uint32_t addr2en              : 1; /* [0] */
+      __IO uint32_t addr2                : 7; /* [7:1] */
+      __IO uint32_t reserved1            : 24;/* [31:8] */
+    } oaddr2_bit;
+  };
+
+  /**
+    * @brief i2c dt register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t dt;
+    struct
+    {
+      __IO uint32_t dt                   : 8; /* [7:0] */
+      __IO uint32_t reserved1            : 24;/* [31:8] */
+    } dt_bit;
+  };
+
+  /**
+    * @brief i2c sts1 register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t sts1;
+    struct
+    {
+      __IO uint32_t startf               : 1; /* [0] */
+      __IO uint32_t addr7f               : 1; /* [1] */
+      __IO uint32_t tdc                  : 1; /* [2] */
+      __IO uint32_t addrhf               : 1; /* [3] */
+      __IO uint32_t stopf                : 1; /* [4] */
+      __IO uint32_t reserved1            : 1; /* [5] */
+      __IO uint32_t rdbf                 : 1; /* [6] */
+      __IO uint32_t tdbe                 : 1; /* [7] */
+      __IO uint32_t buserr               : 1; /* [8] */
+      __IO uint32_t arlost               : 1; /* [9] */
+      __IO uint32_t ackfail              : 1; /* [10] */
+      __IO uint32_t ouf                  : 1; /* [11] */
+      __IO uint32_t pecerr               : 1; /* [12] */
+      __IO uint32_t reserved2            : 1; /* [13] */
+      __IO uint32_t tmout                : 1; /* [14] */
+      __IO uint32_t alertf               : 1; /* [15] */
+      __IO uint32_t reserved3            : 16; /* [31:16] */
+    } sts1_bit;
+  };
+
+  /**
+    * @brief i2c sts2 register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t sts2;
+    struct
+    {
+      __IO uint32_t trmode               : 1; /* [0] */
+      __IO uint32_t busyf                : 1; /* [1] */
+      __IO uint32_t dirf                 : 1; /* [2] */
+      __IO uint32_t reserved1            : 1; /* [3] */
+      __IO uint32_t gcaddrf              : 1; /* [4] */
+      __IO uint32_t devaddrf             : 1; /* [5] */
+      __IO uint32_t hostaddrf            : 1; /* [6] */
+      __IO uint32_t addr2                : 1; /* [7] */
+      __IO uint32_t pecval               : 8; /* [15:8] */
+      __IO uint32_t reserved2            : 16;/* [31:16] */
+    } sts2_bit;
+  };
+
+  /**
+    * @brief i2c clkctrl register, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t clkctrl;
+    struct
+    {
+      __IO uint32_t speed                : 12;/* [11:0] */
+      __IO uint32_t reserved1            : 2; /* [13:12] */
+      __IO uint32_t dutymode             : 1; /* [14] */
+      __IO uint32_t speedmode            : 1; /* [15] */
+      __IO uint32_t reserved2            : 16;/* [31:16] */
+    } clkctrl_bit;
+  };
+
+  /**
+    * @brief i2c tmrise register, offset:0x20
+    */
+  union
+  {
+    __IO uint32_t tmrise;
+    struct
+    {
+      __IO uint32_t risetime             : 6; /* [5:0] */
+      __IO uint32_t reserved1            : 26;/* [31:6] */
+    } tmrise_bit;
+  };
+
+} i2c_type;
+
+/**
+  * @}
+  */
+
+#define I2C1                             ((i2c_type *) I2C1_BASE)
+#define I2C2                             ((i2c_type *) I2C2_BASE)
+
+/** @defgroup I2C_exported_functions
+  * @{
+  */
+
+void i2c_reset(i2c_type *i2c_x);
+void i2c_software_reset(i2c_type *i2c_x, confirm_state new_state);
+void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed);
+void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
+void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address);
+void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_smbus_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_fast_mode_duty_set(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty);
+void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_master_receive_ack_set(i2c_type *i2c_x, i2c_master_ack_type pos);
+void i2c_pec_position_set(i2c_type *i2c_x, i2c_pec_position_type pos);
+void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_arp_mode_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_smbus_mode_set(i2c_type *i2c_x, i2c_smbus_mode_set_type mode);
+void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
+void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
+uint8_t i2c_pec_value_get(i2c_type *i2c_x);
+void i2c_dma_end_transfer_set(i2c_type *i2c_x, confirm_state new_state);
+void i2c_dma_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_interrupt_enable(i2c_type *i2c_x, uint16_t source, confirm_state new_state);
+void i2c_start_generate(i2c_type *i2c_x);
+void i2c_stop_generate(i2c_type *i2c_x);
+void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type direction);
+void i2c_data_send(i2c_type *i2c_x, uint8_t data);
+uint8_t i2c_data_receive(i2c_type *i2c_x);
+flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
+void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_misc.h

@@ -0,0 +1,123 @@
+/**
+  **************************************************************************
+  * @file     at32f413_misc.h
+  * @brief    at32f413 misc header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_MISC_H
+#define __AT32F413_MISC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/** @defgroup MISC_vector_table_base_address
+  * @{
+  */
+
+#define NVIC_VECTTAB_RAM                 ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
+#define NVIC_VECTTAB_FLASH               ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_exported_types
+  * @{
+  */
+
+/**
+  * @brief nvic interrupt priority group
+  */
+typedef enum
+{
+  NVIC_PRIORITY_GROUP_0                  = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
+  NVIC_PRIORITY_GROUP_1                  = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
+  NVIC_PRIORITY_GROUP_2                  = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
+  NVIC_PRIORITY_GROUP_3                  = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
+  NVIC_PRIORITY_GROUP_4                  = ((uint32_t)0x3)  /*!< 4 bits for preemption priority, 0 bits for subpriority */
+} nvic_priority_group_type;
+
+/**
+  * @brief nvic low power mode
+  */
+typedef enum
+{
+  NVIC_LP_SLEEPONEXIT                    = 0x02, /*!< enable sleep-on-exit feature */
+  NVIC_LP_SLEEPDEEP                      = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
+  NVIC_LP_SEVONPEND                      = 0x10  /*!< send event on pending */
+} nvic_lowpower_mode_type;
+
+/**
+  * @brief systick clock source
+  */
+typedef enum
+{
+  SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8       = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
+  SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV      = ((uint32_t)0x00000004)  /*!< systick clock source from core clock */
+} systick_clock_source_type;
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_exported_functions
+  * @{
+  */
+
+void nvic_system_reset(void);
+void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
+void nvic_irq_disable(IRQn_Type irqn);
+void nvic_priority_group_config(nvic_priority_group_type priority_group);
+void nvic_vector_table_set(uint32_t base, uint32_t offset);
+void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
+void systick_clock_source_config(systick_clock_source_type source);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_pwc.h

@@ -0,0 +1,179 @@
+/**
+  **************************************************************************
+  * @file     at32f413_pwc.h
+  * @brief    at32f413 pwc header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_PWC_H
+#define __AT32F413_PWC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup PWC
+  * @{
+  */
+
+/** @defgroup PWC_flags_definition
+  * @brief pwc flag
+  * @{
+  */
+
+#define PWC_WAKEUP_FLAG                  ((uint32_t)0x00000001) /*!< wakeup flag */
+#define PWC_STANDBY_FLAG                 ((uint32_t)0x00000002) /*!< standby flag */
+#define PWC_PVM_OUTPUT_FLAG              ((uint32_t)0x00000004) /*!< pvm output flag */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief pwc wakeup pin num definition
+  */
+#define PWC_WAKEUP_PIN_1                 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
+
+/** @defgroup PWC_exported_types
+  * @{
+  */
+
+/**
+  * @brief pwc pvm voltage type
+  */
+typedef enum
+{
+  PWC_PVM_VOLTAGE_2V3                    = 0x01, /*!< power voltage monitoring boundary 2.3v */
+  PWC_PVM_VOLTAGE_2V4                    = 0x02, /*!< power voltage monitoring boundary 2.4v */
+  PWC_PVM_VOLTAGE_2V5                    = 0x03, /*!< power voltage monitoring boundary 2.5v */
+  PWC_PVM_VOLTAGE_2V6                    = 0x04, /*!< power voltage monitoring boundary 2.6v */
+  PWC_PVM_VOLTAGE_2V7                    = 0x05, /*!< power voltage monitoring boundary 2.7v */
+  PWC_PVM_VOLTAGE_2V8                    = 0x06, /*!< power voltage monitoring boundary 2.8v */
+  PWC_PVM_VOLTAGE_2V9                    = 0x07  /*!< power voltage monitoring boundary 2.9v */
+} pwc_pvm_voltage_type;
+
+/**
+  * @brief pwc sleep enter type
+  */
+typedef enum
+{
+  PWC_SLEEP_ENTER_WFI                    = 0x00, /*!< use wfi enter sleep mode */
+  PWC_SLEEP_ENTER_WFE                    = 0x01  /*!< use wfe enter sleep mode */
+} pwc_sleep_enter_type;
+
+/**
+  * @brief pwc deep sleep enter type
+  */
+typedef enum
+{
+  PWC_DEEP_SLEEP_ENTER_WFI               = 0x00, /*!< use wfi enter deepsleep mode */
+  PWC_DEEP_SLEEP_ENTER_WFE               = 0x01  /*!< use wfe enter deepsleep mode */
+} pwc_deep_sleep_enter_type;
+
+/**
+  * @brief type define pwc register all
+  */
+typedef struct
+{
+  /**
+    * @brief pwc ctrl register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t ctrl;
+    struct
+    {
+      __IO uint32_t reserved1            : 1; /* [0] */
+      __IO uint32_t lpsel                : 1; /* [1] */
+      __IO uint32_t clswef               : 1; /* [2] */
+      __IO uint32_t clsef                : 1; /* [3] */
+      __IO uint32_t pvmen                : 1; /* [4] */
+      __IO uint32_t pvmsel               : 3; /* [7:5] */
+      __IO uint32_t bpwen                : 1; /* [8] */
+      __IO uint32_t reserved2            : 23;/* [31:9] */
+    } ctrl_bit;
+  };
+
+  /**
+    * @brief pwc ctrlsts register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t ctrlsts;
+    struct
+    {
+      __IO uint32_t swef                 : 1; /* [0] */
+      __IO uint32_t sef                  : 1; /* [1] */
+      __IO uint32_t pvmof                : 1; /* [2] */
+      __IO uint32_t reserved1            : 5; /* [7:3] */
+      __IO uint32_t swpen                : 1; /* [8] */
+      __IO uint32_t reserved2            : 23;/* [31:9] */
+    } ctrlsts_bit;
+  };
+
+} pwc_type;
+
+/**
+  * @}
+  */
+
+#define PWC                              ((pwc_type *) PWC_BASE)
+
+/** @defgroup PWC_exported_functions
+  * @{
+  */
+
+void pwc_reset(void);
+void pwc_battery_powered_domain_access(confirm_state new_state);
+void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
+void pwc_power_voltage_monitor_enable(confirm_state new_state);
+void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
+void pwc_flag_clear(uint32_t pwc_flag);
+flag_status pwc_flag_get(uint32_t pwc_flag);
+void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
+void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
+void pwc_standby_mode_enter(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_rtc.h

@@ -0,0 +1,259 @@
+/**
+  **************************************************************************
+  * @file     at32f413_rtc.h
+  * @brief    at32f413 rtc header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_RTC_H
+#define __AT32F413_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */
+
+/** @defgroup RTC_interrupts_definition
+  * @brief rtc interrupt
+  * @{
+  */
+
+#define RTC_TS_INT                       ((uint16_t)0x0001) /*!< rtc time second interrupt */
+#define RTC_TA_INT                       ((uint16_t)0x0002) /*!< rtc time alarm interrupt */
+#define RTC_OVF_INT                      ((uint16_t)0x0004) /*!< rtc overflow interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_flags_definition
+  * @brief rtc flag
+  * @{
+  */
+
+#define RTC_TS_FLAG                      ((uint16_t)0x0001) /*!< rtc time second flag */
+#define RTC_TA_FLAG                      ((uint16_t)0x0002) /*!< rtc time alarm flag */
+#define RTC_OVF_FLAG                     ((uint16_t)0x0004) /*!< rtc overflow flag */
+#define RTC_UPDF_FLAG                    ((uint16_t)0x0008) /*!< rtc update finish flag */
+#define RTC_CFGF_FLAG                    ((uint16_t)0x0020) /*!< rtc configuration finish flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_exported_types
+  * @{
+  */
+
+/**
+  * @brief type define rtc register all
+  */
+typedef struct
+{
+
+  /**
+    * @brief rtc ctrlh register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t ctrlh;
+    struct
+    {
+      __IO uint32_t tsien                : 1; /* [0] */
+      __IO uint32_t taien                : 1; /* [1] */
+      __IO uint32_t ovfien               : 1; /* [2] */
+      __IO uint32_t reserved1            : 29;/* [31:3] */
+    } ctrlh_bit;
+  };
+
+  /**
+    * @brief rtc ctrll register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t ctrll;
+    struct
+    {
+      __IO uint32_t tsf                  : 1; /* [0] */
+      __IO uint32_t taf                  : 1; /* [1] */
+      __IO uint32_t ovff                 : 1; /* [2] */
+      __IO uint32_t updf                 : 1; /* [3] */
+      __IO uint32_t cfgen                : 1; /* [4] */
+      __IO uint32_t cfgf                 : 1; /* [5] */
+      __IO uint32_t reserved1            : 26;/* [31:6] */
+    } ctrll_bit;
+  };
+
+  /**
+    * @brief rtc divh register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t divh;
+    struct
+    {
+      __IO uint32_t div                  : 4; /* [3:0] */
+      __IO uint32_t reserved1            : 28;/* [31:4] */
+    } divh_bit;
+  };
+
+  /**
+    * @brief rtc divl register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t divl;
+    struct
+    {
+      __IO uint32_t div                  : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } divl_bit;
+  };
+
+  /**
+    * @brief rtc divcnth register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t divcnth;
+    struct
+    {
+      __IO uint32_t divcnt               : 4; /* [3:0] */
+      __IO uint32_t reserved1            : 28;/* [31:15] */
+    } divcnth_bit;
+  };
+
+  /**
+    * @brief rtc divcntl register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t divcntl;
+    struct
+    {
+      __IO uint32_t divcnt               : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } divcntl_bit;
+  };
+
+  /**
+    * @brief rtc cnth register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t cnth;
+    struct
+    {
+      __IO uint32_t cnt                  : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } cnth_bit;
+  };
+
+  /**
+    * @brief rtc cntl register, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t cntl;
+    struct
+    {
+      __IO uint32_t cnt                  : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } cntl_bit;
+  };
+
+  /**
+    * @brief rtc tah register, offset:0x20
+    */
+  union
+  {
+    __IO uint32_t tah;
+    struct
+    {
+      __IO uint32_t ta                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } tah_bit;
+  };
+
+  /**
+    * @brief rtc tal register, offset:0x24
+    */
+  union
+  {
+    __IO uint32_t tal;
+    struct
+    {
+      __IO uint32_t ta                   : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:15] */
+    } tal_bit;
+  };
+
+} rtc_type;
+
+/**
+  * @}
+  */
+
+#define RTC                              ((rtc_type *) RTC_BASE)
+
+/** @defgroup RTC_exported_functions
+  * @{
+  */
+
+void rtc_counter_set(uint32_t counter_value);
+uint32_t rtc_counter_get(void);
+void rtc_divider_set(uint32_t div_value);
+uint32_t rtc_divider_get(void);
+void rtc_alarm_set(uint32_t alarm_value);
+void rtc_interrupt_enable(uint16_t source, confirm_state new_state);
+flag_status rtc_flag_get(uint16_t flag);
+void rtc_flag_clear(uint16_t flag);
+void rtc_wait_config_finish(void);
+void rtc_wait_update_finish(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_sdio.h

@@ -0,0 +1,624 @@
+/**
+  **************************************************************************
+  * @file     at32f413_sdio.h
+  * @brief    at32f413 sdio header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_SDIO_H
+#define __AT32F413_SDIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+
+/** @defgroup SDIO_interrupts_definition
+  * @brief sdio interrupt
+  * @{
+  */
+
+#define SDIO_CMDFAIL_INT                 ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
+#define SDIO_DTFAIL_INT                  ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
+#define SDIO_CMDTIMEOUT_INT              ((uint32_t)0x00000004) /*!< command response timerout interrupt */
+#define SDIO_DTTIMEOUT_INT               ((uint32_t)0x00000008) /*!< data timeout interrupt */
+#define SDIO_TXERRU_INT                  ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
+#define SDIO_RXERRO_INT                  ((uint32_t)0x00000020) /*!< received overrun error interrupt */
+#define SDIO_CMDRSPCMPL_INT              ((uint32_t)0x00000040) /*!< command response received interrupt */
+#define SDIO_CMDCMPL_INT                 ((uint32_t)0x00000080) /*!< command sent interrupt */
+#define SDIO_DTCMP_INT                   ((uint32_t)0x00000100) /*!< data sent interrupt */
+#define SDIO_SBITERR_INT                 ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
+#define SDIO_DTBLKCMPL_INT               ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
+#define SDIO_DOCMD_INT                   ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
+#define SDIO_DOTX_INT                    ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
+#define SDIO_DORX_INT                    ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
+#define SDIO_TXBUFH_INT                  ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
+#define SDIO_RXBUFH_INT                  ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
+#define SDIO_TXBUFF_INT                  ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
+#define SDIO_RXBUFF_INT                  ((uint32_t)0x00020000) /*!< receive buf full interrupt */
+#define SDIO_TXBUFE_INT                  ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
+#define SDIO_RXBUFE_INT                  ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
+#define SDIO_TXBUF_INT                   ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
+#define SDIO_RXBUF_INT                   ((uint32_t)0x00200000) /*!< data available in receive interrupt */
+#define SDIO_SDIOIF_INT                  ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_flags_definition
+  * @brief sdio flag
+  * @{
+  */
+
+#define SDIO_CMDFAIL_FLAG                ((uint32_t)0x00000001) /*!< command response received check failed flag */
+#define SDIO_DTFAIL_FLAG                 ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
+#define SDIO_CMDTIMEOUT_FLAG             ((uint32_t)0x00000004) /*!< command response timerout flag */
+#define SDIO_DTTIMEOUT_FLAG              ((uint32_t)0x00000008) /*!< data timeout flag */
+#define SDIO_TXERRU_FLAG                 ((uint32_t)0x00000010) /*!< transmit underrun error flag */
+#define SDIO_RXERRO_FLAG                 ((uint32_t)0x00000020) /*!< received overrun error flag */
+#define SDIO_CMDRSPCMPL_FLAG             ((uint32_t)0x00000040) /*!< command response received flag */
+#define SDIO_CMDCMPL_FLAG                ((uint32_t)0x00000080) /*!< command sent flag */
+#define SDIO_DTCMPL_FLAG                 ((uint32_t)0x00000100) /*!< data sent flag */
+#define SDIO_SBITERR_FLAG                ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
+#define SDIO_DTBLKCMPL_FLAG              ((uint32_t)0x00000400) /*!< data block sent/received flag */
+#define SDIO_DOCMD_FLAG                  ((uint32_t)0x00000800) /*!< command transfer in progress flag */
+#define SDIO_DOTX_FLAG                   ((uint32_t)0x00001000) /*!< data transmit in progress flag */
+#define SDIO_DORX_FLAG                   ((uint32_t)0x00002000) /*!< data receive in progress flag */
+#define SDIO_TXBUFH_FLAG                 ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
+#define SDIO_RXBUFH_FLAG                 ((uint32_t)0x00008000) /*!< receive buf half full flag */
+#define SDIO_TXBUFF_FLAG                 ((uint32_t)0x00010000) /*!< transmit buf full flag */
+#define SDIO_RXBUFF_FLAG                 ((uint32_t)0x00020000) /*!< receive buf full flag */
+#define SDIO_TXBUFE_FLAG                 ((uint32_t)0x00040000) /*!< transmit buf empty flag */
+#define SDIO_RXBUFE_FLAG                 ((uint32_t)0x00080000) /*!< receive buf empty flag */
+#define SDIO_TXBUF_FLAG                  ((uint32_t)0x00100000) /*!< data available in transmit flag */
+#define SDIO_RXBUF_FLAG                  ((uint32_t)0x00200000) /*!< data available in receive flag */
+#define SDIO_SDIOIF_FLAG                 ((uint32_t)0x00400000) /*!< sdio interface received flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_exported_types
+  * @{
+  */
+
+/**
+  * @brief sdio power state
+  */
+typedef enum
+{
+  SDIO_POWER_OFF                         = 0x00, /*!< power-off, clock to card is stopped */
+  SDIO_POWER_ON                          = 0x03  /*!< power-on, the card is clocked */
+} sdio_power_state_type;
+
+/**
+  * @brief sdio edge phase
+  */
+typedef enum
+{
+  SDIO_CLOCK_EDGE_RISING                 = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
+  SDIO_CLOCK_EDGE_FALLING                = 0x01  /*!< sdio bus clock generated on the falling edge of the master clock */
+} sdio_edge_phase_type;
+
+/**
+  * @brief sdio bus width
+  */
+typedef enum
+{
+  SDIO_BUS_WIDTH_D1                      = 0x00, /*!< sdio wide bus select 1-bit */
+  SDIO_BUS_WIDTH_D4                      = 0x01, /*!< sdio wide bus select 4-bit */
+  SDIO_BUS_WIDTH_D8                      = 0x02  /*!< sdio wide bus select 8-bit */
+} sdio_bus_width_type;
+
+/**
+  * @brief sdio response type
+  */
+typedef enum
+{
+  SDIO_RESPONSE_NO                       = 0x00, /*!< no response */
+  SDIO_RESPONSE_SHORT                    = 0x01, /*!< short response */
+  SDIO_RESPONSE_LONG                     = 0x03  /*!< long response */
+} sdio_reponse_type;
+
+/**
+  * @brief sdio wait type
+  */
+typedef enum
+{
+  SDIO_WAIT_FOR_NO                       = 0x00, /*!< no wait */
+  SDIO_WAIT_FOR_INT                      = 0x01, /*!< wait interrupt request */
+  SDIO_WAIT_FOR_PEND                     = 0x02  /*!< wait end of transfer */
+} sdio_wait_type;
+
+/**
+  * @brief sdio response register index
+  */
+typedef enum
+{
+  SDIO_RSP1_INDEX                        = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
+  SDIO_RSP2_INDEX                        = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
+  SDIO_RSP3_INDEX                        = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
+  SDIO_RSP4_INDEX                        = 0x03  /*!< response index 4, corresponding to sdio_rsp register 4 */
+} sdio_rsp_index_type;
+
+/**
+  * @brief sdio data block size
+  */
+typedef enum
+{
+  SDIO_DATA_BLOCK_SIZE_1B                = 0x00, /*!< data block size 1 byte */
+  SDIO_DATA_BLOCK_SIZE_2B                = 0x01, /*!< data block size 2 bytes */
+  SDIO_DATA_BLOCK_SIZE_4B                = 0x02, /*!< data block size 4 bytes */
+  SDIO_DATA_BLOCK_SIZE_8B                = 0x03, /*!< data block size 8 bytes */
+  SDIO_DATA_BLOCK_SIZE_16B               = 0x04, /*!< data block size 16 bytes */
+  SDIO_DATA_BLOCK_SIZE_32B               = 0x05, /*!< data block size 32 bytes */
+  SDIO_DATA_BLOCK_SIZE_64B               = 0x06, /*!< data block size 64 bytes */
+  SDIO_DATA_BLOCK_SIZE_128B              = 0x07, /*!< data block size 128 bytes */
+  SDIO_DATA_BLOCK_SIZE_256B              = 0x08, /*!< data block size 256 bytes */
+  SDIO_DATA_BLOCK_SIZE_512B              = 0x09, /*!< data block size 512 bytes */
+  SDIO_DATA_BLOCK_SIZE_1024B             = 0x0A, /*!< data block size 1024 bytes */
+  SDIO_DATA_BLOCK_SIZE_2048B             = 0x0B, /*!< data block size 2048 bytes */
+  SDIO_DATA_BLOCK_SIZE_4096B             = 0x0C, /*!< data block size 4096 bytes */
+  SDIO_DATA_BLOCK_SIZE_8192B             = 0x0D, /*!< data block size 8192 bytes */
+  SDIO_DATA_BLOCK_SIZE_16384B            = 0x0E  /*!< data block size 16384 bytes */
+} sdio_block_size_type;
+
+/**
+  * @brief sdio data transfer mode
+  */
+typedef enum
+{
+  SDIO_DATA_BLOCK_TRANSFER               = 0x00, /*!< the sdio block transfer mode */
+  SDIO_DATA_STREAM_TRANSFER              = 0x01  /*!< the sdio stream transfer mode */
+} sdio_transfer_mode_type;
+
+/**
+  * @brief sdio data transfer direction
+  */
+typedef enum
+{
+  SDIO_DATA_TRANSFER_TO_CARD             = 0x00, /*!< the sdio controller write */
+  SDIO_DATA_TRANSFER_TO_CONTROLLER       = 0x01  /*!< the sdio controller read */
+} sdio_transfer_direction_type;
+
+/**
+  * @brief sdio read wait mode
+  */
+typedef enum
+{
+  SDIO_READ_WAIT_CONTROLLED_BY_D2        = 0x00, /*!< the sdio read wait on data2 line */
+  SDIO_READ_WAIT_CONTROLLED_BY_CK        = 0x01  /*!< the sdio read wait on clock line */
+} sdio_read_wait_mode_type;
+
+/**
+  * @brief sdio command structure
+  */
+typedef struct
+{
+  uint32_t                               argument;  /*!< the sdio command argument is sent to a card as part of command message */
+  uint8_t                                cmd_index; /*!< the sdio command index */
+  sdio_reponse_type                      rsp_type;  /*!< the sdio response type */
+  sdio_wait_type                         wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
+} sdio_command_struct_type;
+
+/**
+  * @brief sdio data structure
+  */
+typedef struct
+{
+  uint32_t                               timeout;            /*!< the sdio data timeout period in car bus clock periods */
+  uint32_t                               data_length;        /*!< the sdio data length */
+  sdio_block_size_type                   block_size;         /*!< the sdio data block size of block transfer mode */
+  sdio_transfer_mode_type                transfer_mode;      /*!< the sdio transfer mode, block or stream */
+  sdio_transfer_direction_type           transfer_direction; /*!< the sdio data transfer direction */
+} sdio_data_struct_type;
+
+/**
+  * @brief type define sdio register all
+  */
+typedef struct
+{
+  /**
+    * @brief sdio pwrctrl register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t pwrctrl;
+    struct
+    {
+      __IO uint32_t ps                   : 2; /* [1:0] */
+      __IO uint32_t reserved1            : 30;/* [31:2] */
+    } pwrctrl_bit;
+  };
+
+  /**
+    * @brief sdio clkctrl register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t clkctrl;
+    struct
+    {
+      __IO uint32_t clkdiv_l             : 8; /* [7:0] */
+      __IO uint32_t clkoen               : 1; /* [8] */
+      __IO uint32_t pwrsven              : 1; /* [9] */
+      __IO uint32_t bypsen               : 1; /* [10] */
+      __IO uint32_t busws                : 2; /* [12:11] */
+      __IO uint32_t clkegs               : 1; /* [13] */
+      __IO uint32_t hfcen                : 1; /* [14] */
+      __IO uint32_t clkdiv_h             : 2; /* [16:15] */
+      __IO uint32_t reserved1            : 15;/* [31:17] */
+    } clkctrl_bit;
+  };
+
+  /**
+    * @brief sdio argu register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t argu;
+    struct
+    {
+      __IO uint32_t argu                 : 32;/* [31:0] */
+    } argu_bit;
+  };
+
+  /**
+    * @brief sdio cmdctrl register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t cmdctrl;
+    struct
+    {
+      __IO uint32_t cmdidx               : 6; /* [5:0] */
+      __IO uint32_t rspwt                : 2; /* [7:6] */
+      __IO uint32_t intwt                : 1; /* [8] */
+      __IO uint32_t pndwt                : 1; /* [9] */
+      __IO uint32_t ccsmen               : 1; /* [10] */
+      __IO uint32_t iosusp               : 1; /* [11] */
+      __IO uint32_t reserved1            : 20;/* [31:12] */
+    } cmdctrl_bit;
+  };
+
+  /**
+    * @brief sdio rspcmd register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t rspcmd;
+    struct
+    {
+      __IO uint32_t rspcmd               : 6; /* [5:0] */
+      __IO uint32_t reserved1            : 26;/* [31:6] */
+    } rspcmd_bit;
+  };
+
+  /**
+    * @brief sdio rsp1 register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t rsp1;
+    struct
+    {
+      __IO uint32_t cardsts1             : 32;/* [31:0] */
+    } rsp1_bit;
+  };
+
+  /**
+    * @brief sdio rsp2 register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t rsp2;
+    struct
+    {
+      __IO uint32_t cardsts2             : 32;/* [31:0] */
+    } rsp2_bit;
+  };
+
+  /**
+    * @brief sdio rsp3 register, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t rsp3;
+    struct
+    {
+      __IO uint32_t cardsts3             : 32;/* [31:0] */
+    } rsp3_bit;
+  };
+
+  /**
+    * @brief sdio rsp4 register, offset:0x20
+    */
+  union
+  {
+    __IO uint32_t rsp4;
+    struct
+    {
+      __IO uint32_t cardsts4             : 32;/* [31:0] */
+    } rsp4_bit;
+  };
+
+  /**
+    * @brief sdio dttmr register, offset:0x24
+    */
+  union
+  {
+    __IO uint32_t dttmr;
+    struct
+    {
+      __IO uint32_t timeout              : 32;/* [31:0] */
+    } dttmr_bit;
+  };
+
+  /**
+    * @brief sdio dtlen register, offset:0x28
+    */
+  union
+  {
+    __IO uint32_t dtlen;
+    struct
+    {
+      __IO uint32_t dtlen                : 25;/* [24:0] */
+      __IO uint32_t reserved1            : 7; /* [31:25] */
+    } dtlen_bit;
+  };
+
+  /**
+    * @brief sdio dtctrl register, offset:0x2C
+    */
+  union
+  {
+    __IO uint32_t dtctrl;
+    struct
+    {
+      __IO uint32_t tfren                : 1; /* [0] */
+      __IO uint32_t tfrdir               : 1; /* [1] */
+      __IO uint32_t tfrmode              : 1; /* [2] */
+      __IO uint32_t dmaen                : 1; /* [3] */
+      __IO uint32_t blksize              : 4; /* [7:4] */
+      __IO uint32_t rdwtstart            : 1; /* [8] */
+      __IO uint32_t rdwtstop             : 1; /* [9] */
+      __IO uint32_t rdwtmode             : 1; /* [10] */
+      __IO uint32_t ioen                 : 1; /* [11] */
+      __IO uint32_t reserved1            : 20;/* [31:12] */
+    } dtctrl_bit;
+  };
+
+  /**
+    * @brief sdio dtcnt register, offset:0x30
+    */
+  union
+  {
+    __IO uint32_t dtcnt;
+    struct
+    {
+      __IO uint32_t cnt                  : 25;/* [24:0] */
+      __IO uint32_t reserved1            : 7; /* [31:25] */
+    } dtcnt_bit;
+  };
+
+  /**
+    * @brief sdio sts register, offset:0x34
+    */
+  union
+  {
+    __IO uint32_t sts;
+    struct
+    {
+      __IO uint32_t cmdfail              : 1; /* [0] */
+      __IO uint32_t dtfail               : 1; /* [1] */
+      __IO uint32_t cmdtimeout           : 1; /* [2] */
+      __IO uint32_t dttimeout            : 1; /* [3] */
+      __IO uint32_t txerru               : 1; /* [4] */
+      __IO uint32_t rxerro               : 1; /* [5] */
+      __IO uint32_t cmdrspcmpl           : 1; /* [6] */
+      __IO uint32_t cmdcmpl              : 1; /* [7] */
+      __IO uint32_t dtcmpl               : 1; /* [8] */
+      __IO uint32_t sbiterr              : 1; /* [9] */
+      __IO uint32_t dtblkcmpl            : 1; /* [10] */
+      __IO uint32_t docmd                : 1; /* [11] */
+      __IO uint32_t dotx                 : 1; /* [12] */
+      __IO uint32_t dorx                 : 1; /* [13] */
+      __IO uint32_t txbufh               : 1; /* [14] */
+      __IO uint32_t rxbufh               : 1; /* [15] */
+      __IO uint32_t txbuff               : 1; /* [16] */
+      __IO uint32_t rxbuff               : 1; /* [17] */
+      __IO uint32_t txbufe               : 1; /* [18] */
+      __IO uint32_t rxbufe               : 1; /* [19] */
+      __IO uint32_t txbuf                : 1; /* [20] */
+      __IO uint32_t rxbuf                : 1; /* [21] */
+      __IO uint32_t ioif                 : 1; /* [22] */
+      __IO uint32_t reserved1            : 9; /* [31:23] */
+    } sts_bit;
+  };
+
+  /**
+    * @brief sdio intclr register, offset:0x38
+    */
+  union
+  {
+    __IO uint32_t intclr;
+    struct
+    {
+      __IO uint32_t cmdfail              : 1; /* [0] */
+      __IO uint32_t dtfail               : 1; /* [1] */
+      __IO uint32_t cmdtimeout           : 1; /* [2] */
+      __IO uint32_t dttimeout            : 1; /* [3] */
+      __IO uint32_t txerru               : 1; /* [4] */
+      __IO uint32_t rxerro               : 1; /* [5] */
+      __IO uint32_t cmdrspcmpl           : 1; /* [6] */
+      __IO uint32_t cmdcmpl              : 1; /* [7] */
+      __IO uint32_t dtcmpl               : 1; /* [8] */
+      __IO uint32_t sbiterr              : 1; /* [9] */
+      __IO uint32_t dtblkcmpl            : 1; /* [10] */
+      __IO uint32_t reserved1            : 11;/* [21:11] */
+      __IO uint32_t ioif                 : 1; /* [22] */
+      __IO uint32_t reserved2            : 9; /* [31:23] */
+    } intclr_bit;
+  };
+
+  /**
+    * @brief sdio inten register, offset:0x3C
+    */
+  union
+  {
+    __IO uint32_t inten;
+    struct
+    {
+      __IO uint32_t cmdfailien           : 1; /* [0] */
+      __IO uint32_t dtfailien            : 1; /* [1] */
+      __IO uint32_t cmdtimeoutien        : 1; /* [2] */
+      __IO uint32_t dttimeoutien         : 1; /* [3] */
+      __IO uint32_t txerruien            : 1; /* [4] */
+      __IO uint32_t rxerroien            : 1; /* [5] */
+      __IO uint32_t cmdrspcmplien        : 1; /* [6] */
+      __IO uint32_t cmdcmplien           : 1; /* [7] */
+      __IO uint32_t dtcmplien            : 1; /* [8] */
+      __IO uint32_t sbiterrien           : 1; /* [9] */
+      __IO uint32_t dtblkcmplien         : 1; /* [10] */
+      __IO uint32_t docmdien             : 1; /* [11] */
+      __IO uint32_t dotxien              : 1; /* [12] */
+      __IO uint32_t dorxien              : 1; /* [13] */
+      __IO uint32_t txbufhien            : 1; /* [14] */
+      __IO uint32_t rxbufhien            : 1; /* [15] */
+      __IO uint32_t txbuffien            : 1; /* [16] */
+      __IO uint32_t rxbuffien            : 1; /* [17] */
+      __IO uint32_t txbufeien            : 1; /* [18] */
+      __IO uint32_t rxbufeien            : 1; /* [19] */
+      __IO uint32_t txbufien             : 1; /* [20] */
+      __IO uint32_t rxbufien             : 1; /* [21] */
+      __IO uint32_t ioifien              : 1; /* [22] */
+      __IO uint32_t reserved1            : 9; /* [31:23] */
+    } inten_bit;
+  };
+
+  /**
+    * @brief sdio reserved1 register, offset:0x40~0x44
+    */
+  __IO uint32_t reserved1[2];
+
+  /**
+    * @brief sdio bufcnt register, offset:0x48
+    */
+  union
+  {
+    __IO uint32_t bufcnt;
+    struct
+    {
+      __IO uint32_t cnt                  : 24;/* [23:0] */
+      __IO uint32_t reserved1            : 8; /* [31:24] */
+    } bufcnt_bit;
+  };
+
+  /**
+    * @brief sdio reserved2 register, offset:0x4C~0x7C
+    */
+  __IO uint32_t reserved2[13];
+
+  /**
+    * @brief sdio buf register, offset:0x80
+    */
+  union
+  {
+    __IO uint32_t buf;
+    struct
+    {
+      __IO uint32_t dt                   : 32;/* [31:0] */
+    } buf_bit;
+  };
+
+} sdio_type;
+
+/**
+  * @}
+  */
+
+#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \
+    defined (AT32F413Kx)
+#define SDIO1                            ((sdio_type *) SDIO1_BASE)
+#endif
+
+/** @defgroup SDIO_exported_functions
+  * @{
+  */
+
+void sdio_reset(sdio_type *sdio_x);
+void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
+sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
+void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
+void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
+void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
+void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt,  confirm_state new_state);
+flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
+void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
+void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
+void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
+uint8_t sdio_command_response_get(sdio_type *sdio_x);
+uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
+void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
+void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
+uint32_t sdio_data_counter_get(sdio_type *sdio_x);
+uint32_t sdio_data_read(sdio_type *sdio_x);
+uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
+void sdio_data_write(sdio_type *sdio_x, uint32_t data);
+void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
+void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
+void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
+void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_spi.h

@@ -0,0 +1,494 @@
+/**
+  **************************************************************************
+  * @file     at32f413_spi.h
+  * @brief    at32f413 spi header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_SPI_H
+#define __AT32F413_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/**
+  * @defgroup SPI_I2S_flags_definition
+  * @brief spi i2s flag
+  * @{
+  */
+
+#define SPI_I2S_RDBF_FLAG                0x0001 /*!< spi or i2s receive data buffer full flag */
+#define SPI_I2S_TDBE_FLAG                0x0002 /*!< spi or i2s transmit data buffer empty flag */
+#define I2S_ACS_FLAG                     0x0004 /*!< i2s audio channel state flag */
+#define I2S_TUERR_FLAG                   0x0008 /*!< i2s transmitter underload error flag */
+#define SPI_CCERR_FLAG                   0x0010 /*!< spi crc calculation error flag */
+#define SPI_MMERR_FLAG                   0x0020 /*!< spi master mode error flag */
+#define SPI_I2S_ROERR_FLAG               0x0040 /*!< spi or i2s receiver overflow error flag */
+#define SPI_I2S_BF_FLAG                  0x0080 /*!< spi or i2s busy flag */
+
+/**
+  * @}
+  */
+
+/**
+  * @defgroup SPI_I2S_interrupts_definition
+  * @brief spi i2s interrupt
+  * @{
+  */
+
+#define SPI_I2S_ERROR_INT                0x0020 /*!< error interrupt */
+#define SPI_I2S_RDBF_INT                 0x0040 /*!< receive data buffer full interrupt */
+#define SPI_I2S_TDBE_INT                 0x0080 /*!< transmit data buffer empty interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_exported_types
+  * @{
+  */
+
+/**
+  * @brief spi frame bit num type
+  */
+typedef enum
+{
+  SPI_FRAME_8BIT                         = 0x00, /*!< 8-bit data frame format */
+  SPI_FRAME_16BIT                        = 0x01  /*!< 16-bit data frame format */
+} spi_frame_bit_num_type;
+
+/**
+  * @brief spi master/slave mode type
+  */
+typedef enum
+{
+  SPI_MODE_SLAVE                         = 0x00, /*!< select as slave mode */
+  SPI_MODE_MASTER                        = 0x01  /*!< select as master mode */
+} spi_master_slave_mode_type;
+
+/**
+  * @brief spi clock polarity (clkpol) type
+  */
+typedef enum
+{
+  SPI_CLOCK_POLARITY_LOW                 = 0x00, /*!< sck keeps low at idle state */
+  SPI_CLOCK_POLARITY_HIGH                = 0x01  /*!< sck keeps high at idle state */
+} spi_clock_polarity_type;
+
+/**
+  * @brief spi clock phase (clkpha) type
+  */
+typedef enum
+{
+  SPI_CLOCK_PHASE_1EDGE                  = 0x00, /*!< data capture start from the first clock edge */
+  SPI_CLOCK_PHASE_2EDGE                  = 0x01  /*!< data capture start from the second clock edge */
+} spi_clock_phase_type;
+
+/**
+  * @brief spi cs mode type
+  */
+typedef enum
+{
+  SPI_CS_HARDWARE_MODE                   = 0x00, /*!< cs is hardware mode */
+  SPI_CS_SOFTWARE_MODE                   = 0x01  /*!< cs is software mode */
+} spi_cs_mode_type;
+
+/**
+  * @brief spi master clock frequency division type
+  */
+typedef enum
+{
+  SPI_MCLK_DIV_2                        = 0x00, /*!< master clock frequency division 2 */
+  SPI_MCLK_DIV_4                        = 0x01, /*!< master clock frequency division 4 */
+  SPI_MCLK_DIV_8                        = 0x02, /*!< master clock frequency division 8 */
+  SPI_MCLK_DIV_16                       = 0x03, /*!< master clock frequency division 16 */
+  SPI_MCLK_DIV_32                       = 0x04, /*!< master clock frequency division 32 */
+  SPI_MCLK_DIV_64                       = 0x05, /*!< master clock frequency division 64 */
+  SPI_MCLK_DIV_128                      = 0x06, /*!< master clock frequency division 128 */
+  SPI_MCLK_DIV_256                      = 0x07, /*!< master clock frequency division 256 */
+  SPI_MCLK_DIV_512                      = 0x08, /*!< master clock frequency division 512 */
+  SPI_MCLK_DIV_1024                     = 0x09  /*!< master clock frequency division 1024 */
+} spi_mclk_freq_div_type;
+
+/**
+  * @brief spi transmit first bit (lsb/msb) type
+  */
+typedef enum
+{
+  SPI_FIRST_BIT_MSB                      = 0x00, /*!< the frame format is msb first */
+  SPI_FIRST_BIT_LSB                      = 0x01  /*!< the frame format is lsb first */
+} spi_first_bit_type;
+
+/**
+  * @brief spi transmission mode type
+  */
+typedef enum
+{
+  SPI_TRANSMIT_FULL_DUPLEX               = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
+  SPI_TRANSMIT_SIMPLEX_RX                = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
+  SPI_TRANSMIT_HALF_DUPLEX_RX            = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
+  SPI_TRANSMIT_HALF_DUPLEX_TX            = 0x03  /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
+} spi_transmission_mode_type;
+
+/**
+  * @brief spi crc direction type
+  */
+typedef enum
+{
+  SPI_CRC_RX                             = 0x0014, /*!< crc direction is rx */
+  SPI_CRC_TX                             = 0x0018  /*!< crc direction is tx */
+} spi_crc_direction_type;
+
+/**
+  * @brief spi single line bidirectional direction type
+  */
+typedef enum
+{
+  SPI_HALF_DUPLEX_DIRECTION_RX           = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
+  SPI_HALF_DUPLEX_DIRECTION_TX           = 0x01  /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
+} spi_half_duplex_direction_type;
+
+/**
+  * @brief spi software cs internal level type
+  */
+typedef enum
+{
+  SPI_SWCS_INTERNAL_LEVEL_LOW            = 0x00, /*!< internal level low */
+  SPI_SWCS_INTERNAL_LEVEL_HIGHT          = 0x01  /*!< internal level high */
+} spi_software_cs_level_type;
+
+/**
+  * @brief i2s audio protocol type
+  */
+typedef enum
+{
+  I2S_AUDIO_PROTOCOL_PHILLIPS            = 0x00, /*!< i2s philip standard */
+  I2S_AUDIO_PROTOCOL_MSB                 = 0x01, /*!< msb-justified standard */
+  I2S_AUDIO_PROTOCOL_LSB                 = 0x02, /*!< lsb-justified standard */
+  I2S_AUDIO_PROTOCOL_PCM_SHORT           = 0x03, /*!< pcm standard-short frame */
+  I2S_AUDIO_PROTOCOL_PCM_LONG            = 0x04  /*!< pcm standard-long frame */
+} i2s_audio_protocol_type;
+
+/**
+  * @brief i2s audio frequency type
+  */
+typedef enum
+{
+  I2S_AUDIO_FREQUENCY_DEFAULT            = 2,     /*!< i2s audio sampling frequency default */
+  I2S_AUDIO_FREQUENCY_8K                 = 8000,  /*!< i2s audio sampling frequency 8k */
+  I2S_AUDIO_FREQUENCY_11_025K            = 11025, /*!< i2s audio sampling frequency 11.025k */
+  I2S_AUDIO_FREQUENCY_16K                = 16000, /*!< i2s audio sampling frequency 16k */
+  I2S_AUDIO_FREQUENCY_22_05K             = 22050, /*!< i2s audio sampling frequency 22.05k */
+  I2S_AUDIO_FREQUENCY_32K                = 32000, /*!< i2s audio sampling frequency 32k */
+  I2S_AUDIO_FREQUENCY_44_1K              = 44100, /*!< i2s audio sampling frequency 44.1k */
+  I2S_AUDIO_FREQUENCY_48K                = 48000, /*!< i2s audio sampling frequency 48k */
+  I2S_AUDIO_FREQUENCY_96K                = 96000, /*!< i2s audio sampling frequency 96k */
+  I2S_AUDIO_FREQUENCY_192K               = 192000 /*!< i2s audio sampling frequency 192k */
+} i2s_audio_sampling_freq_type;
+
+/**
+  * @brief i2s data bit num and channel bit num type
+  */
+typedef enum
+{
+  I2S_DATA_16BIT_CHANNEL_16BIT           = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
+  I2S_DATA_16BIT_CHANNEL_32BIT           = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
+  I2S_DATA_24BIT_CHANNEL_32BIT           = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
+  I2S_DATA_32BIT_CHANNEL_32BIT           = 0x04  /*!< 32-bit data packed in 32-bit channel frame */
+} i2s_data_channel_format_type;
+
+/**
+  * @brief i2s operation mode type
+  */
+typedef enum
+{
+  I2S_MODE_SLAVE_TX                      = 0x00, /*!< slave transmission mode */
+  I2S_MODE_SLAVE_RX                      = 0x01, /*!< slave reception mode */
+  I2S_MODE_MASTER_TX                     = 0x02, /*!< master transmission mode */
+  I2S_MODE_MASTER_RX                     = 0x03  /*!< master reception mode */
+} i2s_operation_mode_type;
+
+/**
+  * @brief i2s clock polarity type
+  */
+typedef enum
+{
+  I2S_CLOCK_POLARITY_LOW                 = 0x00, /*!< i2s clock steady state is low level */
+  I2S_CLOCK_POLARITY_HIGH                = 0x01  /*!< i2s clock steady state is high level */
+} i2s_clock_polarity_type;
+
+/**
+  * @brief spi init type
+  */
+typedef struct
+{
+  spi_transmission_mode_type             transmission_mode;     /*!< transmission mode selection */
+  spi_master_slave_mode_type             master_slave_mode;     /*!< master or slave mode selection */
+  spi_mclk_freq_div_type                 mclk_freq_division;    /*!< master clock frequency division selection */
+  spi_first_bit_type                     first_bit_transmission;/*!< transmit lsb or msb selection */
+  spi_frame_bit_num_type                 frame_bit_num;         /*!< frame bit num 8 or 16 bit selection */
+  spi_clock_polarity_type                clock_polarity;        /*!< clock polarity selection */
+  spi_clock_phase_type                   clock_phase;           /*!< clock phase selection */
+  spi_cs_mode_type                       cs_mode_selection;     /*!< hardware or software cs mode selection */
+} spi_init_type;
+
+/**
+  * @brief i2s init type
+  */
+typedef struct
+{
+  i2s_operation_mode_type                operation_mode;        /*!< operation mode selection */
+  i2s_audio_protocol_type                audio_protocol;        /*!< audio protocol selection */
+  i2s_audio_sampling_freq_type           audio_sampling_freq;   /*!< audio frequency selection */
+  i2s_data_channel_format_type           data_channel_format;   /*!< data bit num and channel bit num selection */
+  i2s_clock_polarity_type                clock_polarity;        /*!< clock polarity selection */
+  confirm_state                          mclk_output_enable;    /*!< mclk_output selection */
+} i2s_init_type;
+
+/**
+  * @brief type define spi register all
+  */
+typedef struct
+{
+
+  /**
+    * @brief spi ctrl1 register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t ctrl1;
+    struct
+    {
+      __IO uint32_t clkpha               : 1; /* [0] */
+      __IO uint32_t clkpol               : 1; /* [1] */
+      __IO uint32_t msten                : 1; /* [2] */
+      __IO uint32_t mdiv_l               : 3; /* [5:3] */
+      __IO uint32_t spien                : 1; /* [6] */
+      __IO uint32_t ltf                  : 1; /* [7] */
+      __IO uint32_t swcsil               : 1; /* [8] */
+      __IO uint32_t swcsen               : 1; /* [9] */
+      __IO uint32_t ora                  : 1; /* [10] */
+      __IO uint32_t fbn                  : 1; /* [11] */
+      __IO uint32_t ntc                  : 1; /* [12] */
+      __IO uint32_t ccen                 : 1; /* [13] */
+      __IO uint32_t slbtd                : 1; /* [14] */
+      __IO uint32_t slben                : 1; /* [15] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } ctrl1_bit;
+  };
+
+  /**
+    * @brief spi ctrl2 register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t ctrl2;
+    struct
+    {
+      __IO uint32_t dmaren               : 1; /* [0] */
+      __IO uint32_t dmaten               : 1; /* [1] */
+      __IO uint32_t hwcsoe               : 1; /* [2] */
+      __IO uint32_t reserved1            : 2; /* [4:3] */
+      __IO uint32_t errie                : 1; /* [5] */
+      __IO uint32_t rdbfie               : 1; /* [6] */
+      __IO uint32_t tdbeie               : 1; /* [7] */
+      __IO uint32_t mdiv_h               : 1; /* [8] */
+      __IO uint32_t reserved2            : 23;/* [31:9] */
+    } ctrl2_bit;
+  };
+
+  /**
+    * @brief spi sts register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t sts;
+    struct
+    {
+      __IO uint32_t rdbf                 : 1; /* [0] */
+      __IO uint32_t tdbe                 : 1; /* [1] */
+      __IO uint32_t acs                  : 1; /* [2] */
+      __IO uint32_t tuerr                : 1; /* [3] */
+      __IO uint32_t ccerr                : 1; /* [4] */
+      __IO uint32_t mmerr                : 1; /* [5] */
+      __IO uint32_t roerr                : 1; /* [6] */
+      __IO uint32_t bf                   : 1; /* [7] */
+      __IO uint32_t reserved1            : 24;/* [31:8] */
+    } sts_bit;
+  };
+
+  /**
+    * @brief spi dt register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t dt;
+    struct
+    {
+      __IO uint32_t dt                  : 16;/* [15:0] */
+      __IO uint32_t reserved1           : 16;/* [31:16] */
+    } dt_bit;
+  };
+
+  /**
+    * @brief spi cpoly register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t cpoly;
+    struct
+    {
+      __IO uint32_t cpoly               : 16;/* [15:0] */
+      __IO uint32_t reserved1           : 16;/* [31:16] */
+    } cpoly_bit;
+  };
+
+  /**
+    * @brief spi rcrc register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t rcrc;
+    struct
+    {
+      __IO uint32_t rcrc                : 16;/* [15:0] */
+      __IO uint32_t reserved1           : 16;/* [31:16] */
+    } rcrc_bit;
+  };
+
+  /**
+    * @brief spi tcrc register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t tcrc;
+    struct
+    {
+      __IO uint32_t tcrc                : 16;/* [15:0] */
+      __IO uint32_t reserved1           : 16;/* [31:16] */
+    } tcrc_bit;
+  };
+
+  /**
+    * @brief spi i2sctrl register, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t i2sctrl;
+    struct
+    {
+      __IO uint32_t i2scbn              : 1; /* [0] */
+      __IO uint32_t i2sdbn              : 2; /* [2:1] */
+      __IO uint32_t i2sclkpol           : 1; /* [3] */
+      __IO uint32_t stdsel              : 2; /* [5:4] */
+      __IO uint32_t reserved1           : 1; /* [6] */
+      __IO uint32_t pcmfssel            : 1; /* [7] */
+      __IO uint32_t opersel             : 2; /* [9:8] */
+      __IO uint32_t i2sen               : 1; /* [10] */
+      __IO uint32_t i2smsel             : 1; /* [11] */
+      __IO uint32_t reserved2           : 20;/* [31:12] */
+    } i2sctrl_bit;
+  };
+
+  /**
+    * @brief spi i2sclk register, offset:0x20
+    */
+  union
+  {
+    __IO uint32_t i2sclk;
+    struct
+    {
+      __IO uint32_t i2sdiv_l            : 8; /* [7:0] */
+      __IO uint32_t i2sodd              : 1; /* [8] */
+      __IO uint32_t i2smclkoe           : 1; /* [9] */
+      __IO uint32_t i2sdiv_h            : 2; /* [11:10] */
+      __IO uint32_t reserved1           : 20;/* [31:12] */
+    } i2sclk_bit;
+  };
+
+} spi_type;
+
+/**
+  * @}
+  */
+
+#define SPI1                            ((spi_type *) SPI1_BASE)
+#define SPI2                            ((spi_type *) SPI2_BASE)
+
+
+/** @defgroup SPI_exported_functions
+  * @{
+  */
+
+void spi_i2s_reset(spi_type *spi_x);
+void spi_default_para_init(spi_init_type* spi_init_struct);
+void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
+void spi_crc_next_transmit(spi_type* spi_x);
+void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
+uint16_t spi_crc_polynomial_get(spi_type* spi_x);
+void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
+uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
+void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
+void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
+void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
+void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
+void spi_enable(spi_type* spi_x, confirm_state new_state);
+void i2s_default_para_init(i2s_init_type* i2s_init_struct);
+void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
+void i2s_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
+void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
+uint16_t spi_i2s_data_receive(spi_type* spi_x);
+flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
+void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_tmr.h

@@ -0,0 +1,939 @@
+/**
+  **************************************************************************
+  * @file     at32f413_tmr.h
+  * @brief    at32f413 tmr header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_TMR_H
+#define __AT32F413_TMR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup TMR
+  * @{
+  */
+
+/** @defgroup TMR_flags_definition
+  * @brief tmr flag
+  * @{
+  */
+
+#define TMR_OVF_FLAG                     ((uint32_t)0x000001) /*!< tmr flag overflow */
+#define TMR_C1_FLAG                      ((uint32_t)0x000002) /*!< tmr flag channel 1 */
+#define TMR_C2_FLAG                      ((uint32_t)0x000004) /*!< tmr flag channel 2 */
+#define TMR_C3_FLAG                      ((uint32_t)0x000008) /*!< tmr flag channel 3 */
+#define TMR_C4_FLAG                      ((uint32_t)0x000010) /*!< tmr flag channel 4 */
+#define TMR_HALL_FLAG                    ((uint32_t)0x000020) /*!< tmr flag hall */
+#define TMR_TRIGGER_FLAG                 ((uint32_t)0x000040) /*!< tmr flag trigger */
+#define TMR_BRK_FLAG                     ((uint32_t)0x000080) /*!< tmr flag brake */
+#define TMR_C1_RECAPTURE_FLAG            ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
+#define TMR_C2_RECAPTURE_FLAG            ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
+#define TMR_C3_RECAPTURE_FLAG            ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
+#define TMR_C4_RECAPTURE_FLAG            ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_interrupt_select_type_definition
+  * @brief tmr interrupt select type
+  * @{
+  */
+
+#define TMR_OVF_INT                      ((uint32_t)0x000001) /*!< tmr interrupt overflow */
+#define TMR_C1_INT                       ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
+#define TMR_C2_INT                       ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
+#define TMR_C3_INT                       ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
+#define TMR_C4_INT                       ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
+#define TMR_HALL_INT                     ((uint32_t)0x000020) /*!< tmr interrupt hall */
+#define TMR_TRIGGER_INT                  ((uint32_t)0x000040) /*!< tmr interrupt trigger */
+#define TMR_BRK_INT                      ((uint32_t)0x000080) /*!< tmr interrupt brake */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_exported_types
+  * @{
+  */
+
+/**
+  * @brief tmr clock division type
+  */
+typedef enum
+{
+  TMR_CLOCK_DIV1                         = 0x00, /*!< tmr clock division 1 */
+  TMR_CLOCK_DIV2                         = 0x01, /*!< tmr clock division 2 */
+  TMR_CLOCK_DIV4                         = 0x02  /*!< tmr clock division 4 */
+} tmr_clock_division_type;
+
+/**
+  * @brief tmr counter mode type
+  */
+typedef enum
+{
+  TMR_COUNT_UP                           = 0x00, /*!< tmr counter mode up */
+  TMR_COUNT_DOWN                         = 0x01, /*!< tmr counter mode down */
+  TMR_COUNT_TWO_WAY_1                    = 0x02, /*!< tmr counter mode two way 1 */
+  TMR_COUNT_TWO_WAY_2                    = 0x04, /*!< tmr counter mode two way 2 */
+  TMR_COUNT_TWO_WAY_3                    = 0x06  /*!< tmr counter mode two way 3 */
+} tmr_count_mode_type;
+
+/**
+  * @brief tmr primary mode select type
+  */
+typedef enum
+{
+  TMR_PRIMARY_SEL_RESET                  = 0x00, /*!< tmr primary mode select reset */
+  TMR_PRIMARY_SEL_ENABLE                 = 0x01, /*!< tmr primary mode select enable */
+  TMR_PRIMARY_SEL_OVERFLOW               = 0x02, /*!< tmr primary mode select overflow */
+  TMR_PRIMARY_SEL_COMPARE                = 0x03, /*!< tmr primary mode select compare */
+  TMR_PRIMARY_SEL_C1ORAW                 = 0x04, /*!< tmr primary mode select c1oraw */
+  TMR_PRIMARY_SEL_C2ORAW                 = 0x05, /*!< tmr primary mode select c2oraw */
+  TMR_PRIMARY_SEL_C3ORAW                 = 0x06, /*!< tmr primary mode select c3oraw */
+  TMR_PRIMARY_SEL_C4ORAW                 = 0x07  /*!< tmr primary mode select c4oraw */
+} tmr_primary_select_type;
+
+/**
+  * @brief tmr subordinate mode input select type
+  */
+typedef enum
+{
+  TMR_SUB_INPUT_SEL_IS0                  = 0x00, /*!< subordinate mode input select is0 */
+  TMR_SUB_INPUT_SEL_IS1                  = 0x01, /*!< subordinate mode input select is1 */
+  TMR_SUB_INPUT_SEL_IS2                  = 0x02, /*!< subordinate mode input select is2 */
+  TMR_SUB_INPUT_SEL_IS3                  = 0x03, /*!< subordinate mode input select is3 */
+  TMR_SUB_INPUT_SEL_C1INC                = 0x04, /*!< subordinate mode input select c1inc */
+  TMR_SUB_INPUT_SEL_C1DF1                = 0x05, /*!< subordinate mode input select c1df1 */
+  TMR_SUB_INPUT_SEL_C2DF2                = 0x06, /*!< subordinate mode input select c2df2 */
+  TMR_SUB_INPUT_SEL_EXTIN                = 0x07  /*!< subordinate mode input select extin */
+} sub_tmr_input_sel_type;
+
+/**
+  * @brief tmr subordinate mode select type
+  */
+typedef enum
+{
+  TMR_SUB_MODE_DIABLE                    = 0x00, /*!< subordinate mode disable */
+  TMR_SUB_ENCODER_MODE_A                 = 0x01, /*!< subordinate mode select encoder mode a */
+  TMR_SUB_ENCODER_MODE_B                 = 0x02, /*!< subordinate mode select encoder mode b */
+  TMR_SUB_ENCODER_MODE_C                 = 0x03, /*!< subordinate mode select encoder mode c */
+  TMR_SUB_RESET_MODE                     = 0x04, /*!< subordinate mode select reset */
+  TMR_SUB_HANG_MODE                      = 0x05, /*!< subordinate mode select hang */
+  TMR_SUB_TRIGGER_MODE                   = 0x06, /*!< subordinate mode select trigger */
+  TMR_SUB_EXTERNAL_CLOCK_MODE_A          = 0x07  /*!< subordinate mode external clock mode a */
+} tmr_sub_mode_select_type;
+
+/**
+  * @brief tmr encoder mode type
+  */
+typedef enum
+{
+  TMR_ENCODER_MODE_A                     = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
+  TMR_ENCODER_MODE_B                     = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
+  TMR_ENCODER_MODE_C                     = TMR_SUB_ENCODER_MODE_C  /*!< tmr encoder mode c */
+} tmr_encoder_mode_type;
+
+/**
+  * @brief tmr output control mode type
+  */
+typedef enum
+{
+  TMR_OUTPUT_CONTROL_OFF                 = 0x00, /*!< tmr output control mode off */
+  TMR_OUTPUT_CONTROL_HIGH                = 0x01, /*!< tmr output control mode high */
+  TMR_OUTPUT_CONTROL_LOW                 = 0x02, /*!< tmr output control mode low */
+  TMR_OUTPUT_CONTROL_SWITCH              = 0x03, /*!< tmr output control mode switch */
+  TMR_OUTPUT_CONTROL_FORCE_LOW           = 0x04, /*!< tmr output control mode force low */
+  TMR_OUTPUT_CONTROL_FORCE_HIGH          = 0x05, /*!< tmr output control mode force high */
+  TMR_OUTPUT_CONTROL_PWM_MODE_A          = 0x06, /*!< tmr output control mode pwm a */
+  TMR_OUTPUT_CONTROL_PWM_MODE_B          = 0x07  /*!< tmr output control mode pwm b */
+} tmr_output_control_mode_type;
+
+/**
+  * @brief tmr force output type
+  */
+typedef enum
+{
+  TMR_FORCE_OUTPUT_HIGH                  = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
+  TMR_FORCE_OUTPUT_LOW                   = TMR_OUTPUT_CONTROL_FORCE_LOW   /*!< tmr force output low */
+} tmr_force_output_type;
+
+/**
+  * @brief tmr output channel polarity type
+  */
+typedef enum
+{
+  TMR_OUTPUT_ACTIVE_HIGH                 = 0x00, /*!< tmr output channel polarity high */
+  TMR_OUTPUT_ACTIVE_LOW                  = 0x01  /*!< tmr output channel polarity low */
+} tmr_output_polarity_type;
+
+/**
+  * @brief tmr input channel polarity type
+  */
+typedef enum
+{
+  TMR_INPUT_RISING_EDGE                  = 0x00, /*!< tmr input channel polarity rising */
+  TMR_INPUT_FALLING_EDGE                 = 0x01, /*!< tmr input channel polarity falling */
+  TMR_INPUT_BOTH_EDGE                    = 0x03  /*!< tmr input channel polarity both edge */
+} tmr_input_polarity_type;
+
+/**
+  * @brief tmr channel select type
+  */
+typedef enum
+{
+  TMR_SELECT_CHANNEL_1                   = 0x00, /*!< tmr channel select channel 1 */
+  TMR_SELECT_CHANNEL_1C                  = 0x01, /*!< tmr channel select channel 1 complementary */
+  TMR_SELECT_CHANNEL_2                   = 0x02, /*!< tmr channel select channel 2 */
+  TMR_SELECT_CHANNEL_2C                  = 0x03, /*!< tmr channel select channel 2 complementary */
+  TMR_SELECT_CHANNEL_3                   = 0x04, /*!< tmr channel select channel 3 */
+  TMR_SELECT_CHANNEL_3C                  = 0x05, /*!< tmr channel select channel 3 complementary */
+  TMR_SELECT_CHANNEL_4                   = 0x06  /*!< tmr channel select channel 4 */
+} tmr_channel_select_type;
+
+/**
+  * @brief tmr channel1 input connected type
+  */
+typedef enum
+{
+  TMR_CHANEL1_CONNECTED_C1IRAW           = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
+  TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR   = 0x01  /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
+} tmr_channel1_input_connected_type;
+
+/**
+  * @brief tmr input channel mapped type channel direction
+  */
+typedef enum
+{
+  TMR_CC_CHANNEL_MAPPED_DIRECT           = 0x01, /*!< channel is configured as input, mapped direct */
+  TMR_CC_CHANNEL_MAPPED_INDIRECT         = 0x02, /*!< channel is configured as input, mapped indirect */
+  TMR_CC_CHANNEL_MAPPED_STI              = 0x03  /*!< channel is configured as input, mapped sti */
+} tmr_input_direction_mapped_type;
+
+/**
+  * @brief tmr input divider type
+  */
+typedef enum
+{
+  TMR_CHANNEL_INPUT_DIV_1                = 0x00, /*!< tmr channel input divider 1 */
+  TMR_CHANNEL_INPUT_DIV_2                = 0x01, /*!< tmr channel input divider 2 */
+  TMR_CHANNEL_INPUT_DIV_4                = 0x02, /*!< tmr channel input divider 4 */
+  TMR_CHANNEL_INPUT_DIV_8                = 0x03  /*!< tmr channel input divider 8 */
+} tmr_channel_input_divider_type;
+
+/**
+  * @brief tmr dma request source select type
+  */
+typedef enum
+{
+  TMR_DMA_REQUEST_BY_CHANNEL             = 0x00, /*!< tmr dma request source select channel */
+  TMR_DMA_REQUEST_BY_OVERFLOW            = 0x01  /*!< tmr dma request source select overflow */
+} tmr_dma_request_source_type;
+
+/**
+  * @brief tmr dma request type
+  */
+typedef enum
+{
+  TMR_OVERFLOW_DMA_REQUEST               = 0x00000100, /*!< tmr dma request select overflow */
+  TMR_C1_DMA_REQUEST                     = 0x00000200, /*!< tmr dma request select channel 1 */
+  TMR_C2_DMA_REQUEST                     = 0x00000400, /*!< tmr dma request select channel 2 */
+  TMR_C3_DMA_REQUEST                     = 0x00000800, /*!< tmr dma request select channel 3 */
+  TMR_C4_DMA_REQUEST                     = 0x00001000, /*!< tmr dma request select channel 4 */
+  TMR_HALL_DMA_REQUEST                   = 0x00002000, /*!< tmr dma request select hall */
+  TMR_TRIGGER_DMA_REQUEST                = 0x00004000  /*!< tmr dma request select trigger */
+} tmr_dma_request_type;
+
+/**
+  * @brief tmr event triggered by software type
+  */
+typedef enum
+{
+  TMR_OVERFLOW_SWTRIG                    = 0x00000001, /*!< tmr event triggered by software of overflow */
+  TMR_C1_SWTRIG                          = 0x00000002, /*!< tmr event triggered by software of channel 1 */
+  TMR_C2_SWTRIG                          = 0x00000004, /*!< tmr event triggered by software of channel 2 */
+  TMR_C3_SWTRIG                          = 0x00000008, /*!< tmr event triggered by software of channel 3 */
+  TMR_C4_SWTRIG                          = 0x00000010, /*!< tmr event triggered by software of channel 4 */
+  TMR_HALL_SWTRIG                        = 0x00000020, /*!< tmr event triggered by software of hall */
+  TMR_TRIGGER_SWTRIG                     = 0x00000040, /*!< tmr event triggered by software of trigger */
+  TMR_BRK_SWTRIG                         = 0x00000080  /*!< tmr event triggered by software of brake */
+}tmr_event_trigger_type;
+
+/**
+  * @brief tmr polarity active type
+  */
+typedef enum
+{
+  TMR_POLARITY_ACTIVE_HIGH               = 0x00, /*!< tmr polarity active high */
+  TMR_POLARITY_ACTIVE_LOW                = 0x01, /*!< tmr polarity active low */
+  TMR_POLARITY_ACTIVE_BOTH               = 0x02  /*!< tmr polarity active both high ande low */
+}tmr_polarity_active_type;
+
+/**
+  * @brief tmr external signal divider type
+  */
+typedef enum
+{
+  TMR_ES_FREQUENCY_DIV_1                 = 0x00, /*!< tmr external signal frequency divider 1 */
+  TMR_ES_FREQUENCY_DIV_2                 = 0x01, /*!< tmr external signal frequency divider 2 */
+  TMR_ES_FREQUENCY_DIV_4                 = 0x02, /*!< tmr external signal frequency divider 4 */
+  TMR_ES_FREQUENCY_DIV_8                 = 0x03  /*!< tmr external signal frequency divider 8 */
+}tmr_external_signal_divider_type;
+
+/**
+  * @brief tmr external signal polarity type
+  */
+typedef enum
+{
+  TMR_ES_POLARITY_NON_INVERTED           = 0x00, /*!< tmr external signal polarity non-inerted */
+  TMR_ES_POLARITY_INVERTED               = 0x01  /*!< tmr external signal polarity inerted */
+}tmr_external_signal_polarity_type;
+
+/**
+  * @brief tmr dma transfer length type
+  */
+typedef enum
+{
+  TMR_DMA_TRANSFER_1BYTE                 = 0x00, /*!< tmr dma transfer length 1 byte */
+  TMR_DMA_TRANSFER_2BYTES                = 0x01, /*!< tmr dma transfer length 2 bytes */
+  TMR_DMA_TRANSFER_3BYTES                = 0x02, /*!< tmr dma transfer length 3 bytes */
+  TMR_DMA_TRANSFER_4BYTES                = 0x03, /*!< tmr dma transfer length 4 bytes */
+  TMR_DMA_TRANSFER_5BYTES                = 0x04, /*!< tmr dma transfer length 5 bytes */
+  TMR_DMA_TRANSFER_6BYTES                = 0x05, /*!< tmr dma transfer length 6 bytes */
+  TMR_DMA_TRANSFER_7BYTES                = 0x06, /*!< tmr dma transfer length 7 bytes */
+  TMR_DMA_TRANSFER_8BYTES                = 0x07, /*!< tmr dma transfer length 8 bytes */
+  TMR_DMA_TRANSFER_9BYTES                = 0x08, /*!< tmr dma transfer length 9 bytes */
+  TMR_DMA_TRANSFER_10BYTES               = 0x09, /*!< tmr dma transfer length 10 bytes */
+  TMR_DMA_TRANSFER_11BYTES               = 0x0A, /*!< tmr dma transfer length 11 bytes */
+  TMR_DMA_TRANSFER_12BYTES               = 0x0B, /*!< tmr dma transfer length 12 bytes */
+  TMR_DMA_TRANSFER_13BYTES               = 0x0C, /*!< tmr dma transfer length 13 bytes */
+  TMR_DMA_TRANSFER_14BYTES               = 0x0D, /*!< tmr dma transfer length 14 bytes */
+  TMR_DMA_TRANSFER_15BYTES               = 0x0E, /*!< tmr dma transfer length 15 bytes */
+  TMR_DMA_TRANSFER_16BYTES               = 0x0F, /*!< tmr dma transfer length 16 bytes */
+  TMR_DMA_TRANSFER_17BYTES               = 0x10, /*!< tmr dma transfer length 17 bytes */
+  TMR_DMA_TRANSFER_18BYTES               = 0x11  /*!< tmr dma transfer length 18 bytes */
+}tmr_dma_transfer_length_type;
+
+/**
+  * @brief tmr dma base address type
+  */
+typedef enum
+{
+  TMR_CTRL1_ADDRESS                      = 0x0000, /*!< tmr dma base address ctrl1 */
+  TMR_CTRL2_ADDRESS                      = 0x0001, /*!< tmr dma base address ctrl2 */
+  TMR_STCTRL_ADDRESS                     = 0x0002, /*!< tmr dma base address stctrl */
+  TMR_IDEN_ADDRESS                       = 0x0003, /*!< tmr dma base address iden */
+  TMR_ISTS_ADDRESS                       = 0x0004, /*!< tmr dma base address ists */
+  TMR_SWEVT_ADDRESS                      = 0x0005, /*!< tmr dma base address swevt */
+  TMR_CM1_ADDRESS                        = 0x0006, /*!< tmr dma base address cm1 */
+  TMR_CM2_ADDRESS                        = 0x0007, /*!< tmr dma base address cm2 */
+  TMR_CCTRL_ADDRESS                      = 0x0008, /*!< tmr dma base address cctrl */
+  TMR_CVAL_ADDRESS                       = 0x0009, /*!< tmr dma base address cval */
+  TMR_DIV_ADDRESS                        = 0x000A, /*!< tmr dma base address div */
+  TMR_PR_ADDRESS                         = 0x000B, /*!< tmr dma base address pr */
+  TMR_RPR_ADDRESS                        = 0x000C, /*!< tmr dma base address rpr */
+  TMR_C1DT_ADDRESS                       = 0x000D, /*!< tmr dma base address c1dt */
+  TMR_C2DT_ADDRESS                       = 0x000E, /*!< tmr dma base address c2dt */
+  TMR_C3DT_ADDRESS                       = 0x000F, /*!< tmr dma base address c3dt */
+  TMR_C4DT_ADDRESS                       = 0x0010, /*!< tmr dma base address c4dt */
+  TMR_BRK_ADDRESS                        = 0x0011, /*!< tmr dma base address brake */
+  TMR_DMACTRL_ADDRESS                    = 0x0012  /*!< tmr dma base address dmactrl */
+}tmr_dma_address_type;
+
+/**
+  * @brief tmr brk polarity type
+  */
+typedef enum
+{
+  TMR_BRK_INPUT_ACTIVE_LOW               = 0x00, /*!< tmr brk input channel active low */
+  TMR_BRK_INPUT_ACTIVE_HIGH              = 0x01  /*!< tmr brk input channel active high */
+}tmr_brk_polarity_type;
+
+/**
+  * @brief tmr write protect level type
+  */
+typedef enum
+{
+  TMR_WP_OFF                             = 0x00, /*!< tmr write protect off */
+  TMR_WP_LEVEL_3                         = 0x01, /*!< tmr write protect level 3 */
+  TMR_WP_LEVEL_2                         = 0x02, /*!< tmr write protect level 2 */
+  TMR_WP_LEVEL_1                         = 0x03  /*!< tmr write protect level 1 */
+}tmr_wp_level_type;
+
+/**
+  * @brief tmr output config type
+  */
+typedef struct
+{
+  tmr_output_control_mode_type           oc_mode;             /*!< output channel mode */
+  confirm_state                          oc_idle_state;       /*!< output channel idle state */
+  confirm_state                          occ_idle_state;      /*!< output channel complementary idle state */
+  tmr_output_polarity_type               oc_polarity;         /*!< output channel polarity */
+  tmr_output_polarity_type               occ_polarity;        /*!< output channel complementary polarity */
+  confirm_state                          oc_output_state;     /*!< output channel enable */
+  confirm_state                          occ_output_state;    /*!< output channel complementary enable */
+} tmr_output_config_type;
+
+/**
+  * @brief tmr input capture config type
+  */
+typedef struct
+{
+  tmr_channel_select_type                input_channel_select;   /*!< tmr input channel select */
+  tmr_input_polarity_type                input_polarity_select;  /*!< tmr input polarity select */
+  tmr_input_direction_mapped_type        input_mapped_select;    /*!< tmr channel mapped direct or indirect */
+  uint8_t                                input_filter_value;     /*!< tmr channel filter value */
+} tmr_input_config_type;
+
+/**
+  * @brief tmr brkdt config type
+  */
+typedef struct
+{
+  uint8_t                                deadtime;            /*!< dead-time generator setup */
+  tmr_brk_polarity_type                  brk_polarity;        /*!< tmr brake polarity */
+  tmr_wp_level_type                      wp_level;            /*!< write protect configuration */
+  confirm_state                          auto_output_enable;  /*!< automatic output enable */
+  confirm_state                          fcsoen_state;        /*!< frozen channel status when output enable */
+  confirm_state                          fcsodis_state;       /*!< frozen channel status when output disable */
+  confirm_state                          brk_enable;          /*!< tmr brk enale */
+} tmr_brkdt_config_type;
+
+/**
+  * @brief type define tmr register all
+  */
+typedef struct
+{
+  /**
+    * @brief tmr ctrl1 register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t ctrl1;
+    struct
+    {
+      __IO uint32_t tmren                : 1; /* [0] */
+      __IO uint32_t ovfen                : 1; /* [1] */
+      __IO uint32_t ovfs                 : 1; /* [2] */
+      __IO uint32_t ocmen                : 1; /* [3] */
+      __IO uint32_t cnt_dir              : 3; /* [6:4] */
+      __IO uint32_t prben                : 1; /* [7] */
+      __IO uint32_t clkdiv               : 2; /* [9:8] */
+      __IO uint32_t pmen                 : 1; /* [10] */
+      __IO uint32_t reserved1            : 21;/* [31:11] */
+    } ctrl1_bit;
+  };
+
+  /**
+    * @brief tmr ctrl2 register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t ctrl2;
+    struct
+    {
+      __IO uint32_t cbctrl               : 1; /* [0] */
+      __IO uint32_t reserved1            : 1; /* [1] */
+      __IO uint32_t ccfs                 : 1; /* [2] */
+      __IO uint32_t drs                  : 1; /* [3] */
+      __IO uint32_t ptos                 : 3; /* [6:4] */
+      __IO uint32_t c1insel              : 1; /* [7] */
+      __IO uint32_t c1ios                : 1; /* [8] */
+      __IO uint32_t c1cios               : 1; /* [9] */
+      __IO uint32_t c2ios                : 1; /* [10] */
+      __IO uint32_t c2cios               : 1; /* [11] */
+      __IO uint32_t c3ios                : 1; /* [12] */
+      __IO uint32_t c3cios               : 1; /* [13] */
+      __IO uint32_t c4ios                : 1; /* [14] */
+      __IO uint32_t reserved2            : 17;/* [31:15] */
+    } ctrl2_bit;
+  };
+
+  /**
+    * @brief tmr smc register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t stctrl;
+    struct
+    {
+      __IO uint32_t smsel                : 3; /* [2:0] */
+      __IO uint32_t reserved1            : 1; /* [3] */
+      __IO uint32_t stis                 : 3; /* [6:4] */
+      __IO uint32_t sts                  : 1; /* [7] */
+      __IO uint32_t esf                  : 4; /* [11:8] */
+      __IO uint32_t esdiv                : 2; /* [13:12] */
+      __IO uint32_t ecmben               : 1; /* [14] */
+      __IO uint32_t esp                  : 1; /* [15] */
+      __IO uint32_t reserved2            : 16;/* [31:16] */
+    } stctrl_bit;
+  };
+
+  /**
+    * @brief tmr die register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t iden;
+    struct
+    {
+      __IO uint32_t ovfien               : 1; /* [0] */
+      __IO uint32_t c1ien                : 1; /* [1] */
+      __IO uint32_t c2ien                : 1; /* [2] */
+      __IO uint32_t c3ien                : 1; /* [3] */
+      __IO uint32_t c4ien                : 1; /* [4] */
+      __IO uint32_t hallien              : 1; /* [5] */
+      __IO uint32_t tien                 : 1; /* [6] */
+      __IO uint32_t brkie                : 1; /* [7] */
+      __IO uint32_t ovfden               : 1; /* [8] */
+      __IO uint32_t c1den                : 1; /* [9] */
+      __IO uint32_t c2den                : 1; /* [10] */
+      __IO uint32_t c3den                : 1; /* [11] */
+      __IO uint32_t c4den                : 1; /* [12] */
+      __IO uint32_t hallde               : 1; /* [13] */
+      __IO uint32_t tden                 : 1; /* [14] */
+      __IO uint32_t reserved1            : 17;/* [31:15] */
+    } iden_bit;
+  };
+
+  /**
+    * @brief tmr ists register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t ists;
+    struct
+    {
+      __IO uint32_t ovfif                : 1; /* [0] */
+      __IO uint32_t c1if                 : 1; /* [1] */
+      __IO uint32_t c2if                 : 1; /* [2] */
+      __IO uint32_t c3if                 : 1; /* [3] */
+      __IO uint32_t c4if                 : 1; /* [4] */
+      __IO uint32_t hallif               : 1; /* [5] */
+      __IO uint32_t trgif                : 1; /* [6] */
+      __IO uint32_t brkif                : 1; /* [7] */
+      __IO uint32_t reserved1            : 1; /* [8] */
+      __IO uint32_t c1rf                 : 1; /* [9] */
+      __IO uint32_t c2rf                 : 1; /* [10] */
+      __IO uint32_t c3rf                 : 1; /* [11] */
+      __IO uint32_t c4rf                 : 1; /* [12] */
+      __IO uint32_t reserved2            : 19;/* [31:13] */
+    } ists_bit;
+  };
+
+  /**
+    * @brief tmr eveg register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t swevt;
+    struct
+    {
+      __IO uint32_t  ovfswtr             : 1; /* [0] */
+      __IO uint32_t  c1swtr              : 1; /* [1] */
+      __IO uint32_t  c2swtr              : 1; /* [2] */
+      __IO uint32_t  c3swtr              : 1; /* [3] */
+      __IO uint32_t  c4swtr              : 1; /* [4] */
+      __IO uint32_t  hallswtr            : 1; /* [5] */
+      __IO uint32_t  trgswtr             : 1; /* [6] */
+      __IO uint32_t  brkswtr             : 1; /* [7] */
+      __IO uint32_t  reserved            : 24;/* [31:8] */
+    } swevt_bit;
+  };
+
+  /**
+    * @brief tmr ccm1 register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t cm1;
+
+    /**
+     * @brief channel mode
+     */
+    struct
+    {
+      __IO uint32_t c1c                  : 2; /* [1:0] */
+      __IO uint32_t c1oien               : 1; /* [2] */
+      __IO uint32_t c1oben               : 1; /* [3] */
+      __IO uint32_t c1octrl              : 3; /* [6:4] */
+      __IO uint32_t c1osen               : 1; /* [7] */
+      __IO uint32_t c2c                  : 2; /* [9:8] */
+      __IO uint32_t c2oien               : 1; /* [10] */
+      __IO uint32_t c2oben               : 1; /* [11] */
+      __IO uint32_t c2octrl              : 3; /* [14:12] */
+      __IO uint32_t c2osen               : 1; /* [15] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } cm1_output_bit;
+
+    /**
+      * @brief input capture mode
+      */
+    struct
+    {
+      __IO uint32_t c1c                  : 2; /* [1:0] */
+      __IO uint32_t c1idiv               : 2; /* [3:2] */
+      __IO uint32_t c1df                 : 4; /* [7:4] */
+      __IO uint32_t c2c                  : 2; /* [9:8] */
+      __IO uint32_t c2idiv               : 2; /* [11:10] */
+      __IO uint32_t c2df                 : 4; /* [15:12] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } cm1_input_bit;
+  };
+
+  /**
+    * @brief tmr ccm2 register, offset:0x1C
+    */
+  union
+  {
+    __IO uint32_t cm2;
+
+    /**
+      * @brief channel mode
+      */
+    struct
+    {
+      __IO uint32_t c3c                  : 2; /* [1:0] */
+      __IO uint32_t c3oien               : 1; /* [2] */
+      __IO uint32_t c3oben               : 1; /* [3] */
+      __IO uint32_t c3octrl              : 3; /* [6:4] */
+      __IO uint32_t c3osen               : 1; /* [7] */
+      __IO uint32_t c4c                  : 2; /* [9:8] */
+      __IO uint32_t c4oien               : 1; /* [10] */
+      __IO uint32_t c4oben               : 1; /* [11] */
+      __IO uint32_t c4octrl              : 3; /* [14:12] */
+      __IO uint32_t c4osen               : 1; /* [15] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } cm2_output_bit;
+
+    /**
+      * @brief input capture mode
+      */
+    struct
+    {
+      __IO uint32_t c3c                  : 2; /* [1:0] */
+      __IO uint32_t c3idiv               : 2; /* [3:2] */
+      __IO uint32_t c3df                 : 4; /* [7:4] */
+      __IO uint32_t c4c                  : 2; /* [9:8] */
+      __IO uint32_t c4idiv               : 2; /* [11:10] */
+      __IO uint32_t c4df                 : 4; /* [15:12] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } cm2_input_bit;
+  };
+
+  /**
+    * @brief tmr cce register, offset:0x20
+    */
+  union
+  {
+    uint32_t cctrl;
+    struct
+    {
+      __IO uint32_t c1en                 : 1; /* [0] */
+      __IO uint32_t c1p                  : 1; /* [1] */
+      __IO uint32_t c1cen                : 1; /* [2] */
+      __IO uint32_t c1cp                 : 1; /* [3] */
+      __IO uint32_t c2en                 : 1; /* [4] */
+      __IO uint32_t c2p                  : 1; /* [5] */
+      __IO uint32_t c2cen                : 1; /* [6] */
+      __IO uint32_t c2cp                 : 1; /* [7] */
+      __IO uint32_t c3en                 : 1; /* [8] */
+      __IO uint32_t c3p                  : 1; /* [9] */
+      __IO uint32_t c3cen                : 1; /* [10] */
+      __IO uint32_t c3cp                 : 1; /* [11] */
+      __IO uint32_t c4en                 : 1; /* [12] */
+      __IO uint32_t c4p                  : 1; /* [13] */
+      __IO uint32_t reserved1            : 18;/* [31:14] */
+    } cctrl_bit;
+  };
+
+  /**
+    * @brief tmr cnt register, offset:0x24
+    */
+  union
+  {
+    __IO uint32_t cval;
+    struct
+    {
+      __IO uint32_t cval                 : 32;/* [31:0] */
+    } cval_bit;
+  };
+
+  /**
+    * @brief tmr div, offset:0x28
+    */
+  union
+  {
+    __IO uint32_t div;
+    struct
+    {
+      __IO uint32_t div                  : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } div_bit;
+  };
+
+  /**
+    * @brief tmr pr register, offset:0x2C
+    */
+  union
+  {
+    __IO  uint32_t pr;
+    struct
+    {
+      __IO uint32_t pr                   : 32;/* [31:0] */
+    } pr_bit;
+  };
+
+  /**
+    * @brief tmr rpr register, offset:0x30
+    */
+  union
+  {
+    __IO uint32_t rpr;
+    struct
+    {
+      __IO uint32_t rpr                  : 8; /* [7:0] */
+      __IO uint32_t reserved1            : 24;/* [31:8] */
+    } rpr_bit;
+  };
+
+  /**
+    * @brief tmr c1dt register, offset:0x34
+    */
+  union
+  {
+    uint32_t c1dt;
+    struct
+    {
+      __IO uint32_t c1dt                 : 32;/* [31:0] */
+    } c1dt_bit;
+  };
+
+  /**
+    * @brief tmr c2dt register, offset:0x38
+    */
+  union
+  {
+    uint32_t c2dt;
+    struct
+    {
+      __IO uint32_t c2dt                 : 32;/* [31:0] */
+    } c2dt_bit;
+  };
+
+  /**
+    * @brief tmr c3dt register, offset:0x3C
+    */
+  union
+  {
+    __IO uint32_t c3dt;
+    struct
+    {
+      __IO uint32_t c3dt                 : 32;/* [31:0] */
+    } c3dt_bit;
+  };
+
+  /**
+    * @brief tmr c4dt register, offset:0x40
+    */
+  union
+  {
+    __IO uint32_t c4dt;
+    struct
+    {
+      __IO uint32_t c4dt                 : 32;/* [31:0] */
+    } c4dt_bit;
+  };
+
+  /**
+    * @brief tmr brk register, offset:0x44
+    */
+  union
+  {
+    __IO uint32_t brk;
+    struct
+    {
+      __IO uint32_t dtc                  : 8; /* [7:0] */
+      __IO uint32_t wpc                  : 2; /* [9:8] */
+      __IO uint32_t fcsodis              : 1; /* [10] */
+      __IO uint32_t fcsoen               : 1; /* [11] */
+      __IO uint32_t brken                : 1; /* [12] */
+      __IO uint32_t brkv                 : 1; /* [13] */
+      __IO uint32_t aoen                 : 1; /* [14] */
+      __IO uint32_t oen                  : 1; /* [15] */
+      __IO uint32_t reserved1            : 16; /* [31:16] */
+    } brk_bit;
+  };
+  /**
+    * @brief tmr dmactrl register, offset:0x48
+    */
+  union
+  {
+    __IO uint32_t dmactrl;
+    struct
+    {
+      __IO uint32_t addr                 : 5; /* [4:0] */
+      __IO uint32_t reserved1            : 3; /* [7:5] */
+      __IO uint32_t dtb                  : 5; /* [12:8] */
+      __IO uint32_t reserved2            : 19;/* [31:13] */
+    } dmactrl_bit;
+  };
+
+  /**
+    * @brief tmr dmadt register, offset:0x4C
+    */
+  union
+  {
+    __IO uint32_t dmadt;
+    struct
+    {
+      __IO uint32_t dmadt                : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } dmadt_bit;
+  };
+
+} tmr_type;
+
+/**
+  * @}
+  */
+
+#define TMR1                             ((tmr_type *) TMR1_BASE)
+#define TMR2                             ((tmr_type *) TMR2_BASE)
+#define TMR3                             ((tmr_type *) TMR3_BASE)
+#define TMR4                             ((tmr_type *) TMR4_BASE)
+#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \
+    defined (AT32F413Kx)
+#define TMR5                             ((tmr_type *) TMR5_BASE)
+#if defined (AT32F413CCU7) || defined (AT32F413CCT7) || defined (AT32F413RCT7)
+#define TMR8                             ((tmr_type *) TMR8_BASE)
+#endif
+#define TMR9                             ((tmr_type *) TMR9_BASE)
+#define TMR10                            ((tmr_type *) TMR10_BASE)
+#define TMR11                            ((tmr_type *) TMR11_BASE)
+#endif
+
+/** @defgroup TMR_exported_functions
+  * @{
+  */
+
+void tmr_reset(tmr_type *tmr_x);
+void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
+void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
+void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
+void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
+void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
+void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
+void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
+void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
+uint32_t tmr_counter_value_get(tmr_type *tmr_x);
+void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
+uint32_t tmr_div_value_get(tmr_type *tmr_x);
+void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+                               tmr_output_config_type *tmr_output_struct);
+void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+                                    tmr_output_control_mode_type oc_mode);
+void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
+uint32_t tmr_period_value_get(tmr_type *tmr_x);
+void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+                           uint32_t tmr_channel_value);
+uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
+void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+                                   confirm_state new_state);
+void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+                                        confirm_state new_state);
+void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+                                   confirm_state new_state);
+void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
+void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
+void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+                            tmr_channel_input_divider_type divider_factor);
+void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
+void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+                                  uint16_t filter_value);
+void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+                          tmr_channel_input_divider_type divider_factor);
+void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect);
+void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+                                   tmr_channel_input_divider_type divider_factor);
+void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
+void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
+void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
+void tmr_hall_select(tmr_type *tmr_x,  confirm_state new_state);
+void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
+void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
+void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
+void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
+flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
+void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
+void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
+void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_internal_clock_set(tmr_type *tmr_x);
+
+void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+                                     tmr_polarity_active_type oc_polarity);
+void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+                               tmr_external_signal_polarity_type  es_polarity, uint16_t es_filter);
+void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+                                     tmr_external_signal_polarity_type  es_polarity, uint16_t es_filter);
+void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+                                     tmr_external_signal_polarity_type  es_polarity, uint16_t es_filter);
+void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
+                             ic1_polarity, tmr_input_polarity_type ic2_polarity);
+void tmr_force_output_set(tmr_type *tmr_x,  tmr_channel_select_type tmr_channel, \
+                          tmr_force_output_type force_output);
+void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
+                            tmr_dma_address_type dma_base_address);
+void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_usart.h

@@ -0,0 +1,377 @@
+/**
+  **************************************************************************
+  * @file     at32f413_usart.h
+  * @brief    at32f413 usart header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_USART_H
+#define __AT32F413_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */
+
+/** @defgroup USART_flags_definition
+  * @brief usart flag
+  * @{
+  */
+
+#define USART_PERR_FLAG                  ((uint32_t)0x00000001) /*!< usart parity error flag */
+#define USART_FERR_FLAG                  ((uint32_t)0x00000002) /*!< usart framing error flag */
+#define USART_NERR_FLAG                  ((uint32_t)0x00000004) /*!< usart noise error flag */
+#define USART_ROERR_FLAG                 ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
+#define USART_IDLEF_FLAG                 ((uint32_t)0x00000010) /*!< usart idle flag */
+#define USART_RDBF_FLAG                  ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
+#define USART_TDC_FLAG                   ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
+#define USART_TDBE_FLAG                  ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
+#define USART_BFF_FLAG                   ((uint32_t)0x00000100) /*!< usart break frame flag */
+#define USART_CTSCF_FLAG                 ((uint32_t)0x00000200) /*!< usart cts change flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_interrupts_definition
+  * @brief usart interrupt
+  * @{
+  */
+
+#define USART_IDLE_INT                   MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
+#define USART_RDBF_INT                   MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
+#define USART_TDC_INT                    MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
+#define USART_TDBE_INT                   MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
+#define USART_PERR_INT                   MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
+#define USART_BF_INT                     MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
+#define USART_ERR_INT                    MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
+#define USART_CTSCF_INT                  MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_exported_types
+  * @{
+  */
+
+/**
+  * @brief  usart parity selection type
+  */
+typedef enum
+{
+  USART_PARITY_NONE                      = 0x00, /*!< usart no parity */
+  USART_PARITY_EVEN                      = 0x01, /*!< usart even parity */
+  USART_PARITY_ODD                       = 0x02  /*!< usart odd parity */
+} usart_parity_selection_type;
+
+/**
+  * @brief  usart wakeup mode type
+  */
+typedef enum
+{
+  USART_WAKEUP_BY_IDLE_FRAME             = 0x00, /*!< usart wakeup by idle frame */
+  USART_WAKEUP_BY_MATCHING_ID            = 0x01  /*!< usart wakeup by matching id */
+} usart_wakeup_mode_type;
+
+/**
+  * @brief  usart data bit num type
+  */
+typedef enum
+{
+  USART_DATA_8BITS                       = 0x00, /*!< usart data size is 8 bits */
+  USART_DATA_9BITS                       = 0x01  /*!< usart data size is 9 bits */
+} usart_data_bit_num_type;
+
+/**
+  * @brief  usart break frame bit num type
+  */
+typedef enum
+{
+  USART_BREAK_10BITS                     = 0x00, /*!< usart lin mode berak frame detection 10 bits */
+  USART_BREAK_11BITS                     = 0x01  /*!< usart lin mode berak frame detection 11 bits */
+} usart_break_bit_num_type;
+
+/**
+  * @brief  usart phase of the clock type
+  */
+typedef enum
+{
+  USART_CLOCK_PHASE_1EDGE                = 0x00, /*!< usart data capture is done on the clock leading edge */
+  USART_CLOCK_PHASE_2EDGE                = 0x01  /*!< usart data capture is done on the clock trailing edge */
+} usart_clock_phase_type;
+
+/**
+  * @brief  usart polarity of the clock type
+  */
+typedef enum
+{
+  USART_CLOCK_POLARITY_LOW               = 0x00, /*!< usart clock stay low level outside transmission window */
+  USART_CLOCK_POLARITY_HIGH              = 0x01  /*!< usart clock stay high level outside transmission window */
+} usart_clock_polarity_type;
+
+/**
+  * @brief  usart last bit clock pulse type
+  */
+typedef enum
+{
+  USART_CLOCK_LAST_BIT_NONE              = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
+  USART_CLOCK_LAST_BIT_OUTPUT            = 0x01  /*!< usart clock pulse of the last data bit is outputted */
+} usart_lbcp_type;
+
+/**
+  * @brief  usart stop bit num type
+  */
+typedef enum
+{
+  USART_STOP_1_BIT                       = 0x00, /*!< usart stop bits num is 1 */
+  USART_STOP_0_5_BIT                     = 0x01, /*!< usart stop bits num is 0.5 */
+  USART_STOP_2_BIT                       = 0x02, /*!< usart stop bits num is 2 */
+  USART_STOP_1_5_BIT                     = 0x03  /*!< usart stop bits num is 1.5 */
+} usart_stop_bit_num_type;
+
+/**
+  * @brief  usart hardware flow control type
+  */
+typedef enum
+{
+  USART_HARDWARE_FLOW_NONE               = 0x00, /*!< usart without hardware flow */
+  USART_HARDWARE_FLOW_RTS                = 0x01, /*!< usart hardware flow only rts */
+  USART_HARDWARE_FLOW_CTS                = 0x02, /*!< usart hardware flow only cts */
+  USART_HARDWARE_FLOW_RTS_CTS            = 0x03  /*!< usart hardware flow both rts and cts */
+} usart_hardware_flow_control_type;
+
+/**
+  * @brief type define usart register all
+  */
+typedef struct
+{
+  /**
+    * @brief usart sts register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t sts;
+    struct
+    {
+      __IO uint32_t perr                 : 1; /* [0] */
+      __IO uint32_t ferr                 : 1; /* [1] */
+      __IO uint32_t nerr                 : 1; /* [2] */
+      __IO uint32_t roerr                : 1; /* [3] */
+      __IO uint32_t idlef                : 1; /* [4] */
+      __IO uint32_t rdbf                 : 1; /* [5] */
+      __IO uint32_t tdc                  : 1; /* [6] */
+      __IO uint32_t tdbe                 : 1; /* [7] */
+      __IO uint32_t bff                  : 1; /* [8] */
+      __IO uint32_t ctscf                : 1; /* [9] */
+      __IO uint32_t reserved1            : 22;/* [31:10] */
+    } sts_bit;
+  };
+
+  /**
+    * @brief usart dt register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t dt;
+    struct
+    {
+      __IO uint32_t dt                   : 9; /* [8:0] */
+      __IO uint32_t reserved1            : 23;/* [31:9] */
+    } dt_bit;
+  };
+
+  /**
+    * @brief usart baudr register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t baudr;
+    struct
+    {
+      __IO uint32_t div                  : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } baudr_bit;
+  };
+
+  /**
+    * @brief usart ctrl1 register, offset:0x0C
+    */
+  union
+  {
+    __IO uint32_t ctrl1;
+    struct
+    {
+      __IO uint32_t sbf                  : 1; /* [0] */
+      __IO uint32_t rm                   : 1; /* [1] */
+      __IO uint32_t ren                  : 1; /* [2] */
+      __IO uint32_t ten                  : 1; /* [3] */
+      __IO uint32_t idleien              : 1; /* [4] */
+      __IO uint32_t rdbfien              : 1; /* [5] */
+      __IO uint32_t tdcien               : 1; /* [6] */
+      __IO uint32_t tdbeien              : 1; /* [7] */
+      __IO uint32_t perrien              : 1; /* [8] */
+      __IO uint32_t psel                 : 1; /* [9] */
+      __IO uint32_t pen                  : 1; /* [10] */
+      __IO uint32_t wum                  : 1; /* [11] */
+      __IO uint32_t dbn                  : 1; /* [12] */
+      __IO uint32_t uen                  : 1; /* [13] */
+      __IO uint32_t reserved1            : 18;/* [31:14] */
+    } ctrl1_bit;
+  };
+
+  /**
+    * @brief usart ctrl2 register, offset:0x10
+    */
+  union
+  {
+    __IO uint32_t ctrl2;
+    struct
+    {
+      __IO uint32_t id                   : 4; /* [3:0] */
+      __IO uint32_t reserved1            : 1; /* [4] */
+      __IO uint32_t bfbn                 : 1; /* [5] */
+      __IO uint32_t bfien                : 1; /* [6] */
+      __IO uint32_t reserved2            : 1; /* [7] */
+      __IO uint32_t lbcp                 : 1; /* [8] */
+      __IO uint32_t clkpha               : 1; /* [9] */
+      __IO uint32_t clkpol               : 1; /* [10] */
+      __IO uint32_t clken                : 1; /* [11] */
+      __IO uint32_t stopbn               : 2; /* [13:12] */
+      __IO uint32_t linen                : 1; /* [14] */
+      __IO uint32_t reserved3            : 17;/* [31:15] */
+    } ctrl2_bit;
+  };
+
+  /**
+    * @brief usart ctrl3 register, offset:0x14
+    */
+  union
+  {
+    __IO uint32_t ctrl3;
+    struct
+    {
+      __IO uint32_t errien               : 1; /* [0] */
+      __IO uint32_t irdaen               : 1; /* [1] */
+      __IO uint32_t irdalp               : 1; /* [2] */
+      __IO uint32_t slben                : 1; /* [3] */
+      __IO uint32_t scnacken             : 1; /* [4] */
+      __IO uint32_t scmen                : 1; /* [5] */
+      __IO uint32_t dmaren               : 1; /* [6] */
+      __IO uint32_t dmaten               : 1; /* [7] */
+      __IO uint32_t rtsen                : 1; /* [8] */
+      __IO uint32_t ctsen                : 1; /* [9] */
+      __IO uint32_t ctscfien             : 1; /* [10] */
+      __IO uint32_t reserved1            : 21;/* [31:11] */
+    } ctrl3_bit;
+  };
+
+  /**
+    * @brief usart gdiv register, offset:0x18
+    */
+  union
+  {
+    __IO uint32_t gdiv;
+    struct
+    {
+      __IO uint32_t isdiv                : 8; /* [7:0] */
+      __IO uint32_t scgt                 : 8; /* [15:8] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } gdiv_bit;
+  };
+} usart_type;
+
+/**
+  * @}
+  */
+
+#define USART1                           ((usart_type *) USART1_BASE)
+#define USART2                           ((usart_type *) USART2_BASE)
+#if defined (AT32F413Rx) || defined (AT32F413Cx) || defined (AT32FEBKC8T7)
+#define USART3                           ((usart_type *) USART3_BASE)
+#endif
+#if defined (AT32F413Rx)
+#define UART4                            ((usart_type *) UART4_BASE)
+#define UART5                            ((usart_type *) UART5_BASE)
+#endif
+
+/** @defgroup USART_exported_functions
+  * @{
+  */
+
+void usart_reset(usart_type* usart_x);
+void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
+void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
+void usart_enable(usart_type* usart_x, confirm_state new_state);
+void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
+void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
+void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
+void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
+void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
+void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
+void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
+void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
+void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
+void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
+void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
+void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_data_transmit(usart_type* usart_x, uint16_t data);
+uint16_t usart_data_receive(usart_type* usart_x);
+void usart_break_send(usart_type* usart_x);
+void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
+void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
+void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
+void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
+void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
+void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
+flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
+void usart_flag_clear(usart_type* usart_x, uint32_t flag);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_usb.h

@@ -0,0 +1,709 @@
+/**
+  **************************************************************************
+  * @file     at32f413_usb.h
+  * @brief    at32f413 usb header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup USB
+  * @{
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_USB_H
+#define __AT32F413_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+
+
+/** @defgroup USB_interrupts_definition
+  * @brief usb interrupt mask
+  * @{
+  */
+
+#define USB_LSOF_INT                     ((uint32_t)0x00000100) /*!< usb lost sof interrupt */
+#define USB_SOF_INT                      ((uint32_t)0x00000200) /*!< usb sof interrupt */
+#define USB_RST_INT                      ((uint32_t)0x00000400) /*!< usb reset interrupt */
+#define USB_SP_INT                       ((uint32_t)0x00000800) /*!< usb suspend interrupt */
+#define USB_WK_INT                       ((uint32_t)0x00001000) /*!< usb wakeup interrupt */
+#define USB_BE_INT                       ((uint32_t)0x00002000) /*!< usb bus error interrupt */
+#define USB_UCFOR_INT                    ((uint32_t)0x00004000) /*!< usb core fifo overrun interrupt */
+#define USB_TC_INT                       ((uint32_t)0x00008000) /*!< usb transmission completed interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup USB_interrupt_flags_definition
+  * @brief usb interrupt flag
+  * @{
+  */
+
+#define USB_EPT_NUM_FLAG                 ((uint32_t)0x0000000F) /*!< usb endpoint number */
+#define USB_INOUT_FLAG                   ((uint32_t)0x00000010) /*!< usb in/out transcation flag */
+#define USB_LSOF_FLAG                    ((uint32_t)0x00000100) /*!< usb lost sof flag */
+#define USB_SOF_FLAG                     ((uint32_t)0x00000200) /*!< usb sof flag */
+#define USB_RST_FLAG                     ((uint32_t)0x00000400) /*!< usb reset flag */
+#define USB_SP_FLAG                      ((uint32_t)0x00000800) /*!< usb suspend flag */
+#define USB_WK_FLAG                      ((uint32_t)0x00001000) /*!< usb wakeup flag */
+#define USB_BE_FLAG                      ((uint32_t)0x00002000) /*!< usb bus error flag */
+#define USB_UCFOR_FLAG                   ((uint32_t)0x00004000) /*!< usb core fifo overrun flag */
+#define USB_TC_FLAG                      ((uint32_t)0x00008000) /*!< usb transmission completed flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup USB_endpoint_register_bit_definition
+  * @brief usb endpoint register bit define
+  * @{
+  */
+
+#define USB_EPTADDR                      ((uint32_t)0x0000000F) /*!< usb endpoint address */
+#define USB_TXSTS                        ((uint32_t)0x00000030) /*!< usb tx status */
+#define USB_TXDTS                        ((uint32_t)0x00000040) /*!< usb tx data toggle synchronization */
+#define USB_TXTC                         ((uint32_t)0x00000080) /*!< usb tx transcation completed */
+#define USB_EXF                          ((uint32_t)0x00000100) /*!< usb endpoint extend funtion */
+#define USB_TRANS_TYPE                   ((uint32_t)0x00000600) /*!< usb transfer type */
+#define USB_SETUPTC                      ((uint32_t)0x00000800) /*!< usb setup transcation completed */
+#define USB_RXSTS                        ((uint32_t)0x00003000) /*!< usb rx status */
+#define USB_RXDTS                        ((uint32_t)0x00004000) /*!< usb rx data toggle synchronization */
+#define USB_RXTC                         ((uint32_t)0x00008000) /*!< usb rx transcation completed */
+
+#define USB_EPT_BIT_MASK                 (uint32_t)(USB_TXTC | USB_SETUPTC | USB_EPTADDR | USB_EXF | USB_RXTC | USB_TRANS_TYPE) /*!< usb bit mask */
+#define USB_TX_MASK                      (USB_TXSTS | USB_EPT_BIT_MASK) /*!< usb tx mask */
+#define USB_RX_MASK                      (USB_RXSTS | USB_EPT_BIT_MASK) /*!< usb rx mask */
+
+/**
+  * @}
+  */
+
+/** @defgroup USB_endpoint_tx_and_rx_status_definition
+  * @brief usb endpoint tx and rx status
+  * @{
+  */
+
+#define USB_TX_DISABLE                   ((uint32_t)0x00000000) /*!< usb tx status disable */
+#define USB_TX_STALL                     ((uint32_t)0x00000010) /*!< usb tx status stall */
+#define USB_TX_NAK                       ((uint32_t)0x00000020) /*!< usb tx status nak */
+#define USB_TX_VALID                     ((uint32_t)0x00000030) /*!< usb tx status valid */
+
+#define USB_TXDTS0                       ((uint32_t)0x00000010) /*!< usb tx data toggle bit 0 */
+#define USB_TXDTS1                       ((uint32_t)0x00000020) /*!< usb tx data toggle bit 1 */
+
+#define USB_RX_DISABLE                   ((uint32_t)0x00000000) /*!< usb rx status disable */
+#define USB_RX_STALL                     ((uint32_t)0x00001000) /*!< usb rx status stall */
+#define USB_RX_NAK                       ((uint32_t)0x00002000) /*!< usb rx status nak */
+#define USB_RX_VALID                     ((uint32_t)0x00003000) /*!< usb rx status valid */
+
+#define USB_RXDTS0                       ((uint32_t)0x00001000) /*!< usb rx data toggle bit 0 */
+#define USB_RXDTS1                       ((uint32_t)0x00002000) /*!< usb rx data toggle bit 1 */
+
+/**
+  * @}
+  */
+
+/** @defgroup USB_device_endpoint_register_type_definition
+  * @brief usb device endpoint register type define
+  * @{
+  */
+
+#define USB_EPT_CONTROL                  ((uint32_t)0x00000200) /*!< usb endpoint transfer type control */
+#define USB_EPT_BULK                     ((uint32_t)0x00000000) /*!< usb endpoint transfer type bulk */
+#define USB_EPT_INT                      ((uint32_t)0x00000600) /*!< usb endpoint transfer type interrupt */
+#define USB_EPT_ISO                      ((uint32_t)0x00000400) /*!< usb endpoint transfer type iso */
+
+/**
+  * @}
+  */
+
+/** @defgroup USB_buffer_table_default_offset_address_definition
+  * @brief usb buffer table default offset address
+  * @{
+  */
+
+#define USB_BUFFER_TABLE_ADDRESS          0x0000 /*!< usb buffer table address */
+
+/**
+  * @}
+  */
+
+/** @defgroup USB_packet_buffer_start_address_definition
+  * @brief usb packet buffer start address
+  * @{
+  */
+
+#define USB_PACKET_BUFFER_ADDRESS         0x40006000 /*!< usb buffer address */
+#define USB_PACKET_BUFFER_ADDRESS_EX      0x40007800 /*!< usb buffer extend address */
+
+/**
+  * @}
+  */
+
+/** @defgroup USB_exported_enum_types
+  * @{
+  */
+
+/**
+  * @brief usb endpoint number define
+  */
+typedef enum
+{
+  USB_EPT0                               = 0x00, /*!< usb endpoint 0 */
+  USB_EPT1                               = 0x01, /*!< usb endpoint 1 */
+  USB_EPT2                               = 0x02, /*!< usb endpoint 2 */
+  USB_EPT3                               = 0x03, /*!< usb endpoint 3 */
+  USB_EPT4                               = 0x04, /*!< usb endpoint 4 */
+  USB_EPT5                               = 0x05, /*!< usb endpoint 5 */
+  USB_EPT6                               = 0x06, /*!< usb endpoint 6 */
+  USB_EPT7                               = 0x07  /*!< usb endpoint 7 */
+} usb_ept_number_type;
+
+/**
+  * @brief usb endpoint max num define
+  */
+#ifndef USB_EPT_MAX_NUM
+#define USB_EPT_MAX_NUM                   8  /*!< usb device support endpoint number */
+#endif
+/**
+  * @brief endpoint transfer type define
+  */
+typedef enum
+{
+  EPT_CONTROL_TYPE                       = 0x00, /*!< usb transfer type control */
+  EPT_BULK_TYPE                          = 0x01, /*!< usb transfer type bulk */
+  EPT_INT_TYPE                           = 0x02, /*!< usb transfer type interrut */
+  EPT_ISO_TYPE                           = 0x03  /*!< usb transfer type iso */
+}ept_trans_type;
+
+/**
+  * @brief endpoint endpoint direction define
+  */
+typedef enum
+{
+  EPT_IN                                 = 0x00, /*!< usb endpoint direction in */
+  EPT_OUT                                = 0x01  /*!< usb endpoint direction out */
+}ept_inout_type;
+
+/**
+  * @brief data transfer direction
+  */
+typedef enum
+{
+  DATA_TRANS_OUT                         = 0x00, /*!< usb data transfer direction out */
+  DATA_TRANS_IN                          = 0x01  /*!< usb data transfer direction in */
+}data_trans_dir;
+
+/**
+  * @brief usb clock select
+  */
+typedef enum
+{
+  USB_CLK_HICK,
+  USB_CLK_HEXT
+}usb_clk48_s;
+/**
+  * @}
+  */
+
+/** @defgroup USB_macro_definition
+  * @{
+  */
+
+/**
+  * @brief  set usb endpoint tx status
+  * @param  ept_num: endpoint number
+  * @param  new_sts: the new tx status of this endpoint number
+  * @retval none
+  */
+#define USB_SET_TXSTS(ept_num, new_sts) { \
+  register uint16_t epsts = (USB->ept[ept_num]) & USB_TX_MASK; \
+  if((new_sts & USB_TXDTS0) != 0)                    \
+    epsts ^= USB_TXDTS0;                             \
+  if((new_sts & USB_TXDTS1) != 0)                    \
+    epsts ^= USB_TXDTS1;                             \
+  USB->ept[ept_num] = epsts | USB_RXTC | USB_TXTC; \
+}
+
+/**
+  * @brief  set usb endpoint rx status
+  * @param  ept_num: endpoint number
+  * @param  new_sts: the new rx status of this endpoint number
+  * @retval none
+  */
+#define USB_SET_RXSTS(ept_num, new_sts) { \
+  register uint16_t epsts = (USB->ept[ept_num]) & USB_RX_MASK; \
+  if((new_sts & USB_RXDTS0) != 0) \
+    epsts ^= USB_RXDTS0; \
+  if((new_sts & USB_RXDTS1) != 0) \
+    epsts ^= USB_RXDTS1; \
+  USB->ept[ept_num] = epsts | USB_RXTC | USB_TXTC; \
+}
+
+/**
+  * @brief  get usb endpoint tx/rx length address
+  * @param  eptn: endpoint number
+  * @retval the length address of tx/rx
+  */
+#define GET_TX_LEN_ADDR(eptn) (uint32_t *)((USB->buftbl + eptn * 8 + 2) * 2 + g_usb_packet_address)
+#define GET_RX_LEN_ADDR(eptn) (uint32_t *)((USB->buftbl + eptn * 8 + 6) * 2 + g_usb_packet_address)
+
+/**
+  * @brief  get usb endpoint tx/rx data length
+  * @param  eptn: endpoint number
+  * @retval the length of tx/rx
+  */
+#define USB_GET_TX_LEN(eptn)  ((uint16_t)(*GET_TX_LEN_ADDR(eptn)) & 0x3ff)
+#define USB_GET_RX_LEN(eptn)  ((uint16_t)(*GET_RX_LEN_ADDR(eptn)) & 0x3ff)
+
+/**
+  * @brief  double buffer mode get endpoint buf0/buf1 data length
+  * @param  eptn: endpoint number
+  * @retval the length of buf0/buf1
+  */
+#define USB_DBUF0_GET_LEN(eptn) USB_GET_TX_LEN(eptn)
+#define USB_DBUF1_GET_LEN(eptn) USB_GET_RX_LEN(eptn)
+
+/**
+  * @brief  set usb length of rx buffer
+  * @param  reg: usb rx length register
+  * @param  len: rx max length
+  * @param  blks: number of blocks
+  */
+#define BLK32(reg, len, blks) { \
+  blks = (len) >> 5; \
+  if(((len) & 0x1F) == 0) \
+    blks --; \
+  *reg = ((uint16_t)((blks) << 10) | 0x8000); \
+}
+
+#define BLK2(reg, len, blks) { \
+  blks = (len) >> 1; \
+  if(((len) & 0x1) == 0) \
+    blks ++; \
+  *reg = (uint16_t)((blks) << 10); \
+}
+
+#define USB_SET_RXLEN_REG(reg, len) { \
+  uint16_t blks;                         \
+  if(len > 62)                         \
+  {                                      \
+    BLK32(reg, len, blks);             \
+  }                                      \
+  else                                   \
+  {                                      \
+    BLK2(reg, len, blks);              \
+  }                                      \
+}
+
+/**
+  * @brief  set endpoint tx/rx transfer length
+  * @param  eptn: endpoint number
+  * @param  len: transfer length
+  * @retval none
+  */
+#define USB_SET_TXLEN(eptn, len) (*(GET_TX_LEN_ADDR(eptn)) = (len))
+#define USB_SET_RXLEN(eptn, len) { \
+  uint32_t *rx_reg = GET_RX_LEN_ADDR(eptn); \
+  USB_SET_RXLEN_REG(rx_reg, (len)); \
+}
+
+/**
+  * @brief  double buffer mode set endpoint rx buf0 length
+  * @param  eptn: endpoint number
+  * @param  len: transfer length
+  * @retval none
+  */
+#define USB_OUT_EPT_DOUBLE_BUF0(eptn, len) { \
+  uint32_t *rx_reg = GET_TX_LEN_ADDR(eptn); \
+  USB_SET_RXLEN_REG(rx_reg, (len)); \
+}
+
+/**
+  * @brief  double buffer mode set endpoint buf0 length
+  * @param  eptn: endpoint number
+  * @param  len: transfer length
+  * @param  dir: transfer direction(in/out)
+  * @retval none
+  */
+#define USB_SET_EPT_DOUBLE_BUF0_LEN(eptn, len, dir) { \
+  if(dir == DATA_TRANS_OUT) \
+  { \
+    USB_OUT_EPT_DOUBLE_BUF0(eptn, len); \
+  } \
+  else \
+  { \
+    *(GET_TX_LEN_ADDR(eptn)) = (len); \
+  } \
+}
+
+/**
+  * @brief  double buffer mode set endpoint buf1 length
+  * @param  eptn: endpoint number
+  * @param  len: transfer length
+  * @param  dir: transfer direction(in/out)
+  * @retval none
+  */
+#define USB_SET_EPT_DOUBLE_BUF1_LEN(eptn, len, dir) { \
+  if(dir == DATA_TRANS_OUT) \
+  { \
+    USB_SET_RXLEN(eptn, len); \
+  } \
+  else \
+  { \
+    *(GET_RX_LEN_ADDR(eptn)) = (len); \
+  } \
+}
+
+/**
+  * @brief  set usb endpoint tx/rx fifo address
+  * @param  eptn: endpoint number
+  * @param  address: offset of the fifo address
+  * @retval none
+  */
+#define USB_SET_TX_ADDRESS(eptn, address) (*(uint32_t *)((USB->buftbl + eptn * 8) * 2 + g_usb_packet_address) = address)
+#define USB_SET_RX_ADDRESS(eptn, address) (*(uint32_t *)((USB->buftbl + eptn * 8 + 4) * 2 + g_usb_packet_address) = address)
+
+/**
+  * @brief  set double buffer mode usb endpoint buf0/buf1 fifo address
+  * @param  eptn: endpoint number
+  * @param  address: offset of the fifo address
+  * @retval none
+  */
+#define USB_SET_DOUBLE_BUFF0_ADDRESS(eptn, address) (USB_SET_TX_ADDRESS(eptn, address))
+#define USB_SET_DOUBLE_BUFF1_ADDRESS(eptn, address) (USB_SET_RX_ADDRESS(eptn, address))
+
+/**
+  * @brief  set usb tx/rx toggle
+  * @param  eptn: endpoint number
+  * @retval none
+  */
+#define USB_TOGGLE_TXDTS(eptn) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK) | USB_TXDTS | USB_RXTC | USB_TXTC))
+#define USB_TOGGLE_RXDTS(eptn) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK) | USB_RXDTS | USB_RXTC | USB_TXTC))
+
+/**
+  * @brief  clear usb tx/rx toggle
+  * @param  eptn: endpoint number
+  * @retval none
+  */
+#define USB_CLEAR_TXDTS(eptn) { \
+  if(USB->ept_bit[eptn].txdts != 0) \
+    USB_TOGGLE_TXDTS(eptn); \
+}
+#define USB_CLEAR_RXDTS(eptn) { \
+  if(USB->ept_bit[eptn].rxdts != 0) \
+    USB_TOGGLE_RXDTS(eptn); \
+}
+
+/**
+  * @brief set usb endpoint type
+  */
+
+/**
+  * @brief  set usb transfer type
+  * @param  eptn: endpoint number
+  * @param  type: transfer type
+  * @retval none
+  */
+#define USB_SET_TRANS_TYPE(eptn, type) (USB->ept[eptn] = (USB->ept[eptn] & USB_EPT_BIT_MASK & (~USB_TRANS_TYPE)) | type)
+
+/**
+  * @brief  set/clear usb extend function
+  * @param  eptn: endpoint number
+  * @retval none
+  */
+#define USB_SET_EXF(eptn) (USB->ept[eptn] = USB_TXTC | USB_RXTC | ((USB->ept[eptn] | USB_EXF) & USB_EPT_BIT_MASK))
+#define USB_CLEAR_EXF(eptn) (USB->ept[eptn] = USB_TXTC | USB_RXTC | (USB->ept[eptn] & ((~USB_EXF) & USB_EPT_BIT_MASK)))
+
+/**
+  * @brief  set usb device address
+  * @param  eptn: endpoint number
+  * @param  address: device address
+  * @retval none
+  */
+#define USB_SET_EPT_ADDRESS(eptn, address) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK & (~USB_EPTADDR)) | address))
+
+/**
+  * @brief  free buffer used by application
+  * @param  eptn: endpoint number
+  * @param  inout: transfer direction
+  * @retval none
+  */
+#define USB_FREE_DB_USER_BUFFER(eptn, inout) { \
+  if(inout == DATA_TRANS_IN) \
+  { \
+    USB_TOGGLE_RXDTS(eptn); \
+  } \
+  else \
+  { \
+    USB_TOGGLE_TXDTS(eptn); \
+  } \
+}
+
+/**
+  * @brief  clear tx/rx transfer completed flag
+  * @param  eptn: endpoint number
+  * @retval none
+  */
+#define USB_CLEAR_TXTC(eptn)    (USB->ept[eptn] &= 0xFF7F & USB_EPT_BIT_MASK)
+#define USB_CLEAR_RXTC(eptn)    (USB->ept[eptn] &= 0x7FFF & USB_EPT_BIT_MASK)
+
+/**
+  * @brief  set/clear endpoint double buffer mode
+  * @param  eptn: endpoint number
+  * @retval none
+  */
+#define USB_SET_EPT_DOUBLE_BUFFER(eptn)   USB_SET_EXF(eptn)
+#define USB_CLEAR_EPT_DOUBLE_BUFFER(eptn) USB_CLEAR_EXF(eptn)
+
+/**
+  * @}
+  */
+
+/** @defgroup USB_exported_types
+  * @{
+  */
+
+/**
+  * @brief  usb endpoint infomation structure definition
+  */
+typedef struct
+{
+  uint8_t                                eptn;                        /*!< endpoint register number (0~7) */
+  uint8_t                                ept_address;                 /*!< endpoint address */
+  uint8_t                                inout;                       /*!< endpoint dir DATA_TRANS_IN or DATA_TRANS_OUT */
+  uint8_t                                trans_type;                  /*!< endpoint type:
+                                                                           EPT_CONTROL_TYPE, EPT_BULK_TYPE, EPT_INT_TYPE, EPT_ISO_TYPE*/
+  uint16_t                               tx_addr;                     /*!< endpoint tx buffer offset address */
+  uint16_t                               rx_addr;                     /*!< endpoint rx buffer offset address */
+  uint16_t                               maxpacket;                   /*!< endpoint max packet*/
+  uint8_t                                is_double_buffer;            /*!< endpoint double buffer flag */
+  uint8_t                                stall;                       /*!< endpoint is stall state */
+  uint16_t                               status;                      /*!< endpoint status */
+
+  /* transmission buffer and count */
+  uint16_t                               total_len;                   /*!< endpoint transmission total length */
+  uint16_t                               trans_len;                   /*!< endpoint transmission length*/
+  uint8_t                                *trans_buf;                  /*!< endpoint transmission buffer */
+
+  uint16_t                               last_len;                    /*!< last transfer length */
+  uint16_t                               rem0_len;                    /*!< rem transfer length */
+  uint16_t                               ept0_slen;                   /*!< endpoint 0 transfer sum length */
+}usb_ept_info;
+
+/**
+ * @brief type define usb register all
+ */
+typedef struct
+{
+  /**
+  * @brief usb endpoint register, offset:0x00
+  */
+  union
+  {
+    __IO uint32_t ept[8];
+    struct
+    {
+      __IO uint32_t eptaddr                  : 4; /* [3:0] */
+      __IO uint32_t txsts                    : 2; /* [5:4] */
+      __IO uint32_t txdts                    : 1; /* [6] */
+      __IO uint32_t txtc                     : 1; /* [7] */
+      __IO uint32_t exf                      : 1; /* [8] */
+      __IO uint32_t trans_type               : 2; /* [10:9] */
+      __IO uint32_t setuptc                  : 1; /* [11] */
+      __IO uint32_t rxsts                    : 2; /* [13:12] */
+      __IO uint32_t rxdts                    : 1; /* [14] */
+      __IO uint32_t rxtc                     : 1; /* [15] */
+      __IO uint32_t reserved1                : 16; /* [31:16] */
+    } ept_bit[8];
+  };
+
+  __IO uint32_t reserved1[8];
+
+  /**
+  * @brief usb control register, offset:0x40
+  */
+  union
+  {
+    __IO uint32_t ctrl;
+    struct
+    {
+      __IO uint32_t csrst                    : 1; /* [0] */
+      __IO uint32_t disusb                   : 1; /* [1] */
+      __IO uint32_t lpm                      : 1; /* [2] */
+      __IO uint32_t ssp                      : 1; /* [3] */
+      __IO uint32_t gresume                  : 1; /* [4] */
+      __IO uint32_t reserved1                : 3; /* [7:5] */
+      __IO uint32_t lsofien                  : 1; /* [8] */
+      __IO uint32_t sofien                   : 1; /* [9] */
+      __IO uint32_t rstien                   : 1; /* [10] */
+      __IO uint32_t spien                    : 1; /* [11] */
+      __IO uint32_t wkien                    : 1; /* [12] */
+      __IO uint32_t beien                    : 1; /* [13] */
+      __IO uint32_t ucforien                 : 1; /* [14] */
+      __IO uint32_t tcien                    : 1; /* [15] */
+      __IO uint32_t reserved2                : 16; /* [31:16] */
+    } ctrl_bit;
+  };
+
+  /**
+  * @brief usb interrupt status register, offset:0x44
+  */
+  union
+  {
+    __IO uint32_t intsts;
+    struct
+    {
+      __IO uint32_t ept_num                  : 4; /* [3:0] */
+      __IO uint32_t inout                    : 1; /* [4] */
+      __IO uint32_t reserved1                : 3; /* [7:5] */
+      __IO uint32_t lsof                     : 1; /* [8] */
+      __IO uint32_t sof                      : 1; /* [9] */
+      __IO uint32_t rst                      : 1; /* [10] */
+      __IO uint32_t sp                       : 1; /* [11] */
+      __IO uint32_t wk                       : 1; /* [12] */
+      __IO uint32_t be                       : 1; /* [13] */
+      __IO uint32_t ucfor                    : 1; /* [14] */
+      __IO uint32_t tc                       : 1; /* [15] */
+      __IO uint32_t reserved2                : 16; /* [31:16] */
+    } intsts_bit;
+  };
+
+  /**
+  * @brief usb frame number register, offset:0x48
+  */
+  union
+  {
+    __IO uint32_t sofrnum;
+    struct
+    {
+      __IO uint32_t sofnum                   : 11; /* [10:0] */
+      __IO uint32_t lsofnum                  : 2; /* [12:11] */
+      __IO uint32_t clck                     : 1; /* [13] */
+      __IO uint32_t dmsts                    : 1; /* [14] */
+      __IO uint32_t dpsts                    : 1; /* [15] */
+      __IO uint32_t reserved1                : 16; /* [31:16] */
+    } sofrnum_bit;
+  };
+
+  /**
+  * @brief usb device address register, offset:0x4c
+  */
+  union
+  {
+    __IO uint32_t devaddr;
+    struct
+    {
+      __IO uint32_t addr                     : 7; /* [6:0] */
+      __IO uint32_t cen                      : 1; /* [7] */
+      __IO uint32_t reserved1                : 24; /* [31:8] */
+    } devaddr_bit;
+  };
+
+  /**
+  * @brief usb buffer address register, offset:0x50
+  */
+  union
+  {
+    __IO uint32_t buftbl;
+    struct
+    {
+      __IO uint32_t reserved1                : 3; /* [2:0] */
+      __IO uint32_t btaddr                   : 13; /* [15:3] */
+      __IO uint32_t reserved2                : 16; /* [31:16] */
+    } buftbl_bit;
+  };
+  __IO uint32_t reserved2[3];
+  /**
+  * @brief usb cfg control register, offset:0x60
+  */
+  union
+  {
+    __IO uint32_t cfg;
+    struct
+    {
+      __IO uint32_t sofouten                 : 1; /* [0] */
+      __IO uint32_t reserved1                : 31; /* [31:1] */
+    } cfg_bit;
+  };
+
+} usbd_type;
+
+/**
+  * @}
+  */
+
+#define USB                              ((usbd_type *) USBFS_BASE)
+
+typedef usbd_type usb_reg_type;
+extern uint32_t g_usb_packet_address;
+
+/** @defgroup USB_exported_functions
+  * @{
+  */
+
+void usb_dev_init(usbd_type *usbx);
+void usb_connect(usbd_type *usbx);
+void usb_disconnect(usbd_type *usbx);
+void usb_usbbufs_enable(usbd_type *usbx, confirm_state state);
+void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info);
+void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info);
+void usb_write_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes);
+void usb_read_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes);
+void usb_interrupt_enable(usbd_type *usbx, uint16_t interrupt, confirm_state new_state);
+void usb_set_address(usbd_type *usbx, uint8_t address);
+void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info);
+void usb_enter_suspend(usbd_type *usbx);
+void usb_exit_suspend(usbd_type *usbx);
+void usb_remote_wkup_set(usbd_type *usbx);
+void usb_remote_wkup_clear(usbd_type *usbx);
+uint16_t usb_buffer_malloc(uint16_t maxpacket);
+void usb_buffer_free(void);
+flag_status usb_flag_get(usbd_type *usbx, uint16_t flag);
+void usb_flag_clear(usbd_type *usbx, uint16_t flag);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/inc/at32f413_wdt.h

@@ -0,0 +1,181 @@
+/**
+  **************************************************************************
+  * @file     at32f413_wdt.h
+  * @brief    at32f413 wdt header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_WDT_H
+#define __AT32F413_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup WDT
+  * @{
+  */
+
+
+/** @defgroup WDT_flags_definition
+  * @brief wdt flag
+  * @{
+  */
+
+#define WDT_DIVF_UPDATE_FLAG             ((uint16_t)0x0001) /*!< wdt division value update complete flag */
+#define WDT_RLDF_UPDATE_FLAG             ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup WDT_exported_types
+  * @{
+  */
+
+/**
+  * @brief wdt division value type
+  */
+typedef enum
+{
+  WDT_CLK_DIV_4                          = 0x00, /*!< wdt clock divider value is 4 */
+  WDT_CLK_DIV_8                          = 0x01, /*!< wdt clock divider value is 8 */
+  WDT_CLK_DIV_16                         = 0x02, /*!< wdt clock divider value is 16 */
+  WDT_CLK_DIV_32                         = 0x03, /*!< wdt clock divider value is 32 */
+  WDT_CLK_DIV_64                         = 0x04, /*!< wdt clock divider value is 64 */
+  WDT_CLK_DIV_128                        = 0x05, /*!< wdt clock divider value is 128 */
+  WDT_CLK_DIV_256                        = 0x06  /*!< wdt clock divider value is 256 */
+} wdt_division_type;
+
+/**
+  * @brief wdt cmd value type
+  */
+typedef enum
+{
+  WDT_CMD_LOCK                           = 0x0000, /*!< disable write protection command */
+  WDT_CMD_UNLOCK                         = 0x5555, /*!< enable write protection command */
+  WDT_CMD_ENABLE                         = 0xCCCC, /*!< enable wdt command */
+  WDT_CMD_RELOAD                         = 0xAAAA  /*!< reload command */
+} wdt_cmd_value_type;
+
+/**
+  * @brief type define wdt register all
+  */
+typedef struct
+{
+
+  /**
+    * @brief wdt cmd register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t cmd;
+    struct
+    {
+      __IO uint32_t cmd                  : 16;/* [15:0] */
+      __IO uint32_t reserved1            : 16;/* [31:16] */
+    } cmd_bit;
+  };
+
+  /**
+    * @brief wdt div register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t div;
+    struct
+    {
+      __IO uint32_t div                   : 3; /* [2:0] */
+      __IO uint32_t reserved1            : 29;/* [31:3] */
+    } div_bit;
+  };
+
+   /**
+    * @brief wdt rld register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t rld;
+    struct
+    {
+      __IO uint32_t rld                  : 12;/* [11:0] */
+      __IO uint32_t reserved1            : 20;/* [31:12] */
+    } rld_bit;
+  };
+
+  /**
+  * @brief wdt sts register, offset:0x0C
+  */
+  union
+  {
+    __IO uint32_t sts;
+    struct
+    {
+      __IO uint32_t divf                 : 1; /* [0] */
+      __IO uint32_t rldf                 : 1; /* [1] */
+      __IO uint32_t reserved1            : 30;/* [31:2] */
+    } sts_bit;
+  };
+
+} wdt_type;
+
+/**
+  * @}
+  */
+
+#define WDT                             ((wdt_type *) WDT_BASE)
+
+/** @defgroup WDT_exported_functions
+  * @{
+  */
+
+void wdt_enable(void);
+void wdt_counter_reload(void);
+void wdt_reload_value_set(uint16_t reload_value);
+void wdt_divider_set(wdt_division_type division);
+void wdt_register_write_enable( confirm_state new_state);
+flag_status wdt_flag_get(uint16_t wdt_flag);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/inc/at32f413_wwdt.h

@@ -0,0 +1,156 @@
+/**
+  **************************************************************************
+  * @file     at32f413_wwdt.h
+  * @brief    at32f413 wwdt header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_WWDT_H
+#define __AT32F413_WWDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @addtogroup WWDT
+  * @{
+  */
+
+/** @defgroup WWDT_enable_bit_definition
+  * @brief wwdt enable bit
+  * @{
+  */
+
+#define WWDT_EN_BIT                      ((uint32_t)0x00000080) /*!< wwdt enable bit */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDT_exported_types
+  * @{
+  */
+
+/**
+  * @brief wwdt division type
+  */
+typedef enum
+{
+  WWDT_PCLK1_DIV_4096                    = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
+  WWDT_PCLK1_DIV_8192                    = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
+  WWDT_PCLK1_DIV_16384                   = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
+  WWDT_PCLK1_DIV_32768                   = 0x03  /*!< wwdt counter clock = (pclk1/4096)/8) */
+} wwdt_division_type;
+
+/**
+  * @brief type define wwdt register all
+  */
+typedef struct
+{
+
+  /**
+    * @brief wwdt ctrl register, offset:0x00
+    */
+  union
+  {
+    __IO uint32_t ctrl;
+    struct
+    {
+      __IO uint32_t cnt                  : 7; /* [6:0] */
+      __IO uint32_t wwdten               : 1; /* [7] */
+      __IO uint32_t reserved1            : 24;/* [31:8] */
+    } ctrl_bit;
+  };
+
+  /**
+    * @brief wwdt cfg register, offset:0x04
+    */
+  union
+  {
+    __IO uint32_t cfg;
+    struct
+    {
+      __IO uint32_t win                  : 7; /* [6:0] */
+      __IO uint32_t div                  : 2; /* [8:7] */
+      __IO uint32_t rldien               : 1; /* [9] */
+      __IO uint32_t reserved1            : 22;/* [31:10] */
+    } cfg_bit;
+  };
+
+  /**
+    * @brief wwdt cfg register, offset:0x08
+    */
+  union
+  {
+    __IO uint32_t sts;
+    struct
+    {
+      __IO uint32_t rldf                 : 1; /* [0] */
+      __IO uint32_t reserved1            : 31;/* [31:1] */
+    } sts_bit;
+  };
+
+} wwdt_type;
+
+/**
+  * @}
+  */
+
+#define WWDT                             ((wwdt_type *) WWDT_BASE)
+
+/** @defgroup WWDT_exported_functions
+  * @{
+  */
+
+void wwdt_reset(void);
+void wwdt_divider_set(wwdt_division_type division);
+void wwdt_flag_clear(void);
+void wwdt_enable(uint8_t wwdt_cnt);
+void wwdt_interrupt_enable(void);
+flag_status wwdt_flag_get(void);
+void wwdt_counter_set(uint8_t wwdt_cnt);
+void wwdt_window_counter_set(uint8_t window_cnt);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/AT32F41x_Drivers/src/at32f413_acc.c

@@ -0,0 +1,216 @@
+/**
+  **************************************************************************
+  * @file     at32f413_acc.c
+  * @brief    contains all the functions for the acc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup ACC
+  * @brief ACC driver modules
+  * @{
+  */
+
+#ifdef ACC_MODULE_ENABLED
+
+/** @defgroup ACC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  enable or disable the acc calibration mode.
+  * @param  acc_trim: specifies the acc calibration type.
+  *         this parameter can be one of the following values:
+  *         - ACC_CAL_HICKCAL
+  *         - ACC_CAL_HICKTRIM
+  * @param  new_state: specifies the acc calibration to be enabled or disabled.(TRUE or FALSE)
+  * @retval none
+  */
+void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state)
+{
+  if(acc_trim == ACC_CAL_HICKCAL)
+  {
+    ACC->ctrl1_bit.entrim = FALSE;
+  }
+  else
+  {
+    ACC->ctrl1_bit.entrim = TRUE;
+  }
+  ACC->ctrl1_bit.calon = new_state;
+}
+
+/**
+  * @brief  store calibration step data in acc's ctrl1 register.
+  * @param  step_value:  value to be stored in the acc's ctrl1 register
+  * @retval none
+  */
+void acc_step_set(uint8_t step_value)
+{
+  ACC->ctrl1_bit.step = step_value;
+}
+
+/**
+  * @brief  enable or disable the specified acc interrupts.
+  * @param  acc_int: specifies the acc interrupt sources to be enabled or disabled.
+  *         this parameter can be one of the following values:
+  *         - ACC_CALRDYIEN_INT
+  *         - ACC_EIEN_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state)
+{
+  if(acc_int == ACC_CALRDYIEN_INT)
+  {
+    ACC->ctrl1_bit.calrdyien = new_state;
+  }
+  else
+  {
+    ACC->ctrl1_bit.eien = new_state;
+  }
+}
+
+/**
+  * @brief  return the current acc hicktrim value.
+  * @param  none
+  * @retval 8-bit hicktrim value.
+  */
+uint8_t acc_hicktrim_get(void)
+{
+  return ((uint8_t)(ACC->ctrl2_bit.hicktrim));
+}
+
+/**
+  * @brief  return the current acc hickcal value.
+  * @param  none
+  * @retval 8-bit hicktrim value.
+  */
+uint8_t acc_hickcal_get(void)
+{
+  return ((uint8_t)(ACC->ctrl2_bit.hickcal));
+}
+
+/**
+  * @brief  wtire the value to  acc c1 register.
+  * @param  acc_c1_value
+  * @retval none.
+  */
+void acc_write_c1(uint16_t acc_c1_value)
+{
+  ACC->c1 = acc_c1_value;
+}
+
+/**
+  * @brief  wtire the value to  acc c2 register.
+  * @param  acc_c2_value
+  * @retval none.
+  */
+void acc_write_c2(uint16_t acc_c2_value)
+{
+  ACC->c2 = acc_c2_value;
+}
+
+/**
+  * @brief  wtire the value to  acc c3 register.
+  * @param  acc_c3_value
+  * @retval none.
+  */
+void acc_write_c3(uint16_t acc_c3_value)
+{
+  ACC->c3 = acc_c3_value;
+}
+
+/**
+  * @brief  return the current acc c1 value.
+  * @param  none
+  * @retval 16-bit c1 value.
+  */
+uint16_t acc_read_c1(void)
+{
+  return ((uint16_t)(ACC->c1));
+}
+
+/**
+  * @brief  return the current acc c2 value.
+  * @param  none
+  * @retval 16-bit c2 value.
+  */
+uint16_t acc_read_c2(void)
+{
+  return ((uint16_t)(ACC->c2));
+}
+
+/**
+  * @brief  return the current acc c3 value.
+  * @param  none
+  * @retval 16-bit c3 value.
+  */
+uint16_t acc_read_c3(void)
+{
+  return ((uint16_t)(ACC->c3));
+}
+
+/**
+  * @brief  check whether the specified acc flag is set or not.
+  * @param  acc_flag: specifies the flag to check.
+  *         this parameter can be one of the following values:
+  *         - ACC_RSLOST_FLAG
+  *         - ACC_CALRDY_FLAG
+  * @retval  flag_status (SET or RESET)
+  */
+flag_status acc_flag_get(uint16_t acc_flag)
+{
+  if(acc_flag == ACC_CALRDY_FLAG)
+    return (flag_status)(ACC->sts_bit.calrdy);
+  else
+    return (flag_status)(ACC->sts_bit.rslost);
+}
+
+/**
+  * @brief  clear the specified acc flag is set or not.
+  * @param  acc_flag: specifies the flag to check.
+  *         this parameter can be any combination of the following values:
+  *         - ACC_RSLOST_FLAG
+  *         - ACC_CALRDY_FLAG
+  * @retval  none
+  */
+void acc_flag_clear(uint16_t acc_flag)
+{
+  ACC->sts = ~acc_flag;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_adc.c

@@ -0,0 +1,934 @@
+/**
+  **************************************************************************
+  * @file     at32f413_adc.c
+  * @brief    contains all the functions for the adc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup ADC
+  * @brief ADC driver modules
+  * @{
+  */
+
+#ifdef ADC_MODULE_ENABLED
+
+/** @defgroup ADC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  deinitialize the adc peripheral registers to their default reset values.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @retval none
+  */
+void adc_reset(adc_type *adc_x)
+{
+  if(adc_x == ADC1)
+  {
+    crm_periph_reset(CRM_ADC1_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_ADC1_PERIPH_RESET, FALSE);
+  }
+  else if(adc_x == ADC2)
+  {
+    crm_periph_reset(CRM_ADC2_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_ADC2_PERIPH_RESET, FALSE);
+  }
+}
+
+/**
+  * @brief  enable or disable the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  new_state: new state of a/d converter.
+  *         this parameter can be: TRUE or FALSE.
+  *         note:after adc ready,user set adcen bit will cause ordinary conversion
+  * @retval none
+  */
+void adc_enable(adc_type *adc_x, confirm_state new_state)
+{
+  adc_x->ctrl2_bit.adcen = new_state;
+}
+
+/**
+  * @brief  select combine mode of the specified adc peripheral.
+  * @param  combine_mode: select the adc combine mode.
+  *         this parameter can be one of the following values:
+  *         - ADC_INDEPENDENT_MODE
+  *         - ADC_ORDINARY_SMLT_PREEMPT_SMLT_MODE
+  *         - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_MODE
+  *         - ADC_ORDINARY_SHORTSHIFT_PREEMPT_SMLT_MODE
+  *         - ADC_ORDINARY_LONGSHIFT_PREEMPT_SMLT_MODE
+  *         - ADC_PREEMPT_SMLT_ONLY_MODE
+  *         - ADC_ORDINARY_SMLT_ONLY_MODE
+  *         - ADC_ORDINARY_SHORTSHIFT_ONLY_MODE
+  *         - ADC_ORDINARY_LONGSHIFT_ONLY_MODE
+  *         - ADC_PREEMPT_INTERLTRIG_ONLY_MODE
+  *         note:these bits are reserved in adc2
+  * @retval none
+  */
+void adc_combine_mode_select(adc_combine_mode_type combine_mode)
+{
+    ADC1->ctrl1_bit.mssel = combine_mode;
+}
+
+/**
+  * @brief  adc base default para init.
+  * @param  sequence_mode: set the state of adc sequence mode.
+  *         this parameter can be:TRUE or FALSE
+  * @param  repeat_mode: set the state of adc repeat conversion mode.
+  *         this parameter can be:TRUE or FALSE
+  * @param  data_align: set the state of adc data alignment.
+  *         this parameter can be one of the following values:
+  *         - ADC_RIGHT_ALIGNMENT
+  *         - ADC_LEFT_ALIGNMENT
+  * @param  ordinary_channel_length: configure the adc ordinary channel sequence length.
+  *         this parameter can be:
+  *         - (0x1~0xf)
+  * @retval none
+  */
+void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
+{
+  adc_base_struct->sequence_mode = FALSE;
+  adc_base_struct->repeat_mode = FALSE;
+  adc_base_struct->data_align = ADC_RIGHT_ALIGNMENT;
+  adc_base_struct->ordinary_channel_length = 1;
+}
+
+/**
+  * @brief  initialize the adc peripheral according to the specified parameters.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  sequence_mode: set the state of adc sequence mode.
+  *         this parameter can be:TRUE or FALSE
+  * @param  repeat_mode: set the state of adc repeat conversion mode.
+  *         this parameter can be:TRUE or FALSE
+  * @param  data_align: set the state of adc data alignment.
+  *         this parameter can be one of the following values:
+  *         - ADC_RIGHT_ALIGNMENT
+  *         - ADC_LEFT_ALIGNMENT
+  * @param  ordinary_channel_length: configure the adc ordinary channel sequence length.
+  *         this parameter can be:
+  *         - (0x1~0xf)
+  * @retval none
+  */
+void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct)
+{
+  adc_x->ctrl1_bit.sqen = adc_base_struct->sequence_mode;
+  adc_x->ctrl2_bit.rpen = adc_base_struct->repeat_mode;
+  adc_x->ctrl2_bit.dtalign = adc_base_struct->data_align;
+  adc_x->osq1_bit.oclen = adc_base_struct->ordinary_channel_length - 1;
+}
+
+/**
+  * @brief  enable or disable the adc dma transfer.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1.
+  *         note:this bit is reserved in adc2
+  * @param  new_state: new state of the adc dma transfer.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+  adc_x->ctrl2_bit.ocdmaen = new_state;
+}
+
+/**
+  * @brief  enable or disable the specified adc interrupts.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_int: specifies the adc interrupt sources to be enabled or disabled.
+  *         this parameter can be one of the following values:
+  *         - ADC_VMOR_INT
+  *         - ADC_CCE_INT
+  *         - ADC_PCCE_INT
+  * @param  new_state: new state of the specified adc interrupts.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    adc_x->ctrl1 |= adc_int;
+  }
+  else if(new_state == FALSE)
+  {
+    adc_x->ctrl1 &= ~adc_int;
+  }
+}
+
+/**
+  * @brief  initialize calibration register of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @retval none
+  */
+void adc_calibration_init(adc_type *adc_x)
+{
+  adc_x->ctrl2_bit.adcalinit = TRUE;
+}
+
+/**
+  * @brief  get calibration register's initialize status of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @retval the new state of reset calibration register status(SET or RESET).
+  */
+flag_status adc_calibration_init_status_get(adc_type *adc_x)
+{
+  if(adc_x->ctrl2_bit.adcalinit)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  start calibration process of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @retval none
+  */
+void adc_calibration_start(adc_type *adc_x)
+{
+  adc_x->ctrl2_bit.adcal = TRUE;
+}
+
+/**
+  * @brief  get calibration status of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @retval the new state of calibration status(SET or RESET).
+  */
+flag_status adc_calibration_status_get(adc_type *adc_x)
+{
+  if(adc_x->ctrl2_bit.adcal)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  enable or disable the voltage monitoring on single/all ordinary or preempt channels of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_voltage_monitoring: choose the adc_voltage_monitoring config.
+  *         this parameter can be one of the following values:
+  *         - ADC_VMONITOR_SINGLE_ORDINARY
+  *         - ADC_VMONITOR_SINGLE_PREEMPT
+  *         - ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT
+  *         - ADC_VMONITOR_ALL_ORDINARY
+  *         - ADC_VMONITOR_ALL_PREEMPT
+  *         - ADC_VMONITOR_ALL_ORDINARY_PREEMPT
+  *         - ADC_VMONITOR_NONE
+  * @retval none
+  */
+void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring)
+{
+  adc_x->ctrl1_bit.ocvmen = FALSE;
+  adc_x->ctrl1_bit.pcvmen = FALSE;
+  adc_x->ctrl1_bit.vmsgen = FALSE;
+  adc_x->ctrl1 |= adc_voltage_monitoring;
+}
+
+/**
+  * @brief  set voltage monitoring's high and low thresholds value of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_high_threshold: voltage monitoring's high thresholds value.
+  *         this parameter can be:
+  *         - (0x000~0xFFF)
+  * @param  adc_low_threshold: voltage monitoring's low thresholds value.
+  *         this parameter can be:
+  *         - (0x000~0xFFF)
+  * @retval none
+  */
+void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold)
+{
+  adc_x->vmhb_bit.vmhb = adc_high_threshold;
+  adc_x->vmlb_bit.vmlb = adc_low_threshold;
+}
+
+/**
+  * @brief  select the voltage monitoring's channel of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_channel: select the channel.
+  *         this parameter can be one of the following values:
+  *         - ADC_CHANNEL_0    - ADC_CHANNEL_1    - ADC_CHANNEL_2    - ADC_CHANNEL_3
+  *         - ADC_CHANNEL_4    - ADC_CHANNEL_5    - ADC_CHANNEL_6    - ADC_CHANNEL_7
+  *         - ADC_CHANNEL_8    - ADC_CHANNEL_9    - ADC_CHANNEL_10   - ADC_CHANNEL_11
+  *         - ADC_CHANNEL_12   - ADC_CHANNEL_13   - ADC_CHANNEL_14   - ADC_CHANNEL_15
+  *         - ADC_CHANNEL_16   - ADC_CHANNEL_17
+  * @retval none
+  */
+void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel)
+{
+  adc_x->ctrl1_bit.vmcsel = adc_channel;
+}
+
+/**
+  * @brief  set ordinary channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_channel: select the channel.
+  *         this parameter can be one of the following values:
+  *         - ADC_CHANNEL_0    - ADC_CHANNEL_1    - ADC_CHANNEL_2    - ADC_CHANNEL_3
+  *         - ADC_CHANNEL_4    - ADC_CHANNEL_5    - ADC_CHANNEL_6    - ADC_CHANNEL_7
+  *         - ADC_CHANNEL_8    - ADC_CHANNEL_9    - ADC_CHANNEL_10   - ADC_CHANNEL_11
+  *         - ADC_CHANNEL_12   - ADC_CHANNEL_13   - ADC_CHANNEL_14   - ADC_CHANNEL_15
+  *         - ADC_CHANNEL_16   - ADC_CHANNEL_17
+  * @param  adc_sequence: set rank in the ordinary group sequencer.
+  *         this parameter must be:
+  *         - between 1 to 16
+  * @param  adc_sampletime: set the sampletime of adc channel.
+  *         this parameter can be one of the following values:
+  *         - ADC_SAMPLETIME_1_5
+  *         - ADC_SAMPLETIME_7_5
+  *         - ADC_SAMPLETIME_13_5
+  *         - ADC_SAMPLETIME_28_5
+  *         - ADC_SAMPLETIME_41_5
+  *         - ADC_SAMPLETIME_55_5
+  *         - ADC_SAMPLETIME_71_5
+  *         - ADC_SAMPLETIME_239_5
+  * @retval none
+  */
+void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
+{
+  switch(adc_channel)
+  {
+    case ADC_CHANNEL_0:
+      adc_x->spt2_bit.cspt0 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_1:
+      adc_x->spt2_bit.cspt1 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_2:
+      adc_x->spt2_bit.cspt2 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_3:
+      adc_x->spt2_bit.cspt3 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_4:
+      adc_x->spt2_bit.cspt4 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_5:
+      adc_x->spt2_bit.cspt5 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_6:
+      adc_x->spt2_bit.cspt6 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_7:
+      adc_x->spt2_bit.cspt7 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_8:
+      adc_x->spt2_bit.cspt8 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_9:
+      adc_x->spt2_bit.cspt9 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_10:
+      adc_x->spt1_bit.cspt10 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_11:
+      adc_x->spt1_bit.cspt11 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_12:
+      adc_x->spt1_bit.cspt12 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_13:
+      adc_x->spt1_bit.cspt13 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_14:
+      adc_x->spt1_bit.cspt14 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_15:
+      adc_x->spt1_bit.cspt15 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_16:
+      adc_x->spt1_bit.cspt16 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_17:
+      adc_x->spt1_bit.cspt17 = adc_sampletime;
+      break;
+    default:
+      break;
+  }
+  switch(adc_sequence)
+  {
+    case 1:
+      adc_x->osq3_bit.osn1 = adc_channel;
+      break;
+    case 2:
+      adc_x->osq3_bit.osn2 = adc_channel;
+      break;
+    case 3:
+      adc_x->osq3_bit.osn3 = adc_channel;
+      break;
+    case 4:
+      adc_x->osq3_bit.osn4 = adc_channel;
+      break;
+    case 5:
+      adc_x->osq3_bit.osn5 = adc_channel;
+      break;
+    case 6:
+      adc_x->osq3_bit.osn6 = adc_channel;
+      break;
+    case 7:
+      adc_x->osq2_bit.osn7 = adc_channel;
+      break;
+    case 8:
+      adc_x->osq2_bit.osn8 = adc_channel;
+      break;
+    case 9:
+      adc_x->osq2_bit.osn9 = adc_channel;
+      break;
+    case 10:
+      adc_x->osq2_bit.osn10 = adc_channel;
+      break;
+    case 11:
+      adc_x->osq2_bit.osn11 = adc_channel;
+      break;
+    case 12:
+      adc_x->osq2_bit.osn12 = adc_channel;
+      break;
+    case 13:
+      adc_x->osq1_bit.osn13 = adc_channel;
+      break;
+    case 14:
+      adc_x->osq1_bit.osn14 = adc_channel;
+      break;
+    case 15:
+      adc_x->osq1_bit.osn15 = adc_channel;
+      break;
+    case 16:
+      adc_x->osq1_bit.osn16 = adc_channel;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  set preempt channel lenghth of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_channel_lenght: set the adc preempt channel lenghth.
+  *         this parameter can be:
+  *         - (0x1~0x4)
+  * @retval none
+  */
+void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght)
+{
+  adc_x->psq_bit.pclen =  adc_channel_lenght - 1;
+}
+
+/**
+  * @brief  configure preempt channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_channel: select the channel.
+  *         this parameter can be one of the following values:
+  *         - ADC_CHANNEL_0    - ADC_CHANNEL_1    - ADC_CHANNEL_2    - ADC_CHANNEL_3
+  *         - ADC_CHANNEL_4    - ADC_CHANNEL_5    - ADC_CHANNEL_6    - ADC_CHANNEL_7
+  *         - ADC_CHANNEL_8    - ADC_CHANNEL_9    - ADC_CHANNEL_10   - ADC_CHANNEL_11
+  *         - ADC_CHANNEL_12   - ADC_CHANNEL_13   - ADC_CHANNEL_14   - ADC_CHANNEL_15
+  *         - ADC_CHANNEL_16   - ADC_CHANNEL_17
+  * @param  adc_sequence: set rank in the preempt group sequencer.
+  *         this parameter must be:
+  *         - between 1 to 4
+  * @param  adc_sampletime: config the sampletime of adc channel.
+  *         this parameter can be one of the following values:
+  *         - ADC_SAMPLETIME_1_5
+  *         - ADC_SAMPLETIME_7_5
+  *         - ADC_SAMPLETIME_13_5
+  *         - ADC_SAMPLETIME_28_5
+  *         - ADC_SAMPLETIME_41_5
+  *         - ADC_SAMPLETIME_55_5
+  *         - ADC_SAMPLETIME_71_5
+  *         - ADC_SAMPLETIME_239_5
+  * @retval none
+  */
+void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
+{
+  uint16_t sequence_index=0;
+  switch(adc_channel)
+  {
+    case ADC_CHANNEL_0:
+      adc_x->spt2_bit.cspt0 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_1:
+      adc_x->spt2_bit.cspt1 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_2:
+      adc_x->spt2_bit.cspt2 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_3:
+      adc_x->spt2_bit.cspt3 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_4:
+      adc_x->spt2_bit.cspt4 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_5:
+      adc_x->spt2_bit.cspt5 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_6:
+      adc_x->spt2_bit.cspt6 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_7:
+      adc_x->spt2_bit.cspt7 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_8:
+      adc_x->spt2_bit.cspt8 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_9:
+      adc_x->spt2_bit.cspt9 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_10:
+      adc_x->spt1_bit.cspt10 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_11:
+      adc_x->spt1_bit.cspt11 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_12:
+      adc_x->spt1_bit.cspt12 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_13:
+      adc_x->spt1_bit.cspt13 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_14:
+      adc_x->spt1_bit.cspt14 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_15:
+      adc_x->spt1_bit.cspt15 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_16:
+      adc_x->spt1_bit.cspt16 = adc_sampletime;
+      break;
+    case ADC_CHANNEL_17:
+      adc_x->spt1_bit.cspt17 = adc_sampletime;
+      break;
+    default:
+      break;
+  }
+  sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen;
+  switch(sequence_index)
+  {
+    case 1:
+      adc_x->psq_bit.psn1 = adc_channel;
+      break;
+    case 2:
+      adc_x->psq_bit.psn2 = adc_channel;
+      break;
+    case 3:
+      adc_x->psq_bit.psn3 = adc_channel;
+      break;
+    case 4:
+      adc_x->psq_bit.psn4 = adc_channel;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  enable or disable the ordinary channel's external trigger and
+  *         set external trigger event of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_ordinary_trig: select the external trigger event.
+  *         this parameter can be one of the following values:
+  *         adc1 & adc2
+  *         - ADC12_ORDINARY_TRIG_TMR1CH1     - ADC12_ORDINARY_TRIG_TMR1CH2  - ADC12_ORDINARY_TRIG_TMR1CH3             - ADC12_ORDINARY_TRIG_TMR2CH2
+  *         - ADC12_ORDINARY_TRIG_TMR3TRGOUT  - ADC12_ORDINARY_TRIG_TMR4CH4  - ADC12_ORDINARY_TRIG_EXINT11_TMR8TRGOUT  - ADC12_ORDINARY_TRIG_SOFTWARE
+  *         - ADC12_ORDINARY_TRIG_TMR1TRGOUT  - ADC12_ORDINARY_TRIG_TMR8CH1  - ADC12_ORDINARY_TRIG_TMR8CH2
+  * @param  new_state: new state of ordinary channel's external trigger.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state)
+{
+  if(adc_ordinary_trig > 7)
+  {
+    adc_x->ctrl2_bit.octesel_h = 1;
+    adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7;
+  }
+  else
+  {
+    adc_x->ctrl2_bit.octesel_h = 0;
+    adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7;
+  }
+  adc_x->ctrl2_bit.octen = new_state;
+}
+
+/**
+  * @brief  enable or disable the preempt channel's external trigger and
+  *         set external trigger event of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_preempt_trig: select the external trigger event.
+  *         this parameter can be one of the following values:
+  *         adc1 & adc2
+  *         - ADC12_PREEMPT_TRIG_TMR1TRGOUT  - ADC12_PREEMPT_TRIG_TMR1CH4     - ADC12_PREEMPT_TRIG_TMR2TRGOUT      - ADC12_PREEMPT_TRIG_TMR2CH1
+  *         - ADC12_PREEMPT_TRIG_TMR3CH4     - ADC12_PREEMPT_TRIG_TMR4TRGOUT  - ADC12_PREEMPT_TRIG_EXINT15_TMR8CH4 - ADC12_PREEMPT_TRIG_SOFTWARE
+  *         - ADC12_PREEMPT_TRIG_TMR1CH1     - ADC12_PREEMPT_TRIG_TMR8CH1     - ADC12_PREEMPT_TRIG_TMR8TRGOUT
+  * @param  new_state: new state of preempt channel's external trigger.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state)
+{
+  if(adc_preempt_trig > 7)
+  {
+    adc_x->ctrl2_bit.pctesel_h = 1;
+    adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7;
+  }
+  else
+  {
+    adc_x->ctrl2_bit.pctesel_h = 0;
+    adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7;
+  }
+  adc_x->ctrl2_bit.pcten = new_state;
+}
+
+
+/**
+  * @brief  set preempt channel's conversion value offset of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_preempt_channel: select the preempt channel.
+  *         this parameter can be one of the following values:
+  *         - ADC_PREEMPT_CHANNEL_1
+  *         - ADC_PREEMPT_CHANNEL_2
+  *         - ADC_PREEMPT_CHANNEL_3
+  *         - ADC_PREEMPT_CHANNEL_4
+  * @param  adc_offset_value: set the adc preempt channel's conversion value offset.
+  *         this parameter can be:
+  *         - (0x000~0xFFF)
+  * @retval none
+  */
+void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value)
+{
+  switch(adc_preempt_channel)
+  {
+    case ADC_PREEMPT_CHANNEL_1:
+      adc_x->pcdto1_bit.pcdto1 = adc_offset_value;
+      break;
+    case ADC_PREEMPT_CHANNEL_2:
+      adc_x->pcdto2_bit.pcdto2 = adc_offset_value;
+      break;
+    case ADC_PREEMPT_CHANNEL_3:
+      adc_x->pcdto3_bit.pcdto3 = adc_offset_value;
+      break;
+    case ADC_PREEMPT_CHANNEL_4:
+      adc_x->pcdto4_bit.pcdto4 = adc_offset_value;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  set partitioned mode channel count of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_channel_count: configure the adc partitioned mode channel count.
+  *         this parameter can be:
+  *         - (0x1~0x8)
+  * @retval none
+  */
+void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count)
+{
+
+  adc_x->ctrl1_bit.ocpcnt =  adc_channel_count - 1;
+}
+
+/**
+  * @brief  enable or disable the partitioned mode on ordinary channel of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  new_state: new state of ordinary channel's partitioned mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+  adc_x->ctrl1_bit.ocpen = new_state;
+}
+
+/**
+  * @brief  enable or disable the partitioned mode on preempt channel of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  new_state: new state of preempt channel's partitioned mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+  adc_x->ctrl1_bit.pcpen = new_state;
+}
+
+/**
+  * @brief  enable or disable automatic preempt group conversion of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  new_state: new state of automatic preempt group conversion.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+  adc_x->ctrl1_bit.pcautoen = new_state;
+}
+
+/**
+  * @brief  enable or disable the temperature sensor and vintrv channel.
+  * @param  new_state: new state of Internal temperature sensor and vintrv.
+  *         this parameter can be: TRUE or FALSE.
+  *         note:this bit is present only in adc1
+  * @retval none
+  */
+void adc_tempersensor_vintrv_enable(confirm_state new_state)
+{
+  ADC1->ctrl2_bit.itsrven = new_state;
+}
+
+/**
+  * @brief  enable or disable ordinary software start conversion of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  new_state: new state of ordinary software start conversion.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
+{
+  adc_x->ctrl2_bit.ocswtrg = new_state;
+}
+
+/**
+  * @brief  get ordinary software start conversion status of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @retval the new state of ordinary software start conversion status(SET or RESET).
+  */
+flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x)
+{
+  if(adc_x->ctrl2_bit.ocswtrg)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  enable or disable preempt software start conversion of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  new_state: new state of preempt software start conversion.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
+{
+  adc_x->ctrl2_bit.pcswtrg = new_state;
+}
+
+/**
+  * @brief  get preempt software start conversion status of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @retval the new state of preempt software start conversion status(SET or RESET).
+  */
+flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x)
+{
+  if(adc_x->ctrl2_bit.pcswtrg)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  return the last conversion data for ordinary channel of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @retval the last conversion data for ordinary channel.
+  */
+uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x)
+{
+  return (uint16_t)(adc_x->odt_bit.odt);
+}
+
+/**
+  * @brief  return the last conversion data for ordinary channel of combine adc(adc1 and adc2).
+  * @retval the last conversion data for ordinary channel.
+  */
+uint32_t adc_combine_ordinary_conversion_data_get(void)
+{
+  return (uint32_t)(ADC1->odt);
+}
+
+/**
+  * @brief  return the conversion data for selection preempt channel of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_preempt_channel: select the preempt channel.
+  *         this parameter can be one of the following values:
+  *         - ADC_PREEMPTED_CHANNEL_1
+  *         - ADC_PREEMPTED_CHANNEL_2
+  *         - ADC_PREEMPTED_CHANNEL_3
+  *         - ADC_PREEMPTED_CHANNEL_4
+  * @retval the conversion data for selection preempt channel.
+  */
+uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel)
+{
+  uint16_t preempt_conv_data_index = 0;
+  switch(adc_preempt_channel)
+  {
+    case ADC_PREEMPT_CHANNEL_1:
+      preempt_conv_data_index = (uint16_t)(adc_x->pdt1_bit.pdt1);
+      break;
+    case ADC_PREEMPT_CHANNEL_2:
+      preempt_conv_data_index = (uint16_t)(adc_x->pdt2_bit.pdt2);
+      break;
+    case ADC_PREEMPT_CHANNEL_3:
+      preempt_conv_data_index = (uint16_t)(adc_x->pdt3_bit.pdt3);
+      break;
+    case ADC_PREEMPT_CHANNEL_4:
+      preempt_conv_data_index = (uint16_t)(adc_x->pdt4_bit.pdt4);
+      break;
+    default:
+      break;
+  }
+  return preempt_conv_data_index;
+}
+
+/**
+  * @brief  get flag of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_flag: select the adc flag.
+  *         this parameter can be one of the following values:
+  *         - ADC_VMOR_FLAG
+  *         - ADC_CCE_FLAG
+  *         - ADC_PCCE_FLAG
+  *         - ADC_PCCS_FLAG(no interrupt associated)
+  *         - ADC_OCCS_FLAG(no interrupt associated)
+  * @retval the new state of adc flag status(SET or RESET).
+  */
+flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
+{
+  flag_status status = RESET;
+
+  if((adc_x->sts & adc_flag) == RESET)
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+  return status;
+}
+
+/**
+  * @brief  clear flag of the specified adc peripheral.
+  * @param  adc_x: select the adc peripheral.
+  *         this parameter can be one of the following values:
+  *         ADC1, ADC2.
+  * @param  adc_flag: select the adc flag.
+  *         this parameter can be any combination of the following values:
+  *         - ADC_VMOR_FLAG
+  *         - ADC_CCE_FLAG(also can clear by reading the adc_x->odt)
+  *         - ADC_PCCE_FLAG
+  *         - ADC_PCCS_FLAG
+  *         - ADC_OCCS_FLAG
+  * @retval none
+  */
+void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag)
+{
+  adc_x->sts = ~adc_flag;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_bpr.c

@@ -0,0 +1,204 @@
+/**
+  **************************************************************************
+  * @file     at32f413_bpr.c
+  * @brief    contains all the functions for the bpr firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup BPR
+  * @brief BPR driver modules
+  * @{
+  */
+
+#ifdef BPR_MODULE_ENABLED
+
+/** @defgroup BPR_private_functions
+  * @{
+  */
+
+/**
+  * @brief  bpr reset by crm reset register
+  * @param  none
+  * @retval none
+  */
+void bpr_reset(void)
+{
+  crm_battery_powered_domain_reset(TRUE);
+  crm_battery_powered_domain_reset(FALSE);
+}
+
+/**
+  * @brief  bpr event flag get, for tamper event flag
+  * @param  flag: specifies the flag to check.
+  *         this parameter can be one of the following values:
+  *         - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
+  *         - BPR_TAMPER_EVENT_FLAG:   tamper event flag
+  * @retval state of tamper event flag
+  */
+flag_status bpr_flag_get(uint32_t flag)
+{
+  if(flag == BPR_TAMPER_INTERRUPT_FLAG)
+  {
+    return (flag_status)(BPR->ctrlsts_bit.tpif);
+  }
+  else
+  {
+    return (flag_status)(BPR->ctrlsts_bit.tpef);
+  }
+}
+
+/**
+  * @brief  clear bpr tamper flag
+  * @param  flag: specifies the flag to clear.
+  *         this parameter can be one of the following values:
+  *         - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
+  *         - BPR_TAMPER_EVENT_FLAG:   tamper event flag
+  * @retval none
+  */
+void bpr_flag_clear(uint32_t flag)
+{
+  if(flag == BPR_TAMPER_INTERRUPT_FLAG)
+  {
+    BPR->ctrlsts_bit.tpifclr = TRUE;
+  }
+  else
+  {
+    BPR->ctrlsts_bit.tpefclr = TRUE;
+  }
+}
+
+/**
+  * @brief  enable or disable bpr tamper interrupt
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void bpr_interrupt_enable(confirm_state new_state)
+{
+  BPR->ctrlsts_bit.tpien = new_state;
+}
+
+/**
+  * @brief  read bpr bpr data
+  * @param  bpr_data
+  *         this parameter can be one of the following values:
+  *         - BPR_DATA1
+  *         - BPR_DATA2
+  *         ...
+  *         - BPR_DATA41
+  *         - BPR_DATA42
+  * @retval none
+  */
+uint16_t bpr_data_read(bpr_data_type bpr_data)
+{
+  return (*(__IO uint16_t *)(BPR_BASE + bpr_data));
+}
+
+/**
+  * @brief  write bpr data
+  * @param  bpr_data
+  *         this parameter can be one of the following values:
+  *         - BPR_DATA1
+  *         - BPR_DATA2
+  *         ...
+  *         - BPR_DATA41
+  *         - BPR_DATA42
+  * @param  data_value (0x0000~0xFFFF)
+  * @retval none
+  */
+void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value)
+{
+  (*(__IO uint32_t *)(BPR_BASE + bpr_data)) = data_value;
+}
+
+/**
+  * @brief  select bpr rtc output
+  * @param  output_source
+  *         this parameter can be one of the following values:
+  *         - BPR_RTC_OUTPUT_NONE: output disable.
+  *         - BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE: output clock before calibration.
+  *         - BPR_RTC_OUTPUT_ALARM: output alarm event with pluse mode.
+  *         - BPR_RTC_OUTPUT_SECOND: output second event with pluse mode.
+  *         - BPR_RTC_OUTPUT_CLOCK_CAL_AFTER: output clock after calibration.
+  *         - BPR_RTC_OUTPUT_ALARM_TOGGLE: output alarm event with toggle mode.
+  *         - BPR_RTC_OUTPUT_SECOND_TOGGLE: output second event with toggle mode.
+  * @retval none
+  */
+void bpr_rtc_output_select(bpr_rtc_output_type output_source)
+{
+  /* clear cco,asoe,asos,ccos,togen bits */
+  BPR->rtccal &= (uint32_t)~0x0F80;
+
+  /* set output_source value */
+  BPR->rtccal |= output_source;
+}
+
+/**
+  * @brief  set rtc clock calibration value
+  * @param  calibration_value (0x00~0x7f)
+  * @retval none
+  */
+void bpr_rtc_clock_calibration_value_set(uint8_t calibration_value)
+{
+  /* set rtc clock calibration value */
+  BPR->rtccal_bit.calval= calibration_value;
+}
+
+/**
+  * @brief  enable or disable bpr tamper pin
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void bpr_tamper_pin_enable(confirm_state new_state)
+{
+  BPR->ctrl_bit.tpen = new_state;
+}
+
+/**
+  * @brief  set bpr tamper pin active level
+  * @param  active_level
+  *         this parameter can be one of the following values:
+  *         - BPR_TAMPER_PIN_ACTIVE_HIGH: tamper pin input active level is high.
+  *         - BPR_TAMPER_PIN_ACTIVE_LOW: tamper pin input active level is low.
+  * @retval none
+  */
+void bpr_tamper_pin_active_level_set(bpr_tamper_pin_active_level_type active_level)
+{
+  BPR->ctrl_bit.tpp = active_level;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_can.c

@@ -0,0 +1,1150 @@
+/**
+  **************************************************************************
+  * @file     at32f413_can.c
+  * @brief    contains all the functions for the can firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup CAN
+  * @brief CAN driver modules
+  * @{
+  */
+
+#ifdef CAN_MODULE_ENABLED
+
+/** @defgroup CAN_private_functions
+  * @{
+  */
+
+/**
+  * @brief  deinitialize the can peripheral registers to their default reset values.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @retval none.
+  */
+void can_reset(can_type* can_x)
+{
+  if(can_x == CAN1)
+  {
+    crm_periph_reset(CRM_CAN1_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_CAN1_PERIPH_RESET, FALSE);
+  }
+#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \
+    defined (AT32F413Kx)
+  else if(can_x == CAN2)
+  {
+    crm_periph_reset(CRM_CAN2_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_CAN2_PERIPH_RESET, FALSE);
+  }
+#endif
+}
+
+/**
+  * @brief  fill each can_baudrate_struct member with its default value.
+  * @param  can_baudrate_struct: pointer to a can_baudrate_type structure which will be initialized.
+  * @retval none.
+  */
+void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct)
+{
+  /* reset can baudrate structure parameters values */
+
+  /* baud rate division */
+  can_baudrate_struct->baudrate_div = 1;
+
+  /* resynchronization adjust width */
+  can_baudrate_struct->rsaw_size = CAN_RSAW_2TQ;
+
+  /* bit time segment 1 */
+  can_baudrate_struct->bts1_size = CAN_BTS1_4TQ;
+
+  /* bit time segment 2 */
+  can_baudrate_struct->bts2_size = CAN_BTS2_3TQ;
+}
+
+/**
+  * @brief  set the baudrate of the can peripheral
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  can_baudrate_struct: pointer to a can_baudrate_type structure which will be set.
+  * @note   baudrate calculate method is:
+  *         baudrate = fpclk/(baudrate_div *(3 + bts1_size + bts2_size))
+  * @retval the result of baudrate set
+  *         this parameter can be one of the following values:
+  *         SUCCESS or ERROR
+  */
+error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct)
+{
+  error_status status_index = ERROR;
+  uint32_t wait_ack_index = 0x00000000;
+  /* exit from doze mode */
+  can_x->mctrl_bit.dzen = FALSE;
+
+  /* request freeze mode */
+  can_x->mctrl_bit.fzen = TRUE;
+
+  /* wait the acknowledge */
+  while((!can_x->msts_bit.fzc) && (wait_ack_index != FZC_TIMEOUT))
+  {
+    wait_ack_index++;
+  }
+
+  /* check acknowledge */
+  if(can_x->msts_bit.fzc)
+  {
+    can_x->btmg_bit.brdiv = can_baudrate_struct->baudrate_div - 1;
+    can_x->btmg_bit.rsaw = can_baudrate_struct->rsaw_size;
+    can_x->btmg_bit.bts1 = can_baudrate_struct->bts1_size;
+    can_x->btmg_bit.bts2 = can_baudrate_struct->bts2_size;
+
+    /* request leave freeze mode */
+    can_x->mctrl_bit.fzen = FALSE;
+
+    /* wait the acknowledge */
+    wait_ack_index = 0;
+    while((can_x->msts_bit.fzc) && (wait_ack_index != FZC_TIMEOUT))
+    {
+      wait_ack_index++;
+    }
+
+    /* check acknowledged */
+    if(can_x->msts_bit.fzc)
+    {
+      status_index = ERROR;
+    }
+    else
+    {
+      status_index = SUCCESS ;
+    }
+  }
+  else
+  {
+    status_index = ERROR;
+  }
+
+  /* return the status of baudrate set */
+  return status_index;
+}
+
+/**
+  * @brief  fill each can_init_struct member with its default value.
+  * @param  can_base_struct: pointer to a can_base_type structure which will be initialized.
+  * @retval none.
+  */
+void can_default_para_init(can_base_type* can_base_struct)
+{
+  /* reset can init structure parameters values */
+
+  /* initialize the time triggered communication mode */
+  can_base_struct->ttc_enable = FALSE;
+
+  /* initialize the automatic exit bus-off management */
+  can_base_struct->aebo_enable = FALSE;
+
+  /* initialize the automatic exit doze mode */
+  can_base_struct->aed_enable = FALSE;
+
+  /* initialize the prohibit retransmission when sending fails */
+  can_base_struct->prsf_enable = FALSE;
+
+  /* initialize the message discarding rule select when overflow */
+  can_base_struct->mdrsel_selection = CAN_DISCARDING_FIRST_RECEIVED;
+
+  /* initialize the multiple message sending sequence rule */
+  can_base_struct->mmssr_selection = CAN_SENDING_BY_ID;
+
+  /* initialize the can_mode */
+  can_base_struct->mode_selection = CAN_MODE_COMMUNICATE;
+}
+
+/**
+  * @brief  initialize the can peripheral according to the specified
+  *         parameters in the can_init_struct.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  can_base_struct: pointer to a can_base_struct structure that contains the configuration information for the can peripheral.
+  * @retval the status of initialization
+  *         this parameter can be one of the following values:
+  *         SUCCESS or ERROR
+  */
+error_status can_base_init(can_type* can_x, can_base_type* can_base_struct)
+{
+  error_status init_status_index = ERROR;
+  uint32_t wait_ack_index = 0x00000000;
+  /* exit from doze mode */
+  can_x->mctrl_bit.dzen = FALSE;
+
+  /* request freeze mode */
+  can_x->mctrl_bit.fzen = TRUE;
+
+  /* wait the acknowledge */
+  while((!can_x->msts_bit.fzc) && (wait_ack_index != FZC_TIMEOUT))
+  {
+    wait_ack_index++;
+  }
+
+  /* check acknowledge */
+  if(can_x->msts_bit.fzc)
+  {
+    /* set the time triggered communication mode */
+    can_x->mctrl_bit.ttcen = can_base_struct->ttc_enable;
+
+    /* set the automatic exit bus-off management */
+    can_x->mctrl_bit.aeboen = can_base_struct->aebo_enable;
+
+    /* set the automatic automatic exit doze mode */
+    can_x->mctrl_bit.aeden = can_base_struct->aed_enable;
+
+    /* set the prohibit retransmission when sending fails */
+    can_x->mctrl_bit.prsfen = can_base_struct->prsf_enable;
+
+    /* set the message discarding rule select when overflow */
+    can_x->mctrl_bit.mdrsel = can_base_struct->mdrsel_selection;
+
+    /* set the multiple message sending sequence rule */
+    can_x->mctrl_bit.mmssr = can_base_struct->mmssr_selection;
+
+    /* set the test mode */
+    can_x->btmg_bit.lben = can_base_struct->mode_selection & 0x01;
+    can_x->btmg_bit.loen = (can_base_struct->mode_selection >> 1) & 0x01;
+
+    /* request leave freeze mode */
+    can_x->mctrl_bit.fzen = FALSE;
+
+    /* wait the acknowledge */
+    wait_ack_index = 0;
+    while((can_x->msts_bit.fzc) && (wait_ack_index != FZC_TIMEOUT))
+    {
+      wait_ack_index++;
+    }
+
+    /* check acknowledged */
+    if(can_x->msts_bit.fzc)
+    {
+      init_status_index = ERROR;
+    }
+    else
+    {
+      init_status_index = SUCCESS ;
+    }
+  }
+  else
+  {
+    init_status_index = ERROR;
+  }
+
+  /* return the status of initialization */
+  return init_status_index;
+}
+
+/**
+  * @brief  fill each can_filter_init_struct member with its default value.
+  * @param  can_filter_init_struct: pointer to a can_filter_init_type structure which will be initialized.
+  * @retval none.
+  */
+void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct)
+{
+  /* reset can filter init structure parameters values */
+
+  /* initialize the filter activate state */
+  can_filter_init_struct->filter_activate_enable = FALSE;
+
+  /* filter mode */
+  can_filter_init_struct->filter_mode = CAN_FILTER_MODE_ID_MASK;
+
+  /* filter relation fifo select */
+  can_filter_init_struct->filter_fifo = CAN_FILTER_FIFO0;
+
+  /* filter number select */
+  can_filter_init_struct->filter_number = 0;
+
+  /* initialize the filter bit width */
+  can_filter_init_struct->filter_bit = CAN_FILTER_16BIT;
+
+  /* initialize the filters filter data bit */
+  can_filter_init_struct->filter_id_high = 0;
+  can_filter_init_struct->filter_id_low = 0;
+  can_filter_init_struct->filter_mask_high = 0;
+  can_filter_init_struct->filter_mask_low = 0;
+}
+
+/**
+  * @brief  initialize the can peripheral according to the specified
+  *         parameters in the can_filter_init_struct.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  can_filter_init_struct: pointer to a can_filter_init_type structure that contains the configuration information.
+  * @retval none.
+  */
+void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct)
+{
+  uint32_t filter_number_bit_pos = 0;
+  filter_number_bit_pos = ((uint32_t)1) << can_filter_init_struct->filter_number;
+  /* set the filter turn into configuration condition */
+  can_x->fctrl_bit.fcs = TRUE;
+
+  /* filter activate disable */
+  can_x->facfg &= ~(uint32_t)filter_number_bit_pos;
+
+  /* filter bit width */
+  switch(can_filter_init_struct->filter_bit)
+  {
+    case CAN_FILTER_16BIT:
+      can_x->fbwcfg &= ~(uint32_t)filter_number_bit_pos;
+      /* first 16-bit identifier and first 16-bit mask or first 16-bit identifier and second 16-bit identifier */
+      can_x->ffb[can_filter_init_struct->filter_number].ffdb1 = ((0x0000FFFF & (uint32_t)can_filter_init_struct->filter_mask_low) << 16);
+      can_x->ffb[can_filter_init_struct->filter_number].ffdb1 |= (0x0000FFFF & (uint32_t)can_filter_init_struct->filter_id_low);
+
+      /* second 16-bit identifier and second 16-bit mask or third 16-bit identifier and fourth 16-bit identifier */
+      can_x->ffb[can_filter_init_struct->filter_number].ffdb2 = ((0x0000FFFF & (uint32_t)can_filter_init_struct->filter_mask_high) << 16);
+      can_x->ffb[can_filter_init_struct->filter_number].ffdb2 |= (0x0000FFFF & (uint32_t)can_filter_init_struct->filter_id_high);
+
+      break;
+    case CAN_FILTER_32BIT:
+      can_x->fbwcfg |= filter_number_bit_pos;
+      /* 32-bit identifier or first 32-bit identifier */
+      can_x->ffb[can_filter_init_struct->filter_number].ffdb1 = ((0x0000FFFF & (uint32_t)can_filter_init_struct->filter_id_high) << 16);
+      can_x->ffb[can_filter_init_struct->filter_number].ffdb1 |= (0x0000FFFF & (uint32_t)can_filter_init_struct->filter_id_low);
+
+      /* 32-bit mask or second 32-bit identifier */
+      can_x->ffb[can_filter_init_struct->filter_number].ffdb2 = ((0x0000FFFF & (uint32_t)can_filter_init_struct->filter_mask_high) << 16);
+      can_x->ffb[can_filter_init_struct->filter_number].ffdb2 |= (0x0000FFFF & (uint32_t)can_filter_init_struct->filter_mask_low);
+
+      break;
+    default:
+      break;
+  }
+
+  /* filter mode */
+  switch(can_filter_init_struct->filter_mode)
+  {
+    case CAN_FILTER_MODE_ID_MASK:
+      can_x->fmcfg &= ~(uint32_t)filter_number_bit_pos;
+      break;
+    case CAN_FILTER_MODE_ID_LIST:
+      can_x->fmcfg |= (uint32_t)filter_number_bit_pos;
+      break;
+    default:
+      break;
+  }
+
+  /* filter relation fifo select */
+  switch(can_filter_init_struct->filter_fifo)
+  {
+    case CAN_FILTER_FIFO0:
+      can_x->frf &= ~(uint32_t)filter_number_bit_pos;
+      break;
+    case CAN_FILTER_FIFO1:
+      can_x->frf |= (uint32_t)filter_number_bit_pos;
+      break;
+    default:
+      break;
+  }
+
+  /* filter activate enable */
+  switch(can_filter_init_struct->filter_activate_enable)
+  {
+    case TRUE:
+      can_x->facfg |= (uint32_t)filter_number_bit_pos;
+      break;
+    case FALSE:
+      can_x->facfg &= ~(uint32_t)filter_number_bit_pos;
+      break;
+    default:
+      break;
+  }
+
+  /* set the filter turn into working condition */
+  can_x->fctrl_bit.fcs = FALSE;
+}
+
+/**
+  * @brief  enable or disable the debug transmission prohibit of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  new_state: new state of debug transmission prohibit.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none.
+  */
+void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state)
+{
+  can_x->mctrl_bit.ptd = new_state;
+}
+
+/**
+  * @brief  enable or disable time trigger operation communication mode of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1 or CAN2.
+  * @param  new_state : new state of time trigger operation communication mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @note
+  *         note1:
+  *         when enabled, transmit mailbox time stamp(tmts[15:0]) value is sent in the last two data bytes of
+  *         the 8-byte message: tmts[7:0] in data byte 6 and tmts[15:8] in data byte 7
+  * @note
+  *         note2:
+  *         tmdtbl must be programmed as 8 in order time stamp (2 bytes) to be sent over the can bus.
+  * @retval none
+  */
+void can_ttc_mode_enable(can_type* can_x, confirm_state new_state)
+{
+  /* config the ttc mode new_state */
+  can_x->mctrl_bit.ttcen = new_state;
+
+  /* config tmtsten bits new_state */
+  can_x->tx_mailbox[0].tmc_bit.tmtsten = new_state;
+  can_x->tx_mailbox[1].tmc_bit.tmtsten = new_state;
+  can_x->tx_mailbox[2].tmc_bit.tmtsten = new_state;
+}
+
+/**
+  * @brief  fill the transmission message and transmit of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  tx_message_struct: pointer to a structure which contains the message to be trans.
+  * @retval the number of the mailbox that is used for transmission:
+  *         this parameter can be one of the following values:
+  *         - CAN_TX_MAILBOX0
+  *         - CAN_TX_MAILBOX1
+  *         - CAN_TX_MAILBOX2
+  *         - CAN_TX_STATUS_NO_EMPTY <meanings there is no empty mailbox, message cannot be filled>
+  */
+uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct)
+{
+  uint8_t transmit_mailbox = CAN_TX_STATUS_NO_EMPTY;
+
+  /* select one empty transmit mailbox */
+  if(can_x->tsts_bit.tm0ef)
+  {
+    transmit_mailbox = CAN_TX_MAILBOX0;
+  }
+  else if(can_x->tsts_bit.tm1ef)
+  {
+    transmit_mailbox = CAN_TX_MAILBOX1;
+  }
+  else if(can_x->tsts_bit.tm2ef)
+  {
+    transmit_mailbox = CAN_TX_MAILBOX2;
+  }
+  else
+  {
+    transmit_mailbox = CAN_TX_STATUS_NO_EMPTY;
+  }
+
+  if(transmit_mailbox != CAN_TX_STATUS_NO_EMPTY)
+  {
+    /* set up the id */
+    can_x->tx_mailbox[transmit_mailbox].tmi &= 0x00000001;
+    can_x->tx_mailbox[transmit_mailbox].tmi_bit.tmidsel = tx_message_struct->id_type;
+    switch(tx_message_struct->id_type)
+    {
+      case CAN_ID_STANDARD:
+        can_x->tx_mailbox[transmit_mailbox].tmi_bit.tmsid = tx_message_struct->standard_id;
+        break;
+      case CAN_ID_EXTENDED:
+        can_x->tx_mailbox[transmit_mailbox].tmi |= (tx_message_struct->extended_id << 3);
+        break;
+      default:
+        break;
+    }
+    can_x->tx_mailbox[transmit_mailbox].tmi_bit.tmfrsel = tx_message_struct->frame_type;
+    /* set up the dlc */
+    can_x->tx_mailbox[transmit_mailbox].tmc_bit.tmdtbl = (tx_message_struct->dlc & ((uint8_t)0x0F));
+
+    /* set up the data field */
+    can_x->tx_mailbox[transmit_mailbox].tmdtl = (((uint32_t)tx_message_struct->data[3] << 24) |
+                                                ((uint32_t)tx_message_struct->data[2] << 16) |
+                                                ((uint32_t)tx_message_struct->data[1] << 8) |
+                                                ((uint32_t)tx_message_struct->data[0]));
+    can_x->tx_mailbox[transmit_mailbox].tmdth = (((uint32_t)tx_message_struct->data[7] << 24) |
+                                                ((uint32_t)tx_message_struct->data[6] << 16) |
+                                                ((uint32_t)tx_message_struct->data[5] << 8) |
+                                                ((uint32_t)tx_message_struct->data[4]));
+
+    /* request transmission */
+    can_x->tx_mailbox[transmit_mailbox].tmi_bit.tmsr = TRUE;
+  }
+  return transmit_mailbox;
+}
+
+/**
+  * @brief  check the transmission state of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1 or CAN2.
+  * @param  transmit_mailbox: the number of the mailbox that is used for transmission.
+  *         this parameter can be one of the following values:
+  *         - CAN_TX_MAILBOX0
+  *         - CAN_TX_MAILBOX1
+  *         - CAN_TX_MAILBOX2
+  * @retval can transmit status
+  *         this parameter can be one of the following values:
+  *         - CAN_TX_STATUS_SUCCESSFUL
+  *         - CAN_TX_STATUS_FAILED
+  *         - CAN_TX_STATUS_PENDING
+  */
+can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox)
+{
+  can_transmit_status_type state_index = CAN_TX_STATUS_FAILED;
+  switch(transmit_mailbox)
+  {
+    case CAN_TX_MAILBOX0:
+      if(can_x->tsts_bit.tm0tcf != RESET)
+      {
+        if(can_x->tsts_bit.tm0tsf != RESET)
+        {
+          state_index = CAN_TX_STATUS_SUCCESSFUL;
+        }
+        else
+        {
+          state_index = CAN_TX_STATUS_FAILED;
+        }
+      }
+      else
+      {
+        state_index = CAN_TX_STATUS_PENDING;
+      }
+      break;
+    case CAN_TX_MAILBOX1:
+      if(can_x->tsts_bit.tm1tcf != RESET)
+      {
+        if(can_x->tsts_bit.tm1tsf != RESET)
+        {
+          state_index = CAN_TX_STATUS_SUCCESSFUL;
+        }
+        else
+        {
+          state_index = CAN_TX_STATUS_FAILED;
+        }
+      }
+      else
+      {
+        state_index = CAN_TX_STATUS_PENDING;
+      }
+      break;
+    case CAN_TX_MAILBOX2:
+      if(can_x->tsts_bit.tm2tcf != RESET)
+      {
+        if(can_x->tsts_bit.tm2tsf != RESET)
+        {
+          state_index = CAN_TX_STATUS_SUCCESSFUL;
+        }
+        else
+        {
+          state_index = CAN_TX_STATUS_FAILED;
+        }
+      }
+      else
+      {
+        state_index = CAN_TX_STATUS_PENDING;
+      }
+      break;
+    default:
+      state_index = CAN_TX_STATUS_FAILED;
+      break;
+  }
+  return state_index;
+}
+
+/**
+  * @brief  cancel a transmit request of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1 or CAN2.
+  * @param  mailbox:  mailbox number.
+  *         this parameter can be one of the following values:
+  *         - CAN_TX_MAILBOX0
+  *         - CAN_TX_MAILBOX1
+  *         - CAN_TX_MAILBOX2
+  * @retval none.
+  */
+void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox)
+{
+  switch (transmit_mailbox)
+  {
+    case CAN_TX_MAILBOX0:
+      can_x->tsts = CAN_TSTS_TM0CT_VAL;
+      break;
+    case CAN_TX_MAILBOX1:
+      can_x->tsts = CAN_TSTS_TM1CT_VAL;
+      break;
+    case CAN_TX_MAILBOX2:
+      can_x->tsts = CAN_TSTS_TM2CT_VAL;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  receive message of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  fifo_number: receive fifo number.
+  *         this parameter can be one of the following values:
+  *         - CAN_RX_FIFO0
+  *         - CAN_RX_FIFO1
+  * @param  rx_message_struct: pointer to a structure which store the receive message.
+  * @retval none.
+  */
+void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct)
+{
+  /* get the id type */
+  rx_message_struct->id_type = (can_identifier_type)can_x->fifo_mailbox[fifo_number].rfi_bit.rfidi;
+  switch (rx_message_struct->id_type)
+  {
+    case CAN_ID_STANDARD:
+      rx_message_struct->standard_id = can_x->fifo_mailbox[fifo_number].rfi_bit.rfsid;
+      break;
+    case CAN_ID_EXTENDED:
+      rx_message_struct->extended_id = 0x1FFFFFFF & (can_x->fifo_mailbox[fifo_number].rfi >> 3);
+      break;
+    default:
+      break;
+  }
+  rx_message_struct->frame_type = (can_trans_frame_type)can_x->fifo_mailbox[fifo_number].rfi_bit.rffri;
+  /* get the dlc */
+  rx_message_struct->dlc = can_x->fifo_mailbox[fifo_number].rfc_bit.rfdtl;
+
+  /* get the filter match number */
+  rx_message_struct->filter_index = can_x->fifo_mailbox[fifo_number].rfc_bit.rffmn;
+
+  /* get the data field */
+  rx_message_struct->data[0] = can_x->fifo_mailbox[fifo_number].rfdtl_bit.rfdt0;
+  rx_message_struct->data[1] = can_x->fifo_mailbox[fifo_number].rfdtl_bit.rfdt1;
+  rx_message_struct->data[2] = can_x->fifo_mailbox[fifo_number].rfdtl_bit.rfdt2;
+  rx_message_struct->data[3] = can_x->fifo_mailbox[fifo_number].rfdtl_bit.rfdt3;
+  rx_message_struct->data[4] = can_x->fifo_mailbox[fifo_number].rfdth_bit.rfdt4;
+  rx_message_struct->data[5] = can_x->fifo_mailbox[fifo_number].rfdth_bit.rfdt5;
+  rx_message_struct->data[6] = can_x->fifo_mailbox[fifo_number].rfdth_bit.rfdt6;
+  rx_message_struct->data[7] = can_x->fifo_mailbox[fifo_number].rfdth_bit.rfdt7;
+
+  /* release the fifo */
+  can_receive_fifo_release(can_x, fifo_number);
+}
+
+/**
+  * @brief  release the specified fifo of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  fifo_number: fifo to be release.
+  *         this parameter can be one of the following values:
+  *         - CAN_RX_FIFO0
+  *         - CAN_RX_FIFO1
+  * @retval none.
+  */
+void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number)
+{
+  switch (fifo_number)
+  {
+    case CAN_RX_FIFO0:
+      can_x->rf0 = CAN_RF0_RF0R_VAL;
+      break;
+    case CAN_RX_FIFO1:
+      can_x->rf1 = CAN_RF1_RF1R_VAL;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  return the number of pending messages of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  fifo_number: receive fifo number.
+  *         this parameter can be one of the following values:
+  *         - CAN_RX_FIFO0
+  *         - CAN_RX_FIFO1
+  * @retval the number of message pending in the receive fifo.
+  */
+uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number)
+{
+  uint8_t message_pending = 0;
+  switch (fifo_number)
+  {
+    case CAN_RX_FIFO0:
+      message_pending = can_x->rf0_bit.rf0mn;
+      break;
+    case CAN_RX_FIFO1:
+      message_pending = can_x->rf1_bit.rf1mn;
+      break;
+    default:
+      break;
+  }
+  return message_pending;
+}
+
+/**
+  * @brief  set the operation mode of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  can_operating_mode: can operating mode.
+  *         this parameter can be one of the following values:
+  *         - CAN_OPERATINGMODE_FREEZE
+  *         - CAN_OPERATINGMODE_DOZE
+  *         - CAN_OPERATINGMODE_COMMUNICATE
+  * @retval status of operation mode set
+  *         this parameter can be one of the following values:
+  *         SUCCESS or ERROR
+  */
+error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode)
+{
+  error_status status = ERROR;
+  uint32_t time_out_index = FZC_TIMEOUT;
+
+  if (can_operating_mode == CAN_OPERATINGMODE_FREEZE)
+  {
+    /* request enter freeze mode */
+    can_x->mctrl_bit.dzen = FALSE;
+    can_x->mctrl_bit.fzen = TRUE;
+
+    while(((can_x->msts_bit.dzc) || (!can_x->msts_bit.fzc)) && (time_out_index != 0))
+    {
+      time_out_index--;
+    }
+    if((can_x->msts_bit.dzc) || (!can_x->msts_bit.fzc))
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  else if(can_operating_mode == CAN_OPERATINGMODE_DOZE)
+  {
+    /* request enter doze mode */
+    can_x->mctrl_bit.dzen = TRUE;
+    can_x->mctrl_bit.fzen = FALSE;
+
+    while(((!can_x->msts_bit.dzc) || (can_x->msts_bit.fzc)) && (time_out_index != 0))
+    {
+      time_out_index--;
+    }
+    if((!can_x->msts_bit.dzc) || (can_x->msts_bit.fzc))
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  else if(can_operating_mode == CAN_OPERATINGMODE_COMMUNICATE)
+  {
+    /* request enter normal mode */
+    can_x->mctrl_bit.dzen = FALSE;
+    can_x->mctrl_bit.fzen = FALSE;
+
+    while(((can_x->msts_bit.dzc) || (can_x->msts_bit.fzc)) && (time_out_index != 0))
+    {
+      time_out_index--;
+    }
+    if((can_x->msts_bit.dzc) || (can_x->msts_bit.fzc))
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  else
+  {
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  enter the low power mode of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @retval status of doze mode enter, the returned value can be:
+  *         - CAN_ENTER_DOZE_SUCCESSFUL  <it meaning enter the doze mode succeed>
+  *         - CAN_ENTER_DOZE_FAILED  <it meaning enter the doze mode failed>
+  */
+can_enter_doze_status_type can_doze_mode_enter(can_type* can_x)
+{
+  can_enter_doze_status_type status = CAN_ENTER_DOZE_FAILED;
+  uint32_t time_out_index = FZC_TIMEOUT;
+  can_x->mctrl_bit.fzen = FALSE;
+  can_x->mctrl_bit.dzen = TRUE;
+  while(((!can_x->msts_bit.dzc) || (can_x->msts_bit.fzc)) && (time_out_index != 0))
+  {
+    time_out_index--;
+  }
+  if((!can_x->msts_bit.dzc) || (can_x->msts_bit.fzc))
+  {
+    status =  CAN_ENTER_DOZE_FAILED;
+  }
+  else
+  {
+    status =  CAN_ENTER_DOZE_SUCCESSFUL;
+  }
+  return status;
+}
+
+/**
+  * @brief  exit the doze mode of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @retval status of doze mode enter, the returned value can be:
+  *         - CAN_QUIT_DOZE_SUCCESSFUL  <it meaning exit the doze mode succeed>
+  *         - CAN_QUIT_DOZE_FAILED  <it meaning exit the doze mode failed>
+  */
+can_quit_doze_status_type can_doze_mode_exit(can_type* can_x)
+{
+  can_quit_doze_status_type status = CAN_QUIT_DOZE_FAILED;
+  uint32_t time_out_index = DZC_TIMEOUT;
+  can_x->mctrl_bit.dzen = FALSE;
+  while((can_x->msts_bit.dzc) && (time_out_index != 0))
+  {
+    time_out_index--;
+  }
+  if(!can_x->msts_bit.dzc)
+  {
+    status = CAN_QUIT_DOZE_SUCCESSFUL;
+  }
+  return status;
+}
+
+/**
+  * @brief  return the error type record (etr) of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @retval the value of the error code
+  *         the return can be one of the follow values:
+  *         - CAN_ERRORRECORD_NOERR
+  *         - CAN_ERRORRECORD_STUFFERR,
+  *         - CAN_ERRORRECORD_FORMERR,
+  *         - CAN_ERRORRECORD_ACKERR,
+  *         - CAN_ERRORRECORD_BITRECESSIVEERR,
+  *         - CAN_ERRORRECORD_BITDOMINANTERR,
+  *         - CAN_ERRORRECORD_CRCERR,
+  *         - CAN_ERRORRECORD_SOFTWARESETERR
+  */
+can_error_record_type can_error_type_record_get(can_type* can_x)
+{
+  can_error_record_type error_code = CAN_ERRORRECORD_NOERR;
+
+  error_code = (can_error_record_type)can_x->ests_bit.etr;
+  return error_code;
+}
+
+/**
+  * @brief  return the receive error counter (rec) of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @retval the value of receive error counter.
+  */
+uint8_t can_receive_error_counter_get(can_type* can_x)
+{
+  uint8_t counter = 0;
+  counter = can_x->ests_bit.rec;
+  return counter;
+}
+
+/**
+  * @brief  return the transmit error counter of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @retval the value of transmit error counter.
+  */
+uint8_t can_transmit_error_counter_get(can_type* can_x)
+{
+  uint8_t counter = 0;
+  counter = can_x->ests_bit.tec;
+  return counter;
+}
+
+/**
+  * @brief  enable or disable the interrupt of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  can_int: specifies the can interrupt sources to be enabled or disabled.
+  *         this parameter can be one of the following values:
+  *         - CAN_TCIEN_INT
+  *         - CAN_RF0MIEN_INT
+  *         - CAN_RF0FIEN_INT
+  *         - CAN_RF0OIEN_INT
+  *         - CAN_RF1MIEN_INT
+  *         - CAN_RF1FIEN_INT
+  *         - CAN_RF1OIEN_INT
+  *         - CAN_EAIEN_INT
+  *         - CAN_EPIEN_INT
+  *         - CAN_BOIEN_INT
+  *         - CAN_ETRIEN_INT
+  *         - CAN_EOIEN_INT
+  *         - CAN_QDZIEN_INT
+  *         - CAN_EDZIEN_INT
+  * @param  new_state: new state of the can interrupts.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none.
+  */
+void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state)
+{
+  if (new_state != FALSE)
+  {
+    can_x->inten |= can_int;
+  }
+  else
+  {
+    can_x->inten &= ~can_int;
+  }
+}
+
+/**
+  * @brief  get flag of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  can_flag: select the flag.
+  *         this parameter can be one of the following flags:
+  *         - CAN_EAF_FLAG
+  *         - CAN_EPF_FLAG
+  *         - CAN_BOF_FLAG
+  *         - CAN_ETR_FLAG
+  *         - CAN_EOIF_FLAG
+  *         - CAN_TM0TCF_FLAG
+  *         - CAN_TM1TCF_FLAG
+  *         - CAN_TM2TCF_FLAG
+  *         - CAN_RF0MN_FLAG
+  *         - CAN_RF0FF_FLAG
+  *         - CAN_RF0OF_FLAG
+  *         - CAN_RF1MN_FLAG
+  *         - CAN_RF1FF_FLAG
+  *         - CAN_RF1OF_FLAG
+  *         - CAN_QDZIF_FLAG
+  *         - CAN_EDZC_FLAG
+  *         - CAN_TMEF_FLAG
+  *         note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit
+  *         note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit
+  * @retval status of can_flag, the returned value can be:SET or RESET.
+  */
+flag_status can_flag_get(can_type* can_x, uint32_t can_flag)
+{
+  flag_status bit_status = RESET;
+  switch(can_flag)
+  {
+    case CAN_EAF_FLAG:
+      bit_status = (flag_status)can_x->ests_bit.eaf;
+      break;
+    case CAN_EPF_FLAG:
+      bit_status = (flag_status)can_x->ests_bit.epf;
+      break;
+    case CAN_BOF_FLAG:
+      bit_status = (flag_status)can_x->ests_bit.bof;
+      break;
+    case CAN_ETR_FLAG:
+      if(can_x->ests_bit.etr != 0)
+      {
+        bit_status = SET;
+      }
+      else
+      {
+        bit_status = RESET;
+      }
+      break;
+    case CAN_EOIF_FLAG:
+      bit_status = (flag_status)can_x->msts_bit.eoif;
+      break;
+    case CAN_TM0TCF_FLAG:
+      bit_status = (flag_status)can_x->tsts_bit.tm0tcf;
+      break;
+    case CAN_TM1TCF_FLAG:
+      bit_status = (flag_status)can_x->tsts_bit.tm1tcf;
+      break;
+    case CAN_TM2TCF_FLAG:
+      bit_status = (flag_status)can_x->tsts_bit.tm2tcf;
+      break;
+    case CAN_RF0MN_FLAG:
+      if(can_x->rf0_bit.rf0mn != 0)
+      {
+        bit_status = SET;
+      }
+      else
+      {
+        bit_status = RESET;
+      }
+      break;
+    case CAN_RF0FF_FLAG:
+      bit_status = (flag_status)can_x->rf0_bit.rf0ff;
+      break;
+    case CAN_RF0OF_FLAG:
+      bit_status = (flag_status)can_x->rf0_bit.rf0of;
+      break;
+    case CAN_RF1MN_FLAG:
+      if(can_x->rf1_bit.rf1mn != 0)
+      {
+        bit_status = SET;
+      }
+      else
+      {
+        bit_status = RESET;
+      }
+      break;
+    case CAN_RF1FF_FLAG:
+      bit_status = (flag_status)can_x->rf1_bit.rf1ff;
+      break;
+    case CAN_RF1OF_FLAG:
+      bit_status = (flag_status)can_x->rf1_bit.rf1of;
+      break;
+    case CAN_QDZIF_FLAG:
+      bit_status = (flag_status)can_x->msts_bit.qdzif;
+      break;
+    case CAN_EDZC_FLAG:
+      if((can_x->msts_bit.dzc != RESET) ||(can_x->msts_bit.edzif != RESET))
+      {
+        bit_status = SET;
+      }
+      else
+      {
+        bit_status = RESET;
+      }
+      break;
+    case CAN_TMEF_FLAG:
+      if((can_x->tsts_bit.tm0ef != RESET) || (can_x->tsts_bit.tm1ef != RESET) || (can_x->tsts_bit.tm2ef != RESET))
+      {
+        bit_status = SET;
+      }
+      else
+      {
+        bit_status = RESET;
+      }
+      break;
+    default:
+      bit_status = RESET;
+      break;
+  }
+  return bit_status;
+}
+
+/**
+  * @brief  clear flag of the specified can peripheral.
+  * @param  can_x: select the can peripheral.
+  *         this parameter can be one of the following values:
+  *         CAN1,CAN2.
+  * @param  can_flag: select the flag.
+  *         this parameter can be one of the following flags:
+  *         - CAN_EAF_FLAG
+  *         - CAN_EPF_FLAG
+  *         - CAN_BOF_FLAG
+  *         - CAN_ETR_FLAG
+  *         - CAN_EOIF_FLAG
+  *         - CAN_TM0TCF_FLAG
+  *         - CAN_TM1TCF_FLAG
+  *         - CAN_TM2TCF_FLAG
+  *         - CAN_RF0FF_FLAG
+  *         - CAN_RF0OF_FLAG
+  *         - CAN_RF1FF_FLAG
+  *         - CAN_RF1OF_FLAG
+  *         - CAN_QDZIF_FLAG
+  *         - CAN_EDZC_FLAG
+  *         - CAN_TMEF_FLAG
+  *         - CAN_ETR_SOFTWARE_FLAG
+  *         note:CAN_RF0MN_FLAG and CAN_RF1MN_FLAG can not clear by this function
+  * @retval none.
+  */
+void can_flag_clear(can_type* can_x, uint32_t can_flag)
+{
+  switch(can_flag)
+  {
+    case CAN_EAF_FLAG:
+    case CAN_EPF_FLAG:
+    case CAN_BOF_FLAG:
+    case CAN_EOIF_FLAG:
+      can_x->msts = CAN_MSTS_EOIF_VAL;
+      break;
+    case CAN_ETR_FLAG:
+      can_x->msts = CAN_MSTS_EOIF_VAL;
+      can_x->ests = 0;
+      break;
+    case CAN_TM0TCF_FLAG:
+      can_x->tsts = CAN_TSTS_TM0TCF_VAL;
+      break;
+    case CAN_TM1TCF_FLAG:
+      can_x->tsts = CAN_TSTS_TM1TCF_VAL;
+      break;
+    case CAN_TM2TCF_FLAG:
+      can_x->tsts = CAN_TSTS_TM2TCF_VAL;
+      break;
+    case CAN_RF0FF_FLAG:
+      can_x->rf0 = CAN_RF0_RF0FF_VAL;
+      break;
+    case CAN_RF0OF_FLAG:
+      can_x->rf0 = CAN_RF0_RF0OF_VAL;
+      break;
+    case CAN_RF1FF_FLAG:
+      can_x->rf1 = CAN_RF1_RF1FF_VAL;
+      break;
+    case CAN_RF1OF_FLAG:
+      can_x->rf1 = CAN_RF1_RF1OF_VAL;
+      break;
+    case CAN_QDZIF_FLAG:
+      can_x->msts = CAN_MSTS_QDZIF_VAL;
+      break;
+    case CAN_EDZC_FLAG:
+      can_x->msts = CAN_MSTS_EDZIF_VAL;
+      break;
+    case CAN_TMEF_FLAG:
+      can_x->tsts = CAN_TSTS_TM0TCF_VAL | CAN_TSTS_TM1TCF_VAL | CAN_TSTS_TM2TCF_VAL;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_crc.c

@@ -0,0 +1,162 @@
+/**
+  **************************************************************************
+  * @file     at32f413_crc.c
+  * @brief    contains all the functions for the crc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup CRC
+  * @brief CRC driver modules
+  * @{
+  */
+
+#ifdef CRC_MODULE_ENABLED
+
+/** @defgroup CRC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the crc data register.
+  * @param  none
+  * @retval none
+  */
+void crc_data_reset(void)
+{
+  /* reset crc generator */
+  CRC->ctrl_bit.rst = 0x1;
+}
+
+/**
+  * @brief  compute the 32-bit crc of a given data word(32-bit).
+  * @param  data: data word(32-bit) to compute its crc
+  * @retval 32-bit crc
+  */
+uint32_t crc_one_word_calculate(uint32_t data)
+{
+  CRC->dt = data;
+  return (CRC->dt);
+}
+
+/**
+  * @brief  compute the 32-bit crc of a given buffer of data word(32-bit).
+  * @param  pbuffer: pointer to the buffer containing the data to be computed
+  * @param  length: length of the buffer to be computed
+  * @retval 32-bit crc
+  */
+uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length)
+{
+  uint32_t index = 0;
+
+  for(index = 0; index < length; index++)
+  {
+    CRC->dt = pbuffer[index];
+  }
+
+  return (CRC->dt);
+}
+
+/**
+  * @brief  return the current crc value.
+  * @param  none
+  * @retval 32-bit crc
+  */
+uint32_t crc_data_get(void)
+{
+  return (CRC->dt);
+}
+
+/**
+  * @brief  store a 8-bit data in the common data register.
+  * @param  cdt_value: 8-bit value to be stored in the common data register
+  * @retval none
+  */
+void crc_common_data_set(uint8_t cdt_value)
+{
+  CRC->cdt_bit.cdt = cdt_value;
+}
+
+/**
+  * @brief  return the 8-bit data stored in the common data register
+  * @param  none
+  * @retval 8-bit value of the common data register
+  */
+uint8_t crc_common_data_get(void)
+{
+  return (CRC->cdt_bit.cdt);
+}
+
+/**
+  * @brief  set the 32-bit initial data of crc
+  * @param  value: initial data
+  * @retval none
+  */
+void crc_init_data_set(uint32_t value)
+{
+  CRC->idt = value;
+}
+
+/**
+  * @brief  control the reversal of the bit order in the input data
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRC_REVERSE_INPUT_NO_AFFECTE
+  *         - CRC_REVERSE_INPUT_BY_BYTE
+  *         - CRC_REVERSE_INPUT_BY_HALFWORD
+  *         - CRC_REVERSE_INPUT_BY_WORD
+  * @retval none.
+  */
+void crc_reverse_input_data_set(crc_reverse_input_type value)
+{
+  CRC->ctrl_bit.revid = value;
+}
+
+/**
+  * @brief  control the reversal of the bit order in the output data
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRC_REVERSE_OUTPUT_NO_AFFECTE
+  *         - CRC_REVERSE_OUTPUT_DATA
+  * @retval none.
+  */
+void crc_reverse_output_data_set(crc_reverse_output_type value)
+{
+  CRC->ctrl_bit.revod = value;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_crm.c

@@ -0,0 +1,822 @@
+/**
+  **************************************************************************
+  * @file     at32f413_crm.c
+  * @brief    contains all the functions for the crm firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup CRM
+  * @brief CRM driver modules
+  * @{
+  */
+
+#ifdef CRM_MODULE_ENABLED
+
+/** @defgroup CRM_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the crm register
+  * @param  none
+  * @retval none
+  */
+void crm_reset(void)
+{
+  /* reset the crm clock configuration to the default reset state(for debug purpose) */
+  /* set hicken bit */
+  CRM->ctrl_bit.hicken = TRUE;
+
+  /* wait hick stable */
+  while(CRM->ctrl_bit.hickstbl != SET);
+
+  /* hick used as system clock */
+  CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
+
+  /* wait sclk switch status */
+  while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
+
+  /* reset hexten, hextbyps, cfden and pllen bits */
+  CRM->ctrl &= ~(0x010D0000U);
+
+  /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
+     clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
+  CRM->cfg = 0;
+
+  /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
+  CRM->misc1 = 0;
+
+  /* disable all interrupts enable and clear pending bits  */
+  CRM->clkint = 0x009F0000;
+}
+
+/**
+  * @brief  enable or disable crm low speed external crystal bypass
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_lext_bypass(confirm_state new_state)
+{
+  CRM->bpdc_bit.lextbyps = new_state;
+}
+
+/**
+  * @brief  enable or disable crm high speed external crystal bypass
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_hext_bypass(confirm_state new_state)
+{
+  CRM->ctrl_bit.hextbyps = new_state;
+}
+
+/**
+  * @brief  get crm flag status
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         - CRM_HICK_STABLE_FLAG
+  *         - CRM_HEXT_STABLE_FLAG
+  *         - CRM_PLL_STABLE_FLAG
+  *         - CRM_LEXT_STABLE_FLAG
+  *         - CRM_LICK_STABLE_FLAG
+  *         - CRM_NRST_RESET_FLAG
+  *         - CRM_POR_RESET_FLAG
+  *         - CRM_SW_RESET_FLAG
+  *         - CRM_WDT_RESET_FLAG
+  *         - CRM_WWDT_RESET_FLAG
+  *         - CRM_LOWPOWER_RESET_FLAG
+  *         interrupt flag:
+  *         - CRM_LICK_READY_INT_FLAG
+  *         - CRM_LEXT_READY_INT_FLAG
+  *         - CRM_HICK_READY_INT_FLAG
+  *         - CRM_HEXT_READY_INT_FLAG
+  *         - CRM_PLL_READY_INT_FLAG
+  *         - CRM_CLOCK_FAILURE_INT_FLAG
+  * @retval flag_status (SET or RESET)
+  */
+flag_status crm_flag_get(uint32_t flag)
+{
+  flag_status status = RESET;
+  if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+  return status;
+}
+
+/**
+  * @brief  wait for hext stable
+  * @param  none
+  * @retval error_status (ERROR or SUCCESS)
+  */
+error_status crm_hext_stable_wait(void)
+{
+  uint32_t stable_cnt = 0;
+  error_status status = ERROR;
+
+  while((crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET) && (stable_cnt < HEXT_STARTUP_TIMEOUT))
+  {
+    stable_cnt ++;
+  }
+
+  if(crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    status = SUCCESS;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  set the hick trimming value
+  * @param  trim_value (0x00~0x3F)
+  * @retval none
+  */
+void crm_hick_clock_trimming_set(uint8_t trim_value)
+{
+  CRM->ctrl_bit.hicktrim = trim_value;
+}
+
+/**
+  * @brief  set the crm calibration value
+  * @param  cali_value (0x00~0xFF)
+  * @retval none
+  */
+void crm_hick_clock_calibration_set(uint8_t cali_value)
+{
+  /* enable write hick calibration */
+  CRM->misc1_bit.hickcal_key = 0x5A;
+
+  /* write hick calibration value */
+  CRM->ctrl_bit.hickcal = cali_value;
+
+  /* disable write hick calibration */
+  CRM->misc1_bit.hickcal_key = 0x0;
+}
+
+/**
+  * @brief  enable or disable the peripheral clock
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_DMA1_PERIPH_CLOCK         - CRM_DMA2_PERIPH_CLOCK         - CRM_CRC_PERIPH_CLOCK         - CRM_SDIO1_PERIPH_CLOCK
+  *         - CRM_IOMUX_PERIPH_CLOCK        - CRM_GPIOA_PERIPH_CLOCK        - CRM_GPIOB_PERIPH_CLOCK       - CRM_GPIOC_PERIPH_CLOCK
+  *         - CRM_GPIOD_PERIPH_CLOCK        - CRM_GPIOF_PERIPH_CLOCK        - CRM_ADC1_PERIPH_CLOCK        - CRM_ADC2_PERIPH_CLOCK
+  *         - CRM_TMR1_PERIPH_CLOCK         - CRM_SPI1_PERIPH_CLOCK         - CRM_TMR8_PERIPH_CLOCK        - CRM_USART1_PERIPH_CLOCK
+  *         - CRM_TMR9_PERIPH_CLOCK         - CRM_TMR10_PERIPH_CLOCK        - CRM_TMR11_PERIPH_CLOCK       - CRM_ACC_PERIPH_CLOCK
+  *         - CRM_TMR3_PERIPH_CLOCK         - CRM_TMR4_PERIPH_CLOCK         - CRM_TMR5_PERIPH_CLOCK        - CRM_WWDT_PERIPH_CLOCK
+  *         - CRM_SPI2_PERIPH_CLOCK         - CRM_USART2_PERIPH_CLOCK       - CRM_USART3_PERIPH_CLOCK      - CRM_UART4_PERIPH_CLOCK
+  *         - CRM_UART5_PERIPH_CLOCK        - CRM_I2C1_PERIPH_CLOCK         - CRM_I2C2_PERIPH_CLOCK        - CRM_USB_PERIPH_CLOCK
+  *         - CRM_CAN1_PERIPH_CLOCK         - CRM_BPR_PERIPH_CLOCK          - CRM_PWC_PERIPH_CLOCK         - CRM_CAN2_PERIPH_CLOCK
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state)
+{
+  /* enable periph clock */
+  if(TRUE == new_state)
+  {
+    CRM_REG(value) |= CRM_REG_BIT(value);
+  }
+  /* disable periph clock */
+  else
+  {
+    CRM_REG(value) &= ~(CRM_REG_BIT(value));
+  }
+}
+
+/**
+  * @brief  enable or disable the peripheral reset
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_IOMUX_PERIPH_RESET        - CRM_EXINT_PERIPH_RESET        - CRM_GPIOA_PERIPH_RESET       - CRM_GPIOB_PERIPH_RESET
+  *         - CRM_GPIOC_PERIPH_RESET        - CRM_GPIOD_PERIPH_RESET        - CRM_GPIOF_PERIPH_RESET       - CRM_ADC1_PERIPH_RESET
+  *         - CRM_ADC2_PERIPH_RESET         - CRM_TMR1_PERIPH_RESET         - CRM_SPI1_PERIPH_RESET        - CRM_TMR8_PERIPH_RESET
+  *         - CRM_USART1_PERIPH_RESET       - CRM_TMR9_PERIPH_RESET         - CRM_TMR10_PERIPH_RESET       - CRM_TMR11_PERIPH_RESET
+  *         - CRM_ACC_PERIPH_RESET          - CRM_TMR2_PERIPH_RESET         - CRM_TMR3_PERIPH_RESET        - CRM_TMR4_PERIPH_RESET
+  *         - CRM_TMR5_PERIPH_RESET         - CRM_WWDT_PERIPH_RESET         - CRM_SPI2_PERIPH_RESET        - CRM_USART2_PERIPH_RESET
+  *         - CRM_USART3_PERIPH_RESET       - CRM_UART4_PERIPH_RESET        - CRM_UART5_PERIPH_RESET       - CRM_I2C1_PERIPH_RESET
+  *         - CRM_I2C2_PERIPH_RESET         - CRM_USB_PERIPH_RESET          - CRM_CAN1_PERIPH_RESET        - CRM_BPR_PERIPH_RESET
+  *         - CRM_PWC_PERIPH_RESET          - CRM_CAN2_PERIPH_RESET
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
+{
+  /* enable periph reset */
+  if(new_state == TRUE)
+  {
+    CRM_REG(value) |= (CRM_REG_BIT(value));
+  }
+  /* disable periph reset */
+  else
+  {
+    CRM_REG(value) &= ~(CRM_REG_BIT(value));
+  }
+}
+
+/**
+  * @brief  enable or disable the peripheral clock in sleep mode
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_SRAM_PERIPH_CLOCK_SLEEP_MODE
+  *         - CRM_FLASH_PERIPH_CLOCK_SLEEP_MODE
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_periph_sleep_mode_clock_enable(crm_periph_clock_sleepmd_type value, confirm_state new_state)
+{
+  /* enable periph clock in sleep mode */
+  if(new_state == TRUE)
+  {
+    CRM_REG(value) |= (CRM_REG_BIT(value));
+  }
+  /* disable perph clock in sleep mode */
+  else
+  {
+    CRM_REG(value) &= ~(CRM_REG_BIT(value));
+  }
+}
+
+/**
+  * @brief  enable or disable the crm clock source
+  * @param  source
+  *         this parameter can be one of the following values:
+  *         - CRM_CLOCK_SOURCE_HICK
+  *         - CRM_CLOCK_SOURCE_HEXT
+  *         - CRM_CLOCK_SOURCE_PLL
+  *         - CRM_CLOCK_SOURCE_LEXT
+  *         - CRM_CLOCK_SOURCE_LICK
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
+{
+  switch(source)
+  {
+    case CRM_CLOCK_SOURCE_HICK:
+      CRM->ctrl_bit.hicken = new_state;
+      break;
+    case CRM_CLOCK_SOURCE_HEXT:
+      CRM->ctrl_bit.hexten = new_state;
+      break;
+    case CRM_CLOCK_SOURCE_PLL:
+      CRM->ctrl_bit.pllen = new_state;
+      break;
+    case CRM_CLOCK_SOURCE_LEXT:
+      CRM->bpdc_bit.lexten = new_state;
+      break;
+    case CRM_CLOCK_SOURCE_LICK:
+      CRM->ctrlsts_bit.licken = new_state;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  clear the crm reset flags
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         reset flag:
+  *         - CRM_NRST_RESET_FLAG
+  *         - CRM_POR_RESET_FLAG
+  *         - CRM_SW_RESET_FLAG
+  *         - CRM_WDT_RESET_FLAG
+  *         - CRM_WWDT_RESET_FLAG
+  *         - CRM_LOWPOWER_RESET_FLAG
+  *         - CRM_ALL_RESET_FLAG
+  *         interrupt flag:
+  *         - CRM_LICK_READY_INT_FLAG
+  *         - CRM_LEXT_READY_INT_FLAG
+  *         - CRM_HICK_READY_INT_FLAG
+  *         - CRM_HEXT_READY_INT_FLAG
+  *         - CRM_PLL_READY_INT_FLAG
+  *         - CRM_CLOCK_FAILURE_INT_FLAG
+  * @retval none
+  */
+void crm_flag_clear(uint32_t flag)
+{
+  switch(flag)
+  {
+    case CRM_NRST_RESET_FLAG:
+    case CRM_POR_RESET_FLAG:
+    case CRM_SW_RESET_FLAG:
+    case CRM_WDT_RESET_FLAG:
+    case CRM_WWDT_RESET_FLAG:
+    case CRM_LOWPOWER_RESET_FLAG:
+    case CRM_ALL_RESET_FLAG:
+      CRM->ctrlsts_bit.rstfc = TRUE;
+      while(CRM->ctrlsts_bit.rstfc == TRUE);
+      break;
+    case CRM_LICK_READY_INT_FLAG:
+      CRM->clkint_bit.lickstblfc = TRUE;
+      break;
+    case CRM_LEXT_READY_INT_FLAG:
+      CRM->clkint_bit.lextstblfc = TRUE;
+      break;
+    case CRM_HICK_READY_INT_FLAG:
+      CRM->clkint_bit.hickstblfc = TRUE;
+      break;
+    case CRM_HEXT_READY_INT_FLAG:
+      CRM->clkint_bit.hextstblfc = TRUE;
+      break;
+    case CRM_PLL_READY_INT_FLAG:
+      CRM->clkint_bit.pllstblfc = TRUE;
+      break;
+    case CRM_CLOCK_FAILURE_INT_FLAG:
+      CRM->clkint_bit.cfdfc = TRUE;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  select rtc clock
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_RTC_CLOCK_LEXT
+  *         - CRM_RTC_CLOCK_LICK
+  *         - CRM_RTC_CLOCK_HEXT_DIV
+  * @retval none
+  */
+void crm_rtc_clock_select(crm_rtc_clock_type value)
+{
+  CRM->bpdc_bit.rtcsel = value;
+}
+
+/**
+  * @brief  enable or disable rtc
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_rtc_clock_enable(confirm_state new_state)
+{
+  CRM->bpdc_bit.rtcen = new_state;
+}
+
+/**
+  * @brief  set crm ahb division
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_AHB_DIV_1
+  *         - CRM_AHB_DIV_2
+  *         - CRM_AHB_DIV_4
+  *         - CRM_AHB_DIV_8
+  *         - CRM_AHB_DIV_16
+  *         - CRM_AHB_DIV_64
+  *         - CRM_AHB_DIV_128
+  *         - CRM_AHB_DIV_256
+  *         - CRM_AHB_DIV_512
+  * @retval none
+  */
+void crm_ahb_div_set(crm_ahb_div_type value)
+{
+  CRM->cfg_bit.ahbdiv = value;
+}
+
+/**
+  * @brief  set crm apb1 division
+  * @note   the maximum frequency of APB1/APB2 clock is 100 MHz
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_APB1_DIV_1
+  *         - CRM_APB1_DIV_2
+  *         - CRM_APB1_DIV_4
+  *         - CRM_APB1_DIV_8
+  *         - CRM_APB1_DIV_16
+  * @retval none
+  */
+void crm_apb1_div_set(crm_apb1_div_type value)
+{
+  CRM->cfg_bit.apb1div = value;
+}
+
+/**
+  * @brief  set crm apb2 division
+  * @note   the maximum frequency of APB1/APB2 clock is 100 MHz
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_APB2_DIV_1
+  *         - CRM_APB2_DIV_2
+  *         - CRM_APB2_DIV_4
+  *         - CRM_APB2_DIV_8
+  *         - CRM_APB2_DIV_16
+  * @retval none
+  */
+void crm_apb2_div_set(crm_apb2_div_type value)
+{
+  CRM->cfg_bit.apb2div = value;
+}
+
+/**
+  * @brief  set crm adc division
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_ADC_DIV_2
+  *         - CRM_ADC_DIV_4
+  *         - CRM_ADC_DIV_6
+  *         - CRM_ADC_DIV_8
+  *         - CRM_ADC_DIV_12
+  *         - CRM_ADC_DIV_16
+  * @retval none
+  */
+void crm_adc_clock_div_set(crm_adc_div_type div_value)
+{
+  CRM->cfg_bit.adcdiv_l = div_value & 0x03;
+  CRM->cfg_bit.adcdiv_h = (div_value >> 2) & 0x01;
+}
+
+/**
+  * @brief  set crm usb division
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_USB_DIV_1_5
+  *         - CRM_USB_DIV_1
+  *         - CRM_USB_DIV_2_5
+  *         - CRM_USB_DIV_2
+  *         - CRM_USB_DIV_3_5
+  *         - CRM_USB_DIV_3
+  *         - CRM_USB_DIV_4
+  * @retval none
+  */
+void crm_usb_clock_div_set(crm_usb_div_type div_value)
+{
+  CRM->cfg_bit.usbdiv_l = div_value & 0x03;
+  CRM->cfg_bit.usbdiv_h = (div_value >> 2) & 0x01;
+}
+
+/**
+  * @brief  enable or disable clock failure detection
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_clock_failure_detection_enable(confirm_state new_state)
+{
+  CRM->ctrl_bit.cfden = new_state;
+}
+
+/**
+  * @brief  battery powered domain software reset
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_battery_powered_domain_reset(confirm_state new_state)
+{
+  CRM->bpdc_bit.bpdrst = new_state;
+}
+
+/**
+  * @brief  config crm pll
+  * @param  clock_source
+  *         this parameter can be one of the following values:
+  *         - CRM_PLL_SOURCE_HICK
+  *         - CRM_PLL_SOURCE_HEXT
+  *         - CRM_PLL_SOURCE_HEXT_DIV
+  * @param  mult_value (CRM_PLL_MULT_2~64)
+  * @param  pll_range
+  *         this parameter can be one of the following values:
+  *         - CRM_PLL_OUTPUT_RANGE_LE72MHZ
+  *         - CRM_PLL_OUTPUT_RANGE_GT72MHZ
+  * @retval none
+  */
+void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value, crm_pll_output_range_type pll_range)
+{
+  /* config pll clock source */
+  if(clock_source == CRM_PLL_SOURCE_HICK)
+  {
+    CRM->cfg_bit.pllrcs = FALSE;
+    CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV;
+  }
+  else
+  {
+    CRM->cfg_bit.pllrcs = TRUE;
+    if(CRM_PLL_SOURCE_HEXT == clock_source)
+    {
+      CRM->cfg_bit.pllhextdiv = FALSE;
+    }
+    else
+    {
+      CRM->cfg_bit.pllhextdiv = TRUE;
+    }
+  }
+
+  /* config pll multiplication factor */
+  CRM->cfg_bit.pllmult_l = (mult_value & 0x0F);
+  CRM->cfg_bit.pllmult_h = ((mult_value & 0x30) >> 4);
+
+  /* config pll output range */
+  CRM->cfg_bit.pllrange = pll_range;
+}
+
+/**
+  * @brief  select system clock source
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_SCLK_HICK
+  *         - CRM_SCLK_HEXT
+  *         - CRM_SCLK_PLL
+  * @retval none
+  */
+void crm_sysclk_switch(crm_sclk_type value)
+{
+  CRM->cfg_bit.sclksel = value;
+}
+
+/**
+  * @brief  indicate which clock source is used as system clock
+  * @param  none
+  * @retval crm_sclk
+  *         this return can be one of the following values:
+  *         - CRM_SCLK_HICK
+  *         - CRM_SCLK_HEXT
+  *         - CRM_SCLK_PLL
+  */
+crm_sclk_type crm_sysclk_switch_status_get(void)
+{
+  return (crm_sclk_type)CRM->cfg_bit.sclksts;
+}
+
+/**
+  * @brief  get crm clocks freqency
+  * @param  clocks
+  *         - pointer to the crm_clocks_freq structure
+  * @retval none
+  */
+void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
+{
+  uint32_t pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
+  crm_sclk_type sclk_source;
+
+  static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  static const uint8_t ahb_apb1_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+  static const uint8_t ahb_apb2_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+  static const uint8_t adc_div_table[8] = {2, 4, 6, 8, 2, 12, 8, 16};
+
+  /* get sclk source */
+  sclk_source = crm_sysclk_switch_status_get();
+
+  switch(sclk_source)
+  {
+    case CRM_SCLK_HICK:
+      if(((CRM->misc3_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
+        clocks_struct->sclk_freq = HICK_VALUE * 6;
+      else
+        clocks_struct->sclk_freq = HICK_VALUE;
+      break;
+    case CRM_SCLK_HEXT:
+      clocks_struct->sclk_freq = HEXT_VALUE;
+      break;
+    case CRM_SCLK_PLL:
+      pll_clock_source = CRM->cfg_bit.pllrcs;
+      /* get multiplication factor */
+      pll_mult = CRM->cfg_bit.pllmult_l;
+      pll_mult_h = CRM->cfg_bit.pllmult_h;
+
+      /* process high bits */
+      if((pll_mult_h != 0U) || (pll_mult == 15U))
+      {
+          pll_mult += ((16U * pll_mult_h) + 1U);
+      }
+      else
+      {
+          pll_mult += 2U;
+      }
+
+      if (pll_clock_source == 0x00)
+      {
+        /* hick divided by 2 selected as pll clock entry */
+        clocks_struct->sclk_freq = (HICK_VALUE >> 1) * pll_mult;
+      }
+      else
+      {
+        /* hext selected as pll clock entry */
+        if (CRM->cfg_bit.pllhextdiv != RESET)
+        {
+          /* hext clock divided by 2 */
+          clocks_struct->sclk_freq = (HEXT_VALUE / 2) * pll_mult;
+        }
+        else
+        {
+          clocks_struct->sclk_freq = HEXT_VALUE * pll_mult;
+        }
+      }
+      break;
+    default:
+      clocks_struct->sclk_freq = HICK_VALUE;
+      break;
+  }
+
+  /* compute sclk, ahbclk, abp1clk apb2clk and adcclk frequencies */
+  /* get ahb division */
+  temp = CRM->cfg_bit.ahbdiv;
+  div_value = sclk_ahb_div_table[temp];
+  /* ahbclk frequency */
+  clocks_struct->ahb_freq = clocks_struct->sclk_freq >> div_value;
+
+  /* get apb1 division */
+  temp = CRM->cfg_bit.apb1div;
+  div_value = ahb_apb1_div_table[temp];
+  /* apb1clk frequency */
+  clocks_struct->apb1_freq = clocks_struct->ahb_freq >> div_value;
+
+  /* get apb2 division */
+  temp = CRM->cfg_bit.apb2div;
+  div_value = ahb_apb2_div_table[temp];
+  /* apb2clk frequency */
+  clocks_struct->apb2_freq = clocks_struct->ahb_freq >> div_value;
+
+  /* get adc division */
+  temp = CRM->cfg_bit.adcdiv_h;
+  temp = ((temp << 2) | (CRM->cfg_bit.adcdiv_l));
+  div_value = adc_div_table[temp];
+  /* adcclk clock frequency */
+  clocks_struct->adc_freq = clocks_struct->apb2_freq / div_value;
+}
+
+/**
+  * @brief  set crm clkout
+  * @param  clkout
+  *         this parameter can be one of the following values:
+  *         - CRM_CLKOUT_NOCLK
+  *         - CRM_CLKOUT_LICK
+  *         - CRM_CLKOUT_LEXT
+  *         - CRM_CLKOUT_SCLK
+  *         - CRM_CLKOUT_HICK
+  *         - CRM_CLKOUT_HEXT
+  *         - CRM_CLKOUT_PLL_DIV_2
+  *         - CRM_CLKOUT_PLL_DIV_4
+  *         - CRM_CLKOUT_USB
+  *         - CRM_CLKOUT_ADC
+  * @retval none
+  */
+void crm_clock_out_set(crm_clkout_select_type clkout)
+{
+  CRM->cfg_bit.clkout_sel = clkout & 0x7;
+  CRM->misc1_bit.clkout_sel = (clkout >> 3) & 0x1;
+}
+
+/**
+  * @brief  config crm interrupt
+  * @param  int
+  *         this parameter can be any combination of the following values:
+  *         - CRM_LICK_STABLE_INT
+  *         - CRM_LEXT_STABLE_INT
+  *         - CRM_HICK_STABLE_INT
+  *         - CRM_HEXT_STABLE_INT
+  *         - CRM_PLL_STABLE_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state)
+{
+  if(new_state == TRUE)
+    CRM->clkint |= crm_int;
+  else
+    CRM->clkint &= ~crm_int;
+}
+
+/**
+  * @brief  auto step clock switch enable
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_auto_step_mode_enable(confirm_state new_state)
+{
+  if(new_state == TRUE)
+    CRM->misc3_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
+  else
+    CRM->misc3_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
+}
+
+/**
+  * @brief  usbdev interrupt remapping control
+  * @param  int_remap
+  *         this parameter can be one of the following values:
+  *         - CRM_USB_INT19_INT20
+  *         - CRM_USB_INT73_INT74
+  * @retval none
+  */
+void crm_usb_interrupt_remapping_set(crm_usb_int_map_type int_remap)
+{
+  CRM->intmap_bit.usbintmap = int_remap;
+}
+
+/**
+  * @brief  config hick divider select
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_HICK48_DIV6
+  *         - CRM_HICK48_NODIV
+  * @retval none
+  */
+void crm_hick_divider_select(crm_hick_div_6_type value)
+{
+  CRM->misc1_bit.hickdiv = value;
+}
+
+/**
+  * @brief  hick as system clock frequency select
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_HICK_SCLK_8MHZ
+  *         - CRM_HICK_SCLK_48MHZ
+  * @retval none
+  */
+void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
+{
+  crm_hick_divider_select(CRM_HICK48_NODIV);
+  CRM->misc3_bit.hick_to_sclk = value;
+}
+
+/**
+  * @brief  usb 48 mhz clock source select
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_USB_CLOCK_SOURCE_PLL
+  *         - CRM_USB_CLOCK_SOURCE_HICK
+  * @retval none
+  */
+void crm_usb_clock_source_select(crm_usb_clock_source_type value)
+{
+  if(value == CRM_USB_CLOCK_SOURCE_HICK)
+  {
+    crm_hick_sclk_frequency_select(CRM_HICK_SCLK_48MHZ);
+  }
+  CRM->misc3_bit.hick_to_usb = value;
+}
+
+/**
+  * @brief  enable or disable clkout direct to tmr10 channel 1
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_clkout_to_tmr10_enable(confirm_state new_state)
+{
+  CRM->misc2_bit.clk_to_tmr = new_state;
+}
+
+/**
+  * @brief  set crm clkout division
+  * @param  clkout_div
+  *         this parameter can be one of the following values:
+  *         - CRM_CLKOUT_DIV_1
+  *         - CRM_CLKOUT_DIV_2
+  *         - CRM_CLKOUT_DIV_4
+  *         - CRM_CLKOUT_DIV_8
+  *         - CRM_CLKOUT_DIV_16
+  *         - CRM_CLKOUT_DIV_64
+  *         - CRM_CLKOUT_DIV_128
+  *         - CRM_CLKOUT_DIV_256
+  *         - CRM_CLKOUT_DIV_512
+  * @retval none
+  */
+void crm_clkout_div_set(crm_clkout_div_type clkout_div)
+{
+  CRM->misc1_bit.clkoutdiv = clkout_div;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_debug.c

@@ -0,0 +1,102 @@
+/**
+  **************************************************************************
+  * @file     at32f413_debug.c
+  * @brief    contains all the functions for the debug firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup DEBUG
+  * @brief DEBUG driver modules
+  * @{
+  */
+
+#ifdef DEBUG_MODULE_ENABLED
+
+/** @defgroup DEBUG_private_functions
+  * @{
+  */
+
+/**
+  * @brief  get debug device id
+  * @param  none
+  * @retval the debug device id
+  */
+uint32_t debug_device_id_get(void)
+{
+  return DEBUGMCU->pid;
+}
+
+/**
+  * @brief  set periph debug mode
+  * @param  periph_debug_mode
+  *         this parameter can be any combination of the following values:
+  *         - DEBUG_SLEEP
+  *         - DEBUG_DEEPSLEEP
+  *         - DEBUG_STANDBY
+  *         - DEBUG_WDT_PAUSE
+  *         - DEBUG_WWDT_PAUSE
+  *         - DEBUG_TMR1_PAUSE
+  *         - DEBUG_TMR2_PAUSE
+  *         - DEBUG_TMR3_PAUSE
+  *         - DEBUG_TMR4_PAUSE
+  *         - DEBUG_CAN1_PAUSE
+  *         - DEBUG_I2C1_SMBUS_TIMEOUT
+  *         - DEBUG_I2C2_SMBUS_TIMEOUT
+  *         - DEBUG_TMR8_PAUSE
+  *         - DEBUG_TMR5_PAUSE
+  *         - DEBUG_CAN2_PAUSE
+  *         - DEBUG_TMR9_PAUSE
+  *         - DEBUG_TMR10_PAUSE
+  *         - DEBUG_TMR11_PAUSE
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state)
+{
+
+  if(new_state != FALSE)
+  {
+    DEBUGMCU->ctrl |= periph_debug_mode;
+  }
+  else
+  {
+    DEBUGMCU->ctrl &= ~periph_debug_mode;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_dma.c

@@ -0,0 +1,424 @@
+/**
+  **************************************************************************
+  * @file     at32f413_dma.c
+  * @brief    contains all the functions for the dma firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup DMA
+  * @brief DMA driver modules
+  * @{
+  */
+
+#ifdef DMA_MODULE_ENABLED
+
+/** @defgroup DMA_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the dmax channely registers.
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @retval none
+  */
+void dma_reset(dma_channel_type* dmax_channely)
+{
+  uint32_t temp = 0;
+  dmax_channely->ctrl_bit.chen = FALSE;
+  dmax_channely->ctrl = 0;
+  dmax_channely->dtcnt = 0;
+  dmax_channely->paddr = 0;
+  dmax_channely->maddr = 0;
+
+  temp = (uint32_t)dmax_channely;
+
+  if((temp & 0x4ff) < 0x408)
+  {
+    /* dma1 channel */
+    DMA1->clr |= (uint32_t)(0x0f << ((((temp & 0xff) - 0x08) / 0x14) * 4));
+  }
+  else if((temp & 0x4ff) < 0x488)
+  {
+    /* dma2 channel */
+    DMA2->clr |= (uint32_t)(0x0f << ((((temp & 0xff) - 0x08) / 0x14) * 4));
+  }
+}
+
+/**
+  * @brief  set the number of data to be transferred
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @param  data_number: the number of data to be transferred(0x0000~0xFFFF)
+  *         transfer.
+  * @retval none.
+  */
+void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number)
+{
+  dmax_channely->dtcnt = data_number;
+}
+
+/**
+  * @brief  get number of data from dtcnt register
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @retval the number of data.
+  */
+uint16_t dma_data_number_get(dma_channel_type* dmax_channely)
+{
+  return (uint16_t)dmax_channely->dtcnt;
+}
+
+/**
+  * @brief  enable or disable dma interrupt
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @param  dma_int:
+  *         this parameter can be any combination of the following values:
+  *         - DMA_FDT_INT
+  *         - DMA_HDT_INT
+  *         - DMA_DTERR_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state)
+{
+  if (new_state != FALSE)
+  {
+    dmax_channely->ctrl |= dma_int;
+  }
+  else
+  {
+    dmax_channely->ctrl &= ~dma_int;
+  }
+}
+
+/**
+  * @brief  enable or disable dma channely
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @param  new_state (TRUE or FALSE)
+  * @retval None
+  */
+void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state)
+{
+  dmax_channely->ctrl_bit.chen = new_state;
+}
+
+/**
+  * @brief  initialize the dma_x flexible function according to the specified parameters.
+  * @param  dma_x:
+  *         this parameter can be one of the following values:
+  *         - DMA1
+  *         - DMA2
+  * @param  flex_channelx:
+  *         this parameter can be one of the following values:
+  *         - FLEX_CHANNEL1
+  *         - FLEX_CHANNEL2
+  *         - FLEX_CHANNEL3
+  *         - FLEX_CHANNEL4
+  *         - FLEX_CHANNEL5
+  *         - FLEX_CHANNEL6
+  *         - FLEX_CHANNEL7
+  * @param  flexible_request: every peripheral have specified hardware_id.
+  *         this parameter can be one of the following values:
+  *         - DMA_FLEXIBLE_ADC1         - DMA_FLEXIBLE_SPI1_RX      - DMA_FLEXIBLE_SPI1_TX      - DMA_FLEXIBLE_SPI2_RX
+  *         - DMA_FLEXIBLE_SPI2_TX      - DMA_FLEXIBLE_UART1_RX     - DMA_FLEXIBLE_UART1_TX     - DMA_FLEXIBLE_UART2_RX
+  *         - DMA_FLEXIBLE_UART2_TX     - DMA_FLEXIBLE_UART3_RX     - DMA_FLEXIBLE_UART3_TX     - DMA_FLEXIBLE_UART4_RX
+  *         - DMA_FLEXIBLE_UART4_TX     - DMA_FLEXIBLE_UART5_RX     - DMA_FLEXIBLE_UART5_TX     - DMA_FLEXIBLE_I2C1_RX
+  *         - DMA_FLEXIBLE_I2C1_TX      - DMA_FLEXIBLE_I2C2_RX      - DMA_FLEXIBLE_I2C2_TX      - DMA_FLEXIBLE_SDIO1
+  *         - DMA_FLEXIBLE_TMR1_TRIG    - DMA_FLEXIBLE_TMR1_HALL    - DMA_FLEXIBLE_TMR1_OVERFLOW- DMA_FLEXIBLE_TMR1_CH1
+  *         - DMA_FLEXIBLE_TMR1_CH2     - DMA_FLEXIBLE_TMR1_CH3     - DMA_FLEXIBLE_TMR1_CH4     - DMA_FLEXIBLE_TMR2_TRIG
+  *         - DMA_FLEXIBLE_TMR2_OVERFLOW- DMA_FLEXIBLE_TMR2_CH1     - DMA_FLEXIBLE_TMR2_CH2     - DMA_FLEXIBLE_TMR2_CH3
+  *         - DMA_FLEXIBLE_TMR2_CH4     - DMA_FLEXIBLE_TMR3_TRIG    - DMA_FLEXIBLE_TMR3_OVERFLOW- DMA_FLEXIBLE_TMR3_CH1
+  *         - DMA_FLEXIBLE_TMR3_CH2     - DMA_FLEXIBLE_TMR3_CH3     - DMA_FLEXIBLE_TMR3_CH4     - DMA_FLEXIBLE_TMR4_TRIG
+  *         - DMA_FLEXIBLE_TMR4_OVERFLOW- DMA_FLEXIBLE_TMR4_CH1     - DMA_FLEXIBLE_TMR4_CH2     - DMA_FLEXIBLE_TMR4_CH3
+  *         - DMA_FLEXIBLE_TMR4_CH4     - DMA_FLEXIBLE_TMR5_TRIG    - DMA_FLEXIBLE_TMR5_OVERFLOW- DMA_FLEXIBLE_TMR5_CH1
+  *         - DMA_FLEXIBLE_TMR5_CH2     - DMA_FLEXIBLE_TMR5_CH3     - DMA_FLEXIBLE_TMR5_CH4     - DMA_FLEXIBLE_TMR8_TRIG
+  *         - DMA_FLEXIBLE_TMR8_HALL    - DMA_FLEXIBLE_TMR8_OVERFLOW- DMA_FLEXIBLE_TMR8_CH1     - DMA_FLEXIBLE_TMR8_CH2
+  *         - DMA_FLEXIBLE_TMR8_CH3     - DMA_FLEXIBLE_TMR8_CH4
+  * @retval none
+  */
+
+void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request)
+{
+  if(dma_x->src_sel1_bit.dma_flex_en == RESET)
+  {
+    dma_x->src_sel1_bit.dma_flex_en = TRUE;
+  }
+
+  if(flex_channelx == FLEX_CHANNEL1)
+  {
+    dma_x->src_sel0_bit.ch1_src = flexible_request;
+  }
+  else if(flex_channelx == FLEX_CHANNEL2)
+  {
+    dma_x->src_sel0_bit.ch2_src = flexible_request;
+  }
+  else if(flex_channelx == FLEX_CHANNEL3)
+  {
+    dma_x->src_sel0_bit.ch3_src = flexible_request;
+  }
+  else if(flex_channelx == FLEX_CHANNEL4)
+  {
+    dma_x->src_sel0_bit.ch4_src = flexible_request;
+  }
+  else if(flex_channelx == FLEX_CHANNEL5)
+  {
+    dma_x->src_sel1_bit.ch5_src = flexible_request;
+  }
+  else if(flex_channelx == FLEX_CHANNEL6)
+  {
+    dma_x->src_sel1_bit.ch6_src = flexible_request;
+  }
+  else
+  {
+    if(flex_channelx == FLEX_CHANNEL7)
+    {
+      dma_x->src_sel1_bit.ch7_src = flexible_request;
+    }
+  }
+}
+
+/**
+  * @brief  get dma flag
+  * @param  dmax_flag
+  *         this parameter can be one of the following values:
+  *         - DMA1_GL1_FLAG        - DMA1_FDT1_FLAG        - DMA1_HDT1_FLAG        - DMA1_DTERR1_FLAG
+  *         - DMA1_GL2_FLAG        - DMA1_FDT2_FLAG        - DMA1_HDT2_FLAG        - DMA1_DTERR2_FLAG
+  *         - DMA1_GL3_FLAG        - DMA1_FDT3_FLAG        - DMA1_HDT3_FLAG        - DMA1_DTERR3_FLAG
+  *         - DMA1_GL4_FLAG        - DMA1_FDT4_FLAG        - DMA1_HDT4_FLAG        - DMA1_DTERR4_FLAG
+  *         - DMA1_GL5_FLAG        - DMA1_FDT5_FLAG        - DMA1_HDT5_FLAG        - DMA1_DTERR5_FLAG
+  *         - DMA1_GL6_FLAG        - DMA1_FDT6_FLAG        - DMA1_HDT6_FLAG        - DMA1_DTERR6_FLAG
+  *         - DMA1_GL7_FLAG        - DMA1_FDT7_FLAG        - DMA1_HDT7_FLAG        - DMA1_DTERR7_FLAG
+  *         - DMA2_GL1_FLAG        - DMA2_FDT1_FLAG        - DMA2_HDT1_FLAG        - DMA2_DTERR1_FLAG
+  *         - DMA2_GL2_FLAG        - DMA2_FDT2_FLAG        - DMA2_HDT2_FLAG        - DMA2_DTERR2_FLAG
+  *         - DMA2_GL3_FLAG        - DMA2_FDT3_FLAG        - DMA2_HDT3_FLAG        - DMA2_DTERR3_FLAG
+  *         - DMA2_GL4_FLAG        - DMA2_FDT4_FLAG        - DMA2_HDT4_FLAG        - DMA2_DTERR4_FLAG
+  *         - DMA2_GL5_FLAG        - DMA2_FDT5_FLAG        - DMA2_HDT5_FLAG        - DMA2_DTERR5_FLAG
+  *         - DMA2_GL6_FLAG        - DMA2_FDT6_FLAG        - DMA2_HDT6_FLAG        - DMA2_DTERR6_FLAG
+  *         - DMA2_GL7_FLAG        - DMA2_FDT7_FLAG        - DMA2_HDT7_FLAG        - DMA2_DTERR7_FLAG
+  * @retval state of dma flag
+  */
+flag_status dma_flag_get(uint32_t dmax_flag)
+{
+  flag_status status = RESET;
+  uint32_t temp = 0;
+
+  if(dmax_flag > 0x10000000)
+  {
+    temp = DMA2->sts;
+  }
+  else
+  {
+    temp = DMA1->sts;
+  }
+
+  if ((temp & dmax_flag) != (uint16_t)RESET)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  clear dma flag
+  * @param  dmax_flag
+  *         this parameter can be one of the following values:
+  *         - DMA1_GL1_FLAG        - DMA1_FDT1_FLAG        - DMA1_HDT1_FLAG        - DMA1_DTERR1_FLAG
+  *         - DMA1_GL2_FLAG        - DMA1_FDT2_FLAG        - DMA1_HDT2_FLAG        - DMA1_DTERR2_FLAG
+  *         - DMA1_GL3_FLAG        - DMA1_FDT3_FLAG        - DMA1_HDT3_FLAG        - DMA1_DTERR3_FLAG
+  *         - DMA1_GL4_FLAG        - DMA1_FDT4_FLAG        - DMA1_HDT4_FLAG        - DMA1_DTERR4_FLAG
+  *         - DMA1_GL5_FLAG        - DMA1_FDT5_FLAG        - DMA1_HDT5_FLAG        - DMA1_DTERR5_FLAG
+  *         - DMA1_GL6_FLAG        - DMA1_FDT6_FLAG        - DMA1_HDT6_FLAG        - DMA1_DTERR6_FLAG
+  *         - DMA1_GL7_FLAG        - DMA1_FDT7_FLAG        - DMA1_HDT7_FLAG        - DMA1_DTERR7_FLAG
+  *         - DMA2_GL1_FLAG        - DMA2_FDT1_FLAG        - DMA2_HDT1_FLAG        - DMA2_DTERR1_FLAG
+  *         - DMA2_GL2_FLAG        - DMA2_FDT2_FLAG        - DMA2_HDT2_FLAG        - DMA2_DTERR2_FLAG
+  *         - DMA2_GL3_FLAG        - DMA2_FDT3_FLAG        - DMA2_HDT3_FLAG        - DMA2_DTERR3_FLAG
+  *         - DMA2_GL4_FLAG        - DMA2_FDT4_FLAG        - DMA2_HDT4_FLAG        - DMA2_DTERR4_FLAG
+  *         - DMA2_GL5_FLAG        - DMA2_FDT5_FLAG        - DMA2_HDT5_FLAG        - DMA2_DTERR5_FLAG
+  *         - DMA2_GL6_FLAG        - DMA2_FDT6_FLAG        - DMA2_HDT6_FLAG        - DMA2_DTERR6_FLAG
+  *         - DMA2_GL7_FLAG        - DMA2_FDT7_FLAG        - DMA2_HDT7_FLAG        - DMA2_DTERR7_FLAG
+  * @retval none
+  */
+void dma_flag_clear(uint32_t dmax_flag)
+{
+  if(dmax_flag > ((uint32_t)0x10000000))
+  {
+    DMA2->clr = (uint32_t)(dmax_flag & 0x0FFFFFFF);
+  }
+  else
+  {
+    DMA1->clr = dmax_flag;
+  }
+}
+
+/**
+  * @brief  dma init config with its default value.
+  * @param  dma_init_struct : pointer to a dma_init_type structure which will
+  *         be initialized.
+  * @retval none
+  */
+void dma_default_para_init(dma_init_type* dma_init_struct)
+{
+  dma_init_struct->peripheral_base_addr = 0x0;
+  dma_init_struct->memory_base_addr = 0x0;
+  dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
+  dma_init_struct->buffer_size = 0x0;
+  dma_init_struct->peripheral_inc_enable = FALSE;
+  dma_init_struct->memory_inc_enable = FALSE;
+  dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
+  dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
+  dma_init_struct->loop_mode_enable = FALSE;
+  dma_init_struct->priority = DMA_PRIORITY_LOW;
+}
+
+/**
+  * @brief  dma init
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @param  dma_initstruct : pointer to a dma_init_type structure.
+  * @retval none
+  */
+void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct)
+{
+  /* clear ctrl register dtd bit and m2m bit */
+  dmax_channely->ctrl &= 0xbfef;
+  dmax_channely->ctrl |= dma_init_struct->direction;
+
+  dmax_channely->ctrl_bit.chpl =  dma_init_struct->priority;
+  dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
+  dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
+  dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
+  dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
+  dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
+  dmax_channely->dtcnt = dma_init_struct->buffer_size;
+  dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
+  dmax_channely->maddr = dma_init_struct->memory_base_addr;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_exint.c

@@ -0,0 +1,234 @@
+/**
+  **************************************************************************
+  * @file     at32f413_exint.c
+  * @brief    contains all the functions for the exint firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup EXINT
+  * @brief EXINT driver modules
+  * @{
+  */
+
+#ifdef EXINT_MODULE_ENABLED
+
+/** @defgroup EXINT_private_functions
+  * @{
+  */
+
+/**
+  * @brief  exint reset
+  * @param  none
+  * @retval none
+  */
+void exint_reset(void)
+{
+  EXINT->inten = 0x00000000;
+  EXINT->polcfg1 = 0x00000000;
+  EXINT->polcfg2 = 0x00000000;
+  EXINT->evten = 0x00000000;
+  EXINT->intsts = 0x0007FFFF;
+}
+
+/**
+  * @brief  exint default para init
+  * @param  exint_struct
+  *         - to the structure of exint_init_type
+  * @retval none
+  */
+void exint_default_para_init(exint_init_type *exint_struct)
+{
+  exint_struct->line_enable = FALSE;
+  exint_struct->line_select = EXINT_LINE_NONE;
+  exint_struct->line_polarity = EXINT_TRIGGER_FALLING_EDGE;
+  exint_struct->line_mode = EXINT_LINE_EVENT;
+}
+
+/**
+  * @brief  exint init
+  * @param  exint_struct
+  *         - to the structure of exint_init_type
+  * @retval none
+  */
+void exint_init(exint_init_type *exint_struct)
+{
+  uint32_t line_index = 0;
+  line_index = exint_struct->line_select;
+
+  EXINT->inten &= ~line_index;
+  EXINT->evten &= ~line_index;
+
+  if(exint_struct->line_enable != FALSE)
+  {
+    if(exint_struct->line_mode == EXINT_LINE_INTERRUPUT)
+    {
+      EXINT->inten |= line_index;
+    }
+    else
+    {
+      EXINT->evten |= line_index;
+    }
+
+    EXINT->polcfg1 &= ~line_index;
+    EXINT->polcfg2 &= ~line_index;
+    if(exint_struct->line_polarity == EXINT_TRIGGER_RISING_EDGE)
+    {
+      EXINT->polcfg1 |= line_index;
+    }
+    else if(exint_struct->line_polarity == EXINT_TRIGGER_FALLING_EDGE)
+    {
+      EXINT->polcfg2 |= line_index;
+    }
+    else
+    {
+      EXINT->polcfg1 |= line_index;
+      EXINT->polcfg2 |= line_index;
+    }
+  }
+}
+
+/**
+  * @brief  clear exint flag
+  * @param  exint_line
+  *         this parameter can be any combination of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_17
+  *         - EXINT_LINE_18
+  * @retval none
+  */
+void exint_flag_clear(uint32_t exint_line)
+{
+  EXINT->intsts = exint_line;
+}
+
+/**
+  * @brief  get exint flag
+  * @param  exint_line
+  *         this parameter can be one of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_17
+  *         - EXINT_LINE_18
+  * @retval the new state of exint flag(SET or RESET).
+  */
+flag_status exint_flag_get(uint32_t exint_line)
+{
+  flag_status status = RESET;
+  uint32_t exint_flag =0;
+  exint_flag = EXINT->intsts & exint_line;
+  if((exint_flag != (uint16_t)RESET))
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+  return status;
+}
+
+/**
+  * @brief  generate exint software interrupt event
+  * @param  exint_line
+  *         this parameter can be one of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_17
+  *         - EXINT_LINE_18
+  * @retval none
+  */
+void exint_software_interrupt_event_generate(uint32_t exint_line)
+{
+  EXINT->swtrg |= exint_line;
+}
+
+/**
+  * @brief  enable or disable exint interrupt
+  * @param  exint_line
+  *         this parameter can be any combination of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_17
+  *         - EXINT_LINE_18
+  * @param  new_state: new state of exint interrupt.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    EXINT->inten |= exint_line;
+  }
+  else
+  {
+    EXINT->inten &= ~exint_line;
+  }
+}
+
+/**
+  * @brief  enable or disable exint event
+  * @param  exint_line
+  *         this parameter can be any combination of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_17
+  *         - EXINT_LINE_18
+  * @param  new_state: new state of exint event.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void exint_event_enable(uint32_t exint_line, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    EXINT->evten |= exint_line;
+  }
+  else
+  {
+    EXINT->evten &= ~exint_line;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_flash.c

@@ -0,0 +1,890 @@
+/**
+  **************************************************************************
+  * @file     at32f413_flash.c
+  * @brief    contains all the functions for the flash firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup FLASH
+  * @brief FLASH driver modules
+  * @{
+  */
+
+#ifdef FLASH_MODULE_ENABLED
+
+/** @defgroup FLASH_private_functions
+  * @{
+  */
+
+/**
+  * @brief  check whether the specified flash flag is set or not.
+  * @param  flash_flag: specifies the flash flag to check.
+  *         this parameter can be one of flash flag status:
+  *         - FLASH_OBF_FLAG
+  *         - FLASH_ODF_FLAG
+  *         - FLASH_PRGMERR_FLAG
+  *         - FLASH_EPPERR_FLAG
+  *         - FLASH_SPIM_OBF_FLAG
+  *         - FLASH_SPIM_ODF_FLAG
+  *         - FLASH_SPIM_PRGMERR_FLAG
+  *         - FLASH_SPIM_EPPERR_FLAG
+  *         - FLASH_USDERR_FLAG
+  * @retval the new state of flash_flag (SET or RESET).
+  */
+flag_status flash_flag_get(uint32_t flash_flag)
+{
+  flag_status status = RESET;
+  uint32_t flag_position;
+  flag_position = flash_flag & 0x70000000;
+  flash_flag &= 0x8FFFFFFF;
+  switch(flag_position)
+  {
+    case 0x00000000:
+      if(FLASH->sts & flash_flag)
+        status = SET;
+      break;
+    case 0x20000000:
+      if(FLASH->sts3 & flash_flag)
+        status = SET;
+      break;
+    case 0x40000000:
+      if(FLASH->usd & flash_flag)
+        status = SET;
+      break;
+    default:
+      break;
+  }
+  /* return the new state of flash_flag (SET or RESET) */
+  return status;
+}
+
+/**
+  * @brief  clear the flash flag.
+  * @param  flash_flag: specifies the flash flags to clear.
+  *         this parameter can be any combination of the following values:
+  *         - FLASH_ODF_FLAG
+  *         - FLASH_PRGMERR_FLAG
+  *         - FLASH_EPPERR_FLAG
+  *         - FLASH_SPIM_ODF_FLAG
+  *         - FLASH_SPIM_PRGMERR_FLAG
+  *         - FLASH_SPIM_EPPERR_FLAG
+  * @retval none
+  */
+void flash_flag_clear(uint32_t flash_flag)
+{
+  uint32_t flag_position;
+  flag_position = flash_flag & 0x70000000;
+  flash_flag &= 0x8FFFFFFF;
+  switch(flag_position)
+  {
+    case 0x00000000:
+      FLASH->sts = flash_flag;
+      break;
+    case 0x20000000:
+      FLASH->sts3 = flash_flag;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  return the flash operation status.
+  * @param  none
+  * @retval status: the returned value can be: FLASH_OPERATE_BUSY,
+  *         FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
+  */
+flash_status_type flash_operation_status_get(void)
+{
+  flash_status_type flash_status = FLASH_OPERATE_DONE;
+  if(FLASH->sts_bit.obf != RESET)
+  {
+    flash_status = FLASH_OPERATE_BUSY;
+  }
+  else if(FLASH->sts_bit.prgmerr != RESET)
+  {
+    flash_status = FLASH_PROGRAM_ERROR;
+  }
+  else if(FLASH->sts_bit.epperr != RESET)
+  {
+    flash_status = FLASH_EPP_ERROR;
+  }
+  else
+  {
+    flash_status = FLASH_OPERATE_DONE;
+  }
+  /* return the flash status */
+  return flash_status;
+}
+
+/**
+  * @brief  return the flash spim operation status.
+  * @param  none
+  * @retval status: the returned value can be: FLASH_OPERATE_BUSY,
+  *         FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
+  */
+flash_status_type flash_spim_operation_status_get(void)
+{
+  flash_status_type flash_status = FLASH_OPERATE_DONE;
+  if(FLASH->sts3_bit.obf != RESET)
+  {
+    flash_status = FLASH_OPERATE_BUSY;
+  }
+  else if(FLASH->sts3_bit.prgmerr != RESET)
+  {
+    flash_status = FLASH_PROGRAM_ERROR;
+  }
+  else if(FLASH->sts3_bit.epperr != RESET)
+  {
+    flash_status = FLASH_EPP_ERROR;
+  }
+  else
+  {
+    flash_status = FLASH_OPERATE_DONE;
+  }
+  /* return the flash status */
+  return flash_status;
+}
+
+/**
+  * @brief  wait for flash operation complete or timeout.
+  * @param  time_out: flash operation timeout
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_operation_wait_for(uint32_t time_out)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+  /* check for the flash status */
+  status = flash_operation_status_get();
+
+  while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
+  {
+    status = flash_operation_status_get();
+    time_out--;
+  }
+  if(time_out == 0x00)
+  {
+    status = FLASH_OPERATE_TIMEOUT;
+  }
+  /* return the status */
+  return status;
+}
+
+/**
+  * @brief  wait for flash spim operation complete or timeout.
+  * @param  time_out: flash operation timeout
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_spim_operation_wait_for(uint32_t time_out)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+  /* check for the flash status */
+  status = flash_spim_operation_status_get();
+
+  while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
+  {
+    status = flash_spim_operation_status_get();
+    time_out--;
+  }
+  if(time_out == 0x00)
+  {
+    status = FLASH_OPERATE_TIMEOUT;
+  }
+  /* return the operation status */
+  return status;
+}
+
+/**
+  * @brief  unlock the flash controller.
+  * @param  none
+  * @retval none
+  */
+void flash_unlock(void)
+{
+  FLASH->unlock = FLASH_UNLOCK_KEY1;
+  FLASH->unlock = FLASH_UNLOCK_KEY2;
+}
+
+/**
+  * @brief  unlock the flash spim controller.
+  * @param  none
+  * @retval none
+  */
+void flash_spim_unlock(void)
+{
+  FLASH->unlock3 = FLASH_UNLOCK_KEY1;
+  FLASH->unlock3 = FLASH_UNLOCK_KEY2;
+}
+
+/**
+  * @brief  lock the flash controller.
+  * @param  none
+  * @retval none
+  */
+void flash_lock(void)
+{
+  FLASH->ctrl_bit.oplk = TRUE;
+}
+
+/**
+  * @brief  lock the flash spim controller.
+  * @param  none
+  * @retval none
+  */
+void flash_spim_lock(void)
+{
+  FLASH->ctrl3_bit.oplk = TRUE;
+}
+
+/**
+  * @brief  erase a specified flash sector.
+  * @param  sector_address: the sector address to be erased.
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_sector_erase(uint32_t sector_address)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+  /* spim : external flash */
+  if(sector_address >= FLASH_SPIM_START_ADDR)
+  {
+    FLASH->ctrl3_bit.secers = TRUE;
+    FLASH->addr3 = sector_address;
+    FLASH->ctrl3_bit.erstr = TRUE;
+
+    /* wait for operation to be completed */
+    status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT);
+
+    /* disable the secers bit */
+    FLASH->ctrl3_bit.secers = FALSE;
+  }
+  else
+  {
+    FLASH->ctrl_bit.secers = TRUE;
+    FLASH->addr = sector_address;
+    FLASH->ctrl_bit.erstr = TRUE;
+
+    /* wait for operation to be completed */
+    status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+    /* disable the secers bit */
+    FLASH->ctrl_bit.secers = FALSE;
+  }
+  /* return the erase status */
+  return status;
+}
+
+/**
+  * @brief  erase flash all internal sectors.
+  * @param  none
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_internal_all_erase(void)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+
+  FLASH->ctrl_bit.bankers = TRUE;
+  FLASH->ctrl_bit.erstr = TRUE;
+
+  /* wait for operation to be completed */
+  status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+  /* disable the bankers bit */
+  FLASH->ctrl_bit.bankers = FALSE;
+
+  /* return the erase status */
+  return status;
+}
+
+/**
+  * @brief  erase flash spim sectors.
+  * @param  none
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_spim_all_erase(void)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+
+  FLASH->ctrl3_bit.chpers = TRUE;
+  FLASH->ctrl3_bit.erstr = TRUE;
+
+  /* wait for operation to be completed */
+  status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT);
+
+  /* disable the chpers bit */
+  FLASH->ctrl3_bit.chpers = FALSE;
+
+  /* return the erase status */
+  return status;
+}
+
+/**
+  * @brief  erase the flash user system data.
+  * @note   this functions erases all user system data except the fap byte.
+  * @param  none
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_user_system_data_erase(void)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+  uint16_t fap_val = FAP_RELIEVE_KEY;
+  /* get the flash access protection status */
+  if(flash_fap_status_get() != RESET)
+  {
+    fap_val = 0x0000;
+  }
+
+  /* unlock the user system data */
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+  while(FLASH->ctrl_bit.usdulks == RESET);
+
+  /* erase the user system data */
+  FLASH->ctrl_bit.usders = TRUE;
+  FLASH->ctrl_bit.erstr = TRUE;
+
+  /* wait for operation to be completed */
+  status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+  /* disable the usders bit */
+  FLASH->ctrl_bit.usders = FALSE;
+
+  if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY))
+  {
+    /* enable the user system data programming operation */
+    FLASH->ctrl_bit.usdprgm = TRUE;
+
+    /* restore the last flash access protection value */
+    USD->fap = (uint16_t)fap_val;
+
+    /* wait for operation to be completed */
+    status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+    /*disable the usdprgm bit */
+    FLASH->ctrl_bit.usdprgm = FALSE;
+  }
+
+  /* return the erase status */
+  return status;
+}
+
+/**
+  * @brief  program a word at a specified address.
+  * @param  address: specifies the address to be programmed, word alignment is recommended.
+  * @param  data: specifies the data to be programmed.
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_word_program(uint32_t address, uint32_t data)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+  /* spim : external flash */
+  if(address >= FLASH_SPIM_START_ADDR)
+  {
+    FLASH->ctrl3_bit.fprgm = TRUE;
+    *(__IO uint32_t*)address = data;
+    /* wait for operation to be completed */
+    status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT);
+
+    /* disable the fprgm bit */
+    FLASH->ctrl3_bit.fprgm = FALSE;
+  }
+  else
+  {
+    FLASH->ctrl_bit.fprgm = TRUE;
+    *(__IO uint32_t*)address = data;
+    /* wait for operation to be completed */
+    status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+    /* disable the fprgm bit */
+    FLASH->ctrl_bit.fprgm = FALSE;
+  }
+  /* return the program status */
+  return status;
+}
+
+/**
+  * @brief  program a halfword at a specified address.
+  * @param  address: specifies the address to be programmed, halfword alignment is recommended.
+  * @param  data: specifies the data to be programmed.
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_halfword_program(uint32_t address, uint16_t data)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+  /* spim : external flash */
+  if(address >= FLASH_SPIM_START_ADDR)
+  {
+    FLASH->ctrl3_bit.fprgm = TRUE;
+    *(__IO uint16_t*)address = data;
+    /* wait for operation to be completed */
+    status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT);
+
+    /* disable the fprgm bit */
+    FLASH->ctrl3_bit.fprgm = FALSE;
+  }
+  else
+  {
+    FLASH->ctrl_bit.fprgm = TRUE;
+    *(__IO uint16_t*)address = data;
+    /* wait for operation to be completed */
+    status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+    /* disable the fprgm bit */
+    FLASH->ctrl_bit.fprgm = FALSE;
+  }
+  /* return the program status */
+  return status;
+}
+
+/**
+  * @brief  program a byte at a specified address.
+  * @note   this function cannot be used to program spim.
+  * @param  address: specifies the address to be programmed.
+  * @param  data: specifies the data to be programmed.
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_byte_program(uint32_t address, uint8_t data)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+
+  FLASH->ctrl_bit.fprgm = TRUE;
+  *(__IO uint8_t*)address = data;
+  /* wait for operation to be completed */
+  status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+  /* disable the fprgm bit */
+  FLASH->ctrl_bit.fprgm = FALSE;
+
+  /* return the program status */
+  return status;
+}
+
+/**
+  * @brief  program a halfword at a specified user system data address.
+  * @param  address: specifies the address to be programmed.
+  * @param  data: specifies the data to be programmed.
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+
+  if(address == USD_BASE)
+  {
+    if(data != 0xA5)
+      return FLASH_OPERATE_DONE;
+  }
+  
+  /* unlock the user system data */
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+  while(FLASH->ctrl_bit.usdulks==RESET);
+
+  /* enable the user system data programming operation */
+  FLASH->ctrl_bit.usdprgm = TRUE;
+  *(__IO uint16_t*)address = data;
+
+  /* wait for operation to be completed */
+  status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+  /* disable the usdprgm bit */
+  FLASH->ctrl_bit.usdprgm = FALSE;
+
+  /* return the user system data program status */
+  return status;
+}
+
+/**
+  * @brief  config erase/program protection for the desired sectors.
+  * @param  sector_bits:
+  *         the pointer of the address of the sectors to be erase/program protected.
+  *         general every bit is used to protect the 4KB bytes, and the last one bit
+  *         is used to protect the rest.
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_epp_set(uint32_t *sector_bits)
+{
+  uint16_t epp_data[4] = {0xFFFF,0xFFFF,0xFFFF,0xFFFF};
+  flash_status_type status = FLASH_OPERATE_DONE;
+  sector_bits[0] = (uint32_t)(~sector_bits[0]);
+  epp_data[0] = (uint16_t)((sector_bits[0] >> 0) & 0xFF);
+  epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF);
+  epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF);
+  epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF);
+
+  /* unlock the user system data */
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+  while(FLASH->ctrl_bit.usdulks==RESET);
+
+  FLASH->ctrl_bit.usdprgm = TRUE;
+  USD->epp0 = epp_data[0];
+  /* wait for operation to be completed */
+  status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+  if(status == FLASH_OPERATE_DONE)
+  {
+    USD->epp1 = epp_data[1];
+    /* wait for operation to be completed */
+    status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+  }
+  if(status == FLASH_OPERATE_DONE)
+  {
+    USD->epp2 = epp_data[2];
+    /* wait for operation to be completed */
+    status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+  }
+  if(status == FLASH_OPERATE_DONE)
+  {
+    USD->epp3 = epp_data[3];
+    /* wait for operation to be completed */
+    status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+  }
+  /* disable the usdprgm bit */
+  FLASH->ctrl_bit.usdprgm = FALSE;
+
+  /* return the erase/program protection operation status */
+  return status;
+}
+
+/**
+  * @brief  return the flash erase/program protection status.
+  * @param  sector_bits: pointer to get the epps register.
+  * @retval none
+  */
+void flash_epp_status_get(uint32_t *sector_bits)
+{
+  /* return the flash erase/program protection register value */
+  sector_bits[0] = (uint32_t)(FLASH->epps);
+}
+
+/**
+  * @brief  enable or disable the flash access protection.
+  * @note   if the user has already programmed the other user system data before calling
+  *         this function, must re-program them since this function erase all user system data.
+  * @param  new_state: new state of the flash access protection.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_fap_enable(confirm_state new_state)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+
+  /* unlock the user system data */
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+  while(FLASH->ctrl_bit.usdulks==RESET);
+
+  FLASH->ctrl_bit.usders = TRUE;
+  FLASH->ctrl_bit.erstr = TRUE;
+  /* wait for operation to be completed */
+  status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+  /* disable the usders bit */
+  FLASH->ctrl_bit.usders = FALSE;
+
+  if(status == FLASH_OPERATE_DONE)
+  {
+    if(new_state == FALSE)
+    {
+      /* enable the user system data programming operation */
+      FLASH->ctrl_bit.usdprgm = TRUE;
+      USD->fap = FAP_RELIEVE_KEY;
+
+      /* Wait for operation to be completed */
+      status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+      /* disable the usdprgm bit */
+      FLASH->ctrl_bit.usdprgm = FALSE;
+    }
+  }
+
+  /* return the flash access protection operation status */
+  return status;
+}
+
+/**
+  * @brief  check the flash access protection status.
+  * @param  none
+  * @retval flash access protection status(SET or RESET)
+  */
+flag_status flash_fap_status_get(void)
+{
+  return (flag_status)FLASH->usd_bit.fap;
+}
+
+/**
+  * @brief  program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst.
+  * @param  usd_ssb: the system setting byte
+  * @note   this parameter usd_ssb must contain a combination of all the following 3 types of data
+  *         type 1: wdt_ato_en, select the wdt auto start
+  *         this data can be one of the following values:
+  *         - USD_WDT_ATO_DISABLE: disable wdt auto start
+  *         - USD_WDT_ATO_ENABLE: enable wdt auto start
+  *         type 2: depslp_rst, reset event when entering deepsleep mode.
+  *         this data can be one of the following values:
+  *         - USD_DEPSLP_NO_RST: no reset generated when entering in deepsleep
+  *         - USD_DEPSLP_RST: reset generated when entering in deepsleep
+  *         type 3: stdby_rst, reset event when entering standby mode.
+  *         this data can be one of the following values:
+  *         - USD_STDBY_NO_RST: no reset generated when entering in standby
+  *         - USD_STDBY_RST: reset generated when entering in standby
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_ssb_set(uint8_t usd_ssb)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+
+  /* unlock the user system data */
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+  FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+  while(FLASH->ctrl_bit.usdulks==RESET);
+
+  /* enable the user system data programming operation */
+  FLASH->ctrl_bit.usdprgm = TRUE;
+
+  USD->ssb = usd_ssb;
+  /* wait for operation to be completed */
+  status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+  /* disable the usdprgm bit */
+  FLASH->ctrl_bit.usdprgm = FALSE;
+
+  /* return the user system data program status */
+  return status;
+}
+
+/**
+  * @brief  return the flash system setting byte status.
+  * @param  none
+  * @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1) and stdby_rst(bit2).
+  */
+uint8_t flash_ssb_status_get(void)
+{
+  /* return the system setting byte status */
+  return (uint8_t)(FLASH->usd >> 2);
+}
+
+/**
+  * @brief  enable or disable the specified flash interrupts.
+  * @param  flash_int: specifies the flash interrupt sources to be enabled or disabled.
+  *         this parameter can be any combination of the following values:
+  *         - FLASH_ERR_INT
+  *         - FLASH_ODF_INT
+  *         - FLASH_SPIM_ERR_INT
+  *         - FLASH_SPIM_ODF_INT
+  * @param  new_state: new state of the specified flash interrupts.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state)
+{
+  if(flash_int & FLASH_ERR_INT)
+    FLASH->ctrl_bit.errie = new_state;
+  if(flash_int & FLASH_ODF_INT)
+    FLASH->ctrl_bit.odfie = new_state;
+  if(flash_int & FLASH_SPIM_ERR_INT)
+    FLASH->ctrl3_bit.errie = new_state;
+  if(flash_int & FLASH_SPIM_ODF_INT)
+    FLASH->ctrl3_bit.odfie = new_state;
+}
+
+/**
+  * @brief  select spim supports extended spi flash chip model.
+  * @param  mode: the extended spi flash model
+  * @retval none
+  */
+void flash_spim_model_select(flash_spim_model_type mode)
+{
+  FLASH->select = mode;
+}
+
+/**
+  * @brief  set the range of encryption in spim flash.
+  *         when the address is larger than this value, the writing data will be
+  *         directly written to spim without encryption.
+  * @param  decode_address: the end address of encrypted data in spim
+  * @retval none
+  */
+void flash_spim_encryption_range_set(uint32_t decode_address)
+{
+  FLASH->da = decode_address;
+}
+
+/**
+  * @brief  enable security library function.
+  * @param  pwd: slib password
+  *         start_sector: security library start sector
+  *         data_start_sector: security library d-bus area start sector
+  *         end_sector: security library end sector
+  * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+  *         FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+  */
+flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector)
+{
+  uint32_t slib_range;
+  flash_status_type status = FLASH_OPERATE_DONE;
+
+  /*check range param limits*/
+  if((start_sector>=data_start_sector) || ((data_start_sector > end_sector) && \
+     (data_start_sector != 0x7FF)) || (start_sector > end_sector))
+    return FLASH_PROGRAM_ERROR;
+
+
+  /* unlock slib cfg register */
+  FLASH->slib_unlock = SLIB_UNLOCK_KEY;
+  while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
+
+  slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \
+               ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \
+               (start_sector & FLASH_SLIB_START_SECTOR);
+  /* configure slib, set pwd and range */
+  FLASH->slib_set_pwd = pwd;
+  status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+  if(status == FLASH_OPERATE_DONE)
+  {
+    FLASH->slib_set_range = slib_range;
+    status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  disable slib when slib enabled.
+  * @param  pwd: slib password
+  * @retval success or error
+  */
+error_status flash_slib_disable(uint32_t pwd)
+{
+  flash_status_type status = FLASH_OPERATE_DONE;
+  /* write password to disable slib */
+  FLASH->slib_pwd_clr = pwd;
+
+  status = flash_operation_wait_for(ERASE_TIMEOUT);
+  if(status == FLASH_OPERATE_DONE)
+  {
+    if(FLASH->slib_misc_sts_bit.slib_pwd_ok)
+      return SUCCESS;
+    else
+      return ERROR;
+  }
+  return ERROR;
+}
+
+/**
+ * @brief  get remaining count of slib(range: 256~0).
+ * @param  none
+ * @retval uint32_t
+ */
+uint32_t flash_slib_remaining_count_get(void)
+{
+  return (uint32_t)FLASH->slib_misc_sts_bit.slib_rcnt;
+}
+
+/**
+  * @brief  get the slib state.
+  * @param  none
+  * @retval SET or RESET
+  */
+flag_status flash_slib_state_get(void)
+{
+  if(FLASH->slib_sts0_bit.slib_enf)
+    return SET;
+  else
+    return RESET;
+}
+
+/**
+ * @brief  get the start sector of slib.
+ * @param  none
+ * @retval uint16_t
+ */
+uint16_t flash_slib_start_sector_get(void)
+{
+  return (uint16_t)FLASH->slib_sts1_bit.slib_ss;
+}
+
+/**
+ * @brief  get the data start sector of slib.
+ * @param  none
+ * @retval uint16_t
+ */
+uint16_t flash_slib_datastart_sector_get(void)
+{
+  return (uint16_t)FLASH->slib_sts1_bit.slib_dat_ss;
+}
+
+/**
+ * @brief  get the end sector of slib.
+ * @param  none
+ * @retval uint16_t
+ */
+uint16_t flash_slib_end_sector_get(void)
+{
+  return (uint16_t)FLASH->slib_sts1_bit.slib_es;
+}
+
+/**
+  * @brief  flash crc calibration in main block.
+  * @param  start_sector: crc calibration start sector number
+  *         sector_cnt: crc calibration sector count
+  * @retval uint32: crc calibration result
+  */
+uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt)
+{
+  FLASH->crc_ctrl_bit.crc_ss = start_sector;
+  FLASH->crc_ctrl_bit.crc_sn = sector_cnt;
+  FLASH->crc_ctrl_bit.crc_strt = TRUE;
+  flash_operation_wait_for(OPERATION_TIMEOUT);
+  return FLASH->crc_chkr;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_gpio.c

@@ -0,0 +1,611 @@
+/**
+  **************************************************************************
+  * @file     at32f413_gpio.c
+  * @brief    contains all the functions for the gpio firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup GPIO
+  * @brief GPIO driver modules
+  * @{
+  */
+
+#ifdef GPIO_MODULE_ENABLED
+
+/** @defgroup GPIO_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the gpio register
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @retval none
+  */
+void gpio_reset(gpio_type *gpio_x)
+{
+  if(gpio_x == GPIOA)
+  {
+    crm_periph_reset(CRM_GPIOA_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOA_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOB)
+  {
+    crm_periph_reset(CRM_GPIOB_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOB_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOC)
+  {
+    crm_periph_reset(CRM_GPIOC_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOC_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOD)
+  {
+    crm_periph_reset(CRM_GPIOD_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOD_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOF)
+  {
+    crm_periph_reset(CRM_GPIOF_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOF_PERIPH_RESET, FALSE);
+  }
+}
+
+/**
+  * @brief  reset the mux functions (remap, event control
+            and exint configuration) registers to their default values.
+  * @param  none
+  * @retval none
+  */
+void gpio_iomux_reset(void)
+{
+  crm_periph_reset(CRM_IOMUX_PERIPH_RESET, TRUE);
+  crm_periph_reset(CRM_IOMUX_PERIPH_RESET, FALSE);
+}
+
+/**
+  * @brief  initialize the gpio peripheral.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @param  gpio_init_struct: pointer to gpio init structure.
+  * @retval none
+  */
+void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct)
+{
+  uint32_t temp;
+  uint16_t pinx_value, pin_index;
+
+  pin_index = (uint16_t)gpio_init_struct->gpio_pins;
+
+  /* pinx_value indecate pin grounp bit[3:0] from modey[1:0] confy[1:0] */
+
+  /* pin input analog config */
+  if(gpio_init_struct->gpio_mode == GPIO_MODE_ANALOG)
+  {
+    pinx_value = 0x00;
+  }
+  /* pin input config */
+  else if(gpio_init_struct->gpio_mode == GPIO_MODE_INPUT)
+  {
+    pinx_value = gpio_init_struct->gpio_pull & 0x0F;
+
+    if(gpio_init_struct->gpio_pull == GPIO_PULL_UP)
+    {
+      gpio_x->scr = pin_index;
+    }
+    else if(gpio_init_struct->gpio_pull == GPIO_PULL_DOWN)
+    {
+      gpio_x->clr = pin_index;
+    }
+  }
+  else
+  {
+    pinx_value = (gpio_init_struct->gpio_mode & 0x08) | (gpio_init_struct->gpio_out_type & 0x04) | \
+                 (gpio_init_struct->gpio_drive_strength & 0x03);
+  }
+
+  /* pin 0~7 config */
+  if(((uint32_t)pin_index & ((uint32_t)0x00FF)) != 0x00)
+  {
+    for(temp = 0; temp < 0x08; temp++)
+    {
+      if((1 << temp) & pin_index)
+      {
+        gpio_x->cfglr &= (uint32_t)~(0x0F << (temp * 4));
+        gpio_x->cfglr |= (uint32_t)(pinx_value << (temp * 4));
+      }
+    }
+  }
+
+  /* pin 8~15 config */
+  if(pin_index > 0x00ff)
+  {
+    pin_index = pin_index >> 8;
+
+    for(temp = 0; temp < 0x8; temp++)
+    {
+      if((1 << temp) & pin_index)
+      {
+        gpio_x->cfghr &= (uint32_t)~(0xf << (temp * 4));
+        gpio_x->cfghr |= (uint32_t)(pinx_value << (temp * 4));
+      }
+    }
+  }
+}
+
+/**
+  * @brief  fill each gpio_init_type member with its default value.
+  * @param  gpio_init_struct : pointer to a gpio_init_type structure which will be initialized.
+  * @retval none
+  */
+void gpio_default_para_init(gpio_init_type *gpio_init_struct)
+{
+  /* reset gpio init structure parameters values */
+  gpio_init_struct->gpio_pins  = GPIO_PINS_ALL;
+  gpio_init_struct->gpio_mode = GPIO_MODE_INPUT;
+  gpio_init_struct->gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
+  gpio_init_struct->gpio_pull = GPIO_PULL_NONE;
+  gpio_init_struct->gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
+}
+
+/**
+  * @brief  read the specified input port pin.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @param  pins: gpio pin number
+  *         this parameter can be one of the following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  * @retval flag_status (SET or RESET)
+  */
+flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins)
+{
+  flag_status status = RESET;
+
+  if(pins != (pins & gpio_x->idt))
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  read the specified gpio input data port.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @retval gpio input data port value.
+  */
+uint16_t gpio_input_data_read(gpio_type *gpio_x)
+{
+  return ((uint16_t)(gpio_x->idt));
+}
+
+/**
+  * @brief  read the specified output port pin.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @param  pins: gpio pin number
+  *         this parameter can be one of the following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  * @retval flag_status (SET or RESET)
+  */
+flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins)
+{
+  flag_status status = RESET;
+
+  if((gpio_x->odt & pins) != RESET)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  read the specified gpio ouput data port.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @retval gpio input data port value.
+  */
+uint16_t gpio_output_data_read(gpio_type *gpio_x)
+{
+  return ((uint16_t)(gpio_x->odt));
+}
+
+/**
+  * @brief  set the selected data port bits.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @param  pins: gpio pin number
+  *         parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  *         - GPIO_PINS_ALL
+  * @retval none
+  */
+void gpio_bits_set(gpio_type *gpio_x, uint16_t pins)
+{
+  gpio_x->scr = pins;
+}
+
+/**
+  * @brief  clear the selected data port bits.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @param  pins: gpio pin number
+  *         parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  *         - GPIO_PINS_ALL
+  * @retval none
+  */
+void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins)
+{
+  gpio_x->clr = pins;
+}
+
+/**
+  * @brief  set or clear the selected data port bit.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @param  pins: gpio pin number
+  *         parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  *         - GPIO_PINS_ALL
+  * @param  bit_state: specifies the value to be written to the selected bit (TRUE or FALSE).
+  * @retval none
+  */
+void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
+{
+  if(bit_state != FALSE)
+  {
+    gpio_x->scr = pins;
+  }
+  else
+  {
+    gpio_x->clr = pins;
+  }
+}
+
+/**
+  * @brief  write data to the specified gpio data port.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @param  port_value: specifies the value to be written to the port output data register.
+  * @retval none
+  */
+void gpio_port_write(gpio_type *gpio_x, uint16_t port_value)
+{
+  gpio_x->odt = port_value;
+}
+
+/**
+  * @brief  write protect gpio pins configuration registers.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
+  * @param  pins: gpio pin number
+  *         this parameter can be any combination of the following:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  *         - GPIO_PINS_ALL
+  * @retval none
+  */
+void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins)
+{
+  uint32_t temp = 0x00010000;
+
+  temp |= pins;
+  /* set wpen bit */
+  gpio_x->wpr = temp;
+  /* reset wpen bit */
+  gpio_x->wpr =  pins;
+  /* set wpen bit */
+  gpio_x->wpr = temp;
+  /* read wpen bit*/
+  temp = gpio_x->wpr;
+  /* read wpen bit*/
+  temp = gpio_x->wpr;
+}
+
+/**
+  * @brief  select the gpio pin used as event output.
+  * @param  gpio_port_source: select the gpio port to be used as source
+  *         for event output.
+  *         this parameter can be one of the following values:
+  *         - GPIO_PORT_SOURCE_GPIOA
+  *         - GPIO_PORT_SOURCE_GPIOB
+  *         - GPIO_PORT_SOURCE_GPIOC
+  *         - GPIO_PORT_SOURCE_GPIOD
+  *         - GPIO_PORT_SOURCE_GPIOF
+  * @param  gpio_pin_source: specifies the pin for the event output.
+  *         this parameter can be one of the following values:
+  *         - GPIO_PINS_SOURCE0
+  *         - GPIO_PINS_SOURCE1
+  *         - GPIO_PINS_SOURCE2
+  *         - GPIO_PINS_SOURCE3
+  *         - GPIO_PINS_SOURCE4
+  *         - GPIO_PINS_SOURCE5
+  *         - GPIO_PINS_SOURCE6
+  *         - GPIO_PINS_SOURCE7
+  *         - GPIO_PINS_SOURCE8
+  *         - GPIO_PINS_SOURCE9
+  *         - GPIO_PINS_SOURCE10
+  *         - GPIO_PINS_SOURCE11
+  *         - GPIO_PINS_SOURCE12
+  *         - GPIO_PINS_SOURCE13
+  *         - GPIO_PINS_SOURCE14
+  *         - GPIO_PINS_SOURCE15
+  * @retval none
+  */
+void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source)
+{
+  uint32_t tmpreg = 0x00;
+
+  tmpreg = IOMUX->evtout;
+
+  /* clear the port[6:4] and pin[3:0] bits */
+  tmpreg &= 0x80;
+  tmpreg |= (uint32_t)gpio_port_source << 0x04;
+  tmpreg |= gpio_pin_source;
+  IOMUX->evtout = tmpreg;
+}
+
+/**
+  * @brief  enable or disable the event output.
+  * @param  confirm_state: new state of the event output.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void gpio_event_output_enable(confirm_state new_state)
+{
+  IOMUX->evtout_bit.evoen = new_state;
+}
+
+/**
+  * @brief  iomux remap and debug i/o configuration.
+  * @param  gpio_remap: select the pin to remap.
+  *         this parameter can be one of the following values:
+  *         - SPI1_MUX_01                   - I2C1_MUX                      - USART1_MUX                   - USART3_MUX_01
+  *         - TMR1_MUX_01                   - TMR2_MUX_01                   - TMR2_MUX_10                  - TMR2_MUX_11
+  *         - TMR3_MUX_10                   - TMR3_MUX_11                   - CAN_MUX_10                   - PD01_MUX
+  *         - TMR5CH4_MUX                   - ADC1_EXTRGPRE_MUX             - ADC1_EXTRGORD_MUX            - ADC2_EXTRGPRE_MUX
+  *         - ADC2_EXTRGORD_MUX             - SWJTAG_CONF_001               - SWJTAG_CONF_010              - SWJTAG_CONF_100
+  *         - EXT_SPIM_EN_MUX               - TMR9_GMUX                     - TMR10_GMUX                   - TMR11_GMUX
+  *         - TMR1_GMUX_0001                - TMR2_GMUX_001                 - TMR2_GMUX_010                - TMR2_GMUX_011
+  *         - TMR2ITR1_GMUX                 - TMR3_GMUX_0010                - TMR3_GMUX_0011               - TMR5_GMUX_001
+  *         - TMR5CH4_GMUX                  - I2C1_GMUX_0001                - I2C1_GMUX_0011               - I2C2_GMUX_0001
+  *         - I2C2_GMUX_0010                - I2C2_GMUX_0011                - SPI1_GMUX_0001               - SPI2_GMUX_0001
+  *         - CAN1_GMUX_0010                - CAN2_GMUX_0001                - SDIO1_GMUX_0100              - SDIO1_GMUX_0101
+  *         - SDIO1_GMUX_0110               - SDIO1_GMUX_0111               - USART1_GMUX_0001             - USART3_GMUX_0001
+  *         - UART4_GMUX_0001               - EXT_SPIM_GMUX_1000            - EXT_SPIM_GMUX_1001           - ADC1_ETP_GMUX
+  *         - ADC1_ETO_GMUX                 - ADC2_ETP_GMUX                 - ADC2_ETO_GMUX                - SWJTAG_GMUX_001
+  *         - SWJTAG_GMUX_010               - SWJTAG_GMUX_100               - PD01_GMUX
+  * @param  new_state: (TRUE or FALSE)
+  * @retval none
+  */
+void gpio_pin_remap_config(uint32_t gpio_remap, confirm_state new_state)
+{
+  uint32_t reg_addr, remap_mask;
+  uint8_t bit_offset, bit_num, bit_val;
+
+  /* get register address, bit offset, bit number and remap value */
+  reg_addr = IOMUX_BASE + (gpio_remap >> 24);
+  bit_offset = (gpio_remap >> 16) & 0xFF;
+  bit_num = (gpio_remap >> 8) & 0xFF;
+  bit_val = gpio_remap & 0xFF;
+
+  /* get remap mask value */
+  remap_mask = 0xFFFFFFFF << (32 - bit_num - bit_offset);
+  remap_mask = remap_mask >> (32 - bit_num - bit_offset);
+  remap_mask = remap_mask >> bit_offset;
+  remap_mask = remap_mask << bit_offset;
+
+  /* clear remap value */
+  *(uint32_t*)reg_addr &= ~remap_mask;
+
+  if(new_state != FALSE)
+  {
+    /* set remap value */
+    *(uint32_t*)reg_addr |= (uint32_t)(bit_val << bit_offset);
+  }
+}
+
+/**
+  * @brief  select the gpio pin used as exint line.
+  * @param  gpio_port_source: select the gpio port to be used as source for exint.
+  *         this parameter can be one of the following values:
+  *         - GPIO_PORT_SOURCE_GPIOA
+  *         - GPIO_PORT_SOURCE_GPIOB
+  *         - GPIO_PORT_SOURCE_GPIOC
+  *         - GPIO_PORT_SOURCE_GPIOD
+  *         - GPIO_PORT_SOURCE_GPIOF
+  * @param  gpio_pin_source: specifies the pin for the event output.
+  *         this parameter can be one of the following values:
+  *         - GPIO_PINS_SOURCE0
+  *         - GPIO_PINS_SOURCE1
+  *         - GPIO_PINS_SOURCE2
+  *         - GPIO_PINS_SOURCE3
+  *         - GPIO_PINS_SOURCE4
+  *         - GPIO_PINS_SOURCE5
+  *         - GPIO_PINS_SOURCE6
+  *         - GPIO_PINS_SOURCE7
+  *         - GPIO_PINS_SOURCE8
+  *         - GPIO_PINS_SOURCE9
+  *         - GPIO_PINS_SOURCE10
+  *         - GPIO_PINS_SOURCE11
+  *         - GPIO_PINS_SOURCE12
+  *         - GPIO_PINS_SOURCE13
+  *         - GPIO_PINS_SOURCE14
+  *         - GPIO_PINS_SOURCE15
+  * @retval none
+  */
+void gpio_exint_line_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source)
+{
+  uint32_t tmp = 0x00;
+  tmp = ((uint32_t)0x0F) << (0x04 * (gpio_pin_source & (uint8_t)0x03));
+
+  switch (gpio_pin_source >> 0x02)
+  {
+    case 0:
+      IOMUX->exintc1 &= ~tmp;
+      IOMUX->exintc1 |= (((uint32_t)gpio_port_source) << (0x04 * (gpio_pin_source & (uint8_t)0x03)));
+      break;
+    case 1:
+      IOMUX->exintc2 &= ~tmp;
+      IOMUX->exintc2 |= (((uint32_t)gpio_port_source) << (0x04 * (gpio_pin_source & (uint8_t)0x03)));
+      break;
+    case 2:
+      IOMUX->exintc3 &= ~tmp;
+      IOMUX->exintc3 |= (((uint32_t)gpio_port_source) << (0x04 * (gpio_pin_source & (uint8_t)0x03)));
+      break;
+    case 3:
+      IOMUX->exintc4 &= ~tmp;
+      IOMUX->exintc4 |= (((uint32_t)gpio_port_source) << (0x04 * (gpio_pin_source & (uint8_t)0x03)));
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_i2c.c

@@ -0,0 +1,642 @@
+/**
+  **************************************************************************
+  * @file     at32f413_i2c.c
+  * @brief    contains all the functions for the i2c firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup I2C
+  * @brief I2C driver modules
+  * @{
+  */
+
+#ifdef I2C_MODULE_ENABLED
+
+/** @defgroup I2C_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the i2c register
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @retval none
+  */
+void i2c_reset(i2c_type *i2c_x)
+{
+  if(i2c_x == I2C1)
+  {
+    crm_periph_reset(CRM_I2C1_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_I2C1_PERIPH_RESET, FALSE);
+  }
+  else if(i2c_x == I2C2)
+  {
+    crm_periph_reset(CRM_I2C2_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_I2C2_PERIPH_RESET, FALSE);
+  }
+}
+
+/**
+  * @brief  software reset.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_software_reset(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.reset = new_state;
+}
+
+/**
+  * @brief  init i2c speed and duty cycle.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  duty
+  *         this parameter can be one of the following values:
+  *         - I2C_FSMODE_DUTY_2_1: duty cycle 2:1
+  *         - I2C_FSMODE_DUTY_16_9: duty cycle 16:9
+  * @param  speed: i2c scl clock speed, such as 100000
+  * @retval none
+  */
+void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed)
+{
+  uint32_t apb_freq = 0;
+  uint16_t freq_mhz = 0, temp = 0;
+
+  crm_clocks_freq_type clocks;
+
+  /* disable i2c peripherals */
+  i2c_x->ctrl1_bit.i2cen = FALSE;
+
+  /* get system clock */
+  crm_clocks_freq_get(&clocks);
+
+  if((i2c_x == I2C1) || (i2c_x == I2C2))
+  {
+    apb_freq = clocks.apb1_freq;
+  }
+
+  freq_mhz = (apb_freq / 1000000);
+
+  /* set i2c input clock frequency */
+  i2c_x->ctrl2_bit.clkfreq = freq_mhz;
+
+  /* standard mode */
+  if(speed <= 100000)
+  {
+    temp = (uint16_t)(apb_freq / (speed << 1));
+
+    if (temp < 0x04)
+    {
+      temp = 0x04;
+    }
+
+    /* set scl clock */
+    i2c_x->clkctrl_bit.speed = temp;
+
+    /* disable fast mode */
+    i2c_x->clkctrl_bit.speedmode = FALSE;
+
+    /* set the maximum rise time */
+    if((freq_mhz + 1) > 0x3F)
+    {
+      i2c_x->tmrise_bit.risetime = 0x3F;
+    }
+    else
+    {
+      i2c_x->tmrise_bit.risetime = (freq_mhz + 1);
+    }
+  }
+  /* fast mode */
+  else
+  {
+    if (duty == I2C_FSMODE_DUTY_2_1)
+    {
+      temp = (uint16_t)(apb_freq / (speed * 3));
+
+      /* the ratio of high level to low level is 1:2 */
+      i2c_x->clkctrl_bit.dutymode = I2C_FSMODE_DUTY_2_1;
+    }
+    else
+    {
+      temp = (uint16_t)(apb_freq / (speed * 25));
+
+      /* the ratio of high level to low level is 9:16 */
+      i2c_x->clkctrl_bit.dutymode = I2C_FSMODE_DUTY_16_9;
+    }
+
+    if (temp == 0)
+    {
+      temp = 0x0001;
+    }
+
+    /* set scl clock*/
+    i2c_x->clkctrl_bit.speed = temp;
+
+    /* set the mode to fast mode */
+    i2c_x->clkctrl_bit.speedmode = TRUE;
+
+    /* set the maximum rise time */
+    i2c_x->tmrise_bit.risetime = (uint16_t)(((freq_mhz * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+  }
+}
+
+/**
+  * @brief  config own address1.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  mode
+  *         this parameter can be one of the following values:
+  *         - I2C_ADDRESS_MODE_7BIT: 7bit address.
+  *         - I2C_ADDRESS_MODE_10BIT: 10bit address.
+  * @param  address: own address1, such as 0xb0.
+  * @retval none
+  */
+void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address)
+{
+  /* set address mode */
+  i2c_x->oaddr1_bit.addr1mode = mode;
+
+  /* set own address1 */
+  i2c_x->oaddr1_bit.addr1 = address;
+}
+
+/**
+  * @brief  config own address2.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  address: specifies the 7bit i2c own address2, such as 0xa0.
+  * @retval none.
+  */
+void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address)
+{
+  i2c_x->oaddr2_bit.addr2 = (address >> 1);
+}
+
+/**
+  * @brief  enable or disable own address2.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->oaddr2_bit.addr2en = new_state;
+}
+
+/**
+  * @brief  enable or disable the smbus mode
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_smbus_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.permode = new_state;
+}
+
+/**
+  * @brief  enable or disable i2c periph
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.i2cen = new_state;
+}
+
+/**
+  * @brief  config fast mode duty cycle
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  duty
+  *         this parameter can be one of the following values:
+  *         - I2C_FSMODE_DUTY_2_1: duty cycle 2:1
+  *         - I2C_FSMODE_DUTY_16_9: duty cycle 16:9
+  * @retval none
+  */
+void i2c_fast_mode_duty_set(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty)
+{
+  i2c_x->clkctrl_bit.dutymode = duty;
+}
+
+/**
+  * @brief  enable or disable clock stretch.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.stretch = !new_state;
+}
+
+/**
+  * @brief  enable or disable acknowledge.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none.
+  */
+void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.acken = new_state;
+}
+
+/**
+  * @brief  master receiving mode acknowledge control.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  pos
+  *         this parameter can be one of the following values:
+  *         - I2C_MASTER_ACK_CURRENT: acken bit acts on the current byte
+  *         - I2C_MASTER_ACK_NEXT: acken bit acts on the next byte
+  * @retval none
+  */
+void i2c_master_receive_ack_set(i2c_type *i2c_x, i2c_master_ack_type pos)
+{
+  i2c_x->ctrl1_bit.mackctrl = pos;
+}
+
+/**
+  * @brief  pec position set.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  pos
+  *         this parameter can be one of the following values:
+  *         - I2C_PEC_POSITION_CURRENT: the current byte is pec
+  *         - I2C_PEC_POSITION_NEXT: the next byte is pec
+  * @retval none
+  */
+void i2c_pec_position_set(i2c_type *i2c_x, i2c_pec_position_type pos)
+{
+  i2c_x->ctrl1_bit.mackctrl = pos;
+}
+
+/**
+  * @brief  enable or disable general call.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.gcaen = new_state;
+}
+
+/**
+  * @brief  enable or disable arp mode.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_arp_mode_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.arpen = new_state;
+}
+
+/**
+  * @brief  config smbus host or device.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  level
+  *         this parameter can be one of the following values:
+  *         - I2C_SMBUS_MODE_DEVICE: smbus device.
+  *         - I2C_SMBUS_MODE_HOST: smbus host.
+  * @retval none
+  */
+void i2c_smbus_mode_set(i2c_type *i2c_x, i2c_smbus_mode_set_type mode)
+{
+  i2c_x->ctrl1_bit.smbmode = mode;
+}
+
+/**
+  * @brief  drive the smbus alert pin high or low.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  level
+  *         this parameter can be one of the following values:
+  *         - I2C_SMBUS_ALERT_LOW: smbus alert pin set low.
+  *         - I2C_SMBUS_ALERT_HIGH: smbus alert pin set high.
+  * @retval none
+  */
+void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level)
+{
+  i2c_x->ctrl1_bit.smbalert = level;
+}
+
+/**
+  * @brief  enable or disable pec transfer.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.pecten = new_state;
+}
+
+/**
+  * @brief  enable or disable pec calcultetion.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.pecen = new_state;
+}
+
+/**
+  * @brief  get pec value.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @retval uint8_t: pec value.
+  */
+uint8_t i2c_pec_value_get(i2c_type *i2c_x)
+{
+  return i2c_x->sts2_bit.pecval;
+}
+
+/**
+  * @brief  enable or disable if the next dma transfer will be the last one.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_dma_end_transfer_set(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl2_bit.dmaend = new_state;
+}
+
+/**
+  * @brief  enable or disable dma requests.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_dma_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl2_bit.dmaen = new_state;
+}
+
+/**
+  * @brief  enable or disable interrupt
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  source
+  *         this parameter can be one of the following values:
+  *         - I2C_DATA_INT: data interrupt.
+  *         - I2C_EV_INT: event interrupt.
+  *         - I2C_ERR_INT: error interrupt.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void i2c_interrupt_enable(i2c_type *i2c_x, uint16_t source, confirm_state new_state)
+{
+  if (new_state != FALSE)
+  {
+    i2c_x->ctrl2 |= source;
+  }
+  else
+  {
+    i2c_x->ctrl2 &= (uint16_t)~source;
+  }
+}
+
+/**
+  * @brief  generate start condition.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @retval none.
+  */
+void i2c_start_generate(i2c_type *i2c_x)
+{
+  i2c_x->ctrl1_bit.genstart = TRUE;
+}
+
+/**
+  * @brief  generate stop condition.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @retval none.
+  */
+void i2c_stop_generate(i2c_type *i2c_x)
+{
+  i2c_x->ctrl1_bit.genstop = TRUE;
+}
+
+/**
+  * @brief  transmit the slave address.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  address: specifies the slave address which will be transmitted
+  * @param  direction
+  *         this parameter can be one of the following values:
+  *         - I2C_DIRECTION_TRANSMIT: transmit mode.
+  *         - I2C_DIRECTION_RECEIVE: receive mode.
+  * @retval none.
+  */
+void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type direction)
+{
+  if(direction == I2C_DIRECTION_TRANSMIT)
+  {
+    i2c_x->dt = address & 0xFE;
+  }
+  else
+  {
+    i2c_x->dt = address | 0x01;
+  }
+}
+
+/**
+  * @brief  send a byte through the i2c periph.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  data: byte to be transmitted.
+  * @retval none
+  */
+void i2c_data_send(i2c_type *i2c_x, uint8_t data)
+{
+  i2c_x->dt = data;
+}
+
+/**
+  * @brief  receive a byte through the i2c periph.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @retval uint8_t: received byte
+  */
+uint8_t i2c_data_receive(i2c_type *i2c_x)
+{
+  return (uint8_t)i2c_x->dt;
+}
+
+/**
+  * @brief  get flag status
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2.
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         - I2C_STARTF_FLAG: start condition generation complete flag.
+  *         - I2C_ADDR7F_FLAG: 0~7 bit address match flag.
+  *         - I2C_TDC_FLAG: transmit data complete flag.
+  *         - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag.
+  *         - I2C_STOPF_FLAG: stop condition generation complete flag.
+  *         - I2C_RDBF_FLAG: receive data buffer full flag.
+  *         - I2C_TDBE_FLAG: transmit data buffer empty flag.
+  *         - I2C_BUSERR_FLAG: bus error flag.
+  *         - I2C_ARLOST_FLAG: arbitration lost flag.
+  *         - I2C_ACKFAIL_FLAG: acknowledge failure flag.
+  *         - I2C_OUF_FLAG: overflow or underflow flag.
+  *         - I2C_PECERR_FLAG: pec receive error flag.
+  *         - I2C_TMOUT_FLAG: smbus timeout flag.
+  *         - I2C_ALERTF_FLAG: smbus alert flag.
+  *         - I2C_TRMODE_FLAG: transmission mode.
+  *         - I2C_BUSYF_FLAG: bus busy flag transmission mode.
+  *         - I2C_DIRF_FLAG: transmission direction flag.
+  *         - I2C_GCADDRF_FLAG: general call address received flag.
+  *         - I2C_DEVADDRF_FLAG: smbus device address received flag.
+  *         - I2C_HOSTADDRF_FLAG: smbus host address received flag.
+  *         - I2C_ADDR2_FLAG: own address 2 received flag.
+  * @retval flag_status (SET or RESET)
+  */
+flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
+{
+  __IO uint32_t reg = 0, value = 0;
+
+  reg = flag >> 28;
+
+  flag &= (uint32_t)0x00FFFFFF;
+
+  if(reg == 0)
+  {
+    value = i2c_x->sts1;
+  }
+  else
+  {
+    flag = (uint32_t)(flag >> 16);
+
+    value = i2c_x->sts2;
+  }
+
+  if((value & flag) != (uint32_t)RESET)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  clear flag status
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  flag
+  *         this parameter can be any combination of the following values:
+  *         - I2C_BUSERR_FLAG: bus error flag.
+  *         - I2C_ARLOST_FLAG: arbitration lost flag.
+  *         - I2C_ACKFAIL_FLAG: acknowledge failure flag.
+  *         - I2C_OUF_FLAG: overflow or underflow flag.
+  *         - I2C_PECERR_FLAG: pec receive error flag.
+  *         - I2C_TMOUT_FLAG: smbus timeout flag.
+  *         - I2C_ALERTF_FLAG: smbus alert flag.
+  *         - I2C_STOPF_FLAG: stop condition generation complete flag.
+  *         - I2C_ADDR7F_FLAG: i2c 0~7 bit address match flag.
+  * @retval none
+  */
+void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
+{  
+  i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00);
+  
+  if(i2c_x->sts1 & I2C_ADDR7F_FLAG)
+  {
+    UNUSED(i2c_x->sts2);
+  }
+  
+  if(i2c_x->sts1 & I2C_STOPF_FLAG)
+  {
+    i2c_x->ctrl1_bit.i2cen = TRUE;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_misc.c

@@ -0,0 +1,171 @@
+/**
+  **************************************************************************
+  * @file     at32f413_misc.c
+  * @brief    contains all the functions for the misc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup MISC
+  * @brief MISC driver modules
+  * @{
+  */
+
+#ifdef MISC_MODULE_ENABLED
+
+/** @defgroup MISC_private_functions
+  * @{
+  */
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+
+/**
+  * @brief  system reset
+  * @param  none
+  * @retval none
+  */
+void nvic_system_reset(void)
+{
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  enable nvic irq
+  * @param  irqn (IRQn_Type number)
+  * @param  preempt_priority: preemptive priority value (starting from 0)
+  * @param  sub_priority: subpriority value (starting from 0)
+  * @retval none
+  */
+void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority)
+{
+  uint32_t temp_priority = 0;
+
+  /* encode priority */
+  temp_priority = NVIC_EncodePriority(NVIC_GetPriorityGrouping(), preempt_priority, sub_priority);
+  /* set priority */
+  NVIC_SetPriority(irqn, temp_priority);
+  /* enable irqn */
+  NVIC_EnableIRQ(irqn);
+}
+
+/**
+  * @brief  disable nvic irq number
+  * @param  irqn (IRQn_Type number)
+  * @retval none
+  */
+void nvic_irq_disable(IRQn_Type irqn)
+{
+  NVIC_DisableIRQ(irqn);
+}
+
+/**
+  * @brief  config nvic priority group
+  * @param  priority_group
+  *         this parameter can be one of the following values:
+  *         - NVIC_PRIORITY_GROUP_0
+  *         - NVIC_PRIORITY_GROUP_1
+  *         - NVIC_PRIORITY_GROUP_2
+  *         - NVIC_PRIORITY_GROUP_3
+  *         - NVIC_PRIORITY_GROUP_4
+  * @retval none
+  */
+void nvic_priority_group_config(nvic_priority_group_type priority_group)
+{
+  /* set the prigroup[10:8] bits according to nvic_prioritygroup value */
+  NVIC_SetPriorityGrouping(priority_group);
+}
+
+/**
+  * @brief  set the vector table location and offset.
+  * @param  base
+  *         this parameter can be one of the following values:
+  *         - NVIC_VECTTAB_RAM
+  *         - NVIC_VECTTAB_FLASH
+  * @param  offset (vector table base offset field. this value must be a multiple of 0x200)
+  * @retval none
+  */
+void nvic_vector_table_set(uint32_t base, uint32_t offset)
+{
+  SCB->VTOR = base | (offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  config nvic lowpower mode
+  * @param  lp_mode
+  *         this parameter can be one of the following values:
+  *         - NVIC_LP_SEVONPEND
+  *         - NVIC_LP_SLEEPDEEP
+  *         - NVIC_LP_SLEEPONEXIT
+  * @param  new_state (new state of lp condition. ENABLE or DISABLE)
+  * @retval none
+  */
+void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    SCB->SCR |= lp_mode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)lp_mode);
+  }
+}
+
+/**
+  * @brief  config systick clock source
+  * @param  source
+  *         this parameter can be one of the following values:
+  *         - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
+  *         - SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV
+  * @retval none
+  */
+void systick_clock_source_config(systick_clock_source_type source)
+{
+  if(source == SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV)
+  {
+    SysTick->CTRL |= SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
+  }
+  else
+  {
+    SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

Librarys/AT32F41x_Drivers/src/at32f413_pwc.c

@@ -0,0 +1,234 @@
+/**
+  **************************************************************************
+  * @file     at32f413_pwc.c
+  * @brief    contains all the functions for the pwc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup PWC
+  * @brief PWC driver modules
+  * @{
+  */
+
+#ifdef PWC_MODULE_ENABLED
+
+/** @defgroup PWC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  deinitialize the pwc peripheral registers to their default reset values.
+  * @param  none
+  * @retval none
+  */
+void pwc_reset(void)
+{
+  crm_periph_reset(CRM_PWC_PERIPH_RESET, TRUE);
+  crm_periph_reset(CRM_PWC_PERIPH_RESET, FALSE);
+}
+
+/**
+  * @brief  enable or disable access to the battery powered domain.
+  * @param  new_state: new state of battery powered domain access.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void pwc_battery_powered_domain_access(confirm_state new_state)
+{
+  PWC->ctrl_bit.bpwen = new_state;
+}
+
+/**
+  * @brief  select the voltage threshold detected by the power voltage detector.
+  * @param  pvm_voltage: select pwc pvm voltage
+  *         this parameter can be one of the following values:
+  *         - PWC_PVM_VOLTAGE_2V3
+  *         - PWC_PVM_VOLTAGE_2V4
+  *         - PWC_PVM_VOLTAGE_2V5
+  *         - PWC_PVM_VOLTAGE_2V6
+  *         - PWC_PVM_VOLTAGE_2V7
+  *         - PWC_PVM_VOLTAGE_2V8
+  *         - PWC_PVM_VOLTAGE_2V9
+  * @retval none
+  */
+void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage)
+{
+  PWC->ctrl_bit.pvmsel = pvm_voltage;
+}
+
+/**
+  * @brief  enable or disable pwc power voltage monitor (pvm)
+  * @param  new_state: new state of pvm.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void pwc_power_voltage_monitor_enable(confirm_state new_state)
+{
+  PWC->ctrl_bit.pvmen = new_state;
+}
+
+/**
+  * @brief  enable or disable pwc standby wakeup pin
+  * @param  pin_num: choose the wakeup pin.
+  *         this parameter can be be any combination of the following values:
+  *         - PWC_WAKEUP_PIN_1
+  * @param  new_state: new state of the standby wakeup pin.
+  *         this parameter can be one of the following values:
+  *         - TRUE <wakeup pin is used for wake up cpu from standby mode>
+  *         - FALSE <wakeup pin is used for general purpose I/O>
+  * @retval none
+  */
+void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    PWC->ctrlsts |= pin_num;
+  }
+  else
+  {
+    PWC->ctrlsts &= ~pin_num;
+  }
+}
+
+/**
+  * @brief  clear flag of pwc
+  * @param  pwc_flag: select the pwc flag.
+  *         this parameter can be any combination of the following values:
+  *         - PWC_WAKEUP_FLAG
+  *         - PWC_STANDBY_FLAG
+  *         - note:"PWC_PVM_OUTPUT_FLAG" cannot be choose!this bit is readonly bit,it means the voltage monitoring output state
+  * @retval none
+  */
+void pwc_flag_clear(uint32_t pwc_flag)
+{
+  if(pwc_flag & PWC_STANDBY_FLAG)
+    PWC->ctrl_bit.clsef = TRUE;
+  if(pwc_flag & PWC_WAKEUP_FLAG)
+    PWC->ctrl_bit.clswef = TRUE;
+}
+
+/**
+  * @brief  get flag of pwc
+  * @param  pwc_flag: select the pwc flag.
+  *         this parameter can be one of the following values:
+  *         - PWC_WAKEUP_FLAG
+  *         - PWC_STANDBY_FLAG
+  *         - PWC_PVM_OUTPUT_FLAG
+  * @retval state of select flag(SET or RESET).
+  */
+flag_status pwc_flag_get(uint32_t pwc_flag)
+{
+  flag_status status = RESET;
+  if ((PWC->ctrlsts & pwc_flag) == RESET)
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+  return status;
+}
+
+/**
+  * @brief  enter pwc sleep mode
+  * @param  sleep_mode_enter: choose the instruction to enter sleep mode.
+  *         this parameter can be one of the following values:
+  *         - PWC_SLEEP_ENTER_WFI
+  *         - PWC_SLEEP_ENTER_WFE
+  * @retval none
+  */
+void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter)
+{
+  SCB->SCR &= (uint32_t)~0x4;
+  if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFE)
+  {
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+  else if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFI)
+  {
+    __WFI();
+  }
+}
+
+/**
+  * @brief  enter pwc deep-sleep mode
+  * @param  pwc_deep_sleep_enter: choose the instruction to enter deep sleep mode.
+  *         this parameter can be one of the following values:
+  *         - PWC_DEEP_SLEEP_ENTER_WFI
+  *         - PWC_DEEP_SLEEP_ENTER_WFE
+  * @retval none
+  */
+void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
+{
+  SCB->SCR |= 0x04;
+  if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFE)
+  {
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+  else if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFI)
+  {
+    __WFI();
+  }
+  SCB->SCR &= (uint32_t)~0x4;
+}
+
+/**
+  * @brief  enter pwc standby mode
+  * @param  none
+  * @retval none
+  */
+void pwc_standby_mode_enter(void)
+{
+  PWC->ctrl_bit.clswef = TRUE;
+  PWC->ctrl_bit.lpsel = TRUE;
+  SCB->SCR |= 0x04;
+#if defined (__CC_ARM)
+  __force_stores();
+#endif
+  while(1)
+  {
+    __WFI();
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_rtc.c

@@ -0,0 +1,222 @@
+/**
+  **************************************************************************
+  * @file     at32f413_rtc.c
+  * @brief    contains all the functions for the rtc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup RTC
+  * @brief RTC driver modules
+  * @{
+  */
+
+#ifdef RTC_MODULE_ENABLED
+
+/** @defgroup RTC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  rtc counter set
+  * @param  counter_value (0x0000_0000 ~ 0xFFFF_FFFF)
+  * @retval none
+  */
+void rtc_counter_set(uint32_t counter_value)
+{
+  /* enter rtc config mode */
+  RTC->ctrll = 0x003F;
+
+  /* set rtc counter */
+  RTC->cnth_bit.cnt = (uint16_t)(counter_value >> 16);
+  RTC->cntl_bit.cnt = (uint16_t)(counter_value & 0x0000FFFF);
+
+  /* exit rtc config mode */
+  RTC->ctrll = 0x000F;
+}
+
+/**
+  * @brief  rtc counter get
+  * @param  none
+  * @retval rtc counter
+  */
+uint32_t rtc_counter_get(void)
+{
+  uint32_t cnt = 0;
+
+  cnt = RTC->cnth;
+  cnt = (cnt << 16) | RTC->cntl;
+
+  return cnt;
+}
+
+/**
+  * @brief  rtc divider set
+  * @param  div_value (0x0000_0000 ~ 0x000F_FFFF)
+  * @retval none
+  */
+void rtc_divider_set(uint32_t div_value)
+{
+  /* enter rtc config mode */
+  RTC->ctrll = 0x003F;
+
+  /* set rtc divider */
+  RTC->divh_bit.div = (uint16_t)(div_value >> 16);
+  RTC->divl_bit.div = (uint16_t)(div_value & 0x0000FFFF);
+
+  /* exit rtc config mode */
+  RTC->ctrll = 0x000F;
+}
+
+/**
+  * @brief  rtc divider get
+  * @param  none
+  * @retval rtc counter
+  */
+uint32_t rtc_divider_get(void)
+{
+  uint32_t div = 0;
+
+  div = RTC->divcnth;
+  div = (div << 16) | RTC->divcntl;
+
+  return div;
+}
+
+/**
+  * @brief  rtc alarm value set
+  * @param  alarm_value (0x0000_0000 ~ 0xFFFF_FFFF)
+  * @retval none
+  */
+void rtc_alarm_set(uint32_t alarm_value)
+{
+  /* enter rtc config mode */
+  RTC->ctrll = 0x003F;
+
+  /* set rtc alarm value */
+  RTC->tah_bit.ta = (uint16_t)(alarm_value >> 16);
+  RTC->tal_bit.ta = (uint16_t)(alarm_value & 0x0000FFFF);
+
+  /* exit rtc config mode */
+  RTC->ctrll = 0x000F;
+}
+
+/**
+  * @brief  rtc interrupt enable
+  * @param  source
+  *         this parameter can be any combination of the following values:
+  *         - RTC_TS_INT: time second interrupt.
+  *         - RTC_TA_INT: time alarm interrupt.
+  *         - RTC_OVF_INT: overflow interrupt.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void rtc_interrupt_enable(uint16_t source, confirm_state new_state)
+{
+  if(new_state == FALSE)
+  {
+    RTC->ctrlh &= ~source;
+  }
+  else
+  {
+    RTC->ctrlh |= source;
+  }
+}
+
+/**
+  * @brief  rtc flag get
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         - RTC_TS_FLAG: time second flag.
+  *         - RTC_TA_FLAG: time alarm flag.
+  *         - RTC_OVF_FLAG: overflow flag.
+  *         - RTC_UPDF_FLAG: rtc update finish flag.
+  *         - RTC_CFGF_FLAG: rtc configuration finish flag.
+  * @retval state of rtc flag
+  */
+flag_status rtc_flag_get(uint16_t flag)
+{
+  flag_status status = RESET;
+
+  if ((RTC->ctrll & flag) != (uint16_t)RESET)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  rtc flag clear
+  * @param  interrupt_flag
+  *         this parameter can be any combination of the following values:
+  *         - RTC_TS_FLAG: time second flag.
+  *         - RTC_TA_FLAG: time alarm flag.
+  *         - RTC_OVF_FLAG: overflow flag.
+  *         - RTC_UPDF_FLAG: rtc update finish flag.
+  * @retval none
+  */
+void rtc_flag_clear(uint16_t flag)
+{
+  RTC->ctrll = ~(flag | 0x10) | (RTC->ctrll_bit.cfgen << 4);
+}
+
+/**
+  * @brief  rtc wait configuration finish
+  * @param  none
+  * @retval none
+  */
+void rtc_wait_config_finish(void)
+{
+  while (RTC->ctrll_bit.cfgf == 0);
+}
+
+/**
+  * @brief  rtc wait update finish
+  * @param  none
+  * @retval none
+  */
+void rtc_wait_update_finish(void)
+{
+  while (RTC->ctrll_bit.updf == 0);
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_sdio.c

@@ -0,0 +1,573 @@
+/**
+  **************************************************************************
+  * @file     at32f413_sdio.c
+  * @brief    contains all the functions for the sdio firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup SDIO
+  * @brief SDIO driver modules
+  * @{
+  */
+
+#ifdef SDIO_MODULE_ENABLED
+
+/** @defgroup SDIO_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the sdio register
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @retval none
+  */
+void sdio_reset(sdio_type *sdio_x)
+{
+  sdio_x->pwrctrl = 0x0;
+  sdio_x->clkctrl = 0x0;
+  sdio_x->argu = 0x0;
+  sdio_x->cmdctrl = 0x0;
+  sdio_x->dttmr = 0x0;
+  sdio_x->dtlen = 0x0;
+  sdio_x->dtctrl = 0x0;
+  sdio_x->inten = 0x0;
+  sdio_x->intclr = 0x004007FF;
+}
+
+/**
+  * @brief  set the power status of the controller
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  power_state
+  *         this parameter can be one of the following values:
+  *         - SDIO_POWER_OFF
+  *         - SDIO_POWER_ON
+  * @retval none
+  */
+void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state)
+{
+  sdio_x->pwrctrl_bit.ps = power_state;
+}
+
+/**
+  * @brief  get power status.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF)
+  */
+sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x)
+{
+  return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps);
+}
+
+/**
+  * @brief  config sdio clock
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  clk_div: sdio clock divide factor(frequency = sdio_clk / [clk_psc + 2]).
+  * @param  clk_edg
+  *         this parameter can be one of the following values:
+  *         - SDIO_CLOCK_EDGE_RISING
+  *         - SDIO_CLOCK_EDGE_FALLING
+  * @retval none
+  */
+void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg)
+{
+  /* config clock edge */
+  sdio_x->clkctrl_bit.clkegs = clk_edg;
+
+  /* config clock divide [7:0] */
+  sdio_x->clkctrl_bit.clkdiv_l = (clk_div & 0xFF);
+
+  /* config clock divide [9:8] */
+  sdio_x->clkctrl_bit.clkdiv_h = ((clk_div & 0x300) >> 8);
+}
+
+/**
+  * @brief  config sdio bus width
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  width
+  *         this parameter can be one of the following values:
+  *         - SDIO_BUS_WIDTH_D1
+  *         - SDIO_BUS_WIDTH_D4
+  *         - SDIO_BUS_WIDTH_D8
+  * @retval none
+  */
+void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width)
+{
+  sdio_x->clkctrl_bit.busws = width;
+}
+
+/**
+  * @brief  enable or disable clock divider bypss
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->clkctrl_bit.bypsen = new_state;
+}
+
+/**
+  * @brief  enable or disable power saving mode, config sdio_ck clock output
+  *         when the bus is idle.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->clkctrl_bit.pwrsven = new_state;
+}
+
+/**
+  * @brief  enable or disable hardware flow control.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->clkctrl_bit.hfcen = new_state;
+}
+
+/**
+  * @brief  enable or disable sdio_ck output.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->clkctrl_bit.clkoen = new_state;
+}
+
+/**
+  * @brief  enable or disable dma.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.dmaen = new_state;
+}
+
+/**
+  * @brief  config corresponding interrupt.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  int_opt
+  *         this parameter can be one of the following values:
+  *         - SDIO_CMDFAIL_INT
+  *         - SDIO_DTFAIL_INT
+  *         - SDIO_CMDTIMEOUT_INT
+  *         - SDIO_DTTIMEOUT_INT
+  *         - SDIO_TXERRU_INT
+  *         - SDIO_RXERRO_INT
+  *         - SDIO_CMDRSPCMPL_INT
+  *         - SDIO_CMDCMPL_INT
+  *         - SDIO_DTCMP_INT
+  *         - SDIO_SBITERR_INT
+  *         - SDIO_DTBLKCMPL_INT
+  *         - SDIO_DOCMD_INT
+  *         - SDIO_DOTX_INT
+  *         - SDIO_DORX_INT
+  *         - SDIO_TXBUFH_INT
+  *         - SDIO_RXBUFH_INT
+  *         - SDIO_TXBUFF_INT
+  *         - SDIO_RXBUFF_INT
+  *         - SDIO_TXBUFE_INT
+  *         - SDIO_RXBUFE_INT
+  *         - SDIO_TXBUF_INT
+  *         - SDIO_RXBUF_INT
+  *         - SDIO_SDIOIF_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt,  confirm_state new_state)
+{
+  /* enable interrupt */
+  if(TRUE == new_state)
+  {
+    sdio_x->inten |= int_opt;
+  }
+  /* disable interrupt */
+  else
+  {
+    sdio_x->inten &= ~(int_opt);
+  }
+}
+
+/**
+  * @brief  get sdio flag.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         - SDIO_CMDFAIL_FLAG
+  *         - SDIO_DTFAIL_FLAG
+  *         - SDIO_CMDTIMEOUT_FLAG
+  *         - SDIO_DTTIMEOUT_FLAG
+  *         - SDIO_TXERRU_FLAG
+  *         - SDIO_RXERRO_FLAG
+  *         - SDIO_CMDRSPCMPL_FLAG
+  *         - SDIO_CMDCMPL_FLAG
+  *         - SDIO_DTCMPL_FLAG
+  *         - SDIO_SBITERR_FLAG
+  *         - SDIO_DTBLKCMPL_FLAG
+  *         - SDIO_DOCMD_FLAG
+  *         - SDIO_DOTX_FLAG
+  *         - SDIO_DORX_FLAG
+  *         - SDIO_TXBUFH_FLAG
+  *         - SDIO_RXBUFH_FLAG
+  *         - SDIO_TXBUFF_FLAG
+  *         - SDIO_RXBUFF_FLAG
+  *         - SDIO_TXBUFE_FLAG
+  *         - SDIO_RXBUFE_FLAG
+  *         - SDIO_TXBUF_FLAG
+  *         - SDIO_RXBUF_FLAG
+  *         - SDIO_SDIOIF_FLAG
+  * @retval flag_status (SET or RESET)
+  */
+flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag)
+{
+  flag_status status = RESET;
+
+  if((sdio_x->sts & flag) == flag)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  clear sdio flag.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  int_opt
+  *         this parameter can be any combination of the following values:
+  *         - SDIO_CMDFAIL_FLAG
+  *         - SDIO_DTFAIL_FLAG
+  *         - SDIO_CMDTIMEOUT_FLAG
+  *         - SDIO_DTTIMEOUT_FLAG
+  *         - SDIO_TXERRU_FLAG
+  *         - SDIO_RXERRO_FLAG
+  *         - SDIO_CMDRSPCMPL_FLAG
+  *         - SDIO_CMDCMPL_FLAG
+  *         - SDIO_DTCMPL_FLAG
+  *         - SDIO_SBITERR_FLAG
+  *         - SDIO_DTBLKCMPL_FLAG
+  *         - SDIO_SDIOIF_FLAG
+  * @retval none
+  */
+void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag)
+{
+  sdio_x->intclr = flag;
+}
+
+/**
+  * @brief  config sdio command.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  command_struct : pointer to a sdio_command_struct_type structure
+  *         that contains the configuration information for the sdio command.
+  * @retval none
+  */
+void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct)
+{
+  /* disable command path state machine */
+  sdio_x->cmdctrl_bit.ccsmen = FALSE;
+
+  /* config command argument */
+  sdio_x->argu = command_struct->argument;
+
+  /* config command register */
+  sdio_x->cmdctrl_bit.cmdidx = command_struct->cmd_index;
+  sdio_x->cmdctrl_bit.rspwt = command_struct->rsp_type;
+  sdio_x->cmdctrl_bit.intwt = (command_struct->wait_type & 0x1); /* [1:0] -> [0] */
+  sdio_x->cmdctrl_bit.pndwt = (command_struct->wait_type & 0x2)>>1; /* [1:0] -> [1] */
+}
+
+/**
+  * @brief  enable or disable command path state machine(CPSM).
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->cmdctrl_bit.ccsmen = new_state;
+}
+
+/**
+  * @brief  get command index of last command for which response received.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval uint8_t: command index
+  */
+uint8_t sdio_command_response_get(sdio_type *sdio_x)
+{
+  return sdio_x->rspcmd_bit.rspcmd;
+}
+
+/**
+  * @brief  get response received from the card for the last command.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  reg_index
+  *         this parameter can be one of the following values:
+  *         - SDIO_RSP1_INDEX
+  *         - SDIO_RSP2_INDEX
+  *         - SDIO_RSP3_INDEX
+  *         - SDIO_RSP4_INDEX
+  * @retval uint32_t: response register value
+  */
+uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index)
+{
+  uint32_t response_value = 0;
+
+  switch(reg_index)
+  {
+    case SDIO_RSP1_INDEX:
+      response_value = sdio_x->rsp1;
+      break;
+    case SDIO_RSP2_INDEX:
+      response_value = sdio_x->rsp2;
+      break;
+    case SDIO_RSP3_INDEX:
+      response_value = sdio_x->rsp3;
+      break;
+    case SDIO_RSP4_INDEX:
+      response_value = sdio_x->rsp4;
+      break;
+    default: break;
+  }
+
+  return response_value;
+}
+
+/**
+  * @brief  config sdio data.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  data_struct : pointer to a sdio_data_struct_type structure
+  *         that contains the configuration information for the sdio data.
+  * @retval none
+  */
+void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct)
+{
+  /* disable data path state machine */
+  sdio_x->dtctrl_bit.tfren = FALSE;
+
+  /* config data block, transfer mode and transfer direction */
+  sdio_x->dtctrl_bit.blksize = data_struct->block_size;
+  sdio_x->dtctrl_bit.tfrdir = data_struct->transfer_direction;
+  sdio_x->dtctrl_bit.tfrmode = data_struct->transfer_mode;
+
+  /* config data length */
+  sdio_x->dtlen_bit.dtlen = data_struct->data_length;
+
+  /* config data transfer timeout */
+  sdio_x->dttmr_bit.timeout = data_struct->timeout;
+}
+
+/**
+  * @brief  enable or disable data path state machine(DPSM).
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.tfren = new_state;
+}
+
+/**
+  * @brief  get the number of remaining data bytes to be transferred.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @retval uint32_t: number of bytes
+  */
+uint32_t sdio_data_counter_get(sdio_type *sdio_x)
+{
+  return sdio_x->dtcnt;
+}
+
+/**
+  * @brief  read a word data from sdio fifo.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @retval uint32_t: data received
+  */
+uint32_t sdio_data_read(sdio_type *sdio_x)
+{
+  return sdio_x->buf;
+}
+
+/**
+  * @brief  get the number of words left to be written to or read from fifo..
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @retval uint32_t: number of words
+  */
+uint32_t sdio_buffer_counter_get(sdio_type *sdio_x)
+{
+  return sdio_x->bufcnt;
+}
+
+/**
+  * @brief  write one word data to fifo.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  data: data to be transferred.
+  * @retval none
+  */
+void sdio_data_write(sdio_type *sdio_x, uint32_t data)
+{
+  sdio_x->buf = data;
+}
+
+/**
+  * @brief  set the read wait mode.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  mode
+  *         this parameter can be one of the following values:
+  *         - SDIO_READ_WAIT_CONTROLLED_BY_D2
+  *         - SDIO_READ_WAIT_CONTROLLED_BY_CK
+  * @retval none
+  */
+void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode)
+{
+  sdio_x->dtctrl_bit.rdwtmode = mode;
+}
+
+/**
+  * @brief  enable or disable to start sd i/o read wait operation.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.rdwtstart = new_state;
+}
+
+/**
+  * @brief  enable or disable to stop sd i/o read wait operation.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.rdwtstop = new_state;
+}
+
+/**
+  * @brief  enable or disable the sd i/o function.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.ioen = new_state;
+}
+
+/**
+  * @brief  enable or disable sd i/o suspend command sending.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->cmdctrl_bit.iosusp = new_state;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_spi.c

@@ -0,0 +1,610 @@
+/**
+  **************************************************************************
+  * @file     at32f413_spi.c
+  * @brief    contains all the functions for the spi firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup SPI
+  * @brief SPI driver modules
+  * @{
+  */
+
+#ifdef SPI_MODULE_ENABLED
+
+/** @defgroup SPI_private_functions
+  * @{
+  */
+
+/**
+  * @brief  spi reset by crm reset register
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @retval none
+  */
+void spi_i2s_reset(spi_type *spi_x)
+{
+  if(spi_x == SPI1)
+  {
+    crm_periph_reset(CRM_SPI1_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_SPI1_PERIPH_RESET, FALSE);
+  }
+  else if(spi_x == SPI2)
+  {
+    crm_periph_reset(CRM_SPI2_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_SPI2_PERIPH_RESET, FALSE);
+  }
+}
+
+/**
+  * @brief  spi init config with its default value.
+  * @param  spi_init_struct : pointer to a spi_init_type structure which will
+  *         be initialized.
+  * @retval none
+  */
+void spi_default_para_init(spi_init_type* spi_init_struct)
+{
+  spi_init_struct->transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
+  spi_init_struct->master_slave_mode = SPI_MODE_SLAVE;
+  spi_init_struct->mclk_freq_division = SPI_MCLK_DIV_2;
+  spi_init_struct->first_bit_transmission = SPI_FIRST_BIT_MSB;
+  spi_init_struct->frame_bit_num = SPI_FRAME_8BIT;
+  spi_init_struct->clock_polarity = SPI_CLOCK_POLARITY_LOW;
+  spi_init_struct->clock_phase = SPI_CLOCK_PHASE_1EDGE;
+  spi_init_struct->cs_mode_selection = SPI_CS_SOFTWARE_MODE;
+}
+
+/**
+  * @brief  spi init config with its setting value.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  spi_init_struct : pointer to a spi_init_type structure which will be initialized.
+  * @retval none
+  */
+void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct)
+{
+  spi_x->i2sctrl_bit.i2smsel = FALSE;
+  if(spi_init_struct->transmission_mode == SPI_TRANSMIT_FULL_DUPLEX)
+  {
+    spi_x->ctrl1_bit.slben = FALSE;
+    spi_x->ctrl1_bit.slbtd = FALSE;
+    spi_x->ctrl1_bit.ora = FALSE;
+  }
+  else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_SIMPLEX_RX)
+  {
+    spi_x->ctrl1_bit.slben = FALSE;
+    spi_x->ctrl1_bit.slbtd = FALSE;
+    spi_x->ctrl1_bit.ora = TRUE;
+  }
+  else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_RX)
+  {
+    spi_x->ctrl1_bit.slben = TRUE;
+    spi_x->ctrl1_bit.slbtd = FALSE;
+    spi_x->ctrl1_bit.ora = FALSE;
+  }
+  else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_TX)
+  {
+    spi_x->ctrl1_bit.slben = TRUE;
+    spi_x->ctrl1_bit.slbtd = TRUE;
+    spi_x->ctrl1_bit.ora = FALSE;
+  }
+
+  spi_x->ctrl1_bit.swcsen = spi_init_struct->cs_mode_selection;
+  if((spi_init_struct->master_slave_mode == SPI_MODE_MASTER) && (spi_init_struct->cs_mode_selection == SPI_CS_SOFTWARE_MODE))
+  {
+    spi_x->ctrl1_bit.swcsil = TRUE;
+  }
+  else
+  {
+    spi_x->ctrl1_bit.swcsil = FALSE;
+  }
+  spi_x->ctrl1_bit.msten = spi_init_struct->master_slave_mode;
+  if(spi_init_struct->mclk_freq_division > SPI_MCLK_DIV_256)
+  {
+    spi_x->ctrl2_bit.mdiv_h = 1;
+    spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division & 0x7;
+  }
+  else
+  {
+    spi_x->ctrl2_bit.mdiv_h = 0;
+    spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division;
+  }
+  spi_x->ctrl1_bit.ltf = spi_init_struct->first_bit_transmission;
+  spi_x->ctrl1_bit.fbn = spi_init_struct->frame_bit_num;
+  spi_x->ctrl1_bit.clkpol = spi_init_struct->clock_polarity;
+  spi_x->ctrl1_bit.clkpha = spi_init_struct->clock_phase;
+}
+
+/**
+  * @brief  spi next transmit crc for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @retval none
+  */
+void spi_crc_next_transmit(spi_type* spi_x)
+{
+  spi_x->ctrl1_bit.ntc = TRUE;
+}
+
+/**
+  * @brief  set the crc polynomial value for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  crc_poly: crc polynomial value.
+  * @retval none
+  */
+void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly)
+{
+  spi_x->cpoly_bit.cpoly = crc_poly;
+}
+
+/**
+  * @brief  return the crc polynomial register value for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @retval the select crc polynomial register value
+  */
+uint16_t spi_crc_polynomial_get(spi_type* spi_x)
+{
+  return spi_x->cpoly_bit.cpoly;
+}
+
+/**
+  * @brief  enable or disable the hardware crc calculation for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  new_state: new state of crc calculation.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_crc_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl1_bit.ccen = new_state;
+}
+
+/**
+  * @brief  return the transmit or the receive crc value for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  crc_direction: select transmit or receive crc value to be read
+  *         - SPI_CRC_RX
+  *         - SPI_CRC_TX
+  * @retval the select crc register value
+  */
+uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction)
+{
+  if(crc_direction == SPI_CRC_RX)
+    return  spi_x->rcrc_bit.rcrc;
+  else
+    return  spi_x->tcrc_bit.tcrc;
+}
+
+/**
+  * @brief  enable or disable the hardware cs output for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  new_state: new state of spi master cs output.
+  *         this parameter can be: TRUE or FALSE.
+  *         note:the bit only use in spi master mode
+  * @retval none
+  */
+void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl2_bit.hwcsoe = new_state;
+}
+
+/**
+  * @brief  set the software cs internal level for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  level: set the state of spi cs level.
+  *         this parameter can be one of the following values:
+  *         - SPI_SWCS_INTERNAL_LEVEL_LOW
+  *         - SPI_SWCS_INTERNAL_LEVEL_HIGHT
+  *         note:the bit only use when swcsen bit is set.
+  *         note:when use this bit,io operation on the cs pin are invalid.
+  * @retval none
+  */
+void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level)
+{
+  spi_x->ctrl1_bit.swcsil = level;
+}
+
+/**
+  * @brief  set the data frame bit num for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  bit_num: set the data frame size
+  *         - SPI_FRAME_8BIT
+  *         - SPI_FRAME_16BIT
+  * @retval none
+  */
+void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num)
+{
+  spi_x->ctrl1_bit.fbn = bit_num;
+}
+
+/**
+  * @brief  set the data transmission direction in single line bidirectiona half duplex mode of the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  direction: data transfer direction
+  *         this parameter can be one of the following values:
+  *         - SPI_HALF_DUPLEX_DIRECTION_RX
+  *         - SPI_HALF_DUPLEX_DIRECTION_TX
+  * @retval none
+  */
+void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction)
+{
+    spi_x->ctrl1_bit.slbtd = direction;
+}
+
+/**
+  * @brief  enable or disable spi.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  new_state: new state of spi.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl1_bit.spien = new_state;
+}
+
+/**
+  * @brief  i2s init config with its default value.
+  * @param  i2s_init_struct : pointer to a i2s_init_type structure which will
+  *         be initialized.
+  * @retval none
+  */
+void i2s_default_para_init(i2s_init_type* i2s_init_struct)
+{
+  i2s_init_struct->operation_mode = I2S_MODE_SLAVE_TX;
+  i2s_init_struct->audio_protocol = I2S_AUDIO_PROTOCOL_PHILLIPS;
+  i2s_init_struct->audio_sampling_freq = I2S_AUDIO_FREQUENCY_DEFAULT;
+  i2s_init_struct->data_channel_format = I2S_DATA_16BIT_CHANNEL_16BIT;
+  i2s_init_struct->clock_polarity = I2S_CLOCK_POLARITY_LOW;
+  i2s_init_struct->mclk_output_enable = FALSE;
+}
+
+/**
+  * @brief  i2s init config with its setting value.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  i2s_init_struct : pointer to a i2s_init_type structure which will be initialized.
+  * @retval none
+  */
+void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct)
+{
+  crm_clocks_freq_type clocks_freq;
+  uint32_t i2s_sclk_index = 0;
+  uint32_t i2sdiv_index = 2, i2sodd_index = 0, frequency_index = 0;
+
+  /* i2s audio frequency config */
+  if(i2s_init_struct->audio_sampling_freq == I2S_AUDIO_FREQUENCY_DEFAULT)
+  {
+    i2sodd_index = 0;
+    i2sdiv_index = 2;
+  }
+  else
+  {
+    crm_clocks_freq_get(&clocks_freq);
+    i2s_sclk_index = clocks_freq.sclk_freq;
+    if((i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT) || (i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG))
+    {
+      if(i2s_init_struct->mclk_output_enable == TRUE)
+      {
+        frequency_index = (((i2s_sclk_index / 128) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+      }
+      else
+      {
+        if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+          frequency_index = (((i2s_sclk_index / 16) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+        else
+          frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+      }
+    }
+    else
+    {
+      if(i2s_init_struct->mclk_output_enable == TRUE)
+      {
+        frequency_index = (((i2s_sclk_index / 256) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+      }
+      else
+      {
+        if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+          frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+        else
+          frequency_index = (((i2s_sclk_index / 64) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+      }
+    }
+  }
+  frequency_index = frequency_index / 10;
+  i2sodd_index = frequency_index & (uint16_t)0x0001;
+  i2sdiv_index = (frequency_index - i2sodd_index) / 2;
+  if((i2sdiv_index < 2) || (i2sdiv_index > 0x03FF))
+  {
+    i2sodd_index = 0;
+    i2sdiv_index = 2;
+  }
+  spi_x->i2sclk_bit.i2sodd = i2sodd_index;
+  if(i2sdiv_index > 0x00FF)
+  {
+    spi_x->i2sclk_bit.i2sdiv_h = (i2sdiv_index >> 8) & 0x0003;
+    spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index & 0x00FF;
+  }
+  else
+  {
+    spi_x->i2sclk_bit.i2sdiv_h = 0;
+    spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index;
+  }
+
+  /* i2s audio_protocol set*/
+  if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 1;
+    spi_x->i2sctrl_bit.stdsel = 3;
+  }
+  else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 0;
+    spi_x->i2sctrl_bit.stdsel = 3;
+  }
+  else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_LSB)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 0;
+    spi_x->i2sctrl_bit.stdsel = 2;
+  }
+  else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_MSB)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 0;
+    spi_x->i2sctrl_bit.stdsel = 1;
+  }
+  else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PHILLIPS)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 0;
+    spi_x->i2sctrl_bit.stdsel = 0;
+  }
+
+  /* i2s data_channel_format set*/
+  if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+  {
+    spi_x->i2sctrl_bit.i2scbn = 0;
+    spi_x->i2sctrl_bit.i2sdbn = 0;
+  }
+  else if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_32BIT)
+  {
+    spi_x->i2sctrl_bit.i2scbn = 1;
+    spi_x->i2sctrl_bit.i2sdbn = 0;
+  }
+  else if(i2s_init_struct->data_channel_format == I2S_DATA_24BIT_CHANNEL_32BIT)
+  {
+    spi_x->i2sctrl_bit.i2scbn = 1;
+    spi_x->i2sctrl_bit.i2sdbn = 1;
+  }
+  else if(i2s_init_struct->data_channel_format == I2S_DATA_32BIT_CHANNEL_32BIT)
+  {
+    spi_x->i2sctrl_bit.i2scbn = 1;
+    spi_x->i2sctrl_bit.i2sdbn = 2;
+  }
+
+  spi_x->i2sctrl_bit.i2sclkpol = i2s_init_struct->clock_polarity;
+  spi_x->i2sclk_bit.i2smclkoe = i2s_init_struct->mclk_output_enable;
+  spi_x->i2sctrl_bit.opersel = i2s_init_struct->operation_mode;
+  spi_x->i2sctrl_bit.i2smsel = TRUE;
+}
+
+/**
+  * @brief  enable or disable i2s.
+  * @param  spi_x: select the i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  new_state: new state of i2s.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void i2s_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->i2sctrl_bit.i2sen = new_state;
+}
+
+/**
+  * @brief  enable or disable the specified spi/i2s interrupts.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled.
+  *         this parameter can be one of the following values:
+  *         - SPI_I2S_ERROR_INT
+  *         - SPI_I2S_RDBF_INT
+  *         - SPI_I2S_TDBE_INT
+  * @param  new_state: new state of the specified spi/i2s interrupts.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    spi_x->ctrl2 |= spi_i2s_int;
+  }
+  else
+  {
+    spi_x->ctrl2 &= ~spi_i2s_int;
+  }
+}
+
+/**
+  * @brief  enable or disable the spi/i2s dma transmitter mode.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  new_state: new state of the dma request.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl2_bit.dmaten = new_state;
+}
+
+/**
+  * @brief  enable or disable the spi/i2s dma receiver mode.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  new_state: new state of the dma request.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl2_bit.dmaren = new_state;
+}
+
+/**
+  * @brief  spi/i2s data transmit
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  tx_data: the data to be transmit.
+  *         this parameter can be:
+  *         - (0x0000~0xFFFF)
+  * @retval none
+  */
+void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data)
+{
+  spi_x->dt = tx_data;
+}
+
+/**
+  * @brief  spi/i2s data receive
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @retval the received data value
+  */
+uint16_t spi_i2s_data_receive(spi_type* spi_x)
+{
+  return (uint16_t)spi_x->dt;
+}
+
+/**
+  * @brief  get flag of the specified spi/i2s peripheral.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  spi_i2s_flag: select the spi/i2s flag
+  *         this parameter can be one of the following values:
+  *         - SPI_I2S_RDBF_FLAG
+  *         - SPI_I2S_TDBE_FLAG
+  *         - I2S_ACS_FLAG    (this flag only use in i2s mode)
+  *         - I2S_TUERR_FLAG  (this flag only use in i2s mode)
+  *         - SPI_CCERR_FLAG  (this flag only use in spi mode)
+  *         - SPI_MMERR_FLAG  (this flag only use in spi mode)
+  *         - SPI_I2S_ROERR_FLAG
+  *         - SPI_I2S_BF_FLAG
+  * @retval the new state of spi/i2s flag
+  */
+flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
+{
+  flag_status status = RESET;
+  if ((spi_x->sts & spi_i2s_flag) == RESET)
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+  return status;
+}
+
+/**
+  * @brief  clear flag of the specified spi/i2s peripheral.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2
+  * @param  spi_i2s_flag: select the spi/i2s flag
+  *         this parameter can be one of the following values:
+  *         - SPI_CCERR_FLAG
+  *         - SPI_I2S_RDBF_FLAG
+  *         - I2S_TUERR_FLAG
+  *         - SPI_MMERR_FLAG
+  *         - SPI_I2S_ROERR_FLAG
+  * @note
+  *         SPI_I2S_TDBE_FLAG  this flag is cleared when the tx buffer already contain data to be transmit.
+  *         I2S_ACS_FLAG       this flag cann't cleared by software,the flag indicate the channel side(not use in pcm standard mode).
+  *         SPI_I2S_BF_FLAG    this flag cann't cleared by software, it's set and cleared by hardware.
+  * @retval none
+  */
+void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
+{
+  if(spi_i2s_flag == SPI_CCERR_FLAG)
+    spi_x->sts = ~SPI_CCERR_FLAG;
+  else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
+    UNUSED(spi_x->dt);
+  else if(spi_i2s_flag == I2S_TUERR_FLAG)
+    UNUSED(spi_x->sts);
+  else if(spi_i2s_flag == SPI_MMERR_FLAG)
+  {
+    UNUSED(spi_x->sts);
+    spi_x->ctrl1 = spi_x->ctrl1;
+  }
+  else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG)
+  {
+    UNUSED(spi_x->dt);
+    UNUSED(spi_x->sts);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_tmr.c

@@ -0,0 +1,1746 @@
+/**
+  **************************************************************************
+  * @file     at32f413_tmr.c
+  * @brief    contains all the functions for the tmr firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup TMR
+  * @brief TMR driver modules
+  * @{
+  */
+
+#ifdef TMR_MODULE_ENABLED
+
+/** @defgroup TMR_private_functions
+  * @{
+  */
+
+/**
+  * @brief  tmr reset by crm reset register
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @retval none
+  */
+void tmr_reset(tmr_type *tmr_x)
+{
+  if(tmr_x == TMR1)
+  {
+    crm_periph_reset(CRM_TMR1_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_TMR1_PERIPH_RESET, FALSE);
+  }
+  else if(tmr_x == TMR2)
+  {
+    crm_periph_reset(CRM_TMR2_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_TMR2_PERIPH_RESET, FALSE);
+  }
+  else if(tmr_x == TMR3)
+  {
+    crm_periph_reset(CRM_TMR3_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_TMR3_PERIPH_RESET, FALSE);
+  }
+  else if(tmr_x == TMR4)
+  {
+    crm_periph_reset(CRM_TMR4_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_TMR4_PERIPH_RESET, FALSE);
+  }
+#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \
+    defined (AT32F413Kx)
+  else if(tmr_x == TMR5)
+  {
+    crm_periph_reset(CRM_TMR5_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_TMR5_PERIPH_RESET, FALSE);
+  }
+#if defined (AT32F413CCU7) || defined (AT32F413CCT7) || defined (AT32F413RCT7)
+  else if(tmr_x == TMR8)
+  {
+    crm_periph_reset(CRM_TMR8_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_TMR8_PERIPH_RESET, FALSE);
+  }
+#endif
+  else if(tmr_x == TMR9)
+  {
+    crm_periph_reset(CRM_TMR9_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_TMR9_PERIPH_RESET, FALSE);
+  }
+  else if(tmr_x == TMR10)
+  {
+    crm_periph_reset(CRM_TMR10_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_TMR10_PERIPH_RESET, FALSE);
+  }
+  else if(tmr_x == TMR11)
+  {
+    crm_periph_reset(CRM_TMR11_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_TMR11_PERIPH_RESET, FALSE);
+  }
+#endif
+}
+
+/**
+  * @brief  enable or disable tmr counter
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+  /* tmr counter enable  */
+  tmr_x->ctrl1_bit.tmren = new_state;
+}
+
+/**
+  * @brief  init tmr output default para
+  * @param  tmr_output_struct
+  *         - to the structure of tmr_output_config_type
+  * @retval none
+  */
+void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct)
+{
+  tmr_output_struct->oc_mode = TMR_OUTPUT_CONTROL_OFF;
+  tmr_output_struct->oc_idle_state = FALSE;
+  tmr_output_struct->occ_idle_state = FALSE;
+  tmr_output_struct->oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
+  tmr_output_struct->occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
+  tmr_output_struct->oc_output_state = FALSE;
+  tmr_output_struct->occ_output_state = FALSE;
+}
+
+/**
+  * @brief  init tmr input default para
+  * @param  tmr_input_struct
+  *         - to the structure of tmr_input_config_type
+  * @retval none
+  */
+void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct)
+{
+  tmr_input_struct->input_channel_select = TMR_SELECT_CHANNEL_1;
+  tmr_input_struct->input_polarity_select = TMR_INPUT_RISING_EDGE;
+  tmr_input_struct->input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
+  tmr_input_struct->input_filter_value = 0x0;
+}
+
+/**
+  * @brief  init tmr brkdt default para
+  * @param  tmr_brkdt_struct
+  *         - to the structure of tmr_brkdt_config_type
+  * @retval none
+  */
+void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct)
+{
+  tmr_brkdt_struct->deadtime = 0x0;
+  tmr_brkdt_struct->brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW;
+  tmr_brkdt_struct->wp_level = TMR_WP_OFF;
+  tmr_brkdt_struct->auto_output_enable = FALSE ;
+  tmr_brkdt_struct->fcsoen_state = FALSE ;
+  tmr_brkdt_struct->fcsodis_state = FALSE ;
+  tmr_brkdt_struct->brk_enable = FALSE ;
+}
+
+/**
+  * @brief  init tmr base
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_pr (for 16 bit tmr 0x0000~0xFFFF,
+  *                  for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+  * @param  tmr_div (timer div value:0x0000~0xFFFF)
+  * @retval none
+  */
+void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div)
+{
+  /* set the pr value */
+  tmr_x->pr = tmr_pr;
+
+  /* set the div value */
+  tmr_x->div = tmr_div;
+
+  /* trigger the overflow event to immediately reload pr value and div value */
+  tmr_x->swevt_bit.ovfswtr = TRUE;
+}
+
+/**
+  * @brief  set tmr clock source division
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_clock_div
+  *         this parameter can be one of the following values:
+  *         - TMR_CLOCK_DIV1
+  *         - TMR_CLOCK_DIV2
+  *         - TMR_CLOCK_DIV4
+  * @retval none
+  */
+void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div)
+{
+  /* set tmr clock source division */
+  tmr_x->ctrl1_bit.clkdiv = tmr_clock_div;
+}
+
+/**
+  * @brief  set tmr counter count direction
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_cnt_dir
+  *         this parameter can be one of the following values:
+  *         - TMR_COUNT_UP
+  *         - TMR_COUNT_DOWN
+  *         - TMR_COUNT_TWO_WAY_1
+  *         - TMR_COUNT_TWO_WAY_2
+  *         - TMR_COUNT_TWO_WAY_3
+  * @retval none
+  */
+void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir)
+{
+  /* set the cnt direct */
+  tmr_x->ctrl1_bit.cnt_dir = tmr_cnt_dir;
+}
+
+/**
+  * @brief  set the repetition counter register(rpr) value
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR8
+  * @param  tmr_rpr_value (0x00~0xFF)
+  * @retval none
+  */
+void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value)
+{
+  /* set the repetition counter value */
+  tmr_x->rpr_bit.rpr = tmr_rpr_value;
+}
+
+/**
+  * @brief  set tmr counter value
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_cnt_value (for 16 bit tmr 0x0000~0xFFFF,
+  *                        for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+  * @retval none
+  */
+void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value)
+{
+  /* set the tmr counter value */
+  tmr_x->cval = tmr_cnt_value;
+}
+
+/**
+  * @brief  get tmr counter value
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @retval tmr counter value
+  */
+uint32_t tmr_counter_value_get(tmr_type *tmr_x)
+{
+  return tmr_x->cval;
+}
+
+/**
+  * @brief  set tmr div value
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_div_value (for 16 bit tmr 0x0000~0xFFFF,
+  *                        for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+  * @retval none
+  */
+void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value)
+{
+  /* set the tmr div value */
+  tmr_x->div = tmr_div_value;
+}
+
+/**
+  * @brief  get tmr div value
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @retval tmr div value
+  */
+uint32_t tmr_div_value_get(tmr_type *tmr_x)
+{
+  return tmr_x->div;
+}
+
+/**
+  * @brief  config tmr output channel
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  tmr_output_struct
+  *         - to the structure of tmr_output_config_type
+  * @retval none
+  */
+void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
+                               tmr_output_config_type *tmr_output_struct)
+{
+  uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset;
+
+  chx_offset = (8 + tmr_channel);
+  chcx_offset = (9 + tmr_channel);
+  
+  /* get channel idle state bit position in ctrl2 register */
+  channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset);
+
+  /* get channel complementary idle state bit position in ctrl2 register */
+  channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset);
+
+  /* set output channel complementary idle state */
+  tmr_x->ctrl2 &= ~(1<<chcx_offset);
+  tmr_x->ctrl2 |= channel_c_index;
+
+  /* set output channel idle state */
+  tmr_x->ctrl2 &= ~(1<<chx_offset);
+  tmr_x->ctrl2 |= channel_index;
+
+  /* set channel output mode */
+  channel = tmr_channel;
+
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cm1_output_bit.c1octrl = tmr_output_struct->oc_mode;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cm1_output_bit.c2octrl = tmr_output_struct->oc_mode;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cm2_output_bit.c3octrl = tmr_output_struct->oc_mode;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cm2_output_bit.c4octrl = tmr_output_struct->oc_mode;
+      break;
+
+    default:
+      break;
+  }
+
+  chx_offset = ((tmr_channel * 2) + 1);
+  chcx_offset = ((tmr_channel * 2) + 3);
+
+  /* get channel polarity bit position in cctrl register */
+  channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset);
+
+  /* get channel complementary polarity bit position in cctrl register */
+  channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset);
+
+  /* set output channel complementary polarity */
+  tmr_x->cctrl &= ~(1<<chcx_offset);
+  tmr_x->cctrl |= channel_c_index;
+
+  /* set output channel polarity */
+  tmr_x->cctrl &= ~(1<<chx_offset);
+  tmr_x->cctrl |= channel_index;
+
+  chx_offset = (tmr_channel * 2);
+  chcx_offset = ((tmr_channel * 2) + 2);
+
+  /* get channel enable bit position in cctrl register */
+  channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2));
+
+  /* get channel complementary enable bit position in cctrl register */
+  channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2));
+
+  /* set output channel complementary enable bit */
+  tmr_x->cctrl &= ~(1<<chcx_offset);
+  tmr_x->cctrl |= channel_c_index;
+
+  /* set output channel enable bit */
+  tmr_x->cctrl &= ~(1<<chx_offset);
+  tmr_x->cctrl |= channel_index;
+}
+
+/**
+  * @brief  select tmr output channel mode
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  oc_mode
+  *         this parameter can be one of the following values:
+  *         - TMR_OUTPUT_CONTROL_OFF
+  *         - TMR_OUTPUT_CONTROL_HIGH
+  *         - TMR_OUTPUT_CONTROL_LOW
+  *         - TMR_OUTPUT_CONTROL_SWITCH
+  *         - TMR_OUTPUT_CONTROL_FORCE_HIGH
+  *         - TMR_OUTPUT_CONTROL_FORCE_LOW
+  *         - TMR_OUTPUT_CONTROL_PWM_MODE_A
+  *         - TMR_OUTPUT_CONTROL_PWM_MODE_B
+  * @retval none
+  */
+void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
+                                    tmr_output_control_mode_type oc_mode)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cm1_output_bit.c1octrl = oc_mode;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cm1_output_bit.c2octrl = oc_mode;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cm2_output_bit.c3octrl = oc_mode;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cm2_output_bit.c4octrl = oc_mode;
+      break;
+
+    default:
+      break;
+  }
+}
+/**
+  * @brief  set tmr period value
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_pr_value: timer period register value of counter
+  *                       (for 16 bit tmr 0x0000~0xFFFF,
+  *                       for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+  * @retval none
+  */
+void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value)
+{
+  /* set tmr period value */
+  tmr_x->pr = tmr_pr_value;
+}
+
+/**
+  * @brief  get tmr period value
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @retval timer period register value of counter
+  *         (for 16 bit tmr 0x0000~0xFFFF, for 32 bit tmr
+  *         0x0000_0000~0xFFFF_FFFF)
+  */
+uint32_t tmr_period_value_get(tmr_type *tmr_x)
+{
+  return tmr_x->pr;
+}
+
+/**
+  * @brief  set tmr channel value
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  tmr_channel_value (for 16 bit tmr 0x0000~0xFFFF,
+  *                       for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+  * @retval none
+  */
+void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
+                           uint32_t tmr_channel_value)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  /* set tmr channel value */
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->c1dt = tmr_channel_value;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->c2dt = tmr_channel_value;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->c3dt = tmr_channel_value;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->c4dt = tmr_channel_value;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  get tmr channel value
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @retval tmr channel value
+  */
+uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel)
+{
+  uint32_t cc_value_get = 0;
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  /* get tmr channel value */
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      cc_value_get = tmr_x->c1dt;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      cc_value_get = tmr_x->c2dt;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      cc_value_get = tmr_x->c3dt;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      cc_value_get = tmr_x->c4dt;
+      break;
+
+    default:
+      break;
+  }
+
+  return cc_value_get;
+}
+/**
+  * @brief  enable tmr period buffer
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+  /* tmr period buffer set */
+  tmr_x->ctrl1_bit.prben = new_state;
+}
+
+/**
+  * @brief  enable tmr output channel buffer
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
+                                   confirm_state new_state)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  /* get tmr channel value */
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cm1_output_bit.c1oben = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cm1_output_bit.c2oben = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cm2_output_bit.c3oben = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cm2_output_bit.c4oben = new_state;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  set tmr output channel immediately
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
+                                        confirm_state new_state)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  /* get tmr channel value */
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cm1_output_bit.c1oien = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cm1_output_bit.c2oien = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cm2_output_bit.c3oien = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cm2_output_bit.c4oien = new_state;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  set tmr output channel switch
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
+                                   confirm_state new_state)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  /* get tmr channel value */
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cm1_output_bit.c1osen = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cm1_output_bit.c2osen = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cm2_output_bit.c3osen = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cm2_output_bit.c4osen = new_state;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  enable or disable tmr one cycle mode
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+  /* tmr one cycle mode enable */
+  tmr_x->ctrl1_bit.ocmen = new_state;
+}
+
+/**
+  * @brief  enable or disable  tmr 32 bit function(plus mode)
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR2, TMR5
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state)
+{
+  /* tmr 32 bit function(plus mode) enable,only for TMR2/TMR5 */
+  if((tmr_x == TMR2)
+#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \
+    defined (AT32F413Kx)
+     || (tmr_x == TMR5)
+#endif
+  )
+  {
+    tmr_x->ctrl1_bit.pmen = new_state;
+  }
+}
+
+/**
+  * @brief  select tmr the overflow event sources
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state)
+{
+  tmr_x->ctrl1_bit.ovfs = new_state;
+}
+
+/**
+  * @brief  enable or disable tmr overflow event generation
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state)
+{
+  tmr_x->ctrl1_bit.ovfen = new_state;
+}
+
+/**
+  * @brief  init tmr input channel
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  input_struct
+  *         - to the structure of tmr_input_config_type
+  * @param  divider_factor
+  *         this parameter can be one of the following values:
+  *         - TMR_CHANNEL_INPUT_DIV_1
+  *         - TMR_CHANNEL_INPUT_DIV_2
+  *         - TMR_CHANNEL_INPUT_DIV_4
+  *         - TMR_CHANNEL_INPUT_DIV_8
+  * @retval none
+  */
+void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct,
+                            tmr_channel_input_divider_type divider_factor)
+{
+  uint16_t channel = 0;
+
+  /* get channel selected */
+  channel = input_struct->input_channel_select;
+
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+	  tmr_x->cctrl_bit.c1en       = FALSE;
+      tmr_x->cctrl_bit.c1p        = (uint32_t)input_struct->input_polarity_select;
+      tmr_x->cctrl_bit.c1cp       = (input_struct->input_polarity_select & 0x2) >> 1;
+      tmr_x->cm1_input_bit.c1c    = input_struct->input_mapped_select;
+      tmr_x->cm1_input_bit.c1df   = input_struct->input_filter_value;
+      tmr_x->cm1_input_bit.c1idiv = divider_factor;
+      tmr_x->cctrl_bit.c1en       = TRUE;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+	  tmr_x->cctrl_bit.c2en       = FALSE;
+      tmr_x->cctrl_bit.c2p        = (uint32_t)input_struct->input_polarity_select;
+      tmr_x->cctrl_bit.c2cp       = (input_struct->input_polarity_select & 0x2) >> 1;
+      tmr_x->cm1_input_bit.c2c    = input_struct->input_mapped_select;
+      tmr_x->cm1_input_bit.c2df   = input_struct->input_filter_value;
+      tmr_x->cm1_input_bit.c2idiv = divider_factor;
+      tmr_x->cctrl_bit.c2en       = TRUE;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+	  tmr_x->cctrl_bit.c3en       = FALSE;
+      tmr_x->cctrl_bit.c3p        = (uint32_t)input_struct->input_polarity_select;
+      tmr_x->cctrl_bit.c3cp       = (input_struct->input_polarity_select & 0x2) >> 1;
+      tmr_x->cm2_input_bit.c3c    = input_struct->input_mapped_select;
+      tmr_x->cm2_input_bit.c3df   = input_struct->input_filter_value;
+      tmr_x->cm2_input_bit.c3idiv = divider_factor;
+      tmr_x->cctrl_bit.c3en       = TRUE;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+	  tmr_x->cctrl_bit.c4en       = FALSE;
+      tmr_x->cctrl_bit.c4p        = (uint32_t)input_struct->input_polarity_select;
+      tmr_x->cm2_input_bit.c4c    = input_struct->input_mapped_select;
+      tmr_x->cm2_input_bit.c4df   = input_struct->input_filter_value;
+      tmr_x->cm2_input_bit.c4idiv = divider_factor;
+      tmr_x->cctrl_bit.c4en       = TRUE;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  tmr channel enable
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_1C
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_2C
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_3C
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cctrl_bit.c1en         = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_1C:
+      tmr_x->cctrl_bit.c1cen        = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cctrl_bit.c2en         = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_2C:
+      tmr_x->cctrl_bit.c2cen        = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cctrl_bit.c3en         = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_3C:
+      tmr_x->cctrl_bit.c3cen        = new_state;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cctrl_bit.c4en         = new_state;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  set tmr input channel filter
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  filter_value (0x0~0xf)
+  * @retval none
+  */
+void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
+                                  uint16_t filter_value)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cm1_input_bit.c1df = filter_value;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cm1_input_bit.c2df = filter_value;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cm2_input_bit.c3df = filter_value;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cm2_input_bit.c4df = filter_value;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  config tmr pwm input
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  input_struct
+  *         - to the structure of tmr_input_config_type
+  * @param  divider_factor
+  *         this parameter can be one of the following values:
+  *         - TMR_CHANNEL_INPUT_DIV_1
+  *         - TMR_CHANNEL_INPUT_DIV_2
+  *         - TMR_CHANNEL_INPUT_DIV_4
+  *         - TMR_CHANNEL_INPUT_DIV_8
+  * @retval none
+  */
+void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct,
+                          tmr_channel_input_divider_type divider_factor)
+{
+  uint16_t channel = 0;
+
+  /* get channel selected */
+  channel = input_struct->input_channel_select;
+
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      if(input_struct->input_polarity_select == TMR_INPUT_RISING_EDGE)
+      {
+        /* set channel polarity */
+        tmr_x->cctrl_bit.c1p          = TMR_INPUT_RISING_EDGE;
+        tmr_x->cctrl_bit.c2p          = TMR_INPUT_FALLING_EDGE;
+      }
+      else if(input_struct->input_polarity_select == TMR_INPUT_FALLING_EDGE)
+      {
+        /* set channel polarity */
+        tmr_x->cctrl_bit.c1p          = TMR_INPUT_FALLING_EDGE;
+        tmr_x->cctrl_bit.c2p          = TMR_INPUT_RISING_EDGE;
+      }
+
+      if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_DIRECT)
+      {
+        /* ic1 is mapped on ti1 */
+        tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+
+        /* ic1 is mapped on ti2 */
+        tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+      }
+      else if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_INDIRECT)
+      {
+        /* ic1 is mapped on ti1 */
+        tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+
+        /* ic1 is mapped on ti2 */
+        tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+      }
+
+      /* set input ch1 and ch2 filter value*/
+      tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
+      tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
+
+      /*set input ch1 and ch2 divider value*/
+      tmr_x->cm1_input_bit.c1idiv = divider_factor;
+      tmr_x->cm1_input_bit.c2idiv = divider_factor;
+
+      tmr_x->cctrl_bit.c1en = TRUE;
+      tmr_x->cctrl_bit.c2en = TRUE;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      if(input_struct->input_polarity_select == TMR_INPUT_RISING_EDGE)
+      {
+        /* set channel polarity */
+        tmr_x->cctrl_bit.c2p          = TMR_INPUT_RISING_EDGE;
+        tmr_x->cctrl_bit.c1p          = TMR_INPUT_FALLING_EDGE;
+      }
+      else if(input_struct->input_polarity_select == TMR_INPUT_FALLING_EDGE)
+      {
+        /* set channel polarity */
+        tmr_x->cctrl_bit.c2p          = TMR_INPUT_FALLING_EDGE;
+        tmr_x->cctrl_bit.c1p          = TMR_INPUT_RISING_EDGE;
+      }
+
+      if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_DIRECT)
+      {
+        /* set mapped direct */
+        tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+        tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+      }
+      else if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_INDIRECT)
+      {
+        /* set mapped direct */
+        tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+        tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+      }
+
+      /* set input ch1 and ch2 filter value*/
+      tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
+      tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
+
+      /*set input ch1 and ch2 divider value*/
+      tmr_x->cm1_input_bit.c1idiv = divider_factor;
+      tmr_x->cm1_input_bit.c2idiv = divider_factor;
+
+      tmr_x->cctrl_bit.c1en = TRUE;
+      tmr_x->cctrl_bit.c2en = TRUE;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  select tmr channel1 input
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+  * @param  ch1_connect
+  *         this parameter can be one of the following values:
+  *         - TMR_CHANEL1_CONNECTED_C1IRAW
+  *         - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR
+  * @retval none
+  */
+void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect)
+{
+  tmr_x->ctrl2_bit.c1insel = ch1_connect;
+}
+
+/**
+  * @brief  set tmr input channel divider
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  divider_factor
+  *         this parameter can be one of the following values:
+  *         - TMR_CHANNEL_INPUT_DIV_1
+  *         - TMR_CHANNEL_INPUT_DIV_2
+  *         - TMR_CHANNEL_INPUT_DIV_4
+  *         - TMR_CHANNEL_INPUT_DIV_8
+  * @retval none
+  */
+void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
+                                   tmr_channel_input_divider_type divider_factor)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cm1_input_bit.c1idiv = divider_factor;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cm1_input_bit.c2idiv = divider_factor;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cm2_input_bit.c3idiv = divider_factor;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cm2_input_bit.c4idiv = divider_factor;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  select tmr primary mode
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+  * @param  primary_mode
+  *         this parameter can be one of the following values:
+  *         - TMR_PRIMARY_SEL_RESET
+  *         - TMR_PRIMARY_SEL_ENABLE
+  *         - TMR_PRIMARY_SEL_OVERFLOW
+  *         - TMR_PRIMARY_SEL_COMPARE
+  *         - TMR_PRIMARY_SEL_C1ORAW
+  *         - TMR_PRIMARY_SEL_C2ORAW
+  *         - TMR_PRIMARY_SEL_C3ORAW
+  *         - TMR_PRIMARY_SEL_C4ORAW
+  * @retval none
+  */
+void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode)
+{
+  tmr_x->ctrl2_bit.ptos = primary_mode;
+}
+
+/**
+  * @brief  select tmr subordinate mode
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9
+  * @param  sub_mode
+  *         this parameter can be one of the following values:
+  *         - TMR_SUB_MODE_DIABLE
+  *         - TMR_SUB_ENCODER_MODE_A
+  *         - TMR_SUB_ENCODER_MODE_B
+  *         - TMR_SUB_ENCODER_MODE_C
+  *         - TMR_SUB_RESET_MODE
+  *         - TMR_SUB_HANG_MODE
+  *         - TMR_SUB_TRIGGER_MODE
+  *         - TMR_SUB_EXTERNAL_CLOCK_MODE_A
+  * @retval none
+  */
+void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode)
+{
+  tmr_x->stctrl_bit.smsel = sub_mode;
+}
+
+/**
+  * @brief  select tmr channel dma
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9
+  * @param  cc_dma_select
+  *         this parameter can be one of the following values:
+  *         - TMR_DMA_REQUEST_BY_CHANNEL
+  *         - TMR_DMA_REQUEST_BY_OVERFLOW
+  * @retval none
+  */
+void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select)
+{
+  tmr_x->ctrl2_bit.drs = cc_dma_select;
+}
+
+/**
+  * @brief  select tmr hall
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR8
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_hall_select(tmr_type *tmr_x,  confirm_state new_state)
+{
+  tmr_x->ctrl2_bit.ccfs = new_state;
+}
+
+/**
+  * @brief  enable tmr channel buffer
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR8
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+  tmr_x->ctrl2_bit.cbctrl = new_state;
+}
+
+/**
+  * @brief  select tmr sub-trigger
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9
+  * @param  trigger_select
+  *         this parameter can be one of the following values:
+  *         - TMR_SUB_INPUT_SEL_IS0
+  *         - TMR_SUB_INPUT_SEL_IS1
+  *         - TMR_SUB_INPUT_SEL_IS2
+  *         - TMR_SUB_INPUT_SEL_IS3
+  *         - TMR_SUB_INPUT_SEL_C1INC
+  *         - TMR_SUB_INPUT_SEL_C1DF1
+  *         - TMR_SUB_INPUT_SEL_C2DF2
+  *         - TMR_SUB_INPUT_SEL_EXTIN
+  * @retval none
+  */
+void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select)
+{
+  tmr_x->stctrl_bit.stis = trigger_select;
+}
+
+/**
+  * @brief  set tmr subordinate synchronization mode
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state)
+{
+  tmr_x->stctrl_bit.sts = new_state;
+}
+
+/**
+  * @brief  enable or disable tmr dma request
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  dma_request
+  *         this parameter can be one of the following values:
+  *         - TMR_OVERFLOW_DMA_REQUEST
+  *         - TMR_C1_DMA_REQUEST
+  *         - TMR_C2_DMA_REQUEST
+  *         - TMR_C3_DMA_REQUEST
+  *         - TMR_C4_DMA_REQUEST
+  *         - TMR_HALL_DMA_REQUEST
+  *         - TMR_TRIGGER_DMA_REQUEST
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    tmr_x->iden |= dma_request;
+  }
+  else if(new_state == FALSE)
+  {
+    tmr_x->iden &= ~dma_request;
+  }
+}
+
+/**
+  * @brief  enable or disable tmr interrupt
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_interrupt
+  *         this parameter can be one of the following values:
+  *         - TMR_OVF_INT
+  *         - TMR_C1_INT
+  *         - TMR_C2_INT
+  *         - TMR_C3_INT
+  *         - TMR_C4_INT
+  *         - TMR_HALL_INT
+  *         - TMR_TRIGGER_INT
+  *         - TMR_BRK_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    tmr_x->iden |= tmr_interrupt;
+  }
+  else if(new_state == FALSE)
+  {
+    tmr_x->iden &= ~tmr_interrupt;
+  }
+}
+
+/**
+  * @brief  get tmr flag
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_flag
+  *         this parameter can be one of the following values:
+  *         - TMR_OVF_FLAG
+  *         - TMR_C1_FLAG
+  *         - TMR_C2_FLAG
+  *         - TMR_C3_FLAG
+  *         - TMR_C4_FLAG
+  *         - TMR_HALL_FLAG
+  *         - TMR_TRIGGER_FLAG
+  *         - TMR_BRK_FLAG
+  *         - TMR_C1_RECAPTURE_FLAG
+  *         - TMR_C2_RECAPTURE_FLAG
+  *         - TMR_C3_RECAPTURE_FLAG
+  *         - TMR_C4_RECAPTURE_FLAG
+  * @retval state of tmr flag
+  */
+flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
+{
+  flag_status status = RESET;
+
+  if((tmr_x->ists & tmr_flag) != RESET)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  clear tmr flag
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_flag
+  *         this parameter can be any combination of the following values:
+  *         - TMR_OVF_FLAG
+  *         - TMR_C1_FLAG
+  *         - TMR_C2_FLAG
+  *         - TMR_C3_FLAG
+  *         - TMR_C4_FLAG
+  *         - TMR_HALL_FLAG
+  *         - TMR_TRIGGER_FLAG
+  *         - TMR_BRK_FLAG
+  *         - TMR_C1_RECAPTURE_FLAG
+  *         - TMR_C2_RECAPTURE_FLAG
+  *         - TMR_C3_RECAPTURE_FLAG
+  *         - TMR_C4_RECAPTURE_FLAG
+  * @retval none
+  */
+void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag)
+{
+  tmr_x->ists = ~tmr_flag;
+}
+
+/**
+  * @brief  generate tmr event
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_event
+  *         this parameter can be one of the following values:
+  *         - TMR_OVERFLOW_SWTRIG
+  *         - TMR_C1_SWTRIG
+  *         - TMR_C2_SWTRIG
+  *         - TMR_C3_SWTRIG
+  *         - TMR_C4_SWTRIG
+  *         - TMR_HALL_SWTRIG
+  *         - TMR_TRIGGER_SWTRIG
+  *         - TMR_BRK_SWTRIG
+  * @retval none
+  */
+void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event)
+{
+  tmr_x->swevt |= tmr_event;
+}
+
+/**
+  * @brief  tmr output enable(oen),this function is important for advtm output enable
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR8
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+  tmr_x->brk_bit.oen = new_state;
+}
+
+/**
+  * @brief  set tmr select internal clock
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9
+  * @retval none
+  */
+void tmr_internal_clock_set(tmr_type *tmr_x)
+{
+  tmr_x->stctrl_bit.smsel = TMR_SUB_MODE_DIABLE;
+}
+
+/**
+  * @brief  set tmr output channel polarity
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  *         - TMR_SELECT_CHANNEL_1C
+  *         - TMR_SELECT_CHANNEL_2C
+  *         - TMR_SELECT_CHANNEL_3C
+  * @param  oc_polarity
+  *         this parameter can be one of the following values:
+  *         - TMR_POLARITY_ACTIVE_HIGH
+  *         - TMR_POLARITY_ACTIVE_LOW
+  * @retval none
+  */
+void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
+                                     tmr_polarity_active_type oc_polarity)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cctrl_bit.c1p = (uint32_t)oc_polarity;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cctrl_bit.c2p = (uint32_t)oc_polarity;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cctrl_bit.c3p = (uint32_t)oc_polarity;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cctrl_bit.c4p = (uint32_t)oc_polarity;
+      break;
+
+    case TMR_SELECT_CHANNEL_1C:
+      tmr_x->cctrl_bit.c1cp = (uint32_t)oc_polarity;
+      break;
+
+    case TMR_SELECT_CHANNEL_2C:
+      tmr_x->cctrl_bit.c2cp = (uint32_t)oc_polarity;
+      break;
+
+    case TMR_SELECT_CHANNEL_3C:
+      tmr_x->cctrl_bit.c3cp = (uint32_t)oc_polarity;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  config tmr external clock
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+  * @param  es_divide
+  *         this parameter can be one of the following values:
+  *         - TMR_ES_FREQUENCY_DIV_1
+  *         - TMR_ES_FREQUENCY_DIV_2
+  *         - TMR_ES_FREQUENCY_DIV_4
+  *         - TMR_ES_FREQUENCY_DIV_8
+  * @param  es_polarity
+  *         this parameter can be one of the following values:
+  *         - TMR_ES_POLARITY_NON_INVERTED
+  *         - TMR_ES_POLARITY_INVERTED
+  * @param  es_filter (0x0~0xf)
+  * @retval none
+  */
+void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide,
+                               tmr_external_signal_polarity_type  es_polarity, uint16_t es_filter)
+{
+  tmr_x->stctrl_bit.esdiv = es_divide;
+  tmr_x->stctrl_bit.esp = es_polarity;
+  tmr_x->stctrl_bit.esf = es_filter;
+}
+
+/**
+  * @brief  config tmr external clock mode1
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9
+  * @param  es_divide
+  *         this parameter can be one of the following values:
+  *         - TMR_ES_FREQUENCY_DIV_1
+  *         - TMR_ES_FREQUENCY_DIV_2
+  *         - TMR_ES_FREQUENCY_DIV_4
+  *         - TMR_ES_FREQUENCY_DIV_8
+  * @param  es_polarity
+  *         this parameter can be one of the following values:
+  *         - TMR_ES_POLARITY_NON_INVERTED
+  *         - TMR_ES_POLARITY_INVERTED
+  * @param  es_filter (0x0~0xf)
+  * @retval none
+  */
+void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide,
+                                     tmr_external_signal_polarity_type  es_polarity, uint16_t es_filter)
+{
+  tmr_external_clock_config(tmr_x, es_divide, es_polarity, es_filter);
+  tmr_x->stctrl_bit.smsel = TMR_SUB_EXTERNAL_CLOCK_MODE_A;
+  tmr_x->stctrl_bit.stis = TMR_SUB_INPUT_SEL_EXTIN;
+}
+
+/**
+  * @brief  config tmr external clock mode2
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+  * @param  es_divide
+  *         this parameter can be one of the following values:
+  *         - TMR_ES_FREQUENCY_DIV_1
+  *         - TMR_ES_FREQUENCY_DIV_2
+  *         - TMR_ES_FREQUENCY_DIV_4
+  *         - TMR_ES_FREQUENCY_DIV_8
+  * @param  es_polarity
+  *         this parameter can be one of the following values:
+  *         - TMR_ES_POLARITY_NON_INVERTED
+  *         - TMR_ES_POLARITY_INVERTED
+  * @param  es_filter (0x0~0xf)
+  * @retval none
+  */
+void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide,
+                                     tmr_external_signal_polarity_type  es_polarity, uint16_t es_filter)
+{
+  tmr_external_clock_config(tmr_x, es_divide, es_polarity, es_filter);
+  tmr_x->stctrl_bit.ecmben = TRUE;
+}
+
+/**
+  * @brief  config tmr encoder mode
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+  * @param  encoder_mode
+  *         this parameter can be one of the following values:
+  *         - TMR_ENCODER_MODE_A
+  *         - TMR_ENCODER_MODE_B
+  *         - TMR_ENCODER_MODE_C
+  * @param  ic1_polarity
+  *         this parameter can be one of the following values:
+  *         - TMR_INPUT_RISING_EDGE
+  *         - TMR_INPUT_FALLING_EDGE
+  *         - TMR_INPUT_BOTH_EDGE
+  * @param  ic2_polarity
+  *         this parameter can be one of the following values:
+  *         - TMR_INPUT_RISING_EDGE
+  *         - TMR_INPUT_FALLING_EDGE
+  *         - TMR_INPUT_BOTH_EDGE
+  * @retval none
+  */
+void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type
+                             ic1_polarity, tmr_input_polarity_type ic2_polarity)
+{
+  tmr_x->stctrl_bit.smsel = encoder_mode;
+
+  /* set ic1 polarity */
+  tmr_x->cctrl_bit.c1p =  (ic1_polarity & 0x1);
+  tmr_x->cctrl_bit.c1cp = (ic1_polarity >> 1);
+  /* set ic1 as input channel */
+  tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+
+  /* set ic2 polarity */
+  tmr_x->cctrl_bit.c2p =  (ic2_polarity & 0x1);
+  tmr_x->cctrl_bit.c2cp = (ic2_polarity >> 1);
+  /* set ic2 as input channel */
+  tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+}
+
+/**
+  * @brief  set tmr force output
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+  *         TMR11
+  * @param  tmr_channel
+  *         this parameter can be one of the following values:
+  *         - TMR_SELECT_CHANNEL_1
+  *         - TMR_SELECT_CHANNEL_2
+  *         - TMR_SELECT_CHANNEL_3
+  *         - TMR_SELECT_CHANNEL_4
+  * @param  force_output
+  *         this parameter can be one of the following values:
+  *         - TMR_FORCE_OUTPUT_HIGH
+  *         - TMR_FORCE_OUTPUT_LOW
+  * @retval none
+  */
+void tmr_force_output_set(tmr_type *tmr_x,  tmr_channel_select_type tmr_channel,
+                          tmr_force_output_type force_output)
+{
+  uint16_t channel;
+
+  channel = tmr_channel;
+
+  switch(channel)
+  {
+    case TMR_SELECT_CHANNEL_1:
+      tmr_x->cm1_output_bit.c1octrl = force_output;
+      break;
+
+    case TMR_SELECT_CHANNEL_2:
+      tmr_x->cm1_output_bit.c2octrl = force_output;
+      break;
+
+    case TMR_SELECT_CHANNEL_3:
+      tmr_x->cm2_output_bit.c3octrl = force_output;
+      break;
+
+    case TMR_SELECT_CHANNEL_4:
+      tmr_x->cm2_output_bit.c4octrl = force_output;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  config tmr dma control
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+  * @param  dma_length
+  *         this parameter can be one of the following values:
+  *         - TMR_DMA_TRANSFER_1BYTE
+  *         - TMR_DMA_TRANSFER_2BYTES
+  *         - TMR_DMA_TRANSFER_3BYTES
+  *         ...
+  *         - TMR_DMA_TRANSFER_17BYTES
+  *         - TMR_DMA_TRANSFER_18BYTES
+  * @param  dma_base_address
+  *         this parameter can be one of the following values:
+  *         - TMR_CTRL1_ADDRESS
+  *         - TMR_CTRL2_ADDRESS
+  *         - TMR_STCTRL_ADDRESS
+  *         - TMR_IDEN_ADDRESS
+  *         - TMR_ISTS_ADDRESS
+  *         - TMR_SWEVT_ADDRESS
+  *         - TMR_CM1_ADDRESS
+  *         - TMR_CM2_ADDRESS
+  *         - TMR_CCTRL_ADDRESS
+  *         - TMR_CVAL_ADDRESS
+  *         - TMR_DIV_ADDRESS
+  *         - TMR_PR_ADDRESS
+  *         - TMR_RPR_ADDRESS
+  *         - TMR_C1DT_ADDRESS
+  *         - TMR_C2DT_ADDRESS
+  *         - TMR_C3DT_ADDRESS
+  *         - TMR_C4DT_ADDRESS
+  *         - TMR_BRK_ADDRESS
+  *         - TMR_DMACTRL_ADDRESS
+  * @retval none
+  */
+void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length,
+                            tmr_dma_address_type dma_base_address)
+{
+  tmr_x->dmactrl_bit.dtb = dma_length;
+  tmr_x->dmactrl_bit.addr = dma_base_address;
+}
+
+/**
+  * @brief  config tmr break mode and dead-time
+  * @param  tmr_x: select the tmr peripheral.
+  *         this parameter can be one of the following values:
+  *         TMR1, TMR8
+  * @param  brkdt_struct
+  *         - to the structure of tmr_brkdt_config_type
+  * @retval none
+  */
+void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct)
+{
+  tmr_x->brk_bit.brken = brkdt_struct->brk_enable;
+  tmr_x->brk_bit.dtc = brkdt_struct->deadtime;
+  tmr_x->brk_bit.fcsodis = brkdt_struct->fcsodis_state;
+  tmr_x->brk_bit.fcsoen = brkdt_struct->fcsoen_state;
+  tmr_x->brk_bit.brkv = brkdt_struct->brk_polarity;
+  tmr_x->brk_bit.aoen = brkdt_struct->auto_output_enable;
+  tmr_x->brk_bit.wpc = brkdt_struct->wp_level;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_usart.c

@@ -0,0 +1,624 @@
+/**
+  **************************************************************************
+  * @file     at32f413_usart.c
+  * @brief    contains all the functions for the usart firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup USART
+  * @brief USART driver modules
+  * @{
+  */
+
+#ifdef USART_MODULE_ENABLED
+
+/** @defgroup USART_private_functions
+  * @{
+  */
+
+/**
+  * @brief  deinitialize the usart peripheral registers to their default reset values.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @retval none
+  */
+void usart_reset(usart_type* usart_x)
+{
+  if(usart_x == USART1)
+  {
+    crm_periph_reset(CRM_USART1_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_USART1_PERIPH_RESET, FALSE);
+  }
+  else if(usart_x == USART2)
+  {
+    crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE);
+  }
+#if defined (AT32F413Rx) || defined (AT32F413Cx) || defined (AT32FEBKC8T7)
+  else if(usart_x == USART3)
+  {
+    crm_periph_reset(CRM_USART3_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_USART3_PERIPH_RESET, FALSE);
+  }
+#endif
+#if defined (AT32F413Rx)
+  else if(usart_x == UART4)
+  {
+    crm_periph_reset(CRM_UART4_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_UART4_PERIPH_RESET, FALSE);
+  }
+  else if(usart_x == UART5)
+  {
+    crm_periph_reset(CRM_UART5_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_UART5_PERIPH_RESET, FALSE);
+  }
+#endif
+}
+
+/**
+  * @brief  initialize the usart peripheral according to the specified parameters.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  baud_rate: configure the usart communication baud rate.
+  * @param  data_bit: data bits transmitted or received in a frame
+  *         this parameter can be one of the following values:
+  *         - USART_DATA_8BITS
+  *         - USART_DATA_9BITS.
+  * @param  stop_bit: stop bits transmitted
+  *         this parameter can be one of the following values:
+  *         - USART_STOP_1_BIT
+  *         - USART_STOP_0_5_BIT.
+  *         - USART_STOP_2_BIT
+  *         - USART_STOP_1_5_BIT.
+  * @retval none
+  */
+void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit)
+{
+  crm_clocks_freq_type clocks_freq;
+  uint32_t apb_clock, temp_val;
+  crm_clocks_freq_get(&clocks_freq);
+  if(usart_x == USART1)
+  {
+    apb_clock = clocks_freq.apb2_freq;
+  }
+  else
+  {
+    apb_clock = clocks_freq.apb1_freq;
+  }
+  temp_val = (apb_clock * 10 / baud_rate);
+  if((temp_val % 10) < 5)
+  {
+    temp_val = (temp_val / 10);
+  }
+  else
+  {
+    temp_val = (temp_val / 10) + 1;
+  }
+  usart_x->baudr_bit.div = temp_val;
+  usart_x->ctrl1_bit.dbn = data_bit;
+  usart_x->ctrl2_bit.stopbn = stop_bit;
+}
+
+/**
+  * @brief  usart parity selection config.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  parity: select the none, odd or even parity.
+  *         this parameter can be one of the following values:
+  *         - USART_PARITY_NONE
+  *         - USART_PARITY_EVEN.
+  *         - USART_PARITY_ODD
+  * @retval none
+  */
+void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity)
+{
+  if(parity == USART_PARITY_NONE)
+  {
+    usart_x->ctrl1_bit.psel = FALSE;
+    usart_x->ctrl1_bit.pen = FALSE;
+  }
+  else if(parity == USART_PARITY_EVEN)
+  {
+    usart_x->ctrl1_bit.psel = FALSE;
+    usart_x->ctrl1_bit.pen = TRUE;
+  }
+  else if(parity == USART_PARITY_ODD)
+  {
+    usart_x->ctrl1_bit.psel = TRUE;
+    usart_x->ctrl1_bit.pen = TRUE;
+  }
+}
+
+/**
+  * @brief  enable or disable the specified usart peripheral.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: new state of the usart peripheral.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl1_bit.uen = new_state;
+}
+
+/**
+  * @brief  usart transmitter enable.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: TRUE or FALSE.
+  * @retval none
+  */
+void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl1_bit.ten = new_state;
+}
+
+/**
+  * @brief  usart receiver enable.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: TRUE or FALSE.
+  * @retval none
+  */
+void usart_receiver_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl1_bit.ren = new_state;
+}
+
+/**
+  * @brief  usart clock config.
+  * @note   clock config are not available for UART4 and UART5.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2 or USART3.
+  * @param  clk_pol: polarity of the clock output on the ck pin.
+  *         this parameter can be one of the following values:
+  *         - USART_CLOCK_POLARITY_LOW
+  *         - USART_CLOCK_POLARITY_HIGH
+  * @param  clk_pha: phase of the clock output on the ck pin.
+  *         this parameter can be one of the following values:
+  *         - USART_CLOCK_PHASE_1EDGE
+  *         - USART_CLOCK_PHASE_2EDGE
+  * @param  clk_lb: whether the clock pulse of the last data bit transmitted (MSB) is outputted on the ck pin.
+  *         this parameter can be one of the following values:
+  *         - USART_CLOCK_LAST_BIT_NONE
+  *         - USART_CLOCK_LAST_BIT_OUTPUT
+  * @retval none
+  */
+void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb)
+{
+  usart_x->ctrl2_bit.clkpol = clk_pol;
+  usart_x->ctrl2_bit.clkpha = clk_pha;
+  usart_x->ctrl2_bit.lbcp = clk_lb;
+}
+
+/**
+  * @brief  usart enable the ck pin.
+  * @note   clock enable are not available for UART4 and UART5.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2 or USART3.
+  * @param  new_state: TRUE or FALSE
+  * @retval none
+  */
+void usart_clock_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl2_bit.clken = new_state;
+}
+
+/**
+  * @brief  enable or disable the specified usart interrupts.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  usart_int: specifies the USART interrupt sources to be enabled or disabled.
+  *         this parameter can be one of the following values:
+  *         - USART_IDLE_INT:  idle interrupt
+  *         - USART_RDBF_INT:  rdbf interrupt
+  *         - USART_TDC_INT:   tdc interrupt
+  *         - USART_TDBE_INT:  tdbe interrupt
+  *         - USART_PERR_INT:  perr interrupt
+  *         - USART_BF_INT:    break frame interrupt
+  *         - USART_ERR_INT:   err interrupt
+  *         - USART_CTSCF_INT: ctscf interrupt
+  * @param  new_state: new state of the specified usart interrupts.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state)
+{
+  if(new_state == TRUE)
+    PERIPH_REG((uint32_t)usart_x, usart_int) |= PERIPH_REG_BIT(usart_int);
+  else
+    PERIPH_REG((uint32_t)usart_x, usart_int) &= ~PERIPH_REG_BIT(usart_int);
+}
+
+/**
+  * @brief  enable or disable the usart's dma transmitter interface.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: new state of the dma request sources.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.dmaten = new_state;
+}
+
+/**
+  * @brief  enable or disable the usart's dma receiver interface.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: new state of the dma request sources.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.dmaren = new_state;
+}
+
+/**
+  * @brief  set the wakeup id of the usart.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  usart_id: the matching id(0x0~0xF).
+  * @retval none
+  */
+void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id)
+{
+  usart_x->ctrl2_bit.id = usart_id;
+}
+
+/**
+  * @brief  select the usart wakeup method in multi-processor communication.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  wakeup_mode: determines the way to wake up usart method.
+  *         this parameter can be one of the following values:
+  *         - USART_WAKEUP_BY_IDLE_FRAME
+  *         - USART_WAKEUP_BY_MATCHING_ID
+  * @retval none
+  */
+void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode)
+{
+  usart_x->ctrl1_bit.wum = wakeup_mode;
+}
+
+/**
+  * @brief  config the usart in mute mode in multi-processor communication.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: new state of the usart mute mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl1_bit.rm = new_state;
+}
+
+/**
+  * @brief  set the usart break frame bit num.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  break_bit: specifies the break bit num.
+  *         this parameter can be one of the following values:
+  *         - USART_BREAK_10BITS
+  *         - USART_BREAK_11BITS
+  * @retval none
+  */
+void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit)
+{
+  usart_x->ctrl2_bit.bfbn = break_bit;
+}
+
+/**
+  * @brief  enable or disable the usart lin mode.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: new state of the usart lin mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl2_bit.linen = new_state;
+}
+
+/**
+  * @brief  transmit single data through the usart peripheral.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  data: the data to transmit.
+  * @retval none
+  */
+void usart_data_transmit(usart_type* usart_x, uint16_t data)
+{
+  usart_x->dt = (data & 0x01FF);
+}
+
+/**
+  * @brief  return the most recent received data by the usart peripheral.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @retval the received data.
+  */
+uint16_t usart_data_receive(usart_type* usart_x)
+{
+  return (uint16_t)(usart_x->dt);
+}
+
+/**
+  * @brief  transmit break characters.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @retval none
+  */
+void usart_break_send(usart_type* usart_x)
+{
+  usart_x->ctrl1_bit.sbf = TRUE;
+}
+
+/**
+  * @brief  config the specified usart smartcard guard time.
+  * @note   The guard time bits are not available for UART4 and UART5.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2 or USART3.
+  * @param  guard_time_val: specifies the guard time (0x00~0xFF).
+  * @retval none
+  */
+void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
+{
+  usart_x->gdiv_bit.scgt = guard_time_val;
+}
+
+/**
+  * @brief  config the irda/smartcard division.
+  * @note   the division are not available for UART4 and UART5.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2 or USART3.
+  * @param  div_val: specifies the division.
+  * @retval none
+  */
+void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
+{
+  usart_x->gdiv_bit.isdiv = div_val;
+}
+
+/**
+  * @brief  enable or disable the usart smart card mode.
+  * @note   the smart card mode are not available for UART4 and UART5.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2 or USART3.
+  * @param  new_state: new state of the smart card mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.scmen = new_state;
+}
+
+/**
+  * @brief  enable or disable nack transmission in smartcard mode.
+  * @note   the smart card nack are not available for UART4 and UART5.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2 or USART3.
+  * @param  new_state: new state of the nack transmission.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.scnacken = new_state;
+}
+
+/**
+  * @brief  enable or disable the usart single line bidirectional half-duplex communication.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: new state of the single line half-duplex select.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.slben = new_state;
+}
+
+/**
+  * @brief  enable or disable the usart's irda interface.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *          USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: new state of the irda mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.irdaen = new_state;
+}
+
+/**
+  * @brief  configure the usart's irda low power.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *          USART1, USART2, USART3, UART4 or UART5.
+  * @param  new_state: new state of the irda mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.irdalp = new_state;
+}
+
+/**
+  * @brief  configure the usart's hardware flow control.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2 or USART3
+  * @param  flow_state: specifies the hardware flow control.
+  *         this parameter can be one of the following values:
+  *         - USART_HARDWARE_FLOW_NONE
+  *         - USART_HARDWARE_FLOW_RTS,
+  *         - USART_HARDWARE_FLOW_CTS,
+  *         - USART_HARDWARE_FLOW_RTS_CTS
+  * @retval none
+  */
+void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state)
+{
+  if(flow_state == USART_HARDWARE_FLOW_NONE)
+  {
+    usart_x->ctrl3_bit.rtsen = FALSE;
+    usart_x->ctrl3_bit.ctsen = FALSE;
+  }
+  else if(flow_state == USART_HARDWARE_FLOW_RTS)
+  {
+    usart_x->ctrl3_bit.rtsen = TRUE;
+    usart_x->ctrl3_bit.ctsen = FALSE;
+  }
+  else if(flow_state == USART_HARDWARE_FLOW_CTS)
+  {
+    usart_x->ctrl3_bit.rtsen = FALSE;
+    usart_x->ctrl3_bit.ctsen = TRUE;
+  }
+  else if(flow_state == USART_HARDWARE_FLOW_RTS_CTS)
+  {
+    usart_x->ctrl3_bit.rtsen = TRUE;
+    usart_x->ctrl3_bit.ctsen = TRUE;
+  }
+}
+
+/**
+  * @brief  check whether the specified usart flag is set or not.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  flag: specifies the flag to check.
+  *         this parameter can be one of the following values:
+  *         - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5,USART6,UART7 and UART8)
+  *         - USART_BFF_FLAG:   break frame flag
+  *         - USART_TDBE_FLAG:  transmit data buffer empty flag
+  *         - USART_TDC_FLAG:   transmit data complete flag
+  *         - USART_RDBF_FLAG:  receive data buffer full flag
+  *         - USART_IDLEF_FLAG: idle flag
+  *         - USART_ROERR_FLAG: receiver overflow error flag
+  *         - USART_NERR_FLAG:  noise error flag
+  *         - USART_FERR_FLAG:  framing error flag
+  *         - USART_PERR_FLAG:  parity error flag
+  * @retval the new state of usart_flag (SET or RESET).
+  */
+flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
+{
+  if(usart_x->sts & flag)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  clear the usart's pending flags.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 or UART5.
+  * @param  flag: specifies the flag to clear.
+  *         this parameter can be any combination of the following values:
+  *         - USART_CTSCF_FLAG: (not available for UART4 and UART5).
+  *         - USART_BFF_FLAG:
+  *         - USART_TDC_FLAG:
+  *         - USART_RDBF_FLAG:
+  *         - USART_PERR_FLAG:
+  *         - USART_FERR_FLAG:
+  *         - USART_NERR_FLAG:
+  *         - USART_ROERR_FLAG:
+  *         - USART_IDLEF_FLAG:
+  * @note
+  *         - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software
+  *           sequence: a read operation to usart sts register (usart_flag_get())
+  *           followed by a read operation to usart dt register (usart_data_receive()).
+  *         - USART_RDBF_FLAG can be also cleared by a read to the usart dt register(usart_data_receive()).
+  *         - USART_TDC_FLAG can be also cleared by software sequence: a read operation to usart sts register (usart_flag_get())
+  *           followed by a write operation to usart dt register (usart_data_transmit()).
+  *         - USART_TDBE_FLAG is cleared only by a write to the usart dt register(usart_data_transmit()).
+  * @retval none
+  */
+void usart_flag_clear(usart_type* usart_x, uint32_t flag)
+{
+  if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG))
+  {
+    UNUSED(usart_x->sts);
+    UNUSED(usart_x->dt);
+  }
+  else
+  {
+    usart_x->sts = ~flag;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_usb.c

@@ -0,0 +1,553 @@
+/**
+  **************************************************************************
+  * @file     at32f413_usb.c
+  * @brief    contains the functions for the usb firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup USB
+  * @brief USB driver modules
+  * @{
+  */
+
+#include "at32f413_conf.h"
+
+
+#ifdef USB_MODULE_ENABLED
+
+/** @defgroup USB_private_functions
+  * @{
+  */
+
+/**
+  * @brief usb packet buffer start address
+  */
+#define USB_ENDP_DESC_TABLE_OFFSET       0x40
+uint32_t g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS;
+static uint16_t g_usb_offset_addr = USB_ENDP_DESC_TABLE_OFFSET;
+
+/**
+  * @brief  initialize usb peripheral controller register
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @retval none
+  */
+void usb_dev_init(usbd_type *usbx)
+{
+  /* clear usb core reset */
+  usbx->ctrl_bit.csrst = 0;
+
+  /* clear usb interrupt status */
+  usbx->intsts = 0;
+
+  /* set usb packet buffer descirption table address */
+  usbx->buftbl = USB_BUFFER_TABLE_ADDRESS;
+
+  /* enable usb core and set device address to 0 */
+  usbx->devaddr = 0x80;
+
+  usb_interrupt_enable(usbx, USB_SOF_INT | USB_RST_INT | USB_SP_INT | USB_WK_INT | USB_TC_INT, TRUE);
+}
+
+/**
+  * @brief  connect usb device
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @retval none
+  */
+void usb_connect(usbd_type *usbx)
+{
+  /* enable usb phy */
+  usbx->ctrl_bit.disusb = 0;
+}
+
+/**
+  * @brief  disconnect usb device
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @retval none
+  */
+void usb_disconnect(usbd_type *usbx)
+{
+  /* disable usb phy */
+  usbx->ctrl_bit.disusb = TRUE;
+}
+
+
+/**
+  * @brief  mapping usb packet buffer area
+  *         two mapping intervals are available for packet buffer area,
+  *         and are select by the usbbufs in the crm misc1 register.
+  *         when usbbufs is 0,sram size is 512 bytes, packet buffer start
+  *         address is 0x40006000.when usbbufs is 1, sram size is fixed to
+  *         768~1280 bytes, and the  packet buffer start address is fixed to
+  *         0x40007800,packet buffer size decided by whether can1 and can2 are
+  *         enabled;when both can1 and can2 are disabled, usb packet buffer can be set to the
+  *         maximum of 1280 bytes; when either can1 or can2 is enabled, usb packet buffer can be set to the
+  *         maximum of 1024 bytes; when both CAN1 and CAN2 are enabled, usb packet buffer can be set to the
+  *         maximum of 768 bytes.
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @retval none
+  */
+void usb_usbbufs_enable(usbd_type *usbx, confirm_state state)
+{
+  if(state == TRUE)
+  {
+    /* enable usbbufs */
+    g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS_EX;
+    CRM->misc1_bit.usbbufs = TRUE;
+  }
+  else
+  {
+    /* disable usbbufs */
+    g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS;
+    CRM->misc1_bit.usbbufs = FALSE;
+  }
+}
+
+/**
+  * @brief  open usb endpoint
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @param  ept_info: endpoint information structure
+  * @retval none
+  */
+void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info)
+{
+  uint16_t type = 0;
+
+  /* set endpoint address */
+  USB_SET_EPT_ADDRESS(ept_info->eptn, ept_info->ept_address);
+
+  /* select endpoint transfer type */
+  if(ept_info->trans_type == EPT_CONTROL_TYPE)
+  {
+    type = USB_EPT_CONTROL;
+  }
+  else if(ept_info->trans_type == EPT_BULK_TYPE)
+  {
+    type = USB_EPT_BULK;
+  }
+  else if(ept_info->trans_type == EPT_INT_TYPE)
+  {
+    type = USB_EPT_INT;
+  }
+  else if(ept_info->trans_type == EPT_ISO_TYPE)
+  {
+    type = USB_EPT_ISO;
+    ept_info->is_double_buffer = TRUE;
+  }
+
+  /* configure endpoint transfer type (control, bulk, interrupt, isochronous) */
+  USB_SET_TRANS_TYPE(ept_info->eptn, type);
+
+  /* endpoint is in transfer */
+  if(ept_info->inout == DATA_TRANS_IN)
+  {
+      if(ept_info->is_double_buffer == 0)
+      {
+        /* set in endpoint tx offset address */
+        USB_SET_TX_ADDRESS(ept_info->eptn, ept_info->tx_addr);
+
+        /* clear in endpoint data toggle */
+        USB_CLEAR_TXDTS(ept_info->eptn);
+
+        /* set endpoint transmission status: nak */
+        USB_SET_TXSTS(ept_info->eptn, USB_TX_NAK);
+      }
+      else
+      {
+        /* set double buffer endpoint*/
+        USB_SET_EPT_DOUBLE_BUFFER(ept_info->eptn);
+
+        /* set in endpoint offset address0 and address1 */
+        USB_SET_DOUBLE_BUFF0_ADDRESS(ept_info->eptn, ept_info->tx_addr);
+        USB_SET_DOUBLE_BUFF1_ADDRESS(ept_info->eptn, ept_info->rx_addr);
+
+        /* clear in and out data toggle */
+        USB_CLEAR_TXDTS(ept_info->eptn);
+        USB_CLEAR_RXDTS(ept_info->eptn);
+
+        /* toggle rx data toggle flag */
+        USB_TOGGLE_RXDTS(ept_info->eptn);
+
+        /* set endpoint reception status: disable */
+        USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE);
+
+        /* set endpoint transmision status: nak */
+        USB_SET_TXSTS(ept_info->eptn, USB_TX_NAK);
+      }
+  }
+  else
+  {
+    if(ept_info->is_double_buffer == 0)
+    {
+      /* set out endpoint rx offset address */
+      USB_SET_RX_ADDRESS(ept_info->eptn, ept_info->rx_addr);
+
+      /* clear out endpoint data toggle */
+      USB_CLEAR_RXDTS(ept_info->eptn);
+
+      /* set out endpoint max reception buffer size */
+      USB_SET_RXLEN(ept_info->eptn, ept_info->maxpacket);
+
+      /* set endpoint reception status: valid */
+      USB_SET_RXSTS(ept_info->eptn, USB_RX_VALID);
+    }
+    else
+    {
+      /* set double buffer endpoint */
+      USB_SET_EPT_DOUBLE_BUFFER(ept_info->eptn);
+
+      /* set out endpoint offset address0 and address1 */
+      USB_SET_DOUBLE_BUFF0_ADDRESS(ept_info->eptn, ept_info->tx_addr);
+      USB_SET_DOUBLE_BUFF1_ADDRESS(ept_info->eptn, ept_info->rx_addr);
+
+      /* set out endpoint max reception buffer size */
+      USB_SET_EPT_DOUBLE_BUF0_LEN(ept_info->eptn, ept_info->maxpacket, DATA_TRANS_OUT);
+      USB_SET_EPT_DOUBLE_BUF1_LEN(ept_info->eptn, ept_info->maxpacket, DATA_TRANS_OUT);
+
+      /* clear in and out data toggle */
+      USB_CLEAR_TXDTS(ept_info->eptn);
+      USB_CLEAR_RXDTS(ept_info->eptn);
+
+      /* toggle tx data toggle flag */
+      USB_TOGGLE_TXDTS(ept_info->eptn);
+
+      /* set endpoint reception status: valid */
+      USB_SET_RXSTS(ept_info->eptn, USB_RX_VALID);
+
+      /* set endpoint transmision status: disable */
+      USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE);
+    }
+  }
+}
+
+
+/**
+  * @brief  close usb endpoint
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @param  ept_info: endpoint information structure
+  * @retval none
+  */
+void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info)
+{
+  if(ept_info->is_double_buffer == 0)
+  {
+    if(ept_info->inout == DATA_TRANS_IN)
+    {
+      /*clear tx data toggle */
+      USB_CLEAR_TXDTS(ept_info->eptn);
+
+      /* set tx status: disable */
+      USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE);
+    }
+    else
+    {
+      /*clear rx data toggle */
+      USB_CLEAR_RXDTS(ept_info->eptn);
+
+      /* set rx status: disable */
+      USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE);
+
+    }
+  }
+  else
+  {
+    /* double buffer */
+
+    /*clear rx and tx data toggle */
+    USB_CLEAR_TXDTS(ept_info->eptn);
+    USB_CLEAR_RXDTS(ept_info->eptn);
+
+    if(ept_info->inout == DATA_TRANS_IN)
+    {
+      /* toggle tx */
+      USB_TOGGLE_TXDTS(ept_info->eptn);
+
+      /* set tx and rx status: disable */
+      USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE);
+      USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE);
+    }
+    else
+    {
+      /* toggle rx */
+      USB_TOGGLE_RXDTS(ept_info->eptn);
+
+      /* set tx and rx status: disable */
+      USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE);
+      USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  write data from user memory to usb buffer
+  * @param  pusr_buf: point to user buffer
+  * @param  offset_addr: endpoint tx offset address
+  * @param  nbytes: number of bytes data write to usb buffer
+  * @retval none
+  */
+void usb_write_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes)
+{
+  /* endpoint tx buffer address */
+  __IO uint16_t *d_addr = (__IO uint16_t *)(offset_addr * 2 + g_usb_packet_address);
+
+  uint32_t nhbytes = (nbytes + 1) >> 1;
+  uint32_t n_index;
+  uint16_t *pbuf = (uint16_t *)pusr_buf;
+  for(n_index = 0; n_index < nhbytes; n_index ++)
+  {
+#if defined (__ICCARM__) && (__VER__ < 7000000)
+    *d_addr++  = *(__packed uint16_t *)pbuf;
+#else
+    *d_addr++ = __UNALIGNED_UINT16_READ(pbuf);
+#endif
+    d_addr ++;
+    pbuf ++;
+  }
+}
+
+/**
+  * @brief  read data from usb buffer to user buffer
+  * @param  pusr_buf: point to user buffer
+  * @param  offset_addr: endpoint rx offset address
+  * @param  nbytes: number of bytes data write to usb buffer
+  * @retval none
+  */
+void usb_read_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes)
+{
+  __IO uint16_t *s_addr = (__IO uint16_t *)(offset_addr * 2 + g_usb_packet_address);
+  uint32_t nhbytes = (nbytes + 1) >> 1;
+  uint32_t n_index;
+  uint16_t *pbuf = (uint16_t *)pusr_buf;
+  for(n_index = 0; n_index < nhbytes; n_index ++)
+  {
+#if defined (__ICCARM__) && (__VER__ < 7000000)
+    *(__packed uint16_t *)pbuf = *(__IO uint16_t *)s_addr ++;
+#else
+    __UNALIGNED_UINT16_WRITE(pbuf, *(__IO uint16_t *)s_addr ++);
+#endif
+    s_addr ++;
+    pbuf ++;
+  }
+}
+
+
+/**
+  * @brief  usb interrupt enable
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @param  interrupt:
+  *         this parameter can be any combination of the following values:
+  *         - USB_LSOF_INT
+  *         - USB_SOF_INT
+  *         - USB_RST_INT
+  *         - USB_SP_INT
+  *         - USB_WK_INT
+  *         - USB_BE_INT
+  *         - USB_UCFOR_INT
+  *         - USB_TC_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void usb_interrupt_enable(usbd_type *usbx, uint16_t interrupt, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    usbx->ctrl |= interrupt;
+  }
+  else
+  {
+    usbx->ctrl &= ~interrupt;
+  }
+}
+
+/**
+  * @brief  set the host assignment address
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @param  address: host assignment address
+  * @retval none
+  */
+void usb_set_address(usbd_type *usbx, uint8_t address)
+{
+  usbx->devaddr_bit.addr = address;
+  usbx->devaddr_bit.cen = TRUE;
+}
+
+/**
+  * @brief  set endpoint tx or rx status to stall
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @param  ept_info: endpoint information structure
+  * @retval none
+  */
+void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info)
+{
+  if(ept_info->inout == DATA_TRANS_IN)
+  {
+    USB_SET_TXSTS(ept_info->eptn, USB_TX_STALL)
+  }
+  else
+  {
+    USB_SET_RXSTS(ept_info->eptn, USB_RX_STALL)
+  }
+}
+
+/**
+  * @brief  usb device enter suspend mode
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @retval none
+  */
+void usb_enter_suspend(usbd_type *usbx)
+{
+  usbx->ctrl_bit.ssp = TRUE;
+  usbx->ctrl_bit.lpm = TRUE;
+}
+
+/**
+  * @brief  usb device exit suspend mode
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @retval none
+  */
+void usb_exit_suspend(usbd_type *usbx)
+{
+  usbx->ctrl_bit.ssp = FALSE;
+  usbx->ctrl_bit.lpm = FALSE;
+}
+
+/**
+  * @brief  usb remote wakeup set
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @retval none
+  */
+void usb_remote_wkup_set(usbd_type *usbx)
+{
+   usbx->ctrl_bit.gresume = TRUE;
+}
+
+/**
+  * @brief  usb remote wakeup clear
+  * @param  usbx: to select the usb peripheral.
+  *         parameter as following values: USB
+  * @retval none
+  */
+void usb_remote_wkup_clear(usbd_type *usbx)
+{
+  usbx->ctrl_bit.gresume = FALSE;
+}
+
+/**
+  * @brief  usb auto malloc endpoint buffer
+  * @param  mapacket: endpoint support max packet size
+  * @retval none
+  */
+uint16_t usb_buffer_malloc(uint16_t maxpacket)
+{
+  uint16_t offset = g_usb_offset_addr;
+  g_usb_offset_addr += maxpacket;
+  return offset;
+}
+
+/**
+  * @brief  free usb endpoint buffer
+  * @param  none
+  * @retval none
+  */
+void usb_buffer_free(void)
+{
+  g_usb_offset_addr = USB_ENDP_DESC_TABLE_OFFSET;
+}
+
+/**
+  * @brief  get flag of usb.
+  * @param  usbx: select the usb peripheral
+  * @param  flag: select the usb flag
+  *         this parameter can be one of the following values:
+  *         - USB_INOUT_FLAG
+  *         - USB_LSOF_FLAG
+  *         - USB_SOF_FLAG
+  *         - USB_RST_FLAG
+  *         - USB_SP_FLAG
+  *         - USB_WK_FLAG
+  *         - USB_BE_FLAG
+  *         - USB_UCFOR_FLAG
+  *         - USB_TC_FLAG
+  * @retval none
+  */
+flag_status usb_flag_get(usbd_type *usbx, uint16_t flag)
+{
+  flag_status status = RESET;
+
+  if((usbx->intsts & flag) == RESET)
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+  return status;
+}
+
+/**
+  * @brief  clear flag of usb.
+  * @param  usbx: select the usb peripheral
+  * @param  flag: select the usb flag
+  *         this parameter can be one of the following values:
+  *         - USB_INOUT_FLAG
+  *         - USB_LSOF_FLAG
+  *         - USB_SOF_FLAG
+  *         - USB_RST_FLAG
+  *         - USB_SP_FLAG
+  *         - USB_WK_FLAG
+  *         - USB_BE_FLAG
+  *         - USB_UCFOR_FLAG
+  *         - USB_TC_FLAG
+  * @retval none
+  */
+void usb_flag_clear(usbd_type *usbx, uint16_t flag)
+{
+  usbx->intsts = ~flag;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_wdt.c

@@ -0,0 +1,143 @@
+/**
+  **************************************************************************
+  * @file     at32f413_wdt.c
+  * @brief    contains all the functions for the wdt firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup WDT
+  * @brief WDT driver modules
+  * @{
+  */
+
+#ifdef WDT_MODULE_ENABLED
+
+/** @defgroup WDT_private_functions
+  * @{
+  */
+
+/**
+  * @brief  wdt enable ,the reload value will be sent to the counter
+  * @param  none
+  * @retval none
+  */
+void wdt_enable(void)
+{
+  WDT->cmd = WDT_CMD_ENABLE;
+}
+
+/**
+  * @brief  reload wdt counter
+  * @param  none
+  * @retval none
+  */
+void wdt_counter_reload(void)
+{
+  WDT->cmd = WDT_CMD_RELOAD;
+}
+
+/**
+  * @brief  set wdt counter reload value
+  * @param  reload_value (0x0000~0x0FFF)
+  * @retval none
+  */
+void wdt_reload_value_set(uint16_t reload_value)
+{
+  WDT->rld = reload_value;
+}
+
+/**
+  * @brief  set wdt division divider
+  * @param  division
+  *         this parameter can be one of the following values:
+  *         - WDT_CLK_DIV_4
+  *         - WDT_CLK_DIV_8
+  *         - WDT_CLK_DIV_16
+  *         - WDT_CLK_DIV_32
+  *         - WDT_CLK_DIV_64
+  *         - WDT_CLK_DIV_128
+  *         - WDT_CLK_DIV_256
+  * @retval none
+  */
+void wdt_divider_set(wdt_division_type division)
+{
+  WDT->div_bit.div = division;
+}
+
+/**
+  * @brief  enable or disable wdt cmd register write
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void wdt_register_write_enable( confirm_state new_state)
+{
+  if(new_state == FALSE)
+  {
+    WDT->cmd = WDT_CMD_LOCK;
+  }
+  else
+  {
+    WDT->cmd = WDT_CMD_UNLOCK;
+  }
+}
+
+/**
+  * @brief  get wdt flag
+  * @param  wdt_flag
+  *         this parameter can be one of the following values:
+  *         - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
+  *         - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
+  * @retval state of wdt flag
+  */
+flag_status wdt_flag_get(uint16_t wdt_flag)
+{
+  flag_status status = RESET;
+
+  if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/AT32F41x_Drivers/src/at32f413_wwdt.c

@@ -0,0 +1,139 @@
+/**
+  **************************************************************************
+  * @file     at32f413_wwdt.c
+  * @brief    contains all the functions for the wwdt firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f413_conf.h"
+
+/** @addtogroup AT32F413_periph_driver
+  * @{
+  */
+
+/** @defgroup WWDT
+  * @brief WWDT driver modules
+  * @{
+  */
+
+#ifdef WWDT_MODULE_ENABLED
+
+/** @defgroup WWDT_private_functions
+  * @{
+  */
+
+/**
+  * @brief  wwdt reset by crm reset register
+  * @retval none
+  */
+void wwdt_reset(void)
+{
+  crm_periph_reset(CRM_WWDT_PERIPH_RESET, TRUE);
+  crm_periph_reset(CRM_WWDT_PERIPH_RESET, FALSE);
+}
+
+/**
+  * @brief  wwdt division set
+  * @param  division
+  *         this parameter can be one of the following values:
+  *         - WWDT_PCLK1_DIV_4096        (wwdt counter clock = (pclk1/4096)/1)
+  *         - WWDT_PCLK1_DIV_8192        (wwdt counter clock = (pclk1/4096)/2)
+  *         - WWDT_PCLK1_DIV_16384       (wwdt counter clock = (pclk1/4096)/4)
+  *         - WWDT_PCLK1_DIV_32768       (wwdt counter clock = (pclk1/4096)/8)
+  * @retval none
+  */
+void wwdt_divider_set(wwdt_division_type division)
+{
+  WWDT->cfg_bit.div = division;
+}
+
+/**
+  * @brief  wwdt reload counter interrupt flag clear
+  * @param  none
+  * @retval none
+  */
+void wwdt_flag_clear(void)
+{
+  WWDT->sts = 0;
+}
+
+/**
+  * @brief  wwdt enable and the counter value load
+  * @param  wwdt_cnt (0x40~0x7f)
+  * @retval none
+  */
+void wwdt_enable(uint8_t wwdt_cnt)
+{
+  WWDT->ctrl = wwdt_cnt | WWDT_EN_BIT;
+}
+
+/**
+  * @brief  wwdt reload counter interrupt enable
+  * @param  none
+  * @retval none
+  */
+void wwdt_interrupt_enable(void)
+{
+  WWDT->cfg_bit.rldien = TRUE;
+}
+
+/**
+  * @brief  wwdt reload counter interrupt flag get
+  * @param  none
+  * @retval state of reload counter interrupt flag
+  */
+flag_status wwdt_flag_get(void)
+{
+  return (flag_status)WWDT->sts_bit.rldf;
+}
+
+/**
+  * @brief  wwdt counter value set
+  * @param  wwdt_cnt (0x40~0x7f)
+  * @retval none
+  */
+void wwdt_counter_set(uint8_t wwdt_cnt)
+{
+  WWDT->ctrl_bit.cnt = wwdt_cnt;
+}
+
+/**
+  * @brief  wwdt window counter value set
+  * @param  window_cnt (0x40~0x7f)
+  * @retval none
+  */
+void wwdt_window_counter_set(uint8_t window_cnt)
+{
+  WWDT->cfg_bit.win = window_cnt;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Librarys/CMSIS/AT32/at32f413.h

@@ -0,0 +1,396 @@
+/**
+  **************************************************************************
+  * @file     at32f413.h
+  * @brief    at32f413 header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#ifndef __AT32F413_H
+#define __AT32F413_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__CC_ARM)
+ #pragma anon_unions
+#endif
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup AT32F413
+  * @{
+  */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * tip: to avoid modifying this file each time you need to switch between these
+  *      devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined (AT32F413KBU7_4) && !defined (AT32F413KCU7_4) && !defined (AT32F413CBU7) && \
+    !defined (AT32F413CCU7)   && !defined (AT32F413C8T7)   && !defined (AT32F413CBT7) && \
+    !defined (AT32F413CCT7)   && !defined (AT32F413RBT7)   && !defined (AT32F413RCT7) && \
+    !defined (AT32FEBKC8T7)   && !defined (AT32F413TBU7)
+
+    #error "Please select first the target device used in your application (in at32f413.h file)"
+#endif
+
+#if defined (AT32F413KBU7_4) || defined (AT32F413KCU7_4) || defined (AT32F413CBU7) || \
+    defined (AT32F413CCU7)   || defined (AT32F413C8T7)   || defined (AT32F413CBT7) || \
+    defined (AT32F413CCT7)   || defined (AT32F413RBT7)   || defined (AT32F413RCT7) || \
+    defined (AT32FEBKC8T7)   || defined (AT32F413TBU7)
+
+    #define AT32F413xx
+#endif
+
+#if defined (AT32F413RBT7)   || defined (AT32F413RCT7)
+
+    #define AT32F413Rx
+#endif
+
+#if defined (AT32F413CBU7)   || defined (AT32F413CCU7)   || defined (AT32F413C8T7) || \
+    defined (AT32F413CBT7)   || defined (AT32F413CCT7)
+
+    #define AT32F413Cx
+#endif
+
+#if defined (AT32F413KBU7_4) || defined (AT32F413KCU7_4)
+
+    #define AT32F413Kx
+#endif
+
+#ifndef USE_STDPERIPH_DRIVER
+/**
+  * @brief comment the line below if you will not use the peripherals drivers.
+  * in this case, these drivers will not be included and the application code will
+  * be based on direct access to peripherals registers
+  */
+  #ifdef _RTE_
+    #include "RTE_Components.h"
+    #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
+      #define USE_STDPERIPH_DRIVER
+    #endif
+  #endif
+#endif
+
+/**
+  * @brief at32f413 standard peripheral library version number
+  */
+#define __AT32F413_LIBRARY_VERSION_MAJOR    (0x02) /*!< [31:24] major version */
+#define __AT32F413_LIBRARY_VERSION_MIDDLE   (0x00) /*!< [23:16] middle version */
+#define __AT32F413_LIBRARY_VERSION_MINOR    (0x09) /*!< [15:8]  minor version */
+#define __AT32F413_LIBRARY_VERSION_RC       (0x00) /*!< [7:0]  release candidate */
+#define __AT32F413_LIBRARY_VERSION          ((__AT32F413_LIBRARY_VERSION_MAJOR << 24)  | \
+                                             (__AT32F413_LIBRARY_VERSION_MIDDLE << 16) | \
+                                             (__AT32F413_LIBRARY_VERSION_MINOR << 8)   | \
+                                             (__AT32F413_LIBRARY_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief configuration of the cortex-m4 processor and core peripherals
+  */
+#define __CM4_REV                 0x0001U  /*!< core revision r0p1                           */
+#define __MPU_PRESENT             1        /*!< mpu present                                  */
+#define __NVIC_PRIO_BITS          4        /*!< at32 uses 4 bits for the priority levels     */
+#define __Vendor_SysTickConfig    0        /*!< set to 1 if different systick config is used */
+#define __FPU_PRESENT             1U       /*!< fpu present                                  */
+
+/**
+  * @brief at32f413 interrupt number definition, according to the selected device
+  *        in @ref Library_configuration_section
+  */
+typedef enum IRQn
+{
+    /******  cortex-m4 processor exceptions numbers ***************************************************/
+    Reset_IRQn                  = -15,    /*!< 1 reset vector, invoked on power up and warm reset   */
+    NonMaskableInt_IRQn         = -14,    /*!< 2 non maskable interrupt                             */
+    HardFault_IRQn              = -13,    /*!< 3 hard fault, all classes of fault                   */
+    MemoryManagement_IRQn       = -12,    /*!< 4 cortex-m4 memory management interrupt              */
+    BusFault_IRQn               = -11,    /*!< 5 cortex-m4 bus fault interrupt                      */
+    UsageFault_IRQn             = -10,    /*!< 6 cortex-m4 usage fault interrupt                    */
+    SVCall_IRQn                 = -5,     /*!< 11 cortex-m4 sv call interrupt                       */
+    DebugMonitor_IRQn           = -4,     /*!< 12 cortex-m4 debug monitor interrupt                 */
+    PendSV_IRQn                 = -2,     /*!< 14 cortex-m4 pend sv interrupt                       */
+    SysTick_IRQn                = -1,     /*!< 15 cortex-m4 system tick interrupt                   */
+
+    /******  at32 specific interrupt numbers *********************************************************/
+    WWDT_IRQn                   = 0,      /*!< window watchdog timer interrupt                      */
+    PVM_IRQn                    = 1,      /*!< pvm through exint line detection interrupt           */
+    TAMPER_IRQn                 = 2,      /*!< tamper interrupt                                     */
+    RTC_IRQn                    = 3,      /*!< rtc global interrupt                                 */
+    FLASH_IRQn                  = 4,      /*!< flash global interrupt                               */
+    CRM_IRQn                    = 5,      /*!< crm global interrupt                                 */
+    EXINT0_IRQn                 = 6,      /*!< external line0 interrupt                             */
+    EXINT1_IRQn                 = 7,      /*!< external line1 interrupt                             */
+    EXINT2_IRQn                 = 8,      /*!< external line2 interrupt                             */
+    EXINT3_IRQn                 = 9,      /*!< external line3 interrupt                             */
+    EXINT4_IRQn                 = 10,     /*!< external line4 interrupt                             */
+    DMA1_Channel1_IRQn          = 11,     /*!< dma1 channel 1 global interrupt                      */
+    DMA1_Channel2_IRQn          = 12,     /*!< dma1 channel 2 global interrupt                      */
+    DMA1_Channel3_IRQn          = 13,     /*!< dma1 channel 3 global interrupt                      */
+    DMA1_Channel4_IRQn          = 14,     /*!< dma1 channel 4 global interrupt                      */
+    DMA1_Channel5_IRQn          = 15,     /*!< dma1 channel 5 global interrupt                      */
+    DMA1_Channel6_IRQn          = 16,     /*!< dma1 channel 6 global interrupt                      */
+    DMA1_Channel7_IRQn          = 17,     /*!< dma1 channel 7 global interrupt                      */
+
+    ADC1_2_IRQn                 = 18,     /*!< adc1 and adc2 global interrupt                       */
+    USBFS_H_CAN1_TX_IRQn        = 19,     /*!< usb device high priority or can1 tx interrupts       */
+    USBFS_L_CAN1_RX0_IRQn       = 20,     /*!< usb device low priority or can1 rx0 interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< can1 rx1 interrupt                                   */
+    CAN1_SE_IRQn                = 22,     /*!< can1 se interrupt                                    */
+    EXINT9_5_IRQn               = 23,     /*!< external line[9:5] interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< tmr1 brake interrupt                                 */
+    TMR1_OVF_TMR10_IRQn         = 25,     /*!< tmr1 overflow interrupt                              */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< tmr1 trigger and hall interrupt                      */
+    TMR1_CH_IRQn                = 27,     /*!< tmr1 channel interrupt                               */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< tmr2 global interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< tmr3 global interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< tmr4 global interrupt                                */
+    I2C1_EVT_IRQn               = 31,     /*!< i2c1 event interrupt                                 */
+    I2C1_ERR_IRQn               = 32,     /*!< i2c1 error interrupt                                 */
+    I2C2_EVT_IRQn               = 33,     /*!< i2c2 event interrupt                                 */
+    I2C2_ERR_IRQn               = 34,     /*!< i2c2 error interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< spi1 global interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< spi2 global interrupt                                */
+    USART1_IRQn                 = 37,     /*!< usart1 global interrupt                              */
+    USART2_IRQn                 = 38,     /*!< usart2 global interrupt                              */
+    USART3_IRQn                 = 39,     /*!< usart3 global interrupt                              */
+    EXINT15_10_IRQn             = 40,     /*!< external line[15:10] interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< rtc alarm through exint line interrupt               */
+    USBFSWakeUp_IRQn            = 42,     /*!< usb device wakeup from suspend through exint line interrupt */
+    TMR8_BRK_IRQn               = 43,     /*!< tmr8 brake interrupt                                 */
+    TMR8_OVF_IRQn               = 44,     /*!< tmr8 overflow interrupt                              */
+    TMR8_TRG_HALL_IRQn          = 45,     /*!< tmr8 trigger and hall interrupt                      */
+    TMR8_CH_IRQn                = 46,     /*!< tmr8 channel interrupt                               */
+    SDIO1_IRQn                  = 49,     /*!< sdio1 global interrupt                               */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< tmr5 global interrupt                                */
+    UART4_IRQn                  = 52,     /*!< uart4 global interrupt                               */
+    UART5_IRQn                  = 53,     /*!< uart5 global interrupt                               */
+    DMA2_Channel1_IRQn          = 56,     /*!< dma2 channel 1 global interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< dma2 channel 2 global interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< dma2 channel 3 global interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< dma2 channel 4 and channel 5 global interrupt        */
+    CAN2_TX_IRQn                = 68,     /*!< can2 tx interrupt                                    */
+    CAN2_RX0_IRQn               = 69,     /*!< can2 rx0 interrupt                                   */
+    CAN2_RX1_IRQn               = 70,     /*!< can2 rx1 interrupt                                   */
+    CAN2_SE_IRQn                = 71,     /*!< can2 se interrupt                                    */
+    ACC_IRQn                    = 72,     /*!< acc interrupt                                        */
+    USBFS_MAPH_IRQn             = 73,     /*!< usb map hp interrupt                                 */
+    USBFS_MAPL_IRQn             = 74,     /*!< usb map lp interrupt                                 */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< dma2 channel 6 and channel 7 global interrupt        */
+
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"
+#include "system_at32f413.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */
+
+typedef int32_t  INT32;
+typedef int16_t  INT16;
+typedef int8_t   INT8;
+typedef uint32_t UINT32;
+typedef uint16_t UINT16;
+typedef uint8_t  UINT8;
+
+typedef int32_t  s32;
+typedef int16_t  s16;
+typedef int8_t   s8;
+
+typedef const int32_t sc32;   /*!< read only */
+typedef const int16_t sc16;   /*!< read only */
+typedef const int8_t  sc8;    /*!< read only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;    /*!< read only */
+typedef __I int16_t vsc16;    /*!< read only */
+typedef __I int8_t  vsc8;     /*!< read only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< read only */
+typedef const uint16_t uc16;  /*!< read only */
+typedef const uint8_t  uc8;   /*!< read only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;   /*!< read only */
+typedef __I uint16_t vuc16;   /*!< read only */
+typedef __I uint8_t  vuc8;    /*!< read only */
+
+/**
+  * @brief flag status
+  */
+typedef enum {RESET = 0, SET = !RESET} flag_status;
+
+/**
+  * @brief confirm state
+  */
+typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
+
+/**
+  * @brief error status
+  */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define REG8(addr)                       *(volatile uint8_t *)(addr)
+#define REG16(addr)                      *(volatile uint16_t *)(addr)
+#define REG32(addr)                      *(volatile uint32_t *)(addr)
+
+#define MAKE_VALUE(reg_offset, bit_num)  (uint32_t)(((reg_offset) << 16) | (bit_num & 0x1F))
+
+#define PERIPH_REG(periph_base, value)   REG32((periph_base + (value >> 16)))
+#define PERIPH_REG_BIT(value)            (0x1U << (value & 0x1F))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE                       ((uint32_t)0x08000000)
+#define SPIM_FLASH_BASE                  ((uint32_t)0x08400000)
+#define USD_BASE                         ((uint32_t)0x1FFFF800)
+#define SRAM_BASE                        ((uint32_t)0x20000000)
+#define PERIPH_BASE                      ((uint32_t)0x40000000)
+#define XMC_REG_BASE                     ((uint32_t)0xA0000000)
+#define DEBUG_BASE                       ((uint32_t)0xE0042000)
+
+#define APB1PERIPH_BASE                  (PERIPH_BASE + 0x00000)
+#define APB2PERIPH_BASE                  (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE                   (PERIPH_BASE + 0x20000)
+
+/* apb1 bus base address */
+#define TMR2_BASE                        (APB1PERIPH_BASE + 0x0000)
+#define TMR3_BASE                        (APB1PERIPH_BASE + 0x0400)
+#define TMR4_BASE                        (APB1PERIPH_BASE + 0x0800)
+#define TMR5_BASE                        (APB1PERIPH_BASE + 0x0C00)
+#define RTC_BASE                         (APB1PERIPH_BASE + 0x2800)
+#define WWDT_BASE                        (APB1PERIPH_BASE + 0x2C00)
+#define WDT_BASE                         (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE                        (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE                      (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE                      (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE                       (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE                       (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE                        (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE                        (APB1PERIPH_BASE + 0x5800)
+#define USBFS_BASE                       (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE                        (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE                        (APB1PERIPH_BASE + 0x6800)
+#define BPR_BASE                         (APB1PERIPH_BASE + 0x6C00)
+#define PWC_BASE                         (APB1PERIPH_BASE + 0x7000)
+/* apb2 bus base address */
+#define IOMUX_BASE                       (APB2PERIPH_BASE + 0x0000)
+#define EXINT_BASE                       (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE                       (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE                       (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE                       (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE                       (APB2PERIPH_BASE + 0x1400)
+#define GPIOF_BASE                       (APB2PERIPH_BASE + 0x1C00)
+#define ADC1_BASE                        (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE                        (APB2PERIPH_BASE + 0x2800)
+#define TMR1_BASE                        (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE                        (APB2PERIPH_BASE + 0x3000)
+#define TMR8_BASE                        (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE                      (APB2PERIPH_BASE + 0x3800)
+#define TMR9_BASE                        (APB2PERIPH_BASE + 0x4C00)
+#define TMR10_BASE                       (APB2PERIPH_BASE + 0x5000)
+#define TMR11_BASE                       (APB2PERIPH_BASE + 0x5400)
+#define ACC_BASE                         (APB2PERIPH_BASE + 0x5800)
+#define SDIO1_BASE                       (APB2PERIPH_BASE + 0x8000)
+/* ahb bus base address */
+#define DMA1_BASE                        (AHBPERIPH_BASE + 0x0000)
+#define DMA1_CHANNEL1_BASE               (AHBPERIPH_BASE + 0x0008)
+#define DMA1_CHANNEL2_BASE               (AHBPERIPH_BASE + 0x001C)
+#define DMA1_CHANNEL3_BASE               (AHBPERIPH_BASE + 0x0030)
+#define DMA1_CHANNEL4_BASE               (AHBPERIPH_BASE + 0x0044)
+#define DMA1_CHANNEL5_BASE               (AHBPERIPH_BASE + 0x0058)
+#define DMA1_CHANNEL6_BASE               (AHBPERIPH_BASE + 0x006C)
+#define DMA1_CHANNEL7_BASE               (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE                        (AHBPERIPH_BASE + 0x0400)
+#define DMA2_CHANNEL1_BASE               (AHBPERIPH_BASE + 0x0408)
+#define DMA2_CHANNEL2_BASE               (AHBPERIPH_BASE + 0x041C)
+#define DMA2_CHANNEL3_BASE               (AHBPERIPH_BASE + 0x0430)
+#define DMA2_CHANNEL4_BASE               (AHBPERIPH_BASE + 0x0444)
+#define DMA2_CHANNEL5_BASE               (AHBPERIPH_BASE + 0x0458)
+#define DMA2_CHANNEL6_BASE               (AHBPERIPH_BASE + 0x046C)
+#define DMA2_CHANNEL7_BASE               (AHBPERIPH_BASE + 0x0480)
+#define CRM_BASE                         (AHBPERIPH_BASE + 0x1000)
+#define FLASH_REG_BASE                   (AHBPERIPH_BASE + 0x2000)
+#define CRC_BASE                         (AHBPERIPH_BASE + 0x3000)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#include "at32f413_def.h"
+#include "at32f413_conf.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Librarys/CMSIS/AT32/at32f413_conf_template.h

@@ -0,0 +1,150 @@
+/**
+  **************************************************************************
+  * @file     at32f413_conf.h
+  * @brief    at32f413 config header file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F413_CONF_H
+#define __AT32F413_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+  * @brief in the following line adjust the value of high speed exernal crystal (hext)
+  * used in your application
+  * tip: to avoid modifying this file each time you need to use different hext, you
+  *      can define the hext value in your toolchain compiler preprocessor.
+  */
+#if !defined  HEXT_VALUE
+#define HEXT_VALUE               ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */
+#endif
+
+/**
+  * @brief in the following line adjust the high speed exernal crystal (hext) startup
+  * timeout value
+  */
+#define HEXT_STARTUP_TIMEOUT             ((uint16_t)0x3000)  /*!< time out for hext start up */
+#define HICK_VALUE                       ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
+#define LEXT_VALUE                       ((uint32_t)32768)   /*!< value of the low speed exernal clock in hz */
+
+/* module define -------------------------------------------------------------*/
+#define CRM_MODULE_ENABLED
+#define TMR_MODULE_ENABLED
+#define RTC_MODULE_ENABLED
+#define BPR_MODULE_ENABLED
+#define GPIO_MODULE_ENABLED
+#define I2C_MODULE_ENABLED
+#define USART_MODULE_ENABLED
+#define PWC_MODULE_ENABLED
+#define CAN_MODULE_ENABLED
+#define ADC_MODULE_ENABLED
+#define SPI_MODULE_ENABLED
+#define DMA_MODULE_ENABLED
+#define DEBUG_MODULE_ENABLED
+#define FLASH_MODULE_ENABLED
+#define CRC_MODULE_ENABLED
+#define WWDT_MODULE_ENABLED
+#define WDT_MODULE_ENABLED
+#define EXINT_MODULE_ENABLED
+#define SDIO_MODULE_ENABLED
+#define USB_MODULE_ENABLED
+#define ACC_MODULE_ENABLED
+#define MISC_MODULE_ENABLED
+
+/* includes ------------------------------------------------------------------*/
+#ifdef CRM_MODULE_ENABLED
+#include "at32f413_crm.h"
+#endif
+#ifdef TMR_MODULE_ENABLED
+#include "at32f413_tmr.h"
+#endif
+#ifdef RTC_MODULE_ENABLED
+#include "at32f413_rtc.h"
+#endif
+#ifdef BPR_MODULE_ENABLED
+#include "at32f413_bpr.h"
+#endif
+#ifdef GPIO_MODULE_ENABLED
+#include "at32f413_gpio.h"
+#endif
+#ifdef I2C_MODULE_ENABLED
+#include "at32f413_i2c.h"
+#endif
+#ifdef USART_MODULE_ENABLED
+#include "at32f413_usart.h"
+#endif
+#ifdef PWC_MODULE_ENABLED
+#include "at32f413_pwc.h"
+#endif
+#ifdef CAN_MODULE_ENABLED
+#include "at32f413_can.h"
+#endif
+#ifdef ADC_MODULE_ENABLED
+#include "at32f413_adc.h"
+#endif
+#ifdef SPI_MODULE_ENABLED
+#include "at32f413_spi.h"
+#endif
+#ifdef DMA_MODULE_ENABLED
+#include "at32f413_dma.h"
+#endif
+#ifdef DEBUG_MODULE_ENABLED
+#include "at32f413_debug.h"
+#endif
+#ifdef FLASH_MODULE_ENABLED
+#include "at32f413_flash.h"
+#endif
+#ifdef CRC_MODULE_ENABLED
+#include "at32f413_crc.h"
+#endif
+#ifdef WWDT_MODULE_ENABLED
+#include "at32f413_wwdt.h"
+#endif
+#ifdef WDT_MODULE_ENABLED
+#include "at32f413_wdt.h"
+#endif
+#ifdef EXINT_MODULE_ENABLED
+#include "at32f413_exint.h"
+#endif
+#ifdef SDIO_MODULE_ENABLED
+#include "at32f413_sdio.h"
+#endif
+#ifdef ACC_MODULE_ENABLED
+#include "at32f413_acc.h"
+#endif
+#ifdef MISC_MODULE_ENABLED
+#include "at32f413_misc.h"
+#endif
+#ifdef USB_MODULE_ENABLED
+#include "at32f413_usb.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F413_CONF_H */
+
+

Librarys/CMSIS/AT32/startup/gcc/linker/AT32F413x8_FLASH.ld

@@ -0,0 +1,168 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F413x8_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F413x8 Device with
+**                64KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+SPIM (rx)       : ORIGIN = 0x08400000, LENGTH = 16384K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  _spim_init_base = LOADADDR(.spim);
+  _spim_init_length = SIZEOF(.spim);
+  
+  .spim :
+  {
+    . = ALIGN(4);
+    _spim_start = .;        /* create a global symbol at spim start */
+    *(.spim)                /* .spim sections */
+    *(.spim*)               /* .spim* sections */
+    . = ALIGN(4);
+    _spim_end = .;         /* define a global symbols at end of spim */
+  } >SPIM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

Librarys/CMSIS/AT32/startup/gcc/linker/AT32F413xB_FLASH.ld

@@ -0,0 +1,168 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F413xB_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F413xB Device with
+**                128KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+SPIM (rx)       : ORIGIN = 0x08400000, LENGTH = 16384K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  _spim_init_base = LOADADDR(.spim);
+  _spim_init_length = SIZEOF(.spim);
+  
+  .spim :
+  {
+    . = ALIGN(4);
+    _spim_start = .;        /* create a global symbol at spim start */
+    *(.spim)                /* .spim sections */
+    *(.spim*)               /* .spim* sections */
+    . = ALIGN(4);
+    _spim_end = .;         /* define a global symbols at end of spim */
+  } >SPIM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

Librarys/CMSIS/AT32/startup/gcc/linker/AT32F413xC_FLASH.ld

@@ -0,0 +1,168 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F413xC_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F413xC Device with
+**                256KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+SPIM (rx)       : ORIGIN = 0x08400000, LENGTH = 16384K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  _spim_init_base = LOADADDR(.spim);
+  _spim_init_length = SIZEOF(.spim);
+  
+  .spim :
+  {
+    . = ALIGN(4);
+    _spim_start = .;        /* create a global symbol at spim start */
+    *(.spim)                /* .spim sections */
+    *(.spim*)               /* .spim* sections */
+    . = ALIGN(4);
+    _spim_end = .;         /* define a global symbols at end of spim */
+  } >SPIM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

Librarys/CMSIS/AT32/startup/gcc/startup_at32f413.s

@@ -0,0 +1,431 @@
+/**
+  ******************************************************************************
+  * @file     startup_at32f413.s
+  * @brief    at32f413xx devices vector table for gcc toolchain.
+  *           this module performs:
+  *           - set the initial sp
+  *           - set the initial pc == reset_handler,
+  *           - set the vector table entries with the exceptions isr address
+  *           - configure the clock system and the external sram to
+  *             be used as data memory (optional, to be enabled by user)
+  *           - branches to main in the c library (which eventually
+  *             calls main()).
+  *           after reset the cortex-m4 processor is in thread mode,
+  *           priority is privileged, and the stack is set to main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word  WWDT_IRQHandler                     /* Window Watchdog Timer                   */
+  .word  PVM_IRQHandler                      /* PVM through EXINT Line detect           */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  CRM_IRQHandler                      /* CRM                                     */
+  .word  EXINT0_IRQHandler                   /* EXINT Line 0                            */
+  .word  EXINT1_IRQHandler                   /* EXINT Line 1                            */
+  .word  EXINT2_IRQHandler                   /* EXINT Line 2                            */
+  .word  EXINT3_IRQHandler                   /* EXINT Line 3                            */
+  .word  EXINT4_IRQHandler                   /* EXINT Line 4                            */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USBFS_H_CAN1_TX_IRQHandler          /* USB High Priority or CAN1 TX            */
+  .word  USBFS_L_CAN1_RX0_IRQHandler         /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SE_IRQHandler                  /* CAN1 SE                                 */
+  .word  EXINT9_5_IRQHandler                 /* EXINT Line [9:5]                        */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Brake and TMR9                     */
+  .word  TMR1_OVF_TMR10_IRQHandler           /* TMR1 Overflow and TMR10                 */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and hall and TMR11         */
+  .word  TMR1_CH_IRQHandler                  /* TMR1 Channel                            */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EVT_IRQHandler                 /* I2C1 Event                              */
+  .word  I2C1_ERR_IRQHandler                 /* I2C1 Error                              */
+  .word  I2C2_EVT_IRQHandler                 /* I2C2 Event                              */
+  .word  I2C2_ERR_IRQHandler                 /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* Reserved                                */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXINT15_10_IRQHandler               /* EXINT Line [15:10]                      */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXINT Line            */
+  .word  USBFSWakeUp_IRQHandler              /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_IRQHandler                 /* TMR8 Brake                              */
+  .word  TMR8_OVF_IRQHandler                 /* TMR8 Overflow                           */
+  .word  TMR8_TRG_HALL_IRQHandler            /* TMR8 Trigger and hall                   */
+  .word  TMR8_CH_IRQHandler                  /* TMR8 Channel                            */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  0                                   /* Reserved                                */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SE_IRQHandler                  /* CAN2 SE                                 */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USBFS_MAPH_IRQHandler               /* USB Map HP                              */
+  .word  USBFS_MAPL_IRQHandler               /* USB Map LP                              */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDT_IRQHandler
+   .thumb_set WWDT_IRQHandler,Default_Handler
+
+   .weak      PVM_IRQHandler
+   .thumb_set PVM_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      CRM_IRQHandler
+   .thumb_set CRM_IRQHandler,Default_Handler
+
+   .weak      EXINT0_IRQHandler
+   .thumb_set EXINT0_IRQHandler,Default_Handler
+
+   .weak      EXINT1_IRQHandler
+   .thumb_set EXINT1_IRQHandler,Default_Handler
+
+   .weak      EXINT2_IRQHandler
+   .thumb_set EXINT2_IRQHandler,Default_Handler
+
+   .weak      EXINT3_IRQHandler
+   .thumb_set EXINT3_IRQHandler,Default_Handler
+
+   .weak      EXINT4_IRQHandler
+   .thumb_set EXINT4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USBFS_H_CAN1_TX_IRQHandler
+   .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USBFS_L_CAN1_RX0_IRQHandler
+   .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SE_IRQHandler
+   .thumb_set CAN1_SE_IRQHandler,Default_Handler
+
+   .weak      EXINT9_5_IRQHandler
+   .thumb_set EXINT9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OVF_TMR10_IRQHandler
+   .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CH_IRQHandler
+   .thumb_set TMR1_CH_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EVT_IRQHandler
+   .thumb_set I2C1_EVT_IRQHandler,Default_Handler
+
+   .weak      I2C1_ERR_IRQHandler
+   .thumb_set I2C1_ERR_IRQHandler,Default_Handler
+
+   .weak      I2C2_EVT_IRQHandler
+   .thumb_set I2C2_EVT_IRQHandler,Default_Handler
+
+   .weak      I2C2_ERR_IRQHandler
+   .thumb_set I2C2_ERR_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXINT15_10_IRQHandler
+   .thumb_set EXINT15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBFSWakeUp_IRQHandler
+   .thumb_set USBFSWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_IRQHandler
+   .thumb_set TMR8_BRK_IRQHandler,Default_Handler
+
+   .weak      TMR8_OVF_IRQHandler
+   .thumb_set TMR8_OVF_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_IRQHandler
+   .thumb_set TMR8_TRG_HALL_IRQHandler,Default_Handler
+
+   .weak      TMR8_CH_IRQHandler
+   .thumb_set TMR8_CH_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SE_IRQHandler
+   .thumb_set CAN2_SE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USBFS_MAPH_IRQHandler
+   .thumb_set USBFS_MAPH_IRQHandler,Default_Handler
+
+   .weak      USBFS_MAPL_IRQHandler
+   .thumb_set USBFS_MAPL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler

Librarys/CMSIS/AT32/startup/iar/linker/AT32F413x8.icf

@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

Librarys/CMSIS/AT32/startup/iar/linker/AT32F413xB.icf

@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

Librarys/CMSIS/AT32/startup/iar/linker/AT32F413xC.icf

@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

Librarys/CMSIS/AT32/startup/iar/startup_at32f413.s

@@ -0,0 +1,496 @@
+;**************************************************************************
+;* @file     startup_at32f413.s
+;* @brief    at32f413 startup file for IAR Systems
+;**************************************************************************
+;
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                       ; Reset Handler
+        DCD     NMI_Handler                         ; NMI Handler
+        DCD     HardFault_Handler                   ; Hard Fault Handler
+        DCD     MemManage_Handler                   ; MPU Fault Handler
+        DCD     BusFault_Handler                    ; Bus Fault Handler
+        DCD     UsageFault_Handler                  ; Usage Fault Handler
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     SVC_Handler                         ; SVCall Handler
+        DCD     DebugMon_Handler                    ; Debug Monitor Handler
+        DCD     0                                   ; Reserved
+        DCD     PendSV_Handler                      ; PendSV Handler
+        DCD     SysTick_Handler                     ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDT_IRQHandler                     ; Window Watchdog Timer
+        DCD     PVM_IRQHandler                      ; PVM through EXINT Line detect
+        DCD     TAMPER_IRQHandler                   ; Tamper
+        DCD     RTC_IRQHandler                      ; RTC
+        DCD     FLASH_IRQHandler                    ; Flash
+        DCD     CRM_IRQHandler                      ; CRM
+        DCD     EXINT0_IRQHandler                   ; EXINT Line 0
+        DCD     EXINT1_IRQHandler                   ; EXINT Line 1
+        DCD     EXINT2_IRQHandler                   ; EXINT Line 2
+        DCD     EXINT3_IRQHandler                   ; EXINT Line 3
+        DCD     EXINT4_IRQHandler                   ; EXINT Line 4
+        DCD     DMA1_Channel1_IRQHandler            ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler            ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler            ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler            ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler            ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler            ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler            ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                   ; ADC1 & ADC2
+        DCD     USBFS_H_CAN1_TX_IRQHandler          ; USB High Priority or CAN1 TX
+        DCD     USBFS_L_CAN1_RX0_IRQHandler         ; USB Low  Priority or CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler                 ; CAN1 RX1
+        DCD     CAN1_SE_IRQHandler                  ; CAN1 SE
+        DCD     EXINT9_5_IRQHandler                 ; EXINT Line [9:5]
+        DCD     TMR1_BRK_TMR9_IRQHandler            ; TMR1 Brake and TMR9
+        DCD     TMR1_OVF_TMR10_IRQHandler           ; TMR1 Overflow and TMR10
+        DCD     TMR1_TRG_HALL_TMR11_IRQHandler      ; TMR1 Trigger and hall and TMR11
+        DCD     TMR1_CH_IRQHandler                  ; TMR1 Channel
+        DCD     TMR2_GLOBAL_IRQHandler              ; TMR2
+        DCD     TMR3_GLOBAL_IRQHandler              ; TMR3
+        DCD     TMR4_GLOBAL_IRQHandler              ; TMR4
+        DCD     I2C1_EVT_IRQHandler                 ; I2C1 Event
+        DCD     I2C1_ERR_IRQHandler                 ; I2C1 Error
+        DCD     I2C2_EVT_IRQHandler                 ; I2C2 Event
+        DCD     I2C2_ERR_IRQHandler                 ; I2C2 Error
+        DCD     SPI1_IRQHandler                     ; SPI1
+        DCD     SPI2_IRQHandler                     ; SPI2
+        DCD     USART1_IRQHandler                   ; USART1
+        DCD     USART2_IRQHandler                   ; USART2
+        DCD     USART3_IRQHandler                   ; USART3
+        DCD     EXINT15_10_IRQHandler               ; EXINT Line [15:10]
+        DCD     RTCAlarm_IRQHandler                 ; RTC Alarm through EXINT Line
+        DCD     USBFSWakeUp_IRQHandler              ; USB Wakeup from suspend
+        DCD     TMR8_BRK_IRQHandler                 ; TMR8 Brake
+        DCD     TMR8_OVF_IRQHandler                 ; TMR8 Overflow
+        DCD     TMR8_TRG_HALL_IRQHandler            ; TMR8 Trigger and hall
+        DCD     TMR8_CH_IRQHandler                  ; TMR8 Channel
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     SDIO1_IRQHandler                    ; SDIO1
+        DCD     TMR5_GLOBAL_IRQHandler              ; TMR5
+        DCD     0                                   ; Reserved
+        DCD     UART4_IRQHandler                    ; UART4
+        DCD     UART5_IRQHandler                    ; UART5
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     DMA2_Channel1_IRQHandler            ; DMA2 Channel1
+        DCD     DMA2_Channel2_IRQHandler            ; DMA2 Channel2
+        DCD     DMA2_Channel3_IRQHandler            ; DMA2 Channel3
+        DCD     DMA2_Channel4_5_IRQHandler          ; DMA2 Channel4 & Channel5
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     CAN2_TX_IRQHandler                  ; CAN2 TX
+        DCD     CAN2_RX0_IRQHandler                 ; CAN2 RX0
+        DCD     CAN2_RX1_IRQHandler                 ; CAN2 RX1
+        DCD     CAN2_SE_IRQHandler                  ; CAN2 SE
+        DCD     ACC_IRQHandler                      ; ACC
+        DCD     USBFS_MAPH_IRQHandler               ; USB Map HP
+        DCD     USBFS_MAPL_IRQHandler               ; USB Map LP
+        DCD     DMA2_Channel6_7_IRQHandler          ; DMA2 Channel6 & Channel7
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WWDT_IRQHandler
+        B WWDT_IRQHandler
+
+        PUBWEAK PVM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PVM_IRQHandler
+        B PVM_IRQHandler
+
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK CRM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CRM_IRQHandler
+        B CRM_IRQHandler
+
+        PUBWEAK EXINT0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT0_IRQHandler
+        B EXINT0_IRQHandler
+
+        PUBWEAK EXINT1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT1_IRQHandler
+        B EXINT1_IRQHandler
+
+        PUBWEAK EXINT2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT2_IRQHandler
+        B EXINT2_IRQHandler
+
+        PUBWEAK EXINT3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT3_IRQHandler
+        B EXINT3_IRQHandler
+
+        PUBWEAK EXINT4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT4_IRQHandler
+        B EXINT4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK USBFS_H_CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBFS_H_CAN1_TX_IRQHandler
+        B USBFS_H_CAN1_TX_IRQHandler
+
+        PUBWEAK USBFS_L_CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBFS_L_CAN1_RX0_IRQHandler
+        B USBFS_L_CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_SE_IRQHandler
+        B CAN1_SE_IRQHandler
+
+        PUBWEAK EXINT9_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT9_5_IRQHandler
+        B EXINT9_5_IRQHandler
+
+        PUBWEAK TMR1_BRK_TMR9_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_BRK_TMR9_IRQHandler
+        B TMR1_BRK_TMR9_IRQHandler
+
+        PUBWEAK TMR1_OVF_TMR10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_OVF_TMR10_IRQHandler
+        B TMR1_OVF_TMR10_IRQHandler
+
+        PUBWEAK TMR1_TRG_HALL_TMR11_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_TRG_HALL_TMR11_IRQHandler
+        B TMR1_TRG_HALL_TMR11_IRQHandler
+
+        PUBWEAK TMR1_CH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_CH_IRQHandler
+        B TMR1_CH_IRQHandler
+
+        PUBWEAK TMR2_GLOBAL_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_GLOBAL_IRQHandler
+        B TMR2_GLOBAL_IRQHandler
+
+        PUBWEAK TMR3_GLOBAL_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR3_GLOBAL_IRQHandler
+        B TMR3_GLOBAL_IRQHandler
+
+        PUBWEAK TMR4_GLOBAL_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR4_GLOBAL_IRQHandler
+        B TMR4_GLOBAL_IRQHandler
+
+        PUBWEAK I2C1_EVT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EVT_IRQHandler
+        B I2C1_EVT_IRQHandler
+
+        PUBWEAK I2C1_ERR_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ERR_IRQHandler
+        B I2C1_ERR_IRQHandler
+
+        PUBWEAK I2C2_EVT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EVT_IRQHandler
+        B I2C2_EVT_IRQHandler
+
+        PUBWEAK I2C2_ERR_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ERR_IRQHandler
+        B I2C2_ERR_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXINT15_10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT15_10_IRQHandler
+        B EXINT15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK USBFSWakeUp_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBFSWakeUp_IRQHandler
+        B USBFSWakeUp_IRQHandler
+
+        PUBWEAK TMR8_BRK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_BRK_IRQHandler
+        B TMR8_BRK_IRQHandler
+
+        PUBWEAK TMR8_OVF_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_OVF_IRQHandler
+        B TMR8_OVF_IRQHandler
+
+        PUBWEAK TMR8_TRG_HALL_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_TRG_HALL_IRQHandler
+        B TMR8_TRG_HALL_IRQHandler
+
+        PUBWEAK TMR8_CH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_CH_IRQHandler
+        B TMR8_CH_IRQHandler
+
+        PUBWEAK SDIO1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SDIO1_IRQHandler
+        B SDIO1_IRQHandler
+
+        PUBWEAK TMR5_GLOBAL_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR5_GLOBAL_IRQHandler
+        B TMR5_GLOBAL_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel4_5_IRQHandler
+        B DMA2_Channel4_5_IRQHandler
+
+        PUBWEAK CAN2_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_TX_IRQHandler
+        B CAN2_TX_IRQHandler
+
+        PUBWEAK CAN2_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX0_IRQHandler
+        B CAN2_RX0_IRQHandler
+
+        PUBWEAK CAN2_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX1_IRQHandler
+        B CAN2_RX1_IRQHandler
+
+        PUBWEAK CAN2_SE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_SE_IRQHandler
+        B CAN2_SE_IRQHandler
+
+        PUBWEAK ACC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ACC_IRQHandler
+        B ACC_IRQHandler
+
+        PUBWEAK USBFS_MAPH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBFS_MAPH_IRQHandler
+        B USBFS_MAPH_IRQHandler
+
+        PUBWEAK USBFS_MAPL_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBFS_MAPL_IRQHandler
+        B USBFS_MAPL_IRQHandler
+
+        PUBWEAK DMA2_Channel6_7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel6_7_IRQHandler
+        B DMA2_Channel6_7_IRQHandler
+
+        END

Librarys/CMSIS/AT32/startup/mdk/startup_at32f413.s

@@ -0,0 +1,357 @@
+;**************************************************************************
+;* @file     startup_at32f403a_407.s
+;* @brief    at32f403a_407 startup file for keil
+;* <<< Use Configuration Wizard in Context Menu >>>  
+;**************************************************************************
+;
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                        ; Top of Stack
+                DCD     Reset_Handler                       ; Reset Handler
+                DCD     NMI_Handler                         ; NMI Handler
+                DCD     HardFault_Handler                   ; Hard Fault Handler
+                DCD     MemManage_Handler                   ; MPU Fault Handler
+                DCD     BusFault_Handler                    ; Bus Fault Handler
+                DCD     UsageFault_Handler                  ; Usage Fault Handler
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     SVC_Handler                         ; SVCall Handler
+                DCD     DebugMon_Handler                    ; Debug Monitor Handler
+                DCD     0                                   ; Reserved
+                DCD     PendSV_Handler                      ; PendSV Handler
+                DCD     SysTick_Handler                     ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDT_IRQHandler                     ; Window Watchdog Timer
+                DCD     PVM_IRQHandler                      ; PVM through EXINT Line detect
+                DCD     TAMPER_IRQHandler                   ; Tamper
+                DCD     RTC_IRQHandler                      ; RTC
+                DCD     FLASH_IRQHandler                    ; Flash
+                DCD     CRM_IRQHandler                      ; CRM
+                DCD     EXINT0_IRQHandler                   ; EXINT Line 0
+                DCD     EXINT1_IRQHandler                   ; EXINT Line 1
+                DCD     EXINT2_IRQHandler                   ; EXINT Line 2
+                DCD     EXINT3_IRQHandler                   ; EXINT Line 3
+                DCD     EXINT4_IRQHandler                   ; EXINT Line 4
+                DCD     DMA1_Channel1_IRQHandler            ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler            ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler            ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler            ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler            ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler            ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler            ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                   ; ADC1 & ADC2
+                DCD     USBFS_H_CAN1_TX_IRQHandler          ; USB High Priority or CAN1 TX
+                DCD     USBFS_L_CAN1_RX0_IRQHandler         ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler                 ; CAN1 RX1
+                DCD     CAN1_SE_IRQHandler                  ; CAN1 SE
+                DCD     EXINT9_5_IRQHandler                 ; EXINT Line [9:5]
+                DCD     TMR1_BRK_TMR9_IRQHandler            ; TMR1 Brake and TMR9
+                DCD     TMR1_OVF_TMR10_IRQHandler           ; TMR1 overflow and TMR10
+                DCD     TMR1_TRG_HALL_TMR11_IRQHandler      ; TMR1 Trigger and hall and TMR11
+                DCD     TMR1_CH_IRQHandler                  ; TMR1 channel
+                DCD     TMR2_GLOBAL_IRQHandler              ; TMR2
+                DCD     TMR3_GLOBAL_IRQHandler              ; TMR3
+                DCD     TMR4_GLOBAL_IRQHandler              ; TMR4
+                DCD     I2C1_EVT_IRQHandler                 ; I2C1 Event
+                DCD     I2C1_ERR_IRQHandler                 ; I2C1 Error
+                DCD     I2C2_EVT_IRQHandler                 ; I2C2 Event
+                DCD     I2C2_ERR_IRQHandler                 ; I2C2 Error
+                DCD     SPI1_IRQHandler                     ; SPI1
+                DCD     SPI2_IRQHandler                     ; SPI2
+                DCD     USART1_IRQHandler                   ; USART1
+                DCD     USART2_IRQHandler                   ; USART2
+                DCD     USART3_IRQHandler                   ; USART3
+                DCD     EXINT15_10_IRQHandler               ; EXINT Line [15:10]
+                DCD     RTCAlarm_IRQHandler                 ; RTC Alarm through EXINT Line
+                DCD     USBFSWakeUp_IRQHandler              ; USB Wakeup from suspend
+                DCD     TMR8_BRK_IRQHandler                 ; TMR8 Brake
+                DCD     TMR8_OVF_IRQHandler                 ; TMR8 overflow
+                DCD     TMR8_TRG_HALL_IRQHandler            ; TMR8 Trigger and hall
+                DCD     TMR8_CH_IRQHandler                  ; TMR8 channel
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     SDIO1_IRQHandler                    ; SDIO1
+                DCD     TMR5_GLOBAL_IRQHandler              ; TMR5
+                DCD     0                                   ; Reserved
+                DCD     UART4_IRQHandler                    ; UART4
+                DCD     UART5_IRQHandler                    ; UART5
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     DMA2_Channel1_IRQHandler            ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler            ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler            ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler          ; DMA2 Channel4 & Channel5
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     0                                   ; Reserved
+                DCD     CAN2_TX_IRQHandler                  ; CAN2 TX
+                DCD     CAN2_RX0_IRQHandler                 ; CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler                 ; CAN2 RX1
+                DCD     CAN2_SE_IRQHandler                  ; CAN2 SE
+                DCD     ACC_IRQHandler                      ; ACC
+                DCD     USBFS_MAPH_IRQHandler               ; USB Map High
+                DCD     USBFS_MAPL_IRQHandler               ; USB Map Low
+                DCD     DMA2_Channel6_7_IRQHandler          ; DMA2 Channel6 & Channel7
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler                       [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                         [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                   [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                   [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                    [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler                  [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                         [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                      [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                     [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDT_IRQHandler                     [WEAK]
+                EXPORT  PVM_IRQHandler                      [WEAK]
+                EXPORT  TAMPER_IRQHandler                   [WEAK]
+                EXPORT  RTC_IRQHandler                      [WEAK]
+                EXPORT  FLASH_IRQHandler                    [WEAK]
+                EXPORT  CRM_IRQHandler                      [WEAK]
+                EXPORT  EXINT0_IRQHandler                   [WEAK]
+                EXPORT  EXINT1_IRQHandler                   [WEAK]
+                EXPORT  EXINT2_IRQHandler                   [WEAK]
+                EXPORT  EXINT3_IRQHandler                   [WEAK]
+                EXPORT  EXINT4_IRQHandler                   [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler            [WEAK]
+                EXPORT  ADC1_2_IRQHandler                   [WEAK]
+                EXPORT  USBFS_H_CAN1_TX_IRQHandler          [WEAK]
+                EXPORT  USBFS_L_CAN1_RX0_IRQHandler         [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler                 [WEAK]
+                EXPORT  CAN1_SE_IRQHandler                  [WEAK]
+                EXPORT  EXINT9_5_IRQHandler                 [WEAK]
+                EXPORT  TMR1_BRK_TMR9_IRQHandler            [WEAK]
+                EXPORT  TMR1_OVF_TMR10_IRQHandler           [WEAK]
+                EXPORT  TMR1_TRG_HALL_TMR11_IRQHandler      [WEAK]
+                EXPORT  TMR1_CH_IRQHandler                  [WEAK]
+                EXPORT  TMR2_GLOBAL_IRQHandler              [WEAK]
+                EXPORT  TMR3_GLOBAL_IRQHandler              [WEAK]
+                EXPORT  TMR4_GLOBAL_IRQHandler              [WEAK]
+                EXPORT  I2C1_EVT_IRQHandler                 [WEAK]
+                EXPORT  I2C1_ERR_IRQHandler                 [WEAK]
+                EXPORT  I2C2_EVT_IRQHandler                 [WEAK]
+                EXPORT  I2C2_ERR_IRQHandler                 [WEAK]
+                EXPORT  SPI1_IRQHandler                     [WEAK]
+                EXPORT  SPI2_IRQHandler                     [WEAK]
+                EXPORT  USART1_IRQHandler                   [WEAK]
+                EXPORT  USART2_IRQHandler                   [WEAK]
+                EXPORT  USART3_IRQHandler                   [WEAK]
+                EXPORT  EXINT15_10_IRQHandler               [WEAK]
+                EXPORT  RTCAlarm_IRQHandler                 [WEAK]
+                EXPORT  USBFSWakeUp_IRQHandler              [WEAK]
+                EXPORT  TMR8_BRK_IRQHandler                 [WEAK]
+                EXPORT  TMR8_OVF_IRQHandler                 [WEAK]
+                EXPORT  TMR8_TRG_HALL_IRQHandler            [WEAK]
+                EXPORT  TMR8_CH_IRQHandler                  [WEAK]
+                EXPORT  SDIO1_IRQHandler                    [WEAK]
+                EXPORT  TMR5_GLOBAL_IRQHandler              [WEAK]
+                EXPORT  UART4_IRQHandler                    [WEAK]
+                EXPORT  UART5_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler            [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler            [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler            [WEAK]
+                EXPORT  DMA2_Channel4_5_IRQHandler          [WEAK]
+                EXPORT  CAN2_TX_IRQHandler                  [WEAK]
+                EXPORT  CAN2_RX0_IRQHandler                 [WEAK]
+                EXPORT  CAN2_RX1_IRQHandler                 [WEAK]
+                EXPORT  CAN2_SE_IRQHandler                  [WEAK]
+                EXPORT  ACC_IRQHandler                      [WEAK]
+                EXPORT  USBFS_MAPH_IRQHandler               [WEAK]
+                EXPORT  USBFS_MAPL_IRQHandler               [WEAK]
+                EXPORT  DMA2_Channel6_7_IRQHandler          [WEAK]
+
+WWDT_IRQHandler
+PVM_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+CRM_IRQHandler
+EXINT0_IRQHandler
+EXINT1_IRQHandler
+EXINT2_IRQHandler
+EXINT3_IRQHandler
+EXINT4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USBFS_H_CAN1_TX_IRQHandler
+USBFS_L_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SE_IRQHandler
+EXINT9_5_IRQHandler
+TMR1_BRK_TMR9_IRQHandler
+TMR1_OVF_TMR10_IRQHandler
+TMR1_TRG_HALL_TMR11_IRQHandler
+TMR1_CH_IRQHandler
+TMR2_GLOBAL_IRQHandler
+TMR3_GLOBAL_IRQHandler
+TMR4_GLOBAL_IRQHandler
+I2C1_EVT_IRQHandler
+I2C1_ERR_IRQHandler
+I2C2_EVT_IRQHandler
+I2C2_ERR_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXINT15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBFSWakeUp_IRQHandler
+TMR8_BRK_IRQHandler
+TMR8_OVF_IRQHandler
+TMR8_TRG_HALL_IRQHandler
+TMR8_CH_IRQHandler
+SDIO1_IRQHandler
+TMR5_GLOBAL_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SE_IRQHandler
+ACC_IRQHandler
+USBFS_MAPH_IRQHandler
+USBFS_MAPL_IRQHandler
+DMA2_Channel6_7_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, = Heap_Mem
+                 LDR     R1, = (Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END

Librarys/CMSIS/AT32/system_at32f413.c

@@ -0,0 +1,189 @@
+/**
+  **************************************************************************
+  * @file     system_at32f413.c
+  * @brief    contains all the functions for cmsis cortex-m4 system source file
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup AT32F413_system
+  * @{
+  */
+
+#include "at32f413.h"
+
+/** @addtogroup AT32F413_system_private_defines
+  * @{
+  */
+#define VECT_TAB_OFFSET                  0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup AT32F413_system_private_variables
+  * @{
+  */
+unsigned int system_core_clock           = HICK_VALUE; /*!< system clock frequency (core clock) */
+/**
+  * @}
+  */
+
+/** @addtogroup AT32F413_system_private_functions
+  * @{
+  */
+
+/**
+  * @brief  setup the microcontroller system
+  *         initialize the flash interface.
+  * @note   this function should be used only after reset.
+  * @param  none
+  * @retval none
+  */
+void SystemInit (void)
+{
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U * 2U) |         /* set cp10 full access */
+                 (3U << 11U * 2U)  );       /* set cp11 full access */
+#endif
+
+  /* reset the crm clock configuration to the default reset state(for debug purpose) */
+  /* set hicken bit */
+  CRM->ctrl_bit.hicken = TRUE;
+
+  /* wait hick stable */
+  while(CRM->ctrl_bit.hickstbl != SET);
+
+  /* hick used as system clock */
+  CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
+
+  /* wait sclk switch status */
+  while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
+
+  /* reset hexten, hextbyps, cfden and pllen bits */
+  CRM->ctrl &= ~(0x010D0000U);
+
+  /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
+     clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
+  CRM->cfg = 0;
+
+  /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
+  CRM->misc1 = 0;
+
+  /* disable all interrupts enable and clear pending bits  */
+  CRM->clkint = 0x009F0000;
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE  | VECT_TAB_OFFSET;  /* vector table relocation in internal sram. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;  /* vector table relocation in internal flash. */
+#endif
+}
+
+/**
+  * @brief  update system_core_clock variable according to clock register values.
+  *         the system_core_clock variable contains the core clock (hclk), it can
+  *         be used by the user application to setup the systick timer or configure
+  *         other parameters.
+  * @param  none
+  * @retval none
+  */
+void system_core_clock_update(void)
+{
+  uint32_t pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
+  crm_sclk_type sclk_source;
+
+  static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+  /* get sclk source */
+  sclk_source = crm_sysclk_switch_status_get();
+
+  switch(sclk_source)
+  {
+    case CRM_SCLK_HICK:
+      if(((CRM->misc3_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
+        system_core_clock = HICK_VALUE * 6;
+      else
+        system_core_clock = HICK_VALUE;
+      break;
+    case CRM_SCLK_HEXT:
+      system_core_clock = HEXT_VALUE;
+      break;
+    case CRM_SCLK_PLL:
+      pll_clock_source = CRM->cfg_bit.pllrcs;
+      {
+        /* get multiplication factor */
+        pll_mult = CRM->cfg_bit.pllmult_l;
+        pll_mult_h = CRM->cfg_bit.pllmult_h;
+        /* process high bits */
+        if((pll_mult_h != 0U) || (pll_mult == 15U)){
+            pll_mult += ((16U * pll_mult_h) + 1U);
+        }
+        else
+        {
+            pll_mult += 2U;
+        }
+
+        if (pll_clock_source == 0x00)
+        {
+          /* hick divided by 2 selected as pll clock entry */
+          system_core_clock = (HICK_VALUE >> 1) * pll_mult;
+        }
+        else
+        {
+          /* hext selected as pll clock entry */
+          if (CRM->cfg_bit.pllhextdiv != RESET)
+          {
+            /* hext clock divided by 2 */
+            system_core_clock = (HEXT_VALUE / 2) * pll_mult;
+          }
+          else
+          {
+            system_core_clock = HEXT_VALUE * pll_mult;
+          }
+        }
+      }
+      break;
+    default:
+      system_core_clock = HICK_VALUE;
+      break;
+  }
+
+  /* compute sclk, ahbclk frequency */
+  /* get ahb division */
+  temp = CRM->cfg_bit.ahbdiv;
+  div_value = sys_ahb_div_table[temp];
+  /* ahbclk frequency */
+  system_core_clock = system_core_clock >> div_value;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

Librarys/CMSIS/AT32/system_at32f413.h

@@ -0,0 +1,85 @@
+/**
+  **************************************************************************
+  * @file     system_at32f413.h
+  * @brief    cmsis cortex-m4 system header file.
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#ifndef __SYSTEM_AT32F413_H
+#define __SYSTEM_AT32F413_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup AT32F413_system
+  * @{
+  */
+
+/** @defgroup AT32F413_system_clock_stable_definition
+  * @{
+  */
+
+#define HEXT_STABLE_DELAY                (5000u)
+#define PLL_STABLE_DELAY                 (500u)
+#define SystemCoreClock                  system_core_clock
+
+/**
+  * @}
+  */
+
+/** @defgroup AT32F413_system_exported_variables
+  * @{
+  */
+
+extern unsigned int system_core_clock; /*!< system clock frequency (core clock) */
+
+/**
+  * @}
+  */
+
+/** @defgroup AT32F413_system_exported_functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void system_core_clock_update(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif