|
@@ -11,7 +11,7 @@
|
|
|
#define ADC01_NUM 7
|
|
#define ADC01_NUM 7
|
|
|
#define ADC2_NUM 0
|
|
#define ADC2_NUM 0
|
|
|
#else
|
|
#else
|
|
|
-#define ADC01_NUM 5
|
|
|
|
|
|
|
+#define ADC01_NUM (5)
|
|
|
#define ADC2_NUM 4
|
|
#define ADC2_NUM 4
|
|
|
#endif
|
|
#endif
|
|
|
#define REG_CHAN_NUM (ADC01_NUM + ADC2_NUM)
|
|
#define REG_CHAN_NUM (ADC01_NUM + ADC2_NUM)
|
|
@@ -186,8 +186,6 @@ static void adc1_init(void){
|
|
|
|
|
|
|
|
#ifdef MC100_HW_V1
|
|
#ifdef MC100_HW_V1
|
|
|
static void adc2_init(void){
|
|
static void adc2_init(void){
|
|
|
- /* config ADC clock */
|
|
|
|
|
- rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV4); //APB2 clk 120M, adc clk 30M
|
|
|
|
|
|
|
|
|
|
rcu_periph_clock_enable(RCU_ADC2);
|
|
rcu_periph_clock_enable(RCU_ADC2);
|
|
|
|
|
|
|
@@ -199,9 +197,6 @@ static void adc2_init(void){
|
|
|
/* configure ADC data alignment */
|
|
/* configure ADC data alignment */
|
|
|
adc_data_alignment_config(ADC2, ADC_DATAALIGN_RIGHT);
|
|
adc_data_alignment_config(ADC2, ADC_DATAALIGN_RIGHT);
|
|
|
|
|
|
|
|
- adc_oversample_mode_config(ADC2, ADC_OVERSAMPLING_ALL_CONVERT, ADC_OVERSAMPLING_SHIFT_1B, ADC_OVERSAMPLING_RATIO_MUL2);
|
|
|
|
|
- adc_oversample_mode_enable(ADC2);
|
|
|
|
|
-
|
|
|
|
|
#ifdef REG_CHAN_DMA
|
|
#ifdef REG_CHAN_DMA
|
|
|
/* configure ADC regular channel */
|
|
/* configure ADC regular channel */
|
|
|
adc_channel_length_config(ADC2, ADC_REGULAR_CHANNEL, ADC2_NUM);
|
|
adc_channel_length_config(ADC2, ADC_REGULAR_CHANNEL, ADC2_NUM);
|