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@@ -0,0 +1,472 @@
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+#include "uart.h"
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+#include "libs/os.h"
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+#include "libs/task.h"
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+#include "libs/crc16.h"
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+#include "libs/logger.h"
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+
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+#define SHARK_UART_BAUDRATE 38400
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+
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+#define SHARK_UART0_com UART3
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+#define SHARK_UART0_tx_port GPIOB
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+#define SHARK_UART0_tx_pin GPIO_PIN_10
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+#define SHARK_UART0_rx_port GPIOB
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+#define SHARK_UART0_rx_pin GPIO_PIN_11
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+#define SHARK_UART0_irq UART3_IRQn
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+#define SHARK_UART0_clk RCU_USART0
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+#define SHARK_UART0_tx_gpio_clk RCU_GPIOB
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+#define SHARK_UART0_rx_gpio_clk RCU_GPIOB
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+#define SHARK_UART0_tx_dma DMA1
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+#define SHARK_UART0_tx_dma_ch DMA_CH4
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+#define SHARK_UART0_tx_dma_clk RCU_DMA1
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+#define SHARK_UART0_rx_dma DMA1
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+#define SHARK_UART0_rx_dma_ch DMA_CH2
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+#define SHARK_UART0_rx_dma_clk RCU_DMA1
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+
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+
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+// ================================================================================
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+#define ENABLE_RX_DMA 1
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+#define UART_NUM 1
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+static u8 shark_uart0_tx_cache[SHARK_UART_TX_MEM_SIZE];
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+#if UART_NUM==2
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+static u8 shark_uart1_tx_cache[SHARK_UART_TX_MEM_SIZE];
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+#endif
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+
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+static u8 shark_uart0_rx_cache[SHARK_UART_RX_MEM_SIZE];
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+#if UART_NUM==2
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+static u8 shark_uart1_rx_cache[SHARK_UART_RX_MEM_SIZE];
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+#endif
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+
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+static shark_uart_t _shark_uart[1];
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+static task_t _uart_task;
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+///static bool uart_no_data = false;
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+#if ENABLE_RX_DMA==1
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+#define update_dma_w_pos(uart) circle_update_write_position(&uart->rx_queue, SHARK_UART_RX_MEM_SIZE - DMA_CHCNT(SHARK_UART0_rx_dma, uart->rx_dma_ch))
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+#else
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+#define update_dma_w_pos(uart){}
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+#endif
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+
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+// ================================================================================
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+static uart_enum_t _uart_index(uint32_t com){
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+ return com == SHARK_UART0_com?SHARK_UART0:SHARK_UART1;
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+}
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+static bool shark_uart_on_rx_frame(shark_uart_t *uart)
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+{
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+ u16 crc0 = DECODE_U16(uart->rx_frame + uart->rx_length);
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+ u16 crc1 = crc16_get(uart->rx_frame, uart->rx_length);
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+
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+ if (crc0 != crc1) {
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+ return false;
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+ }
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+ //protocol_recv_frame(_uart_index(uart->uart_com), (char *)uart->rx_frame, uart->rx_length);
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+ return true;
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+}
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+
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+static void shark_uart_rx(shark_uart_t *uart){
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+ while(1) {
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+ u8 data;
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+ update_dma_w_pos(uart);
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+ if (circle_get_one_data(&uart->rx_queue, &data) != 1) {
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+ break;
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+ }
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+ switch(data){
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+ case CH_START:
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+ uart->rx_length = 0;
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+ uart->escape = false;
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+ uart->start = true;
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+ break;
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+ case CH_END:
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+ if (uart->rx_length > 2 && uart->rx_length != 0xFFFF){
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+ uart->rx_length -= 2; //skip crc
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+ shark_uart_on_rx_frame(uart);
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+ }
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+ uart->rx_length = 0xFFFF;
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+ uart->start = false;
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+ break;
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+ case CH_ESC:
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+ uart->escape = true;
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+ break;
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+ default:
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+ if (uart->escape) {
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+ uart->escape = false;
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+ switch (data) {
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+ case CH_ESC_START:
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+ data = CH_START;
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+ break;
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+
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+ case CH_ESC_END:
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+ data = CH_END;
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+ break;
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+
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+ case CH_ESC_ESC:
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+ data = CH_ESC;
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+ break;
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+
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+ default:
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+ data = 0xFF;
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+ }
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+ }
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+
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+ if (uart->rx_length < sizeof(uart->rx_frame)) {
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+ uart->rx_frame[uart->rx_length] = data;
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+ uart->rx_length++;
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+ } else {
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+ uart->rx_length = 0xFFFF;
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+ }
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+ }
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+ }
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+}
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+
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+
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+static void shark_uart_dma_tx(shark_uart_t *uart)
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+{
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+ u32 value = DMA_CHCTL(SHARK_UART0_tx_dma, uart->tx_dma_ch);
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+
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+ if (value & DMA_CHXCTL_CHEN) {
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+ if (SET != dma_flag_get(SHARK_UART0_tx_dma, uart->tx_dma_ch, DMA_FLAG_FTF)) {
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+ return;
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+ }
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+
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+ byte_queue_skip(&uart->tx_queue, uart->tx_length);
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+ DMA_CHCTL(SHARK_UART0_tx_dma, uart->tx_dma_ch) = value & (~DMA_CHXCTL_CHEN);
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+ }
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+
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+ uart->tx_length = byte_queue_peek(&uart->tx_queue);
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+ if (uart->tx_length > 0) {
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+ DMA_CHCNT(SHARK_UART0_tx_dma, uart->tx_dma_ch) = uart->tx_length;
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+ DMA_CHMADDR(SHARK_UART0_tx_dma, uart->tx_dma_ch) = (u32) byte_queue_head(&uart->tx_queue);
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+
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+ dma_flag_clear(SHARK_UART0_tx_dma, uart->tx_dma_ch, DMA_FLAG_FTF);
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+ DMA_CHCTL(SHARK_UART0_tx_dma, uart->tx_dma_ch) = value | DMA_CHXCTL_CHEN;
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+ }
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+}
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+
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+
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+
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+static void shark_uart_write(shark_uart_t *uart, const u8 *buff, u16 size)
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+{
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+ while (size > 0) {
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+ u16 length = byte_queue_write(&uart->tx_queue, buff, size);
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+
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+ if (length == size) {
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+ shark_uart_dma_tx(uart);
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+ break;
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+ }
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+
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+ shark_uart_dma_tx(uart);
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+ buff += length;
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+ size -= length;
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+ }
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+}
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+
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+static void shark_uart_write_byte(shark_uart_t *uart, u8 value)
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+{
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+ shark_uart_write(uart, &value, 1);
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+}
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+
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+
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+static void shark_uart_tx_dma_init(shark_uart_t *uart){
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+ dma_parameter_struct dma_init_struct;
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+ rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART0_tx_dma_clk);
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+ dma_deinit(SHARK_UART0_tx_dma, uart->tx_dma_ch);
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+ dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
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+ dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
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+ dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
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+ dma_init_struct.periph_addr = (u32) &USART_DATA(uart->uart_com);
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+ dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
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+ dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
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+ dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
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+ dma_init(SHARK_UART0_tx_dma, uart->tx_dma_ch, &dma_init_struct);
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+ dma_circulation_disable(SHARK_UART0_tx_dma, uart->tx_dma_ch);
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+ dma_memory_to_memory_disable(SHARK_UART0_tx_dma, uart->tx_dma_ch);
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+ usart_dma_transmit_config(uart->uart_com, USART_DENT_ENABLE);
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+#if 0
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+ if (uart->tx_dma_ch == DMA_CH1) {
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+ nvic_irq_enable(DMA_Channel1_2_IRQn ,4, 0);
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+ }else {
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+ nvic_irq_enable(DMA_Channel3_4_IRQn ,4, 0);
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+ }
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+ dma_interrupt_enable(uart->tx_dma_ch, DMA_INT_FTF);
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+#endif
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+}
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+
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+#if ENABLE_RX_DMA==1
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+static void shark_uart_rx_dma_init(shark_uart_t *uart){
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+ dma_parameter_struct dma_init_struct;
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+ rcu_periph_clock_enable(_uart_index(uart->uart_com)== SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART0_rx_dma_clk);
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+ dma_deinit(SHARK_UART0_rx_dma, uart->rx_dma_ch);
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+ dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
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+ dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
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+ dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
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+ dma_init_struct.memory_addr = (u32)uart->rx_queue.buffer;
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+ dma_init_struct.number = uart->rx_queue.buffer_len;
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+ dma_init_struct.periph_addr = (u32) &USART_DATA(uart->uart_com);
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+ dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
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+ dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
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+ dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
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+ dma_init(SHARK_UART0_rx_dma, uart->rx_dma_ch, &dma_init_struct);
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+ dma_circulation_enable(SHARK_UART0_rx_dma, uart->rx_dma_ch);
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+ dma_memory_to_memory_disable(SHARK_UART0_rx_dma, uart->rx_dma_ch);
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+ dma_channel_enable(SHARK_UART0_rx_dma, uart->rx_dma_ch);
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+ usart_dma_receive_config(uart->uart_com, USART_DENR_ENABLE);
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+}
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+#endif
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+static void shark_uart_pin_init(shark_uart_t *uart){
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+ rcu_periph_clock_enable(SHARK_UART0_clk);
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+ rcu_periph_clock_enable(SHARK_UART0_rx_gpio_clk);
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+ rcu_periph_clock_enable(SHARK_UART0_tx_gpio_clk);
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+ gpio_init(SHARK_UART0_tx_port, GPIO_MODE_OUT_PP,GPIO_OSPEED_50MHZ,SHARK_UART0_tx_pin);
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+ gpio_init(SHARK_UART0_rx_port, GPIO_MODE_IN_FLOATING,GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
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+}
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+
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+static void shark_uart_pin_deinit(shark_uart_t *uart){
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+ if (_uart_index(uart->uart_com) == SHARK_UART0) {
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+ gpio_init(SHARK_UART0_tx_port, GPIO_MODE_IN_FLOATING,GPIO_OSPEED_50MHZ,SHARK_UART0_tx_pin);
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+ gpio_init(SHARK_UART0_rx_port, GPIO_MODE_IN_FLOATING,GPIO_OSPEED_50MHZ,SHARK_UART0_rx_pin);
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+ }
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+}
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+
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+
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+static void shark_uart_device_init(shark_uart_t *uart){
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+ usart_deinit(uart->uart_com);
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+ usart_baudrate_set(uart->uart_com, SHARK_UART_BAUDRATE);
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+
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+ usart_word_length_set(uart->uart_com, USART_WL_8BIT);
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+ usart_stop_bit_set(uart->uart_com, USART_STB_1BIT);
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+ usart_parity_config(uart->uart_com, USART_PM_NONE);
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+ usart_hardware_flow_rts_config(uart->uart_com, USART_RTS_DISABLE);
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+ usart_hardware_flow_cts_config(uart->uart_com, USART_CTS_DISABLE);
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+ usart_receive_config(uart->uart_com, USART_RECEIVE_ENABLE);
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+ usart_transmit_config(uart->uart_com, USART_TRANSMIT_ENABLE);
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+
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+#if ENABLE_RX_DMA==0
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+ usart_lin_mode_disable(uart->uart_com);
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+ usart_receiver_timeout_disable(uart->uart_com);
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+ usart_interrupt_enable(uart->uart_com,USART_INT_RBNE);
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+#endif
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+}
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+
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+static u32 shark_uart_handler(void)
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+{
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+ shark_uart_t *uart = _shark_uart + SHARK_UART0;
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+ if (uart->uart_com != 0) {
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+ shark_uart_rx(uart);
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+ shark_uart_dma_tx(uart);
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+ }
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+#if UART_NUM==2
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+ uart = _shark_uart + SHARK_UART1;
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+ if (uart->uart_com != 0) {
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+ shark_uart_rx(uart);
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+ shark_uart_dma_tx(uart);
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+ }
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+#endif
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+ return 0;
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+}
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+
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+
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+void shark_uart_flush(void){
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+ shark_uart_t *uart = _shark_uart + SHARK_UART0;
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+ if (uart->uart_com != 0) {
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+ while(!byte_queue_empty(&uart->tx_queue)) {
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+ shark_uart_dma_tx(uart);
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+ }
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+ }
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+#if UART_NUM==2
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+ uart = _shark_uart + SHARK_UART1;
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+ if (uart->uart_com != 0) {
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+ while(!byte_queue_empty(&uart->tx_queue)) {
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+ shark_uart_dma_tx(uart);
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+ }
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+ }
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+#endif
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+}
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+
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+
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+#if 0
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+void DMA_Channel1_2_IRQHandler(void){
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+ shark_uart_t *uart = _shark_uart + SHARK_UART0;
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+ if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
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+ shark_uart_dma_tx(uart);
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+ dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
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+ }
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+}
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+
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+void DMA_Channel3_4_IRQHandler(void){
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+ shark_uart_t *uart = _shark_uart + SHARK_UART1;
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+ if (dma_interrupt_flag_get(uart->tx_dma_ch, DMA_INT_FLAG_FTF) != RESET){
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+ shark_uart_dma_tx(uart);
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+ dma_interrupt_flag_clear(uart->tx_dma_ch, DMA_INT_FLAG_FTF);
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+ }
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+}
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+#endif
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+
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+static u8 *tx_cache_addr(uart_enum_t uart_no){
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+#if UART_NUM==2
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+ return (uart_no == SHARK_UART0)?shark_uart0_tx_cache:shark_uart1_tx_cache;
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+#else
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+ return shark_uart0_tx_cache;
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+#endif
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+}
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+
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+static u8 *rx_cache_addr(uart_enum_t uart_no){
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+#if UART_NUM==2
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+ return (uart_no == SHARK_UART0)?shark_uart0_rx_cache:shark_uart1_rx_cache;
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+#else
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+ return shark_uart0_rx_cache;
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+#endif
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+}
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+
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+
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+void shark_uart_deinit(uart_enum_t uart_no){
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+ shark_uart_t *uart = _shark_uart + uart_no;
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+ if (uart->uart_com != 0) {
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+ usart_disable(uart->uart_com);
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+ usart_deinit(uart->uart_com);
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+ rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_clk:SHARK_UART0_clk);
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+ dma_channel_disable(SHARK_UART0_rx_dma, uart->rx_dma_ch);
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+ dma_channel_disable(SHARK_UART0_tx_dma, uart->tx_dma_ch);
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+ rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_tx_dma_clk:SHARK_UART0_tx_dma_clk);
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+ rcu_periph_clock_disable(uart_no == SHARK_UART0?SHARK_UART0_rx_dma_clk:SHARK_UART0_rx_dma_clk);
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+ shark_uart_pin_deinit(uart);
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+ }
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+ if (uart_no == SHARK_UART0) {
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+#if ENABLE_RX_DMA==0
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+ nvic_irq_disable(USART0_IRQn);
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+#endif
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+ }else {
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+#if ENABLE_RX_DMA==0
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+ nvic_irq_disable(USART1_IRQn);
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+#endif
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+ }
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+}
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+
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+
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+bool shark_uart_timeout(void){
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+#if UART_NUM==2
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+ return (_shark_uart[0].uart_no_data && _shark_uart[1].uart_no_data)?TRUE:FALSE;
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+#else
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+ return (_shark_uart[0].uart_no_data)?TRUE:FALSE;
|
|
|
+#endif
|
|
|
+}
|
|
|
+void shark_uart_init(uart_enum_t uart_no)
|
|
|
+{
|
|
|
+ shark_uart_t *uart = _shark_uart + uart_no;
|
|
|
+ uart->escape = false;
|
|
|
+ uart->rx_length = 0;
|
|
|
+ uart->tx_length = 0;
|
|
|
+ uart->uart_com = (uart_no == SHARK_UART0)?SHARK_UART0_com:SHARK_UART0_com;
|
|
|
+
|
|
|
+ circle_buffer_init(&uart->rx_queue, rx_cache_addr(uart_no), SHARK_UART_RX_MEM_SIZE);
|
|
|
+ byte_queue_init(&uart->tx_queue,tx_cache_addr(uart_no), SHARK_UART_TX_MEM_SIZE);
|
|
|
+
|
|
|
+ uart->rx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_rx_dma_ch:SHARK_UART0_rx_dma_ch;
|
|
|
+ uart->tx_dma_ch = (uart_no == SHARK_UART0)?SHARK_UART0_tx_dma_ch:SHARK_UART0_tx_dma_ch;
|
|
|
+
|
|
|
+ shark_uart_pin_init(uart);
|
|
|
+ shark_uart_device_init(uart);
|
|
|
+#if ENABLE_RX_DMA==1
|
|
|
+ shark_uart_rx_dma_init(uart);
|
|
|
+#endif
|
|
|
+ shark_uart_tx_dma_init(uart);
|
|
|
+ usart_enable(uart->uart_com);
|
|
|
+
|
|
|
+ if (_uart_task.handler == NULL) {
|
|
|
+ _uart_task.handler = shark_uart_handler;
|
|
|
+ task_add(&_uart_task);
|
|
|
+ }
|
|
|
+ if (uart_no == SHARK_UART0) {
|
|
|
+#if ENABLE_RX_DMA==0
|
|
|
+ nvic_irq_enable(UART3_IRQn, 3, 0);
|
|
|
+#endif
|
|
|
+ }else {
|
|
|
+#if ENABLE_RX_DMA==0
|
|
|
+ nvic_irq_enable(USART1_IRQn, 3, 0);
|
|
|
+#endif
|
|
|
+ }
|
|
|
+ uart->uart_no_data = false;
|
|
|
+}
|
|
|
+
|
|
|
+#if ENABLE_RX_DMA==0
|
|
|
+void USART3_IRQHandler(void){
|
|
|
+ if(usart_flag_get(USART0, USART_FLAG_RBNE) == SET){
|
|
|
+ shark_uart_t *uart = _shark_uart + SHARK_UART0;
|
|
|
+ u8 c = usart_data_receive(USART0);
|
|
|
+ circle_put_one_data(&uart->rx_queue, c);
|
|
|
+ }
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static void shark_uart_write_byte_esc(shark_uart_t *uart, u8 value)
|
|
|
+{
|
|
|
+ switch (value) {
|
|
|
+ case CH_START:
|
|
|
+ shark_uart_write_byte(uart, CH_ESC);
|
|
|
+ value = CH_ESC_START;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case CH_END:
|
|
|
+ shark_uart_write_byte(uart, CH_ESC);
|
|
|
+ value = CH_ESC_END;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case CH_ESC:
|
|
|
+ shark_uart_write_byte(uart, CH_ESC);
|
|
|
+ value = CH_ESC_ESC;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ shark_uart_write_byte(uart, value);
|
|
|
+}
|
|
|
+
|
|
|
+static void shark_uart_write_esc(shark_uart_t *uart, const u8 *buff, u16 length)
|
|
|
+{
|
|
|
+ const u8 *buff_end;
|
|
|
+
|
|
|
+ for (buff_end = buff + length; buff < buff_end; buff++) {
|
|
|
+ shark_uart_write_byte_esc(uart, *buff);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void shark_uart_tx_start(shark_uart_t *uart)
|
|
|
+{
|
|
|
+ shark_uart_write_byte(uart, CH_START);
|
|
|
+ uart->tx_crc16 = 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void shark_uart_tx_continue(shark_uart_t *uart, const void *buff, u16 length)
|
|
|
+{
|
|
|
+ shark_uart_write_esc(uart, (const u8 *) buff, length);
|
|
|
+ uart->tx_crc16 = crc16_update(uart->tx_crc16, (const u8 *) buff, length);
|
|
|
+}
|
|
|
+
|
|
|
+static void shark_uart_tx_end(shark_uart_t *uart)
|
|
|
+{
|
|
|
+ shark_uart_write_esc(uart, (u8 *)&uart->tx_crc16, sizeof(uart->tx_crc16));
|
|
|
+ shark_uart_write_byte(uart, CH_END);
|
|
|
+}
|
|
|
+
|
|
|
+void shark_uart_write_frame(uart_enum_t uart_no, uint8_t *bytes, int len){
|
|
|
+ shark_uart_t *uart = _shark_uart + uart_no;
|
|
|
+ shark_uart_tx_start(uart);
|
|
|
+ shark_uart_tx_continue(uart, bytes, len);
|
|
|
+ shark_uart_tx_end(uart);
|
|
|
+}
|
|
|
+
|
|
|
+void shark_uart_frame_start(uart_enum_t uart_no, uint8_t *bytes, int len){
|
|
|
+ shark_uart_t *uart = _shark_uart + uart_no;
|
|
|
+ shark_uart_tx_start(uart);
|
|
|
+ shark_uart_tx_continue(uart, bytes, len);
|
|
|
+}
|
|
|
+
|
|
|
+void shark_uart_frame_continue(uart_enum_t uart_no, uint8_t *bytes, int len){
|
|
|
+ shark_uart_t *uart = _shark_uart + uart_no;
|
|
|
+ shark_uart_tx_continue(uart, bytes, len);
|
|
|
+}
|
|
|
+
|
|
|
+void shark_uart_frame_end(uart_enum_t uart_no){
|
|
|
+ shark_uart_tx_end(_shark_uart + uart_no);
|
|
|
+}
|
|
|
+
|
|
|
+void shark_uart_write_bytes(uart_enum_t uart_no, u8 *buff, u16 size){
|
|
|
+ shark_uart_write(_shark_uart + uart_no, buff, size);
|
|
|
+}
|
|
|
+
|