1/*



2 * rtGetInf.c



3 *



4 * Code generation for model "PWM_sf".



5 *



6 * Model version              : 1.825



7 * Simulink Coder version : 9.4 (R2020b) 29-Jul-2020



8 * C source code generated on : Fri Apr 14 12:53:29 2023



9 *



10 * Target selection: rtwsfcn.tlc



11 * Note: GRT includes extra infrastructure and instrumentation for prototyping



12 * Embedded hardware selection: ARM Compatible->ARM Cortex-M



13 * Emulation hardware selection:



14 *    Differs from embedded hardware (MATLAB Host)



15 * Code generation objectives:



16 *    1. Execution efficiency



17 *    2. RAM efficiency



18 * Validation result: Not run



19 */



20



21/*



22 * Abstract:



23 *      Function to initialize non-finite, Inf



24 */



25#include "rtGetInf.h"



26#define NumBitsPerChar                 8U



27



28/*



29 * Initialize rtInf needed by the generated code.



30 * Inf is initialized as non-signaling. Assumes IEEE.



31 */



32real_T rtGetInf(void)



33{



34  size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);



35  real_T inf = 0.0;



36  if (bitsPerReal == 32U) {



37    inf = rtGetInfF();



38  } else {



39    uint16_T one = 1U;



40    enum {



41      LittleEndian,



42      BigEndian



43    } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;



44    switch (machByteOrder) {



45     case LittleEndian:



46      {



47        union {



48          LittleEndianIEEEDouble bitVal;



49          real_T fltVal;



50        } tmpVal;



51



52        tmpVal.bitVal.words.wordH = 0x7FF00000U;



53        tmpVal.bitVal.words.wordL = 0x00000000U;



54        inf = tmpVal.fltVal;



55        break;



56      }



57



58     case BigEndian:



59      {



60        union {



61          BigEndianIEEEDouble bitVal;



62          real_T fltVal;



63        } tmpVal;



64



65        tmpVal.bitVal.words.wordH = 0x7FF00000U;



66        tmpVal.bitVal.words.wordL = 0x00000000U;



67        inf = tmpVal.fltVal;



68        break;



69      }



70    }



71  }



72



73  return inf;



74}



75



76/*



77 * Initialize rtInfF needed by the generated code.



78 * Inf is initialized as non-signaling. Assumes IEEE.



79 */



80real32_T rtGetInfF(void)



81{



82  IEEESingle infF;



83  infF.wordL.wordLuint = 0x7F800000U;



84  return infF.wordL.wordLreal;



85}



86



87/*



88 * Initialize rtMinusInf needed by the generated code.



89 * Inf is initialized as non-signaling. Assumes IEEE.



90 */



91real_T rtGetMinusInf(void)



92{



93  size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);



94  real_T minf = 0.0;



95  if (bitsPerReal == 32U) {



96    minf = rtGetMinusInfF();



97  } else {



98    uint16_T one = 1U;



99    enum {



100      LittleEndian,



101      BigEndian



102    } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;



103    switch (machByteOrder) {



104     case LittleEndian:



105      {



106        union {



107          LittleEndianIEEEDouble bitVal;



108          real_T fltVal;



109        } tmpVal;



110



111        tmpVal.bitVal.words.wordH = 0xFFF00000U;



112        tmpVal.bitVal.words.wordL = 0x00000000U;



113        minf = tmpVal.fltVal;



114        break;



115      }



116



117     case BigEndian:



118      {



119        union {



120          BigEndianIEEEDouble bitVal;



121          real_T fltVal;



122        } tmpVal;



123



124        tmpVal.bitVal.words.wordH = 0xFFF00000U;



125        tmpVal.bitVal.words.wordL = 0x00000000U;



126        minf = tmpVal.fltVal;



127        break;



128      }



129    }



130  }



131



132  return minf;



133}



134



135/*



136 * Initialize rtMinusInfF needed by the generated code.



137 * Inf is initialized as non-signaling. Assumes IEEE.



138 */



139real32_T rtGetMinusInfF(void)



140{



141  IEEESingle minfF;



142  minfF.wordL.wordLuint = 0xFF800000U;



143  return minfF.wordL.wordLreal;



144}



145